1 /******************************************************************************* 2 3 Copyright (c) 2001-2005, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 *******************************************************************************/ 33 34 /* $OpenBSD: if_em_hw.c,v 1.92 2016/08/23 04:04:23 jsg Exp $ */ 35 /* 36 * if_em_hw.c Shared functions for accessing and configuring the MAC 37 */ 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/sockio.h> 42 #include <sys/mbuf.h> 43 #include <sys/malloc.h> 44 #include <sys/kernel.h> 45 #include <sys/device.h> 46 #include <sys/socket.h> 47 48 #include <net/if.h> 49 #include <net/if_media.h> 50 51 #include <netinet/in.h> 52 #include <netinet/if_ether.h> 53 54 #include <uvm/uvm_extern.h> 55 56 #include <dev/pci/pcireg.h> 57 #include <dev/pci/pcivar.h> 58 59 #include <dev/pci/if_em_hw.h> 60 #include <dev/pci/if_em_soc.h> 61 62 #include <dev/mii/rgephyreg.h> 63 64 #define STATIC 65 66 static int32_t em_swfw_sync_acquire(struct em_hw *, uint16_t); 67 static void em_swfw_sync_release(struct em_hw *, uint16_t); 68 static int32_t em_read_kmrn_reg(struct em_hw *, uint32_t, uint16_t *); 69 static int32_t em_write_kmrn_reg(struct em_hw *hw, uint32_t, uint16_t); 70 static int32_t em_get_software_semaphore(struct em_hw *); 71 static void em_release_software_semaphore(struct em_hw *); 72 73 static int32_t em_check_downshift(struct em_hw *); 74 static void em_clear_vfta(struct em_hw *); 75 void em_clear_vfta_i350(struct em_hw *); 76 static int32_t em_commit_shadow_ram(struct em_hw *); 77 static int32_t em_config_dsp_after_link_change(struct em_hw *, boolean_t); 78 static int32_t em_config_fc_after_link_up(struct em_hw *); 79 static int32_t em_match_gig_phy(struct em_hw *); 80 static int32_t em_detect_gig_phy(struct em_hw *); 81 static int32_t em_erase_ich8_4k_segment(struct em_hw *, uint32_t); 82 static int32_t em_get_auto_rd_done(struct em_hw *); 83 static int32_t em_get_cable_length(struct em_hw *, uint16_t *, uint16_t *); 84 static int32_t em_get_hw_eeprom_semaphore(struct em_hw *); 85 static int32_t em_get_phy_cfg_done(struct em_hw *); 86 static int32_t em_get_software_flag(struct em_hw *); 87 static int32_t em_ich8_cycle_init(struct em_hw *); 88 static int32_t em_ich8_flash_cycle(struct em_hw *, uint32_t); 89 static int32_t em_id_led_init(struct em_hw *); 90 static int32_t em_init_lcd_from_nvm_config_region(struct em_hw *, uint32_t, 91 uint32_t); 92 static int32_t em_init_lcd_from_nvm(struct em_hw *); 93 static int32_t em_phy_no_cable_workaround(struct em_hw *); 94 static void em_init_rx_addrs(struct em_hw *); 95 static void em_initialize_hardware_bits(struct em_hw *); 96 static boolean_t em_is_onboard_nvm_eeprom(struct em_hw *); 97 static int32_t em_kumeran_lock_loss_workaround(struct em_hw *); 98 static int32_t em_mng_enable_host_if(struct em_hw *); 99 static int32_t em_read_eeprom_eerd(struct em_hw *, uint16_t, uint16_t, 100 uint16_t *); 101 static int32_t em_write_eeprom_eewr(struct em_hw *, uint16_t, uint16_t, 102 uint16_t *data); 103 static int32_t em_poll_eerd_eewr_done(struct em_hw *, int); 104 static void em_put_hw_eeprom_semaphore(struct em_hw *); 105 static int32_t em_read_ich8_byte(struct em_hw *, uint32_t, uint8_t *); 106 static int32_t em_verify_write_ich8_byte(struct em_hw *, uint32_t, uint8_t); 107 static int32_t em_write_ich8_byte(struct em_hw *, uint32_t, uint8_t); 108 static int32_t em_read_ich8_word(struct em_hw *, uint32_t, uint16_t *); 109 static int32_t em_read_ich8_dword(struct em_hw *, uint32_t, uint32_t *); 110 static int32_t em_read_ich8_data(struct em_hw *, uint32_t, uint32_t, 111 uint16_t *); 112 static int32_t em_write_ich8_data(struct em_hw *, uint32_t, uint32_t, 113 uint16_t); 114 static int32_t em_read_eeprom_ich8(struct em_hw *, uint16_t, uint16_t, 115 uint16_t *); 116 static int32_t em_write_eeprom_ich8(struct em_hw *, uint16_t, uint16_t, 117 uint16_t *); 118 static int32_t em_read_invm_i210(struct em_hw *, uint16_t, uint16_t, 119 uint16_t *); 120 static int32_t em_read_invm_word_i210(struct em_hw *, uint16_t, uint16_t *); 121 static void em_release_software_flag(struct em_hw *); 122 static int32_t em_set_d3_lplu_state(struct em_hw *, boolean_t); 123 static int32_t em_set_d0_lplu_state(struct em_hw *, boolean_t); 124 static int32_t em_set_lplu_state_pchlan(struct em_hw *, boolean_t); 125 static int32_t em_set_pci_ex_no_snoop(struct em_hw *, uint32_t); 126 static void em_set_pci_express_master_disable(struct em_hw *); 127 static int32_t em_wait_autoneg(struct em_hw *); 128 static void em_write_reg_io(struct em_hw *, uint32_t, uint32_t); 129 static int32_t em_set_phy_type(struct em_hw *); 130 static void em_phy_init_script(struct em_hw *); 131 static int32_t em_setup_copper_link(struct em_hw *); 132 static int32_t em_setup_fiber_serdes_link(struct em_hw *); 133 static int32_t em_adjust_serdes_amplitude(struct em_hw *); 134 static int32_t em_phy_force_speed_duplex(struct em_hw *); 135 static int32_t em_config_mac_to_phy(struct em_hw *); 136 static void em_raise_mdi_clk(struct em_hw *, uint32_t *); 137 static void em_lower_mdi_clk(struct em_hw *, uint32_t *); 138 static void em_shift_out_mdi_bits(struct em_hw *, uint32_t, uint16_t); 139 static uint16_t em_shift_in_mdi_bits(struct em_hw *); 140 static int32_t em_phy_reset_dsp(struct em_hw *); 141 static int32_t em_write_eeprom_spi(struct em_hw *, uint16_t, uint16_t, 142 uint16_t *); 143 static int32_t em_write_eeprom_microwire(struct em_hw *, uint16_t, uint16_t, 144 uint16_t *); 145 static int32_t em_spi_eeprom_ready(struct em_hw *); 146 static void em_raise_ee_clk(struct em_hw *, uint32_t *); 147 static void em_lower_ee_clk(struct em_hw *, uint32_t *); 148 static void em_shift_out_ee_bits(struct em_hw *, uint16_t, uint16_t); 149 static int32_t em_write_phy_reg_ex(struct em_hw *, uint32_t, uint16_t); 150 static int32_t em_read_phy_reg_ex(struct em_hw *, uint32_t, uint16_t *); 151 static uint16_t em_shift_in_ee_bits(struct em_hw *, uint16_t); 152 static int32_t em_acquire_eeprom(struct em_hw *); 153 static void em_release_eeprom(struct em_hw *); 154 static void em_standby_eeprom(struct em_hw *); 155 static int32_t em_set_vco_speed(struct em_hw *); 156 static int32_t em_polarity_reversal_workaround(struct em_hw *); 157 static int32_t em_set_phy_mode(struct em_hw *); 158 static int32_t em_host_if_read_cookie(struct em_hw *, uint8_t *); 159 static uint8_t em_calculate_mng_checksum(char *, uint32_t); 160 static int32_t em_configure_kmrn_for_10_100(struct em_hw *, uint16_t); 161 static int32_t em_configure_kmrn_for_1000(struct em_hw *); 162 static int32_t em_set_pciex_completion_timeout(struct em_hw *hw); 163 static int32_t em_set_mdio_slow_mode_hv(struct em_hw *); 164 int32_t em_hv_phy_workarounds_ich8lan(struct em_hw *); 165 int32_t em_lv_phy_workarounds_ich8lan(struct em_hw *); 166 int32_t em_link_stall_workaround_hv(struct em_hw *); 167 int32_t em_k1_gig_workaround_hv(struct em_hw *, boolean_t); 168 int32_t em_k1_workaround_lv(struct em_hw *); 169 int32_t em_k1_workaround_lpt_lp(struct em_hw *, boolean_t); 170 int32_t em_configure_k1_ich8lan(struct em_hw *, boolean_t); 171 void em_gate_hw_phy_config_ich8lan(struct em_hw *, boolean_t); 172 int32_t em_access_phy_wakeup_reg_bm(struct em_hw *, uint32_t, 173 uint16_t *, boolean_t); 174 int32_t em_access_phy_debug_regs_hv(struct em_hw *, uint32_t, 175 uint16_t *, boolean_t); 176 int32_t em_access_phy_reg_hv(struct em_hw *, uint32_t, uint16_t *, 177 boolean_t); 178 int32_t em_oem_bits_config_pchlan(struct em_hw *, boolean_t); 179 void em_power_up_serdes_link_82575(struct em_hw *); 180 int32_t em_get_pcs_speed_and_duplex_82575(struct em_hw *, uint16_t *, 181 uint16_t *); 182 int32_t em_set_eee_i350(struct em_hw *); 183 int32_t em_set_eee_pchlan(struct em_hw *); 184 int32_t em_valid_nvm_bank_detect_ich8lan(struct em_hw *, uint32_t *); 185 int32_t em_initialize_M88E1512_phy(struct em_hw *); 186 187 /* IGP cable length table */ 188 static const uint16_t 189 em_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = 190 {5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 191 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25, 192 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40, 193 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60, 194 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90, 195 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 196 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 197 110, 198 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 199 120}; 200 201 static const uint16_t 202 em_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] = 203 {0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 204 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 205 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 206 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 207 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 208 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 209 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 210 121, 124}; 211 212 /****************************************************************************** 213 * Set the phy type member in the hw struct. 214 * 215 * hw - Struct containing variables accessed by shared code 216 *****************************************************************************/ 217 STATIC int32_t 218 em_set_phy_type(struct em_hw *hw) 219 { 220 DEBUGFUNC("em_set_phy_type"); 221 222 if (hw->mac_type == em_undefined) 223 return -E1000_ERR_PHY_TYPE; 224 225 switch (hw->phy_id) { 226 case M88E1000_E_PHY_ID: 227 case M88E1000_I_PHY_ID: 228 case M88E1011_I_PHY_ID: 229 case M88E1111_I_PHY_ID: 230 case M88E1112_E_PHY_ID: 231 case M88E1543_E_PHY_ID: 232 case M88E1512_E_PHY_ID: 233 case I210_I_PHY_ID: 234 case I347AT4_E_PHY_ID: 235 hw->phy_type = em_phy_m88; 236 break; 237 case IGP01E1000_I_PHY_ID: 238 if (hw->mac_type == em_82541 || 239 hw->mac_type == em_82541_rev_2 || 240 hw->mac_type == em_82547 || 241 hw->mac_type == em_82547_rev_2) { 242 hw->phy_type = em_phy_igp; 243 break; 244 } 245 case IGP03E1000_E_PHY_ID: 246 case IGP04E1000_E_PHY_ID: 247 hw->phy_type = em_phy_igp_3; 248 break; 249 case IFE_E_PHY_ID: 250 case IFE_PLUS_E_PHY_ID: 251 case IFE_C_E_PHY_ID: 252 hw->phy_type = em_phy_ife; 253 break; 254 case M88E1141_E_PHY_ID: 255 hw->phy_type = em_phy_oem; 256 break; 257 case I82577_E_PHY_ID: 258 hw->phy_type = em_phy_82577; 259 break; 260 case I82578_E_PHY_ID: 261 hw->phy_type = em_phy_82578; 262 break; 263 case I82579_E_PHY_ID: 264 hw->phy_type = em_phy_82579; 265 break; 266 case I217_E_PHY_ID: 267 hw->phy_type = em_phy_i217; 268 break; 269 case I82580_I_PHY_ID: 270 case I350_I_PHY_ID: 271 hw->phy_type = em_phy_82580; 272 break; 273 case RTL8211_E_PHY_ID: 274 hw->phy_type = em_phy_rtl8211; 275 break; 276 case BME1000_E_PHY_ID: 277 if (hw->phy_revision == 1) { 278 hw->phy_type = em_phy_bm; 279 break; 280 } 281 /* FALLTHROUGH */ 282 case GG82563_E_PHY_ID: 283 if (hw->mac_type == em_80003es2lan) { 284 hw->phy_type = em_phy_gg82563; 285 break; 286 } 287 /* FALLTHROUGH */ 288 default: 289 /* Should never have loaded on this device */ 290 hw->phy_type = em_phy_undefined; 291 return -E1000_ERR_PHY_TYPE; 292 } 293 294 return E1000_SUCCESS; 295 } 296 297 /****************************************************************************** 298 * IGP phy init script - initializes the GbE PHY 299 * 300 * hw - Struct containing variables accessed by shared code 301 *****************************************************************************/ 302 static void 303 em_phy_init_script(struct em_hw *hw) 304 { 305 uint16_t phy_saved_data; 306 DEBUGFUNC("em_phy_init_script"); 307 308 if (hw->phy_init_script) { 309 msec_delay(20); 310 /* 311 * Save off the current value of register 0x2F5B to be 312 * restored at the end of this routine. 313 */ 314 em_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 315 316 /* Disabled the PHY transmitter */ 317 em_write_phy_reg(hw, 0x2F5B, 0x0003); 318 msec_delay(20); 319 em_write_phy_reg(hw, 0x0000, 0x0140); 320 msec_delay(5); 321 322 switch (hw->mac_type) { 323 case em_82541: 324 case em_82547: 325 em_write_phy_reg(hw, 0x1F95, 0x0001); 326 em_write_phy_reg(hw, 0x1F71, 0xBD21); 327 em_write_phy_reg(hw, 0x1F79, 0x0018); 328 em_write_phy_reg(hw, 0x1F30, 0x1600); 329 em_write_phy_reg(hw, 0x1F31, 0x0014); 330 em_write_phy_reg(hw, 0x1F32, 0x161C); 331 em_write_phy_reg(hw, 0x1F94, 0x0003); 332 em_write_phy_reg(hw, 0x1F96, 0x003F); 333 em_write_phy_reg(hw, 0x2010, 0x0008); 334 break; 335 case em_82541_rev_2: 336 case em_82547_rev_2: 337 em_write_phy_reg(hw, 0x1F73, 0x0099); 338 break; 339 default: 340 break; 341 } 342 343 em_write_phy_reg(hw, 0x0000, 0x3300); 344 msec_delay(20); 345 346 /* Now enable the transmitter */ 347 em_write_phy_reg(hw, 0x2F5B, phy_saved_data); 348 349 if (hw->mac_type == em_82547) { 350 uint16_t fused, fine, coarse; 351 /* Move to analog registers page */ 352 em_read_phy_reg(hw, 353 IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused); 354 355 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { 356 em_read_phy_reg(hw, 357 IGP01E1000_ANALOG_FUSE_STATUS, &fused); 358 359 fine = fused & 360 IGP01E1000_ANALOG_FUSE_FINE_MASK; 361 coarse = fused & 362 IGP01E1000_ANALOG_FUSE_COARSE_MASK; 363 364 if (coarse > 365 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { 366 coarse -= 367 IGP01E1000_ANALOG_FUSE_COARSE_10; 368 fine -= 369 IGP01E1000_ANALOG_FUSE_FINE_1; 370 } else if (coarse == 371 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) 372 fine -= IGP01E1000_ANALOG_FUSE_FINE_10; 373 374 fused = (fused & 375 IGP01E1000_ANALOG_FUSE_POLY_MASK) | 376 (fine & 377 IGP01E1000_ANALOG_FUSE_FINE_MASK) | 378 (coarse & 379 IGP01E1000_ANALOG_FUSE_COARSE_MASK); 380 381 em_write_phy_reg(hw, 382 IGP01E1000_ANALOG_FUSE_CONTROL, 383 fused); 384 385 em_write_phy_reg(hw, 386 IGP01E1000_ANALOG_FUSE_BYPASS, 387 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL); 388 } 389 } 390 } 391 } 392 393 /****************************************************************************** 394 * Set the mac type member in the hw struct. 395 * 396 * hw - Struct containing variables accessed by shared code 397 *****************************************************************************/ 398 int32_t 399 em_set_mac_type(struct em_hw *hw) 400 { 401 DEBUGFUNC("em_set_mac_type"); 402 403 switch (hw->device_id) { 404 case E1000_DEV_ID_82542: 405 switch (hw->revision_id) { 406 case E1000_82542_2_0_REV_ID: 407 hw->mac_type = em_82542_rev2_0; 408 break; 409 case E1000_82542_2_1_REV_ID: 410 hw->mac_type = em_82542_rev2_1; 411 break; 412 default: 413 /* Invalid 82542 revision ID */ 414 return -E1000_ERR_MAC_TYPE; 415 } 416 break; 417 case E1000_DEV_ID_82543GC_FIBER: 418 case E1000_DEV_ID_82543GC_COPPER: 419 hw->mac_type = em_82543; 420 break; 421 case E1000_DEV_ID_82544EI_COPPER: 422 case E1000_DEV_ID_82544EI_FIBER: 423 case E1000_DEV_ID_82544GC_COPPER: 424 case E1000_DEV_ID_82544GC_LOM: 425 hw->mac_type = em_82544; 426 break; 427 case E1000_DEV_ID_82540EM: 428 case E1000_DEV_ID_82540EM_LOM: 429 case E1000_DEV_ID_82540EP: 430 case E1000_DEV_ID_82540EP_LOM: 431 case E1000_DEV_ID_82540EP_LP: 432 hw->mac_type = em_82540; 433 break; 434 case E1000_DEV_ID_82545EM_COPPER: 435 case E1000_DEV_ID_82545EM_FIBER: 436 hw->mac_type = em_82545; 437 break; 438 case E1000_DEV_ID_82545GM_COPPER: 439 case E1000_DEV_ID_82545GM_FIBER: 440 case E1000_DEV_ID_82545GM_SERDES: 441 hw->mac_type = em_82545_rev_3; 442 break; 443 case E1000_DEV_ID_82546EB_COPPER: 444 case E1000_DEV_ID_82546EB_FIBER: 445 case E1000_DEV_ID_82546EB_QUAD_COPPER: 446 hw->mac_type = em_82546; 447 break; 448 case E1000_DEV_ID_82546GB_COPPER: 449 case E1000_DEV_ID_82546GB_FIBER: 450 case E1000_DEV_ID_82546GB_SERDES: 451 case E1000_DEV_ID_82546GB_PCIE: 452 case E1000_DEV_ID_82546GB_QUAD_COPPER: 453 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 454 case E1000_DEV_ID_82546GB_2: 455 hw->mac_type = em_82546_rev_3; 456 break; 457 case E1000_DEV_ID_82541EI: 458 case E1000_DEV_ID_82541EI_MOBILE: 459 case E1000_DEV_ID_82541ER_LOM: 460 hw->mac_type = em_82541; 461 break; 462 case E1000_DEV_ID_82541ER: 463 case E1000_DEV_ID_82541GI: 464 case E1000_DEV_ID_82541GI_LF: 465 case E1000_DEV_ID_82541GI_MOBILE: 466 hw->mac_type = em_82541_rev_2; 467 break; 468 case E1000_DEV_ID_82547EI: 469 case E1000_DEV_ID_82547EI_MOBILE: 470 hw->mac_type = em_82547; 471 break; 472 case E1000_DEV_ID_82547GI: 473 hw->mac_type = em_82547_rev_2; 474 break; 475 case E1000_DEV_ID_82571EB_AF: 476 case E1000_DEV_ID_82571EB_AT: 477 case E1000_DEV_ID_82571EB_COPPER: 478 case E1000_DEV_ID_82571EB_FIBER: 479 case E1000_DEV_ID_82571EB_SERDES: 480 case E1000_DEV_ID_82571EB_QUAD_COPPER: 481 case E1000_DEV_ID_82571EB_QUAD_FIBER: 482 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 483 case E1000_DEV_ID_82571EB_SERDES_DUAL: 484 case E1000_DEV_ID_82571EB_SERDES_QUAD: 485 case E1000_DEV_ID_82571PT_QUAD_COPPER: 486 hw->mac_type = em_82571; 487 break; 488 case E1000_DEV_ID_82572EI_COPPER: 489 case E1000_DEV_ID_82572EI_FIBER: 490 case E1000_DEV_ID_82572EI_SERDES: 491 case E1000_DEV_ID_82572EI: 492 hw->mac_type = em_82572; 493 break; 494 case E1000_DEV_ID_82573E: 495 case E1000_DEV_ID_82573E_IAMT: 496 case E1000_DEV_ID_82573E_PM: 497 case E1000_DEV_ID_82573L: 498 case E1000_DEV_ID_82573L_PL_1: 499 case E1000_DEV_ID_82573L_PL_2: 500 case E1000_DEV_ID_82573V_PM: 501 hw->mac_type = em_82573; 502 break; 503 case E1000_DEV_ID_82574L: 504 case E1000_DEV_ID_82574LA: 505 case E1000_DEV_ID_82583V: 506 hw->mac_type = em_82574; 507 break; 508 case E1000_DEV_ID_82575EB_PT: 509 case E1000_DEV_ID_82575EB_PF: 510 case E1000_DEV_ID_82575GB_QP: 511 case E1000_DEV_ID_82575GB_QP_PM: 512 case E1000_DEV_ID_82576: 513 case E1000_DEV_ID_82576_FIBER: 514 case E1000_DEV_ID_82576_SERDES: 515 case E1000_DEV_ID_82576_QUAD_COPPER: 516 case E1000_DEV_ID_82576_QUAD_CU_ET2: 517 case E1000_DEV_ID_82576_NS: 518 case E1000_DEV_ID_82576_NS_SERDES: 519 case E1000_DEV_ID_82576_SERDES_QUAD: 520 hw->mac_type = em_82575; 521 hw->initialize_hw_bits_disable = 1; 522 break; 523 case E1000_DEV_ID_82580_COPPER: 524 case E1000_DEV_ID_82580_FIBER: 525 case E1000_DEV_ID_82580_QUAD_FIBER: 526 case E1000_DEV_ID_82580_SERDES: 527 case E1000_DEV_ID_82580_SGMII: 528 case E1000_DEV_ID_82580_COPPER_DUAL: 529 case E1000_DEV_ID_DH89XXCC_SGMII: 530 case E1000_DEV_ID_DH89XXCC_SERDES: 531 case E1000_DEV_ID_DH89XXCC_BACKPLANE: 532 case E1000_DEV_ID_DH89XXCC_SFP: 533 hw->mac_type = em_82580; 534 hw->initialize_hw_bits_disable = 1; 535 break; 536 case E1000_DEV_ID_I210_COPPER: 537 case E1000_DEV_ID_I210_FIBER: 538 case E1000_DEV_ID_I210_SERDES: 539 case E1000_DEV_ID_I210_SGMII: 540 case E1000_DEV_ID_I210_COPPER_FLASHLESS: 541 case E1000_DEV_ID_I210_SERDES_FLASHLESS: 542 case E1000_DEV_ID_I211_COPPER: 543 hw->mac_type = em_i210; 544 hw->initialize_hw_bits_disable = 1; 545 hw->eee_enable = 1; 546 break; 547 case E1000_DEV_ID_I350_COPPER: 548 case E1000_DEV_ID_I350_FIBER: 549 case E1000_DEV_ID_I350_SERDES: 550 case E1000_DEV_ID_I350_SGMII: 551 case E1000_DEV_ID_I350_DA4: 552 case E1000_DEV_ID_I354_BACKPLANE_1GBPS: 553 case E1000_DEV_ID_I354_SGMII: 554 case E1000_DEV_ID_I354_BACKPLANE_2_5GBPS: 555 hw->mac_type = em_i350; 556 hw->initialize_hw_bits_disable = 1; 557 hw->eee_enable = 1; 558 break; 559 case E1000_DEV_ID_80003ES2LAN_COPPER_SPT: 560 case E1000_DEV_ID_80003ES2LAN_SERDES_SPT: 561 case E1000_DEV_ID_80003ES2LAN_COPPER_DPT: 562 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: 563 hw->mac_type = em_80003es2lan; 564 break; 565 case E1000_DEV_ID_ICH8_IFE: 566 case E1000_DEV_ID_ICH8_IFE_G: 567 case E1000_DEV_ID_ICH8_IFE_GT: 568 case E1000_DEV_ID_ICH8_IGP_AMT: 569 case E1000_DEV_ID_ICH8_IGP_C: 570 case E1000_DEV_ID_ICH8_IGP_M: 571 case E1000_DEV_ID_ICH8_IGP_M_AMT: 572 case E1000_DEV_ID_ICH8_82567V_3: 573 hw->mac_type = em_ich8lan; 574 break; 575 case E1000_DEV_ID_ICH9_BM: 576 case E1000_DEV_ID_ICH9_IFE: 577 case E1000_DEV_ID_ICH9_IFE_G: 578 case E1000_DEV_ID_ICH9_IFE_GT: 579 case E1000_DEV_ID_ICH9_IGP_AMT: 580 case E1000_DEV_ID_ICH9_IGP_C: 581 case E1000_DEV_ID_ICH9_IGP_M: 582 case E1000_DEV_ID_ICH9_IGP_M_AMT: 583 case E1000_DEV_ID_ICH9_IGP_M_V: 584 case E1000_DEV_ID_ICH10_R_BM_LF: 585 case E1000_DEV_ID_ICH10_R_BM_LM: 586 case E1000_DEV_ID_ICH10_R_BM_V: 587 hw->mac_type = em_ich9lan; 588 break; 589 case E1000_DEV_ID_ICH10_D_BM_LF: 590 case E1000_DEV_ID_ICH10_D_BM_LM: 591 hw->mac_type = em_ich10lan; 592 break; 593 case E1000_DEV_ID_PCH_M_HV_LC: 594 case E1000_DEV_ID_PCH_M_HV_LM: 595 case E1000_DEV_ID_PCH_D_HV_DC: 596 case E1000_DEV_ID_PCH_D_HV_DM: 597 hw->mac_type = em_pchlan; 598 hw->eee_enable = 1; 599 break; 600 case E1000_DEV_ID_PCH2_LV_LM: 601 case E1000_DEV_ID_PCH2_LV_V: 602 hw->mac_type = em_pch2lan; 603 break; 604 case E1000_DEV_ID_PCH_LPT_I217_LM: 605 case E1000_DEV_ID_PCH_LPT_I217_V: 606 case E1000_DEV_ID_PCH_LPTLP_I218_LM: 607 case E1000_DEV_ID_PCH_LPTLP_I218_V: 608 case E1000_DEV_ID_PCH_I218_LM2: 609 case E1000_DEV_ID_PCH_I218_V2: 610 case E1000_DEV_ID_PCH_I218_LM3: 611 case E1000_DEV_ID_PCH_I218_V3: 612 hw->mac_type = em_pch_lpt; 613 break; 614 case E1000_DEV_ID_PCH_SPT_I219_LM: 615 case E1000_DEV_ID_PCH_SPT_I219_V: 616 case E1000_DEV_ID_PCH_SPT_I219_LM2: 617 case E1000_DEV_ID_PCH_SPT_I219_V2: 618 hw->mac_type = em_pch_spt; 619 break; 620 case E1000_DEV_ID_EP80579_LAN_1: 621 hw->mac_type = em_icp_xxxx; 622 hw->icp_xxxx_port_num = 0; 623 break; 624 case E1000_DEV_ID_EP80579_LAN_2: 625 case E1000_DEV_ID_EP80579_LAN_4: 626 hw->mac_type = em_icp_xxxx; 627 hw->icp_xxxx_port_num = 1; 628 break; 629 case E1000_DEV_ID_EP80579_LAN_3: 630 case E1000_DEV_ID_EP80579_LAN_5: 631 hw->mac_type = em_icp_xxxx; 632 hw->icp_xxxx_port_num = 2; 633 break; 634 case E1000_DEV_ID_EP80579_LAN_6: 635 hw->mac_type = em_icp_xxxx; 636 hw->icp_xxxx_port_num = 3; 637 break; 638 default: 639 /* Should never have loaded on this device */ 640 return -E1000_ERR_MAC_TYPE; 641 } 642 643 switch (hw->mac_type) { 644 case em_ich8lan: 645 case em_ich9lan: 646 case em_ich10lan: 647 case em_pchlan: 648 case em_pch2lan: 649 case em_pch_lpt: 650 case em_pch_spt: 651 hw->swfwhw_semaphore_present = TRUE; 652 hw->asf_firmware_present = TRUE; 653 break; 654 case em_80003es2lan: 655 case em_82575: 656 case em_82580: 657 case em_i210: 658 case em_i350: 659 hw->swfw_sync_present = TRUE; 660 /* FALLTHROUGH */ 661 case em_82571: 662 case em_82572: 663 case em_82573: 664 case em_82574: 665 hw->eeprom_semaphore_present = TRUE; 666 /* FALLTHROUGH */ 667 case em_82541: 668 case em_82547: 669 case em_82541_rev_2: 670 case em_82547_rev_2: 671 hw->asf_firmware_present = TRUE; 672 break; 673 default: 674 break; 675 } 676 677 return E1000_SUCCESS; 678 } 679 /***************************************************************************** 680 * Set media type and TBI compatibility. 681 * 682 * hw - Struct containing variables accessed by shared code 683 * **************************************************************************/ 684 void 685 em_set_media_type(struct em_hw *hw) 686 { 687 uint32_t status, ctrl_ext; 688 DEBUGFUNC("em_set_media_type"); 689 690 if (hw->mac_type != em_82543) { 691 /* tbi_compatibility is only valid on 82543 */ 692 hw->tbi_compatibility_en = FALSE; 693 } 694 695 if (hw->mac_type == em_82575 || hw->mac_type == em_82580 || 696 hw->mac_type == em_i210 || hw->mac_type == em_i350) { 697 hw->media_type = em_media_type_copper; 698 699 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 700 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) { 701 case E1000_CTRL_EXT_LINK_MODE_SGMII: 702 ctrl_ext |= E1000_CTRL_I2C_ENA; 703 break; 704 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: 705 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES: 706 hw->media_type = em_media_type_internal_serdes; 707 ctrl_ext |= E1000_CTRL_I2C_ENA; 708 break; 709 default: 710 ctrl_ext &= ~E1000_CTRL_I2C_ENA; 711 break; 712 } 713 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 714 return; 715 } 716 717 switch (hw->device_id) { 718 case E1000_DEV_ID_82545GM_SERDES: 719 case E1000_DEV_ID_82546GB_SERDES: 720 case E1000_DEV_ID_82571EB_SERDES: 721 case E1000_DEV_ID_82571EB_SERDES_DUAL: 722 case E1000_DEV_ID_82571EB_SERDES_QUAD: 723 case E1000_DEV_ID_82572EI_SERDES: 724 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: 725 hw->media_type = em_media_type_internal_serdes; 726 break; 727 case E1000_DEV_ID_EP80579_LAN_1: 728 case E1000_DEV_ID_EP80579_LAN_2: 729 case E1000_DEV_ID_EP80579_LAN_3: 730 case E1000_DEV_ID_EP80579_LAN_4: 731 case E1000_DEV_ID_EP80579_LAN_5: 732 case E1000_DEV_ID_EP80579_LAN_6: 733 hw->media_type = em_media_type_copper; 734 break; 735 default: 736 switch (hw->mac_type) { 737 case em_82542_rev2_0: 738 case em_82542_rev2_1: 739 hw->media_type = em_media_type_fiber; 740 break; 741 case em_ich8lan: 742 case em_ich9lan: 743 case em_ich10lan: 744 case em_pchlan: 745 case em_pch2lan: 746 case em_pch_lpt: 747 case em_pch_spt: 748 case em_82573: 749 case em_82574: 750 /* 751 * The STATUS_TBIMODE bit is reserved or reused for 752 * the this device. 753 */ 754 hw->media_type = em_media_type_copper; 755 break; 756 default: 757 status = E1000_READ_REG(hw, STATUS); 758 if (status & E1000_STATUS_TBIMODE) { 759 hw->media_type = em_media_type_fiber; 760 /* tbi_compatibility not valid on fiber */ 761 hw->tbi_compatibility_en = FALSE; 762 } else { 763 hw->media_type = em_media_type_copper; 764 } 765 break; 766 } 767 } 768 } 769 /****************************************************************************** 770 * Reset the transmit and receive units; mask and clear all interrupts. 771 * 772 * hw - Struct containing variables accessed by shared code 773 *****************************************************************************/ 774 int32_t 775 em_reset_hw(struct em_hw *hw) 776 { 777 uint32_t ctrl; 778 uint32_t ctrl_ext; 779 uint32_t icr; 780 uint32_t manc; 781 uint32_t led_ctrl; 782 uint32_t timeout; 783 uint32_t extcnf_ctrl; 784 int32_t ret_val; 785 DEBUGFUNC("em_reset_hw"); 786 787 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ 788 if (hw->mac_type == em_82542_rev2_0) { 789 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 790 em_pci_clear_mwi(hw); 791 } 792 if (hw->bus_type == em_bus_type_pci_express) { 793 /* 794 * Prevent the PCI-E bus from sticking if there is no TLP 795 * connection on the last TLP read/write transaction when MAC 796 * is reset. 797 */ 798 if (em_disable_pciex_master(hw) != E1000_SUCCESS) { 799 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 800 } 801 } 802 803 /* Set the completion timeout for 82575 chips */ 804 if (hw->mac_type == em_82575 || hw->mac_type == em_82580 || 805 hw->mac_type == em_i210 || hw->mac_type == em_i350) { 806 ret_val = em_set_pciex_completion_timeout(hw); 807 if (ret_val) { 808 DEBUGOUT("PCI-E Set completion timeout has failed.\n"); 809 } 810 } 811 812 /* Clear interrupt mask to stop board from generating interrupts */ 813 DEBUGOUT("Masking off all interrupts\n"); 814 E1000_WRITE_REG(hw, IMC, 0xffffffff); 815 /* 816 * Disable the Transmit and Receive units. Then delay to allow any 817 * pending transactions to complete before we hit the MAC with the 818 * global reset. 819 */ 820 E1000_WRITE_REG(hw, RCTL, 0); 821 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP); 822 E1000_WRITE_FLUSH(hw); 823 /* 824 * The tbi_compatibility_on Flag must be cleared when Rctl is 825 * cleared. 826 */ 827 hw->tbi_compatibility_on = FALSE; 828 /* 829 * Delay to allow any outstanding PCI transactions to complete before 830 * resetting the device 831 */ 832 msec_delay(10); 833 834 ctrl = E1000_READ_REG(hw, CTRL); 835 836 /* Must reset the PHY before resetting the MAC */ 837 if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) { 838 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST)); 839 msec_delay(5); 840 } 841 /* 842 * Must acquire the MDIO ownership before MAC reset. Ownership 843 * defaults to firmware after a reset. 844 */ 845 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) { 846 timeout = 10; 847 848 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 849 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 850 851 do { 852 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); 853 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 854 855 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) 856 break; 857 else 858 extcnf_ctrl |= 859 E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 860 861 msec_delay(2); 862 timeout--; 863 } while (timeout); 864 } 865 /* Workaround for ICH8 bit corruption issue in FIFO memory */ 866 if (hw->mac_type == em_ich8lan) { 867 /* Set Tx and Rx buffer allocation to 8k apiece. */ 868 E1000_WRITE_REG(hw, PBA, E1000_PBA_8K); 869 /* Set Packet Buffer Size to 16k. */ 870 E1000_WRITE_REG(hw, PBS, E1000_PBS_16K); 871 } 872 /* 873 * Issue a global reset to the MAC. This will reset the chip's 874 * transmit, receive, DMA, and link units. It will not effect the 875 * current PCI configuration. The global reset bit is self- 876 * clearing, and should clear within a microsecond. 877 */ 878 DEBUGOUT("Issuing a global reset to MAC\n"); 879 880 switch (hw->mac_type) { 881 case em_82544: 882 case em_82540: 883 case em_82545: 884 case em_82546: 885 case em_82541: 886 case em_82541_rev_2: 887 /* 888 * These controllers can't ack the 64-bit write when issuing 889 * the reset, so use IO-mapping as a workaround to issue the 890 * reset 891 */ 892 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST)); 893 break; 894 case em_82545_rev_3: 895 case em_82546_rev_3: 896 /* Reset is performed on a shadow of the control register */ 897 E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST)); 898 break; 899 case em_ich8lan: 900 case em_ich9lan: 901 case em_ich10lan: 902 case em_pchlan: 903 case em_pch2lan: 904 case em_pch_lpt: 905 case em_pch_spt: 906 if (!hw->phy_reset_disable && 907 em_check_phy_reset_block(hw) == E1000_SUCCESS) { 908 /* 909 * PHY HW reset requires MAC CORE reset at the same 910 * time to make sure the interface between MAC and 911 * the external PHY is reset. 912 */ 913 ctrl |= E1000_CTRL_PHY_RST; 914 /* 915 * Gate automatic PHY configuration by hardware on 916 * non-managed 82579 917 */ 918 if ((hw->mac_type == em_pch2lan) && 919 !(E1000_READ_REG(hw, FWSM) & E1000_FWSM_FW_VALID)) { 920 em_gate_hw_phy_config_ich8lan(hw, TRUE); 921 } 922 } 923 em_get_software_flag(hw); 924 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); 925 msec_delay(5); 926 927 /* Ungate automatic PHY configuration on non-managed 82579 */ 928 if (hw->mac_type == em_pch2lan && !hw->phy_reset_disable && 929 !(E1000_READ_REG(hw, FWSM) & E1000_FWSM_FW_VALID)) { 930 msec_delay(10); 931 em_gate_hw_phy_config_ich8lan(hw, FALSE); 932 } 933 break; 934 default: 935 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); 936 break; 937 } 938 939 if (em_check_phy_reset_block(hw) == E1000_SUCCESS) { 940 if (hw->mac_type == em_pchlan) { 941 ret_val = em_hv_phy_workarounds_ich8lan(hw); 942 if (ret_val) 943 return ret_val; 944 } 945 else if (hw->mac_type == em_pch2lan) { 946 ret_val = em_lv_phy_workarounds_ich8lan(hw); 947 if (ret_val) 948 return ret_val; 949 } 950 } 951 952 /* 953 * After MAC reset, force reload of EEPROM to restore power-on 954 * settings to device. Later controllers reload the EEPROM 955 * automatically, so just wait for reload to complete. 956 */ 957 switch (hw->mac_type) { 958 case em_82542_rev2_0: 959 case em_82542_rev2_1: 960 case em_82543: 961 case em_82544: 962 /* Wait for reset to complete */ 963 usec_delay(10); 964 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 965 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 966 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 967 E1000_WRITE_FLUSH(hw); 968 /* Wait for EEPROM reload */ 969 msec_delay(2); 970 break; 971 case em_82541: 972 case em_82541_rev_2: 973 case em_82547: 974 case em_82547_rev_2: 975 /* Wait for EEPROM reload */ 976 msec_delay(20); 977 break; 978 case em_82573: 979 case em_82574: 980 if (em_is_onboard_nvm_eeprom(hw) == FALSE) { 981 usec_delay(10); 982 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 983 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 984 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 985 E1000_WRITE_FLUSH(hw); 986 } 987 /* FALLTHROUGH */ 988 989 /* Auto read done will delay 5ms or poll based on mac type */ 990 ret_val = em_get_auto_rd_done(hw); 991 if (ret_val) 992 return ret_val; 993 break; 994 default: 995 /* Wait for EEPROM reload (it happens automatically) */ 996 msec_delay(5); 997 break; 998 } 999 1000 /* Disable HW ARPs on ASF enabled adapters */ 1001 if (hw->mac_type >= em_82540 && hw->mac_type <= em_82547_rev_2 && 1002 hw->mac_type != em_icp_xxxx) { 1003 manc = E1000_READ_REG(hw, MANC); 1004 manc &= ~(E1000_MANC_ARP_EN); 1005 E1000_WRITE_REG(hw, MANC, manc); 1006 } 1007 if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) { 1008 em_phy_init_script(hw); 1009 1010 /* Configure activity LED after PHY reset */ 1011 led_ctrl = E1000_READ_REG(hw, LEDCTL); 1012 led_ctrl &= IGP_ACTIVITY_LED_MASK; 1013 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 1014 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 1015 } 1016 1017 /* 1018 * For PCH, this write will make sure that any noise 1019 * will be detected as a CRC error and be dropped rather than show up 1020 * as a bad packet to the DMA engine. 1021 */ 1022 if (hw->mac_type == em_pchlan) 1023 E1000_WRITE_REG(hw, CRC_OFFSET, 0x65656565); 1024 1025 /* Clear interrupt mask to stop board from generating interrupts */ 1026 DEBUGOUT("Masking off all interrupts\n"); 1027 E1000_WRITE_REG(hw, IMC, 0xffffffff); 1028 1029 /* Clear any pending interrupt events. */ 1030 icr = E1000_READ_REG(hw, ICR); 1031 1032 /* If MWI was previously enabled, reenable it. */ 1033 if (hw->mac_type == em_82542_rev2_0) { 1034 if (hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1035 em_pci_set_mwi(hw); 1036 } 1037 if (IS_ICH8(hw->mac_type)) { 1038 uint32_t kab = E1000_READ_REG(hw, KABGTXD); 1039 kab |= E1000_KABGTXD_BGSQLBIAS; 1040 E1000_WRITE_REG(hw, KABGTXD, kab); 1041 } 1042 1043 if (hw->mac_type == em_82580 || hw->mac_type == em_i350) { 1044 uint32_t mdicnfg; 1045 uint16_t nvm_data; 1046 1047 /* clear global device reset status bit */ 1048 EM_WRITE_REG(hw, E1000_STATUS, E1000_STATUS_DEV_RST_SET); 1049 1050 em_read_eeprom(hw, EEPROM_INIT_CONTROL3_PORT_A + 1051 NVM_82580_LAN_FUNC_OFFSET(hw->bus_func), 1, 1052 &nvm_data); 1053 1054 mdicnfg = EM_READ_REG(hw, E1000_MDICNFG); 1055 if (nvm_data & NVM_WORD24_EXT_MDIO) 1056 mdicnfg |= E1000_MDICNFG_EXT_MDIO; 1057 if (nvm_data & NVM_WORD24_COM_MDIO) 1058 mdicnfg |= E1000_MDICNFG_COM_MDIO; 1059 EM_WRITE_REG(hw, E1000_MDICNFG, mdicnfg); 1060 } 1061 1062 if (hw->mac_type == em_i210 || hw->mac_type == em_i350) 1063 em_set_eee_i350(hw); 1064 1065 return E1000_SUCCESS; 1066 } 1067 1068 /****************************************************************************** 1069 * 1070 * Initialize a number of hardware-dependent bits 1071 * 1072 * hw: Struct containing variables accessed by shared code 1073 * 1074 *****************************************************************************/ 1075 STATIC void 1076 em_initialize_hardware_bits(struct em_hw *hw) 1077 { 1078 DEBUGFUNC("em_initialize_hardware_bits"); 1079 1080 if ((hw->mac_type >= em_82571) && (!hw->initialize_hw_bits_disable)) { 1081 /* Settings common to all silicon */ 1082 uint32_t reg_ctrl, reg_ctrl_ext; 1083 uint32_t reg_tarc0, reg_tarc1; 1084 uint32_t reg_tctl; 1085 uint32_t reg_txdctl, reg_txdctl1; 1086 reg_tarc0 = E1000_READ_REG(hw, TARC0); 1087 reg_tarc0 &= ~0x78000000; /* Clear bits 30, 29, 28, and 1088 * 27 */ 1089 1090 reg_txdctl = E1000_READ_REG(hw, TXDCTL); 1091 reg_txdctl |= E1000_TXDCTL_COUNT_DESC; /* Set bit 22 */ 1092 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl); 1093 1094 reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1); 1095 reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC; /* Set bit 22 */ 1096 E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1); 1097 1098 switch (hw->mac_type) { 1099 case em_82571: 1100 case em_82572: 1101 reg_tarc1 = E1000_READ_REG(hw, TARC1); 1102 reg_tctl = E1000_READ_REG(hw, TCTL); 1103 1104 /* Set the phy Tx compatible mode bits */ 1105 reg_tarc1 &= ~0x60000000; /* Clear bits 30 and 29 */ 1106 1107 reg_tarc0 |= 0x07800000; /* Set TARC0 bits 23-26 */ 1108 reg_tarc1 |= 0x07000000; /* Set TARC1 bits 24-26 */ 1109 1110 if (reg_tctl & E1000_TCTL_MULR) 1111 /* Clear bit 28 if MULR is 1b */ 1112 reg_tarc1 &= ~0x10000000; 1113 else 1114 /* Set bit 28 if MULR is 0b */ 1115 reg_tarc1 |= 0x10000000; 1116 1117 E1000_WRITE_REG(hw, TARC1, reg_tarc1); 1118 break; 1119 case em_82573: 1120 case em_82574: 1121 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1122 reg_ctrl = E1000_READ_REG(hw, CTRL); 1123 1124 reg_ctrl_ext &= ~0x00800000; /* Clear bit 23 */ 1125 reg_ctrl_ext |= 0x00400000; /* Set bit 22 */ 1126 reg_ctrl &= ~0x20000000; /* Clear bit 29 */ 1127 1128 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); 1129 E1000_WRITE_REG(hw, CTRL, reg_ctrl); 1130 break; 1131 case em_80003es2lan: 1132 if ((hw->media_type == em_media_type_fiber) || 1133 (hw->media_type == em_media_type_internal_serdes)) { 1134 /* Clear bit 20 */ 1135 reg_tarc0 &= ~0x00100000; 1136 } 1137 reg_tctl = E1000_READ_REG(hw, TCTL); 1138 reg_tarc1 = E1000_READ_REG(hw, TARC1); 1139 if (reg_tctl & E1000_TCTL_MULR) 1140 /* Clear bit 28 if MULR is 1b */ 1141 reg_tarc1 &= ~0x10000000; 1142 else 1143 /* Set bit 28 if MULR is 0b */ 1144 reg_tarc1 |= 0x10000000; 1145 1146 E1000_WRITE_REG(hw, TARC1, reg_tarc1); 1147 break; 1148 case em_ich8lan: 1149 case em_ich9lan: 1150 case em_ich10lan: 1151 case em_pchlan: 1152 case em_pch2lan: 1153 case em_pch_lpt: 1154 case em_pch_spt: 1155 if (hw->mac_type == em_ich8lan) 1156 /* Set TARC0 bits 29 and 28 */ 1157 reg_tarc0 |= 0x30000000; 1158 1159 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1160 reg_ctrl_ext |= 0x00400000; /* Set bit 22 */ 1161 /* Enable PHY low-power state when MAC is at D3 w/o WoL */ 1162 if (hw->mac_type >= em_pchlan) 1163 reg_ctrl_ext |= E1000_CTRL_EXT_PHYPDEN; 1164 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); 1165 1166 reg_tarc0 |= 0x0d800000; /* Set TARC0 bits 23, 1167 * 24, 26, 27 */ 1168 1169 reg_tarc1 = E1000_READ_REG(hw, TARC1); 1170 reg_tctl = E1000_READ_REG(hw, TCTL); 1171 1172 if (reg_tctl & E1000_TCTL_MULR) 1173 /* Clear bit 28 if MULR is 1b */ 1174 reg_tarc1 &= ~0x10000000; 1175 else 1176 /* Set bit 28 if MULR is 0b */ 1177 reg_tarc1 |= 0x10000000; 1178 1179 reg_tarc1 |= 0x45000000; /* Set bit 24, 26 and 1180 * 30 */ 1181 1182 E1000_WRITE_REG(hw, TARC1, reg_tarc1); 1183 break; 1184 default: 1185 break; 1186 } 1187 1188 E1000_WRITE_REG(hw, TARC0, reg_tarc0); 1189 } 1190 } 1191 1192 /****************************************************************************** 1193 * Performs basic configuration of the adapter. 1194 * 1195 * hw - Struct containing variables accessed by shared code 1196 * 1197 * Assumes that the controller has previously been reset and is in a 1198 * post-reset uninitialized state. Initializes the receive address registers, 1199 * multicast table, and VLAN filter table. Calls routines to setup link 1200 * configuration and flow control settings. Clears all on-chip counters. Leaves 1201 * the transmit and receive units disabled and uninitialized. 1202 *****************************************************************************/ 1203 int32_t 1204 em_init_hw(struct em_hw *hw) 1205 { 1206 uint32_t ctrl; 1207 uint32_t i; 1208 int32_t ret_val; 1209 uint16_t pcix_cmd_word; 1210 uint16_t pcix_stat_hi_word; 1211 uint16_t cmd_mmrbc; 1212 uint16_t stat_mmrbc; 1213 uint32_t mta_size; 1214 uint32_t reg_data; 1215 uint32_t ctrl_ext; 1216 uint32_t snoop; 1217 uint32_t fwsm; 1218 DEBUGFUNC("em_init_hw"); 1219 1220 /* force full DMA clock frequency for ICH8 */ 1221 if (hw->mac_type == em_ich8lan) { 1222 reg_data = E1000_READ_REG(hw, STATUS); 1223 reg_data &= ~0x80000000; 1224 E1000_WRITE_REG(hw, STATUS, reg_data); 1225 } 1226 1227 if (hw->mac_type == em_pchlan || 1228 hw->mac_type == em_pch2lan || 1229 hw->mac_type == em_pch_lpt || 1230 hw->mac_type == em_pch_spt) { 1231 /* 1232 * The MAC-PHY interconnect may still be in SMBus mode 1233 * after Sx->S0. Toggle the LANPHYPC Value bit to force 1234 * the interconnect to PCIe mode, but only if there is no 1235 * firmware present otherwise firmware will have done it. 1236 */ 1237 fwsm = E1000_READ_REG(hw, FWSM); 1238 if ((fwsm & E1000_FWSM_FW_VALID) == 0) { 1239 ctrl = E1000_READ_REG(hw, CTRL); 1240 ctrl |= E1000_CTRL_LANPHYPC_OVERRIDE; 1241 ctrl &= ~E1000_CTRL_LANPHYPC_VALUE; 1242 E1000_WRITE_REG(hw, CTRL, ctrl); 1243 usec_delay(10); 1244 ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE; 1245 E1000_WRITE_REG(hw, CTRL, ctrl); 1246 msec_delay(50); 1247 } 1248 1249 /* Gate automatic PHY configuration on non-managed 82579 */ 1250 if (hw->mac_type == em_pch2lan) 1251 em_gate_hw_phy_config_ich8lan(hw, TRUE); 1252 1253 /* 1254 * Reset the PHY before any acccess to it. Doing so, 1255 * ensures that the PHY is in a known good state before 1256 * we read/write PHY registers. The generic reset is 1257 * sufficient here, because we haven't determined 1258 * the PHY type yet. 1259 */ 1260 em_phy_reset(hw); 1261 1262 /* Ungate automatic PHY configuration on non-managed 82579 */ 1263 if (hw->mac_type == em_pch2lan && 1264 (fwsm & E1000_FWSM_FW_VALID) == 0) 1265 em_gate_hw_phy_config_ich8lan(hw, FALSE); 1266 1267 /* Set MDIO slow mode before any other MDIO access */ 1268 ret_val = em_set_mdio_slow_mode_hv(hw); 1269 if (ret_val) 1270 return ret_val; 1271 } 1272 1273 /* Initialize Identification LED */ 1274 ret_val = em_id_led_init(hw); 1275 if (ret_val) { 1276 DEBUGOUT("Error Initializing Identification LED\n"); 1277 return ret_val; 1278 } 1279 /* Set the media type and TBI compatibility */ 1280 em_set_media_type(hw); 1281 1282 /* Must be called after em_set_media_type because media_type is used */ 1283 em_initialize_hardware_bits(hw); 1284 1285 /* Disabling VLAN filtering. */ 1286 DEBUGOUT("Initializing the IEEE VLAN\n"); 1287 /* VET hardcoded to standard value and VFTA removed in ICH8/ICH9 LAN */ 1288 if (!IS_ICH8(hw->mac_type)) { 1289 if (hw->mac_type < em_82545_rev_3) 1290 E1000_WRITE_REG(hw, VET, 0); 1291 if (hw->mac_type == em_i350) 1292 em_clear_vfta_i350(hw); 1293 else 1294 em_clear_vfta(hw); 1295 } 1296 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ 1297 if (hw->mac_type == em_82542_rev2_0) { 1298 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 1299 em_pci_clear_mwi(hw); 1300 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST); 1301 E1000_WRITE_FLUSH(hw); 1302 msec_delay(5); 1303 } 1304 /* 1305 * Setup the receive address. This involves initializing all of the 1306 * Receive Address Registers (RARs 0 - 15). 1307 */ 1308 em_init_rx_addrs(hw); 1309 1310 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI*/ 1311 if (hw->mac_type == em_82542_rev2_0) { 1312 E1000_WRITE_REG(hw, RCTL, 0); 1313 E1000_WRITE_FLUSH(hw); 1314 msec_delay(1); 1315 if (hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1316 em_pci_set_mwi(hw); 1317 } 1318 /* Zero out the Multicast HASH table */ 1319 DEBUGOUT("Zeroing the MTA\n"); 1320 mta_size = E1000_MC_TBL_SIZE; 1321 if (IS_ICH8(hw->mac_type)) 1322 mta_size = E1000_MC_TBL_SIZE_ICH8LAN; 1323 for (i = 0; i < mta_size; i++) { 1324 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 1325 /* 1326 * use write flush to prevent Memory Write Block (MWB) from 1327 * occuring when accessing our register space 1328 */ 1329 E1000_WRITE_FLUSH(hw); 1330 } 1331 /* 1332 * Set the PCI priority bit correctly in the CTRL register. This 1333 * determines if the adapter gives priority to receives, or if it 1334 * gives equal priority to transmits and receives. Valid only on 1335 * 82542 and 82543 silicon. 1336 */ 1337 if (hw->dma_fairness && hw->mac_type <= em_82543) { 1338 ctrl = E1000_READ_REG(hw, CTRL); 1339 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR); 1340 } 1341 switch (hw->mac_type) { 1342 case em_82545_rev_3: 1343 case em_82546_rev_3: 1344 break; 1345 default: 1346 /* 1347 * Workaround for PCI-X problem when BIOS sets MMRBC 1348 * incorrectly. 1349 */ 1350 if (hw->bus_type == em_bus_type_pcix) { 1351 em_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, 1352 &pcix_cmd_word); 1353 em_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, 1354 &pcix_stat_hi_word); 1355 cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) 1356 >> PCIX_COMMAND_MMRBC_SHIFT; 1357 stat_mmrbc = (pcix_stat_hi_word & 1358 PCIX_STATUS_HI_MMRBC_MASK) >> 1359 PCIX_STATUS_HI_MMRBC_SHIFT; 1360 1361 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) 1362 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; 1363 if (cmd_mmrbc > stat_mmrbc) { 1364 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK; 1365 pcix_cmd_word |= stat_mmrbc << 1366 PCIX_COMMAND_MMRBC_SHIFT; 1367 em_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, 1368 &pcix_cmd_word); 1369 } 1370 } 1371 break; 1372 } 1373 1374 /* More time needed for PHY to initialize */ 1375 if (IS_ICH8(hw->mac_type)) 1376 msec_delay(15); 1377 1378 /* 1379 * The 82578 Rx buffer will stall if wakeup is enabled in host and 1380 * the ME. Reading the BM_WUC register will clear the host wakeup bit. 1381 * Reset the phy after disabling host wakeup to reset the Rx buffer. 1382 */ 1383 if (hw->phy_type == em_phy_82578) { 1384 em_read_phy_reg(hw, PHY_REG(BM_WUC_PAGE, 1), 1385 (uint16_t *)®_data); 1386 ret_val = em_phy_reset(hw); 1387 if (ret_val) 1388 return ret_val; 1389 } 1390 1391 /* Call a subroutine to configure the link and setup flow control. */ 1392 ret_val = em_setup_link(hw); 1393 1394 /* Set the transmit descriptor write-back policy */ 1395 if (hw->mac_type > em_82544) { 1396 ctrl = E1000_READ_REG(hw, TXDCTL); 1397 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | 1398 E1000_TXDCTL_FULL_TX_DESC_WB; 1399 E1000_WRITE_REG(hw, TXDCTL, ctrl); 1400 } 1401 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) { 1402 em_enable_tx_pkt_filtering(hw); 1403 } 1404 switch (hw->mac_type) { 1405 default: 1406 break; 1407 case em_80003es2lan: 1408 /* Enable retransmit on late collisions */ 1409 reg_data = E1000_READ_REG(hw, TCTL); 1410 reg_data |= E1000_TCTL_RTLC; 1411 E1000_WRITE_REG(hw, TCTL, reg_data); 1412 1413 /* Configure Gigabit Carry Extend Padding */ 1414 reg_data = E1000_READ_REG(hw, TCTL_EXT); 1415 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK; 1416 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX; 1417 E1000_WRITE_REG(hw, TCTL_EXT, reg_data); 1418 1419 /* Configure Transmit Inter-Packet Gap */ 1420 reg_data = E1000_READ_REG(hw, TIPG); 1421 reg_data &= ~E1000_TIPG_IPGT_MASK; 1422 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; 1423 E1000_WRITE_REG(hw, TIPG, reg_data); 1424 1425 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001); 1426 reg_data &= ~0x00100000; 1427 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data); 1428 /* FALLTHROUGH */ 1429 case em_82571: 1430 case em_82572: 1431 case em_82575: 1432 case em_82580: 1433 case em_i210: 1434 case em_i350: 1435 case em_ich8lan: 1436 case em_ich9lan: 1437 case em_ich10lan: 1438 case em_pchlan: 1439 case em_pch2lan: 1440 case em_pch_lpt: 1441 case em_pch_spt: 1442 ctrl = E1000_READ_REG(hw, TXDCTL1); 1443 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | 1444 E1000_TXDCTL_FULL_TX_DESC_WB; 1445 E1000_WRITE_REG(hw, TXDCTL1, ctrl); 1446 break; 1447 } 1448 1449 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) { 1450 uint32_t gcr = E1000_READ_REG(hw, GCR); 1451 gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; 1452 E1000_WRITE_REG(hw, GCR, gcr); 1453 } 1454 /* 1455 * Clear all of the statistics registers (clear on read). It is 1456 * important that we do this after we have tried to establish link 1457 * because the symbol error count will increment wildly if there is 1458 * no link. 1459 */ 1460 em_clear_hw_cntrs(hw); 1461 /* 1462 * ICH8 No-snoop bits are opposite polarity. Set to snoop by default 1463 * after reset. 1464 */ 1465 if (IS_ICH8(hw->mac_type)) { 1466 if (hw->mac_type == em_ich8lan) 1467 snoop = PCI_EX_82566_SNOOP_ALL; 1468 else 1469 snoop = (u_int32_t) ~ (PCI_EX_NO_SNOOP_ALL); 1470 1471 em_set_pci_ex_no_snoop(hw, snoop); 1472 } 1473 1474 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER || 1475 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) { 1476 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1477 /* 1478 * Relaxed ordering must be disabled to avoid a parity error 1479 * crash in a PCI slot. 1480 */ 1481 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 1482 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1483 } 1484 return ret_val; 1485 } 1486 1487 /****************************************************************************** 1488 * Adjust SERDES output amplitude based on EEPROM setting. 1489 * 1490 * hw - Struct containing variables accessed by shared code. 1491 *****************************************************************************/ 1492 static int32_t 1493 em_adjust_serdes_amplitude(struct em_hw *hw) 1494 { 1495 uint16_t eeprom_data; 1496 int32_t ret_val; 1497 DEBUGFUNC("em_adjust_serdes_amplitude"); 1498 1499 if (hw->media_type != em_media_type_internal_serdes || 1500 hw->mac_type >= em_82575) 1501 return E1000_SUCCESS; 1502 1503 switch (hw->mac_type) { 1504 case em_82545_rev_3: 1505 case em_82546_rev_3: 1506 break; 1507 default: 1508 return E1000_SUCCESS; 1509 } 1510 1511 ret_val = em_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data); 1512 if (ret_val) { 1513 return ret_val; 1514 } 1515 if (eeprom_data != EEPROM_RESERVED_WORD) { 1516 /* Adjust SERDES output amplitude only. */ 1517 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK; 1518 ret_val = em_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, 1519 eeprom_data); 1520 if (ret_val) 1521 return ret_val; 1522 } 1523 return E1000_SUCCESS; 1524 } 1525 1526 /****************************************************************************** 1527 * Configures flow control and link settings. 1528 * 1529 * hw - Struct containing variables accessed by shared code 1530 * 1531 * Determines which flow control settings to use. Calls the appropriate media- 1532 * specific link configuration function. Configures the flow control settings. 1533 * Assuming the adapter has a valid link partner, a valid link should be 1534 * established. Assumes the hardware has previously been reset and the 1535 * transmitter and receiver are not enabled. 1536 *****************************************************************************/ 1537 int32_t 1538 em_setup_link(struct em_hw *hw) 1539 { 1540 uint32_t ctrl_ext; 1541 int32_t ret_val; 1542 uint16_t eeprom_data; 1543 uint16_t eeprom_control2_reg_offset; 1544 DEBUGFUNC("em_setup_link"); 1545 1546 eeprom_control2_reg_offset = 1547 (hw->mac_type != em_icp_xxxx) 1548 ? EEPROM_INIT_CONTROL2_REG 1549 : EEPROM_INIT_CONTROL3_ICP_xxxx(hw->icp_xxxx_port_num); 1550 /* 1551 * In the case of the phy reset being blocked, we already have a 1552 * link. We do not have to set it up again. 1553 */ 1554 if (em_check_phy_reset_block(hw)) 1555 return E1000_SUCCESS; 1556 /* 1557 * Read and store word 0x0F of the EEPROM. This word contains bits 1558 * that determine the hardware's default PAUSE (flow control) mode, a 1559 * bit that determines whether the HW defaults to enabling or 1560 * disabling auto-negotiation, and the direction of the SW defined 1561 * pins. If there is no SW over-ride of the flow control setting, 1562 * then the variable hw->fc will be initialized based on a value in 1563 * the EEPROM. 1564 */ 1565 if (hw->fc == E1000_FC_DEFAULT) { 1566 switch (hw->mac_type) { 1567 case em_ich8lan: 1568 case em_ich9lan: 1569 case em_ich10lan: 1570 case em_pchlan: 1571 case em_pch2lan: 1572 case em_pch_lpt: 1573 case em_pch_spt: 1574 case em_82573: 1575 case em_82574: 1576 hw->fc = E1000_FC_FULL; 1577 break; 1578 default: 1579 ret_val = em_read_eeprom(hw, 1580 eeprom_control2_reg_offset, 1, &eeprom_data); 1581 if (ret_val) { 1582 DEBUGOUT("EEPROM Read Error\n"); 1583 return -E1000_ERR_EEPROM; 1584 } 1585 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0) 1586 hw->fc = E1000_FC_NONE; 1587 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 1588 EEPROM_WORD0F_ASM_DIR) 1589 hw->fc = E1000_FC_TX_PAUSE; 1590 else 1591 hw->fc = E1000_FC_FULL; 1592 break; 1593 } 1594 } 1595 /* 1596 * We want to save off the original Flow Control configuration just 1597 * in case we get disconnected and then reconnected into a different 1598 * hub or switch with different Flow Control capabilities. 1599 */ 1600 if (hw->mac_type == em_82542_rev2_0) 1601 hw->fc &= (~E1000_FC_TX_PAUSE); 1602 1603 if ((hw->mac_type < em_82543) && (hw->report_tx_early == 1)) 1604 hw->fc &= (~E1000_FC_RX_PAUSE); 1605 1606 hw->original_fc = hw->fc; 1607 1608 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc); 1609 /* 1610 * Take the 4 bits from EEPROM word 0x0F that determine the initial 1611 * polarity value for the SW controlled pins, and setup the Extended 1612 * Device Control reg with that info. This is needed because one of 1613 * the SW controlled pins is used for signal detection. So this 1614 * should be done before em_setup_pcs_link() or em_phy_setup() is 1615 * called. 1616 */ 1617 if (hw->mac_type == em_82543) { 1618 ret_val = em_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1619 1, &eeprom_data); 1620 if (ret_val) { 1621 DEBUGOUT("EEPROM Read Error\n"); 1622 return -E1000_ERR_EEPROM; 1623 } 1624 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << 1625 SWDPIO__EXT_SHIFT); 1626 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1627 } 1628 /* Make sure we have a valid PHY */ 1629 ret_val = em_detect_gig_phy(hw); 1630 if (ret_val) { 1631 DEBUGOUT("Error, did not detect valid phy.\n"); 1632 if (hw->mac_type == em_icp_xxxx) 1633 return E1000_DEFER_INIT; 1634 else 1635 return ret_val; 1636 } 1637 DEBUGOUT1("Phy ID = %x \n", hw->phy_id); 1638 1639 /* Call the necessary subroutine to configure the link. */ 1640 switch (hw->media_type) { 1641 case em_media_type_copper: 1642 case em_media_type_oem: 1643 ret_val = em_setup_copper_link(hw); 1644 break; 1645 default: 1646 ret_val = em_setup_fiber_serdes_link(hw); 1647 break; 1648 } 1649 /* 1650 * Initialize the flow control address, type, and PAUSE timer 1651 * registers to their default values. This is done even if flow 1652 * control is disabled, because it does not hurt anything to 1653 * initialize these registers. 1654 */ 1655 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n" 1656 ); 1657 1658 /* 1659 * FCAL/H and FCT are hardcoded to standard values in 1660 * em_ich8lan / em_ich9lan / em_ich10lan. 1661 */ 1662 if (!IS_ICH8(hw->mac_type)) { 1663 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE); 1664 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH); 1665 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW); 1666 } 1667 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time); 1668 1669 if (hw->phy_type == em_phy_82577 || 1670 hw->phy_type == em_phy_82578 || 1671 hw->phy_type == em_phy_82579 || 1672 hw->phy_type == em_phy_i217) { 1673 E1000_WRITE_REG(hw, FCRTV_PCH, 0x1000); 1674 em_write_phy_reg(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27), 1675 hw->fc_pause_time); 1676 } 1677 1678 /* 1679 * Set the flow control receive threshold registers. Normally, these 1680 * registers will be set to a default threshold that may be adjusted 1681 * later by the driver's runtime code. However, if the ability to 1682 * transmit pause frames in not enabled, then these registers will be 1683 * set to 0. 1684 */ 1685 if (!(hw->fc & E1000_FC_TX_PAUSE)) { 1686 E1000_WRITE_REG(hw, FCRTL, 0); 1687 E1000_WRITE_REG(hw, FCRTH, 0); 1688 } else { 1689 /* 1690 * We need to set up the Receive Threshold high and low water 1691 * marks as well as (optionally) enabling the transmission of 1692 * XON frames. 1693 */ 1694 if (hw->fc_send_xon) { 1695 E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water 1696 | E1000_FCRTL_XONE)); 1697 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); 1698 } else { 1699 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water); 1700 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); 1701 } 1702 } 1703 return ret_val; 1704 } 1705 1706 void 1707 em_power_up_serdes_link_82575(struct em_hw *hw) 1708 { 1709 uint32_t reg; 1710 1711 /* Enable PCS to turn on link */ 1712 reg = E1000_READ_REG(hw, PCS_CFG0); 1713 reg |= E1000_PCS_CFG_PCS_EN; 1714 E1000_WRITE_REG(hw, PCS_CFG0, reg); 1715 1716 /* Power up the laser */ 1717 reg = E1000_READ_REG(hw, CTRL_EXT); 1718 reg &= ~E1000_CTRL_EXT_SDP3_DATA; 1719 E1000_WRITE_REG(hw, CTRL_EXT, reg); 1720 1721 /* flush the write to verify completion */ 1722 E1000_WRITE_FLUSH(hw); 1723 delay(5); 1724 } 1725 1726 /****************************************************************************** 1727 * Sets up link for a fiber based or serdes based adapter 1728 * 1729 * hw - Struct containing variables accessed by shared code 1730 * 1731 * Manipulates Physical Coding Sublayer functions in order to configure 1732 * link. Assumes the hardware has been previously reset and the transmitter 1733 * and receiver are not enabled. 1734 *****************************************************************************/ 1735 static int32_t 1736 em_setup_fiber_serdes_link(struct em_hw *hw) 1737 { 1738 uint32_t ctrl, ctrl_ext, reg; 1739 uint32_t status; 1740 uint32_t txcw = 0; 1741 uint32_t i; 1742 uint32_t signal = 0; 1743 int32_t ret_val; 1744 DEBUGFUNC("em_setup_fiber_serdes_link"); 1745 /* 1746 * On 82571 and 82572 Fiber connections, SerDes loopback mode 1747 * persists until explicitly turned off or a power cycle is 1748 * performed. A read to the register does not indicate its status. 1749 * Therefore, we ensure loopback mode is disabled during 1750 * initialization. 1751 */ 1752 if (hw->mac_type == em_82571 || hw->mac_type == em_82572 || 1753 hw->mac_type >= em_82575) 1754 E1000_WRITE_REG(hw, SCTL, E1000_DISABLE_SERDES_LOOPBACK); 1755 1756 if (hw->mac_type >= em_82575) 1757 em_power_up_serdes_link_82575(hw); 1758 1759 /* 1760 * On adapters with a MAC newer than 82544, SWDP 1 will be set when 1761 * the optics detect a signal. On older adapters, it will be cleared 1762 * when there is a signal. This applies to fiber media only. If 1763 * we're on serdes media, adjust the output amplitude to value set in 1764 * the EEPROM. 1765 */ 1766 ctrl = E1000_READ_REG(hw, CTRL); 1767 if (hw->media_type == em_media_type_fiber) 1768 signal = (hw->mac_type > em_82544) ? E1000_CTRL_SWDPIN1 : 0; 1769 1770 ret_val = em_adjust_serdes_amplitude(hw); 1771 if (ret_val) 1772 return ret_val; 1773 1774 /* Take the link out of reset */ 1775 ctrl &= ~(E1000_CTRL_LRST); 1776 1777 if (hw->mac_type >= em_82575) { 1778 /* set both sw defined pins on 82575/82576*/ 1779 ctrl |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1; 1780 1781 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1782 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) { 1783 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: 1784 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES: 1785 /* the backplane is always connected */ 1786 reg = E1000_READ_REG(hw, PCS_LCTL); 1787 reg |= E1000_PCS_LCTL_FORCE_FCTRL; 1788 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL; 1789 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */ 1790 DEBUGOUT("Configuring Forced Link\n"); 1791 E1000_WRITE_REG(hw, PCS_LCTL, reg); 1792 em_force_mac_fc(hw); 1793 hw->autoneg_failed = 0; 1794 return E1000_SUCCESS; 1795 break; 1796 default: 1797 /* Set switch control to serdes energy detect */ 1798 reg = E1000_READ_REG(hw, CONNSW); 1799 reg |= E1000_CONNSW_ENRGSRC; 1800 E1000_WRITE_REG(hw, CONNSW, reg); 1801 break; 1802 } 1803 } 1804 1805 /* Adjust VCO speed to improve BER performance */ 1806 ret_val = em_set_vco_speed(hw); 1807 if (ret_val) 1808 return ret_val; 1809 1810 em_config_collision_dist(hw); 1811 /* 1812 * Check for a software override of the flow control settings, and 1813 * setup the device accordingly. If auto-negotiation is enabled, 1814 * then software will have to set the "PAUSE" bits to the correct 1815 * value in the Tranmsit Config Word Register (TXCW) and re-start 1816 * auto-negotiation. However, if auto-negotiation is disabled, then 1817 * software will have to manually configure the two flow control 1818 * enable bits in the CTRL register. 1819 * 1820 * The possible values of the "fc" parameter are: 0: Flow control is 1821 * completely disabled 1: Rx flow control is enabled (we can receive 1822 * pause frames, but not send pause frames). 2: Tx flow control is 1823 * enabled (we can send pause frames but we do not support receiving 1824 * pause frames). 3: Both Rx and TX flow control (symmetric) are 1825 * enabled. 1826 */ 1827 switch (hw->fc) { 1828 case E1000_FC_NONE: 1829 /* 1830 * Flow control is completely disabled by a software 1831 * over-ride. 1832 */ 1833 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 1834 break; 1835 case E1000_FC_RX_PAUSE: 1836 /* 1837 * RX Flow control is enabled and TX Flow control is disabled 1838 * by a software over-ride. Since there really isn't a way to 1839 * advertise that we are capable of RX Pause ONLY, we will 1840 * advertise that we support both symmetric and asymmetric RX 1841 * PAUSE. Later, we will disable the adapter's ability to 1842 * send PAUSE frames. 1843 */ 1844 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | 1845 E1000_TXCW_PAUSE_MASK); 1846 break; 1847 case E1000_FC_TX_PAUSE: 1848 /* 1849 * TX Flow control is enabled, and RX Flow control is 1850 * disabled, by a software over-ride. 1851 */ 1852 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 1853 break; 1854 case E1000_FC_FULL: 1855 /* 1856 * Flow control (both RX and TX) is enabled by a software 1857 * over-ride. 1858 */ 1859 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | 1860 E1000_TXCW_PAUSE_MASK); 1861 break; 1862 default: 1863 DEBUGOUT("Flow control param set incorrectly\n"); 1864 return -E1000_ERR_CONFIG; 1865 break; 1866 } 1867 /* 1868 * Since auto-negotiation is enabled, take the link out of reset (the 1869 * link will be in reset, because we previously reset the chip). This 1870 * will restart auto-negotiation. If auto-neogtiation is successful 1871 * then the link-up status bit will be set and the flow control 1872 * enable bits (RFCE and TFCE) will be set according to their 1873 * negotiated value. 1874 */ 1875 DEBUGOUT("Auto-negotiation enabled\n"); 1876 1877 E1000_WRITE_REG(hw, TXCW, txcw); 1878 E1000_WRITE_REG(hw, CTRL, ctrl); 1879 E1000_WRITE_FLUSH(hw); 1880 1881 hw->txcw = txcw; 1882 msec_delay(1); 1883 /* 1884 * If we have a signal (the cable is plugged in) then poll for a 1885 * "Link-Up" indication in the Device Status Register. Time-out if a 1886 * link isn't seen in 500 milliseconds seconds (Auto-negotiation 1887 * should complete in less than 500 milliseconds even if the other 1888 * end is doing it in SW). For internal serdes, we just assume a 1889 * signal is present, then poll. 1890 */ 1891 if (hw->media_type == em_media_type_internal_serdes || 1892 (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) { 1893 DEBUGOUT("Looking for Link\n"); 1894 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) { 1895 msec_delay(10); 1896 status = E1000_READ_REG(hw, STATUS); 1897 if (status & E1000_STATUS_LU) 1898 break; 1899 } 1900 if (i == (LINK_UP_TIMEOUT / 10)) { 1901 DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 1902 hw->autoneg_failed = 1; 1903 /* 1904 * AutoNeg failed to achieve a link, so we'll call 1905 * em_check_for_link. This routine will force the 1906 * link up if we detect a signal. This will allow us 1907 * to communicate with non-autonegotiating link 1908 * partners. 1909 */ 1910 ret_val = em_check_for_link(hw); 1911 if (ret_val) { 1912 DEBUGOUT("Error while checking for link\n"); 1913 return ret_val; 1914 } 1915 hw->autoneg_failed = 0; 1916 } else { 1917 hw->autoneg_failed = 0; 1918 DEBUGOUT("Valid Link Found\n"); 1919 } 1920 } else { 1921 DEBUGOUT("No Signal Detected\n"); 1922 } 1923 return E1000_SUCCESS; 1924 } 1925 1926 /****************************************************************************** 1927 * Make sure we have a valid PHY and change PHY mode before link setup. 1928 * 1929 * hw - Struct containing variables accessed by shared code 1930 *****************************************************************************/ 1931 static int32_t 1932 em_copper_link_preconfig(struct em_hw *hw) 1933 { 1934 uint32_t ctrl; 1935 int32_t ret_val; 1936 uint16_t phy_data; 1937 DEBUGFUNC("em_copper_link_preconfig"); 1938 1939 ctrl = E1000_READ_REG(hw, CTRL); 1940 /* 1941 * With 82543, we need to force speed and duplex on the MAC equal to 1942 * what the PHY speed and duplex configuration is. In addition, we 1943 * need to perform a hardware reset on the PHY to take it out of 1944 * reset. 1945 */ 1946 if (hw->mac_type > em_82543) { 1947 ctrl |= E1000_CTRL_SLU; 1948 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1949 E1000_WRITE_REG(hw, CTRL, ctrl); 1950 } else { 1951 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | 1952 E1000_CTRL_SLU); 1953 E1000_WRITE_REG(hw, CTRL, ctrl); 1954 ret_val = em_phy_hw_reset(hw); 1955 if (ret_val) 1956 return ret_val; 1957 } 1958 1959 /* Set PHY to class A mode (if necessary) */ 1960 ret_val = em_set_phy_mode(hw); 1961 if (ret_val) 1962 return ret_val; 1963 1964 if ((hw->mac_type == em_82545_rev_3) || 1965 (hw->mac_type == em_82546_rev_3)) { 1966 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 1967 &phy_data); 1968 phy_data |= 0x00000008; 1969 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 1970 phy_data); 1971 } 1972 if (hw->mac_type <= em_82543 || 1973 hw->mac_type == em_82541 || hw->mac_type == em_82547 || 1974 hw->mac_type == em_82541_rev_2 || hw->mac_type == em_82547_rev_2) 1975 hw->phy_reset_disable = FALSE; 1976 1977 return E1000_SUCCESS; 1978 } 1979 1980 /****************************************************************************** 1981 * Copper link setup for em_phy_igp series. 1982 * 1983 * hw - Struct containing variables accessed by shared code 1984 *****************************************************************************/ 1985 static int32_t 1986 em_copper_link_igp_setup(struct em_hw *hw) 1987 { 1988 uint32_t led_ctrl; 1989 int32_t ret_val; 1990 uint16_t phy_data; 1991 DEBUGFUNC("em_copper_link_igp_setup"); 1992 1993 if (hw->phy_reset_disable) 1994 return E1000_SUCCESS; 1995 1996 ret_val = em_phy_reset(hw); 1997 if (ret_val) { 1998 DEBUGOUT("Error Resetting the PHY\n"); 1999 return ret_val; 2000 } 2001 /* Wait 15ms for MAC to configure PHY from eeprom settings */ 2002 msec_delay(15); 2003 if (hw->mac_type != em_ich8lan && 2004 hw->mac_type != em_ich9lan && 2005 hw->mac_type != em_ich10lan) { 2006 /* Configure activity LED after PHY reset */ 2007 led_ctrl = E1000_READ_REG(hw, LEDCTL); 2008 led_ctrl &= IGP_ACTIVITY_LED_MASK; 2009 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 2010 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 2011 } 2012 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */ 2013 if (hw->phy_type == em_phy_igp) { 2014 /* disable lplu d3 during driver init */ 2015 ret_val = em_set_d3_lplu_state(hw, FALSE); 2016 if (ret_val) { 2017 DEBUGOUT("Error Disabling LPLU D3\n"); 2018 return ret_val; 2019 } 2020 } 2021 /* disable lplu d0 during driver init */ 2022 if (hw->mac_type == em_pchlan || 2023 hw->mac_type == em_pch2lan || 2024 hw->mac_type == em_pch_lpt || 2025 hw->mac_type == em_pch_spt) 2026 ret_val = em_set_lplu_state_pchlan(hw, FALSE); 2027 else 2028 ret_val = em_set_d0_lplu_state(hw, FALSE); 2029 if (ret_val) { 2030 DEBUGOUT("Error Disabling LPLU D0\n"); 2031 return ret_val; 2032 } 2033 /* Configure mdi-mdix settings */ 2034 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 2035 if (ret_val) 2036 return ret_val; 2037 2038 if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) { 2039 hw->dsp_config_state = em_dsp_config_disabled; 2040 /* Force MDI for earlier revs of the IGP PHY */ 2041 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | 2042 IGP01E1000_PSCR_FORCE_MDI_MDIX); 2043 hw->mdix = 1; 2044 2045 } else { 2046 hw->dsp_config_state = em_dsp_config_enabled; 2047 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 2048 2049 switch (hw->mdix) { 2050 case 1: 2051 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 2052 break; 2053 case 2: 2054 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; 2055 break; 2056 case 0: 2057 default: 2058 phy_data |= IGP01E1000_PSCR_AUTO_MDIX; 2059 break; 2060 } 2061 } 2062 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 2063 if (ret_val) 2064 return ret_val; 2065 2066 /* set auto-master slave resolution settings */ 2067 if (hw->autoneg) { 2068 em_ms_type phy_ms_setting = hw->master_slave; 2069 if (hw->ffe_config_state == em_ffe_config_active) 2070 hw->ffe_config_state = em_ffe_config_enabled; 2071 2072 if (hw->dsp_config_state == em_dsp_config_activated) 2073 hw->dsp_config_state = em_dsp_config_enabled; 2074 /* 2075 * when autonegotiation advertisement is only 1000Mbps then 2076 * we should disable SmartSpeed and enable Auto MasterSlave 2077 * resolution as hardware default. 2078 */ 2079 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) { 2080 /* Disable SmartSpeed */ 2081 ret_val = em_read_phy_reg(hw, 2082 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2083 if (ret_val) 2084 return ret_val; 2085 2086 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2087 ret_val = em_write_phy_reg(hw, 2088 IGP01E1000_PHY_PORT_CONFIG, phy_data); 2089 if (ret_val) 2090 return ret_val; 2091 /* Set auto Master/Slave resolution process */ 2092 ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, 2093 &phy_data); 2094 if (ret_val) 2095 return ret_val; 2096 2097 phy_data &= ~CR_1000T_MS_ENABLE; 2098 ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL, 2099 phy_data); 2100 if (ret_val) 2101 return ret_val; 2102 } 2103 ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); 2104 if (ret_val) 2105 return ret_val; 2106 2107 /* load defaults for future use */ 2108 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ? 2109 ((phy_data & CR_1000T_MS_VALUE) ? em_ms_force_master : 2110 em_ms_force_slave) : em_ms_auto; 2111 2112 switch (phy_ms_setting) { 2113 case em_ms_force_master: 2114 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 2115 break; 2116 case em_ms_force_slave: 2117 phy_data |= CR_1000T_MS_ENABLE; 2118 phy_data &= ~(CR_1000T_MS_VALUE); 2119 break; 2120 case em_ms_auto: 2121 phy_data &= ~CR_1000T_MS_ENABLE; 2122 break; 2123 default: 2124 break; 2125 } 2126 ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); 2127 if (ret_val) 2128 return ret_val; 2129 } 2130 return E1000_SUCCESS; 2131 } 2132 2133 /****************************************************************************** 2134 * Copper link setup for em_phy_gg82563 series. 2135 * 2136 * hw - Struct containing variables accessed by shared code 2137 *****************************************************************************/ 2138 static int32_t 2139 em_copper_link_ggp_setup(struct em_hw *hw) 2140 { 2141 int32_t ret_val; 2142 uint16_t phy_data; 2143 uint32_t reg_data; 2144 DEBUGFUNC("em_copper_link_ggp_setup"); 2145 2146 if (!hw->phy_reset_disable) { 2147 2148 /* Enable CRS on TX for half-duplex operation. */ 2149 ret_val = em_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 2150 &phy_data); 2151 if (ret_val) 2152 return ret_val; 2153 2154 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 2155 /* Use 25MHz for both link down and 1000BASE-T for Tx clock */ 2156 phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ; 2157 2158 ret_val = em_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 2159 phy_data); 2160 if (ret_val) 2161 return ret_val; 2162 /* 2163 * Options: MDI/MDI-X = 0 (default) 0 - Auto for all speeds 1 2164 * - MDI mode 2 - MDI-X mode 3 - Auto for 1000Base-T only 2165 * (MDI-X for 10/100Base-T modes) 2166 */ 2167 ret_val = em_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, 2168 &phy_data); 2169 2170 if (ret_val) 2171 return ret_val; 2172 2173 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK; 2174 2175 switch (hw->mdix) { 2176 case 1: 2177 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI; 2178 break; 2179 case 2: 2180 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX; 2181 break; 2182 case 0: 2183 default: 2184 phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO; 2185 break; 2186 } 2187 /* 2188 * Options: disable_polarity_correction = 0 (default) 2189 * Automatic Correction for Reversed Cable Polarity 0 - 2190 * Disabled 1 - Enabled 2191 */ 2192 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 2193 if (hw->disable_polarity_correction == 1) 2194 phy_data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 2195 ret_val = em_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, 2196 phy_data); 2197 2198 if (ret_val) 2199 return ret_val; 2200 2201 /* SW Reset the PHY so all changes take effect */ 2202 ret_val = em_phy_reset(hw); 2203 if (ret_val) { 2204 DEBUGOUT("Error Resetting the PHY\n"); 2205 return ret_val; 2206 } 2207 } /* phy_reset_disable */ 2208 if (hw->mac_type == em_80003es2lan) { 2209 /* Bypass RX and TX FIFO's */ 2210 ret_val = em_write_kmrn_reg(hw, 2211 E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL, 2212 E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS | 2213 E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS); 2214 if (ret_val) 2215 return ret_val; 2216 2217 ret_val = em_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, 2218 &phy_data); 2219 if (ret_val) 2220 return ret_val; 2221 2222 phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG; 2223 ret_val = em_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, 2224 phy_data); 2225 2226 if (ret_val) 2227 return ret_val; 2228 2229 reg_data = E1000_READ_REG(hw, CTRL_EXT); 2230 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK); 2231 E1000_WRITE_REG(hw, CTRL_EXT, reg_data); 2232 2233 ret_val = em_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, 2234 &phy_data); 2235 if (ret_val) 2236 return ret_val; 2237 /* 2238 * Do not init these registers when the HW is in IAMT mode, 2239 * since the firmware will have already initialized them. We 2240 * only initialize them if the HW is not in IAMT mode. 2241 */ 2242 if (em_check_mng_mode(hw) == FALSE) { 2243 /* Enable Electrical Idle on the PHY */ 2244 phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; 2245 ret_val = em_write_phy_reg(hw, 2246 GG82563_PHY_PWR_MGMT_CTRL, phy_data); 2247 if (ret_val) 2248 return ret_val; 2249 2250 ret_val = em_read_phy_reg(hw, 2251 GG82563_PHY_KMRN_MODE_CTRL, &phy_data); 2252 if (ret_val) 2253 return ret_val; 2254 2255 phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 2256 ret_val = em_write_phy_reg(hw, 2257 GG82563_PHY_KMRN_MODE_CTRL, phy_data); 2258 2259 if (ret_val) 2260 return ret_val; 2261 } 2262 /* 2263 * Workaround: Disable padding in Kumeran interface in the 2264 * MAC and in the PHY to avoid CRC errors. 2265 */ 2266 ret_val = em_read_phy_reg(hw, GG82563_PHY_INBAND_CTRL, 2267 &phy_data); 2268 if (ret_val) 2269 return ret_val; 2270 phy_data |= GG82563_ICR_DIS_PADDING; 2271 ret_val = em_write_phy_reg(hw, GG82563_PHY_INBAND_CTRL, 2272 phy_data); 2273 if (ret_val) 2274 return ret_val; 2275 } 2276 return E1000_SUCCESS; 2277 } 2278 2279 /****************************************************************************** 2280 * Copper link setup for em_phy_m88 series. 2281 * 2282 * hw - Struct containing variables accessed by shared code 2283 *****************************************************************************/ 2284 static int32_t 2285 em_copper_link_mgp_setup(struct em_hw *hw) 2286 { 2287 int32_t ret_val; 2288 uint16_t phy_data; 2289 DEBUGFUNC("em_copper_link_mgp_setup"); 2290 2291 if (hw->phy_reset_disable) 2292 return E1000_SUCCESS; 2293 2294 /* disable lplu d0 during driver init */ 2295 if (hw->mac_type == em_pchlan || 2296 hw->mac_type == em_pch2lan || 2297 hw->mac_type == em_pch_lpt || 2298 hw->mac_type == em_pch_spt) 2299 ret_val = em_set_lplu_state_pchlan(hw, FALSE); 2300 2301 /* Enable CRS on TX. This must be set for half-duplex operation. */ 2302 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 2303 if (ret_val) 2304 return ret_val; 2305 2306 if (hw->phy_id == M88E1141_E_PHY_ID) { 2307 phy_data |= 0x00000008; 2308 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 2309 phy_data); 2310 if (ret_val) 2311 return ret_val; 2312 2313 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 2314 &phy_data); 2315 if (ret_val) 2316 return ret_val; 2317 2318 phy_data &= ~M88E1000_PSCR_ASSERT_CRS_ON_TX; 2319 2320 } 2321 /* For BM PHY this bit is downshift enable */ 2322 else if (hw->phy_type != em_phy_bm) 2323 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 2324 /* 2325 * Options: MDI/MDI-X = 0 (default) 0 - Auto for all speeds 1 - MDI 2326 * mode 2 - MDI-X mode 3 - Auto for 1000Base-T only (MDI-X for 2327 * 10/100Base-T modes) 2328 */ 2329 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 2330 2331 switch (hw->mdix) { 2332 case 1: 2333 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 2334 break; 2335 case 2: 2336 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 2337 break; 2338 case 3: 2339 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 2340 break; 2341 case 0: 2342 default: 2343 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 2344 break; 2345 } 2346 /* 2347 * Options: disable_polarity_correction = 0 (default) Automatic 2348 * Correction for Reversed Cable Polarity 0 - Disabled 1 - Enabled 2349 */ 2350 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 2351 if (hw->disable_polarity_correction == 1) 2352 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 2353 2354 /* Enable downshift on BM (disabled by default) */ 2355 if (hw->phy_type == em_phy_bm) 2356 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT; 2357 2358 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 2359 if (ret_val) 2360 return ret_val; 2361 2362 if (((hw->phy_type == em_phy_m88) && 2363 (hw->phy_revision < M88E1011_I_REV_4) && 2364 (hw->phy_id != BME1000_E_PHY_ID)) || 2365 (hw->phy_type == em_phy_oem)) { 2366 /* 2367 * Force TX_CLK in the Extended PHY Specific Control Register 2368 * to 25MHz clock. 2369 */ 2370 ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 2371 &phy_data); 2372 if (ret_val) 2373 return ret_val; 2374 2375 if (hw->phy_type == em_phy_oem) { 2376 phy_data |= M88E1000_EPSCR_TX_TIME_CTRL; 2377 phy_data |= M88E1000_EPSCR_RX_TIME_CTRL; 2378 } 2379 phy_data |= M88E1000_EPSCR_TX_CLK_25; 2380 2381 if ((hw->phy_revision == E1000_REVISION_2) && 2382 (hw->phy_id == M88E1111_I_PHY_ID)) { 2383 /* Vidalia Phy, set the downshift counter to 5x */ 2384 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK); 2385 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; 2386 ret_val = em_write_phy_reg(hw, 2387 M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 2388 if (ret_val) 2389 return ret_val; 2390 } else { 2391 /* Configure Master and Slave downshift values */ 2392 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 2393 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 2394 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 2395 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 2396 ret_val = em_write_phy_reg(hw, 2397 M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 2398 if (ret_val) 2399 return ret_val; 2400 } 2401 } 2402 if ((hw->phy_type == em_phy_bm) && (hw->phy_revision == 1)) { 2403 /* 2404 * Set PHY page 0, register 29 to 0x0003 2405 * The next two writes are supposed to lower BER for gig 2406 * conection 2407 */ 2408 ret_val = em_write_phy_reg(hw, BM_REG_BIAS1, 0x0003); 2409 if (ret_val) 2410 return ret_val; 2411 2412 /* Set PHY page 0, register 30 to 0x0000 */ 2413 ret_val = em_write_phy_reg(hw, BM_REG_BIAS2, 0x0000); 2414 if (ret_val) 2415 return ret_val; 2416 } 2417 if (hw->phy_type == em_phy_82578) { 2418 ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 2419 &phy_data); 2420 if (ret_val) 2421 return ret_val; 2422 2423 /* 82578 PHY - set the downshift count to 1x. */ 2424 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE; 2425 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK; 2426 ret_val = em_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 2427 phy_data); 2428 if (ret_val) 2429 return ret_val; 2430 } 2431 /* SW Reset the PHY so all changes take effect */ 2432 ret_val = em_phy_reset(hw); 2433 if (ret_val) { 2434 DEBUGOUT("Error Resetting the PHY\n"); 2435 return ret_val; 2436 } 2437 return E1000_SUCCESS; 2438 } 2439 2440 /****************************************************************************** 2441 * Copper link setup for em_phy_82577 series. 2442 * 2443 * hw - Struct containing variables accessed by shared code 2444 *****************************************************************************/ 2445 static int32_t 2446 em_copper_link_82577_setup(struct em_hw *hw) 2447 { 2448 int32_t ret_val; 2449 uint16_t phy_data; 2450 uint32_t led_ctl; 2451 DEBUGFUNC("em_copper_link_82577_setup"); 2452 2453 if (hw->phy_reset_disable) 2454 return E1000_SUCCESS; 2455 2456 /* Enable CRS on TX for half-duplex operation. */ 2457 ret_val = em_read_phy_reg(hw, I82577_PHY_CFG_REG, &phy_data); 2458 if (ret_val) 2459 return ret_val; 2460 2461 phy_data |= I82577_PHY_CFG_ENABLE_CRS_ON_TX | 2462 I82577_PHY_CFG_ENABLE_DOWNSHIFT; 2463 2464 ret_val = em_write_phy_reg(hw, I82577_PHY_CFG_REG, phy_data); 2465 if (ret_val) 2466 return ret_val; 2467 2468 /* Wait 15ms for MAC to configure PHY from eeprom settings */ 2469 msec_delay(15); 2470 led_ctl = hw->ledctl_mode1; 2471 2472 /* disable lplu d0 during driver init */ 2473 ret_val = em_set_lplu_state_pchlan(hw, FALSE); 2474 if (ret_val) { 2475 DEBUGOUT("Error Disabling LPLU D0\n"); 2476 return ret_val; 2477 } 2478 2479 E1000_WRITE_REG(hw, LEDCTL, led_ctl); 2480 2481 return E1000_SUCCESS; 2482 } 2483 2484 static int32_t 2485 em_copper_link_82580_setup(struct em_hw *hw) 2486 { 2487 int32_t ret_val; 2488 uint16_t phy_data; 2489 2490 if (hw->phy_reset_disable) 2491 return E1000_SUCCESS; 2492 2493 ret_val = em_phy_reset(hw); 2494 if (ret_val) 2495 goto out; 2496 2497 /* Enable CRS on TX. This must be set for half-duplex operation. */ 2498 ret_val = em_read_phy_reg(hw, I82580_CFG_REG, &phy_data); 2499 if (ret_val) 2500 goto out; 2501 2502 phy_data |= I82580_CFG_ASSERT_CRS_ON_TX | 2503 I82580_CFG_ENABLE_DOWNSHIFT; 2504 2505 ret_val = em_write_phy_reg(hw, I82580_CFG_REG, phy_data); 2506 2507 out: 2508 return ret_val; 2509 } 2510 2511 static int32_t 2512 em_copper_link_rtl8211_setup(struct em_hw *hw) 2513 { 2514 int32_t ret_val; 2515 uint16_t phy_data; 2516 2517 DEBUGFUNC("em_copper_link_rtl8211_setup: begin"); 2518 2519 if (!hw) { 2520 return -1; 2521 } 2522 /* SW Reset the PHY so all changes take effect */ 2523 em_phy_hw_reset(hw); 2524 2525 /* Enable CRS on TX. This must be set for half-duplex operation. */ 2526 phy_data = 0; 2527 2528 ret_val = em_read_phy_reg_ex(hw, RGEPHY_CR, &phy_data); 2529 if (ret_val) { 2530 printf("Unable to read RGEPHY_CR register\n"); 2531 return ret_val; 2532 } 2533 DEBUGOUT3("RTL8211: Rx phy_id=%X addr=%X SPEC_CTRL=%X\n", hw->phy_id, 2534 hw->phy_addr, phy_data); 2535 phy_data |= RGEPHY_CR_ASSERT_CRS; 2536 2537 ret_val = em_write_phy_reg_ex(hw, RGEPHY_CR, phy_data); 2538 if (ret_val) { 2539 printf("Unable to write RGEPHY_CR register\n"); 2540 return ret_val; 2541 } 2542 2543 phy_data = 0; /* LED Control Register 0x18 */ 2544 ret_val = em_read_phy_reg_ex(hw, RGEPHY_LC, &phy_data); 2545 if (ret_val) { 2546 printf("Unable to read RGEPHY_LC register\n"); 2547 return ret_val; 2548 } 2549 2550 phy_data &= 0x80FF; /* bit-15=0 disable, clear bit 8-10 */ 2551 ret_val = em_write_phy_reg_ex(hw, RGEPHY_LC, phy_data); 2552 if (ret_val) { 2553 printf("Unable to write RGEPHY_LC register\n"); 2554 return ret_val; 2555 } 2556 /* LED Control and Definition Register 0x11, PHY spec status reg */ 2557 phy_data = 0; 2558 ret_val = em_read_phy_reg_ex(hw, RGEPHY_SR, &phy_data); 2559 if (ret_val) { 2560 printf("Unable to read RGEPHY_SR register\n"); 2561 return ret_val; 2562 } 2563 2564 phy_data |= 0x0010; /* LED active Low */ 2565 ret_val = em_write_phy_reg_ex(hw, RGEPHY_SR, phy_data); 2566 if (ret_val) { 2567 printf("Unable to write RGEPHY_SR register\n"); 2568 return ret_val; 2569 } 2570 2571 phy_data = 0; 2572 ret_val = em_read_phy_reg_ex(hw, RGEPHY_SR, &phy_data); 2573 if (ret_val) { 2574 printf("Unable to read RGEPHY_SR register\n"); 2575 return ret_val; 2576 } 2577 2578 /* Switch to Page2 */ 2579 phy_data = RGEPHY_PS_PAGE_2; 2580 ret_val = em_write_phy_reg_ex(hw, RGEPHY_PS, phy_data); 2581 if (ret_val) { 2582 printf("Unable to write PHY RGEPHY_PS register\n"); 2583 return ret_val; 2584 } 2585 2586 phy_data = 0x0000; 2587 ret_val = em_write_phy_reg_ex(hw, RGEPHY_LC_P2, phy_data); 2588 if (ret_val) { 2589 printf("Unable to write RGEPHY_LC_P2 register\n"); 2590 return ret_val; 2591 } 2592 usec_delay(5); 2593 2594 2595 /* LED Configuration Control Reg for setting for 0x1A Register */ 2596 phy_data = 0; 2597 ret_val = em_read_phy_reg_ex(hw, RGEPHY_LC_P2, &phy_data); 2598 if (ret_val) { 2599 printf("Unable to read RGEPHY_LC_P2 register\n"); 2600 return ret_val; 2601 } 2602 2603 phy_data &= 0xF000; 2604 phy_data |= 0x0F24; 2605 ret_val = em_write_phy_reg_ex(hw, RGEPHY_LC_P2, phy_data); 2606 if (ret_val) { 2607 printf("Unable to write RGEPHY_LC_P2 register\n"); 2608 return ret_val; 2609 } 2610 phy_data = 0; 2611 ret_val= em_read_phy_reg_ex(hw, RGEPHY_LC_P2, &phy_data); 2612 if (ret_val) { 2613 printf("Unable to read RGEPHY_LC_P2 register\n"); 2614 return ret_val; 2615 } 2616 DEBUGOUT1("RTL8211:ReadBack for check, LED_CFG->data=%X\n", phy_data); 2617 2618 2619 /* After setting Page2, go back to Page 0 */ 2620 phy_data = 0; 2621 ret_val = em_write_phy_reg_ex(hw, RGEPHY_PS, phy_data); 2622 if (ret_val) { 2623 printf("Unable to write PHY RGEPHY_PS register\n"); 2624 return ret_val; 2625 } 2626 2627 /* pulse streching= 42-84ms, blink rate=84mm */ 2628 phy_data = 0x140 | RGEPHY_LC_PULSE_42MS | RGEPHY_LC_LINK | 2629 RGEPHY_LC_DUPLEX | RGEPHY_LC_RX; 2630 2631 ret_val = em_write_phy_reg_ex(hw, RGEPHY_LC, phy_data); 2632 if (ret_val) { 2633 printf("Unable to write RGEPHY_LC register\n"); 2634 return ret_val; 2635 } 2636 return E1000_SUCCESS; 2637 } 2638 2639 /****************************************************************************** 2640 * Setup auto-negotiation and flow control advertisements, 2641 * and then perform auto-negotiation. 2642 * 2643 * hw - Struct containing variables accessed by shared code 2644 *****************************************************************************/ 2645 int32_t 2646 em_copper_link_autoneg(struct em_hw *hw) 2647 { 2648 int32_t ret_val; 2649 uint16_t phy_data; 2650 DEBUGFUNC("em_copper_link_autoneg"); 2651 /* 2652 * Perform some bounds checking on the hw->autoneg_advertised 2653 * parameter. If this variable is zero, then set it to the default. 2654 */ 2655 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT; 2656 /* 2657 * If autoneg_advertised is zero, we assume it was not defaulted by 2658 * the calling code so we set to advertise full capability. 2659 */ 2660 if (hw->autoneg_advertised == 0) 2661 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 2662 2663 /* IFE phy only supports 10/100 */ 2664 if (hw->phy_type == em_phy_ife) 2665 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL; 2666 2667 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); 2668 ret_val = em_phy_setup_autoneg(hw); 2669 if (ret_val) { 2670 DEBUGOUT("Error Setting up Auto-Negotiation\n"); 2671 return ret_val; 2672 } 2673 DEBUGOUT("Restarting Auto-Neg\n"); 2674 /* 2675 * Restart auto-negotiation by setting the Auto Neg Enable bit and 2676 * the Auto Neg Restart bit in the PHY control register. 2677 */ 2678 ret_val = em_read_phy_reg(hw, PHY_CTRL, &phy_data); 2679 if (ret_val) 2680 return ret_val; 2681 2682 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 2683 ret_val = em_write_phy_reg(hw, PHY_CTRL, phy_data); 2684 if (ret_val) 2685 return ret_val; 2686 /* 2687 * Does the user want to wait for Auto-Neg to complete here, or check 2688 * at a later time (for example, callback routine). 2689 */ 2690 if (hw->wait_autoneg_complete) { 2691 ret_val = em_wait_autoneg(hw); 2692 if (ret_val) { 2693 DEBUGOUT("Error while waiting for autoneg to complete\n" 2694 ); 2695 return ret_val; 2696 } 2697 } 2698 hw->get_link_status = TRUE; 2699 2700 return E1000_SUCCESS; 2701 } 2702 2703 /****************************************************************************** 2704 * Config the MAC and the PHY after link is up. 2705 * 1) Set up the MAC to the current PHY speed/duplex 2706 * if we are on 82543. If we 2707 * are on newer silicon, we only need to configure 2708 * collision distance in the Transmit Control Register. 2709 * 2) Set up flow control on the MAC to that established with 2710 * the link partner. 2711 * 3) Config DSP to improve Gigabit link quality for some PHY revisions. 2712 * 2713 * hw - Struct containing variables accessed by shared code 2714 *****************************************************************************/ 2715 int32_t 2716 em_copper_link_postconfig(struct em_hw *hw) 2717 { 2718 int32_t ret_val; 2719 DEBUGFUNC("em_copper_link_postconfig"); 2720 2721 if (hw->mac_type >= em_82544 && 2722 hw->mac_type != em_icp_xxxx) { 2723 em_config_collision_dist(hw); 2724 } else { 2725 ret_val = em_config_mac_to_phy(hw); 2726 if (ret_val) { 2727 DEBUGOUT("Error configuring MAC to PHY settings\n"); 2728 return ret_val; 2729 } 2730 } 2731 ret_val = em_config_fc_after_link_up(hw); 2732 if (ret_val) { 2733 DEBUGOUT("Error Configuring Flow Control\n"); 2734 return ret_val; 2735 } 2736 /* Config DSP to improve Giga link quality */ 2737 if (hw->phy_type == em_phy_igp) { 2738 ret_val = em_config_dsp_after_link_change(hw, TRUE); 2739 if (ret_val) { 2740 DEBUGOUT("Error Configuring DSP after link up\n"); 2741 return ret_val; 2742 } 2743 } 2744 return E1000_SUCCESS; 2745 } 2746 2747 /****************************************************************************** 2748 * Detects which PHY is present and setup the speed and duplex 2749 * 2750 * hw - Struct containing variables accessed by shared code 2751 *****************************************************************************/ 2752 static int32_t 2753 em_setup_copper_link(struct em_hw *hw) 2754 { 2755 int32_t ret_val; 2756 uint16_t i; 2757 uint16_t phy_data; 2758 uint16_t reg_data; 2759 DEBUGFUNC("em_setup_copper_link"); 2760 2761 switch (hw->mac_type) { 2762 case em_80003es2lan: 2763 case em_ich8lan: 2764 case em_ich9lan: 2765 case em_ich10lan: 2766 case em_pchlan: 2767 case em_pch2lan: 2768 case em_pch_lpt: 2769 case em_pch_spt: 2770 /* 2771 * Set the mac to wait the maximum time between each 2772 * iteration and increase the max iterations when polling the 2773 * phy; this fixes erroneous timeouts at 10Mbps. 2774 */ 2775 ret_val = em_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF); 2776 if (ret_val) 2777 return ret_val; 2778 ret_val = em_read_kmrn_reg(hw, GG82563_REG(0x34, 9), 2779 ®_data); 2780 if (ret_val) 2781 return ret_val; 2782 reg_data |= 0x3F; 2783 ret_val = em_write_kmrn_reg(hw, GG82563_REG(0x34, 9), 2784 reg_data); 2785 if (ret_val) 2786 return ret_val; 2787 default: 2788 break; 2789 } 2790 2791 /* Check if it is a valid PHY and set PHY mode if necessary. */ 2792 ret_val = em_copper_link_preconfig(hw); 2793 if (ret_val) 2794 return ret_val; 2795 2796 switch (hw->mac_type) { 2797 case em_80003es2lan: 2798 /* Kumeran registers are written-only */ 2799 reg_data = 2800 E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT; 2801 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING; 2802 ret_val = em_write_kmrn_reg(hw, 2803 E1000_KUMCTRLSTA_OFFSET_INB_CTRL, reg_data); 2804 if (ret_val) 2805 return ret_val; 2806 break; 2807 default: 2808 break; 2809 } 2810 2811 if (hw->phy_type == em_phy_igp || 2812 hw->phy_type == em_phy_igp_3 || 2813 hw->phy_type == em_phy_igp_2) { 2814 ret_val = em_copper_link_igp_setup(hw); 2815 if (ret_val) 2816 return ret_val; 2817 } else if (hw->phy_type == em_phy_m88 || 2818 hw->phy_type == em_phy_bm || 2819 hw->phy_type == em_phy_oem || 2820 hw->phy_type == em_phy_82578) { 2821 ret_val = em_copper_link_mgp_setup(hw); 2822 if (ret_val) 2823 return ret_val; 2824 } else if (hw->phy_type == em_phy_gg82563) { 2825 ret_val = em_copper_link_ggp_setup(hw); 2826 if (ret_val) 2827 return ret_val; 2828 } else if (hw->phy_type == em_phy_82577 || 2829 hw->phy_type == em_phy_82579 || 2830 hw->phy_type == em_phy_i217) { 2831 ret_val = em_copper_link_82577_setup(hw); 2832 if (ret_val) 2833 return ret_val; 2834 } else if (hw->phy_type == em_phy_82580) { 2835 ret_val = em_copper_link_82580_setup(hw); 2836 if (ret_val) 2837 return ret_val; 2838 } else if (hw->phy_type == em_phy_rtl8211) { 2839 ret_val = em_copper_link_rtl8211_setup(hw); 2840 if (ret_val) 2841 return ret_val; 2842 } 2843 if (hw->autoneg) { 2844 /* 2845 * Setup autoneg and flow control advertisement and perform 2846 * autonegotiation 2847 */ 2848 ret_val = em_copper_link_autoneg(hw); 2849 if (ret_val) 2850 return ret_val; 2851 } else { 2852 /* 2853 * PHY will be set to 10H, 10F, 100H,or 100F depending on 2854 * value from forced_speed_duplex. 2855 */ 2856 DEBUGOUT("Forcing speed and duplex\n"); 2857 ret_val = em_phy_force_speed_duplex(hw); 2858 if (ret_val) { 2859 DEBUGOUT("Error Forcing Speed and Duplex\n"); 2860 return ret_val; 2861 } 2862 } 2863 /* 2864 * Check link status. Wait up to 100 microseconds for link to become 2865 * valid. 2866 */ 2867 for (i = 0; i < 10; i++) { 2868 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 2869 if (ret_val) 2870 return ret_val; 2871 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 2872 if (ret_val) 2873 return ret_val; 2874 2875 hw->icp_xxxx_is_link_up = (phy_data & MII_SR_LINK_STATUS) != 0; 2876 2877 if (phy_data & MII_SR_LINK_STATUS) { 2878 /* Config the MAC and PHY after link is up */ 2879 ret_val = em_copper_link_postconfig(hw); 2880 if (ret_val) 2881 return ret_val; 2882 2883 DEBUGOUT("Valid link established!!!\n"); 2884 return E1000_SUCCESS; 2885 } 2886 usec_delay(10); 2887 } 2888 2889 DEBUGOUT("Unable to establish link!!!\n"); 2890 return E1000_SUCCESS; 2891 } 2892 2893 /****************************************************************************** 2894 * Configure the MAC-to-PHY interface for 10/100Mbps 2895 * 2896 * hw - Struct containing variables accessed by shared code 2897 *****************************************************************************/ 2898 static int32_t 2899 em_configure_kmrn_for_10_100(struct em_hw *hw, uint16_t duplex) 2900 { 2901 int32_t ret_val = E1000_SUCCESS; 2902 uint32_t tipg; 2903 uint16_t reg_data; 2904 DEBUGFUNC("em_configure_kmrn_for_10_100"); 2905 2906 reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT; 2907 ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL, 2908 reg_data); 2909 if (ret_val) 2910 return ret_val; 2911 2912 /* Configure Transmit Inter-Packet Gap */ 2913 tipg = E1000_READ_REG(hw, TIPG); 2914 tipg &= ~E1000_TIPG_IPGT_MASK; 2915 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100; 2916 E1000_WRITE_REG(hw, TIPG, tipg); 2917 2918 ret_val = em_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); 2919 2920 if (ret_val) 2921 return ret_val; 2922 2923 if (duplex == HALF_DUPLEX) 2924 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER; 2925 else 2926 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 2927 2928 ret_val = em_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 2929 2930 return ret_val; 2931 } 2932 2933 static int32_t 2934 em_configure_kmrn_for_1000(struct em_hw *hw) 2935 { 2936 int32_t ret_val = E1000_SUCCESS; 2937 uint16_t reg_data; 2938 uint32_t tipg; 2939 DEBUGFUNC("em_configure_kmrn_for_1000"); 2940 2941 reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT; 2942 ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL, 2943 reg_data); 2944 if (ret_val) 2945 return ret_val; 2946 2947 /* Configure Transmit Inter-Packet Gap */ 2948 tipg = E1000_READ_REG(hw, TIPG); 2949 tipg &= ~E1000_TIPG_IPGT_MASK; 2950 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; 2951 E1000_WRITE_REG(hw, TIPG, tipg); 2952 2953 ret_val = em_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); 2954 2955 if (ret_val) 2956 return ret_val; 2957 2958 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 2959 ret_val = em_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 2960 2961 return ret_val; 2962 } 2963 2964 /****************************************************************************** 2965 * Configures PHY autoneg and flow control advertisement settings 2966 * 2967 * hw - Struct containing variables accessed by shared code 2968 *****************************************************************************/ 2969 int32_t 2970 em_phy_setup_autoneg(struct em_hw *hw) 2971 { 2972 int32_t ret_val; 2973 uint16_t mii_autoneg_adv_reg; 2974 uint16_t mii_1000t_ctrl_reg; 2975 DEBUGFUNC("em_phy_setup_autoneg"); 2976 2977 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 2978 ret_val = em_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 2979 if (ret_val) 2980 return ret_val; 2981 2982 if (hw->phy_type != em_phy_ife) { 2983 /* Read the MII 1000Base-T Control Register (Address 9). */ 2984 ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, 2985 &mii_1000t_ctrl_reg); 2986 if (ret_val) 2987 return ret_val; 2988 } else 2989 mii_1000t_ctrl_reg = 0; 2990 /* 2991 * Need to parse both autoneg_advertised and fc and set up the 2992 * appropriate PHY registers. First we will parse for 2993 * autoneg_advertised software override. Since we can advertise a 2994 * plethora of combinations, we need to check each bit individually. 2995 */ 2996 /* 2997 * First we clear all the 10/100 mb speed bits in the Auto-Neg 2998 * Advertisement Register (Address 4) and the 1000 mb speed bits in 2999 * the 1000Base-T Control Register (Address 9). 3000 */ 3001 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK; 3002 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK; 3003 3004 DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised); 3005 3006 /* Do we want to advertise 10 Mb Half Duplex? */ 3007 if (hw->autoneg_advertised & ADVERTISE_10_HALF) { 3008 DEBUGOUT("Advertise 10mb Half duplex\n"); 3009 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 3010 } 3011 /* Do we want to advertise 10 Mb Full Duplex? */ 3012 if (hw->autoneg_advertised & ADVERTISE_10_FULL) { 3013 DEBUGOUT("Advertise 10mb Full duplex\n"); 3014 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 3015 } 3016 /* Do we want to advertise 100 Mb Half Duplex? */ 3017 if (hw->autoneg_advertised & ADVERTISE_100_HALF) { 3018 DEBUGOUT("Advertise 100mb Half duplex\n"); 3019 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 3020 } 3021 /* Do we want to advertise 100 Mb Full Duplex? */ 3022 if (hw->autoneg_advertised & ADVERTISE_100_FULL) { 3023 DEBUGOUT("Advertise 100mb Full duplex\n"); 3024 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 3025 } 3026 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 3027 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) { 3028 DEBUGOUT("Advertise 1000mb Half duplex requested, request" 3029 " denied!\n"); 3030 } 3031 /* Do we want to advertise 1000 Mb Full Duplex? */ 3032 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) { 3033 DEBUGOUT("Advertise 1000mb Full duplex\n"); 3034 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 3035 if (hw->phy_type == em_phy_ife) { 3036 DEBUGOUT("em_phy_ife is a 10/100 PHY. Gigabit speed is" 3037 " not supported.\n"); 3038 } 3039 } 3040 /* 3041 * Check for a software override of the flow control settings, and 3042 * setup the PHY advertisement registers accordingly. If 3043 * auto-negotiation is enabled, then software will have to set the 3044 * "PAUSE" bits to the correct value in the Auto-Negotiation 3045 * Advertisement Register (PHY_AUTONEG_ADV) and re-start 3046 * auto-negotiation. 3047 * 3048 * The possible values of the "fc" parameter are: 0: Flow control is 3049 * completely disabled 1: Rx flow control is enabled (we can receive 3050 * pause frames but not send pause frames). 2: Tx flow control is 3051 * enabled (we can send pause frames but we do not support receiving 3052 * pause frames). 3: Both Rx and TX flow control (symmetric) are 3053 * enabled. other: No software override. The flow control 3054 * configuration in the EEPROM is used. 3055 */ 3056 switch (hw->fc) { 3057 case E1000_FC_NONE: /* 0 */ 3058 /* 3059 * Flow control (RX & TX) is completely disabled by a 3060 * software over-ride. 3061 */ 3062 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 3063 break; 3064 case E1000_FC_RX_PAUSE:/* 1 */ 3065 /* 3066 * RX Flow control is enabled, and TX Flow control is 3067 * disabled, by a software over-ride. 3068 */ 3069 /* 3070 * Since there really isn't a way to advertise that we are 3071 * capable of RX Pause ONLY, we will advertise that we 3072 * support both symmetric and asymmetric RX PAUSE. Later (in 3073 * em_config_fc_after_link_up) we will disable the hw's 3074 * ability to send PAUSE frames. 3075 */ 3076 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 3077 break; 3078 case E1000_FC_TX_PAUSE:/* 2 */ 3079 /* 3080 * TX Flow control is enabled, and RX Flow control is 3081 * disabled, by a software over-ride. 3082 */ 3083 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 3084 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 3085 break; 3086 case E1000_FC_FULL: /* 3 */ 3087 /* 3088 * Flow control (both RX and TX) is enabled by a software 3089 * over-ride. 3090 */ 3091 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 3092 break; 3093 default: 3094 DEBUGOUT("Flow control param set incorrectly\n"); 3095 return -E1000_ERR_CONFIG; 3096 } 3097 3098 ret_val = em_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 3099 if (ret_val) 3100 return ret_val; 3101 3102 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 3103 3104 if (hw->phy_type != em_phy_ife) { 3105 ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL, 3106 mii_1000t_ctrl_reg); 3107 if (ret_val) 3108 return ret_val; 3109 } 3110 return E1000_SUCCESS; 3111 } 3112 /****************************************************************************** 3113 * Force PHY speed and duplex settings to hw->forced_speed_duplex 3114 * 3115 * hw - Struct containing variables accessed by shared code 3116 *****************************************************************************/ 3117 static int32_t 3118 em_phy_force_speed_duplex(struct em_hw *hw) 3119 { 3120 uint32_t ctrl; 3121 int32_t ret_val; 3122 uint16_t mii_ctrl_reg; 3123 uint16_t mii_status_reg; 3124 uint16_t phy_data; 3125 uint16_t i; 3126 DEBUGFUNC("em_phy_force_speed_duplex"); 3127 3128 /* Turn off Flow control if we are forcing speed and duplex. */ 3129 hw->fc = E1000_FC_NONE; 3130 3131 DEBUGOUT1("hw->fc = %d\n", hw->fc); 3132 3133 /* Read the Device Control Register. */ 3134 ctrl = E1000_READ_REG(hw, CTRL); 3135 3136 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */ 3137 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 3138 ctrl &= ~(DEVICE_SPEED_MASK); 3139 3140 /* Clear the Auto Speed Detect Enable bit. */ 3141 ctrl &= ~E1000_CTRL_ASDE; 3142 3143 /* Read the MII Control Register. */ 3144 ret_val = em_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg); 3145 if (ret_val) 3146 return ret_val; 3147 3148 /* We need to disable autoneg in order to force link and duplex. */ 3149 3150 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN; 3151 3152 /* Are we forcing Full or Half Duplex? */ 3153 if (hw->forced_speed_duplex == em_100_full || 3154 hw->forced_speed_duplex == em_10_full) { 3155 /* 3156 * We want to force full duplex so we SET the full duplex 3157 * bits in the Device and MII Control Registers. 3158 */ 3159 ctrl |= E1000_CTRL_FD; 3160 mii_ctrl_reg |= MII_CR_FULL_DUPLEX; 3161 DEBUGOUT("Full Duplex\n"); 3162 } else { 3163 /* 3164 * We want to force half duplex so we CLEAR the full duplex 3165 * bits in the Device and MII Control Registers. 3166 */ 3167 ctrl &= ~E1000_CTRL_FD; 3168 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX; 3169 DEBUGOUT("Half Duplex\n"); 3170 } 3171 3172 /* Are we forcing 100Mbps??? */ 3173 if (hw->forced_speed_duplex == em_100_full || 3174 hw->forced_speed_duplex == em_100_half) { 3175 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */ 3176 ctrl |= E1000_CTRL_SPD_100; 3177 mii_ctrl_reg |= MII_CR_SPEED_100; 3178 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); 3179 DEBUGOUT("Forcing 100mb "); 3180 } else { 3181 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */ 3182 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 3183 mii_ctrl_reg |= MII_CR_SPEED_10; 3184 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); 3185 DEBUGOUT("Forcing 10mb "); 3186 } 3187 3188 em_config_collision_dist(hw); 3189 3190 /* Write the configured values back to the Device Control Reg. */ 3191 E1000_WRITE_REG(hw, CTRL, ctrl); 3192 3193 if ((hw->phy_type == em_phy_m88) || 3194 (hw->phy_type == em_phy_gg82563) || 3195 (hw->phy_type == em_phy_bm) || 3196 (hw->phy_type == em_phy_oem || 3197 (hw->phy_type == em_phy_82578))) { 3198 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 3199 &phy_data); 3200 if (ret_val) 3201 return ret_val; 3202 /* 3203 * Clear Auto-Crossover to force MDI manually. M88E1000 3204 * requires MDI forced whenever speed are duplex are forced. 3205 */ 3206 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 3207 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 3208 phy_data); 3209 if (ret_val) 3210 return ret_val; 3211 3212 DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data); 3213 3214 /* Need to reset the PHY or these changes will be ignored */ 3215 mii_ctrl_reg |= MII_CR_RESET; 3216 3217 } 3218 else if (hw->phy_type == em_phy_rtl8211) { 3219 ret_val = em_read_phy_reg_ex(hw, RGEPHY_CR, &phy_data); 3220 if(ret_val) { 3221 printf("Unable to read RGEPHY_CR register\n" 3222 ); 3223 return ret_val; 3224 } 3225 3226 /* 3227 * Clear Auto-Crossover to force MDI manually. RTL8211 requires 3228 * MDI forced whenever speed are duplex are forced. 3229 */ 3230 3231 phy_data |= RGEPHY_CR_MDI_MASK; // enable MDIX 3232 ret_val = em_write_phy_reg_ex(hw, RGEPHY_CR, phy_data); 3233 if(ret_val) { 3234 printf("Unable to write RGEPHY_CR register\n"); 3235 return ret_val; 3236 } 3237 mii_ctrl_reg |= MII_CR_RESET; 3238 3239 } 3240 /* Disable MDI-X support for 10/100 */ 3241 else if (hw->phy_type == em_phy_ife) { 3242 ret_val = em_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data); 3243 if (ret_val) 3244 return ret_val; 3245 3246 phy_data &= ~IFE_PMC_AUTO_MDIX; 3247 phy_data &= ~IFE_PMC_FORCE_MDIX; 3248 3249 ret_val = em_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, phy_data); 3250 if (ret_val) 3251 return ret_val; 3252 } else { 3253 /* 3254 * Clear Auto-Crossover to force MDI manually. IGP requires 3255 * MDI forced whenever speed or duplex are forced. 3256 */ 3257 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, 3258 &phy_data); 3259 if (ret_val) 3260 return ret_val; 3261 3262 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 3263 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 3264 3265 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, 3266 phy_data); 3267 if (ret_val) 3268 return ret_val; 3269 } 3270 3271 /* Write back the modified PHY MII control register. */ 3272 ret_val = em_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg); 3273 if (ret_val) 3274 return ret_val; 3275 3276 usec_delay(1); 3277 /* 3278 * The wait_autoneg_complete flag may be a little misleading here. 3279 * Since we are forcing speed and duplex, Auto-Neg is not enabled. 3280 * But we do want to delay for a period while forcing only so we 3281 * don't generate false No Link messages. So we will wait here only 3282 * if the user has set wait_autoneg_complete to 1, which is the 3283 * default. 3284 */ 3285 if (hw->wait_autoneg_complete) { 3286 /* We will wait for autoneg to complete. */ 3287 DEBUGOUT("Waiting for forced speed/duplex link.\n"); 3288 mii_status_reg = 0; 3289 /* 3290 * We will wait for autoneg to complete or 4.5 seconds to 3291 * expire. 3292 */ 3293 for (i = PHY_FORCE_TIME; i > 0; i--) { 3294 /* 3295 * Read the MII Status Register and wait for Auto-Neg 3296 * Complete bit to be set. 3297 */ 3298 ret_val = em_read_phy_reg(hw, PHY_STATUS, 3299 &mii_status_reg); 3300 if (ret_val) 3301 return ret_val; 3302 3303 ret_val = em_read_phy_reg(hw, PHY_STATUS, 3304 &mii_status_reg); 3305 if (ret_val) 3306 return ret_val; 3307 3308 if (mii_status_reg & MII_SR_LINK_STATUS) 3309 break; 3310 msec_delay(100); 3311 } 3312 if ((i == 0) && 3313 ((hw->phy_type == em_phy_m88) || 3314 (hw->phy_type == em_phy_gg82563) || 3315 (hw->phy_type == em_phy_bm))) { 3316 /* 3317 * We didn't get link. Reset the DSP and wait again 3318 * for link. 3319 */ 3320 ret_val = em_phy_reset_dsp(hw); 3321 if (ret_val) { 3322 DEBUGOUT("Error Resetting PHY DSP\n"); 3323 return ret_val; 3324 } 3325 } 3326 /* 3327 * This loop will early-out if the link condition has been 3328 * met. 3329 */ 3330 for (i = PHY_FORCE_TIME; i > 0; i--) { 3331 if (mii_status_reg & MII_SR_LINK_STATUS) 3332 break; 3333 msec_delay(100); 3334 /* 3335 * Read the MII Status Register and wait for Auto-Neg 3336 * Complete bit to be set. 3337 */ 3338 ret_val = em_read_phy_reg(hw, PHY_STATUS, 3339 &mii_status_reg); 3340 if (ret_val) 3341 return ret_val; 3342 3343 ret_val = em_read_phy_reg(hw, PHY_STATUS, 3344 &mii_status_reg); 3345 if (ret_val) 3346 return ret_val; 3347 } 3348 } 3349 if (hw->phy_type == em_phy_m88 || 3350 hw->phy_type == em_phy_bm || 3351 hw->phy_type == em_phy_oem) { 3352 /* 3353 * Because we reset the PHY above, we need to re-force TX_CLK 3354 * in the Extended PHY Specific Control Register to 25MHz 3355 * clock. This value defaults back to a 2.5MHz clock when 3356 * the PHY is reset. 3357 */ 3358 ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 3359 &phy_data); 3360 if (ret_val) 3361 return ret_val; 3362 3363 phy_data |= M88E1000_EPSCR_TX_CLK_25; 3364 ret_val = em_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 3365 phy_data); 3366 if (ret_val) 3367 return ret_val; 3368 /* 3369 * In addition, because of the s/w reset above, we need to 3370 * enable CRS on TX. This must be set for both full and half 3371 * duplex operation. 3372 */ 3373 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 3374 &phy_data); 3375 if (ret_val) 3376 return ret_val; 3377 3378 if (hw->phy_id == M88E1141_E_PHY_ID) 3379 phy_data &= ~M88E1000_PSCR_ASSERT_CRS_ON_TX; 3380 else 3381 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 3382 3383 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 3384 phy_data); 3385 if (ret_val) 3386 return ret_val; 3387 3388 if ((hw->mac_type == em_82544 || hw->mac_type == em_82543) && 3389 (!hw->autoneg) && (hw->forced_speed_duplex == em_10_full || 3390 hw->forced_speed_duplex == em_10_half)) { 3391 ret_val = em_polarity_reversal_workaround(hw); 3392 if (ret_val) 3393 return ret_val; 3394 } 3395 } else if (hw->phy_type == em_phy_rtl8211) { 3396 /* 3397 * In addition, because of the s/w reset above, we need to enable 3398 * CRX on TX. This must be set for both full and half duplex 3399 * operation. 3400 */ 3401 3402 ret_val = em_read_phy_reg_ex(hw, RGEPHY_CR, &phy_data); 3403 if(ret_val) { 3404 printf("Unable to read RGEPHY_CR register\n"); 3405 return ret_val; 3406 } 3407 3408 phy_data &= ~RGEPHY_CR_ASSERT_CRS; 3409 ret_val = em_write_phy_reg_ex(hw, RGEPHY_CR, phy_data); 3410 if(ret_val) { 3411 printf("Unable to write RGEPHY_CR register\n"); 3412 return ret_val; 3413 } 3414 } else if (hw->phy_type == em_phy_gg82563) { 3415 /* 3416 * The TX_CLK of the Extended PHY Specific Control Register 3417 * defaults to 2.5MHz on a reset. We need to re-force it 3418 * back to 25MHz, if we're not in a forced 10/duplex 3419 * configuration. 3420 */ 3421 ret_val = em_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 3422 &phy_data); 3423 if (ret_val) 3424 return ret_val; 3425 3426 phy_data &= ~GG82563_MSCR_TX_CLK_MASK; 3427 if ((hw->forced_speed_duplex == em_10_full) || 3428 (hw->forced_speed_duplex == em_10_half)) 3429 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ; 3430 else 3431 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25MHZ; 3432 3433 /* Also due to the reset, we need to enable CRS on Tx. */ 3434 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 3435 3436 ret_val = em_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 3437 phy_data); 3438 if (ret_val) 3439 return ret_val; 3440 } 3441 return E1000_SUCCESS; 3442 } 3443 3444 /****************************************************************************** 3445 * Sets the collision distance in the Transmit Control register 3446 * 3447 * hw - Struct containing variables accessed by shared code 3448 * 3449 * Link should have been established previously. Reads the speed and duplex 3450 * information from the Device Status register. 3451 *****************************************************************************/ 3452 void 3453 em_config_collision_dist(struct em_hw *hw) 3454 { 3455 uint32_t tctl, coll_dist; 3456 DEBUGFUNC("em_config_collision_dist"); 3457 3458 if (hw->mac_type < em_82543) 3459 coll_dist = E1000_COLLISION_DISTANCE_82542; 3460 else 3461 coll_dist = E1000_COLLISION_DISTANCE; 3462 3463 tctl = E1000_READ_REG(hw, TCTL); 3464 3465 tctl &= ~E1000_TCTL_COLD; 3466 tctl |= coll_dist << E1000_COLD_SHIFT; 3467 3468 E1000_WRITE_REG(hw, TCTL, tctl); 3469 E1000_WRITE_FLUSH(hw); 3470 } 3471 3472 /****************************************************************************** 3473 * Sets MAC speed and duplex settings to reflect the those in the PHY 3474 * 3475 * hw - Struct containing variables accessed by shared code 3476 * mii_reg - data to write to the MII control register 3477 * 3478 * The contents of the PHY register containing the needed information need to 3479 * be passed in. 3480 *****************************************************************************/ 3481 static int32_t 3482 em_config_mac_to_phy(struct em_hw *hw) 3483 { 3484 uint32_t ctrl; 3485 int32_t ret_val; 3486 uint16_t phy_data; 3487 DEBUGFUNC("em_config_mac_to_phy"); 3488 /* 3489 * 82544 or newer MAC, Auto Speed Detection takes care of MAC 3490 * speed/duplex configuration. 3491 */ 3492 if (hw->mac_type >= em_82544 3493 && hw->mac_type != em_icp_xxxx) 3494 return E1000_SUCCESS; 3495 /* 3496 * Read the Device Control Register and set the bits to Force Speed 3497 * and Duplex. 3498 */ 3499 ctrl = E1000_READ_REG(hw, CTRL); 3500 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 3501 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); 3502 /* 3503 * Set up duplex in the Device Control and Transmit Control registers 3504 * depending on negotiated values. 3505 */ 3506 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 3507 if (ret_val) 3508 return ret_val; 3509 3510 if (phy_data & M88E1000_PSSR_DPLX) 3511 ctrl |= E1000_CTRL_FD; 3512 else 3513 ctrl &= ~E1000_CTRL_FD; 3514 3515 em_config_collision_dist(hw); 3516 /* 3517 * Set up speed in the Device Control register depending on 3518 * negotiated values. 3519 */ 3520 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) 3521 ctrl |= E1000_CTRL_SPD_1000; 3522 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) 3523 ctrl |= E1000_CTRL_SPD_100; 3524 3525 /* Write the configured values back to the Device Control Reg. */ 3526 E1000_WRITE_REG(hw, CTRL, ctrl); 3527 return E1000_SUCCESS; 3528 } 3529 3530 /****************************************************************************** 3531 * Forces the MAC's flow control settings. 3532 * 3533 * hw - Struct containing variables accessed by shared code 3534 * 3535 * Sets the TFCE and RFCE bits in the device control register to reflect 3536 * the adapter settings. TFCE and RFCE need to be explicitly set by 3537 * software when a Copper PHY is used because autonegotiation is managed 3538 * by the PHY rather than the MAC. Software must also configure these 3539 * bits when link is forced on a fiber connection. 3540 *****************************************************************************/ 3541 int32_t 3542 em_force_mac_fc(struct em_hw *hw) 3543 { 3544 uint32_t ctrl; 3545 DEBUGFUNC("em_force_mac_fc"); 3546 3547 /* Get the current configuration of the Device Control Register */ 3548 ctrl = E1000_READ_REG(hw, CTRL); 3549 /* 3550 * Because we didn't get link via the internal auto-negotiation 3551 * mechanism (we either forced link or we got link via PHY auto-neg), 3552 * we have to manually enable/disable transmit an receive flow 3553 * control. 3554 * 3555 * The "Case" statement below enables/disable flow control according to 3556 * the "hw->fc" parameter. 3557 * 3558 * The possible values of the "fc" parameter are: 0: Flow control is 3559 * completely disabled 1: Rx flow control is enabled (we can receive 3560 * pause frames but not send pause frames). 2: Tx flow control is 3561 * enabled (we can send pause frames frames but we do not receive 3562 * pause frames). 3: Both Rx and TX flow control (symmetric) is 3563 * enabled. other: No other values should be possible at this point. 3564 */ 3565 3566 switch (hw->fc) { 3567 case E1000_FC_NONE: 3568 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 3569 break; 3570 case E1000_FC_RX_PAUSE: 3571 ctrl &= (~E1000_CTRL_TFCE); 3572 ctrl |= E1000_CTRL_RFCE; 3573 break; 3574 case E1000_FC_TX_PAUSE: 3575 ctrl &= (~E1000_CTRL_RFCE); 3576 ctrl |= E1000_CTRL_TFCE; 3577 break; 3578 case E1000_FC_FULL: 3579 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 3580 break; 3581 default: 3582 DEBUGOUT("Flow control param set incorrectly\n"); 3583 return -E1000_ERR_CONFIG; 3584 } 3585 3586 /* Disable TX Flow Control for 82542 (rev 2.0) */ 3587 if (hw->mac_type == em_82542_rev2_0) 3588 ctrl &= (~E1000_CTRL_TFCE); 3589 3590 E1000_WRITE_REG(hw, CTRL, ctrl); 3591 return E1000_SUCCESS; 3592 } 3593 /****************************************************************************** 3594 * Configures flow control settings after link is established 3595 * 3596 * hw - Struct containing variables accessed by shared code 3597 * 3598 * Should be called immediately after a valid link has been established. 3599 * Forces MAC flow control settings if link was forced. When in MII/GMII mode 3600 * and autonegotiation is enabled, the MAC flow control settings will be set 3601 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE 3602 * and RFCE bits will be automaticaly set to the negotiated flow control mode. 3603 *****************************************************************************/ 3604 STATIC int32_t 3605 em_config_fc_after_link_up(struct em_hw *hw) 3606 { 3607 int32_t ret_val; 3608 uint16_t mii_status_reg; 3609 uint16_t mii_nway_adv_reg; 3610 uint16_t mii_nway_lp_ability_reg; 3611 uint16_t speed; 3612 uint16_t duplex; 3613 DEBUGFUNC("em_config_fc_after_link_up"); 3614 /* 3615 * Check for the case where we have fiber media and auto-neg failed 3616 * so we had to force link. In this case, we need to force the 3617 * configuration of the MAC to match the "fc" parameter. 3618 */ 3619 if (((hw->media_type == em_media_type_fiber) && (hw->autoneg_failed)) 3620 || ((hw->media_type == em_media_type_internal_serdes) && 3621 (hw->autoneg_failed)) || 3622 ((hw->media_type == em_media_type_copper) && (!hw->autoneg)) || 3623 ((hw->media_type == em_media_type_oem) && (!hw->autoneg))) { 3624 ret_val = em_force_mac_fc(hw); 3625 if (ret_val) { 3626 DEBUGOUT("Error forcing flow control settings\n"); 3627 return ret_val; 3628 } 3629 } 3630 /* 3631 * Check for the case where we have copper media and auto-neg is 3632 * enabled. In this case, we need to check and see if Auto-Neg has 3633 * completed, and if so, how the PHY and link partner has flow 3634 * control configured. 3635 */ 3636 if ((hw->media_type == em_media_type_copper || 3637 (hw->media_type == em_media_type_oem)) && 3638 hw->autoneg) { 3639 /* 3640 * Read the MII Status Register and check to see if AutoNeg 3641 * has completed. We read this twice because this reg has 3642 * some "sticky" (latched) bits. 3643 */ 3644 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 3645 if (ret_val) 3646 return ret_val; 3647 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 3648 if (ret_val) 3649 return ret_val; 3650 3651 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) { 3652 /* 3653 * The AutoNeg process has completed, so we now need 3654 * to read both the Auto Negotiation Advertisement 3655 * Register (Address 4) and the Auto_Negotiation Base 3656 * Page Ability Register (Address 5) to determine how 3657 * flow control was negotiated. 3658 */ 3659 ret_val = em_read_phy_reg(hw, PHY_AUTONEG_ADV, 3660 &mii_nway_adv_reg); 3661 if (ret_val) 3662 return ret_val; 3663 ret_val = em_read_phy_reg(hw, PHY_LP_ABILITY, 3664 &mii_nway_lp_ability_reg); 3665 if (ret_val) 3666 return ret_val; 3667 /* 3668 * Two bits in the Auto Negotiation Advertisement 3669 * Register (Address 4) and two bits in the Auto 3670 * Negotiation Base Page Ability Register (Address 5) 3671 * determine flow control for both the PHY and the 3672 * link partner. The following table, taken out of 3673 * the IEEE 802.3ab/D6.0 dated March 25, 1999, 3674 * describes these PAUSE resolution bits and how flow 3675 * control is determined based upon these settings. 3676 * NOTE: DC = Don't Care 3677 * 3678 * LOCAL DEVICE | LINK PARTNER | 3679 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 3680 * -------|---------|-------|---------|--------------- 3681 * 0 | 0 | DC | DC | em_fc_none 3682 * 0 | 1 | 0 | DC | em_fc_none 3683 * 0 | 1 | 1 | 0 | em_fc_none 3684 * 0 | 1 | 1 | 1 | em_fc_tx_pause 3685 * 1 | 0 | 0 | DC | em_fc_none 3686 * 1 | DC | 1 | DC | em_fc_full 3687 * 1 | 1 | 0 | 0 | em_fc_none 3688 * 1 | 1 | 0 | 1 | em_fc_rx_pause 3689 * 3690 */ 3691 /* 3692 * Are both PAUSE bits set to 1? If so, this implies 3693 * Symmetric Flow Control is enabled at both ends. 3694 * The ASM_DIR bits are irrelevant per the spec. 3695 * 3696 * For Symmetric Flow Control: 3697 * 3698 * LOCAL DEVICE | LINK PARTNER 3699 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 3700 * -------|---------|-------|---------|--------------- 3701 * 1 | DC | 1 | DC | em_fc_full 3702 * 3703 */ 3704 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 3705 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 3706 /* 3707 * Now we need to check if the user selected 3708 * RX ONLY of pause frames. In this case, we 3709 * had to advertise FULL flow control because 3710 * we could not advertise RX ONLY. Hence, we 3711 * must now check to see if we need to turn 3712 * OFF the TRANSMISSION of PAUSE frames. 3713 */ 3714 if (hw->original_fc == E1000_FC_FULL) { 3715 hw->fc = E1000_FC_FULL; 3716 DEBUGOUT("Flow Control = FULL.\n"); 3717 } else { 3718 hw->fc = E1000_FC_RX_PAUSE; 3719 DEBUGOUT("Flow Control = RX PAUSE" 3720 " frames only.\n"); 3721 } 3722 } 3723 /* 3724 * For receiving PAUSE frames ONLY. 3725 * 3726 * LOCAL DEVICE | LINK PARTNER PAUSE | ASM_DIR | 3727 * PAUSE | ASM_DIR | Result 3728 * -------|---------|-------|---------|--------------- 3729 * ----- 0 | 1 | 1 | 1 | 3730 * em_fc_tx_pause 3731 * 3732 */ 3733 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 3734 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 3735 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 3736 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 3737 hw->fc = E1000_FC_TX_PAUSE; 3738 DEBUGOUT("Flow Control = TX PAUSE frames only." 3739 "\n"); 3740 } 3741 /* 3742 * For transmitting PAUSE frames ONLY. 3743 * 3744 * LOCAL DEVICE | LINK PARTNER 3745 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 3746 * -------|---------|-------|---------|--------------- 3747 * 1 | 1 | 0 | 1 | em_fc_rx_pause 3748 * 3749 */ 3750 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 3751 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 3752 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 3753 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 3754 hw->fc = E1000_FC_RX_PAUSE; 3755 DEBUGOUT("Flow Control = RX PAUSE frames only." 3756 "\n"); 3757 } 3758 /* 3759 * Per the IEEE spec, at this point flow control 3760 * should be disabled. However, we want to consider 3761 * that we could be connected to a legacy switch that 3762 * doesn't advertise desired flow control, but can be 3763 * forced on the link partner. So if we advertised 3764 * no flow control, that is what we will resolve to. 3765 * If we advertised some kind of receive capability 3766 * (Rx Pause Only or Full Flow Control) and the link 3767 * partner advertised none, we will configure 3768 * ourselves to enable Rx Flow Control only. We can 3769 * do this safely for two reasons: If the link 3770 * partner really didn't want flow control enabled, 3771 * and we enable Rx, no harm done since we won't be 3772 * receiving any PAUSE frames anyway. If the intent 3773 * on the link partner was to have flow control 3774 * enabled, then by us enabling RX only, we can at 3775 * least receive pause frames and process them. This 3776 * is a good idea because in most cases, since we are 3777 * predominantly a server NIC, more times than not we 3778 * will be asked to delay transmission of packets 3779 * than asking our link partner to pause transmission 3780 * of frames. 3781 */ 3782 else if ((hw->original_fc == E1000_FC_NONE || 3783 hw->original_fc == E1000_FC_TX_PAUSE) || 3784 hw->fc_strict_ieee) { 3785 hw->fc = E1000_FC_NONE; 3786 DEBUGOUT("Flow Control = NONE.\n"); 3787 } else { 3788 hw->fc = E1000_FC_RX_PAUSE; 3789 DEBUGOUT("Flow Control = RX PAUSE frames only." 3790 "\n"); 3791 } 3792 /* 3793 * Now we need to do one last check... If we auto- 3794 * negotiated to HALF DUPLEX, flow control should not 3795 * be enabled per IEEE 802.3 spec. 3796 */ 3797 ret_val = em_get_speed_and_duplex(hw, &speed, &duplex); 3798 if (ret_val) { 3799 DEBUGOUT("Error getting link speed and duplex" 3800 "\n"); 3801 return ret_val; 3802 } 3803 if (duplex == HALF_DUPLEX) 3804 hw->fc = E1000_FC_NONE; 3805 /* 3806 * Now we call a subroutine to actually force the MAC 3807 * controller to use the correct flow control 3808 * settings. 3809 */ 3810 ret_val = em_force_mac_fc(hw); 3811 if (ret_val) { 3812 DEBUGOUT("Error forcing flow control settings" 3813 "\n"); 3814 return ret_val; 3815 } 3816 } else { 3817 DEBUGOUT("Copper PHY and Auto Neg has not completed." 3818 "\n"); 3819 } 3820 } 3821 return E1000_SUCCESS; 3822 } 3823 /****************************************************************************** 3824 * Checks to see if the link status of the hardware has changed. 3825 * 3826 * hw - Struct containing variables accessed by shared code 3827 * 3828 * Called by any function that needs to check the link status of the adapter. 3829 *****************************************************************************/ 3830 int32_t 3831 em_check_for_link(struct em_hw *hw) 3832 { 3833 uint32_t rxcw = 0; 3834 uint32_t ctrl; 3835 uint32_t status; 3836 uint32_t rctl; 3837 uint32_t icr; 3838 uint32_t signal = 0; 3839 int32_t ret_val; 3840 uint16_t phy_data; 3841 DEBUGFUNC("em_check_for_link"); 3842 uint16_t speed, duplex; 3843 3844 if (hw->mac_type >= em_82575 && 3845 hw->media_type != em_media_type_copper) { 3846 ret_val = em_get_pcs_speed_and_duplex_82575(hw, &speed, 3847 &duplex); 3848 hw->get_link_status = hw->serdes_link_down; 3849 3850 return (ret_val); 3851 } 3852 3853 ctrl = E1000_READ_REG(hw, CTRL); 3854 status = E1000_READ_REG(hw, STATUS); 3855 /* 3856 * On adapters with a MAC newer than 82544, SW Defineable pin 1 will 3857 * be set when the optics detect a signal. On older adapters, it will 3858 * be cleared when there is a signal. This applies to fiber media 3859 * only. 3860 */ 3861 if ((hw->media_type == em_media_type_fiber) || 3862 (hw->media_type == em_media_type_internal_serdes)) { 3863 rxcw = E1000_READ_REG(hw, RXCW); 3864 3865 if (hw->media_type == em_media_type_fiber) { 3866 signal = (hw->mac_type > em_82544) ? 3867 E1000_CTRL_SWDPIN1 : 0; 3868 if (status & E1000_STATUS_LU) 3869 hw->get_link_status = FALSE; 3870 } 3871 } 3872 /* 3873 * If we have a copper PHY then we only want to go out to the PHY 3874 * registers to see if Auto-Neg has completed and/or if our link 3875 * status has changed. The get_link_status flag will be set if we 3876 * receive a Link Status Change interrupt or we have Rx Sequence 3877 * Errors. 3878 */ 3879 if ((hw->media_type == em_media_type_copper || 3880 (hw->media_type == em_media_type_oem)) && 3881 hw->get_link_status) { 3882 /* 3883 * First we want to see if the MII Status Register reports 3884 * link. If so, then we want to get the current speed/duplex 3885 * of the PHY. Read the register twice since the link bit is 3886 * sticky. 3887 */ 3888 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 3889 if (ret_val) 3890 return ret_val; 3891 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 3892 if (ret_val) 3893 return ret_val; 3894 3895 hw->icp_xxxx_is_link_up = (phy_data & MII_SR_LINK_STATUS) != 0; 3896 3897 if (hw->mac_type == em_pchlan) { 3898 ret_val = em_k1_gig_workaround_hv(hw, 3899 hw->icp_xxxx_is_link_up); 3900 if (ret_val) 3901 return ret_val; 3902 } 3903 3904 if (phy_data & MII_SR_LINK_STATUS) { 3905 hw->get_link_status = FALSE; 3906 3907 if (hw->phy_type == em_phy_82578) { 3908 ret_val = em_link_stall_workaround_hv(hw); 3909 if (ret_val) 3910 return ret_val; 3911 } 3912 3913 if (hw->mac_type == em_pch2lan) { 3914 ret_val = em_k1_workaround_lv(hw); 3915 if (ret_val) 3916 return ret_val; 3917 } 3918 /* Work-around I218 hang issue */ 3919 if ((hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) || 3920 (hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) || 3921 (hw->device_id == E1000_DEV_ID_PCH_I218_LM3) || 3922 (hw->device_id == E1000_DEV_ID_PCH_I218_V3)) { 3923 ret_val = em_k1_workaround_lpt_lp(hw, 3924 hw->icp_xxxx_is_link_up); 3925 if (ret_val) 3926 return ret_val; 3927 } 3928 3929 /* 3930 * Check if there was DownShift, must be checked 3931 * immediately after link-up 3932 */ 3933 em_check_downshift(hw); 3934 3935 /* Enable/Disable EEE after link up */ 3936 if (hw->mac_type == em_pch2lan || 3937 hw->mac_type == em_pch_lpt || 3938 hw->mac_type == em_pch_spt) { 3939 ret_val = em_set_eee_pchlan(hw); 3940 if (ret_val) 3941 return ret_val; 3942 } 3943 3944 /* 3945 * If we are on 82544 or 82543 silicon and 3946 * speed/duplex are forced to 10H or 10F, then we 3947 * will implement the polarity reversal workaround. 3948 * We disable interrupts first, and upon returning, 3949 * place the devices interrupt state to its previous 3950 * value except for the link status change interrupt 3951 * which will happen due to the execution of this 3952 * workaround. 3953 */ 3954 if ((hw->mac_type == em_82544 || 3955 hw->mac_type == em_82543) && (!hw->autoneg) && 3956 (hw->forced_speed_duplex == em_10_full || 3957 hw->forced_speed_duplex == em_10_half)) { 3958 E1000_WRITE_REG(hw, IMC, 0xffffffff); 3959 ret_val = em_polarity_reversal_workaround(hw); 3960 icr = E1000_READ_REG(hw, ICR); 3961 E1000_WRITE_REG(hw, ICS, 3962 (icr & ~E1000_ICS_LSC)); 3963 E1000_WRITE_REG(hw, IMS, IMS_ENABLE_MASK); 3964 } 3965 } else { 3966 /* No link detected */ 3967 em_config_dsp_after_link_change(hw, FALSE); 3968 return 0; 3969 } 3970 /* 3971 * If we are forcing speed/duplex, then we simply return 3972 * since we have already determined whether we have link or 3973 * not. 3974 */ 3975 if (!hw->autoneg) 3976 return -E1000_ERR_CONFIG; 3977 3978 /* optimize the dsp settings for the igp phy */ 3979 em_config_dsp_after_link_change(hw, TRUE); 3980 /* 3981 * We have a M88E1000 PHY and Auto-Neg is enabled. If we 3982 * have Si on board that is 82544 or newer, Auto Speed 3983 * Detection takes care of MAC speed/duplex configuration. 3984 * So we only need to configure Collision Distance in the 3985 * MAC. Otherwise, we need to force speed/duplex on the MAC 3986 * to the current PHY speed/duplex settings. 3987 */ 3988 if (hw->mac_type >= em_82544 && hw->mac_type != em_icp_xxxx) { 3989 em_config_collision_dist(hw); 3990 } else { 3991 ret_val = em_config_mac_to_phy(hw); 3992 if (ret_val) { 3993 DEBUGOUT("Error configuring MAC to PHY" 3994 " settings\n"); 3995 return ret_val; 3996 } 3997 } 3998 /* 3999 * Configure Flow Control now that Auto-Neg has completed. 4000 * First, we need to restore the desired flow control 4001 * settings because we may have had to re-autoneg with a 4002 * different link partner. 4003 */ 4004 ret_val = em_config_fc_after_link_up(hw); 4005 if (ret_val) { 4006 DEBUGOUT("Error configuring flow control\n"); 4007 return ret_val; 4008 } 4009 /* 4010 * At this point we know that we are on copper and we have 4011 * auto-negotiated link. These are conditions for checking 4012 * the link partner capability register. We use the link 4013 * speed to determine if TBI compatibility needs to be turned 4014 * on or off. If the link is not at gigabit speed, then TBI 4015 * compatibility is not needed. If we are at gigabit speed, 4016 * we turn on TBI compatibility. 4017 */ 4018 if (hw->tbi_compatibility_en) { 4019 uint16_t speed, duplex; 4020 ret_val = em_get_speed_and_duplex(hw, &speed, &duplex); 4021 if (ret_val) { 4022 DEBUGOUT("Error getting link speed and duplex" 4023 "\n"); 4024 return ret_val; 4025 } 4026 if (speed != SPEED_1000) { 4027 /* 4028 * If link speed is not set to gigabit speed, 4029 * we do not need to enable TBI 4030 * compatibility. 4031 */ 4032 if (hw->tbi_compatibility_on) { 4033 /* 4034 * If we previously were in the mode, 4035 * turn it off. 4036 */ 4037 rctl = E1000_READ_REG(hw, RCTL); 4038 rctl &= ~E1000_RCTL_SBP; 4039 E1000_WRITE_REG(hw, RCTL, rctl); 4040 hw->tbi_compatibility_on = FALSE; 4041 } 4042 } else { 4043 /* 4044 * If TBI compatibility is was previously 4045 * off, turn it on. For compatibility with a 4046 * TBI link partner, we will store bad 4047 * packets. Some frames have an additional 4048 * byte on the end and will look like CRC 4049 * errors to to the hardware. 4050 */ 4051 if (!hw->tbi_compatibility_on) { 4052 hw->tbi_compatibility_on = TRUE; 4053 rctl = E1000_READ_REG(hw, RCTL); 4054 rctl |= E1000_RCTL_SBP; 4055 E1000_WRITE_REG(hw, RCTL, rctl); 4056 } 4057 } 4058 } 4059 } 4060 /* 4061 * If we don't have link (auto-negotiation failed or link partner 4062 * cannot auto-negotiate), the cable is plugged in (we have signal), 4063 * and our link partner is not trying to auto-negotiate with us (we 4064 * are receiving idles or data), we need to force link up. We also 4065 * need to give auto-negotiation time to complete, in case the cable 4066 * was just plugged in. The autoneg_failed flag does this. 4067 */ 4068 else if ((((hw->media_type == em_media_type_fiber) && 4069 ((ctrl & E1000_CTRL_SWDPIN1) == signal)) || 4070 (hw->media_type == em_media_type_internal_serdes)) && 4071 (!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) { 4072 if (hw->autoneg_failed == 0) { 4073 hw->autoneg_failed = 1; 4074 return 0; 4075 } 4076 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 4077 4078 /* Disable auto-negotiation in the TXCW register */ 4079 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE)); 4080 4081 /* Force link-up and also force full-duplex. */ 4082 ctrl = E1000_READ_REG(hw, CTRL); 4083 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 4084 E1000_WRITE_REG(hw, CTRL, ctrl); 4085 4086 /* Configure Flow Control after forcing link up. */ 4087 ret_val = em_config_fc_after_link_up(hw); 4088 if (ret_val) { 4089 DEBUGOUT("Error configuring flow control\n"); 4090 return ret_val; 4091 } 4092 } 4093 /* 4094 * If we are forcing link and we are receiving /C/ ordered sets, 4095 * re-enable auto-negotiation in the TXCW register and disable forced 4096 * link in the Device Control register in an attempt to 4097 * auto-negotiate with our link partner. 4098 */ 4099 else if (((hw->media_type == em_media_type_fiber) || 4100 (hw->media_type == em_media_type_internal_serdes)) && 4101 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 4102 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 4103 E1000_WRITE_REG(hw, TXCW, hw->txcw); 4104 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU)); 4105 4106 hw->serdes_link_down = FALSE; 4107 } 4108 /* 4109 * If we force link for non-auto-negotiation switch, check link 4110 * status based on MAC synchronization for internal serdes media 4111 * type. 4112 */ 4113 else if ((hw->media_type == em_media_type_internal_serdes) && 4114 !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) { 4115 /* SYNCH bit and IV bit are sticky. */ 4116 usec_delay(10); 4117 if (E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) { 4118 if (!(rxcw & E1000_RXCW_IV)) { 4119 hw->serdes_link_down = FALSE; 4120 DEBUGOUT("SERDES: Link is up.\n"); 4121 } 4122 } else { 4123 hw->serdes_link_down = TRUE; 4124 DEBUGOUT("SERDES: Link is down.\n"); 4125 } 4126 } 4127 if ((hw->media_type == em_media_type_internal_serdes) && 4128 (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) { 4129 hw->serdes_link_down = !(E1000_STATUS_LU & 4130 E1000_READ_REG(hw, STATUS)); 4131 } 4132 return E1000_SUCCESS; 4133 } 4134 4135 int32_t 4136 em_get_pcs_speed_and_duplex_82575(struct em_hw *hw, uint16_t *speed, 4137 uint16_t *duplex) 4138 { 4139 uint32_t pcs; 4140 4141 hw->serdes_link_down = TRUE; 4142 *speed = 0; 4143 *duplex = 0; 4144 4145 /* 4146 * Read the PCS Status register for link state. For non-copper mode, 4147 * the status register is not accurate. The PCS status register is 4148 * used instead. 4149 */ 4150 pcs = E1000_READ_REG(hw, PCS_LSTAT); 4151 4152 /* 4153 * The link up bit determines when link is up on autoneg. The sync ok 4154 * gets set once both sides sync up and agree upon link. Stable link 4155 * can be determined by checking for both link up and link sync ok 4156 */ 4157 if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) { 4158 hw->serdes_link_down = FALSE; 4159 4160 /* Detect and store PCS speed */ 4161 if (pcs & E1000_PCS_LSTS_SPEED_1000) { 4162 *speed = SPEED_1000; 4163 } else if (pcs & E1000_PCS_LSTS_SPEED_100) { 4164 *speed = SPEED_100; 4165 } else { 4166 *speed = SPEED_10; 4167 } 4168 4169 /* Detect and store PCS duplex */ 4170 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) { 4171 *duplex = FULL_DUPLEX; 4172 } else { 4173 *duplex = HALF_DUPLEX; 4174 } 4175 } 4176 4177 return (0); 4178 } 4179 4180 4181 /****************************************************************************** 4182 * Detects the current speed and duplex settings of the hardware. 4183 * 4184 * hw - Struct containing variables accessed by shared code 4185 * speed - Speed of the connection 4186 * duplex - Duplex setting of the connection 4187 *****************************************************************************/ 4188 int32_t 4189 em_get_speed_and_duplex(struct em_hw *hw, uint16_t *speed, uint16_t *duplex) 4190 { 4191 uint32_t status; 4192 int32_t ret_val; 4193 uint16_t phy_data; 4194 DEBUGFUNC("em_get_speed_and_duplex"); 4195 4196 if (hw->mac_type >= em_82575 && hw->media_type != em_media_type_copper) 4197 return em_get_pcs_speed_and_duplex_82575(hw, speed, duplex); 4198 4199 if (hw->mac_type >= em_82543) { 4200 status = E1000_READ_REG(hw, STATUS); 4201 if (status & E1000_STATUS_SPEED_1000) { 4202 *speed = SPEED_1000; 4203 DEBUGOUT("1000 Mbs, "); 4204 } else if (status & E1000_STATUS_SPEED_100) { 4205 *speed = SPEED_100; 4206 DEBUGOUT("100 Mbs, "); 4207 } else { 4208 *speed = SPEED_10; 4209 DEBUGOUT("10 Mbs, "); 4210 } 4211 4212 if (status & E1000_STATUS_FD) { 4213 *duplex = FULL_DUPLEX; 4214 DEBUGOUT("Full Duplex\n"); 4215 } else { 4216 *duplex = HALF_DUPLEX; 4217 DEBUGOUT(" Half Duplex\n"); 4218 } 4219 } else { 4220 DEBUGOUT("1000 Mbs, Full Duplex\n"); 4221 *speed = SPEED_1000; 4222 *duplex = FULL_DUPLEX; 4223 } 4224 /* 4225 * IGP01 PHY may advertise full duplex operation after speed 4226 * downgrade even if it is operating at half duplex. Here we set the 4227 * duplex settings to match the duplex in the link partner's 4228 * capabilities. 4229 */ 4230 if (hw->phy_type == em_phy_igp && hw->speed_downgraded) { 4231 ret_val = em_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data); 4232 if (ret_val) 4233 return ret_val; 4234 4235 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS)) 4236 *duplex = HALF_DUPLEX; 4237 else { 4238 ret_val = em_read_phy_reg(hw, PHY_LP_ABILITY, 4239 &phy_data); 4240 if (ret_val) 4241 return ret_val; 4242 if ((*speed == SPEED_100 && 4243 !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) || 4244 (*speed == SPEED_10 && 4245 !(phy_data & NWAY_LPAR_10T_FD_CAPS))) 4246 *duplex = HALF_DUPLEX; 4247 } 4248 } 4249 if ((hw->mac_type == em_80003es2lan) && 4250 (hw->media_type == em_media_type_copper)) { 4251 if (*speed == SPEED_1000) 4252 ret_val = em_configure_kmrn_for_1000(hw); 4253 else 4254 ret_val = em_configure_kmrn_for_10_100(hw, *duplex); 4255 if (ret_val) 4256 return ret_val; 4257 } 4258 if ((hw->mac_type == em_ich8lan) && 4259 (hw->phy_type == em_phy_igp_3) && 4260 (*speed == SPEED_1000)) { 4261 ret_val = em_kumeran_lock_loss_workaround(hw); 4262 if (ret_val) 4263 return ret_val; 4264 } 4265 return E1000_SUCCESS; 4266 } 4267 4268 /****************************************************************************** 4269 * Blocks until autoneg completes or times out (~4.5 seconds) 4270 * 4271 * hw - Struct containing variables accessed by shared code 4272 *****************************************************************************/ 4273 STATIC int32_t 4274 em_wait_autoneg(struct em_hw *hw) 4275 { 4276 int32_t ret_val; 4277 uint16_t i; 4278 uint16_t phy_data; 4279 DEBUGFUNC("em_wait_autoneg"); 4280 DEBUGOUT("Waiting for Auto-Neg to complete.\n"); 4281 4282 /* We will wait for autoneg to complete or 4.5 seconds to expire. */ 4283 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) { 4284 /* 4285 * Read the MII Status Register and wait for Auto-Neg 4286 * Complete bit to be set. 4287 */ 4288 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 4289 if (ret_val) 4290 return ret_val; 4291 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 4292 if (ret_val) 4293 return ret_val; 4294 if (phy_data & MII_SR_AUTONEG_COMPLETE) { 4295 return E1000_SUCCESS; 4296 } 4297 msec_delay(100); 4298 } 4299 return E1000_SUCCESS; 4300 } 4301 4302 /****************************************************************************** 4303 * Raises the Management Data Clock 4304 * 4305 * hw - Struct containing variables accessed by shared code 4306 * ctrl - Device control register's current value 4307 *****************************************************************************/ 4308 static void 4309 em_raise_mdi_clk(struct em_hw *hw, uint32_t *ctrl) 4310 { 4311 /* 4312 * Raise the clock input to the Management Data Clock (by setting the 4313 * MDC bit), and then delay 10 microseconds. 4314 */ 4315 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC)); 4316 E1000_WRITE_FLUSH(hw); 4317 usec_delay(10); 4318 } 4319 4320 /****************************************************************************** 4321 * Lowers the Management Data Clock 4322 * 4323 * hw - Struct containing variables accessed by shared code 4324 * ctrl - Device control register's current value 4325 *****************************************************************************/ 4326 static void 4327 em_lower_mdi_clk(struct em_hw *hw, uint32_t *ctrl) 4328 { 4329 /* 4330 * Lower the clock input to the Management Data Clock (by clearing 4331 * the MDC bit), and then delay 10 microseconds. 4332 */ 4333 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC)); 4334 E1000_WRITE_FLUSH(hw); 4335 usec_delay(10); 4336 } 4337 4338 /****************************************************************************** 4339 * Shifts data bits out to the PHY 4340 * 4341 * hw - Struct containing variables accessed by shared code 4342 * data - Data to send out to the PHY 4343 * count - Number of bits to shift out 4344 * 4345 * Bits are shifted out in MSB to LSB order. 4346 *****************************************************************************/ 4347 static void 4348 em_shift_out_mdi_bits(struct em_hw *hw, uint32_t data, uint16_t count) 4349 { 4350 uint32_t ctrl; 4351 uint32_t mask; 4352 /* 4353 * We need to shift "count" number of bits out to the PHY. So, the 4354 * value in the "data" parameter will be shifted out to the PHY one 4355 * bit at a time. In order to do this, "data" must be broken down 4356 * into bits. 4357 */ 4358 mask = 0x01; 4359 mask <<= (count - 1); 4360 4361 ctrl = E1000_READ_REG(hw, CTRL); 4362 4363 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output 4364 * pins. 4365 */ 4366 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); 4367 4368 while (mask) { 4369 /* 4370 * A "1" is shifted out to the PHY by setting the MDIO bit to 4371 * "1" and then raising and lowering the Management Data 4372 * Clock. A "0" is shifted out to the PHY by setting the MDIO 4373 * bit to "0" and then raising and lowering the clock. 4374 */ 4375 if (data & mask) 4376 ctrl |= E1000_CTRL_MDIO; 4377 else 4378 ctrl &= ~E1000_CTRL_MDIO; 4379 4380 E1000_WRITE_REG(hw, CTRL, ctrl); 4381 E1000_WRITE_FLUSH(hw); 4382 4383 usec_delay(10); 4384 4385 em_raise_mdi_clk(hw, &ctrl); 4386 em_lower_mdi_clk(hw, &ctrl); 4387 4388 mask = mask >> 1; 4389 } 4390 } 4391 4392 /****************************************************************************** 4393 * Shifts data bits in from the PHY 4394 * 4395 * hw - Struct containing variables accessed by shared code 4396 * 4397 * Bits are shifted in in MSB to LSB order. 4398 *****************************************************************************/ 4399 static uint16_t 4400 em_shift_in_mdi_bits(struct em_hw *hw) 4401 { 4402 uint32_t ctrl; 4403 uint16_t data = 0; 4404 uint8_t i; 4405 /* 4406 * In order to read a register from the PHY, we need to shift in a 4407 * total of 18 bits from the PHY. The first two bit (turnaround) 4408 * times are used to avoid contention on the MDIO pin when a read 4409 * operation is performed. These two bits are ignored by us and 4410 * thrown away. Bits are "shifted in" by raising the input to the 4411 * Management Data Clock (setting the MDC bit), and then reading the 4412 * value of the MDIO bit. 4413 */ 4414 ctrl = E1000_READ_REG(hw, CTRL); 4415 /* 4416 * Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as 4417 * input. 4418 */ 4419 ctrl &= ~E1000_CTRL_MDIO_DIR; 4420 ctrl &= ~E1000_CTRL_MDIO; 4421 4422 E1000_WRITE_REG(hw, CTRL, ctrl); 4423 E1000_WRITE_FLUSH(hw); 4424 /* 4425 * Raise and Lower the clock before reading in the data. This 4426 * accounts for the turnaround bits. The first clock occurred when we 4427 * clocked out the last bit of the Register Address. 4428 */ 4429 em_raise_mdi_clk(hw, &ctrl); 4430 em_lower_mdi_clk(hw, &ctrl); 4431 4432 for (data = 0, i = 0; i < 16; i++) { 4433 data = data << 1; 4434 em_raise_mdi_clk(hw, &ctrl); 4435 ctrl = E1000_READ_REG(hw, CTRL); 4436 /* Check to see if we shifted in a "1". */ 4437 if (ctrl & E1000_CTRL_MDIO) 4438 data |= 1; 4439 em_lower_mdi_clk(hw, &ctrl); 4440 } 4441 4442 em_raise_mdi_clk(hw, &ctrl); 4443 em_lower_mdi_clk(hw, &ctrl); 4444 4445 return data; 4446 } 4447 4448 STATIC int32_t 4449 em_swfw_sync_acquire(struct em_hw *hw, uint16_t mask) 4450 { 4451 uint32_t swfw_sync = 0; 4452 uint32_t swmask = mask; 4453 uint32_t fwmask = mask << 16; 4454 int32_t timeout = 200; 4455 DEBUGFUNC("em_swfw_sync_acquire"); 4456 4457 if (hw->swfwhw_semaphore_present) 4458 return em_get_software_flag(hw); 4459 4460 if (!hw->swfw_sync_present) 4461 return em_get_hw_eeprom_semaphore(hw); 4462 4463 while (timeout) { 4464 if (em_get_hw_eeprom_semaphore(hw)) 4465 return -E1000_ERR_SWFW_SYNC; 4466 4467 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); 4468 if (!(swfw_sync & (fwmask | swmask))) { 4469 break; 4470 } 4471 /* 4472 * firmware currently using resource (fwmask) 4473 * or other software thread currently using resource (swmask) 4474 */ 4475 em_put_hw_eeprom_semaphore(hw); 4476 msec_delay_irq(5); 4477 timeout--; 4478 } 4479 4480 if (!timeout) { 4481 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout." 4482 "\n"); 4483 return -E1000_ERR_SWFW_SYNC; 4484 } 4485 swfw_sync |= swmask; 4486 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync); 4487 4488 em_put_hw_eeprom_semaphore(hw); 4489 return E1000_SUCCESS; 4490 } 4491 4492 STATIC void 4493 em_swfw_sync_release(struct em_hw *hw, uint16_t mask) 4494 { 4495 uint32_t swfw_sync; 4496 uint32_t swmask = mask; 4497 DEBUGFUNC("em_swfw_sync_release"); 4498 4499 if (hw->swfwhw_semaphore_present) { 4500 em_release_software_flag(hw); 4501 return; 4502 } 4503 if (!hw->swfw_sync_present) { 4504 em_put_hw_eeprom_semaphore(hw); 4505 return; 4506 } 4507 /* 4508 * if (em_get_hw_eeprom_semaphore(hw)) return -E1000_ERR_SWFW_SYNC; 4509 */ 4510 while (em_get_hw_eeprom_semaphore(hw) != E1000_SUCCESS); 4511 /* empty */ 4512 4513 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); 4514 swfw_sync &= ~swmask; 4515 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync); 4516 4517 em_put_hw_eeprom_semaphore(hw); 4518 } 4519 4520 /**************************************************************************** 4521 * Read BM PHY wakeup register. It works as such: 4522 * 1) Set page 769, register 17, bit 2 = 1 4523 * 2) Set page to 800 for host (801 if we were manageability) 4524 * 3) Write the address using the address opcode (0x11) 4525 * 4) Read or write the data using the data opcode (0x12) 4526 * 5) Restore 769_17.2 to its original value 4527 ****************************************************************************/ 4528 int32_t 4529 em_access_phy_wakeup_reg_bm(struct em_hw *hw, uint32_t reg_addr, 4530 uint16_t *phy_data, boolean_t read) 4531 { 4532 int32_t ret_val; 4533 uint16_t reg = BM_PHY_REG_NUM(reg_addr); 4534 uint16_t phy_reg = 0; 4535 4536 /* All operations in this function are phy address 1 */ 4537 hw->phy_addr = 1; 4538 4539 /* Set page 769 */ 4540 em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 4541 (BM_WUC_ENABLE_PAGE << PHY_PAGE_SHIFT)); 4542 4543 ret_val = em_read_phy_reg_ex(hw, BM_WUC_ENABLE_REG, &phy_reg); 4544 if (ret_val) 4545 goto out; 4546 4547 /* First clear bit 4 to avoid a power state change */ 4548 phy_reg &= ~(BM_WUC_HOST_WU_BIT); 4549 ret_val = em_write_phy_reg_ex(hw, BM_WUC_ENABLE_REG, phy_reg); 4550 if (ret_val) 4551 goto out; 4552 4553 /* Write bit 2 = 1, and clear bit 4 to 769_17 */ 4554 ret_val = em_write_phy_reg_ex(hw, BM_WUC_ENABLE_REG, 4555 phy_reg | BM_WUC_ENABLE_BIT); 4556 if (ret_val) 4557 goto out; 4558 4559 /* Select page 800 */ 4560 ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 4561 (BM_WUC_PAGE << PHY_PAGE_SHIFT)); 4562 4563 /* Write the page 800 offset value using opcode 0x11 */ 4564 ret_val = em_write_phy_reg_ex(hw, BM_WUC_ADDRESS_OPCODE, reg); 4565 if (ret_val) 4566 goto out; 4567 4568 if (read) 4569 /* Read the page 800 value using opcode 0x12 */ 4570 ret_val = em_read_phy_reg_ex(hw, BM_WUC_DATA_OPCODE, 4571 phy_data); 4572 else 4573 /* Write the page 800 value using opcode 0x12 */ 4574 ret_val = em_write_phy_reg_ex(hw, BM_WUC_DATA_OPCODE, 4575 *phy_data); 4576 4577 if (ret_val) 4578 goto out; 4579 4580 /* 4581 * Restore 769_17.2 to its original value 4582 * Set page 769 4583 */ 4584 em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 4585 (BM_WUC_ENABLE_PAGE << PHY_PAGE_SHIFT)); 4586 4587 /* Clear 769_17.2 */ 4588 ret_val = em_write_phy_reg_ex(hw, BM_WUC_ENABLE_REG, phy_reg); 4589 if (ret_val) 4590 goto out; 4591 4592 out: 4593 return ret_val; 4594 } 4595 4596 /*************************************************************************** 4597 * Read HV PHY vendor specific high registers 4598 ***************************************************************************/ 4599 int32_t 4600 em_access_phy_debug_regs_hv(struct em_hw *hw, uint32_t reg_addr, 4601 uint16_t *phy_data, boolean_t read) 4602 { 4603 int32_t ret_val; 4604 uint32_t addr_reg = 0; 4605 uint32_t data_reg = 0; 4606 4607 /* This takes care of the difference with desktop vs mobile phy */ 4608 addr_reg = (hw->phy_type == em_phy_82578) ? 4609 I82578_PHY_ADDR_REG : I82577_PHY_ADDR_REG; 4610 data_reg = addr_reg + 1; 4611 4612 /* All operations in this function are phy address 2 */ 4613 hw->phy_addr = 2; 4614 4615 /* masking with 0x3F to remove the page from offset */ 4616 ret_val = em_write_phy_reg_ex(hw, addr_reg, (uint16_t)reg_addr & 0x3F); 4617 if (ret_val) { 4618 printf("Could not write PHY the HV address register\n"); 4619 goto out; 4620 } 4621 4622 /* Read or write the data value next */ 4623 if (read) 4624 ret_val = em_read_phy_reg_ex(hw, data_reg, phy_data); 4625 else 4626 ret_val = em_write_phy_reg_ex(hw, data_reg, *phy_data); 4627 4628 if (ret_val) { 4629 printf("Could not read data value from HV data register\n"); 4630 goto out; 4631 } 4632 4633 out: 4634 return ret_val; 4635 } 4636 4637 /****************************************************************************** 4638 * Reads or writes the value from a PHY register, if the value is on a specific 4639 * non zero page, sets the page first. 4640 * hw - Struct containing variables accessed by shared code 4641 * reg_addr - address of the PHY register to read 4642 *****************************************************************************/ 4643 int32_t 4644 em_access_phy_reg_hv(struct em_hw *hw, uint32_t reg_addr, uint16_t *phy_data, 4645 boolean_t read) 4646 { 4647 uint32_t ret_val; 4648 uint16_t swfw; 4649 uint16_t page = BM_PHY_REG_PAGE(reg_addr); 4650 uint16_t reg = BM_PHY_REG_NUM(reg_addr); 4651 4652 DEBUGFUNC("em_access_phy_reg_hv"); 4653 4654 swfw = E1000_SWFW_PHY0_SM; 4655 4656 if (em_swfw_sync_acquire(hw, swfw)) 4657 return -E1000_ERR_SWFW_SYNC; 4658 4659 if (page == BM_WUC_PAGE) { 4660 ret_val = em_access_phy_wakeup_reg_bm(hw, reg_addr, 4661 phy_data, read); 4662 goto release; 4663 } 4664 4665 if (page >= HV_INTC_FC_PAGE_START) 4666 hw->phy_addr = 1; 4667 else 4668 hw->phy_addr = 2; 4669 4670 if (page == HV_INTC_FC_PAGE_START) 4671 page = 0; 4672 4673 /* 4674 * Workaround MDIO accesses being disabled after entering IEEE Power 4675 * Down (whenever bit 11 of the PHY Control register is set) 4676 */ 4677 if (!read && 4678 (hw->phy_type == em_phy_82578) && 4679 (hw->phy_revision >= 1) && 4680 (hw->phy_addr == 2) && 4681 ((MAX_PHY_REG_ADDRESS & reg) == 0) && 4682 (*phy_data & (1 << 11))) { 4683 uint16_t data2 = 0x7EFF; 4684 4685 ret_val = em_access_phy_debug_regs_hv(hw, (1 << 6) | 0x3, 4686 &data2, FALSE); 4687 if (ret_val) 4688 return ret_val; 4689 } 4690 4691 if (reg_addr > MAX_PHY_MULTI_PAGE_REG) { 4692 ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 4693 (page << PHY_PAGE_SHIFT)); 4694 if (ret_val) 4695 return ret_val; 4696 } 4697 if (read) 4698 ret_val = em_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg, 4699 phy_data); 4700 else 4701 ret_val = em_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg, 4702 *phy_data); 4703 release: 4704 em_swfw_sync_release(hw, swfw); 4705 return ret_val; 4706 } 4707 4708 /****************************************************************************** 4709 * Reads the value from a PHY register, if the value is on a specific non zero 4710 * page, sets the page first. 4711 * hw - Struct containing variables accessed by shared code 4712 * reg_addr - address of the PHY register to read 4713 *****************************************************************************/ 4714 int32_t 4715 em_read_phy_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t *phy_data) 4716 { 4717 uint32_t ret_val; 4718 uint16_t swfw; 4719 DEBUGFUNC("em_read_phy_reg"); 4720 4721 if (hw->mac_type == em_pchlan || 4722 hw->mac_type == em_pch2lan || 4723 hw->mac_type == em_pch_lpt || 4724 hw->mac_type == em_pch_spt) 4725 return (em_access_phy_reg_hv(hw, reg_addr, phy_data, TRUE)); 4726 4727 if (((hw->mac_type == em_80003es2lan) || (hw->mac_type == em_82575)) && 4728 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { 4729 swfw = E1000_SWFW_PHY1_SM; 4730 } else { 4731 swfw = E1000_SWFW_PHY0_SM; 4732 } 4733 if (em_swfw_sync_acquire(hw, swfw)) 4734 return -E1000_ERR_SWFW_SYNC; 4735 4736 if ((hw->phy_type == em_phy_igp || 4737 hw->phy_type == em_phy_igp_3 || 4738 hw->phy_type == em_phy_igp_2) && 4739 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { 4740 ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 4741 (uint16_t) reg_addr); 4742 if (ret_val) { 4743 em_swfw_sync_release(hw, swfw); 4744 return ret_val; 4745 } 4746 } else if (hw->phy_type == em_phy_gg82563) { 4747 if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) || 4748 (hw->mac_type == em_80003es2lan)) { 4749 /* Select Configuration Page */ 4750 if ((reg_addr & MAX_PHY_REG_ADDRESS) < 4751 GG82563_MIN_ALT_REG) { 4752 ret_val = em_write_phy_reg_ex(hw, 4753 GG82563_PHY_PAGE_SELECT, 4754 (uint16_t) ((uint16_t) reg_addr >> 4755 GG82563_PAGE_SHIFT)); 4756 } else { 4757 /* 4758 * Use Alternative Page Select register to 4759 * access registers 30 and 31 4760 */ 4761 ret_val = em_write_phy_reg_ex(hw, 4762 GG82563_PHY_PAGE_SELECT_ALT, 4763 (uint16_t) ((uint16_t) reg_addr >> 4764 GG82563_PAGE_SHIFT)); 4765 } 4766 4767 if (ret_val) { 4768 em_swfw_sync_release(hw, swfw); 4769 return ret_val; 4770 } 4771 } 4772 } else if ((hw->phy_type == em_phy_bm) && (hw->phy_revision == 1)) { 4773 if (reg_addr > MAX_PHY_MULTI_PAGE_REG) { 4774 ret_val = em_write_phy_reg_ex(hw, BM_PHY_PAGE_SELECT, 4775 (uint16_t) ((uint16_t) reg_addr >> 4776 PHY_PAGE_SHIFT)); 4777 if (ret_val) 4778 return ret_val; 4779 } 4780 } 4781 ret_val = em_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, 4782 phy_data); 4783 4784 em_swfw_sync_release(hw, swfw); 4785 return ret_val; 4786 } 4787 4788 STATIC int32_t 4789 em_read_phy_reg_ex(struct em_hw *hw, uint32_t reg_addr, uint16_t *phy_data) 4790 { 4791 uint32_t i; 4792 uint32_t mdic = 0; 4793 DEBUGFUNC("em_read_phy_reg_ex"); 4794 4795 if (reg_addr > MAX_PHY_REG_ADDRESS) { 4796 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); 4797 return -E1000_ERR_PARAM; 4798 } 4799 if (hw->mac_type == em_icp_xxxx) { 4800 *phy_data = gcu_miibus_readreg(hw, hw->icp_xxxx_port_num, 4801 reg_addr); 4802 return E1000_SUCCESS; 4803 } 4804 if (hw->mac_type > em_82543) { 4805 /* 4806 * Set up Op-code, Phy Address, and register address in the 4807 * MDI Control register. The MAC will take care of 4808 * interfacing with the PHY to retrieve the desired data. 4809 */ 4810 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) | 4811 (hw->phy_addr << E1000_MDIC_PHY_SHIFT) | 4812 (E1000_MDIC_OP_READ)); 4813 4814 E1000_WRITE_REG(hw, MDIC, mdic); 4815 4816 /* 4817 * Poll the ready bit to see if the MDI read completed 4818 * Increasing the time out as testing showed failures with 4819 * the lower time out (from FreeBSD driver) 4820 */ 4821 for (i = 0; i < 1960; i++) { 4822 usec_delay(50); 4823 mdic = E1000_READ_REG(hw, MDIC); 4824 if (mdic & E1000_MDIC_READY) 4825 break; 4826 } 4827 if (!(mdic & E1000_MDIC_READY)) { 4828 DEBUGOUT("MDI Read did not complete\n"); 4829 return -E1000_ERR_PHY; 4830 } 4831 if (mdic & E1000_MDIC_ERROR) { 4832 DEBUGOUT("MDI Error\n"); 4833 return -E1000_ERR_PHY; 4834 } 4835 *phy_data = (uint16_t) mdic; 4836 4837 if (hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt || hw->mac_type == em_pch_spt) 4838 usec_delay(100); 4839 } else { 4840 /* 4841 * We must first send a preamble through the MDIO pin to 4842 * signal the beginning of an MII instruction. This is done 4843 * by sending 32 consecutive "1" bits. 4844 */ 4845 em_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 4846 /* 4847 * Now combine the next few fields that are required for a 4848 * read operation. We use this method instead of calling the 4849 * em_shift_out_mdi_bits routine five different times. The 4850 * format of a MII read instruction consists of a shift out 4851 * of 14 bits and is defined as follows: <Preamble><SOF><Op 4852 * Code><Phy Addr><Reg Addr> followed by a shift in of 18 4853 * bits. This first two bits shifted in are TurnAround bits 4854 * used to avoid contention on the MDIO pin when a READ 4855 * operation is performed. These two bits are thrown away 4856 * followed by a shift in of 16 bits which contains the 4857 * desired data. 4858 */ 4859 mdic = ((reg_addr) | (hw->phy_addr << 5) | 4860 (PHY_OP_READ << 10) | (PHY_SOF << 12)); 4861 4862 em_shift_out_mdi_bits(hw, mdic, 14); 4863 /* 4864 * Now that we've shifted out the read command to the MII, we 4865 * need to "shift in" the 16-bit value (18 total bits) of the 4866 * requested PHY register address. 4867 */ 4868 *phy_data = em_shift_in_mdi_bits(hw); 4869 } 4870 return E1000_SUCCESS; 4871 } 4872 4873 /****************************************************************************** 4874 * Writes a value to a PHY register 4875 * 4876 * hw - Struct containing variables accessed by shared code 4877 * reg_addr - address of the PHY register to write 4878 * data - data to write to the PHY 4879 *****************************************************************************/ 4880 int32_t 4881 em_write_phy_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t phy_data) 4882 { 4883 uint32_t ret_val; 4884 DEBUGFUNC("em_write_phy_reg"); 4885 4886 if (hw->mac_type == em_pchlan || 4887 hw->mac_type == em_pch2lan || 4888 hw->mac_type == em_pch_lpt || 4889 hw->mac_type == em_pch_spt) 4890 return (em_access_phy_reg_hv(hw, reg_addr, &phy_data, FALSE)); 4891 4892 if (em_swfw_sync_acquire(hw, hw->swfw)) 4893 return -E1000_ERR_SWFW_SYNC; 4894 4895 if ((hw->phy_type == em_phy_igp || 4896 hw->phy_type == em_phy_igp_3 || 4897 hw->phy_type == em_phy_igp_2) && 4898 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { 4899 ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 4900 (uint16_t) reg_addr); 4901 if (ret_val) { 4902 em_swfw_sync_release(hw, hw->swfw); 4903 return ret_val; 4904 } 4905 } else if (hw->phy_type == em_phy_gg82563) { 4906 if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) || 4907 (hw->mac_type == em_80003es2lan)) { 4908 /* Select Configuration Page */ 4909 if ((reg_addr & MAX_PHY_REG_ADDRESS) < 4910 GG82563_MIN_ALT_REG) { 4911 ret_val = em_write_phy_reg_ex(hw, 4912 GG82563_PHY_PAGE_SELECT, 4913 (uint16_t) ((uint16_t) reg_addr >> 4914 GG82563_PAGE_SHIFT)); 4915 } else { 4916 /* 4917 * Use Alternative Page Select register to 4918 * access registers 30 and 31 4919 */ 4920 ret_val = em_write_phy_reg_ex(hw, 4921 GG82563_PHY_PAGE_SELECT_ALT, 4922 (uint16_t) ((uint16_t) reg_addr >> 4923 GG82563_PAGE_SHIFT)); 4924 } 4925 4926 if (ret_val) { 4927 em_swfw_sync_release(hw, hw->swfw); 4928 return ret_val; 4929 } 4930 } 4931 } else if ((hw->phy_type == em_phy_bm) && (hw->phy_revision == 1)) { 4932 if (reg_addr > MAX_PHY_MULTI_PAGE_REG) { 4933 ret_val = em_write_phy_reg_ex(hw, BM_PHY_PAGE_SELECT, 4934 (uint16_t) ((uint16_t) reg_addr >> 4935 PHY_PAGE_SHIFT)); 4936 if (ret_val) 4937 return ret_val; 4938 } 4939 } 4940 ret_val = em_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, 4941 phy_data); 4942 4943 em_swfw_sync_release(hw, hw->swfw); 4944 return ret_val; 4945 } 4946 4947 STATIC int32_t 4948 em_write_phy_reg_ex(struct em_hw *hw, uint32_t reg_addr, uint16_t phy_data) 4949 { 4950 uint32_t i; 4951 uint32_t mdic = 0; 4952 DEBUGFUNC("em_write_phy_reg_ex"); 4953 4954 if (reg_addr > MAX_PHY_REG_ADDRESS) { 4955 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); 4956 return -E1000_ERR_PARAM; 4957 } 4958 if (hw->mac_type == em_icp_xxxx) { 4959 gcu_miibus_writereg(hw, hw->icp_xxxx_port_num, 4960 reg_addr, phy_data); 4961 return E1000_SUCCESS; 4962 } 4963 if (hw->mac_type > em_82543) { 4964 /* 4965 * Set up Op-code, Phy Address, register address, and data 4966 * intended for the PHY register in the MDI Control register. 4967 * The MAC will take care of interfacing with the PHY to send 4968 * the desired data. 4969 */ 4970 mdic = (((uint32_t) phy_data) | 4971 (reg_addr << E1000_MDIC_REG_SHIFT) | 4972 (hw->phy_addr << E1000_MDIC_PHY_SHIFT) | 4973 (E1000_MDIC_OP_WRITE)); 4974 4975 E1000_WRITE_REG(hw, MDIC, mdic); 4976 4977 /* Poll the ready bit to see if the MDI read completed */ 4978 for (i = 0; i < 641; i++) { 4979 usec_delay(5); 4980 mdic = E1000_READ_REG(hw, MDIC); 4981 if (mdic & E1000_MDIC_READY) 4982 break; 4983 } 4984 if (!(mdic & E1000_MDIC_READY)) { 4985 DEBUGOUT("MDI Write did not complete\n"); 4986 return -E1000_ERR_PHY; 4987 } 4988 4989 if (hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt || hw->mac_type == em_pch_spt) 4990 usec_delay(100); 4991 } else { 4992 /* 4993 * We'll need to use the SW defined pins to shift the write 4994 * command out to the PHY. We first send a preamble to the 4995 * PHY to signal the beginning of the MII instruction. This 4996 * is done by sending 32 consecutive "1" bits. 4997 */ 4998 em_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 4999 /* 5000 * Now combine the remaining required fields that will 5001 * indicate a write operation. We use this method instead of 5002 * calling the em_shift_out_mdi_bits routine for each field 5003 * in the command. The format of a MII write instruction is 5004 * as follows: <Preamble><SOF><Op Code><Phy Addr><Reg 5005 * Addr><Turnaround><Data>. 5006 */ 5007 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | 5008 (hw->phy_addr << 7) | (PHY_OP_WRITE << 12) | 5009 (PHY_SOF << 14)); 5010 mdic <<= 16; 5011 mdic |= (uint32_t) phy_data; 5012 5013 em_shift_out_mdi_bits(hw, mdic, 32); 5014 } 5015 5016 return E1000_SUCCESS; 5017 } 5018 5019 STATIC int32_t 5020 em_read_kmrn_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t *data) 5021 { 5022 uint32_t reg_val; 5023 DEBUGFUNC("em_read_kmrn_reg"); 5024 5025 if (em_swfw_sync_acquire(hw, hw->swfw)) 5026 return -E1000_ERR_SWFW_SYNC; 5027 5028 /* Write register address */ 5029 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) & 5030 E1000_KUMCTRLSTA_OFFSET) | 5031 E1000_KUMCTRLSTA_REN; 5032 5033 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); 5034 usec_delay(2); 5035 5036 /* Read the data returned */ 5037 reg_val = E1000_READ_REG(hw, KUMCTRLSTA); 5038 *data = (uint16_t) reg_val; 5039 5040 em_swfw_sync_release(hw, hw->swfw); 5041 return E1000_SUCCESS; 5042 } 5043 5044 STATIC int32_t 5045 em_write_kmrn_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t data) 5046 { 5047 uint32_t reg_val; 5048 DEBUGFUNC("em_write_kmrn_reg"); 5049 5050 if (em_swfw_sync_acquire(hw, hw->swfw)) 5051 return -E1000_ERR_SWFW_SYNC; 5052 5053 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) & 5054 E1000_KUMCTRLSTA_OFFSET) | data; 5055 5056 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); 5057 usec_delay(2); 5058 5059 em_swfw_sync_release(hw, hw->swfw); 5060 return E1000_SUCCESS; 5061 } 5062 5063 /****************************************************************************** 5064 * Returns the PHY to the power-on reset state 5065 * 5066 * hw - Struct containing variables accessed by shared code 5067 *****************************************************************************/ 5068 int32_t 5069 em_phy_hw_reset(struct em_hw *hw) 5070 { 5071 uint32_t ctrl, ctrl_ext; 5072 uint32_t led_ctrl; 5073 int32_t ret_val; 5074 DEBUGFUNC("em_phy_hw_reset"); 5075 /* 5076 * In the case of the phy reset being blocked, it's not an error, we 5077 * simply return success without performing the reset. 5078 */ 5079 ret_val = em_check_phy_reset_block(hw); 5080 if (ret_val) 5081 return E1000_SUCCESS; 5082 5083 DEBUGOUT("Resetting Phy...\n"); 5084 5085 if (hw->mac_type > em_82543 && hw->mac_type != em_icp_xxxx) { 5086 if (em_swfw_sync_acquire(hw, hw->swfw)) { 5087 DEBUGOUT("Unable to acquire swfw sync\n"); 5088 return -E1000_ERR_SWFW_SYNC; 5089 } 5090 /* 5091 * Read the device control register and assert the 5092 * E1000_CTRL_PHY_RST bit. Then, take it out of reset. For 5093 * pre-em_82571 hardware, we delay for 10ms between the 5094 * assert and deassert. For em_82571 hardware and later, we 5095 * instead delay for 50us between and 10ms after the 5096 * deassertion. 5097 */ 5098 ctrl = E1000_READ_REG(hw, CTRL); 5099 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST); 5100 E1000_WRITE_FLUSH(hw); 5101 5102 if (hw->mac_type < em_82571) 5103 msec_delay(10); 5104 else 5105 usec_delay(100); 5106 5107 E1000_WRITE_REG(hw, CTRL, ctrl); 5108 E1000_WRITE_FLUSH(hw); 5109 5110 if (hw->mac_type >= em_82571) 5111 msec_delay_irq(10); 5112 em_swfw_sync_release(hw, hw->swfw); 5113 /* 5114 * the M88E1141_E_PHY_ID might need reset here, but nothing 5115 * proves it 5116 */ 5117 } else { 5118 /* 5119 * Read the Extended Device Control Register, assert the 5120 * PHY_RESET_DIR bit to put the PHY into reset. Then, take it 5121 * out of reset. 5122 */ 5123 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 5124 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; 5125 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; 5126 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 5127 E1000_WRITE_FLUSH(hw); 5128 msec_delay(10); 5129 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; 5130 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 5131 E1000_WRITE_FLUSH(hw); 5132 } 5133 usec_delay(150); 5134 5135 if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) { 5136 /* Configure activity LED after PHY reset */ 5137 led_ctrl = E1000_READ_REG(hw, LEDCTL); 5138 led_ctrl &= IGP_ACTIVITY_LED_MASK; 5139 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 5140 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 5141 } 5142 /* Wait for FW to finish PHY configuration. */ 5143 ret_val = em_get_phy_cfg_done(hw); 5144 if (ret_val != E1000_SUCCESS) 5145 return ret_val; 5146 em_release_software_semaphore(hw); 5147 5148 if ((hw->mac_type == em_ich8lan) && (hw->phy_type == em_phy_igp_3)) 5149 ret_val = em_init_lcd_from_nvm(hw); 5150 5151 return ret_val; 5152 } 5153 5154 /***************************************************************************** 5155 * SW-based LCD Configuration. 5156 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are 5157 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit 5158 * in NVM determines whether HW should configure LPLU and Gbe Disable. 5159 *****************************************************************************/ 5160 int32_t 5161 em_oem_bits_config_pchlan(struct em_hw *hw, boolean_t d0_state) 5162 { 5163 int32_t ret_val = E1000_SUCCESS; 5164 uint32_t mac_reg; 5165 uint16_t oem_reg; 5166 uint16_t swfw = E1000_SWFW_PHY0_SM; 5167 5168 if (hw->mac_type < em_pchlan) 5169 return ret_val; 5170 5171 ret_val = em_swfw_sync_acquire(hw, swfw); 5172 if (ret_val) 5173 return ret_val; 5174 5175 if (hw->mac_type == em_pchlan) { 5176 mac_reg = E1000_READ_REG(hw, EXTCNF_CTRL); 5177 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) 5178 goto out; 5179 } 5180 5181 mac_reg = E1000_READ_REG(hw, FEXTNVM); 5182 if (!(mac_reg & FEXTNVM_SW_CONFIG_ICH8M)) 5183 goto out; 5184 5185 mac_reg = E1000_READ_REG(hw, PHY_CTRL); 5186 5187 ret_val = em_read_phy_reg(hw, HV_OEM_BITS, &oem_reg); 5188 if (ret_val) 5189 goto out; 5190 5191 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU); 5192 5193 if (d0_state) { 5194 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE) 5195 oem_reg |= HV_OEM_BITS_GBE_DIS; 5196 5197 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU) 5198 oem_reg |= HV_OEM_BITS_LPLU; 5199 /* Restart auto-neg to activate the bits */ 5200 if (!em_check_phy_reset_block(hw)) 5201 oem_reg |= HV_OEM_BITS_RESTART_AN; 5202 5203 } else { 5204 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE | 5205 E1000_PHY_CTRL_NOND0A_GBE_DISABLE)) 5206 oem_reg |= HV_OEM_BITS_GBE_DIS; 5207 5208 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU | 5209 E1000_PHY_CTRL_NOND0A_LPLU)) 5210 oem_reg |= HV_OEM_BITS_LPLU; 5211 } 5212 5213 ret_val = em_write_phy_reg(hw, HV_OEM_BITS, oem_reg); 5214 5215 out: 5216 em_swfw_sync_release(hw, swfw); 5217 5218 return ret_val; 5219 } 5220 5221 5222 /****************************************************************************** 5223 * Resets the PHY 5224 * 5225 * hw - Struct containing variables accessed by shared code 5226 * 5227 * Sets bit 15 of the MII Control regiser 5228 *****************************************************************************/ 5229 int32_t 5230 em_phy_reset(struct em_hw *hw) 5231 { 5232 int32_t ret_val; 5233 uint16_t phy_data; 5234 DEBUGFUNC("em_phy_reset"); 5235 /* 5236 * In the case of the phy reset being blocked, it's not an error, we 5237 * simply return success without performing the reset. 5238 */ 5239 ret_val = em_check_phy_reset_block(hw); 5240 if (ret_val) 5241 return E1000_SUCCESS; 5242 5243 switch (hw->phy_type) { 5244 case em_phy_igp: 5245 case em_phy_igp_2: 5246 case em_phy_igp_3: 5247 case em_phy_ife: 5248 ret_val = em_phy_hw_reset(hw); 5249 if (ret_val) 5250 return ret_val; 5251 break; 5252 default: 5253 ret_val = em_read_phy_reg(hw, PHY_CTRL, &phy_data); 5254 if (ret_val) 5255 return ret_val; 5256 5257 phy_data |= MII_CR_RESET; 5258 ret_val = em_write_phy_reg(hw, PHY_CTRL, phy_data); 5259 if (ret_val) 5260 return ret_val; 5261 5262 usec_delay(1); 5263 break; 5264 } 5265 5266 /* Allow time for h/w to get to a quiescent state after reset */ 5267 msec_delay(10); 5268 5269 if (hw->phy_type == em_phy_igp || hw->phy_type == em_phy_igp_2) 5270 em_phy_init_script(hw); 5271 5272 if (hw->mac_type == em_pchlan) { 5273 ret_val = em_hv_phy_workarounds_ich8lan(hw); 5274 if (ret_val) 5275 return ret_val; 5276 } else if (hw->mac_type == em_pch2lan) { 5277 ret_val = em_lv_phy_workarounds_ich8lan(hw); 5278 if (ret_val) 5279 return ret_val; 5280 } 5281 5282 if (hw->mac_type >= em_pchlan) { 5283 ret_val = em_oem_bits_config_pchlan(hw, TRUE); 5284 if (ret_val) 5285 return ret_val; 5286 } 5287 5288 /* Ungate automatic PHY configuration on non-managed 82579 */ 5289 if ((hw->mac_type == em_pch2lan) && 5290 !(E1000_READ_REG(hw, FWSM) & E1000_FWSM_FW_VALID)) { 5291 msec_delay(10); 5292 em_gate_hw_phy_config_ich8lan(hw, FALSE); 5293 } 5294 5295 if (hw->phy_id == M88E1512_E_PHY_ID) { 5296 ret_val = em_initialize_M88E1512_phy(hw); 5297 if (ret_val) 5298 return ret_val; 5299 } 5300 5301 return E1000_SUCCESS; 5302 } 5303 5304 /****************************************************************************** 5305 * Work-around for 82566 Kumeran PCS lock loss: 5306 * On link status change (i.e. PCI reset, speed change) and link is up and 5307 * speed is gigabit- 5308 * 0) if workaround is optionally disabled do nothing 5309 * 1) wait 1ms for Kumeran link to come up 5310 * 2) check Kumeran Diagnostic register PCS lock loss bit 5311 * 3) if not set the link is locked (all is good), otherwise... 5312 * 4) reset the PHY 5313 * 5) repeat up to 10 times 5314 * Note: this is only called for IGP3 copper when speed is 1gb. 5315 * 5316 * hw - struct containing variables accessed by shared code 5317 *****************************************************************************/ 5318 STATIC int32_t 5319 em_kumeran_lock_loss_workaround(struct em_hw *hw) 5320 { 5321 int32_t ret_val; 5322 int32_t reg; 5323 int32_t cnt; 5324 uint16_t phy_data; 5325 if (hw->kmrn_lock_loss_workaround_disabled) 5326 return E1000_SUCCESS; 5327 /* 5328 * Make sure link is up before proceeding. If not just return. 5329 * Attempting this while link is negotiating fouled up link stability 5330 */ 5331 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 5332 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 5333 5334 if (phy_data & MII_SR_LINK_STATUS) { 5335 for (cnt = 0; cnt < 10; cnt++) { 5336 /* read once to clear */ 5337 ret_val = em_read_phy_reg(hw, IGP3_KMRN_DIAG, 5338 &phy_data); 5339 if (ret_val) 5340 return ret_val; 5341 /* and again to get new status */ 5342 ret_val = em_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data); 5343 if (ret_val) 5344 return ret_val; 5345 5346 /* check for PCS lock */ 5347 if (!(phy_data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) 5348 return E1000_SUCCESS; 5349 5350 /* Issue PHY reset */ 5351 em_phy_hw_reset(hw); 5352 msec_delay_irq(5); 5353 } 5354 /* Disable GigE link negotiation */ 5355 reg = E1000_READ_REG(hw, PHY_CTRL); 5356 E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE 5357 | E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 5358 5359 /* unable to acquire PCS lock */ 5360 return E1000_ERR_PHY; 5361 } 5362 return E1000_SUCCESS; 5363 } 5364 5365 /****************************************************************************** 5366 * Reads and matches the expected PHY address for known PHY IDs 5367 * 5368 * hw - Struct containing variables accessed by shared code 5369 *****************************************************************************/ 5370 STATIC int32_t 5371 em_match_gig_phy(struct em_hw *hw) 5372 { 5373 int32_t phy_init_status, ret_val; 5374 uint16_t phy_id_high, phy_id_low; 5375 boolean_t match = FALSE; 5376 DEBUGFUNC("em_match_gig_phy"); 5377 5378 ret_val = em_read_phy_reg(hw, PHY_ID1, &phy_id_high); 5379 if (ret_val) 5380 return ret_val; 5381 5382 hw->phy_id = (uint32_t) (phy_id_high << 16); 5383 usec_delay(20); 5384 ret_val = em_read_phy_reg(hw, PHY_ID2, &phy_id_low); 5385 if (ret_val) 5386 return ret_val; 5387 5388 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK); 5389 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK; 5390 5391 switch (hw->mac_type) { 5392 case em_82543: 5393 if (hw->phy_id == M88E1000_E_PHY_ID) 5394 match = TRUE; 5395 break; 5396 case em_82544: 5397 if (hw->phy_id == M88E1000_I_PHY_ID) 5398 match = TRUE; 5399 break; 5400 case em_82540: 5401 case em_82545: 5402 case em_82545_rev_3: 5403 case em_82546: 5404 case em_82546_rev_3: 5405 if (hw->phy_id == M88E1011_I_PHY_ID) 5406 match = TRUE; 5407 break; 5408 case em_82541: 5409 case em_82541_rev_2: 5410 case em_82547: 5411 case em_82547_rev_2: 5412 if (hw->phy_id == IGP01E1000_I_PHY_ID) 5413 match = TRUE; 5414 break; 5415 case em_82573: 5416 if (hw->phy_id == M88E1111_I_PHY_ID) 5417 match = TRUE; 5418 break; 5419 case em_82574: 5420 if (hw->phy_id == BME1000_E_PHY_ID) 5421 match = TRUE; 5422 break; 5423 case em_82575: 5424 if (hw->phy_id == M88E1000_E_PHY_ID) 5425 match = TRUE; 5426 if (hw->phy_id == IGP01E1000_I_PHY_ID) 5427 match = TRUE; 5428 if (hw->phy_id == IGP03E1000_E_PHY_ID) 5429 match = TRUE; 5430 break; 5431 case em_82580: 5432 case em_i210: 5433 case em_i350: 5434 if (hw->phy_id == I82580_I_PHY_ID || 5435 hw->phy_id == I210_I_PHY_ID || 5436 hw->phy_id == I347AT4_E_PHY_ID || 5437 hw->phy_id == I350_I_PHY_ID || 5438 hw->phy_id == M88E1112_E_PHY_ID || 5439 hw->phy_id == M88E1543_E_PHY_ID || 5440 hw->phy_id == M88E1512_E_PHY_ID) { 5441 uint32_t mdic; 5442 5443 mdic = EM_READ_REG(hw, E1000_MDICNFG); 5444 mdic &= E1000_MDICNFG_PHY_MASK; 5445 hw->phy_addr = mdic >> E1000_MDICNFG_PHY_SHIFT; 5446 DEBUGOUT1("MDICNFG PHY ADDR %d", 5447 mdic >> E1000_MDICNFG_PHY_SHIFT); 5448 match = TRUE; 5449 } 5450 break; 5451 case em_80003es2lan: 5452 if (hw->phy_id == GG82563_E_PHY_ID) 5453 match = TRUE; 5454 break; 5455 case em_ich8lan: 5456 case em_ich9lan: 5457 case em_ich10lan: 5458 case em_pchlan: 5459 case em_pch2lan: 5460 if (hw->phy_id == IGP03E1000_E_PHY_ID) 5461 match = TRUE; 5462 if (hw->phy_id == IFE_E_PHY_ID) 5463 match = TRUE; 5464 if (hw->phy_id == IFE_PLUS_E_PHY_ID) 5465 match = TRUE; 5466 if (hw->phy_id == IFE_C_E_PHY_ID) 5467 match = TRUE; 5468 if (hw->phy_id == BME1000_E_PHY_ID) 5469 match = TRUE; 5470 if (hw->phy_id == I82577_E_PHY_ID) 5471 match = TRUE; 5472 if (hw->phy_id == I82578_E_PHY_ID) 5473 match = TRUE; 5474 if (hw->phy_id == I82579_E_PHY_ID) 5475 match = TRUE; 5476 break; 5477 case em_pch_lpt: 5478 case em_pch_spt: 5479 if (hw->phy_id == I217_E_PHY_ID) 5480 match = TRUE; 5481 break; 5482 case em_icp_xxxx: 5483 if (hw->phy_id == M88E1141_E_PHY_ID) 5484 match = TRUE; 5485 if (hw->phy_id == RTL8211_E_PHY_ID) 5486 match = TRUE; 5487 break; 5488 default: 5489 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type); 5490 return -E1000_ERR_CONFIG; 5491 } 5492 phy_init_status = em_set_phy_type(hw); 5493 5494 if ((match) && (phy_init_status == E1000_SUCCESS)) { 5495 DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id); 5496 return E1000_SUCCESS; 5497 } 5498 DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id); 5499 return -E1000_ERR_PHY; 5500 } 5501 5502 /****************************************************************************** 5503 * Probes the expected PHY address for known PHY IDs 5504 * 5505 * hw - Struct containing variables accessed by shared code 5506 *****************************************************************************/ 5507 STATIC int32_t 5508 em_detect_gig_phy(struct em_hw *hw) 5509 { 5510 int32_t ret_val; 5511 DEBUGFUNC("em_detect_gig_phy"); 5512 5513 if (hw->phy_id != 0) 5514 return E1000_SUCCESS; 5515 5516 /* default phy address, most phys reside here, but not all (ICH10) */ 5517 if (hw->mac_type != em_icp_xxxx) 5518 hw->phy_addr = 1; 5519 else 5520 hw->phy_addr = 0; /* There is a phy at phy_addr 0 on EP80579 */ 5521 5522 /* 5523 * The 82571 firmware may still be configuring the PHY. In this 5524 * case, we cannot access the PHY until the configuration is done. 5525 * So we explicitly set the PHY values. 5526 */ 5527 if (hw->mac_type == em_82571 || 5528 hw->mac_type == em_82572) { 5529 hw->phy_id = IGP01E1000_I_PHY_ID; 5530 hw->phy_type = em_phy_igp_2; 5531 return E1000_SUCCESS; 5532 } 5533 5534 /* 5535 * Some of the fiber cards dont have a phy, so we must exit cleanly 5536 * here 5537 */ 5538 if ((hw->media_type == em_media_type_fiber) && 5539 (hw->mac_type == em_82542_rev2_0 || 5540 hw->mac_type == em_82542_rev2_1 || 5541 hw->mac_type == em_82543 || 5542 hw->mac_type == em_82573 || 5543 hw->mac_type == em_82574 || 5544 hw->mac_type == em_80003es2lan)) { 5545 hw->phy_type = em_phy_undefined; 5546 return E1000_SUCCESS; 5547 } 5548 5549 if ((hw->media_type == em_media_type_internal_serdes || 5550 hw->media_type == em_media_type_fiber) && 5551 hw->mac_type >= em_82575) { 5552 hw->phy_type = em_phy_undefined; 5553 return E1000_SUCCESS; 5554 } 5555 5556 /* 5557 * Up to 82543 (incl), we need reset the phy, or it might not get 5558 * detected 5559 */ 5560 if (hw->mac_type <= em_82543) { 5561 ret_val = em_phy_hw_reset(hw); 5562 if (ret_val) 5563 return ret_val; 5564 } 5565 /* 5566 * ESB-2 PHY reads require em_phy_gg82563 to be set because of a 5567 * work- around that forces PHY page 0 to be set or the reads fail. 5568 * The rest of the code in this routine uses em_read_phy_reg to read 5569 * the PHY ID. So for ESB-2 we need to have this set so our reads 5570 * won't fail. If the attached PHY is not a em_phy_gg82563, the 5571 * routines below will figure this out as well. 5572 */ 5573 if (hw->mac_type == em_80003es2lan) 5574 hw->phy_type = em_phy_gg82563; 5575 5576 /* Power on SGMII phy if it is disabled */ 5577 if (hw->mac_type == em_82580 || hw->mac_type == em_i210 || 5578 hw->mac_type == em_i350) { 5579 uint32_t ctrl_ext = EM_READ_REG(hw, E1000_CTRL_EXT); 5580 EM_WRITE_REG(hw, E1000_CTRL_EXT, 5581 ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA); 5582 delay(300); 5583 } 5584 5585 /* Read the PHY ID Registers to identify which PHY is onboard. */ 5586 for (hw->phy_addr = 1; (hw->phy_addr < 4); hw->phy_addr++) { 5587 ret_val = em_match_gig_phy(hw); 5588 if (ret_val == E1000_SUCCESS) 5589 return E1000_SUCCESS; 5590 } 5591 return -E1000_ERR_PHY; 5592 } 5593 5594 /****************************************************************************** 5595 * Resets the PHY's DSP 5596 * 5597 * hw - Struct containing variables accessed by shared code 5598 *****************************************************************************/ 5599 static int32_t 5600 em_phy_reset_dsp(struct em_hw *hw) 5601 { 5602 int32_t ret_val; 5603 DEBUGFUNC("em_phy_reset_dsp"); 5604 5605 do { 5606 if (hw->phy_type != em_phy_gg82563) { 5607 ret_val = em_write_phy_reg(hw, 29, 0x001d); 5608 if (ret_val) 5609 break; 5610 } 5611 ret_val = em_write_phy_reg(hw, 30, 0x00c1); 5612 if (ret_val) 5613 break; 5614 ret_val = em_write_phy_reg(hw, 30, 0x0000); 5615 if (ret_val) 5616 break; 5617 ret_val = E1000_SUCCESS; 5618 } while (0); 5619 5620 return ret_val; 5621 } 5622 5623 /****************************************************************************** 5624 * Sets up eeprom variables in the hw struct. Must be called after mac_type 5625 * is configured. Additionally, if this is ICH8, the flash controller GbE 5626 * registers must be mapped, or this will crash. 5627 * 5628 * hw - Struct containing variables accessed by shared code 5629 *****************************************************************************/ 5630 int32_t 5631 em_init_eeprom_params(struct em_hw *hw) 5632 { 5633 struct em_eeprom_info *eeprom = &hw->eeprom; 5634 uint32_t eecd = E1000_READ_REG(hw, EECD); 5635 int32_t ret_val = E1000_SUCCESS; 5636 uint16_t eeprom_size; 5637 DEBUGFUNC("em_init_eeprom_params"); 5638 5639 switch (hw->mac_type) { 5640 case em_82542_rev2_0: 5641 case em_82542_rev2_1: 5642 case em_82543: 5643 case em_82544: 5644 eeprom->type = em_eeprom_microwire; 5645 eeprom->word_size = 64; 5646 eeprom->opcode_bits = 3; 5647 eeprom->address_bits = 6; 5648 eeprom->delay_usec = 50; 5649 eeprom->use_eerd = FALSE; 5650 eeprom->use_eewr = FALSE; 5651 break; 5652 case em_82540: 5653 case em_82545: 5654 case em_82545_rev_3: 5655 case em_icp_xxxx: 5656 case em_82546: 5657 case em_82546_rev_3: 5658 eeprom->type = em_eeprom_microwire; 5659 eeprom->opcode_bits = 3; 5660 eeprom->delay_usec = 50; 5661 if (eecd & E1000_EECD_SIZE) { 5662 eeprom->word_size = 256; 5663 eeprom->address_bits = 8; 5664 } else { 5665 eeprom->word_size = 64; 5666 eeprom->address_bits = 6; 5667 } 5668 eeprom->use_eerd = FALSE; 5669 eeprom->use_eewr = FALSE; 5670 break; 5671 case em_82541: 5672 case em_82541_rev_2: 5673 case em_82547: 5674 case em_82547_rev_2: 5675 if (eecd & E1000_EECD_TYPE) { 5676 eeprom->type = em_eeprom_spi; 5677 eeprom->opcode_bits = 8; 5678 eeprom->delay_usec = 1; 5679 if (eecd & E1000_EECD_ADDR_BITS) { 5680 eeprom->page_size = 32; 5681 eeprom->address_bits = 16; 5682 } else { 5683 eeprom->page_size = 8; 5684 eeprom->address_bits = 8; 5685 } 5686 } else { 5687 eeprom->type = em_eeprom_microwire; 5688 eeprom->opcode_bits = 3; 5689 eeprom->delay_usec = 50; 5690 if (eecd & E1000_EECD_ADDR_BITS) { 5691 eeprom->word_size = 256; 5692 eeprom->address_bits = 8; 5693 } else { 5694 eeprom->word_size = 64; 5695 eeprom->address_bits = 6; 5696 } 5697 } 5698 eeprom->use_eerd = FALSE; 5699 eeprom->use_eewr = FALSE; 5700 break; 5701 case em_82571: 5702 case em_82572: 5703 eeprom->type = em_eeprom_spi; 5704 eeprom->opcode_bits = 8; 5705 eeprom->delay_usec = 1; 5706 if (eecd & E1000_EECD_ADDR_BITS) { 5707 eeprom->page_size = 32; 5708 eeprom->address_bits = 16; 5709 } else { 5710 eeprom->page_size = 8; 5711 eeprom->address_bits = 8; 5712 } 5713 eeprom->use_eerd = FALSE; 5714 eeprom->use_eewr = FALSE; 5715 break; 5716 case em_82573: 5717 case em_82574: 5718 case em_82575: 5719 case em_82580: 5720 case em_i210: 5721 case em_i350: 5722 eeprom->type = em_eeprom_spi; 5723 eeprom->opcode_bits = 8; 5724 eeprom->delay_usec = 1; 5725 if (eecd & E1000_EECD_ADDR_BITS) { 5726 eeprom->page_size = 32; 5727 eeprom->address_bits = 16; 5728 } else { 5729 eeprom->page_size = 8; 5730 eeprom->address_bits = 8; 5731 } 5732 eeprom->use_eerd = TRUE; 5733 eeprom->use_eewr = TRUE; 5734 if (em_is_onboard_nvm_eeprom(hw) == FALSE) { 5735 eeprom->type = em_eeprom_flash; 5736 eeprom->word_size = 2048; 5737 /* 5738 * Ensure that the Autonomous FLASH update bit is 5739 * cleared due to Flash update issue on parts which 5740 * use a FLASH for NVM. 5741 */ 5742 eecd &= ~E1000_EECD_AUPDEN; 5743 E1000_WRITE_REG(hw, EECD, eecd); 5744 } 5745 if (em_get_flash_presence_i210(hw) == FALSE) { 5746 eeprom->type = em_eeprom_invm; 5747 eeprom->word_size = INVM_SIZE; 5748 eeprom->use_eerd = FALSE; 5749 eeprom->use_eewr = FALSE; 5750 } 5751 break; 5752 case em_80003es2lan: 5753 eeprom->type = em_eeprom_spi; 5754 eeprom->opcode_bits = 8; 5755 eeprom->delay_usec = 1; 5756 if (eecd & E1000_EECD_ADDR_BITS) { 5757 eeprom->page_size = 32; 5758 eeprom->address_bits = 16; 5759 } else { 5760 eeprom->page_size = 8; 5761 eeprom->address_bits = 8; 5762 } 5763 eeprom->use_eerd = TRUE; 5764 eeprom->use_eewr = FALSE; 5765 break; 5766 case em_ich8lan: 5767 case em_ich9lan: 5768 case em_ich10lan: 5769 case em_pchlan: 5770 case em_pch2lan: 5771 case em_pch_lpt: 5772 { 5773 int32_t i = 0; 5774 uint32_t flash_size = 5775 E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_GFPREG); 5776 eeprom->type = em_eeprom_ich8; 5777 eeprom->use_eerd = FALSE; 5778 eeprom->use_eewr = FALSE; 5779 eeprom->word_size = E1000_SHADOW_RAM_WORDS; 5780 /* 5781 * Zero the shadow RAM structure. But don't load it 5782 * from NVM so as to save time for driver init 5783 */ 5784 if (hw->eeprom_shadow_ram != NULL) { 5785 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 5786 hw->eeprom_shadow_ram[i].modified = 5787 FALSE; 5788 hw->eeprom_shadow_ram[i].eeprom_word = 5789 0xFFFF; 5790 } 5791 } 5792 hw->flash_base_addr = (flash_size & 5793 ICH_GFPREG_BASE_MASK) * ICH_FLASH_SECTOR_SIZE; 5794 5795 hw->flash_bank_size = ((flash_size >> 16) & 5796 ICH_GFPREG_BASE_MASK) + 1; 5797 hw->flash_bank_size -= (flash_size & 5798 ICH_GFPREG_BASE_MASK); 5799 5800 hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE; 5801 5802 hw->flash_bank_size /= 2 * sizeof(uint16_t); 5803 5804 break; 5805 } 5806 case em_pch_spt: 5807 { 5808 int32_t i = 0; 5809 uint32_t flash_size = EM_READ_REG(hw, 0xc /* STRAP */); 5810 5811 eeprom->type = em_eeprom_ich8; 5812 eeprom->use_eerd = FALSE; 5813 eeprom->use_eewr = FALSE; 5814 eeprom->word_size = E1000_SHADOW_RAM_WORDS; 5815 /* 5816 * Zero the shadow RAM structure. But don't load it 5817 * from NVM so as to save time for driver init 5818 */ 5819 if (hw->eeprom_shadow_ram != NULL) { 5820 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 5821 hw->eeprom_shadow_ram[i].modified = 5822 FALSE; 5823 hw->eeprom_shadow_ram[i].eeprom_word = 5824 0xFFFF; 5825 } 5826 } 5827 hw->flash_base_addr = 0; 5828 flash_size = ((flash_size >> 1) & 0x1f) + 1; 5829 flash_size *= 4096; 5830 hw->flash_bank_size = flash_size / 4; 5831 } 5832 break; 5833 default: 5834 break; 5835 } 5836 5837 if (eeprom->type == em_eeprom_spi) { 5838 /* 5839 * eeprom_size will be an enum [0..8] that maps to eeprom 5840 * sizes 128B to 32KB (incremented by powers of 2). 5841 */ 5842 if (hw->mac_type <= em_82547_rev_2) { 5843 /* Set to default value for initial eeprom read. */ 5844 eeprom->word_size = 64; 5845 ret_val = em_read_eeprom(hw, EEPROM_CFG, 1, 5846 &eeprom_size); 5847 if (ret_val) 5848 return ret_val; 5849 eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> 5850 EEPROM_SIZE_SHIFT; 5851 /* 5852 * 256B eeprom size was not supported in earlier 5853 * hardware, so we bump eeprom_size up one to ensure 5854 * that "1" (which maps to 256B) is never the result 5855 * used in the shifting logic below. 5856 */ 5857 if (eeprom_size) 5858 eeprom_size++; 5859 } else { 5860 eeprom_size = (uint16_t) ( 5861 (eecd & E1000_EECD_SIZE_EX_MASK) >> 5862 E1000_EECD_SIZE_EX_SHIFT); 5863 } 5864 5865 /* EEPROM access above 16k is unsupported */ 5866 if (eeprom_size + EEPROM_WORD_SIZE_SHIFT > 5867 EEPROM_WORD_SIZE_SHIFT_MAX) { 5868 eeprom->word_size = 1 << EEPROM_WORD_SIZE_SHIFT_MAX; 5869 } else { 5870 eeprom->word_size = 1 << 5871 (eeprom_size + EEPROM_WORD_SIZE_SHIFT); 5872 } 5873 } 5874 return ret_val; 5875 } 5876 5877 /****************************************************************************** 5878 * Raises the EEPROM's clock input. 5879 * 5880 * hw - Struct containing variables accessed by shared code 5881 * eecd - EECD's current value 5882 *****************************************************************************/ 5883 static void 5884 em_raise_ee_clk(struct em_hw *hw, uint32_t *eecd) 5885 { 5886 /* 5887 * Raise the clock input to the EEPROM (by setting the SK bit), and 5888 * then wait <delay> microseconds. 5889 */ 5890 *eecd = *eecd | E1000_EECD_SK; 5891 E1000_WRITE_REG(hw, EECD, *eecd); 5892 E1000_WRITE_FLUSH(hw); 5893 usec_delay(hw->eeprom.delay_usec); 5894 } 5895 5896 /****************************************************************************** 5897 * Lowers the EEPROM's clock input. 5898 * 5899 * hw - Struct containing variables accessed by shared code 5900 * eecd - EECD's current value 5901 *****************************************************************************/ 5902 static void 5903 em_lower_ee_clk(struct em_hw *hw, uint32_t *eecd) 5904 { 5905 /* 5906 * Lower the clock input to the EEPROM (by clearing the SK bit), and 5907 * then wait 50 microseconds. 5908 */ 5909 *eecd = *eecd & ~E1000_EECD_SK; 5910 E1000_WRITE_REG(hw, EECD, *eecd); 5911 E1000_WRITE_FLUSH(hw); 5912 usec_delay(hw->eeprom.delay_usec); 5913 } 5914 5915 /****************************************************************************** 5916 * Shift data bits out to the EEPROM. 5917 * 5918 * hw - Struct containing variables accessed by shared code 5919 * data - data to send to the EEPROM 5920 * count - number of bits to shift out 5921 *****************************************************************************/ 5922 static void 5923 em_shift_out_ee_bits(struct em_hw *hw, uint16_t data, uint16_t count) 5924 { 5925 struct em_eeprom_info *eeprom = &hw->eeprom; 5926 uint32_t eecd; 5927 uint32_t mask; 5928 /* 5929 * We need to shift "count" bits out to the EEPROM. So, value in the 5930 * "data" parameter will be shifted out to the EEPROM one bit at a 5931 * time. In order to do this, "data" must be broken down into bits. 5932 */ 5933 mask = 0x01 << (count - 1); 5934 eecd = E1000_READ_REG(hw, EECD); 5935 if (eeprom->type == em_eeprom_microwire) { 5936 eecd &= ~E1000_EECD_DO; 5937 } else if (eeprom->type == em_eeprom_spi) { 5938 eecd |= E1000_EECD_DO; 5939 } 5940 do { 5941 /* 5942 * A "1" is shifted out to the EEPROM by setting bit "DI" to 5943 * a "1", and then raising and then lowering the clock (the 5944 * SK bit controls the clock input to the EEPROM). A "0" is 5945 * shifted out to the EEPROM by setting "DI" to "0" and then 5946 * raising and then lowering the clock. 5947 */ 5948 eecd &= ~E1000_EECD_DI; 5949 5950 if (data & mask) 5951 eecd |= E1000_EECD_DI; 5952 5953 E1000_WRITE_REG(hw, EECD, eecd); 5954 E1000_WRITE_FLUSH(hw); 5955 5956 usec_delay(eeprom->delay_usec); 5957 5958 em_raise_ee_clk(hw, &eecd); 5959 em_lower_ee_clk(hw, &eecd); 5960 5961 mask = mask >> 1; 5962 5963 } while (mask); 5964 5965 /* We leave the "DI" bit set to "0" when we leave this routine. */ 5966 eecd &= ~E1000_EECD_DI; 5967 E1000_WRITE_REG(hw, EECD, eecd); 5968 } 5969 5970 /****************************************************************************** 5971 * Shift data bits in from the EEPROM 5972 * 5973 * hw - Struct containing variables accessed by shared code 5974 *****************************************************************************/ 5975 static uint16_t 5976 em_shift_in_ee_bits(struct em_hw *hw, uint16_t count) 5977 { 5978 uint32_t eecd; 5979 uint32_t i; 5980 uint16_t data; 5981 /* 5982 * In order to read a register from the EEPROM, we need to shift 5983 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising 5984 * the clock input to the EEPROM (setting the SK bit), and then 5985 * reading the value of the "DO" bit. During this "shifting in" 5986 * process the "DI" bit should always be clear. 5987 */ 5988 5989 eecd = E1000_READ_REG(hw, EECD); 5990 5991 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 5992 data = 0; 5993 5994 for (i = 0; i < count; i++) { 5995 data = data << 1; 5996 em_raise_ee_clk(hw, &eecd); 5997 5998 eecd = E1000_READ_REG(hw, EECD); 5999 6000 eecd &= ~(E1000_EECD_DI); 6001 if (eecd & E1000_EECD_DO) 6002 data |= 1; 6003 6004 em_lower_ee_clk(hw, &eecd); 6005 } 6006 6007 return data; 6008 } 6009 /****************************************************************************** 6010 * Prepares EEPROM for access 6011 * 6012 * hw - Struct containing variables accessed by shared code 6013 * 6014 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This 6015 * function should be called before issuing a command to the EEPROM. 6016 *****************************************************************************/ 6017 static int32_t 6018 em_acquire_eeprom(struct em_hw *hw) 6019 { 6020 struct em_eeprom_info *eeprom = &hw->eeprom; 6021 uint32_t eecd, i = 0; 6022 DEBUGFUNC("em_acquire_eeprom"); 6023 6024 if (em_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM)) 6025 return -E1000_ERR_SWFW_SYNC; 6026 eecd = E1000_READ_REG(hw, EECD); 6027 6028 if ((hw->mac_type != em_82573) && (hw->mac_type != em_82574)) { 6029 /* Request EEPROM Access */ 6030 if (hw->mac_type > em_82544) { 6031 eecd |= E1000_EECD_REQ; 6032 E1000_WRITE_REG(hw, EECD, eecd); 6033 eecd = E1000_READ_REG(hw, EECD); 6034 while ((!(eecd & E1000_EECD_GNT)) && 6035 (i < E1000_EEPROM_GRANT_ATTEMPTS)) { 6036 i++; 6037 usec_delay(5); 6038 eecd = E1000_READ_REG(hw, EECD); 6039 } 6040 if (!(eecd & E1000_EECD_GNT)) { 6041 eecd &= ~E1000_EECD_REQ; 6042 E1000_WRITE_REG(hw, EECD, eecd); 6043 DEBUGOUT("Could not acquire EEPROM grant\n"); 6044 em_swfw_sync_release(hw, E1000_SWFW_EEP_SM); 6045 return -E1000_ERR_EEPROM; 6046 } 6047 } 6048 } 6049 6050 /* Setup EEPROM for Read/Write */ 6051 if (eeprom->type == em_eeprom_microwire) { 6052 /* Clear SK and DI */ 6053 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK); 6054 E1000_WRITE_REG(hw, EECD, eecd); 6055 6056 /* Set CS */ 6057 eecd |= E1000_EECD_CS; 6058 E1000_WRITE_REG(hw, EECD, eecd); 6059 } else if (eeprom->type == em_eeprom_spi) { 6060 /* Clear SK and CS */ 6061 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 6062 E1000_WRITE_REG(hw, EECD, eecd); 6063 usec_delay(1); 6064 } 6065 return E1000_SUCCESS; 6066 } 6067 6068 /****************************************************************************** 6069 * Returns EEPROM to a "standby" state 6070 * 6071 * hw - Struct containing variables accessed by shared code 6072 *****************************************************************************/ 6073 static void 6074 em_standby_eeprom(struct em_hw *hw) 6075 { 6076 struct em_eeprom_info *eeprom = &hw->eeprom; 6077 uint32_t eecd; 6078 eecd = E1000_READ_REG(hw, EECD); 6079 6080 if (eeprom->type == em_eeprom_microwire) { 6081 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 6082 E1000_WRITE_REG(hw, EECD, eecd); 6083 E1000_WRITE_FLUSH(hw); 6084 usec_delay(eeprom->delay_usec); 6085 6086 /* Clock high */ 6087 eecd |= E1000_EECD_SK; 6088 E1000_WRITE_REG(hw, EECD, eecd); 6089 E1000_WRITE_FLUSH(hw); 6090 usec_delay(eeprom->delay_usec); 6091 6092 /* Select EEPROM */ 6093 eecd |= E1000_EECD_CS; 6094 E1000_WRITE_REG(hw, EECD, eecd); 6095 E1000_WRITE_FLUSH(hw); 6096 usec_delay(eeprom->delay_usec); 6097 6098 /* Clock low */ 6099 eecd &= ~E1000_EECD_SK; 6100 E1000_WRITE_REG(hw, EECD, eecd); 6101 E1000_WRITE_FLUSH(hw); 6102 usec_delay(eeprom->delay_usec); 6103 } else if (eeprom->type == em_eeprom_spi) { 6104 /* Toggle CS to flush commands */ 6105 eecd |= E1000_EECD_CS; 6106 E1000_WRITE_REG(hw, EECD, eecd); 6107 E1000_WRITE_FLUSH(hw); 6108 usec_delay(eeprom->delay_usec); 6109 eecd &= ~E1000_EECD_CS; 6110 E1000_WRITE_REG(hw, EECD, eecd); 6111 E1000_WRITE_FLUSH(hw); 6112 usec_delay(eeprom->delay_usec); 6113 } 6114 } 6115 6116 /****************************************************************************** 6117 * Terminates a command by inverting the EEPROM's chip select pin 6118 * 6119 * hw - Struct containing variables accessed by shared code 6120 *****************************************************************************/ 6121 static void 6122 em_release_eeprom(struct em_hw *hw) 6123 { 6124 uint32_t eecd; 6125 DEBUGFUNC("em_release_eeprom"); 6126 6127 eecd = E1000_READ_REG(hw, EECD); 6128 6129 if (hw->eeprom.type == em_eeprom_spi) { 6130 eecd |= E1000_EECD_CS; /* Pull CS high */ 6131 eecd &= ~E1000_EECD_SK; /* Lower SCK */ 6132 6133 E1000_WRITE_REG(hw, EECD, eecd); 6134 6135 usec_delay(hw->eeprom.delay_usec); 6136 } else if (hw->eeprom.type == em_eeprom_microwire) { 6137 /* cleanup eeprom */ 6138 6139 /* CS on Microwire is active-high */ 6140 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); 6141 6142 E1000_WRITE_REG(hw, EECD, eecd); 6143 6144 /* Rising edge of clock */ 6145 eecd |= E1000_EECD_SK; 6146 E1000_WRITE_REG(hw, EECD, eecd); 6147 E1000_WRITE_FLUSH(hw); 6148 usec_delay(hw->eeprom.delay_usec); 6149 6150 /* Falling edge of clock */ 6151 eecd &= ~E1000_EECD_SK; 6152 E1000_WRITE_REG(hw, EECD, eecd); 6153 E1000_WRITE_FLUSH(hw); 6154 usec_delay(hw->eeprom.delay_usec); 6155 } 6156 /* Stop requesting EEPROM access */ 6157 if (hw->mac_type > em_82544) { 6158 eecd &= ~E1000_EECD_REQ; 6159 E1000_WRITE_REG(hw, EECD, eecd); 6160 } 6161 em_swfw_sync_release(hw, E1000_SWFW_EEP_SM); 6162 } 6163 6164 /****************************************************************************** 6165 * Reads a 16 bit word from the EEPROM. 6166 * 6167 * hw - Struct containing variables accessed by shared code 6168 *****************************************************************************/ 6169 STATIC int32_t 6170 em_spi_eeprom_ready(struct em_hw *hw) 6171 { 6172 uint16_t retry_count = 0; 6173 uint8_t spi_stat_reg; 6174 DEBUGFUNC("em_spi_eeprom_ready"); 6175 /* 6176 * Read "Status Register" repeatedly until the LSB is cleared. The 6177 * EEPROM will signal that the command has been completed by clearing 6178 * bit 0 of the internal status register. If it's not cleared within 6179 * 5 milliseconds, then error out. 6180 */ 6181 retry_count = 0; 6182 do { 6183 em_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI, 6184 hw->eeprom.opcode_bits); 6185 spi_stat_reg = (uint8_t) em_shift_in_ee_bits(hw, 8); 6186 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI)) 6187 break; 6188 6189 usec_delay(5); 6190 retry_count += 5; 6191 6192 em_standby_eeprom(hw); 6193 } while (retry_count < EEPROM_MAX_RETRY_SPI); 6194 /* 6195 * ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and 6196 * only 0-5mSec on 5V devices) 6197 */ 6198 if (retry_count >= EEPROM_MAX_RETRY_SPI) { 6199 DEBUGOUT("SPI EEPROM Status error\n"); 6200 return -E1000_ERR_EEPROM; 6201 } 6202 return E1000_SUCCESS; 6203 } 6204 6205 /****************************************************************************** 6206 * Reads a 16 bit word from the EEPROM. 6207 * 6208 * hw - Struct containing variables accessed by shared code 6209 * offset - offset of word in the EEPROM to read 6210 * data - word read from the EEPROM 6211 * words - number of words to read 6212 *****************************************************************************/ 6213 int32_t 6214 em_read_eeprom(struct em_hw *hw, uint16_t offset, uint16_t words, 6215 uint16_t *data) 6216 { 6217 struct em_eeprom_info *eeprom = &hw->eeprom; 6218 uint32_t i = 0; 6219 DEBUGFUNC("em_read_eeprom"); 6220 6221 /* If eeprom is not yet detected, do so now */ 6222 if (eeprom->word_size == 0) 6223 em_init_eeprom_params(hw); 6224 /* 6225 * A check for invalid values: offset too large, too many words, and 6226 * not enough words. 6227 */ 6228 if ((offset >= eeprom->word_size) || 6229 (words > eeprom->word_size - offset) || 6230 (words == 0)) { 6231 DEBUGOUT2("\"words\" parameter out of bounds. Words = %d," 6232 " size = %d\n", offset, eeprom->word_size); 6233 return -E1000_ERR_EEPROM; 6234 } 6235 /* 6236 * EEPROM's that don't use EERD to read require us to bit-bang the 6237 * SPI directly. In this case, we need to acquire the EEPROM so that 6238 * FW or other port software does not interrupt. 6239 */ 6240 if (em_is_onboard_nvm_eeprom(hw) == TRUE && 6241 em_get_flash_presence_i210(hw) == TRUE && 6242 hw->eeprom.use_eerd == FALSE) { 6243 /* Prepare the EEPROM for bit-bang reading */ 6244 if (em_acquire_eeprom(hw) != E1000_SUCCESS) 6245 return -E1000_ERR_EEPROM; 6246 } 6247 /* Eerd register EEPROM access requires no eeprom aquire/release */ 6248 if (eeprom->use_eerd == TRUE) 6249 return em_read_eeprom_eerd(hw, offset, words, data); 6250 6251 /* ICH EEPROM access is done via the ICH flash controller */ 6252 if (eeprom->type == em_eeprom_ich8) 6253 return em_read_eeprom_ich8(hw, offset, words, data); 6254 6255 /* Some i210/i211 have a special OTP chip */ 6256 if (eeprom->type == em_eeprom_invm) 6257 return em_read_invm_i210(hw, offset, words, data); 6258 6259 /* 6260 * Set up the SPI or Microwire EEPROM for bit-bang reading. We have 6261 * acquired the EEPROM at this point, so any returns should relase it 6262 */ 6263 if (eeprom->type == em_eeprom_spi) { 6264 uint16_t word_in; 6265 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI; 6266 if (em_spi_eeprom_ready(hw)) { 6267 em_release_eeprom(hw); 6268 return -E1000_ERR_EEPROM; 6269 } 6270 em_standby_eeprom(hw); 6271 /* 6272 * Some SPI eeproms use the 8th address bit embedded in the 6273 * opcode 6274 */ 6275 if ((eeprom->address_bits == 8) && (offset >= 128)) 6276 read_opcode |= EEPROM_A8_OPCODE_SPI; 6277 6278 /* Send the READ command (opcode + addr) */ 6279 em_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits); 6280 em_shift_out_ee_bits(hw, (uint16_t) (offset * 2), 6281 eeprom->address_bits); 6282 /* 6283 * Read the data. The address of the eeprom internally 6284 * increments with each byte (spi) being read, saving on the 6285 * overhead of eeprom setup and tear-down. The address 6286 * counter will roll over if reading beyond the size of the 6287 * eeprom, thus allowing the entire memory to be read 6288 * starting from any offset. 6289 */ 6290 for (i = 0; i < words; i++) { 6291 word_in = em_shift_in_ee_bits(hw, 16); 6292 data[i] = (word_in >> 8) | (word_in << 8); 6293 } 6294 } else if (eeprom->type == em_eeprom_microwire) { 6295 for (i = 0; i < words; i++) { 6296 /* Send the READ command (opcode + addr) */ 6297 em_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE, 6298 eeprom->opcode_bits); 6299 em_shift_out_ee_bits(hw, (uint16_t) (offset + i), 6300 eeprom->address_bits); 6301 /* 6302 * Read the data. For microwire, each word requires 6303 * the overhead of eeprom setup and tear-down. 6304 */ 6305 data[i] = em_shift_in_ee_bits(hw, 16); 6306 em_standby_eeprom(hw); 6307 } 6308 } 6309 /* End this read operation */ 6310 em_release_eeprom(hw); 6311 6312 return E1000_SUCCESS; 6313 } 6314 6315 /****************************************************************************** 6316 * Reads a 16 bit word from the EEPROM using the EERD register. 6317 * 6318 * hw - Struct containing variables accessed by shared code 6319 * offset - offset of word in the EEPROM to read 6320 * data - word read from the EEPROM 6321 * words - number of words to read 6322 *****************************************************************************/ 6323 STATIC int32_t 6324 em_read_eeprom_eerd(struct em_hw *hw, uint16_t offset, uint16_t words, 6325 uint16_t *data) 6326 { 6327 uint32_t i, eerd = 0; 6328 int32_t error = 0; 6329 for (i = 0; i < words; i++) { 6330 eerd = ((offset + i) << E1000_EEPROM_RW_ADDR_SHIFT) + 6331 E1000_EEPROM_RW_REG_START; 6332 6333 E1000_WRITE_REG(hw, EERD, eerd); 6334 error = em_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ); 6335 6336 if (error) { 6337 break; 6338 } 6339 data[i] = (E1000_READ_REG(hw, EERD) >> 6340 E1000_EEPROM_RW_REG_DATA); 6341 6342 } 6343 6344 return error; 6345 } 6346 6347 /****************************************************************************** 6348 * Writes a 16 bit word from the EEPROM using the EEWR register. 6349 * 6350 * hw - Struct containing variables accessed by shared code 6351 * offset - offset of word in the EEPROM to read 6352 * data - word read from the EEPROM 6353 * words - number of words to read 6354 *****************************************************************************/ 6355 STATIC int32_t 6356 em_write_eeprom_eewr(struct em_hw *hw, uint16_t offset, uint16_t words, 6357 uint16_t *data) 6358 { 6359 uint32_t register_value = 0; 6360 uint32_t i = 0; 6361 int32_t error = 0; 6362 if (em_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM)) 6363 return -E1000_ERR_SWFW_SYNC; 6364 6365 for (i = 0; i < words; i++) { 6366 register_value = (data[i] << E1000_EEPROM_RW_REG_DATA) | 6367 ((offset + i) << E1000_EEPROM_RW_ADDR_SHIFT) | 6368 E1000_EEPROM_RW_REG_START; 6369 6370 error = em_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE); 6371 if (error) { 6372 break; 6373 } 6374 E1000_WRITE_REG(hw, EEWR, register_value); 6375 6376 error = em_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE); 6377 6378 if (error) { 6379 break; 6380 } 6381 } 6382 6383 em_swfw_sync_release(hw, E1000_SWFW_EEP_SM); 6384 return error; 6385 } 6386 6387 /****************************************************************************** 6388 * Polls the status bit (bit 1) of the EERD to determine when the read is done. 6389 * 6390 * hw - Struct containing variables accessed by shared code 6391 *****************************************************************************/ 6392 STATIC int32_t 6393 em_poll_eerd_eewr_done(struct em_hw *hw, int eerd) 6394 { 6395 uint32_t attempts = 100000; 6396 uint32_t i, reg = 0; 6397 int32_t done = E1000_ERR_EEPROM; 6398 for (i = 0; i < attempts; i++) { 6399 if (eerd == E1000_EEPROM_POLL_READ) 6400 reg = E1000_READ_REG(hw, EERD); 6401 else 6402 reg = E1000_READ_REG(hw, EEWR); 6403 6404 if (reg & E1000_EEPROM_RW_REG_DONE) { 6405 done = E1000_SUCCESS; 6406 break; 6407 } 6408 usec_delay(5); 6409 } 6410 6411 return done; 6412 } 6413 6414 /****************************************************************************** 6415 * Description: Determines if the onboard NVM is FLASH or EEPROM. 6416 * 6417 * hw - Struct containing variables accessed by shared code 6418 *****************************************************************************/ 6419 STATIC boolean_t 6420 em_is_onboard_nvm_eeprom(struct em_hw *hw) 6421 { 6422 uint32_t eecd = 0; 6423 DEBUGFUNC("em_is_onboard_nvm_eeprom"); 6424 6425 if (IS_ICH8(hw->mac_type)) 6426 return FALSE; 6427 6428 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) { 6429 eecd = E1000_READ_REG(hw, EECD); 6430 6431 /* Isolate bits 15 & 16 */ 6432 eecd = ((eecd >> 15) & 0x03); 6433 6434 /* If both bits are set, device is Flash type */ 6435 if (eecd == 0x03) { 6436 return FALSE; 6437 } 6438 } 6439 return TRUE; 6440 } 6441 6442 /****************************************************************************** 6443 * Check if flash device is detected. 6444 * 6445 * hw - Struct containing variables accessed by shared code 6446 *****************************************************************************/ 6447 boolean_t 6448 em_get_flash_presence_i210(struct em_hw *hw) 6449 { 6450 uint32_t eecd; 6451 DEBUGFUNC("em_get_flash_presence_i210"); 6452 6453 if (hw->mac_type != em_i210) 6454 return TRUE; 6455 6456 eecd = E1000_READ_REG(hw, EECD); 6457 6458 if (eecd & E1000_EECD_FLUPD) 6459 return TRUE; 6460 6461 return FALSE; 6462 } 6463 6464 /****************************************************************************** 6465 * Verifies that the EEPROM has a valid checksum 6466 * 6467 * hw - Struct containing variables accessed by shared code 6468 * 6469 * Reads the first 64 16 bit words of the EEPROM and sums the values read. 6470 * If the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is 6471 * valid. 6472 *****************************************************************************/ 6473 int32_t 6474 em_validate_eeprom_checksum(struct em_hw *hw) 6475 { 6476 uint16_t checksum = 0; 6477 uint16_t i, eeprom_data; 6478 uint16_t checksum_reg; 6479 DEBUGFUNC("em_validate_eeprom_checksum"); 6480 6481 checksum_reg = hw->mac_type != em_icp_xxxx ? 6482 EEPROM_CHECKSUM_REG : 6483 EEPROM_CHECKSUM_REG_ICP_xxxx; 6484 6485 if (((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) && 6486 (em_is_onboard_nvm_eeprom(hw) == FALSE)) { 6487 /* 6488 * Check bit 4 of word 10h. If it is 0, firmware is done 6489 * updating 10h-12h. Checksum may need to be fixed. 6490 */ 6491 em_read_eeprom(hw, 0x10, 1, &eeprom_data); 6492 if ((eeprom_data & 0x10) == 0) { 6493 /* 6494 * Read 0x23 and check bit 15. This bit is a 1 when 6495 * the checksum has already been fixed. If the 6496 * checksum is still wrong and this bit is a 1, we 6497 * need to return bad checksum. Otherwise, we need 6498 * to set this bit to a 1 and update the checksum. 6499 */ 6500 em_read_eeprom(hw, 0x23, 1, &eeprom_data); 6501 if ((eeprom_data & 0x8000) == 0) { 6502 eeprom_data |= 0x8000; 6503 em_write_eeprom(hw, 0x23, 1, &eeprom_data); 6504 em_update_eeprom_checksum(hw); 6505 } 6506 } 6507 } 6508 if (IS_ICH8(hw->mac_type)) { 6509 uint16_t word; 6510 uint16_t valid_csum_mask; 6511 6512 /* 6513 * Drivers must allocate the shadow ram structure for the 6514 * EEPROM checksum to be updated. Otherwise, this bit as 6515 * well as the checksum must both be set correctly for this 6516 * validation to pass. 6517 */ 6518 switch (hw->mac_type) { 6519 case em_pch_lpt: 6520 case em_pch_spt: 6521 word = EEPROM_COMPAT; 6522 valid_csum_mask = EEPROM_COMPAT_VALID_CSUM; 6523 break; 6524 default: 6525 word = EEPROM_FUTURE_INIT_WORD1; 6526 valid_csum_mask = EEPROM_FUTURE_INIT_WORD1_VALID_CSUM; 6527 break; 6528 } 6529 em_read_eeprom(hw, word, 1, &eeprom_data); 6530 if ((eeprom_data & valid_csum_mask) == 0) { 6531 eeprom_data |= valid_csum_mask; 6532 em_write_eeprom(hw, word, 1, &eeprom_data); 6533 em_update_eeprom_checksum(hw); 6534 } 6535 } 6536 for (i = 0; i < (checksum_reg + 1); i++) { 6537 if (em_read_eeprom(hw, i, 1, &eeprom_data) < 0) { 6538 DEBUGOUT("EEPROM Read Error\n"); 6539 return -E1000_ERR_EEPROM; 6540 } 6541 checksum += eeprom_data; 6542 } 6543 6544 if (checksum == (uint16_t) EEPROM_SUM) 6545 return E1000_SUCCESS; 6546 else { 6547 DEBUGOUT("EEPROM Checksum Invalid\n"); 6548 return -E1000_ERR_EEPROM; 6549 } 6550 } 6551 6552 /****************************************************************************** 6553 * Calculates the EEPROM checksum and writes it to the EEPROM 6554 * 6555 * hw - Struct containing variables accessed by shared code 6556 * 6557 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA. 6558 * Writes the difference to word offset 63 of the EEPROM. 6559 *****************************************************************************/ 6560 int32_t 6561 em_update_eeprom_checksum(struct em_hw *hw) 6562 { 6563 uint32_t ctrl_ext; 6564 uint16_t checksum = 0; 6565 uint16_t i, eeprom_data; 6566 DEBUGFUNC("em_update_eeprom_checksum"); 6567 6568 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) { 6569 if (em_read_eeprom(hw, i, 1, &eeprom_data) < 0) { 6570 DEBUGOUT("EEPROM Read Error\n"); 6571 return -E1000_ERR_EEPROM; 6572 } 6573 checksum += eeprom_data; 6574 } 6575 checksum = (uint16_t) EEPROM_SUM - checksum; 6576 if (em_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) { 6577 DEBUGOUT("EEPROM Write Error\n"); 6578 return -E1000_ERR_EEPROM; 6579 } else if (hw->eeprom.type == em_eeprom_flash) { 6580 em_commit_shadow_ram(hw); 6581 } else if (hw->eeprom.type == em_eeprom_ich8) { 6582 em_commit_shadow_ram(hw); 6583 /* 6584 * Reload the EEPROM, or else modifications will not appear 6585 * until after next adapter reset. 6586 */ 6587 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 6588 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 6589 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 6590 msec_delay(10); 6591 } 6592 return E1000_SUCCESS; 6593 } 6594 6595 /****************************************************************************** 6596 * Parent function for writing words to the different EEPROM types. 6597 * 6598 * hw - Struct containing variables accessed by shared code 6599 * offset - offset within the EEPROM to be written to 6600 * words - number of words to write 6601 * data - 16 bit word to be written to the EEPROM 6602 * 6603 * If em_update_eeprom_checksum is not called after this function, the 6604 * EEPROM will most likely contain an invalid checksum. 6605 *****************************************************************************/ 6606 int32_t 6607 em_write_eeprom(struct em_hw *hw, uint16_t offset, uint16_t words, 6608 uint16_t *data) 6609 { 6610 struct em_eeprom_info *eeprom = &hw->eeprom; 6611 int32_t status = 0; 6612 DEBUGFUNC("em_write_eeprom"); 6613 6614 /* If eeprom is not yet detected, do so now */ 6615 if (eeprom->word_size == 0) 6616 em_init_eeprom_params(hw); 6617 /* 6618 * A check for invalid values: offset too large, too many words, and 6619 * not enough words. 6620 */ 6621 if ((offset >= eeprom->word_size) || 6622 (words > eeprom->word_size - offset) || 6623 (words == 0)) { 6624 DEBUGOUT("\"words\" parameter out of bounds\n"); 6625 return -E1000_ERR_EEPROM; 6626 } 6627 /* 82573/4 writes only through eewr */ 6628 if (eeprom->use_eewr == TRUE) 6629 return em_write_eeprom_eewr(hw, offset, words, data); 6630 6631 if (eeprom->type == em_eeprom_ich8) 6632 return em_write_eeprom_ich8(hw, offset, words, data); 6633 6634 /* Prepare the EEPROM for writing */ 6635 if (em_acquire_eeprom(hw) != E1000_SUCCESS) 6636 return -E1000_ERR_EEPROM; 6637 6638 if (eeprom->type == em_eeprom_microwire) { 6639 status = em_write_eeprom_microwire(hw, offset, words, data); 6640 } else { 6641 status = em_write_eeprom_spi(hw, offset, words, data); 6642 msec_delay(10); 6643 } 6644 6645 /* Done with writing */ 6646 em_release_eeprom(hw); 6647 6648 return status; 6649 } 6650 6651 /****************************************************************************** 6652 * Writes a 16 bit word to a given offset in an SPI EEPROM. 6653 * 6654 * hw - Struct containing variables accessed by shared code 6655 * offset - offset within the EEPROM to be written to 6656 * words - number of words to write 6657 * data - pointer to array of 8 bit words to be written to the EEPROM 6658 * 6659 *****************************************************************************/ 6660 STATIC int32_t 6661 em_write_eeprom_spi(struct em_hw *hw, uint16_t offset, uint16_t words, 6662 uint16_t *data) 6663 { 6664 struct em_eeprom_info *eeprom = &hw->eeprom; 6665 uint16_t widx = 0; 6666 DEBUGFUNC("em_write_eeprom_spi"); 6667 6668 while (widx < words) { 6669 uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI; 6670 if (em_spi_eeprom_ready(hw)) 6671 return -E1000_ERR_EEPROM; 6672 6673 em_standby_eeprom(hw); 6674 6675 /* Send the WRITE ENABLE command (8 bit opcode ) */ 6676 em_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI, 6677 eeprom->opcode_bits); 6678 6679 em_standby_eeprom(hw); 6680 /* 6681 * Some SPI eeproms use the 8th address bit embedded in the 6682 * opcode 6683 */ 6684 if ((eeprom->address_bits == 8) && (offset >= 128)) 6685 write_opcode |= EEPROM_A8_OPCODE_SPI; 6686 6687 /* Send the Write command (8-bit opcode + addr) */ 6688 em_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits); 6689 6690 em_shift_out_ee_bits(hw, (uint16_t) ((offset + widx) * 2), 6691 eeprom->address_bits); 6692 6693 /* Send the data */ 6694 /* 6695 * Loop to allow for up to whole page write (32 bytes) of 6696 * eeprom 6697 */ 6698 while (widx < words) { 6699 uint16_t word_out = data[widx]; 6700 word_out = (word_out >> 8) | (word_out << 8); 6701 em_shift_out_ee_bits(hw, word_out, 16); 6702 widx++; 6703 /* 6704 * Some larger eeprom sizes are capable of a 32-byte 6705 * PAGE WRITE operation, while the smaller eeproms 6706 * are capable of an 8-byte PAGE WRITE operation. 6707 * Break the inner loop to pass new address 6708 */ 6709 if ((((offset + widx) * 2) % eeprom->page_size) == 0) { 6710 em_standby_eeprom(hw); 6711 break; 6712 } 6713 } 6714 } 6715 6716 return E1000_SUCCESS; 6717 } 6718 6719 /****************************************************************************** 6720 * Writes a 16 bit word to a given offset in a Microwire EEPROM. 6721 * 6722 * hw - Struct containing variables accessed by shared code 6723 * offset - offset within the EEPROM to be written to 6724 * words - number of words to write 6725 * data - pointer to array of 16 bit words to be written to the EEPROM 6726 * 6727 *****************************************************************************/ 6728 STATIC int32_t 6729 em_write_eeprom_microwire(struct em_hw *hw, uint16_t offset, uint16_t words, 6730 uint16_t *data) 6731 { 6732 struct em_eeprom_info *eeprom = &hw->eeprom; 6733 uint32_t eecd; 6734 uint16_t words_written = 0; 6735 uint16_t i = 0; 6736 DEBUGFUNC("em_write_eeprom_microwire"); 6737 /* 6738 * Send the write enable command to the EEPROM (3-bit opcode plus 6739 * 6/8-bit dummy address beginning with 11). It's less work to 6740 * include the 11 of the dummy address as part of the opcode than it 6741 * is to shift it over the correct number of bits for the address. 6742 * This puts the EEPROM into write/erase mode. 6743 */ 6744 em_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE, 6745 (uint16_t) (eeprom->opcode_bits + 2)); 6746 6747 em_shift_out_ee_bits(hw, 0, (uint16_t) (eeprom->address_bits - 2)); 6748 6749 /* Prepare the EEPROM */ 6750 em_standby_eeprom(hw); 6751 6752 while (words_written < words) { 6753 /* Send the Write command (3-bit opcode + addr) */ 6754 em_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE, 6755 eeprom->opcode_bits); 6756 6757 em_shift_out_ee_bits(hw, (uint16_t) (offset + words_written), 6758 eeprom->address_bits); 6759 6760 /* Send the data */ 6761 em_shift_out_ee_bits(hw, data[words_written], 16); 6762 /* 6763 * Toggle the CS line. This in effect tells the EEPROM to 6764 * execute the previous command. 6765 */ 6766 em_standby_eeprom(hw); 6767 /* 6768 * Read DO repeatedly until it is high (equal to '1'). The 6769 * EEPROM will signal that the command has been completed by 6770 * raising the DO signal. If DO does not go high in 10 6771 * milliseconds, then error out. 6772 */ 6773 for (i = 0; i < 200; i++) { 6774 eecd = E1000_READ_REG(hw, EECD); 6775 if (eecd & E1000_EECD_DO) 6776 break; 6777 usec_delay(50); 6778 } 6779 if (i == 200) { 6780 DEBUGOUT("EEPROM Write did not complete\n"); 6781 return -E1000_ERR_EEPROM; 6782 } 6783 /* Recover from write */ 6784 em_standby_eeprom(hw); 6785 6786 words_written++; 6787 } 6788 /* 6789 * Send the write disable command to the EEPROM (3-bit opcode plus 6790 * 6/8-bit dummy address beginning with 10). It's less work to 6791 * include the 10 of the dummy address as part of the opcode than it 6792 * is to shift it over the correct number of bits for the address. 6793 * This takes the EEPROM out of write/erase mode. 6794 */ 6795 em_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE, 6796 (uint16_t) (eeprom->opcode_bits + 2)); 6797 6798 em_shift_out_ee_bits(hw, 0, (uint16_t) (eeprom->address_bits - 2)); 6799 6800 return E1000_SUCCESS; 6801 } 6802 6803 /****************************************************************************** 6804 * Flushes the cached eeprom to NVM. This is done by saving the modified values 6805 * in the eeprom cache and the non modified values in the currently active bank 6806 * to the new bank. 6807 * 6808 * hw - Struct containing variables accessed by shared code 6809 * offset - offset of word in the EEPROM to read 6810 * data - word read from the EEPROM 6811 * words - number of words to read 6812 *****************************************************************************/ 6813 STATIC int32_t 6814 em_commit_shadow_ram(struct em_hw *hw) 6815 { 6816 uint32_t attempts = 100000; 6817 uint32_t eecd = 0; 6818 uint32_t flop = 0; 6819 uint32_t i = 0; 6820 int32_t error = E1000_SUCCESS; 6821 uint32_t old_bank_offset = 0; 6822 uint32_t new_bank_offset = 0; 6823 uint8_t low_byte = 0; 6824 uint8_t high_byte = 0; 6825 boolean_t sector_write_failed = FALSE; 6826 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) { 6827 /* 6828 * The flop register will be used to determine if flash type 6829 * is STM 6830 */ 6831 flop = E1000_READ_REG(hw, FLOP); 6832 for (i = 0; i < attempts; i++) { 6833 eecd = E1000_READ_REG(hw, EECD); 6834 if ((eecd & E1000_EECD_FLUPD) == 0) { 6835 break; 6836 } 6837 usec_delay(5); 6838 } 6839 6840 if (i == attempts) { 6841 return -E1000_ERR_EEPROM; 6842 } 6843 /* 6844 * If STM opcode located in bits 15:8 of flop, reset firmware 6845 */ 6846 if ((flop & 0xFF00) == E1000_STM_OPCODE) { 6847 E1000_WRITE_REG(hw, HICR, E1000_HICR_FW_RESET); 6848 } 6849 /* Perform the flash update */ 6850 E1000_WRITE_REG(hw, EECD, eecd | E1000_EECD_FLUPD); 6851 6852 for (i = 0; i < attempts; i++) { 6853 eecd = E1000_READ_REG(hw, EECD); 6854 if ((eecd & E1000_EECD_FLUPD) == 0) { 6855 break; 6856 } 6857 usec_delay(5); 6858 } 6859 6860 if (i == attempts) { 6861 return -E1000_ERR_EEPROM; 6862 } 6863 } 6864 if ((hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) && 6865 hw->eeprom_shadow_ram != NULL) { 6866 /* 6867 * We're writing to the opposite bank so if we're on bank 1, 6868 * write to bank 0 etc. We also need to erase the segment 6869 * that is going to be written 6870 */ 6871 if (!(E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL)) { 6872 new_bank_offset = hw->flash_bank_size * 2; 6873 old_bank_offset = 0; 6874 em_erase_ich8_4k_segment(hw, 1); 6875 } else { 6876 old_bank_offset = hw->flash_bank_size * 2; 6877 new_bank_offset = 0; 6878 em_erase_ich8_4k_segment(hw, 0); 6879 } 6880 6881 sector_write_failed = FALSE; 6882 /* 6883 * Loop for every byte in the shadow RAM, which is in units 6884 * of words. 6885 */ 6886 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 6887 /* 6888 * Determine whether to write the value stored in the 6889 * other NVM bank or a modified value stored in the 6890 * shadow RAM 6891 */ 6892 if (hw->eeprom_shadow_ram[i].modified == TRUE) { 6893 low_byte = (uint8_t) 6894 hw->eeprom_shadow_ram[i].eeprom_word; 6895 usec_delay(100); 6896 error = em_verify_write_ich8_byte(hw, 6897 (i << 1) + new_bank_offset, low_byte); 6898 6899 if (error != E1000_SUCCESS) 6900 sector_write_failed = TRUE; 6901 else { 6902 high_byte = (uint8_t) 6903 (hw->eeprom_shadow_ram 6904 [i].eeprom_word >> 8); 6905 usec_delay(100); 6906 } 6907 } else { 6908 em_read_ich8_byte(hw, (i << 1) + 6909 old_bank_offset, &low_byte); 6910 usec_delay(100); 6911 error = em_verify_write_ich8_byte(hw, 6912 (i << 1) + new_bank_offset, low_byte); 6913 6914 if (error != E1000_SUCCESS) 6915 sector_write_failed = TRUE; 6916 else { 6917 em_read_ich8_byte(hw, (i << 1) + 6918 old_bank_offset + 1, &high_byte); 6919 usec_delay(100); 6920 } 6921 } 6922 /* 6923 * If the write of the low byte was successful, go 6924 * ahread and write the high byte while checking to 6925 * make sure that if it is the signature byte, then 6926 * it is handled properly 6927 */ 6928 if (sector_write_failed == FALSE) { 6929 /* 6930 * If the word is 0x13, then make sure the 6931 * signature bits (15:14) are 11b until the 6932 * commit has completed. This will allow us 6933 * to write 10b which indicates the signature 6934 * is valid. We want to do this after the 6935 * write has completed so that we don't mark 6936 * the segment valid while the write is still 6937 * in progress 6938 */ 6939 if (i == E1000_ICH_NVM_SIG_WORD) 6940 high_byte = E1000_ICH_NVM_VALID_SIG_MASK | 6941 high_byte; 6942 6943 error = em_verify_write_ich8_byte(hw, (i << 1) 6944 + new_bank_offset + 1, high_byte); 6945 if (error != E1000_SUCCESS) 6946 sector_write_failed = TRUE; 6947 6948 } else { 6949 /* 6950 * If the write failed then break from the 6951 * loop and return an error 6952 */ 6953 break; 6954 } 6955 } 6956 /* 6957 * Don't bother writing the segment valid bits if sector 6958 * programming failed. 6959 */ 6960 if (sector_write_failed == FALSE) { 6961 /* 6962 * Finally validate the new segment by setting bit 6963 * 15:14 to 10b in word 0x13 , this can be done 6964 * without an erase as well since these bits are 11 6965 * to start with and we need to change bit 14 to 0b 6966 */ 6967 em_read_ich8_byte(hw, E1000_ICH_NVM_SIG_WORD * 2 + 1 + 6968 new_bank_offset, &high_byte); 6969 high_byte &= 0xBF; 6970 error = em_verify_write_ich8_byte(hw, 6971 E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset, 6972 high_byte); 6973 /* 6974 * And invalidate the previously valid segment by 6975 * setting its signature word (0x13) high_byte to 0b. 6976 * This can be done without an erase because flash 6977 * erase sets all bits to 1's. We can write 1's to 6978 * 0's without an erase 6979 */ 6980 if (error == E1000_SUCCESS) { 6981 error = em_verify_write_ich8_byte(hw, 6982 E1000_ICH_NVM_SIG_WORD * 2 + 1 + 6983 old_bank_offset, 0); 6984 } 6985 /* Clear the now not used entry in the cache */ 6986 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 6987 hw->eeprom_shadow_ram[i].modified = FALSE; 6988 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF; 6989 } 6990 } 6991 } 6992 return error; 6993 } 6994 6995 /****************************************************************************** 6996 * Reads the adapter's part number from the EEPROM 6997 * 6998 * hw - Struct containing variables accessed by shared code 6999 * part_num - Adapter's part number 7000 *****************************************************************************/ 7001 int32_t 7002 em_read_part_num(struct em_hw *hw, uint32_t *part_num) 7003 { 7004 uint16_t offset = EEPROM_PBA_BYTE_1; 7005 uint16_t eeprom_data; 7006 DEBUGFUNC("em_read_part_num"); 7007 7008 /* Get word 0 from EEPROM */ 7009 if (em_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { 7010 DEBUGOUT("EEPROM Read Error\n"); 7011 return -E1000_ERR_EEPROM; 7012 } 7013 /* Save word 0 in upper half of part_num */ 7014 *part_num = (uint32_t) (eeprom_data << 16); 7015 7016 /* Get word 1 from EEPROM */ 7017 if (em_read_eeprom(hw, ++offset, 1, &eeprom_data) < 0) { 7018 DEBUGOUT("EEPROM Read Error\n"); 7019 return -E1000_ERR_EEPROM; 7020 } 7021 /* Save word 1 in lower half of part_num */ 7022 *part_num |= eeprom_data; 7023 7024 return E1000_SUCCESS; 7025 } 7026 7027 /****************************************************************************** 7028 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the 7029 * second function of dual function devices 7030 * 7031 * hw - Struct containing variables accessed by shared code 7032 *****************************************************************************/ 7033 int32_t 7034 em_read_mac_addr(struct em_hw *hw) 7035 { 7036 uint16_t offset; 7037 uint16_t eeprom_data, i; 7038 uint16_t ia_base_addr = 0; 7039 DEBUGFUNC("em_read_mac_addr"); 7040 7041 if (hw->mac_type == em_icp_xxxx) { 7042 ia_base_addr = (uint16_t) 7043 EEPROM_IA_START_ICP_xxxx(hw->icp_xxxx_port_num); 7044 } else if (hw->mac_type == em_82580 || hw->mac_type == em_i350) { 7045 ia_base_addr = NVM_82580_LAN_FUNC_OFFSET(hw->bus_func); 7046 } 7047 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) { 7048 offset = i >> 1; 7049 if (em_read_eeprom(hw, offset + ia_base_addr, 1, &eeprom_data) 7050 < 0) { 7051 DEBUGOUT("EEPROM Read Error\n"); 7052 return -E1000_ERR_EEPROM; 7053 } 7054 hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF); 7055 hw->perm_mac_addr[i + 1] = (uint8_t) (eeprom_data >> 8); 7056 } 7057 7058 switch (hw->mac_type) { 7059 default: 7060 break; 7061 case em_82546: 7062 case em_82546_rev_3: 7063 case em_82571: 7064 case em_82575: 7065 case em_80003es2lan: 7066 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) 7067 hw->perm_mac_addr[5] ^= 0x01; 7068 break; 7069 } 7070 7071 for (i = 0; i < NODE_ADDRESS_SIZE; i++) 7072 hw->mac_addr[i] = hw->perm_mac_addr[i]; 7073 return E1000_SUCCESS; 7074 } 7075 7076 /****************************************************************************** 7077 * Explicitly disables jumbo frames and resets some PHY registers back to hw- 7078 * defaults. This is necessary in case the ethernet cable was inserted AFTER 7079 * the firmware initialized the PHY. Otherwise it is left in a state where 7080 * it is possible to transmit but not receive packets. Observed on I217-LM and 7081 * fixed in FreeBSD's sys/dev/e1000/e1000_ich8lan.c. 7082 * 7083 * hw - Struct containing variables accessed by shared code 7084 *****************************************************************************/ 7085 STATIC int32_t 7086 em_phy_no_cable_workaround(struct em_hw *hw) { 7087 int32_t ret_val, dft_ret_val; 7088 uint32_t mac_reg; 7089 uint16_t data, phy_reg; 7090 7091 /* disable Rx path while enabling workaround */ 7092 em_read_phy_reg(hw, I2_DFT_CTRL, &phy_reg); 7093 ret_val = em_write_phy_reg(hw, I2_DFT_CTRL, phy_reg | (1 << 14)); 7094 if (ret_val) 7095 return ret_val; 7096 7097 /* Write MAC register values back to h/w defaults */ 7098 mac_reg = E1000_READ_REG(hw, FFLT_DBG); 7099 mac_reg &= ~(0xF << 14); 7100 E1000_WRITE_REG(hw, FFLT_DBG, mac_reg); 7101 7102 mac_reg = E1000_READ_REG(hw, RCTL); 7103 mac_reg &= ~E1000_RCTL_SECRC; 7104 E1000_WRITE_REG(hw, RCTL, mac_reg); 7105 7106 ret_val = em_read_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_CTRL, &data); 7107 if (ret_val) 7108 goto out; 7109 ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_CTRL, 7110 data & ~(1 << 0)); 7111 if (ret_val) 7112 goto out; 7113 7114 ret_val = em_read_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL, &data); 7115 if (ret_val) 7116 goto out; 7117 7118 data &= ~(0xF << 8); 7119 data |= (0xB << 8); 7120 ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL, data); 7121 if (ret_val) 7122 goto out; 7123 7124 /* Write PHY register values back to h/w defaults */ 7125 em_read_phy_reg(hw, I2_SMBUS_CTRL, &data); 7126 data &= ~(0x7F << 5); 7127 ret_val = em_write_phy_reg(hw, I2_SMBUS_CTRL, data); 7128 if (ret_val) 7129 goto out; 7130 7131 em_read_phy_reg(hw, I2_MODE_CTRL, &data); 7132 data |= (1 << 13); 7133 ret_val = em_write_phy_reg(hw, I2_MODE_CTRL, data); 7134 if (ret_val) 7135 goto out; 7136 7137 /* 7138 * 776.20 and 776.23 are not documented in 7139 * i217-ethernet-controller-datasheet.pdf... 7140 */ 7141 em_read_phy_reg(hw, PHY_REG(776, 20), &data); 7142 data &= ~(0x3FF << 2); 7143 data |= (0x8 << 2); 7144 ret_val = em_write_phy_reg(hw, PHY_REG(776, 20), data); 7145 if (ret_val) 7146 goto out; 7147 7148 ret_val = em_write_phy_reg(hw, PHY_REG(776, 23), 0x7E00); 7149 if (ret_val) 7150 goto out; 7151 7152 em_read_phy_reg(hw, I2_PCIE_POWER_CTRL, &data); 7153 ret_val = em_write_phy_reg(hw, I2_PCIE_POWER_CTRL, data & ~(1 << 10)); 7154 if (ret_val) 7155 goto out; 7156 7157 out: 7158 /* re-enable Rx path after enabling workaround */ 7159 dft_ret_val = em_write_phy_reg(hw, I2_DFT_CTRL, phy_reg & ~(1 << 14)); 7160 if (ret_val) 7161 return ret_val; 7162 else 7163 return dft_ret_val; 7164 } 7165 7166 /****************************************************************************** 7167 * Initializes receive address filters. 7168 * 7169 * hw - Struct containing variables accessed by shared code 7170 * 7171 * Places the MAC address in receive address register 0 and clears the rest 7172 * of the receive addresss registers. Clears the multicast table. Assumes 7173 * the receiver is in reset when the routine is called. 7174 *****************************************************************************/ 7175 STATIC void 7176 em_init_rx_addrs(struct em_hw *hw) 7177 { 7178 uint32_t i; 7179 uint32_t rar_num; 7180 DEBUGFUNC("em_init_rx_addrs"); 7181 7182 if (hw->mac_type == em_pch_lpt || hw->mac_type == em_pch_spt || hw->mac_type == em_pch2lan) 7183 if (em_phy_no_cable_workaround(hw)) 7184 printf(" ...failed to apply em_phy_no_cable_" 7185 "workaround.\n"); 7186 7187 /* Setup the receive address. */ 7188 DEBUGOUT("Programming MAC Address into RAR[0]\n"); 7189 7190 em_rar_set(hw, hw->mac_addr, 0); 7191 7192 rar_num = E1000_RAR_ENTRIES; 7193 /* 7194 * Reserve a spot for the Locally Administered Address to work around 7195 * an 82571 issue in which a reset on one port will reload the MAC on 7196 * the other port. 7197 */ 7198 if ((hw->mac_type == em_82571) && (hw->laa_is_present == TRUE)) 7199 rar_num -= 1; 7200 if (IS_ICH8(hw->mac_type)) 7201 rar_num = E1000_RAR_ENTRIES_ICH8LAN; 7202 if (hw->mac_type == em_ich8lan) 7203 rar_num -= 1; 7204 if (hw->mac_type == em_82580) 7205 rar_num = E1000_RAR_ENTRIES_82580; 7206 if (hw->mac_type == em_i210) 7207 rar_num = E1000_RAR_ENTRIES_82575; 7208 if (hw->mac_type == em_i350) 7209 rar_num = E1000_RAR_ENTRIES_I350; 7210 7211 /* Zero out the other 15 receive addresses. */ 7212 DEBUGOUT("Clearing RAR[1-15]\n"); 7213 for (i = 1; i < rar_num; i++) { 7214 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 7215 E1000_WRITE_FLUSH(hw); 7216 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 7217 E1000_WRITE_FLUSH(hw); 7218 } 7219 } 7220 7221 /****************************************************************************** 7222 * Updates the MAC's list of multicast addresses. 7223 * 7224 * hw - Struct containing variables accessed by shared code 7225 * mc_addr_list - the list of new multicast addresses 7226 * mc_addr_count - number of addresses 7227 * pad - number of bytes between addresses in the list 7228 * rar_used_count - offset where to start adding mc addresses into the RAR's 7229 * 7230 * The given list replaces any existing list. Clears the last 15 receive 7231 * address registers and the multicast table. Uses receive address registers 7232 * for the first 15 multicast addresses, and hashes the rest into the 7233 * multicast table. 7234 *****************************************************************************/ 7235 void 7236 em_mc_addr_list_update(struct em_hw *hw, uint8_t *mc_addr_list, 7237 uint32_t mc_addr_count, uint32_t pad, uint32_t rar_used_count) 7238 { 7239 uint32_t hash_value; 7240 uint32_t i; 7241 uint32_t num_rar_entry; 7242 uint32_t num_mta_entry; 7243 DEBUGFUNC("em_mc_addr_list_update"); 7244 /* 7245 * Set the new number of MC addresses that we are being requested to 7246 * use. 7247 */ 7248 hw->num_mc_addrs = mc_addr_count; 7249 7250 /* Clear RAR[1-15] */ 7251 DEBUGOUT(" Clearing RAR[1-15]\n"); 7252 num_rar_entry = E1000_RAR_ENTRIES; 7253 if (IS_ICH8(hw->mac_type)) 7254 num_rar_entry = E1000_RAR_ENTRIES_ICH8LAN; 7255 if (hw->mac_type == em_ich8lan) 7256 num_rar_entry -= 1; 7257 /* 7258 * Reserve a spot for the Locally Administered Address to work around 7259 * an 82571 issue in which a reset on one port will reload the MAC on 7260 * the other port. 7261 */ 7262 if ((hw->mac_type == em_82571) && (hw->laa_is_present == TRUE)) 7263 num_rar_entry -= 1; 7264 7265 for (i = rar_used_count; i < num_rar_entry; i++) { 7266 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 7267 E1000_WRITE_FLUSH(hw); 7268 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 7269 E1000_WRITE_FLUSH(hw); 7270 } 7271 7272 /* Clear the MTA */ 7273 DEBUGOUT(" Clearing MTA\n"); 7274 num_mta_entry = E1000_NUM_MTA_REGISTERS; 7275 if (IS_ICH8(hw->mac_type)) 7276 num_mta_entry = E1000_NUM_MTA_REGISTERS_ICH8LAN; 7277 7278 for (i = 0; i < num_mta_entry; i++) { 7279 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 7280 E1000_WRITE_FLUSH(hw); 7281 } 7282 7283 /* Add the new addresses */ 7284 for (i = 0; i < mc_addr_count; i++) { 7285 DEBUGOUT(" Adding the multicast addresses:\n"); 7286 DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i, 7287 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad)], 7288 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 1], 7289 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 2], 7290 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 3], 7291 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 4], 7292 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 5]); 7293 7294 hash_value = em_hash_mc_addr(hw, mc_addr_list + 7295 (i * (ETH_LENGTH_OF_ADDRESS + pad))); 7296 7297 DEBUGOUT1(" Hash value = 0x%03X\n", hash_value); 7298 /* 7299 * Place this multicast address in the RAR if there is room, * 7300 * else put it in the MTA 7301 */ 7302 if (rar_used_count < num_rar_entry) { 7303 em_rar_set(hw, mc_addr_list + 7304 (i * (ETH_LENGTH_OF_ADDRESS + pad)), 7305 rar_used_count); 7306 rar_used_count++; 7307 } else { 7308 em_mta_set(hw, hash_value); 7309 } 7310 } 7311 DEBUGOUT("MC Update Complete\n"); 7312 } 7313 7314 /****************************************************************************** 7315 * Hashes an address to determine its location in the multicast table 7316 * 7317 * hw - Struct containing variables accessed by shared code 7318 * mc_addr - the multicast address to hash 7319 *****************************************************************************/ 7320 uint32_t 7321 em_hash_mc_addr(struct em_hw *hw, uint8_t *mc_addr) 7322 { 7323 uint32_t hash_value = 0; 7324 /* 7325 * The portion of the address that is used for the hash table is 7326 * determined by the mc_filter_type setting. 7327 */ 7328 switch (hw->mc_filter_type) { 7329 /* 7330 * [0] [1] [2] [3] [4] [5] 01 AA 00 12 34 56 LSB 7331 * MSB 7332 */ 7333 case 0: 7334 if (IS_ICH8(hw->mac_type)) { 7335 /* [47:38] i.e. 0x158 for above example address */ 7336 hash_value = ((mc_addr[4] >> 6) | 7337 (((uint16_t) mc_addr[5]) << 2)); 7338 } else { 7339 /* [47:36] i.e. 0x563 for above example address */ 7340 hash_value = ((mc_addr[4] >> 4) | 7341 (((uint16_t) mc_addr[5]) << 4)); 7342 } 7343 break; 7344 case 1: 7345 if (IS_ICH8(hw->mac_type)) { 7346 /* [46:37] i.e. 0x2B1 for above example address */ 7347 hash_value = ((mc_addr[4] >> 5) | 7348 (((uint16_t) mc_addr[5]) << 3)); 7349 } else { 7350 /* [46:35] i.e. 0xAC6 for above example address */ 7351 hash_value = ((mc_addr[4] >> 3) | 7352 (((uint16_t) mc_addr[5]) << 5)); 7353 } 7354 break; 7355 case 2: 7356 if (IS_ICH8(hw->mac_type)) { 7357 /* [45:36] i.e. 0x163 for above example address */ 7358 hash_value = ((mc_addr[4] >> 4) | 7359 (((uint16_t) mc_addr[5]) << 4)); 7360 } else { 7361 /* [45:34] i.e. 0x5D8 for above example address */ 7362 hash_value = ((mc_addr[4] >> 2) | 7363 (((uint16_t) mc_addr[5]) << 6)); 7364 } 7365 break; 7366 case 3: 7367 if (IS_ICH8(hw->mac_type)) { 7368 /* [43:34] i.e. 0x18D for above example address */ 7369 hash_value = ((mc_addr[4] >> 2) | 7370 (((uint16_t) mc_addr[5]) << 6)); 7371 } else { 7372 /* [43:32] i.e. 0x634 for above example address */ 7373 hash_value = ((mc_addr[4]) | 7374 (((uint16_t) mc_addr[5]) << 8)); 7375 } 7376 break; 7377 } 7378 7379 hash_value &= 0xFFF; 7380 if (IS_ICH8(hw->mac_type)) 7381 hash_value &= 0x3FF; 7382 7383 return hash_value; 7384 } 7385 7386 /****************************************************************************** 7387 * Sets the bit in the multicast table corresponding to the hash value. 7388 * 7389 * hw - Struct containing variables accessed by shared code 7390 * hash_value - Multicast address hash value 7391 *****************************************************************************/ 7392 void 7393 em_mta_set(struct em_hw *hw, uint32_t hash_value) 7394 { 7395 uint32_t hash_bit, hash_reg; 7396 uint32_t mta; 7397 uint32_t temp; 7398 /* 7399 * The MTA is a register array of 128 32-bit registers. It is treated 7400 * like an array of 4096 bits. We want to set bit 7401 * BitArray[hash_value]. So we figure out what register the bit is 7402 * in, read it, OR in the new bit, then write back the new value. 7403 * The register is determined by the upper 7 bits of the hash value 7404 * and the bit within that register are determined by the lower 5 7405 * bits of the value. 7406 */ 7407 hash_reg = (hash_value >> 5) & 0x7F; 7408 if (IS_ICH8(hw->mac_type)) 7409 hash_reg &= 0x1F; 7410 7411 hash_bit = hash_value & 0x1F; 7412 7413 mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg); 7414 7415 mta |= (1 << hash_bit); 7416 /* 7417 * If we are on an 82544 and we are trying to write an odd offset in 7418 * the MTA, save off the previous entry before writing and restore 7419 * the old value after writing. 7420 */ 7421 if ((hw->mac_type == em_82544) && ((hash_reg & 0x1) == 1)) { 7422 temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1)); 7423 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta); 7424 E1000_WRITE_FLUSH(hw); 7425 E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp); 7426 E1000_WRITE_FLUSH(hw); 7427 } else { 7428 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta); 7429 E1000_WRITE_FLUSH(hw); 7430 } 7431 } 7432 7433 /****************************************************************************** 7434 * Puts an ethernet address into a receive address register. 7435 * 7436 * hw - Struct containing variables accessed by shared code 7437 * addr - Address to put into receive address register 7438 * index - Receive address register to write 7439 *****************************************************************************/ 7440 void 7441 em_rar_set(struct em_hw *hw, uint8_t *addr, uint32_t index) 7442 { 7443 uint32_t rar_low, rar_high; 7444 /* 7445 * HW expects these in little endian so we reverse the byte order 7446 * from network order (big endian) to little endian 7447 */ 7448 rar_low = ((uint32_t) addr[0] | ((uint32_t) addr[1] << 8) | 7449 ((uint32_t) addr[2] << 16) | ((uint32_t) addr[3] << 24)); 7450 rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8)); 7451 /* 7452 * Disable Rx and flush all Rx frames before enabling RSS to avoid Rx 7453 * unit hang. 7454 * 7455 * Description: If there are any Rx frames queued up or otherwise 7456 * present in the HW before RSS is enabled, and then we enable RSS, 7457 * the HW Rx unit will hang. To work around this issue, we have to 7458 * disable receives and flush out all Rx frames before we enable RSS. 7459 * To do so, we modify we redirect all Rx traffic to manageability 7460 * and then reset the HW. This flushes away Rx frames, and (since the 7461 * redirections to manageability persists across resets) keeps new 7462 * ones from coming in while we work. Then, we clear the Address 7463 * Valid AV bit for all MAC addresses and undo the re-direction to 7464 * manageability. Now, frames are coming in again, but the MAC won't 7465 * accept them, so far so good. We now proceed to initialize RSS (if 7466 * necessary) and configure the Rx unit. Last, we re-enable the AV 7467 * bits and continue on our merry way. 7468 */ 7469 switch (hw->mac_type) { 7470 case em_82571: 7471 case em_82572: 7472 case em_80003es2lan: 7473 if (hw->leave_av_bit_off == TRUE) 7474 break; 7475 default: 7476 /* Indicate to hardware the Address is Valid. */ 7477 rar_high |= E1000_RAH_AV; 7478 break; 7479 } 7480 7481 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low); 7482 E1000_WRITE_FLUSH(hw); 7483 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high); 7484 E1000_WRITE_FLUSH(hw); 7485 } 7486 7487 /****************************************************************************** 7488 * Clears the VLAN filer table 7489 * 7490 * hw - Struct containing variables accessed by shared code 7491 *****************************************************************************/ 7492 STATIC void 7493 em_clear_vfta(struct em_hw *hw) 7494 { 7495 uint32_t offset; 7496 uint32_t vfta_value = 0; 7497 uint32_t vfta_offset = 0; 7498 uint32_t vfta_bit_in_reg = 0; 7499 if (IS_ICH8(hw->mac_type)) 7500 return; 7501 7502 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) { 7503 if (hw->mng_cookie.vlan_id != 0) { 7504 /* 7505 * The VFTA is a 4096b bit-field, each identifying a 7506 * single VLAN ID. The following operations 7507 * determine which 32b entry (i.e. offset) into the 7508 * array we want to set the VLAN ID (i.e. bit) of the 7509 * manageability unit. 7510 */ 7511 vfta_offset = (hw->mng_cookie.vlan_id >> 7512 E1000_VFTA_ENTRY_SHIFT) & E1000_VFTA_ENTRY_MASK; 7513 7514 vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id & 7515 E1000_VFTA_ENTRY_BIT_SHIFT_MASK); 7516 } 7517 } 7518 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 7519 /* 7520 * If the offset we want to clear is the same offset of the 7521 * manageability VLAN ID, then clear all bits except that of 7522 * the manageability unit 7523 */ 7524 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; 7525 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value); 7526 E1000_WRITE_FLUSH(hw); 7527 } 7528 } 7529 7530 /* 7531 * Due to hw errata, if the host tries to configure the VFTA register 7532 * while performing queries from the BMC or DMA, then the VFTA in some 7533 * cases won't be written. 7534 */ 7535 void 7536 em_clear_vfta_i350(struct em_hw *hw) 7537 { 7538 uint32_t offset; 7539 int i; 7540 7541 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 7542 for (i = 0; i < 10; i++) 7543 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0); 7544 E1000_WRITE_FLUSH(hw); 7545 } 7546 } 7547 7548 STATIC int32_t 7549 em_id_led_init(struct em_hw *hw) 7550 { 7551 uint32_t ledctl; 7552 const uint32_t ledctl_mask = 0x000000FF; 7553 const uint32_t ledctl_on = E1000_LEDCTL_MODE_LED_ON; 7554 const uint32_t ledctl_off = E1000_LEDCTL_MODE_LED_OFF; 7555 uint16_t eeprom_data, i, temp; 7556 const uint16_t led_mask = 0x0F; 7557 DEBUGFUNC("em_id_led_init"); 7558 7559 if (hw->mac_type < em_82540 || hw->mac_type == em_icp_xxxx) { 7560 /* Nothing to do */ 7561 return E1000_SUCCESS; 7562 } 7563 ledctl = E1000_READ_REG(hw, LEDCTL); 7564 hw->ledctl_default = ledctl; 7565 hw->ledctl_mode1 = hw->ledctl_default; 7566 hw->ledctl_mode2 = hw->ledctl_default; 7567 7568 if (em_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) { 7569 DEBUGOUT("EEPROM Read Error\n"); 7570 return -E1000_ERR_EEPROM; 7571 } 7572 if ((hw->mac_type == em_82573) && 7573 (eeprom_data == ID_LED_RESERVED_82573)) 7574 eeprom_data = ID_LED_DEFAULT_82573; 7575 else if ((eeprom_data == ID_LED_RESERVED_0000) || 7576 (eeprom_data == ID_LED_RESERVED_FFFF)) { 7577 if (hw->mac_type == em_ich8lan || 7578 hw->mac_type == em_ich9lan || 7579 hw->mac_type == em_ich10lan) // XXX 7580 eeprom_data = ID_LED_DEFAULT_ICH8LAN; 7581 else 7582 eeprom_data = ID_LED_DEFAULT; 7583 } 7584 for (i = 0; i < 4; i++) { 7585 temp = (eeprom_data >> (i << 2)) & led_mask; 7586 switch (temp) { 7587 case ID_LED_ON1_DEF2: 7588 case ID_LED_ON1_ON2: 7589 case ID_LED_ON1_OFF2: 7590 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 7591 hw->ledctl_mode1 |= ledctl_on << (i << 3); 7592 break; 7593 case ID_LED_OFF1_DEF2: 7594 case ID_LED_OFF1_ON2: 7595 case ID_LED_OFF1_OFF2: 7596 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 7597 hw->ledctl_mode1 |= ledctl_off << (i << 3); 7598 break; 7599 default: 7600 /* Do nothing */ 7601 break; 7602 } 7603 switch (temp) { 7604 case ID_LED_DEF1_ON2: 7605 case ID_LED_ON1_ON2: 7606 case ID_LED_OFF1_ON2: 7607 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 7608 hw->ledctl_mode2 |= ledctl_on << (i << 3); 7609 break; 7610 case ID_LED_DEF1_OFF2: 7611 case ID_LED_ON1_OFF2: 7612 case ID_LED_OFF1_OFF2: 7613 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 7614 hw->ledctl_mode2 |= ledctl_off << (i << 3); 7615 break; 7616 default: 7617 /* Do nothing */ 7618 break; 7619 } 7620 } 7621 return E1000_SUCCESS; 7622 } 7623 7624 /****************************************************************************** 7625 * Clears all hardware statistics counters. 7626 * 7627 * hw - Struct containing variables accessed by shared code 7628 *****************************************************************************/ 7629 void 7630 em_clear_hw_cntrs(struct em_hw *hw) 7631 { 7632 volatile uint32_t temp; 7633 temp = E1000_READ_REG(hw, CRCERRS); 7634 temp = E1000_READ_REG(hw, SYMERRS); 7635 temp = E1000_READ_REG(hw, MPC); 7636 temp = E1000_READ_REG(hw, SCC); 7637 temp = E1000_READ_REG(hw, ECOL); 7638 temp = E1000_READ_REG(hw, MCC); 7639 temp = E1000_READ_REG(hw, LATECOL); 7640 temp = E1000_READ_REG(hw, COLC); 7641 temp = E1000_READ_REG(hw, DC); 7642 temp = E1000_READ_REG(hw, SEC); 7643 temp = E1000_READ_REG(hw, RLEC); 7644 temp = E1000_READ_REG(hw, XONRXC); 7645 temp = E1000_READ_REG(hw, XONTXC); 7646 temp = E1000_READ_REG(hw, XOFFRXC); 7647 temp = E1000_READ_REG(hw, XOFFTXC); 7648 temp = E1000_READ_REG(hw, FCRUC); 7649 7650 if (!IS_ICH8(hw->mac_type)) { 7651 temp = E1000_READ_REG(hw, PRC64); 7652 temp = E1000_READ_REG(hw, PRC127); 7653 temp = E1000_READ_REG(hw, PRC255); 7654 temp = E1000_READ_REG(hw, PRC511); 7655 temp = E1000_READ_REG(hw, PRC1023); 7656 temp = E1000_READ_REG(hw, PRC1522); 7657 } 7658 temp = E1000_READ_REG(hw, GPRC); 7659 temp = E1000_READ_REG(hw, BPRC); 7660 temp = E1000_READ_REG(hw, MPRC); 7661 temp = E1000_READ_REG(hw, GPTC); 7662 temp = E1000_READ_REG(hw, GORCL); 7663 temp = E1000_READ_REG(hw, GORCH); 7664 temp = E1000_READ_REG(hw, GOTCL); 7665 temp = E1000_READ_REG(hw, GOTCH); 7666 temp = E1000_READ_REG(hw, RNBC); 7667 temp = E1000_READ_REG(hw, RUC); 7668 temp = E1000_READ_REG(hw, RFC); 7669 temp = E1000_READ_REG(hw, ROC); 7670 temp = E1000_READ_REG(hw, RJC); 7671 temp = E1000_READ_REG(hw, TORL); 7672 temp = E1000_READ_REG(hw, TORH); 7673 temp = E1000_READ_REG(hw, TOTL); 7674 temp = E1000_READ_REG(hw, TOTH); 7675 temp = E1000_READ_REG(hw, TPR); 7676 temp = E1000_READ_REG(hw, TPT); 7677 7678 if (!IS_ICH8(hw->mac_type)) { 7679 temp = E1000_READ_REG(hw, PTC64); 7680 temp = E1000_READ_REG(hw, PTC127); 7681 temp = E1000_READ_REG(hw, PTC255); 7682 temp = E1000_READ_REG(hw, PTC511); 7683 temp = E1000_READ_REG(hw, PTC1023); 7684 temp = E1000_READ_REG(hw, PTC1522); 7685 } 7686 temp = E1000_READ_REG(hw, MPTC); 7687 temp = E1000_READ_REG(hw, BPTC); 7688 7689 if (hw->mac_type < em_82543) 7690 return; 7691 7692 temp = E1000_READ_REG(hw, ALGNERRC); 7693 temp = E1000_READ_REG(hw, RXERRC); 7694 temp = E1000_READ_REG(hw, TNCRS); 7695 temp = E1000_READ_REG(hw, CEXTERR); 7696 temp = E1000_READ_REG(hw, TSCTC); 7697 temp = E1000_READ_REG(hw, TSCTFC); 7698 7699 if (hw->mac_type <= em_82544 7700 || hw->mac_type == em_icp_xxxx) 7701 return; 7702 7703 temp = E1000_READ_REG(hw, MGTPRC); 7704 temp = E1000_READ_REG(hw, MGTPDC); 7705 temp = E1000_READ_REG(hw, MGTPTC); 7706 7707 if (hw->mac_type <= em_82547_rev_2) 7708 return; 7709 7710 temp = E1000_READ_REG(hw, IAC); 7711 temp = E1000_READ_REG(hw, ICRXOC); 7712 7713 if (hw->phy_type == em_phy_82577 || 7714 hw->phy_type == em_phy_82578 || 7715 hw->phy_type == em_phy_82579 || 7716 hw->phy_type == em_phy_i217) { 7717 uint16_t phy_data; 7718 7719 em_read_phy_reg(hw, HV_SCC_UPPER, &phy_data); 7720 em_read_phy_reg(hw, HV_SCC_LOWER, &phy_data); 7721 em_read_phy_reg(hw, HV_ECOL_UPPER, &phy_data); 7722 em_read_phy_reg(hw, HV_ECOL_LOWER, &phy_data); 7723 em_read_phy_reg(hw, HV_MCC_UPPER, &phy_data); 7724 em_read_phy_reg(hw, HV_MCC_LOWER, &phy_data); 7725 em_read_phy_reg(hw, HV_LATECOL_UPPER, &phy_data); 7726 em_read_phy_reg(hw, HV_LATECOL_LOWER, &phy_data); 7727 em_read_phy_reg(hw, HV_COLC_UPPER, &phy_data); 7728 em_read_phy_reg(hw, HV_COLC_LOWER, &phy_data); 7729 em_read_phy_reg(hw, HV_DC_UPPER, &phy_data); 7730 em_read_phy_reg(hw, HV_DC_LOWER, &phy_data); 7731 em_read_phy_reg(hw, HV_TNCRS_UPPER, &phy_data); 7732 em_read_phy_reg(hw, HV_TNCRS_LOWER, &phy_data); 7733 } 7734 7735 if (hw->mac_type == em_ich8lan || 7736 hw->mac_type == em_ich9lan || 7737 hw->mac_type == em_ich10lan || 7738 hw->mac_type == em_pchlan || 7739 (hw->mac_type != em_pch2lan && hw->mac_type != em_pch_lpt && hw->mac_type != em_pch_spt)) 7740 return; 7741 7742 temp = E1000_READ_REG(hw, ICRXPTC); 7743 temp = E1000_READ_REG(hw, ICRXATC); 7744 temp = E1000_READ_REG(hw, ICTXPTC); 7745 temp = E1000_READ_REG(hw, ICTXATC); 7746 temp = E1000_READ_REG(hw, ICTXQEC); 7747 temp = E1000_READ_REG(hw, ICTXQMTC); 7748 temp = E1000_READ_REG(hw, ICRXDMTC); 7749 } 7750 7751 #ifndef SMALL_KERNEL 7752 /****************************************************************************** 7753 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT 7754 * 7755 * hw - Struct containing variables accessed by shared code 7756 * frame_len - The length of the frame in question 7757 * mac_addr - The Ethernet destination address of the frame in question 7758 *****************************************************************************/ 7759 void 7760 em_tbi_adjust_stats(struct em_hw *hw, struct em_hw_stats *stats, 7761 uint32_t frame_len, uint8_t *mac_addr) 7762 { 7763 uint64_t carry_bit; 7764 /* First adjust the frame length. */ 7765 frame_len--; 7766 /* 7767 * We need to adjust the statistics counters, since the hardware 7768 * counters overcount this packet as a CRC error and undercount the 7769 * packet as a good packet 7770 */ 7771 /* This packet should not be counted as a CRC error. */ 7772 stats->crcerrs--; 7773 /* This packet does count as a Good Packet Received. */ 7774 stats->gprc++; 7775 7776 /* Adjust the Good Octets received counters */ 7777 carry_bit = 0x80000000 & stats->gorcl; 7778 stats->gorcl += frame_len; 7779 /* 7780 * If the high bit of Gorcl (the low 32 bits of the Good Octets 7781 * Received Count) was one before the addition, AND it is zero after, 7782 * then we lost the carry out, need to add one to Gorch (Good Octets 7783 * Received Count High). This could be simplified if all environments 7784 * supported 64-bit integers. 7785 */ 7786 if (carry_bit && ((stats->gorcl & 0x80000000) == 0)) 7787 stats->gorch++; 7788 /* 7789 * Is this a broadcast or multicast? Check broadcast first, since 7790 * the test for a multicast frame will test positive on a broadcast 7791 * frame. 7792 */ 7793 if ((mac_addr[0] == (uint8_t) 0xff) && (mac_addr[1] == (uint8_t) 0xff)) 7794 /* Broadcast packet */ 7795 stats->bprc++; 7796 else if (*mac_addr & 0x01) 7797 /* Multicast packet */ 7798 stats->mprc++; 7799 7800 if (frame_len == hw->max_frame_size) { 7801 /* 7802 * In this case, the hardware has overcounted the number of 7803 * oversize frames. 7804 */ 7805 if (stats->roc > 0) 7806 stats->roc--; 7807 } 7808 /* 7809 * Adjust the bin counters when the extra byte put the frame in the 7810 * wrong bin. Remember that the frame_len was adjusted above. 7811 */ 7812 if (frame_len == 64) { 7813 stats->prc64++; 7814 stats->prc127--; 7815 } else if (frame_len == 127) { 7816 stats->prc127++; 7817 stats->prc255--; 7818 } else if (frame_len == 255) { 7819 stats->prc255++; 7820 stats->prc511--; 7821 } else if (frame_len == 511) { 7822 stats->prc511++; 7823 stats->prc1023--; 7824 } else if (frame_len == 1023) { 7825 stats->prc1023++; 7826 stats->prc1522--; 7827 } else if (frame_len == 1522) { 7828 stats->prc1522++; 7829 } 7830 } 7831 #endif /* !SMALL_KERNEL */ 7832 7833 /****************************************************************************** 7834 * Gets the current PCI bus type, speed, and width of the hardware 7835 * 7836 * hw - Struct containing variables accessed by shared code 7837 *****************************************************************************/ 7838 void 7839 em_get_bus_info(struct em_hw *hw) 7840 { 7841 int32_t ret_val; 7842 uint16_t pci_ex_link_status; 7843 uint32_t status; 7844 switch (hw->mac_type) { 7845 case em_82542_rev2_0: 7846 case em_82542_rev2_1: 7847 hw->bus_type = em_bus_type_unknown; 7848 hw->bus_speed = em_bus_speed_unknown; 7849 hw->bus_width = em_bus_width_unknown; 7850 break; 7851 case em_icp_xxxx: 7852 hw->bus_type = em_bus_type_cpp; 7853 hw->bus_speed = em_bus_speed_unknown; 7854 hw->bus_width = em_bus_width_unknown; 7855 break; 7856 case em_82571: 7857 case em_82572: 7858 case em_82573: 7859 case em_82574: 7860 case em_82575: 7861 case em_82580: 7862 case em_80003es2lan: 7863 case em_i210: 7864 case em_i350: 7865 hw->bus_type = em_bus_type_pci_express; 7866 hw->bus_speed = em_bus_speed_2500; 7867 ret_val = em_read_pcie_cap_reg(hw, PCI_EX_LINK_STATUS, 7868 &pci_ex_link_status); 7869 if (ret_val) 7870 hw->bus_width = em_bus_width_unknown; 7871 else 7872 hw->bus_width = (pci_ex_link_status & 7873 PCI_EX_LINK_WIDTH_MASK) >> PCI_EX_LINK_WIDTH_SHIFT; 7874 break; 7875 case em_ich8lan: 7876 case em_ich9lan: 7877 case em_ich10lan: 7878 case em_pchlan: 7879 case em_pch2lan: 7880 case em_pch_lpt: 7881 case em_pch_spt: 7882 hw->bus_type = em_bus_type_pci_express; 7883 hw->bus_speed = em_bus_speed_2500; 7884 hw->bus_width = em_bus_width_pciex_1; 7885 break; 7886 default: 7887 status = E1000_READ_REG(hw, STATUS); 7888 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ? 7889 em_bus_type_pcix : em_bus_type_pci; 7890 7891 if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) { 7892 hw->bus_speed = (hw->bus_type == em_bus_type_pci) ? 7893 em_bus_speed_66 : em_bus_speed_120; 7894 } else if (hw->bus_type == em_bus_type_pci) { 7895 hw->bus_speed = (status & E1000_STATUS_PCI66) ? 7896 em_bus_speed_66 : em_bus_speed_33; 7897 } else { 7898 switch (status & E1000_STATUS_PCIX_SPEED) { 7899 case E1000_STATUS_PCIX_SPEED_66: 7900 hw->bus_speed = em_bus_speed_66; 7901 break; 7902 case E1000_STATUS_PCIX_SPEED_100: 7903 hw->bus_speed = em_bus_speed_100; 7904 break; 7905 case E1000_STATUS_PCIX_SPEED_133: 7906 hw->bus_speed = em_bus_speed_133; 7907 break; 7908 default: 7909 hw->bus_speed = em_bus_speed_reserved; 7910 break; 7911 } 7912 } 7913 hw->bus_width = (status & E1000_STATUS_BUS64) ? 7914 em_bus_width_64 : em_bus_width_32; 7915 break; 7916 } 7917 } 7918 7919 /****************************************************************************** 7920 * Writes a value to one of the devices registers using port I/O (as opposed to 7921 * memory mapped I/O). Only 82544 and newer devices support port I/O. 7922 * 7923 * hw - Struct containing variables accessed by shared code 7924 * offset - offset to write to 7925 * value - value to write 7926 *****************************************************************************/ 7927 STATIC void 7928 em_write_reg_io(struct em_hw *hw, uint32_t offset, uint32_t value) 7929 { 7930 unsigned long io_addr = hw->io_base; 7931 unsigned long io_data = hw->io_base + 4; 7932 em_io_write(hw, io_addr, offset); 7933 em_io_write(hw, io_data, value); 7934 } 7935 7936 /****************************************************************************** 7937 * Estimates the cable length. 7938 * 7939 * hw - Struct containing variables accessed by shared code 7940 * min_length - The estimated minimum length 7941 * max_length - The estimated maximum length 7942 * 7943 * returns: - E1000_ERR_XXX 7944 * E1000_SUCCESS 7945 * 7946 * This function always returns a ranged length (minimum & maximum). 7947 * So for M88 phy's, this function interprets the one value returned from the 7948 * register to the minimum and maximum range. 7949 * For IGP phy's, the function calculates the range by the AGC registers. 7950 *****************************************************************************/ 7951 STATIC int32_t 7952 em_get_cable_length(struct em_hw *hw, uint16_t *min_length, 7953 uint16_t *max_length) 7954 { 7955 int32_t ret_val; 7956 uint16_t agc_value = 0; 7957 uint16_t i, phy_data; 7958 uint16_t cable_length; 7959 DEBUGFUNC("em_get_cable_length"); 7960 7961 *min_length = *max_length = 0; 7962 7963 /* Use old method for Phy older than IGP */ 7964 if (hw->phy_type == em_phy_m88 || 7965 hw->phy_type == em_phy_oem || 7966 hw->phy_type == em_phy_82578) { 7967 7968 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, 7969 &phy_data); 7970 if (ret_val) 7971 return ret_val; 7972 cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 7973 M88E1000_PSSR_CABLE_LENGTH_SHIFT; 7974 7975 /* Convert the enum value to ranged values */ 7976 switch (cable_length) { 7977 case em_cable_length_50: 7978 *min_length = 0; 7979 *max_length = em_igp_cable_length_50; 7980 break; 7981 case em_cable_length_50_80: 7982 *min_length = em_igp_cable_length_50; 7983 *max_length = em_igp_cable_length_80; 7984 break; 7985 case em_cable_length_80_110: 7986 *min_length = em_igp_cable_length_80; 7987 *max_length = em_igp_cable_length_110; 7988 break; 7989 case em_cable_length_110_140: 7990 *min_length = em_igp_cable_length_110; 7991 *max_length = em_igp_cable_length_140; 7992 break; 7993 case em_cable_length_140: 7994 *min_length = em_igp_cable_length_140; 7995 *max_length = em_igp_cable_length_170; 7996 break; 7997 default: 7998 return -E1000_ERR_PHY; 7999 break; 8000 } 8001 } else if (hw->phy_type == em_phy_rtl8211) { 8002 /* no cable length info on RTL8211, fake */ 8003 *min_length = 0; 8004 *max_length = em_igp_cable_length_50; 8005 } else if (hw->phy_type == em_phy_gg82563) { 8006 ret_val = em_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE, 8007 &phy_data); 8008 if (ret_val) 8009 return ret_val; 8010 cable_length = phy_data & GG82563_DSPD_CABLE_LENGTH; 8011 8012 switch (cable_length) { 8013 case em_gg_cable_length_60: 8014 *min_length = 0; 8015 *max_length = em_igp_cable_length_60; 8016 break; 8017 case em_gg_cable_length_60_115: 8018 *min_length = em_igp_cable_length_60; 8019 *max_length = em_igp_cable_length_115; 8020 break; 8021 case em_gg_cable_length_115_150: 8022 *min_length = em_igp_cable_length_115; 8023 *max_length = em_igp_cable_length_150; 8024 break; 8025 case em_gg_cable_length_150: 8026 *min_length = em_igp_cable_length_150; 8027 *max_length = em_igp_cable_length_180; 8028 break; 8029 default: 8030 return -E1000_ERR_PHY; 8031 break; 8032 } 8033 } else if (hw->phy_type == em_phy_igp) { /* For IGP PHY */ 8034 uint16_t cur_agc_value; 8035 uint16_t min_agc_value = 8036 IGP01E1000_AGC_LENGTH_TABLE_SIZE; 8037 uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = 8038 {IGP01E1000_PHY_AGC_A, IGP01E1000_PHY_AGC_B, 8039 IGP01E1000_PHY_AGC_C, IGP01E1000_PHY_AGC_D}; 8040 8041 /* Read the AGC registers for all channels */ 8042 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 8043 ret_val = em_read_phy_reg(hw, agc_reg_array[i], 8044 &phy_data); 8045 if (ret_val) 8046 return ret_val; 8047 8048 cur_agc_value = phy_data >> 8049 IGP01E1000_AGC_LENGTH_SHIFT; 8050 8051 /* Value bound check. */ 8052 if ((cur_agc_value >= 8053 IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) || 8054 (cur_agc_value == 0)) 8055 return -E1000_ERR_PHY; 8056 8057 agc_value += cur_agc_value; 8058 8059 /* Update minimal AGC value. */ 8060 if (min_agc_value > cur_agc_value) 8061 min_agc_value = cur_agc_value; 8062 } 8063 8064 /* Remove the minimal AGC result for length < 50m */ 8065 if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * 8066 em_igp_cable_length_50) { 8067 agc_value -= min_agc_value; 8068 8069 /* 8070 * Get the average length of the remaining 3 channels 8071 */ 8072 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1); 8073 } else { 8074 /* Get the average length of all the 4 channels. */ 8075 agc_value /= IGP01E1000_PHY_CHANNEL_NUM; 8076 } 8077 8078 /* Set the range of the calculated length. */ 8079 *min_length = ((em_igp_cable_length_table[agc_value] - 8080 IGP01E1000_AGC_RANGE) > 0) ? 8081 (em_igp_cable_length_table[agc_value] - 8082 IGP01E1000_AGC_RANGE) : 0; 8083 *max_length = em_igp_cable_length_table[agc_value] + 8084 IGP01E1000_AGC_RANGE; 8085 } else if (hw->phy_type == em_phy_igp_2 || 8086 hw->phy_type == em_phy_igp_3) { 8087 uint16_t cur_agc_index, max_agc_index = 0; 8088 uint16_t min_agc_index = IGP02E1000_AGC_LENGTH_TABLE_SIZE - 1; 8089 uint16_t agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = 8090 {IGP02E1000_PHY_AGC_A, IGP02E1000_PHY_AGC_B, 8091 IGP02E1000_PHY_AGC_C, IGP02E1000_PHY_AGC_D}; 8092 /* Read the AGC registers for all channels */ 8093 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { 8094 ret_val = em_read_phy_reg(hw, agc_reg_array[i], 8095 &phy_data); 8096 if (ret_val) 8097 return ret_val; 8098 /* 8099 * Getting bits 15:9, which represent the combination 8100 * of course and fine gain values. The result is a 8101 * number that can be put into the lookup table to 8102 * obtain the approximate cable length. 8103 */ 8104 cur_agc_index = (phy_data >> 8105 IGP02E1000_AGC_LENGTH_SHIFT) & 8106 IGP02E1000_AGC_LENGTH_MASK; 8107 8108 /* Array index bound check. */ 8109 if ((cur_agc_index >= IGP02E1000_AGC_LENGTH_TABLE_SIZE) 8110 || (cur_agc_index == 0)) 8111 return -E1000_ERR_PHY; 8112 8113 /* Remove min & max AGC values from calculation. */ 8114 if (em_igp_2_cable_length_table[min_agc_index] > 8115 em_igp_2_cable_length_table[cur_agc_index]) 8116 min_agc_index = cur_agc_index; 8117 if (em_igp_2_cable_length_table[max_agc_index] < 8118 em_igp_2_cable_length_table[cur_agc_index]) 8119 max_agc_index = cur_agc_index; 8120 8121 agc_value += em_igp_2_cable_length_table 8122 [cur_agc_index]; 8123 } 8124 8125 agc_value -= (em_igp_2_cable_length_table[min_agc_index] + 8126 em_igp_2_cable_length_table[max_agc_index]); 8127 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); 8128 /* 8129 * Calculate cable length with the error range of +/- 10 8130 * meters. 8131 */ 8132 *min_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ? 8133 (agc_value - IGP02E1000_AGC_RANGE) : 0; 8134 *max_length = agc_value + IGP02E1000_AGC_RANGE; 8135 } 8136 return E1000_SUCCESS; 8137 } 8138 8139 /****************************************************************************** 8140 * Check if Downshift occured 8141 * 8142 * hw - Struct containing variables accessed by shared code 8143 * downshift - output parameter : 0 - No Downshift ocured. 8144 * 1 - Downshift ocured. 8145 * 8146 * returns: - E1000_ERR_XXX 8147 * E1000_SUCCESS 8148 * 8149 * For phy's older then IGP, this function reads the Downshift bit in the Phy 8150 * Specific Status register. For IGP phy's, it reads the Downgrade bit in the 8151 * Link Health register. In IGP this bit is latched high, so the driver must 8152 * read it immediately after link is established. 8153 *****************************************************************************/ 8154 STATIC int32_t 8155 em_check_downshift(struct em_hw *hw) 8156 { 8157 int32_t ret_val; 8158 uint16_t phy_data; 8159 DEBUGFUNC("em_check_downshift"); 8160 8161 if (hw->phy_type == em_phy_igp || 8162 hw->phy_type == em_phy_igp_3 || 8163 hw->phy_type == em_phy_igp_2) { 8164 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH, 8165 &phy_data); 8166 if (ret_val) 8167 return ret_val; 8168 8169 hw->speed_downgraded = (phy_data & 8170 IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0; 8171 } else if ((hw->phy_type == em_phy_m88) || 8172 (hw->phy_type == em_phy_gg82563) || 8173 (hw->phy_type == em_phy_oem) || 8174 (hw->phy_type == em_phy_82578)) { 8175 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, 8176 &phy_data); 8177 if (ret_val) 8178 return ret_val; 8179 8180 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >> 8181 M88E1000_PSSR_DOWNSHIFT_SHIFT; 8182 } else if (hw->phy_type == em_phy_ife) { 8183 /* em_phy_ife supports 10/100 speed only */ 8184 hw->speed_downgraded = FALSE; 8185 } 8186 return E1000_SUCCESS; 8187 } 8188 8189 /***************************************************************************** 8190 * 8191 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a 8192 * gigabit link is achieved to improve link quality. 8193 * 8194 * hw: Struct containing variables accessed by shared code 8195 * 8196 * returns: - E1000_ERR_PHY if fail to read/write the PHY 8197 * E1000_SUCCESS at any other case. 8198 * 8199 ****************************************************************************/ 8200 STATIC int32_t 8201 em_config_dsp_after_link_change(struct em_hw *hw, boolean_t link_up) 8202 { 8203 int32_t ret_val; 8204 uint16_t phy_data, phy_saved_data, speed, duplex, i; 8205 uint16_t dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = 8206 {IGP01E1000_PHY_AGC_PARAM_A, IGP01E1000_PHY_AGC_PARAM_B, 8207 IGP01E1000_PHY_AGC_PARAM_C, IGP01E1000_PHY_AGC_PARAM_D}; 8208 uint16_t min_length, max_length; 8209 DEBUGFUNC("em_config_dsp_after_link_change"); 8210 8211 if (hw->phy_type != em_phy_igp) 8212 return E1000_SUCCESS; 8213 8214 if (link_up) { 8215 ret_val = em_get_speed_and_duplex(hw, &speed, &duplex); 8216 if (ret_val) { 8217 DEBUGOUT("Error getting link speed and duplex\n"); 8218 return ret_val; 8219 } 8220 if (speed == SPEED_1000) { 8221 8222 ret_val = em_get_cable_length(hw, &min_length, &max_length); 8223 if (ret_val) 8224 return ret_val; 8225 8226 if ((hw->dsp_config_state == em_dsp_config_enabled) && 8227 min_length >= em_igp_cable_length_50) { 8228 8229 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; 8230 i++) { 8231 ret_val = em_read_phy_reg(hw, 8232 dsp_reg_array[i], &phy_data); 8233 if (ret_val) 8234 return ret_val; 8235 8236 phy_data &= 8237 ~IGP01E1000_PHY_EDAC_MU_INDEX; 8238 8239 ret_val = em_write_phy_reg(hw, 8240 dsp_reg_array[i], phy_data); 8241 if (ret_val) 8242 return ret_val; 8243 } 8244 hw->dsp_config_state = em_dsp_config_activated; 8245 } 8246 if ((hw->ffe_config_state == em_ffe_config_enabled) && 8247 (min_length < em_igp_cable_length_50)) { 8248 8249 uint16_t ffe_idle_err_timeout = 8250 FFE_IDLE_ERR_COUNT_TIMEOUT_20; 8251 uint32_t idle_errs = 0; 8252 /* clear previous idle error counts */ 8253 ret_val = em_read_phy_reg(hw, PHY_1000T_STATUS, 8254 &phy_data); 8255 if (ret_val) 8256 return ret_val; 8257 8258 for (i = 0; i < ffe_idle_err_timeout; i++) { 8259 usec_delay(1000); 8260 ret_val = em_read_phy_reg(hw, 8261 PHY_1000T_STATUS, &phy_data); 8262 if (ret_val) 8263 return ret_val; 8264 8265 idle_errs += (phy_data & 8266 SR_1000T_IDLE_ERROR_CNT); 8267 if (idle_errs > 8268 SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) { 8269 hw->ffe_config_state = 8270 em_ffe_config_active; 8271 8272 ret_val = em_write_phy_reg(hw, 8273 IGP01E1000_PHY_DSP_FFE, 8274 IGP01E1000_PHY_DSP_FFE_CM_CP); 8275 if (ret_val) 8276 return ret_val; 8277 break; 8278 } 8279 if (idle_errs) 8280 ffe_idle_err_timeout = 8281 FFE_IDLE_ERR_COUNT_TIMEOUT_100; 8282 } 8283 } 8284 } 8285 } else { 8286 if (hw->dsp_config_state == em_dsp_config_activated) { 8287 /* 8288 * Save off the current value of register 0x2F5B to 8289 * be restored at the end of the routines. 8290 */ 8291 ret_val = em_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 8292 8293 if (ret_val) 8294 return ret_val; 8295 8296 /* Disable the PHY transmitter */ 8297 ret_val = em_write_phy_reg(hw, 0x2F5B, 0x0003); 8298 8299 if (ret_val) 8300 return ret_val; 8301 8302 msec_delay_irq(20); 8303 8304 ret_val = em_write_phy_reg(hw, 0x0000, 8305 IGP01E1000_IEEE_FORCE_GIGA); 8306 if (ret_val) 8307 return ret_val; 8308 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 8309 ret_val = em_read_phy_reg(hw, dsp_reg_array[i], 8310 &phy_data); 8311 if (ret_val) 8312 return ret_val; 8313 8314 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; 8315 phy_data |= 8316 IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS; 8317 8318 ret_val = em_write_phy_reg(hw, 8319 dsp_reg_array[i], phy_data); 8320 if (ret_val) 8321 return ret_val; 8322 } 8323 8324 ret_val = em_write_phy_reg(hw, 0x0000, 8325 IGP01E1000_IEEE_RESTART_AUTONEG); 8326 if (ret_val) 8327 return ret_val; 8328 8329 msec_delay_irq(20); 8330 8331 /* Now enable the transmitter */ 8332 ret_val = em_write_phy_reg(hw, 0x2F5B, phy_saved_data); 8333 8334 if (ret_val) 8335 return ret_val; 8336 8337 hw->dsp_config_state = em_dsp_config_enabled; 8338 } 8339 if (hw->ffe_config_state == em_ffe_config_active) { 8340 /* 8341 * Save off the current value of register 0x2F5B to 8342 * be restored at the end of the routines. 8343 */ 8344 ret_val = em_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 8345 8346 if (ret_val) 8347 return ret_val; 8348 8349 /* Disable the PHY transmitter */ 8350 ret_val = em_write_phy_reg(hw, 0x2F5B, 0x0003); 8351 8352 if (ret_val) 8353 return ret_val; 8354 8355 msec_delay_irq(20); 8356 8357 ret_val = em_write_phy_reg(hw, 0x0000, 8358 IGP01E1000_IEEE_FORCE_GIGA); 8359 if (ret_val) 8360 return ret_val; 8361 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE, 8362 IGP01E1000_PHY_DSP_FFE_DEFAULT); 8363 if (ret_val) 8364 return ret_val; 8365 8366 ret_val = em_write_phy_reg(hw, 0x0000, 8367 IGP01E1000_IEEE_RESTART_AUTONEG); 8368 if (ret_val) 8369 return ret_val; 8370 8371 msec_delay_irq(20); 8372 8373 /* Now enable the transmitter */ 8374 ret_val = em_write_phy_reg(hw, 0x2F5B, phy_saved_data); 8375 8376 if (ret_val) 8377 return ret_val; 8378 8379 hw->ffe_config_state = em_ffe_config_enabled; 8380 } 8381 } 8382 return E1000_SUCCESS; 8383 } 8384 8385 /***************************************************************************** 8386 * Set PHY to class A mode 8387 * Assumes the following operations will follow to enable the new class mode. 8388 * 1. Do a PHY soft reset 8389 * 2. Restart auto-negotiation or force link. 8390 * 8391 * hw - Struct containing variables accessed by shared code 8392 ****************************************************************************/ 8393 static int32_t 8394 em_set_phy_mode(struct em_hw *hw) 8395 { 8396 int32_t ret_val; 8397 uint16_t eeprom_data; 8398 DEBUGFUNC("em_set_phy_mode"); 8399 8400 if ((hw->mac_type == em_82545_rev_3) && 8401 (hw->media_type == em_media_type_copper)) { 8402 ret_val = em_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, 8403 &eeprom_data); 8404 if (ret_val) { 8405 return ret_val; 8406 } 8407 if ((eeprom_data != EEPROM_RESERVED_WORD) && 8408 (eeprom_data & EEPROM_PHY_CLASS_A)) { 8409 ret_val = em_write_phy_reg(hw, 8410 M88E1000_PHY_PAGE_SELECT, 0x000B); 8411 if (ret_val) 8412 return ret_val; 8413 ret_val = em_write_phy_reg(hw, 8414 M88E1000_PHY_GEN_CONTROL, 0x8104); 8415 if (ret_val) 8416 return ret_val; 8417 8418 hw->phy_reset_disable = FALSE; 8419 } 8420 } 8421 return E1000_SUCCESS; 8422 } 8423 8424 /***************************************************************************** 8425 * 8426 * This function sets the lplu state according to the active flag. When 8427 * activating lplu this function also disables smart speed and vise versa. 8428 * lplu will not be activated unless the device autonegotiation advertisement 8429 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. 8430 * hw: Struct containing variables accessed by shared code 8431 * active - true to enable lplu false to disable lplu. 8432 * 8433 * returns: - E1000_ERR_PHY if fail to read/write the PHY 8434 * E1000_SUCCESS at any other case. 8435 * 8436 ****************************************************************************/ 8437 STATIC int32_t 8438 em_set_d3_lplu_state(struct em_hw *hw, boolean_t active) 8439 { 8440 uint32_t phy_ctrl = 0; 8441 int32_t ret_val; 8442 uint16_t phy_data; 8443 DEBUGFUNC("em_set_d3_lplu_state"); 8444 8445 if (hw->phy_type != em_phy_igp && hw->phy_type != em_phy_igp_2 8446 && hw->phy_type != em_phy_igp_3) 8447 return E1000_SUCCESS; 8448 /* 8449 * During driver activity LPLU should not be used or it will attain 8450 * link from the lowest speeds starting from 10Mbps. The capability 8451 * is used for Dx transitions and states 8452 */ 8453 if (hw->mac_type == em_82541_rev_2 || hw->mac_type == em_82547_rev_2) { 8454 ret_val = em_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data); 8455 if (ret_val) 8456 return ret_val; 8457 } else if (IS_ICH8(hw->mac_type)) { 8458 /* 8459 * MAC writes into PHY register based on the state transition 8460 * and start auto-negotiation. SW driver can overwrite the 8461 * settings in CSR PHY power control E1000_PHY_CTRL register. 8462 */ 8463 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); 8464 } else { 8465 ret_val = em_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, 8466 &phy_data); 8467 if (ret_val) 8468 return ret_val; 8469 } 8470 8471 if (!active) { 8472 if (hw->mac_type == em_82541_rev_2 || 8473 hw->mac_type == em_82547_rev_2) { 8474 phy_data &= ~IGP01E1000_GMII_FLEX_SPD; 8475 ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO, 8476 phy_data); 8477 if (ret_val) 8478 return ret_val; 8479 } else { 8480 if (IS_ICH8(hw->mac_type)) { 8481 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; 8482 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 8483 } else { 8484 phy_data &= ~IGP02E1000_PM_D3_LPLU; 8485 ret_val = em_write_phy_reg(hw, 8486 IGP02E1000_PHY_POWER_MGMT, phy_data); 8487 if (ret_val) 8488 return ret_val; 8489 } 8490 } 8491 /* 8492 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 8493 * during Dx states where the power conservation is most 8494 * important. During driver activity we should enable 8495 * SmartSpeed, so performance is maintained. 8496 */ 8497 if (hw->smart_speed == em_smart_speed_on) { 8498 ret_val = em_read_phy_reg(hw, 8499 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 8500 if (ret_val) 8501 return ret_val; 8502 8503 phy_data |= IGP01E1000_PSCFR_SMART_SPEED; 8504 ret_val = em_write_phy_reg(hw, 8505 IGP01E1000_PHY_PORT_CONFIG, phy_data); 8506 if (ret_val) 8507 return ret_val; 8508 } else if (hw->smart_speed == em_smart_speed_off) { 8509 ret_val = em_read_phy_reg(hw, 8510 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 8511 if (ret_val) 8512 return ret_val; 8513 8514 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 8515 ret_val = em_write_phy_reg(hw, 8516 IGP01E1000_PHY_PORT_CONFIG, phy_data); 8517 if (ret_val) 8518 return ret_val; 8519 } 8520 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) 8521 || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) || 8522 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) { 8523 8524 if (hw->mac_type == em_82541_rev_2 || 8525 hw->mac_type == em_82547_rev_2) { 8526 phy_data |= IGP01E1000_GMII_FLEX_SPD; 8527 ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO, 8528 phy_data); 8529 if (ret_val) 8530 return ret_val; 8531 } else { 8532 if (IS_ICH8(hw->mac_type)) { 8533 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; 8534 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 8535 } else { 8536 phy_data |= IGP02E1000_PM_D3_LPLU; 8537 ret_val = em_write_phy_reg(hw, 8538 IGP02E1000_PHY_POWER_MGMT, phy_data); 8539 if (ret_val) 8540 return ret_val; 8541 } 8542 } 8543 8544 /* When LPLU is enabled we should disable SmartSpeed */ 8545 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 8546 &phy_data); 8547 if (ret_val) 8548 return ret_val; 8549 8550 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 8551 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 8552 phy_data); 8553 if (ret_val) 8554 return ret_val; 8555 8556 } 8557 return E1000_SUCCESS; 8558 } 8559 8560 /***************************************************************************** 8561 * 8562 * This function sets the lplu d0 state according to the active flag. When 8563 * activating lplu this function also disables smart speed and vise versa. 8564 * lplu will not be activated unless the device autonegotiation advertisement 8565 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. 8566 * hw: Struct containing variables accessed by shared code 8567 * active - true to enable lplu false to disable lplu. 8568 * 8569 * returns: - E1000_ERR_PHY if fail to read/write the PHY 8570 * E1000_SUCCESS at any other case. 8571 * 8572 ****************************************************************************/ 8573 STATIC int32_t 8574 em_set_d0_lplu_state(struct em_hw *hw, boolean_t active) 8575 { 8576 uint32_t phy_ctrl = 0; 8577 int32_t ret_val; 8578 uint16_t phy_data; 8579 DEBUGFUNC("em_set_d0_lplu_state"); 8580 8581 if (hw->mac_type <= em_82547_rev_2) 8582 return E1000_SUCCESS; 8583 8584 if (IS_ICH8(hw->mac_type)) { 8585 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); 8586 } else { 8587 ret_val = em_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, 8588 &phy_data); 8589 if (ret_val) 8590 return ret_val; 8591 } 8592 8593 if (!active) { 8594 if (IS_ICH8(hw->mac_type)) { 8595 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; 8596 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 8597 } else { 8598 phy_data &= ~IGP02E1000_PM_D0_LPLU; 8599 ret_val = em_write_phy_reg(hw, 8600 IGP02E1000_PHY_POWER_MGMT, phy_data); 8601 if (ret_val) 8602 return ret_val; 8603 } 8604 /* 8605 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 8606 * during Dx states where the power conservation is most 8607 * important. During driver activity we should enable 8608 * SmartSpeed, so performance is maintained. 8609 */ 8610 if (hw->smart_speed == em_smart_speed_on) { 8611 ret_val = em_read_phy_reg(hw, 8612 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 8613 if (ret_val) 8614 return ret_val; 8615 8616 phy_data |= IGP01E1000_PSCFR_SMART_SPEED; 8617 ret_val = em_write_phy_reg(hw, 8618 IGP01E1000_PHY_PORT_CONFIG, phy_data); 8619 if (ret_val) 8620 return ret_val; 8621 } else if (hw->smart_speed == em_smart_speed_off) { 8622 ret_val = em_read_phy_reg(hw, 8623 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 8624 if (ret_val) 8625 return ret_val; 8626 8627 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 8628 ret_val = em_write_phy_reg(hw, 8629 IGP01E1000_PHY_PORT_CONFIG, phy_data); 8630 if (ret_val) 8631 return ret_val; 8632 } 8633 } else { 8634 if (IS_ICH8(hw->mac_type)) { 8635 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; 8636 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 8637 } else { 8638 phy_data |= IGP02E1000_PM_D0_LPLU; 8639 ret_val = em_write_phy_reg(hw, 8640 IGP02E1000_PHY_POWER_MGMT, phy_data); 8641 if (ret_val) 8642 return ret_val; 8643 } 8644 8645 /* When LPLU is enabled we should disable SmartSpeed */ 8646 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 8647 &phy_data); 8648 if (ret_val) 8649 return ret_val; 8650 8651 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 8652 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 8653 phy_data); 8654 if (ret_val) 8655 return ret_val; 8656 8657 } 8658 return E1000_SUCCESS; 8659 } 8660 8661 /*************************************************************************** 8662 * Set Low Power Link Up state 8663 * 8664 * Sets the LPLU state according to the active flag. For PCH, if OEM write 8665 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set 8666 * the phy speed. This function will manually set the LPLU bit and restart 8667 * auto-neg as hw would do. D3 and D0 LPLU will call the same function 8668 * since it configures the same bit. 8669 ***************************************************************************/ 8670 int32_t 8671 em_set_lplu_state_pchlan(struct em_hw *hw, boolean_t active) 8672 { 8673 int32_t ret_val = E1000_SUCCESS; 8674 uint16_t oem_reg; 8675 8676 DEBUGFUNC("e1000_set_lplu_state_pchlan"); 8677 8678 ret_val = em_read_phy_reg(hw, HV_OEM_BITS, &oem_reg); 8679 if (ret_val) 8680 goto out; 8681 8682 if (active) 8683 oem_reg |= HV_OEM_BITS_LPLU; 8684 else 8685 oem_reg &= ~HV_OEM_BITS_LPLU; 8686 8687 oem_reg |= HV_OEM_BITS_RESTART_AN; 8688 ret_val = em_write_phy_reg(hw, HV_OEM_BITS, oem_reg); 8689 8690 out: 8691 return ret_val; 8692 } 8693 8694 /****************************************************************************** 8695 * Change VCO speed register to improve Bit Error Rate performance of SERDES. 8696 * 8697 * hw - Struct containing variables accessed by shared code 8698 *****************************************************************************/ 8699 static int32_t 8700 em_set_vco_speed(struct em_hw *hw) 8701 { 8702 int32_t ret_val; 8703 uint16_t default_page = 0; 8704 uint16_t phy_data; 8705 DEBUGFUNC("em_set_vco_speed"); 8706 8707 switch (hw->mac_type) { 8708 case em_82545_rev_3: 8709 case em_82546_rev_3: 8710 break; 8711 default: 8712 return E1000_SUCCESS; 8713 } 8714 8715 /* Set PHY register 30, page 5, bit 8 to 0 */ 8716 8717 ret_val = em_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page); 8718 if (ret_val) 8719 return ret_val; 8720 8721 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005); 8722 if (ret_val) 8723 return ret_val; 8724 8725 ret_val = em_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); 8726 if (ret_val) 8727 return ret_val; 8728 8729 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8; 8730 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); 8731 if (ret_val) 8732 return ret_val; 8733 8734 /* Set PHY register 30, page 4, bit 11 to 1 */ 8735 8736 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004); 8737 if (ret_val) 8738 return ret_val; 8739 8740 ret_val = em_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); 8741 if (ret_val) 8742 return ret_val; 8743 8744 phy_data |= M88E1000_PHY_VCO_REG_BIT11; 8745 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); 8746 if (ret_val) 8747 return ret_val; 8748 8749 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page); 8750 if (ret_val) 8751 return ret_val; 8752 8753 return E1000_SUCCESS; 8754 } 8755 8756 /***************************************************************************** 8757 * This function reads the cookie from ARC ram. 8758 * 8759 * returns: - E1000_SUCCESS . 8760 ****************************************************************************/ 8761 STATIC int32_t 8762 em_host_if_read_cookie(struct em_hw *hw, uint8_t *buffer) 8763 { 8764 uint8_t i; 8765 uint32_t offset = E1000_MNG_DHCP_COOKIE_OFFSET; 8766 uint8_t length = E1000_MNG_DHCP_COOKIE_LENGTH; 8767 length = (length >> 2); 8768 offset = (offset >> 2); 8769 8770 for (i = 0; i < length; i++) { 8771 *((uint32_t *) buffer + i) = 8772 E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i); 8773 } 8774 return E1000_SUCCESS; 8775 } 8776 8777 /***************************************************************************** 8778 * This function checks whether the HOST IF is enabled for command operaton 8779 * and also checks whether the previous command is completed. 8780 * It busy waits in case of previous command is not completed. 8781 * 8782 * returns: - E1000_ERR_HOST_INTERFACE_COMMAND in case if is not ready or 8783 * timeout 8784 * - E1000_SUCCESS for success. 8785 ****************************************************************************/ 8786 STATIC int32_t 8787 em_mng_enable_host_if(struct em_hw *hw) 8788 { 8789 uint32_t hicr; 8790 uint8_t i; 8791 /* Check that the host interface is enabled. */ 8792 hicr = E1000_READ_REG(hw, HICR); 8793 if ((hicr & E1000_HICR_EN) == 0) { 8794 DEBUGOUT("E1000_HOST_EN bit disabled.\n"); 8795 return -E1000_ERR_HOST_INTERFACE_COMMAND; 8796 } 8797 /* check the previous command is completed */ 8798 for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) { 8799 hicr = E1000_READ_REG(hw, HICR); 8800 if (!(hicr & E1000_HICR_C)) 8801 break; 8802 msec_delay_irq(1); 8803 } 8804 8805 if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) { 8806 DEBUGOUT("Previous command timeout failed .\n"); 8807 return -E1000_ERR_HOST_INTERFACE_COMMAND; 8808 } 8809 return E1000_SUCCESS; 8810 } 8811 8812 /***************************************************************************** 8813 * This function checks the mode of the firmware. 8814 * 8815 * returns - TRUE when the mode is IAMT or FALSE. 8816 ****************************************************************************/ 8817 boolean_t 8818 em_check_mng_mode(struct em_hw *hw) 8819 { 8820 uint32_t fwsm; 8821 fwsm = E1000_READ_REG(hw, FWSM); 8822 8823 if (IS_ICH8(hw->mac_type)) { 8824 if ((fwsm & E1000_FWSM_MODE_MASK) == 8825 (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) 8826 return TRUE; 8827 } else if ((fwsm & E1000_FWSM_MODE_MASK) == 8828 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) 8829 return TRUE; 8830 8831 return FALSE; 8832 } 8833 8834 /***************************************************************************** 8835 * This function calculates the checksum. 8836 * 8837 * returns - checksum of buffer contents. 8838 ****************************************************************************/ 8839 STATIC uint8_t 8840 em_calculate_mng_checksum(char *buffer, uint32_t length) 8841 { 8842 uint8_t sum = 0; 8843 uint32_t i; 8844 if (!buffer) 8845 return 0; 8846 8847 for (i = 0; i < length; i++) 8848 sum += buffer[i]; 8849 8850 return (uint8_t) (0 - sum); 8851 } 8852 8853 /***************************************************************************** 8854 * This function checks whether tx pkt filtering needs to be enabled or not. 8855 * 8856 * returns - TRUE for packet filtering or FALSE. 8857 ****************************************************************************/ 8858 boolean_t 8859 em_enable_tx_pkt_filtering(struct em_hw *hw) 8860 { 8861 /* called in init as well as watchdog timer functions */ 8862 int32_t ret_val, checksum; 8863 boolean_t tx_filter = FALSE; 8864 struct em_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie); 8865 uint8_t *buffer = (uint8_t *) & (hw->mng_cookie); 8866 if (em_check_mng_mode(hw)) { 8867 ret_val = em_mng_enable_host_if(hw); 8868 if (ret_val == E1000_SUCCESS) { 8869 ret_val = em_host_if_read_cookie(hw, buffer); 8870 if (ret_val == E1000_SUCCESS) { 8871 checksum = hdr->checksum; 8872 hdr->checksum = 0; 8873 if ((hdr->signature == E1000_IAMT_SIGNATURE) && 8874 checksum == em_calculate_mng_checksum( 8875 (char *) buffer, 8876 E1000_MNG_DHCP_COOKIE_LENGTH)) { 8877 if (hdr->status & 8878 E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT) 8879 tx_filter = TRUE; 8880 } else 8881 tx_filter = TRUE; 8882 } else 8883 tx_filter = TRUE; 8884 } 8885 } 8886 hw->tx_pkt_filtering = tx_filter; 8887 return tx_filter; 8888 } 8889 8890 static int32_t 8891 em_polarity_reversal_workaround(struct em_hw *hw) 8892 { 8893 int32_t ret_val; 8894 uint16_t mii_status_reg; 8895 uint16_t i; 8896 /* Polarity reversal workaround for forced 10F/10H links. */ 8897 8898 /* Disable the transmitter on the PHY */ 8899 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 8900 if (ret_val) 8901 return ret_val; 8902 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF); 8903 if (ret_val) 8904 return ret_val; 8905 8906 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 8907 if (ret_val) 8908 return ret_val; 8909 8910 /* This loop will early-out if the NO link condition has been met. */ 8911 for (i = PHY_FORCE_TIME; i > 0; i--) { 8912 /* 8913 * Read the MII Status Register and wait for Link Status bit 8914 * to be clear. 8915 */ 8916 8917 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 8918 if (ret_val) 8919 return ret_val; 8920 8921 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 8922 if (ret_val) 8923 return ret_val; 8924 8925 if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) 8926 break; 8927 msec_delay_irq(100); 8928 } 8929 8930 /* Recommended delay time after link has been lost */ 8931 msec_delay_irq(1000); 8932 8933 /* Now we will re-enable the transmitter on the PHY */ 8934 8935 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 8936 if (ret_val) 8937 return ret_val; 8938 msec_delay_irq(50); 8939 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0); 8940 if (ret_val) 8941 return ret_val; 8942 msec_delay_irq(50); 8943 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00); 8944 if (ret_val) 8945 return ret_val; 8946 msec_delay_irq(50); 8947 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000); 8948 if (ret_val) 8949 return ret_val; 8950 8951 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 8952 if (ret_val) 8953 return ret_val; 8954 8955 /* This loop will early-out if the link condition has been met. */ 8956 for (i = PHY_FORCE_TIME; i > 0; i--) { 8957 /* 8958 * Read the MII Status Register and wait for Link Status bit 8959 * to be set. 8960 */ 8961 8962 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 8963 if (ret_val) 8964 return ret_val; 8965 8966 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 8967 if (ret_val) 8968 return ret_val; 8969 8970 if (mii_status_reg & MII_SR_LINK_STATUS) 8971 break; 8972 msec_delay_irq(100); 8973 } 8974 return E1000_SUCCESS; 8975 } 8976 8977 /****************************************************************************** 8978 * 8979 * Disables PCI-Express master access. 8980 * 8981 * hw: Struct containing variables accessed by shared code 8982 * 8983 * returns: - none. 8984 * 8985 *****************************************************************************/ 8986 STATIC void 8987 em_set_pci_express_master_disable(struct em_hw *hw) 8988 { 8989 uint32_t ctrl; 8990 DEBUGFUNC("em_set_pci_express_master_disable"); 8991 8992 if (hw->bus_type != em_bus_type_pci_express) 8993 return; 8994 8995 ctrl = E1000_READ_REG(hw, CTRL); 8996 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; 8997 E1000_WRITE_REG(hw, CTRL, ctrl); 8998 } 8999 9000 /****************************************************************************** 9001 * 9002 * Disables PCI-Express master access and verifies there are no pending 9003 * requests 9004 * 9005 * hw: Struct containing variables accessed by shared code 9006 * 9007 * returns: - E1000_ERR_MASTER_REQUESTS_PENDING if master disable bit hasn't 9008 * caused the master requests to be disabled. 9009 * E1000_SUCCESS master requests disabled. 9010 * 9011 ******************************************************************************/ 9012 int32_t 9013 em_disable_pciex_master(struct em_hw *hw) 9014 { 9015 int32_t timeout = MASTER_DISABLE_TIMEOUT; /* 80ms */ 9016 DEBUGFUNC("em_disable_pciex_master"); 9017 9018 if (hw->bus_type != em_bus_type_pci_express) 9019 return E1000_SUCCESS; 9020 9021 em_set_pci_express_master_disable(hw); 9022 9023 while (timeout) { 9024 if (!(E1000_READ_REG(hw, STATUS) & 9025 E1000_STATUS_GIO_MASTER_ENABLE)) 9026 break; 9027 else 9028 usec_delay(100); 9029 timeout--; 9030 } 9031 9032 if (!timeout) { 9033 DEBUGOUT("Master requests are pending.\n"); 9034 return -E1000_ERR_MASTER_REQUESTS_PENDING; 9035 } 9036 return E1000_SUCCESS; 9037 } 9038 9039 /****************************************************************************** 9040 * 9041 * Check for EEPROM Auto Read bit done. 9042 * 9043 * hw: Struct containing variables accessed by shared code 9044 * 9045 * returns: - E1000_ERR_RESET if fail to reset MAC 9046 * E1000_SUCCESS at any other case. 9047 * 9048 ******************************************************************************/ 9049 STATIC int32_t 9050 em_get_auto_rd_done(struct em_hw *hw) 9051 { 9052 int32_t timeout = AUTO_READ_DONE_TIMEOUT; 9053 DEBUGFUNC("em_get_auto_rd_done"); 9054 9055 switch (hw->mac_type) { 9056 default: 9057 msec_delay(5); 9058 break; 9059 case em_82571: 9060 case em_82572: 9061 case em_82573: 9062 case em_82574: 9063 case em_82575: 9064 case em_82580: 9065 case em_80003es2lan: 9066 case em_i210: 9067 case em_i350: 9068 case em_ich8lan: 9069 case em_ich9lan: 9070 case em_ich10lan: 9071 case em_pchlan: 9072 case em_pch2lan: 9073 case em_pch_lpt: 9074 case em_pch_spt: 9075 while (timeout) { 9076 if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD) 9077 break; 9078 else 9079 msec_delay(1); 9080 timeout--; 9081 } 9082 9083 if (!timeout) { 9084 DEBUGOUT("Auto read by HW from EEPROM has not" 9085 " completed.\n"); 9086 return -E1000_ERR_RESET; 9087 } 9088 break; 9089 } 9090 /* 9091 * PHY configuration from NVM just starts after EECD_AUTO_RD sets to 9092 * high. Need to wait for PHY configuration completion before 9093 * accessing NVM and PHY. 9094 */ 9095 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) 9096 msec_delay(25); 9097 9098 return E1000_SUCCESS; 9099 } 9100 9101 /*************************************************************************** 9102 * Checks if the PHY configuration is done 9103 * 9104 * hw: Struct containing variables accessed by shared code 9105 * 9106 * returns: - E1000_ERR_RESET if fail to reset MAC 9107 * E1000_SUCCESS at any other case. 9108 * 9109 ***************************************************************************/ 9110 STATIC int32_t 9111 em_get_phy_cfg_done(struct em_hw *hw) 9112 { 9113 int32_t timeout = PHY_CFG_TIMEOUT; 9114 uint32_t cfg_mask = E1000_NVM_CFG_DONE_PORT_0; 9115 DEBUGFUNC("em_get_phy_cfg_done"); 9116 9117 switch (hw->mac_type) { 9118 default: 9119 msec_delay_irq(10); 9120 break; 9121 case em_80003es2lan: 9122 case em_82575: 9123 case em_82580: 9124 case em_i350: 9125 switch (hw->bus_func) { 9126 case 1: 9127 cfg_mask = E1000_NVM_CFG_DONE_PORT_1; 9128 break; 9129 case 2: 9130 cfg_mask = E1000_NVM_CFG_DONE_PORT_2; 9131 break; 9132 case 3: 9133 cfg_mask = E1000_NVM_CFG_DONE_PORT_3; 9134 break; 9135 } 9136 /* FALLTHROUGH */ 9137 case em_82571: 9138 case em_82572: 9139 while (timeout) { 9140 if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask) 9141 break; 9142 else 9143 msec_delay(1); 9144 timeout--; 9145 } 9146 if (!timeout) { 9147 DEBUGOUT("MNG configuration cycle has not completed." 9148 "\n"); 9149 } 9150 break; 9151 } 9152 9153 return E1000_SUCCESS; 9154 } 9155 9156 /*************************************************************************** 9157 * 9158 * Using the combination of SMBI and SWESMBI semaphore bits when resetting 9159 * adapter or Eeprom access. 9160 * 9161 * hw: Struct containing variables accessed by shared code 9162 * 9163 * returns: - E1000_ERR_EEPROM if fail to access EEPROM. 9164 * E1000_SUCCESS at any other case. 9165 * 9166 ***************************************************************************/ 9167 STATIC int32_t 9168 em_get_hw_eeprom_semaphore(struct em_hw *hw) 9169 { 9170 int32_t timeout; 9171 uint32_t swsm; 9172 DEBUGFUNC("em_get_hw_eeprom_semaphore"); 9173 9174 if (!hw->eeprom_semaphore_present) 9175 return E1000_SUCCESS; 9176 9177 if (hw->mac_type == em_80003es2lan) { 9178 /* Get the SW semaphore. */ 9179 if (em_get_software_semaphore(hw) != E1000_SUCCESS) 9180 return -E1000_ERR_EEPROM; 9181 } 9182 /* Get the FW semaphore. */ 9183 timeout = hw->eeprom.word_size + 1; 9184 while (timeout) { 9185 swsm = E1000_READ_REG(hw, SWSM); 9186 swsm |= E1000_SWSM_SWESMBI; 9187 E1000_WRITE_REG(hw, SWSM, swsm); 9188 /* if we managed to set the bit we got the semaphore. */ 9189 swsm = E1000_READ_REG(hw, SWSM); 9190 if (swsm & E1000_SWSM_SWESMBI) 9191 break; 9192 9193 usec_delay(50); 9194 timeout--; 9195 } 9196 9197 if (!timeout) { 9198 /* Release semaphores */ 9199 em_put_hw_eeprom_semaphore(hw); 9200 DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set." 9201 "\n"); 9202 return -E1000_ERR_EEPROM; 9203 } 9204 return E1000_SUCCESS; 9205 } 9206 9207 /*************************************************************************** 9208 * This function clears HW semaphore bits. 9209 * 9210 * hw: Struct containing variables accessed by shared code 9211 * 9212 * returns: - None. 9213 * 9214 ***************************************************************************/ 9215 STATIC void 9216 em_put_hw_eeprom_semaphore(struct em_hw *hw) 9217 { 9218 uint32_t swsm; 9219 DEBUGFUNC("em_put_hw_eeprom_semaphore"); 9220 9221 if (!hw->eeprom_semaphore_present) 9222 return; 9223 9224 swsm = E1000_READ_REG(hw, SWSM); 9225 if (hw->mac_type == em_80003es2lan) { 9226 /* Release both semaphores. */ 9227 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 9228 } else 9229 swsm &= ~(E1000_SWSM_SWESMBI); 9230 E1000_WRITE_REG(hw, SWSM, swsm); 9231 } 9232 9233 /*************************************************************************** 9234 * 9235 * Obtaining software semaphore bit (SMBI) before resetting PHY. 9236 * 9237 * hw: Struct containing variables accessed by shared code 9238 * 9239 * returns: - E1000_ERR_RESET if fail to obtain semaphore. 9240 * E1000_SUCCESS at any other case. 9241 * 9242 ***************************************************************************/ 9243 STATIC int32_t 9244 em_get_software_semaphore(struct em_hw *hw) 9245 { 9246 int32_t timeout = hw->eeprom.word_size + 1; 9247 uint32_t swsm; 9248 DEBUGFUNC("em_get_software_semaphore"); 9249 9250 if (hw->mac_type != em_80003es2lan) 9251 return E1000_SUCCESS; 9252 9253 while (timeout) { 9254 swsm = E1000_READ_REG(hw, SWSM); 9255 /* 9256 * If SMBI bit cleared, it is now set and we hold the 9257 * semaphore 9258 */ 9259 if (!(swsm & E1000_SWSM_SMBI)) 9260 break; 9261 msec_delay_irq(1); 9262 timeout--; 9263 } 9264 9265 if (!timeout) { 9266 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 9267 return -E1000_ERR_RESET; 9268 } 9269 return E1000_SUCCESS; 9270 } 9271 9272 /*************************************************************************** 9273 * 9274 * Release semaphore bit (SMBI). 9275 * 9276 * hw: Struct containing variables accessed by shared code 9277 * 9278 ***************************************************************************/ 9279 STATIC void 9280 em_release_software_semaphore(struct em_hw *hw) 9281 { 9282 uint32_t swsm; 9283 DEBUGFUNC("em_release_software_semaphore"); 9284 9285 if (hw->mac_type != em_80003es2lan) 9286 return; 9287 9288 swsm = E1000_READ_REG(hw, SWSM); 9289 /* Release the SW semaphores. */ 9290 swsm &= ~E1000_SWSM_SMBI; 9291 E1000_WRITE_REG(hw, SWSM, swsm); 9292 } 9293 9294 /****************************************************************************** 9295 * Checks if PHY reset is blocked due to SOL/IDER session, for example. 9296 * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to 9297 * the caller to figure out how to deal with it. 9298 * 9299 * hw - Struct containing variables accessed by shared code 9300 * 9301 * returns: - E1000_BLK_PHY_RESET 9302 * E1000_SUCCESS 9303 * 9304 *****************************************************************************/ 9305 int32_t 9306 em_check_phy_reset_block(struct em_hw *hw) 9307 { 9308 uint32_t manc = 0; 9309 uint32_t fwsm = 0; 9310 DEBUGFUNC("em_check_phy_reset_block\n"); 9311 9312 if (IS_ICH8(hw->mac_type)) { 9313 fwsm = E1000_READ_REG(hw, FWSM); 9314 return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS : 9315 E1000_BLK_PHY_RESET; 9316 } 9317 if (hw->mac_type > em_82547_rev_2) 9318 manc = E1000_READ_REG(hw, MANC); 9319 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? 9320 E1000_BLK_PHY_RESET : E1000_SUCCESS; 9321 } 9322 9323 /****************************************************************************** 9324 * Configure PCI-Ex no-snoop 9325 * 9326 * hw - Struct containing variables accessed by shared code. 9327 * no_snoop - Bitmap of no-snoop events. 9328 * 9329 * returns: E1000_SUCCESS 9330 * 9331 *****************************************************************************/ 9332 STATIC int32_t 9333 em_set_pci_ex_no_snoop(struct em_hw *hw, uint32_t no_snoop) 9334 { 9335 uint32_t gcr_reg = 0; 9336 DEBUGFUNC("em_set_pci_ex_no_snoop"); 9337 9338 if (hw->bus_type == em_bus_type_unknown) 9339 em_get_bus_info(hw); 9340 9341 if (hw->bus_type != em_bus_type_pci_express) 9342 return E1000_SUCCESS; 9343 9344 if (no_snoop) { 9345 gcr_reg = E1000_READ_REG(hw, GCR); 9346 gcr_reg &= ~(PCI_EX_NO_SNOOP_ALL); 9347 gcr_reg |= no_snoop; 9348 E1000_WRITE_REG(hw, GCR, gcr_reg); 9349 } 9350 if (IS_ICH8(hw->mac_type)) { 9351 uint32_t ctrl_ext; 9352 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 9353 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 9354 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 9355 } 9356 return E1000_SUCCESS; 9357 } 9358 9359 /*************************************************************************** 9360 * 9361 * Get software semaphore FLAG bit (SWFLAG). 9362 * SWFLAG is used to synchronize the access to all shared resource between 9363 * SW, FW and HW. 9364 * 9365 * hw: Struct containing variables accessed by shared code 9366 * 9367 ***************************************************************************/ 9368 STATIC int32_t 9369 em_get_software_flag(struct em_hw *hw) 9370 { 9371 int32_t timeout = PHY_CFG_TIMEOUT; 9372 uint32_t extcnf_ctrl; 9373 DEBUGFUNC("em_get_software_flag"); 9374 9375 if (IS_ICH8(hw->mac_type)) { 9376 while (timeout) { 9377 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 9378 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; 9379 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); 9380 9381 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 9382 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) 9383 break; 9384 msec_delay_irq(1); 9385 timeout--; 9386 } 9387 9388 if (!timeout) { 9389 DEBUGOUT("FW or HW locks the resource too long.\n"); 9390 return -E1000_ERR_CONFIG; 9391 } 9392 } 9393 return E1000_SUCCESS; 9394 } 9395 9396 /*************************************************************************** 9397 * 9398 * Release software semaphore FLAG bit (SWFLAG). 9399 * SWFLAG is used to synchronize the access to all shared resource between 9400 * SW, FW and HW. 9401 * 9402 * hw: Struct containing variables accessed by shared code 9403 * 9404 ***************************************************************************/ 9405 STATIC void 9406 em_release_software_flag(struct em_hw *hw) 9407 { 9408 uint32_t extcnf_ctrl; 9409 DEBUGFUNC("em_release_software_flag"); 9410 9411 if (IS_ICH8(hw->mac_type)) { 9412 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 9413 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 9414 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); 9415 } 9416 return; 9417 } 9418 9419 /** 9420 * em_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1 9421 * @hw: pointer to the HW structure 9422 * @bank: pointer to the variable that returns the active bank 9423 * 9424 * Reads signature byte from the NVM using the flash access registers. 9425 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank. 9426 **/ 9427 int32_t 9428 em_valid_nvm_bank_detect_ich8lan(struct em_hw *hw, uint32_t *bank) 9429 { 9430 uint32_t eecd; 9431 uint32_t bank1_offset = hw->flash_bank_size * sizeof(uint16_t); 9432 uint32_t act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1; 9433 uint32_t nvm_dword = 0; 9434 uint8_t sig_byte = 0; 9435 int32_t ret_val; 9436 9437 DEBUGFUNC("em_valid_nvm_bank_detect_ich8lan"); 9438 9439 switch (hw->mac_type) { 9440 case em_pch_spt: 9441 bank1_offset = hw->flash_bank_size * 2; 9442 act_offset = E1000_ICH_NVM_SIG_WORD * 2; 9443 9444 /* set bank to 0 in case flash read fails. */ 9445 *bank = 0; 9446 9447 /* Check bank 0 */ 9448 ret_val = em_read_ich8_dword(hw, act_offset, &nvm_dword); 9449 if (ret_val) 9450 return ret_val; 9451 sig_byte = (uint8_t)((nvm_dword & 0xFF00) >> 8); 9452 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 9453 E1000_ICH_NVM_SIG_VALUE) { 9454 *bank = 0; 9455 return 0; 9456 } 9457 9458 /* Check bank 1 */ 9459 ret_val = em_read_ich8_dword(hw, act_offset + bank1_offset, 9460 &nvm_dword); 9461 if (ret_val) 9462 return ret_val; 9463 sig_byte = (uint8_t)((nvm_dword & 0xFF00) >> 8); 9464 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 9465 E1000_ICH_NVM_SIG_VALUE) { 9466 *bank = 1; 9467 return 0; 9468 } 9469 9470 DEBUGOUT("ERROR: No valid NVM bank present\n"); 9471 return -1; 9472 case em_ich8lan: 9473 case em_ich9lan: 9474 eecd = E1000_READ_REG(hw, EECD); 9475 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) == 9476 E1000_EECD_SEC1VAL_VALID_MASK) { 9477 if (eecd & E1000_EECD_SEC1VAL) 9478 *bank = 1; 9479 else 9480 *bank = 0; 9481 9482 return E1000_SUCCESS; 9483 } 9484 DEBUGOUT("Unable to determine valid NVM bank via EEC - reading flash signature\n"); 9485 /* fall-thru */ 9486 default: 9487 /* set bank to 0 in case flash read fails */ 9488 *bank = 0; 9489 9490 /* Check bank 0 */ 9491 ret_val = em_read_ich8_byte(hw, act_offset, 9492 &sig_byte); 9493 if (ret_val) 9494 return ret_val; 9495 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 9496 E1000_ICH_NVM_SIG_VALUE) { 9497 *bank = 0; 9498 return E1000_SUCCESS; 9499 } 9500 9501 /* Check bank 1 */ 9502 ret_val = em_read_ich8_byte(hw, act_offset + 9503 bank1_offset, 9504 &sig_byte); 9505 if (ret_val) 9506 return ret_val; 9507 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 9508 E1000_ICH_NVM_SIG_VALUE) { 9509 *bank = 1; 9510 return E1000_SUCCESS; 9511 } 9512 9513 DEBUGOUT("ERROR: No valid NVM bank present\n"); 9514 return -1; 9515 } 9516 } 9517 9518 STATIC int32_t 9519 em_read_eeprom_spt(struct em_hw *hw, uint16_t offset, uint16_t words, 9520 uint16_t *data) 9521 { 9522 int32_t error = E1000_SUCCESS; 9523 uint32_t flash_bank = 0; 9524 uint32_t act_offset = 0; 9525 uint32_t bank_offset = 0; 9526 uint32_t dword = 0; 9527 uint16_t i = 0, add; 9528 9529 /* 9530 * We need to know which is the valid flash bank. In the event that 9531 * we didn't allocate eeprom_shadow_ram, we may not be managing 9532 * flash_bank. So it cannot be trusted and needs to be updated with 9533 * each read. 9534 */ 9535 9536 if (hw->mac_type != em_pch_spt) 9537 return -E1000_ERR_EEPROM; 9538 9539 error = em_get_software_flag(hw); 9540 if (error != E1000_SUCCESS) 9541 return error; 9542 9543 error = em_valid_nvm_bank_detect_ich8lan(hw, &flash_bank); 9544 if (error != E1000_SUCCESS) { 9545 DEBUGOUT("Could not detect valid bank, assuming bank 0\n"); 9546 flash_bank = 0; 9547 } 9548 9549 /* 9550 * Adjust offset appropriately if we're on bank 1 - adjust for word 9551 * size 9552 */ 9553 bank_offset = flash_bank * (hw->flash_bank_size * 2); 9554 9555 for (i = add = 0; i < words; i += add) { 9556 if ((offset + i) % 2) { 9557 add = 1; 9558 if (hw->eeprom_shadow_ram != NULL 9559 && hw->eeprom_shadow_ram[offset + i].modified) { 9560 data[i] = 9561 hw->eeprom_shadow_ram[offset+i].eeprom_word; 9562 continue; 9563 } 9564 act_offset = bank_offset + (offset + i - 1) * 2; 9565 } else { 9566 add = 2; 9567 if (hw->eeprom_shadow_ram != NULL 9568 && hw->eeprom_shadow_ram[offset+i].modified 9569 && hw->eeprom_shadow_ram[offset+i+1].modified) { 9570 data[i] = hw->eeprom_shadow_ram[offset+i].eeprom_word; 9571 data[i+1] = hw->eeprom_shadow_ram[offset+i+1].eeprom_word; 9572 continue; 9573 } 9574 act_offset = bank_offset + (offset + i) * 2; 9575 } 9576 error = em_read_ich8_dword(hw, act_offset, &dword); 9577 if (error != E1000_SUCCESS) 9578 break; 9579 if (hw->eeprom_shadow_ram != NULL 9580 && hw->eeprom_shadow_ram[offset+i].modified) { 9581 data[i] = hw->eeprom_shadow_ram[offset+i].eeprom_word; 9582 } else { 9583 if (add == 1) 9584 data[i] = dword >> 16; 9585 else 9586 data[i] = dword & 0xFFFFUL; 9587 } 9588 if (add == 1 || words-i == 1) 9589 continue; 9590 if (hw->eeprom_shadow_ram != NULL 9591 && hw->eeprom_shadow_ram[offset+i+1].modified) { 9592 data[i+1] = 9593 hw->eeprom_shadow_ram[offset+i+1].eeprom_word; 9594 } else { 9595 data[i+1] = dword >> 16; 9596 } 9597 } 9598 9599 em_release_software_flag(hw); 9600 9601 return error; 9602 } 9603 9604 /****************************************************************************** 9605 * Reads a 16 bit word or words from the EEPROM using the ICH8's flash access 9606 * register. 9607 * 9608 * hw - Struct containing variables accessed by shared code 9609 * offset - offset of word in the EEPROM to read 9610 * data - word read from the EEPROM 9611 * words - number of words to read 9612 *****************************************************************************/ 9613 STATIC int32_t 9614 em_read_eeprom_ich8(struct em_hw *hw, uint16_t offset, uint16_t words, 9615 uint16_t *data) 9616 { 9617 int32_t error = E1000_SUCCESS; 9618 uint32_t flash_bank = 0; 9619 uint32_t act_offset = 0; 9620 uint32_t bank_offset = 0; 9621 uint16_t word = 0; 9622 uint16_t i = 0; 9623 /* 9624 * We need to know which is the valid flash bank. In the event that 9625 * we didn't allocate eeprom_shadow_ram, we may not be managing 9626 * flash_bank. So it cannot be trusted and needs to be updated with 9627 * each read. 9628 */ 9629 9630 if (hw->mac_type == em_pch_spt) 9631 return em_read_eeprom_spt(hw, offset, words, data); 9632 9633 error = em_get_software_flag(hw); 9634 if (error != E1000_SUCCESS) 9635 return error; 9636 9637 error = em_valid_nvm_bank_detect_ich8lan(hw, &flash_bank); 9638 if (error != E1000_SUCCESS) { 9639 DEBUGOUT("Could not detect valid bank, assuming bank 0\n"); 9640 flash_bank = 0; 9641 } 9642 9643 /* 9644 * Adjust offset appropriately if we're on bank 1 - adjust for word 9645 * size 9646 */ 9647 bank_offset = flash_bank * (hw->flash_bank_size * 2); 9648 9649 for (i = 0; i < words; i++) { 9650 if (hw->eeprom_shadow_ram != NULL && 9651 hw->eeprom_shadow_ram[offset + i].modified == TRUE) { 9652 data[i] = 9653 hw->eeprom_shadow_ram[offset + i].eeprom_word; 9654 } else { 9655 /* The NVM part needs a byte offset, hence * 2 */ 9656 act_offset = bank_offset + ((offset + i) * 2); 9657 error = em_read_ich8_word(hw, act_offset, &word); 9658 if (error != E1000_SUCCESS) 9659 break; 9660 data[i] = word; 9661 } 9662 } 9663 9664 em_release_software_flag(hw); 9665 9666 return error; 9667 } 9668 9669 /****************************************************************************** 9670 * Writes a 16 bit word or words to the EEPROM using the ICH8's flash access 9671 * register. Actually, writes are written to the shadow ram cache in the hw 9672 * structure hw->em_shadow_ram. em_commit_shadow_ram flushes this to 9673 * the NVM, which occurs when the NVM checksum is updated. 9674 * 9675 * hw - Struct containing variables accessed by shared code 9676 * offset - offset of word in the EEPROM to write 9677 * words - number of words to write 9678 * data - words to write to the EEPROM 9679 *****************************************************************************/ 9680 STATIC int32_t 9681 em_write_eeprom_ich8(struct em_hw *hw, uint16_t offset, uint16_t words, 9682 uint16_t *data) 9683 { 9684 uint32_t i = 0; 9685 int32_t error = E1000_SUCCESS; 9686 error = em_get_software_flag(hw); 9687 if (error != E1000_SUCCESS) 9688 return error; 9689 /* 9690 * A driver can write to the NVM only if it has eeprom_shadow_ram 9691 * allocated. Subsequent reads to the modified words are read from 9692 * this cached structure as well. Writes will only go into this 9693 * cached structure unless it's followed by a call to 9694 * em_update_eeprom_checksum() where it will commit the changes and 9695 * clear the "modified" field. 9696 */ 9697 if (hw->eeprom_shadow_ram != NULL) { 9698 for (i = 0; i < words; i++) { 9699 if ((offset + i) < E1000_SHADOW_RAM_WORDS) { 9700 hw->eeprom_shadow_ram[offset + i].modified = 9701 TRUE; 9702 hw->eeprom_shadow_ram[offset + i].eeprom_word = 9703 data[i]; 9704 } else { 9705 error = -E1000_ERR_EEPROM; 9706 break; 9707 } 9708 } 9709 } else { 9710 /* 9711 * Drivers have the option to not allocate eeprom_shadow_ram 9712 * as long as they don't perform any NVM writes. An attempt 9713 * in doing so will result in this error. 9714 */ 9715 error = -E1000_ERR_EEPROM; 9716 } 9717 9718 em_release_software_flag(hw); 9719 9720 return error; 9721 } 9722 9723 /****************************************************************************** 9724 * This function does initial flash setup so that a new read/write/erase cycle 9725 * can be started. 9726 * 9727 * hw - The pointer to the hw structure 9728 ****************************************************************************/ 9729 STATIC int32_t 9730 em_ich8_cycle_init(struct em_hw *hw) 9731 { 9732 union ich8_hws_flash_status hsfsts; 9733 int32_t error = E1000_ERR_EEPROM; 9734 int32_t i = 0; 9735 DEBUGFUNC("em_ich8_cycle_init"); 9736 9737 if (hw->mac_type == em_pch_spt) 9738 hsfsts.regval = E1000_READ_ICH_FLASH_REG32(hw, 9739 ICH_FLASH_HSFSTS) & 0xFFFFUL; 9740 else 9741 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, 9742 ICH_FLASH_HSFSTS); 9743 9744 /* May be check the Flash Des Valid bit in Hw status */ 9745 if (hsfsts.hsf_status.fldesvalid == 0) { 9746 DEBUGOUT("Flash descriptor invalid. SW Sequencing must be" 9747 " used."); 9748 return error; 9749 } 9750 /* Clear FCERR in Hw status by writing 1 */ 9751 /* Clear DAEL in Hw status by writing a 1 */ 9752 hsfsts.hsf_status.flcerr = 1; 9753 hsfsts.hsf_status.dael = 1; 9754 if (hw->mac_type == em_pch_spt) 9755 E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_HSFSTS, 9756 hsfsts.regval & 0xFFFFUL); 9757 else 9758 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, 9759 hsfsts.regval); 9760 /* 9761 * Either we should have a hardware SPI cycle in progress bit to 9762 * check against, in order to start a new cycle or FDONE bit should 9763 * be changed in the hardware so that it is 1 after hardware reset, 9764 * which can then be used as an indication whether a cycle is in 9765 * progress or has been completed .. we should also have some 9766 * software semaphore mechanism to guard FDONE or the cycle in 9767 * progress bit so that two threads access to those bits can be 9768 * sequentiallized or a way so that 2 threads dont start the cycle at 9769 * the same time 9770 */ 9771 9772 if (hsfsts.hsf_status.flcinprog == 0) { 9773 /* 9774 * There is no cycle running at present, so we can start a 9775 * cycle 9776 */ 9777 /* Begin by setting Flash Cycle Done. */ 9778 hsfsts.hsf_status.flcdone = 1; 9779 if (hw->mac_type == em_pch_spt) 9780 E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_HSFSTS, 9781 hsfsts.regval & 0xFFFFUL); 9782 else 9783 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, 9784 hsfsts.regval); 9785 error = E1000_SUCCESS; 9786 } else { 9787 /* 9788 * otherwise poll for sometime so the current cycle has a 9789 * chance to end before giving up. 9790 */ 9791 for (i = 0; i < ICH_FLASH_COMMAND_TIMEOUT; i++) { 9792 if (hw->mac_type == em_pch_spt) 9793 hsfsts.regval = E1000_READ_ICH_FLASH_REG32( 9794 hw, ICH_FLASH_HSFSTS) & 0xFFFFUL; 9795 else 9796 hsfsts.regval = E1000_READ_ICH_FLASH_REG16( 9797 hw, ICH_FLASH_HSFSTS); 9798 if (hsfsts.hsf_status.flcinprog == 0) { 9799 error = E1000_SUCCESS; 9800 break; 9801 } 9802 usec_delay(1); 9803 } 9804 if (error == E1000_SUCCESS) { 9805 /* 9806 * Successful in waiting for previous cycle to 9807 * timeout, now set the Flash Cycle Done. 9808 */ 9809 hsfsts.hsf_status.flcdone = 1; 9810 if (hw->mac_type == em_pch_spt) 9811 E1000_WRITE_ICH_FLASH_REG32(hw, 9812 ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFFUL); 9813 else 9814 E1000_WRITE_ICH_FLASH_REG16(hw, 9815 ICH_FLASH_HSFSTS, hsfsts.regval); 9816 } else { 9817 DEBUGOUT("Flash controller busy, cannot get access"); 9818 } 9819 } 9820 return error; 9821 } 9822 9823 /****************************************************************************** 9824 * This function starts a flash cycle and waits for its completion 9825 * 9826 * hw - The pointer to the hw structure 9827 *****************************************************************************/ 9828 STATIC int32_t 9829 em_ich8_flash_cycle(struct em_hw *hw, uint32_t timeout) 9830 { 9831 union ich8_hws_flash_ctrl hsflctl; 9832 union ich8_hws_flash_status hsfsts; 9833 int32_t error = E1000_ERR_EEPROM; 9834 uint32_t i = 0; 9835 9836 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ 9837 if (hw->mac_type == em_pch_spt) 9838 hsflctl.regval = E1000_READ_ICH_FLASH_REG32(hw, 9839 ICH_FLASH_HSFSTS) >> 16; 9840 else 9841 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, 9842 ICH_FLASH_HSFCTL); 9843 hsflctl.hsf_ctrl.flcgo = 1; 9844 9845 if (hw->mac_type == em_pch_spt) 9846 E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_HSFSTS, 9847 (uint32_t)hsflctl.regval << 16); 9848 else 9849 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, 9850 hsflctl.regval); 9851 9852 /* wait till FDONE bit is set to 1 */ 9853 do { 9854 if (hw->mac_type == em_pch_spt) 9855 hsfsts.regval = E1000_READ_ICH_FLASH_REG32(hw, 9856 ICH_FLASH_HSFSTS) & 0xFFFFUL; 9857 else 9858 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, 9859 ICH_FLASH_HSFSTS); 9860 if (hsfsts.hsf_status.flcdone == 1) 9861 break; 9862 usec_delay(1); 9863 i++; 9864 } while (i < timeout); 9865 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) { 9866 error = E1000_SUCCESS; 9867 } 9868 return error; 9869 } 9870 9871 /****************************************************************************** 9872 * Reads a byte or word from the NVM using the ICH8 flash access registers. 9873 * 9874 * hw - The pointer to the hw structure 9875 * index - The index of the byte or word to read. 9876 * size - Size of data to read, 1=byte 2=word 9877 * data - Pointer to the word to store the value read. 9878 *****************************************************************************/ 9879 STATIC int32_t 9880 em_read_ich8_data(struct em_hw *hw, uint32_t index, uint32_t size, 9881 uint16_t *data) 9882 { 9883 union ich8_hws_flash_status hsfsts; 9884 union ich8_hws_flash_ctrl hsflctl; 9885 uint32_t flash_linear_address; 9886 uint32_t flash_data = 0; 9887 int32_t error = -E1000_ERR_EEPROM; 9888 int32_t count = 0; 9889 DEBUGFUNC("em_read_ich8_data"); 9890 9891 if (size < 1 || size > 2 || data == 0x0 || 9892 index > ICH_FLASH_LINEAR_ADDR_MASK) 9893 return error; 9894 9895 flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) + 9896 hw->flash_base_addr; 9897 9898 do { 9899 usec_delay(1); 9900 /* Steps */ 9901 error = em_ich8_cycle_init(hw); 9902 if (error != E1000_SUCCESS) 9903 break; 9904 9905 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, 9906 ICH_FLASH_HSFCTL); 9907 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 9908 hsflctl.hsf_ctrl.fldbcount = size - 1; 9909 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; 9910 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, 9911 hsflctl.regval); 9912 /* 9913 * Write the last 24 bits of index into Flash Linear address 9914 * field in Flash Address 9915 */ 9916 /* TODO: TBD maybe check the index against the size of flash */ 9917 9918 E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_FADDR, 9919 flash_linear_address); 9920 9921 error = em_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT); 9922 /* 9923 * Check if FCERR is set to 1, if set to 1, clear it and try 9924 * the whole sequence a few more times, else read in (shift 9925 * in) the Flash Data0, the order is least significant byte 9926 * first msb to lsb 9927 */ 9928 if (error == E1000_SUCCESS) { 9929 flash_data = E1000_READ_ICH_FLASH_REG(hw, 9930 ICH_FLASH_FDATA0); 9931 if (size == 1) { 9932 *data = (uint8_t) (flash_data & 0x000000FF); 9933 } else if (size == 2) { 9934 *data = (uint16_t) (flash_data & 0x0000FFFF); 9935 } 9936 break; 9937 } else { 9938 /* 9939 * If we've gotten here, then things are probably 9940 * completely hosed, but if the error condition is 9941 * detected, it won't hurt to give it another 9942 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 9943 */ 9944 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, 9945 ICH_FLASH_HSFSTS); 9946 if (hsfsts.hsf_status.flcerr == 1) { 9947 /* Repeat for some time before giving up. */ 9948 continue; 9949 } else if (hsfsts.hsf_status.flcdone == 0) { 9950 DEBUGOUT("Timeout error - flash cycle did not" 9951 " complete."); 9952 break; 9953 } 9954 } 9955 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 9956 9957 return error; 9958 } 9959 9960 STATIC int32_t 9961 em_read_ich8_data32(struct em_hw *hw, uint32_t offset, uint32_t *data) 9962 { 9963 union ich8_hws_flash_status hsfsts; 9964 union ich8_hws_flash_ctrl hsflctl; 9965 uint32_t flash_linear_address; 9966 int32_t error = -E1000_ERR_EEPROM; 9967 uint32_t count = 0; 9968 DEBUGFUNC("em_read_ich8_data32"); 9969 9970 if (hw->mac_type != em_pch_spt) 9971 return error; 9972 if (offset > ICH_FLASH_LINEAR_ADDR_MASK) 9973 return error; 9974 flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & offset) + 9975 hw->flash_base_addr; 9976 9977 do { 9978 usec_delay(1); 9979 /* Steps */ 9980 error = em_ich8_cycle_init(hw); 9981 if (error != E1000_SUCCESS) 9982 break; 9983 9984 /* 32 bit accesses in SPT. */ 9985 hsflctl.regval = E1000_READ_ICH_FLASH_REG32(hw, 9986 ICH_FLASH_HSFSTS) >> 16; 9987 9988 hsflctl.hsf_ctrl.fldbcount = sizeof(uint32_t) - 1; 9989 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; 9990 9991 E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_HSFSTS, 9992 (uint32_t)hsflctl.regval << 16); 9993 /* 9994 * Write the last 24 bits of offset into Flash Linear address 9995 * field in Flash Address 9996 */ 9997 /* TODO: TBD maybe check the offset against the size of flash */ 9998 9999 E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_FADDR, 10000 flash_linear_address); 10001 10002 error = em_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT); 10003 /* 10004 * Check if FCERR is set to 1, if set to 1, clear it and try 10005 * the whole sequence a few more times, else read in (shift 10006 * in) the Flash Data0, the order is least significant byte 10007 * first msb to lsb 10008 */ 10009 if (error == E1000_SUCCESS) { 10010 (*data) = (uint32_t)E1000_READ_ICH_FLASH_REG32(hw, 10011 ICH_FLASH_FDATA0); 10012 break; 10013 } else { 10014 /* 10015 * If we've gotten here, then things are probably 10016 * completely hosed, but if the error condition is 10017 * detected, it won't hurt to give it another 10018 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 10019 */ 10020 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, 10021 ICH_FLASH_HSFSTS); 10022 if (hsfsts.hsf_status.flcerr == 1) { 10023 /* Repeat for some time before giving up. */ 10024 continue; 10025 } else if (hsfsts.hsf_status.flcdone == 0) { 10026 DEBUGOUT("Timeout error - flash cycle did not" 10027 " complete."); 10028 break; 10029 } 10030 } 10031 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 10032 10033 return error; 10034 } 10035 10036 10037 /****************************************************************************** 10038 * Writes One /two bytes to the NVM using the ICH8 flash access registers. 10039 * 10040 * hw - The pointer to the hw structure 10041 * index - The index of the byte/word to write. 10042 * size - Size of data to read, 1=byte 2=word 10043 * data - The byte(s) to write to the NVM. 10044 *****************************************************************************/ 10045 STATIC int32_t 10046 em_write_ich8_data(struct em_hw *hw, uint32_t index, uint32_t size, 10047 uint16_t data) 10048 { 10049 union ich8_hws_flash_status hsfsts; 10050 union ich8_hws_flash_ctrl hsflctl; 10051 uint32_t flash_linear_address; 10052 uint32_t flash_data = 0; 10053 int32_t error = -E1000_ERR_EEPROM; 10054 int32_t count = 0; 10055 DEBUGFUNC("em_write_ich8_data"); 10056 10057 if (hw->mac_type == em_pch_spt) 10058 return -E1000_ERR_EEPROM; 10059 if (size < 1 || size > 2 || data > size * 0xff || 10060 index > ICH_FLASH_LINEAR_ADDR_MASK) 10061 return error; 10062 10063 flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) + 10064 hw->flash_base_addr; 10065 10066 do { 10067 usec_delay(1); 10068 /* Steps */ 10069 error = em_ich8_cycle_init(hw); 10070 if (error != E1000_SUCCESS) 10071 break; 10072 10073 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, 10074 ICH_FLASH_HSFCTL); 10075 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 10076 hsflctl.hsf_ctrl.fldbcount = size - 1; 10077 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; 10078 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, 10079 hsflctl.regval); 10080 /* 10081 * Write the last 24 bits of index into Flash Linear address 10082 * field in Flash Address 10083 */ 10084 E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_FADDR, 10085 flash_linear_address); 10086 10087 if (size == 1) 10088 flash_data = (uint32_t) data & 0x00FF; 10089 else 10090 flash_data = (uint32_t) data; 10091 10092 E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_FDATA0, flash_data); 10093 /* 10094 * check if FCERR is set to 1 , if set to 1, clear it and try 10095 * the whole sequence a few more times else done 10096 */ 10097 error = em_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT); 10098 if (error == E1000_SUCCESS) { 10099 break; 10100 } else { 10101 /* 10102 * If we're here, then things are most likely 10103 * completely hosed, but if the error condition is 10104 * detected, it won't hurt to give it another 10105 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 10106 */ 10107 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, 10108 ICH_FLASH_HSFSTS); 10109 if (hsfsts.hsf_status.flcerr == 1) { 10110 /* Repeat for some time before giving up. */ 10111 continue; 10112 } else if (hsfsts.hsf_status.flcdone == 0) { 10113 DEBUGOUT("Timeout error - flash cycle did not" 10114 " complete."); 10115 break; 10116 } 10117 } 10118 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 10119 10120 return error; 10121 } 10122 10123 /****************************************************************************** 10124 * Reads a single byte from the NVM using the ICH8 flash access registers. 10125 * 10126 * hw - pointer to em_hw structure 10127 * index - The index of the byte to read. 10128 * data - Pointer to a byte to store the value read. 10129 *****************************************************************************/ 10130 STATIC int32_t 10131 em_read_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t *data) 10132 { 10133 int32_t status = E1000_SUCCESS; 10134 uint16_t word = 0; 10135 10136 if (hw->mac_type == em_pch_spt) 10137 return -E1000_ERR_EEPROM; 10138 else 10139 status = em_read_ich8_data(hw, index, 1, &word); 10140 if (status == E1000_SUCCESS) { 10141 *data = (uint8_t) word; 10142 } 10143 return status; 10144 } 10145 10146 /****************************************************************************** 10147 * Writes a single byte to the NVM using the ICH8 flash access registers. 10148 * Performs verification by reading back the value and then going through 10149 * a retry algorithm before giving up. 10150 * 10151 * hw - pointer to em_hw structure 10152 * index - The index of the byte to write. 10153 * byte - The byte to write to the NVM. 10154 *****************************************************************************/ 10155 STATIC int32_t 10156 em_verify_write_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t byte) 10157 { 10158 int32_t error = E1000_SUCCESS; 10159 int32_t program_retries = 0; 10160 DEBUGOUT2("Byte := %2.2X Offset := %d\n", byte, index); 10161 10162 error = em_write_ich8_byte(hw, index, byte); 10163 10164 if (error != E1000_SUCCESS) { 10165 for (program_retries = 0; program_retries < 100; 10166 program_retries++) { 10167 DEBUGOUT2("Retrying \t Byte := %2.2X Offset := %d\n", 10168 byte, index); 10169 error = em_write_ich8_byte(hw, index, byte); 10170 usec_delay(100); 10171 if (error == E1000_SUCCESS) 10172 break; 10173 } 10174 } 10175 if (program_retries == 100) 10176 error = E1000_ERR_EEPROM; 10177 10178 return error; 10179 } 10180 10181 /****************************************************************************** 10182 * Writes a single byte to the NVM using the ICH8 flash access registers. 10183 * 10184 * hw - pointer to em_hw structure 10185 * index - The index of the byte to read. 10186 * data - The byte to write to the NVM. 10187 *****************************************************************************/ 10188 STATIC int32_t 10189 em_write_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t data) 10190 { 10191 int32_t status = E1000_SUCCESS; 10192 uint16_t word = (uint16_t) data; 10193 status = em_write_ich8_data(hw, index, 1, word); 10194 10195 return status; 10196 } 10197 10198 /****************************************************************************** 10199 * Reads a dword from the NVM using the ICH8 flash access registers. 10200 * 10201 * hw - pointer to em_hw structure 10202 * index - The starting BYTE index of the word to read. 10203 * data - Pointer to a word to store the value read. 10204 *****************************************************************************/ 10205 STATIC int32_t 10206 em_read_ich8_dword(struct em_hw *hw, uint32_t index, uint32_t *data) 10207 { 10208 int32_t status = E1000_SUCCESS; 10209 status = em_read_ich8_data32(hw, index, data); 10210 return status; 10211 } 10212 10213 /****************************************************************************** 10214 * Reads a word from the NVM using the ICH8 flash access registers. 10215 * 10216 * hw - pointer to em_hw structure 10217 * index - The starting byte index of the word to read. 10218 * data - Pointer to a word to store the value read. 10219 *****************************************************************************/ 10220 STATIC int32_t 10221 em_read_ich8_word(struct em_hw *hw, uint32_t index, uint16_t *data) 10222 { 10223 int32_t status = E1000_SUCCESS; 10224 status = em_read_ich8_data(hw, index, 2, data); 10225 return status; 10226 } 10227 10228 /****************************************************************************** 10229 * Erases the bank specified. Each bank may be a 4, 8 or 64k block. Banks are 0 10230 * based. 10231 * 10232 * hw - pointer to em_hw structure 10233 * bank - 0 for first bank, 1 for second bank 10234 * 10235 * Note that this function may actually erase as much as 8 or 64 KBytes. The 10236 * amount of NVM used in each bank is a *minimum* of 4 KBytes, but in fact the 10237 * bank size may be 4, 8 or 64 KBytes 10238 *****************************************************************************/ 10239 int32_t 10240 em_erase_ich8_4k_segment(struct em_hw *hw, uint32_t bank) 10241 { 10242 union ich8_hws_flash_status hsfsts; 10243 union ich8_hws_flash_ctrl hsflctl; 10244 uint32_t flash_linear_address; 10245 int32_t count = 0; 10246 int32_t error = E1000_ERR_EEPROM; 10247 int32_t iteration; 10248 int32_t sub_sector_size = 0; 10249 int32_t bank_size; 10250 int32_t j = 0; 10251 int32_t error_flag = 0; 10252 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 10253 /* 10254 * Determine HW Sector size: Read BERASE bits of Hw flash Status 10255 * register 10256 */ 10257 /* 10258 * 00: The Hw sector is 256 bytes, hence we need to erase 16 10259 * consecutive sectors. The start index for the nth Hw sector can be 10260 * calculated as bank * 4096 + n * 256 01: The Hw sector is 4K bytes, 10261 * hence we need to erase 1 sector. The start index for the nth Hw 10262 * sector can be calculated as bank * 4096 10: The HW sector is 8K 10263 * bytes 11: The Hw sector size is 64K bytes 10264 */ 10265 if (hsfsts.hsf_status.berasesz == 0x0) { 10266 /* Hw sector size 256 */ 10267 sub_sector_size = ICH_FLASH_SEG_SIZE_256; 10268 bank_size = ICH_FLASH_SECTOR_SIZE; 10269 iteration = ICH_FLASH_SECTOR_SIZE / ICH_FLASH_SEG_SIZE_256; 10270 } else if (hsfsts.hsf_status.berasesz == 0x1) { 10271 bank_size = ICH_FLASH_SEG_SIZE_4K; 10272 iteration = 1; 10273 } else if (hsfsts.hsf_status.berasesz == 0x2) { 10274 if (hw->mac_type == em_ich9lan) { 10275 uint32_t gfpreg, sector_base_addr, sector_end_addr; 10276 gfpreg = E1000_READ_ICH_FLASH_REG(hw, 10277 ICH_FLASH_GFPREG); 10278 /* 10279 * sector_X_addr is a "sector"-aligned address (4096 bytes) 10280 * Add 1 to sector_end_addr since this sector is included in 10281 * the overall size. 10282 */ 10283 sector_base_addr = gfpreg & ICH_GFPREG_BASE_MASK; 10284 sector_end_addr = 10285 ((gfpreg >> 16) & ICH_GFPREG_BASE_MASK) + 1; 10286 10287 /* 10288 * find total size of the NVM, then cut in half since the total 10289 * size represents two separate NVM banks. 10290 */ 10291 bank_size = (sector_end_addr - sector_base_addr) 10292 << ICH_FLASH_SECT_ADDR_SHIFT; 10293 bank_size /= 2; 10294 /* Word align */ 10295 bank_size = 10296 (bank_size / sizeof(uint16_t)) * sizeof(uint16_t); 10297 10298 sub_sector_size = ICH_FLASH_SEG_SIZE_8K; 10299 iteration = bank_size / ICH_FLASH_SEG_SIZE_8K; 10300 } else { 10301 return error; 10302 } 10303 } else if (hsfsts.hsf_status.berasesz == 0x3) { 10304 bank_size = ICH_FLASH_SEG_SIZE_64K; 10305 iteration = 1; 10306 } else { 10307 return error; 10308 } 10309 10310 for (j = 0; j < iteration; j++) { 10311 do { 10312 count++; 10313 /* Steps */ 10314 error = em_ich8_cycle_init(hw); 10315 if (error != E1000_SUCCESS) { 10316 error_flag = 1; 10317 break; 10318 } 10319 /* 10320 * Write a value 11 (block Erase) in Flash Cycle 10321 * field in Hw flash Control 10322 */ 10323 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, 10324 ICH_FLASH_HSFCTL); 10325 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE; 10326 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, 10327 hsflctl.regval); 10328 /* 10329 * Write the last 24 bits of an index within the 10330 * block into Flash Linear address field in Flash 10331 * Address. This probably needs to be calculated 10332 * here based off the on-chip erase sector size and 10333 * the software bank size (4, 8 or 64 KBytes) 10334 */ 10335 flash_linear_address = 10336 bank * bank_size + j * sub_sector_size; 10337 flash_linear_address += hw->flash_base_addr; 10338 flash_linear_address &= ICH_FLASH_LINEAR_ADDR_MASK; 10339 10340 E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_FADDR, 10341 flash_linear_address); 10342 10343 error = 10344 em_ich8_flash_cycle(hw, ICH_FLASH_ERASE_TIMEOUT); 10345 /* 10346 * Check if FCERR is set to 1. If 1, clear it and 10347 * try the whole sequence a few more times else Done 10348 */ 10349 if (error == E1000_SUCCESS) { 10350 break; 10351 } else { 10352 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, 10353 ICH_FLASH_HSFSTS); 10354 if (hsfsts.hsf_status.flcerr == 1) { 10355 /* 10356 * repeat for some time before giving 10357 * up 10358 */ 10359 continue; 10360 } else if (hsfsts.hsf_status.flcdone == 0) { 10361 error_flag = 1; 10362 break; 10363 } 10364 } 10365 } while ((count < ICH_FLASH_CYCLE_REPEAT_COUNT) && !error_flag); 10366 if (error_flag == 1) 10367 break; 10368 } 10369 if (error_flag != 1) 10370 error = E1000_SUCCESS; 10371 return error; 10372 } 10373 10374 /****************************************************************************** 10375 * Reads 16-bit words from the OTP. Return error when the word is not 10376 * stored in OTP. 10377 * 10378 * hw - Struct containing variables accessed by shared code 10379 * offset - offset of word in the OTP to read 10380 * data - word read from the OTP 10381 * words - number of words to read 10382 *****************************************************************************/ 10383 STATIC int32_t 10384 em_read_invm_i210(struct em_hw *hw, uint16_t offset, uint16_t words, 10385 uint16_t *data) 10386 { 10387 int32_t ret_val = E1000_SUCCESS; 10388 10389 switch (offset) 10390 { 10391 case EEPROM_MAC_ADDR_WORD0: 10392 case EEPROM_MAC_ADDR_WORD1: 10393 case EEPROM_MAC_ADDR_WORD2: 10394 /* Generate random MAC address if there's none. */ 10395 ret_val = em_read_invm_word_i210(hw, offset, data); 10396 if (ret_val != E1000_SUCCESS) { 10397 DEBUGOUT("MAC Addr not found in iNVM\n"); 10398 *data = 0xFFFF; 10399 ret_val = E1000_SUCCESS; 10400 } 10401 break; 10402 case EEPROM_INIT_CONTROL2_REG: 10403 ret_val = em_read_invm_word_i210(hw, offset, data); 10404 if (ret_val != E1000_SUCCESS) { 10405 *data = NVM_INIT_CTRL_2_DEFAULT_I211; 10406 ret_val = E1000_SUCCESS; 10407 } 10408 break; 10409 case EEPROM_INIT_CONTROL4_REG: 10410 ret_val = em_read_invm_word_i210(hw, offset, data); 10411 if (ret_val != E1000_SUCCESS) { 10412 *data = NVM_INIT_CTRL_4_DEFAULT_I211; 10413 ret_val = E1000_SUCCESS; 10414 } 10415 break; 10416 case EEPROM_LED_1_CFG: 10417 ret_val = em_read_invm_word_i210(hw, offset, data); 10418 if (ret_val != E1000_SUCCESS) { 10419 *data = NVM_LED_1_CFG_DEFAULT_I211; 10420 ret_val = E1000_SUCCESS; 10421 } 10422 break; 10423 case EEPROM_LED_0_2_CFG: 10424 ret_val = em_read_invm_word_i210(hw, offset, data); 10425 if (ret_val != E1000_SUCCESS) { 10426 *data = NVM_LED_0_2_CFG_DEFAULT_I211; 10427 ret_val = E1000_SUCCESS; 10428 } 10429 break; 10430 case EEPROM_ID_LED_SETTINGS: 10431 ret_val = em_read_invm_word_i210(hw, offset, data); 10432 if (ret_val != E1000_SUCCESS) { 10433 *data = ID_LED_RESERVED_FFFF; 10434 ret_val = E1000_SUCCESS; 10435 } 10436 break; 10437 default: 10438 DEBUGOUT1("NVM word 0x%02x is not mapped.\n", offset); 10439 *data = NVM_RESERVED_WORD; 10440 break; 10441 } 10442 10443 return ret_val; 10444 } 10445 10446 /****************************************************************************** 10447 * Reads 16-bit words from the OTP. Return error when the word is not 10448 * stored in OTP. 10449 * 10450 * hw - Struct containing variables accessed by shared code 10451 * offset - offset of word in the OTP to read 10452 * data - word read from the OTP 10453 *****************************************************************************/ 10454 STATIC int32_t 10455 em_read_invm_word_i210(struct em_hw *hw, uint16_t address, uint16_t *data) 10456 { 10457 int32_t error = -E1000_NOT_IMPLEMENTED; 10458 uint32_t invm_dword; 10459 uint16_t i; 10460 uint8_t record_type, word_address; 10461 10462 for (i = 0; i < INVM_SIZE; i++) { 10463 invm_dword = EM_READ_REG(hw, E1000_INVM_DATA_REG(i)); 10464 /* Get record type */ 10465 record_type = INVM_DWORD_TO_RECORD_TYPE(invm_dword); 10466 if (record_type == INVM_UNINITIALIZED_STRUCTURE) 10467 break; 10468 if (record_type == INVM_CSR_AUTOLOAD_STRUCTURE) 10469 i += INVM_CSR_AUTOLOAD_DATA_SIZE_IN_DWORDS; 10470 if (record_type == INVM_RSA_KEY_SHA256_STRUCTURE) 10471 i += INVM_RSA_KEY_SHA256_DATA_SIZE_IN_DWORDS; 10472 if (record_type == INVM_WORD_AUTOLOAD_STRUCTURE) { 10473 word_address = INVM_DWORD_TO_WORD_ADDRESS(invm_dword); 10474 if (word_address == address) { 10475 *data = INVM_DWORD_TO_WORD_DATA(invm_dword); 10476 error = E1000_SUCCESS; 10477 break; 10478 } 10479 } 10480 } 10481 10482 return error; 10483 } 10484 10485 STATIC int32_t 10486 em_init_lcd_from_nvm_config_region(struct em_hw *hw, uint32_t cnf_base_addr, 10487 uint32_t cnf_size) 10488 { 10489 uint32_t ret_val = E1000_SUCCESS; 10490 uint16_t word_addr, reg_data, reg_addr; 10491 uint16_t i; 10492 /* cnf_base_addr is in DWORD */ 10493 word_addr = (uint16_t) (cnf_base_addr << 1); 10494 10495 /* cnf_size is returned in size of dwords */ 10496 for (i = 0; i < cnf_size; i++) { 10497 ret_val = 10498 em_read_eeprom(hw, (word_addr + i * 2), 1, ®_data); 10499 if (ret_val) 10500 return ret_val; 10501 10502 ret_val = 10503 em_read_eeprom(hw, (word_addr + i * 2 + 1), 1, ®_addr); 10504 if (ret_val) 10505 return ret_val; 10506 10507 ret_val = em_get_software_flag(hw); 10508 if (ret_val != E1000_SUCCESS) 10509 return ret_val; 10510 10511 ret_val = 10512 em_write_phy_reg_ex(hw, (uint32_t) reg_addr, reg_data); 10513 10514 em_release_software_flag(hw); 10515 } 10516 10517 return ret_val; 10518 } 10519 10520 /****************************************************************************** 10521 * This function initializes the PHY from the NVM on ICH8 platforms. This 10522 * is needed due to an issue where the NVM configuration is not properly 10523 * autoloaded after power transitions. Therefore, after each PHY reset, we 10524 * will load the configuration data out of the NVM manually. 10525 * 10526 * hw: Struct containing variables accessed by shared code 10527 *****************************************************************************/ 10528 STATIC int32_t 10529 em_init_lcd_from_nvm(struct em_hw *hw) 10530 { 10531 uint32_t reg_data, cnf_base_addr, cnf_size, ret_val, loop, sw_cfg_mask; 10532 if (hw->phy_type != em_phy_igp_3) 10533 return E1000_SUCCESS; 10534 10535 /* Check if SW needs configure the PHY */ 10536 if (hw->device_id == E1000_DEV_ID_ICH8_IGP_M_AMT || 10537 hw->device_id == E1000_DEV_ID_ICH8_IGP_M || 10538 hw->mac_type == em_pchlan || 10539 hw->mac_type == em_pch2lan || 10540 hw->mac_type == em_pch_lpt || 10541 hw->mac_type == em_pch_spt) 10542 sw_cfg_mask = FEXTNVM_SW_CONFIG_ICH8M; 10543 else 10544 sw_cfg_mask = FEXTNVM_SW_CONFIG; 10545 10546 reg_data = E1000_READ_REG(hw, FEXTNVM); 10547 if (!(reg_data & sw_cfg_mask)) 10548 return E1000_SUCCESS; 10549 10550 /* Wait for basic configuration completes before proceeding */ 10551 loop = 0; 10552 do { 10553 reg_data = 10554 E1000_READ_REG(hw, STATUS) & E1000_STATUS_LAN_INIT_DONE; 10555 usec_delay(100); 10556 loop++; 10557 } while ((!reg_data) && (loop < 50)); 10558 10559 /* Clear the Init Done bit for the next init event */ 10560 reg_data = E1000_READ_REG(hw, STATUS); 10561 reg_data &= ~E1000_STATUS_LAN_INIT_DONE; 10562 E1000_WRITE_REG(hw, STATUS, reg_data); 10563 /* 10564 * Make sure HW does not configure LCD from PHY extended 10565 * configuration before SW configuration 10566 */ 10567 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL); 10568 if ((reg_data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) == 0x0000) { 10569 reg_data = E1000_READ_REG(hw, EXTCNF_SIZE); 10570 cnf_size = reg_data & E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH; 10571 cnf_size >>= 16; 10572 if (cnf_size) { 10573 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL); 10574 cnf_base_addr = reg_data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER; 10575 /* cnf_base_addr is in DWORD */ 10576 cnf_base_addr >>= 16; 10577 10578 /* Configure LCD from extended configuration region. */ 10579 ret_val = em_init_lcd_from_nvm_config_region(hw, 10580 cnf_base_addr, cnf_size); 10581 if (ret_val) 10582 return ret_val; 10583 } 10584 } 10585 return E1000_SUCCESS; 10586 } 10587 10588 /****************************************************************************** 10589 * em_set_pciex_completion_timeout - set pci-e completion timeout 10590 * 10591 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms, 10592 * however the hardware default for these parts is 500us to 1ms which is less 10593 * than the 10ms recommended by the pci-e spec. To address this we need to 10594 * increase the value to either 10ms to 200ms for capability version 1 config, 10595 * or 16ms to 55ms for version 2. 10596 * 10597 * * hw - pointer to em_hw structure 10598 *****************************************************************************/ 10599 int32_t 10600 em_set_pciex_completion_timeout(struct em_hw *hw) 10601 { 10602 uint32_t gcr = E1000_READ_REG(hw, GCR); 10603 int32_t ret_val = E1000_SUCCESS; 10604 10605 /* Only take action if timeout value is not set by system BIOS */ 10606 if (gcr & E1000_GCR_CMPL_TMOUT_MASK) 10607 goto out; 10608 10609 DEBUGOUT("PCIe completion timeout not set by system BIOS."); 10610 10611 /* 10612 * If capababilities version is type 1 we can write the 10613 * timeout of 10ms to 200ms through the GCR register 10614 */ 10615 10616 if (!(gcr & E1000_GCR_CAP_VER2)) { 10617 gcr |= E1000_GCR_CMPL_TMOUT_10ms; 10618 DEBUGOUT("PCIe capability version 1 detected, setting \ 10619 completion timeout to 10ms."); 10620 goto out; 10621 } 10622 10623 /* 10624 * For version 2 capabilities we need to write the config space 10625 * directly in order to set the completion timeout value for 10626 * 16ms to 55ms 10627 * 10628 * XXX: Implement em_*_pcie_cap_reg() first. 10629 */ 10630 #if 0 10631 ret_val = em_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 10632 &pciex_devctl2); 10633 10634 if (ret_val) 10635 goto out; 10636 10637 pciex_devctl2 |= PCIE_DEVICE_CONTROL2_16ms; 10638 10639 ret_val = em_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 10640 &pciex_devctl2); 10641 #endif 10642 10643 out: 10644 10645 /* Disable completion timeout resend */ 10646 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND; 10647 10648 DEBUGOUT("PCIe completion timeout resend disabled."); 10649 10650 E1000_WRITE_REG(hw, GCR, gcr); 10651 return ret_val; 10652 } 10653 10654 /*************************************************************************** 10655 * Set slow MDIO access mode 10656 ***************************************************************************/ 10657 static int32_t 10658 em_set_mdio_slow_mode_hv(struct em_hw *hw) 10659 { 10660 int32_t ret_val; 10661 uint16_t data; 10662 DEBUGFUNC("em_set_mdio_slow_mode_hv"); 10663 10664 ret_val = em_read_phy_reg(hw, HV_KMRN_MODE_CTRL, &data); 10665 if (ret_val) 10666 return ret_val; 10667 10668 data |= HV_KMRN_MDIO_SLOW; 10669 10670 ret_val = em_write_phy_reg(hw, HV_KMRN_MODE_CTRL, data); 10671 10672 return ret_val; 10673 } 10674 10675 /*************************************************************************** 10676 * A series of Phy workarounds to be done after every PHY reset. 10677 ***************************************************************************/ 10678 int32_t 10679 em_hv_phy_workarounds_ich8lan(struct em_hw *hw) 10680 { 10681 int32_t ret_val = E1000_SUCCESS; 10682 uint16_t phy_data; 10683 uint16_t swfw; 10684 DEBUGFUNC("em_hv_phy_workarounds_ich8lan"); 10685 10686 if (hw->mac_type != em_pchlan) 10687 goto out; 10688 10689 swfw = E1000_SWFW_PHY0_SM; 10690 10691 /* Set MDIO slow mode before any other MDIO access */ 10692 if (hw->phy_type == em_phy_82577 || 10693 hw->phy_type == em_phy_82578) { 10694 ret_val = em_set_mdio_slow_mode_hv(hw); 10695 if (ret_val) 10696 goto out; 10697 } 10698 10699 /* Hanksville M Phy init for IEEE. */ 10700 if ((hw->revision_id == 2) && 10701 (hw->phy_type == em_phy_82577) && 10702 ((hw->phy_revision == 2) || (hw->phy_revision == 3))) { 10703 em_write_phy_reg(hw, 0x10, 0x8823); 10704 em_write_phy_reg(hw, 0x11, 0x0018); 10705 em_write_phy_reg(hw, 0x10, 0x8824); 10706 em_write_phy_reg(hw, 0x11, 0x0016); 10707 em_write_phy_reg(hw, 0x10, 0x8825); 10708 em_write_phy_reg(hw, 0x11, 0x001A); 10709 em_write_phy_reg(hw, 0x10, 0x888C); 10710 em_write_phy_reg(hw, 0x11, 0x0007); 10711 em_write_phy_reg(hw, 0x10, 0x888D); 10712 em_write_phy_reg(hw, 0x11, 0x0007); 10713 em_write_phy_reg(hw, 0x10, 0x888E); 10714 em_write_phy_reg(hw, 0x11, 0x0007); 10715 em_write_phy_reg(hw, 0x10, 0x8827); 10716 em_write_phy_reg(hw, 0x11, 0x0001); 10717 em_write_phy_reg(hw, 0x10, 0x8835); 10718 em_write_phy_reg(hw, 0x11, 0x0001); 10719 em_write_phy_reg(hw, 0x10, 0x8834); 10720 em_write_phy_reg(hw, 0x11, 0x0001); 10721 em_write_phy_reg(hw, 0x10, 0x8833); 10722 em_write_phy_reg(hw, 0x11, 0x0002); 10723 } 10724 10725 if (((hw->phy_type == em_phy_82577) && 10726 ((hw->phy_revision == 1) || (hw->phy_revision == 2))) || 10727 ((hw->phy_type == em_phy_82578) && (hw->phy_revision == 1))) { 10728 /* Disable generation of early preamble */ 10729 ret_val = em_write_phy_reg(hw, PHY_REG(769, 25), 0x4431); 10730 if (ret_val) 10731 goto out; 10732 10733 /* Preamble tuning for SSC */ 10734 ret_val = em_write_phy_reg(hw, PHY_REG(770, 16), 0xA204); 10735 if (ret_val) 10736 goto out; 10737 } 10738 10739 if (hw->phy_type == em_phy_82578) { 10740 /* 10741 * Return registers to default by doing a soft reset then 10742 * writing 0x3140 to the control register. 10743 */ 10744 if (hw->phy_revision < 2) { 10745 em_phy_reset(hw); 10746 ret_val = em_write_phy_reg(hw, PHY_CTRL, 0x3140); 10747 } 10748 } 10749 10750 if ((hw->revision_id == 2) && 10751 (hw->phy_type == em_phy_82577) && 10752 ((hw->phy_revision == 2) || (hw->phy_revision == 3))) { 10753 /* 10754 * Workaround for OEM (GbE) not operating after reset - 10755 * restart AN (twice) 10756 */ 10757 ret_val = em_write_phy_reg(hw, PHY_REG(0, 25), 0x0400); 10758 if (ret_val) 10759 goto out; 10760 ret_val = em_write_phy_reg(hw, PHY_REG(0, 25), 0x0400); 10761 if (ret_val) 10762 goto out; 10763 } 10764 10765 /* Select page 0 */ 10766 ret_val = em_swfw_sync_acquire(hw, swfw); 10767 if (ret_val) 10768 goto out; 10769 10770 hw->phy_addr = 1; 10771 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT, 0); 10772 em_swfw_sync_release(hw, swfw); 10773 if (ret_val) 10774 goto out; 10775 10776 /* Workaround for link disconnects on a busy hub in half duplex */ 10777 ret_val = em_read_phy_reg(hw, 10778 PHY_REG(BM_PORT_CTRL_PAGE, 17), 10779 &phy_data); 10780 if (ret_val) 10781 goto release; 10782 ret_val = em_write_phy_reg(hw, 10783 PHY_REG(BM_PORT_CTRL_PAGE, 17), 10784 phy_data & 0x00FF); 10785 release: 10786 out: 10787 return ret_val; 10788 } 10789 10790 10791 /*************************************************************************** 10792 * Si workaround 10793 * 10794 * This function works around a Si bug where the link partner can get 10795 * a link up indication before the PHY does. If small packets are sent 10796 * by the link partner they can be placed in the packet buffer without 10797 * being properly accounted for by the PHY and will stall preventing 10798 * further packets from being received. The workaround is to clear the 10799 * packet buffer after the PHY detects link up. 10800 ***************************************************************************/ 10801 int32_t 10802 em_link_stall_workaround_hv(struct em_hw *hw) 10803 { 10804 int32_t ret_val = E1000_SUCCESS; 10805 uint16_t phy_data; 10806 10807 if (hw->phy_type != em_phy_82578) 10808 goto out; 10809 10810 /* Do not apply workaround if in PHY loopback bit 14 set */ 10811 em_read_phy_reg(hw, PHY_CTRL, &phy_data); 10812 if (phy_data & E1000_PHY_CTRL_LOOPBACK) 10813 goto out; 10814 10815 /* check if link is up and at 1Gbps */ 10816 ret_val = em_read_phy_reg(hw, BM_CS_STATUS, &phy_data); 10817 if (ret_val) 10818 goto out; 10819 10820 phy_data &= BM_CS_STATUS_LINK_UP | 10821 BM_CS_STATUS_RESOLVED | 10822 BM_CS_STATUS_SPEED_MASK; 10823 10824 if (phy_data != (BM_CS_STATUS_LINK_UP | 10825 BM_CS_STATUS_RESOLVED | 10826 BM_CS_STATUS_SPEED_1000)) 10827 goto out; 10828 10829 msec_delay(200); 10830 10831 /* flush the packets in the fifo buffer */ 10832 ret_val = em_write_phy_reg(hw, HV_MUX_DATA_CTRL, 10833 HV_MUX_DATA_CTRL_GEN_TO_MAC | HV_MUX_DATA_CTRL_FORCE_SPEED); 10834 if (ret_val) 10835 goto out; 10836 10837 ret_val = em_write_phy_reg(hw, HV_MUX_DATA_CTRL, 10838 HV_MUX_DATA_CTRL_GEN_TO_MAC); 10839 10840 out: 10841 return ret_val; 10842 } 10843 10844 /**************************************************************************** 10845 * K1 Si workaround 10846 * 10847 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning 10848 * from a lower speed. This workaround disables K1 whenever link is at 1Gig. 10849 * If link is down, the function will restore the default K1 setting located 10850 * in the NVM. 10851 ****************************************************************************/ 10852 int32_t 10853 em_k1_gig_workaround_hv(struct em_hw *hw, boolean_t link) 10854 { 10855 int32_t ret_val; 10856 uint16_t phy_data; 10857 boolean_t k1_enable; 10858 10859 DEBUGFUNC("em_k1_gig_workaround_hv"); 10860 10861 if (hw->mac_type != em_pchlan) 10862 return E1000_SUCCESS; 10863 10864 ret_val = em_read_eeprom_ich8(hw, E1000_NVM_K1_CONFIG, 1, &phy_data); 10865 if (ret_val) 10866 return ret_val; 10867 10868 k1_enable = phy_data & E1000_NVM_K1_ENABLE ? TRUE : FALSE; 10869 10870 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */ 10871 if (link) { 10872 if (hw->phy_type == em_phy_82578) { 10873 ret_val = em_read_phy_reg(hw, BM_CS_STATUS, 10874 &phy_data); 10875 if (ret_val) 10876 return ret_val; 10877 10878 phy_data &= BM_CS_STATUS_LINK_UP | 10879 BM_CS_STATUS_RESOLVED | 10880 BM_CS_STATUS_SPEED_MASK; 10881 10882 if (phy_data == (BM_CS_STATUS_LINK_UP | 10883 BM_CS_STATUS_RESOLVED | 10884 BM_CS_STATUS_SPEED_1000)) 10885 k1_enable = FALSE; 10886 } 10887 10888 if (hw->phy_type == em_phy_82577) { 10889 ret_val = em_read_phy_reg(hw, HV_M_STATUS, 10890 &phy_data); 10891 if (ret_val) 10892 return ret_val; 10893 10894 phy_data &= HV_M_STATUS_LINK_UP | 10895 HV_M_STATUS_AUTONEG_COMPLETE | 10896 HV_M_STATUS_SPEED_MASK; 10897 10898 if (phy_data == (HV_M_STATUS_LINK_UP | 10899 HV_M_STATUS_AUTONEG_COMPLETE | 10900 HV_M_STATUS_SPEED_1000)) 10901 k1_enable = FALSE; 10902 } 10903 10904 /* Link stall fix for link up */ 10905 ret_val = em_write_phy_reg(hw, PHY_REG(770, 19), 10906 0x0100); 10907 if (ret_val) 10908 return ret_val; 10909 10910 } else { 10911 /* Link stall fix for link down */ 10912 ret_val = em_write_phy_reg(hw, PHY_REG(770, 19), 10913 0x4100); 10914 if (ret_val) 10915 return ret_val; 10916 } 10917 10918 ret_val = em_configure_k1_ich8lan(hw, k1_enable); 10919 10920 return ret_val; 10921 } 10922 10923 /* Workaround to set the K1 beacon duration for 82579 parts */ 10924 int32_t 10925 em_k1_workaround_lv(struct em_hw *hw) 10926 { 10927 int32_t ret_val; 10928 uint16_t phy_data; 10929 uint32_t mac_reg; 10930 10931 ret_val = em_read_phy_reg(hw, BM_CS_STATUS, &phy_data); 10932 if (ret_val) 10933 return ret_val; 10934 10935 if ((phy_data & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) 10936 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) { 10937 mac_reg = E1000_READ_REG(hw, FEXTNVM4); 10938 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK; 10939 10940 if (phy_data & HV_M_STATUS_SPEED_1000) 10941 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC; 10942 else 10943 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC; 10944 10945 E1000_WRITE_REG(hw, FEXTNVM4, mac_reg); 10946 } 10947 10948 return E1000_SUCCESS; 10949 } 10950 10951 /** 10952 * em_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP 10953 * 10954 * When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications 10955 * preventing further DMA write requests. Workaround the issue by disabling 10956 * the de-assertion of the clock request when in 1Gbps mode. 10957 * Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link 10958 * speeds in order to avoid Tx hangs. 10959 **/ 10960 int32_t 10961 em_k1_workaround_lpt_lp(struct em_hw *hw, boolean_t link) 10962 { 10963 uint32_t fextnvm6 = E1000_READ_REG(hw, FEXTNVM6); 10964 uint32_t status = E1000_READ_REG(hw, STATUS); 10965 int32_t ret_val = E1000_SUCCESS; 10966 uint16_t reg; 10967 10968 if (link && (status & E1000_STATUS_SPEED_1000)) { 10969 ret_val = em_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 10970 ®); 10971 if (ret_val) 10972 return ret_val; 10973 10974 ret_val = em_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 10975 reg & ~E1000_KMRNCTRLSTA_K1_ENABLE); 10976 if (ret_val) 10977 return ret_val; 10978 10979 usec_delay(10); 10980 10981 E1000_WRITE_REG(hw, FEXTNVM6, 10982 fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK); 10983 10984 ret_val = em_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 10985 reg); 10986 } else { 10987 /* clear FEXTNVM6 bit 8 on link down or 10/100 */ 10988 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK; 10989 10990 if (!link || ((status & E1000_STATUS_SPEED_100) && 10991 (status & E1000_STATUS_FD))) 10992 goto update_fextnvm6; 10993 10994 ret_val = em_read_phy_reg(hw, I217_INBAND_CTRL, ®); 10995 if (ret_val) 10996 return ret_val; 10997 10998 /* Clear link status transmit timeout */ 10999 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK; 11000 11001 if (status & E1000_STATUS_SPEED_100) { 11002 /* Set inband Tx timeout to 5x10us for 100Half */ 11003 reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT; 11004 11005 /* Do not extend the K1 entry latency for 100Half */ 11006 fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION; 11007 } else { 11008 /* Set inband Tx timeout to 50x10us for 10Full/Half */ 11009 reg |= 50 << 11010 I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT; 11011 11012 /* Extend the K1 entry latency for 10 Mbps */ 11013 fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION; 11014 } 11015 11016 ret_val = em_write_phy_reg(hw, I217_INBAND_CTRL, reg); 11017 if (ret_val) 11018 return ret_val; 11019 11020 update_fextnvm6: 11021 E1000_WRITE_REG(hw, FEXTNVM6, fextnvm6); 11022 } 11023 11024 return ret_val; 11025 11026 } 11027 11028 11029 /*************************************************************************** 11030 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware 11031 * @hw: pointer to the HW structure 11032 * @gate: boolean set to TRUE to gate, FALSE to ungate 11033 * 11034 * Gate/ungate the automatic PHY configuration via hardware; perform 11035 * the configuration via software instead. 11036 ***************************************************************************/ 11037 void 11038 em_gate_hw_phy_config_ich8lan(struct em_hw *hw, boolean_t gate) 11039 { 11040 uint32_t extcnf_ctrl; 11041 11042 DEBUGFUNC("em_gate_hw_phy_config_ich8lan"); 11043 11044 if (hw->mac_type != em_pch2lan) 11045 return; 11046 11047 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 11048 11049 if (gate) 11050 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG; 11051 else 11052 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG; 11053 11054 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); 11055 } 11056 11057 /*************************************************************************** 11058 * Configure K1 power state 11059 * 11060 * Configure the K1 power state based on the provided parameter. 11061 * Assumes semaphore already acquired. 11062 * 11063 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 11064 ***************************************************************************/ 11065 int32_t 11066 em_configure_k1_ich8lan(struct em_hw *hw, boolean_t k1_enable) 11067 { 11068 int32_t ret_val = E1000_SUCCESS; 11069 uint32_t ctrl_reg = 0; 11070 uint32_t ctrl_ext = 0; 11071 uint32_t reg = 0; 11072 uint16_t kmrn_reg = 0; 11073 11074 ret_val = em_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 11075 &kmrn_reg); 11076 if (ret_val) 11077 goto out; 11078 11079 if (k1_enable) 11080 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE; 11081 else 11082 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE; 11083 11084 ret_val = em_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 11085 kmrn_reg); 11086 if (ret_val) 11087 goto out; 11088 11089 usec_delay(20); 11090 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 11091 ctrl_reg = E1000_READ_REG(hw, CTRL); 11092 11093 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 11094 reg |= E1000_CTRL_FRCSPD; 11095 E1000_WRITE_REG(hw, CTRL, reg); 11096 11097 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS); 11098 usec_delay(20); 11099 E1000_WRITE_REG(hw, CTRL, ctrl_reg); 11100 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 11101 usec_delay(20); 11102 11103 out: 11104 return ret_val; 11105 } 11106 11107 /*************************************************************************** 11108 * em_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be 11109 * done after every PHY reset. 11110 ***************************************************************************/ 11111 int32_t 11112 em_lv_phy_workarounds_ich8lan(struct em_hw *hw) 11113 { 11114 int32_t ret_val = E1000_SUCCESS; 11115 uint16_t swfw; 11116 11117 DEBUGFUNC("e1000_lv_phy_workarounds_ich8lan"); 11118 11119 if (hw->mac_type != em_pch2lan) 11120 goto out; 11121 11122 /* Set MDIO slow mode before any other MDIO access */ 11123 ret_val = em_set_mdio_slow_mode_hv(hw); 11124 11125 swfw = E1000_SWFW_PHY0_SM; 11126 ret_val = em_swfw_sync_acquire(hw, swfw); 11127 if (ret_val) 11128 goto out; 11129 ret_val = em_write_phy_reg(hw, I82579_EMI_ADDR, 11130 I82579_MSE_THRESHOLD); 11131 if (ret_val) 11132 goto release; 11133 /* set MSE higher to enable link to stay up when noise is high */ 11134 ret_val = em_write_phy_reg(hw, I82579_EMI_DATA, 11135 0x0034); 11136 if (ret_val) 11137 goto release; 11138 ret_val = em_write_phy_reg(hw, I82579_EMI_ADDR, 11139 I82579_MSE_LINK_DOWN); 11140 if (ret_val) 11141 goto release; 11142 /* drop link after 5 times MSE threshold was reached */ 11143 ret_val = em_write_phy_reg(hw, I82579_EMI_DATA, 11144 0x0005); 11145 release: 11146 em_swfw_sync_release(hw, swfw); 11147 11148 out: 11149 return ret_val; 11150 } 11151 11152 int32_t 11153 em_set_eee_i350(struct em_hw *hw) 11154 { 11155 int32_t ret_val = E1000_SUCCESS; 11156 uint32_t ipcnfg, eeer; 11157 11158 if ((hw->mac_type < em_i350) || 11159 (hw->media_type != em_media_type_copper)) 11160 goto out; 11161 ipcnfg = EM_READ_REG(hw, E1000_IPCNFG); 11162 eeer = EM_READ_REG(hw, E1000_EEER); 11163 11164 if (hw->eee_enable) { 11165 ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN); 11166 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN | 11167 E1000_EEER_LPI_FC); 11168 } else { 11169 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN); 11170 eeer &= ~(E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN | 11171 E1000_EEER_LPI_FC); 11172 } 11173 EM_WRITE_REG(hw, E1000_IPCNFG, ipcnfg); 11174 EM_WRITE_REG(hw, E1000_EEER, eeer); 11175 EM_READ_REG(hw, E1000_IPCNFG); 11176 EM_READ_REG(hw, E1000_EEER); 11177 out: 11178 return ret_val; 11179 } 11180 11181 /*************************************************************************** 11182 * em_set_eee_pchlan - Enable/disable EEE support 11183 * @hw: pointer to the HW structure 11184 * 11185 * Enable/disable EEE based on setting in dev_spec structure. The bits in 11186 * the LPI Control register will remain set only if/when link is up. 11187 ***************************************************************************/ 11188 int32_t 11189 em_set_eee_pchlan(struct em_hw *hw) 11190 { 11191 int32_t ret_val = E1000_SUCCESS; 11192 uint16_t phy_reg; 11193 11194 DEBUGFUNC("em_set_eee_pchlan"); 11195 11196 if (hw->phy_type != em_phy_82579 && 11197 hw->phy_type != em_phy_i217) 11198 goto out; 11199 11200 ret_val = em_read_phy_reg(hw, I82579_LPI_CTRL, &phy_reg); 11201 if (ret_val) 11202 goto out; 11203 11204 if (hw->eee_enable) 11205 phy_reg &= ~I82579_LPI_CTRL_ENABLE_MASK; 11206 else 11207 phy_reg |= I82579_LPI_CTRL_ENABLE_MASK; 11208 11209 ret_val = em_write_phy_reg(hw, I82579_LPI_CTRL, phy_reg); 11210 out: 11211 return ret_val; 11212 } 11213 11214 /** 11215 * em_initialize_M88E1512_phy - Initialize M88E1512 PHY 11216 * @hw: pointer to the HW structure 11217 * 11218 * Initialize Marvell 1512 to work correctly with Avoton. 11219 **/ 11220 int32_t 11221 em_initialize_M88E1512_phy(struct em_hw *hw) 11222 { 11223 int32_t ret_val = E1000_SUCCESS; 11224 11225 DEBUGFUNC("e1000_initialize_M88E1512_phy"); 11226 11227 /* Check if this is correct PHY. */ 11228 if (hw->phy_id != M88E1512_E_PHY_ID) 11229 goto out; 11230 11231 /* Switch to PHY page 0xFF. */ 11232 ret_val = em_write_phy_reg(hw, M88E1543_PAGE_ADDR, 0x00FF); 11233 if (ret_val) 11234 goto out; 11235 11236 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_2, 0x214B); 11237 if (ret_val) 11238 goto out; 11239 11240 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_1, 0x2144); 11241 if (ret_val) 11242 goto out; 11243 11244 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_2, 0x0C28); 11245 if (ret_val) 11246 goto out; 11247 11248 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_1, 0x2146); 11249 if (ret_val) 11250 goto out; 11251 11252 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_2, 0xB233); 11253 if (ret_val) 11254 goto out; 11255 11256 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_1, 0x214D); 11257 if (ret_val) 11258 goto out; 11259 11260 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_2, 0xCC0C); 11261 if (ret_val) 11262 goto out; 11263 11264 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_1, 0x2159); 11265 if (ret_val) 11266 goto out; 11267 11268 /* Switch to PHY page 0xFB. */ 11269 ret_val = em_write_phy_reg(hw, M88E1543_PAGE_ADDR, 0x00FB); 11270 if (ret_val) 11271 goto out; 11272 11273 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_3, 0x000D); 11274 if (ret_val) 11275 goto out; 11276 11277 /* Switch to PHY page 0x12. */ 11278 ret_val = em_write_phy_reg(hw, M88E1543_PAGE_ADDR, 0x12); 11279 if (ret_val) 11280 goto out; 11281 11282 /* Change mode to SGMII-to-Copper */ 11283 ret_val = em_write_phy_reg(hw, M88E1512_MODE, 0x8001); 11284 if (ret_val) 11285 goto out; 11286 11287 /* Return the PHY to page 0. */ 11288 ret_val = em_write_phy_reg(hw, M88E1543_PAGE_ADDR, 0); 11289 if (ret_val) 11290 goto out; 11291 11292 ret_val = em_phy_hw_reset(hw); 11293 if (ret_val) { 11294 DEBUGOUT("Error committing the PHY changes\n"); 11295 return ret_val; 11296 } 11297 11298 msec_delay(1000); 11299 out: 11300 return ret_val; 11301 } 11302 11303