1 /******************************************************************************* 2 3 Copyright (c) 2001-2005, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 *******************************************************************************/ 33 34 /* $OpenBSD: if_em_hw.c,v 1.110 2021/01/24 10:21:43 jsg Exp $ */ 35 /* 36 * if_em_hw.c Shared functions for accessing and configuring the MAC 37 */ 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/sockio.h> 42 #include <sys/mbuf.h> 43 #include <sys/malloc.h> 44 #include <sys/kernel.h> 45 #include <sys/device.h> 46 #include <sys/socket.h> 47 #include <sys/kstat.h> 48 49 #include <net/if.h> 50 #include <net/if_media.h> 51 52 #include <netinet/in.h> 53 #include <netinet/if_ether.h> 54 55 #include <uvm/uvm_extern.h> 56 57 #include <dev/pci/pcireg.h> 58 #include <dev/pci/pcivar.h> 59 60 #include <dev/pci/if_em.h> 61 #include <dev/pci/if_em_hw.h> 62 #include <dev/pci/if_em_soc.h> 63 64 #include <dev/mii/rgephyreg.h> 65 66 #define STATIC 67 68 static int32_t em_swfw_sync_acquire(struct em_hw *, uint16_t); 69 static void em_swfw_sync_release(struct em_hw *, uint16_t); 70 static int32_t em_read_kmrn_reg(struct em_hw *, uint32_t, uint16_t *); 71 static int32_t em_write_kmrn_reg(struct em_hw *hw, uint32_t, uint16_t); 72 static int32_t em_get_software_semaphore(struct em_hw *); 73 static void em_release_software_semaphore(struct em_hw *); 74 75 static int32_t em_check_downshift(struct em_hw *); 76 static void em_clear_vfta(struct em_hw *); 77 void em_clear_vfta_i350(struct em_hw *); 78 static int32_t em_commit_shadow_ram(struct em_hw *); 79 static int32_t em_config_dsp_after_link_change(struct em_hw *, boolean_t); 80 static int32_t em_config_fc_after_link_up(struct em_hw *); 81 static int32_t em_match_gig_phy(struct em_hw *); 82 static int32_t em_detect_gig_phy(struct em_hw *); 83 static int32_t em_erase_ich8_4k_segment(struct em_hw *, uint32_t); 84 static int32_t em_get_auto_rd_done(struct em_hw *); 85 static int32_t em_get_cable_length(struct em_hw *, uint16_t *, uint16_t *); 86 static int32_t em_get_hw_eeprom_semaphore(struct em_hw *); 87 static int32_t em_get_phy_cfg_done(struct em_hw *); 88 static int32_t em_get_software_flag(struct em_hw *); 89 static int32_t em_ich8_cycle_init(struct em_hw *); 90 static int32_t em_ich8_flash_cycle(struct em_hw *, uint32_t); 91 static int32_t em_id_led_init(struct em_hw *); 92 static int32_t em_init_lcd_from_nvm_config_region(struct em_hw *, uint32_t, 93 uint32_t); 94 static int32_t em_init_lcd_from_nvm(struct em_hw *); 95 static int32_t em_phy_no_cable_workaround(struct em_hw *); 96 static void em_init_rx_addrs(struct em_hw *); 97 static void em_initialize_hardware_bits(struct em_softc *); 98 static void em_toggle_lanphypc_pch_lpt(struct em_hw *); 99 static int em_disable_ulp_lpt_lp(struct em_hw *hw, bool force); 100 static boolean_t em_is_onboard_nvm_eeprom(struct em_hw *); 101 static int32_t em_kumeran_lock_loss_workaround(struct em_hw *); 102 static int32_t em_mng_enable_host_if(struct em_hw *); 103 static int32_t em_read_eeprom_eerd(struct em_hw *, uint16_t, uint16_t, 104 uint16_t *); 105 static int32_t em_write_eeprom_eewr(struct em_hw *, uint16_t, uint16_t, 106 uint16_t *data); 107 static int32_t em_poll_eerd_eewr_done(struct em_hw *, int); 108 static void em_put_hw_eeprom_semaphore(struct em_hw *); 109 static int32_t em_read_ich8_byte(struct em_hw *, uint32_t, uint8_t *); 110 static int32_t em_verify_write_ich8_byte(struct em_hw *, uint32_t, uint8_t); 111 static int32_t em_write_ich8_byte(struct em_hw *, uint32_t, uint8_t); 112 static int32_t em_read_ich8_word(struct em_hw *, uint32_t, uint16_t *); 113 static int32_t em_read_ich8_dword(struct em_hw *, uint32_t, uint32_t *); 114 static int32_t em_read_ich8_data(struct em_hw *, uint32_t, uint32_t, 115 uint16_t *); 116 static int32_t em_write_ich8_data(struct em_hw *, uint32_t, uint32_t, 117 uint16_t); 118 static int32_t em_read_eeprom_ich8(struct em_hw *, uint16_t, uint16_t, 119 uint16_t *); 120 static int32_t em_write_eeprom_ich8(struct em_hw *, uint16_t, uint16_t, 121 uint16_t *); 122 static int32_t em_read_invm_i210(struct em_hw *, uint16_t, uint16_t, 123 uint16_t *); 124 static int32_t em_read_invm_word_i210(struct em_hw *, uint16_t, uint16_t *); 125 static void em_release_software_flag(struct em_hw *); 126 static int32_t em_set_d3_lplu_state(struct em_hw *, boolean_t); 127 static int32_t em_set_d0_lplu_state(struct em_hw *, boolean_t); 128 static int32_t em_set_lplu_state_pchlan(struct em_hw *, boolean_t); 129 static int32_t em_set_pci_ex_no_snoop(struct em_hw *, uint32_t); 130 static void em_set_pci_express_master_disable(struct em_hw *); 131 static int32_t em_wait_autoneg(struct em_hw *); 132 static void em_write_reg_io(struct em_hw *, uint32_t, uint32_t); 133 static int32_t em_set_phy_type(struct em_hw *); 134 static void em_phy_init_script(struct em_hw *); 135 static int32_t em_setup_copper_link(struct em_hw *); 136 static int32_t em_setup_fiber_serdes_link(struct em_hw *); 137 static int32_t em_adjust_serdes_amplitude(struct em_hw *); 138 static int32_t em_phy_force_speed_duplex(struct em_hw *); 139 static int32_t em_config_mac_to_phy(struct em_hw *); 140 static void em_raise_mdi_clk(struct em_hw *, uint32_t *); 141 static void em_lower_mdi_clk(struct em_hw *, uint32_t *); 142 static void em_shift_out_mdi_bits(struct em_hw *, uint32_t, uint16_t); 143 static uint16_t em_shift_in_mdi_bits(struct em_hw *); 144 static int32_t em_phy_reset_dsp(struct em_hw *); 145 static int32_t em_write_eeprom_spi(struct em_hw *, uint16_t, uint16_t, 146 uint16_t *); 147 static int32_t em_write_eeprom_microwire(struct em_hw *, uint16_t, uint16_t, 148 uint16_t *); 149 static int32_t em_spi_eeprom_ready(struct em_hw *); 150 static void em_raise_ee_clk(struct em_hw *, uint32_t *); 151 static void em_lower_ee_clk(struct em_hw *, uint32_t *); 152 static void em_shift_out_ee_bits(struct em_hw *, uint16_t, uint16_t); 153 static int32_t em_write_phy_reg_ex(struct em_hw *, uint32_t, uint16_t); 154 static int32_t em_read_phy_reg_ex(struct em_hw *, uint32_t, uint16_t *); 155 static uint16_t em_shift_in_ee_bits(struct em_hw *, uint16_t); 156 static int32_t em_acquire_eeprom(struct em_hw *); 157 static void em_release_eeprom(struct em_hw *); 158 static void em_standby_eeprom(struct em_hw *); 159 static int32_t em_set_vco_speed(struct em_hw *); 160 static int32_t em_polarity_reversal_workaround(struct em_hw *); 161 static int32_t em_set_phy_mode(struct em_hw *); 162 static int32_t em_host_if_read_cookie(struct em_hw *, uint8_t *); 163 static uint8_t em_calculate_mng_checksum(char *, uint32_t); 164 static int32_t em_configure_kmrn_for_10_100(struct em_hw *, uint16_t); 165 static int32_t em_configure_kmrn_for_1000(struct em_hw *); 166 static int32_t em_set_pciex_completion_timeout(struct em_hw *hw); 167 static int32_t em_set_mdio_slow_mode_hv(struct em_hw *); 168 int32_t em_hv_phy_workarounds_ich8lan(struct em_hw *); 169 int32_t em_lv_phy_workarounds_ich8lan(struct em_hw *); 170 int32_t em_link_stall_workaround_hv(struct em_hw *); 171 int32_t em_k1_gig_workaround_hv(struct em_hw *, boolean_t); 172 int32_t em_k1_workaround_lv(struct em_hw *); 173 int32_t em_k1_workaround_lpt_lp(struct em_hw *, boolean_t); 174 int32_t em_configure_k1_ich8lan(struct em_hw *, boolean_t); 175 void em_gate_hw_phy_config_ich8lan(struct em_hw *, boolean_t); 176 int32_t em_access_phy_wakeup_reg_bm(struct em_hw *, uint32_t, 177 uint16_t *, boolean_t); 178 int32_t em_access_phy_debug_regs_hv(struct em_hw *, uint32_t, 179 uint16_t *, boolean_t); 180 int32_t em_access_phy_reg_hv(struct em_hw *, uint32_t, uint16_t *, 181 boolean_t); 182 int32_t em_oem_bits_config_pchlan(struct em_hw *, boolean_t); 183 void em_power_up_serdes_link_82575(struct em_hw *); 184 int32_t em_get_pcs_speed_and_duplex_82575(struct em_hw *, uint16_t *, 185 uint16_t *); 186 int32_t em_set_eee_i350(struct em_hw *); 187 int32_t em_set_eee_pchlan(struct em_hw *); 188 int32_t em_valid_nvm_bank_detect_ich8lan(struct em_hw *, uint32_t *); 189 int32_t em_initialize_M88E1512_phy(struct em_hw *); 190 191 /* IGP cable length table */ 192 static const uint16_t 193 em_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = 194 {5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 195 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25, 196 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40, 197 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60, 198 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90, 199 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 200 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 201 110, 202 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 203 120}; 204 205 static const uint16_t 206 em_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] = 207 {0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 208 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 209 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 210 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 211 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 212 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 213 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 214 121, 124}; 215 216 /****************************************************************************** 217 * Set the phy type member in the hw struct. 218 * 219 * hw - Struct containing variables accessed by shared code 220 *****************************************************************************/ 221 STATIC int32_t 222 em_set_phy_type(struct em_hw *hw) 223 { 224 DEBUGFUNC("em_set_phy_type"); 225 226 if (hw->mac_type == em_undefined) 227 return -E1000_ERR_PHY_TYPE; 228 229 switch (hw->phy_id) { 230 case M88E1000_E_PHY_ID: 231 case M88E1000_I_PHY_ID: 232 case M88E1011_I_PHY_ID: 233 case M88E1111_I_PHY_ID: 234 case M88E1112_E_PHY_ID: 235 case M88E1543_E_PHY_ID: 236 case M88E1512_E_PHY_ID: 237 case I210_I_PHY_ID: 238 case I347AT4_E_PHY_ID: 239 hw->phy_type = em_phy_m88; 240 break; 241 case IGP01E1000_I_PHY_ID: 242 if (hw->mac_type == em_82541 || 243 hw->mac_type == em_82541_rev_2 || 244 hw->mac_type == em_82547 || 245 hw->mac_type == em_82547_rev_2) { 246 hw->phy_type = em_phy_igp; 247 break; 248 } 249 case IGP03E1000_E_PHY_ID: 250 case IGP04E1000_E_PHY_ID: 251 hw->phy_type = em_phy_igp_3; 252 break; 253 case IFE_E_PHY_ID: 254 case IFE_PLUS_E_PHY_ID: 255 case IFE_C_E_PHY_ID: 256 hw->phy_type = em_phy_ife; 257 break; 258 case M88E1141_E_PHY_ID: 259 hw->phy_type = em_phy_oem; 260 break; 261 case I82577_E_PHY_ID: 262 hw->phy_type = em_phy_82577; 263 break; 264 case I82578_E_PHY_ID: 265 hw->phy_type = em_phy_82578; 266 break; 267 case I82579_E_PHY_ID: 268 hw->phy_type = em_phy_82579; 269 break; 270 case I217_E_PHY_ID: 271 hw->phy_type = em_phy_i217; 272 break; 273 case I82580_I_PHY_ID: 274 case I350_I_PHY_ID: 275 hw->phy_type = em_phy_82580; 276 break; 277 case RTL8211_E_PHY_ID: 278 hw->phy_type = em_phy_rtl8211; 279 break; 280 case BME1000_E_PHY_ID: 281 if (hw->phy_revision == 1) { 282 hw->phy_type = em_phy_bm; 283 break; 284 } 285 /* FALLTHROUGH */ 286 case GG82563_E_PHY_ID: 287 if (hw->mac_type == em_80003es2lan) { 288 hw->phy_type = em_phy_gg82563; 289 break; 290 } 291 /* FALLTHROUGH */ 292 default: 293 /* Should never have loaded on this device */ 294 hw->phy_type = em_phy_undefined; 295 return -E1000_ERR_PHY_TYPE; 296 } 297 298 return E1000_SUCCESS; 299 } 300 301 /****************************************************************************** 302 * IGP phy init script - initializes the GbE PHY 303 * 304 * hw - Struct containing variables accessed by shared code 305 *****************************************************************************/ 306 static void 307 em_phy_init_script(struct em_hw *hw) 308 { 309 uint16_t phy_saved_data; 310 DEBUGFUNC("em_phy_init_script"); 311 312 if (hw->phy_init_script) { 313 msec_delay(20); 314 /* 315 * Save off the current value of register 0x2F5B to be 316 * restored at the end of this routine. 317 */ 318 em_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 319 320 /* Disabled the PHY transmitter */ 321 em_write_phy_reg(hw, 0x2F5B, 0x0003); 322 msec_delay(20); 323 em_write_phy_reg(hw, 0x0000, 0x0140); 324 msec_delay(5); 325 326 switch (hw->mac_type) { 327 case em_82541: 328 case em_82547: 329 em_write_phy_reg(hw, 0x1F95, 0x0001); 330 em_write_phy_reg(hw, 0x1F71, 0xBD21); 331 em_write_phy_reg(hw, 0x1F79, 0x0018); 332 em_write_phy_reg(hw, 0x1F30, 0x1600); 333 em_write_phy_reg(hw, 0x1F31, 0x0014); 334 em_write_phy_reg(hw, 0x1F32, 0x161C); 335 em_write_phy_reg(hw, 0x1F94, 0x0003); 336 em_write_phy_reg(hw, 0x1F96, 0x003F); 337 em_write_phy_reg(hw, 0x2010, 0x0008); 338 break; 339 case em_82541_rev_2: 340 case em_82547_rev_2: 341 em_write_phy_reg(hw, 0x1F73, 0x0099); 342 break; 343 default: 344 break; 345 } 346 347 em_write_phy_reg(hw, 0x0000, 0x3300); 348 msec_delay(20); 349 350 /* Now enable the transmitter */ 351 em_write_phy_reg(hw, 0x2F5B, phy_saved_data); 352 353 if (hw->mac_type == em_82547) { 354 uint16_t fused, fine, coarse; 355 /* Move to analog registers page */ 356 em_read_phy_reg(hw, 357 IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused); 358 359 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { 360 em_read_phy_reg(hw, 361 IGP01E1000_ANALOG_FUSE_STATUS, &fused); 362 363 fine = fused & 364 IGP01E1000_ANALOG_FUSE_FINE_MASK; 365 coarse = fused & 366 IGP01E1000_ANALOG_FUSE_COARSE_MASK; 367 368 if (coarse > 369 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { 370 coarse -= 371 IGP01E1000_ANALOG_FUSE_COARSE_10; 372 fine -= 373 IGP01E1000_ANALOG_FUSE_FINE_1; 374 } else if (coarse == 375 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) 376 fine -= IGP01E1000_ANALOG_FUSE_FINE_10; 377 378 fused = (fused & 379 IGP01E1000_ANALOG_FUSE_POLY_MASK) | 380 (fine & 381 IGP01E1000_ANALOG_FUSE_FINE_MASK) | 382 (coarse & 383 IGP01E1000_ANALOG_FUSE_COARSE_MASK); 384 385 em_write_phy_reg(hw, 386 IGP01E1000_ANALOG_FUSE_CONTROL, 387 fused); 388 389 em_write_phy_reg(hw, 390 IGP01E1000_ANALOG_FUSE_BYPASS, 391 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL); 392 } 393 } 394 } 395 } 396 397 /****************************************************************************** 398 * Set the mac type member in the hw struct. 399 * 400 * hw - Struct containing variables accessed by shared code 401 *****************************************************************************/ 402 int32_t 403 em_set_mac_type(struct em_hw *hw) 404 { 405 DEBUGFUNC("em_set_mac_type"); 406 407 switch (hw->device_id) { 408 case E1000_DEV_ID_82542: 409 switch (hw->revision_id) { 410 case E1000_82542_2_0_REV_ID: 411 hw->mac_type = em_82542_rev2_0; 412 break; 413 case E1000_82542_2_1_REV_ID: 414 hw->mac_type = em_82542_rev2_1; 415 break; 416 default: 417 /* Invalid 82542 revision ID */ 418 return -E1000_ERR_MAC_TYPE; 419 } 420 break; 421 case E1000_DEV_ID_82543GC_FIBER: 422 case E1000_DEV_ID_82543GC_COPPER: 423 hw->mac_type = em_82543; 424 break; 425 case E1000_DEV_ID_82544EI_COPPER: 426 case E1000_DEV_ID_82544EI_FIBER: 427 case E1000_DEV_ID_82544GC_COPPER: 428 case E1000_DEV_ID_82544GC_LOM: 429 hw->mac_type = em_82544; 430 break; 431 case E1000_DEV_ID_82540EM: 432 case E1000_DEV_ID_82540EM_LOM: 433 case E1000_DEV_ID_82540EP: 434 case E1000_DEV_ID_82540EP_LOM: 435 case E1000_DEV_ID_82540EP_LP: 436 hw->mac_type = em_82540; 437 break; 438 case E1000_DEV_ID_82545EM_COPPER: 439 case E1000_DEV_ID_82545EM_FIBER: 440 hw->mac_type = em_82545; 441 break; 442 case E1000_DEV_ID_82545GM_COPPER: 443 case E1000_DEV_ID_82545GM_FIBER: 444 case E1000_DEV_ID_82545GM_SERDES: 445 hw->mac_type = em_82545_rev_3; 446 break; 447 case E1000_DEV_ID_82546EB_COPPER: 448 case E1000_DEV_ID_82546EB_FIBER: 449 case E1000_DEV_ID_82546EB_QUAD_COPPER: 450 hw->mac_type = em_82546; 451 break; 452 case E1000_DEV_ID_82546GB_COPPER: 453 case E1000_DEV_ID_82546GB_FIBER: 454 case E1000_DEV_ID_82546GB_SERDES: 455 case E1000_DEV_ID_82546GB_PCIE: 456 case E1000_DEV_ID_82546GB_QUAD_COPPER: 457 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 458 case E1000_DEV_ID_82546GB_2: 459 hw->mac_type = em_82546_rev_3; 460 break; 461 case E1000_DEV_ID_82541EI: 462 case E1000_DEV_ID_82541EI_MOBILE: 463 case E1000_DEV_ID_82541ER_LOM: 464 hw->mac_type = em_82541; 465 break; 466 case E1000_DEV_ID_82541ER: 467 case E1000_DEV_ID_82541GI: 468 case E1000_DEV_ID_82541GI_LF: 469 case E1000_DEV_ID_82541GI_MOBILE: 470 hw->mac_type = em_82541_rev_2; 471 break; 472 case E1000_DEV_ID_82547EI: 473 case E1000_DEV_ID_82547EI_MOBILE: 474 hw->mac_type = em_82547; 475 break; 476 case E1000_DEV_ID_82547GI: 477 hw->mac_type = em_82547_rev_2; 478 break; 479 case E1000_DEV_ID_82571EB_AF: 480 case E1000_DEV_ID_82571EB_AT: 481 case E1000_DEV_ID_82571EB_COPPER: 482 case E1000_DEV_ID_82571EB_FIBER: 483 case E1000_DEV_ID_82571EB_SERDES: 484 case E1000_DEV_ID_82571EB_QUAD_COPPER: 485 case E1000_DEV_ID_82571EB_QUAD_FIBER: 486 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 487 case E1000_DEV_ID_82571EB_SERDES_DUAL: 488 case E1000_DEV_ID_82571EB_SERDES_QUAD: 489 case E1000_DEV_ID_82571PT_QUAD_COPPER: 490 hw->mac_type = em_82571; 491 break; 492 case E1000_DEV_ID_82572EI_COPPER: 493 case E1000_DEV_ID_82572EI_FIBER: 494 case E1000_DEV_ID_82572EI_SERDES: 495 case E1000_DEV_ID_82572EI: 496 hw->mac_type = em_82572; 497 break; 498 case E1000_DEV_ID_82573E: 499 case E1000_DEV_ID_82573E_IAMT: 500 case E1000_DEV_ID_82573E_PM: 501 case E1000_DEV_ID_82573L: 502 case E1000_DEV_ID_82573L_PL_1: 503 case E1000_DEV_ID_82573L_PL_2: 504 case E1000_DEV_ID_82573V_PM: 505 hw->mac_type = em_82573; 506 break; 507 case E1000_DEV_ID_82574L: 508 case E1000_DEV_ID_82574LA: 509 case E1000_DEV_ID_82583V: 510 hw->mac_type = em_82574; 511 break; 512 case E1000_DEV_ID_82575EB_PT: 513 case E1000_DEV_ID_82575EB_PF: 514 case E1000_DEV_ID_82575GB_QP: 515 case E1000_DEV_ID_82575GB_QP_PM: 516 hw->mac_type = em_82575; 517 hw->initialize_hw_bits_disable = 1; 518 break; 519 case E1000_DEV_ID_82576: 520 case E1000_DEV_ID_82576_FIBER: 521 case E1000_DEV_ID_82576_SERDES: 522 case E1000_DEV_ID_82576_QUAD_COPPER: 523 case E1000_DEV_ID_82576_QUAD_CU_ET2: 524 case E1000_DEV_ID_82576_NS: 525 case E1000_DEV_ID_82576_NS_SERDES: 526 case E1000_DEV_ID_82576_SERDES_QUAD: 527 hw->mac_type = em_82576; 528 hw->initialize_hw_bits_disable = 1; 529 break; 530 case E1000_DEV_ID_82580_COPPER: 531 case E1000_DEV_ID_82580_FIBER: 532 case E1000_DEV_ID_82580_QUAD_FIBER: 533 case E1000_DEV_ID_82580_SERDES: 534 case E1000_DEV_ID_82580_SGMII: 535 case E1000_DEV_ID_82580_COPPER_DUAL: 536 case E1000_DEV_ID_DH89XXCC_SGMII: 537 case E1000_DEV_ID_DH89XXCC_SERDES: 538 case E1000_DEV_ID_DH89XXCC_BACKPLANE: 539 case E1000_DEV_ID_DH89XXCC_SFP: 540 hw->mac_type = em_82580; 541 hw->initialize_hw_bits_disable = 1; 542 break; 543 case E1000_DEV_ID_I210_COPPER: 544 case E1000_DEV_ID_I210_COPPER_OEM1: 545 case E1000_DEV_ID_I210_COPPER_IT: 546 case E1000_DEV_ID_I210_FIBER: 547 case E1000_DEV_ID_I210_SERDES: 548 case E1000_DEV_ID_I210_SGMII: 549 case E1000_DEV_ID_I210_COPPER_FLASHLESS: 550 case E1000_DEV_ID_I210_SERDES_FLASHLESS: 551 case E1000_DEV_ID_I211_COPPER: 552 hw->mac_type = em_i210; 553 hw->initialize_hw_bits_disable = 1; 554 hw->eee_enable = 1; 555 break; 556 case E1000_DEV_ID_I350_COPPER: 557 case E1000_DEV_ID_I350_FIBER: 558 case E1000_DEV_ID_I350_SERDES: 559 case E1000_DEV_ID_I350_SGMII: 560 case E1000_DEV_ID_I350_DA4: 561 case E1000_DEV_ID_I354_BACKPLANE_1GBPS: 562 case E1000_DEV_ID_I354_SGMII: 563 case E1000_DEV_ID_I354_BACKPLANE_2_5GBPS: 564 hw->mac_type = em_i350; 565 hw->initialize_hw_bits_disable = 1; 566 hw->eee_enable = 1; 567 break; 568 case E1000_DEV_ID_80003ES2LAN_COPPER_SPT: 569 case E1000_DEV_ID_80003ES2LAN_SERDES_SPT: 570 case E1000_DEV_ID_80003ES2LAN_COPPER_DPT: 571 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: 572 hw->mac_type = em_80003es2lan; 573 break; 574 case E1000_DEV_ID_ICH8_IFE: 575 case E1000_DEV_ID_ICH8_IFE_G: 576 case E1000_DEV_ID_ICH8_IFE_GT: 577 case E1000_DEV_ID_ICH8_IGP_AMT: 578 case E1000_DEV_ID_ICH8_IGP_C: 579 case E1000_DEV_ID_ICH8_IGP_M: 580 case E1000_DEV_ID_ICH8_IGP_M_AMT: 581 case E1000_DEV_ID_ICH8_82567V_3: 582 hw->mac_type = em_ich8lan; 583 break; 584 case E1000_DEV_ID_ICH9_BM: 585 case E1000_DEV_ID_ICH9_IFE: 586 case E1000_DEV_ID_ICH9_IFE_G: 587 case E1000_DEV_ID_ICH9_IFE_GT: 588 case E1000_DEV_ID_ICH9_IGP_AMT: 589 case E1000_DEV_ID_ICH9_IGP_C: 590 case E1000_DEV_ID_ICH9_IGP_M: 591 case E1000_DEV_ID_ICH9_IGP_M_AMT: 592 case E1000_DEV_ID_ICH9_IGP_M_V: 593 case E1000_DEV_ID_ICH10_R_BM_LF: 594 case E1000_DEV_ID_ICH10_R_BM_LM: 595 case E1000_DEV_ID_ICH10_R_BM_V: 596 hw->mac_type = em_ich9lan; 597 break; 598 case E1000_DEV_ID_ICH10_D_BM_LF: 599 case E1000_DEV_ID_ICH10_D_BM_LM: 600 case E1000_DEV_ID_ICH10_D_BM_V: 601 hw->mac_type = em_ich10lan; 602 break; 603 case E1000_DEV_ID_PCH_M_HV_LC: 604 case E1000_DEV_ID_PCH_M_HV_LM: 605 case E1000_DEV_ID_PCH_D_HV_DC: 606 case E1000_DEV_ID_PCH_D_HV_DM: 607 hw->mac_type = em_pchlan; 608 hw->eee_enable = 1; 609 break; 610 case E1000_DEV_ID_PCH2_LV_LM: 611 case E1000_DEV_ID_PCH2_LV_V: 612 hw->mac_type = em_pch2lan; 613 break; 614 case E1000_DEV_ID_PCH_LPT_I217_LM: 615 case E1000_DEV_ID_PCH_LPT_I217_V: 616 case E1000_DEV_ID_PCH_LPTLP_I218_LM: 617 case E1000_DEV_ID_PCH_LPTLP_I218_V: 618 case E1000_DEV_ID_PCH_I218_LM2: 619 case E1000_DEV_ID_PCH_I218_V2: 620 case E1000_DEV_ID_PCH_I218_LM3: 621 case E1000_DEV_ID_PCH_I218_V3: 622 hw->mac_type = em_pch_lpt; 623 break; 624 case E1000_DEV_ID_PCH_SPT_I219_LM: 625 case E1000_DEV_ID_PCH_SPT_I219_V: 626 case E1000_DEV_ID_PCH_SPT_I219_LM2: 627 case E1000_DEV_ID_PCH_SPT_I219_V2: 628 case E1000_DEV_ID_PCH_LBG_I219_LM3: 629 case E1000_DEV_ID_PCH_SPT_I219_LM4: 630 case E1000_DEV_ID_PCH_SPT_I219_V4: 631 case E1000_DEV_ID_PCH_SPT_I219_LM5: 632 case E1000_DEV_ID_PCH_SPT_I219_V5: 633 case E1000_DEV_ID_PCH_CMP_I219_LM12: 634 case E1000_DEV_ID_PCH_CMP_I219_V12: 635 hw->mac_type = em_pch_spt; 636 break; 637 case E1000_DEV_ID_PCH_CNP_I219_LM6: 638 case E1000_DEV_ID_PCH_CNP_I219_V6: 639 case E1000_DEV_ID_PCH_CNP_I219_LM7: 640 case E1000_DEV_ID_PCH_CNP_I219_V7: 641 case E1000_DEV_ID_PCH_ICP_I219_LM8: 642 case E1000_DEV_ID_PCH_ICP_I219_V8: 643 case E1000_DEV_ID_PCH_ICP_I219_LM9: 644 case E1000_DEV_ID_PCH_ICP_I219_V9: 645 case E1000_DEV_ID_PCH_CMP_I219_LM10: 646 case E1000_DEV_ID_PCH_CMP_I219_V10: 647 case E1000_DEV_ID_PCH_CMP_I219_LM11: 648 case E1000_DEV_ID_PCH_CMP_I219_V11: 649 case E1000_DEV_ID_PCH_TGP_I219_LM13: 650 case E1000_DEV_ID_PCH_TGP_I219_V13: 651 case E1000_DEV_ID_PCH_TGP_I219_LM14: 652 case E1000_DEV_ID_PCH_TGP_I219_V14: 653 case E1000_DEV_ID_PCH_TGP_I219_LM15: 654 case E1000_DEV_ID_PCH_TGP_I219_V15: 655 case E1000_DEV_ID_PCH_ADP_I219_LM16: 656 case E1000_DEV_ID_PCH_ADP_I219_V16: 657 case E1000_DEV_ID_PCH_ADP_I219_LM17: 658 case E1000_DEV_ID_PCH_ADP_I219_V17: 659 case E1000_DEV_ID_PCH_MTP_I219_LM18: 660 case E1000_DEV_ID_PCH_MTP_I219_V18: 661 case E1000_DEV_ID_PCH_MTP_I219_LM19: 662 case E1000_DEV_ID_PCH_MTP_I219_V19: 663 hw->mac_type = em_pch_cnp; 664 break; 665 case E1000_DEV_ID_EP80579_LAN_1: 666 hw->mac_type = em_icp_xxxx; 667 hw->icp_xxxx_port_num = 0; 668 break; 669 case E1000_DEV_ID_EP80579_LAN_2: 670 case E1000_DEV_ID_EP80579_LAN_4: 671 hw->mac_type = em_icp_xxxx; 672 hw->icp_xxxx_port_num = 1; 673 break; 674 case E1000_DEV_ID_EP80579_LAN_3: 675 case E1000_DEV_ID_EP80579_LAN_5: 676 hw->mac_type = em_icp_xxxx; 677 hw->icp_xxxx_port_num = 2; 678 break; 679 case E1000_DEV_ID_EP80579_LAN_6: 680 hw->mac_type = em_icp_xxxx; 681 hw->icp_xxxx_port_num = 3; 682 break; 683 default: 684 /* Should never have loaded on this device */ 685 return -E1000_ERR_MAC_TYPE; 686 } 687 688 switch (hw->mac_type) { 689 case em_ich8lan: 690 case em_ich9lan: 691 case em_ich10lan: 692 case em_pchlan: 693 case em_pch2lan: 694 case em_pch_lpt: 695 case em_pch_spt: 696 case em_pch_cnp: 697 hw->swfwhw_semaphore_present = TRUE; 698 hw->asf_firmware_present = TRUE; 699 break; 700 case em_80003es2lan: 701 case em_82575: 702 case em_82576: 703 case em_82580: 704 case em_i210: 705 case em_i350: 706 hw->swfw_sync_present = TRUE; 707 /* FALLTHROUGH */ 708 case em_82571: 709 case em_82572: 710 case em_82573: 711 case em_82574: 712 hw->eeprom_semaphore_present = TRUE; 713 /* FALLTHROUGH */ 714 case em_82541: 715 case em_82547: 716 case em_82541_rev_2: 717 case em_82547_rev_2: 718 hw->asf_firmware_present = TRUE; 719 break; 720 default: 721 break; 722 } 723 724 return E1000_SUCCESS; 725 } 726 727 /***************************************************************************** 728 * Set media type and TBI compatibility. 729 * 730 * hw - Struct containing variables accessed by shared code 731 * **************************************************************************/ 732 void 733 em_set_media_type(struct em_hw *hw) 734 { 735 uint32_t status, ctrl_ext; 736 DEBUGFUNC("em_set_media_type"); 737 738 if (hw->mac_type != em_82543) { 739 /* tbi_compatibility is only valid on 82543 */ 740 hw->tbi_compatibility_en = FALSE; 741 } 742 743 if (hw->mac_type == em_82575 || hw->mac_type == em_82580 || 744 hw->mac_type == em_82576 || 745 hw->mac_type == em_i210 || hw->mac_type == em_i350) { 746 hw->media_type = em_media_type_copper; 747 748 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 749 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) { 750 case E1000_CTRL_EXT_LINK_MODE_SGMII: 751 ctrl_ext |= E1000_CTRL_I2C_ENA; 752 break; 753 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: 754 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES: 755 hw->media_type = em_media_type_internal_serdes; 756 ctrl_ext |= E1000_CTRL_I2C_ENA; 757 break; 758 default: 759 ctrl_ext &= ~E1000_CTRL_I2C_ENA; 760 break; 761 } 762 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 763 return; 764 } 765 766 switch (hw->device_id) { 767 case E1000_DEV_ID_82545GM_SERDES: 768 case E1000_DEV_ID_82546GB_SERDES: 769 case E1000_DEV_ID_82571EB_SERDES: 770 case E1000_DEV_ID_82571EB_SERDES_DUAL: 771 case E1000_DEV_ID_82571EB_SERDES_QUAD: 772 case E1000_DEV_ID_82572EI_SERDES: 773 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: 774 hw->media_type = em_media_type_internal_serdes; 775 break; 776 case E1000_DEV_ID_EP80579_LAN_1: 777 case E1000_DEV_ID_EP80579_LAN_2: 778 case E1000_DEV_ID_EP80579_LAN_3: 779 case E1000_DEV_ID_EP80579_LAN_4: 780 case E1000_DEV_ID_EP80579_LAN_5: 781 case E1000_DEV_ID_EP80579_LAN_6: 782 hw->media_type = em_media_type_copper; 783 break; 784 default: 785 switch (hw->mac_type) { 786 case em_82542_rev2_0: 787 case em_82542_rev2_1: 788 hw->media_type = em_media_type_fiber; 789 break; 790 case em_ich8lan: 791 case em_ich9lan: 792 case em_ich10lan: 793 case em_pchlan: 794 case em_pch2lan: 795 case em_pch_lpt: 796 case em_pch_spt: 797 case em_pch_cnp: 798 case em_82573: 799 case em_82574: 800 /* 801 * The STATUS_TBIMODE bit is reserved or reused for 802 * the this device. 803 */ 804 hw->media_type = em_media_type_copper; 805 break; 806 default: 807 status = E1000_READ_REG(hw, STATUS); 808 if (status & E1000_STATUS_TBIMODE) { 809 hw->media_type = em_media_type_fiber; 810 /* tbi_compatibility not valid on fiber */ 811 hw->tbi_compatibility_en = FALSE; 812 } else { 813 hw->media_type = em_media_type_copper; 814 } 815 break; 816 } 817 } 818 } 819 /****************************************************************************** 820 * Reset the transmit and receive units; mask and clear all interrupts. 821 * 822 * hw - Struct containing variables accessed by shared code 823 *****************************************************************************/ 824 int32_t 825 em_reset_hw(struct em_hw *hw) 826 { 827 uint32_t ctrl; 828 uint32_t ctrl_ext; 829 uint32_t icr; 830 uint32_t manc; 831 uint32_t led_ctrl; 832 uint32_t timeout; 833 uint32_t extcnf_ctrl; 834 int32_t ret_val; 835 DEBUGFUNC("em_reset_hw"); 836 837 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ 838 if (hw->mac_type == em_82542_rev2_0) { 839 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 840 em_pci_clear_mwi(hw); 841 } 842 if (hw->bus_type == em_bus_type_pci_express) { 843 /* 844 * Prevent the PCI-E bus from sticking if there is no TLP 845 * connection on the last TLP read/write transaction when MAC 846 * is reset. 847 */ 848 if (em_disable_pciex_master(hw) != E1000_SUCCESS) { 849 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 850 } 851 } 852 853 /* Set the completion timeout for 82575 chips */ 854 if (hw->mac_type == em_82575 || hw->mac_type == em_82580 || 855 hw->mac_type == em_82576 || 856 hw->mac_type == em_i210 || hw->mac_type == em_i350) { 857 ret_val = em_set_pciex_completion_timeout(hw); 858 if (ret_val) { 859 DEBUGOUT("PCI-E Set completion timeout has failed.\n"); 860 } 861 } 862 863 /* Clear interrupt mask to stop board from generating interrupts */ 864 DEBUGOUT("Masking off all interrupts\n"); 865 E1000_WRITE_REG(hw, IMC, 0xffffffff); 866 /* 867 * Disable the Transmit and Receive units. Then delay to allow any 868 * pending transactions to complete before we hit the MAC with the 869 * global reset. 870 */ 871 E1000_WRITE_REG(hw, RCTL, 0); 872 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP); 873 E1000_WRITE_FLUSH(hw); 874 /* 875 * The tbi_compatibility_on Flag must be cleared when Rctl is 876 * cleared. 877 */ 878 hw->tbi_compatibility_on = FALSE; 879 /* 880 * Delay to allow any outstanding PCI transactions to complete before 881 * resetting the device 882 */ 883 msec_delay(10); 884 885 ctrl = E1000_READ_REG(hw, CTRL); 886 887 /* Must reset the PHY before resetting the MAC */ 888 if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) { 889 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST)); 890 msec_delay(5); 891 } 892 /* 893 * Must acquire the MDIO ownership before MAC reset. Ownership 894 * defaults to firmware after a reset. 895 */ 896 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) { 897 timeout = 10; 898 899 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 900 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 901 902 do { 903 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); 904 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 905 906 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) 907 break; 908 else 909 extcnf_ctrl |= 910 E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 911 912 msec_delay(2); 913 timeout--; 914 } while (timeout); 915 } 916 /* Workaround for ICH8 bit corruption issue in FIFO memory */ 917 if (hw->mac_type == em_ich8lan) { 918 /* Set Tx and Rx buffer allocation to 8k apiece. */ 919 E1000_WRITE_REG(hw, PBA, E1000_PBA_8K); 920 /* Set Packet Buffer Size to 16k. */ 921 E1000_WRITE_REG(hw, PBS, E1000_PBS_16K); 922 } 923 /* 924 * Issue a global reset to the MAC. This will reset the chip's 925 * transmit, receive, DMA, and link units. It will not effect the 926 * current PCI configuration. The global reset bit is self- 927 * clearing, and should clear within a microsecond. 928 */ 929 DEBUGOUT("Issuing a global reset to MAC\n"); 930 931 switch (hw->mac_type) { 932 case em_82544: 933 case em_82540: 934 case em_82545: 935 case em_82546: 936 case em_82541: 937 case em_82541_rev_2: 938 /* 939 * These controllers can't ack the 64-bit write when issuing 940 * the reset, so use IO-mapping as a workaround to issue the 941 * reset 942 */ 943 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST)); 944 break; 945 case em_82545_rev_3: 946 case em_82546_rev_3: 947 /* Reset is performed on a shadow of the control register */ 948 E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST)); 949 break; 950 case em_ich8lan: 951 case em_ich9lan: 952 case em_ich10lan: 953 case em_pchlan: 954 case em_pch2lan: 955 case em_pch_lpt: 956 case em_pch_spt: 957 case em_pch_cnp: 958 if (!hw->phy_reset_disable && 959 em_check_phy_reset_block(hw) == E1000_SUCCESS) { 960 /* 961 * PHY HW reset requires MAC CORE reset at the same 962 * time to make sure the interface between MAC and 963 * the external PHY is reset. 964 */ 965 ctrl |= E1000_CTRL_PHY_RST; 966 /* 967 * Gate automatic PHY configuration by hardware on 968 * non-managed 82579 969 */ 970 if ((hw->mac_type == em_pch2lan) && 971 !(E1000_READ_REG(hw, FWSM) & E1000_FWSM_FW_VALID)) { 972 em_gate_hw_phy_config_ich8lan(hw, TRUE); 973 } 974 } 975 em_get_software_flag(hw); 976 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); 977 /* HW reset releases software_flag */ 978 hw->sw_flag = 0; 979 msec_delay(20); 980 981 /* Ungate automatic PHY configuration on non-managed 82579 */ 982 if (hw->mac_type == em_pch2lan && !hw->phy_reset_disable && 983 !(E1000_READ_REG(hw, FWSM) & E1000_FWSM_FW_VALID)) { 984 msec_delay(10); 985 em_gate_hw_phy_config_ich8lan(hw, FALSE); 986 } 987 break; 988 default: 989 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); 990 break; 991 } 992 993 if (em_check_phy_reset_block(hw) == E1000_SUCCESS) { 994 if (hw->mac_type == em_pchlan) { 995 ret_val = em_hv_phy_workarounds_ich8lan(hw); 996 if (ret_val) 997 return ret_val; 998 } 999 else if (hw->mac_type == em_pch2lan) { 1000 ret_val = em_lv_phy_workarounds_ich8lan(hw); 1001 if (ret_val) 1002 return ret_val; 1003 } 1004 } 1005 1006 /* 1007 * After MAC reset, force reload of EEPROM to restore power-on 1008 * settings to device. Later controllers reload the EEPROM 1009 * automatically, so just wait for reload to complete. 1010 */ 1011 switch (hw->mac_type) { 1012 case em_82542_rev2_0: 1013 case em_82542_rev2_1: 1014 case em_82543: 1015 case em_82544: 1016 /* Wait for reset to complete */ 1017 usec_delay(10); 1018 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1019 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 1020 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1021 E1000_WRITE_FLUSH(hw); 1022 /* Wait for EEPROM reload */ 1023 msec_delay(2); 1024 break; 1025 case em_82541: 1026 case em_82541_rev_2: 1027 case em_82547: 1028 case em_82547_rev_2: 1029 /* Wait for EEPROM reload */ 1030 msec_delay(20); 1031 break; 1032 case em_82573: 1033 case em_82574: 1034 if (em_is_onboard_nvm_eeprom(hw) == FALSE) { 1035 usec_delay(10); 1036 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1037 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 1038 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1039 E1000_WRITE_FLUSH(hw); 1040 } 1041 /* FALLTHROUGH */ 1042 1043 /* Auto read done will delay 5ms or poll based on mac type */ 1044 ret_val = em_get_auto_rd_done(hw); 1045 if (ret_val) 1046 return ret_val; 1047 break; 1048 default: 1049 /* Wait for EEPROM reload (it happens automatically) */ 1050 msec_delay(5); 1051 break; 1052 } 1053 1054 /* Disable HW ARPs on ASF enabled adapters */ 1055 if (hw->mac_type >= em_82540 && hw->mac_type <= em_82547_rev_2 && 1056 hw->mac_type != em_icp_xxxx) { 1057 manc = E1000_READ_REG(hw, MANC); 1058 manc &= ~(E1000_MANC_ARP_EN); 1059 E1000_WRITE_REG(hw, MANC, manc); 1060 } 1061 if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) { 1062 em_phy_init_script(hw); 1063 1064 /* Configure activity LED after PHY reset */ 1065 led_ctrl = E1000_READ_REG(hw, LEDCTL); 1066 led_ctrl &= IGP_ACTIVITY_LED_MASK; 1067 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 1068 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 1069 } 1070 1071 /* 1072 * For PCH, this write will make sure that any noise 1073 * will be detected as a CRC error and be dropped rather than show up 1074 * as a bad packet to the DMA engine. 1075 */ 1076 if (hw->mac_type == em_pchlan) 1077 E1000_WRITE_REG(hw, CRC_OFFSET, 0x65656565); 1078 1079 /* Clear interrupt mask to stop board from generating interrupts */ 1080 DEBUGOUT("Masking off all interrupts\n"); 1081 E1000_WRITE_REG(hw, IMC, 0xffffffff); 1082 1083 /* Clear any pending interrupt events. */ 1084 icr = E1000_READ_REG(hw, ICR); 1085 1086 /* If MWI was previously enabled, reenable it. */ 1087 if (hw->mac_type == em_82542_rev2_0) { 1088 if (hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1089 em_pci_set_mwi(hw); 1090 } 1091 if (IS_ICH8(hw->mac_type)) { 1092 uint32_t kab = E1000_READ_REG(hw, KABGTXD); 1093 kab |= E1000_KABGTXD_BGSQLBIAS; 1094 E1000_WRITE_REG(hw, KABGTXD, kab); 1095 } 1096 1097 if (hw->mac_type == em_82580 || hw->mac_type == em_i350) { 1098 uint32_t mdicnfg; 1099 uint16_t nvm_data; 1100 1101 /* clear global device reset status bit */ 1102 EM_WRITE_REG(hw, E1000_STATUS, E1000_STATUS_DEV_RST_SET); 1103 1104 em_read_eeprom(hw, EEPROM_INIT_CONTROL3_PORT_A + 1105 NVM_82580_LAN_FUNC_OFFSET(hw->bus_func), 1, 1106 &nvm_data); 1107 1108 mdicnfg = EM_READ_REG(hw, E1000_MDICNFG); 1109 if (nvm_data & NVM_WORD24_EXT_MDIO) 1110 mdicnfg |= E1000_MDICNFG_EXT_MDIO; 1111 if (nvm_data & NVM_WORD24_COM_MDIO) 1112 mdicnfg |= E1000_MDICNFG_COM_MDIO; 1113 EM_WRITE_REG(hw, E1000_MDICNFG, mdicnfg); 1114 } 1115 1116 if (hw->mac_type == em_i210 || hw->mac_type == em_i350) 1117 em_set_eee_i350(hw); 1118 1119 return E1000_SUCCESS; 1120 } 1121 1122 /****************************************************************************** 1123 * 1124 * Initialize a number of hardware-dependent bits 1125 * 1126 * hw: Struct containing variables accessed by shared code 1127 * 1128 *****************************************************************************/ 1129 STATIC void 1130 em_initialize_hardware_bits(struct em_softc *sc) 1131 { 1132 struct em_hw *hw = &sc->hw; 1133 struct em_queue *que; 1134 1135 DEBUGFUNC("em_initialize_hardware_bits"); 1136 1137 if ((hw->mac_type >= em_82571) && (!hw->initialize_hw_bits_disable)) { 1138 /* Settings common to all silicon */ 1139 uint32_t reg_ctrl, reg_ctrl_ext; 1140 uint32_t reg_tarc0, reg_tarc1; 1141 uint32_t reg_tctl; 1142 uint32_t reg_txdctl; 1143 reg_tarc0 = E1000_READ_REG(hw, TARC0); 1144 reg_tarc0 &= ~0x78000000; /* Clear bits 30, 29, 28, and 1145 * 27 */ 1146 FOREACH_QUEUE(sc, que) { 1147 reg_txdctl = E1000_READ_REG(hw, TXDCTL(que->me)); 1148 reg_txdctl |= E1000_TXDCTL_COUNT_DESC; /* Set bit 22 */ 1149 E1000_WRITE_REG(hw, TXDCTL(que->me), reg_txdctl); 1150 } 1151 1152 /* 1153 * Old code always initialized queue 1, 1154 * even when unused, keep behaviour 1155 */ 1156 if (sc->num_queues == 1) { 1157 reg_txdctl = E1000_READ_REG(hw, TXDCTL(1)); 1158 reg_txdctl |= E1000_TXDCTL_COUNT_DESC; 1159 E1000_WRITE_REG(hw, TXDCTL(1), reg_txdctl); 1160 } 1161 1162 switch (hw->mac_type) { 1163 case em_82571: 1164 case em_82572: 1165 reg_tarc1 = E1000_READ_REG(hw, TARC1); 1166 reg_tctl = E1000_READ_REG(hw, TCTL); 1167 1168 /* Set the phy Tx compatible mode bits */ 1169 reg_tarc1 &= ~0x60000000; /* Clear bits 30 and 29 */ 1170 1171 reg_tarc0 |= 0x07800000; /* Set TARC0 bits 23-26 */ 1172 reg_tarc1 |= 0x07000000; /* Set TARC1 bits 24-26 */ 1173 1174 if (reg_tctl & E1000_TCTL_MULR) 1175 /* Clear bit 28 if MULR is 1b */ 1176 reg_tarc1 &= ~0x10000000; 1177 else 1178 /* Set bit 28 if MULR is 0b */ 1179 reg_tarc1 |= 0x10000000; 1180 1181 E1000_WRITE_REG(hw, TARC1, reg_tarc1); 1182 break; 1183 case em_82573: 1184 case em_82574: 1185 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1186 reg_ctrl = E1000_READ_REG(hw, CTRL); 1187 1188 reg_ctrl_ext &= ~0x00800000; /* Clear bit 23 */ 1189 reg_ctrl_ext |= 0x00400000; /* Set bit 22 */ 1190 reg_ctrl &= ~0x20000000; /* Clear bit 29 */ 1191 1192 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); 1193 E1000_WRITE_REG(hw, CTRL, reg_ctrl); 1194 break; 1195 case em_80003es2lan: 1196 if ((hw->media_type == em_media_type_fiber) || 1197 (hw->media_type == em_media_type_internal_serdes)) { 1198 /* Clear bit 20 */ 1199 reg_tarc0 &= ~0x00100000; 1200 } 1201 reg_tctl = E1000_READ_REG(hw, TCTL); 1202 reg_tarc1 = E1000_READ_REG(hw, TARC1); 1203 if (reg_tctl & E1000_TCTL_MULR) 1204 /* Clear bit 28 if MULR is 1b */ 1205 reg_tarc1 &= ~0x10000000; 1206 else 1207 /* Set bit 28 if MULR is 0b */ 1208 reg_tarc1 |= 0x10000000; 1209 1210 E1000_WRITE_REG(hw, TARC1, reg_tarc1); 1211 break; 1212 case em_ich8lan: 1213 case em_ich9lan: 1214 case em_ich10lan: 1215 case em_pchlan: 1216 case em_pch2lan: 1217 case em_pch_lpt: 1218 case em_pch_spt: 1219 case em_pch_cnp: 1220 if (hw->mac_type == em_ich8lan) 1221 /* Set TARC0 bits 29 and 28 */ 1222 reg_tarc0 |= 0x30000000; 1223 1224 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1225 reg_ctrl_ext |= 0x00400000; /* Set bit 22 */ 1226 /* Enable PHY low-power state when MAC is at D3 w/o WoL */ 1227 if (hw->mac_type >= em_pchlan) 1228 reg_ctrl_ext |= E1000_CTRL_EXT_PHYPDEN; 1229 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); 1230 1231 reg_tarc0 |= 0x0d800000; /* Set TARC0 bits 23, 1232 * 24, 26, 27 */ 1233 1234 reg_tarc1 = E1000_READ_REG(hw, TARC1); 1235 reg_tctl = E1000_READ_REG(hw, TCTL); 1236 1237 if (reg_tctl & E1000_TCTL_MULR) 1238 /* Clear bit 28 if MULR is 1b */ 1239 reg_tarc1 &= ~0x10000000; 1240 else 1241 /* Set bit 28 if MULR is 0b */ 1242 reg_tarc1 |= 0x10000000; 1243 1244 reg_tarc1 |= 0x45000000; /* Set bit 24, 26 and 1245 * 30 */ 1246 1247 E1000_WRITE_REG(hw, TARC1, reg_tarc1); 1248 break; 1249 default: 1250 break; 1251 } 1252 1253 E1000_WRITE_REG(hw, TARC0, reg_tarc0); 1254 } 1255 } 1256 1257 /** 1258 * e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value 1259 * @hw: pointer to the HW structure 1260 * 1261 * Toggling the LANPHYPC pin value fully power-cycles the PHY and is 1262 * used to reset the PHY to a quiescent state when necessary. 1263 **/ 1264 static void 1265 em_toggle_lanphypc_pch_lpt(struct em_hw *hw) 1266 { 1267 uint32_t mac_reg; 1268 1269 DEBUGFUNC("e1000_toggle_lanphypc_pch_lpt"); 1270 1271 /* Set Phy Config Counter to 50msec */ 1272 mac_reg = E1000_READ_REG(hw, FEXTNVM3); 1273 mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK; 1274 mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC; 1275 E1000_WRITE_REG(hw, FEXTNVM3, mac_reg); 1276 1277 /* Toggle LANPHYPC Value bit */ 1278 mac_reg = E1000_READ_REG(hw, CTRL); 1279 mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE; 1280 mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE; 1281 E1000_WRITE_REG(hw, CTRL, mac_reg); 1282 E1000_WRITE_FLUSH(hw); 1283 msec_delay(1); 1284 mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE; 1285 E1000_WRITE_REG(hw, CTRL, mac_reg); 1286 E1000_WRITE_FLUSH(hw); 1287 1288 if (hw->mac_type < em_pch_lpt) { 1289 msec_delay(50); 1290 } else { 1291 uint16_t count = 20; 1292 1293 do { 1294 msec_delay(5); 1295 } while (!(E1000_READ_REG(hw, CTRL_EXT) & 1296 E1000_CTRL_EXT_LPCD) && count--); 1297 1298 msec_delay(30); 1299 } 1300 } 1301 1302 /** 1303 * em_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP 1304 * @hw: pointer to the HW structure 1305 * @force: boolean indicating whether or not to force disabling ULP 1306 * 1307 * Un-configure ULP mode when link is up, the system is transitioned from 1308 * Sx or the driver is unloaded. If on a Manageability Engine (ME) enabled 1309 * system, poll for an indication from ME that ULP has been un-configured. 1310 * If not on an ME enabled system, un-configure the ULP mode by software. 1311 * 1312 * During nominal operation, this function is called when link is acquired 1313 * to disable ULP mode (force=FALSE); otherwise, for example when unloading 1314 * the driver or during Sx->S0 transitions, this is called with force=TRUE 1315 * to forcibly disable ULP. 1316 */ 1317 static int 1318 em_disable_ulp_lpt_lp(struct em_hw *hw, bool force) 1319 { 1320 int ret_val = E1000_SUCCESS; 1321 uint32_t mac_reg; 1322 uint16_t phy_reg; 1323 int i = 0; 1324 1325 if ((hw->mac_type < em_pch_lpt) || 1326 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) || 1327 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) || 1328 (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) || 1329 (hw->device_id == E1000_DEV_ID_PCH_I218_V2)) 1330 return 0; 1331 1332 if (E1000_READ_REG(hw, FWSM) & E1000_FWSM_FW_VALID) { 1333 if (force) { 1334 /* Request ME un-configure ULP mode in the PHY */ 1335 mac_reg = E1000_READ_REG(hw, H2ME); 1336 mac_reg &= ~E1000_H2ME_ULP; 1337 mac_reg |= E1000_H2ME_ENFORCE_SETTINGS; 1338 E1000_WRITE_REG(hw, H2ME, mac_reg); 1339 } 1340 1341 /* Poll up to 300msec for ME to clear ULP_CFG_DONE. */ 1342 while (E1000_READ_REG(hw, FWSM) & E1000_FWSM_ULP_CFG_DONE) { 1343 if (i++ == 30) { 1344 ret_val = -E1000_ERR_PHY; 1345 goto out; 1346 } 1347 1348 msec_delay(10); 1349 } 1350 DEBUGOUT1("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10); 1351 1352 if (force) { 1353 mac_reg = E1000_READ_REG(hw, H2ME); 1354 mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS; 1355 E1000_WRITE_REG(hw, H2ME, mac_reg); 1356 } else { 1357 /* Clear H2ME.ULP after ME ULP configuration */ 1358 mac_reg = E1000_READ_REG(hw, H2ME); 1359 mac_reg &= ~E1000_H2ME_ULP; 1360 E1000_WRITE_REG(hw, H2ME, mac_reg); 1361 } 1362 1363 goto out; 1364 } 1365 1366 ret_val = em_get_software_flag(hw); 1367 if (ret_val) 1368 goto out; 1369 1370 if (force) 1371 /* Toggle LANPHYPC Value bit */ 1372 em_toggle_lanphypc_pch_lpt(hw); 1373 1374 /* Unforce SMBus mode in PHY */ 1375 ret_val = em_read_phy_reg(hw, CV_SMB_CTRL, &phy_reg); 1376 if (ret_val) { 1377 /* The MAC might be in PCIe mode, so temporarily force to 1378 * SMBus mode in order to access the PHY. 1379 */ 1380 mac_reg = E1000_READ_REG(hw, CTRL_EXT); 1381 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS; 1382 E1000_WRITE_REG(hw, CTRL_EXT, mac_reg); 1383 1384 msec_delay(50); 1385 1386 ret_val = em_read_phy_reg(hw, CV_SMB_CTRL, &phy_reg); 1387 if (ret_val) 1388 goto release; 1389 } 1390 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS; 1391 em_write_phy_reg(hw, CV_SMB_CTRL, phy_reg); 1392 1393 /* Unforce SMBus mode in MAC */ 1394 mac_reg = E1000_READ_REG(hw, CTRL_EXT); 1395 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; 1396 E1000_WRITE_REG(hw, CTRL_EXT, mac_reg); 1397 1398 /* When ULP mode was previously entered, K1 was disabled by the 1399 * hardware. Re-Enable K1 in the PHY when exiting ULP. 1400 */ 1401 ret_val = em_read_phy_reg(hw, HV_PM_CTRL, &phy_reg); 1402 if (ret_val) 1403 goto release; 1404 phy_reg |= HV_PM_CTRL_K1_ENABLE; 1405 em_write_phy_reg(hw, HV_PM_CTRL, phy_reg); 1406 1407 /* Clear ULP enabled configuration */ 1408 ret_val = em_read_phy_reg(hw, I218_ULP_CONFIG1, &phy_reg); 1409 if (ret_val) 1410 goto release; 1411 phy_reg &= ~(I218_ULP_CONFIG1_IND | 1412 I218_ULP_CONFIG1_STICKY_ULP | 1413 I218_ULP_CONFIG1_RESET_TO_SMBUS | 1414 I218_ULP_CONFIG1_WOL_HOST | 1415 I218_ULP_CONFIG1_INBAND_EXIT | 1416 I218_ULP_CONFIG1_EN_ULP_LANPHYPC | 1417 I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST | 1418 I218_ULP_CONFIG1_DISABLE_SMB_PERST); 1419 em_write_phy_reg(hw, I218_ULP_CONFIG1, phy_reg); 1420 1421 /* Commit ULP changes by starting auto ULP configuration */ 1422 phy_reg |= I218_ULP_CONFIG1_START; 1423 em_write_phy_reg(hw, I218_ULP_CONFIG1, phy_reg); 1424 1425 /* Clear Disable SMBus Release on PERST# in MAC */ 1426 mac_reg = E1000_READ_REG(hw, FEXTNVM7); 1427 mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST; 1428 E1000_WRITE_REG(hw, FEXTNVM7, mac_reg); 1429 1430 release: 1431 em_release_software_flag(hw); 1432 if (force) { 1433 em_phy_reset(hw); 1434 msec_delay(50); 1435 } 1436 out: 1437 if (ret_val) 1438 DEBUGOUT1("Error in ULP disable flow: %d\n", ret_val); 1439 1440 return ret_val; 1441 } 1442 1443 /****************************************************************************** 1444 * Performs basic configuration of the adapter. 1445 * 1446 * hw - Struct containing variables accessed by shared code 1447 * 1448 * Assumes that the controller has previously been reset and is in a 1449 * post-reset uninitialized state. Initializes the receive address registers, 1450 * multicast table, and VLAN filter table. Calls routines to setup link 1451 * configuration and flow control settings. Clears all on-chip counters. Leaves 1452 * the transmit and receive units disabled and uninitialized. 1453 *****************************************************************************/ 1454 int32_t 1455 em_init_hw(struct em_softc *sc) 1456 { 1457 struct em_hw *hw = &sc->hw; 1458 struct em_queue *que; 1459 uint32_t ctrl; 1460 uint32_t i; 1461 int32_t ret_val; 1462 uint16_t pcix_cmd_word; 1463 uint16_t pcix_stat_hi_word; 1464 uint16_t cmd_mmrbc; 1465 uint16_t stat_mmrbc; 1466 uint32_t mta_size; 1467 uint32_t reg_data; 1468 uint32_t ctrl_ext; 1469 uint32_t snoop; 1470 uint32_t fwsm; 1471 DEBUGFUNC("em_init_hw"); 1472 1473 /* force full DMA clock frequency for ICH8 */ 1474 if (hw->mac_type == em_ich8lan) { 1475 reg_data = E1000_READ_REG(hw, STATUS); 1476 reg_data &= ~0x80000000; 1477 E1000_WRITE_REG(hw, STATUS, reg_data); 1478 } 1479 1480 if (hw->mac_type == em_pchlan || 1481 hw->mac_type == em_pch2lan || 1482 hw->mac_type == em_pch_lpt || 1483 hw->mac_type == em_pch_spt || 1484 hw->mac_type == em_pch_cnp) { 1485 /* 1486 * The MAC-PHY interconnect may still be in SMBus mode 1487 * after Sx->S0. Toggle the LANPHYPC Value bit to force 1488 * the interconnect to PCIe mode, but only if there is no 1489 * firmware present otherwise firmware will have done it. 1490 */ 1491 fwsm = E1000_READ_REG(hw, FWSM); 1492 if ((fwsm & E1000_FWSM_FW_VALID) == 0) { 1493 ctrl = E1000_READ_REG(hw, CTRL); 1494 ctrl |= E1000_CTRL_LANPHYPC_OVERRIDE; 1495 ctrl &= ~E1000_CTRL_LANPHYPC_VALUE; 1496 E1000_WRITE_REG(hw, CTRL, ctrl); 1497 usec_delay(10); 1498 ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE; 1499 E1000_WRITE_REG(hw, CTRL, ctrl); 1500 msec_delay(50); 1501 } 1502 1503 /* Gate automatic PHY configuration on non-managed 82579 */ 1504 if (hw->mac_type == em_pch2lan) 1505 em_gate_hw_phy_config_ich8lan(hw, TRUE); 1506 1507 em_disable_ulp_lpt_lp(hw, TRUE); 1508 /* 1509 * Reset the PHY before any acccess to it. Doing so, 1510 * ensures that the PHY is in a known good state before 1511 * we read/write PHY registers. The generic reset is 1512 * sufficient here, because we haven't determined 1513 * the PHY type yet. 1514 */ 1515 em_phy_reset(hw); 1516 1517 /* Ungate automatic PHY configuration on non-managed 82579 */ 1518 if (hw->mac_type == em_pch2lan && 1519 (fwsm & E1000_FWSM_FW_VALID) == 0) 1520 em_gate_hw_phy_config_ich8lan(hw, FALSE); 1521 1522 /* Set MDIO slow mode before any other MDIO access */ 1523 ret_val = em_set_mdio_slow_mode_hv(hw); 1524 if (ret_val) 1525 return ret_val; 1526 } 1527 1528 /* Initialize Identification LED */ 1529 ret_val = em_id_led_init(hw); 1530 if (ret_val) { 1531 DEBUGOUT("Error Initializing Identification LED\n"); 1532 return ret_val; 1533 } 1534 /* Set the media type and TBI compatibility */ 1535 em_set_media_type(hw); 1536 1537 /* Magic delay that improves problems with i219LM on HP Elitebook */ 1538 msec_delay(1); 1539 /* Must be called after em_set_media_type because media_type is used */ 1540 em_initialize_hardware_bits(sc); 1541 1542 /* Disabling VLAN filtering. */ 1543 DEBUGOUT("Initializing the IEEE VLAN\n"); 1544 /* VET hardcoded to standard value and VFTA removed in ICH8/ICH9 LAN */ 1545 if (!IS_ICH8(hw->mac_type)) { 1546 if (hw->mac_type < em_82545_rev_3) 1547 E1000_WRITE_REG(hw, VET, 0); 1548 if (hw->mac_type == em_i350) 1549 em_clear_vfta_i350(hw); 1550 else 1551 em_clear_vfta(hw); 1552 } 1553 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ 1554 if (hw->mac_type == em_82542_rev2_0) { 1555 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 1556 em_pci_clear_mwi(hw); 1557 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST); 1558 E1000_WRITE_FLUSH(hw); 1559 msec_delay(5); 1560 } 1561 /* 1562 * Setup the receive address. This involves initializing all of the 1563 * Receive Address Registers (RARs 0 - 15). 1564 */ 1565 em_init_rx_addrs(hw); 1566 1567 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI*/ 1568 if (hw->mac_type == em_82542_rev2_0) { 1569 E1000_WRITE_REG(hw, RCTL, 0); 1570 E1000_WRITE_FLUSH(hw); 1571 msec_delay(1); 1572 if (hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1573 em_pci_set_mwi(hw); 1574 } 1575 /* Zero out the Multicast HASH table */ 1576 DEBUGOUT("Zeroing the MTA\n"); 1577 mta_size = E1000_MC_TBL_SIZE; 1578 if (IS_ICH8(hw->mac_type)) 1579 mta_size = E1000_MC_TBL_SIZE_ICH8LAN; 1580 for (i = 0; i < mta_size; i++) { 1581 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 1582 /* 1583 * use write flush to prevent Memory Write Block (MWB) from 1584 * occuring when accessing our register space 1585 */ 1586 E1000_WRITE_FLUSH(hw); 1587 } 1588 /* 1589 * Set the PCI priority bit correctly in the CTRL register. This 1590 * determines if the adapter gives priority to receives, or if it 1591 * gives equal priority to transmits and receives. Valid only on 1592 * 82542 and 82543 silicon. 1593 */ 1594 if (hw->dma_fairness && hw->mac_type <= em_82543) { 1595 ctrl = E1000_READ_REG(hw, CTRL); 1596 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR); 1597 } 1598 switch (hw->mac_type) { 1599 case em_82545_rev_3: 1600 case em_82546_rev_3: 1601 break; 1602 default: 1603 /* 1604 * Workaround for PCI-X problem when BIOS sets MMRBC 1605 * incorrectly. 1606 */ 1607 if (hw->bus_type == em_bus_type_pcix) { 1608 em_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, 1609 &pcix_cmd_word); 1610 em_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, 1611 &pcix_stat_hi_word); 1612 cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) 1613 >> PCIX_COMMAND_MMRBC_SHIFT; 1614 stat_mmrbc = (pcix_stat_hi_word & 1615 PCIX_STATUS_HI_MMRBC_MASK) >> 1616 PCIX_STATUS_HI_MMRBC_SHIFT; 1617 1618 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) 1619 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; 1620 if (cmd_mmrbc > stat_mmrbc) { 1621 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK; 1622 pcix_cmd_word |= stat_mmrbc << 1623 PCIX_COMMAND_MMRBC_SHIFT; 1624 em_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, 1625 &pcix_cmd_word); 1626 } 1627 } 1628 break; 1629 } 1630 1631 /* More time needed for PHY to initialize */ 1632 if (IS_ICH8(hw->mac_type)) 1633 msec_delay(15); 1634 1635 /* 1636 * The 82578 Rx buffer will stall if wakeup is enabled in host and 1637 * the ME. Reading the BM_WUC register will clear the host wakeup bit. 1638 * Reset the phy after disabling host wakeup to reset the Rx buffer. 1639 */ 1640 if (hw->phy_type == em_phy_82578) { 1641 em_read_phy_reg(hw, PHY_REG(BM_WUC_PAGE, 1), 1642 (uint16_t *)®_data); 1643 ret_val = em_phy_reset(hw); 1644 if (ret_val) 1645 return ret_val; 1646 } 1647 1648 /* Call a subroutine to configure the link and setup flow control. */ 1649 ret_val = em_setup_link(hw); 1650 1651 /* Set the transmit descriptor write-back policy */ 1652 if (hw->mac_type > em_82544) { 1653 FOREACH_QUEUE(sc, que) { 1654 ctrl = E1000_READ_REG(hw, TXDCTL(que->me)); 1655 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | 1656 E1000_TXDCTL_FULL_TX_DESC_WB; 1657 E1000_WRITE_REG(hw, TXDCTL(que->me), ctrl); 1658 } 1659 } 1660 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) { 1661 em_enable_tx_pkt_filtering(hw); 1662 } 1663 switch (hw->mac_type) { 1664 default: 1665 break; 1666 case em_80003es2lan: 1667 /* Enable retransmit on late collisions */ 1668 reg_data = E1000_READ_REG(hw, TCTL); 1669 reg_data |= E1000_TCTL_RTLC; 1670 E1000_WRITE_REG(hw, TCTL, reg_data); 1671 1672 /* Configure Gigabit Carry Extend Padding */ 1673 reg_data = E1000_READ_REG(hw, TCTL_EXT); 1674 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK; 1675 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX; 1676 E1000_WRITE_REG(hw, TCTL_EXT, reg_data); 1677 1678 /* Configure Transmit Inter-Packet Gap */ 1679 reg_data = E1000_READ_REG(hw, TIPG); 1680 reg_data &= ~E1000_TIPG_IPGT_MASK; 1681 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; 1682 E1000_WRITE_REG(hw, TIPG, reg_data); 1683 1684 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001); 1685 reg_data &= ~0x00100000; 1686 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data); 1687 /* FALLTHROUGH */ 1688 case em_82571: 1689 case em_82572: 1690 case em_82575: 1691 case em_82576: 1692 case em_82580: 1693 case em_i210: 1694 case em_i350: 1695 case em_ich8lan: 1696 case em_ich9lan: 1697 case em_ich10lan: 1698 case em_pchlan: 1699 case em_pch2lan: 1700 case em_pch_lpt: 1701 case em_pch_spt: 1702 case em_pch_cnp: 1703 /* 1704 * Old code always initialized queue 1, 1705 * even when unused, keep behaviour 1706 */ 1707 if (sc->num_queues == 1) { 1708 ctrl = E1000_READ_REG(hw, TXDCTL(1)); 1709 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | 1710 E1000_TXDCTL_FULL_TX_DESC_WB; 1711 E1000_WRITE_REG(hw, TXDCTL(1), ctrl); 1712 } 1713 break; 1714 } 1715 1716 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) { 1717 uint32_t gcr = E1000_READ_REG(hw, GCR); 1718 gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; 1719 E1000_WRITE_REG(hw, GCR, gcr); 1720 } 1721 /* 1722 * Clear all of the statistics registers (clear on read). It is 1723 * important that we do this after we have tried to establish link 1724 * because the symbol error count will increment wildly if there is 1725 * no link. 1726 */ 1727 em_clear_hw_cntrs(hw); 1728 /* 1729 * ICH8 No-snoop bits are opposite polarity. Set to snoop by default 1730 * after reset. 1731 */ 1732 if (IS_ICH8(hw->mac_type)) { 1733 if (hw->mac_type == em_ich8lan) 1734 snoop = PCI_EX_82566_SNOOP_ALL; 1735 else 1736 snoop = (u_int32_t) ~ (PCI_EX_NO_SNOOP_ALL); 1737 1738 em_set_pci_ex_no_snoop(hw, snoop); 1739 } 1740 1741 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER || 1742 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) { 1743 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1744 /* 1745 * Relaxed ordering must be disabled to avoid a parity error 1746 * crash in a PCI slot. 1747 */ 1748 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 1749 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1750 } 1751 return ret_val; 1752 } 1753 1754 /****************************************************************************** 1755 * Adjust SERDES output amplitude based on EEPROM setting. 1756 * 1757 * hw - Struct containing variables accessed by shared code. 1758 *****************************************************************************/ 1759 static int32_t 1760 em_adjust_serdes_amplitude(struct em_hw *hw) 1761 { 1762 uint16_t eeprom_data; 1763 int32_t ret_val; 1764 DEBUGFUNC("em_adjust_serdes_amplitude"); 1765 1766 if (hw->media_type != em_media_type_internal_serdes || 1767 hw->mac_type >= em_82575) 1768 return E1000_SUCCESS; 1769 1770 switch (hw->mac_type) { 1771 case em_82545_rev_3: 1772 case em_82546_rev_3: 1773 break; 1774 default: 1775 return E1000_SUCCESS; 1776 } 1777 1778 ret_val = em_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data); 1779 if (ret_val) { 1780 return ret_val; 1781 } 1782 if (eeprom_data != EEPROM_RESERVED_WORD) { 1783 /* Adjust SERDES output amplitude only. */ 1784 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK; 1785 ret_val = em_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, 1786 eeprom_data); 1787 if (ret_val) 1788 return ret_val; 1789 } 1790 return E1000_SUCCESS; 1791 } 1792 1793 /****************************************************************************** 1794 * Configures flow control and link settings. 1795 * 1796 * hw - Struct containing variables accessed by shared code 1797 * 1798 * Determines which flow control settings to use. Calls the appropriate media- 1799 * specific link configuration function. Configures the flow control settings. 1800 * Assuming the adapter has a valid link partner, a valid link should be 1801 * established. Assumes the hardware has previously been reset and the 1802 * transmitter and receiver are not enabled. 1803 *****************************************************************************/ 1804 int32_t 1805 em_setup_link(struct em_hw *hw) 1806 { 1807 uint32_t ctrl_ext; 1808 int32_t ret_val; 1809 uint16_t eeprom_data; 1810 uint16_t eeprom_control2_reg_offset; 1811 DEBUGFUNC("em_setup_link"); 1812 1813 eeprom_control2_reg_offset = 1814 (hw->mac_type != em_icp_xxxx) 1815 ? EEPROM_INIT_CONTROL2_REG 1816 : EEPROM_INIT_CONTROL3_ICP_xxxx(hw->icp_xxxx_port_num); 1817 /* 1818 * In the case of the phy reset being blocked, we already have a 1819 * link. We do not have to set it up again. 1820 */ 1821 if (em_check_phy_reset_block(hw)) 1822 return E1000_SUCCESS; 1823 /* 1824 * Read and store word 0x0F of the EEPROM. This word contains bits 1825 * that determine the hardware's default PAUSE (flow control) mode, a 1826 * bit that determines whether the HW defaults to enabling or 1827 * disabling auto-negotiation, and the direction of the SW defined 1828 * pins. If there is no SW over-ride of the flow control setting, 1829 * then the variable hw->fc will be initialized based on a value in 1830 * the EEPROM. 1831 */ 1832 if (hw->fc == E1000_FC_DEFAULT) { 1833 switch (hw->mac_type) { 1834 case em_ich8lan: 1835 case em_ich9lan: 1836 case em_ich10lan: 1837 case em_pchlan: 1838 case em_pch2lan: 1839 case em_pch_lpt: 1840 case em_pch_spt: 1841 case em_pch_cnp: 1842 case em_82573: 1843 case em_82574: 1844 hw->fc = E1000_FC_FULL; 1845 break; 1846 default: 1847 ret_val = em_read_eeprom(hw, 1848 eeprom_control2_reg_offset, 1, &eeprom_data); 1849 if (ret_val) { 1850 DEBUGOUT("EEPROM Read Error\n"); 1851 return -E1000_ERR_EEPROM; 1852 } 1853 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0) 1854 hw->fc = E1000_FC_NONE; 1855 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 1856 EEPROM_WORD0F_ASM_DIR) 1857 hw->fc = E1000_FC_TX_PAUSE; 1858 else 1859 hw->fc = E1000_FC_FULL; 1860 break; 1861 } 1862 } 1863 /* 1864 * We want to save off the original Flow Control configuration just 1865 * in case we get disconnected and then reconnected into a different 1866 * hub or switch with different Flow Control capabilities. 1867 */ 1868 if (hw->mac_type == em_82542_rev2_0) 1869 hw->fc &= (~E1000_FC_TX_PAUSE); 1870 1871 if ((hw->mac_type < em_82543) && (hw->report_tx_early == 1)) 1872 hw->fc &= (~E1000_FC_RX_PAUSE); 1873 1874 hw->original_fc = hw->fc; 1875 1876 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc); 1877 /* 1878 * Take the 4 bits from EEPROM word 0x0F that determine the initial 1879 * polarity value for the SW controlled pins, and setup the Extended 1880 * Device Control reg with that info. This is needed because one of 1881 * the SW controlled pins is used for signal detection. So this 1882 * should be done before em_setup_pcs_link() or em_phy_setup() is 1883 * called. 1884 */ 1885 if (hw->mac_type == em_82543) { 1886 ret_val = em_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1887 1, &eeprom_data); 1888 if (ret_val) { 1889 DEBUGOUT("EEPROM Read Error\n"); 1890 return -E1000_ERR_EEPROM; 1891 } 1892 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << 1893 SWDPIO__EXT_SHIFT); 1894 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1895 } 1896 /* Make sure we have a valid PHY */ 1897 ret_val = em_detect_gig_phy(hw); 1898 if (ret_val) { 1899 DEBUGOUT("Error, did not detect valid phy.\n"); 1900 if (hw->mac_type == em_icp_xxxx) 1901 return E1000_DEFER_INIT; 1902 else 1903 return ret_val; 1904 } 1905 DEBUGOUT1("Phy ID = %x \n", hw->phy_id); 1906 1907 /* Call the necessary subroutine to configure the link. */ 1908 switch (hw->media_type) { 1909 case em_media_type_copper: 1910 case em_media_type_oem: 1911 ret_val = em_setup_copper_link(hw); 1912 break; 1913 default: 1914 ret_val = em_setup_fiber_serdes_link(hw); 1915 break; 1916 } 1917 /* 1918 * Initialize the flow control address, type, and PAUSE timer 1919 * registers to their default values. This is done even if flow 1920 * control is disabled, because it does not hurt anything to 1921 * initialize these registers. 1922 */ 1923 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n" 1924 ); 1925 1926 /* 1927 * FCAL/H and FCT are hardcoded to standard values in 1928 * em_ich8lan / em_ich9lan / em_ich10lan. 1929 */ 1930 if (!IS_ICH8(hw->mac_type)) { 1931 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE); 1932 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH); 1933 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW); 1934 } 1935 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time); 1936 1937 if (hw->phy_type == em_phy_82577 || 1938 hw->phy_type == em_phy_82578 || 1939 hw->phy_type == em_phy_82579 || 1940 hw->phy_type == em_phy_i217) { 1941 E1000_WRITE_REG(hw, FCRTV_PCH, 0x1000); 1942 em_write_phy_reg(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27), 1943 hw->fc_pause_time); 1944 } 1945 1946 /* 1947 * Set the flow control receive threshold registers. Normally, these 1948 * registers will be set to a default threshold that may be adjusted 1949 * later by the driver's runtime code. However, if the ability to 1950 * transmit pause frames in not enabled, then these registers will be 1951 * set to 0. 1952 */ 1953 if (!(hw->fc & E1000_FC_TX_PAUSE)) { 1954 E1000_WRITE_REG(hw, FCRTL, 0); 1955 E1000_WRITE_REG(hw, FCRTH, 0); 1956 } else { 1957 /* 1958 * We need to set up the Receive Threshold high and low water 1959 * marks as well as (optionally) enabling the transmission of 1960 * XON frames. 1961 */ 1962 if (hw->fc_send_xon) { 1963 E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water 1964 | E1000_FCRTL_XONE)); 1965 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); 1966 } else { 1967 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water); 1968 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); 1969 } 1970 } 1971 return ret_val; 1972 } 1973 1974 void 1975 em_power_up_serdes_link_82575(struct em_hw *hw) 1976 { 1977 uint32_t reg; 1978 1979 /* Enable PCS to turn on link */ 1980 reg = E1000_READ_REG(hw, PCS_CFG0); 1981 reg |= E1000_PCS_CFG_PCS_EN; 1982 E1000_WRITE_REG(hw, PCS_CFG0, reg); 1983 1984 /* Power up the laser */ 1985 reg = E1000_READ_REG(hw, CTRL_EXT); 1986 reg &= ~E1000_CTRL_EXT_SDP3_DATA; 1987 E1000_WRITE_REG(hw, CTRL_EXT, reg); 1988 1989 /* flush the write to verify completion */ 1990 E1000_WRITE_FLUSH(hw); 1991 delay(5); 1992 } 1993 1994 /****************************************************************************** 1995 * Sets up link for a fiber based or serdes based adapter 1996 * 1997 * hw - Struct containing variables accessed by shared code 1998 * 1999 * Manipulates Physical Coding Sublayer functions in order to configure 2000 * link. Assumes the hardware has been previously reset and the transmitter 2001 * and receiver are not enabled. 2002 *****************************************************************************/ 2003 static int32_t 2004 em_setup_fiber_serdes_link(struct em_hw *hw) 2005 { 2006 uint32_t ctrl, ctrl_ext, reg; 2007 uint32_t status; 2008 uint32_t txcw = 0; 2009 uint32_t i; 2010 uint32_t signal = 0; 2011 int32_t ret_val; 2012 DEBUGFUNC("em_setup_fiber_serdes_link"); 2013 /* 2014 * On 82571 and 82572 Fiber connections, SerDes loopback mode 2015 * persists until explicitly turned off or a power cycle is 2016 * performed. A read to the register does not indicate its status. 2017 * Therefore, we ensure loopback mode is disabled during 2018 * initialization. 2019 */ 2020 if (hw->mac_type == em_82571 || hw->mac_type == em_82572 || 2021 hw->mac_type >= em_82575) 2022 E1000_WRITE_REG(hw, SCTL, E1000_DISABLE_SERDES_LOOPBACK); 2023 2024 if (hw->mac_type >= em_82575) 2025 em_power_up_serdes_link_82575(hw); 2026 2027 /* 2028 * On adapters with a MAC newer than 82544, SWDP 1 will be set when 2029 * the optics detect a signal. On older adapters, it will be cleared 2030 * when there is a signal. This applies to fiber media only. If 2031 * we're on serdes media, adjust the output amplitude to value set in 2032 * the EEPROM. 2033 */ 2034 ctrl = E1000_READ_REG(hw, CTRL); 2035 if (hw->media_type == em_media_type_fiber) 2036 signal = (hw->mac_type > em_82544) ? E1000_CTRL_SWDPIN1 : 0; 2037 2038 ret_val = em_adjust_serdes_amplitude(hw); 2039 if (ret_val) 2040 return ret_val; 2041 2042 /* Take the link out of reset */ 2043 ctrl &= ~(E1000_CTRL_LRST); 2044 2045 if (hw->mac_type >= em_82575) { 2046 /* set both sw defined pins on 82575/82576*/ 2047 ctrl |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1; 2048 2049 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 2050 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) { 2051 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: 2052 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES: 2053 /* the backplane is always connected */ 2054 reg = E1000_READ_REG(hw, PCS_LCTL); 2055 reg |= E1000_PCS_LCTL_FORCE_FCTRL; 2056 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL; 2057 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */ 2058 DEBUGOUT("Configuring Forced Link\n"); 2059 E1000_WRITE_REG(hw, PCS_LCTL, reg); 2060 em_force_mac_fc(hw); 2061 hw->autoneg_failed = 0; 2062 return E1000_SUCCESS; 2063 break; 2064 default: 2065 /* Set switch control to serdes energy detect */ 2066 reg = E1000_READ_REG(hw, CONNSW); 2067 reg |= E1000_CONNSW_ENRGSRC; 2068 E1000_WRITE_REG(hw, CONNSW, reg); 2069 break; 2070 } 2071 } 2072 2073 /* Adjust VCO speed to improve BER performance */ 2074 ret_val = em_set_vco_speed(hw); 2075 if (ret_val) 2076 return ret_val; 2077 2078 em_config_collision_dist(hw); 2079 /* 2080 * Check for a software override of the flow control settings, and 2081 * setup the device accordingly. If auto-negotiation is enabled, 2082 * then software will have to set the "PAUSE" bits to the correct 2083 * value in the Tranmsit Config Word Register (TXCW) and re-start 2084 * auto-negotiation. However, if auto-negotiation is disabled, then 2085 * software will have to manually configure the two flow control 2086 * enable bits in the CTRL register. 2087 * 2088 * The possible values of the "fc" parameter are: 0: Flow control is 2089 * completely disabled 1: Rx flow control is enabled (we can receive 2090 * pause frames, but not send pause frames). 2: Tx flow control is 2091 * enabled (we can send pause frames but we do not support receiving 2092 * pause frames). 3: Both Rx and TX flow control (symmetric) are 2093 * enabled. 2094 */ 2095 switch (hw->fc) { 2096 case E1000_FC_NONE: 2097 /* 2098 * Flow control is completely disabled by a software 2099 * over-ride. 2100 */ 2101 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 2102 break; 2103 case E1000_FC_RX_PAUSE: 2104 /* 2105 * RX Flow control is enabled and TX Flow control is disabled 2106 * by a software over-ride. Since there really isn't a way to 2107 * advertise that we are capable of RX Pause ONLY, we will 2108 * advertise that we support both symmetric and asymmetric RX 2109 * PAUSE. Later, we will disable the adapter's ability to 2110 * send PAUSE frames. 2111 */ 2112 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | 2113 E1000_TXCW_PAUSE_MASK); 2114 break; 2115 case E1000_FC_TX_PAUSE: 2116 /* 2117 * TX Flow control is enabled, and RX Flow control is 2118 * disabled, by a software over-ride. 2119 */ 2120 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 2121 break; 2122 case E1000_FC_FULL: 2123 /* 2124 * Flow control (both RX and TX) is enabled by a software 2125 * over-ride. 2126 */ 2127 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | 2128 E1000_TXCW_PAUSE_MASK); 2129 break; 2130 default: 2131 DEBUGOUT("Flow control param set incorrectly\n"); 2132 return -E1000_ERR_CONFIG; 2133 break; 2134 } 2135 /* 2136 * Since auto-negotiation is enabled, take the link out of reset (the 2137 * link will be in reset, because we previously reset the chip). This 2138 * will restart auto-negotiation. If auto-neogtiation is successful 2139 * then the link-up status bit will be set and the flow control 2140 * enable bits (RFCE and TFCE) will be set according to their 2141 * negotiated value. 2142 */ 2143 DEBUGOUT("Auto-negotiation enabled\n"); 2144 2145 E1000_WRITE_REG(hw, TXCW, txcw); 2146 E1000_WRITE_REG(hw, CTRL, ctrl); 2147 E1000_WRITE_FLUSH(hw); 2148 2149 hw->txcw = txcw; 2150 msec_delay(1); 2151 /* 2152 * If we have a signal (the cable is plugged in) then poll for a 2153 * "Link-Up" indication in the Device Status Register. Time-out if a 2154 * link isn't seen in 500 milliseconds seconds (Auto-negotiation 2155 * should complete in less than 500 milliseconds even if the other 2156 * end is doing it in SW). For internal serdes, we just assume a 2157 * signal is present, then poll. 2158 */ 2159 if (hw->media_type == em_media_type_internal_serdes || 2160 (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) { 2161 DEBUGOUT("Looking for Link\n"); 2162 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) { 2163 msec_delay(10); 2164 status = E1000_READ_REG(hw, STATUS); 2165 if (status & E1000_STATUS_LU) 2166 break; 2167 } 2168 if (i == (LINK_UP_TIMEOUT / 10)) { 2169 DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 2170 hw->autoneg_failed = 1; 2171 /* 2172 * AutoNeg failed to achieve a link, so we'll call 2173 * em_check_for_link. This routine will force the 2174 * link up if we detect a signal. This will allow us 2175 * to communicate with non-autonegotiating link 2176 * partners. 2177 */ 2178 ret_val = em_check_for_link(hw); 2179 if (ret_val) { 2180 DEBUGOUT("Error while checking for link\n"); 2181 return ret_val; 2182 } 2183 hw->autoneg_failed = 0; 2184 } else { 2185 hw->autoneg_failed = 0; 2186 DEBUGOUT("Valid Link Found\n"); 2187 } 2188 } else { 2189 DEBUGOUT("No Signal Detected\n"); 2190 } 2191 return E1000_SUCCESS; 2192 } 2193 2194 /****************************************************************************** 2195 * Make sure we have a valid PHY and change PHY mode before link setup. 2196 * 2197 * hw - Struct containing variables accessed by shared code 2198 *****************************************************************************/ 2199 static int32_t 2200 em_copper_link_preconfig(struct em_hw *hw) 2201 { 2202 uint32_t ctrl; 2203 int32_t ret_val; 2204 uint16_t phy_data; 2205 DEBUGFUNC("em_copper_link_preconfig"); 2206 2207 ctrl = E1000_READ_REG(hw, CTRL); 2208 /* 2209 * With 82543, we need to force speed and duplex on the MAC equal to 2210 * what the PHY speed and duplex configuration is. In addition, we 2211 * need to perform a hardware reset on the PHY to take it out of 2212 * reset. 2213 */ 2214 if (hw->mac_type > em_82543) { 2215 ctrl |= E1000_CTRL_SLU; 2216 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 2217 E1000_WRITE_REG(hw, CTRL, ctrl); 2218 } else { 2219 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | 2220 E1000_CTRL_SLU); 2221 E1000_WRITE_REG(hw, CTRL, ctrl); 2222 ret_val = em_phy_hw_reset(hw); 2223 if (ret_val) 2224 return ret_val; 2225 } 2226 2227 /* Set PHY to class A mode (if necessary) */ 2228 ret_val = em_set_phy_mode(hw); 2229 if (ret_val) 2230 return ret_val; 2231 2232 if ((hw->mac_type == em_82545_rev_3) || 2233 (hw->mac_type == em_82546_rev_3)) { 2234 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 2235 &phy_data); 2236 phy_data |= 0x00000008; 2237 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 2238 phy_data); 2239 } 2240 if (hw->mac_type <= em_82543 || 2241 hw->mac_type == em_82541 || hw->mac_type == em_82547 || 2242 hw->mac_type == em_82541_rev_2 || hw->mac_type == em_82547_rev_2) 2243 hw->phy_reset_disable = FALSE; 2244 2245 return E1000_SUCCESS; 2246 } 2247 2248 /****************************************************************************** 2249 * Copper link setup for em_phy_igp series. 2250 * 2251 * hw - Struct containing variables accessed by shared code 2252 *****************************************************************************/ 2253 static int32_t 2254 em_copper_link_igp_setup(struct em_hw *hw) 2255 { 2256 uint32_t led_ctrl; 2257 int32_t ret_val; 2258 uint16_t phy_data; 2259 DEBUGFUNC("em_copper_link_igp_setup"); 2260 2261 if (hw->phy_reset_disable) 2262 return E1000_SUCCESS; 2263 2264 ret_val = em_phy_reset(hw); 2265 if (ret_val) { 2266 DEBUGOUT("Error Resetting the PHY\n"); 2267 return ret_val; 2268 } 2269 /* Wait 15ms for MAC to configure PHY from eeprom settings */ 2270 msec_delay(15); 2271 if (hw->mac_type != em_ich8lan && 2272 hw->mac_type != em_ich9lan && 2273 hw->mac_type != em_ich10lan) { 2274 /* Configure activity LED after PHY reset */ 2275 led_ctrl = E1000_READ_REG(hw, LEDCTL); 2276 led_ctrl &= IGP_ACTIVITY_LED_MASK; 2277 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 2278 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 2279 } 2280 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */ 2281 if (hw->phy_type == em_phy_igp) { 2282 /* disable lplu d3 during driver init */ 2283 ret_val = em_set_d3_lplu_state(hw, FALSE); 2284 if (ret_val) { 2285 DEBUGOUT("Error Disabling LPLU D3\n"); 2286 return ret_val; 2287 } 2288 } 2289 /* disable lplu d0 during driver init */ 2290 if (hw->mac_type == em_pchlan || 2291 hw->mac_type == em_pch2lan || 2292 hw->mac_type == em_pch_lpt || 2293 hw->mac_type == em_pch_spt || 2294 hw->mac_type == em_pch_cnp) 2295 ret_val = em_set_lplu_state_pchlan(hw, FALSE); 2296 else 2297 ret_val = em_set_d0_lplu_state(hw, FALSE); 2298 if (ret_val) { 2299 DEBUGOUT("Error Disabling LPLU D0\n"); 2300 return ret_val; 2301 } 2302 /* Configure mdi-mdix settings */ 2303 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 2304 if (ret_val) 2305 return ret_val; 2306 2307 if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) { 2308 hw->dsp_config_state = em_dsp_config_disabled; 2309 /* Force MDI for earlier revs of the IGP PHY */ 2310 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | 2311 IGP01E1000_PSCR_FORCE_MDI_MDIX); 2312 hw->mdix = 1; 2313 2314 } else { 2315 hw->dsp_config_state = em_dsp_config_enabled; 2316 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 2317 2318 switch (hw->mdix) { 2319 case 1: 2320 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 2321 break; 2322 case 2: 2323 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; 2324 break; 2325 case 0: 2326 default: 2327 phy_data |= IGP01E1000_PSCR_AUTO_MDIX; 2328 break; 2329 } 2330 } 2331 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 2332 if (ret_val) 2333 return ret_val; 2334 2335 /* set auto-master slave resolution settings */ 2336 if (hw->autoneg) { 2337 em_ms_type phy_ms_setting = hw->master_slave; 2338 if (hw->ffe_config_state == em_ffe_config_active) 2339 hw->ffe_config_state = em_ffe_config_enabled; 2340 2341 if (hw->dsp_config_state == em_dsp_config_activated) 2342 hw->dsp_config_state = em_dsp_config_enabled; 2343 /* 2344 * when autonegotiation advertisement is only 1000Mbps then 2345 * we should disable SmartSpeed and enable Auto MasterSlave 2346 * resolution as hardware default. 2347 */ 2348 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) { 2349 /* Disable SmartSpeed */ 2350 ret_val = em_read_phy_reg(hw, 2351 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2352 if (ret_val) 2353 return ret_val; 2354 2355 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2356 ret_val = em_write_phy_reg(hw, 2357 IGP01E1000_PHY_PORT_CONFIG, phy_data); 2358 if (ret_val) 2359 return ret_val; 2360 /* Set auto Master/Slave resolution process */ 2361 ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, 2362 &phy_data); 2363 if (ret_val) 2364 return ret_val; 2365 2366 phy_data &= ~CR_1000T_MS_ENABLE; 2367 ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL, 2368 phy_data); 2369 if (ret_val) 2370 return ret_val; 2371 } 2372 ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); 2373 if (ret_val) 2374 return ret_val; 2375 2376 /* load defaults for future use */ 2377 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ? 2378 ((phy_data & CR_1000T_MS_VALUE) ? em_ms_force_master : 2379 em_ms_force_slave) : em_ms_auto; 2380 2381 switch (phy_ms_setting) { 2382 case em_ms_force_master: 2383 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 2384 break; 2385 case em_ms_force_slave: 2386 phy_data |= CR_1000T_MS_ENABLE; 2387 phy_data &= ~(CR_1000T_MS_VALUE); 2388 break; 2389 case em_ms_auto: 2390 phy_data &= ~CR_1000T_MS_ENABLE; 2391 break; 2392 default: 2393 break; 2394 } 2395 ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); 2396 if (ret_val) 2397 return ret_val; 2398 } 2399 return E1000_SUCCESS; 2400 } 2401 2402 /****************************************************************************** 2403 * Copper link setup for em_phy_gg82563 series. 2404 * 2405 * hw - Struct containing variables accessed by shared code 2406 *****************************************************************************/ 2407 static int32_t 2408 em_copper_link_ggp_setup(struct em_hw *hw) 2409 { 2410 int32_t ret_val; 2411 uint16_t phy_data; 2412 uint32_t reg_data; 2413 DEBUGFUNC("em_copper_link_ggp_setup"); 2414 2415 if (!hw->phy_reset_disable) { 2416 2417 /* Enable CRS on TX for half-duplex operation. */ 2418 ret_val = em_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 2419 &phy_data); 2420 if (ret_val) 2421 return ret_val; 2422 2423 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 2424 /* Use 25MHz for both link down and 1000BASE-T for Tx clock */ 2425 phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ; 2426 2427 ret_val = em_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 2428 phy_data); 2429 if (ret_val) 2430 return ret_val; 2431 /* 2432 * Options: MDI/MDI-X = 0 (default) 0 - Auto for all speeds 1 2433 * - MDI mode 2 - MDI-X mode 3 - Auto for 1000Base-T only 2434 * (MDI-X for 10/100Base-T modes) 2435 */ 2436 ret_val = em_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, 2437 &phy_data); 2438 2439 if (ret_val) 2440 return ret_val; 2441 2442 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK; 2443 2444 switch (hw->mdix) { 2445 case 1: 2446 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI; 2447 break; 2448 case 2: 2449 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX; 2450 break; 2451 case 0: 2452 default: 2453 phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO; 2454 break; 2455 } 2456 /* 2457 * Options: disable_polarity_correction = 0 (default) 2458 * Automatic Correction for Reversed Cable Polarity 0 - 2459 * Disabled 1 - Enabled 2460 */ 2461 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 2462 if (hw->disable_polarity_correction == 1) 2463 phy_data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 2464 ret_val = em_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, 2465 phy_data); 2466 2467 if (ret_val) 2468 return ret_val; 2469 2470 /* SW Reset the PHY so all changes take effect */ 2471 ret_val = em_phy_reset(hw); 2472 if (ret_val) { 2473 DEBUGOUT("Error Resetting the PHY\n"); 2474 return ret_val; 2475 } 2476 } /* phy_reset_disable */ 2477 if (hw->mac_type == em_80003es2lan) { 2478 /* Bypass RX and TX FIFO's */ 2479 ret_val = em_write_kmrn_reg(hw, 2480 E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL, 2481 E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS | 2482 E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS); 2483 if (ret_val) 2484 return ret_val; 2485 2486 ret_val = em_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, 2487 &phy_data); 2488 if (ret_val) 2489 return ret_val; 2490 2491 phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG; 2492 ret_val = em_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, 2493 phy_data); 2494 2495 if (ret_val) 2496 return ret_val; 2497 2498 reg_data = E1000_READ_REG(hw, CTRL_EXT); 2499 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK); 2500 E1000_WRITE_REG(hw, CTRL_EXT, reg_data); 2501 2502 ret_val = em_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, 2503 &phy_data); 2504 if (ret_val) 2505 return ret_val; 2506 /* 2507 * Do not init these registers when the HW is in IAMT mode, 2508 * since the firmware will have already initialized them. We 2509 * only initialize them if the HW is not in IAMT mode. 2510 */ 2511 if (em_check_mng_mode(hw) == FALSE) { 2512 /* Enable Electrical Idle on the PHY */ 2513 phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; 2514 ret_val = em_write_phy_reg(hw, 2515 GG82563_PHY_PWR_MGMT_CTRL, phy_data); 2516 if (ret_val) 2517 return ret_val; 2518 2519 ret_val = em_read_phy_reg(hw, 2520 GG82563_PHY_KMRN_MODE_CTRL, &phy_data); 2521 if (ret_val) 2522 return ret_val; 2523 2524 phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 2525 ret_val = em_write_phy_reg(hw, 2526 GG82563_PHY_KMRN_MODE_CTRL, phy_data); 2527 2528 if (ret_val) 2529 return ret_val; 2530 } 2531 /* 2532 * Workaround: Disable padding in Kumeran interface in the 2533 * MAC and in the PHY to avoid CRC errors. 2534 */ 2535 ret_val = em_read_phy_reg(hw, GG82563_PHY_INBAND_CTRL, 2536 &phy_data); 2537 if (ret_val) 2538 return ret_val; 2539 phy_data |= GG82563_ICR_DIS_PADDING; 2540 ret_val = em_write_phy_reg(hw, GG82563_PHY_INBAND_CTRL, 2541 phy_data); 2542 if (ret_val) 2543 return ret_val; 2544 } 2545 return E1000_SUCCESS; 2546 } 2547 2548 /****************************************************************************** 2549 * Copper link setup for em_phy_m88 series. 2550 * 2551 * hw - Struct containing variables accessed by shared code 2552 *****************************************************************************/ 2553 static int32_t 2554 em_copper_link_mgp_setup(struct em_hw *hw) 2555 { 2556 int32_t ret_val; 2557 uint16_t phy_data; 2558 DEBUGFUNC("em_copper_link_mgp_setup"); 2559 2560 if (hw->phy_reset_disable) 2561 return E1000_SUCCESS; 2562 2563 /* disable lplu d0 during driver init */ 2564 if (hw->mac_type == em_pchlan || 2565 hw->mac_type == em_pch2lan || 2566 hw->mac_type == em_pch_lpt || 2567 hw->mac_type == em_pch_spt || 2568 hw->mac_type == em_pch_cnp) 2569 ret_val = em_set_lplu_state_pchlan(hw, FALSE); 2570 2571 /* Enable CRS on TX. This must be set for half-duplex operation. */ 2572 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 2573 if (ret_val) 2574 return ret_val; 2575 2576 if (hw->phy_id == M88E1141_E_PHY_ID) { 2577 phy_data |= 0x00000008; 2578 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 2579 phy_data); 2580 if (ret_val) 2581 return ret_val; 2582 2583 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 2584 &phy_data); 2585 if (ret_val) 2586 return ret_val; 2587 2588 phy_data &= ~M88E1000_PSCR_ASSERT_CRS_ON_TX; 2589 2590 } 2591 /* For BM PHY this bit is downshift enable */ 2592 else if (hw->phy_type != em_phy_bm) 2593 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 2594 /* 2595 * Options: MDI/MDI-X = 0 (default) 0 - Auto for all speeds 1 - MDI 2596 * mode 2 - MDI-X mode 3 - Auto for 1000Base-T only (MDI-X for 2597 * 10/100Base-T modes) 2598 */ 2599 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 2600 2601 switch (hw->mdix) { 2602 case 1: 2603 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 2604 break; 2605 case 2: 2606 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 2607 break; 2608 case 3: 2609 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 2610 break; 2611 case 0: 2612 default: 2613 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 2614 break; 2615 } 2616 /* 2617 * Options: disable_polarity_correction = 0 (default) Automatic 2618 * Correction for Reversed Cable Polarity 0 - Disabled 1 - Enabled 2619 */ 2620 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 2621 if (hw->disable_polarity_correction == 1) 2622 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 2623 2624 /* Enable downshift on BM (disabled by default) */ 2625 if (hw->phy_type == em_phy_bm) 2626 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT; 2627 2628 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 2629 if (ret_val) 2630 return ret_val; 2631 2632 if (((hw->phy_type == em_phy_m88) && 2633 (hw->phy_revision < M88E1011_I_REV_4) && 2634 (hw->phy_id != BME1000_E_PHY_ID)) || 2635 (hw->phy_type == em_phy_oem)) { 2636 /* 2637 * Force TX_CLK in the Extended PHY Specific Control Register 2638 * to 25MHz clock. 2639 */ 2640 ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 2641 &phy_data); 2642 if (ret_val) 2643 return ret_val; 2644 2645 if (hw->phy_type == em_phy_oem) { 2646 phy_data |= M88E1000_EPSCR_TX_TIME_CTRL; 2647 phy_data |= M88E1000_EPSCR_RX_TIME_CTRL; 2648 } 2649 phy_data |= M88E1000_EPSCR_TX_CLK_25; 2650 2651 if ((hw->phy_revision == E1000_REVISION_2) && 2652 (hw->phy_id == M88E1111_I_PHY_ID)) { 2653 /* Vidalia Phy, set the downshift counter to 5x */ 2654 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK); 2655 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; 2656 ret_val = em_write_phy_reg(hw, 2657 M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 2658 if (ret_val) 2659 return ret_val; 2660 } else { 2661 /* Configure Master and Slave downshift values */ 2662 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 2663 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 2664 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 2665 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 2666 ret_val = em_write_phy_reg(hw, 2667 M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 2668 if (ret_val) 2669 return ret_val; 2670 } 2671 } 2672 if ((hw->phy_type == em_phy_bm) && (hw->phy_revision == 1)) { 2673 /* 2674 * Set PHY page 0, register 29 to 0x0003 2675 * The next two writes are supposed to lower BER for gig 2676 * conection 2677 */ 2678 ret_val = em_write_phy_reg(hw, BM_REG_BIAS1, 0x0003); 2679 if (ret_val) 2680 return ret_val; 2681 2682 /* Set PHY page 0, register 30 to 0x0000 */ 2683 ret_val = em_write_phy_reg(hw, BM_REG_BIAS2, 0x0000); 2684 if (ret_val) 2685 return ret_val; 2686 } 2687 if (hw->phy_type == em_phy_82578) { 2688 ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 2689 &phy_data); 2690 if (ret_val) 2691 return ret_val; 2692 2693 /* 82578 PHY - set the downshift count to 1x. */ 2694 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE; 2695 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK; 2696 ret_val = em_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 2697 phy_data); 2698 if (ret_val) 2699 return ret_val; 2700 } 2701 /* SW Reset the PHY so all changes take effect */ 2702 ret_val = em_phy_reset(hw); 2703 if (ret_val) { 2704 DEBUGOUT("Error Resetting the PHY\n"); 2705 return ret_val; 2706 } 2707 return E1000_SUCCESS; 2708 } 2709 2710 /****************************************************************************** 2711 * Copper link setup for em_phy_82577 series. 2712 * 2713 * hw - Struct containing variables accessed by shared code 2714 *****************************************************************************/ 2715 static int32_t 2716 em_copper_link_82577_setup(struct em_hw *hw) 2717 { 2718 int32_t ret_val; 2719 uint16_t phy_data; 2720 uint32_t led_ctl; 2721 DEBUGFUNC("em_copper_link_82577_setup"); 2722 2723 if (hw->phy_reset_disable) 2724 return E1000_SUCCESS; 2725 2726 /* Enable CRS on TX for half-duplex operation. */ 2727 ret_val = em_read_phy_reg(hw, I82577_PHY_CFG_REG, &phy_data); 2728 if (ret_val) 2729 return ret_val; 2730 2731 phy_data |= I82577_PHY_CFG_ENABLE_CRS_ON_TX | 2732 I82577_PHY_CFG_ENABLE_DOWNSHIFT; 2733 2734 ret_val = em_write_phy_reg(hw, I82577_PHY_CFG_REG, phy_data); 2735 if (ret_val) 2736 return ret_val; 2737 2738 /* Wait 15ms for MAC to configure PHY from eeprom settings */ 2739 msec_delay(15); 2740 led_ctl = hw->ledctl_mode1; 2741 2742 /* disable lplu d0 during driver init */ 2743 ret_val = em_set_lplu_state_pchlan(hw, FALSE); 2744 if (ret_val) { 2745 DEBUGOUT("Error Disabling LPLU D0\n"); 2746 return ret_val; 2747 } 2748 2749 E1000_WRITE_REG(hw, LEDCTL, led_ctl); 2750 2751 return E1000_SUCCESS; 2752 } 2753 2754 static int32_t 2755 em_copper_link_82580_setup(struct em_hw *hw) 2756 { 2757 int32_t ret_val; 2758 uint16_t phy_data; 2759 2760 if (hw->phy_reset_disable) 2761 return E1000_SUCCESS; 2762 2763 ret_val = em_phy_reset(hw); 2764 if (ret_val) 2765 goto out; 2766 2767 /* Enable CRS on TX. This must be set for half-duplex operation. */ 2768 ret_val = em_read_phy_reg(hw, I82580_CFG_REG, &phy_data); 2769 if (ret_val) 2770 goto out; 2771 2772 phy_data |= I82580_CFG_ASSERT_CRS_ON_TX | 2773 I82580_CFG_ENABLE_DOWNSHIFT; 2774 2775 ret_val = em_write_phy_reg(hw, I82580_CFG_REG, phy_data); 2776 2777 out: 2778 return ret_val; 2779 } 2780 2781 static int32_t 2782 em_copper_link_rtl8211_setup(struct em_hw *hw) 2783 { 2784 int32_t ret_val; 2785 uint16_t phy_data; 2786 2787 DEBUGFUNC("em_copper_link_rtl8211_setup: begin"); 2788 2789 if (!hw) { 2790 return -1; 2791 } 2792 /* SW Reset the PHY so all changes take effect */ 2793 em_phy_hw_reset(hw); 2794 2795 /* Enable CRS on TX. This must be set for half-duplex operation. */ 2796 phy_data = 0; 2797 2798 ret_val = em_read_phy_reg_ex(hw, RGEPHY_CR, &phy_data); 2799 if (ret_val) { 2800 printf("Unable to read RGEPHY_CR register\n"); 2801 return ret_val; 2802 } 2803 DEBUGOUT3("RTL8211: Rx phy_id=%X addr=%X SPEC_CTRL=%X\n", hw->phy_id, 2804 hw->phy_addr, phy_data); 2805 phy_data |= RGEPHY_CR_ASSERT_CRS; 2806 2807 ret_val = em_write_phy_reg_ex(hw, RGEPHY_CR, phy_data); 2808 if (ret_val) { 2809 printf("Unable to write RGEPHY_CR register\n"); 2810 return ret_val; 2811 } 2812 2813 phy_data = 0; /* LED Control Register 0x18 */ 2814 ret_val = em_read_phy_reg_ex(hw, RGEPHY_LC, &phy_data); 2815 if (ret_val) { 2816 printf("Unable to read RGEPHY_LC register\n"); 2817 return ret_val; 2818 } 2819 2820 phy_data &= 0x80FF; /* bit-15=0 disable, clear bit 8-10 */ 2821 ret_val = em_write_phy_reg_ex(hw, RGEPHY_LC, phy_data); 2822 if (ret_val) { 2823 printf("Unable to write RGEPHY_LC register\n"); 2824 return ret_val; 2825 } 2826 /* LED Control and Definition Register 0x11, PHY spec status reg */ 2827 phy_data = 0; 2828 ret_val = em_read_phy_reg_ex(hw, RGEPHY_SR, &phy_data); 2829 if (ret_val) { 2830 printf("Unable to read RGEPHY_SR register\n"); 2831 return ret_val; 2832 } 2833 2834 phy_data |= 0x0010; /* LED active Low */ 2835 ret_val = em_write_phy_reg_ex(hw, RGEPHY_SR, phy_data); 2836 if (ret_val) { 2837 printf("Unable to write RGEPHY_SR register\n"); 2838 return ret_val; 2839 } 2840 2841 phy_data = 0; 2842 ret_val = em_read_phy_reg_ex(hw, RGEPHY_SR, &phy_data); 2843 if (ret_val) { 2844 printf("Unable to read RGEPHY_SR register\n"); 2845 return ret_val; 2846 } 2847 2848 /* Switch to Page2 */ 2849 phy_data = RGEPHY_PS_PAGE_2; 2850 ret_val = em_write_phy_reg_ex(hw, RGEPHY_PS, phy_data); 2851 if (ret_val) { 2852 printf("Unable to write PHY RGEPHY_PS register\n"); 2853 return ret_val; 2854 } 2855 2856 phy_data = 0x0000; 2857 ret_val = em_write_phy_reg_ex(hw, RGEPHY_LC_P2, phy_data); 2858 if (ret_val) { 2859 printf("Unable to write RGEPHY_LC_P2 register\n"); 2860 return ret_val; 2861 } 2862 usec_delay(5); 2863 2864 2865 /* LED Configuration Control Reg for setting for 0x1A Register */ 2866 phy_data = 0; 2867 ret_val = em_read_phy_reg_ex(hw, RGEPHY_LC_P2, &phy_data); 2868 if (ret_val) { 2869 printf("Unable to read RGEPHY_LC_P2 register\n"); 2870 return ret_val; 2871 } 2872 2873 phy_data &= 0xF000; 2874 phy_data |= 0x0F24; 2875 ret_val = em_write_phy_reg_ex(hw, RGEPHY_LC_P2, phy_data); 2876 if (ret_val) { 2877 printf("Unable to write RGEPHY_LC_P2 register\n"); 2878 return ret_val; 2879 } 2880 phy_data = 0; 2881 ret_val= em_read_phy_reg_ex(hw, RGEPHY_LC_P2, &phy_data); 2882 if (ret_val) { 2883 printf("Unable to read RGEPHY_LC_P2 register\n"); 2884 return ret_val; 2885 } 2886 DEBUGOUT1("RTL8211:ReadBack for check, LED_CFG->data=%X\n", phy_data); 2887 2888 2889 /* After setting Page2, go back to Page 0 */ 2890 phy_data = 0; 2891 ret_val = em_write_phy_reg_ex(hw, RGEPHY_PS, phy_data); 2892 if (ret_val) { 2893 printf("Unable to write PHY RGEPHY_PS register\n"); 2894 return ret_val; 2895 } 2896 2897 /* pulse streching= 42-84ms, blink rate=84mm */ 2898 phy_data = 0x140 | RGEPHY_LC_PULSE_42MS | RGEPHY_LC_LINK | 2899 RGEPHY_LC_DUPLEX | RGEPHY_LC_RX; 2900 2901 ret_val = em_write_phy_reg_ex(hw, RGEPHY_LC, phy_data); 2902 if (ret_val) { 2903 printf("Unable to write RGEPHY_LC register\n"); 2904 return ret_val; 2905 } 2906 return E1000_SUCCESS; 2907 } 2908 2909 /****************************************************************************** 2910 * Setup auto-negotiation and flow control advertisements, 2911 * and then perform auto-negotiation. 2912 * 2913 * hw - Struct containing variables accessed by shared code 2914 *****************************************************************************/ 2915 int32_t 2916 em_copper_link_autoneg(struct em_hw *hw) 2917 { 2918 int32_t ret_val; 2919 uint16_t phy_data; 2920 DEBUGFUNC("em_copper_link_autoneg"); 2921 /* 2922 * Perform some bounds checking on the hw->autoneg_advertised 2923 * parameter. If this variable is zero, then set it to the default. 2924 */ 2925 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT; 2926 /* 2927 * If autoneg_advertised is zero, we assume it was not defaulted by 2928 * the calling code so we set to advertise full capability. 2929 */ 2930 if (hw->autoneg_advertised == 0) 2931 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 2932 2933 /* IFE phy only supports 10/100 */ 2934 if (hw->phy_type == em_phy_ife) 2935 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL; 2936 2937 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); 2938 ret_val = em_phy_setup_autoneg(hw); 2939 if (ret_val) { 2940 DEBUGOUT("Error Setting up Auto-Negotiation\n"); 2941 return ret_val; 2942 } 2943 DEBUGOUT("Restarting Auto-Neg\n"); 2944 /* 2945 * Restart auto-negotiation by setting the Auto Neg Enable bit and 2946 * the Auto Neg Restart bit in the PHY control register. 2947 */ 2948 ret_val = em_read_phy_reg(hw, PHY_CTRL, &phy_data); 2949 if (ret_val) 2950 return ret_val; 2951 2952 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 2953 ret_val = em_write_phy_reg(hw, PHY_CTRL, phy_data); 2954 if (ret_val) 2955 return ret_val; 2956 /* 2957 * Does the user want to wait for Auto-Neg to complete here, or check 2958 * at a later time (for example, callback routine). 2959 */ 2960 if (hw->wait_autoneg_complete) { 2961 ret_val = em_wait_autoneg(hw); 2962 if (ret_val) { 2963 DEBUGOUT("Error while waiting for autoneg to complete\n" 2964 ); 2965 return ret_val; 2966 } 2967 } 2968 hw->get_link_status = TRUE; 2969 2970 return E1000_SUCCESS; 2971 } 2972 2973 /****************************************************************************** 2974 * Config the MAC and the PHY after link is up. 2975 * 1) Set up the MAC to the current PHY speed/duplex 2976 * if we are on 82543. If we 2977 * are on newer silicon, we only need to configure 2978 * collision distance in the Transmit Control Register. 2979 * 2) Set up flow control on the MAC to that established with 2980 * the link partner. 2981 * 3) Config DSP to improve Gigabit link quality for some PHY revisions. 2982 * 2983 * hw - Struct containing variables accessed by shared code 2984 *****************************************************************************/ 2985 int32_t 2986 em_copper_link_postconfig(struct em_hw *hw) 2987 { 2988 int32_t ret_val; 2989 DEBUGFUNC("em_copper_link_postconfig"); 2990 2991 if (hw->mac_type >= em_82544 && 2992 hw->mac_type != em_icp_xxxx) { 2993 em_config_collision_dist(hw); 2994 } else { 2995 ret_val = em_config_mac_to_phy(hw); 2996 if (ret_val) { 2997 DEBUGOUT("Error configuring MAC to PHY settings\n"); 2998 return ret_val; 2999 } 3000 } 3001 ret_val = em_config_fc_after_link_up(hw); 3002 if (ret_val) { 3003 DEBUGOUT("Error Configuring Flow Control\n"); 3004 return ret_val; 3005 } 3006 /* Config DSP to improve Giga link quality */ 3007 if (hw->phy_type == em_phy_igp) { 3008 ret_val = em_config_dsp_after_link_change(hw, TRUE); 3009 if (ret_val) { 3010 DEBUGOUT("Error Configuring DSP after link up\n"); 3011 return ret_val; 3012 } 3013 } 3014 return E1000_SUCCESS; 3015 } 3016 3017 /****************************************************************************** 3018 * Detects which PHY is present and setup the speed and duplex 3019 * 3020 * hw - Struct containing variables accessed by shared code 3021 *****************************************************************************/ 3022 static int32_t 3023 em_setup_copper_link(struct em_hw *hw) 3024 { 3025 int32_t ret_val; 3026 uint16_t i; 3027 uint16_t phy_data; 3028 uint16_t reg_data; 3029 DEBUGFUNC("em_setup_copper_link"); 3030 3031 switch (hw->mac_type) { 3032 case em_80003es2lan: 3033 case em_ich8lan: 3034 case em_ich9lan: 3035 case em_ich10lan: 3036 case em_pchlan: 3037 case em_pch2lan: 3038 case em_pch_lpt: 3039 case em_pch_spt: 3040 case em_pch_cnp: 3041 /* 3042 * Set the mac to wait the maximum time between each 3043 * iteration and increase the max iterations when polling the 3044 * phy; this fixes erroneous timeouts at 10Mbps. 3045 */ 3046 ret_val = em_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF); 3047 if (ret_val) 3048 return ret_val; 3049 ret_val = em_read_kmrn_reg(hw, GG82563_REG(0x34, 9), 3050 ®_data); 3051 if (ret_val) 3052 return ret_val; 3053 reg_data |= 0x3F; 3054 ret_val = em_write_kmrn_reg(hw, GG82563_REG(0x34, 9), 3055 reg_data); 3056 if (ret_val) 3057 return ret_val; 3058 default: 3059 break; 3060 } 3061 3062 /* Check if it is a valid PHY and set PHY mode if necessary. */ 3063 ret_val = em_copper_link_preconfig(hw); 3064 if (ret_val) 3065 return ret_val; 3066 3067 switch (hw->mac_type) { 3068 case em_80003es2lan: 3069 /* Kumeran registers are written-only */ 3070 reg_data = 3071 E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT; 3072 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING; 3073 ret_val = em_write_kmrn_reg(hw, 3074 E1000_KUMCTRLSTA_OFFSET_INB_CTRL, reg_data); 3075 if (ret_val) 3076 return ret_val; 3077 break; 3078 default: 3079 break; 3080 } 3081 3082 if (hw->phy_type == em_phy_igp || 3083 hw->phy_type == em_phy_igp_3 || 3084 hw->phy_type == em_phy_igp_2) { 3085 ret_val = em_copper_link_igp_setup(hw); 3086 if (ret_val) 3087 return ret_val; 3088 } else if (hw->phy_type == em_phy_m88 || 3089 hw->phy_type == em_phy_bm || 3090 hw->phy_type == em_phy_oem || 3091 hw->phy_type == em_phy_82578) { 3092 ret_val = em_copper_link_mgp_setup(hw); 3093 if (ret_val) 3094 return ret_val; 3095 } else if (hw->phy_type == em_phy_gg82563) { 3096 ret_val = em_copper_link_ggp_setup(hw); 3097 if (ret_val) 3098 return ret_val; 3099 } else if (hw->phy_type == em_phy_82577 || 3100 hw->phy_type == em_phy_82579 || 3101 hw->phy_type == em_phy_i217) { 3102 ret_val = em_copper_link_82577_setup(hw); 3103 if (ret_val) 3104 return ret_val; 3105 } else if (hw->phy_type == em_phy_82580) { 3106 ret_val = em_copper_link_82580_setup(hw); 3107 if (ret_val) 3108 return ret_val; 3109 } else if (hw->phy_type == em_phy_rtl8211) { 3110 ret_val = em_copper_link_rtl8211_setup(hw); 3111 if (ret_val) 3112 return ret_val; 3113 } 3114 if (hw->autoneg) { 3115 /* 3116 * Setup autoneg and flow control advertisement and perform 3117 * autonegotiation 3118 */ 3119 ret_val = em_copper_link_autoneg(hw); 3120 if (ret_val) 3121 return ret_val; 3122 } else { 3123 /* 3124 * PHY will be set to 10H, 10F, 100H,or 100F depending on 3125 * value from forced_speed_duplex. 3126 */ 3127 DEBUGOUT("Forcing speed and duplex\n"); 3128 ret_val = em_phy_force_speed_duplex(hw); 3129 if (ret_val) { 3130 DEBUGOUT("Error Forcing Speed and Duplex\n"); 3131 return ret_val; 3132 } 3133 } 3134 /* 3135 * Check link status. Wait up to 100 microseconds for link to become 3136 * valid. 3137 */ 3138 for (i = 0; i < 10; i++) { 3139 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 3140 if (ret_val) 3141 return ret_val; 3142 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 3143 if (ret_val) 3144 return ret_val; 3145 3146 hw->icp_xxxx_is_link_up = (phy_data & MII_SR_LINK_STATUS) != 0; 3147 3148 if (phy_data & MII_SR_LINK_STATUS) { 3149 /* Config the MAC and PHY after link is up */ 3150 ret_val = em_copper_link_postconfig(hw); 3151 if (ret_val) 3152 return ret_val; 3153 3154 DEBUGOUT("Valid link established!!!\n"); 3155 return E1000_SUCCESS; 3156 } 3157 usec_delay(10); 3158 } 3159 3160 DEBUGOUT("Unable to establish link!!!\n"); 3161 return E1000_SUCCESS; 3162 } 3163 3164 /****************************************************************************** 3165 * Configure the MAC-to-PHY interface for 10/100Mbps 3166 * 3167 * hw - Struct containing variables accessed by shared code 3168 *****************************************************************************/ 3169 static int32_t 3170 em_configure_kmrn_for_10_100(struct em_hw *hw, uint16_t duplex) 3171 { 3172 int32_t ret_val = E1000_SUCCESS; 3173 uint32_t tipg; 3174 uint16_t reg_data; 3175 DEBUGFUNC("em_configure_kmrn_for_10_100"); 3176 3177 reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT; 3178 ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL, 3179 reg_data); 3180 if (ret_val) 3181 return ret_val; 3182 3183 /* Configure Transmit Inter-Packet Gap */ 3184 tipg = E1000_READ_REG(hw, TIPG); 3185 tipg &= ~E1000_TIPG_IPGT_MASK; 3186 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100; 3187 E1000_WRITE_REG(hw, TIPG, tipg); 3188 3189 ret_val = em_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); 3190 3191 if (ret_val) 3192 return ret_val; 3193 3194 if (duplex == HALF_DUPLEX) 3195 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER; 3196 else 3197 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 3198 3199 ret_val = em_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 3200 3201 return ret_val; 3202 } 3203 3204 static int32_t 3205 em_configure_kmrn_for_1000(struct em_hw *hw) 3206 { 3207 int32_t ret_val = E1000_SUCCESS; 3208 uint16_t reg_data; 3209 uint32_t tipg; 3210 DEBUGFUNC("em_configure_kmrn_for_1000"); 3211 3212 reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT; 3213 ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL, 3214 reg_data); 3215 if (ret_val) 3216 return ret_val; 3217 3218 /* Configure Transmit Inter-Packet Gap */ 3219 tipg = E1000_READ_REG(hw, TIPG); 3220 tipg &= ~E1000_TIPG_IPGT_MASK; 3221 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; 3222 E1000_WRITE_REG(hw, TIPG, tipg); 3223 3224 ret_val = em_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); 3225 3226 if (ret_val) 3227 return ret_val; 3228 3229 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 3230 ret_val = em_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 3231 3232 return ret_val; 3233 } 3234 3235 /****************************************************************************** 3236 * Configures PHY autoneg and flow control advertisement settings 3237 * 3238 * hw - Struct containing variables accessed by shared code 3239 *****************************************************************************/ 3240 int32_t 3241 em_phy_setup_autoneg(struct em_hw *hw) 3242 { 3243 int32_t ret_val; 3244 uint16_t mii_autoneg_adv_reg; 3245 uint16_t mii_1000t_ctrl_reg; 3246 DEBUGFUNC("em_phy_setup_autoneg"); 3247 3248 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 3249 ret_val = em_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 3250 if (ret_val) 3251 return ret_val; 3252 3253 if (hw->phy_type != em_phy_ife) { 3254 /* Read the MII 1000Base-T Control Register (Address 9). */ 3255 ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, 3256 &mii_1000t_ctrl_reg); 3257 if (ret_val) 3258 return ret_val; 3259 } else 3260 mii_1000t_ctrl_reg = 0; 3261 /* 3262 * Need to parse both autoneg_advertised and fc and set up the 3263 * appropriate PHY registers. First we will parse for 3264 * autoneg_advertised software override. Since we can advertise a 3265 * plethora of combinations, we need to check each bit individually. 3266 */ 3267 /* 3268 * First we clear all the 10/100 mb speed bits in the Auto-Neg 3269 * Advertisement Register (Address 4) and the 1000 mb speed bits in 3270 * the 1000Base-T Control Register (Address 9). 3271 */ 3272 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK; 3273 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK; 3274 3275 DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised); 3276 3277 /* Do we want to advertise 10 Mb Half Duplex? */ 3278 if (hw->autoneg_advertised & ADVERTISE_10_HALF) { 3279 DEBUGOUT("Advertise 10mb Half duplex\n"); 3280 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 3281 } 3282 /* Do we want to advertise 10 Mb Full Duplex? */ 3283 if (hw->autoneg_advertised & ADVERTISE_10_FULL) { 3284 DEBUGOUT("Advertise 10mb Full duplex\n"); 3285 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 3286 } 3287 /* Do we want to advertise 100 Mb Half Duplex? */ 3288 if (hw->autoneg_advertised & ADVERTISE_100_HALF) { 3289 DEBUGOUT("Advertise 100mb Half duplex\n"); 3290 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 3291 } 3292 /* Do we want to advertise 100 Mb Full Duplex? */ 3293 if (hw->autoneg_advertised & ADVERTISE_100_FULL) { 3294 DEBUGOUT("Advertise 100mb Full duplex\n"); 3295 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 3296 } 3297 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 3298 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) { 3299 DEBUGOUT("Advertise 1000mb Half duplex requested, request" 3300 " denied!\n"); 3301 } 3302 /* Do we want to advertise 1000 Mb Full Duplex? */ 3303 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) { 3304 DEBUGOUT("Advertise 1000mb Full duplex\n"); 3305 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 3306 if (hw->phy_type == em_phy_ife) { 3307 DEBUGOUT("em_phy_ife is a 10/100 PHY. Gigabit speed is" 3308 " not supported.\n"); 3309 } 3310 } 3311 /* 3312 * Check for a software override of the flow control settings, and 3313 * setup the PHY advertisement registers accordingly. If 3314 * auto-negotiation is enabled, then software will have to set the 3315 * "PAUSE" bits to the correct value in the Auto-Negotiation 3316 * Advertisement Register (PHY_AUTONEG_ADV) and re-start 3317 * auto-negotiation. 3318 * 3319 * The possible values of the "fc" parameter are: 0: Flow control is 3320 * completely disabled 1: Rx flow control is enabled (we can receive 3321 * pause frames but not send pause frames). 2: Tx flow control is 3322 * enabled (we can send pause frames but we do not support receiving 3323 * pause frames). 3: Both Rx and TX flow control (symmetric) are 3324 * enabled. other: No software override. The flow control 3325 * configuration in the EEPROM is used. 3326 */ 3327 switch (hw->fc) { 3328 case E1000_FC_NONE: /* 0 */ 3329 /* 3330 * Flow control (RX & TX) is completely disabled by a 3331 * software over-ride. 3332 */ 3333 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 3334 break; 3335 case E1000_FC_RX_PAUSE:/* 1 */ 3336 /* 3337 * RX Flow control is enabled, and TX Flow control is 3338 * disabled, by a software over-ride. 3339 */ 3340 /* 3341 * Since there really isn't a way to advertise that we are 3342 * capable of RX Pause ONLY, we will advertise that we 3343 * support both symmetric and asymmetric RX PAUSE. Later (in 3344 * em_config_fc_after_link_up) we will disable the hw's 3345 * ability to send PAUSE frames. 3346 */ 3347 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 3348 break; 3349 case E1000_FC_TX_PAUSE:/* 2 */ 3350 /* 3351 * TX Flow control is enabled, and RX Flow control is 3352 * disabled, by a software over-ride. 3353 */ 3354 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 3355 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 3356 break; 3357 case E1000_FC_FULL: /* 3 */ 3358 /* 3359 * Flow control (both RX and TX) is enabled by a software 3360 * over-ride. 3361 */ 3362 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 3363 break; 3364 default: 3365 DEBUGOUT("Flow control param set incorrectly\n"); 3366 return -E1000_ERR_CONFIG; 3367 } 3368 3369 ret_val = em_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 3370 if (ret_val) 3371 return ret_val; 3372 3373 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 3374 3375 if (hw->phy_type != em_phy_ife) { 3376 ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL, 3377 mii_1000t_ctrl_reg); 3378 if (ret_val) 3379 return ret_val; 3380 } 3381 return E1000_SUCCESS; 3382 } 3383 /****************************************************************************** 3384 * Force PHY speed and duplex settings to hw->forced_speed_duplex 3385 * 3386 * hw - Struct containing variables accessed by shared code 3387 *****************************************************************************/ 3388 static int32_t 3389 em_phy_force_speed_duplex(struct em_hw *hw) 3390 { 3391 uint32_t ctrl; 3392 int32_t ret_val; 3393 uint16_t mii_ctrl_reg; 3394 uint16_t mii_status_reg; 3395 uint16_t phy_data; 3396 uint16_t i; 3397 DEBUGFUNC("em_phy_force_speed_duplex"); 3398 3399 /* Turn off Flow control if we are forcing speed and duplex. */ 3400 hw->fc = E1000_FC_NONE; 3401 3402 DEBUGOUT1("hw->fc = %d\n", hw->fc); 3403 3404 /* Read the Device Control Register. */ 3405 ctrl = E1000_READ_REG(hw, CTRL); 3406 3407 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */ 3408 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 3409 ctrl &= ~(DEVICE_SPEED_MASK); 3410 3411 /* Clear the Auto Speed Detect Enable bit. */ 3412 ctrl &= ~E1000_CTRL_ASDE; 3413 3414 /* Read the MII Control Register. */ 3415 ret_val = em_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg); 3416 if (ret_val) 3417 return ret_val; 3418 3419 /* We need to disable autoneg in order to force link and duplex. */ 3420 3421 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN; 3422 3423 /* Are we forcing Full or Half Duplex? */ 3424 if (hw->forced_speed_duplex == em_100_full || 3425 hw->forced_speed_duplex == em_10_full) { 3426 /* 3427 * We want to force full duplex so we SET the full duplex 3428 * bits in the Device and MII Control Registers. 3429 */ 3430 ctrl |= E1000_CTRL_FD; 3431 mii_ctrl_reg |= MII_CR_FULL_DUPLEX; 3432 DEBUGOUT("Full Duplex\n"); 3433 } else { 3434 /* 3435 * We want to force half duplex so we CLEAR the full duplex 3436 * bits in the Device and MII Control Registers. 3437 */ 3438 ctrl &= ~E1000_CTRL_FD; 3439 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX; 3440 DEBUGOUT("Half Duplex\n"); 3441 } 3442 3443 /* Are we forcing 100Mbps??? */ 3444 if (hw->forced_speed_duplex == em_100_full || 3445 hw->forced_speed_duplex == em_100_half) { 3446 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */ 3447 ctrl |= E1000_CTRL_SPD_100; 3448 mii_ctrl_reg |= MII_CR_SPEED_100; 3449 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); 3450 DEBUGOUT("Forcing 100mb "); 3451 } else { 3452 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */ 3453 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 3454 mii_ctrl_reg |= MII_CR_SPEED_10; 3455 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); 3456 DEBUGOUT("Forcing 10mb "); 3457 } 3458 3459 em_config_collision_dist(hw); 3460 3461 /* Write the configured values back to the Device Control Reg. */ 3462 E1000_WRITE_REG(hw, CTRL, ctrl); 3463 3464 if ((hw->phy_type == em_phy_m88) || 3465 (hw->phy_type == em_phy_gg82563) || 3466 (hw->phy_type == em_phy_bm) || 3467 (hw->phy_type == em_phy_oem || 3468 (hw->phy_type == em_phy_82578))) { 3469 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 3470 &phy_data); 3471 if (ret_val) 3472 return ret_val; 3473 /* 3474 * Clear Auto-Crossover to force MDI manually. M88E1000 3475 * requires MDI forced whenever speed are duplex are forced. 3476 */ 3477 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 3478 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 3479 phy_data); 3480 if (ret_val) 3481 return ret_val; 3482 3483 DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data); 3484 3485 /* Need to reset the PHY or these changes will be ignored */ 3486 mii_ctrl_reg |= MII_CR_RESET; 3487 3488 } 3489 else if (hw->phy_type == em_phy_rtl8211) { 3490 ret_val = em_read_phy_reg_ex(hw, RGEPHY_CR, &phy_data); 3491 if(ret_val) { 3492 printf("Unable to read RGEPHY_CR register\n" 3493 ); 3494 return ret_val; 3495 } 3496 3497 /* 3498 * Clear Auto-Crossover to force MDI manually. RTL8211 requires 3499 * MDI forced whenever speed are duplex are forced. 3500 */ 3501 3502 phy_data |= RGEPHY_CR_MDI_MASK; // enable MDIX 3503 ret_val = em_write_phy_reg_ex(hw, RGEPHY_CR, phy_data); 3504 if(ret_val) { 3505 printf("Unable to write RGEPHY_CR register\n"); 3506 return ret_val; 3507 } 3508 mii_ctrl_reg |= MII_CR_RESET; 3509 3510 } 3511 /* Disable MDI-X support for 10/100 */ 3512 else if (hw->phy_type == em_phy_ife) { 3513 ret_val = em_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data); 3514 if (ret_val) 3515 return ret_val; 3516 3517 phy_data &= ~IFE_PMC_AUTO_MDIX; 3518 phy_data &= ~IFE_PMC_FORCE_MDIX; 3519 3520 ret_val = em_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, phy_data); 3521 if (ret_val) 3522 return ret_val; 3523 } else { 3524 /* 3525 * Clear Auto-Crossover to force MDI manually. IGP requires 3526 * MDI forced whenever speed or duplex are forced. 3527 */ 3528 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, 3529 &phy_data); 3530 if (ret_val) 3531 return ret_val; 3532 3533 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 3534 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 3535 3536 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, 3537 phy_data); 3538 if (ret_val) 3539 return ret_val; 3540 } 3541 3542 /* Write back the modified PHY MII control register. */ 3543 ret_val = em_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg); 3544 if (ret_val) 3545 return ret_val; 3546 3547 usec_delay(1); 3548 /* 3549 * The wait_autoneg_complete flag may be a little misleading here. 3550 * Since we are forcing speed and duplex, Auto-Neg is not enabled. 3551 * But we do want to delay for a period while forcing only so we 3552 * don't generate false No Link messages. So we will wait here only 3553 * if the user has set wait_autoneg_complete to 1, which is the 3554 * default. 3555 */ 3556 if (hw->wait_autoneg_complete) { 3557 /* We will wait for autoneg to complete. */ 3558 DEBUGOUT("Waiting for forced speed/duplex link.\n"); 3559 mii_status_reg = 0; 3560 /* 3561 * We will wait for autoneg to complete or 4.5 seconds to 3562 * expire. 3563 */ 3564 for (i = PHY_FORCE_TIME; i > 0; i--) { 3565 /* 3566 * Read the MII Status Register and wait for Auto-Neg 3567 * Complete bit to be set. 3568 */ 3569 ret_val = em_read_phy_reg(hw, PHY_STATUS, 3570 &mii_status_reg); 3571 if (ret_val) 3572 return ret_val; 3573 3574 ret_val = em_read_phy_reg(hw, PHY_STATUS, 3575 &mii_status_reg); 3576 if (ret_val) 3577 return ret_val; 3578 3579 if (mii_status_reg & MII_SR_LINK_STATUS) 3580 break; 3581 msec_delay(100); 3582 } 3583 if ((i == 0) && 3584 ((hw->phy_type == em_phy_m88) || 3585 (hw->phy_type == em_phy_gg82563) || 3586 (hw->phy_type == em_phy_bm))) { 3587 /* 3588 * We didn't get link. Reset the DSP and wait again 3589 * for link. 3590 */ 3591 ret_val = em_phy_reset_dsp(hw); 3592 if (ret_val) { 3593 DEBUGOUT("Error Resetting PHY DSP\n"); 3594 return ret_val; 3595 } 3596 } 3597 /* 3598 * This loop will early-out if the link condition has been 3599 * met. 3600 */ 3601 for (i = PHY_FORCE_TIME; i > 0; i--) { 3602 if (mii_status_reg & MII_SR_LINK_STATUS) 3603 break; 3604 msec_delay(100); 3605 /* 3606 * Read the MII Status Register and wait for Auto-Neg 3607 * Complete bit to be set. 3608 */ 3609 ret_val = em_read_phy_reg(hw, PHY_STATUS, 3610 &mii_status_reg); 3611 if (ret_val) 3612 return ret_val; 3613 3614 ret_val = em_read_phy_reg(hw, PHY_STATUS, 3615 &mii_status_reg); 3616 if (ret_val) 3617 return ret_val; 3618 } 3619 } 3620 if (hw->phy_type == em_phy_m88 || 3621 hw->phy_type == em_phy_bm || 3622 hw->phy_type == em_phy_oem) { 3623 /* 3624 * Because we reset the PHY above, we need to re-force TX_CLK 3625 * in the Extended PHY Specific Control Register to 25MHz 3626 * clock. This value defaults back to a 2.5MHz clock when 3627 * the PHY is reset. 3628 */ 3629 ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 3630 &phy_data); 3631 if (ret_val) 3632 return ret_val; 3633 3634 phy_data |= M88E1000_EPSCR_TX_CLK_25; 3635 ret_val = em_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 3636 phy_data); 3637 if (ret_val) 3638 return ret_val; 3639 /* 3640 * In addition, because of the s/w reset above, we need to 3641 * enable CRS on TX. This must be set for both full and half 3642 * duplex operation. 3643 */ 3644 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 3645 &phy_data); 3646 if (ret_val) 3647 return ret_val; 3648 3649 if (hw->phy_id == M88E1141_E_PHY_ID) 3650 phy_data &= ~M88E1000_PSCR_ASSERT_CRS_ON_TX; 3651 else 3652 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 3653 3654 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 3655 phy_data); 3656 if (ret_val) 3657 return ret_val; 3658 3659 if ((hw->mac_type == em_82544 || hw->mac_type == em_82543) && 3660 (!hw->autoneg) && (hw->forced_speed_duplex == em_10_full || 3661 hw->forced_speed_duplex == em_10_half)) { 3662 ret_val = em_polarity_reversal_workaround(hw); 3663 if (ret_val) 3664 return ret_val; 3665 } 3666 } else if (hw->phy_type == em_phy_rtl8211) { 3667 /* 3668 * In addition, because of the s/w reset above, we need to enable 3669 * CRX on TX. This must be set for both full and half duplex 3670 * operation. 3671 */ 3672 3673 ret_val = em_read_phy_reg_ex(hw, RGEPHY_CR, &phy_data); 3674 if(ret_val) { 3675 printf("Unable to read RGEPHY_CR register\n"); 3676 return ret_val; 3677 } 3678 3679 phy_data &= ~RGEPHY_CR_ASSERT_CRS; 3680 ret_val = em_write_phy_reg_ex(hw, RGEPHY_CR, phy_data); 3681 if(ret_val) { 3682 printf("Unable to write RGEPHY_CR register\n"); 3683 return ret_val; 3684 } 3685 } else if (hw->phy_type == em_phy_gg82563) { 3686 /* 3687 * The TX_CLK of the Extended PHY Specific Control Register 3688 * defaults to 2.5MHz on a reset. We need to re-force it 3689 * back to 25MHz, if we're not in a forced 10/duplex 3690 * configuration. 3691 */ 3692 ret_val = em_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 3693 &phy_data); 3694 if (ret_val) 3695 return ret_val; 3696 3697 phy_data &= ~GG82563_MSCR_TX_CLK_MASK; 3698 if ((hw->forced_speed_duplex == em_10_full) || 3699 (hw->forced_speed_duplex == em_10_half)) 3700 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ; 3701 else 3702 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25MHZ; 3703 3704 /* Also due to the reset, we need to enable CRS on Tx. */ 3705 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 3706 3707 ret_val = em_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 3708 phy_data); 3709 if (ret_val) 3710 return ret_val; 3711 } 3712 return E1000_SUCCESS; 3713 } 3714 3715 /****************************************************************************** 3716 * Sets the collision distance in the Transmit Control register 3717 * 3718 * hw - Struct containing variables accessed by shared code 3719 * 3720 * Link should have been established previously. Reads the speed and duplex 3721 * information from the Device Status register. 3722 *****************************************************************************/ 3723 void 3724 em_config_collision_dist(struct em_hw *hw) 3725 { 3726 uint32_t tctl, coll_dist; 3727 DEBUGFUNC("em_config_collision_dist"); 3728 3729 if (hw->mac_type < em_82543) 3730 coll_dist = E1000_COLLISION_DISTANCE_82542; 3731 else 3732 coll_dist = E1000_COLLISION_DISTANCE; 3733 3734 tctl = E1000_READ_REG(hw, TCTL); 3735 3736 tctl &= ~E1000_TCTL_COLD; 3737 tctl |= coll_dist << E1000_COLD_SHIFT; 3738 3739 E1000_WRITE_REG(hw, TCTL, tctl); 3740 E1000_WRITE_FLUSH(hw); 3741 } 3742 3743 /****************************************************************************** 3744 * Sets MAC speed and duplex settings to reflect the those in the PHY 3745 * 3746 * hw - Struct containing variables accessed by shared code 3747 * mii_reg - data to write to the MII control register 3748 * 3749 * The contents of the PHY register containing the needed information need to 3750 * be passed in. 3751 *****************************************************************************/ 3752 static int32_t 3753 em_config_mac_to_phy(struct em_hw *hw) 3754 { 3755 uint32_t ctrl; 3756 int32_t ret_val; 3757 uint16_t phy_data; 3758 DEBUGFUNC("em_config_mac_to_phy"); 3759 /* 3760 * 82544 or newer MAC, Auto Speed Detection takes care of MAC 3761 * speed/duplex configuration. 3762 */ 3763 if (hw->mac_type >= em_82544 3764 && hw->mac_type != em_icp_xxxx) 3765 return E1000_SUCCESS; 3766 /* 3767 * Read the Device Control Register and set the bits to Force Speed 3768 * and Duplex. 3769 */ 3770 ctrl = E1000_READ_REG(hw, CTRL); 3771 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 3772 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); 3773 /* 3774 * Set up duplex in the Device Control and Transmit Control registers 3775 * depending on negotiated values. 3776 */ 3777 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 3778 if (ret_val) 3779 return ret_val; 3780 3781 if (phy_data & M88E1000_PSSR_DPLX) 3782 ctrl |= E1000_CTRL_FD; 3783 else 3784 ctrl &= ~E1000_CTRL_FD; 3785 3786 em_config_collision_dist(hw); 3787 /* 3788 * Set up speed in the Device Control register depending on 3789 * negotiated values. 3790 */ 3791 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) 3792 ctrl |= E1000_CTRL_SPD_1000; 3793 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) 3794 ctrl |= E1000_CTRL_SPD_100; 3795 3796 /* Write the configured values back to the Device Control Reg. */ 3797 E1000_WRITE_REG(hw, CTRL, ctrl); 3798 return E1000_SUCCESS; 3799 } 3800 3801 /****************************************************************************** 3802 * Forces the MAC's flow control settings. 3803 * 3804 * hw - Struct containing variables accessed by shared code 3805 * 3806 * Sets the TFCE and RFCE bits in the device control register to reflect 3807 * the adapter settings. TFCE and RFCE need to be explicitly set by 3808 * software when a Copper PHY is used because autonegotiation is managed 3809 * by the PHY rather than the MAC. Software must also configure these 3810 * bits when link is forced on a fiber connection. 3811 *****************************************************************************/ 3812 int32_t 3813 em_force_mac_fc(struct em_hw *hw) 3814 { 3815 uint32_t ctrl; 3816 DEBUGFUNC("em_force_mac_fc"); 3817 3818 /* Get the current configuration of the Device Control Register */ 3819 ctrl = E1000_READ_REG(hw, CTRL); 3820 /* 3821 * Because we didn't get link via the internal auto-negotiation 3822 * mechanism (we either forced link or we got link via PHY auto-neg), 3823 * we have to manually enable/disable transmit an receive flow 3824 * control. 3825 * 3826 * The "Case" statement below enables/disable flow control according to 3827 * the "hw->fc" parameter. 3828 * 3829 * The possible values of the "fc" parameter are: 0: Flow control is 3830 * completely disabled 1: Rx flow control is enabled (we can receive 3831 * pause frames but not send pause frames). 2: Tx flow control is 3832 * enabled (we can send pause frames frames but we do not receive 3833 * pause frames). 3: Both Rx and TX flow control (symmetric) is 3834 * enabled. other: No other values should be possible at this point. 3835 */ 3836 3837 switch (hw->fc) { 3838 case E1000_FC_NONE: 3839 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 3840 break; 3841 case E1000_FC_RX_PAUSE: 3842 ctrl &= (~E1000_CTRL_TFCE); 3843 ctrl |= E1000_CTRL_RFCE; 3844 break; 3845 case E1000_FC_TX_PAUSE: 3846 ctrl &= (~E1000_CTRL_RFCE); 3847 ctrl |= E1000_CTRL_TFCE; 3848 break; 3849 case E1000_FC_FULL: 3850 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 3851 break; 3852 default: 3853 DEBUGOUT("Flow control param set incorrectly\n"); 3854 return -E1000_ERR_CONFIG; 3855 } 3856 3857 /* Disable TX Flow Control for 82542 (rev 2.0) */ 3858 if (hw->mac_type == em_82542_rev2_0) 3859 ctrl &= (~E1000_CTRL_TFCE); 3860 3861 E1000_WRITE_REG(hw, CTRL, ctrl); 3862 return E1000_SUCCESS; 3863 } 3864 /****************************************************************************** 3865 * Configures flow control settings after link is established 3866 * 3867 * hw - Struct containing variables accessed by shared code 3868 * 3869 * Should be called immediately after a valid link has been established. 3870 * Forces MAC flow control settings if link was forced. When in MII/GMII mode 3871 * and autonegotiation is enabled, the MAC flow control settings will be set 3872 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE 3873 * and RFCE bits will be automaticaly set to the negotiated flow control mode. 3874 *****************************************************************************/ 3875 STATIC int32_t 3876 em_config_fc_after_link_up(struct em_hw *hw) 3877 { 3878 int32_t ret_val; 3879 uint16_t mii_status_reg; 3880 uint16_t mii_nway_adv_reg; 3881 uint16_t mii_nway_lp_ability_reg; 3882 uint16_t speed; 3883 uint16_t duplex; 3884 DEBUGFUNC("em_config_fc_after_link_up"); 3885 /* 3886 * Check for the case where we have fiber media and auto-neg failed 3887 * so we had to force link. In this case, we need to force the 3888 * configuration of the MAC to match the "fc" parameter. 3889 */ 3890 if (((hw->media_type == em_media_type_fiber) && (hw->autoneg_failed)) 3891 || ((hw->media_type == em_media_type_internal_serdes) && 3892 (hw->autoneg_failed)) || 3893 ((hw->media_type == em_media_type_copper) && (!hw->autoneg)) || 3894 ((hw->media_type == em_media_type_oem) && (!hw->autoneg))) { 3895 ret_val = em_force_mac_fc(hw); 3896 if (ret_val) { 3897 DEBUGOUT("Error forcing flow control settings\n"); 3898 return ret_val; 3899 } 3900 } 3901 /* 3902 * Check for the case where we have copper media and auto-neg is 3903 * enabled. In this case, we need to check and see if Auto-Neg has 3904 * completed, and if so, how the PHY and link partner has flow 3905 * control configured. 3906 */ 3907 if ((hw->media_type == em_media_type_copper || 3908 (hw->media_type == em_media_type_oem)) && 3909 hw->autoneg) { 3910 /* 3911 * Read the MII Status Register and check to see if AutoNeg 3912 * has completed. We read this twice because this reg has 3913 * some "sticky" (latched) bits. 3914 */ 3915 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 3916 if (ret_val) 3917 return ret_val; 3918 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 3919 if (ret_val) 3920 return ret_val; 3921 3922 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) { 3923 /* 3924 * The AutoNeg process has completed, so we now need 3925 * to read both the Auto Negotiation Advertisement 3926 * Register (Address 4) and the Auto_Negotiation Base 3927 * Page Ability Register (Address 5) to determine how 3928 * flow control was negotiated. 3929 */ 3930 ret_val = em_read_phy_reg(hw, PHY_AUTONEG_ADV, 3931 &mii_nway_adv_reg); 3932 if (ret_val) 3933 return ret_val; 3934 ret_val = em_read_phy_reg(hw, PHY_LP_ABILITY, 3935 &mii_nway_lp_ability_reg); 3936 if (ret_val) 3937 return ret_val; 3938 /* 3939 * Two bits in the Auto Negotiation Advertisement 3940 * Register (Address 4) and two bits in the Auto 3941 * Negotiation Base Page Ability Register (Address 5) 3942 * determine flow control for both the PHY and the 3943 * link partner. The following table, taken out of 3944 * the IEEE 802.3ab/D6.0 dated March 25, 1999, 3945 * describes these PAUSE resolution bits and how flow 3946 * control is determined based upon these settings. 3947 * NOTE: DC = Don't Care 3948 * 3949 * LOCAL DEVICE | LINK PARTNER | 3950 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 3951 * -------|---------|-------|---------|--------------- 3952 * 0 | 0 | DC | DC | em_fc_none 3953 * 0 | 1 | 0 | DC | em_fc_none 3954 * 0 | 1 | 1 | 0 | em_fc_none 3955 * 0 | 1 | 1 | 1 | em_fc_tx_pause 3956 * 1 | 0 | 0 | DC | em_fc_none 3957 * 1 | DC | 1 | DC | em_fc_full 3958 * 1 | 1 | 0 | 0 | em_fc_none 3959 * 1 | 1 | 0 | 1 | em_fc_rx_pause 3960 * 3961 */ 3962 /* 3963 * Are both PAUSE bits set to 1? If so, this implies 3964 * Symmetric Flow Control is enabled at both ends. 3965 * The ASM_DIR bits are irrelevant per the spec. 3966 * 3967 * For Symmetric Flow Control: 3968 * 3969 * LOCAL DEVICE | LINK PARTNER 3970 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 3971 * -------|---------|-------|---------|--------------- 3972 * 1 | DC | 1 | DC | em_fc_full 3973 * 3974 */ 3975 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 3976 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 3977 /* 3978 * Now we need to check if the user selected 3979 * RX ONLY of pause frames. In this case, we 3980 * had to advertise FULL flow control because 3981 * we could not advertise RX ONLY. Hence, we 3982 * must now check to see if we need to turn 3983 * OFF the TRANSMISSION of PAUSE frames. 3984 */ 3985 if (hw->original_fc == E1000_FC_FULL) { 3986 hw->fc = E1000_FC_FULL; 3987 DEBUGOUT("Flow Control = FULL.\n"); 3988 } else { 3989 hw->fc = E1000_FC_RX_PAUSE; 3990 DEBUGOUT("Flow Control = RX PAUSE" 3991 " frames only.\n"); 3992 } 3993 } 3994 /* 3995 * For receiving PAUSE frames ONLY. 3996 * 3997 * LOCAL DEVICE | LINK PARTNER PAUSE | ASM_DIR | 3998 * PAUSE | ASM_DIR | Result 3999 * -------|---------|-------|---------|--------------- 4000 * ----- 0 | 1 | 1 | 1 | 4001 * em_fc_tx_pause 4002 * 4003 */ 4004 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 4005 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 4006 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 4007 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 4008 hw->fc = E1000_FC_TX_PAUSE; 4009 DEBUGOUT("Flow Control = TX PAUSE frames only." 4010 "\n"); 4011 } 4012 /* 4013 * For transmitting PAUSE frames ONLY. 4014 * 4015 * LOCAL DEVICE | LINK PARTNER 4016 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 4017 * -------|---------|-------|---------|--------------- 4018 * 1 | 1 | 0 | 1 | em_fc_rx_pause 4019 * 4020 */ 4021 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 4022 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 4023 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 4024 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 4025 hw->fc = E1000_FC_RX_PAUSE; 4026 DEBUGOUT("Flow Control = RX PAUSE frames only." 4027 "\n"); 4028 } 4029 /* 4030 * Per the IEEE spec, at this point flow control 4031 * should be disabled. However, we want to consider 4032 * that we could be connected to a legacy switch that 4033 * doesn't advertise desired flow control, but can be 4034 * forced on the link partner. So if we advertised 4035 * no flow control, that is what we will resolve to. 4036 * If we advertised some kind of receive capability 4037 * (Rx Pause Only or Full Flow Control) and the link 4038 * partner advertised none, we will configure 4039 * ourselves to enable Rx Flow Control only. We can 4040 * do this safely for two reasons: If the link 4041 * partner really didn't want flow control enabled, 4042 * and we enable Rx, no harm done since we won't be 4043 * receiving any PAUSE frames anyway. If the intent 4044 * on the link partner was to have flow control 4045 * enabled, then by us enabling RX only, we can at 4046 * least receive pause frames and process them. This 4047 * is a good idea because in most cases, since we are 4048 * predominantly a server NIC, more times than not we 4049 * will be asked to delay transmission of packets 4050 * than asking our link partner to pause transmission 4051 * of frames. 4052 */ 4053 else if ((hw->original_fc == E1000_FC_NONE || 4054 hw->original_fc == E1000_FC_TX_PAUSE) || 4055 hw->fc_strict_ieee) { 4056 hw->fc = E1000_FC_NONE; 4057 DEBUGOUT("Flow Control = NONE.\n"); 4058 } else { 4059 hw->fc = E1000_FC_RX_PAUSE; 4060 DEBUGOUT("Flow Control = RX PAUSE frames only." 4061 "\n"); 4062 } 4063 /* 4064 * Now we need to do one last check... If we auto- 4065 * negotiated to HALF DUPLEX, flow control should not 4066 * be enabled per IEEE 802.3 spec. 4067 */ 4068 ret_val = em_get_speed_and_duplex(hw, &speed, &duplex); 4069 if (ret_val) { 4070 DEBUGOUT("Error getting link speed and duplex" 4071 "\n"); 4072 return ret_val; 4073 } 4074 if (duplex == HALF_DUPLEX) 4075 hw->fc = E1000_FC_NONE; 4076 /* 4077 * Now we call a subroutine to actually force the MAC 4078 * controller to use the correct flow control 4079 * settings. 4080 */ 4081 ret_val = em_force_mac_fc(hw); 4082 if (ret_val) { 4083 DEBUGOUT("Error forcing flow control settings" 4084 "\n"); 4085 return ret_val; 4086 } 4087 } else { 4088 DEBUGOUT("Copper PHY and Auto Neg has not completed." 4089 "\n"); 4090 } 4091 } 4092 return E1000_SUCCESS; 4093 } 4094 /****************************************************************************** 4095 * Checks to see if the link status of the hardware has changed. 4096 * 4097 * hw - Struct containing variables accessed by shared code 4098 * 4099 * Called by any function that needs to check the link status of the adapter. 4100 *****************************************************************************/ 4101 int32_t 4102 em_check_for_link(struct em_hw *hw) 4103 { 4104 uint32_t rxcw = 0; 4105 uint32_t ctrl; 4106 uint32_t status; 4107 uint32_t rctl; 4108 uint32_t icr; 4109 uint32_t signal = 0; 4110 int32_t ret_val; 4111 uint16_t phy_data; 4112 DEBUGFUNC("em_check_for_link"); 4113 uint16_t speed, duplex; 4114 4115 if (hw->mac_type >= em_82575 && 4116 hw->media_type != em_media_type_copper) { 4117 ret_val = em_get_pcs_speed_and_duplex_82575(hw, &speed, 4118 &duplex); 4119 hw->get_link_status = hw->serdes_link_down; 4120 4121 return (ret_val); 4122 } 4123 4124 ctrl = E1000_READ_REG(hw, CTRL); 4125 status = E1000_READ_REG(hw, STATUS); 4126 /* 4127 * On adapters with a MAC newer than 82544, SW Defineable pin 1 will 4128 * be set when the optics detect a signal. On older adapters, it will 4129 * be cleared when there is a signal. This applies to fiber media 4130 * only. 4131 */ 4132 if ((hw->media_type == em_media_type_fiber) || 4133 (hw->media_type == em_media_type_internal_serdes)) { 4134 rxcw = E1000_READ_REG(hw, RXCW); 4135 4136 if (hw->media_type == em_media_type_fiber) { 4137 signal = (hw->mac_type > em_82544) ? 4138 E1000_CTRL_SWDPIN1 : 0; 4139 if (status & E1000_STATUS_LU) 4140 hw->get_link_status = FALSE; 4141 } 4142 } 4143 /* 4144 * If we have a copper PHY then we only want to go out to the PHY 4145 * registers to see if Auto-Neg has completed and/or if our link 4146 * status has changed. The get_link_status flag will be set if we 4147 * receive a Link Status Change interrupt or we have Rx Sequence 4148 * Errors. 4149 */ 4150 if ((hw->media_type == em_media_type_copper || 4151 (hw->media_type == em_media_type_oem)) && 4152 hw->get_link_status) { 4153 /* 4154 * First we want to see if the MII Status Register reports 4155 * link. If so, then we want to get the current speed/duplex 4156 * of the PHY. Read the register twice since the link bit is 4157 * sticky. 4158 */ 4159 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 4160 if (ret_val) 4161 return ret_val; 4162 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 4163 if (ret_val) 4164 return ret_val; 4165 4166 hw->icp_xxxx_is_link_up = (phy_data & MII_SR_LINK_STATUS) != 0; 4167 4168 if (hw->mac_type == em_pchlan) { 4169 ret_val = em_k1_gig_workaround_hv(hw, 4170 hw->icp_xxxx_is_link_up); 4171 if (ret_val) 4172 return ret_val; 4173 } 4174 4175 if (phy_data & MII_SR_LINK_STATUS) { 4176 hw->get_link_status = FALSE; 4177 4178 if (hw->phy_type == em_phy_82578) { 4179 ret_val = em_link_stall_workaround_hv(hw); 4180 if (ret_val) 4181 return ret_val; 4182 } 4183 4184 if (hw->mac_type == em_pch2lan) { 4185 ret_val = em_k1_workaround_lv(hw); 4186 if (ret_val) 4187 return ret_val; 4188 } 4189 /* Work-around I218 hang issue */ 4190 if ((hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) || 4191 (hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) || 4192 (hw->device_id == E1000_DEV_ID_PCH_I218_LM3) || 4193 (hw->device_id == E1000_DEV_ID_PCH_I218_V3)) { 4194 ret_val = em_k1_workaround_lpt_lp(hw, 4195 hw->icp_xxxx_is_link_up); 4196 if (ret_val) 4197 return ret_val; 4198 } 4199 4200 /* 4201 * Check if there was DownShift, must be checked 4202 * immediately after link-up 4203 */ 4204 em_check_downshift(hw); 4205 4206 /* Enable/Disable EEE after link up */ 4207 if (hw->mac_type == em_pch2lan || 4208 hw->mac_type == em_pch_lpt || 4209 hw->mac_type == em_pch_spt || 4210 hw->mac_type == em_pch_cnp) { 4211 ret_val = em_set_eee_pchlan(hw); 4212 if (ret_val) 4213 return ret_val; 4214 } 4215 4216 /* 4217 * If we are on 82544 or 82543 silicon and 4218 * speed/duplex are forced to 10H or 10F, then we 4219 * will implement the polarity reversal workaround. 4220 * We disable interrupts first, and upon returning, 4221 * place the devices interrupt state to its previous 4222 * value except for the link status change interrupt 4223 * which will happen due to the execution of this 4224 * workaround. 4225 */ 4226 if ((hw->mac_type == em_82544 || 4227 hw->mac_type == em_82543) && (!hw->autoneg) && 4228 (hw->forced_speed_duplex == em_10_full || 4229 hw->forced_speed_duplex == em_10_half)) { 4230 E1000_WRITE_REG(hw, IMC, 0xffffffff); 4231 ret_val = em_polarity_reversal_workaround(hw); 4232 icr = E1000_READ_REG(hw, ICR); 4233 E1000_WRITE_REG(hw, ICS, 4234 (icr & ~E1000_ICS_LSC)); 4235 E1000_WRITE_REG(hw, IMS, IMS_ENABLE_MASK); 4236 } 4237 } else { 4238 /* No link detected */ 4239 em_config_dsp_after_link_change(hw, FALSE); 4240 return 0; 4241 } 4242 /* 4243 * If we are forcing speed/duplex, then we simply return 4244 * since we have already determined whether we have link or 4245 * not. 4246 */ 4247 if (!hw->autoneg) 4248 return -E1000_ERR_CONFIG; 4249 4250 /* optimize the dsp settings for the igp phy */ 4251 em_config_dsp_after_link_change(hw, TRUE); 4252 /* 4253 * We have a M88E1000 PHY and Auto-Neg is enabled. If we 4254 * have Si on board that is 82544 or newer, Auto Speed 4255 * Detection takes care of MAC speed/duplex configuration. 4256 * So we only need to configure Collision Distance in the 4257 * MAC. Otherwise, we need to force speed/duplex on the MAC 4258 * to the current PHY speed/duplex settings. 4259 */ 4260 if (hw->mac_type >= em_82544 && hw->mac_type != em_icp_xxxx) { 4261 em_config_collision_dist(hw); 4262 } else { 4263 ret_val = em_config_mac_to_phy(hw); 4264 if (ret_val) { 4265 DEBUGOUT("Error configuring MAC to PHY" 4266 " settings\n"); 4267 return ret_val; 4268 } 4269 } 4270 /* 4271 * Configure Flow Control now that Auto-Neg has completed. 4272 * First, we need to restore the desired flow control 4273 * settings because we may have had to re-autoneg with a 4274 * different link partner. 4275 */ 4276 ret_val = em_config_fc_after_link_up(hw); 4277 if (ret_val) { 4278 DEBUGOUT("Error configuring flow control\n"); 4279 return ret_val; 4280 } 4281 /* 4282 * At this point we know that we are on copper and we have 4283 * auto-negotiated link. These are conditions for checking 4284 * the link partner capability register. We use the link 4285 * speed to determine if TBI compatibility needs to be turned 4286 * on or off. If the link is not at gigabit speed, then TBI 4287 * compatibility is not needed. If we are at gigabit speed, 4288 * we turn on TBI compatibility. 4289 */ 4290 if (hw->tbi_compatibility_en) { 4291 uint16_t speed, duplex; 4292 ret_val = em_get_speed_and_duplex(hw, &speed, &duplex); 4293 if (ret_val) { 4294 DEBUGOUT("Error getting link speed and duplex" 4295 "\n"); 4296 return ret_val; 4297 } 4298 if (speed != SPEED_1000) { 4299 /* 4300 * If link speed is not set to gigabit speed, 4301 * we do not need to enable TBI 4302 * compatibility. 4303 */ 4304 if (hw->tbi_compatibility_on) { 4305 /* 4306 * If we previously were in the mode, 4307 * turn it off. 4308 */ 4309 rctl = E1000_READ_REG(hw, RCTL); 4310 rctl &= ~E1000_RCTL_SBP; 4311 E1000_WRITE_REG(hw, RCTL, rctl); 4312 hw->tbi_compatibility_on = FALSE; 4313 } 4314 } else { 4315 /* 4316 * If TBI compatibility is was previously 4317 * off, turn it on. For compatibility with a 4318 * TBI link partner, we will store bad 4319 * packets. Some frames have an additional 4320 * byte on the end and will look like CRC 4321 * errors to to the hardware. 4322 */ 4323 if (!hw->tbi_compatibility_on) { 4324 hw->tbi_compatibility_on = TRUE; 4325 rctl = E1000_READ_REG(hw, RCTL); 4326 rctl |= E1000_RCTL_SBP; 4327 E1000_WRITE_REG(hw, RCTL, rctl); 4328 } 4329 } 4330 } 4331 } 4332 /* 4333 * If we don't have link (auto-negotiation failed or link partner 4334 * cannot auto-negotiate), the cable is plugged in (we have signal), 4335 * and our link partner is not trying to auto-negotiate with us (we 4336 * are receiving idles or data), we need to force link up. We also 4337 * need to give auto-negotiation time to complete, in case the cable 4338 * was just plugged in. The autoneg_failed flag does this. 4339 */ 4340 else if ((((hw->media_type == em_media_type_fiber) && 4341 ((ctrl & E1000_CTRL_SWDPIN1) == signal)) || 4342 (hw->media_type == em_media_type_internal_serdes)) && 4343 (!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) { 4344 if (hw->autoneg_failed == 0) { 4345 hw->autoneg_failed = 1; 4346 return 0; 4347 } 4348 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 4349 4350 /* Disable auto-negotiation in the TXCW register */ 4351 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE)); 4352 4353 /* Force link-up and also force full-duplex. */ 4354 ctrl = E1000_READ_REG(hw, CTRL); 4355 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 4356 E1000_WRITE_REG(hw, CTRL, ctrl); 4357 4358 /* Configure Flow Control after forcing link up. */ 4359 ret_val = em_config_fc_after_link_up(hw); 4360 if (ret_val) { 4361 DEBUGOUT("Error configuring flow control\n"); 4362 return ret_val; 4363 } 4364 } 4365 /* 4366 * If we are forcing link and we are receiving /C/ ordered sets, 4367 * re-enable auto-negotiation in the TXCW register and disable forced 4368 * link in the Device Control register in an attempt to 4369 * auto-negotiate with our link partner. 4370 */ 4371 else if (((hw->media_type == em_media_type_fiber) || 4372 (hw->media_type == em_media_type_internal_serdes)) && 4373 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 4374 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 4375 E1000_WRITE_REG(hw, TXCW, hw->txcw); 4376 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU)); 4377 4378 hw->serdes_link_down = FALSE; 4379 } 4380 /* 4381 * If we force link for non-auto-negotiation switch, check link 4382 * status based on MAC synchronization for internal serdes media 4383 * type. 4384 */ 4385 else if ((hw->media_type == em_media_type_internal_serdes) && 4386 !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) { 4387 /* SYNCH bit and IV bit are sticky. */ 4388 usec_delay(10); 4389 if (E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) { 4390 if (!(rxcw & E1000_RXCW_IV)) { 4391 hw->serdes_link_down = FALSE; 4392 DEBUGOUT("SERDES: Link is up.\n"); 4393 } 4394 } else { 4395 hw->serdes_link_down = TRUE; 4396 DEBUGOUT("SERDES: Link is down.\n"); 4397 } 4398 } 4399 if ((hw->media_type == em_media_type_internal_serdes) && 4400 (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) { 4401 hw->serdes_link_down = !(E1000_STATUS_LU & 4402 E1000_READ_REG(hw, STATUS)); 4403 } 4404 return E1000_SUCCESS; 4405 } 4406 4407 int32_t 4408 em_get_pcs_speed_and_duplex_82575(struct em_hw *hw, uint16_t *speed, 4409 uint16_t *duplex) 4410 { 4411 uint32_t pcs; 4412 4413 hw->serdes_link_down = TRUE; 4414 *speed = 0; 4415 *duplex = 0; 4416 4417 /* 4418 * Read the PCS Status register for link state. For non-copper mode, 4419 * the status register is not accurate. The PCS status register is 4420 * used instead. 4421 */ 4422 pcs = E1000_READ_REG(hw, PCS_LSTAT); 4423 4424 /* 4425 * The link up bit determines when link is up on autoneg. The sync ok 4426 * gets set once both sides sync up and agree upon link. Stable link 4427 * can be determined by checking for both link up and link sync ok 4428 */ 4429 if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) { 4430 hw->serdes_link_down = FALSE; 4431 4432 /* Detect and store PCS speed */ 4433 if (pcs & E1000_PCS_LSTS_SPEED_1000) { 4434 *speed = SPEED_1000; 4435 } else if (pcs & E1000_PCS_LSTS_SPEED_100) { 4436 *speed = SPEED_100; 4437 } else { 4438 *speed = SPEED_10; 4439 } 4440 4441 /* Detect and store PCS duplex */ 4442 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) { 4443 *duplex = FULL_DUPLEX; 4444 } else { 4445 *duplex = HALF_DUPLEX; 4446 } 4447 } 4448 4449 return (0); 4450 } 4451 4452 4453 /****************************************************************************** 4454 * Detects the current speed and duplex settings of the hardware. 4455 * 4456 * hw - Struct containing variables accessed by shared code 4457 * speed - Speed of the connection 4458 * duplex - Duplex setting of the connection 4459 *****************************************************************************/ 4460 int32_t 4461 em_get_speed_and_duplex(struct em_hw *hw, uint16_t *speed, uint16_t *duplex) 4462 { 4463 uint32_t status; 4464 int32_t ret_val; 4465 uint16_t phy_data; 4466 DEBUGFUNC("em_get_speed_and_duplex"); 4467 4468 if (hw->mac_type >= em_82575 && hw->media_type != em_media_type_copper) 4469 return em_get_pcs_speed_and_duplex_82575(hw, speed, duplex); 4470 4471 if (hw->mac_type >= em_82543) { 4472 status = E1000_READ_REG(hw, STATUS); 4473 if (status & E1000_STATUS_SPEED_1000) { 4474 *speed = SPEED_1000; 4475 DEBUGOUT("1000 Mbs, "); 4476 } else if (status & E1000_STATUS_SPEED_100) { 4477 *speed = SPEED_100; 4478 DEBUGOUT("100 Mbs, "); 4479 } else { 4480 *speed = SPEED_10; 4481 DEBUGOUT("10 Mbs, "); 4482 } 4483 4484 if (status & E1000_STATUS_FD) { 4485 *duplex = FULL_DUPLEX; 4486 DEBUGOUT("Full Duplex\n"); 4487 } else { 4488 *duplex = HALF_DUPLEX; 4489 DEBUGOUT(" Half Duplex\n"); 4490 } 4491 } else { 4492 DEBUGOUT("1000 Mbs, Full Duplex\n"); 4493 *speed = SPEED_1000; 4494 *duplex = FULL_DUPLEX; 4495 } 4496 /* 4497 * IGP01 PHY may advertise full duplex operation after speed 4498 * downgrade even if it is operating at half duplex. Here we set the 4499 * duplex settings to match the duplex in the link partner's 4500 * capabilities. 4501 */ 4502 if (hw->phy_type == em_phy_igp && hw->speed_downgraded) { 4503 ret_val = em_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data); 4504 if (ret_val) 4505 return ret_val; 4506 4507 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS)) 4508 *duplex = HALF_DUPLEX; 4509 else { 4510 ret_val = em_read_phy_reg(hw, PHY_LP_ABILITY, 4511 &phy_data); 4512 if (ret_val) 4513 return ret_val; 4514 if ((*speed == SPEED_100 && 4515 !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) || 4516 (*speed == SPEED_10 && 4517 !(phy_data & NWAY_LPAR_10T_FD_CAPS))) 4518 *duplex = HALF_DUPLEX; 4519 } 4520 } 4521 if ((hw->mac_type == em_80003es2lan) && 4522 (hw->media_type == em_media_type_copper)) { 4523 if (*speed == SPEED_1000) 4524 ret_val = em_configure_kmrn_for_1000(hw); 4525 else 4526 ret_val = em_configure_kmrn_for_10_100(hw, *duplex); 4527 if (ret_val) 4528 return ret_val; 4529 } 4530 if ((hw->mac_type == em_ich8lan) && 4531 (hw->phy_type == em_phy_igp_3) && 4532 (*speed == SPEED_1000)) { 4533 ret_val = em_kumeran_lock_loss_workaround(hw); 4534 if (ret_val) 4535 return ret_val; 4536 } 4537 return E1000_SUCCESS; 4538 } 4539 4540 /****************************************************************************** 4541 * Blocks until autoneg completes or times out (~4.5 seconds) 4542 * 4543 * hw - Struct containing variables accessed by shared code 4544 *****************************************************************************/ 4545 STATIC int32_t 4546 em_wait_autoneg(struct em_hw *hw) 4547 { 4548 int32_t ret_val; 4549 uint16_t i; 4550 uint16_t phy_data; 4551 DEBUGFUNC("em_wait_autoneg"); 4552 DEBUGOUT("Waiting for Auto-Neg to complete.\n"); 4553 4554 /* We will wait for autoneg to complete or 4.5 seconds to expire. */ 4555 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) { 4556 /* 4557 * Read the MII Status Register and wait for Auto-Neg 4558 * Complete bit to be set. 4559 */ 4560 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 4561 if (ret_val) 4562 return ret_val; 4563 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 4564 if (ret_val) 4565 return ret_val; 4566 if (phy_data & MII_SR_AUTONEG_COMPLETE) { 4567 return E1000_SUCCESS; 4568 } 4569 msec_delay(100); 4570 } 4571 return E1000_SUCCESS; 4572 } 4573 4574 /****************************************************************************** 4575 * Raises the Management Data Clock 4576 * 4577 * hw - Struct containing variables accessed by shared code 4578 * ctrl - Device control register's current value 4579 *****************************************************************************/ 4580 static void 4581 em_raise_mdi_clk(struct em_hw *hw, uint32_t *ctrl) 4582 { 4583 /* 4584 * Raise the clock input to the Management Data Clock (by setting the 4585 * MDC bit), and then delay 10 microseconds. 4586 */ 4587 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC)); 4588 E1000_WRITE_FLUSH(hw); 4589 usec_delay(10); 4590 } 4591 4592 /****************************************************************************** 4593 * Lowers the Management Data Clock 4594 * 4595 * hw - Struct containing variables accessed by shared code 4596 * ctrl - Device control register's current value 4597 *****************************************************************************/ 4598 static void 4599 em_lower_mdi_clk(struct em_hw *hw, uint32_t *ctrl) 4600 { 4601 /* 4602 * Lower the clock input to the Management Data Clock (by clearing 4603 * the MDC bit), and then delay 10 microseconds. 4604 */ 4605 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC)); 4606 E1000_WRITE_FLUSH(hw); 4607 usec_delay(10); 4608 } 4609 4610 /****************************************************************************** 4611 * Shifts data bits out to the PHY 4612 * 4613 * hw - Struct containing variables accessed by shared code 4614 * data - Data to send out to the PHY 4615 * count - Number of bits to shift out 4616 * 4617 * Bits are shifted out in MSB to LSB order. 4618 *****************************************************************************/ 4619 static void 4620 em_shift_out_mdi_bits(struct em_hw *hw, uint32_t data, uint16_t count) 4621 { 4622 uint32_t ctrl; 4623 uint32_t mask; 4624 /* 4625 * We need to shift "count" number of bits out to the PHY. So, the 4626 * value in the "data" parameter will be shifted out to the PHY one 4627 * bit at a time. In order to do this, "data" must be broken down 4628 * into bits. 4629 */ 4630 mask = 0x01; 4631 mask <<= (count - 1); 4632 4633 ctrl = E1000_READ_REG(hw, CTRL); 4634 4635 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output 4636 * pins. 4637 */ 4638 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); 4639 4640 while (mask) { 4641 /* 4642 * A "1" is shifted out to the PHY by setting the MDIO bit to 4643 * "1" and then raising and lowering the Management Data 4644 * Clock. A "0" is shifted out to the PHY by setting the MDIO 4645 * bit to "0" and then raising and lowering the clock. 4646 */ 4647 if (data & mask) 4648 ctrl |= E1000_CTRL_MDIO; 4649 else 4650 ctrl &= ~E1000_CTRL_MDIO; 4651 4652 E1000_WRITE_REG(hw, CTRL, ctrl); 4653 E1000_WRITE_FLUSH(hw); 4654 4655 usec_delay(10); 4656 4657 em_raise_mdi_clk(hw, &ctrl); 4658 em_lower_mdi_clk(hw, &ctrl); 4659 4660 mask = mask >> 1; 4661 } 4662 } 4663 4664 /****************************************************************************** 4665 * Shifts data bits in from the PHY 4666 * 4667 * hw - Struct containing variables accessed by shared code 4668 * 4669 * Bits are shifted in in MSB to LSB order. 4670 *****************************************************************************/ 4671 static uint16_t 4672 em_shift_in_mdi_bits(struct em_hw *hw) 4673 { 4674 uint32_t ctrl; 4675 uint16_t data = 0; 4676 uint8_t i; 4677 /* 4678 * In order to read a register from the PHY, we need to shift in a 4679 * total of 18 bits from the PHY. The first two bit (turnaround) 4680 * times are used to avoid contention on the MDIO pin when a read 4681 * operation is performed. These two bits are ignored by us and 4682 * thrown away. Bits are "shifted in" by raising the input to the 4683 * Management Data Clock (setting the MDC bit), and then reading the 4684 * value of the MDIO bit. 4685 */ 4686 ctrl = E1000_READ_REG(hw, CTRL); 4687 /* 4688 * Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as 4689 * input. 4690 */ 4691 ctrl &= ~E1000_CTRL_MDIO_DIR; 4692 ctrl &= ~E1000_CTRL_MDIO; 4693 4694 E1000_WRITE_REG(hw, CTRL, ctrl); 4695 E1000_WRITE_FLUSH(hw); 4696 /* 4697 * Raise and Lower the clock before reading in the data. This 4698 * accounts for the turnaround bits. The first clock occurred when we 4699 * clocked out the last bit of the Register Address. 4700 */ 4701 em_raise_mdi_clk(hw, &ctrl); 4702 em_lower_mdi_clk(hw, &ctrl); 4703 4704 for (data = 0, i = 0; i < 16; i++) { 4705 data = data << 1; 4706 em_raise_mdi_clk(hw, &ctrl); 4707 ctrl = E1000_READ_REG(hw, CTRL); 4708 /* Check to see if we shifted in a "1". */ 4709 if (ctrl & E1000_CTRL_MDIO) 4710 data |= 1; 4711 em_lower_mdi_clk(hw, &ctrl); 4712 } 4713 4714 em_raise_mdi_clk(hw, &ctrl); 4715 em_lower_mdi_clk(hw, &ctrl); 4716 4717 return data; 4718 } 4719 4720 STATIC int32_t 4721 em_swfw_sync_acquire(struct em_hw *hw, uint16_t mask) 4722 { 4723 uint32_t swfw_sync = 0; 4724 uint32_t swmask = mask; 4725 uint32_t fwmask = mask << 16; 4726 int32_t timeout = 200; 4727 DEBUGFUNC("em_swfw_sync_acquire"); 4728 4729 if (hw->swfwhw_semaphore_present) 4730 return em_get_software_flag(hw); 4731 4732 if (!hw->swfw_sync_present) 4733 return em_get_hw_eeprom_semaphore(hw); 4734 4735 while (timeout) { 4736 if (em_get_hw_eeprom_semaphore(hw)) 4737 return -E1000_ERR_SWFW_SYNC; 4738 4739 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); 4740 if (!(swfw_sync & (fwmask | swmask))) { 4741 break; 4742 } 4743 /* 4744 * firmware currently using resource (fwmask) 4745 * or other software thread currently using resource (swmask) 4746 */ 4747 em_put_hw_eeprom_semaphore(hw); 4748 msec_delay_irq(5); 4749 timeout--; 4750 } 4751 4752 if (!timeout) { 4753 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout." 4754 "\n"); 4755 return -E1000_ERR_SWFW_SYNC; 4756 } 4757 swfw_sync |= swmask; 4758 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync); 4759 4760 em_put_hw_eeprom_semaphore(hw); 4761 return E1000_SUCCESS; 4762 } 4763 4764 STATIC void 4765 em_swfw_sync_release(struct em_hw *hw, uint16_t mask) 4766 { 4767 uint32_t swfw_sync; 4768 uint32_t swmask = mask; 4769 DEBUGFUNC("em_swfw_sync_release"); 4770 4771 if (hw->swfwhw_semaphore_present) { 4772 em_release_software_flag(hw); 4773 return; 4774 } 4775 if (!hw->swfw_sync_present) { 4776 em_put_hw_eeprom_semaphore(hw); 4777 return; 4778 } 4779 /* 4780 * if (em_get_hw_eeprom_semaphore(hw)) return -E1000_ERR_SWFW_SYNC; 4781 */ 4782 while (em_get_hw_eeprom_semaphore(hw) != E1000_SUCCESS); 4783 /* empty */ 4784 4785 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); 4786 swfw_sync &= ~swmask; 4787 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync); 4788 4789 em_put_hw_eeprom_semaphore(hw); 4790 } 4791 4792 /**************************************************************************** 4793 * Read BM PHY wakeup register. It works as such: 4794 * 1) Set page 769, register 17, bit 2 = 1 4795 * 2) Set page to 800 for host (801 if we were manageability) 4796 * 3) Write the address using the address opcode (0x11) 4797 * 4) Read or write the data using the data opcode (0x12) 4798 * 5) Restore 769_17.2 to its original value 4799 ****************************************************************************/ 4800 int32_t 4801 em_access_phy_wakeup_reg_bm(struct em_hw *hw, uint32_t reg_addr, 4802 uint16_t *phy_data, boolean_t read) 4803 { 4804 int32_t ret_val; 4805 uint16_t reg = BM_PHY_REG_NUM(reg_addr); 4806 uint16_t phy_reg = 0; 4807 4808 /* All operations in this function are phy address 1 */ 4809 hw->phy_addr = 1; 4810 4811 /* Set page 769 */ 4812 em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 4813 (BM_WUC_ENABLE_PAGE << PHY_PAGE_SHIFT)); 4814 4815 ret_val = em_read_phy_reg_ex(hw, BM_WUC_ENABLE_REG, &phy_reg); 4816 if (ret_val) 4817 goto out; 4818 4819 /* First clear bit 4 to avoid a power state change */ 4820 phy_reg &= ~(BM_WUC_HOST_WU_BIT); 4821 ret_val = em_write_phy_reg_ex(hw, BM_WUC_ENABLE_REG, phy_reg); 4822 if (ret_val) 4823 goto out; 4824 4825 /* Write bit 2 = 1, and clear bit 4 to 769_17 */ 4826 ret_val = em_write_phy_reg_ex(hw, BM_WUC_ENABLE_REG, 4827 phy_reg | BM_WUC_ENABLE_BIT); 4828 if (ret_val) 4829 goto out; 4830 4831 /* Select page 800 */ 4832 ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 4833 (BM_WUC_PAGE << PHY_PAGE_SHIFT)); 4834 4835 /* Write the page 800 offset value using opcode 0x11 */ 4836 ret_val = em_write_phy_reg_ex(hw, BM_WUC_ADDRESS_OPCODE, reg); 4837 if (ret_val) 4838 goto out; 4839 4840 if (read) 4841 /* Read the page 800 value using opcode 0x12 */ 4842 ret_val = em_read_phy_reg_ex(hw, BM_WUC_DATA_OPCODE, 4843 phy_data); 4844 else 4845 /* Write the page 800 value using opcode 0x12 */ 4846 ret_val = em_write_phy_reg_ex(hw, BM_WUC_DATA_OPCODE, 4847 *phy_data); 4848 4849 if (ret_val) 4850 goto out; 4851 4852 /* 4853 * Restore 769_17.2 to its original value 4854 * Set page 769 4855 */ 4856 em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 4857 (BM_WUC_ENABLE_PAGE << PHY_PAGE_SHIFT)); 4858 4859 /* Clear 769_17.2 */ 4860 ret_val = em_write_phy_reg_ex(hw, BM_WUC_ENABLE_REG, phy_reg); 4861 if (ret_val) 4862 goto out; 4863 4864 out: 4865 return ret_val; 4866 } 4867 4868 /*************************************************************************** 4869 * Read HV PHY vendor specific high registers 4870 ***************************************************************************/ 4871 int32_t 4872 em_access_phy_debug_regs_hv(struct em_hw *hw, uint32_t reg_addr, 4873 uint16_t *phy_data, boolean_t read) 4874 { 4875 int32_t ret_val; 4876 uint32_t addr_reg = 0; 4877 uint32_t data_reg = 0; 4878 4879 /* This takes care of the difference with desktop vs mobile phy */ 4880 addr_reg = (hw->phy_type == em_phy_82578) ? 4881 I82578_PHY_ADDR_REG : I82577_PHY_ADDR_REG; 4882 data_reg = addr_reg + 1; 4883 4884 /* All operations in this function are phy address 2 */ 4885 hw->phy_addr = 2; 4886 4887 /* masking with 0x3F to remove the page from offset */ 4888 ret_val = em_write_phy_reg_ex(hw, addr_reg, (uint16_t)reg_addr & 0x3F); 4889 if (ret_val) { 4890 printf("Could not write PHY the HV address register\n"); 4891 goto out; 4892 } 4893 4894 /* Read or write the data value next */ 4895 if (read) 4896 ret_val = em_read_phy_reg_ex(hw, data_reg, phy_data); 4897 else 4898 ret_val = em_write_phy_reg_ex(hw, data_reg, *phy_data); 4899 4900 if (ret_val) { 4901 printf("Could not read data value from HV data register\n"); 4902 goto out; 4903 } 4904 4905 out: 4906 return ret_val; 4907 } 4908 4909 /****************************************************************************** 4910 * Reads or writes the value from a PHY register, if the value is on a specific 4911 * non zero page, sets the page first. 4912 * hw - Struct containing variables accessed by shared code 4913 * reg_addr - address of the PHY register to read 4914 *****************************************************************************/ 4915 int32_t 4916 em_access_phy_reg_hv(struct em_hw *hw, uint32_t reg_addr, uint16_t *phy_data, 4917 boolean_t read) 4918 { 4919 uint32_t ret_val; 4920 uint16_t swfw; 4921 uint16_t page = BM_PHY_REG_PAGE(reg_addr); 4922 uint16_t reg = BM_PHY_REG_NUM(reg_addr); 4923 4924 DEBUGFUNC("em_access_phy_reg_hv"); 4925 4926 swfw = E1000_SWFW_PHY0_SM; 4927 4928 if (em_swfw_sync_acquire(hw, swfw)) 4929 return -E1000_ERR_SWFW_SYNC; 4930 4931 if (page == BM_WUC_PAGE) { 4932 ret_val = em_access_phy_wakeup_reg_bm(hw, reg_addr, 4933 phy_data, read); 4934 goto release; 4935 } 4936 4937 if (page >= HV_INTC_FC_PAGE_START) 4938 hw->phy_addr = 1; 4939 else 4940 hw->phy_addr = 2; 4941 4942 if (page == HV_INTC_FC_PAGE_START) 4943 page = 0; 4944 4945 /* 4946 * Workaround MDIO accesses being disabled after entering IEEE Power 4947 * Down (whenever bit 11 of the PHY Control register is set) 4948 */ 4949 if (!read && 4950 (hw->phy_type == em_phy_82578) && 4951 (hw->phy_revision >= 1) && 4952 (hw->phy_addr == 2) && 4953 ((MAX_PHY_REG_ADDRESS & reg) == 0) && 4954 (*phy_data & (1 << 11))) { 4955 uint16_t data2 = 0x7EFF; 4956 4957 ret_val = em_access_phy_debug_regs_hv(hw, (1 << 6) | 0x3, 4958 &data2, FALSE); 4959 if (ret_val) 4960 return ret_val; 4961 } 4962 4963 if (reg_addr > MAX_PHY_MULTI_PAGE_REG) { 4964 ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 4965 (page << PHY_PAGE_SHIFT)); 4966 if (ret_val) 4967 return ret_val; 4968 } 4969 if (read) 4970 ret_val = em_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg, 4971 phy_data); 4972 else 4973 ret_val = em_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg, 4974 *phy_data); 4975 release: 4976 em_swfw_sync_release(hw, swfw); 4977 return ret_val; 4978 } 4979 4980 /****************************************************************************** 4981 * Reads the value from a PHY register, if the value is on a specific non zero 4982 * page, sets the page first. 4983 * hw - Struct containing variables accessed by shared code 4984 * reg_addr - address of the PHY register to read 4985 *****************************************************************************/ 4986 int32_t 4987 em_read_phy_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t *phy_data) 4988 { 4989 uint32_t ret_val; 4990 uint16_t swfw; 4991 DEBUGFUNC("em_read_phy_reg"); 4992 4993 if (hw->mac_type == em_pchlan || 4994 hw->mac_type == em_pch2lan || 4995 hw->mac_type == em_pch_lpt || 4996 hw->mac_type == em_pch_spt || 4997 hw->mac_type == em_pch_cnp) 4998 return (em_access_phy_reg_hv(hw, reg_addr, phy_data, TRUE)); 4999 5000 if (((hw->mac_type == em_80003es2lan) || (hw->mac_type == em_82575) || 5001 (hw->mac_type == em_82576)) && 5002 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { 5003 swfw = E1000_SWFW_PHY1_SM; 5004 } else { 5005 swfw = E1000_SWFW_PHY0_SM; 5006 } 5007 if (em_swfw_sync_acquire(hw, swfw)) 5008 return -E1000_ERR_SWFW_SYNC; 5009 5010 if ((hw->phy_type == em_phy_igp || 5011 hw->phy_type == em_phy_igp_3 || 5012 hw->phy_type == em_phy_igp_2) && 5013 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { 5014 ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 5015 (uint16_t) reg_addr); 5016 if (ret_val) { 5017 em_swfw_sync_release(hw, swfw); 5018 return ret_val; 5019 } 5020 } else if (hw->phy_type == em_phy_gg82563) { 5021 if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) || 5022 (hw->mac_type == em_80003es2lan)) { 5023 /* Select Configuration Page */ 5024 if ((reg_addr & MAX_PHY_REG_ADDRESS) < 5025 GG82563_MIN_ALT_REG) { 5026 ret_val = em_write_phy_reg_ex(hw, 5027 GG82563_PHY_PAGE_SELECT, 5028 (uint16_t) ((uint16_t) reg_addr >> 5029 GG82563_PAGE_SHIFT)); 5030 } else { 5031 /* 5032 * Use Alternative Page Select register to 5033 * access registers 30 and 31 5034 */ 5035 ret_val = em_write_phy_reg_ex(hw, 5036 GG82563_PHY_PAGE_SELECT_ALT, 5037 (uint16_t) ((uint16_t) reg_addr >> 5038 GG82563_PAGE_SHIFT)); 5039 } 5040 5041 if (ret_val) { 5042 em_swfw_sync_release(hw, swfw); 5043 return ret_val; 5044 } 5045 } 5046 } else if ((hw->phy_type == em_phy_bm) && (hw->phy_revision == 1)) { 5047 if (reg_addr > MAX_PHY_MULTI_PAGE_REG) { 5048 ret_val = em_write_phy_reg_ex(hw, BM_PHY_PAGE_SELECT, 5049 (uint16_t) ((uint16_t) reg_addr >> 5050 PHY_PAGE_SHIFT)); 5051 if (ret_val) 5052 return ret_val; 5053 } 5054 } 5055 ret_val = em_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, 5056 phy_data); 5057 5058 em_swfw_sync_release(hw, swfw); 5059 return ret_val; 5060 } 5061 5062 STATIC int32_t 5063 em_read_phy_reg_ex(struct em_hw *hw, uint32_t reg_addr, uint16_t *phy_data) 5064 { 5065 uint32_t i; 5066 uint32_t mdic = 0; 5067 DEBUGFUNC("em_read_phy_reg_ex"); 5068 5069 if (reg_addr > MAX_PHY_REG_ADDRESS) { 5070 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); 5071 return -E1000_ERR_PARAM; 5072 } 5073 if (hw->mac_type == em_icp_xxxx) { 5074 *phy_data = gcu_miibus_readreg(hw, hw->icp_xxxx_port_num, 5075 reg_addr); 5076 return E1000_SUCCESS; 5077 } 5078 if (hw->mac_type > em_82543) { 5079 /* 5080 * Set up Op-code, Phy Address, and register address in the 5081 * MDI Control register. The MAC will take care of 5082 * interfacing with the PHY to retrieve the desired data. 5083 */ 5084 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) | 5085 (hw->phy_addr << E1000_MDIC_PHY_SHIFT) | 5086 (E1000_MDIC_OP_READ)); 5087 5088 E1000_WRITE_REG(hw, MDIC, mdic); 5089 5090 /* 5091 * Poll the ready bit to see if the MDI read completed 5092 * Increasing the time out as testing showed failures with 5093 * the lower time out (from FreeBSD driver) 5094 */ 5095 for (i = 0; i < 1960; i++) { 5096 usec_delay(50); 5097 mdic = E1000_READ_REG(hw, MDIC); 5098 if (mdic & E1000_MDIC_READY) 5099 break; 5100 } 5101 if (!(mdic & E1000_MDIC_READY)) { 5102 DEBUGOUT("MDI Read did not complete\n"); 5103 return -E1000_ERR_PHY; 5104 } 5105 if (mdic & E1000_MDIC_ERROR) { 5106 DEBUGOUT("MDI Error\n"); 5107 return -E1000_ERR_PHY; 5108 } 5109 *phy_data = (uint16_t) mdic; 5110 5111 if (hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt || 5112 hw->mac_type == em_pch_spt || hw->mac_type == em_pch_cnp) 5113 usec_delay(100); 5114 } else { 5115 /* 5116 * We must first send a preamble through the MDIO pin to 5117 * signal the beginning of an MII instruction. This is done 5118 * by sending 32 consecutive "1" bits. 5119 */ 5120 em_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 5121 /* 5122 * Now combine the next few fields that are required for a 5123 * read operation. We use this method instead of calling the 5124 * em_shift_out_mdi_bits routine five different times. The 5125 * format of a MII read instruction consists of a shift out 5126 * of 14 bits and is defined as follows: <Preamble><SOF><Op 5127 * Code><Phy Addr><Reg Addr> followed by a shift in of 18 5128 * bits. This first two bits shifted in are TurnAround bits 5129 * used to avoid contention on the MDIO pin when a READ 5130 * operation is performed. These two bits are thrown away 5131 * followed by a shift in of 16 bits which contains the 5132 * desired data. 5133 */ 5134 mdic = ((reg_addr) | (hw->phy_addr << 5) | 5135 (PHY_OP_READ << 10) | (PHY_SOF << 12)); 5136 5137 em_shift_out_mdi_bits(hw, mdic, 14); 5138 /* 5139 * Now that we've shifted out the read command to the MII, we 5140 * need to "shift in" the 16-bit value (18 total bits) of the 5141 * requested PHY register address. 5142 */ 5143 *phy_data = em_shift_in_mdi_bits(hw); 5144 } 5145 return E1000_SUCCESS; 5146 } 5147 5148 /****************************************************************************** 5149 * Writes a value to a PHY register 5150 * 5151 * hw - Struct containing variables accessed by shared code 5152 * reg_addr - address of the PHY register to write 5153 * data - data to write to the PHY 5154 *****************************************************************************/ 5155 int32_t 5156 em_write_phy_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t phy_data) 5157 { 5158 uint32_t ret_val; 5159 DEBUGFUNC("em_write_phy_reg"); 5160 5161 if (hw->mac_type == em_pchlan || 5162 hw->mac_type == em_pch2lan || 5163 hw->mac_type == em_pch_lpt || 5164 hw->mac_type == em_pch_spt || 5165 hw->mac_type == em_pch_cnp) 5166 return (em_access_phy_reg_hv(hw, reg_addr, &phy_data, FALSE)); 5167 5168 if (em_swfw_sync_acquire(hw, hw->swfw)) 5169 return -E1000_ERR_SWFW_SYNC; 5170 5171 if ((hw->phy_type == em_phy_igp || 5172 hw->phy_type == em_phy_igp_3 || 5173 hw->phy_type == em_phy_igp_2) && 5174 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { 5175 ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 5176 (uint16_t) reg_addr); 5177 if (ret_val) { 5178 em_swfw_sync_release(hw, hw->swfw); 5179 return ret_val; 5180 } 5181 } else if (hw->phy_type == em_phy_gg82563) { 5182 if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) || 5183 (hw->mac_type == em_80003es2lan)) { 5184 /* Select Configuration Page */ 5185 if ((reg_addr & MAX_PHY_REG_ADDRESS) < 5186 GG82563_MIN_ALT_REG) { 5187 ret_val = em_write_phy_reg_ex(hw, 5188 GG82563_PHY_PAGE_SELECT, 5189 (uint16_t) ((uint16_t) reg_addr >> 5190 GG82563_PAGE_SHIFT)); 5191 } else { 5192 /* 5193 * Use Alternative Page Select register to 5194 * access registers 30 and 31 5195 */ 5196 ret_val = em_write_phy_reg_ex(hw, 5197 GG82563_PHY_PAGE_SELECT_ALT, 5198 (uint16_t) ((uint16_t) reg_addr >> 5199 GG82563_PAGE_SHIFT)); 5200 } 5201 5202 if (ret_val) { 5203 em_swfw_sync_release(hw, hw->swfw); 5204 return ret_val; 5205 } 5206 } 5207 } else if ((hw->phy_type == em_phy_bm) && (hw->phy_revision == 1)) { 5208 if (reg_addr > MAX_PHY_MULTI_PAGE_REG) { 5209 ret_val = em_write_phy_reg_ex(hw, BM_PHY_PAGE_SELECT, 5210 (uint16_t) ((uint16_t) reg_addr >> 5211 PHY_PAGE_SHIFT)); 5212 if (ret_val) 5213 return ret_val; 5214 } 5215 } 5216 ret_val = em_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, 5217 phy_data); 5218 5219 em_swfw_sync_release(hw, hw->swfw); 5220 return ret_val; 5221 } 5222 5223 STATIC int32_t 5224 em_write_phy_reg_ex(struct em_hw *hw, uint32_t reg_addr, uint16_t phy_data) 5225 { 5226 uint32_t i; 5227 uint32_t mdic = 0; 5228 DEBUGFUNC("em_write_phy_reg_ex"); 5229 5230 if (reg_addr > MAX_PHY_REG_ADDRESS) { 5231 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); 5232 return -E1000_ERR_PARAM; 5233 } 5234 if (hw->mac_type == em_icp_xxxx) { 5235 gcu_miibus_writereg(hw, hw->icp_xxxx_port_num, 5236 reg_addr, phy_data); 5237 return E1000_SUCCESS; 5238 } 5239 if (hw->mac_type > em_82543) { 5240 /* 5241 * Set up Op-code, Phy Address, register address, and data 5242 * intended for the PHY register in the MDI Control register. 5243 * The MAC will take care of interfacing with the PHY to send 5244 * the desired data. 5245 */ 5246 mdic = (((uint32_t) phy_data) | 5247 (reg_addr << E1000_MDIC_REG_SHIFT) | 5248 (hw->phy_addr << E1000_MDIC_PHY_SHIFT) | 5249 (E1000_MDIC_OP_WRITE)); 5250 5251 E1000_WRITE_REG(hw, MDIC, mdic); 5252 5253 /* Poll the ready bit to see if the MDI read completed */ 5254 for (i = 0; i < 641; i++) { 5255 usec_delay(5); 5256 mdic = E1000_READ_REG(hw, MDIC); 5257 if (mdic & E1000_MDIC_READY) 5258 break; 5259 } 5260 if (!(mdic & E1000_MDIC_READY)) { 5261 DEBUGOUT("MDI Write did not complete\n"); 5262 return -E1000_ERR_PHY; 5263 } 5264 5265 if (hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt || 5266 hw->mac_type == em_pch_spt || hw->mac_type == em_pch_cnp) 5267 usec_delay(100); 5268 } else { 5269 /* 5270 * We'll need to use the SW defined pins to shift the write 5271 * command out to the PHY. We first send a preamble to the 5272 * PHY to signal the beginning of the MII instruction. This 5273 * is done by sending 32 consecutive "1" bits. 5274 */ 5275 em_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 5276 /* 5277 * Now combine the remaining required fields that will 5278 * indicate a write operation. We use this method instead of 5279 * calling the em_shift_out_mdi_bits routine for each field 5280 * in the command. The format of a MII write instruction is 5281 * as follows: <Preamble><SOF><Op Code><Phy Addr><Reg 5282 * Addr><Turnaround><Data>. 5283 */ 5284 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | 5285 (hw->phy_addr << 7) | (PHY_OP_WRITE << 12) | 5286 (PHY_SOF << 14)); 5287 mdic <<= 16; 5288 mdic |= (uint32_t) phy_data; 5289 5290 em_shift_out_mdi_bits(hw, mdic, 32); 5291 } 5292 5293 return E1000_SUCCESS; 5294 } 5295 5296 STATIC int32_t 5297 em_read_kmrn_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t *data) 5298 { 5299 uint32_t reg_val; 5300 DEBUGFUNC("em_read_kmrn_reg"); 5301 5302 if (em_swfw_sync_acquire(hw, hw->swfw)) 5303 return -E1000_ERR_SWFW_SYNC; 5304 5305 /* Write register address */ 5306 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) & 5307 E1000_KUMCTRLSTA_OFFSET) | 5308 E1000_KUMCTRLSTA_REN; 5309 5310 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); 5311 usec_delay(2); 5312 5313 /* Read the data returned */ 5314 reg_val = E1000_READ_REG(hw, KUMCTRLSTA); 5315 *data = (uint16_t) reg_val; 5316 5317 em_swfw_sync_release(hw, hw->swfw); 5318 return E1000_SUCCESS; 5319 } 5320 5321 STATIC int32_t 5322 em_write_kmrn_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t data) 5323 { 5324 uint32_t reg_val; 5325 DEBUGFUNC("em_write_kmrn_reg"); 5326 5327 if (em_swfw_sync_acquire(hw, hw->swfw)) 5328 return -E1000_ERR_SWFW_SYNC; 5329 5330 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) & 5331 E1000_KUMCTRLSTA_OFFSET) | data; 5332 5333 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); 5334 usec_delay(2); 5335 5336 em_swfw_sync_release(hw, hw->swfw); 5337 return E1000_SUCCESS; 5338 } 5339 5340 /****************************************************************************** 5341 * Returns the PHY to the power-on reset state 5342 * 5343 * hw - Struct containing variables accessed by shared code 5344 *****************************************************************************/ 5345 int32_t 5346 em_phy_hw_reset(struct em_hw *hw) 5347 { 5348 uint32_t ctrl, ctrl_ext; 5349 uint32_t led_ctrl; 5350 int32_t ret_val; 5351 DEBUGFUNC("em_phy_hw_reset"); 5352 /* 5353 * In the case of the phy reset being blocked, it's not an error, we 5354 * simply return success without performing the reset. 5355 */ 5356 ret_val = em_check_phy_reset_block(hw); 5357 if (ret_val) 5358 return E1000_SUCCESS; 5359 5360 DEBUGOUT("Resetting Phy...\n"); 5361 5362 if (hw->mac_type > em_82543 && hw->mac_type != em_icp_xxxx) { 5363 if (em_swfw_sync_acquire(hw, hw->swfw)) { 5364 DEBUGOUT("Unable to acquire swfw sync\n"); 5365 return -E1000_ERR_SWFW_SYNC; 5366 } 5367 /* 5368 * Read the device control register and assert the 5369 * E1000_CTRL_PHY_RST bit. Then, take it out of reset. For 5370 * pre-em_82571 hardware, we delay for 10ms between the 5371 * assert and deassert. For em_82571 hardware and later, we 5372 * instead delay for 50us between and 10ms after the 5373 * deassertion. 5374 */ 5375 ctrl = E1000_READ_REG(hw, CTRL); 5376 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST); 5377 E1000_WRITE_FLUSH(hw); 5378 5379 if (hw->mac_type < em_82571) 5380 msec_delay(10); 5381 else 5382 usec_delay(100); 5383 5384 E1000_WRITE_REG(hw, CTRL, ctrl); 5385 E1000_WRITE_FLUSH(hw); 5386 5387 if (hw->mac_type >= em_82571) 5388 msec_delay_irq(10); 5389 em_swfw_sync_release(hw, hw->swfw); 5390 /* 5391 * the M88E1141_E_PHY_ID might need reset here, but nothing 5392 * proves it 5393 */ 5394 } else { 5395 /* 5396 * Read the Extended Device Control Register, assert the 5397 * PHY_RESET_DIR bit to put the PHY into reset. Then, take it 5398 * out of reset. 5399 */ 5400 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 5401 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; 5402 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; 5403 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 5404 E1000_WRITE_FLUSH(hw); 5405 msec_delay(10); 5406 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; 5407 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 5408 E1000_WRITE_FLUSH(hw); 5409 } 5410 usec_delay(150); 5411 5412 if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) { 5413 /* Configure activity LED after PHY reset */ 5414 led_ctrl = E1000_READ_REG(hw, LEDCTL); 5415 led_ctrl &= IGP_ACTIVITY_LED_MASK; 5416 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 5417 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 5418 } 5419 /* Wait for FW to finish PHY configuration. */ 5420 ret_val = em_get_phy_cfg_done(hw); 5421 if (ret_val != E1000_SUCCESS) 5422 return ret_val; 5423 em_release_software_semaphore(hw); 5424 5425 if ((hw->mac_type == em_ich8lan) && (hw->phy_type == em_phy_igp_3)) 5426 ret_val = em_init_lcd_from_nvm(hw); 5427 5428 return ret_val; 5429 } 5430 5431 /***************************************************************************** 5432 * SW-based LCD Configuration. 5433 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are 5434 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit 5435 * in NVM determines whether HW should configure LPLU and Gbe Disable. 5436 *****************************************************************************/ 5437 int32_t 5438 em_oem_bits_config_pchlan(struct em_hw *hw, boolean_t d0_state) 5439 { 5440 int32_t ret_val = E1000_SUCCESS; 5441 uint32_t mac_reg; 5442 uint16_t oem_reg; 5443 uint16_t swfw = E1000_SWFW_PHY0_SM; 5444 5445 if (hw->mac_type < em_pchlan) 5446 return ret_val; 5447 5448 ret_val = em_swfw_sync_acquire(hw, swfw); 5449 if (ret_val) 5450 return ret_val; 5451 5452 if (hw->mac_type == em_pchlan) { 5453 mac_reg = E1000_READ_REG(hw, EXTCNF_CTRL); 5454 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) 5455 goto out; 5456 } 5457 5458 mac_reg = E1000_READ_REG(hw, FEXTNVM); 5459 if (!(mac_reg & FEXTNVM_SW_CONFIG_ICH8M)) 5460 goto out; 5461 5462 mac_reg = E1000_READ_REG(hw, PHY_CTRL); 5463 5464 ret_val = em_read_phy_reg(hw, HV_OEM_BITS, &oem_reg); 5465 if (ret_val) 5466 goto out; 5467 5468 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU); 5469 5470 if (d0_state) { 5471 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE) 5472 oem_reg |= HV_OEM_BITS_GBE_DIS; 5473 5474 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU) 5475 oem_reg |= HV_OEM_BITS_LPLU; 5476 /* Restart auto-neg to activate the bits */ 5477 if (!em_check_phy_reset_block(hw)) 5478 oem_reg |= HV_OEM_BITS_RESTART_AN; 5479 5480 } else { 5481 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE | 5482 E1000_PHY_CTRL_NOND0A_GBE_DISABLE)) 5483 oem_reg |= HV_OEM_BITS_GBE_DIS; 5484 5485 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU | 5486 E1000_PHY_CTRL_NOND0A_LPLU)) 5487 oem_reg |= HV_OEM_BITS_LPLU; 5488 } 5489 5490 ret_val = em_write_phy_reg(hw, HV_OEM_BITS, oem_reg); 5491 5492 out: 5493 em_swfw_sync_release(hw, swfw); 5494 5495 return ret_val; 5496 } 5497 5498 5499 /****************************************************************************** 5500 * Resets the PHY 5501 * 5502 * hw - Struct containing variables accessed by shared code 5503 * 5504 * Sets bit 15 of the MII Control regiser 5505 *****************************************************************************/ 5506 int32_t 5507 em_phy_reset(struct em_hw *hw) 5508 { 5509 int32_t ret_val; 5510 uint16_t phy_data; 5511 DEBUGFUNC("em_phy_reset"); 5512 /* 5513 * In the case of the phy reset being blocked, it's not an error, we 5514 * simply return success without performing the reset. 5515 */ 5516 ret_val = em_check_phy_reset_block(hw); 5517 if (ret_val) 5518 return E1000_SUCCESS; 5519 5520 switch (hw->phy_type) { 5521 case em_phy_igp: 5522 case em_phy_igp_2: 5523 case em_phy_igp_3: 5524 case em_phy_ife: 5525 ret_val = em_phy_hw_reset(hw); 5526 if (ret_val) 5527 return ret_val; 5528 break; 5529 default: 5530 ret_val = em_read_phy_reg(hw, PHY_CTRL, &phy_data); 5531 if (ret_val) 5532 return ret_val; 5533 5534 phy_data |= MII_CR_RESET; 5535 ret_val = em_write_phy_reg(hw, PHY_CTRL, phy_data); 5536 if (ret_val) 5537 return ret_val; 5538 5539 usec_delay(1); 5540 break; 5541 } 5542 5543 /* Allow time for h/w to get to a quiescent state after reset */ 5544 msec_delay(10); 5545 5546 if (hw->phy_type == em_phy_igp || hw->phy_type == em_phy_igp_2) 5547 em_phy_init_script(hw); 5548 5549 if (hw->mac_type == em_pchlan) { 5550 ret_val = em_hv_phy_workarounds_ich8lan(hw); 5551 if (ret_val) 5552 return ret_val; 5553 } else if (hw->mac_type == em_pch2lan) { 5554 ret_val = em_lv_phy_workarounds_ich8lan(hw); 5555 if (ret_val) 5556 return ret_val; 5557 } 5558 5559 if (hw->mac_type >= em_pchlan) { 5560 ret_val = em_oem_bits_config_pchlan(hw, TRUE); 5561 if (ret_val) 5562 return ret_val; 5563 } 5564 5565 /* Ungate automatic PHY configuration on non-managed 82579 */ 5566 if ((hw->mac_type == em_pch2lan) && 5567 !(E1000_READ_REG(hw, FWSM) & E1000_FWSM_FW_VALID)) { 5568 msec_delay(10); 5569 em_gate_hw_phy_config_ich8lan(hw, FALSE); 5570 } 5571 5572 if (hw->phy_id == M88E1512_E_PHY_ID) { 5573 ret_val = em_initialize_M88E1512_phy(hw); 5574 if (ret_val) 5575 return ret_val; 5576 } 5577 5578 return E1000_SUCCESS; 5579 } 5580 5581 /****************************************************************************** 5582 * Work-around for 82566 Kumeran PCS lock loss: 5583 * On link status change (i.e. PCI reset, speed change) and link is up and 5584 * speed is gigabit- 5585 * 0) if workaround is optionally disabled do nothing 5586 * 1) wait 1ms for Kumeran link to come up 5587 * 2) check Kumeran Diagnostic register PCS lock loss bit 5588 * 3) if not set the link is locked (all is good), otherwise... 5589 * 4) reset the PHY 5590 * 5) repeat up to 10 times 5591 * Note: this is only called for IGP3 copper when speed is 1gb. 5592 * 5593 * hw - struct containing variables accessed by shared code 5594 *****************************************************************************/ 5595 STATIC int32_t 5596 em_kumeran_lock_loss_workaround(struct em_hw *hw) 5597 { 5598 int32_t ret_val; 5599 int32_t reg; 5600 int32_t cnt; 5601 uint16_t phy_data; 5602 if (hw->kmrn_lock_loss_workaround_disabled) 5603 return E1000_SUCCESS; 5604 /* 5605 * Make sure link is up before proceeding. If not just return. 5606 * Attempting this while link is negotiating fouled up link stability 5607 */ 5608 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 5609 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 5610 5611 if (phy_data & MII_SR_LINK_STATUS) { 5612 for (cnt = 0; cnt < 10; cnt++) { 5613 /* read once to clear */ 5614 ret_val = em_read_phy_reg(hw, IGP3_KMRN_DIAG, 5615 &phy_data); 5616 if (ret_val) 5617 return ret_val; 5618 /* and again to get new status */ 5619 ret_val = em_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data); 5620 if (ret_val) 5621 return ret_val; 5622 5623 /* check for PCS lock */ 5624 if (!(phy_data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) 5625 return E1000_SUCCESS; 5626 5627 /* Issue PHY reset */ 5628 em_phy_hw_reset(hw); 5629 msec_delay_irq(5); 5630 } 5631 /* Disable GigE link negotiation */ 5632 reg = E1000_READ_REG(hw, PHY_CTRL); 5633 E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE 5634 | E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 5635 5636 /* unable to acquire PCS lock */ 5637 return E1000_ERR_PHY; 5638 } 5639 return E1000_SUCCESS; 5640 } 5641 5642 /****************************************************************************** 5643 * Reads and matches the expected PHY address for known PHY IDs 5644 * 5645 * hw - Struct containing variables accessed by shared code 5646 *****************************************************************************/ 5647 STATIC int32_t 5648 em_match_gig_phy(struct em_hw *hw) 5649 { 5650 int32_t phy_init_status, ret_val; 5651 uint16_t phy_id_high, phy_id_low; 5652 boolean_t match = FALSE; 5653 DEBUGFUNC("em_match_gig_phy"); 5654 5655 ret_val = em_read_phy_reg(hw, PHY_ID1, &phy_id_high); 5656 if (ret_val) 5657 return ret_val; 5658 5659 hw->phy_id = (uint32_t) (phy_id_high << 16); 5660 usec_delay(20); 5661 ret_val = em_read_phy_reg(hw, PHY_ID2, &phy_id_low); 5662 if (ret_val) 5663 return ret_val; 5664 5665 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK); 5666 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK; 5667 5668 switch (hw->mac_type) { 5669 case em_82543: 5670 if (hw->phy_id == M88E1000_E_PHY_ID) 5671 match = TRUE; 5672 break; 5673 case em_82544: 5674 if (hw->phy_id == M88E1000_I_PHY_ID) 5675 match = TRUE; 5676 break; 5677 case em_82540: 5678 case em_82545: 5679 case em_82545_rev_3: 5680 case em_82546: 5681 case em_82546_rev_3: 5682 if (hw->phy_id == M88E1011_I_PHY_ID) 5683 match = TRUE; 5684 break; 5685 case em_82541: 5686 case em_82541_rev_2: 5687 case em_82547: 5688 case em_82547_rev_2: 5689 if (hw->phy_id == IGP01E1000_I_PHY_ID) 5690 match = TRUE; 5691 break; 5692 case em_82573: 5693 if (hw->phy_id == M88E1111_I_PHY_ID) 5694 match = TRUE; 5695 break; 5696 case em_82574: 5697 if (hw->phy_id == BME1000_E_PHY_ID) 5698 match = TRUE; 5699 break; 5700 case em_82575: 5701 case em_82576: 5702 if (hw->phy_id == M88E1000_E_PHY_ID) 5703 match = TRUE; 5704 if (hw->phy_id == IGP01E1000_I_PHY_ID) 5705 match = TRUE; 5706 if (hw->phy_id == IGP03E1000_E_PHY_ID) 5707 match = TRUE; 5708 break; 5709 case em_82580: 5710 case em_i210: 5711 case em_i350: 5712 if (hw->phy_id == I82580_I_PHY_ID || 5713 hw->phy_id == I210_I_PHY_ID || 5714 hw->phy_id == I347AT4_E_PHY_ID || 5715 hw->phy_id == I350_I_PHY_ID || 5716 hw->phy_id == M88E1112_E_PHY_ID || 5717 hw->phy_id == M88E1543_E_PHY_ID || 5718 hw->phy_id == M88E1512_E_PHY_ID) { 5719 uint32_t mdic; 5720 5721 mdic = EM_READ_REG(hw, E1000_MDICNFG); 5722 mdic &= E1000_MDICNFG_PHY_MASK; 5723 hw->phy_addr = mdic >> E1000_MDICNFG_PHY_SHIFT; 5724 DEBUGOUT1("MDICNFG PHY ADDR %d", 5725 mdic >> E1000_MDICNFG_PHY_SHIFT); 5726 match = TRUE; 5727 } 5728 break; 5729 case em_80003es2lan: 5730 if (hw->phy_id == GG82563_E_PHY_ID) 5731 match = TRUE; 5732 break; 5733 case em_ich8lan: 5734 case em_ich9lan: 5735 case em_ich10lan: 5736 case em_pchlan: 5737 case em_pch2lan: 5738 if (hw->phy_id == IGP03E1000_E_PHY_ID) 5739 match = TRUE; 5740 if (hw->phy_id == IFE_E_PHY_ID) 5741 match = TRUE; 5742 if (hw->phy_id == IFE_PLUS_E_PHY_ID) 5743 match = TRUE; 5744 if (hw->phy_id == IFE_C_E_PHY_ID) 5745 match = TRUE; 5746 if (hw->phy_id == BME1000_E_PHY_ID) 5747 match = TRUE; 5748 if (hw->phy_id == I82577_E_PHY_ID) 5749 match = TRUE; 5750 if (hw->phy_id == I82578_E_PHY_ID) 5751 match = TRUE; 5752 if (hw->phy_id == I82579_E_PHY_ID) 5753 match = TRUE; 5754 break; 5755 case em_pch_lpt: 5756 case em_pch_spt: 5757 case em_pch_cnp: 5758 if (hw->phy_id == I217_E_PHY_ID) 5759 match = TRUE; 5760 break; 5761 case em_icp_xxxx: 5762 if (hw->phy_id == M88E1141_E_PHY_ID) 5763 match = TRUE; 5764 if (hw->phy_id == RTL8211_E_PHY_ID) 5765 match = TRUE; 5766 break; 5767 default: 5768 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type); 5769 return -E1000_ERR_CONFIG; 5770 } 5771 phy_init_status = em_set_phy_type(hw); 5772 5773 if ((match) && (phy_init_status == E1000_SUCCESS)) { 5774 DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id); 5775 return E1000_SUCCESS; 5776 } 5777 DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id); 5778 return -E1000_ERR_PHY; 5779 } 5780 5781 /****************************************************************************** 5782 * Probes the expected PHY address for known PHY IDs 5783 * 5784 * hw - Struct containing variables accessed by shared code 5785 *****************************************************************************/ 5786 STATIC int32_t 5787 em_detect_gig_phy(struct em_hw *hw) 5788 { 5789 int32_t ret_val, i; 5790 DEBUGFUNC("em_detect_gig_phy"); 5791 5792 if (hw->phy_id != 0) 5793 return E1000_SUCCESS; 5794 5795 /* default phy address, most phys reside here, but not all (ICH10) */ 5796 if (hw->mac_type != em_icp_xxxx) 5797 hw->phy_addr = 1; 5798 else 5799 hw->phy_addr = 0; /* There is a phy at phy_addr 0 on EP80579 */ 5800 5801 /* 5802 * The 82571 firmware may still be configuring the PHY. In this 5803 * case, we cannot access the PHY until the configuration is done. 5804 * So we explicitly set the PHY values. 5805 */ 5806 if (hw->mac_type == em_82571 || 5807 hw->mac_type == em_82572) { 5808 hw->phy_id = IGP01E1000_I_PHY_ID; 5809 hw->phy_type = em_phy_igp_2; 5810 return E1000_SUCCESS; 5811 } 5812 5813 /* 5814 * Some of the fiber cards dont have a phy, so we must exit cleanly 5815 * here 5816 */ 5817 if ((hw->media_type == em_media_type_fiber) && 5818 (hw->mac_type == em_82542_rev2_0 || 5819 hw->mac_type == em_82542_rev2_1 || 5820 hw->mac_type == em_82543 || 5821 hw->mac_type == em_82573 || 5822 hw->mac_type == em_82574 || 5823 hw->mac_type == em_80003es2lan)) { 5824 hw->phy_type = em_phy_undefined; 5825 return E1000_SUCCESS; 5826 } 5827 5828 if ((hw->media_type == em_media_type_internal_serdes || 5829 hw->media_type == em_media_type_fiber) && 5830 hw->mac_type >= em_82575) { 5831 hw->phy_type = em_phy_undefined; 5832 return E1000_SUCCESS; 5833 } 5834 5835 /* 5836 * Up to 82543 (incl), we need reset the phy, or it might not get 5837 * detected 5838 */ 5839 if (hw->mac_type <= em_82543) { 5840 ret_val = em_phy_hw_reset(hw); 5841 if (ret_val) 5842 return ret_val; 5843 } 5844 /* 5845 * ESB-2 PHY reads require em_phy_gg82563 to be set because of a 5846 * work- around that forces PHY page 0 to be set or the reads fail. 5847 * The rest of the code in this routine uses em_read_phy_reg to read 5848 * the PHY ID. So for ESB-2 we need to have this set so our reads 5849 * won't fail. If the attached PHY is not a em_phy_gg82563, the 5850 * routines below will figure this out as well. 5851 */ 5852 if (hw->mac_type == em_80003es2lan) 5853 hw->phy_type = em_phy_gg82563; 5854 5855 /* Power on SGMII phy if it is disabled */ 5856 if (hw->mac_type == em_82580 || hw->mac_type == em_i210 || 5857 hw->mac_type == em_i350) { 5858 uint32_t ctrl_ext = EM_READ_REG(hw, E1000_CTRL_EXT); 5859 EM_WRITE_REG(hw, E1000_CTRL_EXT, 5860 ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA); 5861 delay(300); 5862 } 5863 5864 /* Read the PHY ID Registers to identify which PHY is onboard. */ 5865 for (i = 1; i < 4; i++) { 5866 /* 5867 * hw->phy_addr may be modified down in the call stack, 5868 * we can't use it as loop variable. 5869 */ 5870 hw->phy_addr = i; 5871 ret_val = em_match_gig_phy(hw); 5872 if (ret_val == E1000_SUCCESS) 5873 return E1000_SUCCESS; 5874 } 5875 return -E1000_ERR_PHY; 5876 } 5877 5878 /****************************************************************************** 5879 * Resets the PHY's DSP 5880 * 5881 * hw - Struct containing variables accessed by shared code 5882 *****************************************************************************/ 5883 static int32_t 5884 em_phy_reset_dsp(struct em_hw *hw) 5885 { 5886 int32_t ret_val; 5887 DEBUGFUNC("em_phy_reset_dsp"); 5888 5889 do { 5890 if (hw->phy_type != em_phy_gg82563) { 5891 ret_val = em_write_phy_reg(hw, 29, 0x001d); 5892 if (ret_val) 5893 break; 5894 } 5895 ret_val = em_write_phy_reg(hw, 30, 0x00c1); 5896 if (ret_val) 5897 break; 5898 ret_val = em_write_phy_reg(hw, 30, 0x0000); 5899 if (ret_val) 5900 break; 5901 ret_val = E1000_SUCCESS; 5902 } while (0); 5903 5904 return ret_val; 5905 } 5906 5907 /****************************************************************************** 5908 * Sets up eeprom variables in the hw struct. Must be called after mac_type 5909 * is configured. Additionally, if this is ICH8, the flash controller GbE 5910 * registers must be mapped, or this will crash. 5911 * 5912 * hw - Struct containing variables accessed by shared code 5913 *****************************************************************************/ 5914 int32_t 5915 em_init_eeprom_params(struct em_hw *hw) 5916 { 5917 struct em_eeprom_info *eeprom = &hw->eeprom; 5918 uint32_t eecd = E1000_READ_REG(hw, EECD); 5919 int32_t ret_val = E1000_SUCCESS; 5920 uint16_t eeprom_size; 5921 DEBUGFUNC("em_init_eeprom_params"); 5922 5923 switch (hw->mac_type) { 5924 case em_82542_rev2_0: 5925 case em_82542_rev2_1: 5926 case em_82543: 5927 case em_82544: 5928 eeprom->type = em_eeprom_microwire; 5929 eeprom->word_size = 64; 5930 eeprom->opcode_bits = 3; 5931 eeprom->address_bits = 6; 5932 eeprom->delay_usec = 50; 5933 eeprom->use_eerd = FALSE; 5934 eeprom->use_eewr = FALSE; 5935 break; 5936 case em_82540: 5937 case em_82545: 5938 case em_82545_rev_3: 5939 case em_icp_xxxx: 5940 case em_82546: 5941 case em_82546_rev_3: 5942 eeprom->type = em_eeprom_microwire; 5943 eeprom->opcode_bits = 3; 5944 eeprom->delay_usec = 50; 5945 if (eecd & E1000_EECD_SIZE) { 5946 eeprom->word_size = 256; 5947 eeprom->address_bits = 8; 5948 } else { 5949 eeprom->word_size = 64; 5950 eeprom->address_bits = 6; 5951 } 5952 eeprom->use_eerd = FALSE; 5953 eeprom->use_eewr = FALSE; 5954 break; 5955 case em_82541: 5956 case em_82541_rev_2: 5957 case em_82547: 5958 case em_82547_rev_2: 5959 if (eecd & E1000_EECD_TYPE) { 5960 eeprom->type = em_eeprom_spi; 5961 eeprom->opcode_bits = 8; 5962 eeprom->delay_usec = 1; 5963 if (eecd & E1000_EECD_ADDR_BITS) { 5964 eeprom->page_size = 32; 5965 eeprom->address_bits = 16; 5966 } else { 5967 eeprom->page_size = 8; 5968 eeprom->address_bits = 8; 5969 } 5970 } else { 5971 eeprom->type = em_eeprom_microwire; 5972 eeprom->opcode_bits = 3; 5973 eeprom->delay_usec = 50; 5974 if (eecd & E1000_EECD_ADDR_BITS) { 5975 eeprom->word_size = 256; 5976 eeprom->address_bits = 8; 5977 } else { 5978 eeprom->word_size = 64; 5979 eeprom->address_bits = 6; 5980 } 5981 } 5982 eeprom->use_eerd = FALSE; 5983 eeprom->use_eewr = FALSE; 5984 break; 5985 case em_82571: 5986 case em_82572: 5987 eeprom->type = em_eeprom_spi; 5988 eeprom->opcode_bits = 8; 5989 eeprom->delay_usec = 1; 5990 if (eecd & E1000_EECD_ADDR_BITS) { 5991 eeprom->page_size = 32; 5992 eeprom->address_bits = 16; 5993 } else { 5994 eeprom->page_size = 8; 5995 eeprom->address_bits = 8; 5996 } 5997 eeprom->use_eerd = FALSE; 5998 eeprom->use_eewr = FALSE; 5999 break; 6000 case em_82573: 6001 case em_82574: 6002 case em_82575: 6003 case em_82576: 6004 case em_82580: 6005 case em_i210: 6006 case em_i350: 6007 eeprom->type = em_eeprom_spi; 6008 eeprom->opcode_bits = 8; 6009 eeprom->delay_usec = 1; 6010 if (eecd & E1000_EECD_ADDR_BITS) { 6011 eeprom->page_size = 32; 6012 eeprom->address_bits = 16; 6013 } else { 6014 eeprom->page_size = 8; 6015 eeprom->address_bits = 8; 6016 } 6017 eeprom->use_eerd = TRUE; 6018 eeprom->use_eewr = TRUE; 6019 if (em_is_onboard_nvm_eeprom(hw) == FALSE) { 6020 eeprom->type = em_eeprom_flash; 6021 eeprom->word_size = 2048; 6022 /* 6023 * Ensure that the Autonomous FLASH update bit is 6024 * cleared due to Flash update issue on parts which 6025 * use a FLASH for NVM. 6026 */ 6027 eecd &= ~E1000_EECD_AUPDEN; 6028 E1000_WRITE_REG(hw, EECD, eecd); 6029 } 6030 if (em_get_flash_presence_i210(hw) == FALSE) { 6031 eeprom->type = em_eeprom_invm; 6032 eeprom->word_size = INVM_SIZE; 6033 eeprom->use_eerd = FALSE; 6034 eeprom->use_eewr = FALSE; 6035 } 6036 break; 6037 case em_80003es2lan: 6038 eeprom->type = em_eeprom_spi; 6039 eeprom->opcode_bits = 8; 6040 eeprom->delay_usec = 1; 6041 if (eecd & E1000_EECD_ADDR_BITS) { 6042 eeprom->page_size = 32; 6043 eeprom->address_bits = 16; 6044 } else { 6045 eeprom->page_size = 8; 6046 eeprom->address_bits = 8; 6047 } 6048 eeprom->use_eerd = TRUE; 6049 eeprom->use_eewr = FALSE; 6050 break; 6051 case em_ich8lan: 6052 case em_ich9lan: 6053 case em_ich10lan: 6054 case em_pchlan: 6055 case em_pch2lan: 6056 case em_pch_lpt: 6057 { 6058 int32_t i = 0; 6059 uint32_t flash_size = 6060 E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_GFPREG); 6061 eeprom->type = em_eeprom_ich8; 6062 eeprom->use_eerd = FALSE; 6063 eeprom->use_eewr = FALSE; 6064 eeprom->word_size = E1000_SHADOW_RAM_WORDS; 6065 /* 6066 * Zero the shadow RAM structure. But don't load it 6067 * from NVM so as to save time for driver init 6068 */ 6069 if (hw->eeprom_shadow_ram != NULL) { 6070 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 6071 hw->eeprom_shadow_ram[i].modified = 6072 FALSE; 6073 hw->eeprom_shadow_ram[i].eeprom_word = 6074 0xFFFF; 6075 } 6076 } 6077 hw->flash_base_addr = (flash_size & 6078 ICH_GFPREG_BASE_MASK) * ICH_FLASH_SECTOR_SIZE; 6079 6080 hw->flash_bank_size = ((flash_size >> 16) & 6081 ICH_GFPREG_BASE_MASK) + 1; 6082 hw->flash_bank_size -= (flash_size & 6083 ICH_GFPREG_BASE_MASK); 6084 6085 hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE; 6086 6087 hw->flash_bank_size /= 2 * sizeof(uint16_t); 6088 6089 break; 6090 } 6091 case em_pch_spt: 6092 case em_pch_cnp: 6093 { 6094 int32_t i = 0; 6095 uint32_t flash_size = EM_READ_REG(hw, 0xc /* STRAP */); 6096 6097 eeprom->type = em_eeprom_ich8; 6098 eeprom->use_eerd = FALSE; 6099 eeprom->use_eewr = FALSE; 6100 eeprom->word_size = E1000_SHADOW_RAM_WORDS; 6101 /* 6102 * Zero the shadow RAM structure. But don't load it 6103 * from NVM so as to save time for driver init 6104 */ 6105 if (hw->eeprom_shadow_ram != NULL) { 6106 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 6107 hw->eeprom_shadow_ram[i].modified = 6108 FALSE; 6109 hw->eeprom_shadow_ram[i].eeprom_word = 6110 0xFFFF; 6111 } 6112 } 6113 hw->flash_base_addr = 0; 6114 flash_size = ((flash_size >> 1) & 0x1f) + 1; 6115 flash_size *= 4096; 6116 hw->flash_bank_size = flash_size / 4; 6117 } 6118 break; 6119 default: 6120 break; 6121 } 6122 6123 if (eeprom->type == em_eeprom_spi) { 6124 /* 6125 * eeprom_size will be an enum [0..8] that maps to eeprom 6126 * sizes 128B to 32KB (incremented by powers of 2). 6127 */ 6128 if (hw->mac_type <= em_82547_rev_2) { 6129 /* Set to default value for initial eeprom read. */ 6130 eeprom->word_size = 64; 6131 ret_val = em_read_eeprom(hw, EEPROM_CFG, 1, 6132 &eeprom_size); 6133 if (ret_val) 6134 return ret_val; 6135 eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> 6136 EEPROM_SIZE_SHIFT; 6137 /* 6138 * 256B eeprom size was not supported in earlier 6139 * hardware, so we bump eeprom_size up one to ensure 6140 * that "1" (which maps to 256B) is never the result 6141 * used in the shifting logic below. 6142 */ 6143 if (eeprom_size) 6144 eeprom_size++; 6145 } else { 6146 eeprom_size = (uint16_t) ( 6147 (eecd & E1000_EECD_SIZE_EX_MASK) >> 6148 E1000_EECD_SIZE_EX_SHIFT); 6149 } 6150 6151 /* EEPROM access above 16k is unsupported */ 6152 if (eeprom_size + EEPROM_WORD_SIZE_SHIFT > 6153 EEPROM_WORD_SIZE_SHIFT_MAX) { 6154 eeprom->word_size = 1 << EEPROM_WORD_SIZE_SHIFT_MAX; 6155 } else { 6156 eeprom->word_size = 1 << 6157 (eeprom_size + EEPROM_WORD_SIZE_SHIFT); 6158 } 6159 } 6160 return ret_val; 6161 } 6162 6163 /****************************************************************************** 6164 * Raises the EEPROM's clock input. 6165 * 6166 * hw - Struct containing variables accessed by shared code 6167 * eecd - EECD's current value 6168 *****************************************************************************/ 6169 static void 6170 em_raise_ee_clk(struct em_hw *hw, uint32_t *eecd) 6171 { 6172 /* 6173 * Raise the clock input to the EEPROM (by setting the SK bit), and 6174 * then wait <delay> microseconds. 6175 */ 6176 *eecd = *eecd | E1000_EECD_SK; 6177 E1000_WRITE_REG(hw, EECD, *eecd); 6178 E1000_WRITE_FLUSH(hw); 6179 usec_delay(hw->eeprom.delay_usec); 6180 } 6181 6182 /****************************************************************************** 6183 * Lowers the EEPROM's clock input. 6184 * 6185 * hw - Struct containing variables accessed by shared code 6186 * eecd - EECD's current value 6187 *****************************************************************************/ 6188 static void 6189 em_lower_ee_clk(struct em_hw *hw, uint32_t *eecd) 6190 { 6191 /* 6192 * Lower the clock input to the EEPROM (by clearing the SK bit), and 6193 * then wait 50 microseconds. 6194 */ 6195 *eecd = *eecd & ~E1000_EECD_SK; 6196 E1000_WRITE_REG(hw, EECD, *eecd); 6197 E1000_WRITE_FLUSH(hw); 6198 usec_delay(hw->eeprom.delay_usec); 6199 } 6200 6201 /****************************************************************************** 6202 * Shift data bits out to the EEPROM. 6203 * 6204 * hw - Struct containing variables accessed by shared code 6205 * data - data to send to the EEPROM 6206 * count - number of bits to shift out 6207 *****************************************************************************/ 6208 static void 6209 em_shift_out_ee_bits(struct em_hw *hw, uint16_t data, uint16_t count) 6210 { 6211 struct em_eeprom_info *eeprom = &hw->eeprom; 6212 uint32_t eecd; 6213 uint32_t mask; 6214 /* 6215 * We need to shift "count" bits out to the EEPROM. So, value in the 6216 * "data" parameter will be shifted out to the EEPROM one bit at a 6217 * time. In order to do this, "data" must be broken down into bits. 6218 */ 6219 mask = 0x01 << (count - 1); 6220 eecd = E1000_READ_REG(hw, EECD); 6221 if (eeprom->type == em_eeprom_microwire) { 6222 eecd &= ~E1000_EECD_DO; 6223 } else if (eeprom->type == em_eeprom_spi) { 6224 eecd |= E1000_EECD_DO; 6225 } 6226 do { 6227 /* 6228 * A "1" is shifted out to the EEPROM by setting bit "DI" to 6229 * a "1", and then raising and then lowering the clock (the 6230 * SK bit controls the clock input to the EEPROM). A "0" is 6231 * shifted out to the EEPROM by setting "DI" to "0" and then 6232 * raising and then lowering the clock. 6233 */ 6234 eecd &= ~E1000_EECD_DI; 6235 6236 if (data & mask) 6237 eecd |= E1000_EECD_DI; 6238 6239 E1000_WRITE_REG(hw, EECD, eecd); 6240 E1000_WRITE_FLUSH(hw); 6241 6242 usec_delay(eeprom->delay_usec); 6243 6244 em_raise_ee_clk(hw, &eecd); 6245 em_lower_ee_clk(hw, &eecd); 6246 6247 mask = mask >> 1; 6248 6249 } while (mask); 6250 6251 /* We leave the "DI" bit set to "0" when we leave this routine. */ 6252 eecd &= ~E1000_EECD_DI; 6253 E1000_WRITE_REG(hw, EECD, eecd); 6254 } 6255 6256 /****************************************************************************** 6257 * Shift data bits in from the EEPROM 6258 * 6259 * hw - Struct containing variables accessed by shared code 6260 *****************************************************************************/ 6261 static uint16_t 6262 em_shift_in_ee_bits(struct em_hw *hw, uint16_t count) 6263 { 6264 uint32_t eecd; 6265 uint32_t i; 6266 uint16_t data; 6267 /* 6268 * In order to read a register from the EEPROM, we need to shift 6269 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising 6270 * the clock input to the EEPROM (setting the SK bit), and then 6271 * reading the value of the "DO" bit. During this "shifting in" 6272 * process the "DI" bit should always be clear. 6273 */ 6274 6275 eecd = E1000_READ_REG(hw, EECD); 6276 6277 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 6278 data = 0; 6279 6280 for (i = 0; i < count; i++) { 6281 data = data << 1; 6282 em_raise_ee_clk(hw, &eecd); 6283 6284 eecd = E1000_READ_REG(hw, EECD); 6285 6286 eecd &= ~(E1000_EECD_DI); 6287 if (eecd & E1000_EECD_DO) 6288 data |= 1; 6289 6290 em_lower_ee_clk(hw, &eecd); 6291 } 6292 6293 return data; 6294 } 6295 /****************************************************************************** 6296 * Prepares EEPROM for access 6297 * 6298 * hw - Struct containing variables accessed by shared code 6299 * 6300 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This 6301 * function should be called before issuing a command to the EEPROM. 6302 *****************************************************************************/ 6303 static int32_t 6304 em_acquire_eeprom(struct em_hw *hw) 6305 { 6306 struct em_eeprom_info *eeprom = &hw->eeprom; 6307 uint32_t eecd, i = 0; 6308 DEBUGFUNC("em_acquire_eeprom"); 6309 6310 if (em_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM)) 6311 return -E1000_ERR_SWFW_SYNC; 6312 eecd = E1000_READ_REG(hw, EECD); 6313 6314 if ((hw->mac_type != em_82573) && (hw->mac_type != em_82574)) { 6315 /* Request EEPROM Access */ 6316 if (hw->mac_type > em_82544) { 6317 eecd |= E1000_EECD_REQ; 6318 E1000_WRITE_REG(hw, EECD, eecd); 6319 eecd = E1000_READ_REG(hw, EECD); 6320 while ((!(eecd & E1000_EECD_GNT)) && 6321 (i < E1000_EEPROM_GRANT_ATTEMPTS)) { 6322 i++; 6323 usec_delay(5); 6324 eecd = E1000_READ_REG(hw, EECD); 6325 } 6326 if (!(eecd & E1000_EECD_GNT)) { 6327 eecd &= ~E1000_EECD_REQ; 6328 E1000_WRITE_REG(hw, EECD, eecd); 6329 DEBUGOUT("Could not acquire EEPROM grant\n"); 6330 em_swfw_sync_release(hw, E1000_SWFW_EEP_SM); 6331 return -E1000_ERR_EEPROM; 6332 } 6333 } 6334 } 6335 6336 /* Setup EEPROM for Read/Write */ 6337 if (eeprom->type == em_eeprom_microwire) { 6338 /* Clear SK and DI */ 6339 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK); 6340 E1000_WRITE_REG(hw, EECD, eecd); 6341 6342 /* Set CS */ 6343 eecd |= E1000_EECD_CS; 6344 E1000_WRITE_REG(hw, EECD, eecd); 6345 } else if (eeprom->type == em_eeprom_spi) { 6346 /* Clear SK and CS */ 6347 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 6348 E1000_WRITE_REG(hw, EECD, eecd); 6349 usec_delay(1); 6350 } 6351 return E1000_SUCCESS; 6352 } 6353 6354 /****************************************************************************** 6355 * Returns EEPROM to a "standby" state 6356 * 6357 * hw - Struct containing variables accessed by shared code 6358 *****************************************************************************/ 6359 static void 6360 em_standby_eeprom(struct em_hw *hw) 6361 { 6362 struct em_eeprom_info *eeprom = &hw->eeprom; 6363 uint32_t eecd; 6364 eecd = E1000_READ_REG(hw, EECD); 6365 6366 if (eeprom->type == em_eeprom_microwire) { 6367 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 6368 E1000_WRITE_REG(hw, EECD, eecd); 6369 E1000_WRITE_FLUSH(hw); 6370 usec_delay(eeprom->delay_usec); 6371 6372 /* Clock high */ 6373 eecd |= E1000_EECD_SK; 6374 E1000_WRITE_REG(hw, EECD, eecd); 6375 E1000_WRITE_FLUSH(hw); 6376 usec_delay(eeprom->delay_usec); 6377 6378 /* Select EEPROM */ 6379 eecd |= E1000_EECD_CS; 6380 E1000_WRITE_REG(hw, EECD, eecd); 6381 E1000_WRITE_FLUSH(hw); 6382 usec_delay(eeprom->delay_usec); 6383 6384 /* Clock low */ 6385 eecd &= ~E1000_EECD_SK; 6386 E1000_WRITE_REG(hw, EECD, eecd); 6387 E1000_WRITE_FLUSH(hw); 6388 usec_delay(eeprom->delay_usec); 6389 } else if (eeprom->type == em_eeprom_spi) { 6390 /* Toggle CS to flush commands */ 6391 eecd |= E1000_EECD_CS; 6392 E1000_WRITE_REG(hw, EECD, eecd); 6393 E1000_WRITE_FLUSH(hw); 6394 usec_delay(eeprom->delay_usec); 6395 eecd &= ~E1000_EECD_CS; 6396 E1000_WRITE_REG(hw, EECD, eecd); 6397 E1000_WRITE_FLUSH(hw); 6398 usec_delay(eeprom->delay_usec); 6399 } 6400 } 6401 6402 /****************************************************************************** 6403 * Terminates a command by inverting the EEPROM's chip select pin 6404 * 6405 * hw - Struct containing variables accessed by shared code 6406 *****************************************************************************/ 6407 static void 6408 em_release_eeprom(struct em_hw *hw) 6409 { 6410 uint32_t eecd; 6411 DEBUGFUNC("em_release_eeprom"); 6412 6413 eecd = E1000_READ_REG(hw, EECD); 6414 6415 if (hw->eeprom.type == em_eeprom_spi) { 6416 eecd |= E1000_EECD_CS; /* Pull CS high */ 6417 eecd &= ~E1000_EECD_SK; /* Lower SCK */ 6418 6419 E1000_WRITE_REG(hw, EECD, eecd); 6420 6421 usec_delay(hw->eeprom.delay_usec); 6422 } else if (hw->eeprom.type == em_eeprom_microwire) { 6423 /* cleanup eeprom */ 6424 6425 /* CS on Microwire is active-high */ 6426 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); 6427 6428 E1000_WRITE_REG(hw, EECD, eecd); 6429 6430 /* Rising edge of clock */ 6431 eecd |= E1000_EECD_SK; 6432 E1000_WRITE_REG(hw, EECD, eecd); 6433 E1000_WRITE_FLUSH(hw); 6434 usec_delay(hw->eeprom.delay_usec); 6435 6436 /* Falling edge of clock */ 6437 eecd &= ~E1000_EECD_SK; 6438 E1000_WRITE_REG(hw, EECD, eecd); 6439 E1000_WRITE_FLUSH(hw); 6440 usec_delay(hw->eeprom.delay_usec); 6441 } 6442 /* Stop requesting EEPROM access */ 6443 if (hw->mac_type > em_82544) { 6444 eecd &= ~E1000_EECD_REQ; 6445 E1000_WRITE_REG(hw, EECD, eecd); 6446 } 6447 em_swfw_sync_release(hw, E1000_SWFW_EEP_SM); 6448 } 6449 6450 /****************************************************************************** 6451 * Reads a 16 bit word from the EEPROM. 6452 * 6453 * hw - Struct containing variables accessed by shared code 6454 *****************************************************************************/ 6455 STATIC int32_t 6456 em_spi_eeprom_ready(struct em_hw *hw) 6457 { 6458 uint16_t retry_count = 0; 6459 uint8_t spi_stat_reg; 6460 DEBUGFUNC("em_spi_eeprom_ready"); 6461 /* 6462 * Read "Status Register" repeatedly until the LSB is cleared. The 6463 * EEPROM will signal that the command has been completed by clearing 6464 * bit 0 of the internal status register. If it's not cleared within 6465 * 5 milliseconds, then error out. 6466 */ 6467 retry_count = 0; 6468 do { 6469 em_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI, 6470 hw->eeprom.opcode_bits); 6471 spi_stat_reg = (uint8_t) em_shift_in_ee_bits(hw, 8); 6472 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI)) 6473 break; 6474 6475 usec_delay(5); 6476 retry_count += 5; 6477 6478 em_standby_eeprom(hw); 6479 } while (retry_count < EEPROM_MAX_RETRY_SPI); 6480 /* 6481 * ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and 6482 * only 0-5mSec on 5V devices) 6483 */ 6484 if (retry_count >= EEPROM_MAX_RETRY_SPI) { 6485 DEBUGOUT("SPI EEPROM Status error\n"); 6486 return -E1000_ERR_EEPROM; 6487 } 6488 return E1000_SUCCESS; 6489 } 6490 6491 /****************************************************************************** 6492 * Reads a 16 bit word from the EEPROM. 6493 * 6494 * hw - Struct containing variables accessed by shared code 6495 * offset - offset of word in the EEPROM to read 6496 * data - word read from the EEPROM 6497 * words - number of words to read 6498 *****************************************************************************/ 6499 int32_t 6500 em_read_eeprom(struct em_hw *hw, uint16_t offset, uint16_t words, 6501 uint16_t *data) 6502 { 6503 struct em_eeprom_info *eeprom = &hw->eeprom; 6504 uint32_t i = 0; 6505 DEBUGFUNC("em_read_eeprom"); 6506 6507 /* If eeprom is not yet detected, do so now */ 6508 if (eeprom->word_size == 0) 6509 em_init_eeprom_params(hw); 6510 /* 6511 * A check for invalid values: offset too large, too many words, and 6512 * not enough words. 6513 */ 6514 if ((offset >= eeprom->word_size) || 6515 (words > eeprom->word_size - offset) || 6516 (words == 0)) { 6517 DEBUGOUT2("\"words\" parameter out of bounds. Words = %d," 6518 " size = %d\n", offset, eeprom->word_size); 6519 return -E1000_ERR_EEPROM; 6520 } 6521 /* 6522 * EEPROM's that don't use EERD to read require us to bit-bang the 6523 * SPI directly. In this case, we need to acquire the EEPROM so that 6524 * FW or other port software does not interrupt. 6525 */ 6526 if (em_is_onboard_nvm_eeprom(hw) == TRUE && 6527 em_get_flash_presence_i210(hw) == TRUE && 6528 hw->eeprom.use_eerd == FALSE) { 6529 /* Prepare the EEPROM for bit-bang reading */ 6530 if (em_acquire_eeprom(hw) != E1000_SUCCESS) 6531 return -E1000_ERR_EEPROM; 6532 } 6533 /* Eerd register EEPROM access requires no eeprom aquire/release */ 6534 if (eeprom->use_eerd == TRUE) 6535 return em_read_eeprom_eerd(hw, offset, words, data); 6536 6537 /* ICH EEPROM access is done via the ICH flash controller */ 6538 if (eeprom->type == em_eeprom_ich8) 6539 return em_read_eeprom_ich8(hw, offset, words, data); 6540 6541 /* Some i210/i211 have a special OTP chip */ 6542 if (eeprom->type == em_eeprom_invm) 6543 return em_read_invm_i210(hw, offset, words, data); 6544 6545 /* 6546 * Set up the SPI or Microwire EEPROM for bit-bang reading. We have 6547 * acquired the EEPROM at this point, so any returns should relase it 6548 */ 6549 if (eeprom->type == em_eeprom_spi) { 6550 uint16_t word_in; 6551 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI; 6552 if (em_spi_eeprom_ready(hw)) { 6553 em_release_eeprom(hw); 6554 return -E1000_ERR_EEPROM; 6555 } 6556 em_standby_eeprom(hw); 6557 /* 6558 * Some SPI eeproms use the 8th address bit embedded in the 6559 * opcode 6560 */ 6561 if ((eeprom->address_bits == 8) && (offset >= 128)) 6562 read_opcode |= EEPROM_A8_OPCODE_SPI; 6563 6564 /* Send the READ command (opcode + addr) */ 6565 em_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits); 6566 em_shift_out_ee_bits(hw, (uint16_t) (offset * 2), 6567 eeprom->address_bits); 6568 /* 6569 * Read the data. The address of the eeprom internally 6570 * increments with each byte (spi) being read, saving on the 6571 * overhead of eeprom setup and tear-down. The address 6572 * counter will roll over if reading beyond the size of the 6573 * eeprom, thus allowing the entire memory to be read 6574 * starting from any offset. 6575 */ 6576 for (i = 0; i < words; i++) { 6577 word_in = em_shift_in_ee_bits(hw, 16); 6578 data[i] = (word_in >> 8) | (word_in << 8); 6579 } 6580 } else if (eeprom->type == em_eeprom_microwire) { 6581 for (i = 0; i < words; i++) { 6582 /* Send the READ command (opcode + addr) */ 6583 em_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE, 6584 eeprom->opcode_bits); 6585 em_shift_out_ee_bits(hw, (uint16_t) (offset + i), 6586 eeprom->address_bits); 6587 /* 6588 * Read the data. For microwire, each word requires 6589 * the overhead of eeprom setup and tear-down. 6590 */ 6591 data[i] = em_shift_in_ee_bits(hw, 16); 6592 em_standby_eeprom(hw); 6593 } 6594 } 6595 /* End this read operation */ 6596 em_release_eeprom(hw); 6597 6598 return E1000_SUCCESS; 6599 } 6600 6601 /****************************************************************************** 6602 * Reads a 16 bit word from the EEPROM using the EERD register. 6603 * 6604 * hw - Struct containing variables accessed by shared code 6605 * offset - offset of word in the EEPROM to read 6606 * data - word read from the EEPROM 6607 * words - number of words to read 6608 *****************************************************************************/ 6609 STATIC int32_t 6610 em_read_eeprom_eerd(struct em_hw *hw, uint16_t offset, uint16_t words, 6611 uint16_t *data) 6612 { 6613 uint32_t i, eerd = 0; 6614 int32_t error = 0; 6615 for (i = 0; i < words; i++) { 6616 eerd = ((offset + i) << E1000_EEPROM_RW_ADDR_SHIFT) + 6617 E1000_EEPROM_RW_REG_START; 6618 6619 E1000_WRITE_REG(hw, EERD, eerd); 6620 error = em_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ); 6621 6622 if (error) { 6623 break; 6624 } 6625 data[i] = (E1000_READ_REG(hw, EERD) >> 6626 E1000_EEPROM_RW_REG_DATA); 6627 6628 } 6629 6630 return error; 6631 } 6632 6633 /****************************************************************************** 6634 * Writes a 16 bit word from the EEPROM using the EEWR register. 6635 * 6636 * hw - Struct containing variables accessed by shared code 6637 * offset - offset of word in the EEPROM to read 6638 * data - word read from the EEPROM 6639 * words - number of words to read 6640 *****************************************************************************/ 6641 STATIC int32_t 6642 em_write_eeprom_eewr(struct em_hw *hw, uint16_t offset, uint16_t words, 6643 uint16_t *data) 6644 { 6645 uint32_t register_value = 0; 6646 uint32_t i = 0; 6647 int32_t error = 0; 6648 if (em_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM)) 6649 return -E1000_ERR_SWFW_SYNC; 6650 6651 for (i = 0; i < words; i++) { 6652 register_value = (data[i] << E1000_EEPROM_RW_REG_DATA) | 6653 ((offset + i) << E1000_EEPROM_RW_ADDR_SHIFT) | 6654 E1000_EEPROM_RW_REG_START; 6655 6656 error = em_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE); 6657 if (error) { 6658 break; 6659 } 6660 E1000_WRITE_REG(hw, EEWR, register_value); 6661 6662 error = em_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE); 6663 6664 if (error) { 6665 break; 6666 } 6667 } 6668 6669 em_swfw_sync_release(hw, E1000_SWFW_EEP_SM); 6670 return error; 6671 } 6672 6673 /****************************************************************************** 6674 * Polls the status bit (bit 1) of the EERD to determine when the read is done. 6675 * 6676 * hw - Struct containing variables accessed by shared code 6677 *****************************************************************************/ 6678 STATIC int32_t 6679 em_poll_eerd_eewr_done(struct em_hw *hw, int eerd) 6680 { 6681 uint32_t attempts = 100000; 6682 uint32_t i, reg = 0; 6683 int32_t done = E1000_ERR_EEPROM; 6684 for (i = 0; i < attempts; i++) { 6685 if (eerd == E1000_EEPROM_POLL_READ) 6686 reg = E1000_READ_REG(hw, EERD); 6687 else 6688 reg = E1000_READ_REG(hw, EEWR); 6689 6690 if (reg & E1000_EEPROM_RW_REG_DONE) { 6691 done = E1000_SUCCESS; 6692 break; 6693 } 6694 usec_delay(5); 6695 } 6696 6697 return done; 6698 } 6699 6700 /****************************************************************************** 6701 * Description: Determines if the onboard NVM is FLASH or EEPROM. 6702 * 6703 * hw - Struct containing variables accessed by shared code 6704 *****************************************************************************/ 6705 STATIC boolean_t 6706 em_is_onboard_nvm_eeprom(struct em_hw *hw) 6707 { 6708 uint32_t eecd = 0; 6709 DEBUGFUNC("em_is_onboard_nvm_eeprom"); 6710 6711 if (IS_ICH8(hw->mac_type)) 6712 return FALSE; 6713 6714 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) { 6715 eecd = E1000_READ_REG(hw, EECD); 6716 6717 /* Isolate bits 15 & 16 */ 6718 eecd = ((eecd >> 15) & 0x03); 6719 6720 /* If both bits are set, device is Flash type */ 6721 if (eecd == 0x03) { 6722 return FALSE; 6723 } 6724 } 6725 return TRUE; 6726 } 6727 6728 /****************************************************************************** 6729 * Check if flash device is detected. 6730 * 6731 * hw - Struct containing variables accessed by shared code 6732 *****************************************************************************/ 6733 boolean_t 6734 em_get_flash_presence_i210(struct em_hw *hw) 6735 { 6736 uint32_t eecd; 6737 DEBUGFUNC("em_get_flash_presence_i210"); 6738 6739 if (hw->mac_type != em_i210) 6740 return TRUE; 6741 6742 eecd = E1000_READ_REG(hw, EECD); 6743 6744 if (eecd & E1000_EECD_FLUPD) 6745 return TRUE; 6746 6747 return FALSE; 6748 } 6749 6750 /****************************************************************************** 6751 * Verifies that the EEPROM has a valid checksum 6752 * 6753 * hw - Struct containing variables accessed by shared code 6754 * 6755 * Reads the first 64 16 bit words of the EEPROM and sums the values read. 6756 * If the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is 6757 * valid. 6758 *****************************************************************************/ 6759 int32_t 6760 em_validate_eeprom_checksum(struct em_hw *hw) 6761 { 6762 uint16_t checksum = 0; 6763 uint16_t i, eeprom_data; 6764 uint16_t checksum_reg; 6765 DEBUGFUNC("em_validate_eeprom_checksum"); 6766 6767 checksum_reg = hw->mac_type != em_icp_xxxx ? 6768 EEPROM_CHECKSUM_REG : 6769 EEPROM_CHECKSUM_REG_ICP_xxxx; 6770 6771 if (((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) && 6772 (em_is_onboard_nvm_eeprom(hw) == FALSE)) { 6773 /* 6774 * Check bit 4 of word 10h. If it is 0, firmware is done 6775 * updating 10h-12h. Checksum may need to be fixed. 6776 */ 6777 em_read_eeprom(hw, 0x10, 1, &eeprom_data); 6778 if ((eeprom_data & 0x10) == 0) { 6779 /* 6780 * Read 0x23 and check bit 15. This bit is a 1 when 6781 * the checksum has already been fixed. If the 6782 * checksum is still wrong and this bit is a 1, we 6783 * need to return bad checksum. Otherwise, we need 6784 * to set this bit to a 1 and update the checksum. 6785 */ 6786 em_read_eeprom(hw, 0x23, 1, &eeprom_data); 6787 if ((eeprom_data & 0x8000) == 0) { 6788 eeprom_data |= 0x8000; 6789 em_write_eeprom(hw, 0x23, 1, &eeprom_data); 6790 em_update_eeprom_checksum(hw); 6791 } 6792 } 6793 } 6794 if (IS_ICH8(hw->mac_type)) { 6795 uint16_t word; 6796 uint16_t valid_csum_mask; 6797 6798 /* 6799 * Drivers must allocate the shadow ram structure for the 6800 * EEPROM checksum to be updated. Otherwise, this bit as 6801 * well as the checksum must both be set correctly for this 6802 * validation to pass. 6803 */ 6804 switch (hw->mac_type) { 6805 case em_pch_lpt: 6806 case em_pch_spt: 6807 case em_pch_cnp: 6808 word = EEPROM_COMPAT; 6809 valid_csum_mask = EEPROM_COMPAT_VALID_CSUM; 6810 break; 6811 default: 6812 word = EEPROM_FUTURE_INIT_WORD1; 6813 valid_csum_mask = EEPROM_FUTURE_INIT_WORD1_VALID_CSUM; 6814 break; 6815 } 6816 em_read_eeprom(hw, word, 1, &eeprom_data); 6817 if ((eeprom_data & valid_csum_mask) == 0) { 6818 eeprom_data |= valid_csum_mask; 6819 em_write_eeprom(hw, word, 1, &eeprom_data); 6820 em_update_eeprom_checksum(hw); 6821 } 6822 } 6823 for (i = 0; i < (checksum_reg + 1); i++) { 6824 if (em_read_eeprom(hw, i, 1, &eeprom_data) < 0) { 6825 DEBUGOUT("EEPROM Read Error\n"); 6826 return -E1000_ERR_EEPROM; 6827 } 6828 checksum += eeprom_data; 6829 } 6830 6831 if (checksum == (uint16_t) EEPROM_SUM) 6832 return E1000_SUCCESS; 6833 else { 6834 DEBUGOUT("EEPROM Checksum Invalid\n"); 6835 return -E1000_ERR_EEPROM; 6836 } 6837 } 6838 6839 /****************************************************************************** 6840 * Calculates the EEPROM checksum and writes it to the EEPROM 6841 * 6842 * hw - Struct containing variables accessed by shared code 6843 * 6844 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA. 6845 * Writes the difference to word offset 63 of the EEPROM. 6846 *****************************************************************************/ 6847 int32_t 6848 em_update_eeprom_checksum(struct em_hw *hw) 6849 { 6850 uint32_t ctrl_ext; 6851 uint16_t checksum = 0; 6852 uint16_t i, eeprom_data; 6853 DEBUGFUNC("em_update_eeprom_checksum"); 6854 6855 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) { 6856 if (em_read_eeprom(hw, i, 1, &eeprom_data) < 0) { 6857 DEBUGOUT("EEPROM Read Error\n"); 6858 return -E1000_ERR_EEPROM; 6859 } 6860 checksum += eeprom_data; 6861 } 6862 checksum = (uint16_t) EEPROM_SUM - checksum; 6863 if (em_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) { 6864 DEBUGOUT("EEPROM Write Error\n"); 6865 return -E1000_ERR_EEPROM; 6866 } else if (hw->eeprom.type == em_eeprom_flash) { 6867 em_commit_shadow_ram(hw); 6868 } else if (hw->eeprom.type == em_eeprom_ich8) { 6869 em_commit_shadow_ram(hw); 6870 /* 6871 * Reload the EEPROM, or else modifications will not appear 6872 * until after next adapter reset. 6873 */ 6874 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 6875 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 6876 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 6877 msec_delay(10); 6878 } 6879 return E1000_SUCCESS; 6880 } 6881 6882 /****************************************************************************** 6883 * Parent function for writing words to the different EEPROM types. 6884 * 6885 * hw - Struct containing variables accessed by shared code 6886 * offset - offset within the EEPROM to be written to 6887 * words - number of words to write 6888 * data - 16 bit word to be written to the EEPROM 6889 * 6890 * If em_update_eeprom_checksum is not called after this function, the 6891 * EEPROM will most likely contain an invalid checksum. 6892 *****************************************************************************/ 6893 int32_t 6894 em_write_eeprom(struct em_hw *hw, uint16_t offset, uint16_t words, 6895 uint16_t *data) 6896 { 6897 struct em_eeprom_info *eeprom = &hw->eeprom; 6898 int32_t status = 0; 6899 DEBUGFUNC("em_write_eeprom"); 6900 6901 /* If eeprom is not yet detected, do so now */ 6902 if (eeprom->word_size == 0) 6903 em_init_eeprom_params(hw); 6904 /* 6905 * A check for invalid values: offset too large, too many words, and 6906 * not enough words. 6907 */ 6908 if ((offset >= eeprom->word_size) || 6909 (words > eeprom->word_size - offset) || 6910 (words == 0)) { 6911 DEBUGOUT("\"words\" parameter out of bounds\n"); 6912 return -E1000_ERR_EEPROM; 6913 } 6914 /* 82573/4 writes only through eewr */ 6915 if (eeprom->use_eewr == TRUE) 6916 return em_write_eeprom_eewr(hw, offset, words, data); 6917 6918 if (eeprom->type == em_eeprom_ich8) 6919 return em_write_eeprom_ich8(hw, offset, words, data); 6920 6921 /* Prepare the EEPROM for writing */ 6922 if (em_acquire_eeprom(hw) != E1000_SUCCESS) 6923 return -E1000_ERR_EEPROM; 6924 6925 if (eeprom->type == em_eeprom_microwire) { 6926 status = em_write_eeprom_microwire(hw, offset, words, data); 6927 } else { 6928 status = em_write_eeprom_spi(hw, offset, words, data); 6929 msec_delay(10); 6930 } 6931 6932 /* Done with writing */ 6933 em_release_eeprom(hw); 6934 6935 return status; 6936 } 6937 6938 /****************************************************************************** 6939 * Writes a 16 bit word to a given offset in an SPI EEPROM. 6940 * 6941 * hw - Struct containing variables accessed by shared code 6942 * offset - offset within the EEPROM to be written to 6943 * words - number of words to write 6944 * data - pointer to array of 8 bit words to be written to the EEPROM 6945 * 6946 *****************************************************************************/ 6947 STATIC int32_t 6948 em_write_eeprom_spi(struct em_hw *hw, uint16_t offset, uint16_t words, 6949 uint16_t *data) 6950 { 6951 struct em_eeprom_info *eeprom = &hw->eeprom; 6952 uint16_t widx = 0; 6953 DEBUGFUNC("em_write_eeprom_spi"); 6954 6955 while (widx < words) { 6956 uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI; 6957 if (em_spi_eeprom_ready(hw)) 6958 return -E1000_ERR_EEPROM; 6959 6960 em_standby_eeprom(hw); 6961 6962 /* Send the WRITE ENABLE command (8 bit opcode ) */ 6963 em_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI, 6964 eeprom->opcode_bits); 6965 6966 em_standby_eeprom(hw); 6967 /* 6968 * Some SPI eeproms use the 8th address bit embedded in the 6969 * opcode 6970 */ 6971 if ((eeprom->address_bits == 8) && (offset >= 128)) 6972 write_opcode |= EEPROM_A8_OPCODE_SPI; 6973 6974 /* Send the Write command (8-bit opcode + addr) */ 6975 em_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits); 6976 6977 em_shift_out_ee_bits(hw, (uint16_t) ((offset + widx) * 2), 6978 eeprom->address_bits); 6979 6980 /* Send the data */ 6981 /* 6982 * Loop to allow for up to whole page write (32 bytes) of 6983 * eeprom 6984 */ 6985 while (widx < words) { 6986 uint16_t word_out = data[widx]; 6987 word_out = (word_out >> 8) | (word_out << 8); 6988 em_shift_out_ee_bits(hw, word_out, 16); 6989 widx++; 6990 /* 6991 * Some larger eeprom sizes are capable of a 32-byte 6992 * PAGE WRITE operation, while the smaller eeproms 6993 * are capable of an 8-byte PAGE WRITE operation. 6994 * Break the inner loop to pass new address 6995 */ 6996 if ((((offset + widx) * 2) % eeprom->page_size) == 0) { 6997 em_standby_eeprom(hw); 6998 break; 6999 } 7000 } 7001 } 7002 7003 return E1000_SUCCESS; 7004 } 7005 7006 /****************************************************************************** 7007 * Writes a 16 bit word to a given offset in a Microwire EEPROM. 7008 * 7009 * hw - Struct containing variables accessed by shared code 7010 * offset - offset within the EEPROM to be written to 7011 * words - number of words to write 7012 * data - pointer to array of 16 bit words to be written to the EEPROM 7013 * 7014 *****************************************************************************/ 7015 STATIC int32_t 7016 em_write_eeprom_microwire(struct em_hw *hw, uint16_t offset, uint16_t words, 7017 uint16_t *data) 7018 { 7019 struct em_eeprom_info *eeprom = &hw->eeprom; 7020 uint32_t eecd; 7021 uint16_t words_written = 0; 7022 uint16_t i = 0; 7023 DEBUGFUNC("em_write_eeprom_microwire"); 7024 /* 7025 * Send the write enable command to the EEPROM (3-bit opcode plus 7026 * 6/8-bit dummy address beginning with 11). It's less work to 7027 * include the 11 of the dummy address as part of the opcode than it 7028 * is to shift it over the correct number of bits for the address. 7029 * This puts the EEPROM into write/erase mode. 7030 */ 7031 em_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE, 7032 (uint16_t) (eeprom->opcode_bits + 2)); 7033 7034 em_shift_out_ee_bits(hw, 0, (uint16_t) (eeprom->address_bits - 2)); 7035 7036 /* Prepare the EEPROM */ 7037 em_standby_eeprom(hw); 7038 7039 while (words_written < words) { 7040 /* Send the Write command (3-bit opcode + addr) */ 7041 em_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE, 7042 eeprom->opcode_bits); 7043 7044 em_shift_out_ee_bits(hw, (uint16_t) (offset + words_written), 7045 eeprom->address_bits); 7046 7047 /* Send the data */ 7048 em_shift_out_ee_bits(hw, data[words_written], 16); 7049 /* 7050 * Toggle the CS line. This in effect tells the EEPROM to 7051 * execute the previous command. 7052 */ 7053 em_standby_eeprom(hw); 7054 /* 7055 * Read DO repeatedly until it is high (equal to '1'). The 7056 * EEPROM will signal that the command has been completed by 7057 * raising the DO signal. If DO does not go high in 10 7058 * milliseconds, then error out. 7059 */ 7060 for (i = 0; i < 200; i++) { 7061 eecd = E1000_READ_REG(hw, EECD); 7062 if (eecd & E1000_EECD_DO) 7063 break; 7064 usec_delay(50); 7065 } 7066 if (i == 200) { 7067 DEBUGOUT("EEPROM Write did not complete\n"); 7068 return -E1000_ERR_EEPROM; 7069 } 7070 /* Recover from write */ 7071 em_standby_eeprom(hw); 7072 7073 words_written++; 7074 } 7075 /* 7076 * Send the write disable command to the EEPROM (3-bit opcode plus 7077 * 6/8-bit dummy address beginning with 10). It's less work to 7078 * include the 10 of the dummy address as part of the opcode than it 7079 * is to shift it over the correct number of bits for the address. 7080 * This takes the EEPROM out of write/erase mode. 7081 */ 7082 em_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE, 7083 (uint16_t) (eeprom->opcode_bits + 2)); 7084 7085 em_shift_out_ee_bits(hw, 0, (uint16_t) (eeprom->address_bits - 2)); 7086 7087 return E1000_SUCCESS; 7088 } 7089 7090 /****************************************************************************** 7091 * Flushes the cached eeprom to NVM. This is done by saving the modified values 7092 * in the eeprom cache and the non modified values in the currently active bank 7093 * to the new bank. 7094 * 7095 * hw - Struct containing variables accessed by shared code 7096 * offset - offset of word in the EEPROM to read 7097 * data - word read from the EEPROM 7098 * words - number of words to read 7099 *****************************************************************************/ 7100 STATIC int32_t 7101 em_commit_shadow_ram(struct em_hw *hw) 7102 { 7103 uint32_t attempts = 100000; 7104 uint32_t eecd = 0; 7105 uint32_t flop = 0; 7106 uint32_t i = 0; 7107 int32_t error = E1000_SUCCESS; 7108 uint32_t old_bank_offset = 0; 7109 uint32_t new_bank_offset = 0; 7110 uint8_t low_byte = 0; 7111 uint8_t high_byte = 0; 7112 boolean_t sector_write_failed = FALSE; 7113 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) { 7114 /* 7115 * The flop register will be used to determine if flash type 7116 * is STM 7117 */ 7118 flop = E1000_READ_REG(hw, FLOP); 7119 for (i = 0; i < attempts; i++) { 7120 eecd = E1000_READ_REG(hw, EECD); 7121 if ((eecd & E1000_EECD_FLUPD) == 0) { 7122 break; 7123 } 7124 usec_delay(5); 7125 } 7126 7127 if (i == attempts) { 7128 return -E1000_ERR_EEPROM; 7129 } 7130 /* 7131 * If STM opcode located in bits 15:8 of flop, reset firmware 7132 */ 7133 if ((flop & 0xFF00) == E1000_STM_OPCODE) { 7134 E1000_WRITE_REG(hw, HICR, E1000_HICR_FW_RESET); 7135 } 7136 /* Perform the flash update */ 7137 E1000_WRITE_REG(hw, EECD, eecd | E1000_EECD_FLUPD); 7138 7139 for (i = 0; i < attempts; i++) { 7140 eecd = E1000_READ_REG(hw, EECD); 7141 if ((eecd & E1000_EECD_FLUPD) == 0) { 7142 break; 7143 } 7144 usec_delay(5); 7145 } 7146 7147 if (i == attempts) { 7148 return -E1000_ERR_EEPROM; 7149 } 7150 } 7151 if ((hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) && 7152 hw->eeprom_shadow_ram != NULL) { 7153 /* 7154 * We're writing to the opposite bank so if we're on bank 1, 7155 * write to bank 0 etc. We also need to erase the segment 7156 * that is going to be written 7157 */ 7158 if (!(E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL)) { 7159 new_bank_offset = hw->flash_bank_size * 2; 7160 old_bank_offset = 0; 7161 em_erase_ich8_4k_segment(hw, 1); 7162 } else { 7163 old_bank_offset = hw->flash_bank_size * 2; 7164 new_bank_offset = 0; 7165 em_erase_ich8_4k_segment(hw, 0); 7166 } 7167 7168 sector_write_failed = FALSE; 7169 /* 7170 * Loop for every byte in the shadow RAM, which is in units 7171 * of words. 7172 */ 7173 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 7174 /* 7175 * Determine whether to write the value stored in the 7176 * other NVM bank or a modified value stored in the 7177 * shadow RAM 7178 */ 7179 if (hw->eeprom_shadow_ram[i].modified == TRUE) { 7180 low_byte = (uint8_t) 7181 hw->eeprom_shadow_ram[i].eeprom_word; 7182 usec_delay(100); 7183 error = em_verify_write_ich8_byte(hw, 7184 (i << 1) + new_bank_offset, low_byte); 7185 7186 if (error != E1000_SUCCESS) 7187 sector_write_failed = TRUE; 7188 else { 7189 high_byte = (uint8_t) 7190 (hw->eeprom_shadow_ram 7191 [i].eeprom_word >> 8); 7192 usec_delay(100); 7193 } 7194 } else { 7195 em_read_ich8_byte(hw, (i << 1) + 7196 old_bank_offset, &low_byte); 7197 usec_delay(100); 7198 error = em_verify_write_ich8_byte(hw, 7199 (i << 1) + new_bank_offset, low_byte); 7200 7201 if (error != E1000_SUCCESS) 7202 sector_write_failed = TRUE; 7203 else { 7204 em_read_ich8_byte(hw, (i << 1) + 7205 old_bank_offset + 1, &high_byte); 7206 usec_delay(100); 7207 } 7208 } 7209 /* 7210 * If the write of the low byte was successful, go 7211 * ahread and write the high byte while checking to 7212 * make sure that if it is the signature byte, then 7213 * it is handled properly 7214 */ 7215 if (sector_write_failed == FALSE) { 7216 /* 7217 * If the word is 0x13, then make sure the 7218 * signature bits (15:14) are 11b until the 7219 * commit has completed. This will allow us 7220 * to write 10b which indicates the signature 7221 * is valid. We want to do this after the 7222 * write has completed so that we don't mark 7223 * the segment valid while the write is still 7224 * in progress 7225 */ 7226 if (i == E1000_ICH_NVM_SIG_WORD) 7227 high_byte = E1000_ICH_NVM_VALID_SIG_MASK | 7228 high_byte; 7229 7230 error = em_verify_write_ich8_byte(hw, (i << 1) 7231 + new_bank_offset + 1, high_byte); 7232 if (error != E1000_SUCCESS) 7233 sector_write_failed = TRUE; 7234 7235 } else { 7236 /* 7237 * If the write failed then break from the 7238 * loop and return an error 7239 */ 7240 break; 7241 } 7242 } 7243 /* 7244 * Don't bother writing the segment valid bits if sector 7245 * programming failed. 7246 */ 7247 if (sector_write_failed == FALSE) { 7248 /* 7249 * Finally validate the new segment by setting bit 7250 * 15:14 to 10b in word 0x13 , this can be done 7251 * without an erase as well since these bits are 11 7252 * to start with and we need to change bit 14 to 0b 7253 */ 7254 em_read_ich8_byte(hw, E1000_ICH_NVM_SIG_WORD * 2 + 1 + 7255 new_bank_offset, &high_byte); 7256 high_byte &= 0xBF; 7257 error = em_verify_write_ich8_byte(hw, 7258 E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset, 7259 high_byte); 7260 /* 7261 * And invalidate the previously valid segment by 7262 * setting its signature word (0x13) high_byte to 0b. 7263 * This can be done without an erase because flash 7264 * erase sets all bits to 1's. We can write 1's to 7265 * 0's without an erase 7266 */ 7267 if (error == E1000_SUCCESS) { 7268 error = em_verify_write_ich8_byte(hw, 7269 E1000_ICH_NVM_SIG_WORD * 2 + 1 + 7270 old_bank_offset, 0); 7271 } 7272 /* Clear the now not used entry in the cache */ 7273 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 7274 hw->eeprom_shadow_ram[i].modified = FALSE; 7275 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF; 7276 } 7277 } 7278 } 7279 return error; 7280 } 7281 7282 /****************************************************************************** 7283 * Reads the adapter's part number from the EEPROM 7284 * 7285 * hw - Struct containing variables accessed by shared code 7286 * part_num - Adapter's part number 7287 *****************************************************************************/ 7288 int32_t 7289 em_read_part_num(struct em_hw *hw, uint32_t *part_num) 7290 { 7291 uint16_t offset = EEPROM_PBA_BYTE_1; 7292 uint16_t eeprom_data; 7293 DEBUGFUNC("em_read_part_num"); 7294 7295 /* Get word 0 from EEPROM */ 7296 if (em_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { 7297 DEBUGOUT("EEPROM Read Error\n"); 7298 return -E1000_ERR_EEPROM; 7299 } 7300 /* Save word 0 in upper half of part_num */ 7301 *part_num = (uint32_t) (eeprom_data << 16); 7302 7303 /* Get word 1 from EEPROM */ 7304 if (em_read_eeprom(hw, ++offset, 1, &eeprom_data) < 0) { 7305 DEBUGOUT("EEPROM Read Error\n"); 7306 return -E1000_ERR_EEPROM; 7307 } 7308 /* Save word 1 in lower half of part_num */ 7309 *part_num |= eeprom_data; 7310 7311 return E1000_SUCCESS; 7312 } 7313 7314 /****************************************************************************** 7315 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the 7316 * second function of dual function devices 7317 * 7318 * hw - Struct containing variables accessed by shared code 7319 *****************************************************************************/ 7320 int32_t 7321 em_read_mac_addr(struct em_hw *hw) 7322 { 7323 uint16_t offset; 7324 uint16_t eeprom_data, i; 7325 uint16_t ia_base_addr = 0; 7326 DEBUGFUNC("em_read_mac_addr"); 7327 7328 if (hw->mac_type == em_icp_xxxx) { 7329 ia_base_addr = (uint16_t) 7330 EEPROM_IA_START_ICP_xxxx(hw->icp_xxxx_port_num); 7331 } else if (hw->mac_type == em_82580 || hw->mac_type == em_i350) { 7332 ia_base_addr = NVM_82580_LAN_FUNC_OFFSET(hw->bus_func); 7333 } 7334 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) { 7335 offset = i >> 1; 7336 if (em_read_eeprom(hw, offset + ia_base_addr, 1, &eeprom_data) 7337 < 0) { 7338 DEBUGOUT("EEPROM Read Error\n"); 7339 return -E1000_ERR_EEPROM; 7340 } 7341 hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF); 7342 hw->perm_mac_addr[i + 1] = (uint8_t) (eeprom_data >> 8); 7343 } 7344 7345 switch (hw->mac_type) { 7346 default: 7347 break; 7348 case em_82546: 7349 case em_82546_rev_3: 7350 case em_82571: 7351 case em_82575: 7352 case em_82576: 7353 case em_80003es2lan: 7354 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) 7355 hw->perm_mac_addr[5] ^= 0x01; 7356 break; 7357 } 7358 7359 for (i = 0; i < NODE_ADDRESS_SIZE; i++) 7360 hw->mac_addr[i] = hw->perm_mac_addr[i]; 7361 return E1000_SUCCESS; 7362 } 7363 7364 /****************************************************************************** 7365 * Explicitly disables jumbo frames and resets some PHY registers back to hw- 7366 * defaults. This is necessary in case the ethernet cable was inserted AFTER 7367 * the firmware initialized the PHY. Otherwise it is left in a state where 7368 * it is possible to transmit but not receive packets. Observed on I217-LM and 7369 * fixed in FreeBSD's sys/dev/e1000/e1000_ich8lan.c. 7370 * 7371 * hw - Struct containing variables accessed by shared code 7372 *****************************************************************************/ 7373 STATIC int32_t 7374 em_phy_no_cable_workaround(struct em_hw *hw) { 7375 int32_t ret_val, dft_ret_val; 7376 uint32_t mac_reg; 7377 uint16_t data, phy_reg; 7378 7379 /* disable Rx path while enabling workaround */ 7380 em_read_phy_reg(hw, I2_DFT_CTRL, &phy_reg); 7381 ret_val = em_write_phy_reg(hw, I2_DFT_CTRL, phy_reg | (1 << 14)); 7382 if (ret_val) 7383 return ret_val; 7384 7385 /* Write MAC register values back to h/w defaults */ 7386 mac_reg = E1000_READ_REG(hw, FFLT_DBG); 7387 mac_reg &= ~(0xF << 14); 7388 E1000_WRITE_REG(hw, FFLT_DBG, mac_reg); 7389 7390 mac_reg = E1000_READ_REG(hw, RCTL); 7391 mac_reg &= ~E1000_RCTL_SECRC; 7392 E1000_WRITE_REG(hw, RCTL, mac_reg); 7393 7394 ret_val = em_read_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_CTRL, &data); 7395 if (ret_val) 7396 goto out; 7397 ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_CTRL, 7398 data & ~(1 << 0)); 7399 if (ret_val) 7400 goto out; 7401 7402 ret_val = em_read_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL, &data); 7403 if (ret_val) 7404 goto out; 7405 7406 data &= ~(0xF << 8); 7407 data |= (0xB << 8); 7408 ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL, data); 7409 if (ret_val) 7410 goto out; 7411 7412 /* Write PHY register values back to h/w defaults */ 7413 em_read_phy_reg(hw, I2_SMBUS_CTRL, &data); 7414 data &= ~(0x7F << 5); 7415 ret_val = em_write_phy_reg(hw, I2_SMBUS_CTRL, data); 7416 if (ret_val) 7417 goto out; 7418 7419 em_read_phy_reg(hw, I2_MODE_CTRL, &data); 7420 data |= (1 << 13); 7421 ret_val = em_write_phy_reg(hw, I2_MODE_CTRL, data); 7422 if (ret_val) 7423 goto out; 7424 7425 /* 7426 * 776.20 and 776.23 are not documented in 7427 * i217-ethernet-controller-datasheet.pdf... 7428 */ 7429 em_read_phy_reg(hw, PHY_REG(776, 20), &data); 7430 data &= ~(0x3FF << 2); 7431 data |= (0x8 << 2); 7432 ret_val = em_write_phy_reg(hw, PHY_REG(776, 20), data); 7433 if (ret_val) 7434 goto out; 7435 7436 ret_val = em_write_phy_reg(hw, PHY_REG(776, 23), 0x7E00); 7437 if (ret_val) 7438 goto out; 7439 7440 em_read_phy_reg(hw, I2_PCIE_POWER_CTRL, &data); 7441 ret_val = em_write_phy_reg(hw, I2_PCIE_POWER_CTRL, data & ~(1 << 10)); 7442 if (ret_val) 7443 goto out; 7444 7445 out: 7446 /* re-enable Rx path after enabling workaround */ 7447 dft_ret_val = em_write_phy_reg(hw, I2_DFT_CTRL, phy_reg & ~(1 << 14)); 7448 if (ret_val) 7449 return ret_val; 7450 else 7451 return dft_ret_val; 7452 } 7453 7454 /****************************************************************************** 7455 * Initializes receive address filters. 7456 * 7457 * hw - Struct containing variables accessed by shared code 7458 * 7459 * Places the MAC address in receive address register 0 and clears the rest 7460 * of the receive addresss registers. Clears the multicast table. Assumes 7461 * the receiver is in reset when the routine is called. 7462 *****************************************************************************/ 7463 STATIC void 7464 em_init_rx_addrs(struct em_hw *hw) 7465 { 7466 uint32_t i; 7467 uint32_t rar_num; 7468 DEBUGFUNC("em_init_rx_addrs"); 7469 7470 if (hw->mac_type == em_pch_lpt || hw->mac_type == em_pch_spt || 7471 hw->mac_type == em_pch_cnp || hw->mac_type == em_pch2lan) 7472 if (em_phy_no_cable_workaround(hw)) 7473 printf(" ...failed to apply em_phy_no_cable_" 7474 "workaround.\n"); 7475 7476 /* Setup the receive address. */ 7477 DEBUGOUT("Programming MAC Address into RAR[0]\n"); 7478 7479 em_rar_set(hw, hw->mac_addr, 0); 7480 7481 rar_num = E1000_RAR_ENTRIES; 7482 /* 7483 * Reserve a spot for the Locally Administered Address to work around 7484 * an 82571 issue in which a reset on one port will reload the MAC on 7485 * the other port. 7486 */ 7487 if ((hw->mac_type == em_82571) && (hw->laa_is_present == TRUE)) 7488 rar_num -= 1; 7489 if (IS_ICH8(hw->mac_type)) 7490 rar_num = E1000_RAR_ENTRIES_ICH8LAN; 7491 if (hw->mac_type == em_ich8lan) 7492 rar_num -= 1; 7493 if (hw->mac_type == em_82580) 7494 rar_num = E1000_RAR_ENTRIES_82580; 7495 if (hw->mac_type == em_i210) 7496 rar_num = E1000_RAR_ENTRIES_82575; 7497 if (hw->mac_type == em_i350) 7498 rar_num = E1000_RAR_ENTRIES_I350; 7499 7500 /* Zero out the other 15 receive addresses. */ 7501 DEBUGOUT("Clearing RAR[1-15]\n"); 7502 for (i = 1; i < rar_num; i++) { 7503 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 7504 E1000_WRITE_FLUSH(hw); 7505 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 7506 E1000_WRITE_FLUSH(hw); 7507 } 7508 } 7509 7510 /****************************************************************************** 7511 * Updates the MAC's list of multicast addresses. 7512 * 7513 * hw - Struct containing variables accessed by shared code 7514 * mc_addr_list - the list of new multicast addresses 7515 * mc_addr_count - number of addresses 7516 * pad - number of bytes between addresses in the list 7517 * rar_used_count - offset where to start adding mc addresses into the RAR's 7518 * 7519 * The given list replaces any existing list. Clears the last 15 receive 7520 * address registers and the multicast table. Uses receive address registers 7521 * for the first 15 multicast addresses, and hashes the rest into the 7522 * multicast table. 7523 *****************************************************************************/ 7524 void 7525 em_mc_addr_list_update(struct em_hw *hw, uint8_t *mc_addr_list, 7526 uint32_t mc_addr_count, uint32_t pad, uint32_t rar_used_count) 7527 { 7528 uint32_t hash_value; 7529 uint32_t i; 7530 uint32_t num_rar_entry; 7531 uint32_t num_mta_entry; 7532 DEBUGFUNC("em_mc_addr_list_update"); 7533 /* 7534 * Set the new number of MC addresses that we are being requested to 7535 * use. 7536 */ 7537 hw->num_mc_addrs = mc_addr_count; 7538 7539 /* Clear RAR[1-15] */ 7540 DEBUGOUT(" Clearing RAR[1-15]\n"); 7541 num_rar_entry = E1000_RAR_ENTRIES; 7542 if (IS_ICH8(hw->mac_type)) 7543 num_rar_entry = E1000_RAR_ENTRIES_ICH8LAN; 7544 if (hw->mac_type == em_ich8lan) 7545 num_rar_entry -= 1; 7546 /* 7547 * Reserve a spot for the Locally Administered Address to work around 7548 * an 82571 issue in which a reset on one port will reload the MAC on 7549 * the other port. 7550 */ 7551 if ((hw->mac_type == em_82571) && (hw->laa_is_present == TRUE)) 7552 num_rar_entry -= 1; 7553 7554 for (i = rar_used_count; i < num_rar_entry; i++) { 7555 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 7556 E1000_WRITE_FLUSH(hw); 7557 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 7558 E1000_WRITE_FLUSH(hw); 7559 } 7560 7561 /* Clear the MTA */ 7562 DEBUGOUT(" Clearing MTA\n"); 7563 num_mta_entry = E1000_NUM_MTA_REGISTERS; 7564 if (IS_ICH8(hw->mac_type)) 7565 num_mta_entry = E1000_NUM_MTA_REGISTERS_ICH8LAN; 7566 7567 for (i = 0; i < num_mta_entry; i++) { 7568 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 7569 E1000_WRITE_FLUSH(hw); 7570 } 7571 7572 /* Add the new addresses */ 7573 for (i = 0; i < mc_addr_count; i++) { 7574 DEBUGOUT(" Adding the multicast addresses:\n"); 7575 DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i, 7576 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad)], 7577 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 1], 7578 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 2], 7579 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 3], 7580 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 4], 7581 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 5]); 7582 7583 hash_value = em_hash_mc_addr(hw, mc_addr_list + 7584 (i * (ETH_LENGTH_OF_ADDRESS + pad))); 7585 7586 DEBUGOUT1(" Hash value = 0x%03X\n", hash_value); 7587 /* 7588 * Place this multicast address in the RAR if there is room, * 7589 * else put it in the MTA 7590 */ 7591 if (rar_used_count < num_rar_entry) { 7592 em_rar_set(hw, mc_addr_list + 7593 (i * (ETH_LENGTH_OF_ADDRESS + pad)), 7594 rar_used_count); 7595 rar_used_count++; 7596 } else { 7597 em_mta_set(hw, hash_value); 7598 } 7599 } 7600 DEBUGOUT("MC Update Complete\n"); 7601 } 7602 7603 /****************************************************************************** 7604 * Hashes an address to determine its location in the multicast table 7605 * 7606 * hw - Struct containing variables accessed by shared code 7607 * mc_addr - the multicast address to hash 7608 *****************************************************************************/ 7609 uint32_t 7610 em_hash_mc_addr(struct em_hw *hw, uint8_t *mc_addr) 7611 { 7612 uint32_t hash_value = 0; 7613 /* 7614 * The portion of the address that is used for the hash table is 7615 * determined by the mc_filter_type setting. 7616 */ 7617 switch (hw->mc_filter_type) { 7618 /* 7619 * [0] [1] [2] [3] [4] [5] 01 AA 00 12 34 56 LSB 7620 * MSB 7621 */ 7622 case 0: 7623 if (IS_ICH8(hw->mac_type)) { 7624 /* [47:38] i.e. 0x158 for above example address */ 7625 hash_value = ((mc_addr[4] >> 6) | 7626 (((uint16_t) mc_addr[5]) << 2)); 7627 } else { 7628 /* [47:36] i.e. 0x563 for above example address */ 7629 hash_value = ((mc_addr[4] >> 4) | 7630 (((uint16_t) mc_addr[5]) << 4)); 7631 } 7632 break; 7633 case 1: 7634 if (IS_ICH8(hw->mac_type)) { 7635 /* [46:37] i.e. 0x2B1 for above example address */ 7636 hash_value = ((mc_addr[4] >> 5) | 7637 (((uint16_t) mc_addr[5]) << 3)); 7638 } else { 7639 /* [46:35] i.e. 0xAC6 for above example address */ 7640 hash_value = ((mc_addr[4] >> 3) | 7641 (((uint16_t) mc_addr[5]) << 5)); 7642 } 7643 break; 7644 case 2: 7645 if (IS_ICH8(hw->mac_type)) { 7646 /* [45:36] i.e. 0x163 for above example address */ 7647 hash_value = ((mc_addr[4] >> 4) | 7648 (((uint16_t) mc_addr[5]) << 4)); 7649 } else { 7650 /* [45:34] i.e. 0x5D8 for above example address */ 7651 hash_value = ((mc_addr[4] >> 2) | 7652 (((uint16_t) mc_addr[5]) << 6)); 7653 } 7654 break; 7655 case 3: 7656 if (IS_ICH8(hw->mac_type)) { 7657 /* [43:34] i.e. 0x18D for above example address */ 7658 hash_value = ((mc_addr[4] >> 2) | 7659 (((uint16_t) mc_addr[5]) << 6)); 7660 } else { 7661 /* [43:32] i.e. 0x634 for above example address */ 7662 hash_value = ((mc_addr[4]) | 7663 (((uint16_t) mc_addr[5]) << 8)); 7664 } 7665 break; 7666 } 7667 7668 hash_value &= 0xFFF; 7669 if (IS_ICH8(hw->mac_type)) 7670 hash_value &= 0x3FF; 7671 7672 return hash_value; 7673 } 7674 7675 /****************************************************************************** 7676 * Sets the bit in the multicast table corresponding to the hash value. 7677 * 7678 * hw - Struct containing variables accessed by shared code 7679 * hash_value - Multicast address hash value 7680 *****************************************************************************/ 7681 void 7682 em_mta_set(struct em_hw *hw, uint32_t hash_value) 7683 { 7684 uint32_t hash_bit, hash_reg; 7685 uint32_t mta; 7686 uint32_t temp; 7687 /* 7688 * The MTA is a register array of 128 32-bit registers. It is treated 7689 * like an array of 4096 bits. We want to set bit 7690 * BitArray[hash_value]. So we figure out what register the bit is 7691 * in, read it, OR in the new bit, then write back the new value. 7692 * The register is determined by the upper 7 bits of the hash value 7693 * and the bit within that register are determined by the lower 5 7694 * bits of the value. 7695 */ 7696 hash_reg = (hash_value >> 5) & 0x7F; 7697 if (IS_ICH8(hw->mac_type)) 7698 hash_reg &= 0x1F; 7699 7700 hash_bit = hash_value & 0x1F; 7701 7702 mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg); 7703 7704 mta |= (1 << hash_bit); 7705 /* 7706 * If we are on an 82544 and we are trying to write an odd offset in 7707 * the MTA, save off the previous entry before writing and restore 7708 * the old value after writing. 7709 */ 7710 if ((hw->mac_type == em_82544) && ((hash_reg & 0x1) == 1)) { 7711 temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1)); 7712 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta); 7713 E1000_WRITE_FLUSH(hw); 7714 E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp); 7715 E1000_WRITE_FLUSH(hw); 7716 } else { 7717 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta); 7718 E1000_WRITE_FLUSH(hw); 7719 } 7720 } 7721 7722 /****************************************************************************** 7723 * Puts an ethernet address into a receive address register. 7724 * 7725 * hw - Struct containing variables accessed by shared code 7726 * addr - Address to put into receive address register 7727 * index - Receive address register to write 7728 *****************************************************************************/ 7729 void 7730 em_rar_set(struct em_hw *hw, uint8_t *addr, uint32_t index) 7731 { 7732 uint32_t rar_low, rar_high; 7733 /* 7734 * HW expects these in little endian so we reverse the byte order 7735 * from network order (big endian) to little endian 7736 */ 7737 rar_low = ((uint32_t) addr[0] | ((uint32_t) addr[1] << 8) | 7738 ((uint32_t) addr[2] << 16) | ((uint32_t) addr[3] << 24)); 7739 rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8)); 7740 /* 7741 * Disable Rx and flush all Rx frames before enabling RSS to avoid Rx 7742 * unit hang. 7743 * 7744 * Description: If there are any Rx frames queued up or otherwise 7745 * present in the HW before RSS is enabled, and then we enable RSS, 7746 * the HW Rx unit will hang. To work around this issue, we have to 7747 * disable receives and flush out all Rx frames before we enable RSS. 7748 * To do so, we modify we redirect all Rx traffic to manageability 7749 * and then reset the HW. This flushes away Rx frames, and (since the 7750 * redirections to manageability persists across resets) keeps new 7751 * ones from coming in while we work. Then, we clear the Address 7752 * Valid AV bit for all MAC addresses and undo the re-direction to 7753 * manageability. Now, frames are coming in again, but the MAC won't 7754 * accept them, so far so good. We now proceed to initialize RSS (if 7755 * necessary) and configure the Rx unit. Last, we re-enable the AV 7756 * bits and continue on our merry way. 7757 */ 7758 switch (hw->mac_type) { 7759 case em_82571: 7760 case em_82572: 7761 case em_80003es2lan: 7762 if (hw->leave_av_bit_off == TRUE) 7763 break; 7764 default: 7765 /* Indicate to hardware the Address is Valid. */ 7766 rar_high |= E1000_RAH_AV; 7767 break; 7768 } 7769 7770 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low); 7771 E1000_WRITE_FLUSH(hw); 7772 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high); 7773 E1000_WRITE_FLUSH(hw); 7774 } 7775 7776 /****************************************************************************** 7777 * Clears the VLAN filer table 7778 * 7779 * hw - Struct containing variables accessed by shared code 7780 *****************************************************************************/ 7781 STATIC void 7782 em_clear_vfta(struct em_hw *hw) 7783 { 7784 uint32_t offset; 7785 uint32_t vfta_value = 0; 7786 uint32_t vfta_offset = 0; 7787 uint32_t vfta_bit_in_reg = 0; 7788 if (IS_ICH8(hw->mac_type)) 7789 return; 7790 7791 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) { 7792 if (hw->mng_cookie.vlan_id != 0) { 7793 /* 7794 * The VFTA is a 4096b bit-field, each identifying a 7795 * single VLAN ID. The following operations 7796 * determine which 32b entry (i.e. offset) into the 7797 * array we want to set the VLAN ID (i.e. bit) of the 7798 * manageability unit. 7799 */ 7800 vfta_offset = (hw->mng_cookie.vlan_id >> 7801 E1000_VFTA_ENTRY_SHIFT) & E1000_VFTA_ENTRY_MASK; 7802 7803 vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id & 7804 E1000_VFTA_ENTRY_BIT_SHIFT_MASK); 7805 } 7806 } 7807 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 7808 /* 7809 * If the offset we want to clear is the same offset of the 7810 * manageability VLAN ID, then clear all bits except that of 7811 * the manageability unit 7812 */ 7813 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; 7814 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value); 7815 E1000_WRITE_FLUSH(hw); 7816 } 7817 } 7818 7819 /* 7820 * Due to hw errata, if the host tries to configure the VFTA register 7821 * while performing queries from the BMC or DMA, then the VFTA in some 7822 * cases won't be written. 7823 */ 7824 void 7825 em_clear_vfta_i350(struct em_hw *hw) 7826 { 7827 uint32_t offset; 7828 int i; 7829 7830 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 7831 for (i = 0; i < 10; i++) 7832 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0); 7833 E1000_WRITE_FLUSH(hw); 7834 } 7835 } 7836 7837 STATIC int32_t 7838 em_id_led_init(struct em_hw *hw) 7839 { 7840 uint32_t ledctl; 7841 const uint32_t ledctl_mask = 0x000000FF; 7842 const uint32_t ledctl_on = E1000_LEDCTL_MODE_LED_ON; 7843 const uint32_t ledctl_off = E1000_LEDCTL_MODE_LED_OFF; 7844 uint16_t eeprom_data, i, temp; 7845 const uint16_t led_mask = 0x0F; 7846 DEBUGFUNC("em_id_led_init"); 7847 7848 if (hw->mac_type < em_82540 || hw->mac_type == em_icp_xxxx) { 7849 /* Nothing to do */ 7850 return E1000_SUCCESS; 7851 } 7852 ledctl = E1000_READ_REG(hw, LEDCTL); 7853 hw->ledctl_default = ledctl; 7854 hw->ledctl_mode1 = hw->ledctl_default; 7855 hw->ledctl_mode2 = hw->ledctl_default; 7856 7857 if (em_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) { 7858 DEBUGOUT("EEPROM Read Error\n"); 7859 return -E1000_ERR_EEPROM; 7860 } 7861 if ((hw->mac_type == em_82573) && 7862 (eeprom_data == ID_LED_RESERVED_82573)) 7863 eeprom_data = ID_LED_DEFAULT_82573; 7864 else if ((eeprom_data == ID_LED_RESERVED_0000) || 7865 (eeprom_data == ID_LED_RESERVED_FFFF)) { 7866 if (hw->mac_type == em_ich8lan || 7867 hw->mac_type == em_ich9lan || 7868 hw->mac_type == em_ich10lan) // XXX 7869 eeprom_data = ID_LED_DEFAULT_ICH8LAN; 7870 else 7871 eeprom_data = ID_LED_DEFAULT; 7872 } 7873 for (i = 0; i < 4; i++) { 7874 temp = (eeprom_data >> (i << 2)) & led_mask; 7875 switch (temp) { 7876 case ID_LED_ON1_DEF2: 7877 case ID_LED_ON1_ON2: 7878 case ID_LED_ON1_OFF2: 7879 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 7880 hw->ledctl_mode1 |= ledctl_on << (i << 3); 7881 break; 7882 case ID_LED_OFF1_DEF2: 7883 case ID_LED_OFF1_ON2: 7884 case ID_LED_OFF1_OFF2: 7885 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 7886 hw->ledctl_mode1 |= ledctl_off << (i << 3); 7887 break; 7888 default: 7889 /* Do nothing */ 7890 break; 7891 } 7892 switch (temp) { 7893 case ID_LED_DEF1_ON2: 7894 case ID_LED_ON1_ON2: 7895 case ID_LED_OFF1_ON2: 7896 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 7897 hw->ledctl_mode2 |= ledctl_on << (i << 3); 7898 break; 7899 case ID_LED_DEF1_OFF2: 7900 case ID_LED_ON1_OFF2: 7901 case ID_LED_OFF1_OFF2: 7902 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 7903 hw->ledctl_mode2 |= ledctl_off << (i << 3); 7904 break; 7905 default: 7906 /* Do nothing */ 7907 break; 7908 } 7909 } 7910 return E1000_SUCCESS; 7911 } 7912 7913 /****************************************************************************** 7914 * Clears all hardware statistics counters. 7915 * 7916 * hw - Struct containing variables accessed by shared code 7917 *****************************************************************************/ 7918 void 7919 em_clear_hw_cntrs(struct em_hw *hw) 7920 { 7921 volatile uint32_t temp; 7922 temp = E1000_READ_REG(hw, CRCERRS); 7923 temp = E1000_READ_REG(hw, SYMERRS); 7924 temp = E1000_READ_REG(hw, MPC); 7925 temp = E1000_READ_REG(hw, SCC); 7926 temp = E1000_READ_REG(hw, ECOL); 7927 temp = E1000_READ_REG(hw, MCC); 7928 temp = E1000_READ_REG(hw, LATECOL); 7929 temp = E1000_READ_REG(hw, COLC); 7930 temp = E1000_READ_REG(hw, DC); 7931 temp = E1000_READ_REG(hw, SEC); 7932 temp = E1000_READ_REG(hw, RLEC); 7933 temp = E1000_READ_REG(hw, XONRXC); 7934 temp = E1000_READ_REG(hw, XONTXC); 7935 temp = E1000_READ_REG(hw, XOFFRXC); 7936 temp = E1000_READ_REG(hw, XOFFTXC); 7937 temp = E1000_READ_REG(hw, FCRUC); 7938 7939 if (!IS_ICH8(hw->mac_type)) { 7940 temp = E1000_READ_REG(hw, PRC64); 7941 temp = E1000_READ_REG(hw, PRC127); 7942 temp = E1000_READ_REG(hw, PRC255); 7943 temp = E1000_READ_REG(hw, PRC511); 7944 temp = E1000_READ_REG(hw, PRC1023); 7945 temp = E1000_READ_REG(hw, PRC1522); 7946 } 7947 temp = E1000_READ_REG(hw, GPRC); 7948 temp = E1000_READ_REG(hw, BPRC); 7949 temp = E1000_READ_REG(hw, MPRC); 7950 temp = E1000_READ_REG(hw, GPTC); 7951 temp = E1000_READ_REG(hw, GORCL); 7952 temp = E1000_READ_REG(hw, GORCH); 7953 temp = E1000_READ_REG(hw, GOTCL); 7954 temp = E1000_READ_REG(hw, GOTCH); 7955 temp = E1000_READ_REG(hw, RNBC); 7956 temp = E1000_READ_REG(hw, RUC); 7957 temp = E1000_READ_REG(hw, RFC); 7958 temp = E1000_READ_REG(hw, ROC); 7959 temp = E1000_READ_REG(hw, RJC); 7960 temp = E1000_READ_REG(hw, TORL); 7961 temp = E1000_READ_REG(hw, TORH); 7962 temp = E1000_READ_REG(hw, TOTL); 7963 temp = E1000_READ_REG(hw, TOTH); 7964 temp = E1000_READ_REG(hw, TPR); 7965 temp = E1000_READ_REG(hw, TPT); 7966 7967 if (!IS_ICH8(hw->mac_type)) { 7968 temp = E1000_READ_REG(hw, PTC64); 7969 temp = E1000_READ_REG(hw, PTC127); 7970 temp = E1000_READ_REG(hw, PTC255); 7971 temp = E1000_READ_REG(hw, PTC511); 7972 temp = E1000_READ_REG(hw, PTC1023); 7973 temp = E1000_READ_REG(hw, PTC1522); 7974 } 7975 temp = E1000_READ_REG(hw, MPTC); 7976 temp = E1000_READ_REG(hw, BPTC); 7977 7978 if (hw->mac_type < em_82543) 7979 return; 7980 7981 temp = E1000_READ_REG(hw, ALGNERRC); 7982 temp = E1000_READ_REG(hw, RXERRC); 7983 temp = E1000_READ_REG(hw, TNCRS); 7984 temp = E1000_READ_REG(hw, CEXTERR); 7985 temp = E1000_READ_REG(hw, TSCTC); 7986 temp = E1000_READ_REG(hw, TSCTFC); 7987 7988 if (hw->mac_type <= em_82544 7989 || hw->mac_type == em_icp_xxxx) 7990 return; 7991 7992 temp = E1000_READ_REG(hw, MGTPRC); 7993 temp = E1000_READ_REG(hw, MGTPDC); 7994 temp = E1000_READ_REG(hw, MGTPTC); 7995 7996 if (hw->mac_type <= em_82547_rev_2) 7997 return; 7998 7999 temp = E1000_READ_REG(hw, IAC); 8000 temp = E1000_READ_REG(hw, ICRXOC); 8001 8002 if (hw->phy_type == em_phy_82577 || 8003 hw->phy_type == em_phy_82578 || 8004 hw->phy_type == em_phy_82579 || 8005 hw->phy_type == em_phy_i217) { 8006 uint16_t phy_data; 8007 8008 em_read_phy_reg(hw, HV_SCC_UPPER, &phy_data); 8009 em_read_phy_reg(hw, HV_SCC_LOWER, &phy_data); 8010 em_read_phy_reg(hw, HV_ECOL_UPPER, &phy_data); 8011 em_read_phy_reg(hw, HV_ECOL_LOWER, &phy_data); 8012 em_read_phy_reg(hw, HV_MCC_UPPER, &phy_data); 8013 em_read_phy_reg(hw, HV_MCC_LOWER, &phy_data); 8014 em_read_phy_reg(hw, HV_LATECOL_UPPER, &phy_data); 8015 em_read_phy_reg(hw, HV_LATECOL_LOWER, &phy_data); 8016 em_read_phy_reg(hw, HV_COLC_UPPER, &phy_data); 8017 em_read_phy_reg(hw, HV_COLC_LOWER, &phy_data); 8018 em_read_phy_reg(hw, HV_DC_UPPER, &phy_data); 8019 em_read_phy_reg(hw, HV_DC_LOWER, &phy_data); 8020 em_read_phy_reg(hw, HV_TNCRS_UPPER, &phy_data); 8021 em_read_phy_reg(hw, HV_TNCRS_LOWER, &phy_data); 8022 } 8023 8024 if (hw->mac_type == em_ich8lan || 8025 hw->mac_type == em_ich9lan || 8026 hw->mac_type == em_ich10lan || 8027 hw->mac_type == em_pchlan || 8028 (hw->mac_type != em_pch2lan && hw->mac_type != em_pch_lpt && 8029 hw->mac_type != em_pch_spt && hw->mac_type != em_pch_cnp)) 8030 return; 8031 8032 temp = E1000_READ_REG(hw, ICRXPTC); 8033 temp = E1000_READ_REG(hw, ICRXATC); 8034 temp = E1000_READ_REG(hw, ICTXPTC); 8035 temp = E1000_READ_REG(hw, ICTXATC); 8036 temp = E1000_READ_REG(hw, ICTXQEC); 8037 temp = E1000_READ_REG(hw, ICTXQMTC); 8038 temp = E1000_READ_REG(hw, ICRXDMTC); 8039 } 8040 8041 /****************************************************************************** 8042 * Gets the current PCI bus type, speed, and width of the hardware 8043 * 8044 * hw - Struct containing variables accessed by shared code 8045 *****************************************************************************/ 8046 void 8047 em_get_bus_info(struct em_hw *hw) 8048 { 8049 int32_t ret_val; 8050 uint16_t pci_ex_link_status; 8051 uint32_t status; 8052 switch (hw->mac_type) { 8053 case em_82542_rev2_0: 8054 case em_82542_rev2_1: 8055 hw->bus_type = em_bus_type_unknown; 8056 hw->bus_speed = em_bus_speed_unknown; 8057 hw->bus_width = em_bus_width_unknown; 8058 break; 8059 case em_icp_xxxx: 8060 hw->bus_type = em_bus_type_cpp; 8061 hw->bus_speed = em_bus_speed_unknown; 8062 hw->bus_width = em_bus_width_unknown; 8063 break; 8064 case em_82571: 8065 case em_82572: 8066 case em_82573: 8067 case em_82574: 8068 case em_82575: 8069 case em_82576: 8070 case em_82580: 8071 case em_80003es2lan: 8072 case em_i210: 8073 case em_i350: 8074 hw->bus_type = em_bus_type_pci_express; 8075 hw->bus_speed = em_bus_speed_2500; 8076 ret_val = em_read_pcie_cap_reg(hw, PCI_EX_LINK_STATUS, 8077 &pci_ex_link_status); 8078 if (ret_val) 8079 hw->bus_width = em_bus_width_unknown; 8080 else 8081 hw->bus_width = (pci_ex_link_status & 8082 PCI_EX_LINK_WIDTH_MASK) >> PCI_EX_LINK_WIDTH_SHIFT; 8083 break; 8084 case em_ich8lan: 8085 case em_ich9lan: 8086 case em_ich10lan: 8087 case em_pchlan: 8088 case em_pch2lan: 8089 case em_pch_lpt: 8090 case em_pch_spt: 8091 case em_pch_cnp: 8092 hw->bus_type = em_bus_type_pci_express; 8093 hw->bus_speed = em_bus_speed_2500; 8094 hw->bus_width = em_bus_width_pciex_1; 8095 break; 8096 default: 8097 status = E1000_READ_REG(hw, STATUS); 8098 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ? 8099 em_bus_type_pcix : em_bus_type_pci; 8100 8101 if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) { 8102 hw->bus_speed = (hw->bus_type == em_bus_type_pci) ? 8103 em_bus_speed_66 : em_bus_speed_120; 8104 } else if (hw->bus_type == em_bus_type_pci) { 8105 hw->bus_speed = (status & E1000_STATUS_PCI66) ? 8106 em_bus_speed_66 : em_bus_speed_33; 8107 } else { 8108 switch (status & E1000_STATUS_PCIX_SPEED) { 8109 case E1000_STATUS_PCIX_SPEED_66: 8110 hw->bus_speed = em_bus_speed_66; 8111 break; 8112 case E1000_STATUS_PCIX_SPEED_100: 8113 hw->bus_speed = em_bus_speed_100; 8114 break; 8115 case E1000_STATUS_PCIX_SPEED_133: 8116 hw->bus_speed = em_bus_speed_133; 8117 break; 8118 default: 8119 hw->bus_speed = em_bus_speed_reserved; 8120 break; 8121 } 8122 } 8123 hw->bus_width = (status & E1000_STATUS_BUS64) ? 8124 em_bus_width_64 : em_bus_width_32; 8125 break; 8126 } 8127 } 8128 8129 /****************************************************************************** 8130 * Writes a value to one of the devices registers using port I/O (as opposed to 8131 * memory mapped I/O). Only 82544 and newer devices support port I/O. 8132 * 8133 * hw - Struct containing variables accessed by shared code 8134 * offset - offset to write to 8135 * value - value to write 8136 *****************************************************************************/ 8137 STATIC void 8138 em_write_reg_io(struct em_hw *hw, uint32_t offset, uint32_t value) 8139 { 8140 unsigned long io_addr = hw->io_base; 8141 unsigned long io_data = hw->io_base + 4; 8142 em_io_write(hw, io_addr, offset); 8143 em_io_write(hw, io_data, value); 8144 } 8145 8146 /****************************************************************************** 8147 * Estimates the cable length. 8148 * 8149 * hw - Struct containing variables accessed by shared code 8150 * min_length - The estimated minimum length 8151 * max_length - The estimated maximum length 8152 * 8153 * returns: - E1000_ERR_XXX 8154 * E1000_SUCCESS 8155 * 8156 * This function always returns a ranged length (minimum & maximum). 8157 * So for M88 phy's, this function interprets the one value returned from the 8158 * register to the minimum and maximum range. 8159 * For IGP phy's, the function calculates the range by the AGC registers. 8160 *****************************************************************************/ 8161 STATIC int32_t 8162 em_get_cable_length(struct em_hw *hw, uint16_t *min_length, 8163 uint16_t *max_length) 8164 { 8165 int32_t ret_val; 8166 uint16_t agc_value = 0; 8167 uint16_t i, phy_data; 8168 uint16_t cable_length; 8169 DEBUGFUNC("em_get_cable_length"); 8170 8171 *min_length = *max_length = 0; 8172 8173 /* Use old method for Phy older than IGP */ 8174 if (hw->phy_type == em_phy_m88 || 8175 hw->phy_type == em_phy_oem || 8176 hw->phy_type == em_phy_82578) { 8177 8178 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, 8179 &phy_data); 8180 if (ret_val) 8181 return ret_val; 8182 cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 8183 M88E1000_PSSR_CABLE_LENGTH_SHIFT; 8184 8185 /* Convert the enum value to ranged values */ 8186 switch (cable_length) { 8187 case em_cable_length_50: 8188 *min_length = 0; 8189 *max_length = em_igp_cable_length_50; 8190 break; 8191 case em_cable_length_50_80: 8192 *min_length = em_igp_cable_length_50; 8193 *max_length = em_igp_cable_length_80; 8194 break; 8195 case em_cable_length_80_110: 8196 *min_length = em_igp_cable_length_80; 8197 *max_length = em_igp_cable_length_110; 8198 break; 8199 case em_cable_length_110_140: 8200 *min_length = em_igp_cable_length_110; 8201 *max_length = em_igp_cable_length_140; 8202 break; 8203 case em_cable_length_140: 8204 *min_length = em_igp_cable_length_140; 8205 *max_length = em_igp_cable_length_170; 8206 break; 8207 default: 8208 return -E1000_ERR_PHY; 8209 break; 8210 } 8211 } else if (hw->phy_type == em_phy_rtl8211) { 8212 /* no cable length info on RTL8211, fake */ 8213 *min_length = 0; 8214 *max_length = em_igp_cable_length_50; 8215 } else if (hw->phy_type == em_phy_gg82563) { 8216 ret_val = em_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE, 8217 &phy_data); 8218 if (ret_val) 8219 return ret_val; 8220 cable_length = phy_data & GG82563_DSPD_CABLE_LENGTH; 8221 8222 switch (cable_length) { 8223 case em_gg_cable_length_60: 8224 *min_length = 0; 8225 *max_length = em_igp_cable_length_60; 8226 break; 8227 case em_gg_cable_length_60_115: 8228 *min_length = em_igp_cable_length_60; 8229 *max_length = em_igp_cable_length_115; 8230 break; 8231 case em_gg_cable_length_115_150: 8232 *min_length = em_igp_cable_length_115; 8233 *max_length = em_igp_cable_length_150; 8234 break; 8235 case em_gg_cable_length_150: 8236 *min_length = em_igp_cable_length_150; 8237 *max_length = em_igp_cable_length_180; 8238 break; 8239 default: 8240 return -E1000_ERR_PHY; 8241 break; 8242 } 8243 } else if (hw->phy_type == em_phy_igp) { /* For IGP PHY */ 8244 uint16_t cur_agc_value; 8245 uint16_t min_agc_value = 8246 IGP01E1000_AGC_LENGTH_TABLE_SIZE; 8247 uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = 8248 {IGP01E1000_PHY_AGC_A, IGP01E1000_PHY_AGC_B, 8249 IGP01E1000_PHY_AGC_C, IGP01E1000_PHY_AGC_D}; 8250 8251 /* Read the AGC registers for all channels */ 8252 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 8253 ret_val = em_read_phy_reg(hw, agc_reg_array[i], 8254 &phy_data); 8255 if (ret_val) 8256 return ret_val; 8257 8258 cur_agc_value = phy_data >> 8259 IGP01E1000_AGC_LENGTH_SHIFT; 8260 8261 /* Value bound check. */ 8262 if ((cur_agc_value >= 8263 IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) || 8264 (cur_agc_value == 0)) 8265 return -E1000_ERR_PHY; 8266 8267 agc_value += cur_agc_value; 8268 8269 /* Update minimal AGC value. */ 8270 if (min_agc_value > cur_agc_value) 8271 min_agc_value = cur_agc_value; 8272 } 8273 8274 /* Remove the minimal AGC result for length < 50m */ 8275 if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * 8276 em_igp_cable_length_50) { 8277 agc_value -= min_agc_value; 8278 8279 /* 8280 * Get the average length of the remaining 3 channels 8281 */ 8282 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1); 8283 } else { 8284 /* Get the average length of all the 4 channels. */ 8285 agc_value /= IGP01E1000_PHY_CHANNEL_NUM; 8286 } 8287 8288 /* Set the range of the calculated length. */ 8289 *min_length = ((em_igp_cable_length_table[agc_value] - 8290 IGP01E1000_AGC_RANGE) > 0) ? 8291 (em_igp_cable_length_table[agc_value] - 8292 IGP01E1000_AGC_RANGE) : 0; 8293 *max_length = em_igp_cable_length_table[agc_value] + 8294 IGP01E1000_AGC_RANGE; 8295 } else if (hw->phy_type == em_phy_igp_2 || 8296 hw->phy_type == em_phy_igp_3) { 8297 uint16_t cur_agc_index, max_agc_index = 0; 8298 uint16_t min_agc_index = IGP02E1000_AGC_LENGTH_TABLE_SIZE - 1; 8299 uint16_t agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = 8300 {IGP02E1000_PHY_AGC_A, IGP02E1000_PHY_AGC_B, 8301 IGP02E1000_PHY_AGC_C, IGP02E1000_PHY_AGC_D}; 8302 /* Read the AGC registers for all channels */ 8303 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { 8304 ret_val = em_read_phy_reg(hw, agc_reg_array[i], 8305 &phy_data); 8306 if (ret_val) 8307 return ret_val; 8308 /* 8309 * Getting bits 15:9, which represent the combination 8310 * of course and fine gain values. The result is a 8311 * number that can be put into the lookup table to 8312 * obtain the approximate cable length. 8313 */ 8314 cur_agc_index = (phy_data >> 8315 IGP02E1000_AGC_LENGTH_SHIFT) & 8316 IGP02E1000_AGC_LENGTH_MASK; 8317 8318 /* Array index bound check. */ 8319 if ((cur_agc_index >= IGP02E1000_AGC_LENGTH_TABLE_SIZE) 8320 || (cur_agc_index == 0)) 8321 return -E1000_ERR_PHY; 8322 8323 /* Remove min & max AGC values from calculation. */ 8324 if (em_igp_2_cable_length_table[min_agc_index] > 8325 em_igp_2_cable_length_table[cur_agc_index]) 8326 min_agc_index = cur_agc_index; 8327 if (em_igp_2_cable_length_table[max_agc_index] < 8328 em_igp_2_cable_length_table[cur_agc_index]) 8329 max_agc_index = cur_agc_index; 8330 8331 agc_value += em_igp_2_cable_length_table 8332 [cur_agc_index]; 8333 } 8334 8335 agc_value -= (em_igp_2_cable_length_table[min_agc_index] + 8336 em_igp_2_cable_length_table[max_agc_index]); 8337 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); 8338 /* 8339 * Calculate cable length with the error range of +/- 10 8340 * meters. 8341 */ 8342 *min_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ? 8343 (agc_value - IGP02E1000_AGC_RANGE) : 0; 8344 *max_length = agc_value + IGP02E1000_AGC_RANGE; 8345 } 8346 return E1000_SUCCESS; 8347 } 8348 8349 /****************************************************************************** 8350 * Check if Downshift occured 8351 * 8352 * hw - Struct containing variables accessed by shared code 8353 * downshift - output parameter : 0 - No Downshift ocured. 8354 * 1 - Downshift ocured. 8355 * 8356 * returns: - E1000_ERR_XXX 8357 * E1000_SUCCESS 8358 * 8359 * For phy's older then IGP, this function reads the Downshift bit in the Phy 8360 * Specific Status register. For IGP phy's, it reads the Downgrade bit in the 8361 * Link Health register. In IGP this bit is latched high, so the driver must 8362 * read it immediately after link is established. 8363 *****************************************************************************/ 8364 STATIC int32_t 8365 em_check_downshift(struct em_hw *hw) 8366 { 8367 int32_t ret_val; 8368 uint16_t phy_data; 8369 DEBUGFUNC("em_check_downshift"); 8370 8371 if (hw->phy_type == em_phy_igp || 8372 hw->phy_type == em_phy_igp_3 || 8373 hw->phy_type == em_phy_igp_2) { 8374 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH, 8375 &phy_data); 8376 if (ret_val) 8377 return ret_val; 8378 8379 hw->speed_downgraded = (phy_data & 8380 IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0; 8381 } else if ((hw->phy_type == em_phy_m88) || 8382 (hw->phy_type == em_phy_gg82563) || 8383 (hw->phy_type == em_phy_oem) || 8384 (hw->phy_type == em_phy_82578)) { 8385 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, 8386 &phy_data); 8387 if (ret_val) 8388 return ret_val; 8389 8390 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >> 8391 M88E1000_PSSR_DOWNSHIFT_SHIFT; 8392 } else if (hw->phy_type == em_phy_ife) { 8393 /* em_phy_ife supports 10/100 speed only */ 8394 hw->speed_downgraded = FALSE; 8395 } 8396 return E1000_SUCCESS; 8397 } 8398 8399 /***************************************************************************** 8400 * 8401 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a 8402 * gigabit link is achieved to improve link quality. 8403 * 8404 * hw: Struct containing variables accessed by shared code 8405 * 8406 * returns: - E1000_ERR_PHY if fail to read/write the PHY 8407 * E1000_SUCCESS at any other case. 8408 * 8409 ****************************************************************************/ 8410 STATIC int32_t 8411 em_config_dsp_after_link_change(struct em_hw *hw, boolean_t link_up) 8412 { 8413 int32_t ret_val; 8414 uint16_t phy_data, phy_saved_data, speed, duplex, i; 8415 uint16_t dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = 8416 {IGP01E1000_PHY_AGC_PARAM_A, IGP01E1000_PHY_AGC_PARAM_B, 8417 IGP01E1000_PHY_AGC_PARAM_C, IGP01E1000_PHY_AGC_PARAM_D}; 8418 uint16_t min_length, max_length; 8419 DEBUGFUNC("em_config_dsp_after_link_change"); 8420 8421 if (hw->phy_type != em_phy_igp) 8422 return E1000_SUCCESS; 8423 8424 if (link_up) { 8425 ret_val = em_get_speed_and_duplex(hw, &speed, &duplex); 8426 if (ret_val) { 8427 DEBUGOUT("Error getting link speed and duplex\n"); 8428 return ret_val; 8429 } 8430 if (speed == SPEED_1000) { 8431 8432 ret_val = em_get_cable_length(hw, &min_length, &max_length); 8433 if (ret_val) 8434 return ret_val; 8435 8436 if ((hw->dsp_config_state == em_dsp_config_enabled) && 8437 min_length >= em_igp_cable_length_50) { 8438 8439 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; 8440 i++) { 8441 ret_val = em_read_phy_reg(hw, 8442 dsp_reg_array[i], &phy_data); 8443 if (ret_val) 8444 return ret_val; 8445 8446 phy_data &= 8447 ~IGP01E1000_PHY_EDAC_MU_INDEX; 8448 8449 ret_val = em_write_phy_reg(hw, 8450 dsp_reg_array[i], phy_data); 8451 if (ret_val) 8452 return ret_val; 8453 } 8454 hw->dsp_config_state = em_dsp_config_activated; 8455 } 8456 if ((hw->ffe_config_state == em_ffe_config_enabled) && 8457 (min_length < em_igp_cable_length_50)) { 8458 8459 uint16_t ffe_idle_err_timeout = 8460 FFE_IDLE_ERR_COUNT_TIMEOUT_20; 8461 uint32_t idle_errs = 0; 8462 /* clear previous idle error counts */ 8463 ret_val = em_read_phy_reg(hw, PHY_1000T_STATUS, 8464 &phy_data); 8465 if (ret_val) 8466 return ret_val; 8467 8468 for (i = 0; i < ffe_idle_err_timeout; i++) { 8469 usec_delay(1000); 8470 ret_val = em_read_phy_reg(hw, 8471 PHY_1000T_STATUS, &phy_data); 8472 if (ret_val) 8473 return ret_val; 8474 8475 idle_errs += (phy_data & 8476 SR_1000T_IDLE_ERROR_CNT); 8477 if (idle_errs > 8478 SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) { 8479 hw->ffe_config_state = 8480 em_ffe_config_active; 8481 8482 ret_val = em_write_phy_reg(hw, 8483 IGP01E1000_PHY_DSP_FFE, 8484 IGP01E1000_PHY_DSP_FFE_CM_CP); 8485 if (ret_val) 8486 return ret_val; 8487 break; 8488 } 8489 if (idle_errs) 8490 ffe_idle_err_timeout = 8491 FFE_IDLE_ERR_COUNT_TIMEOUT_100; 8492 } 8493 } 8494 } 8495 } else { 8496 if (hw->dsp_config_state == em_dsp_config_activated) { 8497 /* 8498 * Save off the current value of register 0x2F5B to 8499 * be restored at the end of the routines. 8500 */ 8501 ret_val = em_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 8502 8503 if (ret_val) 8504 return ret_val; 8505 8506 /* Disable the PHY transmitter */ 8507 ret_val = em_write_phy_reg(hw, 0x2F5B, 0x0003); 8508 8509 if (ret_val) 8510 return ret_val; 8511 8512 msec_delay_irq(20); 8513 8514 ret_val = em_write_phy_reg(hw, 0x0000, 8515 IGP01E1000_IEEE_FORCE_GIGA); 8516 if (ret_val) 8517 return ret_val; 8518 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 8519 ret_val = em_read_phy_reg(hw, dsp_reg_array[i], 8520 &phy_data); 8521 if (ret_val) 8522 return ret_val; 8523 8524 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; 8525 phy_data |= 8526 IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS; 8527 8528 ret_val = em_write_phy_reg(hw, 8529 dsp_reg_array[i], phy_data); 8530 if (ret_val) 8531 return ret_val; 8532 } 8533 8534 ret_val = em_write_phy_reg(hw, 0x0000, 8535 IGP01E1000_IEEE_RESTART_AUTONEG); 8536 if (ret_val) 8537 return ret_val; 8538 8539 msec_delay_irq(20); 8540 8541 /* Now enable the transmitter */ 8542 ret_val = em_write_phy_reg(hw, 0x2F5B, phy_saved_data); 8543 8544 if (ret_val) 8545 return ret_val; 8546 8547 hw->dsp_config_state = em_dsp_config_enabled; 8548 } 8549 if (hw->ffe_config_state == em_ffe_config_active) { 8550 /* 8551 * Save off the current value of register 0x2F5B to 8552 * be restored at the end of the routines. 8553 */ 8554 ret_val = em_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 8555 8556 if (ret_val) 8557 return ret_val; 8558 8559 /* Disable the PHY transmitter */ 8560 ret_val = em_write_phy_reg(hw, 0x2F5B, 0x0003); 8561 8562 if (ret_val) 8563 return ret_val; 8564 8565 msec_delay_irq(20); 8566 8567 ret_val = em_write_phy_reg(hw, 0x0000, 8568 IGP01E1000_IEEE_FORCE_GIGA); 8569 if (ret_val) 8570 return ret_val; 8571 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE, 8572 IGP01E1000_PHY_DSP_FFE_DEFAULT); 8573 if (ret_val) 8574 return ret_val; 8575 8576 ret_val = em_write_phy_reg(hw, 0x0000, 8577 IGP01E1000_IEEE_RESTART_AUTONEG); 8578 if (ret_val) 8579 return ret_val; 8580 8581 msec_delay_irq(20); 8582 8583 /* Now enable the transmitter */ 8584 ret_val = em_write_phy_reg(hw, 0x2F5B, phy_saved_data); 8585 8586 if (ret_val) 8587 return ret_val; 8588 8589 hw->ffe_config_state = em_ffe_config_enabled; 8590 } 8591 } 8592 return E1000_SUCCESS; 8593 } 8594 8595 /***************************************************************************** 8596 * Set PHY to class A mode 8597 * Assumes the following operations will follow to enable the new class mode. 8598 * 1. Do a PHY soft reset 8599 * 2. Restart auto-negotiation or force link. 8600 * 8601 * hw - Struct containing variables accessed by shared code 8602 ****************************************************************************/ 8603 static int32_t 8604 em_set_phy_mode(struct em_hw *hw) 8605 { 8606 int32_t ret_val; 8607 uint16_t eeprom_data; 8608 DEBUGFUNC("em_set_phy_mode"); 8609 8610 if ((hw->mac_type == em_82545_rev_3) && 8611 (hw->media_type == em_media_type_copper)) { 8612 ret_val = em_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, 8613 &eeprom_data); 8614 if (ret_val) { 8615 return ret_val; 8616 } 8617 if ((eeprom_data != EEPROM_RESERVED_WORD) && 8618 (eeprom_data & EEPROM_PHY_CLASS_A)) { 8619 ret_val = em_write_phy_reg(hw, 8620 M88E1000_PHY_PAGE_SELECT, 0x000B); 8621 if (ret_val) 8622 return ret_val; 8623 ret_val = em_write_phy_reg(hw, 8624 M88E1000_PHY_GEN_CONTROL, 0x8104); 8625 if (ret_val) 8626 return ret_val; 8627 8628 hw->phy_reset_disable = FALSE; 8629 } 8630 } 8631 return E1000_SUCCESS; 8632 } 8633 8634 /***************************************************************************** 8635 * 8636 * This function sets the lplu state according to the active flag. When 8637 * activating lplu this function also disables smart speed and vise versa. 8638 * lplu will not be activated unless the device autonegotiation advertisement 8639 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. 8640 * hw: Struct containing variables accessed by shared code 8641 * active - true to enable lplu false to disable lplu. 8642 * 8643 * returns: - E1000_ERR_PHY if fail to read/write the PHY 8644 * E1000_SUCCESS at any other case. 8645 * 8646 ****************************************************************************/ 8647 STATIC int32_t 8648 em_set_d3_lplu_state(struct em_hw *hw, boolean_t active) 8649 { 8650 uint32_t phy_ctrl = 0; 8651 int32_t ret_val; 8652 uint16_t phy_data; 8653 DEBUGFUNC("em_set_d3_lplu_state"); 8654 8655 if (hw->phy_type != em_phy_igp && hw->phy_type != em_phy_igp_2 8656 && hw->phy_type != em_phy_igp_3) 8657 return E1000_SUCCESS; 8658 /* 8659 * During driver activity LPLU should not be used or it will attain 8660 * link from the lowest speeds starting from 10Mbps. The capability 8661 * is used for Dx transitions and states 8662 */ 8663 if (hw->mac_type == em_82541_rev_2 || hw->mac_type == em_82547_rev_2) { 8664 ret_val = em_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data); 8665 if (ret_val) 8666 return ret_val; 8667 } else if (IS_ICH8(hw->mac_type)) { 8668 /* 8669 * MAC writes into PHY register based on the state transition 8670 * and start auto-negotiation. SW driver can overwrite the 8671 * settings in CSR PHY power control E1000_PHY_CTRL register. 8672 */ 8673 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); 8674 } else { 8675 ret_val = em_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, 8676 &phy_data); 8677 if (ret_val) 8678 return ret_val; 8679 } 8680 8681 if (!active) { 8682 if (hw->mac_type == em_82541_rev_2 || 8683 hw->mac_type == em_82547_rev_2) { 8684 phy_data &= ~IGP01E1000_GMII_FLEX_SPD; 8685 ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO, 8686 phy_data); 8687 if (ret_val) 8688 return ret_val; 8689 } else { 8690 if (IS_ICH8(hw->mac_type)) { 8691 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; 8692 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 8693 } else { 8694 phy_data &= ~IGP02E1000_PM_D3_LPLU; 8695 ret_val = em_write_phy_reg(hw, 8696 IGP02E1000_PHY_POWER_MGMT, phy_data); 8697 if (ret_val) 8698 return ret_val; 8699 } 8700 } 8701 /* 8702 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 8703 * during Dx states where the power conservation is most 8704 * important. During driver activity we should enable 8705 * SmartSpeed, so performance is maintained. 8706 */ 8707 if (hw->smart_speed == em_smart_speed_on) { 8708 ret_val = em_read_phy_reg(hw, 8709 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 8710 if (ret_val) 8711 return ret_val; 8712 8713 phy_data |= IGP01E1000_PSCFR_SMART_SPEED; 8714 ret_val = em_write_phy_reg(hw, 8715 IGP01E1000_PHY_PORT_CONFIG, phy_data); 8716 if (ret_val) 8717 return ret_val; 8718 } else if (hw->smart_speed == em_smart_speed_off) { 8719 ret_val = em_read_phy_reg(hw, 8720 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 8721 if (ret_val) 8722 return ret_val; 8723 8724 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 8725 ret_val = em_write_phy_reg(hw, 8726 IGP01E1000_PHY_PORT_CONFIG, phy_data); 8727 if (ret_val) 8728 return ret_val; 8729 } 8730 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) 8731 || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) || 8732 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) { 8733 8734 if (hw->mac_type == em_82541_rev_2 || 8735 hw->mac_type == em_82547_rev_2) { 8736 phy_data |= IGP01E1000_GMII_FLEX_SPD; 8737 ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO, 8738 phy_data); 8739 if (ret_val) 8740 return ret_val; 8741 } else { 8742 if (IS_ICH8(hw->mac_type)) { 8743 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; 8744 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 8745 } else { 8746 phy_data |= IGP02E1000_PM_D3_LPLU; 8747 ret_val = em_write_phy_reg(hw, 8748 IGP02E1000_PHY_POWER_MGMT, phy_data); 8749 if (ret_val) 8750 return ret_val; 8751 } 8752 } 8753 8754 /* When LPLU is enabled we should disable SmartSpeed */ 8755 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 8756 &phy_data); 8757 if (ret_val) 8758 return ret_val; 8759 8760 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 8761 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 8762 phy_data); 8763 if (ret_val) 8764 return ret_val; 8765 8766 } 8767 return E1000_SUCCESS; 8768 } 8769 8770 /***************************************************************************** 8771 * 8772 * This function sets the lplu d0 state according to the active flag. When 8773 * activating lplu this function also disables smart speed and vise versa. 8774 * lplu will not be activated unless the device autonegotiation advertisement 8775 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. 8776 * hw: Struct containing variables accessed by shared code 8777 * active - true to enable lplu false to disable lplu. 8778 * 8779 * returns: - E1000_ERR_PHY if fail to read/write the PHY 8780 * E1000_SUCCESS at any other case. 8781 * 8782 ****************************************************************************/ 8783 STATIC int32_t 8784 em_set_d0_lplu_state(struct em_hw *hw, boolean_t active) 8785 { 8786 uint32_t phy_ctrl = 0; 8787 int32_t ret_val; 8788 uint16_t phy_data; 8789 DEBUGFUNC("em_set_d0_lplu_state"); 8790 8791 if (hw->mac_type <= em_82547_rev_2) 8792 return E1000_SUCCESS; 8793 8794 if (IS_ICH8(hw->mac_type)) { 8795 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); 8796 } else { 8797 ret_val = em_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, 8798 &phy_data); 8799 if (ret_val) 8800 return ret_val; 8801 } 8802 8803 if (!active) { 8804 if (IS_ICH8(hw->mac_type)) { 8805 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; 8806 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 8807 } else { 8808 phy_data &= ~IGP02E1000_PM_D0_LPLU; 8809 ret_val = em_write_phy_reg(hw, 8810 IGP02E1000_PHY_POWER_MGMT, phy_data); 8811 if (ret_val) 8812 return ret_val; 8813 } 8814 /* 8815 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 8816 * during Dx states where the power conservation is most 8817 * important. During driver activity we should enable 8818 * SmartSpeed, so performance is maintained. 8819 */ 8820 if (hw->smart_speed == em_smart_speed_on) { 8821 ret_val = em_read_phy_reg(hw, 8822 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 8823 if (ret_val) 8824 return ret_val; 8825 8826 phy_data |= IGP01E1000_PSCFR_SMART_SPEED; 8827 ret_val = em_write_phy_reg(hw, 8828 IGP01E1000_PHY_PORT_CONFIG, phy_data); 8829 if (ret_val) 8830 return ret_val; 8831 } else if (hw->smart_speed == em_smart_speed_off) { 8832 ret_val = em_read_phy_reg(hw, 8833 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 8834 if (ret_val) 8835 return ret_val; 8836 8837 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 8838 ret_val = em_write_phy_reg(hw, 8839 IGP01E1000_PHY_PORT_CONFIG, phy_data); 8840 if (ret_val) 8841 return ret_val; 8842 } 8843 } else { 8844 if (IS_ICH8(hw->mac_type)) { 8845 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; 8846 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 8847 } else { 8848 phy_data |= IGP02E1000_PM_D0_LPLU; 8849 ret_val = em_write_phy_reg(hw, 8850 IGP02E1000_PHY_POWER_MGMT, phy_data); 8851 if (ret_val) 8852 return ret_val; 8853 } 8854 8855 /* When LPLU is enabled we should disable SmartSpeed */ 8856 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 8857 &phy_data); 8858 if (ret_val) 8859 return ret_val; 8860 8861 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 8862 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 8863 phy_data); 8864 if (ret_val) 8865 return ret_val; 8866 8867 } 8868 return E1000_SUCCESS; 8869 } 8870 8871 /*************************************************************************** 8872 * Set Low Power Link Up state 8873 * 8874 * Sets the LPLU state according to the active flag. For PCH, if OEM write 8875 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set 8876 * the phy speed. This function will manually set the LPLU bit and restart 8877 * auto-neg as hw would do. D3 and D0 LPLU will call the same function 8878 * since it configures the same bit. 8879 ***************************************************************************/ 8880 int32_t 8881 em_set_lplu_state_pchlan(struct em_hw *hw, boolean_t active) 8882 { 8883 int32_t ret_val = E1000_SUCCESS; 8884 uint16_t oem_reg; 8885 8886 DEBUGFUNC("e1000_set_lplu_state_pchlan"); 8887 8888 ret_val = em_read_phy_reg(hw, HV_OEM_BITS, &oem_reg); 8889 if (ret_val) 8890 goto out; 8891 8892 if (active) 8893 oem_reg |= HV_OEM_BITS_LPLU; 8894 else 8895 oem_reg &= ~HV_OEM_BITS_LPLU; 8896 8897 oem_reg |= HV_OEM_BITS_RESTART_AN; 8898 ret_val = em_write_phy_reg(hw, HV_OEM_BITS, oem_reg); 8899 8900 out: 8901 return ret_val; 8902 } 8903 8904 /****************************************************************************** 8905 * Change VCO speed register to improve Bit Error Rate performance of SERDES. 8906 * 8907 * hw - Struct containing variables accessed by shared code 8908 *****************************************************************************/ 8909 static int32_t 8910 em_set_vco_speed(struct em_hw *hw) 8911 { 8912 int32_t ret_val; 8913 uint16_t default_page = 0; 8914 uint16_t phy_data; 8915 DEBUGFUNC("em_set_vco_speed"); 8916 8917 switch (hw->mac_type) { 8918 case em_82545_rev_3: 8919 case em_82546_rev_3: 8920 break; 8921 default: 8922 return E1000_SUCCESS; 8923 } 8924 8925 /* Set PHY register 30, page 5, bit 8 to 0 */ 8926 8927 ret_val = em_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page); 8928 if (ret_val) 8929 return ret_val; 8930 8931 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005); 8932 if (ret_val) 8933 return ret_val; 8934 8935 ret_val = em_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); 8936 if (ret_val) 8937 return ret_val; 8938 8939 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8; 8940 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); 8941 if (ret_val) 8942 return ret_val; 8943 8944 /* Set PHY register 30, page 4, bit 11 to 1 */ 8945 8946 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004); 8947 if (ret_val) 8948 return ret_val; 8949 8950 ret_val = em_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); 8951 if (ret_val) 8952 return ret_val; 8953 8954 phy_data |= M88E1000_PHY_VCO_REG_BIT11; 8955 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); 8956 if (ret_val) 8957 return ret_val; 8958 8959 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page); 8960 if (ret_val) 8961 return ret_val; 8962 8963 return E1000_SUCCESS; 8964 } 8965 8966 /***************************************************************************** 8967 * This function reads the cookie from ARC ram. 8968 * 8969 * returns: - E1000_SUCCESS . 8970 ****************************************************************************/ 8971 STATIC int32_t 8972 em_host_if_read_cookie(struct em_hw *hw, uint8_t *buffer) 8973 { 8974 uint8_t i; 8975 uint32_t offset = E1000_MNG_DHCP_COOKIE_OFFSET; 8976 uint8_t length = E1000_MNG_DHCP_COOKIE_LENGTH; 8977 length = (length >> 2); 8978 offset = (offset >> 2); 8979 8980 for (i = 0; i < length; i++) { 8981 *((uint32_t *) buffer + i) = 8982 E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i); 8983 } 8984 return E1000_SUCCESS; 8985 } 8986 8987 /***************************************************************************** 8988 * This function checks whether the HOST IF is enabled for command operaton 8989 * and also checks whether the previous command is completed. 8990 * It busy waits in case of previous command is not completed. 8991 * 8992 * returns: - E1000_ERR_HOST_INTERFACE_COMMAND in case if is not ready or 8993 * timeout 8994 * - E1000_SUCCESS for success. 8995 ****************************************************************************/ 8996 STATIC int32_t 8997 em_mng_enable_host_if(struct em_hw *hw) 8998 { 8999 uint32_t hicr; 9000 uint8_t i; 9001 /* Check that the host interface is enabled. */ 9002 hicr = E1000_READ_REG(hw, HICR); 9003 if ((hicr & E1000_HICR_EN) == 0) { 9004 DEBUGOUT("E1000_HOST_EN bit disabled.\n"); 9005 return -E1000_ERR_HOST_INTERFACE_COMMAND; 9006 } 9007 /* check the previous command is completed */ 9008 for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) { 9009 hicr = E1000_READ_REG(hw, HICR); 9010 if (!(hicr & E1000_HICR_C)) 9011 break; 9012 msec_delay_irq(1); 9013 } 9014 9015 if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) { 9016 DEBUGOUT("Previous command timeout failed .\n"); 9017 return -E1000_ERR_HOST_INTERFACE_COMMAND; 9018 } 9019 return E1000_SUCCESS; 9020 } 9021 9022 /***************************************************************************** 9023 * This function checks the mode of the firmware. 9024 * 9025 * returns - TRUE when the mode is IAMT or FALSE. 9026 ****************************************************************************/ 9027 boolean_t 9028 em_check_mng_mode(struct em_hw *hw) 9029 { 9030 uint32_t fwsm; 9031 fwsm = E1000_READ_REG(hw, FWSM); 9032 9033 if (IS_ICH8(hw->mac_type)) { 9034 if ((fwsm & E1000_FWSM_MODE_MASK) == 9035 (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) 9036 return TRUE; 9037 } else if ((fwsm & E1000_FWSM_MODE_MASK) == 9038 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) 9039 return TRUE; 9040 9041 return FALSE; 9042 } 9043 9044 /***************************************************************************** 9045 * This function calculates the checksum. 9046 * 9047 * returns - checksum of buffer contents. 9048 ****************************************************************************/ 9049 STATIC uint8_t 9050 em_calculate_mng_checksum(char *buffer, uint32_t length) 9051 { 9052 uint8_t sum = 0; 9053 uint32_t i; 9054 if (!buffer) 9055 return 0; 9056 9057 for (i = 0; i < length; i++) 9058 sum += buffer[i]; 9059 9060 return (uint8_t) (0 - sum); 9061 } 9062 9063 /***************************************************************************** 9064 * This function checks whether tx pkt filtering needs to be enabled or not. 9065 * 9066 * returns - TRUE for packet filtering or FALSE. 9067 ****************************************************************************/ 9068 boolean_t 9069 em_enable_tx_pkt_filtering(struct em_hw *hw) 9070 { 9071 /* called in init as well as watchdog timer functions */ 9072 int32_t ret_val, checksum; 9073 boolean_t tx_filter = FALSE; 9074 struct em_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie); 9075 uint8_t *buffer = (uint8_t *) & (hw->mng_cookie); 9076 if (em_check_mng_mode(hw)) { 9077 ret_val = em_mng_enable_host_if(hw); 9078 if (ret_val == E1000_SUCCESS) { 9079 ret_val = em_host_if_read_cookie(hw, buffer); 9080 if (ret_val == E1000_SUCCESS) { 9081 checksum = hdr->checksum; 9082 hdr->checksum = 0; 9083 if ((hdr->signature == E1000_IAMT_SIGNATURE) && 9084 checksum == em_calculate_mng_checksum( 9085 (char *) buffer, 9086 E1000_MNG_DHCP_COOKIE_LENGTH)) { 9087 if (hdr->status & 9088 E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT) 9089 tx_filter = TRUE; 9090 } else 9091 tx_filter = TRUE; 9092 } else 9093 tx_filter = TRUE; 9094 } 9095 } 9096 hw->tx_pkt_filtering = tx_filter; 9097 return tx_filter; 9098 } 9099 9100 static int32_t 9101 em_polarity_reversal_workaround(struct em_hw *hw) 9102 { 9103 int32_t ret_val; 9104 uint16_t mii_status_reg; 9105 uint16_t i; 9106 /* Polarity reversal workaround for forced 10F/10H links. */ 9107 9108 /* Disable the transmitter on the PHY */ 9109 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 9110 if (ret_val) 9111 return ret_val; 9112 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF); 9113 if (ret_val) 9114 return ret_val; 9115 9116 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 9117 if (ret_val) 9118 return ret_val; 9119 9120 /* This loop will early-out if the NO link condition has been met. */ 9121 for (i = PHY_FORCE_TIME; i > 0; i--) { 9122 /* 9123 * Read the MII Status Register and wait for Link Status bit 9124 * to be clear. 9125 */ 9126 9127 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 9128 if (ret_val) 9129 return ret_val; 9130 9131 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 9132 if (ret_val) 9133 return ret_val; 9134 9135 if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) 9136 break; 9137 msec_delay_irq(100); 9138 } 9139 9140 /* Recommended delay time after link has been lost */ 9141 msec_delay_irq(1000); 9142 9143 /* Now we will re-enable the transmitter on the PHY */ 9144 9145 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 9146 if (ret_val) 9147 return ret_val; 9148 msec_delay_irq(50); 9149 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0); 9150 if (ret_val) 9151 return ret_val; 9152 msec_delay_irq(50); 9153 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00); 9154 if (ret_val) 9155 return ret_val; 9156 msec_delay_irq(50); 9157 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000); 9158 if (ret_val) 9159 return ret_val; 9160 9161 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 9162 if (ret_val) 9163 return ret_val; 9164 9165 /* This loop will early-out if the link condition has been met. */ 9166 for (i = PHY_FORCE_TIME; i > 0; i--) { 9167 /* 9168 * Read the MII Status Register and wait for Link Status bit 9169 * to be set. 9170 */ 9171 9172 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 9173 if (ret_val) 9174 return ret_val; 9175 9176 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 9177 if (ret_val) 9178 return ret_val; 9179 9180 if (mii_status_reg & MII_SR_LINK_STATUS) 9181 break; 9182 msec_delay_irq(100); 9183 } 9184 return E1000_SUCCESS; 9185 } 9186 9187 /****************************************************************************** 9188 * 9189 * Disables PCI-Express master access. 9190 * 9191 * hw: Struct containing variables accessed by shared code 9192 * 9193 * returns: - none. 9194 * 9195 *****************************************************************************/ 9196 STATIC void 9197 em_set_pci_express_master_disable(struct em_hw *hw) 9198 { 9199 uint32_t ctrl; 9200 DEBUGFUNC("em_set_pci_express_master_disable"); 9201 9202 if (hw->bus_type != em_bus_type_pci_express) 9203 return; 9204 9205 ctrl = E1000_READ_REG(hw, CTRL); 9206 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; 9207 E1000_WRITE_REG(hw, CTRL, ctrl); 9208 } 9209 9210 /****************************************************************************** 9211 * 9212 * Disables PCI-Express master access and verifies there are no pending 9213 * requests 9214 * 9215 * hw: Struct containing variables accessed by shared code 9216 * 9217 * returns: - E1000_ERR_MASTER_REQUESTS_PENDING if master disable bit hasn't 9218 * caused the master requests to be disabled. 9219 * E1000_SUCCESS master requests disabled. 9220 * 9221 ******************************************************************************/ 9222 int32_t 9223 em_disable_pciex_master(struct em_hw *hw) 9224 { 9225 int32_t timeout = MASTER_DISABLE_TIMEOUT; /* 80ms */ 9226 DEBUGFUNC("em_disable_pciex_master"); 9227 9228 if (hw->bus_type != em_bus_type_pci_express) 9229 return E1000_SUCCESS; 9230 9231 em_set_pci_express_master_disable(hw); 9232 9233 while (timeout) { 9234 if (!(E1000_READ_REG(hw, STATUS) & 9235 E1000_STATUS_GIO_MASTER_ENABLE)) 9236 break; 9237 else 9238 usec_delay(100); 9239 timeout--; 9240 } 9241 9242 if (!timeout) { 9243 DEBUGOUT("Master requests are pending.\n"); 9244 return -E1000_ERR_MASTER_REQUESTS_PENDING; 9245 } 9246 return E1000_SUCCESS; 9247 } 9248 9249 /****************************************************************************** 9250 * 9251 * Check for EEPROM Auto Read bit done. 9252 * 9253 * hw: Struct containing variables accessed by shared code 9254 * 9255 * returns: - E1000_ERR_RESET if fail to reset MAC 9256 * E1000_SUCCESS at any other case. 9257 * 9258 ******************************************************************************/ 9259 STATIC int32_t 9260 em_get_auto_rd_done(struct em_hw *hw) 9261 { 9262 int32_t timeout = AUTO_READ_DONE_TIMEOUT; 9263 DEBUGFUNC("em_get_auto_rd_done"); 9264 9265 switch (hw->mac_type) { 9266 default: 9267 msec_delay(5); 9268 break; 9269 case em_82571: 9270 case em_82572: 9271 case em_82573: 9272 case em_82574: 9273 case em_82575: 9274 case em_82576: 9275 case em_82580: 9276 case em_80003es2lan: 9277 case em_i210: 9278 case em_i350: 9279 case em_ich8lan: 9280 case em_ich9lan: 9281 case em_ich10lan: 9282 case em_pchlan: 9283 case em_pch2lan: 9284 case em_pch_lpt: 9285 case em_pch_spt: 9286 case em_pch_cnp: 9287 while (timeout) { 9288 if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD) 9289 break; 9290 else 9291 msec_delay(1); 9292 timeout--; 9293 } 9294 9295 if (!timeout) { 9296 DEBUGOUT("Auto read by HW from EEPROM has not" 9297 " completed.\n"); 9298 return -E1000_ERR_RESET; 9299 } 9300 break; 9301 } 9302 /* 9303 * PHY configuration from NVM just starts after EECD_AUTO_RD sets to 9304 * high. Need to wait for PHY configuration completion before 9305 * accessing NVM and PHY. 9306 */ 9307 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) 9308 msec_delay(25); 9309 9310 return E1000_SUCCESS; 9311 } 9312 9313 /*************************************************************************** 9314 * Checks if the PHY configuration is done 9315 * 9316 * hw: Struct containing variables accessed by shared code 9317 * 9318 * returns: - E1000_ERR_RESET if fail to reset MAC 9319 * E1000_SUCCESS at any other case. 9320 * 9321 ***************************************************************************/ 9322 STATIC int32_t 9323 em_get_phy_cfg_done(struct em_hw *hw) 9324 { 9325 int32_t timeout = PHY_CFG_TIMEOUT; 9326 uint32_t cfg_mask = E1000_NVM_CFG_DONE_PORT_0; 9327 DEBUGFUNC("em_get_phy_cfg_done"); 9328 9329 switch (hw->mac_type) { 9330 default: 9331 msec_delay_irq(10); 9332 break; 9333 case em_80003es2lan: 9334 case em_82575: 9335 case em_82576: 9336 case em_82580: 9337 case em_i350: 9338 switch (hw->bus_func) { 9339 case 1: 9340 cfg_mask = E1000_NVM_CFG_DONE_PORT_1; 9341 break; 9342 case 2: 9343 cfg_mask = E1000_NVM_CFG_DONE_PORT_2; 9344 break; 9345 case 3: 9346 cfg_mask = E1000_NVM_CFG_DONE_PORT_3; 9347 break; 9348 } 9349 /* FALLTHROUGH */ 9350 case em_82571: 9351 case em_82572: 9352 while (timeout) { 9353 if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask) 9354 break; 9355 else 9356 msec_delay(1); 9357 timeout--; 9358 } 9359 if (!timeout) { 9360 DEBUGOUT("MNG configuration cycle has not completed." 9361 "\n"); 9362 } 9363 break; 9364 } 9365 9366 return E1000_SUCCESS; 9367 } 9368 9369 /*************************************************************************** 9370 * 9371 * Using the combination of SMBI and SWESMBI semaphore bits when resetting 9372 * adapter or Eeprom access. 9373 * 9374 * hw: Struct containing variables accessed by shared code 9375 * 9376 * returns: - E1000_ERR_EEPROM if fail to access EEPROM. 9377 * E1000_SUCCESS at any other case. 9378 * 9379 ***************************************************************************/ 9380 STATIC int32_t 9381 em_get_hw_eeprom_semaphore(struct em_hw *hw) 9382 { 9383 int32_t timeout; 9384 uint32_t swsm; 9385 DEBUGFUNC("em_get_hw_eeprom_semaphore"); 9386 9387 if (!hw->eeprom_semaphore_present) 9388 return E1000_SUCCESS; 9389 9390 if (hw->mac_type == em_80003es2lan) { 9391 /* Get the SW semaphore. */ 9392 if (em_get_software_semaphore(hw) != E1000_SUCCESS) 9393 return -E1000_ERR_EEPROM; 9394 } 9395 /* Get the FW semaphore. */ 9396 timeout = hw->eeprom.word_size + 1; 9397 while (timeout) { 9398 swsm = E1000_READ_REG(hw, SWSM); 9399 swsm |= E1000_SWSM_SWESMBI; 9400 E1000_WRITE_REG(hw, SWSM, swsm); 9401 /* if we managed to set the bit we got the semaphore. */ 9402 swsm = E1000_READ_REG(hw, SWSM); 9403 if (swsm & E1000_SWSM_SWESMBI) 9404 break; 9405 9406 usec_delay(50); 9407 timeout--; 9408 } 9409 9410 if (!timeout) { 9411 /* Release semaphores */ 9412 em_put_hw_eeprom_semaphore(hw); 9413 DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set." 9414 "\n"); 9415 return -E1000_ERR_EEPROM; 9416 } 9417 return E1000_SUCCESS; 9418 } 9419 9420 /*************************************************************************** 9421 * This function clears HW semaphore bits. 9422 * 9423 * hw: Struct containing variables accessed by shared code 9424 * 9425 * returns: - None. 9426 * 9427 ***************************************************************************/ 9428 STATIC void 9429 em_put_hw_eeprom_semaphore(struct em_hw *hw) 9430 { 9431 uint32_t swsm; 9432 DEBUGFUNC("em_put_hw_eeprom_semaphore"); 9433 9434 if (!hw->eeprom_semaphore_present) 9435 return; 9436 9437 swsm = E1000_READ_REG(hw, SWSM); 9438 if (hw->mac_type == em_80003es2lan) { 9439 /* Release both semaphores. */ 9440 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 9441 } else 9442 swsm &= ~(E1000_SWSM_SWESMBI); 9443 E1000_WRITE_REG(hw, SWSM, swsm); 9444 } 9445 9446 /*************************************************************************** 9447 * 9448 * Obtaining software semaphore bit (SMBI) before resetting PHY. 9449 * 9450 * hw: Struct containing variables accessed by shared code 9451 * 9452 * returns: - E1000_ERR_RESET if fail to obtain semaphore. 9453 * E1000_SUCCESS at any other case. 9454 * 9455 ***************************************************************************/ 9456 STATIC int32_t 9457 em_get_software_semaphore(struct em_hw *hw) 9458 { 9459 int32_t timeout = hw->eeprom.word_size + 1; 9460 uint32_t swsm; 9461 DEBUGFUNC("em_get_software_semaphore"); 9462 9463 if (hw->mac_type != em_80003es2lan) 9464 return E1000_SUCCESS; 9465 9466 while (timeout) { 9467 swsm = E1000_READ_REG(hw, SWSM); 9468 /* 9469 * If SMBI bit cleared, it is now set and we hold the 9470 * semaphore 9471 */ 9472 if (!(swsm & E1000_SWSM_SMBI)) 9473 break; 9474 msec_delay_irq(1); 9475 timeout--; 9476 } 9477 9478 if (!timeout) { 9479 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 9480 return -E1000_ERR_RESET; 9481 } 9482 return E1000_SUCCESS; 9483 } 9484 9485 /*************************************************************************** 9486 * 9487 * Release semaphore bit (SMBI). 9488 * 9489 * hw: Struct containing variables accessed by shared code 9490 * 9491 ***************************************************************************/ 9492 STATIC void 9493 em_release_software_semaphore(struct em_hw *hw) 9494 { 9495 uint32_t swsm; 9496 DEBUGFUNC("em_release_software_semaphore"); 9497 9498 if (hw->mac_type != em_80003es2lan) 9499 return; 9500 9501 swsm = E1000_READ_REG(hw, SWSM); 9502 /* Release the SW semaphores. */ 9503 swsm &= ~E1000_SWSM_SMBI; 9504 E1000_WRITE_REG(hw, SWSM, swsm); 9505 } 9506 9507 /****************************************************************************** 9508 * Checks if PHY reset is blocked due to SOL/IDER session, for example. 9509 * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to 9510 * the caller to figure out how to deal with it. 9511 * 9512 * hw - Struct containing variables accessed by shared code 9513 * 9514 * returns: - E1000_BLK_PHY_RESET 9515 * E1000_SUCCESS 9516 * 9517 *****************************************************************************/ 9518 int32_t 9519 em_check_phy_reset_block(struct em_hw *hw) 9520 { 9521 uint32_t manc = 0; 9522 uint32_t fwsm = 0; 9523 DEBUGFUNC("em_check_phy_reset_block\n"); 9524 9525 if (IS_ICH8(hw->mac_type)) { 9526 int i = 0; 9527 int blocked = 0; 9528 do { 9529 fwsm = E1000_READ_REG(hw, FWSM); 9530 if (!(fwsm & E1000_FWSM_RSPCIPHY)) { 9531 blocked = 1; 9532 msec_delay(10); 9533 continue; 9534 } 9535 blocked = 0; 9536 } while (blocked && (i++ < 30)); 9537 return blocked ? E1000_BLK_PHY_RESET : E1000_SUCCESS; 9538 } 9539 if (hw->mac_type > em_82547_rev_2) 9540 manc = E1000_READ_REG(hw, MANC); 9541 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? 9542 E1000_BLK_PHY_RESET : E1000_SUCCESS; 9543 } 9544 9545 /****************************************************************************** 9546 * Configure PCI-Ex no-snoop 9547 * 9548 * hw - Struct containing variables accessed by shared code. 9549 * no_snoop - Bitmap of no-snoop events. 9550 * 9551 * returns: E1000_SUCCESS 9552 * 9553 *****************************************************************************/ 9554 STATIC int32_t 9555 em_set_pci_ex_no_snoop(struct em_hw *hw, uint32_t no_snoop) 9556 { 9557 uint32_t gcr_reg = 0; 9558 DEBUGFUNC("em_set_pci_ex_no_snoop"); 9559 9560 if (hw->bus_type == em_bus_type_unknown) 9561 em_get_bus_info(hw); 9562 9563 if (hw->bus_type != em_bus_type_pci_express) 9564 return E1000_SUCCESS; 9565 9566 if (no_snoop) { 9567 gcr_reg = E1000_READ_REG(hw, GCR); 9568 gcr_reg &= ~(PCI_EX_NO_SNOOP_ALL); 9569 gcr_reg |= no_snoop; 9570 E1000_WRITE_REG(hw, GCR, gcr_reg); 9571 } 9572 if (IS_ICH8(hw->mac_type)) { 9573 uint32_t ctrl_ext; 9574 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 9575 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 9576 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 9577 } 9578 return E1000_SUCCESS; 9579 } 9580 9581 /*************************************************************************** 9582 * 9583 * Get software semaphore FLAG bit (SWFLAG). 9584 * SWFLAG is used to synchronize the access to all shared resource between 9585 * SW, FW and HW. 9586 * 9587 * hw: Struct containing variables accessed by shared code 9588 * 9589 ***************************************************************************/ 9590 STATIC int32_t 9591 em_get_software_flag(struct em_hw *hw) 9592 { 9593 int32_t timeout = PHY_CFG_TIMEOUT; 9594 uint32_t extcnf_ctrl; 9595 DEBUGFUNC("em_get_software_flag"); 9596 9597 if (IS_ICH8(hw->mac_type)) { 9598 if (hw->sw_flag) { 9599 hw->sw_flag++; 9600 return E1000_SUCCESS; 9601 } 9602 while (timeout) { 9603 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 9604 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)) 9605 break; 9606 msec_delay_irq(1); 9607 timeout--; 9608 } 9609 if (!timeout) { 9610 printf("%s: SW has already locked the resource?\n", 9611 __func__); 9612 return -E1000_ERR_CONFIG; 9613 } 9614 timeout = SW_FLAG_TIMEOUT; 9615 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; 9616 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); 9617 9618 while (timeout) { 9619 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 9620 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) 9621 break; 9622 msec_delay_irq(1); 9623 timeout--; 9624 } 9625 9626 if (!timeout) { 9627 printf("Failed to acquire the semaphore, FW or HW " 9628 "has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n", 9629 E1000_READ_REG(hw, FWSM), extcnf_ctrl); 9630 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 9631 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); 9632 return -E1000_ERR_CONFIG; 9633 } 9634 } 9635 hw->sw_flag++; 9636 return E1000_SUCCESS; 9637 } 9638 9639 /*************************************************************************** 9640 * 9641 * Release software semaphore FLAG bit (SWFLAG). 9642 * SWFLAG is used to synchronize the access to all shared resource between 9643 * SW, FW and HW. 9644 * 9645 * hw: Struct containing variables accessed by shared code 9646 * 9647 ***************************************************************************/ 9648 STATIC void 9649 em_release_software_flag(struct em_hw *hw) 9650 { 9651 uint32_t extcnf_ctrl; 9652 DEBUGFUNC("em_release_software_flag"); 9653 9654 if (IS_ICH8(hw->mac_type)) { 9655 KASSERT(hw->sw_flag > 0); 9656 if (--hw->sw_flag > 0) 9657 return; 9658 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 9659 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 9660 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); 9661 } 9662 return; 9663 } 9664 9665 /** 9666 * em_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1 9667 * @hw: pointer to the HW structure 9668 * @bank: pointer to the variable that returns the active bank 9669 * 9670 * Reads signature byte from the NVM using the flash access registers. 9671 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank. 9672 **/ 9673 int32_t 9674 em_valid_nvm_bank_detect_ich8lan(struct em_hw *hw, uint32_t *bank) 9675 { 9676 uint32_t eecd; 9677 uint32_t bank1_offset = hw->flash_bank_size * sizeof(uint16_t); 9678 uint32_t act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1; 9679 uint32_t nvm_dword = 0; 9680 uint8_t sig_byte = 0; 9681 int32_t ret_val; 9682 9683 DEBUGFUNC("em_valid_nvm_bank_detect_ich8lan"); 9684 9685 switch (hw->mac_type) { 9686 case em_pch_spt: 9687 case em_pch_cnp: 9688 bank1_offset = hw->flash_bank_size * 2; 9689 act_offset = E1000_ICH_NVM_SIG_WORD * 2; 9690 9691 /* set bank to 0 in case flash read fails. */ 9692 *bank = 0; 9693 9694 /* Check bank 0 */ 9695 ret_val = em_read_ich8_dword(hw, act_offset, &nvm_dword); 9696 if (ret_val) 9697 return ret_val; 9698 sig_byte = (uint8_t)((nvm_dword & 0xFF00) >> 8); 9699 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 9700 E1000_ICH_NVM_SIG_VALUE) { 9701 *bank = 0; 9702 return 0; 9703 } 9704 9705 /* Check bank 1 */ 9706 ret_val = em_read_ich8_dword(hw, act_offset + bank1_offset, 9707 &nvm_dword); 9708 if (ret_val) 9709 return ret_val; 9710 sig_byte = (uint8_t)((nvm_dword & 0xFF00) >> 8); 9711 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 9712 E1000_ICH_NVM_SIG_VALUE) { 9713 *bank = 1; 9714 return 0; 9715 } 9716 9717 DEBUGOUT("ERROR: No valid NVM bank present\n"); 9718 return -1; 9719 case em_ich8lan: 9720 case em_ich9lan: 9721 eecd = E1000_READ_REG(hw, EECD); 9722 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) == 9723 E1000_EECD_SEC1VAL_VALID_MASK) { 9724 if (eecd & E1000_EECD_SEC1VAL) 9725 *bank = 1; 9726 else 9727 *bank = 0; 9728 9729 return E1000_SUCCESS; 9730 } 9731 DEBUGOUT("Unable to determine valid NVM bank via EEC - reading flash signature\n"); 9732 /* fall-thru */ 9733 default: 9734 /* set bank to 0 in case flash read fails */ 9735 *bank = 0; 9736 9737 /* Check bank 0 */ 9738 ret_val = em_read_ich8_byte(hw, act_offset, 9739 &sig_byte); 9740 if (ret_val) 9741 return ret_val; 9742 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 9743 E1000_ICH_NVM_SIG_VALUE) { 9744 *bank = 0; 9745 return E1000_SUCCESS; 9746 } 9747 9748 /* Check bank 1 */ 9749 ret_val = em_read_ich8_byte(hw, act_offset + 9750 bank1_offset, 9751 &sig_byte); 9752 if (ret_val) 9753 return ret_val; 9754 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 9755 E1000_ICH_NVM_SIG_VALUE) { 9756 *bank = 1; 9757 return E1000_SUCCESS; 9758 } 9759 9760 DEBUGOUT("ERROR: No valid NVM bank present\n"); 9761 return -1; 9762 } 9763 } 9764 9765 STATIC int32_t 9766 em_read_eeprom_spt(struct em_hw *hw, uint16_t offset, uint16_t words, 9767 uint16_t *data) 9768 { 9769 int32_t error = E1000_SUCCESS; 9770 uint32_t flash_bank = 0; 9771 uint32_t act_offset = 0; 9772 uint32_t bank_offset = 0; 9773 uint32_t dword = 0; 9774 uint16_t i = 0, add; 9775 9776 /* 9777 * We need to know which is the valid flash bank. In the event that 9778 * we didn't allocate eeprom_shadow_ram, we may not be managing 9779 * flash_bank. So it cannot be trusted and needs to be updated with 9780 * each read. 9781 */ 9782 9783 if (hw->mac_type < em_pch_spt) 9784 return -E1000_ERR_EEPROM; 9785 9786 error = em_get_software_flag(hw); 9787 if (error != E1000_SUCCESS) 9788 return error; 9789 9790 error = em_valid_nvm_bank_detect_ich8lan(hw, &flash_bank); 9791 if (error != E1000_SUCCESS) { 9792 DEBUGOUT("Could not detect valid bank, assuming bank 0\n"); 9793 flash_bank = 0; 9794 } 9795 9796 /* 9797 * Adjust offset appropriately if we're on bank 1 - adjust for word 9798 * size 9799 */ 9800 bank_offset = flash_bank * (hw->flash_bank_size * 2); 9801 9802 for (i = add = 0; i < words; i += add) { 9803 if ((offset + i) % 2) { 9804 add = 1; 9805 if (hw->eeprom_shadow_ram != NULL 9806 && hw->eeprom_shadow_ram[offset + i].modified) { 9807 data[i] = 9808 hw->eeprom_shadow_ram[offset+i].eeprom_word; 9809 continue; 9810 } 9811 act_offset = bank_offset + (offset + i - 1) * 2; 9812 } else { 9813 add = 2; 9814 if (hw->eeprom_shadow_ram != NULL 9815 && hw->eeprom_shadow_ram[offset+i].modified 9816 && hw->eeprom_shadow_ram[offset+i+1].modified) { 9817 data[i] = hw->eeprom_shadow_ram[offset+i].eeprom_word; 9818 data[i+1] = hw->eeprom_shadow_ram[offset+i+1].eeprom_word; 9819 continue; 9820 } 9821 act_offset = bank_offset + (offset + i) * 2; 9822 } 9823 error = em_read_ich8_dword(hw, act_offset, &dword); 9824 if (error != E1000_SUCCESS) 9825 break; 9826 if (hw->eeprom_shadow_ram != NULL 9827 && hw->eeprom_shadow_ram[offset+i].modified) { 9828 data[i] = hw->eeprom_shadow_ram[offset+i].eeprom_word; 9829 } else { 9830 if (add == 1) 9831 data[i] = dword >> 16; 9832 else 9833 data[i] = dword & 0xFFFFUL; 9834 } 9835 if (add == 1 || words-i == 1) 9836 continue; 9837 if (hw->eeprom_shadow_ram != NULL 9838 && hw->eeprom_shadow_ram[offset+i+1].modified) { 9839 data[i+1] = 9840 hw->eeprom_shadow_ram[offset+i+1].eeprom_word; 9841 } else { 9842 data[i+1] = dword >> 16; 9843 } 9844 } 9845 9846 em_release_software_flag(hw); 9847 9848 return error; 9849 } 9850 9851 /****************************************************************************** 9852 * Reads a 16 bit word or words from the EEPROM using the ICH8's flash access 9853 * register. 9854 * 9855 * hw - Struct containing variables accessed by shared code 9856 * offset - offset of word in the EEPROM to read 9857 * data - word read from the EEPROM 9858 * words - number of words to read 9859 *****************************************************************************/ 9860 STATIC int32_t 9861 em_read_eeprom_ich8(struct em_hw *hw, uint16_t offset, uint16_t words, 9862 uint16_t *data) 9863 { 9864 int32_t error = E1000_SUCCESS; 9865 uint32_t flash_bank = 0; 9866 uint32_t act_offset = 0; 9867 uint32_t bank_offset = 0; 9868 uint16_t word = 0; 9869 uint16_t i = 0; 9870 /* 9871 * We need to know which is the valid flash bank. In the event that 9872 * we didn't allocate eeprom_shadow_ram, we may not be managing 9873 * flash_bank. So it cannot be trusted and needs to be updated with 9874 * each read. 9875 */ 9876 9877 if (hw->mac_type >= em_pch_spt) 9878 return em_read_eeprom_spt(hw, offset, words, data); 9879 9880 error = em_get_software_flag(hw); 9881 if (error != E1000_SUCCESS) 9882 return error; 9883 9884 error = em_valid_nvm_bank_detect_ich8lan(hw, &flash_bank); 9885 if (error != E1000_SUCCESS) { 9886 DEBUGOUT("Could not detect valid bank, assuming bank 0\n"); 9887 flash_bank = 0; 9888 } 9889 9890 /* 9891 * Adjust offset appropriately if we're on bank 1 - adjust for word 9892 * size 9893 */ 9894 bank_offset = flash_bank * (hw->flash_bank_size * 2); 9895 9896 for (i = 0; i < words; i++) { 9897 if (hw->eeprom_shadow_ram != NULL && 9898 hw->eeprom_shadow_ram[offset + i].modified == TRUE) { 9899 data[i] = 9900 hw->eeprom_shadow_ram[offset + i].eeprom_word; 9901 } else { 9902 /* The NVM part needs a byte offset, hence * 2 */ 9903 act_offset = bank_offset + ((offset + i) * 2); 9904 error = em_read_ich8_word(hw, act_offset, &word); 9905 if (error != E1000_SUCCESS) 9906 break; 9907 data[i] = word; 9908 } 9909 } 9910 9911 em_release_software_flag(hw); 9912 9913 return error; 9914 } 9915 9916 /****************************************************************************** 9917 * Writes a 16 bit word or words to the EEPROM using the ICH8's flash access 9918 * register. Actually, writes are written to the shadow ram cache in the hw 9919 * structure hw->em_shadow_ram. em_commit_shadow_ram flushes this to 9920 * the NVM, which occurs when the NVM checksum is updated. 9921 * 9922 * hw - Struct containing variables accessed by shared code 9923 * offset - offset of word in the EEPROM to write 9924 * words - number of words to write 9925 * data - words to write to the EEPROM 9926 *****************************************************************************/ 9927 STATIC int32_t 9928 em_write_eeprom_ich8(struct em_hw *hw, uint16_t offset, uint16_t words, 9929 uint16_t *data) 9930 { 9931 uint32_t i = 0; 9932 int32_t error = E1000_SUCCESS; 9933 error = em_get_software_flag(hw); 9934 if (error != E1000_SUCCESS) 9935 return error; 9936 /* 9937 * A driver can write to the NVM only if it has eeprom_shadow_ram 9938 * allocated. Subsequent reads to the modified words are read from 9939 * this cached structure as well. Writes will only go into this 9940 * cached structure unless it's followed by a call to 9941 * em_update_eeprom_checksum() where it will commit the changes and 9942 * clear the "modified" field. 9943 */ 9944 if (hw->eeprom_shadow_ram != NULL) { 9945 for (i = 0; i < words; i++) { 9946 if ((offset + i) < E1000_SHADOW_RAM_WORDS) { 9947 hw->eeprom_shadow_ram[offset + i].modified = 9948 TRUE; 9949 hw->eeprom_shadow_ram[offset + i].eeprom_word = 9950 data[i]; 9951 } else { 9952 error = -E1000_ERR_EEPROM; 9953 break; 9954 } 9955 } 9956 } else { 9957 /* 9958 * Drivers have the option to not allocate eeprom_shadow_ram 9959 * as long as they don't perform any NVM writes. An attempt 9960 * in doing so will result in this error. 9961 */ 9962 error = -E1000_ERR_EEPROM; 9963 } 9964 9965 em_release_software_flag(hw); 9966 9967 return error; 9968 } 9969 9970 /****************************************************************************** 9971 * This function does initial flash setup so that a new read/write/erase cycle 9972 * can be started. 9973 * 9974 * hw - The pointer to the hw structure 9975 ****************************************************************************/ 9976 STATIC int32_t 9977 em_ich8_cycle_init(struct em_hw *hw) 9978 { 9979 union ich8_hws_flash_status hsfsts; 9980 int32_t error = E1000_ERR_EEPROM; 9981 int32_t i = 0; 9982 DEBUGFUNC("em_ich8_cycle_init"); 9983 9984 if (hw->mac_type >= em_pch_spt) 9985 hsfsts.regval = E1000_READ_ICH_FLASH_REG32(hw, 9986 ICH_FLASH_HSFSTS) & 0xFFFFUL; 9987 else 9988 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, 9989 ICH_FLASH_HSFSTS); 9990 9991 /* May be check the Flash Des Valid bit in Hw status */ 9992 if (hsfsts.hsf_status.fldesvalid == 0) { 9993 DEBUGOUT("Flash descriptor invalid. SW Sequencing must be" 9994 " used."); 9995 return error; 9996 } 9997 /* Clear FCERR in Hw status by writing 1 */ 9998 /* Clear DAEL in Hw status by writing a 1 */ 9999 hsfsts.hsf_status.flcerr = 1; 10000 hsfsts.hsf_status.dael = 1; 10001 if (hw->mac_type >= em_pch_spt) 10002 E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_HSFSTS, 10003 hsfsts.regval & 0xFFFFUL); 10004 else 10005 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, 10006 hsfsts.regval); 10007 /* 10008 * Either we should have a hardware SPI cycle in progress bit to 10009 * check against, in order to start a new cycle or FDONE bit should 10010 * be changed in the hardware so that it is 1 after hardware reset, 10011 * which can then be used as an indication whether a cycle is in 10012 * progress or has been completed .. we should also have some 10013 * software semaphore mechanism to guard FDONE or the cycle in 10014 * progress bit so that two threads access to those bits can be 10015 * sequentiallized or a way so that 2 threads dont start the cycle at 10016 * the same time 10017 */ 10018 10019 if (hsfsts.hsf_status.flcinprog == 0) { 10020 /* 10021 * There is no cycle running at present, so we can start a 10022 * cycle 10023 */ 10024 /* Begin by setting Flash Cycle Done. */ 10025 hsfsts.hsf_status.flcdone = 1; 10026 if (hw->mac_type >= em_pch_spt) 10027 E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_HSFSTS, 10028 hsfsts.regval & 0xFFFFUL); 10029 else 10030 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, 10031 hsfsts.regval); 10032 error = E1000_SUCCESS; 10033 } else { 10034 /* 10035 * otherwise poll for sometime so the current cycle has a 10036 * chance to end before giving up. 10037 */ 10038 for (i = 0; i < ICH_FLASH_COMMAND_TIMEOUT; i++) { 10039 if (hw->mac_type >= em_pch_spt) 10040 hsfsts.regval = E1000_READ_ICH_FLASH_REG32( 10041 hw, ICH_FLASH_HSFSTS) & 0xFFFFUL; 10042 else 10043 hsfsts.regval = E1000_READ_ICH_FLASH_REG16( 10044 hw, ICH_FLASH_HSFSTS); 10045 if (hsfsts.hsf_status.flcinprog == 0) { 10046 error = E1000_SUCCESS; 10047 break; 10048 } 10049 usec_delay(1); 10050 } 10051 if (error == E1000_SUCCESS) { 10052 /* 10053 * Successful in waiting for previous cycle to 10054 * timeout, now set the Flash Cycle Done. 10055 */ 10056 hsfsts.hsf_status.flcdone = 1; 10057 if (hw->mac_type >= em_pch_spt) 10058 E1000_WRITE_ICH_FLASH_REG32(hw, 10059 ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFFUL); 10060 else 10061 E1000_WRITE_ICH_FLASH_REG16(hw, 10062 ICH_FLASH_HSFSTS, hsfsts.regval); 10063 } else { 10064 DEBUGOUT("Flash controller busy, cannot get access"); 10065 } 10066 } 10067 return error; 10068 } 10069 10070 /****************************************************************************** 10071 * This function starts a flash cycle and waits for its completion 10072 * 10073 * hw - The pointer to the hw structure 10074 *****************************************************************************/ 10075 STATIC int32_t 10076 em_ich8_flash_cycle(struct em_hw *hw, uint32_t timeout) 10077 { 10078 union ich8_hws_flash_ctrl hsflctl; 10079 union ich8_hws_flash_status hsfsts; 10080 int32_t error = E1000_ERR_EEPROM; 10081 uint32_t i = 0; 10082 10083 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ 10084 if (hw->mac_type >= em_pch_spt) 10085 hsflctl.regval = E1000_READ_ICH_FLASH_REG32(hw, 10086 ICH_FLASH_HSFSTS) >> 16; 10087 else 10088 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, 10089 ICH_FLASH_HSFCTL); 10090 hsflctl.hsf_ctrl.flcgo = 1; 10091 10092 if (hw->mac_type >= em_pch_spt) 10093 E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_HSFSTS, 10094 (uint32_t)hsflctl.regval << 16); 10095 else 10096 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, 10097 hsflctl.regval); 10098 10099 /* wait till FDONE bit is set to 1 */ 10100 do { 10101 if (hw->mac_type >= em_pch_spt) 10102 hsfsts.regval = E1000_READ_ICH_FLASH_REG32(hw, 10103 ICH_FLASH_HSFSTS) & 0xFFFFUL; 10104 else 10105 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, 10106 ICH_FLASH_HSFSTS); 10107 if (hsfsts.hsf_status.flcdone == 1) 10108 break; 10109 usec_delay(1); 10110 i++; 10111 } while (i < timeout); 10112 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) { 10113 error = E1000_SUCCESS; 10114 } 10115 return error; 10116 } 10117 10118 /****************************************************************************** 10119 * Reads a byte or word from the NVM using the ICH8 flash access registers. 10120 * 10121 * hw - The pointer to the hw structure 10122 * index - The index of the byte or word to read. 10123 * size - Size of data to read, 1=byte 2=word 10124 * data - Pointer to the word to store the value read. 10125 *****************************************************************************/ 10126 STATIC int32_t 10127 em_read_ich8_data(struct em_hw *hw, uint32_t index, uint32_t size, 10128 uint16_t *data) 10129 { 10130 union ich8_hws_flash_status hsfsts; 10131 union ich8_hws_flash_ctrl hsflctl; 10132 uint32_t flash_linear_address; 10133 uint32_t flash_data = 0; 10134 int32_t error = -E1000_ERR_EEPROM; 10135 int32_t count = 0; 10136 DEBUGFUNC("em_read_ich8_data"); 10137 10138 if (size < 1 || size > 2 || data == 0x0 || 10139 index > ICH_FLASH_LINEAR_ADDR_MASK) 10140 return error; 10141 10142 flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) + 10143 hw->flash_base_addr; 10144 10145 do { 10146 usec_delay(1); 10147 /* Steps */ 10148 error = em_ich8_cycle_init(hw); 10149 if (error != E1000_SUCCESS) 10150 break; 10151 10152 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, 10153 ICH_FLASH_HSFCTL); 10154 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 10155 hsflctl.hsf_ctrl.fldbcount = size - 1; 10156 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; 10157 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, 10158 hsflctl.regval); 10159 /* 10160 * Write the last 24 bits of index into Flash Linear address 10161 * field in Flash Address 10162 */ 10163 /* TODO: TBD maybe check the index against the size of flash */ 10164 10165 E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_FADDR, 10166 flash_linear_address); 10167 10168 error = em_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT); 10169 /* 10170 * Check if FCERR is set to 1, if set to 1, clear it and try 10171 * the whole sequence a few more times, else read in (shift 10172 * in) the Flash Data0, the order is least significant byte 10173 * first msb to lsb 10174 */ 10175 if (error == E1000_SUCCESS) { 10176 flash_data = E1000_READ_ICH_FLASH_REG(hw, 10177 ICH_FLASH_FDATA0); 10178 if (size == 1) { 10179 *data = (uint8_t) (flash_data & 0x000000FF); 10180 } else if (size == 2) { 10181 *data = (uint16_t) (flash_data & 0x0000FFFF); 10182 } 10183 break; 10184 } else { 10185 /* 10186 * If we've gotten here, then things are probably 10187 * completely hosed, but if the error condition is 10188 * detected, it won't hurt to give it another 10189 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 10190 */ 10191 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, 10192 ICH_FLASH_HSFSTS); 10193 if (hsfsts.hsf_status.flcerr == 1) { 10194 /* Repeat for some time before giving up. */ 10195 continue; 10196 } else if (hsfsts.hsf_status.flcdone == 0) { 10197 DEBUGOUT("Timeout error - flash cycle did not" 10198 " complete."); 10199 break; 10200 } 10201 } 10202 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 10203 10204 return error; 10205 } 10206 10207 STATIC int32_t 10208 em_read_ich8_data32(struct em_hw *hw, uint32_t offset, uint32_t *data) 10209 { 10210 union ich8_hws_flash_status hsfsts; 10211 union ich8_hws_flash_ctrl hsflctl; 10212 uint32_t flash_linear_address; 10213 int32_t error = -E1000_ERR_EEPROM; 10214 uint32_t count = 0; 10215 DEBUGFUNC("em_read_ich8_data32"); 10216 10217 if (hw->mac_type < em_pch_spt) 10218 return error; 10219 if (offset > ICH_FLASH_LINEAR_ADDR_MASK) 10220 return error; 10221 flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & offset) + 10222 hw->flash_base_addr; 10223 10224 do { 10225 usec_delay(1); 10226 /* Steps */ 10227 error = em_ich8_cycle_init(hw); 10228 if (error != E1000_SUCCESS) 10229 break; 10230 10231 /* 32 bit accesses in SPT. */ 10232 hsflctl.regval = E1000_READ_ICH_FLASH_REG32(hw, 10233 ICH_FLASH_HSFSTS) >> 16; 10234 10235 hsflctl.hsf_ctrl.fldbcount = sizeof(uint32_t) - 1; 10236 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; 10237 10238 E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_HSFSTS, 10239 (uint32_t)hsflctl.regval << 16); 10240 /* 10241 * Write the last 24 bits of offset into Flash Linear address 10242 * field in Flash Address 10243 */ 10244 /* TODO: TBD maybe check the offset against the size of flash */ 10245 10246 E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_FADDR, 10247 flash_linear_address); 10248 10249 error = em_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT); 10250 /* 10251 * Check if FCERR is set to 1, if set to 1, clear it and try 10252 * the whole sequence a few more times, else read in (shift 10253 * in) the Flash Data0, the order is least significant byte 10254 * first msb to lsb 10255 */ 10256 if (error == E1000_SUCCESS) { 10257 (*data) = (uint32_t)E1000_READ_ICH_FLASH_REG32(hw, 10258 ICH_FLASH_FDATA0); 10259 break; 10260 } else { 10261 /* 10262 * If we've gotten here, then things are probably 10263 * completely hosed, but if the error condition is 10264 * detected, it won't hurt to give it another 10265 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 10266 */ 10267 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, 10268 ICH_FLASH_HSFSTS); 10269 if (hsfsts.hsf_status.flcerr == 1) { 10270 /* Repeat for some time before giving up. */ 10271 continue; 10272 } else if (hsfsts.hsf_status.flcdone == 0) { 10273 DEBUGOUT("Timeout error - flash cycle did not" 10274 " complete."); 10275 break; 10276 } 10277 } 10278 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 10279 10280 return error; 10281 } 10282 10283 10284 /****************************************************************************** 10285 * Writes One /two bytes to the NVM using the ICH8 flash access registers. 10286 * 10287 * hw - The pointer to the hw structure 10288 * index - The index of the byte/word to write. 10289 * size - Size of data to read, 1=byte 2=word 10290 * data - The byte(s) to write to the NVM. 10291 *****************************************************************************/ 10292 STATIC int32_t 10293 em_write_ich8_data(struct em_hw *hw, uint32_t index, uint32_t size, 10294 uint16_t data) 10295 { 10296 union ich8_hws_flash_status hsfsts; 10297 union ich8_hws_flash_ctrl hsflctl; 10298 uint32_t flash_linear_address; 10299 uint32_t flash_data = 0; 10300 int32_t error = -E1000_ERR_EEPROM; 10301 int32_t count = 0; 10302 DEBUGFUNC("em_write_ich8_data"); 10303 10304 if (hw->mac_type >= em_pch_spt) 10305 return -E1000_ERR_EEPROM; 10306 if (size < 1 || size > 2 || data > size * 0xff || 10307 index > ICH_FLASH_LINEAR_ADDR_MASK) 10308 return error; 10309 10310 flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) + 10311 hw->flash_base_addr; 10312 10313 do { 10314 usec_delay(1); 10315 /* Steps */ 10316 error = em_ich8_cycle_init(hw); 10317 if (error != E1000_SUCCESS) 10318 break; 10319 10320 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, 10321 ICH_FLASH_HSFCTL); 10322 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 10323 hsflctl.hsf_ctrl.fldbcount = size - 1; 10324 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; 10325 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, 10326 hsflctl.regval); 10327 /* 10328 * Write the last 24 bits of index into Flash Linear address 10329 * field in Flash Address 10330 */ 10331 E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_FADDR, 10332 flash_linear_address); 10333 10334 if (size == 1) 10335 flash_data = (uint32_t) data & 0x00FF; 10336 else 10337 flash_data = (uint32_t) data; 10338 10339 E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_FDATA0, flash_data); 10340 /* 10341 * check if FCERR is set to 1 , if set to 1, clear it and try 10342 * the whole sequence a few more times else done 10343 */ 10344 error = em_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT); 10345 if (error == E1000_SUCCESS) { 10346 break; 10347 } else { 10348 /* 10349 * If we're here, then things are most likely 10350 * completely hosed, but if the error condition is 10351 * detected, it won't hurt to give it another 10352 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 10353 */ 10354 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, 10355 ICH_FLASH_HSFSTS); 10356 if (hsfsts.hsf_status.flcerr == 1) { 10357 /* Repeat for some time before giving up. */ 10358 continue; 10359 } else if (hsfsts.hsf_status.flcdone == 0) { 10360 DEBUGOUT("Timeout error - flash cycle did not" 10361 " complete."); 10362 break; 10363 } 10364 } 10365 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 10366 10367 return error; 10368 } 10369 10370 /****************************************************************************** 10371 * Reads a single byte from the NVM using the ICH8 flash access registers. 10372 * 10373 * hw - pointer to em_hw structure 10374 * index - The index of the byte to read. 10375 * data - Pointer to a byte to store the value read. 10376 *****************************************************************************/ 10377 STATIC int32_t 10378 em_read_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t *data) 10379 { 10380 int32_t status = E1000_SUCCESS; 10381 uint16_t word = 0; 10382 10383 if (hw->mac_type >= em_pch_spt) 10384 return -E1000_ERR_EEPROM; 10385 else 10386 status = em_read_ich8_data(hw, index, 1, &word); 10387 if (status == E1000_SUCCESS) { 10388 *data = (uint8_t) word; 10389 } 10390 return status; 10391 } 10392 10393 /****************************************************************************** 10394 * Writes a single byte to the NVM using the ICH8 flash access registers. 10395 * Performs verification by reading back the value and then going through 10396 * a retry algorithm before giving up. 10397 * 10398 * hw - pointer to em_hw structure 10399 * index - The index of the byte to write. 10400 * byte - The byte to write to the NVM. 10401 *****************************************************************************/ 10402 STATIC int32_t 10403 em_verify_write_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t byte) 10404 { 10405 int32_t error = E1000_SUCCESS; 10406 int32_t program_retries = 0; 10407 DEBUGOUT2("Byte := %2.2X Offset := %d\n", byte, index); 10408 10409 error = em_write_ich8_byte(hw, index, byte); 10410 10411 if (error != E1000_SUCCESS) { 10412 for (program_retries = 0; program_retries < 100; 10413 program_retries++) { 10414 DEBUGOUT2("Retrying \t Byte := %2.2X Offset := %d\n", 10415 byte, index); 10416 error = em_write_ich8_byte(hw, index, byte); 10417 usec_delay(100); 10418 if (error == E1000_SUCCESS) 10419 break; 10420 } 10421 } 10422 if (program_retries == 100) 10423 error = E1000_ERR_EEPROM; 10424 10425 return error; 10426 } 10427 10428 /****************************************************************************** 10429 * Writes a single byte to the NVM using the ICH8 flash access registers. 10430 * 10431 * hw - pointer to em_hw structure 10432 * index - The index of the byte to read. 10433 * data - The byte to write to the NVM. 10434 *****************************************************************************/ 10435 STATIC int32_t 10436 em_write_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t data) 10437 { 10438 int32_t status = E1000_SUCCESS; 10439 uint16_t word = (uint16_t) data; 10440 status = em_write_ich8_data(hw, index, 1, word); 10441 10442 return status; 10443 } 10444 10445 /****************************************************************************** 10446 * Reads a dword from the NVM using the ICH8 flash access registers. 10447 * 10448 * hw - pointer to em_hw structure 10449 * index - The starting BYTE index of the word to read. 10450 * data - Pointer to a word to store the value read. 10451 *****************************************************************************/ 10452 STATIC int32_t 10453 em_read_ich8_dword(struct em_hw *hw, uint32_t index, uint32_t *data) 10454 { 10455 int32_t status = E1000_SUCCESS; 10456 status = em_read_ich8_data32(hw, index, data); 10457 return status; 10458 } 10459 10460 /****************************************************************************** 10461 * Reads a word from the NVM using the ICH8 flash access registers. 10462 * 10463 * hw - pointer to em_hw structure 10464 * index - The starting byte index of the word to read. 10465 * data - Pointer to a word to store the value read. 10466 *****************************************************************************/ 10467 STATIC int32_t 10468 em_read_ich8_word(struct em_hw *hw, uint32_t index, uint16_t *data) 10469 { 10470 int32_t status = E1000_SUCCESS; 10471 status = em_read_ich8_data(hw, index, 2, data); 10472 return status; 10473 } 10474 10475 /****************************************************************************** 10476 * Erases the bank specified. Each bank may be a 4, 8 or 64k block. Banks are 0 10477 * based. 10478 * 10479 * hw - pointer to em_hw structure 10480 * bank - 0 for first bank, 1 for second bank 10481 * 10482 * Note that this function may actually erase as much as 8 or 64 KBytes. The 10483 * amount of NVM used in each bank is a *minimum* of 4 KBytes, but in fact the 10484 * bank size may be 4, 8 or 64 KBytes 10485 *****************************************************************************/ 10486 int32_t 10487 em_erase_ich8_4k_segment(struct em_hw *hw, uint32_t bank) 10488 { 10489 union ich8_hws_flash_status hsfsts; 10490 union ich8_hws_flash_ctrl hsflctl; 10491 uint32_t flash_linear_address; 10492 int32_t count = 0; 10493 int32_t error = E1000_ERR_EEPROM; 10494 int32_t iteration; 10495 int32_t sub_sector_size = 0; 10496 int32_t bank_size; 10497 int32_t j = 0; 10498 int32_t error_flag = 0; 10499 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 10500 /* 10501 * Determine HW Sector size: Read BERASE bits of Hw flash Status 10502 * register 10503 */ 10504 /* 10505 * 00: The Hw sector is 256 bytes, hence we need to erase 16 10506 * consecutive sectors. The start index for the nth Hw sector can be 10507 * calculated as bank * 4096 + n * 256 01: The Hw sector is 4K bytes, 10508 * hence we need to erase 1 sector. The start index for the nth Hw 10509 * sector can be calculated as bank * 4096 10: The HW sector is 8K 10510 * bytes 11: The Hw sector size is 64K bytes 10511 */ 10512 if (hsfsts.hsf_status.berasesz == 0x0) { 10513 /* Hw sector size 256 */ 10514 sub_sector_size = ICH_FLASH_SEG_SIZE_256; 10515 bank_size = ICH_FLASH_SECTOR_SIZE; 10516 iteration = ICH_FLASH_SECTOR_SIZE / ICH_FLASH_SEG_SIZE_256; 10517 } else if (hsfsts.hsf_status.berasesz == 0x1) { 10518 bank_size = ICH_FLASH_SEG_SIZE_4K; 10519 iteration = 1; 10520 } else if (hsfsts.hsf_status.berasesz == 0x2) { 10521 if (hw->mac_type == em_ich9lan) { 10522 uint32_t gfpreg, sector_base_addr, sector_end_addr; 10523 gfpreg = E1000_READ_ICH_FLASH_REG(hw, 10524 ICH_FLASH_GFPREG); 10525 /* 10526 * sector_X_addr is a "sector"-aligned address (4096 bytes) 10527 * Add 1 to sector_end_addr since this sector is included in 10528 * the overall size. 10529 */ 10530 sector_base_addr = gfpreg & ICH_GFPREG_BASE_MASK; 10531 sector_end_addr = 10532 ((gfpreg >> 16) & ICH_GFPREG_BASE_MASK) + 1; 10533 10534 /* 10535 * find total size of the NVM, then cut in half since the total 10536 * size represents two separate NVM banks. 10537 */ 10538 bank_size = (sector_end_addr - sector_base_addr) 10539 << ICH_FLASH_SECT_ADDR_SHIFT; 10540 bank_size /= 2; 10541 /* Word align */ 10542 bank_size = 10543 (bank_size / sizeof(uint16_t)) * sizeof(uint16_t); 10544 10545 sub_sector_size = ICH_FLASH_SEG_SIZE_8K; 10546 iteration = bank_size / ICH_FLASH_SEG_SIZE_8K; 10547 } else { 10548 return error; 10549 } 10550 } else if (hsfsts.hsf_status.berasesz == 0x3) { 10551 bank_size = ICH_FLASH_SEG_SIZE_64K; 10552 iteration = 1; 10553 } else { 10554 return error; 10555 } 10556 10557 for (j = 0; j < iteration; j++) { 10558 do { 10559 count++; 10560 /* Steps */ 10561 error = em_ich8_cycle_init(hw); 10562 if (error != E1000_SUCCESS) { 10563 error_flag = 1; 10564 break; 10565 } 10566 /* 10567 * Write a value 11 (block Erase) in Flash Cycle 10568 * field in Hw flash Control 10569 */ 10570 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, 10571 ICH_FLASH_HSFCTL); 10572 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE; 10573 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, 10574 hsflctl.regval); 10575 /* 10576 * Write the last 24 bits of an index within the 10577 * block into Flash Linear address field in Flash 10578 * Address. This probably needs to be calculated 10579 * here based off the on-chip erase sector size and 10580 * the software bank size (4, 8 or 64 KBytes) 10581 */ 10582 flash_linear_address = 10583 bank * bank_size + j * sub_sector_size; 10584 flash_linear_address += hw->flash_base_addr; 10585 flash_linear_address &= ICH_FLASH_LINEAR_ADDR_MASK; 10586 10587 E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_FADDR, 10588 flash_linear_address); 10589 10590 error = 10591 em_ich8_flash_cycle(hw, ICH_FLASH_ERASE_TIMEOUT); 10592 /* 10593 * Check if FCERR is set to 1. If 1, clear it and 10594 * try the whole sequence a few more times else Done 10595 */ 10596 if (error == E1000_SUCCESS) { 10597 break; 10598 } else { 10599 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, 10600 ICH_FLASH_HSFSTS); 10601 if (hsfsts.hsf_status.flcerr == 1) { 10602 /* 10603 * repeat for some time before giving 10604 * up 10605 */ 10606 continue; 10607 } else if (hsfsts.hsf_status.flcdone == 0) { 10608 error_flag = 1; 10609 break; 10610 } 10611 } 10612 } while ((count < ICH_FLASH_CYCLE_REPEAT_COUNT) && !error_flag); 10613 if (error_flag == 1) 10614 break; 10615 } 10616 if (error_flag != 1) 10617 error = E1000_SUCCESS; 10618 return error; 10619 } 10620 10621 /****************************************************************************** 10622 * Reads 16-bit words from the OTP. Return error when the word is not 10623 * stored in OTP. 10624 * 10625 * hw - Struct containing variables accessed by shared code 10626 * offset - offset of word in the OTP to read 10627 * data - word read from the OTP 10628 * words - number of words to read 10629 *****************************************************************************/ 10630 STATIC int32_t 10631 em_read_invm_i210(struct em_hw *hw, uint16_t offset, uint16_t words, 10632 uint16_t *data) 10633 { 10634 int32_t ret_val = E1000_SUCCESS; 10635 10636 switch (offset) 10637 { 10638 case EEPROM_MAC_ADDR_WORD0: 10639 case EEPROM_MAC_ADDR_WORD1: 10640 case EEPROM_MAC_ADDR_WORD2: 10641 /* Generate random MAC address if there's none. */ 10642 ret_val = em_read_invm_word_i210(hw, offset, data); 10643 if (ret_val != E1000_SUCCESS) { 10644 DEBUGOUT("MAC Addr not found in iNVM\n"); 10645 *data = 0xFFFF; 10646 ret_val = E1000_SUCCESS; 10647 } 10648 break; 10649 case EEPROM_INIT_CONTROL2_REG: 10650 ret_val = em_read_invm_word_i210(hw, offset, data); 10651 if (ret_val != E1000_SUCCESS) { 10652 *data = NVM_INIT_CTRL_2_DEFAULT_I211; 10653 ret_val = E1000_SUCCESS; 10654 } 10655 break; 10656 case EEPROM_INIT_CONTROL4_REG: 10657 ret_val = em_read_invm_word_i210(hw, offset, data); 10658 if (ret_val != E1000_SUCCESS) { 10659 *data = NVM_INIT_CTRL_4_DEFAULT_I211; 10660 ret_val = E1000_SUCCESS; 10661 } 10662 break; 10663 case EEPROM_LED_1_CFG: 10664 ret_val = em_read_invm_word_i210(hw, offset, data); 10665 if (ret_val != E1000_SUCCESS) { 10666 *data = NVM_LED_1_CFG_DEFAULT_I211; 10667 ret_val = E1000_SUCCESS; 10668 } 10669 break; 10670 case EEPROM_LED_0_2_CFG: 10671 ret_val = em_read_invm_word_i210(hw, offset, data); 10672 if (ret_val != E1000_SUCCESS) { 10673 *data = NVM_LED_0_2_CFG_DEFAULT_I211; 10674 ret_val = E1000_SUCCESS; 10675 } 10676 break; 10677 case EEPROM_ID_LED_SETTINGS: 10678 ret_val = em_read_invm_word_i210(hw, offset, data); 10679 if (ret_val != E1000_SUCCESS) { 10680 *data = ID_LED_RESERVED_FFFF; 10681 ret_val = E1000_SUCCESS; 10682 } 10683 break; 10684 default: 10685 DEBUGOUT1("NVM word 0x%02x is not mapped.\n", offset); 10686 *data = NVM_RESERVED_WORD; 10687 break; 10688 } 10689 10690 return ret_val; 10691 } 10692 10693 /****************************************************************************** 10694 * Reads 16-bit words from the OTP. Return error when the word is not 10695 * stored in OTP. 10696 * 10697 * hw - Struct containing variables accessed by shared code 10698 * offset - offset of word in the OTP to read 10699 * data - word read from the OTP 10700 *****************************************************************************/ 10701 STATIC int32_t 10702 em_read_invm_word_i210(struct em_hw *hw, uint16_t address, uint16_t *data) 10703 { 10704 int32_t error = -E1000_NOT_IMPLEMENTED; 10705 uint32_t invm_dword; 10706 uint16_t i; 10707 uint8_t record_type, word_address; 10708 10709 for (i = 0; i < INVM_SIZE; i++) { 10710 invm_dword = EM_READ_REG(hw, E1000_INVM_DATA_REG(i)); 10711 /* Get record type */ 10712 record_type = INVM_DWORD_TO_RECORD_TYPE(invm_dword); 10713 if (record_type == INVM_UNINITIALIZED_STRUCTURE) 10714 break; 10715 if (record_type == INVM_CSR_AUTOLOAD_STRUCTURE) 10716 i += INVM_CSR_AUTOLOAD_DATA_SIZE_IN_DWORDS; 10717 if (record_type == INVM_RSA_KEY_SHA256_STRUCTURE) 10718 i += INVM_RSA_KEY_SHA256_DATA_SIZE_IN_DWORDS; 10719 if (record_type == INVM_WORD_AUTOLOAD_STRUCTURE) { 10720 word_address = INVM_DWORD_TO_WORD_ADDRESS(invm_dword); 10721 if (word_address == address) { 10722 *data = INVM_DWORD_TO_WORD_DATA(invm_dword); 10723 error = E1000_SUCCESS; 10724 break; 10725 } 10726 } 10727 } 10728 10729 return error; 10730 } 10731 10732 STATIC int32_t 10733 em_init_lcd_from_nvm_config_region(struct em_hw *hw, uint32_t cnf_base_addr, 10734 uint32_t cnf_size) 10735 { 10736 uint32_t ret_val = E1000_SUCCESS; 10737 uint16_t word_addr, reg_data, reg_addr; 10738 uint16_t i; 10739 /* cnf_base_addr is in DWORD */ 10740 word_addr = (uint16_t) (cnf_base_addr << 1); 10741 10742 /* cnf_size is returned in size of dwords */ 10743 for (i = 0; i < cnf_size; i++) { 10744 ret_val = 10745 em_read_eeprom(hw, (word_addr + i * 2), 1, ®_data); 10746 if (ret_val) 10747 return ret_val; 10748 10749 ret_val = 10750 em_read_eeprom(hw, (word_addr + i * 2 + 1), 1, ®_addr); 10751 if (ret_val) 10752 return ret_val; 10753 10754 ret_val = em_get_software_flag(hw); 10755 if (ret_val != E1000_SUCCESS) 10756 return ret_val; 10757 10758 ret_val = 10759 em_write_phy_reg_ex(hw, (uint32_t) reg_addr, reg_data); 10760 10761 em_release_software_flag(hw); 10762 } 10763 10764 return ret_val; 10765 } 10766 10767 /****************************************************************************** 10768 * This function initializes the PHY from the NVM on ICH8 platforms. This 10769 * is needed due to an issue where the NVM configuration is not properly 10770 * autoloaded after power transitions. Therefore, after each PHY reset, we 10771 * will load the configuration data out of the NVM manually. 10772 * 10773 * hw: Struct containing variables accessed by shared code 10774 *****************************************************************************/ 10775 STATIC int32_t 10776 em_init_lcd_from_nvm(struct em_hw *hw) 10777 { 10778 uint32_t reg_data, cnf_base_addr, cnf_size, ret_val, loop, sw_cfg_mask; 10779 if (hw->phy_type != em_phy_igp_3) 10780 return E1000_SUCCESS; 10781 10782 /* Check if SW needs configure the PHY */ 10783 if (hw->device_id == E1000_DEV_ID_ICH8_IGP_M_AMT || 10784 hw->device_id == E1000_DEV_ID_ICH8_IGP_M || 10785 hw->mac_type == em_pchlan || 10786 hw->mac_type == em_pch2lan || 10787 hw->mac_type == em_pch_lpt || 10788 hw->mac_type == em_pch_spt || 10789 hw->mac_type == em_pch_cnp) 10790 sw_cfg_mask = FEXTNVM_SW_CONFIG_ICH8M; 10791 else 10792 sw_cfg_mask = FEXTNVM_SW_CONFIG; 10793 10794 reg_data = E1000_READ_REG(hw, FEXTNVM); 10795 if (!(reg_data & sw_cfg_mask)) 10796 return E1000_SUCCESS; 10797 10798 /* Wait for basic configuration completes before proceeding */ 10799 loop = 0; 10800 do { 10801 reg_data = 10802 E1000_READ_REG(hw, STATUS) & E1000_STATUS_LAN_INIT_DONE; 10803 usec_delay(100); 10804 loop++; 10805 } while ((!reg_data) && (loop < 50)); 10806 10807 /* Clear the Init Done bit for the next init event */ 10808 reg_data = E1000_READ_REG(hw, STATUS); 10809 reg_data &= ~E1000_STATUS_LAN_INIT_DONE; 10810 E1000_WRITE_REG(hw, STATUS, reg_data); 10811 /* 10812 * Make sure HW does not configure LCD from PHY extended 10813 * configuration before SW configuration 10814 */ 10815 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL); 10816 if ((reg_data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) == 0x0000) { 10817 reg_data = E1000_READ_REG(hw, EXTCNF_SIZE); 10818 cnf_size = reg_data & E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH; 10819 cnf_size >>= 16; 10820 if (cnf_size) { 10821 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL); 10822 cnf_base_addr = reg_data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER; 10823 /* cnf_base_addr is in DWORD */ 10824 cnf_base_addr >>= 16; 10825 10826 /* Configure LCD from extended configuration region. */ 10827 ret_val = em_init_lcd_from_nvm_config_region(hw, 10828 cnf_base_addr, cnf_size); 10829 if (ret_val) 10830 return ret_val; 10831 } 10832 } 10833 return E1000_SUCCESS; 10834 } 10835 10836 /****************************************************************************** 10837 * em_set_pciex_completion_timeout - set pci-e completion timeout 10838 * 10839 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms, 10840 * however the hardware default for these parts is 500us to 1ms which is less 10841 * than the 10ms recommended by the pci-e spec. To address this we need to 10842 * increase the value to either 10ms to 200ms for capability version 1 config, 10843 * or 16ms to 55ms for version 2. 10844 * 10845 * * hw - pointer to em_hw structure 10846 *****************************************************************************/ 10847 int32_t 10848 em_set_pciex_completion_timeout(struct em_hw *hw) 10849 { 10850 uint32_t gcr = E1000_READ_REG(hw, GCR); 10851 int32_t ret_val = E1000_SUCCESS; 10852 10853 /* Only take action if timeout value is not set by system BIOS */ 10854 if (gcr & E1000_GCR_CMPL_TMOUT_MASK) 10855 goto out; 10856 10857 DEBUGOUT("PCIe completion timeout not set by system BIOS."); 10858 10859 /* 10860 * If capababilities version is type 1 we can write the 10861 * timeout of 10ms to 200ms through the GCR register 10862 */ 10863 10864 if (!(gcr & E1000_GCR_CAP_VER2)) { 10865 gcr |= E1000_GCR_CMPL_TMOUT_10ms; 10866 DEBUGOUT("PCIe capability version 1 detected, setting \ 10867 completion timeout to 10ms."); 10868 goto out; 10869 } 10870 10871 /* 10872 * For version 2 capabilities we need to write the config space 10873 * directly in order to set the completion timeout value for 10874 * 16ms to 55ms 10875 * 10876 * XXX: Implement em_*_pcie_cap_reg() first. 10877 */ 10878 #if 0 10879 ret_val = em_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 10880 &pciex_devctl2); 10881 10882 if (ret_val) 10883 goto out; 10884 10885 pciex_devctl2 |= PCIE_DEVICE_CONTROL2_16ms; 10886 10887 ret_val = em_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 10888 &pciex_devctl2); 10889 #endif 10890 10891 out: 10892 10893 /* Disable completion timeout resend */ 10894 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND; 10895 10896 DEBUGOUT("PCIe completion timeout resend disabled."); 10897 10898 E1000_WRITE_REG(hw, GCR, gcr); 10899 return ret_val; 10900 } 10901 10902 /*************************************************************************** 10903 * Set slow MDIO access mode 10904 ***************************************************************************/ 10905 static int32_t 10906 em_set_mdio_slow_mode_hv(struct em_hw *hw) 10907 { 10908 int32_t ret_val; 10909 uint16_t data; 10910 DEBUGFUNC("em_set_mdio_slow_mode_hv"); 10911 10912 ret_val = em_read_phy_reg(hw, HV_KMRN_MODE_CTRL, &data); 10913 if (ret_val) 10914 return ret_val; 10915 10916 data |= HV_KMRN_MDIO_SLOW; 10917 10918 ret_val = em_write_phy_reg(hw, HV_KMRN_MODE_CTRL, data); 10919 10920 return ret_val; 10921 } 10922 10923 /*************************************************************************** 10924 * A series of Phy workarounds to be done after every PHY reset. 10925 ***************************************************************************/ 10926 int32_t 10927 em_hv_phy_workarounds_ich8lan(struct em_hw *hw) 10928 { 10929 int32_t ret_val = E1000_SUCCESS; 10930 uint16_t phy_data; 10931 uint16_t swfw; 10932 DEBUGFUNC("em_hv_phy_workarounds_ich8lan"); 10933 10934 if (hw->mac_type != em_pchlan) 10935 goto out; 10936 10937 swfw = E1000_SWFW_PHY0_SM; 10938 10939 /* Set MDIO slow mode before any other MDIO access */ 10940 if (hw->phy_type == em_phy_82577 || 10941 hw->phy_type == em_phy_82578) { 10942 ret_val = em_set_mdio_slow_mode_hv(hw); 10943 if (ret_val) 10944 goto out; 10945 } 10946 10947 /* Hanksville M Phy init for IEEE. */ 10948 if ((hw->revision_id == 2) && 10949 (hw->phy_type == em_phy_82577) && 10950 ((hw->phy_revision == 2) || (hw->phy_revision == 3))) { 10951 em_write_phy_reg(hw, 0x10, 0x8823); 10952 em_write_phy_reg(hw, 0x11, 0x0018); 10953 em_write_phy_reg(hw, 0x10, 0x8824); 10954 em_write_phy_reg(hw, 0x11, 0x0016); 10955 em_write_phy_reg(hw, 0x10, 0x8825); 10956 em_write_phy_reg(hw, 0x11, 0x001A); 10957 em_write_phy_reg(hw, 0x10, 0x888C); 10958 em_write_phy_reg(hw, 0x11, 0x0007); 10959 em_write_phy_reg(hw, 0x10, 0x888D); 10960 em_write_phy_reg(hw, 0x11, 0x0007); 10961 em_write_phy_reg(hw, 0x10, 0x888E); 10962 em_write_phy_reg(hw, 0x11, 0x0007); 10963 em_write_phy_reg(hw, 0x10, 0x8827); 10964 em_write_phy_reg(hw, 0x11, 0x0001); 10965 em_write_phy_reg(hw, 0x10, 0x8835); 10966 em_write_phy_reg(hw, 0x11, 0x0001); 10967 em_write_phy_reg(hw, 0x10, 0x8834); 10968 em_write_phy_reg(hw, 0x11, 0x0001); 10969 em_write_phy_reg(hw, 0x10, 0x8833); 10970 em_write_phy_reg(hw, 0x11, 0x0002); 10971 } 10972 10973 if (((hw->phy_type == em_phy_82577) && 10974 ((hw->phy_revision == 1) || (hw->phy_revision == 2))) || 10975 ((hw->phy_type == em_phy_82578) && (hw->phy_revision == 1))) { 10976 /* Disable generation of early preamble */ 10977 ret_val = em_write_phy_reg(hw, PHY_REG(769, 25), 0x4431); 10978 if (ret_val) 10979 goto out; 10980 10981 /* Preamble tuning for SSC */ 10982 ret_val = em_write_phy_reg(hw, PHY_REG(770, 16), 0xA204); 10983 if (ret_val) 10984 goto out; 10985 } 10986 10987 if (hw->phy_type == em_phy_82578) { 10988 /* 10989 * Return registers to default by doing a soft reset then 10990 * writing 0x3140 to the control register. 10991 */ 10992 if (hw->phy_revision < 2) { 10993 em_phy_reset(hw); 10994 ret_val = em_write_phy_reg(hw, PHY_CTRL, 0x3140); 10995 } 10996 } 10997 10998 if ((hw->revision_id == 2) && 10999 (hw->phy_type == em_phy_82577) && 11000 ((hw->phy_revision == 2) || (hw->phy_revision == 3))) { 11001 /* 11002 * Workaround for OEM (GbE) not operating after reset - 11003 * restart AN (twice) 11004 */ 11005 ret_val = em_write_phy_reg(hw, PHY_REG(0, 25), 0x0400); 11006 if (ret_val) 11007 goto out; 11008 ret_val = em_write_phy_reg(hw, PHY_REG(0, 25), 0x0400); 11009 if (ret_val) 11010 goto out; 11011 } 11012 11013 /* Select page 0 */ 11014 ret_val = em_swfw_sync_acquire(hw, swfw); 11015 if (ret_val) 11016 goto out; 11017 11018 hw->phy_addr = 1; 11019 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT, 0); 11020 em_swfw_sync_release(hw, swfw); 11021 if (ret_val) 11022 goto out; 11023 11024 /* Workaround for link disconnects on a busy hub in half duplex */ 11025 ret_val = em_read_phy_reg(hw, 11026 PHY_REG(BM_PORT_CTRL_PAGE, 17), 11027 &phy_data); 11028 if (ret_val) 11029 goto release; 11030 ret_val = em_write_phy_reg(hw, 11031 PHY_REG(BM_PORT_CTRL_PAGE, 17), 11032 phy_data & 0x00FF); 11033 release: 11034 out: 11035 return ret_val; 11036 } 11037 11038 11039 /*************************************************************************** 11040 * Si workaround 11041 * 11042 * This function works around a Si bug where the link partner can get 11043 * a link up indication before the PHY does. If small packets are sent 11044 * by the link partner they can be placed in the packet buffer without 11045 * being properly accounted for by the PHY and will stall preventing 11046 * further packets from being received. The workaround is to clear the 11047 * packet buffer after the PHY detects link up. 11048 ***************************************************************************/ 11049 int32_t 11050 em_link_stall_workaround_hv(struct em_hw *hw) 11051 { 11052 int32_t ret_val = E1000_SUCCESS; 11053 uint16_t phy_data; 11054 11055 if (hw->phy_type != em_phy_82578) 11056 goto out; 11057 11058 /* Do not apply workaround if in PHY loopback bit 14 set */ 11059 em_read_phy_reg(hw, PHY_CTRL, &phy_data); 11060 if (phy_data & E1000_PHY_CTRL_LOOPBACK) 11061 goto out; 11062 11063 /* check if link is up and at 1Gbps */ 11064 ret_val = em_read_phy_reg(hw, BM_CS_STATUS, &phy_data); 11065 if (ret_val) 11066 goto out; 11067 11068 phy_data &= BM_CS_STATUS_LINK_UP | 11069 BM_CS_STATUS_RESOLVED | 11070 BM_CS_STATUS_SPEED_MASK; 11071 11072 if (phy_data != (BM_CS_STATUS_LINK_UP | 11073 BM_CS_STATUS_RESOLVED | 11074 BM_CS_STATUS_SPEED_1000)) 11075 goto out; 11076 11077 msec_delay(200); 11078 11079 /* flush the packets in the fifo buffer */ 11080 ret_val = em_write_phy_reg(hw, HV_MUX_DATA_CTRL, 11081 HV_MUX_DATA_CTRL_GEN_TO_MAC | HV_MUX_DATA_CTRL_FORCE_SPEED); 11082 if (ret_val) 11083 goto out; 11084 11085 ret_val = em_write_phy_reg(hw, HV_MUX_DATA_CTRL, 11086 HV_MUX_DATA_CTRL_GEN_TO_MAC); 11087 11088 out: 11089 return ret_val; 11090 } 11091 11092 /**************************************************************************** 11093 * K1 Si workaround 11094 * 11095 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning 11096 * from a lower speed. This workaround disables K1 whenever link is at 1Gig. 11097 * If link is down, the function will restore the default K1 setting located 11098 * in the NVM. 11099 ****************************************************************************/ 11100 int32_t 11101 em_k1_gig_workaround_hv(struct em_hw *hw, boolean_t link) 11102 { 11103 int32_t ret_val; 11104 uint16_t phy_data; 11105 boolean_t k1_enable; 11106 11107 DEBUGFUNC("em_k1_gig_workaround_hv"); 11108 11109 if (hw->mac_type != em_pchlan) 11110 return E1000_SUCCESS; 11111 11112 ret_val = em_read_eeprom_ich8(hw, E1000_NVM_K1_CONFIG, 1, &phy_data); 11113 if (ret_val) 11114 return ret_val; 11115 11116 k1_enable = phy_data & E1000_NVM_K1_ENABLE ? TRUE : FALSE; 11117 11118 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */ 11119 if (link) { 11120 if (hw->phy_type == em_phy_82578) { 11121 ret_val = em_read_phy_reg(hw, BM_CS_STATUS, 11122 &phy_data); 11123 if (ret_val) 11124 return ret_val; 11125 11126 phy_data &= BM_CS_STATUS_LINK_UP | 11127 BM_CS_STATUS_RESOLVED | 11128 BM_CS_STATUS_SPEED_MASK; 11129 11130 if (phy_data == (BM_CS_STATUS_LINK_UP | 11131 BM_CS_STATUS_RESOLVED | 11132 BM_CS_STATUS_SPEED_1000)) 11133 k1_enable = FALSE; 11134 } 11135 11136 if (hw->phy_type == em_phy_82577) { 11137 ret_val = em_read_phy_reg(hw, HV_M_STATUS, 11138 &phy_data); 11139 if (ret_val) 11140 return ret_val; 11141 11142 phy_data &= HV_M_STATUS_LINK_UP | 11143 HV_M_STATUS_AUTONEG_COMPLETE | 11144 HV_M_STATUS_SPEED_MASK; 11145 11146 if (phy_data == (HV_M_STATUS_LINK_UP | 11147 HV_M_STATUS_AUTONEG_COMPLETE | 11148 HV_M_STATUS_SPEED_1000)) 11149 k1_enable = FALSE; 11150 } 11151 11152 /* Link stall fix for link up */ 11153 ret_val = em_write_phy_reg(hw, PHY_REG(770, 19), 11154 0x0100); 11155 if (ret_val) 11156 return ret_val; 11157 11158 } else { 11159 /* Link stall fix for link down */ 11160 ret_val = em_write_phy_reg(hw, PHY_REG(770, 19), 11161 0x4100); 11162 if (ret_val) 11163 return ret_val; 11164 } 11165 11166 ret_val = em_configure_k1_ich8lan(hw, k1_enable); 11167 11168 return ret_val; 11169 } 11170 11171 /* Workaround to set the K1 beacon duration for 82579 parts */ 11172 int32_t 11173 em_k1_workaround_lv(struct em_hw *hw) 11174 { 11175 int32_t ret_val; 11176 uint16_t phy_data; 11177 uint32_t mac_reg; 11178 11179 ret_val = em_read_phy_reg(hw, BM_CS_STATUS, &phy_data); 11180 if (ret_val) 11181 return ret_val; 11182 11183 if ((phy_data & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) 11184 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) { 11185 mac_reg = E1000_READ_REG(hw, FEXTNVM4); 11186 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK; 11187 11188 if (phy_data & HV_M_STATUS_SPEED_1000) 11189 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC; 11190 else 11191 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC; 11192 11193 E1000_WRITE_REG(hw, FEXTNVM4, mac_reg); 11194 } 11195 11196 return E1000_SUCCESS; 11197 } 11198 11199 /** 11200 * em_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP 11201 * 11202 * When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications 11203 * preventing further DMA write requests. Workaround the issue by disabling 11204 * the de-assertion of the clock request when in 1Gbps mode. 11205 * Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link 11206 * speeds in order to avoid Tx hangs. 11207 **/ 11208 int32_t 11209 em_k1_workaround_lpt_lp(struct em_hw *hw, boolean_t link) 11210 { 11211 uint32_t fextnvm6 = E1000_READ_REG(hw, FEXTNVM6); 11212 uint32_t status = E1000_READ_REG(hw, STATUS); 11213 int32_t ret_val = E1000_SUCCESS; 11214 uint16_t reg; 11215 11216 if (link && (status & E1000_STATUS_SPEED_1000)) { 11217 ret_val = em_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 11218 ®); 11219 if (ret_val) 11220 return ret_val; 11221 11222 ret_val = em_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 11223 reg & ~E1000_KMRNCTRLSTA_K1_ENABLE); 11224 if (ret_val) 11225 return ret_val; 11226 11227 usec_delay(10); 11228 11229 E1000_WRITE_REG(hw, FEXTNVM6, 11230 fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK); 11231 11232 ret_val = em_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 11233 reg); 11234 } else { 11235 /* clear FEXTNVM6 bit 8 on link down or 10/100 */ 11236 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK; 11237 11238 if (!link || ((status & E1000_STATUS_SPEED_100) && 11239 (status & E1000_STATUS_FD))) 11240 goto update_fextnvm6; 11241 11242 ret_val = em_read_phy_reg(hw, I217_INBAND_CTRL, ®); 11243 if (ret_val) 11244 return ret_val; 11245 11246 /* Clear link status transmit timeout */ 11247 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK; 11248 11249 if (status & E1000_STATUS_SPEED_100) { 11250 /* Set inband Tx timeout to 5x10us for 100Half */ 11251 reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT; 11252 11253 /* Do not extend the K1 entry latency for 100Half */ 11254 fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION; 11255 } else { 11256 /* Set inband Tx timeout to 50x10us for 10Full/Half */ 11257 reg |= 50 << 11258 I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT; 11259 11260 /* Extend the K1 entry latency for 10 Mbps */ 11261 fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION; 11262 } 11263 11264 ret_val = em_write_phy_reg(hw, I217_INBAND_CTRL, reg); 11265 if (ret_val) 11266 return ret_val; 11267 11268 update_fextnvm6: 11269 E1000_WRITE_REG(hw, FEXTNVM6, fextnvm6); 11270 } 11271 11272 return ret_val; 11273 11274 } 11275 11276 11277 /*************************************************************************** 11278 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware 11279 * @hw: pointer to the HW structure 11280 * @gate: boolean set to TRUE to gate, FALSE to ungate 11281 * 11282 * Gate/ungate the automatic PHY configuration via hardware; perform 11283 * the configuration via software instead. 11284 ***************************************************************************/ 11285 void 11286 em_gate_hw_phy_config_ich8lan(struct em_hw *hw, boolean_t gate) 11287 { 11288 uint32_t extcnf_ctrl; 11289 11290 DEBUGFUNC("em_gate_hw_phy_config_ich8lan"); 11291 11292 if (hw->mac_type != em_pch2lan) 11293 return; 11294 11295 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 11296 11297 if (gate) 11298 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG; 11299 else 11300 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG; 11301 11302 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); 11303 } 11304 11305 /*************************************************************************** 11306 * Configure K1 power state 11307 * 11308 * Configure the K1 power state based on the provided parameter. 11309 * Assumes semaphore already acquired. 11310 * 11311 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 11312 ***************************************************************************/ 11313 int32_t 11314 em_configure_k1_ich8lan(struct em_hw *hw, boolean_t k1_enable) 11315 { 11316 int32_t ret_val = E1000_SUCCESS; 11317 uint32_t ctrl_reg = 0; 11318 uint32_t ctrl_ext = 0; 11319 uint32_t reg = 0; 11320 uint16_t kmrn_reg = 0; 11321 11322 ret_val = em_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 11323 &kmrn_reg); 11324 if (ret_val) 11325 goto out; 11326 11327 if (k1_enable) 11328 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE; 11329 else 11330 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE; 11331 11332 ret_val = em_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 11333 kmrn_reg); 11334 if (ret_val) 11335 goto out; 11336 11337 usec_delay(20); 11338 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 11339 ctrl_reg = E1000_READ_REG(hw, CTRL); 11340 11341 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 11342 reg |= E1000_CTRL_FRCSPD; 11343 E1000_WRITE_REG(hw, CTRL, reg); 11344 11345 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS); 11346 usec_delay(20); 11347 E1000_WRITE_REG(hw, CTRL, ctrl_reg); 11348 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 11349 usec_delay(20); 11350 11351 out: 11352 return ret_val; 11353 } 11354 11355 /*************************************************************************** 11356 * em_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be 11357 * done after every PHY reset. 11358 ***************************************************************************/ 11359 int32_t 11360 em_lv_phy_workarounds_ich8lan(struct em_hw *hw) 11361 { 11362 int32_t ret_val = E1000_SUCCESS; 11363 uint16_t swfw; 11364 11365 DEBUGFUNC("e1000_lv_phy_workarounds_ich8lan"); 11366 11367 if (hw->mac_type != em_pch2lan) 11368 goto out; 11369 11370 /* Set MDIO slow mode before any other MDIO access */ 11371 ret_val = em_set_mdio_slow_mode_hv(hw); 11372 11373 swfw = E1000_SWFW_PHY0_SM; 11374 ret_val = em_swfw_sync_acquire(hw, swfw); 11375 if (ret_val) 11376 goto out; 11377 ret_val = em_write_phy_reg(hw, I82579_EMI_ADDR, 11378 I82579_MSE_THRESHOLD); 11379 if (ret_val) 11380 goto release; 11381 /* set MSE higher to enable link to stay up when noise is high */ 11382 ret_val = em_write_phy_reg(hw, I82579_EMI_DATA, 11383 0x0034); 11384 if (ret_val) 11385 goto release; 11386 ret_val = em_write_phy_reg(hw, I82579_EMI_ADDR, 11387 I82579_MSE_LINK_DOWN); 11388 if (ret_val) 11389 goto release; 11390 /* drop link after 5 times MSE threshold was reached */ 11391 ret_val = em_write_phy_reg(hw, I82579_EMI_DATA, 11392 0x0005); 11393 release: 11394 em_swfw_sync_release(hw, swfw); 11395 11396 out: 11397 return ret_val; 11398 } 11399 11400 int32_t 11401 em_set_eee_i350(struct em_hw *hw) 11402 { 11403 int32_t ret_val = E1000_SUCCESS; 11404 uint32_t ipcnfg, eeer; 11405 11406 if ((hw->mac_type < em_i350) || 11407 (hw->media_type != em_media_type_copper)) 11408 goto out; 11409 ipcnfg = EM_READ_REG(hw, E1000_IPCNFG); 11410 eeer = EM_READ_REG(hw, E1000_EEER); 11411 11412 if (hw->eee_enable) { 11413 ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN); 11414 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN | 11415 E1000_EEER_LPI_FC); 11416 } else { 11417 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN); 11418 eeer &= ~(E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN | 11419 E1000_EEER_LPI_FC); 11420 } 11421 EM_WRITE_REG(hw, E1000_IPCNFG, ipcnfg); 11422 EM_WRITE_REG(hw, E1000_EEER, eeer); 11423 EM_READ_REG(hw, E1000_IPCNFG); 11424 EM_READ_REG(hw, E1000_EEER); 11425 out: 11426 return ret_val; 11427 } 11428 11429 /*************************************************************************** 11430 * em_set_eee_pchlan - Enable/disable EEE support 11431 * @hw: pointer to the HW structure 11432 * 11433 * Enable/disable EEE based on setting in dev_spec structure. The bits in 11434 * the LPI Control register will remain set only if/when link is up. 11435 ***************************************************************************/ 11436 int32_t 11437 em_set_eee_pchlan(struct em_hw *hw) 11438 { 11439 int32_t ret_val = E1000_SUCCESS; 11440 uint16_t phy_reg; 11441 11442 DEBUGFUNC("em_set_eee_pchlan"); 11443 11444 if (hw->phy_type != em_phy_82579 && 11445 hw->phy_type != em_phy_i217) 11446 goto out; 11447 11448 ret_val = em_read_phy_reg(hw, I82579_LPI_CTRL, &phy_reg); 11449 if (ret_val) 11450 goto out; 11451 11452 if (hw->eee_enable) 11453 phy_reg &= ~I82579_LPI_CTRL_ENABLE_MASK; 11454 else 11455 phy_reg |= I82579_LPI_CTRL_ENABLE_MASK; 11456 11457 ret_val = em_write_phy_reg(hw, I82579_LPI_CTRL, phy_reg); 11458 out: 11459 return ret_val; 11460 } 11461 11462 /** 11463 * em_initialize_M88E1512_phy - Initialize M88E1512 PHY 11464 * @hw: pointer to the HW structure 11465 * 11466 * Initialize Marvell 1512 to work correctly with Avoton. 11467 **/ 11468 int32_t 11469 em_initialize_M88E1512_phy(struct em_hw *hw) 11470 { 11471 int32_t ret_val = E1000_SUCCESS; 11472 11473 DEBUGFUNC("e1000_initialize_M88E1512_phy"); 11474 11475 /* Check if this is correct PHY. */ 11476 if (hw->phy_id != M88E1512_E_PHY_ID) 11477 goto out; 11478 11479 /* Switch to PHY page 0xFF. */ 11480 ret_val = em_write_phy_reg(hw, M88E1543_PAGE_ADDR, 0x00FF); 11481 if (ret_val) 11482 goto out; 11483 11484 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_2, 0x214B); 11485 if (ret_val) 11486 goto out; 11487 11488 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_1, 0x2144); 11489 if (ret_val) 11490 goto out; 11491 11492 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_2, 0x0C28); 11493 if (ret_val) 11494 goto out; 11495 11496 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_1, 0x2146); 11497 if (ret_val) 11498 goto out; 11499 11500 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_2, 0xB233); 11501 if (ret_val) 11502 goto out; 11503 11504 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_1, 0x214D); 11505 if (ret_val) 11506 goto out; 11507 11508 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_2, 0xCC0C); 11509 if (ret_val) 11510 goto out; 11511 11512 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_1, 0x2159); 11513 if (ret_val) 11514 goto out; 11515 11516 /* Switch to PHY page 0xFB. */ 11517 ret_val = em_write_phy_reg(hw, M88E1543_PAGE_ADDR, 0x00FB); 11518 if (ret_val) 11519 goto out; 11520 11521 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_3, 0x000D); 11522 if (ret_val) 11523 goto out; 11524 11525 /* Switch to PHY page 0x12. */ 11526 ret_val = em_write_phy_reg(hw, M88E1543_PAGE_ADDR, 0x12); 11527 if (ret_val) 11528 goto out; 11529 11530 /* Change mode to SGMII-to-Copper */ 11531 ret_val = em_write_phy_reg(hw, M88E1512_MODE, 0x8001); 11532 if (ret_val) 11533 goto out; 11534 11535 /* Return the PHY to page 0. */ 11536 ret_val = em_write_phy_reg(hw, M88E1543_PAGE_ADDR, 0); 11537 if (ret_val) 11538 goto out; 11539 11540 ret_val = em_phy_hw_reset(hw); 11541 if (ret_val) { 11542 DEBUGOUT("Error committing the PHY changes\n"); 11543 return ret_val; 11544 } 11545 11546 msec_delay(1000); 11547 out: 11548 return ret_val; 11549 } 11550 11551 uint32_t 11552 em_translate_82542_register(uint32_t reg) 11553 { 11554 /* 11555 * Some of the 82542 registers are located at different 11556 * offsets than they are in newer adapters. 11557 * Despite the difference in location, the registers 11558 * function in the same manner. 11559 */ 11560 switch (reg) { 11561 case E1000_RA: 11562 reg = 0x00040; 11563 break; 11564 case E1000_RDTR: 11565 reg = 0x00108; 11566 break; 11567 case E1000_RDBAL(0): 11568 reg = 0x00110; 11569 break; 11570 case E1000_RDBAH(0): 11571 reg = 0x00114; 11572 break; 11573 case E1000_RDLEN(0): 11574 reg = 0x00118; 11575 break; 11576 case E1000_RDH(0): 11577 reg = 0x00120; 11578 break; 11579 case E1000_RDT(0): 11580 reg = 0x00128; 11581 break; 11582 case E1000_RDBAL(1): 11583 reg = 0x00138; 11584 break; 11585 case E1000_RDBAH(1): 11586 reg = 0x0013C; 11587 break; 11588 case E1000_RDLEN(1): 11589 reg = 0x00140; 11590 break; 11591 case E1000_RDH(1): 11592 reg = 0x00148; 11593 break; 11594 case E1000_RDT(1): 11595 reg = 0x00150; 11596 break; 11597 case E1000_FCRTH: 11598 reg = 0x00160; 11599 break; 11600 case E1000_FCRTL: 11601 reg = 0x00168; 11602 break; 11603 case E1000_MTA: 11604 reg = 0x00200; 11605 break; 11606 case E1000_TDBAL(0): 11607 reg = 0x00420; 11608 break; 11609 case E1000_TDBAH(0): 11610 reg = 0x00424; 11611 break; 11612 case E1000_TDLEN(0): 11613 reg = 0x00428; 11614 break; 11615 case E1000_TDH(0): 11616 reg = 0x00430; 11617 break; 11618 case E1000_TDT(0): 11619 reg = 0x00438; 11620 break; 11621 case E1000_TIDV: 11622 reg = 0x00440; 11623 break; 11624 case E1000_VFTA: 11625 reg = 0x00600; 11626 break; 11627 case E1000_TDFH: 11628 reg = 0x08010; 11629 break; 11630 case E1000_TDFT: 11631 reg = 0x08018; 11632 break; 11633 default: 11634 break; 11635 } 11636 11637 return (reg); 11638 } 11639