1 /******************************************************************************* 2 3 Copyright (c) 2001-2003, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 *******************************************************************************/ 33 34 /*$FreeBSD: if_em_hw.c,v 1.9 2003/06/05 17:51:38 pdeuskar Exp $*/ 35 /* $OpenBSD: if_em_hw.c,v 1.2 2003/06/13 19:21:21 henric Exp $ */ 36 /* if_em_hw.c 37 * Shared functions for accessing and configuring the MAC 38 */ 39 40 #include "bpfilter.h" 41 #include "vlan.h" 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/sockio.h> 46 #include <sys/mbuf.h> 47 #include <sys/malloc.h> 48 #include <sys/kernel.h> 49 #include <sys/device.h> 50 #include <sys/socket.h> 51 52 #include <net/if.h> 53 #include <net/if_dl.h> 54 #include <net/if_media.h> 55 56 #ifdef INET 57 #include <netinet/in.h> 58 #include <netinet/in_systm.h> 59 #include <netinet/in_var.h> 60 #include <netinet/ip.h> 61 #include <netinet/if_ether.h> 62 #endif 63 64 #if NVLAN > 0 65 #include <net/if_types.h> 66 #include <net/if_vlan_var.h> 67 #endif 68 69 #if NBPFILTER > 0 70 #include <net/bpf.h> 71 #endif 72 73 #include <uvm/uvm_extern.h> 74 75 #include <dev/pci/pcireg.h> 76 #include <dev/pci/pcivar.h> 77 #include <dev/pci/pcidevs.h> 78 79 #include <dev/pci/if_em_hw.h> 80 81 static int32_t em_set_phy_type(struct em_hw *hw); 82 static void em_phy_init_script(struct em_hw *hw); 83 static int32_t em_setup_fiber_link(struct em_hw *hw); 84 static int32_t em_setup_copper_link(struct em_hw *hw); 85 static int32_t em_phy_force_speed_duplex(struct em_hw *hw); 86 static int32_t em_config_mac_to_phy(struct em_hw *hw); 87 static int32_t em_force_mac_fc(struct em_hw *hw); 88 static void em_raise_mdi_clk(struct em_hw *hw, uint32_t *ctrl); 89 static void em_lower_mdi_clk(struct em_hw *hw, uint32_t *ctrl); 90 static void em_shift_out_mdi_bits(struct em_hw *hw, uint32_t data, uint16_t count); 91 static uint16_t em_shift_in_mdi_bits(struct em_hw *hw); 92 static int32_t em_phy_reset_dsp(struct em_hw *hw); 93 static int32_t em_write_eeprom_spi(struct em_hw *hw, uint16_t offset, 94 uint16_t words, uint16_t *data); 95 static int32_t em_write_eeprom_microwire(struct em_hw *hw, 96 uint16_t offset, uint16_t words, 97 uint16_t *data); 98 static int32_t em_spi_eeprom_ready(struct em_hw *hw); 99 static void em_raise_ee_clk(struct em_hw *hw, uint32_t *eecd); 100 static void em_lower_ee_clk(struct em_hw *hw, uint32_t *eecd); 101 static void em_shift_out_ee_bits(struct em_hw *hw, uint16_t data, uint16_t count); 102 static uint16_t em_shift_in_ee_bits(struct em_hw *hw, uint16_t count); 103 static int32_t em_acquire_eeprom(struct em_hw *hw); 104 static void em_release_eeprom(struct em_hw *hw); 105 static void em_standby_eeprom(struct em_hw *hw); 106 static int32_t em_id_led_init(struct em_hw * hw); 107 108 109 110 /****************************************************************************** 111 * Set the phy type member in the hw struct. 112 * 113 * hw - Struct containing variables accessed by shared code 114 *****************************************************************************/ 115 int32_t 116 em_set_phy_type(struct em_hw *hw) 117 { 118 DEBUGFUNC("em_set_phy_type"); 119 120 switch(hw->phy_id) { 121 case M88E1000_E_PHY_ID: 122 case M88E1000_I_PHY_ID: 123 case M88E1011_I_PHY_ID: 124 hw->phy_type = em_phy_m88; 125 break; 126 case IGP01E1000_I_PHY_ID: 127 hw->phy_type = em_phy_igp; 128 break; 129 default: 130 /* Should never have loaded on this device */ 131 hw->phy_type = em_phy_undefined; 132 return -E1000_ERR_PHY_TYPE; 133 } 134 135 return E1000_SUCCESS; 136 } 137 138 /****************************************************************************** 139 * IGP phy init script - initializes the GbE PHY 140 * 141 * hw - Struct containing variables accessed by shared code 142 *****************************************************************************/ 143 static void 144 em_phy_init_script(struct em_hw *hw) 145 { 146 DEBUGFUNC("em_phy_init_script"); 147 148 if(hw->phy_init_script) { 149 msec_delay(10); 150 151 em_write_phy_reg(hw,IGP01E1000_PHY_PAGE_SELECT,0x0000); 152 em_write_phy_reg(hw,0x0000,0x0140); 153 154 msec_delay(5); 155 em_write_phy_reg(hw,IGP01E1000_PHY_PAGE_SELECT,0x1F95); 156 em_write_phy_reg(hw,0x0015,0x0001); 157 158 em_write_phy_reg(hw,IGP01E1000_PHY_PAGE_SELECT,0x1F71); 159 em_write_phy_reg(hw,0x0011,0xBD21); 160 161 em_write_phy_reg(hw,IGP01E1000_PHY_PAGE_SELECT,0x1F79); 162 em_write_phy_reg(hw,0x0019,0x0018); 163 164 em_write_phy_reg(hw,IGP01E1000_PHY_PAGE_SELECT,0x1F30); 165 em_write_phy_reg(hw,0x0010,0x1600); 166 167 em_write_phy_reg(hw,IGP01E1000_PHY_PAGE_SELECT,0x1F31); 168 em_write_phy_reg(hw,0x0011,0x0014); 169 170 em_write_phy_reg(hw,IGP01E1000_PHY_PAGE_SELECT,0x1F32); 171 em_write_phy_reg(hw,0x0012,0x161C); 172 173 em_write_phy_reg(hw,IGP01E1000_PHY_PAGE_SELECT,0x1F94); 174 em_write_phy_reg(hw,0x0014,0x0003); 175 176 em_write_phy_reg(hw,IGP01E1000_PHY_PAGE_SELECT,0x1F96); 177 em_write_phy_reg(hw,0x0016,0x003F); 178 179 em_write_phy_reg(hw,IGP01E1000_PHY_PAGE_SELECT,0x2010); 180 em_write_phy_reg(hw,0x0010,0x0008); 181 182 em_write_phy_reg(hw,IGP01E1000_PHY_PAGE_SELECT,0x0000); 183 em_write_phy_reg(hw,0x0000,0x3300); 184 } 185 } 186 187 /****************************************************************************** 188 * Set the mac type member in the hw struct. 189 * 190 * hw - Struct containing variables accessed by shared code 191 *****************************************************************************/ 192 int32_t 193 em_set_mac_type(struct em_hw *hw) 194 { 195 DEBUGFUNC("em_set_mac_type"); 196 197 switch (hw->device_id) { 198 case E1000_DEV_ID_82542: 199 switch (hw->revision_id) { 200 case E1000_82542_2_0_REV_ID: 201 hw->mac_type = em_82542_rev2_0; 202 break; 203 case E1000_82542_2_1_REV_ID: 204 hw->mac_type = em_82542_rev2_1; 205 break; 206 default: 207 /* Invalid 82542 revision ID */ 208 return -E1000_ERR_MAC_TYPE; 209 } 210 break; 211 case E1000_DEV_ID_82543GC_FIBER: 212 case E1000_DEV_ID_82543GC_COPPER: 213 hw->mac_type = em_82543; 214 break; 215 case E1000_DEV_ID_82544EI_COPPER: 216 case E1000_DEV_ID_82544EI_FIBER: 217 case E1000_DEV_ID_82544GC_COPPER: 218 case E1000_DEV_ID_82544GC_LOM: 219 hw->mac_type = em_82544; 220 break; 221 case E1000_DEV_ID_82540EM: 222 case E1000_DEV_ID_82540EM_LOM: 223 case E1000_DEV_ID_82540EP: 224 case E1000_DEV_ID_82540EP_LOM: 225 case E1000_DEV_ID_82540EP_LP: 226 hw->mac_type = em_82540; 227 break; 228 case E1000_DEV_ID_82545EM_COPPER: 229 case E1000_DEV_ID_82545EM_FIBER: 230 hw->mac_type = em_82545; 231 break; 232 case E1000_DEV_ID_82546EB_COPPER: 233 case E1000_DEV_ID_82546EB_FIBER: 234 case E1000_DEV_ID_82546EB_QUAD_COPPER: 235 hw->mac_type = em_82546; 236 break; 237 case E1000_DEV_ID_82541EI: 238 case E1000_DEV_ID_82541EP: 239 hw->mac_type = em_82541; 240 break; 241 case E1000_DEV_ID_82547EI: 242 hw->mac_type = em_82547; 243 break; 244 default: 245 /* Should never have loaded on this device */ 246 return -E1000_ERR_MAC_TYPE; 247 } 248 249 250 return E1000_SUCCESS; 251 } 252 /****************************************************************************** 253 * Reset the transmit and receive units; mask and clear all interrupts. 254 * 255 * hw - Struct containing variables accessed by shared code 256 *****************************************************************************/ 257 void 258 em_reset_hw(struct em_hw *hw) 259 { 260 uint32_t ctrl; 261 uint32_t ctrl_ext; 262 uint32_t icr; 263 uint32_t manc; 264 uint32_t led_ctrl; 265 266 DEBUGFUNC("em_reset_hw"); 267 268 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ 269 if(hw->mac_type == em_82542_rev2_0) { 270 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 271 em_pci_clear_mwi(hw); 272 } 273 274 /* Clear interrupt mask to stop board from generating interrupts */ 275 DEBUGOUT("Masking off all interrupts\n"); 276 E1000_WRITE_REG(hw, IMC, 0xffffffff); 277 278 /* Disable the Transmit and Receive units. Then delay to allow 279 * any pending transactions to complete before we hit the MAC with 280 * the global reset. 281 */ 282 E1000_WRITE_REG(hw, RCTL, 0); 283 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP); 284 E1000_WRITE_FLUSH(hw); 285 286 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */ 287 hw->tbi_compatibility_on = FALSE; 288 289 /* Delay to allow any outstanding PCI transactions to complete before 290 * resetting the device 291 */ 292 msec_delay(10); 293 294 /* Issue a global reset to the MAC. This will reset the chip's 295 * transmit, receive, DMA, and link units. It will not effect 296 * the current PCI configuration. The global reset bit is self- 297 * clearing, and should clear within a microsecond. 298 */ 299 DEBUGOUT("Issuing a global reset to MAC\n"); 300 ctrl = E1000_READ_REG(hw, CTRL); 301 302 /* Must reset the PHY before resetting the MAC */ 303 if((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) { 304 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST)); 305 msec_delay(5); 306 } 307 308 switch(hw->mac_type) { 309 case em_82544: 310 case em_82540: 311 case em_82545: 312 case em_82546: 313 case em_82541: 314 /* These controllers can't ack the 64-bit write when issuing the 315 * reset, so use IO-mapping as a workaround to issue the reset */ 316 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST)); 317 break; 318 default: 319 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); 320 break; 321 } 322 323 /* Force a reload from the EEPROM if necessary */ 324 if(hw->mac_type < em_82540) { 325 /* Wait for reset to complete */ 326 usec_delay(10); 327 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 328 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 329 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 330 E1000_WRITE_FLUSH(hw); 331 /* Wait for EEPROM reload */ 332 msec_delay(2); 333 } else { 334 /* Wait for EEPROM reload (it happens automatically) */ 335 msec_delay(5); 336 /* Dissable HW ARPs on ASF enabled adapters */ 337 manc = E1000_READ_REG(hw, MANC); 338 manc &= ~(E1000_MANC_ARP_EN); 339 E1000_WRITE_REG(hw, MANC, manc); 340 } 341 342 if((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) { 343 em_phy_init_script(hw); 344 345 /* Configure activity LED after PHY reset */ 346 led_ctrl = E1000_READ_REG(hw, LEDCTL); 347 led_ctrl &= IGP_ACTIVITY_LED_MASK; 348 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 349 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 350 } 351 352 /* Clear interrupt mask to stop board from generating interrupts */ 353 DEBUGOUT("Masking off all interrupts\n"); 354 E1000_WRITE_REG(hw, IMC, 0xffffffff); 355 356 /* Clear any pending interrupt events. */ 357 icr = E1000_READ_REG(hw, ICR); 358 359 /* If MWI was previously enabled, reenable it. */ 360 if(hw->mac_type == em_82542_rev2_0) { 361 if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 362 em_pci_set_mwi(hw); 363 } 364 } 365 366 /****************************************************************************** 367 * Performs basic configuration of the adapter. 368 * 369 * hw - Struct containing variables accessed by shared code 370 * 371 * Assumes that the controller has previously been reset and is in a 372 * post-reset uninitialized state. Initializes the receive address registers, 373 * multicast table, and VLAN filter table. Calls routines to setup link 374 * configuration and flow control settings. Clears all on-chip counters. Leaves 375 * the transmit and receive units disabled and uninitialized. 376 *****************************************************************************/ 377 int32_t 378 em_init_hw(struct em_hw *hw) 379 { 380 uint32_t ctrl, status; 381 uint32_t i; 382 int32_t ret_val; 383 uint16_t pcix_cmd_word; 384 uint16_t pcix_stat_hi_word; 385 uint16_t cmd_mmrbc; 386 uint16_t stat_mmrbc; 387 388 DEBUGFUNC("em_init_hw"); 389 390 /* Initialize Identification LED */ 391 ret_val = em_id_led_init(hw); 392 if(ret_val < 0) { 393 DEBUGOUT("Error Initializing Identification LED\n"); 394 return ret_val; 395 } 396 397 /* Set the Media Type and exit with error if it is not valid. */ 398 if(hw->mac_type != em_82543) { 399 /* tbi_compatibility is only valid on 82543 */ 400 hw->tbi_compatibility_en = FALSE; 401 } 402 403 if(hw->mac_type >= em_82543) { 404 status = E1000_READ_REG(hw, STATUS); 405 if(status & E1000_STATUS_TBIMODE) { 406 hw->media_type = em_media_type_fiber; 407 /* tbi_compatibility not valid on fiber */ 408 hw->tbi_compatibility_en = FALSE; 409 } else { 410 hw->media_type = em_media_type_copper; 411 } 412 } else { 413 /* This is an 82542 (fiber only) */ 414 hw->media_type = em_media_type_fiber; 415 } 416 417 /* Disabling VLAN filtering. */ 418 DEBUGOUT("Initializing the IEEE VLAN\n"); 419 E1000_WRITE_REG(hw, VET, 0); 420 421 em_clear_vfta(hw); 422 423 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ 424 if(hw->mac_type == em_82542_rev2_0) { 425 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 426 em_pci_clear_mwi(hw); 427 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST); 428 E1000_WRITE_FLUSH(hw); 429 msec_delay(5); 430 } 431 432 /* Setup the receive address. This involves initializing all of the Receive 433 * Address Registers (RARs 0 - 15). 434 */ 435 em_init_rx_addrs(hw); 436 437 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */ 438 if(hw->mac_type == em_82542_rev2_0) { 439 E1000_WRITE_REG(hw, RCTL, 0); 440 E1000_WRITE_FLUSH(hw); 441 msec_delay(1); 442 if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 443 em_pci_set_mwi(hw); 444 } 445 446 /* Zero out the Multicast HASH table */ 447 DEBUGOUT("Zeroing the MTA\n"); 448 for(i = 0; i < E1000_MC_TBL_SIZE; i++) 449 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 450 451 /* Set the PCI priority bit correctly in the CTRL register. This 452 * determines if the adapter gives priority to receives, or if it 453 * gives equal priority to transmits and receives. 454 */ 455 if(hw->dma_fairness) { 456 ctrl = E1000_READ_REG(hw, CTRL); 457 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR); 458 } 459 460 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */ 461 if(hw->bus_type == em_bus_type_pcix) { 462 em_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word); 463 em_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word); 464 cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >> 465 PCIX_COMMAND_MMRBC_SHIFT; 466 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> 467 PCIX_STATUS_HI_MMRBC_SHIFT; 468 if(stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) 469 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; 470 if(cmd_mmrbc > stat_mmrbc) { 471 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK; 472 pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; 473 em_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word); 474 } 475 } 476 477 /* Call a subroutine to configure the link and setup flow control. */ 478 ret_val = em_setup_link(hw); 479 480 /* Set the transmit descriptor write-back policy */ 481 if(hw->mac_type > em_82544) { 482 ctrl = E1000_READ_REG(hw, TXDCTL); 483 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB; 484 E1000_WRITE_REG(hw, TXDCTL, ctrl); 485 } 486 487 /* Clear all of the statistics registers (clear on read). It is 488 * important that we do this after we have tried to establish link 489 * because the symbol error count will increment wildly if there 490 * is no link. 491 */ 492 em_clear_hw_cntrs(hw); 493 494 return ret_val; 495 } 496 497 /****************************************************************************** 498 * Configures flow control and link settings. 499 * 500 * hw - Struct containing variables accessed by shared code 501 * 502 * Determines which flow control settings to use. Calls the apropriate media- 503 * specific link configuration function. Configures the flow control settings. 504 * Assuming the adapter has a valid link partner, a valid link should be 505 * established. Assumes the hardware has previously been reset and the 506 * transmitter and receiver are not enabled. 507 *****************************************************************************/ 508 int32_t 509 em_setup_link(struct em_hw *hw) 510 { 511 uint32_t ctrl_ext; 512 int32_t ret_val; 513 uint16_t eeprom_data; 514 515 DEBUGFUNC("em_setup_link"); 516 517 /* Read and store word 0x0F of the EEPROM. This word contains bits 518 * that determine the hardware's default PAUSE (flow control) mode, 519 * a bit that determines whether the HW defaults to enabling or 520 * disabling auto-negotiation, and the direction of the 521 * SW defined pins. If there is no SW over-ride of the flow 522 * control setting, then the variable hw->fc will 523 * be initialized based on a value in the EEPROM. 524 */ 525 if(em_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data) < 0) { 526 DEBUGOUT("EEPROM Read Error\n"); 527 return -E1000_ERR_EEPROM; 528 } 529 530 if(hw->fc == em_fc_default) { 531 if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0) 532 hw->fc = em_fc_none; 533 else if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 534 EEPROM_WORD0F_ASM_DIR) 535 hw->fc = em_fc_tx_pause; 536 else 537 hw->fc = em_fc_full; 538 } 539 540 /* We want to save off the original Flow Control configuration just 541 * in case we get disconnected and then reconnected into a different 542 * hub or switch with different Flow Control capabilities. 543 */ 544 if(hw->mac_type == em_82542_rev2_0) 545 hw->fc &= (~em_fc_tx_pause); 546 547 if((hw->mac_type < em_82543) && (hw->report_tx_early == 1)) 548 hw->fc &= (~em_fc_rx_pause); 549 550 hw->original_fc = hw->fc; 551 552 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc); 553 554 /* Take the 4 bits from EEPROM word 0x0F that determine the initial 555 * polarity value for the SW controlled pins, and setup the 556 * Extended Device Control reg with that info. 557 * This is needed because one of the SW controlled pins is used for 558 * signal detection. So this should be done before em_setup_pcs_link() 559 * or em_phy_setup() is called. 560 */ 561 if(hw->mac_type == em_82543) { 562 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << 563 SWDPIO__EXT_SHIFT); 564 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 565 } 566 567 /* Call the necessary subroutine to configure the link. */ 568 ret_val = (hw->media_type == em_media_type_fiber) ? 569 em_setup_fiber_link(hw) : 570 em_setup_copper_link(hw); 571 572 /* Initialize the flow control address, type, and PAUSE timer 573 * registers to their default values. This is done even if flow 574 * control is disabled, because it does not hurt anything to 575 * initialize these registers. 576 */ 577 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"); 578 579 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW); 580 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH); 581 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE); 582 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time); 583 584 /* Set the flow control receive threshold registers. Normally, 585 * these registers will be set to a default threshold that may be 586 * adjusted later by the driver's runtime code. However, if the 587 * ability to transmit pause frames in not enabled, then these 588 * registers will be set to 0. 589 */ 590 if(!(hw->fc & em_fc_tx_pause)) { 591 E1000_WRITE_REG(hw, FCRTL, 0); 592 E1000_WRITE_REG(hw, FCRTH, 0); 593 } else { 594 /* We need to set up the Receive Threshold high and low water marks 595 * as well as (optionally) enabling the transmission of XON frames. 596 */ 597 if(hw->fc_send_xon) { 598 E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE)); 599 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); 600 } else { 601 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water); 602 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); 603 } 604 } 605 return ret_val; 606 } 607 608 /****************************************************************************** 609 * Sets up link for a fiber based adapter 610 * 611 * hw - Struct containing variables accessed by shared code 612 * 613 * Manipulates Physical Coding Sublayer functions in order to configure 614 * link. Assumes the hardware has been previously reset and the transmitter 615 * and receiver are not enabled. 616 *****************************************************************************/ 617 static int32_t 618 em_setup_fiber_link(struct em_hw *hw) 619 { 620 uint32_t ctrl; 621 uint32_t status; 622 uint32_t txcw = 0; 623 uint32_t i; 624 uint32_t signal; 625 int32_t ret_val; 626 627 DEBUGFUNC("em_setup_fiber_link"); 628 629 /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be 630 * set when the optics detect a signal. On older adapters, it will be 631 * cleared when there is a signal 632 */ 633 ctrl = E1000_READ_REG(hw, CTRL); 634 if(hw->mac_type > em_82544) signal = E1000_CTRL_SWDPIN1; 635 else signal = 0; 636 637 /* Take the link out of reset */ 638 ctrl &= ~(E1000_CTRL_LRST); 639 640 em_config_collision_dist(hw); 641 642 /* Check for a software override of the flow control settings, and setup 643 * the device accordingly. If auto-negotiation is enabled, then software 644 * will have to set the "PAUSE" bits to the correct value in the Tranmsit 645 * Config Word Register (TXCW) and re-start auto-negotiation. However, if 646 * auto-negotiation is disabled, then software will have to manually 647 * configure the two flow control enable bits in the CTRL register. 648 * 649 * The possible values of the "fc" parameter are: 650 * 0: Flow control is completely disabled 651 * 1: Rx flow control is enabled (we can receive pause frames, but 652 * not send pause frames). 653 * 2: Tx flow control is enabled (we can send pause frames but we do 654 * not support receiving pause frames). 655 * 3: Both Rx and TX flow control (symmetric) are enabled. 656 */ 657 switch (hw->fc) { 658 case em_fc_none: 659 /* Flow control is completely disabled by a software over-ride. */ 660 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 661 break; 662 case em_fc_rx_pause: 663 /* RX Flow control is enabled and TX Flow control is disabled by a 664 * software over-ride. Since there really isn't a way to advertise 665 * that we are capable of RX Pause ONLY, we will advertise that we 666 * support both symmetric and asymmetric RX PAUSE. Later, we will 667 * disable the adapter's ability to send PAUSE frames. 668 */ 669 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 670 break; 671 case em_fc_tx_pause: 672 /* TX Flow control is enabled, and RX Flow control is disabled, by a 673 * software over-ride. 674 */ 675 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 676 break; 677 case em_fc_full: 678 /* Flow control (both RX and TX) is enabled by a software over-ride. */ 679 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 680 break; 681 default: 682 DEBUGOUT("Flow control param set incorrectly\n"); 683 return -E1000_ERR_CONFIG; 684 break; 685 } 686 687 /* Since auto-negotiation is enabled, take the link out of reset (the link 688 * will be in reset, because we previously reset the chip). This will 689 * restart auto-negotiation. If auto-neogtiation is successful then the 690 * link-up status bit will be set and the flow control enable bits (RFCE 691 * and TFCE) will be set according to their negotiated value. 692 */ 693 DEBUGOUT("Auto-negotiation enabled\n"); 694 695 E1000_WRITE_REG(hw, TXCW, txcw); 696 E1000_WRITE_REG(hw, CTRL, ctrl); 697 E1000_WRITE_FLUSH(hw); 698 699 hw->txcw = txcw; 700 msec_delay(1); 701 702 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up" 703 * indication in the Device Status Register. Time-out if a link isn't 704 * seen in 500 milliseconds seconds (Auto-negotiation should complete in 705 * less than 500 milliseconds even if the other end is doing it in SW). 706 */ 707 if((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) { 708 DEBUGOUT("Looking for Link\n"); 709 for(i = 0; i < (LINK_UP_TIMEOUT / 10); i++) { 710 msec_delay(10); 711 status = E1000_READ_REG(hw, STATUS); 712 if(status & E1000_STATUS_LU) break; 713 } 714 if(i == (LINK_UP_TIMEOUT / 10)) { 715 /* AutoNeg failed to achieve a link, so we'll call 716 * em_check_for_link. This routine will force the link up if we 717 * detect a signal. This will allow us to communicate with 718 * non-autonegotiating link partners. 719 */ 720 DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 721 hw->autoneg_failed = 1; 722 ret_val = em_check_for_link(hw); 723 if(ret_val < 0) { 724 DEBUGOUT("Error while checking for link\n"); 725 return ret_val; 726 } 727 hw->autoneg_failed = 0; 728 } else { 729 hw->autoneg_failed = 0; 730 DEBUGOUT("Valid Link Found\n"); 731 } 732 } else { 733 DEBUGOUT("No Signal Detected\n"); 734 } 735 return 0; 736 } 737 738 /****************************************************************************** 739 * Detects which PHY is present and the speed and duplex 740 * 741 * hw - Struct containing variables accessed by shared code 742 ******************************************************************************/ 743 static int32_t 744 em_setup_copper_link(struct em_hw *hw) 745 { 746 uint32_t ctrl; 747 uint32_t led_ctrl; 748 int32_t ret_val; 749 uint16_t i; 750 uint16_t phy_data; 751 752 DEBUGFUNC("em_setup_copper_link"); 753 754 ctrl = E1000_READ_REG(hw, CTRL); 755 /* With 82543, we need to force speed and duplex on the MAC equal to what 756 * the PHY speed and duplex configuration is. In addition, we need to 757 * perform a hardware reset on the PHY to take it out of reset. 758 */ 759 if(hw->mac_type > em_82543) { 760 ctrl |= E1000_CTRL_SLU; 761 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 762 E1000_WRITE_REG(hw, CTRL, ctrl); 763 } else { 764 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU); 765 E1000_WRITE_REG(hw, CTRL, ctrl); 766 em_phy_hw_reset(hw); 767 } 768 769 /* Make sure we have a valid PHY */ 770 ret_val = em_detect_gig_phy(hw); 771 if(ret_val < 0) { 772 DEBUGOUT("Error, did not detect valid phy.\n"); 773 return ret_val; 774 } 775 DEBUGOUT1("Phy ID = %x \n", hw->phy_id); 776 777 if (hw->phy_type == em_phy_igp) { 778 779 ret_val = em_phy_reset(hw); 780 if(ret_val < 0) { 781 DEBUGOUT("Error Resetting the PHY\n"); 782 return ret_val; 783 } 784 785 /* Wait 10ms for MAC to configure PHY from eeprom settings */ 786 msec_delay(15); 787 788 if(em_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT, 0x0000) < 0) { 789 DEBUGOUT("PHY Write Error\n"); 790 return -E1000_ERR_PHY; 791 } 792 793 /* Configure activity LED after PHY reset */ 794 led_ctrl = E1000_READ_REG(hw, LEDCTL); 795 led_ctrl &= IGP_ACTIVITY_LED_MASK; 796 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 797 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 798 799 if(hw->autoneg_advertised == ADVERTISE_1000_FULL) { 800 /* Disable SmartSpeed */ 801 if(em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 802 &phy_data) < 0) { 803 DEBUGOUT("PHY Read Error\n"); 804 return -E1000_ERR_PHY; 805 } 806 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 807 if(em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 808 phy_data) < 0) { 809 DEBUGOUT("PHY Write Error\n"); 810 return -E1000_ERR_PHY; 811 } 812 /* Set auto Master/Slave resolution process */ 813 if(em_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data) < 0) { 814 DEBUGOUT("PHY Read Error\n"); 815 return -E1000_ERR_PHY; 816 } 817 phy_data &= ~CR_1000T_MS_ENABLE; 818 if(em_write_phy_reg(hw, PHY_1000T_CTRL, phy_data) < 0) { 819 DEBUGOUT("PHY Write Error\n"); 820 return -E1000_ERR_PHY; 821 } 822 } 823 824 if(em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data) < 0) { 825 DEBUGOUT("PHY Read Error\n"); 826 return -E1000_ERR_PHY; 827 } 828 829 /* Force MDI for IGP PHY */ 830 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | 831 IGP01E1000_PSCR_FORCE_MDI_MDIX); 832 833 hw->mdix = 1; 834 835 if(em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data) < 0) { 836 DEBUGOUT("PHY Write Error\n"); 837 return -E1000_ERR_PHY; 838 } 839 840 } else { 841 /* Enable CRS on TX. This must be set for half-duplex operation. */ 842 if(em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data) < 0) { 843 DEBUGOUT("PHY Read Error\n"); 844 return -E1000_ERR_PHY; 845 } 846 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 847 848 /* Options: 849 * MDI/MDI-X = 0 (default) 850 * 0 - Auto for all speeds 851 * 1 - MDI mode 852 * 2 - MDI-X mode 853 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 854 */ 855 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 856 857 switch (hw->mdix) { 858 case 1: 859 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 860 break; 861 case 2: 862 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 863 break; 864 case 3: 865 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 866 break; 867 case 0: 868 default: 869 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 870 break; 871 } 872 873 /* Options: 874 * disable_polarity_correction = 0 (default) 875 * Automatic Correction for Reversed Cable Polarity 876 * 0 - Disabled 877 * 1 - Enabled 878 */ 879 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 880 if(hw->disable_polarity_correction == 1) 881 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 882 if(em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data) < 0) { 883 DEBUGOUT("PHY Write Error\n"); 884 return -E1000_ERR_PHY; 885 } 886 887 /* Force TX_CLK in the Extended PHY Specific Control Register 888 * to 25MHz clock. 889 */ 890 if(em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data) < 0) { 891 DEBUGOUT("PHY Read Error\n"); 892 return -E1000_ERR_PHY; 893 } 894 phy_data |= M88E1000_EPSCR_TX_CLK_25; 895 896 if (hw->phy_revision < M88E1011_I_REV_4) { 897 /* Configure Master and Slave downshift values */ 898 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 899 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 900 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 901 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 902 if(em_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 903 phy_data) < 0) { 904 DEBUGOUT("PHY Write Error\n"); 905 return -E1000_ERR_PHY; 906 } 907 } 908 909 /* SW Reset the PHY so all changes take effect */ 910 ret_val = em_phy_reset(hw); 911 if(ret_val < 0) { 912 DEBUGOUT("Error Resetting the PHY\n"); 913 return ret_val; 914 } 915 } 916 917 /* Options: 918 * autoneg = 1 (default) 919 * PHY will advertise value(s) parsed from 920 * autoneg_advertised and fc 921 * autoneg = 0 922 * PHY will be set to 10H, 10F, 100H, or 100F 923 * depending on value parsed from forced_speed_duplex. 924 */ 925 926 /* Is autoneg enabled? This is enabled by default or by software override. 927 * If so, call em_phy_setup_autoneg routine to parse the 928 * autoneg_advertised and fc options. If autoneg is NOT enabled, then the 929 * user should have provided a speed/duplex override. If so, then call 930 * em_phy_force_speed_duplex to parse and set this up. 931 */ 932 if(hw->autoneg) { 933 /* Perform some bounds checking on the hw->autoneg_advertised 934 * parameter. If this variable is zero, then set it to the default. 935 */ 936 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT; 937 938 /* If autoneg_advertised is zero, we assume it was not defaulted 939 * by the calling code so we set to advertise full capability. 940 */ 941 if(hw->autoneg_advertised == 0) 942 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 943 944 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); 945 ret_val = em_phy_setup_autoneg(hw); 946 if(ret_val < 0) { 947 DEBUGOUT("Error Setting up Auto-Negotiation\n"); 948 return ret_val; 949 } 950 DEBUGOUT("Restarting Auto-Neg\n"); 951 952 /* Restart auto-negotiation by setting the Auto Neg Enable bit and 953 * the Auto Neg Restart bit in the PHY control register. 954 */ 955 if(em_read_phy_reg(hw, PHY_CTRL, &phy_data) < 0) { 956 DEBUGOUT("PHY Read Error\n"); 957 return -E1000_ERR_PHY; 958 } 959 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 960 if(em_write_phy_reg(hw, PHY_CTRL, phy_data) < 0) { 961 DEBUGOUT("PHY Write Error\n"); 962 return -E1000_ERR_PHY; 963 } 964 965 /* Does the user want to wait for Auto-Neg to complete here, or 966 * check at a later time (for example, callback routine). 967 */ 968 if(hw->wait_autoneg_complete) { 969 ret_val = em_wait_autoneg(hw); 970 if(ret_val < 0) { 971 DEBUGOUT("Error while waiting for autoneg to complete\n"); 972 return ret_val; 973 } 974 } 975 hw->get_link_status = TRUE; 976 } else { 977 DEBUGOUT("Forcing speed and duplex\n"); 978 ret_val = em_phy_force_speed_duplex(hw); 979 if(ret_val < 0) { 980 DEBUGOUT("Error Forcing Speed and Duplex\n"); 981 return ret_val; 982 } 983 } 984 985 /* Check link status. Wait up to 100 microseconds for link to become 986 * valid. 987 */ 988 for(i = 0; i < 10; i++) { 989 if(em_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 990 DEBUGOUT("PHY Read Error\n"); 991 return -E1000_ERR_PHY; 992 } 993 if(em_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 994 DEBUGOUT("PHY Read Error\n"); 995 return -E1000_ERR_PHY; 996 } 997 if(phy_data & MII_SR_LINK_STATUS) { 998 /* We have link, so we need to finish the config process: 999 * 1) Set up the MAC to the current PHY speed/duplex 1000 * if we are on 82543. If we 1001 * are on newer silicon, we only need to configure 1002 * collision distance in the Transmit Control Register. 1003 * 2) Set up flow control on the MAC to that established with 1004 * the link partner. 1005 */ 1006 if(hw->mac_type >= em_82544) { 1007 em_config_collision_dist(hw); 1008 } else { 1009 ret_val = em_config_mac_to_phy(hw); 1010 if(ret_val < 0) { 1011 DEBUGOUT("Error configuring MAC to PHY settings\n"); 1012 return ret_val; 1013 } 1014 } 1015 ret_val = em_config_fc_after_link_up(hw); 1016 if(ret_val < 0) { 1017 DEBUGOUT("Error Configuring Flow Control\n"); 1018 return ret_val; 1019 } 1020 DEBUGOUT("Valid link established!!!\n"); 1021 return 0; 1022 } 1023 usec_delay(10); 1024 } 1025 1026 DEBUGOUT("Unable to establish link!!!\n"); 1027 return 0; 1028 } 1029 1030 /****************************************************************************** 1031 * Configures PHY autoneg and flow control advertisement settings 1032 * 1033 * hw - Struct containing variables accessed by shared code 1034 ******************************************************************************/ 1035 int32_t 1036 em_phy_setup_autoneg(struct em_hw *hw) 1037 { 1038 uint16_t mii_autoneg_adv_reg; 1039 uint16_t mii_1000t_ctrl_reg; 1040 1041 DEBUGFUNC("em_phy_setup_autoneg"); 1042 1043 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 1044 if(em_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg) < 0) { 1045 DEBUGOUT("PHY Read Error\n"); 1046 return -E1000_ERR_PHY; 1047 } 1048 1049 /* Read the MII 1000Base-T Control Register (Address 9). */ 1050 if(em_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg) < 0) { 1051 DEBUGOUT("PHY Read Error\n"); 1052 return -E1000_ERR_PHY; 1053 } 1054 1055 /* Need to parse both autoneg_advertised and fc and set up 1056 * the appropriate PHY registers. First we will parse for 1057 * autoneg_advertised software override. Since we can advertise 1058 * a plethora of combinations, we need to check each bit 1059 * individually. 1060 */ 1061 1062 /* First we clear all the 10/100 mb speed bits in the Auto-Neg 1063 * Advertisement Register (Address 4) and the 1000 mb speed bits in 1064 * the 1000Base-T Control Register (Address 9). 1065 */ 1066 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK; 1067 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK; 1068 1069 DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised); 1070 1071 /* Do we want to advertise 10 Mb Half Duplex? */ 1072 if(hw->autoneg_advertised & ADVERTISE_10_HALF) { 1073 DEBUGOUT("Advertise 10mb Half duplex\n"); 1074 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 1075 } 1076 1077 /* Do we want to advertise 10 Mb Full Duplex? */ 1078 if(hw->autoneg_advertised & ADVERTISE_10_FULL) { 1079 DEBUGOUT("Advertise 10mb Full duplex\n"); 1080 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 1081 } 1082 1083 /* Do we want to advertise 100 Mb Half Duplex? */ 1084 if(hw->autoneg_advertised & ADVERTISE_100_HALF) { 1085 DEBUGOUT("Advertise 100mb Half duplex\n"); 1086 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 1087 } 1088 1089 /* Do we want to advertise 100 Mb Full Duplex? */ 1090 if(hw->autoneg_advertised & ADVERTISE_100_FULL) { 1091 DEBUGOUT("Advertise 100mb Full duplex\n"); 1092 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 1093 } 1094 1095 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 1096 if(hw->autoneg_advertised & ADVERTISE_1000_HALF) { 1097 DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n"); 1098 } 1099 1100 /* Do we want to advertise 1000 Mb Full Duplex? */ 1101 if(hw->autoneg_advertised & ADVERTISE_1000_FULL) { 1102 DEBUGOUT("Advertise 1000mb Full duplex\n"); 1103 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 1104 } 1105 1106 /* Check for a software override of the flow control settings, and 1107 * setup the PHY advertisement registers accordingly. If 1108 * auto-negotiation is enabled, then software will have to set the 1109 * "PAUSE" bits to the correct value in the Auto-Negotiation 1110 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation. 1111 * 1112 * The possible values of the "fc" parameter are: 1113 * 0: Flow control is completely disabled 1114 * 1: Rx flow control is enabled (we can receive pause frames 1115 * but not send pause frames). 1116 * 2: Tx flow control is enabled (we can send pause frames 1117 * but we do not support receiving pause frames). 1118 * 3: Both Rx and TX flow control (symmetric) are enabled. 1119 * other: No software override. The flow control configuration 1120 * in the EEPROM is used. 1121 */ 1122 switch (hw->fc) { 1123 case em_fc_none: /* 0 */ 1124 /* Flow control (RX & TX) is completely disabled by a 1125 * software over-ride. 1126 */ 1127 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1128 break; 1129 case em_fc_rx_pause: /* 1 */ 1130 /* RX Flow control is enabled, and TX Flow control is 1131 * disabled, by a software over-ride. 1132 */ 1133 /* Since there really isn't a way to advertise that we are 1134 * capable of RX Pause ONLY, we will advertise that we 1135 * support both symmetric and asymmetric RX PAUSE. Later 1136 * (in em_config_fc_after_link_up) we will disable the 1137 *hw's ability to send PAUSE frames. 1138 */ 1139 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1140 break; 1141 case em_fc_tx_pause: /* 2 */ 1142 /* TX Flow control is enabled, and RX Flow control is 1143 * disabled, by a software over-ride. 1144 */ 1145 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 1146 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 1147 break; 1148 case em_fc_full: /* 3 */ 1149 /* Flow control (both RX and TX) is enabled by a software 1150 * over-ride. 1151 */ 1152 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1153 break; 1154 default: 1155 DEBUGOUT("Flow control param set incorrectly\n"); 1156 return -E1000_ERR_CONFIG; 1157 } 1158 1159 if(em_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg) < 0) { 1160 DEBUGOUT("PHY Write Error\n"); 1161 return -E1000_ERR_PHY; 1162 } 1163 1164 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 1165 1166 if(em_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg) < 0) { 1167 DEBUGOUT("PHY Write Error\n"); 1168 return -E1000_ERR_PHY; 1169 } 1170 return 0; 1171 } 1172 1173 /****************************************************************************** 1174 * Force PHY speed and duplex settings to hw->forced_speed_duplex 1175 * 1176 * hw - Struct containing variables accessed by shared code 1177 ******************************************************************************/ 1178 static int32_t 1179 em_phy_force_speed_duplex(struct em_hw *hw) 1180 { 1181 uint32_t ctrl; 1182 int32_t ret_val; 1183 uint16_t mii_ctrl_reg; 1184 uint16_t mii_status_reg; 1185 uint16_t phy_data; 1186 uint16_t i; 1187 1188 DEBUGFUNC("em_phy_force_speed_duplex"); 1189 1190 /* Turn off Flow control if we are forcing speed and duplex. */ 1191 hw->fc = em_fc_none; 1192 1193 DEBUGOUT1("hw->fc = %d\n", hw->fc); 1194 1195 /* Read the Device Control Register. */ 1196 ctrl = E1000_READ_REG(hw, CTRL); 1197 1198 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */ 1199 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1200 ctrl &= ~(DEVICE_SPEED_MASK); 1201 1202 /* Clear the Auto Speed Detect Enable bit. */ 1203 ctrl &= ~E1000_CTRL_ASDE; 1204 1205 /* Read the MII Control Register. */ 1206 if(em_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg) < 0) { 1207 DEBUGOUT("PHY Read Error\n"); 1208 return -E1000_ERR_PHY; 1209 } 1210 1211 /* We need to disable autoneg in order to force link and duplex. */ 1212 1213 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN; 1214 1215 /* Are we forcing Full or Half Duplex? */ 1216 if(hw->forced_speed_duplex == em_100_full || 1217 hw->forced_speed_duplex == em_10_full) { 1218 /* We want to force full duplex so we SET the full duplex bits in the 1219 * Device and MII Control Registers. 1220 */ 1221 ctrl |= E1000_CTRL_FD; 1222 mii_ctrl_reg |= MII_CR_FULL_DUPLEX; 1223 DEBUGOUT("Full Duplex\n"); 1224 } else { 1225 /* We want to force half duplex so we CLEAR the full duplex bits in 1226 * the Device and MII Control Registers. 1227 */ 1228 ctrl &= ~E1000_CTRL_FD; 1229 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX; 1230 DEBUGOUT("Half Duplex\n"); 1231 } 1232 1233 /* Are we forcing 100Mbps??? */ 1234 if(hw->forced_speed_duplex == em_100_full || 1235 hw->forced_speed_duplex == em_100_half) { 1236 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */ 1237 ctrl |= E1000_CTRL_SPD_100; 1238 mii_ctrl_reg |= MII_CR_SPEED_100; 1239 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); 1240 DEBUGOUT("Forcing 100mb "); 1241 } else { 1242 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */ 1243 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 1244 mii_ctrl_reg |= MII_CR_SPEED_10; 1245 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); 1246 DEBUGOUT("Forcing 10mb "); 1247 } 1248 1249 em_config_collision_dist(hw); 1250 1251 /* Write the configured values back to the Device Control Reg. */ 1252 E1000_WRITE_REG(hw, CTRL, ctrl); 1253 1254 if (hw->phy_type == em_phy_m88) { 1255 if(em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data) < 0) { 1256 DEBUGOUT("PHY Read Error\n"); 1257 return -E1000_ERR_PHY; 1258 } 1259 1260 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI 1261 * forced whenever speed are duplex are forced. 1262 */ 1263 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1264 if(em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data) < 0) { 1265 DEBUGOUT("PHY Write Error\n"); 1266 return -E1000_ERR_PHY; 1267 } 1268 DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data); 1269 1270 /* Need to reset the PHY or these changes will be ignored */ 1271 mii_ctrl_reg |= MII_CR_RESET; 1272 } else { 1273 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI 1274 * forced whenever speed or duplex are forced. 1275 */ 1276 if(em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data) < 0) { 1277 DEBUGOUT("PHY Read Error\n"); 1278 return -E1000_ERR_PHY; 1279 } 1280 1281 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 1282 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 1283 1284 if(em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data) < 0) { 1285 DEBUGOUT("PHY Write Error\n"); 1286 return -E1000_ERR_PHY; 1287 } 1288 } 1289 1290 /* Write back the modified PHY MII control register. */ 1291 if(em_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg) < 0) { 1292 DEBUGOUT("PHY Write Error\n"); 1293 return -E1000_ERR_PHY; 1294 } 1295 usec_delay(1); 1296 1297 /* The wait_autoneg_complete flag may be a little misleading here. 1298 * Since we are forcing speed and duplex, Auto-Neg is not enabled. 1299 * But we do want to delay for a period while forcing only so we 1300 * don't generate false No Link messages. So we will wait here 1301 * only if the user has set wait_autoneg_complete to 1, which is 1302 * the default. 1303 */ 1304 if(hw->wait_autoneg_complete) { 1305 /* We will wait for autoneg to complete. */ 1306 DEBUGOUT("Waiting for forced speed/duplex link.\n"); 1307 mii_status_reg = 0; 1308 1309 /* We will wait for autoneg to complete or 4.5 seconds to expire. */ 1310 for(i = PHY_FORCE_TIME; i > 0; i--) { 1311 /* Read the MII Status Register and wait for Auto-Neg Complete bit 1312 * to be set. 1313 */ 1314 if(em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) { 1315 DEBUGOUT("PHY Read Error\n"); 1316 return -E1000_ERR_PHY; 1317 } 1318 if(em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) { 1319 DEBUGOUT("PHY Read Error\n"); 1320 return -E1000_ERR_PHY; 1321 } 1322 if(mii_status_reg & MII_SR_LINK_STATUS) break; 1323 msec_delay(100); 1324 } 1325 if(i == 0) { /* We didn't get link */ 1326 /* Reset the DSP and wait again for link. */ 1327 1328 ret_val = em_phy_reset_dsp(hw); 1329 if(ret_val < 0) { 1330 DEBUGOUT("Error Resetting PHY DSP\n"); 1331 return ret_val; 1332 } 1333 } 1334 /* This loop will early-out if the link condition has been met. */ 1335 for(i = PHY_FORCE_TIME; i > 0; i--) { 1336 if(mii_status_reg & MII_SR_LINK_STATUS) break; 1337 msec_delay(100); 1338 /* Read the MII Status Register and wait for Auto-Neg Complete bit 1339 * to be set. 1340 */ 1341 if(em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) { 1342 DEBUGOUT("PHY Read Error\n"); 1343 return -E1000_ERR_PHY; 1344 } 1345 if(em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) { 1346 DEBUGOUT("PHY Read Error\n"); 1347 return -E1000_ERR_PHY; 1348 } 1349 } 1350 } 1351 1352 if (hw->phy_type == em_phy_m88) { 1353 /* Because we reset the PHY above, we need to re-force TX_CLK in the 1354 * Extended PHY Specific Control Register to 25MHz clock. This value 1355 * defaults back to a 2.5MHz clock when the PHY is reset. 1356 */ 1357 if(em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data) < 0) { 1358 DEBUGOUT("PHY Read Error\n"); 1359 return -E1000_ERR_PHY; 1360 } 1361 phy_data |= M88E1000_EPSCR_TX_CLK_25; 1362 if(em_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data) < 0) { 1363 DEBUGOUT("PHY Write Error\n"); 1364 return -E1000_ERR_PHY; 1365 } 1366 1367 /* In addition, because of the s/w reset above, we need to enable CRS on 1368 * TX. This must be set for both full and half duplex operation. 1369 */ 1370 if(em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data) < 0) { 1371 DEBUGOUT("PHY Read Error\n"); 1372 return -E1000_ERR_PHY; 1373 } 1374 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 1375 if(em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data) < 0) { 1376 DEBUGOUT("PHY Write Error\n"); 1377 return -E1000_ERR_PHY; 1378 } 1379 } 1380 return 0; 1381 } 1382 1383 /****************************************************************************** 1384 * Sets the collision distance in the Transmit Control register 1385 * 1386 * hw - Struct containing variables accessed by shared code 1387 * 1388 * Link should have been established previously. Reads the speed and duplex 1389 * information from the Device Status register. 1390 ******************************************************************************/ 1391 void 1392 em_config_collision_dist(struct em_hw *hw) 1393 { 1394 uint32_t tctl; 1395 1396 DEBUGFUNC("em_config_collision_dist"); 1397 1398 tctl = E1000_READ_REG(hw, TCTL); 1399 1400 tctl &= ~E1000_TCTL_COLD; 1401 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT; 1402 1403 E1000_WRITE_REG(hw, TCTL, tctl); 1404 E1000_WRITE_FLUSH(hw); 1405 } 1406 1407 /****************************************************************************** 1408 * Sets MAC speed and duplex settings to reflect the those in the PHY 1409 * 1410 * hw - Struct containing variables accessed by shared code 1411 * mii_reg - data to write to the MII control register 1412 * 1413 * The contents of the PHY register containing the needed information need to 1414 * be passed in. 1415 ******************************************************************************/ 1416 static int32_t 1417 em_config_mac_to_phy(struct em_hw *hw) 1418 { 1419 uint32_t ctrl; 1420 uint16_t phy_data; 1421 1422 DEBUGFUNC("em_config_mac_to_phy"); 1423 1424 /* Read the Device Control Register and set the bits to Force Speed 1425 * and Duplex. 1426 */ 1427 ctrl = E1000_READ_REG(hw, CTRL); 1428 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1429 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); 1430 1431 /* Set up duplex in the Device Control and Transmit Control 1432 * registers depending on negotiated values. 1433 */ 1434 if (hw->phy_type == em_phy_igp) { 1435 if(em_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data) < 0) { 1436 DEBUGOUT("PHY Read Error\n"); 1437 return -E1000_ERR_PHY; 1438 } 1439 if(phy_data & IGP01E1000_PSSR_FULL_DUPLEX) ctrl |= E1000_CTRL_FD; 1440 else ctrl &= ~E1000_CTRL_FD; 1441 1442 em_config_collision_dist(hw); 1443 1444 /* Set up speed in the Device Control register depending on 1445 * negotiated values. 1446 */ 1447 if((phy_data & IGP01E1000_PSSR_SPEED_MASK) == 1448 IGP01E1000_PSSR_SPEED_1000MBPS) 1449 ctrl |= E1000_CTRL_SPD_1000; 1450 else if((phy_data & IGP01E1000_PSSR_SPEED_MASK) == 1451 IGP01E1000_PSSR_SPEED_100MBPS) 1452 ctrl |= E1000_CTRL_SPD_100; 1453 } else { 1454 if(em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) { 1455 DEBUGOUT("PHY Read Error\n"); 1456 return -E1000_ERR_PHY; 1457 } 1458 if(phy_data & M88E1000_PSSR_DPLX) ctrl |= E1000_CTRL_FD; 1459 else ctrl &= ~E1000_CTRL_FD; 1460 1461 em_config_collision_dist(hw); 1462 1463 /* Set up speed in the Device Control register depending on 1464 * negotiated values. 1465 */ 1466 if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) 1467 ctrl |= E1000_CTRL_SPD_1000; 1468 else if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) 1469 ctrl |= E1000_CTRL_SPD_100; 1470 } 1471 /* Write the configured values back to the Device Control Reg. */ 1472 E1000_WRITE_REG(hw, CTRL, ctrl); 1473 return 0; 1474 } 1475 1476 /****************************************************************************** 1477 * Forces the MAC's flow control settings. 1478 * 1479 * hw - Struct containing variables accessed by shared code 1480 * 1481 * Sets the TFCE and RFCE bits in the device control register to reflect 1482 * the adapter settings. TFCE and RFCE need to be explicitly set by 1483 * software when a Copper PHY is used because autonegotiation is managed 1484 * by the PHY rather than the MAC. Software must also configure these 1485 * bits when link is forced on a fiber connection. 1486 *****************************************************************************/ 1487 static int32_t 1488 em_force_mac_fc(struct em_hw *hw) 1489 { 1490 uint32_t ctrl; 1491 1492 DEBUGFUNC("em_force_mac_fc"); 1493 1494 /* Get the current configuration of the Device Control Register */ 1495 ctrl = E1000_READ_REG(hw, CTRL); 1496 1497 /* Because we didn't get link via the internal auto-negotiation 1498 * mechanism (we either forced link or we got link via PHY 1499 * auto-neg), we have to manually enable/disable transmit an 1500 * receive flow control. 1501 * 1502 * The "Case" statement below enables/disable flow control 1503 * according to the "hw->fc" parameter. 1504 * 1505 * The possible values of the "fc" parameter are: 1506 * 0: Flow control is completely disabled 1507 * 1: Rx flow control is enabled (we can receive pause 1508 * frames but not send pause frames). 1509 * 2: Tx flow control is enabled (we can send pause frames 1510 * frames but we do not receive pause frames). 1511 * 3: Both Rx and TX flow control (symmetric) is enabled. 1512 * other: No other values should be possible at this point. 1513 */ 1514 1515 switch (hw->fc) { 1516 case em_fc_none: 1517 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 1518 break; 1519 case em_fc_rx_pause: 1520 ctrl &= (~E1000_CTRL_TFCE); 1521 ctrl |= E1000_CTRL_RFCE; 1522 break; 1523 case em_fc_tx_pause: 1524 ctrl &= (~E1000_CTRL_RFCE); 1525 ctrl |= E1000_CTRL_TFCE; 1526 break; 1527 case em_fc_full: 1528 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 1529 break; 1530 default: 1531 DEBUGOUT("Flow control param set incorrectly\n"); 1532 return -E1000_ERR_CONFIG; 1533 } 1534 1535 /* Disable TX Flow Control for 82542 (rev 2.0) */ 1536 if(hw->mac_type == em_82542_rev2_0) 1537 ctrl &= (~E1000_CTRL_TFCE); 1538 1539 E1000_WRITE_REG(hw, CTRL, ctrl); 1540 return 0; 1541 } 1542 1543 /****************************************************************************** 1544 * Configures flow control settings after link is established 1545 * 1546 * hw - Struct containing variables accessed by shared code 1547 * 1548 * Should be called immediately after a valid link has been established. 1549 * Forces MAC flow control settings if link was forced. When in MII/GMII mode 1550 * and autonegotiation is enabled, the MAC flow control settings will be set 1551 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE 1552 * and RFCE bits will be automaticaly set to the negotiated flow control mode. 1553 *****************************************************************************/ 1554 int32_t 1555 em_config_fc_after_link_up(struct em_hw *hw) 1556 { 1557 int32_t ret_val; 1558 uint16_t mii_status_reg; 1559 uint16_t mii_nway_adv_reg; 1560 uint16_t mii_nway_lp_ability_reg; 1561 uint16_t speed; 1562 uint16_t duplex; 1563 1564 DEBUGFUNC("em_config_fc_after_link_up"); 1565 1566 /* Check for the case where we have fiber media and auto-neg failed 1567 * so we had to force link. In this case, we need to force the 1568 * configuration of the MAC to match the "fc" parameter. 1569 */ 1570 if(((hw->media_type == em_media_type_fiber) && (hw->autoneg_failed)) || 1571 ((hw->media_type == em_media_type_copper) && (!hw->autoneg))) { 1572 ret_val = em_force_mac_fc(hw); 1573 if(ret_val < 0) { 1574 DEBUGOUT("Error forcing flow control settings\n"); 1575 return ret_val; 1576 } 1577 } 1578 1579 /* Check for the case where we have copper media and auto-neg is 1580 * enabled. In this case, we need to check and see if Auto-Neg 1581 * has completed, and if so, how the PHY and link partner has 1582 * flow control configured. 1583 */ 1584 if((hw->media_type == em_media_type_copper) && hw->autoneg) { 1585 /* Read the MII Status Register and check to see if AutoNeg 1586 * has completed. We read this twice because this reg has 1587 * some "sticky" (latched) bits. 1588 */ 1589 if(em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) { 1590 DEBUGOUT("PHY Read Error \n"); 1591 return -E1000_ERR_PHY; 1592 } 1593 if(em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) { 1594 DEBUGOUT("PHY Read Error \n"); 1595 return -E1000_ERR_PHY; 1596 } 1597 1598 if(mii_status_reg & MII_SR_AUTONEG_COMPLETE) { 1599 /* The AutoNeg process has completed, so we now need to 1600 * read both the Auto Negotiation Advertisement Register 1601 * (Address 4) and the Auto_Negotiation Base Page Ability 1602 * Register (Address 5) to determine how flow control was 1603 * negotiated. 1604 */ 1605 if(em_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg) < 0) { 1606 DEBUGOUT("PHY Read Error\n"); 1607 return -E1000_ERR_PHY; 1608 } 1609 if(em_read_phy_reg(hw, PHY_LP_ABILITY, &mii_nway_lp_ability_reg) < 0) { 1610 DEBUGOUT("PHY Read Error\n"); 1611 return -E1000_ERR_PHY; 1612 } 1613 1614 /* Two bits in the Auto Negotiation Advertisement Register 1615 * (Address 4) and two bits in the Auto Negotiation Base 1616 * Page Ability Register (Address 5) determine flow control 1617 * for both the PHY and the link partner. The following 1618 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 1619 * 1999, describes these PAUSE resolution bits and how flow 1620 * control is determined based upon these settings. 1621 * NOTE: DC = Don't Care 1622 * 1623 * LOCAL DEVICE | LINK PARTNER 1624 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 1625 *-------|---------|-------|---------|-------------------- 1626 * 0 | 0 | DC | DC | em_fc_none 1627 * 0 | 1 | 0 | DC | em_fc_none 1628 * 0 | 1 | 1 | 0 | em_fc_none 1629 * 0 | 1 | 1 | 1 | em_fc_tx_pause 1630 * 1 | 0 | 0 | DC | em_fc_none 1631 * 1 | DC | 1 | DC | em_fc_full 1632 * 1 | 1 | 0 | 0 | em_fc_none 1633 * 1 | 1 | 0 | 1 | em_fc_rx_pause 1634 * 1635 */ 1636 /* Are both PAUSE bits set to 1? If so, this implies 1637 * Symmetric Flow Control is enabled at both ends. The 1638 * ASM_DIR bits are irrelevant per the spec. 1639 * 1640 * For Symmetric Flow Control: 1641 * 1642 * LOCAL DEVICE | LINK PARTNER 1643 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1644 *-------|---------|-------|---------|-------------------- 1645 * 1 | DC | 1 | DC | em_fc_full 1646 * 1647 */ 1648 if((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1649 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 1650 /* Now we need to check if the user selected RX ONLY 1651 * of pause frames. In this case, we had to advertise 1652 * FULL flow control because we could not advertise RX 1653 * ONLY. Hence, we must now check to see if we need to 1654 * turn OFF the TRANSMISSION of PAUSE frames. 1655 */ 1656 if(hw->original_fc == em_fc_full) { 1657 hw->fc = em_fc_full; 1658 DEBUGOUT("Flow Control = FULL.\r\n"); 1659 } else { 1660 hw->fc = em_fc_rx_pause; 1661 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n"); 1662 } 1663 } 1664 /* For receiving PAUSE frames ONLY. 1665 * 1666 * LOCAL DEVICE | LINK PARTNER 1667 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1668 *-------|---------|-------|---------|-------------------- 1669 * 0 | 1 | 1 | 1 | em_fc_tx_pause 1670 * 1671 */ 1672 else if(!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 1673 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1674 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1675 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1676 hw->fc = em_fc_tx_pause; 1677 DEBUGOUT("Flow Control = TX PAUSE frames only.\r\n"); 1678 } 1679 /* For transmitting PAUSE frames ONLY. 1680 * 1681 * LOCAL DEVICE | LINK PARTNER 1682 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1683 *-------|---------|-------|---------|-------------------- 1684 * 1 | 1 | 0 | 1 | em_fc_rx_pause 1685 * 1686 */ 1687 else if((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1688 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1689 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1690 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1691 hw->fc = em_fc_rx_pause; 1692 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n"); 1693 } 1694 /* Per the IEEE spec, at this point flow control should be 1695 * disabled. However, we want to consider that we could 1696 * be connected to a legacy switch that doesn't advertise 1697 * desired flow control, but can be forced on the link 1698 * partner. So if we advertised no flow control, that is 1699 * what we will resolve to. If we advertised some kind of 1700 * receive capability (Rx Pause Only or Full Flow Control) 1701 * and the link partner advertised none, we will configure 1702 * ourselves to enable Rx Flow Control only. We can do 1703 * this safely for two reasons: If the link partner really 1704 * didn't want flow control enabled, and we enable Rx, no 1705 * harm done since we won't be receiving any PAUSE frames 1706 * anyway. If the intent on the link partner was to have 1707 * flow control enabled, then by us enabling RX only, we 1708 * can at least receive pause frames and process them. 1709 * This is a good idea because in most cases, since we are 1710 * predominantly a server NIC, more times than not we will 1711 * be asked to delay transmission of packets than asking 1712 * our link partner to pause transmission of frames. 1713 */ 1714 else if(hw->original_fc == em_fc_none || 1715 hw->original_fc == em_fc_tx_pause) { 1716 hw->fc = em_fc_none; 1717 DEBUGOUT("Flow Control = NONE.\r\n"); 1718 } else { 1719 hw->fc = em_fc_rx_pause; 1720 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n"); 1721 } 1722 1723 /* Now we need to do one last check... If we auto- 1724 * negotiated to HALF DUPLEX, flow control should not be 1725 * enabled per IEEE 802.3 spec. 1726 */ 1727 em_get_speed_and_duplex(hw, &speed, &duplex); 1728 1729 if(duplex == HALF_DUPLEX) 1730 hw->fc = em_fc_none; 1731 1732 /* Now we call a subroutine to actually force the MAC 1733 * controller to use the correct flow control settings. 1734 */ 1735 ret_val = em_force_mac_fc(hw); 1736 if(ret_val < 0) { 1737 DEBUGOUT("Error forcing flow control settings\n"); 1738 return ret_val; 1739 } 1740 } else { 1741 DEBUGOUT("Copper PHY and Auto Neg has not completed.\r\n"); 1742 } 1743 } 1744 return 0; 1745 } 1746 1747 /****************************************************************************** 1748 * Checks to see if the link status of the hardware has changed. 1749 * 1750 * hw - Struct containing variables accessed by shared code 1751 * 1752 * Called by any function that needs to check the link status of the adapter. 1753 *****************************************************************************/ 1754 int32_t 1755 em_check_for_link(struct em_hw *hw) 1756 { 1757 uint32_t rxcw; 1758 uint32_t ctrl; 1759 uint32_t status; 1760 uint32_t rctl; 1761 uint32_t signal; 1762 int32_t ret_val; 1763 uint16_t phy_data; 1764 uint16_t lp_capability; 1765 1766 DEBUGFUNC("em_check_for_link"); 1767 1768 /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be 1769 * set when the optics detect a signal. On older adapters, it will be 1770 * cleared when there is a signal 1771 */ 1772 if(hw->mac_type > em_82544) signal = E1000_CTRL_SWDPIN1; 1773 else signal = 0; 1774 1775 ctrl = E1000_READ_REG(hw, CTRL); 1776 status = E1000_READ_REG(hw, STATUS); 1777 rxcw = E1000_READ_REG(hw, RXCW); 1778 1779 /* If we have a copper PHY then we only want to go out to the PHY 1780 * registers to see if Auto-Neg has completed and/or if our link 1781 * status has changed. The get_link_status flag will be set if we 1782 * receive a Link Status Change interrupt or we have Rx Sequence 1783 * Errors. 1784 */ 1785 if((hw->media_type == em_media_type_copper) && hw->get_link_status) { 1786 /* First we want to see if the MII Status Register reports 1787 * link. If so, then we want to get the current speed/duplex 1788 * of the PHY. 1789 * Read the register twice since the link bit is sticky. 1790 */ 1791 if(em_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 1792 DEBUGOUT("PHY Read Error\n"); 1793 return -E1000_ERR_PHY; 1794 } 1795 if(em_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 1796 DEBUGOUT("PHY Read Error\n"); 1797 return -E1000_ERR_PHY; 1798 } 1799 1800 if(phy_data & MII_SR_LINK_STATUS) { 1801 hw->get_link_status = FALSE; 1802 /* Check if there was DownShift, must be checked immediately after 1803 * link-up */ 1804 em_check_downshift(hw); 1805 1806 } else { 1807 /* No link detected */ 1808 return 0; 1809 } 1810 1811 /* If we are forcing speed/duplex, then we simply return since 1812 * we have already determined whether we have link or not. 1813 */ 1814 if(!hw->autoneg) return -E1000_ERR_CONFIG; 1815 1816 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we 1817 * have Si on board that is 82544 or newer, Auto 1818 * Speed Detection takes care of MAC speed/duplex 1819 * configuration. So we only need to configure Collision 1820 * Distance in the MAC. Otherwise, we need to force 1821 * speed/duplex on the MAC to the current PHY speed/duplex 1822 * settings. 1823 */ 1824 if(hw->mac_type >= em_82544) 1825 em_config_collision_dist(hw); 1826 else { 1827 ret_val = em_config_mac_to_phy(hw); 1828 if(ret_val < 0) { 1829 DEBUGOUT("Error configuring MAC to PHY settings\n"); 1830 return ret_val; 1831 } 1832 } 1833 1834 /* Configure Flow Control now that Auto-Neg has completed. First, we 1835 * need to restore the desired flow control settings because we may 1836 * have had to re-autoneg with a different link partner. 1837 */ 1838 ret_val = em_config_fc_after_link_up(hw); 1839 if(ret_val < 0) { 1840 DEBUGOUT("Error configuring flow control\n"); 1841 return ret_val; 1842 } 1843 1844 /* At this point we know that we are on copper and we have 1845 * auto-negotiated link. These are conditions for checking the link 1846 * parter capability register. We use the link partner capability to 1847 * determine if TBI Compatibility needs to be turned on or off. If 1848 * the link partner advertises any speed in addition to Gigabit, then 1849 * we assume that they are GMII-based, and TBI compatibility is not 1850 * needed. If no other speeds are advertised, we assume the link 1851 * partner is TBI-based, and we turn on TBI Compatibility. 1852 */ 1853 if(hw->tbi_compatibility_en) { 1854 if(em_read_phy_reg(hw, PHY_LP_ABILITY, &lp_capability) < 0) { 1855 DEBUGOUT("PHY Read Error\n"); 1856 return -E1000_ERR_PHY; 1857 } 1858 if(lp_capability & (NWAY_LPAR_10T_HD_CAPS | 1859 NWAY_LPAR_10T_FD_CAPS | 1860 NWAY_LPAR_100TX_HD_CAPS | 1861 NWAY_LPAR_100TX_FD_CAPS | 1862 NWAY_LPAR_100T4_CAPS)) { 1863 /* If our link partner advertises anything in addition to 1864 * gigabit, we do not need to enable TBI compatibility. 1865 */ 1866 if(hw->tbi_compatibility_on) { 1867 /* If we previously were in the mode, turn it off. */ 1868 rctl = E1000_READ_REG(hw, RCTL); 1869 rctl &= ~E1000_RCTL_SBP; 1870 E1000_WRITE_REG(hw, RCTL, rctl); 1871 hw->tbi_compatibility_on = FALSE; 1872 } 1873 } else { 1874 /* If TBI compatibility is was previously off, turn it on. For 1875 * compatibility with a TBI link partner, we will store bad 1876 * packets. Some frames have an additional byte on the end and 1877 * will look like CRC errors to to the hardware. 1878 */ 1879 if(!hw->tbi_compatibility_on) { 1880 hw->tbi_compatibility_on = TRUE; 1881 rctl = E1000_READ_REG(hw, RCTL); 1882 rctl |= E1000_RCTL_SBP; 1883 E1000_WRITE_REG(hw, RCTL, rctl); 1884 } 1885 } 1886 } 1887 } 1888 /* If we don't have link (auto-negotiation failed or link partner cannot 1889 * auto-negotiate), the cable is plugged in (we have signal), and our 1890 * link partner is not trying to auto-negotiate with us (we are receiving 1891 * idles or data), we need to force link up. We also need to give 1892 * auto-negotiation time to complete, in case the cable was just plugged 1893 * in. The autoneg_failed flag does this. 1894 */ 1895 else if((hw->media_type == em_media_type_fiber) && 1896 (!(status & E1000_STATUS_LU)) && 1897 ((ctrl & E1000_CTRL_SWDPIN1) == signal) && 1898 (!(rxcw & E1000_RXCW_C))) { 1899 if(hw->autoneg_failed == 0) { 1900 hw->autoneg_failed = 1; 1901 return 0; 1902 } 1903 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n"); 1904 1905 /* Disable auto-negotiation in the TXCW register */ 1906 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE)); 1907 1908 /* Force link-up and also force full-duplex. */ 1909 ctrl = E1000_READ_REG(hw, CTRL); 1910 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 1911 E1000_WRITE_REG(hw, CTRL, ctrl); 1912 1913 /* Configure Flow Control after forcing link up. */ 1914 ret_val = em_config_fc_after_link_up(hw); 1915 if(ret_val < 0) { 1916 DEBUGOUT("Error configuring flow control\n"); 1917 return ret_val; 1918 } 1919 } 1920 /* If we are forcing link and we are receiving /C/ ordered sets, re-enable 1921 * auto-negotiation in the TXCW register and disable forced link in the 1922 * Device Control register in an attempt to auto-negotiate with our link 1923 * partner. 1924 */ 1925 else if((hw->media_type == em_media_type_fiber) && 1926 (ctrl & E1000_CTRL_SLU) && 1927 (rxcw & E1000_RXCW_C)) { 1928 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\r\n"); 1929 E1000_WRITE_REG(hw, TXCW, hw->txcw); 1930 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU)); 1931 } 1932 return 0; 1933 } 1934 1935 /****************************************************************************** 1936 * Detects the current speed and duplex settings of the hardware. 1937 * 1938 * hw - Struct containing variables accessed by shared code 1939 * speed - Speed of the connection 1940 * duplex - Duplex setting of the connection 1941 *****************************************************************************/ 1942 void 1943 em_get_speed_and_duplex(struct em_hw *hw, 1944 uint16_t *speed, 1945 uint16_t *duplex) 1946 { 1947 uint32_t status; 1948 1949 DEBUGFUNC("em_get_speed_and_duplex"); 1950 1951 if(hw->mac_type >= em_82543) { 1952 status = E1000_READ_REG(hw, STATUS); 1953 if(status & E1000_STATUS_SPEED_1000) { 1954 *speed = SPEED_1000; 1955 DEBUGOUT("1000 Mbs, "); 1956 } else if(status & E1000_STATUS_SPEED_100) { 1957 *speed = SPEED_100; 1958 DEBUGOUT("100 Mbs, "); 1959 } else { 1960 *speed = SPEED_10; 1961 DEBUGOUT("10 Mbs, "); 1962 } 1963 1964 if(status & E1000_STATUS_FD) { 1965 *duplex = FULL_DUPLEX; 1966 DEBUGOUT("Full Duplex\r\n"); 1967 } else { 1968 *duplex = HALF_DUPLEX; 1969 DEBUGOUT(" Half Duplex\r\n"); 1970 } 1971 } else { 1972 DEBUGOUT("1000 Mbs, Full Duplex\r\n"); 1973 *speed = SPEED_1000; 1974 *duplex = FULL_DUPLEX; 1975 } 1976 } 1977 1978 /****************************************************************************** 1979 * Blocks until autoneg completes or times out (~4.5 seconds) 1980 * 1981 * hw - Struct containing variables accessed by shared code 1982 ******************************************************************************/ 1983 int32_t 1984 em_wait_autoneg(struct em_hw *hw) 1985 { 1986 uint16_t i; 1987 uint16_t phy_data; 1988 1989 DEBUGFUNC("em_wait_autoneg"); 1990 DEBUGOUT("Waiting for Auto-Neg to complete.\n"); 1991 1992 /* We will wait for autoneg to complete or 4.5 seconds to expire. */ 1993 for(i = PHY_AUTO_NEG_TIME; i > 0; i--) { 1994 /* Read the MII Status Register and wait for Auto-Neg 1995 * Complete bit to be set. 1996 */ 1997 if(em_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 1998 DEBUGOUT("PHY Read Error\n"); 1999 return -E1000_ERR_PHY; 2000 } 2001 if(em_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 2002 DEBUGOUT("PHY Read Error\n"); 2003 return -E1000_ERR_PHY; 2004 } 2005 if(phy_data & MII_SR_AUTONEG_COMPLETE) { 2006 return 0; 2007 } 2008 msec_delay(100); 2009 } 2010 return 0; 2011 } 2012 2013 /****************************************************************************** 2014 * Raises the Management Data Clock 2015 * 2016 * hw - Struct containing variables accessed by shared code 2017 * ctrl - Device control register's current value 2018 ******************************************************************************/ 2019 static void 2020 em_raise_mdi_clk(struct em_hw *hw, 2021 uint32_t *ctrl) 2022 { 2023 /* Raise the clock input to the Management Data Clock (by setting the MDC 2024 * bit), and then delay 2 microseconds. 2025 */ 2026 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC)); 2027 E1000_WRITE_FLUSH(hw); 2028 usec_delay(2); 2029 } 2030 2031 /****************************************************************************** 2032 * Lowers the Management Data Clock 2033 * 2034 * hw - Struct containing variables accessed by shared code 2035 * ctrl - Device control register's current value 2036 ******************************************************************************/ 2037 static void 2038 em_lower_mdi_clk(struct em_hw *hw, 2039 uint32_t *ctrl) 2040 { 2041 /* Lower the clock input to the Management Data Clock (by clearing the MDC 2042 * bit), and then delay 2 microseconds. 2043 */ 2044 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC)); 2045 E1000_WRITE_FLUSH(hw); 2046 usec_delay(2); 2047 } 2048 2049 /****************************************************************************** 2050 * Shifts data bits out to the PHY 2051 * 2052 * hw - Struct containing variables accessed by shared code 2053 * data - Data to send out to the PHY 2054 * count - Number of bits to shift out 2055 * 2056 * Bits are shifted out in MSB to LSB order. 2057 ******************************************************************************/ 2058 static void 2059 em_shift_out_mdi_bits(struct em_hw *hw, 2060 uint32_t data, 2061 uint16_t count) 2062 { 2063 uint32_t ctrl; 2064 uint32_t mask; 2065 2066 /* We need to shift "count" number of bits out to the PHY. So, the value 2067 * in the "data" parameter will be shifted out to the PHY one bit at a 2068 * time. In order to do this, "data" must be broken down into bits. 2069 */ 2070 mask = 0x01; 2071 mask <<= (count - 1); 2072 2073 ctrl = E1000_READ_REG(hw, CTRL); 2074 2075 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ 2076 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); 2077 2078 while(mask) { 2079 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and 2080 * then raising and lowering the Management Data Clock. A "0" is 2081 * shifted out to the PHY by setting the MDIO bit to "0" and then 2082 * raising and lowering the clock. 2083 */ 2084 if(data & mask) ctrl |= E1000_CTRL_MDIO; 2085 else ctrl &= ~E1000_CTRL_MDIO; 2086 2087 E1000_WRITE_REG(hw, CTRL, ctrl); 2088 E1000_WRITE_FLUSH(hw); 2089 2090 usec_delay(2); 2091 2092 em_raise_mdi_clk(hw, &ctrl); 2093 em_lower_mdi_clk(hw, &ctrl); 2094 2095 mask = mask >> 1; 2096 } 2097 } 2098 2099 /****************************************************************************** 2100 * Shifts data bits in from the PHY 2101 * 2102 * hw - Struct containing variables accessed by shared code 2103 * 2104 * Bits are shifted in in MSB to LSB order. 2105 ******************************************************************************/ 2106 static uint16_t 2107 em_shift_in_mdi_bits(struct em_hw *hw) 2108 { 2109 uint32_t ctrl; 2110 uint16_t data = 0; 2111 uint8_t i; 2112 2113 /* In order to read a register from the PHY, we need to shift in a total 2114 * of 18 bits from the PHY. The first two bit (turnaround) times are used 2115 * to avoid contention on the MDIO pin when a read operation is performed. 2116 * These two bits are ignored by us and thrown away. Bits are "shifted in" 2117 * by raising the input to the Management Data Clock (setting the MDC bit), 2118 * and then reading the value of the MDIO bit. 2119 */ 2120 ctrl = E1000_READ_REG(hw, CTRL); 2121 2122 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */ 2123 ctrl &= ~E1000_CTRL_MDIO_DIR; 2124 ctrl &= ~E1000_CTRL_MDIO; 2125 2126 E1000_WRITE_REG(hw, CTRL, ctrl); 2127 E1000_WRITE_FLUSH(hw); 2128 2129 /* Raise and Lower the clock before reading in the data. This accounts for 2130 * the turnaround bits. The first clock occurred when we clocked out the 2131 * last bit of the Register Address. 2132 */ 2133 em_raise_mdi_clk(hw, &ctrl); 2134 em_lower_mdi_clk(hw, &ctrl); 2135 2136 for(data = 0, i = 0; i < 16; i++) { 2137 data = data << 1; 2138 em_raise_mdi_clk(hw, &ctrl); 2139 ctrl = E1000_READ_REG(hw, CTRL); 2140 /* Check to see if we shifted in a "1". */ 2141 if(ctrl & E1000_CTRL_MDIO) data |= 1; 2142 em_lower_mdi_clk(hw, &ctrl); 2143 } 2144 2145 em_raise_mdi_clk(hw, &ctrl); 2146 em_lower_mdi_clk(hw, &ctrl); 2147 2148 return data; 2149 } 2150 2151 /***************************************************************************** 2152 * Reads the value from a PHY register 2153 * 2154 * hw - Struct containing variables accessed by shared code 2155 * reg_addr - address of the PHY register to read 2156 ******************************************************************************/ 2157 int32_t 2158 em_read_phy_reg(struct em_hw *hw, 2159 uint32_t reg_addr, 2160 uint16_t *phy_data) 2161 { 2162 uint32_t i; 2163 uint32_t mdic = 0; 2164 const uint32_t phy_addr = 1; 2165 2166 DEBUGFUNC("em_read_phy_reg"); 2167 2168 if(reg_addr > MAX_PHY_REG_ADDRESS) { 2169 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); 2170 return -E1000_ERR_PARAM; 2171 } 2172 2173 if(hw->mac_type > em_82543) { 2174 /* Set up Op-code, Phy Address, and register address in the MDI 2175 * Control register. The MAC will take care of interfacing with the 2176 * PHY to retrieve the desired data. 2177 */ 2178 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) | 2179 (phy_addr << E1000_MDIC_PHY_SHIFT) | 2180 (E1000_MDIC_OP_READ)); 2181 2182 E1000_WRITE_REG(hw, MDIC, mdic); 2183 2184 /* Poll the ready bit to see if the MDI read completed */ 2185 for(i = 0; i < 64; i++) { 2186 usec_delay(10); 2187 mdic = E1000_READ_REG(hw, MDIC); 2188 if(mdic & E1000_MDIC_READY) break; 2189 } 2190 if(!(mdic & E1000_MDIC_READY)) { 2191 DEBUGOUT("MDI Read did not complete\n"); 2192 return -E1000_ERR_PHY; 2193 } 2194 if(mdic & E1000_MDIC_ERROR) { 2195 DEBUGOUT("MDI Error\n"); 2196 return -E1000_ERR_PHY; 2197 } 2198 *phy_data = (uint16_t) mdic; 2199 } else { 2200 /* We must first send a preamble through the MDIO pin to signal the 2201 * beginning of an MII instruction. This is done by sending 32 2202 * consecutive "1" bits. 2203 */ 2204 em_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 2205 2206 /* Now combine the next few fields that are required for a read 2207 * operation. We use this method instead of calling the 2208 * em_shift_out_mdi_bits routine five different times. The format of 2209 * a MII read instruction consists of a shift out of 14 bits and is 2210 * defined as follows: 2211 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr> 2212 * followed by a shift in of 18 bits. This first two bits shifted in 2213 * are TurnAround bits used to avoid contention on the MDIO pin when a 2214 * READ operation is performed. These two bits are thrown away 2215 * followed by a shift in of 16 bits which contains the desired data. 2216 */ 2217 mdic = ((reg_addr) | (phy_addr << 5) | 2218 (PHY_OP_READ << 10) | (PHY_SOF << 12)); 2219 2220 em_shift_out_mdi_bits(hw, mdic, 14); 2221 2222 /* Now that we've shifted out the read command to the MII, we need to 2223 * "shift in" the 16-bit value (18 total bits) of the requested PHY 2224 * register address. 2225 */ 2226 *phy_data = em_shift_in_mdi_bits(hw); 2227 } 2228 return 0; 2229 } 2230 2231 /****************************************************************************** 2232 * Writes a value to a PHY register 2233 * 2234 * hw - Struct containing variables accessed by shared code 2235 * reg_addr - address of the PHY register to write 2236 * data - data to write to the PHY 2237 ******************************************************************************/ 2238 int32_t 2239 em_write_phy_reg(struct em_hw *hw, 2240 uint32_t reg_addr, 2241 uint16_t phy_data) 2242 { 2243 uint32_t i; 2244 uint32_t mdic = 0; 2245 const uint32_t phy_addr = 1; 2246 2247 DEBUGFUNC("em_write_phy_reg"); 2248 2249 if(reg_addr > MAX_PHY_REG_ADDRESS) { 2250 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); 2251 return -E1000_ERR_PARAM; 2252 } 2253 2254 if(hw->mac_type > em_82543) { 2255 /* Set up Op-code, Phy Address, register address, and data intended 2256 * for the PHY register in the MDI Control register. The MAC will take 2257 * care of interfacing with the PHY to send the desired data. 2258 */ 2259 mdic = (((uint32_t) phy_data) | 2260 (reg_addr << E1000_MDIC_REG_SHIFT) | 2261 (phy_addr << E1000_MDIC_PHY_SHIFT) | 2262 (E1000_MDIC_OP_WRITE)); 2263 2264 E1000_WRITE_REG(hw, MDIC, mdic); 2265 2266 /* Poll the ready bit to see if the MDI read completed */ 2267 for(i = 0; i < 64; i++) { 2268 usec_delay(10); 2269 mdic = E1000_READ_REG(hw, MDIC); 2270 if(mdic & E1000_MDIC_READY) break; 2271 } 2272 if(!(mdic & E1000_MDIC_READY)) { 2273 DEBUGOUT("MDI Write did not complete\n"); 2274 return -E1000_ERR_PHY; 2275 } 2276 } else { 2277 /* We'll need to use the SW defined pins to shift the write command 2278 * out to the PHY. We first send a preamble to the PHY to signal the 2279 * beginning of the MII instruction. This is done by sending 32 2280 * consecutive "1" bits. 2281 */ 2282 em_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 2283 2284 /* Now combine the remaining required fields that will indicate a 2285 * write operation. We use this method instead of calling the 2286 * em_shift_out_mdi_bits routine for each field in the command. The 2287 * format of a MII write instruction is as follows: 2288 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>. 2289 */ 2290 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) | 2291 (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); 2292 mdic <<= 16; 2293 mdic |= (uint32_t) phy_data; 2294 2295 em_shift_out_mdi_bits(hw, mdic, 32); 2296 } 2297 2298 return 0; 2299 } 2300 2301 /****************************************************************************** 2302 * Returns the PHY to the power-on reset state 2303 * 2304 * hw - Struct containing variables accessed by shared code 2305 ******************************************************************************/ 2306 void 2307 em_phy_hw_reset(struct em_hw *hw) 2308 { 2309 uint32_t ctrl, ctrl_ext; 2310 uint32_t led_ctrl; 2311 2312 DEBUGFUNC("em_phy_hw_reset"); 2313 2314 DEBUGOUT("Resetting Phy...\n"); 2315 2316 if(hw->mac_type > em_82543) { 2317 /* Read the device control register and assert the E1000_CTRL_PHY_RST 2318 * bit. Then, take it out of reset. 2319 */ 2320 ctrl = E1000_READ_REG(hw, CTRL); 2321 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST); 2322 E1000_WRITE_FLUSH(hw); 2323 msec_delay(10); 2324 E1000_WRITE_REG(hw, CTRL, ctrl); 2325 E1000_WRITE_FLUSH(hw); 2326 } else { 2327 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR 2328 * bit to put the PHY into reset. Then, take it out of reset. 2329 */ 2330 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 2331 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; 2332 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; 2333 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 2334 E1000_WRITE_FLUSH(hw); 2335 msec_delay(10); 2336 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; 2337 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 2338 E1000_WRITE_FLUSH(hw); 2339 } 2340 usec_delay(150); 2341 2342 if((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) { 2343 if(em_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT, 0x0000) < 0) { 2344 DEBUGOUT("PHY Write Error\n"); 2345 return; 2346 } 2347 2348 /* Configure activity LED after PHY reset */ 2349 led_ctrl = E1000_READ_REG(hw, LEDCTL); 2350 led_ctrl &= IGP_ACTIVITY_LED_MASK; 2351 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 2352 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 2353 } 2354 } 2355 2356 /****************************************************************************** 2357 * Resets the PHY 2358 * 2359 * hw - Struct containing variables accessed by shared code 2360 * 2361 * Sets bit 15 of the MII Control regiser 2362 ******************************************************************************/ 2363 int32_t 2364 em_phy_reset(struct em_hw *hw) 2365 { 2366 uint16_t phy_data; 2367 2368 DEBUGFUNC("em_phy_reset"); 2369 2370 if(em_read_phy_reg(hw, PHY_CTRL, &phy_data) < 0) { 2371 DEBUGOUT("PHY Read Error\n"); 2372 return -E1000_ERR_PHY; 2373 } 2374 phy_data |= MII_CR_RESET; 2375 if(em_write_phy_reg(hw, PHY_CTRL, phy_data) < 0) { 2376 DEBUGOUT("PHY Write Error\n"); 2377 return -E1000_ERR_PHY; 2378 } 2379 usec_delay(1); 2380 if (hw->phy_type == em_phy_igp) { 2381 em_phy_init_script(hw); 2382 } 2383 return 0; 2384 } 2385 2386 /****************************************************************************** 2387 * Probes the expected PHY address for known PHY IDs 2388 * 2389 * hw - Struct containing variables accessed by shared code 2390 ******************************************************************************/ 2391 int32_t 2392 em_detect_gig_phy(struct em_hw *hw) 2393 { 2394 uint16_t phy_id_high, phy_id_low; 2395 boolean_t match = FALSE; 2396 int32_t phy_init_status; 2397 2398 DEBUGFUNC("em_detect_gig_phy"); 2399 2400 /* Read the PHY ID Registers to identify which PHY is onboard. */ 2401 if(em_read_phy_reg(hw, PHY_ID1, &phy_id_high) < 0) { 2402 DEBUGOUT("PHY Read Error\n"); 2403 return -E1000_ERR_PHY; 2404 } 2405 hw->phy_id = (uint32_t) (phy_id_high << 16); 2406 usec_delay(20); 2407 if(em_read_phy_reg(hw, PHY_ID2, &phy_id_low) < 0) { 2408 DEBUGOUT("PHY Read Error\n"); 2409 return -E1000_ERR_PHY; 2410 } 2411 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK); 2412 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK; 2413 2414 switch(hw->mac_type) { 2415 case em_82543: 2416 if(hw->phy_id == M88E1000_E_PHY_ID) match = TRUE; 2417 break; 2418 case em_82544: 2419 if(hw->phy_id == M88E1000_I_PHY_ID) match = TRUE; 2420 break; 2421 case em_82540: 2422 case em_82545: 2423 case em_82546: 2424 if(hw->phy_id == M88E1011_I_PHY_ID) match = TRUE; 2425 break; 2426 case em_82541: 2427 case em_82547: 2428 if(hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE; 2429 break; 2430 default: 2431 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type); 2432 return -E1000_ERR_CONFIG; 2433 } 2434 phy_init_status = em_set_phy_type(hw); 2435 2436 if ((match) && (phy_init_status == E1000_SUCCESS)) { 2437 DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id); 2438 return 0; 2439 } 2440 DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id); 2441 return -E1000_ERR_PHY; 2442 } 2443 2444 /****************************************************************************** 2445 * Resets the PHY's DSP 2446 * 2447 * hw - Struct containing variables accessed by shared code 2448 ******************************************************************************/ 2449 static int32_t 2450 em_phy_reset_dsp(struct em_hw *hw) 2451 { 2452 int32_t ret_val = -E1000_ERR_PHY; 2453 DEBUGFUNC("em_phy_reset_dsp"); 2454 2455 do { 2456 if(em_write_phy_reg(hw, 29, 0x001d) < 0) break; 2457 if(em_write_phy_reg(hw, 30, 0x00c1) < 0) break; 2458 if(em_write_phy_reg(hw, 30, 0x0000) < 0) break; 2459 ret_val = 0; 2460 } while(0); 2461 2462 if(ret_val < 0) DEBUGOUT("PHY Write Error\n"); 2463 return ret_val; 2464 } 2465 2466 /****************************************************************************** 2467 * Get PHY information from various PHY registers for igp PHY only. 2468 * 2469 * hw - Struct containing variables accessed by shared code 2470 * phy_info - PHY information structure 2471 ******************************************************************************/ 2472 int32_t 2473 em_phy_igp_get_info(struct em_hw *hw, struct em_phy_info *phy_info) 2474 { 2475 uint16_t phy_data, polarity, min_length, max_length, average; 2476 2477 DEBUGFUNC("em_phy_igp_get_info"); 2478 2479 /* The downshift status is checked only once, after link is established, 2480 * and it stored in the hw->speed_downgraded parameter. */ 2481 phy_info->downshift = hw->speed_downgraded; 2482 2483 /* IGP01E1000 does not need to support it. */ 2484 phy_info->extended_10bt_distance = em_10bt_ext_dist_enable_normal; 2485 2486 /* IGP01E1000 always correct polarity reversal */ 2487 phy_info->polarity_correction = em_polarity_reversal_enabled; 2488 2489 /* Check polarity status */ 2490 if(em_check_polarity(hw, &polarity) < 0) 2491 return -E1000_ERR_PHY; 2492 2493 phy_info->cable_polarity = polarity; 2494 2495 if(em_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data) < 0) 2496 return -E1000_ERR_PHY; 2497 2498 phy_info->mdix_mode = (phy_data & IGP01E1000_PSSR_MDIX) >> 2499 IGP01E1000_PSSR_MDIX_SHIFT; 2500 2501 if((phy_data & IGP01E1000_PSSR_SPEED_MASK) == 2502 IGP01E1000_PSSR_SPEED_1000MBPS) { 2503 /* Local/Remote Receiver Information are only valid at 1000 Mbps */ 2504 if(em_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data) < 0) 2505 return -E1000_ERR_PHY; 2506 2507 phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >> 2508 SR_1000T_LOCAL_RX_STATUS_SHIFT; 2509 phy_info->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) >> 2510 SR_1000T_REMOTE_RX_STATUS_SHIFT; 2511 2512 /* Get cable length */ 2513 if(em_get_cable_length(hw, &min_length, &max_length) < 0) 2514 return -E1000_ERR_PHY; 2515 2516 /* transalte to old method */ 2517 average = (max_length + min_length) / 2; 2518 2519 if(average <= em_igp_cable_length_50) 2520 phy_info->cable_length = em_cable_length_50; 2521 else if(average <= em_igp_cable_length_80) 2522 phy_info->cable_length = em_cable_length_50_80; 2523 else if(average <= em_igp_cable_length_110) 2524 phy_info->cable_length = em_cable_length_80_110; 2525 else if(average <= em_igp_cable_length_140) 2526 phy_info->cable_length = em_cable_length_110_140; 2527 else 2528 phy_info->cable_length = em_cable_length_140; 2529 } 2530 2531 return E1000_SUCCESS; 2532 } 2533 2534 /****************************************************************************** 2535 * Get PHY information from various PHY registers fot m88 PHY only. 2536 * 2537 * hw - Struct containing variables accessed by shared code 2538 * phy_info - PHY information structure 2539 ******************************************************************************/ 2540 int32_t 2541 em_phy_m88_get_info(struct em_hw *hw, struct em_phy_info *phy_info) 2542 { 2543 uint16_t phy_data, polarity; 2544 2545 DEBUGFUNC("em_phy_m88_get_info"); 2546 2547 /* The downshift status is checked only once, after link is established, 2548 * and it stored in the hw->speed_downgraded parameter. */ 2549 phy_info->downshift = hw->speed_downgraded; 2550 2551 if(em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data) < 0) 2552 return -E1000_ERR_PHY; 2553 2554 phy_info->extended_10bt_distance = 2555 (phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >> 2556 M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT; 2557 phy_info->polarity_correction = 2558 (phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >> 2559 M88E1000_PSCR_POLARITY_REVERSAL_SHIFT; 2560 2561 /* Check polarity status */ 2562 if(em_check_polarity(hw, &polarity) < 0) 2563 return -E1000_ERR_PHY; 2564 2565 phy_info->cable_polarity = polarity; 2566 2567 if(em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) 2568 return -E1000_ERR_PHY; 2569 2570 phy_info->mdix_mode = (phy_data & M88E1000_PSSR_MDIX) >> 2571 M88E1000_PSSR_MDIX_SHIFT; 2572 2573 if(phy_data & M88E1000_PSSR_1000MBS) { 2574 /* Cable Length Estimation and Local/Remote Receiver Informatoion 2575 * are only valid at 1000 Mbps 2576 */ 2577 phy_info->cable_length = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 2578 M88E1000_PSSR_CABLE_LENGTH_SHIFT); 2579 2580 if(em_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data) < 0) 2581 return -E1000_ERR_PHY; 2582 2583 phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >> 2584 SR_1000T_LOCAL_RX_STATUS_SHIFT; 2585 2586 phy_info->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) >> 2587 SR_1000T_REMOTE_RX_STATUS_SHIFT; 2588 } 2589 2590 return E1000_SUCCESS; 2591 } 2592 2593 /****************************************************************************** 2594 * Get PHY information from various PHY registers 2595 * 2596 * hw - Struct containing variables accessed by shared code 2597 * phy_info - PHY information structure 2598 ******************************************************************************/ 2599 int32_t 2600 em_phy_get_info(struct em_hw *hw, 2601 struct em_phy_info *phy_info) 2602 { 2603 uint16_t phy_data; 2604 2605 DEBUGFUNC("em_phy_get_info"); 2606 2607 phy_info->cable_length = em_cable_length_undefined; 2608 phy_info->extended_10bt_distance = em_10bt_ext_dist_enable_undefined; 2609 phy_info->cable_polarity = em_rev_polarity_undefined; 2610 phy_info->downshift = em_downshift_undefined; 2611 phy_info->polarity_correction = em_polarity_reversal_undefined; 2612 phy_info->mdix_mode = em_auto_x_mode_undefined; 2613 phy_info->local_rx = em_1000t_rx_status_undefined; 2614 phy_info->remote_rx = em_1000t_rx_status_undefined; 2615 2616 if(hw->media_type != em_media_type_copper) { 2617 DEBUGOUT("PHY info is only valid for copper media\n"); 2618 return -E1000_ERR_CONFIG; 2619 } 2620 2621 if(em_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 2622 DEBUGOUT("PHY Read Error\n"); 2623 return -E1000_ERR_PHY; 2624 } 2625 if(em_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { 2626 DEBUGOUT("PHY Read Error\n"); 2627 return -E1000_ERR_PHY; 2628 } 2629 if((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) { 2630 DEBUGOUT("PHY info is only valid if link is up\n"); 2631 return -E1000_ERR_CONFIG; 2632 } 2633 2634 if (hw->phy_type == em_phy_igp) 2635 return em_phy_igp_get_info(hw, phy_info); 2636 else 2637 return em_phy_m88_get_info(hw, phy_info); 2638 } 2639 2640 int32_t 2641 em_validate_mdi_setting(struct em_hw *hw) 2642 { 2643 DEBUGFUNC("em_validate_mdi_settings"); 2644 2645 if(!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) { 2646 DEBUGOUT("Invalid MDI setting detected\n"); 2647 hw->mdix = 1; 2648 return -E1000_ERR_CONFIG; 2649 } 2650 return 0; 2651 } 2652 2653 2654 /****************************************************************************** 2655 * Sets up eeprom variables in the hw struct. Must be called after mac_type 2656 * is configured. 2657 * 2658 * hw - Struct containing variables accessed by shared code 2659 *****************************************************************************/ 2660 void 2661 em_init_eeprom_params(struct em_hw *hw) 2662 { 2663 struct em_eeprom_info *eeprom = &hw->eeprom; 2664 uint32_t eecd = E1000_READ_REG(hw, EECD); 2665 uint16_t eeprom_size; 2666 2667 DEBUGFUNC("em_init_eeprom_params"); 2668 2669 switch (hw->mac_type) { 2670 case em_82542_rev2_0: 2671 case em_82542_rev2_1: 2672 case em_82543: 2673 case em_82544: 2674 eeprom->type = em_eeprom_microwire; 2675 eeprom->word_size = 64; 2676 eeprom->opcode_bits = 3; 2677 eeprom->address_bits = 6; 2678 eeprom->delay_usec = 50; 2679 break; 2680 case em_82540: 2681 case em_82545: 2682 case em_82546: 2683 eeprom->type = em_eeprom_microwire; 2684 eeprom->opcode_bits = 3; 2685 eeprom->delay_usec = 50; 2686 if(eecd & E1000_EECD_SIZE) { 2687 eeprom->word_size = 256; 2688 eeprom->address_bits = 8; 2689 } else { 2690 eeprom->word_size = 64; 2691 eeprom->address_bits = 6; 2692 } 2693 break; 2694 case em_82541: 2695 case em_82547: 2696 default: 2697 if (eecd & E1000_EECD_TYPE) { 2698 eeprom->type = em_eeprom_spi; 2699 eeprom->opcode_bits = 8; 2700 eeprom->delay_usec = 1; 2701 if (eecd & E1000_EECD_ADDR_BITS) { 2702 eeprom->page_size = 32; 2703 eeprom->address_bits = 16; 2704 } else { 2705 eeprom->page_size = 8; 2706 eeprom->address_bits = 8; 2707 } 2708 } else { 2709 eeprom->type = em_eeprom_microwire; 2710 eeprom->opcode_bits = 3; 2711 eeprom->delay_usec = 50; 2712 if (eecd & E1000_EECD_ADDR_BITS) { 2713 eeprom->word_size = 256; 2714 eeprom->address_bits = 8; 2715 } else { 2716 eeprom->word_size = 64; 2717 eeprom->address_bits = 6; 2718 } 2719 } 2720 break; 2721 } 2722 2723 if (eeprom->type == em_eeprom_spi) { 2724 eeprom->word_size = 64; 2725 if (em_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size) == 0) { 2726 eeprom_size &= EEPROM_SIZE_MASK; 2727 2728 switch (eeprom_size) { 2729 case EEPROM_SIZE_16KB: 2730 eeprom->word_size = 8192; 2731 break; 2732 case EEPROM_SIZE_8KB: 2733 eeprom->word_size = 4096; 2734 break; 2735 case EEPROM_SIZE_4KB: 2736 eeprom->word_size = 2048; 2737 break; 2738 case EEPROM_SIZE_2KB: 2739 eeprom->word_size = 1024; 2740 break; 2741 case EEPROM_SIZE_1KB: 2742 eeprom->word_size = 512; 2743 break; 2744 case EEPROM_SIZE_512B: 2745 eeprom->word_size = 256; 2746 break; 2747 case EEPROM_SIZE_128B: 2748 default: 2749 eeprom->word_size = 64; 2750 break; 2751 } 2752 } 2753 } 2754 } 2755 2756 /****************************************************************************** 2757 * Raises the EEPROM's clock input. 2758 * 2759 * hw - Struct containing variables accessed by shared code 2760 * eecd - EECD's current value 2761 *****************************************************************************/ 2762 static void 2763 em_raise_ee_clk(struct em_hw *hw, 2764 uint32_t *eecd) 2765 { 2766 /* Raise the clock input to the EEPROM (by setting the SK bit), and then 2767 * wait <delay> microseconds. 2768 */ 2769 *eecd = *eecd | E1000_EECD_SK; 2770 E1000_WRITE_REG(hw, EECD, *eecd); 2771 E1000_WRITE_FLUSH(hw); 2772 usec_delay(hw->eeprom.delay_usec); 2773 } 2774 2775 /****************************************************************************** 2776 * Lowers the EEPROM's clock input. 2777 * 2778 * hw - Struct containing variables accessed by shared code 2779 * eecd - EECD's current value 2780 *****************************************************************************/ 2781 static void 2782 em_lower_ee_clk(struct em_hw *hw, 2783 uint32_t *eecd) 2784 { 2785 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then 2786 * wait 50 microseconds. 2787 */ 2788 *eecd = *eecd & ~E1000_EECD_SK; 2789 E1000_WRITE_REG(hw, EECD, *eecd); 2790 E1000_WRITE_FLUSH(hw); 2791 usec_delay(hw->eeprom.delay_usec); 2792 } 2793 2794 /****************************************************************************** 2795 * Shift data bits out to the EEPROM. 2796 * 2797 * hw - Struct containing variables accessed by shared code 2798 * data - data to send to the EEPROM 2799 * count - number of bits to shift out 2800 *****************************************************************************/ 2801 static void 2802 em_shift_out_ee_bits(struct em_hw *hw, 2803 uint16_t data, 2804 uint16_t count) 2805 { 2806 struct em_eeprom_info *eeprom = &hw->eeprom; 2807 uint32_t eecd; 2808 uint32_t mask; 2809 2810 /* We need to shift "count" bits out to the EEPROM. So, value in the 2811 * "data" parameter will be shifted out to the EEPROM one bit at a time. 2812 * In order to do this, "data" must be broken down into bits. 2813 */ 2814 mask = 0x01 << (count - 1); 2815 eecd = E1000_READ_REG(hw, EECD); 2816 if (eeprom->type == em_eeprom_microwire) { 2817 eecd &= ~E1000_EECD_DO; 2818 } else if (eeprom->type == em_eeprom_spi) { 2819 eecd |= E1000_EECD_DO; 2820 } 2821 do { 2822 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1", 2823 * and then raising and then lowering the clock (the SK bit controls 2824 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM 2825 * by setting "DI" to "0" and then raising and then lowering the clock. 2826 */ 2827 eecd &= ~E1000_EECD_DI; 2828 2829 if(data & mask) 2830 eecd |= E1000_EECD_DI; 2831 2832 E1000_WRITE_REG(hw, EECD, eecd); 2833 E1000_WRITE_FLUSH(hw); 2834 2835 usec_delay(eeprom->delay_usec); 2836 2837 em_raise_ee_clk(hw, &eecd); 2838 em_lower_ee_clk(hw, &eecd); 2839 2840 mask = mask >> 1; 2841 2842 } while(mask); 2843 2844 /* We leave the "DI" bit set to "0" when we leave this routine. */ 2845 eecd &= ~E1000_EECD_DI; 2846 E1000_WRITE_REG(hw, EECD, eecd); 2847 } 2848 2849 /****************************************************************************** 2850 * Shift data bits in from the EEPROM 2851 * 2852 * hw - Struct containing variables accessed by shared code 2853 *****************************************************************************/ 2854 static uint16_t 2855 em_shift_in_ee_bits(struct em_hw *hw, uint16_t count) 2856 { 2857 uint32_t eecd; 2858 uint32_t i; 2859 uint16_t data; 2860 2861 /* In order to read a register from the EEPROM, we need to shift 'count' 2862 * bits in from the EEPROM. Bits are "shifted in" by raising the clock 2863 * input to the EEPROM (setting the SK bit), and then reading the value of 2864 * the "DO" bit. During this "shifting in" process the "DI" bit should 2865 * always be clear. 2866 */ 2867 2868 eecd = E1000_READ_REG(hw, EECD); 2869 2870 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 2871 data = 0; 2872 2873 for(i = 0; i < count; i++) { 2874 data = data << 1; 2875 em_raise_ee_clk(hw, &eecd); 2876 2877 eecd = E1000_READ_REG(hw, EECD); 2878 2879 eecd &= ~(E1000_EECD_DI); 2880 if(eecd & E1000_EECD_DO) 2881 data |= 1; 2882 2883 em_lower_ee_clk(hw, &eecd); 2884 } 2885 2886 return data; 2887 } 2888 2889 /****************************************************************************** 2890 * Prepares EEPROM for access 2891 * 2892 * hw - Struct containing variables accessed by shared code 2893 * 2894 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This 2895 * function should be called before issuing a command to the EEPROM. 2896 *****************************************************************************/ 2897 static int32_t 2898 em_acquire_eeprom(struct em_hw *hw) 2899 { 2900 struct em_eeprom_info *eeprom = &hw->eeprom; 2901 uint32_t eecd, i=0; 2902 2903 DEBUGFUNC("em_acquire_eeprom"); 2904 2905 eecd = E1000_READ_REG(hw, EECD); 2906 2907 /* Request EEPROM Access */ 2908 if(hw->mac_type > em_82544) { 2909 eecd |= E1000_EECD_REQ; 2910 E1000_WRITE_REG(hw, EECD, eecd); 2911 eecd = E1000_READ_REG(hw, EECD); 2912 while((!(eecd & E1000_EECD_GNT)) && 2913 (i < E1000_EEPROM_GRANT_ATTEMPTS)) { 2914 i++; 2915 usec_delay(5); 2916 eecd = E1000_READ_REG(hw, EECD); 2917 } 2918 if(!(eecd & E1000_EECD_GNT)) { 2919 eecd &= ~E1000_EECD_REQ; 2920 E1000_WRITE_REG(hw, EECD, eecd); 2921 DEBUGOUT("Could not acquire EEPROM grant\n"); 2922 return -E1000_ERR_EEPROM; 2923 } 2924 } 2925 2926 /* Setup EEPROM for Read/Write */ 2927 2928 if (eeprom->type == em_eeprom_microwire) { 2929 /* Clear SK and DI */ 2930 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK); 2931 E1000_WRITE_REG(hw, EECD, eecd); 2932 2933 /* Set CS */ 2934 eecd |= E1000_EECD_CS; 2935 E1000_WRITE_REG(hw, EECD, eecd); 2936 } else if (eeprom->type == em_eeprom_spi) { 2937 /* Clear SK and CS */ 2938 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 2939 E1000_WRITE_REG(hw, EECD, eecd); 2940 usec_delay(1); 2941 } 2942 2943 return E1000_SUCCESS; 2944 } 2945 2946 /****************************************************************************** 2947 * Returns EEPROM to a "standby" state 2948 * 2949 * hw - Struct containing variables accessed by shared code 2950 *****************************************************************************/ 2951 static void 2952 em_standby_eeprom(struct em_hw *hw) 2953 { 2954 struct em_eeprom_info *eeprom = &hw->eeprom; 2955 uint32_t eecd; 2956 2957 eecd = E1000_READ_REG(hw, EECD); 2958 2959 if(eeprom->type == em_eeprom_microwire) { 2960 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 2961 E1000_WRITE_REG(hw, EECD, eecd); 2962 E1000_WRITE_FLUSH(hw); 2963 usec_delay(eeprom->delay_usec); 2964 2965 /* Clock high */ 2966 eecd |= E1000_EECD_SK; 2967 E1000_WRITE_REG(hw, EECD, eecd); 2968 E1000_WRITE_FLUSH(hw); 2969 usec_delay(eeprom->delay_usec); 2970 2971 /* Select EEPROM */ 2972 eecd |= E1000_EECD_CS; 2973 E1000_WRITE_REG(hw, EECD, eecd); 2974 E1000_WRITE_FLUSH(hw); 2975 usec_delay(eeprom->delay_usec); 2976 2977 /* Clock low */ 2978 eecd &= ~E1000_EECD_SK; 2979 E1000_WRITE_REG(hw, EECD, eecd); 2980 E1000_WRITE_FLUSH(hw); 2981 usec_delay(eeprom->delay_usec); 2982 } else if(eeprom->type == em_eeprom_spi) { 2983 /* Toggle CS to flush commands */ 2984 eecd |= E1000_EECD_CS; 2985 E1000_WRITE_REG(hw, EECD, eecd); 2986 E1000_WRITE_FLUSH(hw); 2987 usec_delay(eeprom->delay_usec); 2988 eecd &= ~E1000_EECD_CS; 2989 E1000_WRITE_REG(hw, EECD, eecd); 2990 E1000_WRITE_FLUSH(hw); 2991 usec_delay(eeprom->delay_usec); 2992 } 2993 } 2994 2995 /****************************************************************************** 2996 * Terminates a command by inverting the EEPROM's chip select pin 2997 * 2998 * hw - Struct containing variables accessed by shared code 2999 *****************************************************************************/ 3000 static void 3001 em_release_eeprom(struct em_hw *hw) 3002 { 3003 uint32_t eecd; 3004 3005 DEBUGFUNC("em_release_eeprom"); 3006 3007 eecd = E1000_READ_REG(hw, EECD); 3008 3009 if (hw->eeprom.type == em_eeprom_spi) { 3010 eecd |= E1000_EECD_CS; /* Pull CS high */ 3011 eecd &= ~E1000_EECD_SK; /* Lower SCK */ 3012 3013 E1000_WRITE_REG(hw, EECD, eecd); 3014 3015 usec_delay(hw->eeprom.delay_usec); 3016 } else if(hw->eeprom.type == em_eeprom_microwire) { 3017 /* cleanup eeprom */ 3018 3019 /* CS on Microwire is active-high */ 3020 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); 3021 3022 E1000_WRITE_REG(hw, EECD, eecd); 3023 3024 /* Rising edge of clock */ 3025 eecd |= E1000_EECD_SK; 3026 E1000_WRITE_REG(hw, EECD, eecd); 3027 E1000_WRITE_FLUSH(hw); 3028 usec_delay(hw->eeprom.delay_usec); 3029 3030 /* Falling edge of clock */ 3031 eecd &= ~E1000_EECD_SK; 3032 E1000_WRITE_REG(hw, EECD, eecd); 3033 E1000_WRITE_FLUSH(hw); 3034 usec_delay(hw->eeprom.delay_usec); 3035 } 3036 3037 /* Stop requesting EEPROM access */ 3038 if(hw->mac_type > em_82544) { 3039 eecd &= ~E1000_EECD_REQ; 3040 E1000_WRITE_REG(hw, EECD, eecd); 3041 } 3042 } 3043 3044 /****************************************************************************** 3045 * Reads a 16 bit word from the EEPROM. 3046 * 3047 * hw - Struct containing variables accessed by shared code 3048 *****************************************************************************/ 3049 int32_t 3050 em_spi_eeprom_ready(struct em_hw *hw) 3051 { 3052 uint16_t retry_count = 0; 3053 uint8_t spi_stat_reg; 3054 3055 DEBUGFUNC("em_spi_eeprom_ready"); 3056 3057 /* Read "Status Register" repeatedly until the LSB is cleared. The 3058 * EEPROM will signal that the command has been completed by clearing 3059 * bit 0 of the internal status register. If it's not cleared within 3060 * 5 milliseconds, then error out. 3061 */ 3062 retry_count = 0; 3063 do { 3064 em_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI, 3065 hw->eeprom.opcode_bits); 3066 spi_stat_reg = (uint8_t)em_shift_in_ee_bits(hw, 8); 3067 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI)) 3068 break; 3069 3070 usec_delay(5); 3071 retry_count += 5; 3072 3073 } while(retry_count < EEPROM_MAX_RETRY_SPI); 3074 3075 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and 3076 * only 0-5mSec on 5V devices) 3077 */ 3078 if(retry_count >= EEPROM_MAX_RETRY_SPI) { 3079 DEBUGOUT("SPI EEPROM Status error\n"); 3080 return -E1000_ERR_EEPROM; 3081 } 3082 3083 return E1000_SUCCESS; 3084 } 3085 3086 /****************************************************************************** 3087 * Reads a 16 bit word from the EEPROM. 3088 * 3089 * hw - Struct containing variables accessed by shared code 3090 * offset - offset of word in the EEPROM to read 3091 * data - word read from the EEPROM 3092 * words - number of words to read 3093 *****************************************************************************/ 3094 int32_t 3095 em_read_eeprom(struct em_hw *hw, 3096 uint16_t offset, 3097 uint16_t words, 3098 uint16_t *data) 3099 { 3100 struct em_eeprom_info *eeprom = &hw->eeprom; 3101 uint32_t i = 0; 3102 3103 DEBUGFUNC("em_read_eeprom"); 3104 3105 /* A check for invalid values: offset too large, too many words, and not 3106 * enough words. 3107 */ 3108 if((offset > eeprom->word_size) || (words > eeprom->word_size - offset) || 3109 (words == 0)) { 3110 DEBUGOUT("\"words\" parameter out of bounds\n"); 3111 return -E1000_ERR_EEPROM; 3112 } 3113 3114 /* Prepare the EEPROM for reading */ 3115 if (em_acquire_eeprom(hw) != E1000_SUCCESS) 3116 return -E1000_ERR_EEPROM; 3117 3118 if(eeprom->type == em_eeprom_spi) { 3119 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI; 3120 3121 if(em_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM; 3122 3123 em_standby_eeprom(hw); 3124 3125 /* Some SPI eeproms use the 8th address bit embedded in the opcode */ 3126 if((eeprom->address_bits == 8) && (offset >= 128)) 3127 read_opcode |= EEPROM_A8_OPCODE_SPI; 3128 3129 /* Send the READ command (opcode + addr) */ 3130 em_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits); 3131 em_shift_out_ee_bits(hw, (uint16_t)(offset*2), eeprom->address_bits); 3132 } 3133 else if(eeprom->type == em_eeprom_microwire) { 3134 /* Send the READ command (opcode + addr) */ 3135 em_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE, 3136 eeprom->opcode_bits); 3137 em_shift_out_ee_bits(hw, offset, eeprom->address_bits); 3138 } 3139 3140 /* Read the data. The address of the eeprom internally increments with 3141 * each word (microwire) or byte (spi) being read, saving on the overhead 3142 * of eeprom setup and tear-down. The address counter will roll over if 3143 * reading beyond the size of the eeprom, thus allowing the entire memory 3144 * to be read starting from any offset. */ 3145 for (i = 0; i < words; i++) { 3146 uint16_t word_in = em_shift_in_ee_bits(hw, 16); 3147 if (eeprom->type == em_eeprom_spi) 3148 word_in = (word_in >> 8) | (word_in << 8); 3149 data[i] = word_in; 3150 } 3151 3152 /* End this read operation */ 3153 em_release_eeprom(hw); 3154 3155 return 0; 3156 } 3157 3158 /****************************************************************************** 3159 * Verifies that the EEPROM has a valid checksum 3160 * 3161 * hw - Struct containing variables accessed by shared code 3162 * 3163 * Reads the first 64 16 bit words of the EEPROM and sums the values read. 3164 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is 3165 * valid. 3166 *****************************************************************************/ 3167 int32_t 3168 em_validate_eeprom_checksum(struct em_hw *hw) 3169 { 3170 uint16_t checksum = 0; 3171 uint16_t i, eeprom_data; 3172 3173 DEBUGFUNC("em_validate_eeprom_checksum"); 3174 3175 for(i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) { 3176 if(em_read_eeprom(hw, i, 1, &eeprom_data) < 0) { 3177 DEBUGOUT("EEPROM Read Error\n"); 3178 return -E1000_ERR_EEPROM; 3179 } 3180 checksum += eeprom_data; 3181 } 3182 3183 if(checksum == (uint16_t) EEPROM_SUM) { 3184 return 0; 3185 } else { 3186 DEBUGOUT("EEPROM Checksum Invalid\n"); 3187 return -E1000_ERR_EEPROM; 3188 } 3189 } 3190 3191 /****************************************************************************** 3192 * Calculates the EEPROM checksum and writes it to the EEPROM 3193 * 3194 * hw - Struct containing variables accessed by shared code 3195 * 3196 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA. 3197 * Writes the difference to word offset 63 of the EEPROM. 3198 *****************************************************************************/ 3199 int32_t 3200 em_update_eeprom_checksum(struct em_hw *hw) 3201 { 3202 uint16_t checksum = 0; 3203 uint16_t i, eeprom_data; 3204 3205 DEBUGFUNC("em_update_eeprom_checksum"); 3206 3207 for(i = 0; i < EEPROM_CHECKSUM_REG; i++) { 3208 if(em_read_eeprom(hw, i, 1, &eeprom_data) < 0) { 3209 DEBUGOUT("EEPROM Read Error\n"); 3210 return -E1000_ERR_EEPROM; 3211 } 3212 checksum += eeprom_data; 3213 } 3214 checksum = (uint16_t) EEPROM_SUM - checksum; 3215 if(em_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) { 3216 DEBUGOUT("EEPROM Write Error\n"); 3217 return -E1000_ERR_EEPROM; 3218 } 3219 return 0; 3220 } 3221 3222 /****************************************************************************** 3223 * Parent function for writing words to the different EEPROM types. 3224 * 3225 * hw - Struct containing variables accessed by shared code 3226 * offset - offset within the EEPROM to be written to 3227 * words - number of words to write 3228 * data - 16 bit word to be written to the EEPROM 3229 * 3230 * If em_update_eeprom_checksum is not called after this function, the 3231 * EEPROM will most likely contain an invalid checksum. 3232 *****************************************************************************/ 3233 int32_t 3234 em_write_eeprom(struct em_hw *hw, 3235 uint16_t offset, 3236 uint16_t words, 3237 uint16_t *data) 3238 { 3239 struct em_eeprom_info *eeprom = &hw->eeprom; 3240 int32_t status = 0; 3241 3242 DEBUGFUNC("em_write_eeprom"); 3243 3244 /* A check for invalid values: offset too large, too many words, and not 3245 * enough words. 3246 */ 3247 if((offset > eeprom->word_size) || (words > eeprom->word_size - offset) || 3248 (words == 0)) { 3249 DEBUGOUT("\"words\" parameter out of bounds\n"); 3250 return -E1000_ERR_EEPROM; 3251 } 3252 3253 /* Prepare the EEPROM for writing */ 3254 if (em_acquire_eeprom(hw) != E1000_SUCCESS) 3255 return -E1000_ERR_EEPROM; 3256 3257 if(eeprom->type == em_eeprom_microwire) 3258 status = em_write_eeprom_microwire(hw, offset, words, data); 3259 else 3260 status = em_write_eeprom_spi(hw, offset, words, data); 3261 3262 /* Done with writing */ 3263 em_release_eeprom(hw); 3264 3265 return status; 3266 } 3267 3268 /****************************************************************************** 3269 * Writes a 16 bit word to a given offset in an SPI EEPROM. 3270 * 3271 * hw - Struct containing variables accessed by shared code 3272 * offset - offset within the EEPROM to be written to 3273 * words - number of words to write 3274 * data - pointer to array of 8 bit words to be written to the EEPROM 3275 * 3276 *****************************************************************************/ 3277 int32_t 3278 em_write_eeprom_spi(struct em_hw *hw, 3279 uint16_t offset, 3280 uint16_t words, 3281 uint16_t *data) 3282 { 3283 struct em_eeprom_info *eeprom = &hw->eeprom; 3284 uint16_t widx = 0; 3285 3286 DEBUGFUNC("em_write_eeprom_spi"); 3287 3288 while (widx < words) { 3289 uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI; 3290 3291 if(em_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM; 3292 3293 em_standby_eeprom(hw); 3294 3295 /* Send the WRITE ENABLE command (8 bit opcode ) */ 3296 em_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI, 3297 eeprom->opcode_bits); 3298 3299 em_standby_eeprom(hw); 3300 3301 /* Some SPI eeproms use the 8th address bit embedded in the opcode */ 3302 if((eeprom->address_bits == 8) && (offset >= 128)) 3303 write_opcode |= EEPROM_A8_OPCODE_SPI; 3304 3305 /* Send the Write command (8-bit opcode + addr) */ 3306 em_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits); 3307 3308 em_shift_out_ee_bits(hw, (uint16_t)((offset + widx)*2), 3309 eeprom->address_bits); 3310 3311 /* Send the data */ 3312 3313 /* Loop to allow for up to whole page write (32 bytes) of eeprom */ 3314 while (widx < words) { 3315 uint16_t word_out = data[widx]; 3316 word_out = (word_out >> 8) | (word_out << 8); 3317 em_shift_out_ee_bits(hw, word_out, 16); 3318 widx++; 3319 3320 /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE 3321 * operation, while the smaller eeproms are capable of an 8-byte 3322 * PAGE WRITE operation. Break the inner loop to pass new address 3323 */ 3324 if((((offset + widx)*2) % eeprom->page_size) == 0) { 3325 em_standby_eeprom(hw); 3326 break; 3327 } 3328 } 3329 } 3330 3331 return E1000_SUCCESS; 3332 } 3333 3334 /****************************************************************************** 3335 * Writes a 16 bit word to a given offset in a Microwire EEPROM. 3336 * 3337 * hw - Struct containing variables accessed by shared code 3338 * offset - offset within the EEPROM to be written to 3339 * words - number of words to write 3340 * data - pointer to array of 16 bit words to be written to the EEPROM 3341 * 3342 *****************************************************************************/ 3343 int32_t 3344 em_write_eeprom_microwire(struct em_hw *hw, 3345 uint16_t offset, 3346 uint16_t words, 3347 uint16_t *data) 3348 { 3349 struct em_eeprom_info *eeprom = &hw->eeprom; 3350 uint32_t eecd; 3351 uint16_t words_written = 0; 3352 uint16_t i = 0; 3353 3354 DEBUGFUNC("em_write_eeprom_microwire"); 3355 3356 /* Send the write enable command to the EEPROM (3-bit opcode plus 3357 * 6/8-bit dummy address beginning with 11). It's less work to include 3358 * the 11 of the dummy address as part of the opcode than it is to shift 3359 * it over the correct number of bits for the address. This puts the 3360 * EEPROM into write/erase mode. 3361 */ 3362 em_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE, 3363 (uint16_t)(eeprom->opcode_bits + 2)); 3364 3365 em_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2)); 3366 3367 /* Prepare the EEPROM */ 3368 em_standby_eeprom(hw); 3369 3370 while (words_written < words) { 3371 /* Send the Write command (3-bit opcode + addr) */ 3372 em_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE, 3373 eeprom->opcode_bits); 3374 3375 em_shift_out_ee_bits(hw, (uint16_t)(offset + words_written), 3376 eeprom->address_bits); 3377 3378 /* Send the data */ 3379 em_shift_out_ee_bits(hw, data[words_written], 16); 3380 3381 /* Toggle the CS line. This in effect tells the EEPROM to execute 3382 * the previous command. 3383 */ 3384 em_standby_eeprom(hw); 3385 3386 /* Read DO repeatedly until it is high (equal to '1'). The EEPROM will 3387 * signal that the command has been completed by raising the DO signal. 3388 * If DO does not go high in 10 milliseconds, then error out. 3389 */ 3390 for(i = 0; i < 200; i++) { 3391 eecd = E1000_READ_REG(hw, EECD); 3392 if(eecd & E1000_EECD_DO) break; 3393 usec_delay(50); 3394 } 3395 if(i == 200) { 3396 DEBUGOUT("EEPROM Write did not complete\n"); 3397 return -E1000_ERR_EEPROM; 3398 } 3399 3400 /* Recover from write */ 3401 em_standby_eeprom(hw); 3402 3403 words_written++; 3404 } 3405 3406 /* Send the write disable command to the EEPROM (3-bit opcode plus 3407 * 6/8-bit dummy address beginning with 10). It's less work to include 3408 * the 10 of the dummy address as part of the opcode than it is to shift 3409 * it over the correct number of bits for the address. This takes the 3410 * EEPROM out of write/erase mode. 3411 */ 3412 em_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE, 3413 (uint16_t)(eeprom->opcode_bits + 2)); 3414 3415 em_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2)); 3416 3417 return 0; 3418 } 3419 3420 /****************************************************************************** 3421 * Reads the adapter's part number from the EEPROM 3422 * 3423 * hw - Struct containing variables accessed by shared code 3424 * part_num - Adapter's part number 3425 *****************************************************************************/ 3426 int32_t 3427 em_read_part_num(struct em_hw *hw, 3428 uint32_t *part_num) 3429 { 3430 uint16_t offset = EEPROM_PBA_BYTE_1; 3431 uint16_t eeprom_data; 3432 3433 DEBUGFUNC("em_read_part_num"); 3434 3435 /* Get word 0 from EEPROM */ 3436 if(em_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { 3437 DEBUGOUT("EEPROM Read Error\n"); 3438 return -E1000_ERR_EEPROM; 3439 } 3440 /* Save word 0 in upper half of part_num */ 3441 *part_num = (uint32_t) (eeprom_data << 16); 3442 3443 /* Get word 1 from EEPROM */ 3444 if(em_read_eeprom(hw, ++offset, 1, &eeprom_data) < 0) { 3445 DEBUGOUT("EEPROM Read Error\n"); 3446 return -E1000_ERR_EEPROM; 3447 } 3448 /* Save word 1 in lower half of part_num */ 3449 *part_num |= eeprom_data; 3450 3451 return 0; 3452 } 3453 3454 /****************************************************************************** 3455 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the 3456 * second function of dual function devices 3457 * 3458 * hw - Struct containing variables accessed by shared code 3459 *****************************************************************************/ 3460 int32_t 3461 em_read_mac_addr(struct em_hw * hw) 3462 { 3463 uint16_t offset; 3464 uint16_t eeprom_data, i; 3465 3466 DEBUGFUNC("em_read_mac_addr"); 3467 3468 for(i = 0; i < NODE_ADDRESS_SIZE; i += 2) { 3469 offset = i >> 1; 3470 if(em_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { 3471 DEBUGOUT("EEPROM Read Error\n"); 3472 return -E1000_ERR_EEPROM; 3473 } 3474 hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF); 3475 hw->perm_mac_addr[i+1] = (uint8_t) (eeprom_data >> 8); 3476 } 3477 if((hw->mac_type == em_82546) && 3478 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { 3479 if(hw->perm_mac_addr[5] & 0x01) 3480 hw->perm_mac_addr[5] &= ~(0x01); 3481 else 3482 hw->perm_mac_addr[5] |= 0x01; 3483 } 3484 for(i = 0; i < NODE_ADDRESS_SIZE; i++) 3485 hw->mac_addr[i] = hw->perm_mac_addr[i]; 3486 return 0; 3487 } 3488 3489 /****************************************************************************** 3490 * Initializes receive address filters. 3491 * 3492 * hw - Struct containing variables accessed by shared code 3493 * 3494 * Places the MAC address in receive address register 0 and clears the rest 3495 * of the receive addresss registers. Clears the multicast table. Assumes 3496 * the receiver is in reset when the routine is called. 3497 *****************************************************************************/ 3498 void 3499 em_init_rx_addrs(struct em_hw *hw) 3500 { 3501 uint32_t i; 3502 uint32_t addr_low; 3503 uint32_t addr_high; 3504 3505 DEBUGFUNC("em_init_rx_addrs"); 3506 3507 /* Setup the receive address. */ 3508 DEBUGOUT("Programming MAC Address into RAR[0]\n"); 3509 addr_low = (hw->mac_addr[0] | 3510 (hw->mac_addr[1] << 8) | 3511 (hw->mac_addr[2] << 16) | (hw->mac_addr[3] << 24)); 3512 3513 addr_high = (hw->mac_addr[4] | 3514 (hw->mac_addr[5] << 8) | E1000_RAH_AV); 3515 3516 E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low); 3517 E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high); 3518 3519 /* Zero out the other 15 receive addresses. */ 3520 DEBUGOUT("Clearing RAR[1-15]\n"); 3521 for(i = 1; i < E1000_RAR_ENTRIES; i++) { 3522 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 3523 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 3524 } 3525 } 3526 3527 /****************************************************************************** 3528 * Updates the MAC's list of multicast addresses. 3529 * 3530 * hw - Struct containing variables accessed by shared code 3531 * mc_addr_list - the list of new multicast addresses 3532 * mc_addr_count - number of addresses 3533 * pad - number of bytes between addresses in the list 3534 * 3535 * The given list replaces any existing list. Clears the last 15 receive 3536 * address registers and the multicast table. Uses receive address registers 3537 * for the first 15 multicast addresses, and hashes the rest into the 3538 * multicast table. 3539 *****************************************************************************/ 3540 void 3541 em_mc_addr_list_update(struct em_hw *hw, 3542 uint8_t *mc_addr_list, 3543 uint32_t mc_addr_count, 3544 uint32_t pad) 3545 { 3546 uint32_t hash_value; 3547 uint32_t i; 3548 uint32_t rar_used_count = 1; /* RAR[0] is used for our MAC address */ 3549 3550 DEBUGFUNC("em_mc_addr_list_update"); 3551 3552 /* Set the new number of MC addresses that we are being requested to use. */ 3553 hw->num_mc_addrs = mc_addr_count; 3554 3555 /* Clear RAR[1-15] */ 3556 DEBUGOUT(" Clearing RAR[1-15]\n"); 3557 for(i = rar_used_count; i < E1000_RAR_ENTRIES; i++) { 3558 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 3559 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 3560 } 3561 3562 /* Clear the MTA */ 3563 DEBUGOUT(" Clearing MTA\n"); 3564 for(i = 0; i < E1000_NUM_MTA_REGISTERS; i++) { 3565 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 3566 } 3567 3568 /* Add the new addresses */ 3569 for(i = 0; i < mc_addr_count; i++) { 3570 DEBUGOUT(" Adding the multicast addresses:\n"); 3571 DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i, 3572 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad)], 3573 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 1], 3574 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 2], 3575 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 3], 3576 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 4], 3577 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 5]); 3578 3579 hash_value = em_hash_mc_addr(hw, 3580 mc_addr_list + 3581 (i * (ETH_LENGTH_OF_ADDRESS + pad))); 3582 3583 DEBUGOUT1(" Hash value = 0x%03X\n", hash_value); 3584 3585 /* Place this multicast address in the RAR if there is room, * 3586 * else put it in the MTA 3587 */ 3588 if(rar_used_count < E1000_RAR_ENTRIES) { 3589 em_rar_set(hw, 3590 mc_addr_list + (i * (ETH_LENGTH_OF_ADDRESS + pad)), 3591 rar_used_count); 3592 rar_used_count++; 3593 } else { 3594 em_mta_set(hw, hash_value); 3595 } 3596 } 3597 DEBUGOUT("MC Update Complete\n"); 3598 } 3599 3600 /****************************************************************************** 3601 * Hashes an address to determine its location in the multicast table 3602 * 3603 * hw - Struct containing variables accessed by shared code 3604 * mc_addr - the multicast address to hash 3605 *****************************************************************************/ 3606 uint32_t 3607 em_hash_mc_addr(struct em_hw *hw, 3608 uint8_t *mc_addr) 3609 { 3610 uint32_t hash_value = 0; 3611 3612 /* The portion of the address that is used for the hash table is 3613 * determined by the mc_filter_type setting. 3614 */ 3615 switch (hw->mc_filter_type) { 3616 /* [0] [1] [2] [3] [4] [5] 3617 * 01 AA 00 12 34 56 3618 * LSB MSB 3619 */ 3620 case 0: 3621 /* [47:36] i.e. 0x563 for above example address */ 3622 hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4)); 3623 break; 3624 case 1: 3625 /* [46:35] i.e. 0xAC6 for above example address */ 3626 hash_value = ((mc_addr[4] >> 3) | (((uint16_t) mc_addr[5]) << 5)); 3627 break; 3628 case 2: 3629 /* [45:34] i.e. 0x5D8 for above example address */ 3630 hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6)); 3631 break; 3632 case 3: 3633 /* [43:32] i.e. 0x634 for above example address */ 3634 hash_value = ((mc_addr[4]) | (((uint16_t) mc_addr[5]) << 8)); 3635 break; 3636 } 3637 3638 hash_value &= 0xFFF; 3639 return hash_value; 3640 } 3641 3642 /****************************************************************************** 3643 * Sets the bit in the multicast table corresponding to the hash value. 3644 * 3645 * hw - Struct containing variables accessed by shared code 3646 * hash_value - Multicast address hash value 3647 *****************************************************************************/ 3648 void 3649 em_mta_set(struct em_hw *hw, 3650 uint32_t hash_value) 3651 { 3652 uint32_t hash_bit, hash_reg; 3653 uint32_t mta; 3654 uint32_t temp; 3655 3656 /* The MTA is a register array of 128 32-bit registers. 3657 * It is treated like an array of 4096 bits. We want to set 3658 * bit BitArray[hash_value]. So we figure out what register 3659 * the bit is in, read it, OR in the new bit, then write 3660 * back the new value. The register is determined by the 3661 * upper 7 bits of the hash value and the bit within that 3662 * register are determined by the lower 5 bits of the value. 3663 */ 3664 hash_reg = (hash_value >> 5) & 0x7F; 3665 hash_bit = hash_value & 0x1F; 3666 3667 mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg); 3668 3669 mta |= (1 << hash_bit); 3670 3671 /* If we are on an 82544 and we are trying to write an odd offset 3672 * in the MTA, save off the previous entry before writing and 3673 * restore the old value after writing. 3674 */ 3675 if((hw->mac_type == em_82544) && ((hash_reg & 0x1) == 1)) { 3676 temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1)); 3677 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta); 3678 E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp); 3679 } else { 3680 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta); 3681 } 3682 } 3683 3684 /****************************************************************************** 3685 * Puts an ethernet address into a receive address register. 3686 * 3687 * hw - Struct containing variables accessed by shared code 3688 * addr - Address to put into receive address register 3689 * index - Receive address register to write 3690 *****************************************************************************/ 3691 void 3692 em_rar_set(struct em_hw *hw, 3693 uint8_t *addr, 3694 uint32_t index) 3695 { 3696 uint32_t rar_low, rar_high; 3697 3698 /* HW expects these in little endian so we reverse the byte order 3699 * from network order (big endian) to little endian 3700 */ 3701 rar_low = ((uint32_t) addr[0] | 3702 ((uint32_t) addr[1] << 8) | 3703 ((uint32_t) addr[2] << 16) | ((uint32_t) addr[3] << 24)); 3704 3705 rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8) | E1000_RAH_AV); 3706 3707 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low); 3708 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high); 3709 } 3710 3711 /****************************************************************************** 3712 * Writes a value to the specified offset in the VLAN filter table. 3713 * 3714 * hw - Struct containing variables accessed by shared code 3715 * offset - Offset in VLAN filer table to write 3716 * value - Value to write into VLAN filter table 3717 *****************************************************************************/ 3718 void 3719 em_write_vfta(struct em_hw *hw, 3720 uint32_t offset, 3721 uint32_t value) 3722 { 3723 uint32_t temp; 3724 3725 if((hw->mac_type == em_82544) && ((offset & 0x1) == 1)) { 3726 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1)); 3727 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value); 3728 E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp); 3729 } else { 3730 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value); 3731 } 3732 } 3733 3734 /****************************************************************************** 3735 * Clears the VLAN filer table 3736 * 3737 * hw - Struct containing variables accessed by shared code 3738 *****************************************************************************/ 3739 void 3740 em_clear_vfta(struct em_hw *hw) 3741 { 3742 uint32_t offset; 3743 3744 for(offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) 3745 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0); 3746 } 3747 3748 static int32_t 3749 em_id_led_init(struct em_hw * hw) 3750 { 3751 uint32_t ledctl; 3752 const uint32_t ledctl_mask = 0x000000FF; 3753 const uint32_t ledctl_on = E1000_LEDCTL_MODE_LED_ON; 3754 const uint32_t ledctl_off = E1000_LEDCTL_MODE_LED_OFF; 3755 uint16_t eeprom_data, i, temp; 3756 const uint16_t led_mask = 0x0F; 3757 3758 DEBUGFUNC("em_id_led_init"); 3759 3760 if(hw->mac_type < em_82540) { 3761 /* Nothing to do */ 3762 return 0; 3763 } 3764 3765 ledctl = E1000_READ_REG(hw, LEDCTL); 3766 hw->ledctl_default = ledctl; 3767 hw->ledctl_mode1 = hw->ledctl_default; 3768 hw->ledctl_mode2 = hw->ledctl_default; 3769 3770 if(em_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) { 3771 DEBUGOUT("EEPROM Read Error\n"); 3772 return -E1000_ERR_EEPROM; 3773 } 3774 if((eeprom_data== ID_LED_RESERVED_0000) || 3775 (eeprom_data == ID_LED_RESERVED_FFFF)) eeprom_data = ID_LED_DEFAULT; 3776 for(i = 0; i < 4; i++) { 3777 temp = (eeprom_data >> (i << 2)) & led_mask; 3778 switch(temp) { 3779 case ID_LED_ON1_DEF2: 3780 case ID_LED_ON1_ON2: 3781 case ID_LED_ON1_OFF2: 3782 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 3783 hw->ledctl_mode1 |= ledctl_on << (i << 3); 3784 break; 3785 case ID_LED_OFF1_DEF2: 3786 case ID_LED_OFF1_ON2: 3787 case ID_LED_OFF1_OFF2: 3788 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 3789 hw->ledctl_mode1 |= ledctl_off << (i << 3); 3790 break; 3791 default: 3792 /* Do nothing */ 3793 break; 3794 } 3795 switch(temp) { 3796 case ID_LED_DEF1_ON2: 3797 case ID_LED_ON1_ON2: 3798 case ID_LED_OFF1_ON2: 3799 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 3800 hw->ledctl_mode2 |= ledctl_on << (i << 3); 3801 break; 3802 case ID_LED_DEF1_OFF2: 3803 case ID_LED_ON1_OFF2: 3804 case ID_LED_OFF1_OFF2: 3805 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 3806 hw->ledctl_mode2 |= ledctl_off << (i << 3); 3807 break; 3808 default: 3809 /* Do nothing */ 3810 break; 3811 } 3812 } 3813 return 0; 3814 } 3815 3816 /****************************************************************************** 3817 * Prepares SW controlable LED for use and saves the current state of the LED. 3818 * 3819 * hw - Struct containing variables accessed by shared code 3820 *****************************************************************************/ 3821 int32_t 3822 em_setup_led(struct em_hw *hw) 3823 { 3824 uint32_t ledctl; 3825 3826 DEBUGFUNC("em_setup_led"); 3827 3828 switch(hw->device_id) { 3829 case E1000_DEV_ID_82542: 3830 case E1000_DEV_ID_82543GC_FIBER: 3831 case E1000_DEV_ID_82543GC_COPPER: 3832 case E1000_DEV_ID_82544EI_COPPER: 3833 case E1000_DEV_ID_82544EI_FIBER: 3834 case E1000_DEV_ID_82544GC_COPPER: 3835 case E1000_DEV_ID_82544GC_LOM: 3836 /* No setup necessary */ 3837 break; 3838 case E1000_DEV_ID_82545EM_FIBER: 3839 case E1000_DEV_ID_82546EB_FIBER: 3840 ledctl = E1000_READ_REG(hw, LEDCTL); 3841 /* Save current LEDCTL settings */ 3842 hw->ledctl_default = ledctl; 3843 /* Turn off LED0 */ 3844 ledctl &= ~(E1000_LEDCTL_LED0_IVRT | 3845 E1000_LEDCTL_LED0_BLINK | 3846 E1000_LEDCTL_LED0_MODE_MASK); 3847 ledctl |= (E1000_LEDCTL_MODE_LED_OFF << E1000_LEDCTL_LED0_MODE_SHIFT); 3848 E1000_WRITE_REG(hw, LEDCTL, ledctl); 3849 break; 3850 case E1000_DEV_ID_82540EP: 3851 case E1000_DEV_ID_82540EP_LOM: 3852 case E1000_DEV_ID_82540EP_LP: 3853 case E1000_DEV_ID_82540EM: 3854 case E1000_DEV_ID_82540EM_LOM: 3855 case E1000_DEV_ID_82545EM_COPPER: 3856 case E1000_DEV_ID_82546EB_COPPER: 3857 case E1000_DEV_ID_82546EB_QUAD_COPPER: 3858 case E1000_DEV_ID_82541EI: 3859 case E1000_DEV_ID_82541EP: 3860 case E1000_DEV_ID_82547EI: 3861 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1); 3862 break; 3863 default: 3864 DEBUGOUT("Invalid device ID\n"); 3865 return -E1000_ERR_CONFIG; 3866 } 3867 return 0; 3868 } 3869 3870 /****************************************************************************** 3871 * Restores the saved state of the SW controlable LED. 3872 * 3873 * hw - Struct containing variables accessed by shared code 3874 *****************************************************************************/ 3875 int32_t 3876 em_cleanup_led(struct em_hw *hw) 3877 { 3878 DEBUGFUNC("em_cleanup_led"); 3879 3880 switch(hw->device_id) { 3881 case E1000_DEV_ID_82542: 3882 case E1000_DEV_ID_82543GC_FIBER: 3883 case E1000_DEV_ID_82543GC_COPPER: 3884 case E1000_DEV_ID_82544EI_COPPER: 3885 case E1000_DEV_ID_82544EI_FIBER: 3886 case E1000_DEV_ID_82544GC_COPPER: 3887 case E1000_DEV_ID_82544GC_LOM: 3888 /* No cleanup necessary */ 3889 break; 3890 case E1000_DEV_ID_82540EP: 3891 case E1000_DEV_ID_82540EP_LOM: 3892 case E1000_DEV_ID_82540EP_LP: 3893 case E1000_DEV_ID_82540EM: 3894 case E1000_DEV_ID_82540EM_LOM: 3895 case E1000_DEV_ID_82545EM_COPPER: 3896 case E1000_DEV_ID_82545EM_FIBER: 3897 case E1000_DEV_ID_82546EB_COPPER: 3898 case E1000_DEV_ID_82546EB_FIBER: 3899 case E1000_DEV_ID_82546EB_QUAD_COPPER: 3900 case E1000_DEV_ID_82541EI: 3901 case E1000_DEV_ID_82541EP: 3902 case E1000_DEV_ID_82547EI: 3903 /* Restore LEDCTL settings */ 3904 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_default); 3905 break; 3906 default: 3907 DEBUGOUT("Invalid device ID\n"); 3908 return -E1000_ERR_CONFIG; 3909 } 3910 return 0; 3911 } 3912 3913 /****************************************************************************** 3914 * Turns on the software controllable LED 3915 * 3916 * hw - Struct containing variables accessed by shared code 3917 *****************************************************************************/ 3918 int32_t 3919 em_led_on(struct em_hw *hw) 3920 { 3921 uint32_t ctrl; 3922 3923 DEBUGFUNC("em_led_on"); 3924 3925 switch(hw->device_id) { 3926 case E1000_DEV_ID_82542: 3927 case E1000_DEV_ID_82543GC_FIBER: 3928 case E1000_DEV_ID_82543GC_COPPER: 3929 case E1000_DEV_ID_82544EI_FIBER: 3930 ctrl = E1000_READ_REG(hw, CTRL); 3931 /* Set SW Defineable Pin 0 to turn on the LED */ 3932 ctrl |= E1000_CTRL_SWDPIN0; 3933 ctrl |= E1000_CTRL_SWDPIO0; 3934 E1000_WRITE_REG(hw, CTRL, ctrl); 3935 break; 3936 case E1000_DEV_ID_82544EI_COPPER: 3937 case E1000_DEV_ID_82544GC_COPPER: 3938 case E1000_DEV_ID_82544GC_LOM: 3939 case E1000_DEV_ID_82545EM_FIBER: 3940 case E1000_DEV_ID_82546EB_FIBER: 3941 ctrl = E1000_READ_REG(hw, CTRL); 3942 /* Clear SW Defineable Pin 0 to turn on the LED */ 3943 ctrl &= ~E1000_CTRL_SWDPIN0; 3944 ctrl |= E1000_CTRL_SWDPIO0; 3945 E1000_WRITE_REG(hw, CTRL, ctrl); 3946 break; 3947 case E1000_DEV_ID_82540EP: 3948 case E1000_DEV_ID_82540EP_LOM: 3949 case E1000_DEV_ID_82540EP_LP: 3950 case E1000_DEV_ID_82540EM: 3951 case E1000_DEV_ID_82540EM_LOM: 3952 case E1000_DEV_ID_82545EM_COPPER: 3953 case E1000_DEV_ID_82546EB_COPPER: 3954 case E1000_DEV_ID_82546EB_QUAD_COPPER: 3955 case E1000_DEV_ID_82541EI: 3956 case E1000_DEV_ID_82541EP: 3957 case E1000_DEV_ID_82547EI: 3958 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode2); 3959 break; 3960 default: 3961 DEBUGOUT("Invalid device ID\n"); 3962 return -E1000_ERR_CONFIG; 3963 } 3964 return 0; 3965 } 3966 3967 /****************************************************************************** 3968 * Turns off the software controllable LED 3969 * 3970 * hw - Struct containing variables accessed by shared code 3971 *****************************************************************************/ 3972 int32_t 3973 em_led_off(struct em_hw *hw) 3974 { 3975 uint32_t ctrl; 3976 3977 DEBUGFUNC("em_led_off"); 3978 3979 switch(hw->device_id) { 3980 case E1000_DEV_ID_82542: 3981 case E1000_DEV_ID_82543GC_FIBER: 3982 case E1000_DEV_ID_82543GC_COPPER: 3983 case E1000_DEV_ID_82544EI_FIBER: 3984 ctrl = E1000_READ_REG(hw, CTRL); 3985 /* Clear SW Defineable Pin 0 to turn off the LED */ 3986 ctrl &= ~E1000_CTRL_SWDPIN0; 3987 ctrl |= E1000_CTRL_SWDPIO0; 3988 E1000_WRITE_REG(hw, CTRL, ctrl); 3989 break; 3990 case E1000_DEV_ID_82544EI_COPPER: 3991 case E1000_DEV_ID_82544GC_COPPER: 3992 case E1000_DEV_ID_82544GC_LOM: 3993 case E1000_DEV_ID_82545EM_FIBER: 3994 case E1000_DEV_ID_82546EB_FIBER: 3995 ctrl = E1000_READ_REG(hw, CTRL); 3996 /* Set SW Defineable Pin 0 to turn off the LED */ 3997 ctrl |= E1000_CTRL_SWDPIN0; 3998 ctrl |= E1000_CTRL_SWDPIO0; 3999 E1000_WRITE_REG(hw, CTRL, ctrl); 4000 break; 4001 case E1000_DEV_ID_82540EP: 4002 case E1000_DEV_ID_82540EP_LOM: 4003 case E1000_DEV_ID_82540EP_LP: 4004 case E1000_DEV_ID_82540EM: 4005 case E1000_DEV_ID_82540EM_LOM: 4006 case E1000_DEV_ID_82545EM_COPPER: 4007 case E1000_DEV_ID_82546EB_COPPER: 4008 case E1000_DEV_ID_82546EB_QUAD_COPPER: 4009 case E1000_DEV_ID_82541EI: 4010 case E1000_DEV_ID_82541EP: 4011 case E1000_DEV_ID_82547EI: 4012 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1); 4013 break; 4014 default: 4015 DEBUGOUT("Invalid device ID\n"); 4016 return -E1000_ERR_CONFIG; 4017 } 4018 return 0; 4019 } 4020 4021 /****************************************************************************** 4022 * Clears all hardware statistics counters. 4023 * 4024 * hw - Struct containing variables accessed by shared code 4025 *****************************************************************************/ 4026 void 4027 em_clear_hw_cntrs(struct em_hw *hw) 4028 { 4029 volatile uint32_t temp; 4030 4031 temp = E1000_READ_REG(hw, CRCERRS); 4032 temp = E1000_READ_REG(hw, SYMERRS); 4033 temp = E1000_READ_REG(hw, MPC); 4034 temp = E1000_READ_REG(hw, SCC); 4035 temp = E1000_READ_REG(hw, ECOL); 4036 temp = E1000_READ_REG(hw, MCC); 4037 temp = E1000_READ_REG(hw, LATECOL); 4038 temp = E1000_READ_REG(hw, COLC); 4039 temp = E1000_READ_REG(hw, DC); 4040 temp = E1000_READ_REG(hw, SEC); 4041 temp = E1000_READ_REG(hw, RLEC); 4042 temp = E1000_READ_REG(hw, XONRXC); 4043 temp = E1000_READ_REG(hw, XONTXC); 4044 temp = E1000_READ_REG(hw, XOFFRXC); 4045 temp = E1000_READ_REG(hw, XOFFTXC); 4046 temp = E1000_READ_REG(hw, FCRUC); 4047 temp = E1000_READ_REG(hw, PRC64); 4048 temp = E1000_READ_REG(hw, PRC127); 4049 temp = E1000_READ_REG(hw, PRC255); 4050 temp = E1000_READ_REG(hw, PRC511); 4051 temp = E1000_READ_REG(hw, PRC1023); 4052 temp = E1000_READ_REG(hw, PRC1522); 4053 temp = E1000_READ_REG(hw, GPRC); 4054 temp = E1000_READ_REG(hw, BPRC); 4055 temp = E1000_READ_REG(hw, MPRC); 4056 temp = E1000_READ_REG(hw, GPTC); 4057 temp = E1000_READ_REG(hw, GORCL); 4058 temp = E1000_READ_REG(hw, GORCH); 4059 temp = E1000_READ_REG(hw, GOTCL); 4060 temp = E1000_READ_REG(hw, GOTCH); 4061 temp = E1000_READ_REG(hw, RNBC); 4062 temp = E1000_READ_REG(hw, RUC); 4063 temp = E1000_READ_REG(hw, RFC); 4064 temp = E1000_READ_REG(hw, ROC); 4065 temp = E1000_READ_REG(hw, RJC); 4066 temp = E1000_READ_REG(hw, TORL); 4067 temp = E1000_READ_REG(hw, TORH); 4068 temp = E1000_READ_REG(hw, TOTL); 4069 temp = E1000_READ_REG(hw, TOTH); 4070 temp = E1000_READ_REG(hw, TPR); 4071 temp = E1000_READ_REG(hw, TPT); 4072 temp = E1000_READ_REG(hw, PTC64); 4073 temp = E1000_READ_REG(hw, PTC127); 4074 temp = E1000_READ_REG(hw, PTC255); 4075 temp = E1000_READ_REG(hw, PTC511); 4076 temp = E1000_READ_REG(hw, PTC1023); 4077 temp = E1000_READ_REG(hw, PTC1522); 4078 temp = E1000_READ_REG(hw, MPTC); 4079 temp = E1000_READ_REG(hw, BPTC); 4080 4081 if(hw->mac_type < em_82543) return; 4082 4083 temp = E1000_READ_REG(hw, ALGNERRC); 4084 temp = E1000_READ_REG(hw, RXERRC); 4085 temp = E1000_READ_REG(hw, TNCRS); 4086 temp = E1000_READ_REG(hw, CEXTERR); 4087 temp = E1000_READ_REG(hw, TSCTC); 4088 temp = E1000_READ_REG(hw, TSCTFC); 4089 4090 if(hw->mac_type <= em_82544) return; 4091 4092 temp = E1000_READ_REG(hw, MGTPRC); 4093 temp = E1000_READ_REG(hw, MGTPDC); 4094 temp = E1000_READ_REG(hw, MGTPTC); 4095 } 4096 4097 /****************************************************************************** 4098 * Resets Adaptive IFS to its default state. 4099 * 4100 * hw - Struct containing variables accessed by shared code 4101 * 4102 * Call this after em_init_hw. You may override the IFS defaults by setting 4103 * hw->ifs_params_forced to TRUE. However, you must initialize hw-> 4104 * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio 4105 * before calling this function. 4106 *****************************************************************************/ 4107 void 4108 em_reset_adaptive(struct em_hw *hw) 4109 { 4110 DEBUGFUNC("em_reset_adaptive"); 4111 4112 if(hw->adaptive_ifs) { 4113 if(!hw->ifs_params_forced) { 4114 hw->current_ifs_val = 0; 4115 hw->ifs_min_val = IFS_MIN; 4116 hw->ifs_max_val = IFS_MAX; 4117 hw->ifs_step_size = IFS_STEP; 4118 hw->ifs_ratio = IFS_RATIO; 4119 } 4120 hw->in_ifs_mode = FALSE; 4121 E1000_WRITE_REG(hw, AIT, 0); 4122 } else { 4123 DEBUGOUT("Not in Adaptive IFS mode!\n"); 4124 } 4125 } 4126 4127 /****************************************************************************** 4128 * Called during the callback/watchdog routine to update IFS value based on 4129 * the ratio of transmits to collisions. 4130 * 4131 * hw - Struct containing variables accessed by shared code 4132 * tx_packets - Number of transmits since last callback 4133 * total_collisions - Number of collisions since last callback 4134 *****************************************************************************/ 4135 void 4136 em_update_adaptive(struct em_hw *hw) 4137 { 4138 DEBUGFUNC("em_update_adaptive"); 4139 4140 if(hw->adaptive_ifs) { 4141 if((hw->collision_delta * hw->ifs_ratio) > 4142 hw->tx_packet_delta) { 4143 if(hw->tx_packet_delta > MIN_NUM_XMITS) { 4144 hw->in_ifs_mode = TRUE; 4145 if(hw->current_ifs_val < hw->ifs_max_val) { 4146 if(hw->current_ifs_val == 0) 4147 hw->current_ifs_val = hw->ifs_min_val; 4148 else 4149 hw->current_ifs_val += hw->ifs_step_size; 4150 E1000_WRITE_REG(hw, AIT, hw->current_ifs_val); 4151 } 4152 } 4153 } else { 4154 if((hw->in_ifs_mode == TRUE) && 4155 (hw->tx_packet_delta <= MIN_NUM_XMITS)) { 4156 hw->current_ifs_val = 0; 4157 hw->in_ifs_mode = FALSE; 4158 E1000_WRITE_REG(hw, AIT, 0); 4159 } 4160 } 4161 } else { 4162 DEBUGOUT("Not in Adaptive IFS mode!\n"); 4163 } 4164 } 4165 4166 /****************************************************************************** 4167 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT 4168 * 4169 * hw - Struct containing variables accessed by shared code 4170 * frame_len - The length of the frame in question 4171 * mac_addr - The Ethernet destination address of the frame in question 4172 *****************************************************************************/ 4173 void 4174 em_tbi_adjust_stats(struct em_hw *hw, 4175 struct em_hw_stats *stats, 4176 uint32_t frame_len, 4177 uint8_t *mac_addr) 4178 { 4179 uint64_t carry_bit; 4180 4181 /* First adjust the frame length. */ 4182 frame_len--; 4183 /* We need to adjust the statistics counters, since the hardware 4184 * counters overcount this packet as a CRC error and undercount 4185 * the packet as a good packet 4186 */ 4187 /* This packet should not be counted as a CRC error. */ 4188 stats->crcerrs--; 4189 /* This packet does count as a Good Packet Received. */ 4190 stats->gprc++; 4191 4192 /* Adjust the Good Octets received counters */ 4193 carry_bit = 0x80000000 & stats->gorcl; 4194 stats->gorcl += frame_len; 4195 /* If the high bit of Gorcl (the low 32 bits of the Good Octets 4196 * Received Count) was one before the addition, 4197 * AND it is zero after, then we lost the carry out, 4198 * need to add one to Gorch (Good Octets Received Count High). 4199 * This could be simplified if all environments supported 4200 * 64-bit integers. 4201 */ 4202 if(carry_bit && ((stats->gorcl & 0x80000000) == 0)) 4203 stats->gorch++; 4204 /* Is this a broadcast or multicast? Check broadcast first, 4205 * since the test for a multicast frame will test positive on 4206 * a broadcast frame. 4207 */ 4208 if((mac_addr[0] == (uint8_t) 0xff) && (mac_addr[1] == (uint8_t) 0xff)) 4209 /* Broadcast packet */ 4210 stats->bprc++; 4211 else if(*mac_addr & 0x01) 4212 /* Multicast packet */ 4213 stats->mprc++; 4214 4215 if(frame_len == hw->max_frame_size) { 4216 /* In this case, the hardware has overcounted the number of 4217 * oversize frames. 4218 */ 4219 if(stats->roc > 0) 4220 stats->roc--; 4221 } 4222 4223 /* Adjust the bin counters when the extra byte put the frame in the 4224 * wrong bin. Remember that the frame_len was adjusted above. 4225 */ 4226 if(frame_len == 64) { 4227 stats->prc64++; 4228 stats->prc127--; 4229 } else if(frame_len == 127) { 4230 stats->prc127++; 4231 stats->prc255--; 4232 } else if(frame_len == 255) { 4233 stats->prc255++; 4234 stats->prc511--; 4235 } else if(frame_len == 511) { 4236 stats->prc511++; 4237 stats->prc1023--; 4238 } else if(frame_len == 1023) { 4239 stats->prc1023++; 4240 stats->prc1522--; 4241 } else if(frame_len == 1522) { 4242 stats->prc1522++; 4243 } 4244 } 4245 4246 /****************************************************************************** 4247 * Gets the current PCI bus type, speed, and width of the hardware 4248 * 4249 * hw - Struct containing variables accessed by shared code 4250 *****************************************************************************/ 4251 void 4252 em_get_bus_info(struct em_hw *hw) 4253 { 4254 uint32_t status; 4255 4256 if(hw->mac_type < em_82543) { 4257 hw->bus_type = em_bus_type_unknown; 4258 hw->bus_speed = em_bus_speed_unknown; 4259 hw->bus_width = em_bus_width_unknown; 4260 return; 4261 } 4262 4263 status = E1000_READ_REG(hw, STATUS); 4264 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ? 4265 em_bus_type_pcix : em_bus_type_pci; 4266 4267 if(hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) { 4268 hw->bus_speed = (hw->bus_type == em_bus_type_pci) ? 4269 em_bus_speed_66 : em_bus_speed_120; 4270 } else if(hw->bus_type == em_bus_type_pci) { 4271 hw->bus_speed = (status & E1000_STATUS_PCI66) ? 4272 em_bus_speed_66 : em_bus_speed_33; 4273 } else { 4274 switch (status & E1000_STATUS_PCIX_SPEED) { 4275 case E1000_STATUS_PCIX_SPEED_66: 4276 hw->bus_speed = em_bus_speed_66; 4277 break; 4278 case E1000_STATUS_PCIX_SPEED_100: 4279 hw->bus_speed = em_bus_speed_100; 4280 break; 4281 case E1000_STATUS_PCIX_SPEED_133: 4282 hw->bus_speed = em_bus_speed_133; 4283 break; 4284 default: 4285 hw->bus_speed = em_bus_speed_reserved; 4286 break; 4287 } 4288 } 4289 hw->bus_width = (status & E1000_STATUS_BUS64) ? 4290 em_bus_width_64 : em_bus_width_32; 4291 } 4292 /****************************************************************************** 4293 * Reads a value from one of the devices registers using port I/O (as opposed 4294 * memory mapped I/O). Only 82544 and newer devices support port I/O. 4295 * 4296 * hw - Struct containing variables accessed by shared code 4297 * offset - offset to read from 4298 *****************************************************************************/ 4299 uint32_t 4300 em_read_reg_io(struct em_hw *hw, 4301 uint32_t offset) 4302 { 4303 uint32_t io_addr = hw->io_base; 4304 uint32_t io_data = hw->io_base + 4; 4305 4306 em_io_write(hw, io_addr, offset); 4307 return em_io_read(hw, io_data); 4308 } 4309 4310 /****************************************************************************** 4311 * Writes a value to one of the devices registers using port I/O (as opposed to 4312 * memory mapped I/O). Only 82544 and newer devices support port I/O. 4313 * 4314 * hw - Struct containing variables accessed by shared code 4315 * offset - offset to write to 4316 * value - value to write 4317 *****************************************************************************/ 4318 void 4319 em_write_reg_io(struct em_hw *hw, 4320 uint32_t offset, 4321 uint32_t value) 4322 { 4323 uint32_t io_addr = hw->io_base; 4324 uint32_t io_data = hw->io_base + 4; 4325 4326 em_io_write(hw, io_addr, offset); 4327 em_io_write(hw, io_data, value); 4328 } 4329 4330 4331 /****************************************************************************** 4332 * Estimates the cable length. 4333 * 4334 * hw - Struct containing variables accessed by shared code 4335 * min_length - The estimated minimum length 4336 * max_length - The estimated maximum length 4337 * 4338 * returns: E1000_SUCCESS / -E1000_ERR_XXX 4339 * 4340 * This function always returns a ranged length (minimum & maximum). 4341 * So for M88 phy's, this function interprets the one value returned from the 4342 * register to the minimum and maximum range. 4343 * For IGP phy's, the function calculates the range by the AGC registers. 4344 *****************************************************************************/ 4345 int32_t 4346 em_get_cable_length(struct em_hw *hw, uint16_t *min_length, 4347 uint16_t *max_length) 4348 { 4349 uint16_t agc_value = 0; 4350 uint16_t cur_agc, min_agc = IGP01E1000_AGC_LENGTH_TABLE_SIZE; 4351 uint16_t i, phy_data; 4352 4353 DEBUGFUNC("em_get_cable_length"); 4354 4355 *min_length = *max_length = 0; 4356 4357 /* Use old method for Phy older than IGP */ 4358 if(hw->phy_type == em_phy_m88) { 4359 if(em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) 4360 return -E1000_ERR_PHY; 4361 4362 /* Convert the enum value to ranged values */ 4363 switch((phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 4364 M88E1000_PSSR_CABLE_LENGTH_SHIFT) { 4365 case em_cable_length_50: 4366 *min_length = 0; 4367 *max_length = em_igp_cable_length_50; 4368 break; 4369 case em_cable_length_50_80: 4370 *min_length = em_igp_cable_length_50; 4371 *max_length = em_igp_cable_length_80; 4372 break; 4373 case em_cable_length_80_110: 4374 *min_length = em_igp_cable_length_80; 4375 *max_length = em_igp_cable_length_110; 4376 break; 4377 case em_cable_length_110_140: 4378 *min_length = em_igp_cable_length_110; 4379 *max_length = em_igp_cable_length_140; 4380 break; 4381 case em_cable_length_140: 4382 *min_length = em_igp_cable_length_140; 4383 *max_length = em_igp_cable_length_170; 4384 break; 4385 default: 4386 return -E1000_ERR_PHY; 4387 break; 4388 } 4389 } else if(hw->phy_type == em_phy_igp) { /* For IGP PHY */ 4390 uint16_t agc_reg_array[IGP01E1000_PHY_AGC_NUM] = {IGP01E1000_PHY_AGC_A, 4391 IGP01E1000_PHY_AGC_B, 4392 IGP01E1000_PHY_AGC_C, 4393 IGP01E1000_PHY_AGC_D}; 4394 /* Read the AGC registers for all channels */ 4395 for(i = 0; i < IGP01E1000_PHY_AGC_NUM; i++) { 4396 if(em_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT, 4397 agc_reg_array[i]) != E1000_SUCCESS) 4398 return -E1000_ERR_PHY; 4399 if(em_read_phy_reg(hw, agc_reg_array[i] & 4400 IGP01E1000_PHY_PAGE_SELECT, &phy_data) != 4401 E1000_SUCCESS) 4402 return -E1000_ERR_PHY; 4403 4404 cur_agc = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT; 4405 4406 /* Array bound check. */ 4407 if((cur_agc >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) || 4408 (cur_agc == 0)) 4409 return -E1000_ERR_PHY; 4410 4411 agc_value += cur_agc; 4412 4413 /* Update minimal AGC value. */ 4414 if(min_agc > cur_agc) 4415 min_agc = cur_agc; 4416 } 4417 4418 /* Return to page 0 */ 4419 if(em_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT, 0x0) != 4420 E1000_SUCCESS) 4421 return -E1000_ERR_PHY; 4422 4423 /* Remove the minimal AGC result for length < 50m */ 4424 if(agc_value < IGP01E1000_PHY_AGC_NUM * em_igp_cable_length_50) { 4425 agc_value -= min_agc; 4426 4427 /* Get the average length of the remaining 3 channels */ 4428 agc_value /= (IGP01E1000_PHY_AGC_NUM - 1); 4429 } else { 4430 /* Get the average length of all the 4 channels. */ 4431 agc_value /= IGP01E1000_PHY_AGC_NUM; 4432 } 4433 4434 /* Set the range of the calculated length. */ 4435 *min_length = ((em_igp_cable_length_table[agc_value] - 4436 IGP01E1000_AGC_RANGE) > 0) ? 4437 (em_igp_cable_length_table[agc_value] - 4438 IGP01E1000_AGC_RANGE) : 0; 4439 *max_length = em_igp_cable_length_table[agc_value] + 4440 IGP01E1000_AGC_RANGE; 4441 } 4442 4443 return E1000_SUCCESS; 4444 } 4445 4446 /****************************************************************************** 4447 * Check the cable polarity 4448 * 4449 * hw - Struct containing variables accessed by shared code 4450 * polarity - output parameter : 0 - Polarity is not reversed 4451 * 1 - Polarity is reversed. 4452 * 4453 * returns: E1000_SUCCESS / -E1000_ERR_XXX 4454 * 4455 * For phy's older then IGP, this function simply reads the polarity bit in the 4456 * Phy Status register. For IGP phy's, this bit is valid only if link speed is 4457 * 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will 4458 * return 0. If the link speed is 1000 Mbps the polarity status is in the 4459 * IGP01E1000_PHY_PCS_INIT_REG. 4460 *****************************************************************************/ 4461 int32_t 4462 em_check_polarity(struct em_hw *hw, uint16_t *polarity) 4463 { 4464 uint16_t phy_data; 4465 4466 DEBUGFUNC("em_check_polarity"); 4467 4468 if(hw->phy_type == em_phy_m88) { 4469 /* return the Polarity bit in the Status register. */ 4470 if(em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) 4471 return -E1000_ERR_PHY; 4472 *polarity = (phy_data & M88E1000_PSSR_REV_POLARITY) >> 4473 M88E1000_PSSR_REV_POLARITY_SHIFT; 4474 } else if(hw->phy_type == em_phy_igp) { 4475 /* Read the Status register to check the speed */ 4476 if(em_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data) < 0) 4477 return -E1000_ERR_PHY; 4478 4479 /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to 4480 * find the polarity status */ 4481 if((phy_data & IGP01E1000_PSSR_SPEED_MASK) == 4482 IGP01E1000_PSSR_SPEED_1000MBPS) { 4483 4484 /* Read the GIG initialization PCS register (0x00B4) */ 4485 if(em_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT, 4486 IGP01E1000_PHY_PCS_INIT_REG) < 0) 4487 return -E1000_ERR_PHY; 4488 4489 if(em_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG & 4490 IGP01E1000_PHY_PAGE_SELECT, &phy_data) < 0) 4491 return -E1000_ERR_PHY; 4492 4493 /* Return to page 0 */ 4494 if(em_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT, 0x0) != 4495 E1000_SUCCESS) 4496 return -E1000_ERR_PHY; 4497 4498 /* Check the polarity bits */ 4499 *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ? 1 : 0; 4500 } else { 4501 /* For 10 Mbps, read the polarity bit in the status register. (for 4502 * 100 Mbps this bit is always 0) */ 4503 *polarity = phy_data & IGP01E1000_PSSR_POLARITY_REVERSED; 4504 } 4505 } 4506 return E1000_SUCCESS; 4507 } 4508 4509 /****************************************************************************** 4510 * Check if Downshift occured 4511 * 4512 * hw - Struct containing variables accessed by shared code 4513 * downshift - output parameter : 0 - No Downshift ocured. 4514 * 1 - Downshift ocured. 4515 * 4516 * returns: E1000_SUCCESS / -E1000_ERR_XXX 4517 * 4518 * For phy's older then IGP, this function reads the Downshift bit in the Phy 4519 * Specific Status register. For IGP phy's, it reads the Downgrade bit in the 4520 * Link Health register. In IGP this bit is latched high, so the driver must 4521 * read it immediately after link is established. 4522 *****************************************************************************/ 4523 int32_t 4524 em_check_downshift(struct em_hw *hw) 4525 { 4526 uint16_t phy_data; 4527 4528 DEBUGFUNC("em_check_downshift"); 4529 4530 if(hw->phy_type == em_phy_igp) { 4531 if(em_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH, &phy_data) < 0) { 4532 DEBUGOUT("PHY Read Error\n"); 4533 return -E1000_ERR_PHY; 4534 } 4535 hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0; 4536 } 4537 else if(hw->phy_type == em_phy_m88) { 4538 if(em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) { 4539 DEBUGOUT("PHY Read Error\n"); 4540 return -E1000_ERR_PHY; 4541 } 4542 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >> 4543 M88E1000_PSSR_DOWNSHIFT_SHIFT; 4544 } 4545 return E1000_SUCCESS; 4546 } 4547 4548