1 /******************************************************************************* 2 3 Copyright (c) 2001-2005, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 *******************************************************************************/ 33 34 /* $OpenBSD: if_em_hw.c,v 1.65 2011/05/02 18:16:58 dhill Exp $ */ 35 /* 36 * if_em_hw.c Shared functions for accessing and configuring the MAC 37 */ 38 39 #if 0 40 #include <sys/cdefs.h> 41 __FBSDID("$FreeBSD: if_em_hw.c,v 1.16 2005/05/26 23:32:02 tackerman Exp $"); 42 #endif 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/sockio.h> 47 #include <sys/mbuf.h> 48 #include <sys/malloc.h> 49 #include <sys/kernel.h> 50 #include <sys/device.h> 51 #include <sys/socket.h> 52 53 #include <net/if.h> 54 #include <net/if_dl.h> 55 #include <net/if_media.h> 56 57 #ifdef INET 58 #include <netinet/in.h> 59 #include <netinet/in_systm.h> 60 #include <netinet/in_var.h> 61 #include <netinet/ip.h> 62 #include <netinet/if_ether.h> 63 #endif 64 65 #include <uvm/uvm_extern.h> 66 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pcivar.h> 69 #include <dev/pci/pcidevs.h> 70 71 #include <dev/pci/if_em_hw.h> 72 #include <dev/pci/if_em_soc.h> 73 74 #define STATIC 75 76 static int32_t em_swfw_sync_acquire(struct em_hw *, uint16_t); 77 static void em_swfw_sync_release(struct em_hw *, uint16_t); 78 static int32_t em_read_kmrn_reg(struct em_hw *, uint32_t, uint16_t *); 79 static int32_t em_write_kmrn_reg(struct em_hw *hw, uint32_t, uint16_t); 80 static int32_t em_get_software_semaphore(struct em_hw *); 81 static void em_release_software_semaphore(struct em_hw *); 82 83 static int32_t em_check_downshift(struct em_hw *); 84 static void em_clear_vfta(struct em_hw *); 85 static int32_t em_commit_shadow_ram(struct em_hw *); 86 static int32_t em_config_dsp_after_link_change(struct em_hw *, boolean_t); 87 static int32_t em_config_fc_after_link_up(struct em_hw *); 88 static int32_t em_match_gig_phy(struct em_hw *); 89 static int32_t em_detect_gig_phy(struct em_hw *); 90 static int32_t em_erase_ich8_4k_segment(struct em_hw *, uint32_t); 91 static int32_t em_get_auto_rd_done(struct em_hw *); 92 static int32_t em_get_cable_length(struct em_hw *, uint16_t *, uint16_t *); 93 static int32_t em_get_hw_eeprom_semaphore(struct em_hw *); 94 static int32_t em_get_phy_cfg_done(struct em_hw *); 95 static int32_t em_get_software_flag(struct em_hw *); 96 static int32_t em_ich8_cycle_init(struct em_hw *); 97 static int32_t em_ich8_flash_cycle(struct em_hw *, uint32_t); 98 static int32_t em_id_led_init(struct em_hw *); 99 static int32_t em_init_lcd_from_nvm_config_region(struct em_hw *, uint32_t, 100 uint32_t); 101 static int32_t em_init_lcd_from_nvm(struct em_hw *); 102 static void em_init_rx_addrs(struct em_hw *); 103 static void em_initialize_hardware_bits(struct em_hw *); 104 static boolean_t em_is_onboard_nvm_eeprom(struct em_hw *); 105 static int32_t em_kumeran_lock_loss_workaround(struct em_hw *); 106 static int32_t em_mng_enable_host_if(struct em_hw *); 107 static int32_t em_read_eeprom_eerd(struct em_hw *, uint16_t, uint16_t, 108 uint16_t *); 109 static int32_t em_write_eeprom_eewr(struct em_hw *, uint16_t, uint16_t, 110 uint16_t *data); 111 static int32_t em_poll_eerd_eewr_done(struct em_hw *, int); 112 static void em_put_hw_eeprom_semaphore(struct em_hw *); 113 static int32_t em_read_ich8_byte(struct em_hw *, uint32_t, uint8_t *); 114 static int32_t em_verify_write_ich8_byte(struct em_hw *, uint32_t, uint8_t); 115 static int32_t em_write_ich8_byte(struct em_hw *, uint32_t, uint8_t); 116 static int32_t em_read_ich8_word(struct em_hw *, uint32_t, uint16_t *); 117 static int32_t em_read_ich8_data(struct em_hw *, uint32_t, uint32_t, 118 uint16_t *); 119 static int32_t em_write_ich8_data(struct em_hw *, uint32_t, uint32_t, 120 uint16_t); 121 static int32_t em_read_eeprom_ich8(struct em_hw *, uint16_t, uint16_t, 122 uint16_t *); 123 static int32_t em_write_eeprom_ich8(struct em_hw *, uint16_t, uint16_t, 124 uint16_t *); 125 static void em_release_software_flag(struct em_hw *); 126 static int32_t em_set_d3_lplu_state(struct em_hw *, boolean_t); 127 static int32_t em_set_d0_lplu_state(struct em_hw *, boolean_t); 128 static int32_t em_set_lplu_state_pchlan(struct em_hw *, boolean_t); 129 static int32_t em_set_pci_ex_no_snoop(struct em_hw *, uint32_t); 130 static void em_set_pci_express_master_disable(struct em_hw *); 131 static int32_t em_wait_autoneg(struct em_hw *); 132 static void em_write_reg_io(struct em_hw *, uint32_t, uint32_t); 133 static int32_t em_set_phy_type(struct em_hw *); 134 static void em_phy_init_script(struct em_hw *); 135 static int32_t em_setup_copper_link(struct em_hw *); 136 static int32_t em_setup_fiber_serdes_link(struct em_hw *); 137 static int32_t em_adjust_serdes_amplitude(struct em_hw *); 138 static int32_t em_phy_force_speed_duplex(struct em_hw *); 139 static int32_t em_config_mac_to_phy(struct em_hw *); 140 static void em_raise_mdi_clk(struct em_hw *, uint32_t *); 141 static void em_lower_mdi_clk(struct em_hw *, uint32_t *); 142 static void em_shift_out_mdi_bits(struct em_hw *, uint32_t, uint16_t); 143 static uint16_t em_shift_in_mdi_bits(struct em_hw *); 144 static int32_t em_phy_reset_dsp(struct em_hw *); 145 static int32_t em_write_eeprom_spi(struct em_hw *, uint16_t, uint16_t, 146 uint16_t *); 147 static int32_t em_write_eeprom_microwire(struct em_hw *, uint16_t, uint16_t, 148 uint16_t *); 149 static int32_t em_spi_eeprom_ready(struct em_hw *); 150 static void em_raise_ee_clk(struct em_hw *, uint32_t *); 151 static void em_lower_ee_clk(struct em_hw *, uint32_t *); 152 static void em_shift_out_ee_bits(struct em_hw *, uint16_t, uint16_t); 153 static int32_t em_write_phy_reg_ex(struct em_hw *, uint32_t, uint16_t); 154 static int32_t em_read_phy_reg_ex(struct em_hw *, uint32_t, uint16_t *); 155 static uint16_t em_shift_in_ee_bits(struct em_hw *, uint16_t); 156 static int32_t em_acquire_eeprom(struct em_hw *); 157 static void em_release_eeprom(struct em_hw *); 158 static void em_standby_eeprom(struct em_hw *); 159 static int32_t em_set_vco_speed(struct em_hw *); 160 static int32_t em_polarity_reversal_workaround(struct em_hw *); 161 static void em_pch2lan_disable_hw_config(struct em_hw *, boolean_t); 162 static int32_t em_set_phy_mode(struct em_hw *); 163 static int32_t em_host_if_read_cookie(struct em_hw *, uint8_t *); 164 static uint8_t em_calculate_mng_checksum(char *, uint32_t); 165 static int32_t em_configure_kmrn_for_10_100(struct em_hw *, uint16_t); 166 static int32_t em_configure_kmrn_for_1000(struct em_hw *); 167 static int32_t em_set_pciex_completion_timeout(struct em_hw *hw); 168 static int32_t em_set_mdio_slow_mode_hv(struct em_hw *); 169 int32_t em_hv_phy_workarounds_ich8lan(struct em_hw *); 170 int32_t em_link_stall_workaround_hv(struct em_hw *); 171 int32_t em_k1_gig_workaround_hv(struct em_hw *, boolean_t); 172 int32_t em_k1_workaround_lv(struct em_hw *); 173 int32_t em_configure_k1_ich8lan(struct em_hw *, boolean_t); 174 int32_t em_access_phy_wakeup_reg_bm(struct em_hw *, uint32_t, 175 uint16_t *, boolean_t); 176 int32_t em_access_phy_debug_regs_hv(struct em_hw *, uint32_t, 177 uint16_t *, boolean_t); 178 int32_t em_access_phy_reg_hv(struct em_hw *, uint32_t, uint16_t *, 179 boolean_t); 180 int32_t em_oem_bits_config_pchlan(struct em_hw *, boolean_t); 181 void em_power_up_serdes_link_82575(struct em_hw *); 182 int32_t em_get_pcs_speed_and_duplex_82575(struct em_hw *, uint16_t *, 183 uint16_t *); 184 185 /* IGP cable length table */ 186 static const uint16_t 187 em_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = 188 {5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 189 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25, 190 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40, 191 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60, 192 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90, 193 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 194 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 195 110, 196 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 197 120}; 198 199 static const uint16_t 200 em_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] = 201 {0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 202 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 203 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 204 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 205 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 206 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 207 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 208 121, 124}; 209 210 /****************************************************************************** 211 * Set the phy type member in the hw struct. 212 * 213 * hw - Struct containing variables accessed by shared code 214 *****************************************************************************/ 215 STATIC int32_t 216 em_set_phy_type(struct em_hw *hw) 217 { 218 DEBUGFUNC("em_set_phy_type"); 219 220 if (hw->mac_type == em_undefined) 221 return -E1000_ERR_PHY_TYPE; 222 223 switch (hw->phy_id) { 224 case M88E1000_E_PHY_ID: 225 case M88E1000_I_PHY_ID: 226 case M88E1011_I_PHY_ID: 227 case M88E1111_I_PHY_ID: 228 hw->phy_type = em_phy_m88; 229 break; 230 case IGP01E1000_I_PHY_ID: 231 if (hw->mac_type == em_82541 || 232 hw->mac_type == em_82541_rev_2 || 233 hw->mac_type == em_82547 || 234 hw->mac_type == em_82547_rev_2) { 235 hw->phy_type = em_phy_igp; 236 break; 237 } 238 case IGP03E1000_E_PHY_ID: 239 case IGP04E1000_E_PHY_ID: 240 hw->phy_type = em_phy_igp_3; 241 break; 242 case IFE_E_PHY_ID: 243 case IFE_PLUS_E_PHY_ID: 244 case IFE_C_E_PHY_ID: 245 hw->phy_type = em_phy_ife; 246 break; 247 case M88E1141_E_PHY_ID: 248 hw->phy_type = em_phy_oem; 249 break; 250 case I82577_E_PHY_ID: 251 hw->phy_type = em_phy_82577; 252 break; 253 case I82578_E_PHY_ID: 254 hw->phy_type = em_phy_82578; 255 break; 256 case I82579_E_PHY_ID: 257 hw->phy_type = em_phy_82579; 258 break; 259 case I82580_I_PHY_ID: 260 hw->phy_type = em_phy_82580; 261 break; 262 case BME1000_E_PHY_ID: 263 if (hw->phy_revision == 1) { 264 hw->phy_type = em_phy_bm; 265 break; 266 } 267 /* FALLTHROUGH */ 268 case GG82563_E_PHY_ID: 269 if (hw->mac_type == em_80003es2lan) { 270 hw->phy_type = em_phy_gg82563; 271 break; 272 } 273 /* FALLTHROUGH */ 274 default: 275 /* Should never have loaded on this device */ 276 hw->phy_type = em_phy_undefined; 277 return -E1000_ERR_PHY_TYPE; 278 } 279 280 return E1000_SUCCESS; 281 } 282 283 /****************************************************************************** 284 * IGP phy init script - initializes the GbE PHY 285 * 286 * hw - Struct containing variables accessed by shared code 287 *****************************************************************************/ 288 static void 289 em_phy_init_script(struct em_hw *hw) 290 { 291 uint16_t phy_saved_data; 292 DEBUGFUNC("em_phy_init_script"); 293 294 if (hw->phy_init_script) { 295 msec_delay(20); 296 /* 297 * Save off the current value of register 0x2F5B to be 298 * restored at the end of this routine. 299 */ 300 em_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 301 302 /* Disabled the PHY transmitter */ 303 em_write_phy_reg(hw, 0x2F5B, 0x0003); 304 msec_delay(20); 305 em_write_phy_reg(hw, 0x0000, 0x0140); 306 msec_delay(5); 307 308 switch (hw->mac_type) { 309 case em_82541: 310 case em_82547: 311 em_write_phy_reg(hw, 0x1F95, 0x0001); 312 em_write_phy_reg(hw, 0x1F71, 0xBD21); 313 em_write_phy_reg(hw, 0x1F79, 0x0018); 314 em_write_phy_reg(hw, 0x1F30, 0x1600); 315 em_write_phy_reg(hw, 0x1F31, 0x0014); 316 em_write_phy_reg(hw, 0x1F32, 0x161C); 317 em_write_phy_reg(hw, 0x1F94, 0x0003); 318 em_write_phy_reg(hw, 0x1F96, 0x003F); 319 em_write_phy_reg(hw, 0x2010, 0x0008); 320 break; 321 case em_82541_rev_2: 322 case em_82547_rev_2: 323 em_write_phy_reg(hw, 0x1F73, 0x0099); 324 break; 325 default: 326 break; 327 } 328 329 em_write_phy_reg(hw, 0x0000, 0x3300); 330 msec_delay(20); 331 332 /* Now enable the transmitter */ 333 em_write_phy_reg(hw, 0x2F5B, phy_saved_data); 334 335 if (hw->mac_type == em_82547) { 336 uint16_t fused, fine, coarse; 337 /* Move to analog registers page */ 338 em_read_phy_reg(hw, 339 IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused); 340 341 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { 342 em_read_phy_reg(hw, 343 IGP01E1000_ANALOG_FUSE_STATUS, &fused); 344 345 fine = fused & 346 IGP01E1000_ANALOG_FUSE_FINE_MASK; 347 coarse = fused & 348 IGP01E1000_ANALOG_FUSE_COARSE_MASK; 349 350 if (coarse > 351 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { 352 coarse -= 353 IGP01E1000_ANALOG_FUSE_COARSE_10; 354 fine -= 355 IGP01E1000_ANALOG_FUSE_FINE_1; 356 } else if (coarse == 357 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) 358 fine -= IGP01E1000_ANALOG_FUSE_FINE_10; 359 360 fused = (fused & 361 IGP01E1000_ANALOG_FUSE_POLY_MASK) | 362 (fine & 363 IGP01E1000_ANALOG_FUSE_FINE_MASK) | 364 (coarse & 365 IGP01E1000_ANALOG_FUSE_COARSE_MASK); 366 367 em_write_phy_reg(hw, 368 IGP01E1000_ANALOG_FUSE_CONTROL, 369 fused); 370 371 em_write_phy_reg(hw, 372 IGP01E1000_ANALOG_FUSE_BYPASS, 373 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL); 374 } 375 } 376 } 377 } 378 379 /****************************************************************************** 380 * Set the mac type member in the hw struct. 381 * 382 * hw - Struct containing variables accessed by shared code 383 *****************************************************************************/ 384 int32_t 385 em_set_mac_type(struct em_hw *hw) 386 { 387 DEBUGFUNC("em_set_mac_type"); 388 389 switch (hw->device_id) { 390 case E1000_DEV_ID_82542: 391 switch (hw->revision_id) { 392 case E1000_82542_2_0_REV_ID: 393 hw->mac_type = em_82542_rev2_0; 394 break; 395 case E1000_82542_2_1_REV_ID: 396 hw->mac_type = em_82542_rev2_1; 397 break; 398 default: 399 /* Invalid 82542 revision ID */ 400 return -E1000_ERR_MAC_TYPE; 401 } 402 break; 403 case E1000_DEV_ID_82543GC_FIBER: 404 case E1000_DEV_ID_82543GC_COPPER: 405 hw->mac_type = em_82543; 406 break; 407 case E1000_DEV_ID_82544EI_COPPER: 408 case E1000_DEV_ID_82544EI_FIBER: 409 case E1000_DEV_ID_82544GC_COPPER: 410 case E1000_DEV_ID_82544GC_LOM: 411 hw->mac_type = em_82544; 412 break; 413 case E1000_DEV_ID_82540EM: 414 case E1000_DEV_ID_82540EM_LOM: 415 case E1000_DEV_ID_82540EP: 416 case E1000_DEV_ID_82540EP_LOM: 417 case E1000_DEV_ID_82540EP_LP: 418 hw->mac_type = em_82540; 419 break; 420 case E1000_DEV_ID_82545EM_COPPER: 421 case E1000_DEV_ID_82545EM_FIBER: 422 hw->mac_type = em_82545; 423 break; 424 case E1000_DEV_ID_82545GM_COPPER: 425 case E1000_DEV_ID_82545GM_FIBER: 426 case E1000_DEV_ID_82545GM_SERDES: 427 hw->mac_type = em_82545_rev_3; 428 break; 429 case E1000_DEV_ID_82546EB_COPPER: 430 case E1000_DEV_ID_82546EB_FIBER: 431 case E1000_DEV_ID_82546EB_QUAD_COPPER: 432 hw->mac_type = em_82546; 433 break; 434 case E1000_DEV_ID_82546GB_COPPER: 435 case E1000_DEV_ID_82546GB_FIBER: 436 case E1000_DEV_ID_82546GB_SERDES: 437 case E1000_DEV_ID_82546GB_PCIE: 438 case E1000_DEV_ID_82546GB_QUAD_COPPER: 439 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 440 case E1000_DEV_ID_82546GB_2: 441 hw->mac_type = em_82546_rev_3; 442 break; 443 case E1000_DEV_ID_82541EI: 444 case E1000_DEV_ID_82541EI_MOBILE: 445 case E1000_DEV_ID_82541ER_LOM: 446 hw->mac_type = em_82541; 447 break; 448 case E1000_DEV_ID_82541ER: 449 case E1000_DEV_ID_82541GI: 450 case E1000_DEV_ID_82541GI_LF: 451 case E1000_DEV_ID_82541GI_MOBILE: 452 hw->mac_type = em_82541_rev_2; 453 break; 454 case E1000_DEV_ID_82547EI: 455 case E1000_DEV_ID_82547EI_MOBILE: 456 hw->mac_type = em_82547; 457 break; 458 case E1000_DEV_ID_82547GI: 459 hw->mac_type = em_82547_rev_2; 460 break; 461 case E1000_DEV_ID_82571EB_AF: 462 case E1000_DEV_ID_82571EB_AT: 463 case E1000_DEV_ID_82571EB_COPPER: 464 case E1000_DEV_ID_82571EB_FIBER: 465 case E1000_DEV_ID_82571EB_SERDES: 466 case E1000_DEV_ID_82571EB_QUAD_COPPER: 467 case E1000_DEV_ID_82571EB_QUAD_FIBER: 468 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 469 case E1000_DEV_ID_82571EB_SERDES_DUAL: 470 case E1000_DEV_ID_82571EB_SERDES_QUAD: 471 case E1000_DEV_ID_82571PT_QUAD_COPPER: 472 hw->mac_type = em_82571; 473 break; 474 case E1000_DEV_ID_82572EI_COPPER: 475 case E1000_DEV_ID_82572EI_FIBER: 476 case E1000_DEV_ID_82572EI_SERDES: 477 case E1000_DEV_ID_82572EI: 478 hw->mac_type = em_82572; 479 break; 480 case E1000_DEV_ID_82573E: 481 case E1000_DEV_ID_82573E_IAMT: 482 case E1000_DEV_ID_82573E_PM: 483 case E1000_DEV_ID_82573L: 484 case E1000_DEV_ID_82573L_PL_1: 485 case E1000_DEV_ID_82573L_PL_2: 486 case E1000_DEV_ID_82573V_PM: 487 hw->mac_type = em_82573; 488 break; 489 case E1000_DEV_ID_82574L: 490 case E1000_DEV_ID_82574LA: 491 case E1000_DEV_ID_82583V: 492 hw->mac_type = em_82574; 493 break; 494 case E1000_DEV_ID_82575EB_PT: 495 case E1000_DEV_ID_82575EB_PF: 496 case E1000_DEV_ID_82575GB_QP: 497 case E1000_DEV_ID_82575GB_QP_PM: 498 case E1000_DEV_ID_82576: 499 case E1000_DEV_ID_82576_FIBER: 500 case E1000_DEV_ID_82576_SERDES: 501 case E1000_DEV_ID_82576_QUAD_COPPER: 502 case E1000_DEV_ID_82576_QUAD_CU_ET2: 503 case E1000_DEV_ID_82576_NS: 504 case E1000_DEV_ID_82576_NS_SERDES: 505 case E1000_DEV_ID_82576_SERDES_QUAD: 506 hw->mac_type = em_82575; 507 hw->initialize_hw_bits_disable = 1; 508 break; 509 case E1000_DEV_ID_82580_COPPER: 510 case E1000_DEV_ID_82580_FIBER: 511 case E1000_DEV_ID_82580_SERDES: 512 case E1000_DEV_ID_82580_SGMII: 513 case E1000_DEV_ID_82580_COPPER_DUAL: 514 hw->mac_type = em_82580; 515 hw->initialize_hw_bits_disable = 1; 516 break; 517 case E1000_DEV_ID_80003ES2LAN_COPPER_SPT: 518 case E1000_DEV_ID_80003ES2LAN_SERDES_SPT: 519 case E1000_DEV_ID_80003ES2LAN_COPPER_DPT: 520 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: 521 hw->mac_type = em_80003es2lan; 522 break; 523 case E1000_DEV_ID_ICH8_IFE: 524 case E1000_DEV_ID_ICH8_IFE_G: 525 case E1000_DEV_ID_ICH8_IFE_GT: 526 case E1000_DEV_ID_ICH8_IGP_AMT: 527 case E1000_DEV_ID_ICH8_IGP_C: 528 case E1000_DEV_ID_ICH8_IGP_M: 529 case E1000_DEV_ID_ICH8_IGP_M_AMT: 530 case E1000_DEV_ID_ICH8_82567V_3: 531 hw->mac_type = em_ich8lan; 532 break; 533 case E1000_DEV_ID_ICH9_BM: 534 case E1000_DEV_ID_ICH9_IFE: 535 case E1000_DEV_ID_ICH9_IFE_G: 536 case E1000_DEV_ID_ICH9_IFE_GT: 537 case E1000_DEV_ID_ICH9_IGP_AMT: 538 case E1000_DEV_ID_ICH9_IGP_C: 539 case E1000_DEV_ID_ICH9_IGP_M: 540 case E1000_DEV_ID_ICH9_IGP_M_AMT: 541 case E1000_DEV_ID_ICH9_IGP_M_V: 542 case E1000_DEV_ID_ICH10_R_BM_LF: 543 case E1000_DEV_ID_ICH10_R_BM_LM: 544 case E1000_DEV_ID_ICH10_R_BM_V: 545 hw->mac_type = em_ich9lan; 546 break; 547 case E1000_DEV_ID_ICH10_D_BM_LF: 548 case E1000_DEV_ID_ICH10_D_BM_LM: 549 hw->mac_type = em_ich10lan; 550 break; 551 case E1000_DEV_ID_PCH_M_HV_LC: 552 case E1000_DEV_ID_PCH_M_HV_LM: 553 case E1000_DEV_ID_PCH_D_HV_DC: 554 case E1000_DEV_ID_PCH_D_HV_DM: 555 hw->mac_type = em_pchlan; 556 break; 557 case E1000_DEV_ID_PCH2_LV_LM: 558 case E1000_DEV_ID_PCH2_LV_V: 559 hw->mac_type = em_pch2lan; 560 break; 561 case E1000_DEV_ID_EP80579_LAN_1: 562 hw->mac_type = em_icp_xxxx; 563 hw->icp_xxxx_port_num = 0; 564 break; 565 case E1000_DEV_ID_EP80579_LAN_2: 566 hw->mac_type = em_icp_xxxx; 567 hw->icp_xxxx_port_num = 1; 568 break; 569 case E1000_DEV_ID_EP80579_LAN_3: 570 hw->mac_type = em_icp_xxxx; 571 hw->icp_xxxx_port_num = 2; 572 break; 573 default: 574 /* Should never have loaded on this device */ 575 return -E1000_ERR_MAC_TYPE; 576 } 577 578 switch (hw->mac_type) { 579 case em_ich8lan: 580 case em_ich9lan: 581 case em_ich10lan: 582 case em_pchlan: 583 case em_pch2lan: 584 hw->swfwhw_semaphore_present = TRUE; 585 hw->asf_firmware_present = TRUE; 586 break; 587 case em_80003es2lan: 588 case em_82575: 589 case em_82580: 590 hw->swfw_sync_present = TRUE; 591 /* FALLTHROUGH */ 592 case em_82571: 593 case em_82572: 594 case em_82573: 595 case em_82574: 596 hw->eeprom_semaphore_present = TRUE; 597 /* FALLTHROUGH */ 598 case em_82541: 599 case em_82547: 600 case em_82541_rev_2: 601 case em_82547_rev_2: 602 hw->asf_firmware_present = TRUE; 603 break; 604 default: 605 break; 606 } 607 608 return E1000_SUCCESS; 609 } 610 /***************************************************************************** 611 * Set media type and TBI compatibility. 612 * 613 * hw - Struct containing variables accessed by shared code 614 * **************************************************************************/ 615 void 616 em_set_media_type(struct em_hw *hw) 617 { 618 uint32_t status, ctrl_ext; 619 DEBUGFUNC("em_set_media_type"); 620 621 if (hw->mac_type != em_82543) { 622 /* tbi_compatibility is only valid on 82543 */ 623 hw->tbi_compatibility_en = FALSE; 624 } 625 626 if (hw->mac_type == em_82575 || hw->mac_type == em_82580) { 627 hw->media_type = em_media_type_copper; 628 629 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 630 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) { 631 case E1000_CTRL_EXT_LINK_MODE_SGMII: 632 ctrl_ext |= E1000_CTRL_I2C_ENA; 633 break; 634 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: 635 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES: 636 hw->media_type = em_media_type_internal_serdes; 637 ctrl_ext |= E1000_CTRL_I2C_ENA; 638 break; 639 default: 640 ctrl_ext &= ~E1000_CTRL_I2C_ENA; 641 break; 642 } 643 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 644 return; 645 } 646 647 switch (hw->device_id) { 648 case E1000_DEV_ID_82545GM_SERDES: 649 case E1000_DEV_ID_82546GB_SERDES: 650 case E1000_DEV_ID_82571EB_SERDES: 651 case E1000_DEV_ID_82571EB_SERDES_DUAL: 652 case E1000_DEV_ID_82571EB_SERDES_QUAD: 653 case E1000_DEV_ID_82572EI_SERDES: 654 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: 655 hw->media_type = em_media_type_internal_serdes; 656 break; 657 case E1000_DEV_ID_EP80579_LAN_1: 658 case E1000_DEV_ID_EP80579_LAN_2: 659 case E1000_DEV_ID_EP80579_LAN_3: 660 hw->media_type = em_media_type_oem; 661 break; 662 default: 663 switch (hw->mac_type) { 664 case em_82542_rev2_0: 665 case em_82542_rev2_1: 666 hw->media_type = em_media_type_fiber; 667 break; 668 case em_ich8lan: 669 case em_ich9lan: 670 case em_ich10lan: 671 case em_pchlan: 672 case em_pch2lan: 673 case em_82573: 674 case em_82574: 675 /* 676 * The STATUS_TBIMODE bit is reserved or reused for 677 * the this device. 678 */ 679 hw->media_type = em_media_type_copper; 680 break; 681 default: 682 status = E1000_READ_REG(hw, STATUS); 683 if (status & E1000_STATUS_TBIMODE) { 684 hw->media_type = em_media_type_fiber; 685 /* tbi_compatibility not valid on fiber */ 686 hw->tbi_compatibility_en = FALSE; 687 } else { 688 hw->media_type = em_media_type_copper; 689 } 690 break; 691 } 692 } 693 } 694 /****************************************************************************** 695 * Reset the transmit and receive units; mask and clear all interrupts. 696 * 697 * hw - Struct containing variables accessed by shared code 698 *****************************************************************************/ 699 int32_t 700 em_reset_hw(struct em_hw *hw) 701 { 702 uint32_t ctrl; 703 uint32_t ctrl_ext; 704 uint32_t icr; 705 uint32_t manc; 706 uint32_t led_ctrl; 707 uint32_t timeout; 708 uint32_t extcnf_ctrl; 709 int32_t ret_val; 710 DEBUGFUNC("em_reset_hw"); 711 712 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ 713 if (hw->mac_type == em_82542_rev2_0) { 714 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 715 em_pci_clear_mwi(hw); 716 } 717 if (hw->bus_type == em_bus_type_pci_express) { 718 /* 719 * Prevent the PCI-E bus from sticking if there is no TLP 720 * connection on the last TLP read/write transaction when MAC 721 * is reset. 722 */ 723 if (em_disable_pciex_master(hw) != E1000_SUCCESS) { 724 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 725 } 726 } 727 728 /* Set the completion timeout for 82575 chips */ 729 if (hw->mac_type == em_82575 || hw->mac_type == em_82580) { 730 ret_val = em_set_pciex_completion_timeout(hw); 731 if (ret_val) { 732 DEBUGOUT("PCI-E Set completion timeout has failed.\n"); 733 } 734 } 735 736 /* Clear interrupt mask to stop board from generating interrupts */ 737 DEBUGOUT("Masking off all interrupts\n"); 738 E1000_WRITE_REG(hw, IMC, 0xffffffff); 739 /* 740 * Disable the Transmit and Receive units. Then delay to allow any 741 * pending transactions to complete before we hit the MAC with the 742 * global reset. 743 */ 744 E1000_WRITE_REG(hw, RCTL, 0); 745 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP); 746 E1000_WRITE_FLUSH(hw); 747 /* 748 * The tbi_compatibility_on Flag must be cleared when Rctl is 749 * cleared. 750 */ 751 hw->tbi_compatibility_on = FALSE; 752 /* 753 * Delay to allow any outstanding PCI transactions to complete before 754 * resetting the device 755 */ 756 msec_delay(10); 757 758 ctrl = E1000_READ_REG(hw, CTRL); 759 760 /* Must reset the PHY before resetting the MAC */ 761 if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) { 762 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST)); 763 msec_delay(5); 764 } 765 /* 766 * Must acquire the MDIO ownership before MAC reset. Ownership 767 * defaults to firmware after a reset. 768 */ 769 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) { 770 timeout = 10; 771 772 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 773 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 774 775 do { 776 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); 777 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 778 779 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) 780 break; 781 else 782 extcnf_ctrl |= 783 E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 784 785 msec_delay(2); 786 timeout--; 787 } while (timeout); 788 } 789 /* Workaround for ICH8 bit corruption issue in FIFO memory */ 790 if (hw->mac_type == em_ich8lan) { 791 /* Set Tx and Rx buffer allocation to 8k apiece. */ 792 E1000_WRITE_REG(hw, PBA, E1000_PBA_8K); 793 /* Set Packet Buffer Size to 16k. */ 794 E1000_WRITE_REG(hw, PBS, E1000_PBS_16K); 795 } 796 /* 797 * Issue a global reset to the MAC. This will reset the chip's 798 * transmit, receive, DMA, and link units. It will not effect the 799 * current PCI configuration. The global reset bit is self- 800 * clearing, and should clear within a microsecond. 801 */ 802 DEBUGOUT("Issuing a global reset to MAC\n"); 803 804 switch (hw->mac_type) { 805 case em_82544: 806 case em_82540: 807 case em_82545: 808 case em_82546: 809 case em_82541: 810 case em_82541_rev_2: 811 /* 812 * These controllers can't ack the 64-bit write when issuing 813 * the reset, so use IO-mapping as a workaround to issue the 814 * reset 815 */ 816 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST)); 817 break; 818 case em_82545_rev_3: 819 case em_82546_rev_3: 820 /* Reset is performed on a shadow of the control register */ 821 E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST)); 822 break; 823 case em_ich8lan: 824 case em_ich9lan: 825 case em_ich10lan: 826 case em_pchlan: 827 case em_pch2lan: 828 if (!hw->phy_reset_disable && 829 em_check_phy_reset_block(hw) == E1000_SUCCESS) { 830 /* 831 * PHY HW reset requires MAC CORE reset at the same 832 * time to make sure the interface between MAC and 833 * the external PHY is reset. 834 */ 835 ctrl |= E1000_CTRL_PHY_RST; 836 837 if ((hw->mac_type == em_pch2lan) && 838 !(E1000_READ_REG(hw, FWSM) & E1000_FWSM_FW_VALID)) { 839 em_pch2lan_disable_hw_config(hw, TRUE); 840 } 841 } 842 em_get_software_flag(hw); 843 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); 844 msec_delay(5); 845 break; 846 default: 847 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); 848 break; 849 } 850 851 if (em_check_phy_reset_block(hw) == E1000_SUCCESS) { 852 if (hw->mac_type == em_pchlan) { 853 ret_val = em_hv_phy_workarounds_ich8lan(hw); 854 if (ret_val) 855 return ret_val; 856 } 857 else if (hw->mac_type == em_pch2lan) { 858 ret_val = em_set_mdio_slow_mode_hv(hw); 859 if (ret_val) 860 return ret_val; 861 } 862 } 863 864 /* 865 * After MAC reset, force reload of EEPROM to restore power-on 866 * settings to device. Later controllers reload the EEPROM 867 * automatically, so just wait for reload to complete. 868 */ 869 switch (hw->mac_type) { 870 case em_82542_rev2_0: 871 case em_82542_rev2_1: 872 case em_82543: 873 case em_82544: 874 /* Wait for reset to complete */ 875 usec_delay(10); 876 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 877 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 878 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 879 E1000_WRITE_FLUSH(hw); 880 /* Wait for EEPROM reload */ 881 msec_delay(2); 882 break; 883 case em_82541: 884 case em_82541_rev_2: 885 case em_82547: 886 case em_82547_rev_2: 887 /* Wait for EEPROM reload */ 888 msec_delay(20); 889 break; 890 case em_82573: 891 case em_82574: 892 if (em_is_onboard_nvm_eeprom(hw) == FALSE) { 893 usec_delay(10); 894 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 895 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 896 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 897 E1000_WRITE_FLUSH(hw); 898 } 899 /* FALLTHROUGH */ 900 901 /* Auto read done will delay 5ms or poll based on mac type */ 902 ret_val = em_get_auto_rd_done(hw); 903 if (ret_val) 904 return ret_val; 905 break; 906 default: 907 /* Wait for EEPROM reload (it happens automatically) */ 908 msec_delay(5); 909 break; 910 } 911 912 /* Disable HW ARPs on ASF enabled adapters */ 913 if (hw->mac_type >= em_82540 && hw->mac_type <= em_82547_rev_2 && 914 hw->mac_type != em_icp_xxxx) { 915 manc = E1000_READ_REG(hw, MANC); 916 manc &= ~(E1000_MANC_ARP_EN); 917 E1000_WRITE_REG(hw, MANC, manc); 918 } 919 if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) { 920 em_phy_init_script(hw); 921 922 /* Configure activity LED after PHY reset */ 923 led_ctrl = E1000_READ_REG(hw, LEDCTL); 924 led_ctrl &= IGP_ACTIVITY_LED_MASK; 925 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 926 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 927 } 928 929 /* 930 * For PCH, this write will make sure that any noise 931 * will be detected as a CRC error and be dropped rather than show up 932 * as a bad packet to the DMA engine. 933 */ 934 if (hw->mac_type == em_pchlan) 935 E1000_WRITE_REG(hw, CRC_OFFSET, 0x65656565); 936 937 /* Clear interrupt mask to stop board from generating interrupts */ 938 DEBUGOUT("Masking off all interrupts\n"); 939 E1000_WRITE_REG(hw, IMC, 0xffffffff); 940 941 /* Clear any pending interrupt events. */ 942 icr = E1000_READ_REG(hw, ICR); 943 944 /* If MWI was previously enabled, reenable it. */ 945 if (hw->mac_type == em_82542_rev2_0) { 946 if (hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 947 em_pci_set_mwi(hw); 948 } 949 if (hw->mac_type == em_ich8lan || 950 hw->mac_type == em_ich9lan || 951 hw->mac_type == em_ich10lan || 952 hw->mac_type == em_pchlan || 953 hw->mac_type == em_pch2lan) { 954 uint32_t kab = E1000_READ_REG(hw, KABGTXD); 955 kab |= E1000_KABGTXD_BGSQLBIAS; 956 E1000_WRITE_REG(hw, KABGTXD, kab); 957 } 958 return E1000_SUCCESS; 959 } 960 961 /****************************************************************************** 962 * 963 * Initialize a number of hardware-dependent bits 964 * 965 * hw: Struct containing variables accessed by shared code 966 * 967 *****************************************************************************/ 968 STATIC void 969 em_initialize_hardware_bits(struct em_hw *hw) 970 { 971 DEBUGFUNC("em_initialize_hardware_bits"); 972 973 if ((hw->mac_type >= em_82571) && (!hw->initialize_hw_bits_disable)) { 974 /* Settings common to all silicon */ 975 uint32_t reg_ctrl, reg_ctrl_ext; 976 uint32_t reg_tarc0, reg_tarc1; 977 uint32_t reg_tctl; 978 uint32_t reg_txdctl, reg_txdctl1; 979 reg_tarc0 = E1000_READ_REG(hw, TARC0); 980 reg_tarc0 &= ~0x78000000; /* Clear bits 30, 29, 28, and 981 * 27 */ 982 983 reg_txdctl = E1000_READ_REG(hw, TXDCTL); 984 reg_txdctl |= E1000_TXDCTL_COUNT_DESC; /* Set bit 22 */ 985 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl); 986 987 reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1); 988 reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC; /* Set bit 22 */ 989 E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1); 990 991 switch (hw->mac_type) { 992 case em_82571: 993 case em_82572: 994 reg_tarc1 = E1000_READ_REG(hw, TARC1); 995 reg_tctl = E1000_READ_REG(hw, TCTL); 996 997 /* Set the phy Tx compatible mode bits */ 998 reg_tarc1 &= ~0x60000000; /* Clear bits 30 and 29 */ 999 1000 reg_tarc0 |= 0x07800000; /* Set TARC0 bits 23-26 */ 1001 reg_tarc1 |= 0x07000000; /* Set TARC1 bits 24-26 */ 1002 1003 if (reg_tctl & E1000_TCTL_MULR) 1004 /* Clear bit 28 if MULR is 1b */ 1005 reg_tarc1 &= ~0x10000000; 1006 else 1007 /* Set bit 28 if MULR is 0b */ 1008 reg_tarc1 |= 0x10000000; 1009 1010 E1000_WRITE_REG(hw, TARC1, reg_tarc1); 1011 break; 1012 case em_82573: 1013 case em_82574: 1014 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1015 reg_ctrl = E1000_READ_REG(hw, CTRL); 1016 1017 reg_ctrl_ext &= ~0x00800000; /* Clear bit 23 */ 1018 reg_ctrl_ext |= 0x00400000; /* Set bit 22 */ 1019 reg_ctrl &= ~0x20000000; /* Clear bit 29 */ 1020 1021 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); 1022 E1000_WRITE_REG(hw, CTRL, reg_ctrl); 1023 break; 1024 case em_80003es2lan: 1025 if ((hw->media_type == em_media_type_fiber) || 1026 (hw->media_type == em_media_type_internal_serdes)) { 1027 /* Clear bit 20 */ 1028 reg_tarc0 &= ~0x00100000; 1029 } 1030 reg_tctl = E1000_READ_REG(hw, TCTL); 1031 reg_tarc1 = E1000_READ_REG(hw, TARC1); 1032 if (reg_tctl & E1000_TCTL_MULR) 1033 /* Clear bit 28 if MULR is 1b */ 1034 reg_tarc1 &= ~0x10000000; 1035 else 1036 /* Set bit 28 if MULR is 0b */ 1037 reg_tarc1 |= 0x10000000; 1038 1039 E1000_WRITE_REG(hw, TARC1, reg_tarc1); 1040 break; 1041 case em_ich8lan: 1042 case em_ich9lan: 1043 case em_ich10lan: 1044 case em_pchlan: 1045 case em_pch2lan: 1046 if (hw->mac_type == em_ich8lan) 1047 /* Set TARC0 bits 29 and 28 */ 1048 reg_tarc0 |= 0x30000000; 1049 1050 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1051 reg_ctrl_ext |= 0x00400000; /* Set bit 22 */ 1052 /* Enable PHY low-power state when MAC is at D3 w/o WoL */ 1053 if (hw->mac_type >= em_pchlan) 1054 reg_ctrl_ext |= E1000_CTRL_EXT_PHYPDEN; 1055 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); 1056 1057 reg_tarc0 |= 0x0d800000; /* Set TARC0 bits 23, 1058 * 24, 26, 27 */ 1059 1060 reg_tarc1 = E1000_READ_REG(hw, TARC1); 1061 reg_tctl = E1000_READ_REG(hw, TCTL); 1062 1063 if (reg_tctl & E1000_TCTL_MULR) 1064 /* Clear bit 28 if MULR is 1b */ 1065 reg_tarc1 &= ~0x10000000; 1066 else 1067 /* Set bit 28 if MULR is 0b */ 1068 reg_tarc1 |= 0x10000000; 1069 1070 reg_tarc1 |= 0x45000000; /* Set bit 24, 26 and 1071 * 30 */ 1072 1073 E1000_WRITE_REG(hw, TARC1, reg_tarc1); 1074 break; 1075 default: 1076 break; 1077 } 1078 1079 E1000_WRITE_REG(hw, TARC0, reg_tarc0); 1080 } 1081 } 1082 1083 /****************************************************************************** 1084 * Performs basic configuration of the adapter. 1085 * 1086 * hw - Struct containing variables accessed by shared code 1087 * 1088 * Assumes that the controller has previously been reset and is in a 1089 * post-reset uninitialized state. Initializes the receive address registers, 1090 * multicast table, and VLAN filter table. Calls routines to setup link 1091 * configuration and flow control settings. Clears all on-chip counters. Leaves 1092 * the transmit and receive units disabled and uninitialized. 1093 *****************************************************************************/ 1094 int32_t 1095 em_init_hw(struct em_hw *hw) 1096 { 1097 uint32_t ctrl; 1098 uint32_t i; 1099 int32_t ret_val; 1100 uint16_t pcix_cmd_word; 1101 uint16_t pcix_stat_hi_word; 1102 uint16_t cmd_mmrbc; 1103 uint16_t stat_mmrbc; 1104 uint32_t mta_size; 1105 uint32_t reg_data; 1106 uint32_t ctrl_ext; 1107 uint32_t snoop; 1108 uint32_t fwsm; 1109 DEBUGFUNC("em_init_hw"); 1110 1111 /* force full DMA clock frequency for ICH8 */ 1112 if (hw->mac_type == em_ich8lan) { 1113 reg_data = E1000_READ_REG(hw, STATUS); 1114 reg_data &= ~0x80000000; 1115 E1000_WRITE_REG(hw, STATUS, reg_data); 1116 } 1117 1118 if (hw->mac_type == em_pchlan || 1119 hw->mac_type == em_pch2lan) { 1120 /* 1121 * The MAC-PHY interconnect may still be in SMBus mode 1122 * after Sx->S0. Toggle the LANPHYPC Value bit to force 1123 * the interconnect to PCIe mode, but only if there is no 1124 * firmware present otherwise firmware will have done it. 1125 */ 1126 fwsm = E1000_READ_REG(hw, FWSM); 1127 if ((fwsm & E1000_FWSM_FW_VALID) == 0) { 1128 ctrl = E1000_READ_REG(hw, CTRL); 1129 ctrl |= E1000_CTRL_LANPHYPC_OVERRIDE; 1130 ctrl &= ~E1000_CTRL_LANPHYPC_VALUE; 1131 E1000_WRITE_REG(hw, CTRL, ctrl); 1132 usec_delay(10); 1133 ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE; 1134 E1000_WRITE_REG(hw, CTRL, ctrl); 1135 msec_delay(50); 1136 } 1137 1138 if (hw->mac_type == em_pch2lan) 1139 em_pch2lan_disable_hw_config(hw, TRUE); 1140 1141 /* 1142 * Reset the PHY before any acccess to it. Doing so, 1143 * ensures that the PHY is in a known good state before 1144 * we read/write PHY registers. The generic reset is 1145 * sufficient here, because we haven't determined 1146 * the PHY type yet. 1147 */ 1148 em_phy_reset(hw); 1149 1150 if (hw->mac_type == em_pch2lan && 1151 (fwsm & E1000_FWSM_FW_VALID) == 0) 1152 em_pch2lan_disable_hw_config(hw, FALSE); 1153 1154 /* Set MDIO slow mode before any other MDIO access */ 1155 ret_val = em_set_mdio_slow_mode_hv(hw); 1156 if (ret_val) 1157 return ret_val; 1158 } 1159 1160 /* Initialize Identification LED */ 1161 ret_val = em_id_led_init(hw); 1162 if (ret_val) { 1163 DEBUGOUT("Error Initializing Identification LED\n"); 1164 return ret_val; 1165 } 1166 /* Set the media type and TBI compatibility */ 1167 em_set_media_type(hw); 1168 1169 /* Must be called after em_set_media_type because media_type is used */ 1170 em_initialize_hardware_bits(hw); 1171 1172 /* Disabling VLAN filtering. */ 1173 DEBUGOUT("Initializing the IEEE VLAN\n"); 1174 /* VET hardcoded to standard value and VFTA removed in ICH8/ICH9 LAN */ 1175 if (hw->mac_type != em_ich8lan && 1176 hw->mac_type != em_ich9lan && 1177 hw->mac_type != em_ich10lan && 1178 hw->mac_type != em_pchlan && 1179 hw->mac_type != em_pch2lan) { 1180 if (hw->mac_type < em_82545_rev_3) 1181 E1000_WRITE_REG(hw, VET, 0); 1182 em_clear_vfta(hw); 1183 } 1184 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ 1185 if (hw->mac_type == em_82542_rev2_0) { 1186 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 1187 em_pci_clear_mwi(hw); 1188 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST); 1189 E1000_WRITE_FLUSH(hw); 1190 msec_delay(5); 1191 } 1192 /* 1193 * Setup the receive address. This involves initializing all of the 1194 * Receive Address Registers (RARs 0 - 15). 1195 */ 1196 em_init_rx_addrs(hw); 1197 1198 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI*/ 1199 if (hw->mac_type == em_82542_rev2_0) { 1200 E1000_WRITE_REG(hw, RCTL, 0); 1201 E1000_WRITE_FLUSH(hw); 1202 msec_delay(1); 1203 if (hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1204 em_pci_set_mwi(hw); 1205 } 1206 /* Zero out the Multicast HASH table */ 1207 DEBUGOUT("Zeroing the MTA\n"); 1208 mta_size = E1000_MC_TBL_SIZE; 1209 if (hw->mac_type == em_ich8lan || 1210 hw->mac_type == em_ich9lan || 1211 hw->mac_type == em_ich10lan || 1212 hw->mac_type == em_pchlan || 1213 hw->mac_type == em_pch2lan) 1214 mta_size = E1000_MC_TBL_SIZE_ICH8LAN; 1215 for (i = 0; i < mta_size; i++) { 1216 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 1217 /* 1218 * use write flush to prevent Memory Write Block (MWB) from 1219 * occuring when accessing our register space 1220 */ 1221 E1000_WRITE_FLUSH(hw); 1222 } 1223 /* 1224 * Set the PCI priority bit correctly in the CTRL register. This 1225 * determines if the adapter gives priority to receives, or if it 1226 * gives equal priority to transmits and receives. Valid only on 1227 * 82542 and 82543 silicon. 1228 */ 1229 if (hw->dma_fairness && hw->mac_type <= em_82543) { 1230 ctrl = E1000_READ_REG(hw, CTRL); 1231 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR); 1232 } 1233 switch (hw->mac_type) { 1234 case em_82545_rev_3: 1235 case em_82546_rev_3: 1236 break; 1237 default: 1238 /* 1239 * Workaround for PCI-X problem when BIOS sets MMRBC 1240 * incorrectly. 1241 */ 1242 if (hw->bus_type == em_bus_type_pcix) { 1243 em_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, 1244 &pcix_cmd_word); 1245 em_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, 1246 &pcix_stat_hi_word); 1247 cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) 1248 >> PCIX_COMMAND_MMRBC_SHIFT; 1249 stat_mmrbc = (pcix_stat_hi_word & 1250 PCIX_STATUS_HI_MMRBC_MASK) >> 1251 PCIX_STATUS_HI_MMRBC_SHIFT; 1252 1253 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) 1254 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; 1255 if (cmd_mmrbc > stat_mmrbc) { 1256 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK; 1257 pcix_cmd_word |= stat_mmrbc << 1258 PCIX_COMMAND_MMRBC_SHIFT; 1259 em_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, 1260 &pcix_cmd_word); 1261 } 1262 } 1263 break; 1264 } 1265 1266 /* More time needed for PHY to initialize */ 1267 if (hw->mac_type == em_ich8lan || 1268 hw->mac_type == em_ich9lan || 1269 hw->mac_type == em_ich10lan || 1270 hw->mac_type == em_pchlan || 1271 hw->mac_type == em_pch2lan) 1272 msec_delay(15); 1273 1274 /* 1275 * The 82578 Rx buffer will stall if wakeup is enabled in host and 1276 * the ME. Reading the BM_WUC register will clear the host wakeup bit. 1277 * Reset the phy after disabling host wakeup to reset the Rx buffer. 1278 */ 1279 if (hw->phy_type == em_phy_82578) { 1280 em_read_phy_reg(hw, PHY_REG(BM_WUC_PAGE, 1), 1281 (uint16_t *)®_data); 1282 ret_val = em_phy_reset(hw); 1283 if (ret_val) 1284 return ret_val; 1285 } 1286 1287 /* Call a subroutine to configure the link and setup flow control. */ 1288 ret_val = em_setup_link(hw); 1289 1290 /* Set the transmit descriptor write-back policy */ 1291 if (hw->mac_type > em_82544) { 1292 ctrl = E1000_READ_REG(hw, TXDCTL); 1293 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | 1294 E1000_TXDCTL_FULL_TX_DESC_WB; 1295 E1000_WRITE_REG(hw, TXDCTL, ctrl); 1296 } 1297 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) { 1298 em_enable_tx_pkt_filtering(hw); 1299 } 1300 switch (hw->mac_type) { 1301 default: 1302 break; 1303 case em_80003es2lan: 1304 /* Enable retransmit on late collisions */ 1305 reg_data = E1000_READ_REG(hw, TCTL); 1306 reg_data |= E1000_TCTL_RTLC; 1307 E1000_WRITE_REG(hw, TCTL, reg_data); 1308 1309 /* Configure Gigabit Carry Extend Padding */ 1310 reg_data = E1000_READ_REG(hw, TCTL_EXT); 1311 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK; 1312 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX; 1313 E1000_WRITE_REG(hw, TCTL_EXT, reg_data); 1314 1315 /* Configure Transmit Inter-Packet Gap */ 1316 reg_data = E1000_READ_REG(hw, TIPG); 1317 reg_data &= ~E1000_TIPG_IPGT_MASK; 1318 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; 1319 E1000_WRITE_REG(hw, TIPG, reg_data); 1320 1321 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001); 1322 reg_data &= ~0x00100000; 1323 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data); 1324 /* FALLTHROUGH */ 1325 case em_82571: 1326 case em_82572: 1327 case em_82575: 1328 case em_82580: 1329 case em_ich8lan: 1330 case em_ich9lan: 1331 case em_ich10lan: 1332 case em_pchlan: 1333 case em_pch2lan: 1334 ctrl = E1000_READ_REG(hw, TXDCTL1); 1335 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | 1336 E1000_TXDCTL_FULL_TX_DESC_WB; 1337 E1000_WRITE_REG(hw, TXDCTL1, ctrl); 1338 break; 1339 } 1340 1341 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) { 1342 uint32_t gcr = E1000_READ_REG(hw, GCR); 1343 gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; 1344 E1000_WRITE_REG(hw, GCR, gcr); 1345 } 1346 /* 1347 * Clear all of the statistics registers (clear on read). It is 1348 * important that we do this after we have tried to establish link 1349 * because the symbol error count will increment wildly if there is 1350 * no link. 1351 */ 1352 em_clear_hw_cntrs(hw); 1353 /* 1354 * ICH8 No-snoop bits are opposite polarity. Set to snoop by default 1355 * after reset. 1356 */ 1357 if (hw->mac_type == em_ich8lan) 1358 snoop = PCI_EX_82566_SNOOP_ALL; 1359 else if (hw->mac_type == em_ich9lan || 1360 hw->mac_type == em_ich10lan || 1361 hw->mac_type == em_pchlan) 1362 snoop = (u_int32_t) ~ (PCI_EX_NO_SNOOP_ALL); 1363 if (hw->mac_type == em_ich8lan || 1364 hw->mac_type == em_ich9lan || 1365 hw->mac_type == em_ich10lan || 1366 hw->mac_type == em_pchlan || 1367 hw->mac_type == em_pch2lan) 1368 em_set_pci_ex_no_snoop(hw, snoop); 1369 1370 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER || 1371 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) { 1372 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1373 /* 1374 * Relaxed ordering must be disabled to avoid a parity error 1375 * crash in a PCI slot. 1376 */ 1377 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 1378 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1379 } 1380 return ret_val; 1381 } 1382 1383 /****************************************************************************** 1384 * Adjust SERDES output amplitude based on EEPROM setting. 1385 * 1386 * hw - Struct containing variables accessed by shared code. 1387 *****************************************************************************/ 1388 static int32_t 1389 em_adjust_serdes_amplitude(struct em_hw *hw) 1390 { 1391 uint16_t eeprom_data; 1392 int32_t ret_val; 1393 DEBUGFUNC("em_adjust_serdes_amplitude"); 1394 1395 if (hw->media_type != em_media_type_internal_serdes || 1396 hw->mac_type == em_82575) 1397 return E1000_SUCCESS; 1398 1399 switch (hw->mac_type) { 1400 case em_82545_rev_3: 1401 case em_82546_rev_3: 1402 break; 1403 default: 1404 return E1000_SUCCESS; 1405 } 1406 1407 ret_val = em_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data); 1408 if (ret_val) { 1409 return ret_val; 1410 } 1411 if (eeprom_data != EEPROM_RESERVED_WORD) { 1412 /* Adjust SERDES output amplitude only. */ 1413 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK; 1414 ret_val = em_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, 1415 eeprom_data); 1416 if (ret_val) 1417 return ret_val; 1418 } 1419 return E1000_SUCCESS; 1420 } 1421 1422 /****************************************************************************** 1423 * Configures flow control and link settings. 1424 * 1425 * hw - Struct containing variables accessed by shared code 1426 * 1427 * Determines which flow control settings to use. Calls the appropriate media- 1428 * specific link configuration function. Configures the flow control settings. 1429 * Assuming the adapter has a valid link partner, a valid link should be 1430 * established. Assumes the hardware has previously been reset and the 1431 * transmitter and receiver are not enabled. 1432 *****************************************************************************/ 1433 int32_t 1434 em_setup_link(struct em_hw *hw) 1435 { 1436 uint32_t ctrl_ext; 1437 int32_t ret_val; 1438 uint16_t eeprom_data; 1439 uint16_t eeprom_control2_reg_offset; 1440 DEBUGFUNC("em_setup_link"); 1441 1442 eeprom_control2_reg_offset = 1443 (hw->mac_type != em_icp_xxxx) 1444 ? EEPROM_INIT_CONTROL2_REG 1445 : EEPROM_INIT_CONTROL3_ICP_xxxx(hw->icp_xxxx_port_num); 1446 /* 1447 * In the case of the phy reset being blocked, we already have a 1448 * link. We do not have to set it up again. 1449 */ 1450 if (em_check_phy_reset_block(hw)) 1451 return E1000_SUCCESS; 1452 /* 1453 * Read and store word 0x0F of the EEPROM. This word contains bits 1454 * that determine the hardware's default PAUSE (flow control) mode, a 1455 * bit that determines whether the HW defaults to enabling or 1456 * disabling auto-negotiation, and the direction of the SW defined 1457 * pins. If there is no SW over-ride of the flow control setting, 1458 * then the variable hw->fc will be initialized based on a value in 1459 * the EEPROM. 1460 */ 1461 if (hw->fc == E1000_FC_DEFAULT) { 1462 switch (hw->mac_type) { 1463 case em_ich8lan: 1464 case em_ich9lan: 1465 case em_ich10lan: 1466 case em_pchlan: 1467 case em_pch2lan: 1468 case em_82573: 1469 case em_82574: 1470 hw->fc = E1000_FC_FULL; 1471 break; 1472 default: 1473 ret_val = em_read_eeprom(hw, 1474 eeprom_control2_reg_offset, 1, &eeprom_data); 1475 if (ret_val) { 1476 DEBUGOUT("EEPROM Read Error\n"); 1477 return -E1000_ERR_EEPROM; 1478 } 1479 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0) 1480 hw->fc = E1000_FC_NONE; 1481 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 1482 EEPROM_WORD0F_ASM_DIR) 1483 hw->fc = E1000_FC_TX_PAUSE; 1484 else 1485 hw->fc = E1000_FC_FULL; 1486 break; 1487 } 1488 } 1489 /* 1490 * We want to save off the original Flow Control configuration just 1491 * in case we get disconnected and then reconnected into a different 1492 * hub or switch with different Flow Control capabilities. 1493 */ 1494 if (hw->mac_type == em_82542_rev2_0) 1495 hw->fc &= (~E1000_FC_TX_PAUSE); 1496 1497 if ((hw->mac_type < em_82543) && (hw->report_tx_early == 1)) 1498 hw->fc &= (~E1000_FC_RX_PAUSE); 1499 1500 hw->original_fc = hw->fc; 1501 1502 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc); 1503 /* 1504 * Take the 4 bits from EEPROM word 0x0F that determine the initial 1505 * polarity value for the SW controlled pins, and setup the Extended 1506 * Device Control reg with that info. This is needed because one of 1507 * the SW controlled pins is used for signal detection. So this 1508 * should be done before em_setup_pcs_link() or em_phy_setup() is 1509 * called. 1510 */ 1511 if (hw->mac_type == em_82543) { 1512 ret_val = em_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1513 1, &eeprom_data); 1514 if (ret_val) { 1515 DEBUGOUT("EEPROM Read Error\n"); 1516 return -E1000_ERR_EEPROM; 1517 } 1518 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << 1519 SWDPIO__EXT_SHIFT); 1520 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1521 } 1522 /* Make sure we have a valid PHY */ 1523 ret_val = em_detect_gig_phy(hw); 1524 if (ret_val) { 1525 DEBUGOUT("Error, did not detect valid phy.\n"); 1526 if (hw->mac_type == em_icp_xxxx) 1527 return E1000_DEFER_INIT; 1528 else 1529 return ret_val; 1530 } 1531 DEBUGOUT1("Phy ID = %x \n", hw->phy_id); 1532 1533 /* Call the necessary subroutine to configure the link. */ 1534 switch (hw->media_type) { 1535 case em_media_type_copper: 1536 case em_media_type_oem: 1537 ret_val = em_setup_copper_link(hw); 1538 break; 1539 default: 1540 ret_val = em_setup_fiber_serdes_link(hw); 1541 break; 1542 } 1543 /* 1544 * Initialize the flow control address, type, and PAUSE timer 1545 * registers to their default values. This is done even if flow 1546 * control is disabled, because it does not hurt anything to 1547 * initialize these registers. 1548 */ 1549 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n" 1550 ); 1551 1552 /* 1553 * FCAL/H and FCT are hardcoded to standard values in 1554 * em_ich8lan / em_ich9lan / em_ich10lan. 1555 */ 1556 if (hw->mac_type != em_ich8lan && 1557 hw->mac_type != em_ich9lan && 1558 hw->mac_type != em_ich10lan && 1559 hw->mac_type != em_pchlan && 1560 hw->mac_type != em_pch2lan) { 1561 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE); 1562 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH); 1563 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW); 1564 } 1565 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time); 1566 1567 if (hw->phy_type == em_phy_82577 || 1568 hw->phy_type == em_phy_82578 || 1569 hw->phy_type == em_phy_82579) { 1570 E1000_WRITE_REG(hw, FCRTV_PCH, 0x1000); 1571 em_write_phy_reg(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27), 1572 hw->fc_pause_time); 1573 } 1574 1575 /* 1576 * Set the flow control receive threshold registers. Normally, these 1577 * registers will be set to a default threshold that may be adjusted 1578 * later by the driver's runtime code. However, if the ability to 1579 * transmit pause frames in not enabled, then these registers will be 1580 * set to 0. 1581 */ 1582 if (!(hw->fc & E1000_FC_TX_PAUSE)) { 1583 E1000_WRITE_REG(hw, FCRTL, 0); 1584 E1000_WRITE_REG(hw, FCRTH, 0); 1585 } else { 1586 /* 1587 * We need to set up the Receive Threshold high and low water 1588 * marks as well as (optionally) enabling the transmission of 1589 * XON frames. 1590 */ 1591 if (hw->fc_send_xon) { 1592 E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water 1593 | E1000_FCRTL_XONE)); 1594 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); 1595 } else { 1596 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water); 1597 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); 1598 } 1599 } 1600 return ret_val; 1601 } 1602 1603 void 1604 em_power_up_serdes_link_82575(struct em_hw *hw) 1605 { 1606 uint32_t reg; 1607 1608 /* Enable PCS to turn on link */ 1609 reg = E1000_READ_REG(hw, PCS_CFG0); 1610 reg |= E1000_PCS_CFG_PCS_EN; 1611 E1000_WRITE_REG(hw, PCS_CFG0, reg); 1612 1613 /* Power up the laser */ 1614 reg = E1000_READ_REG(hw, CTRL_EXT); 1615 reg &= ~E1000_CTRL_EXT_SDP3_DATA; 1616 E1000_WRITE_REG(hw, CTRL_EXT, reg); 1617 1618 /* flush the write to verify completion */ 1619 E1000_WRITE_FLUSH(hw); 1620 delay(5); 1621 } 1622 1623 /****************************************************************************** 1624 * Sets up link for a fiber based or serdes based adapter 1625 * 1626 * hw - Struct containing variables accessed by shared code 1627 * 1628 * Manipulates Physical Coding Sublayer functions in order to configure 1629 * link. Assumes the hardware has been previously reset and the transmitter 1630 * and receiver are not enabled. 1631 *****************************************************************************/ 1632 static int32_t 1633 em_setup_fiber_serdes_link(struct em_hw *hw) 1634 { 1635 uint32_t ctrl, ctrl_ext, reg; 1636 uint32_t status; 1637 uint32_t txcw = 0; 1638 uint32_t i; 1639 uint32_t signal = 0; 1640 int32_t ret_val; 1641 DEBUGFUNC("em_setup_fiber_serdes_link"); 1642 /* 1643 * On 82571 and 82572 Fiber connections, SerDes loopback mode 1644 * persists until explicitly turned off or a power cycle is 1645 * performed. A read to the register does not indicate its status. 1646 * Therefore, we ensure loopback mode is disabled during 1647 * initialization. 1648 */ 1649 if (hw->mac_type == em_82571 || hw->mac_type == em_82572 || 1650 hw->mac_type == em_82575) 1651 E1000_WRITE_REG(hw, SCTL, E1000_DISABLE_SERDES_LOOPBACK); 1652 1653 if (hw->mac_type == em_82575) 1654 em_power_up_serdes_link_82575(hw); 1655 1656 /* 1657 * On adapters with a MAC newer than 82544, SWDP 1 will be set when 1658 * the optics detect a signal. On older adapters, it will be cleared 1659 * when there is a signal. This applies to fiber media only. If 1660 * we're on serdes media, adjust the output amplitude to value set in 1661 * the EEPROM. 1662 */ 1663 ctrl = E1000_READ_REG(hw, CTRL); 1664 if (hw->media_type == em_media_type_fiber) 1665 signal = (hw->mac_type > em_82544) ? E1000_CTRL_SWDPIN1 : 0; 1666 1667 ret_val = em_adjust_serdes_amplitude(hw); 1668 if (ret_val) 1669 return ret_val; 1670 1671 /* Take the link out of reset */ 1672 ctrl &= ~(E1000_CTRL_LRST); 1673 1674 if (hw->mac_type == em_82575) { 1675 /* set both sw defined pins on 82575/82576*/ 1676 ctrl |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1; 1677 1678 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1679 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) { 1680 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: 1681 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES: 1682 /* the backplane is always connected */ 1683 reg = E1000_READ_REG(hw, PCS_LCTL); 1684 reg |= E1000_PCS_LCTL_FORCE_FCTRL; 1685 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL; 1686 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */ 1687 DEBUGOUT("Configuring Forced Link\n"); 1688 E1000_WRITE_REG(hw, PCS_LCTL, reg); 1689 em_force_mac_fc(hw); 1690 hw->autoneg_failed = 0; 1691 return E1000_SUCCESS; 1692 break; 1693 default: 1694 /* Set switch control to serdes energy detect */ 1695 reg = E1000_READ_REG(hw, CONNSW); 1696 reg |= E1000_CONNSW_ENRGSRC; 1697 E1000_WRITE_REG(hw, CONNSW, reg); 1698 break; 1699 } 1700 } 1701 1702 /* Adjust VCO speed to improve BER performance */ 1703 ret_val = em_set_vco_speed(hw); 1704 if (ret_val) 1705 return ret_val; 1706 1707 em_config_collision_dist(hw); 1708 /* 1709 * Check for a software override of the flow control settings, and 1710 * setup the device accordingly. If auto-negotiation is enabled, 1711 * then software will have to set the "PAUSE" bits to the correct 1712 * value in the Tranmsit Config Word Register (TXCW) and re-start 1713 * auto-negotiation. However, if auto-negotiation is disabled, then 1714 * software will have to manually configure the two flow control 1715 * enable bits in the CTRL register. 1716 * 1717 * The possible values of the "fc" parameter are: 0: Flow control is 1718 * completely disabled 1: Rx flow control is enabled (we can receive 1719 * pause frames, but not send pause frames). 2: Tx flow control is 1720 * enabled (we can send pause frames but we do not support receiving 1721 * pause frames). 3: Both Rx and TX flow control (symmetric) are 1722 * enabled. 1723 */ 1724 switch (hw->fc) { 1725 case E1000_FC_NONE: 1726 /* 1727 * Flow control is completely disabled by a software 1728 * over-ride. 1729 */ 1730 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 1731 break; 1732 case E1000_FC_RX_PAUSE: 1733 /* 1734 * RX Flow control is enabled and TX Flow control is disabled 1735 * by a software over-ride. Since there really isn't a way to 1736 * advertise that we are capable of RX Pause ONLY, we will 1737 * advertise that we support both symmetric and asymmetric RX 1738 * PAUSE. Later, we will disable the adapter's ability to 1739 * send PAUSE frames. 1740 */ 1741 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | 1742 E1000_TXCW_PAUSE_MASK); 1743 break; 1744 case E1000_FC_TX_PAUSE: 1745 /* 1746 * TX Flow control is enabled, and RX Flow control is 1747 * disabled, by a software over-ride. 1748 */ 1749 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 1750 break; 1751 case E1000_FC_FULL: 1752 /* 1753 * Flow control (both RX and TX) is enabled by a software 1754 * over-ride. 1755 */ 1756 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | 1757 E1000_TXCW_PAUSE_MASK); 1758 break; 1759 default: 1760 DEBUGOUT("Flow control param set incorrectly\n"); 1761 return -E1000_ERR_CONFIG; 1762 break; 1763 } 1764 /* 1765 * Since auto-negotiation is enabled, take the link out of reset (the 1766 * link will be in reset, because we previously reset the chip). This 1767 * will restart auto-negotiation. If auto-neogtiation is successful 1768 * then the link-up status bit will be set and the flow control 1769 * enable bits (RFCE and TFCE) will be set according to their 1770 * negotiated value. 1771 */ 1772 DEBUGOUT("Auto-negotiation enabled\n"); 1773 1774 E1000_WRITE_REG(hw, TXCW, txcw); 1775 E1000_WRITE_REG(hw, CTRL, ctrl); 1776 E1000_WRITE_FLUSH(hw); 1777 1778 hw->txcw = txcw; 1779 msec_delay(1); 1780 /* 1781 * If we have a signal (the cable is plugged in) then poll for a 1782 * "Link-Up" indication in the Device Status Register. Time-out if a 1783 * link isn't seen in 500 milliseconds seconds (Auto-negotiation 1784 * should complete in less than 500 milliseconds even if the other 1785 * end is doing it in SW). For internal serdes, we just assume a 1786 * signal is present, then poll. 1787 */ 1788 if (hw->media_type == em_media_type_internal_serdes || 1789 (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) { 1790 DEBUGOUT("Looking for Link\n"); 1791 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) { 1792 msec_delay(10); 1793 status = E1000_READ_REG(hw, STATUS); 1794 if (status & E1000_STATUS_LU) 1795 break; 1796 } 1797 if (i == (LINK_UP_TIMEOUT / 10)) { 1798 DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 1799 hw->autoneg_failed = 1; 1800 /* 1801 * AutoNeg failed to achieve a link, so we'll call 1802 * em_check_for_link. This routine will force the 1803 * link up if we detect a signal. This will allow us 1804 * to communicate with non-autonegotiating link 1805 * partners. 1806 */ 1807 ret_val = em_check_for_link(hw); 1808 if (ret_val) { 1809 DEBUGOUT("Error while checking for link\n"); 1810 return ret_val; 1811 } 1812 hw->autoneg_failed = 0; 1813 } else { 1814 hw->autoneg_failed = 0; 1815 DEBUGOUT("Valid Link Found\n"); 1816 } 1817 } else { 1818 DEBUGOUT("No Signal Detected\n"); 1819 } 1820 return E1000_SUCCESS; 1821 } 1822 1823 /****************************************************************************** 1824 * Make sure we have a valid PHY and change PHY mode before link setup. 1825 * 1826 * hw - Struct containing variables accessed by shared code 1827 *****************************************************************************/ 1828 static int32_t 1829 em_copper_link_preconfig(struct em_hw *hw) 1830 { 1831 uint32_t ctrl; 1832 int32_t ret_val; 1833 uint16_t phy_data; 1834 DEBUGFUNC("em_copper_link_preconfig"); 1835 1836 ctrl = E1000_READ_REG(hw, CTRL); 1837 /* 1838 * With 82543, we need to force speed and duplex on the MAC equal to 1839 * what the PHY speed and duplex configuration is. In addition, we 1840 * need to perform a hardware reset on the PHY to take it out of 1841 * reset. 1842 */ 1843 if (hw->mac_type > em_82543) { 1844 ctrl |= E1000_CTRL_SLU; 1845 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1846 E1000_WRITE_REG(hw, CTRL, ctrl); 1847 } else { 1848 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | 1849 E1000_CTRL_SLU); 1850 E1000_WRITE_REG(hw, CTRL, ctrl); 1851 ret_val = em_phy_hw_reset(hw); 1852 if (ret_val) 1853 return ret_val; 1854 } 1855 1856 /* Set PHY to class A mode (if necessary) */ 1857 ret_val = em_set_phy_mode(hw); 1858 if (ret_val) 1859 return ret_val; 1860 1861 if ((hw->mac_type == em_82545_rev_3) || 1862 (hw->mac_type == em_82546_rev_3)) { 1863 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 1864 &phy_data); 1865 phy_data |= 0x00000008; 1866 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 1867 phy_data); 1868 } 1869 if (hw->mac_type <= em_82543 || 1870 hw->mac_type == em_82541 || hw->mac_type == em_82547 || 1871 hw->mac_type == em_82541_rev_2 || hw->mac_type == em_82547_rev_2) 1872 hw->phy_reset_disable = FALSE; 1873 1874 return E1000_SUCCESS; 1875 } 1876 1877 /****************************************************************************** 1878 * Copper link setup for em_phy_igp series. 1879 * 1880 * hw - Struct containing variables accessed by shared code 1881 *****************************************************************************/ 1882 static int32_t 1883 em_copper_link_igp_setup(struct em_hw *hw) 1884 { 1885 uint32_t led_ctrl; 1886 int32_t ret_val; 1887 uint16_t phy_data; 1888 DEBUGFUNC("em_copper_link_igp_setup"); 1889 1890 if (hw->phy_reset_disable) 1891 return E1000_SUCCESS; 1892 1893 ret_val = em_phy_reset(hw); 1894 if (ret_val) { 1895 DEBUGOUT("Error Resetting the PHY\n"); 1896 return ret_val; 1897 } 1898 /* Wait 15ms for MAC to configure PHY from eeprom settings */ 1899 msec_delay(15); 1900 if (hw->mac_type != em_ich8lan && 1901 hw->mac_type != em_ich9lan && 1902 hw->mac_type != em_ich10lan) { 1903 /* Configure activity LED after PHY reset */ 1904 led_ctrl = E1000_READ_REG(hw, LEDCTL); 1905 led_ctrl &= IGP_ACTIVITY_LED_MASK; 1906 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 1907 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 1908 } 1909 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */ 1910 if (hw->phy_type == em_phy_igp) { 1911 /* disable lplu d3 during driver init */ 1912 ret_val = em_set_d3_lplu_state(hw, FALSE); 1913 if (ret_val) { 1914 DEBUGOUT("Error Disabling LPLU D3\n"); 1915 return ret_val; 1916 } 1917 } 1918 /* disable lplu d0 during driver init */ 1919 if (hw->mac_type == em_pchlan || 1920 hw->mac_type == em_pch2lan) 1921 ret_val = em_set_lplu_state_pchlan(hw, FALSE); 1922 else 1923 ret_val = em_set_d0_lplu_state(hw, FALSE); 1924 if (ret_val) { 1925 DEBUGOUT("Error Disabling LPLU D0\n"); 1926 return ret_val; 1927 } 1928 /* Configure mdi-mdix settings */ 1929 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 1930 if (ret_val) 1931 return ret_val; 1932 1933 if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) { 1934 hw->dsp_config_state = em_dsp_config_disabled; 1935 /* Force MDI for earlier revs of the IGP PHY */ 1936 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | 1937 IGP01E1000_PSCR_FORCE_MDI_MDIX); 1938 hw->mdix = 1; 1939 1940 } else { 1941 hw->dsp_config_state = em_dsp_config_enabled; 1942 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 1943 1944 switch (hw->mdix) { 1945 case 1: 1946 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 1947 break; 1948 case 2: 1949 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; 1950 break; 1951 case 0: 1952 default: 1953 phy_data |= IGP01E1000_PSCR_AUTO_MDIX; 1954 break; 1955 } 1956 } 1957 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 1958 if (ret_val) 1959 return ret_val; 1960 1961 /* set auto-master slave resolution settings */ 1962 if (hw->autoneg) { 1963 em_ms_type phy_ms_setting = hw->master_slave; 1964 if (hw->ffe_config_state == em_ffe_config_active) 1965 hw->ffe_config_state = em_ffe_config_enabled; 1966 1967 if (hw->dsp_config_state == em_dsp_config_activated) 1968 hw->dsp_config_state = em_dsp_config_enabled; 1969 /* 1970 * when autonegotiation advertisement is only 1000Mbps then 1971 * we should disable SmartSpeed and enable Auto MasterSlave 1972 * resolution as hardware default. 1973 */ 1974 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) { 1975 /* Disable SmartSpeed */ 1976 ret_val = em_read_phy_reg(hw, 1977 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 1978 if (ret_val) 1979 return ret_val; 1980 1981 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1982 ret_val = em_write_phy_reg(hw, 1983 IGP01E1000_PHY_PORT_CONFIG, phy_data); 1984 if (ret_val) 1985 return ret_val; 1986 /* Set auto Master/Slave resolution process */ 1987 ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, 1988 &phy_data); 1989 if (ret_val) 1990 return ret_val; 1991 1992 phy_data &= ~CR_1000T_MS_ENABLE; 1993 ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL, 1994 phy_data); 1995 if (ret_val) 1996 return ret_val; 1997 } 1998 ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); 1999 if (ret_val) 2000 return ret_val; 2001 2002 /* load defaults for future use */ 2003 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ? 2004 ((phy_data & CR_1000T_MS_VALUE) ? em_ms_force_master : 2005 em_ms_force_slave) : em_ms_auto; 2006 2007 switch (phy_ms_setting) { 2008 case em_ms_force_master: 2009 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 2010 break; 2011 case em_ms_force_slave: 2012 phy_data |= CR_1000T_MS_ENABLE; 2013 phy_data &= ~(CR_1000T_MS_VALUE); 2014 break; 2015 case em_ms_auto: 2016 phy_data &= ~CR_1000T_MS_ENABLE; 2017 break; 2018 default: 2019 break; 2020 } 2021 ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); 2022 if (ret_val) 2023 return ret_val; 2024 } 2025 return E1000_SUCCESS; 2026 } 2027 2028 /****************************************************************************** 2029 * Copper link setup for em_phy_gg82563 series. 2030 * 2031 * hw - Struct containing variables accessed by shared code 2032 *****************************************************************************/ 2033 static int32_t 2034 em_copper_link_ggp_setup(struct em_hw *hw) 2035 { 2036 int32_t ret_val; 2037 uint16_t phy_data; 2038 uint32_t reg_data; 2039 DEBUGFUNC("em_copper_link_ggp_setup"); 2040 2041 if (!hw->phy_reset_disable) { 2042 2043 /* Enable CRS on TX for half-duplex operation. */ 2044 ret_val = em_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 2045 &phy_data); 2046 if (ret_val) 2047 return ret_val; 2048 2049 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 2050 /* Use 25MHz for both link down and 1000BASE-T for Tx clock */ 2051 phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ; 2052 2053 ret_val = em_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 2054 phy_data); 2055 if (ret_val) 2056 return ret_val; 2057 /* 2058 * Options: MDI/MDI-X = 0 (default) 0 - Auto for all speeds 1 2059 * - MDI mode 2 - MDI-X mode 3 - Auto for 1000Base-T only 2060 * (MDI-X for 10/100Base-T modes) 2061 */ 2062 ret_val = em_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, 2063 &phy_data); 2064 2065 if (ret_val) 2066 return ret_val; 2067 2068 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK; 2069 2070 switch (hw->mdix) { 2071 case 1: 2072 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI; 2073 break; 2074 case 2: 2075 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX; 2076 break; 2077 case 0: 2078 default: 2079 phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO; 2080 break; 2081 } 2082 /* 2083 * Options: disable_polarity_correction = 0 (default) 2084 * Automatic Correction for Reversed Cable Polarity 0 - 2085 * Disabled 1 - Enabled 2086 */ 2087 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 2088 if (hw->disable_polarity_correction == 1) 2089 phy_data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 2090 ret_val = em_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, 2091 phy_data); 2092 2093 if (ret_val) 2094 return ret_val; 2095 2096 /* SW Reset the PHY so all changes take effect */ 2097 ret_val = em_phy_reset(hw); 2098 if (ret_val) { 2099 DEBUGOUT("Error Resetting the PHY\n"); 2100 return ret_val; 2101 } 2102 } /* phy_reset_disable */ 2103 if (hw->mac_type == em_80003es2lan) { 2104 /* Bypass RX and TX FIFO's */ 2105 ret_val = em_write_kmrn_reg(hw, 2106 E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL, 2107 E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS | 2108 E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS); 2109 if (ret_val) 2110 return ret_val; 2111 2112 ret_val = em_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, 2113 &phy_data); 2114 if (ret_val) 2115 return ret_val; 2116 2117 phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG; 2118 ret_val = em_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, 2119 phy_data); 2120 2121 if (ret_val) 2122 return ret_val; 2123 2124 reg_data = E1000_READ_REG(hw, CTRL_EXT); 2125 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK); 2126 E1000_WRITE_REG(hw, CTRL_EXT, reg_data); 2127 2128 ret_val = em_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, 2129 &phy_data); 2130 if (ret_val) 2131 return ret_val; 2132 /* 2133 * Do not init these registers when the HW is in IAMT mode, 2134 * since the firmware will have already initialized them. We 2135 * only initialize them if the HW is not in IAMT mode. 2136 */ 2137 if (em_check_mng_mode(hw) == FALSE) { 2138 /* Enable Electrical Idle on the PHY */ 2139 phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; 2140 ret_val = em_write_phy_reg(hw, 2141 GG82563_PHY_PWR_MGMT_CTRL, phy_data); 2142 if (ret_val) 2143 return ret_val; 2144 2145 ret_val = em_read_phy_reg(hw, 2146 GG82563_PHY_KMRN_MODE_CTRL, &phy_data); 2147 if (ret_val) 2148 return ret_val; 2149 2150 phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 2151 ret_val = em_write_phy_reg(hw, 2152 GG82563_PHY_KMRN_MODE_CTRL, phy_data); 2153 2154 if (ret_val) 2155 return ret_val; 2156 } 2157 /* 2158 * Workaround: Disable padding in Kumeran interface in the 2159 * MAC and in the PHY to avoid CRC errors. 2160 */ 2161 ret_val = em_read_phy_reg(hw, GG82563_PHY_INBAND_CTRL, 2162 &phy_data); 2163 if (ret_val) 2164 return ret_val; 2165 phy_data |= GG82563_ICR_DIS_PADDING; 2166 ret_val = em_write_phy_reg(hw, GG82563_PHY_INBAND_CTRL, 2167 phy_data); 2168 if (ret_val) 2169 return ret_val; 2170 } 2171 return E1000_SUCCESS; 2172 } 2173 2174 /****************************************************************************** 2175 * Copper link setup for em_phy_m88 series. 2176 * 2177 * hw - Struct containing variables accessed by shared code 2178 *****************************************************************************/ 2179 static int32_t 2180 em_copper_link_mgp_setup(struct em_hw *hw) 2181 { 2182 int32_t ret_val; 2183 uint16_t phy_data; 2184 DEBUGFUNC("em_copper_link_mgp_setup"); 2185 2186 if (hw->phy_reset_disable) 2187 return E1000_SUCCESS; 2188 2189 /* disable lplu d0 during driver init */ 2190 if (hw->mac_type == em_pchlan || 2191 hw->mac_type == em_pch2lan) 2192 ret_val = em_set_lplu_state_pchlan(hw, FALSE); 2193 2194 /* Enable CRS on TX. This must be set for half-duplex operation. */ 2195 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 2196 if (ret_val) 2197 return ret_val; 2198 2199 if (hw->phy_id == M88E1141_E_PHY_ID) { 2200 phy_data |= 0x00000008; 2201 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 2202 phy_data); 2203 if (ret_val) 2204 return ret_val; 2205 2206 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 2207 &phy_data); 2208 if (ret_val) 2209 return ret_val; 2210 2211 phy_data &= ~M88E1000_PSCR_ASSERT_CRS_ON_TX; 2212 2213 } 2214 /* For BM PHY this bit is downshift enable */ 2215 else if (hw->phy_type != em_phy_bm) 2216 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 2217 /* 2218 * Options: MDI/MDI-X = 0 (default) 0 - Auto for all speeds 1 - MDI 2219 * mode 2 - MDI-X mode 3 - Auto for 1000Base-T only (MDI-X for 2220 * 10/100Base-T modes) 2221 */ 2222 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 2223 2224 switch (hw->mdix) { 2225 case 1: 2226 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 2227 break; 2228 case 2: 2229 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 2230 break; 2231 case 3: 2232 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 2233 break; 2234 case 0: 2235 default: 2236 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 2237 break; 2238 } 2239 /* 2240 * Options: disable_polarity_correction = 0 (default) Automatic 2241 * Correction for Reversed Cable Polarity 0 - Disabled 1 - Enabled 2242 */ 2243 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 2244 if (hw->disable_polarity_correction == 1) 2245 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 2246 2247 /* Enable downshift on BM (disabled by default) */ 2248 if (hw->phy_type == em_phy_bm) 2249 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT; 2250 2251 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 2252 if (ret_val) 2253 return ret_val; 2254 2255 if (((hw->phy_type == em_phy_m88) && 2256 (hw->phy_revision < M88E1011_I_REV_4) && 2257 (hw->phy_id != BME1000_E_PHY_ID)) || 2258 (hw->phy_type == em_phy_oem)) { 2259 /* 2260 * Force TX_CLK in the Extended PHY Specific Control Register 2261 * to 25MHz clock. 2262 */ 2263 ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 2264 &phy_data); 2265 if (ret_val) 2266 return ret_val; 2267 2268 if (hw->phy_type == em_phy_oem) { 2269 phy_data |= M88E1000_EPSCR_TX_TIME_CTRL; 2270 phy_data |= M88E1000_EPSCR_RX_TIME_CTRL; 2271 } 2272 phy_data |= M88E1000_EPSCR_TX_CLK_25; 2273 2274 if ((hw->phy_revision == E1000_REVISION_2) && 2275 (hw->phy_id == M88E1111_I_PHY_ID)) { 2276 /* Vidalia Phy, set the downshift counter to 5x */ 2277 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK); 2278 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; 2279 ret_val = em_write_phy_reg(hw, 2280 M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 2281 if (ret_val) 2282 return ret_val; 2283 } else { 2284 /* Configure Master and Slave downshift values */ 2285 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 2286 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 2287 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 2288 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 2289 ret_val = em_write_phy_reg(hw, 2290 M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 2291 if (ret_val) 2292 return ret_val; 2293 } 2294 } 2295 if ((hw->phy_type == em_phy_bm) && (hw->phy_revision == 1)) { 2296 /* 2297 * Set PHY page 0, register 29 to 0x0003 2298 * The next two writes are supposed to lower BER for gig 2299 * conection 2300 */ 2301 ret_val = em_write_phy_reg(hw, BM_REG_BIAS1, 0x0003); 2302 if (ret_val) 2303 return ret_val; 2304 2305 /* Set PHY page 0, register 30 to 0x0000 */ 2306 ret_val = em_write_phy_reg(hw, BM_REG_BIAS2, 0x0000); 2307 if (ret_val) 2308 return ret_val; 2309 } 2310 if (hw->phy_type == em_phy_82578) { 2311 ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 2312 &phy_data); 2313 if (ret_val) 2314 return ret_val; 2315 2316 /* 82578 PHY - set the downshift count to 1x. */ 2317 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE; 2318 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK; 2319 ret_val = em_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 2320 phy_data); 2321 if (ret_val) 2322 return ret_val; 2323 } 2324 /* SW Reset the PHY so all changes take effect */ 2325 ret_val = em_phy_reset(hw); 2326 if (ret_val) { 2327 DEBUGOUT("Error Resetting the PHY\n"); 2328 return ret_val; 2329 } 2330 return E1000_SUCCESS; 2331 } 2332 2333 /****************************************************************************** 2334 * Copper link setup for em_phy_82577 series. 2335 * 2336 * hw - Struct containing variables accessed by shared code 2337 *****************************************************************************/ 2338 static int32_t 2339 em_copper_link_82577_setup(struct em_hw *hw) 2340 { 2341 int32_t ret_val; 2342 uint16_t phy_data; 2343 uint32_t led_ctl; 2344 DEBUGFUNC("em_copper_link_82577_setup"); 2345 2346 if (hw->phy_reset_disable) 2347 return E1000_SUCCESS; 2348 2349 /* Enable CRS on TX for half-duplex operation. */ 2350 ret_val = em_read_phy_reg(hw, I82577_PHY_CFG_REG, &phy_data); 2351 if (ret_val) 2352 return ret_val; 2353 2354 phy_data |= I82577_PHY_CFG_ENABLE_CRS_ON_TX | 2355 I82577_PHY_CFG_ENABLE_DOWNSHIFT; 2356 2357 ret_val = em_write_phy_reg(hw, I82577_PHY_CFG_REG, phy_data); 2358 if (ret_val) 2359 return ret_val; 2360 2361 /* Wait 15ms for MAC to configure PHY from eeprom settings */ 2362 msec_delay(15); 2363 led_ctl = hw->ledctl_mode1; 2364 2365 /* disable lplu d0 during driver init */ 2366 ret_val = em_set_lplu_state_pchlan(hw, FALSE); 2367 if (ret_val) { 2368 DEBUGOUT("Error Disabling LPLU D0\n"); 2369 return ret_val; 2370 } 2371 2372 E1000_WRITE_REG(hw, LEDCTL, led_ctl); 2373 2374 return E1000_SUCCESS; 2375 } 2376 2377 static int32_t 2378 em_copper_link_82580_setup(struct em_hw *hw) 2379 { 2380 int32_t ret_val; 2381 uint16_t phy_data; 2382 2383 if (hw->phy_reset_disable) 2384 return E1000_SUCCESS; 2385 2386 ret_val = em_phy_reset(hw); 2387 if (ret_val) 2388 goto out; 2389 2390 /* Enable CRS on TX. This must be set for half-duplex operation. */ 2391 ret_val = em_read_phy_reg(hw, I82580_CFG_REG, &phy_data); 2392 if (ret_val) 2393 goto out; 2394 2395 phy_data |= I82580_CFG_ASSERT_CRS_ON_TX | 2396 I82580_CFG_ENABLE_DOWNSHIFT; 2397 2398 ret_val = em_write_phy_reg(hw, I82580_CFG_REG, phy_data); 2399 2400 out: 2401 return ret_val; 2402 } 2403 2404 /****************************************************************************** 2405 * Setup auto-negotiation and flow control advertisements, 2406 * and then perform auto-negotiation. 2407 * 2408 * hw - Struct containing variables accessed by shared code 2409 *****************************************************************************/ 2410 int32_t 2411 em_copper_link_autoneg(struct em_hw *hw) 2412 { 2413 int32_t ret_val; 2414 uint16_t phy_data; 2415 DEBUGFUNC("em_copper_link_autoneg"); 2416 /* 2417 * Perform some bounds checking on the hw->autoneg_advertised 2418 * parameter. If this variable is zero, then set it to the default. 2419 */ 2420 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT; 2421 /* 2422 * If autoneg_advertised is zero, we assume it was not defaulted by 2423 * the calling code so we set to advertise full capability. 2424 */ 2425 if (hw->autoneg_advertised == 0) 2426 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 2427 2428 /* IFE phy only supports 10/100 */ 2429 if (hw->phy_type == em_phy_ife) 2430 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL; 2431 2432 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); 2433 ret_val = em_phy_setup_autoneg(hw); 2434 if (ret_val) { 2435 DEBUGOUT("Error Setting up Auto-Negotiation\n"); 2436 return ret_val; 2437 } 2438 DEBUGOUT("Restarting Auto-Neg\n"); 2439 /* 2440 * Restart auto-negotiation by setting the Auto Neg Enable bit and 2441 * the Auto Neg Restart bit in the PHY control register. 2442 */ 2443 ret_val = em_read_phy_reg(hw, PHY_CTRL, &phy_data); 2444 if (ret_val) 2445 return ret_val; 2446 2447 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 2448 ret_val = em_write_phy_reg(hw, PHY_CTRL, phy_data); 2449 if (ret_val) 2450 return ret_val; 2451 /* 2452 * Does the user want to wait for Auto-Neg to complete here, or check 2453 * at a later time (for example, callback routine). 2454 */ 2455 if (hw->wait_autoneg_complete) { 2456 ret_val = em_wait_autoneg(hw); 2457 if (ret_val) { 2458 DEBUGOUT("Error while waiting for autoneg to complete\n" 2459 ); 2460 return ret_val; 2461 } 2462 } 2463 hw->get_link_status = TRUE; 2464 2465 return E1000_SUCCESS; 2466 } 2467 2468 /****************************************************************************** 2469 * Config the MAC and the PHY after link is up. 2470 * 1) Set up the MAC to the current PHY speed/duplex 2471 * if we are on 82543. If we 2472 * are on newer silicon, we only need to configure 2473 * collision distance in the Transmit Control Register. 2474 * 2) Set up flow control on the MAC to that established with 2475 * the link partner. 2476 * 3) Config DSP to improve Gigabit link quality for some PHY revisions. 2477 * 2478 * hw - Struct containing variables accessed by shared code 2479 *****************************************************************************/ 2480 int32_t 2481 em_copper_link_postconfig(struct em_hw *hw) 2482 { 2483 int32_t ret_val; 2484 DEBUGFUNC("em_copper_link_postconfig"); 2485 2486 if (hw->mac_type >= em_82544 && 2487 hw->mac_type != em_icp_xxxx) { 2488 em_config_collision_dist(hw); 2489 } else { 2490 ret_val = em_config_mac_to_phy(hw); 2491 if (ret_val) { 2492 DEBUGOUT("Error configuring MAC to PHY settings\n"); 2493 return ret_val; 2494 } 2495 } 2496 ret_val = em_config_fc_after_link_up(hw); 2497 if (ret_val) { 2498 DEBUGOUT("Error Configuring Flow Control\n"); 2499 return ret_val; 2500 } 2501 /* Config DSP to improve Giga link quality */ 2502 if (hw->phy_type == em_phy_igp) { 2503 ret_val = em_config_dsp_after_link_change(hw, TRUE); 2504 if (ret_val) { 2505 DEBUGOUT("Error Configuring DSP after link up\n"); 2506 return ret_val; 2507 } 2508 } 2509 return E1000_SUCCESS; 2510 } 2511 2512 /****************************************************************************** 2513 * Detects which PHY is present and setup the speed and duplex 2514 * 2515 * hw - Struct containing variables accessed by shared code 2516 *****************************************************************************/ 2517 static int32_t 2518 em_setup_copper_link(struct em_hw *hw) 2519 { 2520 int32_t ret_val; 2521 uint16_t i; 2522 uint16_t phy_data; 2523 uint16_t reg_data; 2524 DEBUGFUNC("em_setup_copper_link"); 2525 2526 switch (hw->mac_type) { 2527 case em_80003es2lan: 2528 case em_ich8lan: 2529 case em_ich9lan: 2530 case em_ich10lan: 2531 case em_pchlan: 2532 case em_pch2lan: 2533 /* 2534 * Set the mac to wait the maximum time between each 2535 * iteration and increase the max iterations when polling the 2536 * phy; this fixes erroneous timeouts at 10Mbps. 2537 */ 2538 ret_val = em_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF); 2539 if (ret_val) 2540 return ret_val; 2541 ret_val = em_read_kmrn_reg(hw, GG82563_REG(0x34, 9), 2542 ®_data); 2543 if (ret_val) 2544 return ret_val; 2545 reg_data |= 0x3F; 2546 ret_val = em_write_kmrn_reg(hw, GG82563_REG(0x34, 9), 2547 reg_data); 2548 if (ret_val) 2549 return ret_val; 2550 default: 2551 break; 2552 } 2553 2554 /* Check if it is a valid PHY and set PHY mode if necessary. */ 2555 ret_val = em_copper_link_preconfig(hw); 2556 if (ret_val) 2557 return ret_val; 2558 2559 switch (hw->mac_type) { 2560 case em_80003es2lan: 2561 /* Kumeran registers are written-only */ 2562 reg_data = 2563 E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT; 2564 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING; 2565 ret_val = em_write_kmrn_reg(hw, 2566 E1000_KUMCTRLSTA_OFFSET_INB_CTRL, reg_data); 2567 if (ret_val) 2568 return ret_val; 2569 break; 2570 default: 2571 break; 2572 } 2573 2574 if (hw->phy_type == em_phy_igp || 2575 hw->phy_type == em_phy_igp_3 || 2576 hw->phy_type == em_phy_igp_2) { 2577 ret_val = em_copper_link_igp_setup(hw); 2578 if (ret_val) 2579 return ret_val; 2580 } else if (hw->phy_type == em_phy_m88 || 2581 hw->phy_type == em_phy_bm || 2582 hw->phy_type == em_phy_oem || 2583 hw->phy_type == em_phy_82578) { 2584 ret_val = em_copper_link_mgp_setup(hw); 2585 if (ret_val) 2586 return ret_val; 2587 } else if (hw->phy_type == em_phy_gg82563) { 2588 ret_val = em_copper_link_ggp_setup(hw); 2589 if (ret_val) 2590 return ret_val; 2591 } else if (hw->phy_type == em_phy_82577 || 2592 hw->phy_type == em_phy_82579) { 2593 ret_val = em_copper_link_82577_setup(hw); 2594 if (ret_val) 2595 return ret_val; 2596 } else if (hw->phy_type == em_phy_82580) { 2597 ret_val = em_copper_link_82580_setup(hw); 2598 if (ret_val) 2599 return ret_val; 2600 } 2601 if (hw->autoneg) { 2602 /* 2603 * Setup autoneg and flow control advertisement and perform 2604 * autonegotiation 2605 */ 2606 ret_val = em_copper_link_autoneg(hw); 2607 if (ret_val) 2608 return ret_val; 2609 } else { 2610 /* 2611 * PHY will be set to 10H, 10F, 100H,or 100F depending on 2612 * value from forced_speed_duplex. 2613 */ 2614 DEBUGOUT("Forcing speed and duplex\n"); 2615 ret_val = em_phy_force_speed_duplex(hw); 2616 if (ret_val) { 2617 DEBUGOUT("Error Forcing Speed and Duplex\n"); 2618 return ret_val; 2619 } 2620 } 2621 /* 2622 * Check link status. Wait up to 100 microseconds for link to become 2623 * valid. 2624 */ 2625 for (i = 0; i < 10; i++) { 2626 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 2627 if (ret_val) 2628 return ret_val; 2629 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 2630 if (ret_val) 2631 return ret_val; 2632 2633 hw->icp_xxxx_is_link_up = (phy_data & MII_SR_LINK_STATUS) != 0; 2634 2635 if (phy_data & MII_SR_LINK_STATUS) { 2636 /* Config the MAC and PHY after link is up */ 2637 ret_val = em_copper_link_postconfig(hw); 2638 if (ret_val) 2639 return ret_val; 2640 2641 DEBUGOUT("Valid link established!!!\n"); 2642 return E1000_SUCCESS; 2643 } 2644 usec_delay(10); 2645 } 2646 2647 DEBUGOUT("Unable to establish link!!!\n"); 2648 return E1000_SUCCESS; 2649 } 2650 2651 /****************************************************************************** 2652 * Configure the MAC-to-PHY interface for 10/100Mbps 2653 * 2654 * hw - Struct containing variables accessed by shared code 2655 *****************************************************************************/ 2656 static int32_t 2657 em_configure_kmrn_for_10_100(struct em_hw *hw, uint16_t duplex) 2658 { 2659 int32_t ret_val = E1000_SUCCESS; 2660 uint32_t tipg; 2661 uint16_t reg_data; 2662 DEBUGFUNC("em_configure_kmrn_for_10_100"); 2663 2664 reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT; 2665 ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL, 2666 reg_data); 2667 if (ret_val) 2668 return ret_val; 2669 2670 /* Configure Transmit Inter-Packet Gap */ 2671 tipg = E1000_READ_REG(hw, TIPG); 2672 tipg &= ~E1000_TIPG_IPGT_MASK; 2673 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100; 2674 E1000_WRITE_REG(hw, TIPG, tipg); 2675 2676 ret_val = em_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); 2677 2678 if (ret_val) 2679 return ret_val; 2680 2681 if (duplex == HALF_DUPLEX) 2682 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER; 2683 else 2684 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 2685 2686 ret_val = em_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 2687 2688 return ret_val; 2689 } 2690 2691 static int32_t 2692 em_configure_kmrn_for_1000(struct em_hw *hw) 2693 { 2694 int32_t ret_val = E1000_SUCCESS; 2695 uint16_t reg_data; 2696 uint32_t tipg; 2697 DEBUGFUNC("em_configure_kmrn_for_1000"); 2698 2699 reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT; 2700 ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL, 2701 reg_data); 2702 if (ret_val) 2703 return ret_val; 2704 2705 /* Configure Transmit Inter-Packet Gap */ 2706 tipg = E1000_READ_REG(hw, TIPG); 2707 tipg &= ~E1000_TIPG_IPGT_MASK; 2708 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; 2709 E1000_WRITE_REG(hw, TIPG, tipg); 2710 2711 ret_val = em_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); 2712 2713 if (ret_val) 2714 return ret_val; 2715 2716 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 2717 ret_val = em_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 2718 2719 return ret_val; 2720 } 2721 2722 /****************************************************************************** 2723 * Configures PHY autoneg and flow control advertisement settings 2724 * 2725 * hw - Struct containing variables accessed by shared code 2726 *****************************************************************************/ 2727 int32_t 2728 em_phy_setup_autoneg(struct em_hw *hw) 2729 { 2730 int32_t ret_val; 2731 uint16_t mii_autoneg_adv_reg; 2732 uint16_t mii_1000t_ctrl_reg; 2733 DEBUGFUNC("em_phy_setup_autoneg"); 2734 2735 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 2736 ret_val = em_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 2737 if (ret_val) 2738 return ret_val; 2739 2740 if (hw->phy_type != em_phy_ife) { 2741 /* Read the MII 1000Base-T Control Register (Address 9). */ 2742 ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, 2743 &mii_1000t_ctrl_reg); 2744 if (ret_val) 2745 return ret_val; 2746 } else 2747 mii_1000t_ctrl_reg = 0; 2748 /* 2749 * Need to parse both autoneg_advertised and fc and set up the 2750 * appropriate PHY registers. First we will parse for 2751 * autoneg_advertised software override. Since we can advertise a 2752 * plethora of combinations, we need to check each bit individually. 2753 */ 2754 /* 2755 * First we clear all the 10/100 mb speed bits in the Auto-Neg 2756 * Advertisement Register (Address 4) and the 1000 mb speed bits in 2757 * the 1000Base-T Control Register (Address 9). 2758 */ 2759 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK; 2760 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK; 2761 2762 DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised); 2763 2764 /* Do we want to advertise 10 Mb Half Duplex? */ 2765 if (hw->autoneg_advertised & ADVERTISE_10_HALF) { 2766 DEBUGOUT("Advertise 10mb Half duplex\n"); 2767 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 2768 } 2769 /* Do we want to advertise 10 Mb Full Duplex? */ 2770 if (hw->autoneg_advertised & ADVERTISE_10_FULL) { 2771 DEBUGOUT("Advertise 10mb Full duplex\n"); 2772 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 2773 } 2774 /* Do we want to advertise 100 Mb Half Duplex? */ 2775 if (hw->autoneg_advertised & ADVERTISE_100_HALF) { 2776 DEBUGOUT("Advertise 100mb Half duplex\n"); 2777 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 2778 } 2779 /* Do we want to advertise 100 Mb Full Duplex? */ 2780 if (hw->autoneg_advertised & ADVERTISE_100_FULL) { 2781 DEBUGOUT("Advertise 100mb Full duplex\n"); 2782 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 2783 } 2784 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 2785 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) { 2786 DEBUGOUT("Advertise 1000mb Half duplex requested, request" 2787 " denied!\n"); 2788 } 2789 /* Do we want to advertise 1000 Mb Full Duplex? */ 2790 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) { 2791 DEBUGOUT("Advertise 1000mb Full duplex\n"); 2792 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 2793 if (hw->phy_type == em_phy_ife) { 2794 DEBUGOUT("em_phy_ife is a 10/100 PHY. Gigabit speed is" 2795 " not supported.\n"); 2796 } 2797 } 2798 /* 2799 * Check for a software override of the flow control settings, and 2800 * setup the PHY advertisement registers accordingly. If 2801 * auto-negotiation is enabled, then software will have to set the 2802 * "PAUSE" bits to the correct value in the Auto-Negotiation 2803 * Advertisement Register (PHY_AUTONEG_ADV) and re-start 2804 * auto-negotiation. 2805 * 2806 * The possible values of the "fc" parameter are: 0: Flow control is 2807 * completely disabled 1: Rx flow control is enabled (we can receive 2808 * pause frames but not send pause frames). 2: Tx flow control is 2809 * enabled (we can send pause frames but we do not support receiving 2810 * pause frames). 3: Both Rx and TX flow control (symmetric) are 2811 * enabled. other: No software override. The flow control 2812 * configuration in the EEPROM is used. 2813 */ 2814 switch (hw->fc) { 2815 case E1000_FC_NONE: /* 0 */ 2816 /* 2817 * Flow control (RX & TX) is completely disabled by a 2818 * software over-ride. 2819 */ 2820 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 2821 break; 2822 case E1000_FC_RX_PAUSE:/* 1 */ 2823 /* 2824 * RX Flow control is enabled, and TX Flow control is 2825 * disabled, by a software over-ride. 2826 */ 2827 /* 2828 * Since there really isn't a way to advertise that we are 2829 * capable of RX Pause ONLY, we will advertise that we 2830 * support both symmetric and asymmetric RX PAUSE. Later (in 2831 * em_config_fc_after_link_up) we will disable the hw's 2832 * ability to send PAUSE frames. 2833 */ 2834 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 2835 break; 2836 case E1000_FC_TX_PAUSE:/* 2 */ 2837 /* 2838 * TX Flow control is enabled, and RX Flow control is 2839 * disabled, by a software over-ride. 2840 */ 2841 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 2842 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 2843 break; 2844 case E1000_FC_FULL: /* 3 */ 2845 /* 2846 * Flow control (both RX and TX) is enabled by a software 2847 * over-ride. 2848 */ 2849 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 2850 break; 2851 default: 2852 DEBUGOUT("Flow control param set incorrectly\n"); 2853 return -E1000_ERR_CONFIG; 2854 } 2855 2856 ret_val = em_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 2857 if (ret_val) 2858 return ret_val; 2859 2860 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 2861 2862 if (hw->phy_type != em_phy_ife) { 2863 ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL, 2864 mii_1000t_ctrl_reg); 2865 if (ret_val) 2866 return ret_val; 2867 } 2868 return E1000_SUCCESS; 2869 } 2870 /****************************************************************************** 2871 * Force PHY speed and duplex settings to hw->forced_speed_duplex 2872 * 2873 * hw - Struct containing variables accessed by shared code 2874 *****************************************************************************/ 2875 static int32_t 2876 em_phy_force_speed_duplex(struct em_hw *hw) 2877 { 2878 uint32_t ctrl; 2879 int32_t ret_val; 2880 uint16_t mii_ctrl_reg; 2881 uint16_t mii_status_reg; 2882 uint16_t phy_data; 2883 uint16_t i; 2884 DEBUGFUNC("em_phy_force_speed_duplex"); 2885 2886 /* Turn off Flow control if we are forcing speed and duplex. */ 2887 hw->fc = E1000_FC_NONE; 2888 2889 DEBUGOUT1("hw->fc = %d\n", hw->fc); 2890 2891 /* Read the Device Control Register. */ 2892 ctrl = E1000_READ_REG(hw, CTRL); 2893 2894 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */ 2895 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 2896 ctrl &= ~(DEVICE_SPEED_MASK); 2897 2898 /* Clear the Auto Speed Detect Enable bit. */ 2899 ctrl &= ~E1000_CTRL_ASDE; 2900 2901 /* Read the MII Control Register. */ 2902 ret_val = em_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg); 2903 if (ret_val) 2904 return ret_val; 2905 2906 /* We need to disable autoneg in order to force link and duplex. */ 2907 2908 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN; 2909 2910 /* Are we forcing Full or Half Duplex? */ 2911 if (hw->forced_speed_duplex == em_100_full || 2912 hw->forced_speed_duplex == em_10_full) { 2913 /* 2914 * We want to force full duplex so we SET the full duplex 2915 * bits in the Device and MII Control Registers. 2916 */ 2917 ctrl |= E1000_CTRL_FD; 2918 mii_ctrl_reg |= MII_CR_FULL_DUPLEX; 2919 DEBUGOUT("Full Duplex\n"); 2920 } else { 2921 /* 2922 * We want to force half duplex so we CLEAR the full duplex 2923 * bits in the Device and MII Control Registers. 2924 */ 2925 ctrl &= ~E1000_CTRL_FD; 2926 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX; 2927 DEBUGOUT("Half Duplex\n"); 2928 } 2929 2930 /* Are we forcing 100Mbps??? */ 2931 if (hw->forced_speed_duplex == em_100_full || 2932 hw->forced_speed_duplex == em_100_half) { 2933 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */ 2934 ctrl |= E1000_CTRL_SPD_100; 2935 mii_ctrl_reg |= MII_CR_SPEED_100; 2936 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); 2937 DEBUGOUT("Forcing 100mb "); 2938 } else { 2939 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */ 2940 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 2941 mii_ctrl_reg |= MII_CR_SPEED_10; 2942 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); 2943 DEBUGOUT("Forcing 10mb "); 2944 } 2945 2946 em_config_collision_dist(hw); 2947 2948 /* Write the configured values back to the Device Control Reg. */ 2949 E1000_WRITE_REG(hw, CTRL, ctrl); 2950 2951 if ((hw->phy_type == em_phy_m88) || 2952 (hw->phy_type == em_phy_gg82563) || 2953 (hw->phy_type == em_phy_bm) || 2954 (hw->phy_type == em_phy_oem || 2955 (hw->phy_type == em_phy_82578))) { 2956 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 2957 &phy_data); 2958 if (ret_val) 2959 return ret_val; 2960 /* 2961 * Clear Auto-Crossover to force MDI manually. M88E1000 2962 * requires MDI forced whenever speed are duplex are forced. 2963 */ 2964 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 2965 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 2966 phy_data); 2967 if (ret_val) 2968 return ret_val; 2969 2970 DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data); 2971 2972 /* Need to reset the PHY or these changes will be ignored */ 2973 mii_ctrl_reg |= MII_CR_RESET; 2974 2975 } 2976 /* Disable MDI-X support for 10/100 */ 2977 else if (hw->phy_type == em_phy_ife) { 2978 ret_val = em_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data); 2979 if (ret_val) 2980 return ret_val; 2981 2982 phy_data &= ~IFE_PMC_AUTO_MDIX; 2983 phy_data &= ~IFE_PMC_FORCE_MDIX; 2984 2985 ret_val = em_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, phy_data); 2986 if (ret_val) 2987 return ret_val; 2988 } else { 2989 /* 2990 * Clear Auto-Crossover to force MDI manually. IGP requires 2991 * MDI forced whenever speed or duplex are forced. 2992 */ 2993 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, 2994 &phy_data); 2995 if (ret_val) 2996 return ret_val; 2997 2998 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 2999 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 3000 3001 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, 3002 phy_data); 3003 if (ret_val) 3004 return ret_val; 3005 } 3006 3007 /* Write back the modified PHY MII control register. */ 3008 ret_val = em_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg); 3009 if (ret_val) 3010 return ret_val; 3011 3012 usec_delay(1); 3013 /* 3014 * The wait_autoneg_complete flag may be a little misleading here. 3015 * Since we are forcing speed and duplex, Auto-Neg is not enabled. 3016 * But we do want to delay for a period while forcing only so we 3017 * don't generate false No Link messages. So we will wait here only 3018 * if the user has set wait_autoneg_complete to 1, which is the 3019 * default. 3020 */ 3021 if (hw->wait_autoneg_complete) { 3022 /* We will wait for autoneg to complete. */ 3023 DEBUGOUT("Waiting for forced speed/duplex link.\n"); 3024 mii_status_reg = 0; 3025 /* 3026 * We will wait for autoneg to complete or 4.5 seconds to 3027 * expire. 3028 */ 3029 for (i = PHY_FORCE_TIME; i > 0; i--) { 3030 /* 3031 * Read the MII Status Register and wait for Auto-Neg 3032 * Complete bit to be set. 3033 */ 3034 ret_val = em_read_phy_reg(hw, PHY_STATUS, 3035 &mii_status_reg); 3036 if (ret_val) 3037 return ret_val; 3038 3039 ret_val = em_read_phy_reg(hw, PHY_STATUS, 3040 &mii_status_reg); 3041 if (ret_val) 3042 return ret_val; 3043 3044 if (mii_status_reg & MII_SR_LINK_STATUS) 3045 break; 3046 msec_delay(100); 3047 } 3048 if ((i == 0) && 3049 ((hw->phy_type == em_phy_m88) || 3050 (hw->phy_type == em_phy_gg82563) || 3051 (hw->phy_type == em_phy_bm))) { 3052 /* 3053 * We didn't get link. Reset the DSP and wait again 3054 * for link. 3055 */ 3056 ret_val = em_phy_reset_dsp(hw); 3057 if (ret_val) { 3058 DEBUGOUT("Error Resetting PHY DSP\n"); 3059 return ret_val; 3060 } 3061 } 3062 /* 3063 * This loop will early-out if the link condition has been 3064 * met. 3065 */ 3066 for (i = PHY_FORCE_TIME; i > 0; i--) { 3067 if (mii_status_reg & MII_SR_LINK_STATUS) 3068 break; 3069 msec_delay(100); 3070 /* 3071 * Read the MII Status Register and wait for Auto-Neg 3072 * Complete bit to be set. 3073 */ 3074 ret_val = em_read_phy_reg(hw, PHY_STATUS, 3075 &mii_status_reg); 3076 if (ret_val) 3077 return ret_val; 3078 3079 ret_val = em_read_phy_reg(hw, PHY_STATUS, 3080 &mii_status_reg); 3081 if (ret_val) 3082 return ret_val; 3083 } 3084 } 3085 if (hw->phy_type == em_phy_m88 || 3086 hw->phy_type == em_phy_bm || 3087 hw->phy_type == em_phy_oem) { 3088 /* 3089 * Because we reset the PHY above, we need to re-force TX_CLK 3090 * in the Extended PHY Specific Control Register to 25MHz 3091 * clock. This value defaults back to a 2.5MHz clock when 3092 * the PHY is reset. 3093 */ 3094 ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 3095 &phy_data); 3096 if (ret_val) 3097 return ret_val; 3098 3099 phy_data |= M88E1000_EPSCR_TX_CLK_25; 3100 ret_val = em_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 3101 phy_data); 3102 if (ret_val) 3103 return ret_val; 3104 /* 3105 * In addition, because of the s/w reset above, we need to 3106 * enable CRS on TX. This must be set for both full and half 3107 * duplex operation. 3108 */ 3109 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 3110 &phy_data); 3111 if (ret_val) 3112 return ret_val; 3113 3114 if (hw->phy_id == M88E1141_E_PHY_ID) 3115 phy_data &= ~M88E1000_PSCR_ASSERT_CRS_ON_TX; 3116 else 3117 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 3118 3119 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 3120 phy_data); 3121 if (ret_val) 3122 return ret_val; 3123 3124 if ((hw->mac_type == em_82544 || hw->mac_type == em_82543) && 3125 (!hw->autoneg) && (hw->forced_speed_duplex == em_10_full || 3126 hw->forced_speed_duplex == em_10_half)) { 3127 ret_val = em_polarity_reversal_workaround(hw); 3128 if (ret_val) 3129 return ret_val; 3130 } 3131 } else if (hw->phy_type == em_phy_gg82563) { 3132 /* 3133 * The TX_CLK of the Extended PHY Specific Control Register 3134 * defaults to 2.5MHz on a reset. We need to re-force it 3135 * back to 25MHz, if we're not in a forced 10/duplex 3136 * configuration. 3137 */ 3138 ret_val = em_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 3139 &phy_data); 3140 if (ret_val) 3141 return ret_val; 3142 3143 phy_data &= ~GG82563_MSCR_TX_CLK_MASK; 3144 if ((hw->forced_speed_duplex == em_10_full) || 3145 (hw->forced_speed_duplex == em_10_half)) 3146 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ; 3147 else 3148 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25MHZ; 3149 3150 /* Also due to the reset, we need to enable CRS on Tx. */ 3151 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 3152 3153 ret_val = em_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 3154 phy_data); 3155 if (ret_val) 3156 return ret_val; 3157 } 3158 return E1000_SUCCESS; 3159 } 3160 3161 /****************************************************************************** 3162 * Sets the collision distance in the Transmit Control register 3163 * 3164 * hw - Struct containing variables accessed by shared code 3165 * 3166 * Link should have been established previously. Reads the speed and duplex 3167 * information from the Device Status register. 3168 *****************************************************************************/ 3169 void 3170 em_config_collision_dist(struct em_hw *hw) 3171 { 3172 uint32_t tctl, coll_dist; 3173 DEBUGFUNC("em_config_collision_dist"); 3174 3175 if (hw->mac_type < em_82543) 3176 coll_dist = E1000_COLLISION_DISTANCE_82542; 3177 else 3178 coll_dist = E1000_COLLISION_DISTANCE; 3179 3180 tctl = E1000_READ_REG(hw, TCTL); 3181 3182 tctl &= ~E1000_TCTL_COLD; 3183 tctl |= coll_dist << E1000_COLD_SHIFT; 3184 3185 E1000_WRITE_REG(hw, TCTL, tctl); 3186 E1000_WRITE_FLUSH(hw); 3187 } 3188 3189 /****************************************************************************** 3190 * Sets MAC speed and duplex settings to reflect the those in the PHY 3191 * 3192 * hw - Struct containing variables accessed by shared code 3193 * mii_reg - data to write to the MII control register 3194 * 3195 * The contents of the PHY register containing the needed information need to 3196 * be passed in. 3197 *****************************************************************************/ 3198 static int32_t 3199 em_config_mac_to_phy(struct em_hw *hw) 3200 { 3201 uint32_t ctrl; 3202 int32_t ret_val; 3203 uint16_t phy_data; 3204 DEBUGFUNC("em_config_mac_to_phy"); 3205 /* 3206 * 82544 or newer MAC, Auto Speed Detection takes care of MAC 3207 * speed/duplex configuration. 3208 */ 3209 if (hw->mac_type >= em_82544 3210 && hw->mac_type != em_icp_xxxx) 3211 return E1000_SUCCESS; 3212 /* 3213 * Read the Device Control Register and set the bits to Force Speed 3214 * and Duplex. 3215 */ 3216 ctrl = E1000_READ_REG(hw, CTRL); 3217 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 3218 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); 3219 /* 3220 * Set up duplex in the Device Control and Transmit Control registers 3221 * depending on negotiated values. 3222 */ 3223 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 3224 if (ret_val) 3225 return ret_val; 3226 3227 if (phy_data & M88E1000_PSSR_DPLX) 3228 ctrl |= E1000_CTRL_FD; 3229 else 3230 ctrl &= ~E1000_CTRL_FD; 3231 3232 em_config_collision_dist(hw); 3233 /* 3234 * Set up speed in the Device Control register depending on 3235 * negotiated values. 3236 */ 3237 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) 3238 ctrl |= E1000_CTRL_SPD_1000; 3239 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) 3240 ctrl |= E1000_CTRL_SPD_100; 3241 3242 /* Write the configured values back to the Device Control Reg. */ 3243 E1000_WRITE_REG(hw, CTRL, ctrl); 3244 return E1000_SUCCESS; 3245 } 3246 3247 /****************************************************************************** 3248 * Forces the MAC's flow control settings. 3249 * 3250 * hw - Struct containing variables accessed by shared code 3251 * 3252 * Sets the TFCE and RFCE bits in the device control register to reflect 3253 * the adapter settings. TFCE and RFCE need to be explicitly set by 3254 * software when a Copper PHY is used because autonegotiation is managed 3255 * by the PHY rather than the MAC. Software must also configure these 3256 * bits when link is forced on a fiber connection. 3257 *****************************************************************************/ 3258 int32_t 3259 em_force_mac_fc(struct em_hw *hw) 3260 { 3261 uint32_t ctrl; 3262 DEBUGFUNC("em_force_mac_fc"); 3263 3264 /* Get the current configuration of the Device Control Register */ 3265 ctrl = E1000_READ_REG(hw, CTRL); 3266 /* 3267 * Because we didn't get link via the internal auto-negotiation 3268 * mechanism (we either forced link or we got link via PHY auto-neg), 3269 * we have to manually enable/disable transmit an receive flow 3270 * control. 3271 * 3272 * The "Case" statement below enables/disable flow control according to 3273 * the "hw->fc" parameter. 3274 * 3275 * The possible values of the "fc" parameter are: 0: Flow control is 3276 * completely disabled 1: Rx flow control is enabled (we can receive 3277 * pause frames but not send pause frames). 2: Tx flow control is 3278 * enabled (we can send pause frames frames but we do not receive 3279 * pause frames). 3: Both Rx and TX flow control (symmetric) is 3280 * enabled. other: No other values should be possible at this point. 3281 */ 3282 3283 switch (hw->fc) { 3284 case E1000_FC_NONE: 3285 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 3286 break; 3287 case E1000_FC_RX_PAUSE: 3288 ctrl &= (~E1000_CTRL_TFCE); 3289 ctrl |= E1000_CTRL_RFCE; 3290 break; 3291 case E1000_FC_TX_PAUSE: 3292 ctrl &= (~E1000_CTRL_RFCE); 3293 ctrl |= E1000_CTRL_TFCE; 3294 break; 3295 case E1000_FC_FULL: 3296 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 3297 break; 3298 default: 3299 DEBUGOUT("Flow control param set incorrectly\n"); 3300 return -E1000_ERR_CONFIG; 3301 } 3302 3303 /* Disable TX Flow Control for 82542 (rev 2.0) */ 3304 if (hw->mac_type == em_82542_rev2_0) 3305 ctrl &= (~E1000_CTRL_TFCE); 3306 3307 E1000_WRITE_REG(hw, CTRL, ctrl); 3308 return E1000_SUCCESS; 3309 } 3310 /****************************************************************************** 3311 * Configures flow control settings after link is established 3312 * 3313 * hw - Struct containing variables accessed by shared code 3314 * 3315 * Should be called immediately after a valid link has been established. 3316 * Forces MAC flow control settings if link was forced. When in MII/GMII mode 3317 * and autonegotiation is enabled, the MAC flow control settings will be set 3318 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE 3319 * and RFCE bits will be automaticaly set to the negotiated flow control mode. 3320 *****************************************************************************/ 3321 STATIC int32_t 3322 em_config_fc_after_link_up(struct em_hw *hw) 3323 { 3324 int32_t ret_val; 3325 uint16_t mii_status_reg; 3326 uint16_t mii_nway_adv_reg; 3327 uint16_t mii_nway_lp_ability_reg; 3328 uint16_t speed; 3329 uint16_t duplex; 3330 DEBUGFUNC("em_config_fc_after_link_up"); 3331 /* 3332 * Check for the case where we have fiber media and auto-neg failed 3333 * so we had to force link. In this case, we need to force the 3334 * configuration of the MAC to match the "fc" parameter. 3335 */ 3336 if (((hw->media_type == em_media_type_fiber) && (hw->autoneg_failed)) 3337 || ((hw->media_type == em_media_type_internal_serdes) && 3338 (hw->autoneg_failed)) || 3339 ((hw->media_type == em_media_type_copper) && (!hw->autoneg)) || 3340 ((hw->media_type == em_media_type_oem) && (!hw->autoneg))) { 3341 ret_val = em_force_mac_fc(hw); 3342 if (ret_val) { 3343 DEBUGOUT("Error forcing flow control settings\n"); 3344 return ret_val; 3345 } 3346 } 3347 /* 3348 * Check for the case where we have copper media and auto-neg is 3349 * enabled. In this case, we need to check and see if Auto-Neg has 3350 * completed, and if so, how the PHY and link partner has flow 3351 * control configured. 3352 */ 3353 if ((hw->media_type == em_media_type_copper || 3354 (hw->media_type == em_media_type_oem)) && 3355 hw->autoneg) { 3356 /* 3357 * Read the MII Status Register and check to see if AutoNeg 3358 * has completed. We read this twice because this reg has 3359 * some "sticky" (latched) bits. 3360 */ 3361 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 3362 if (ret_val) 3363 return ret_val; 3364 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 3365 if (ret_val) 3366 return ret_val; 3367 3368 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) { 3369 /* 3370 * The AutoNeg process has completed, so we now need 3371 * to read both the Auto Negotiation Advertisement 3372 * Register (Address 4) and the Auto_Negotiation Base 3373 * Page Ability Register (Address 5) to determine how 3374 * flow control was negotiated. 3375 */ 3376 ret_val = em_read_phy_reg(hw, PHY_AUTONEG_ADV, 3377 &mii_nway_adv_reg); 3378 if (ret_val) 3379 return ret_val; 3380 ret_val = em_read_phy_reg(hw, PHY_LP_ABILITY, 3381 &mii_nway_lp_ability_reg); 3382 if (ret_val) 3383 return ret_val; 3384 /* 3385 * Two bits in the Auto Negotiation Advertisement 3386 * Register (Address 4) and two bits in the Auto 3387 * Negotiation Base Page Ability Register (Address 5) 3388 * determine flow control for both the PHY and the 3389 * link partner. The following table, taken out of 3390 * the IEEE 802.3ab/D6.0 dated March 25, 1999, 3391 * describes these PAUSE resolution bits and how flow 3392 * control is determined based upon these settings. 3393 * NOTE: DC = Don't Care 3394 * 3395 * LOCAL DEVICE | LINK PARTNER | 3396 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 3397 * -------|---------|-------|---------|--------------- 3398 * 0 | 0 | DC | DC | em_fc_none 3399 * 0 | 1 | 0 | DC | em_fc_none 3400 * 0 | 1 | 1 | 0 | em_fc_none 3401 * 0 | 1 | 1 | 1 | em_fc_tx_pause 3402 * 1 | 0 | 0 | DC | em_fc_none 3403 * 1 | DC | 1 | DC | em_fc_full 3404 * 1 | 1 | 0 | 0 | em_fc_none 3405 * 1 | 1 | 0 | 1 | em_fc_rx_pause 3406 * 3407 */ 3408 /* 3409 * Are both PAUSE bits set to 1? If so, this implies 3410 * Symmetric Flow Control is enabled at both ends. 3411 * The ASM_DIR bits are irrelevant per the spec. 3412 * 3413 * For Symmetric Flow Control: 3414 * 3415 * LOCAL DEVICE | LINK PARTNER 3416 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 3417 * -------|---------|-------|---------|--------------- 3418 * 1 | DC | 1 | DC | em_fc_full 3419 * 3420 */ 3421 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 3422 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 3423 /* 3424 * Now we need to check if the user selected 3425 * RX ONLY of pause frames. In this case, we 3426 * had to advertise FULL flow control because 3427 * we could not advertise RX ONLY. Hence, we 3428 * must now check to see if we need to turn 3429 * OFF the TRANSMISSION of PAUSE frames. 3430 */ 3431 if (hw->original_fc == E1000_FC_FULL) { 3432 hw->fc = E1000_FC_FULL; 3433 DEBUGOUT("Flow Control = FULL.\n"); 3434 } else { 3435 hw->fc = E1000_FC_RX_PAUSE; 3436 DEBUGOUT("Flow Control = RX PAUSE" 3437 " frames only.\n"); 3438 } 3439 } 3440 /* 3441 * For receiving PAUSE frames ONLY. 3442 * 3443 * LOCAL DEVICE | LINK PARTNER PAUSE | ASM_DIR | 3444 * PAUSE | ASM_DIR | Result 3445 * -------|---------|-------|---------|--------------- 3446 * ----- 0 | 1 | 1 | 1 | 3447 * em_fc_tx_pause 3448 * 3449 */ 3450 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 3451 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 3452 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 3453 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 3454 hw->fc = E1000_FC_TX_PAUSE; 3455 DEBUGOUT("Flow Control = TX PAUSE frames only." 3456 "\n"); 3457 } 3458 /* 3459 * For transmitting PAUSE frames ONLY. 3460 * 3461 * LOCAL DEVICE | LINK PARTNER 3462 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 3463 * -------|---------|-------|---------|--------------- 3464 * 1 | 1 | 0 | 1 | em_fc_rx_pause 3465 * 3466 */ 3467 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 3468 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 3469 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 3470 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 3471 hw->fc = E1000_FC_RX_PAUSE; 3472 DEBUGOUT("Flow Control = RX PAUSE frames only." 3473 "\n"); 3474 } 3475 /* 3476 * Per the IEEE spec, at this point flow control 3477 * should be disabled. However, we want to consider 3478 * that we could be connected to a legacy switch that 3479 * doesn't advertise desired flow control, but can be 3480 * forced on the link partner. So if we advertised 3481 * no flow control, that is what we will resolve to. 3482 * If we advertised some kind of receive capability 3483 * (Rx Pause Only or Full Flow Control) and the link 3484 * partner advertised none, we will configure 3485 * ourselves to enable Rx Flow Control only. We can 3486 * do this safely for two reasons: If the link 3487 * partner really didn't want flow control enabled, 3488 * and we enable Rx, no harm done since we won't be 3489 * receiving any PAUSE frames anyway. If the intent 3490 * on the link partner was to have flow control 3491 * enabled, then by us enabling RX only, we can at 3492 * least receive pause frames and process them. This 3493 * is a good idea because in most cases, since we are 3494 * predominantly a server NIC, more times than not we 3495 * will be asked to delay transmission of packets 3496 * than asking our link partner to pause transmission 3497 * of frames. 3498 */ 3499 else if ((hw->original_fc == E1000_FC_NONE || 3500 hw->original_fc == E1000_FC_TX_PAUSE) || 3501 hw->fc_strict_ieee) { 3502 hw->fc = E1000_FC_NONE; 3503 DEBUGOUT("Flow Control = NONE.\n"); 3504 } else { 3505 hw->fc = E1000_FC_RX_PAUSE; 3506 DEBUGOUT("Flow Control = RX PAUSE frames only." 3507 "\n"); 3508 } 3509 /* 3510 * Now we need to do one last check... If we auto- 3511 * negotiated to HALF DUPLEX, flow control should not 3512 * be enabled per IEEE 802.3 spec. 3513 */ 3514 ret_val = em_get_speed_and_duplex(hw, &speed, &duplex); 3515 if (ret_val) { 3516 DEBUGOUT("Error getting link speed and duplex" 3517 "\n"); 3518 return ret_val; 3519 } 3520 if (duplex == HALF_DUPLEX) 3521 hw->fc = E1000_FC_NONE; 3522 /* 3523 * Now we call a subroutine to actually force the MAC 3524 * controller to use the correct flow control 3525 * settings. 3526 */ 3527 ret_val = em_force_mac_fc(hw); 3528 if (ret_val) { 3529 DEBUGOUT("Error forcing flow control settings" 3530 "\n"); 3531 return ret_val; 3532 } 3533 } else { 3534 DEBUGOUT("Copper PHY and Auto Neg has not completed." 3535 "\n"); 3536 } 3537 } 3538 return E1000_SUCCESS; 3539 } 3540 /****************************************************************************** 3541 * Checks to see if the link status of the hardware has changed. 3542 * 3543 * hw - Struct containing variables accessed by shared code 3544 * 3545 * Called by any function that needs to check the link status of the adapter. 3546 *****************************************************************************/ 3547 int32_t 3548 em_check_for_link(struct em_hw *hw) 3549 { 3550 uint32_t rxcw = 0; 3551 uint32_t ctrl; 3552 uint32_t status; 3553 uint32_t rctl; 3554 uint32_t icr; 3555 uint32_t signal = 0; 3556 int32_t ret_val; 3557 uint16_t phy_data; 3558 DEBUGFUNC("em_check_for_link"); 3559 uint16_t speed, duplex; 3560 3561 if (hw->mac_type == em_82575 && 3562 hw->media_type != em_media_type_copper) { 3563 ret_val = em_get_pcs_speed_and_duplex_82575(hw, &speed, 3564 &duplex); 3565 hw->get_link_status = hw->serdes_link_down; 3566 3567 return (ret_val); 3568 } 3569 3570 ctrl = E1000_READ_REG(hw, CTRL); 3571 status = E1000_READ_REG(hw, STATUS); 3572 /* 3573 * On adapters with a MAC newer than 82544, SW Defineable pin 1 will 3574 * be set when the optics detect a signal. On older adapters, it will 3575 * be cleared when there is a signal. This applies to fiber media 3576 * only. 3577 */ 3578 if ((hw->media_type == em_media_type_fiber) || 3579 (hw->media_type == em_media_type_internal_serdes)) { 3580 rxcw = E1000_READ_REG(hw, RXCW); 3581 3582 if (hw->media_type == em_media_type_fiber) { 3583 signal = (hw->mac_type > em_82544) ? 3584 E1000_CTRL_SWDPIN1 : 0; 3585 if (status & E1000_STATUS_LU) 3586 hw->get_link_status = FALSE; 3587 } 3588 } 3589 /* 3590 * If we have a copper PHY then we only want to go out to the PHY 3591 * registers to see if Auto-Neg has completed and/or if our link 3592 * status has changed. The get_link_status flag will be set if we 3593 * receive a Link Status Change interrupt or we have Rx Sequence 3594 * Errors. 3595 */ 3596 if ((hw->media_type == em_media_type_copper || 3597 (hw->media_type == em_media_type_oem)) && 3598 hw->get_link_status) { 3599 /* 3600 * First we want to see if the MII Status Register reports 3601 * link. If so, then we want to get the current speed/duplex 3602 * of the PHY. Read the register twice since the link bit is 3603 * sticky. 3604 */ 3605 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 3606 if (ret_val) 3607 return ret_val; 3608 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 3609 if (ret_val) 3610 return ret_val; 3611 3612 hw->icp_xxxx_is_link_up = (phy_data & MII_SR_LINK_STATUS) != 0; 3613 3614 if (hw->mac_type == em_pchlan) { 3615 ret_val = em_k1_gig_workaround_hv(hw, 3616 hw->icp_xxxx_is_link_up); 3617 if (ret_val) 3618 return ret_val; 3619 } 3620 3621 if (phy_data & MII_SR_LINK_STATUS) { 3622 hw->get_link_status = FALSE; 3623 3624 if (hw->phy_type == em_phy_82578) { 3625 ret_val = em_link_stall_workaround_hv(hw); 3626 if (ret_val) 3627 return ret_val; 3628 } 3629 3630 if (hw->mac_type == em_pch2lan) { 3631 ret_val = em_k1_workaround_lv(hw); 3632 if (ret_val) 3633 return ret_val; 3634 } 3635 3636 /* 3637 * Check if there was DownShift, must be checked 3638 * immediately after link-up 3639 */ 3640 em_check_downshift(hw); 3641 3642 /* 3643 * If we are on 82544 or 82543 silicon and 3644 * speed/duplex are forced to 10H or 10F, then we 3645 * will implement the polarity reversal workaround. 3646 * We disable interrupts first, and upon returning, 3647 * place the devices interrupt state to its previous 3648 * value except for the link status change interrupt 3649 * which will happen due to the execution of this 3650 * workaround. 3651 */ 3652 if ((hw->mac_type == em_82544 || 3653 hw->mac_type == em_82543) && (!hw->autoneg) && 3654 (hw->forced_speed_duplex == em_10_full || 3655 hw->forced_speed_duplex == em_10_half)) { 3656 E1000_WRITE_REG(hw, IMC, 0xffffffff); 3657 ret_val = em_polarity_reversal_workaround(hw); 3658 icr = E1000_READ_REG(hw, ICR); 3659 E1000_WRITE_REG(hw, ICS, 3660 (icr & ~E1000_ICS_LSC)); 3661 E1000_WRITE_REG(hw, IMS, IMS_ENABLE_MASK); 3662 } 3663 } else { 3664 /* No link detected */ 3665 em_config_dsp_after_link_change(hw, FALSE); 3666 return 0; 3667 } 3668 /* 3669 * If we are forcing speed/duplex, then we simply return 3670 * since we have already determined whether we have link or 3671 * not. 3672 */ 3673 if (!hw->autoneg) 3674 return -E1000_ERR_CONFIG; 3675 3676 /* optimize the dsp settings for the igp phy */ 3677 em_config_dsp_after_link_change(hw, TRUE); 3678 /* 3679 * We have a M88E1000 PHY and Auto-Neg is enabled. If we 3680 * have Si on board that is 82544 or newer, Auto Speed 3681 * Detection takes care of MAC speed/duplex configuration. 3682 * So we only need to configure Collision Distance in the 3683 * MAC. Otherwise, we need to force speed/duplex on the MAC 3684 * to the current PHY speed/duplex settings. 3685 */ 3686 if (hw->mac_type >= em_82544 && hw->mac_type != em_icp_xxxx) 3687 em_config_collision_dist(hw); 3688 else { 3689 ret_val = em_config_mac_to_phy(hw); 3690 if (ret_val) { 3691 DEBUGOUT("Error configuring MAC to PHY" 3692 " settings\n"); 3693 return ret_val; 3694 } 3695 } 3696 /* 3697 * Configure Flow Control now that Auto-Neg has completed. 3698 * First, we need to restore the desired flow control 3699 * settings because we may have had to re-autoneg with a 3700 * different link partner. 3701 */ 3702 ret_val = em_config_fc_after_link_up(hw); 3703 if (ret_val) { 3704 DEBUGOUT("Error configuring flow control\n"); 3705 return ret_val; 3706 } 3707 /* 3708 * At this point we know that we are on copper and we have 3709 * auto-negotiated link. These are conditions for checking 3710 * the link partner capability register. We use the link 3711 * speed to determine if TBI compatibility needs to be turned 3712 * on or off. If the link is not at gigabit speed, then TBI 3713 * compatibility is not needed. If we are at gigabit speed, 3714 * we turn on TBI compatibility. 3715 */ 3716 if (hw->tbi_compatibility_en) { 3717 uint16_t speed, duplex; 3718 ret_val = em_get_speed_and_duplex(hw, &speed, &duplex); 3719 if (ret_val) { 3720 DEBUGOUT("Error getting link speed and duplex" 3721 "\n"); 3722 return ret_val; 3723 } 3724 if (speed != SPEED_1000) { 3725 /* 3726 * If link speed is not set to gigabit speed, 3727 * we do not need to enable TBI 3728 * compatibility. 3729 */ 3730 if (hw->tbi_compatibility_on) { 3731 /* 3732 * If we previously were in the mode, 3733 * turn it off. 3734 */ 3735 rctl = E1000_READ_REG(hw, RCTL); 3736 rctl &= ~E1000_RCTL_SBP; 3737 E1000_WRITE_REG(hw, RCTL, rctl); 3738 hw->tbi_compatibility_on = FALSE; 3739 } 3740 } else { 3741 /* 3742 * If TBI compatibility is was previously 3743 * off, turn it on. For compatibility with a 3744 * TBI link partner, we will store bad 3745 * packets. Some frames have an additional 3746 * byte on the end and will look like CRC 3747 * errors to to the hardware. 3748 */ 3749 if (!hw->tbi_compatibility_on) { 3750 hw->tbi_compatibility_on = TRUE; 3751 rctl = E1000_READ_REG(hw, RCTL); 3752 rctl |= E1000_RCTL_SBP; 3753 E1000_WRITE_REG(hw, RCTL, rctl); 3754 } 3755 } 3756 } 3757 } 3758 /* 3759 * If we don't have link (auto-negotiation failed or link partner 3760 * cannot auto-negotiate), the cable is plugged in (we have signal), 3761 * and our link partner is not trying to auto-negotiate with us (we 3762 * are receiving idles or data), we need to force link up. We also 3763 * need to give auto-negotiation time to complete, in case the cable 3764 * was just plugged in. The autoneg_failed flag does this. 3765 */ 3766 else if ((((hw->media_type == em_media_type_fiber) && 3767 ((ctrl & E1000_CTRL_SWDPIN1) == signal)) || 3768 (hw->media_type == em_media_type_internal_serdes)) && 3769 (!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) { 3770 if (hw->autoneg_failed == 0) { 3771 hw->autoneg_failed = 1; 3772 return 0; 3773 } 3774 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 3775 3776 /* Disable auto-negotiation in the TXCW register */ 3777 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE)); 3778 3779 /* Force link-up and also force full-duplex. */ 3780 ctrl = E1000_READ_REG(hw, CTRL); 3781 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 3782 E1000_WRITE_REG(hw, CTRL, ctrl); 3783 3784 /* Configure Flow Control after forcing link up. */ 3785 ret_val = em_config_fc_after_link_up(hw); 3786 if (ret_val) { 3787 DEBUGOUT("Error configuring flow control\n"); 3788 return ret_val; 3789 } 3790 } 3791 /* 3792 * If we are forcing link and we are receiving /C/ ordered sets, 3793 * re-enable auto-negotiation in the TXCW register and disable forced 3794 * link in the Device Control register in an attempt to 3795 * auto-negotiate with our link partner. 3796 */ 3797 else if (((hw->media_type == em_media_type_fiber) || 3798 (hw->media_type == em_media_type_internal_serdes)) && 3799 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 3800 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 3801 E1000_WRITE_REG(hw, TXCW, hw->txcw); 3802 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU)); 3803 3804 hw->serdes_link_down = FALSE; 3805 } 3806 /* 3807 * If we force link for non-auto-negotiation switch, check link 3808 * status based on MAC synchronization for internal serdes media 3809 * type. 3810 */ 3811 else if ((hw->media_type == em_media_type_internal_serdes) && 3812 !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) { 3813 /* SYNCH bit and IV bit are sticky. */ 3814 usec_delay(10); 3815 if (E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) { 3816 if (!(rxcw & E1000_RXCW_IV)) { 3817 hw->serdes_link_down = FALSE; 3818 DEBUGOUT("SERDES: Link is up.\n"); 3819 } 3820 } else { 3821 hw->serdes_link_down = TRUE; 3822 DEBUGOUT("SERDES: Link is down.\n"); 3823 } 3824 } 3825 if ((hw->media_type == em_media_type_internal_serdes) && 3826 (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) { 3827 hw->serdes_link_down = !(E1000_STATUS_LU & 3828 E1000_READ_REG(hw, STATUS)); 3829 } 3830 return E1000_SUCCESS; 3831 } 3832 3833 int32_t 3834 em_get_pcs_speed_and_duplex_82575(struct em_hw *hw, uint16_t *speed, 3835 uint16_t *duplex) 3836 { 3837 uint32_t pcs; 3838 3839 hw->serdes_link_down = TRUE; 3840 *speed = 0; 3841 *duplex = 0; 3842 3843 /* 3844 * Read the PCS Status register for link state. For non-copper mode, 3845 * the status register is not accurate. The PCS status register is 3846 * used instead. 3847 */ 3848 pcs = E1000_READ_REG(hw, PCS_LSTAT); 3849 3850 /* 3851 * The link up bit determines when link is up on autoneg. The sync ok 3852 * gets set once both sides sync up and agree upon link. Stable link 3853 * can be determined by checking for both link up and link sync ok 3854 */ 3855 if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) { 3856 hw->serdes_link_down = FALSE; 3857 3858 /* Detect and store PCS speed */ 3859 if (pcs & E1000_PCS_LSTS_SPEED_1000) { 3860 *speed = SPEED_1000; 3861 } else if (pcs & E1000_PCS_LSTS_SPEED_100) { 3862 *speed = SPEED_100; 3863 } else { 3864 *speed = SPEED_10; 3865 } 3866 3867 /* Detect and store PCS duplex */ 3868 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) { 3869 *duplex = FULL_DUPLEX; 3870 } else { 3871 *duplex = HALF_DUPLEX; 3872 } 3873 } 3874 3875 return (0); 3876 } 3877 3878 3879 /****************************************************************************** 3880 * Detects the current speed and duplex settings of the hardware. 3881 * 3882 * hw - Struct containing variables accessed by shared code 3883 * speed - Speed of the connection 3884 * duplex - Duplex setting of the connection 3885 *****************************************************************************/ 3886 int32_t 3887 em_get_speed_and_duplex(struct em_hw *hw, uint16_t *speed, uint16_t *duplex) 3888 { 3889 uint32_t status; 3890 int32_t ret_val; 3891 uint16_t phy_data; 3892 DEBUGFUNC("em_get_speed_and_duplex"); 3893 3894 if (hw->mac_type == em_82575 && hw->media_type != em_media_type_copper) 3895 return em_get_pcs_speed_and_duplex_82575(hw, speed, duplex); 3896 3897 if (hw->mac_type >= em_82543) { 3898 status = E1000_READ_REG(hw, STATUS); 3899 if (status & E1000_STATUS_SPEED_1000) { 3900 *speed = SPEED_1000; 3901 DEBUGOUT("1000 Mbs, "); 3902 } else if (status & E1000_STATUS_SPEED_100) { 3903 *speed = SPEED_100; 3904 DEBUGOUT("100 Mbs, "); 3905 } else { 3906 *speed = SPEED_10; 3907 DEBUGOUT("10 Mbs, "); 3908 } 3909 3910 if (status & E1000_STATUS_FD) { 3911 *duplex = FULL_DUPLEX; 3912 DEBUGOUT("Full Duplex\n"); 3913 } else { 3914 *duplex = HALF_DUPLEX; 3915 DEBUGOUT(" Half Duplex\n"); 3916 } 3917 } else { 3918 DEBUGOUT("1000 Mbs, Full Duplex\n"); 3919 *speed = SPEED_1000; 3920 *duplex = FULL_DUPLEX; 3921 } 3922 /* 3923 * IGP01 PHY may advertise full duplex operation after speed 3924 * downgrade even if it is operating at half duplex. Here we set the 3925 * duplex settings to match the duplex in the link partner's 3926 * capabilities. 3927 */ 3928 if (hw->phy_type == em_phy_igp && hw->speed_downgraded) { 3929 ret_val = em_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data); 3930 if (ret_val) 3931 return ret_val; 3932 3933 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS)) 3934 *duplex = HALF_DUPLEX; 3935 else { 3936 ret_val = em_read_phy_reg(hw, PHY_LP_ABILITY, 3937 &phy_data); 3938 if (ret_val) 3939 return ret_val; 3940 if ((*speed == SPEED_100 && 3941 !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) || 3942 (*speed == SPEED_10 && 3943 !(phy_data & NWAY_LPAR_10T_FD_CAPS))) 3944 *duplex = HALF_DUPLEX; 3945 } 3946 } 3947 if ((hw->mac_type == em_80003es2lan) && 3948 (hw->media_type == em_media_type_copper)) { 3949 if (*speed == SPEED_1000) 3950 ret_val = em_configure_kmrn_for_1000(hw); 3951 else 3952 ret_val = em_configure_kmrn_for_10_100(hw, *duplex); 3953 if (ret_val) 3954 return ret_val; 3955 } 3956 if ((hw->phy_type == em_phy_igp_3) && (*speed == SPEED_1000)) { 3957 ret_val = em_kumeran_lock_loss_workaround(hw); 3958 if (ret_val) 3959 return ret_val; 3960 } 3961 return E1000_SUCCESS; 3962 } 3963 3964 /****************************************************************************** 3965 * Blocks until autoneg completes or times out (~4.5 seconds) 3966 * 3967 * hw - Struct containing variables accessed by shared code 3968 *****************************************************************************/ 3969 STATIC int32_t 3970 em_wait_autoneg(struct em_hw *hw) 3971 { 3972 int32_t ret_val; 3973 uint16_t i; 3974 uint16_t phy_data; 3975 DEBUGFUNC("em_wait_autoneg"); 3976 DEBUGOUT("Waiting for Auto-Neg to complete.\n"); 3977 3978 /* We will wait for autoneg to complete or 4.5 seconds to expire. */ 3979 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) { 3980 /* 3981 * Read the MII Status Register and wait for Auto-Neg 3982 * Complete bit to be set. 3983 */ 3984 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 3985 if (ret_val) 3986 return ret_val; 3987 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 3988 if (ret_val) 3989 return ret_val; 3990 if (phy_data & MII_SR_AUTONEG_COMPLETE) { 3991 return E1000_SUCCESS; 3992 } 3993 msec_delay(100); 3994 } 3995 return E1000_SUCCESS; 3996 } 3997 3998 /****************************************************************************** 3999 * Raises the Management Data Clock 4000 * 4001 * hw - Struct containing variables accessed by shared code 4002 * ctrl - Device control register's current value 4003 *****************************************************************************/ 4004 static void 4005 em_raise_mdi_clk(struct em_hw *hw, uint32_t *ctrl) 4006 { 4007 /* 4008 * Raise the clock input to the Management Data Clock (by setting the 4009 * MDC bit), and then delay 10 microseconds. 4010 */ 4011 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC)); 4012 E1000_WRITE_FLUSH(hw); 4013 usec_delay(10); 4014 } 4015 4016 /****************************************************************************** 4017 * Lowers the Management Data Clock 4018 * 4019 * hw - Struct containing variables accessed by shared code 4020 * ctrl - Device control register's current value 4021 *****************************************************************************/ 4022 static void 4023 em_lower_mdi_clk(struct em_hw *hw, uint32_t *ctrl) 4024 { 4025 /* 4026 * Lower the clock input to the Management Data Clock (by clearing 4027 * the MDC bit), and then delay 10 microseconds. 4028 */ 4029 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC)); 4030 E1000_WRITE_FLUSH(hw); 4031 usec_delay(10); 4032 } 4033 4034 /****************************************************************************** 4035 * Shifts data bits out to the PHY 4036 * 4037 * hw - Struct containing variables accessed by shared code 4038 * data - Data to send out to the PHY 4039 * count - Number of bits to shift out 4040 * 4041 * Bits are shifted out in MSB to LSB order. 4042 *****************************************************************************/ 4043 static void 4044 em_shift_out_mdi_bits(struct em_hw *hw, uint32_t data, uint16_t count) 4045 { 4046 uint32_t ctrl; 4047 uint32_t mask; 4048 /* 4049 * We need to shift "count" number of bits out to the PHY. So, the 4050 * value in the "data" parameter will be shifted out to the PHY one 4051 * bit at a time. In order to do this, "data" must be broken down 4052 * into bits. 4053 */ 4054 mask = 0x01; 4055 mask <<= (count - 1); 4056 4057 ctrl = E1000_READ_REG(hw, CTRL); 4058 4059 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output 4060 * pins. 4061 */ 4062 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); 4063 4064 while (mask) { 4065 /* 4066 * A "1" is shifted out to the PHY by setting the MDIO bit to 4067 * "1" and then raising and lowering the Management Data 4068 * Clock. A "0" is shifted out to the PHY by setting the MDIO 4069 * bit to "0" and then raising and lowering the clock. 4070 */ 4071 if (data & mask) 4072 ctrl |= E1000_CTRL_MDIO; 4073 else 4074 ctrl &= ~E1000_CTRL_MDIO; 4075 4076 E1000_WRITE_REG(hw, CTRL, ctrl); 4077 E1000_WRITE_FLUSH(hw); 4078 4079 usec_delay(10); 4080 4081 em_raise_mdi_clk(hw, &ctrl); 4082 em_lower_mdi_clk(hw, &ctrl); 4083 4084 mask = mask >> 1; 4085 } 4086 } 4087 4088 /****************************************************************************** 4089 * Shifts data bits in from the PHY 4090 * 4091 * hw - Struct containing variables accessed by shared code 4092 * 4093 * Bits are shifted in in MSB to LSB order. 4094 *****************************************************************************/ 4095 static uint16_t 4096 em_shift_in_mdi_bits(struct em_hw *hw) 4097 { 4098 uint32_t ctrl; 4099 uint16_t data = 0; 4100 uint8_t i; 4101 /* 4102 * In order to read a register from the PHY, we need to shift in a 4103 * total of 18 bits from the PHY. The first two bit (turnaround) 4104 * times are used to avoid contention on the MDIO pin when a read 4105 * operation is performed. These two bits are ignored by us and 4106 * thrown away. Bits are "shifted in" by raising the input to the 4107 * Management Data Clock (setting the MDC bit), and then reading the 4108 * value of the MDIO bit. 4109 */ 4110 ctrl = E1000_READ_REG(hw, CTRL); 4111 /* 4112 * Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as 4113 * input. 4114 */ 4115 ctrl &= ~E1000_CTRL_MDIO_DIR; 4116 ctrl &= ~E1000_CTRL_MDIO; 4117 4118 E1000_WRITE_REG(hw, CTRL, ctrl); 4119 E1000_WRITE_FLUSH(hw); 4120 /* 4121 * Raise and Lower the clock before reading in the data. This 4122 * accounts for the turnaround bits. The first clock occurred when we 4123 * clocked out the last bit of the Register Address. 4124 */ 4125 em_raise_mdi_clk(hw, &ctrl); 4126 em_lower_mdi_clk(hw, &ctrl); 4127 4128 for (data = 0, i = 0; i < 16; i++) { 4129 data = data << 1; 4130 em_raise_mdi_clk(hw, &ctrl); 4131 ctrl = E1000_READ_REG(hw, CTRL); 4132 /* Check to see if we shifted in a "1". */ 4133 if (ctrl & E1000_CTRL_MDIO) 4134 data |= 1; 4135 em_lower_mdi_clk(hw, &ctrl); 4136 } 4137 4138 em_raise_mdi_clk(hw, &ctrl); 4139 em_lower_mdi_clk(hw, &ctrl); 4140 4141 return data; 4142 } 4143 4144 STATIC int32_t 4145 em_swfw_sync_acquire(struct em_hw *hw, uint16_t mask) 4146 { 4147 uint32_t swfw_sync = 0; 4148 uint32_t swmask = mask; 4149 uint32_t fwmask = mask << 16; 4150 int32_t timeout = 200; 4151 DEBUGFUNC("em_swfw_sync_acquire"); 4152 4153 if (hw->swfwhw_semaphore_present) 4154 return em_get_software_flag(hw); 4155 4156 if (!hw->swfw_sync_present) 4157 return em_get_hw_eeprom_semaphore(hw); 4158 4159 while (timeout) { 4160 if (em_get_hw_eeprom_semaphore(hw)) 4161 return -E1000_ERR_SWFW_SYNC; 4162 4163 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); 4164 if (!(swfw_sync & (fwmask | swmask))) { 4165 break; 4166 } 4167 /* 4168 * firmware currently using resource (fwmask) 4169 * or other software thread currently using resource (swmask) 4170 */ 4171 em_put_hw_eeprom_semaphore(hw); 4172 msec_delay_irq(5); 4173 timeout--; 4174 } 4175 4176 if (!timeout) { 4177 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout." 4178 "\n"); 4179 return -E1000_ERR_SWFW_SYNC; 4180 } 4181 swfw_sync |= swmask; 4182 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync); 4183 4184 em_put_hw_eeprom_semaphore(hw); 4185 return E1000_SUCCESS; 4186 } 4187 4188 STATIC void 4189 em_swfw_sync_release(struct em_hw *hw, uint16_t mask) 4190 { 4191 uint32_t swfw_sync; 4192 uint32_t swmask = mask; 4193 DEBUGFUNC("em_swfw_sync_release"); 4194 4195 if (hw->swfwhw_semaphore_present) { 4196 em_release_software_flag(hw); 4197 return; 4198 } 4199 if (!hw->swfw_sync_present) { 4200 em_put_hw_eeprom_semaphore(hw); 4201 return; 4202 } 4203 /* 4204 * if (em_get_hw_eeprom_semaphore(hw)) return -E1000_ERR_SWFW_SYNC; 4205 */ 4206 while (em_get_hw_eeprom_semaphore(hw) != E1000_SUCCESS); 4207 /* empty */ 4208 4209 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); 4210 swfw_sync &= ~swmask; 4211 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync); 4212 4213 em_put_hw_eeprom_semaphore(hw); 4214 } 4215 4216 /**************************************************************************** 4217 * Read BM PHY wakeup register. It works as such: 4218 * 1) Set page 769, register 17, bit 2 = 1 4219 * 2) Set page to 800 for host (801 if we were manageability) 4220 * 3) Write the address using the address opcode (0x11) 4221 * 4) Read or write the data using the data opcode (0x12) 4222 * 5) Restore 769_17.2 to its original value 4223 ****************************************************************************/ 4224 int32_t 4225 em_access_phy_wakeup_reg_bm(struct em_hw *hw, uint32_t reg_addr, 4226 uint16_t *phy_data, boolean_t read) 4227 { 4228 int32_t ret_val; 4229 uint16_t reg = BM_PHY_REG_NUM(reg_addr); 4230 uint16_t phy_reg = 0; 4231 4232 /* All operations in this function are phy address 1 */ 4233 hw->phy_addr = 1; 4234 4235 /* Set page 769 */ 4236 em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 4237 (BM_WUC_ENABLE_PAGE << PHY_PAGE_SHIFT)); 4238 4239 ret_val = em_read_phy_reg_ex(hw, BM_WUC_ENABLE_REG, &phy_reg); 4240 if (ret_val) 4241 goto out; 4242 4243 /* First clear bit 4 to avoid a power state change */ 4244 phy_reg &= ~(BM_WUC_HOST_WU_BIT); 4245 ret_val = em_write_phy_reg_ex(hw, BM_WUC_ENABLE_REG, phy_reg); 4246 if (ret_val) 4247 goto out; 4248 4249 /* Write bit 2 = 1, and clear bit 4 to 769_17 */ 4250 ret_val = em_write_phy_reg_ex(hw, BM_WUC_ENABLE_REG, 4251 phy_reg | BM_WUC_ENABLE_BIT); 4252 if (ret_val) 4253 goto out; 4254 4255 /* Select page 800 */ 4256 ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 4257 (BM_WUC_PAGE << PHY_PAGE_SHIFT)); 4258 4259 /* Write the page 800 offset value using opcode 0x11 */ 4260 ret_val = em_write_phy_reg_ex(hw, BM_WUC_ADDRESS_OPCODE, reg); 4261 if (ret_val) 4262 goto out; 4263 4264 if (read) 4265 /* Read the page 800 value using opcode 0x12 */ 4266 ret_val = em_read_phy_reg_ex(hw, BM_WUC_DATA_OPCODE, 4267 phy_data); 4268 else 4269 /* Write the page 800 value using opcode 0x12 */ 4270 ret_val = em_write_phy_reg_ex(hw, BM_WUC_DATA_OPCODE, 4271 *phy_data); 4272 4273 if (ret_val) 4274 goto out; 4275 4276 /* 4277 * Restore 769_17.2 to its original value 4278 * Set page 769 4279 */ 4280 em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 4281 (BM_WUC_ENABLE_PAGE << PHY_PAGE_SHIFT)); 4282 4283 /* Clear 769_17.2 */ 4284 ret_val = em_write_phy_reg_ex(hw, BM_WUC_ENABLE_REG, phy_reg); 4285 if (ret_val) 4286 goto out; 4287 4288 out: 4289 return ret_val; 4290 } 4291 4292 /*************************************************************************** 4293 * Read HV PHY vendor specific high registers 4294 ***************************************************************************/ 4295 int32_t 4296 em_access_phy_debug_regs_hv(struct em_hw *hw, uint32_t reg_addr, 4297 uint16_t *phy_data, boolean_t read) 4298 { 4299 int32_t ret_val; 4300 uint32_t addr_reg = 0; 4301 uint32_t data_reg = 0; 4302 4303 /* This takes care of the difference with desktop vs mobile phy */ 4304 addr_reg = (hw->phy_type == em_phy_82578) ? 4305 I82578_PHY_ADDR_REG : I82577_PHY_ADDR_REG; 4306 data_reg = addr_reg + 1; 4307 4308 /* All operations in this function are phy address 2 */ 4309 hw->phy_addr = 2; 4310 4311 /* masking with 0x3F to remove the page from offset */ 4312 ret_val = em_write_phy_reg_ex(hw, addr_reg, (uint16_t)reg_addr & 0x3F); 4313 if (ret_val) { 4314 printf("Could not write PHY the HV address register\n"); 4315 goto out; 4316 } 4317 4318 /* Read or write the data value next */ 4319 if (read) 4320 ret_val = em_read_phy_reg_ex(hw, data_reg, phy_data); 4321 else 4322 ret_val = em_write_phy_reg_ex(hw, data_reg, *phy_data); 4323 4324 if (ret_val) { 4325 printf("Could not read data value from HV data register\n"); 4326 goto out; 4327 } 4328 4329 out: 4330 return ret_val; 4331 } 4332 4333 /****************************************************************************** 4334 * Reads or writes the value from a PHY register, if the value is on a specific 4335 * non zero page, sets the page first. 4336 * hw - Struct containing variables accessed by shared code 4337 * reg_addr - address of the PHY register to read 4338 *****************************************************************************/ 4339 int32_t 4340 em_access_phy_reg_hv(struct em_hw *hw, uint32_t reg_addr, uint16_t *phy_data, 4341 boolean_t read) 4342 { 4343 uint32_t ret_val; 4344 uint16_t swfw; 4345 uint16_t page = BM_PHY_REG_PAGE(reg_addr); 4346 uint16_t reg = BM_PHY_REG_NUM(reg_addr); 4347 4348 DEBUGFUNC("em_access_phy_reg_hv"); 4349 4350 swfw = E1000_SWFW_PHY0_SM; 4351 4352 if (em_swfw_sync_acquire(hw, swfw)) 4353 return -E1000_ERR_SWFW_SYNC; 4354 4355 if (page == BM_WUC_PAGE) { 4356 ret_val = em_access_phy_wakeup_reg_bm(hw, reg_addr, 4357 phy_data, read); 4358 goto release; 4359 } 4360 4361 if (page >= HV_INTC_FC_PAGE_START) 4362 hw->phy_addr = 1; 4363 else 4364 hw->phy_addr = 2; 4365 4366 if (page == HV_INTC_FC_PAGE_START) 4367 page = 0; 4368 4369 /* 4370 * Workaround MDIO accesses being disabled after entering IEEE Power 4371 * Down (whenever bit 11 of the PHY Control register is set) 4372 */ 4373 if (!read && 4374 (hw->phy_type == em_phy_82578) && 4375 (hw->phy_revision >= 1) && 4376 (hw->phy_addr == 2) && 4377 ((MAX_PHY_REG_ADDRESS & reg) == 0) && 4378 (*phy_data & (1 << 11))) { 4379 uint16_t data2 = 0x7EFF; 4380 4381 ret_val = em_access_phy_debug_regs_hv(hw, (1 << 6) | 0x3, 4382 &data2, FALSE); 4383 if (ret_val) 4384 return ret_val; 4385 } 4386 4387 if (reg_addr > MAX_PHY_MULTI_PAGE_REG) { 4388 ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 4389 (page << PHY_PAGE_SHIFT)); 4390 if (ret_val) 4391 return ret_val; 4392 } 4393 if (read) 4394 ret_val = em_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg, 4395 phy_data); 4396 else 4397 ret_val = em_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg, 4398 *phy_data); 4399 release: 4400 em_swfw_sync_release(hw, swfw); 4401 return ret_val; 4402 } 4403 4404 /****************************************************************************** 4405 * Reads the value from a PHY register, if the value is on a specific non zero 4406 * page, sets the page first. 4407 * hw - Struct containing variables accessed by shared code 4408 * reg_addr - address of the PHY register to read 4409 *****************************************************************************/ 4410 int32_t 4411 em_read_phy_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t *phy_data) 4412 { 4413 uint32_t ret_val; 4414 uint16_t swfw; 4415 DEBUGFUNC("em_read_phy_reg"); 4416 4417 if (hw->mac_type == em_pchlan || 4418 hw->mac_type == em_pch2lan) 4419 return (em_access_phy_reg_hv(hw, reg_addr, phy_data, TRUE)); 4420 4421 if (((hw->mac_type == em_80003es2lan) || (hw->mac_type == em_82575)) && 4422 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { 4423 swfw = E1000_SWFW_PHY1_SM; 4424 } else { 4425 swfw = E1000_SWFW_PHY0_SM; 4426 } 4427 if (em_swfw_sync_acquire(hw, swfw)) 4428 return -E1000_ERR_SWFW_SYNC; 4429 4430 if ((hw->phy_type == em_phy_igp || 4431 hw->phy_type == em_phy_igp_3 || 4432 hw->phy_type == em_phy_igp_2) && 4433 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { 4434 ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 4435 (uint16_t) reg_addr); 4436 if (ret_val) { 4437 em_swfw_sync_release(hw, swfw); 4438 return ret_val; 4439 } 4440 } else if (hw->phy_type == em_phy_gg82563) { 4441 if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) || 4442 (hw->mac_type == em_80003es2lan)) { 4443 /* Select Configuration Page */ 4444 if ((reg_addr & MAX_PHY_REG_ADDRESS) < 4445 GG82563_MIN_ALT_REG) { 4446 ret_val = em_write_phy_reg_ex(hw, 4447 GG82563_PHY_PAGE_SELECT, 4448 (uint16_t) ((uint16_t) reg_addr >> 4449 GG82563_PAGE_SHIFT)); 4450 } else { 4451 /* 4452 * Use Alternative Page Select register to 4453 * access registers 30 and 31 4454 */ 4455 ret_val = em_write_phy_reg_ex(hw, 4456 GG82563_PHY_PAGE_SELECT_ALT, 4457 (uint16_t) ((uint16_t) reg_addr >> 4458 GG82563_PAGE_SHIFT)); 4459 } 4460 4461 if (ret_val) { 4462 em_swfw_sync_release(hw, swfw); 4463 return ret_val; 4464 } 4465 } 4466 } else if ((hw->phy_type == em_phy_bm) && (hw->phy_revision == 1)) { 4467 if (reg_addr > MAX_PHY_MULTI_PAGE_REG) { 4468 ret_val = em_write_phy_reg_ex(hw, BM_PHY_PAGE_SELECT, 4469 (uint16_t) ((uint16_t) reg_addr >> 4470 PHY_PAGE_SHIFT)); 4471 if (ret_val) 4472 return ret_val; 4473 } 4474 } 4475 ret_val = em_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, 4476 phy_data); 4477 4478 em_swfw_sync_release(hw, swfw); 4479 return ret_val; 4480 } 4481 4482 STATIC int32_t 4483 em_read_phy_reg_ex(struct em_hw *hw, uint32_t reg_addr, uint16_t *phy_data) 4484 { 4485 uint32_t i; 4486 uint32_t mdic = 0; 4487 DEBUGFUNC("em_read_phy_reg_ex"); 4488 4489 if (reg_addr > MAX_PHY_REG_ADDRESS) { 4490 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); 4491 return -E1000_ERR_PARAM; 4492 } 4493 if (hw->mac_type == em_icp_xxxx) { 4494 *phy_data = gcu_miibus_readreg(hw, hw->icp_xxxx_port_num, 4495 reg_addr); 4496 return E1000_SUCCESS; 4497 } 4498 if (hw->mac_type > em_82543) { 4499 /* 4500 * Set up Op-code, Phy Address, and register address in the 4501 * MDI Control register. The MAC will take care of 4502 * interfacing with the PHY to retrieve the desired data. 4503 */ 4504 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) | 4505 (hw->phy_addr << E1000_MDIC_PHY_SHIFT) | 4506 (E1000_MDIC_OP_READ)); 4507 4508 E1000_WRITE_REG(hw, MDIC, mdic); 4509 4510 /* 4511 * Poll the ready bit to see if the MDI read completed 4512 * Increasing the time out as testing showed failures with 4513 * the lower time out (from FreeBSD driver) 4514 */ 4515 for (i = 0; i < 1960; i++) { 4516 usec_delay(50); 4517 mdic = E1000_READ_REG(hw, MDIC); 4518 if (mdic & E1000_MDIC_READY) 4519 break; 4520 } 4521 if (!(mdic & E1000_MDIC_READY)) { 4522 DEBUGOUT("MDI Read did not complete\n"); 4523 return -E1000_ERR_PHY; 4524 } 4525 if (mdic & E1000_MDIC_ERROR) { 4526 DEBUGOUT("MDI Error\n"); 4527 return -E1000_ERR_PHY; 4528 } 4529 *phy_data = (uint16_t) mdic; 4530 4531 if (hw->mac_type == em_pch2lan) 4532 usec_delay(100); 4533 } else { 4534 /* 4535 * We must first send a preamble through the MDIO pin to 4536 * signal the beginning of an MII instruction. This is done 4537 * by sending 32 consecutive "1" bits. 4538 */ 4539 em_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 4540 /* 4541 * Now combine the next few fields that are required for a 4542 * read operation. We use this method instead of calling the 4543 * em_shift_out_mdi_bits routine five different times. The 4544 * format of a MII read instruction consists of a shift out 4545 * of 14 bits and is defined as follows: <Preamble><SOF><Op 4546 * Code><Phy Addr><Reg Addr> followed by a shift in of 18 4547 * bits. This first two bits shifted in are TurnAround bits 4548 * used to avoid contention on the MDIO pin when a READ 4549 * operation is performed. These two bits are thrown away 4550 * followed by a shift in of 16 bits which contains the 4551 * desired data. 4552 */ 4553 mdic = ((reg_addr) | (hw->phy_addr << 5) | 4554 (PHY_OP_READ << 10) | (PHY_SOF << 12)); 4555 4556 em_shift_out_mdi_bits(hw, mdic, 14); 4557 /* 4558 * Now that we've shifted out the read command to the MII, we 4559 * need to "shift in" the 16-bit value (18 total bits) of the 4560 * requested PHY register address. 4561 */ 4562 *phy_data = em_shift_in_mdi_bits(hw); 4563 } 4564 return E1000_SUCCESS; 4565 } 4566 4567 /****************************************************************************** 4568 * Writes a value to a PHY register 4569 * 4570 * hw - Struct containing variables accessed by shared code 4571 * reg_addr - address of the PHY register to write 4572 * data - data to write to the PHY 4573 *****************************************************************************/ 4574 int32_t 4575 em_write_phy_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t phy_data) 4576 { 4577 uint32_t ret_val; 4578 uint16_t swfw; 4579 DEBUGFUNC("em_write_phy_reg"); 4580 4581 if (hw->mac_type == em_pchlan || 4582 hw->mac_type == em_pch2lan) 4583 return (em_access_phy_reg_hv(hw, reg_addr, &phy_data, FALSE)); 4584 4585 if (((hw->mac_type == em_80003es2lan) || (hw->mac_type == em_82575)) && 4586 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { 4587 swfw = E1000_SWFW_PHY1_SM; 4588 } else { 4589 swfw = E1000_SWFW_PHY0_SM; 4590 } 4591 if (em_swfw_sync_acquire(hw, swfw)) 4592 return -E1000_ERR_SWFW_SYNC; 4593 4594 if ((hw->phy_type == em_phy_igp || 4595 hw->phy_type == em_phy_igp_3 || 4596 hw->phy_type == em_phy_igp_2) && 4597 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { 4598 ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 4599 (uint16_t) reg_addr); 4600 if (ret_val) { 4601 em_swfw_sync_release(hw, swfw); 4602 return ret_val; 4603 } 4604 } else if (hw->phy_type == em_phy_gg82563) { 4605 if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) || 4606 (hw->mac_type == em_80003es2lan)) { 4607 /* Select Configuration Page */ 4608 if ((reg_addr & MAX_PHY_REG_ADDRESS) < 4609 GG82563_MIN_ALT_REG) { 4610 ret_val = em_write_phy_reg_ex(hw, 4611 GG82563_PHY_PAGE_SELECT, 4612 (uint16_t) ((uint16_t) reg_addr >> 4613 GG82563_PAGE_SHIFT)); 4614 } else { 4615 /* 4616 * Use Alternative Page Select register to 4617 * access registers 30 and 31 4618 */ 4619 ret_val = em_write_phy_reg_ex(hw, 4620 GG82563_PHY_PAGE_SELECT_ALT, 4621 (uint16_t) ((uint16_t) reg_addr >> 4622 GG82563_PAGE_SHIFT)); 4623 } 4624 4625 if (ret_val) { 4626 em_swfw_sync_release(hw, swfw); 4627 return ret_val; 4628 } 4629 } 4630 } else if ((hw->phy_type == em_phy_bm) && (hw->phy_revision == 1)) { 4631 if (reg_addr > MAX_PHY_MULTI_PAGE_REG) { 4632 ret_val = em_write_phy_reg_ex(hw, BM_PHY_PAGE_SELECT, 4633 (uint16_t) ((uint16_t) reg_addr >> 4634 PHY_PAGE_SHIFT)); 4635 if (ret_val) 4636 return ret_val; 4637 } 4638 } 4639 ret_val = em_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, 4640 phy_data); 4641 4642 em_swfw_sync_release(hw, swfw); 4643 return ret_val; 4644 } 4645 4646 STATIC int32_t 4647 em_write_phy_reg_ex(struct em_hw *hw, uint32_t reg_addr, uint16_t phy_data) 4648 { 4649 uint32_t i; 4650 uint32_t mdic = 0; 4651 DEBUGFUNC("em_write_phy_reg_ex"); 4652 4653 if (reg_addr > MAX_PHY_REG_ADDRESS) { 4654 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); 4655 return -E1000_ERR_PARAM; 4656 } 4657 if (hw->mac_type == em_icp_xxxx) { 4658 gcu_miibus_writereg(hw, hw->icp_xxxx_port_num, 4659 reg_addr, phy_data); 4660 return E1000_SUCCESS; 4661 } 4662 if (hw->mac_type > em_82543) { 4663 /* 4664 * Set up Op-code, Phy Address, register address, and data 4665 * intended for the PHY register in the MDI Control register. 4666 * The MAC will take care of interfacing with the PHY to send 4667 * the desired data. 4668 */ 4669 mdic = (((uint32_t) phy_data) | 4670 (reg_addr << E1000_MDIC_REG_SHIFT) | 4671 (hw->phy_addr << E1000_MDIC_PHY_SHIFT) | 4672 (E1000_MDIC_OP_WRITE)); 4673 4674 E1000_WRITE_REG(hw, MDIC, mdic); 4675 4676 /* Poll the ready bit to see if the MDI read completed */ 4677 for (i = 0; i < 641; i++) { 4678 usec_delay(5); 4679 mdic = E1000_READ_REG(hw, MDIC); 4680 if (mdic & E1000_MDIC_READY) 4681 break; 4682 } 4683 if (!(mdic & E1000_MDIC_READY)) { 4684 DEBUGOUT("MDI Write did not complete\n"); 4685 return -E1000_ERR_PHY; 4686 } 4687 4688 if (hw->mac_type == em_pch2lan) 4689 usec_delay(100); 4690 } else { 4691 /* 4692 * We'll need to use the SW defined pins to shift the write 4693 * command out to the PHY. We first send a preamble to the 4694 * PHY to signal the beginning of the MII instruction. This 4695 * is done by sending 32 consecutive "1" bits. 4696 */ 4697 em_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 4698 /* 4699 * Now combine the remaining required fields that will 4700 * indicate a write operation. We use this method instead of 4701 * calling the em_shift_out_mdi_bits routine for each field 4702 * in the command. The format of a MII write instruction is 4703 * as follows: <Preamble><SOF><Op Code><Phy Addr><Reg 4704 * Addr><Turnaround><Data>. 4705 */ 4706 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | 4707 (hw->phy_addr << 7) | (PHY_OP_WRITE << 12) | 4708 (PHY_SOF << 14)); 4709 mdic <<= 16; 4710 mdic |= (uint32_t) phy_data; 4711 4712 em_shift_out_mdi_bits(hw, mdic, 32); 4713 } 4714 4715 return E1000_SUCCESS; 4716 } 4717 4718 STATIC int32_t 4719 em_read_kmrn_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t *data) 4720 { 4721 uint32_t reg_val; 4722 uint16_t swfw; 4723 DEBUGFUNC("em_read_kmrn_reg"); 4724 4725 if ((hw->mac_type == em_80003es2lan) && 4726 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { 4727 swfw = E1000_SWFW_PHY1_SM; 4728 } else { 4729 swfw = E1000_SWFW_PHY0_SM; 4730 } 4731 if (em_swfw_sync_acquire(hw, swfw)) 4732 return -E1000_ERR_SWFW_SYNC; 4733 4734 /* Write register address */ 4735 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) & 4736 E1000_KUMCTRLSTA_OFFSET) | 4737 E1000_KUMCTRLSTA_REN; 4738 4739 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); 4740 usec_delay(2); 4741 4742 /* Read the data returned */ 4743 reg_val = E1000_READ_REG(hw, KUMCTRLSTA); 4744 *data = (uint16_t) reg_val; 4745 4746 em_swfw_sync_release(hw, swfw); 4747 return E1000_SUCCESS; 4748 } 4749 4750 STATIC int32_t 4751 em_write_kmrn_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t data) 4752 { 4753 uint32_t reg_val; 4754 uint16_t swfw; 4755 DEBUGFUNC("em_write_kmrn_reg"); 4756 4757 if ((hw->mac_type == em_80003es2lan) && 4758 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { 4759 swfw = E1000_SWFW_PHY1_SM; 4760 } else { 4761 swfw = E1000_SWFW_PHY0_SM; 4762 } 4763 4764 if (em_swfw_sync_acquire(hw, swfw)) 4765 return -E1000_ERR_SWFW_SYNC; 4766 4767 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) & 4768 E1000_KUMCTRLSTA_OFFSET) | data; 4769 4770 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); 4771 usec_delay(2); 4772 4773 em_swfw_sync_release(hw, swfw); 4774 return E1000_SUCCESS; 4775 } 4776 4777 /****************************************************************************** 4778 * Returns the PHY to the power-on reset state 4779 * 4780 * hw - Struct containing variables accessed by shared code 4781 *****************************************************************************/ 4782 int32_t 4783 em_phy_hw_reset(struct em_hw *hw) 4784 { 4785 uint32_t ctrl, ctrl_ext; 4786 uint32_t led_ctrl; 4787 int32_t ret_val; 4788 uint16_t swfw; 4789 DEBUGFUNC("em_phy_hw_reset"); 4790 /* 4791 * In the case of the phy reset being blocked, it's not an error, we 4792 * simply return success without performing the reset. 4793 */ 4794 ret_val = em_check_phy_reset_block(hw); 4795 if (ret_val) 4796 return E1000_SUCCESS; 4797 4798 DEBUGOUT("Resetting Phy...\n"); 4799 4800 if (hw->mac_type > em_82543 && hw->mac_type != em_icp_xxxx) { 4801 if (((hw->mac_type == em_80003es2lan) || 4802 (hw->mac_type == em_82575)) && 4803 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { 4804 swfw = E1000_SWFW_PHY1_SM; 4805 } else { 4806 swfw = E1000_SWFW_PHY0_SM; 4807 } 4808 if (em_swfw_sync_acquire(hw, swfw)) { 4809 DEBUGOUT("Unable to acquire swfw sync\n"); 4810 return -E1000_ERR_SWFW_SYNC; 4811 } 4812 /* 4813 * Read the device control register and assert the 4814 * E1000_CTRL_PHY_RST bit. Then, take it out of reset. For 4815 * pre-em_82571 hardware, we delay for 10ms between the 4816 * assert and deassert. For em_82571 hardware and later, we 4817 * instead delay for 50us between and 10ms after the 4818 * deassertion. 4819 */ 4820 ctrl = E1000_READ_REG(hw, CTRL); 4821 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST); 4822 E1000_WRITE_FLUSH(hw); 4823 4824 if (hw->mac_type < em_82571) 4825 msec_delay(10); 4826 else 4827 usec_delay(100); 4828 4829 E1000_WRITE_REG(hw, CTRL, ctrl); 4830 E1000_WRITE_FLUSH(hw); 4831 4832 if (hw->mac_type >= em_82571) 4833 msec_delay_irq(10); 4834 em_swfw_sync_release(hw, swfw); 4835 /* 4836 * the M88E1141_E_PHY_ID might need reset here, but nothing 4837 * proves it 4838 */ 4839 } else { 4840 /* 4841 * Read the Extended Device Control Register, assert the 4842 * PHY_RESET_DIR bit to put the PHY into reset. Then, take it 4843 * out of reset. 4844 */ 4845 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 4846 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; 4847 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; 4848 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 4849 E1000_WRITE_FLUSH(hw); 4850 msec_delay(10); 4851 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; 4852 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 4853 E1000_WRITE_FLUSH(hw); 4854 } 4855 usec_delay(150); 4856 4857 if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) { 4858 /* Configure activity LED after PHY reset */ 4859 led_ctrl = E1000_READ_REG(hw, LEDCTL); 4860 led_ctrl &= IGP_ACTIVITY_LED_MASK; 4861 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 4862 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 4863 } 4864 /* Wait for FW to finish PHY configuration. */ 4865 ret_val = em_get_phy_cfg_done(hw); 4866 if (ret_val != E1000_SUCCESS) 4867 return ret_val; 4868 em_release_software_semaphore(hw); 4869 4870 if ((hw->mac_type == em_ich8lan) && (hw->phy_type == em_phy_igp_3)) 4871 ret_val = em_init_lcd_from_nvm(hw); 4872 4873 return ret_val; 4874 } 4875 4876 /***************************************************************************** 4877 * SW-based LCD Configuration. 4878 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are 4879 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit 4880 * in NVM determines whether HW should configure LPLU and Gbe Disable. 4881 *****************************************************************************/ 4882 int32_t 4883 em_oem_bits_config_pchlan(struct em_hw *hw, boolean_t d0_state) 4884 { 4885 int32_t ret_val = E1000_SUCCESS; 4886 uint32_t mac_reg; 4887 uint16_t oem_reg; 4888 uint16_t swfw = E1000_SWFW_PHY0_SM; 4889 4890 if (hw->mac_type != em_pchlan) 4891 return ret_val; 4892 4893 ret_val = em_swfw_sync_acquire(hw, swfw); 4894 if (ret_val) 4895 return ret_val; 4896 4897 mac_reg = E1000_READ_REG(hw, EXTCNF_CTRL); 4898 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) 4899 goto out; 4900 4901 mac_reg = E1000_READ_REG(hw, FEXTNVM); 4902 if (!(mac_reg & FEXTNVM_SW_CONFIG_ICH8M)) 4903 goto out; 4904 4905 mac_reg = E1000_READ_REG(hw, PHY_CTRL); 4906 4907 ret_val = em_read_phy_reg(hw, HV_OEM_BITS, &oem_reg); 4908 if (ret_val) 4909 goto out; 4910 4911 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU); 4912 4913 if (d0_state) { 4914 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE) 4915 oem_reg |= HV_OEM_BITS_GBE_DIS; 4916 4917 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU) 4918 oem_reg |= HV_OEM_BITS_LPLU; 4919 } else { 4920 if (mac_reg & E1000_PHY_CTRL_NOND0A_GBE_DISABLE) 4921 oem_reg |= HV_OEM_BITS_GBE_DIS; 4922 4923 if (mac_reg & E1000_PHY_CTRL_NOND0A_LPLU) 4924 oem_reg |= HV_OEM_BITS_LPLU; 4925 } 4926 /* Restart auto-neg to activate the bits */ 4927 if (!em_check_phy_reset_block(hw)) 4928 oem_reg |= HV_OEM_BITS_RESTART_AN; 4929 ret_val = em_write_phy_reg(hw, HV_OEM_BITS, oem_reg); 4930 4931 out: 4932 em_swfw_sync_release(hw, swfw); 4933 4934 return ret_val; 4935 } 4936 4937 4938 /****************************************************************************** 4939 * Resets the PHY 4940 * 4941 * hw - Struct containing variables accessed by shared code 4942 * 4943 * Sets bit 15 of the MII Control regiser 4944 *****************************************************************************/ 4945 int32_t 4946 em_phy_reset(struct em_hw *hw) 4947 { 4948 int32_t ret_val; 4949 uint16_t phy_data; 4950 DEBUGFUNC("em_phy_reset"); 4951 /* 4952 * In the case of the phy reset being blocked, it's not an error, we 4953 * simply return success without performing the reset. 4954 */ 4955 ret_val = em_check_phy_reset_block(hw); 4956 if (ret_val) 4957 return E1000_SUCCESS; 4958 4959 switch (hw->phy_type) { 4960 case em_phy_igp: 4961 case em_phy_igp_2: 4962 case em_phy_igp_3: 4963 case em_phy_ife: 4964 ret_val = em_phy_hw_reset(hw); 4965 if (ret_val) 4966 return ret_val; 4967 break; 4968 default: 4969 ret_val = em_read_phy_reg(hw, PHY_CTRL, &phy_data); 4970 if (ret_val) 4971 return ret_val; 4972 4973 phy_data |= MII_CR_RESET; 4974 ret_val = em_write_phy_reg(hw, PHY_CTRL, phy_data); 4975 if (ret_val) 4976 return ret_val; 4977 4978 usec_delay(1); 4979 break; 4980 } 4981 4982 /* Allow time for h/w to get to a quiescent state after reset */ 4983 msec_delay(10); 4984 4985 if (hw->phy_type == em_phy_igp || hw->phy_type == em_phy_igp_2) 4986 em_phy_init_script(hw); 4987 else if (hw->mac_type == em_pchlan) { 4988 ret_val = em_hv_phy_workarounds_ich8lan(hw); 4989 if (ret_val) 4990 return ret_val; 4991 4992 ret_val = em_oem_bits_config_pchlan(hw, TRUE); 4993 if (ret_val) 4994 return ret_val; 4995 } 4996 else if (hw->mac_type == em_pch2lan) { 4997 ret_val = em_set_mdio_slow_mode_hv(hw); 4998 if (ret_val) 4999 return ret_val; 5000 } 5001 5002 return E1000_SUCCESS; 5003 } 5004 5005 /****************************************************************************** 5006 * Work-around for 82566 Kumeran PCS lock loss: 5007 * On link status change (i.e. PCI reset, speed change) and link is up and 5008 * speed is gigabit- 5009 * 0) if workaround is optionally disabled do nothing 5010 * 1) wait 1ms for Kumeran link to come up 5011 * 2) check Kumeran Diagnostic register PCS lock loss bit 5012 * 3) if not set the link is locked (all is good), otherwise... 5013 * 4) reset the PHY 5014 * 5) repeat up to 10 times 5015 * Note: this is only called for IGP3 copper when speed is 1gb. 5016 * 5017 * hw - struct containing variables accessed by shared code 5018 *****************************************************************************/ 5019 STATIC int32_t 5020 em_kumeran_lock_loss_workaround(struct em_hw *hw) 5021 { 5022 int32_t ret_val; 5023 int32_t reg; 5024 int32_t cnt; 5025 uint16_t phy_data; 5026 if (hw->kmrn_lock_loss_workaround_disabled) 5027 return E1000_SUCCESS; 5028 /* 5029 * Make sure link is up before proceeding. If not just return. 5030 * Attempting this while link is negotiating fouled up link stability 5031 */ 5032 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 5033 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 5034 5035 if (phy_data & MII_SR_LINK_STATUS) { 5036 for (cnt = 0; cnt < 10; cnt++) { 5037 /* read once to clear */ 5038 ret_val = em_read_phy_reg(hw, IGP3_KMRN_DIAG, 5039 &phy_data); 5040 if (ret_val) 5041 return ret_val; 5042 /* and again to get new status */ 5043 ret_val = em_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data); 5044 if (ret_val) 5045 return ret_val; 5046 5047 /* check for PCS lock */ 5048 if (!(phy_data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) 5049 return E1000_SUCCESS; 5050 5051 /* Issue PHY reset */ 5052 em_phy_hw_reset(hw); 5053 msec_delay_irq(5); 5054 } 5055 /* Disable GigE link negotiation */ 5056 reg = E1000_READ_REG(hw, PHY_CTRL); 5057 E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE 5058 | E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 5059 5060 /* unable to acquire PCS lock */ 5061 return E1000_ERR_PHY; 5062 } 5063 return E1000_SUCCESS; 5064 } 5065 5066 /****************************************************************************** 5067 * Reads and matches the expected PHY address for known PHY IDs 5068 * 5069 * hw - Struct containing variables accessed by shared code 5070 *****************************************************************************/ 5071 STATIC int32_t 5072 em_match_gig_phy(struct em_hw *hw) 5073 { 5074 int32_t phy_init_status, ret_val; 5075 uint16_t phy_id_high, phy_id_low; 5076 boolean_t match = FALSE; 5077 DEBUGFUNC("em_match_gig_phy"); 5078 5079 ret_val = em_read_phy_reg(hw, PHY_ID1, &phy_id_high); 5080 if (ret_val) 5081 return ret_val; 5082 5083 hw->phy_id = (uint32_t) (phy_id_high << 16); 5084 usec_delay(20); 5085 ret_val = em_read_phy_reg(hw, PHY_ID2, &phy_id_low); 5086 if (ret_val) 5087 return ret_val; 5088 5089 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK); 5090 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK; 5091 5092 switch (hw->mac_type) { 5093 case em_82543: 5094 if (hw->phy_id == M88E1000_E_PHY_ID) 5095 match = TRUE; 5096 break; 5097 case em_82544: 5098 if (hw->phy_id == M88E1000_I_PHY_ID) 5099 match = TRUE; 5100 break; 5101 case em_82540: 5102 case em_82545: 5103 case em_82545_rev_3: 5104 case em_82546: 5105 case em_82546_rev_3: 5106 if (hw->phy_id == M88E1011_I_PHY_ID) 5107 match = TRUE; 5108 break; 5109 case em_82541: 5110 case em_82541_rev_2: 5111 case em_82547: 5112 case em_82547_rev_2: 5113 if (hw->phy_id == IGP01E1000_I_PHY_ID) 5114 match = TRUE; 5115 break; 5116 case em_82573: 5117 if (hw->phy_id == M88E1111_I_PHY_ID) 5118 match = TRUE; 5119 break; 5120 case em_82574: 5121 if (hw->phy_id == BME1000_E_PHY_ID) 5122 match = TRUE; 5123 break; 5124 case em_82575: 5125 if (hw->phy_id == M88E1000_E_PHY_ID) 5126 match = TRUE; 5127 if (hw->phy_id == IGP01E1000_I_PHY_ID) 5128 match = TRUE; 5129 if (hw->phy_id == IGP03E1000_E_PHY_ID) 5130 match = TRUE; 5131 break; 5132 case em_82580: 5133 if (hw->phy_id == I82580_I_PHY_ID) 5134 match = TRUE; 5135 break; 5136 case em_80003es2lan: 5137 if (hw->phy_id == GG82563_E_PHY_ID) 5138 match = TRUE; 5139 break; 5140 case em_ich8lan: 5141 case em_ich9lan: 5142 case em_ich10lan: 5143 case em_pchlan: 5144 case em_pch2lan: 5145 if (hw->phy_id == IGP03E1000_E_PHY_ID) 5146 match = TRUE; 5147 if (hw->phy_id == IFE_E_PHY_ID) 5148 match = TRUE; 5149 if (hw->phy_id == IFE_PLUS_E_PHY_ID) 5150 match = TRUE; 5151 if (hw->phy_id == IFE_C_E_PHY_ID) 5152 match = TRUE; 5153 if (hw->phy_id == BME1000_E_PHY_ID) 5154 match = TRUE; 5155 if (hw->phy_id == I82577_E_PHY_ID) 5156 match = TRUE; 5157 if (hw->phy_id == I82578_E_PHY_ID) 5158 match = TRUE; 5159 if (hw->phy_id == I82579_E_PHY_ID) 5160 match = TRUE; 5161 break; 5162 case em_icp_xxxx: 5163 if (hw->phy_id == M88E1141_E_PHY_ID) 5164 match = TRUE; 5165 break; 5166 default: 5167 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type); 5168 return -E1000_ERR_CONFIG; 5169 } 5170 phy_init_status = em_set_phy_type(hw); 5171 5172 if ((match) && (phy_init_status == E1000_SUCCESS)) { 5173 DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id); 5174 return E1000_SUCCESS; 5175 } 5176 DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id); 5177 return -E1000_ERR_PHY; 5178 } 5179 5180 /****************************************************************************** 5181 * Probes the expected PHY address for known PHY IDs 5182 * 5183 * hw - Struct containing variables accessed by shared code 5184 *****************************************************************************/ 5185 STATIC int32_t 5186 em_detect_gig_phy(struct em_hw *hw) 5187 { 5188 int32_t ret_val; 5189 DEBUGFUNC("em_detect_gig_phy"); 5190 5191 if (hw->phy_id != 0) 5192 return E1000_SUCCESS; 5193 5194 /* default phy address, most phys reside here, but not all (ICH10) */ 5195 if (hw->mac_type != em_icp_xxxx) 5196 hw->phy_addr = 1; 5197 else 5198 hw->phy_addr = 0; /* There is a phy at phy_addr 0 on EP80579 */ 5199 5200 /* 5201 * The 82571 firmware may still be configuring the PHY. In this 5202 * case, we cannot access the PHY until the configuration is done. 5203 * So we explicitly set the PHY values. 5204 */ 5205 if (hw->mac_type == em_82571 || 5206 hw->mac_type == em_82572) { 5207 hw->phy_id = IGP01E1000_I_PHY_ID; 5208 hw->phy_type = em_phy_igp_2; 5209 return E1000_SUCCESS; 5210 } 5211 5212 /* 5213 * Some of the fiber cards dont have a phy, so we must exit cleanly 5214 * here 5215 */ 5216 if ((hw->media_type == em_media_type_fiber) && 5217 (hw->mac_type == em_82542_rev2_0 || 5218 hw->mac_type == em_82542_rev2_1 || 5219 hw->mac_type == em_82543 || 5220 hw->mac_type == em_82574 || 5221 hw->mac_type == em_82573 || 5222 hw->mac_type == em_82574 || 5223 hw->mac_type == em_80003es2lan)) { 5224 hw->phy_type = em_phy_undefined; 5225 return E1000_SUCCESS; 5226 } 5227 5228 if ((hw->media_type == em_media_type_internal_serdes || 5229 hw->media_type == em_media_type_fiber) && 5230 hw->mac_type == em_82575) { 5231 hw->phy_type = em_phy_undefined; 5232 return E1000_SUCCESS; 5233 } 5234 5235 /* 5236 * Up to 82543 (incl), we need reset the phy, or it might not get 5237 * detected 5238 */ 5239 if (hw->mac_type <= em_82543) { 5240 ret_val = em_phy_hw_reset(hw); 5241 if (ret_val) 5242 return ret_val; 5243 } 5244 /* 5245 * ESB-2 PHY reads require em_phy_gg82563 to be set because of a 5246 * work- around that forces PHY page 0 to be set or the reads fail. 5247 * The rest of the code in this routine uses em_read_phy_reg to read 5248 * the PHY ID. So for ESB-2 we need to have this set so our reads 5249 * won't fail. If the attached PHY is not a em_phy_gg82563, the 5250 * routines below will figure this out as well. 5251 */ 5252 if (hw->mac_type == em_80003es2lan) 5253 hw->phy_type = em_phy_gg82563; 5254 5255 /* Read the PHY ID Registers to identify which PHY is onboard. */ 5256 for (hw->phy_addr = 1; (hw->phy_addr < 4); hw->phy_addr++) { 5257 ret_val = em_match_gig_phy(hw); 5258 if (ret_val == E1000_SUCCESS) 5259 return E1000_SUCCESS; 5260 } 5261 return -E1000_ERR_PHY; 5262 } 5263 5264 /****************************************************************************** 5265 * Resets the PHY's DSP 5266 * 5267 * hw - Struct containing variables accessed by shared code 5268 *****************************************************************************/ 5269 static int32_t 5270 em_phy_reset_dsp(struct em_hw *hw) 5271 { 5272 int32_t ret_val; 5273 DEBUGFUNC("em_phy_reset_dsp"); 5274 5275 do { 5276 if (hw->phy_type != em_phy_gg82563) { 5277 ret_val = em_write_phy_reg(hw, 29, 0x001d); 5278 if (ret_val) 5279 break; 5280 } 5281 ret_val = em_write_phy_reg(hw, 30, 0x00c1); 5282 if (ret_val) 5283 break; 5284 ret_val = em_write_phy_reg(hw, 30, 0x0000); 5285 if (ret_val) 5286 break; 5287 ret_val = E1000_SUCCESS; 5288 } while (0); 5289 5290 return ret_val; 5291 } 5292 5293 /****************************************************************************** 5294 * Sets up eeprom variables in the hw struct. Must be called after mac_type 5295 * is configured. Additionally, if this is ICH8, the flash controller GbE 5296 * registers must be mapped, or this will crash. 5297 * 5298 * hw - Struct containing variables accessed by shared code 5299 *****************************************************************************/ 5300 int32_t 5301 em_init_eeprom_params(struct em_hw *hw) 5302 { 5303 struct em_eeprom_info *eeprom = &hw->eeprom; 5304 uint32_t eecd = E1000_READ_REG(hw, EECD); 5305 int32_t ret_val = E1000_SUCCESS; 5306 uint16_t eeprom_size; 5307 DEBUGFUNC("em_init_eeprom_params"); 5308 5309 switch (hw->mac_type) { 5310 case em_82542_rev2_0: 5311 case em_82542_rev2_1: 5312 case em_82543: 5313 case em_82544: 5314 eeprom->type = em_eeprom_microwire; 5315 eeprom->word_size = 64; 5316 eeprom->opcode_bits = 3; 5317 eeprom->address_bits = 6; 5318 eeprom->delay_usec = 50; 5319 eeprom->use_eerd = FALSE; 5320 eeprom->use_eewr = FALSE; 5321 break; 5322 case em_82540: 5323 case em_82545: 5324 case em_82545_rev_3: 5325 case em_icp_xxxx: 5326 case em_82546: 5327 case em_82546_rev_3: 5328 eeprom->type = em_eeprom_microwire; 5329 eeprom->opcode_bits = 3; 5330 eeprom->delay_usec = 50; 5331 if (eecd & E1000_EECD_SIZE) { 5332 eeprom->word_size = 256; 5333 eeprom->address_bits = 8; 5334 } else { 5335 eeprom->word_size = 64; 5336 eeprom->address_bits = 6; 5337 } 5338 eeprom->use_eerd = FALSE; 5339 eeprom->use_eewr = FALSE; 5340 break; 5341 case em_82541: 5342 case em_82541_rev_2: 5343 case em_82547: 5344 case em_82547_rev_2: 5345 if (eecd & E1000_EECD_TYPE) { 5346 eeprom->type = em_eeprom_spi; 5347 eeprom->opcode_bits = 8; 5348 eeprom->delay_usec = 1; 5349 if (eecd & E1000_EECD_ADDR_BITS) { 5350 eeprom->page_size = 32; 5351 eeprom->address_bits = 16; 5352 } else { 5353 eeprom->page_size = 8; 5354 eeprom->address_bits = 8; 5355 } 5356 } else { 5357 eeprom->type = em_eeprom_microwire; 5358 eeprom->opcode_bits = 3; 5359 eeprom->delay_usec = 50; 5360 if (eecd & E1000_EECD_ADDR_BITS) { 5361 eeprom->word_size = 256; 5362 eeprom->address_bits = 8; 5363 } else { 5364 eeprom->word_size = 64; 5365 eeprom->address_bits = 6; 5366 } 5367 } 5368 eeprom->use_eerd = FALSE; 5369 eeprom->use_eewr = FALSE; 5370 break; 5371 case em_82571: 5372 case em_82572: 5373 eeprom->type = em_eeprom_spi; 5374 eeprom->opcode_bits = 8; 5375 eeprom->delay_usec = 1; 5376 if (eecd & E1000_EECD_ADDR_BITS) { 5377 eeprom->page_size = 32; 5378 eeprom->address_bits = 16; 5379 } else { 5380 eeprom->page_size = 8; 5381 eeprom->address_bits = 8; 5382 } 5383 eeprom->use_eerd = FALSE; 5384 eeprom->use_eewr = FALSE; 5385 break; 5386 case em_82573: 5387 case em_82574: 5388 case em_82575: 5389 case em_82580: 5390 eeprom->type = em_eeprom_spi; 5391 eeprom->opcode_bits = 8; 5392 eeprom->delay_usec = 1; 5393 if (eecd & E1000_EECD_ADDR_BITS) { 5394 eeprom->page_size = 32; 5395 eeprom->address_bits = 16; 5396 } else { 5397 eeprom->page_size = 8; 5398 eeprom->address_bits = 8; 5399 } 5400 eeprom->use_eerd = TRUE; 5401 eeprom->use_eewr = TRUE; 5402 if (em_is_onboard_nvm_eeprom(hw) == FALSE) { 5403 eeprom->type = em_eeprom_flash; 5404 eeprom->word_size = 2048; 5405 /* 5406 * Ensure that the Autonomous FLASH update bit is 5407 * cleared due to Flash update issue on parts which 5408 * use a FLASH for NVM. 5409 */ 5410 eecd &= ~E1000_EECD_AUPDEN; 5411 E1000_WRITE_REG(hw, EECD, eecd); 5412 } 5413 break; 5414 case em_80003es2lan: 5415 eeprom->type = em_eeprom_spi; 5416 eeprom->opcode_bits = 8; 5417 eeprom->delay_usec = 1; 5418 if (eecd & E1000_EECD_ADDR_BITS) { 5419 eeprom->page_size = 32; 5420 eeprom->address_bits = 16; 5421 } else { 5422 eeprom->page_size = 8; 5423 eeprom->address_bits = 8; 5424 } 5425 eeprom->use_eerd = TRUE; 5426 eeprom->use_eewr = FALSE; 5427 break; 5428 case em_ich8lan: 5429 case em_ich9lan: 5430 case em_ich10lan: 5431 case em_pchlan: 5432 case em_pch2lan: 5433 { 5434 int32_t i = 0; 5435 uint32_t flash_size = 5436 E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_GFPREG); 5437 eeprom->type = em_eeprom_ich8; 5438 eeprom->use_eerd = FALSE; 5439 eeprom->use_eewr = FALSE; 5440 eeprom->word_size = E1000_SHADOW_RAM_WORDS; 5441 /* 5442 * Zero the shadow RAM structure. But don't load it 5443 * from NVM so as to save time for driver init 5444 */ 5445 if (hw->eeprom_shadow_ram != NULL) { 5446 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 5447 hw->eeprom_shadow_ram[i].modified = 5448 FALSE; 5449 hw->eeprom_shadow_ram[i].eeprom_word = 5450 0xFFFF; 5451 } 5452 } 5453 hw->flash_base_addr = (flash_size & 5454 ICH_GFPREG_BASE_MASK) * ICH_FLASH_SECTOR_SIZE; 5455 5456 hw->flash_bank_size = ((flash_size >> 16) & 5457 ICH_GFPREG_BASE_MASK) + 1; 5458 hw->flash_bank_size -= (flash_size & 5459 ICH_GFPREG_BASE_MASK); 5460 5461 hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE; 5462 5463 hw->flash_bank_size /= 2 * sizeof(uint16_t); 5464 5465 break; 5466 } 5467 default: 5468 break; 5469 } 5470 5471 if (eeprom->type == em_eeprom_spi) { 5472 /* 5473 * eeprom_size will be an enum [0..8] that maps to eeprom 5474 * sizes 128B to 32KB (incremented by powers of 2). 5475 */ 5476 if (hw->mac_type <= em_82547_rev_2) { 5477 /* Set to default value for initial eeprom read. */ 5478 eeprom->word_size = 64; 5479 ret_val = em_read_eeprom(hw, EEPROM_CFG, 1, 5480 &eeprom_size); 5481 if (ret_val) 5482 return ret_val; 5483 eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> 5484 EEPROM_SIZE_SHIFT; 5485 /* 5486 * 256B eeprom size was not supported in earlier 5487 * hardware, so we bump eeprom_size up one to ensure 5488 * that "1" (which maps to 256B) is never the result 5489 * used in the shifting logic below. 5490 */ 5491 if (eeprom_size) 5492 eeprom_size++; 5493 } else { 5494 eeprom_size = (uint16_t) ( 5495 (eecd & E1000_EECD_SIZE_EX_MASK) >> 5496 E1000_EECD_SIZE_EX_SHIFT); 5497 } 5498 5499 /* EEPROM access above 16k is unsupported */ 5500 if (eeprom_size + EEPROM_WORD_SIZE_SHIFT > 5501 EEPROM_WORD_SIZE_SHIFT_MAX) { 5502 eeprom->word_size = 1 << EEPROM_WORD_SIZE_SHIFT_MAX; 5503 } else { 5504 eeprom->word_size = 1 << 5505 (eeprom_size + EEPROM_WORD_SIZE_SHIFT); 5506 } 5507 } 5508 return ret_val; 5509 } 5510 5511 /****************************************************************************** 5512 * Raises the EEPROM's clock input. 5513 * 5514 * hw - Struct containing variables accessed by shared code 5515 * eecd - EECD's current value 5516 *****************************************************************************/ 5517 static void 5518 em_raise_ee_clk(struct em_hw *hw, uint32_t *eecd) 5519 { 5520 /* 5521 * Raise the clock input to the EEPROM (by setting the SK bit), and 5522 * then wait <delay> microseconds. 5523 */ 5524 *eecd = *eecd | E1000_EECD_SK; 5525 E1000_WRITE_REG(hw, EECD, *eecd); 5526 E1000_WRITE_FLUSH(hw); 5527 usec_delay(hw->eeprom.delay_usec); 5528 } 5529 5530 /****************************************************************************** 5531 * Lowers the EEPROM's clock input. 5532 * 5533 * hw - Struct containing variables accessed by shared code 5534 * eecd - EECD's current value 5535 *****************************************************************************/ 5536 static void 5537 em_lower_ee_clk(struct em_hw *hw, uint32_t *eecd) 5538 { 5539 /* 5540 * Lower the clock input to the EEPROM (by clearing the SK bit), and 5541 * then wait 50 microseconds. 5542 */ 5543 *eecd = *eecd & ~E1000_EECD_SK; 5544 E1000_WRITE_REG(hw, EECD, *eecd); 5545 E1000_WRITE_FLUSH(hw); 5546 usec_delay(hw->eeprom.delay_usec); 5547 } 5548 5549 /****************************************************************************** 5550 * Shift data bits out to the EEPROM. 5551 * 5552 * hw - Struct containing variables accessed by shared code 5553 * data - data to send to the EEPROM 5554 * count - number of bits to shift out 5555 *****************************************************************************/ 5556 static void 5557 em_shift_out_ee_bits(struct em_hw *hw, uint16_t data, uint16_t count) 5558 { 5559 struct em_eeprom_info *eeprom = &hw->eeprom; 5560 uint32_t eecd; 5561 uint32_t mask; 5562 /* 5563 * We need to shift "count" bits out to the EEPROM. So, value in the 5564 * "data" parameter will be shifted out to the EEPROM one bit at a 5565 * time. In order to do this, "data" must be broken down into bits. 5566 */ 5567 mask = 0x01 << (count - 1); 5568 eecd = E1000_READ_REG(hw, EECD); 5569 if (eeprom->type == em_eeprom_microwire) { 5570 eecd &= ~E1000_EECD_DO; 5571 } else if (eeprom->type == em_eeprom_spi) { 5572 eecd |= E1000_EECD_DO; 5573 } 5574 do { 5575 /* 5576 * A "1" is shifted out to the EEPROM by setting bit "DI" to 5577 * a "1", and then raising and then lowering the clock (the 5578 * SK bit controls the clock input to the EEPROM). A "0" is 5579 * shifted out to the EEPROM by setting "DI" to "0" and then 5580 * raising and then lowering the clock. 5581 */ 5582 eecd &= ~E1000_EECD_DI; 5583 5584 if (data & mask) 5585 eecd |= E1000_EECD_DI; 5586 5587 E1000_WRITE_REG(hw, EECD, eecd); 5588 E1000_WRITE_FLUSH(hw); 5589 5590 usec_delay(eeprom->delay_usec); 5591 5592 em_raise_ee_clk(hw, &eecd); 5593 em_lower_ee_clk(hw, &eecd); 5594 5595 mask = mask >> 1; 5596 5597 } while (mask); 5598 5599 /* We leave the "DI" bit set to "0" when we leave this routine. */ 5600 eecd &= ~E1000_EECD_DI; 5601 E1000_WRITE_REG(hw, EECD, eecd); 5602 } 5603 5604 /****************************************************************************** 5605 * Shift data bits in from the EEPROM 5606 * 5607 * hw - Struct containing variables accessed by shared code 5608 *****************************************************************************/ 5609 static uint16_t 5610 em_shift_in_ee_bits(struct em_hw *hw, uint16_t count) 5611 { 5612 uint32_t eecd; 5613 uint32_t i; 5614 uint16_t data; 5615 /* 5616 * In order to read a register from the EEPROM, we need to shift 5617 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising 5618 * the clock input to the EEPROM (setting the SK bit), and then 5619 * reading the value of the "DO" bit. During this "shifting in" 5620 * process the "DI" bit should always be clear. 5621 */ 5622 5623 eecd = E1000_READ_REG(hw, EECD); 5624 5625 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 5626 data = 0; 5627 5628 for (i = 0; i < count; i++) { 5629 data = data << 1; 5630 em_raise_ee_clk(hw, &eecd); 5631 5632 eecd = E1000_READ_REG(hw, EECD); 5633 5634 eecd &= ~(E1000_EECD_DI); 5635 if (eecd & E1000_EECD_DO) 5636 data |= 1; 5637 5638 em_lower_ee_clk(hw, &eecd); 5639 } 5640 5641 return data; 5642 } 5643 /****************************************************************************** 5644 * Prepares EEPROM for access 5645 * 5646 * hw - Struct containing variables accessed by shared code 5647 * 5648 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This 5649 * function should be called before issuing a command to the EEPROM. 5650 *****************************************************************************/ 5651 static int32_t 5652 em_acquire_eeprom(struct em_hw *hw) 5653 { 5654 struct em_eeprom_info *eeprom = &hw->eeprom; 5655 uint32_t eecd, i = 0; 5656 DEBUGFUNC("em_acquire_eeprom"); 5657 5658 if (em_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM)) 5659 return -E1000_ERR_SWFW_SYNC; 5660 eecd = E1000_READ_REG(hw, EECD); 5661 5662 if ((hw->mac_type != em_82573) && (hw->mac_type != em_82574)) { 5663 /* Request EEPROM Access */ 5664 if (hw->mac_type > em_82544) { 5665 eecd |= E1000_EECD_REQ; 5666 E1000_WRITE_REG(hw, EECD, eecd); 5667 eecd = E1000_READ_REG(hw, EECD); 5668 while ((!(eecd & E1000_EECD_GNT)) && 5669 (i < E1000_EEPROM_GRANT_ATTEMPTS)) { 5670 i++; 5671 usec_delay(5); 5672 eecd = E1000_READ_REG(hw, EECD); 5673 } 5674 if (!(eecd & E1000_EECD_GNT)) { 5675 eecd &= ~E1000_EECD_REQ; 5676 E1000_WRITE_REG(hw, EECD, eecd); 5677 DEBUGOUT("Could not acquire EEPROM grant\n"); 5678 em_swfw_sync_release(hw, E1000_SWFW_EEP_SM); 5679 return -E1000_ERR_EEPROM; 5680 } 5681 } 5682 } 5683 5684 /* Setup EEPROM for Read/Write */ 5685 if (eeprom->type == em_eeprom_microwire) { 5686 /* Clear SK and DI */ 5687 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK); 5688 E1000_WRITE_REG(hw, EECD, eecd); 5689 5690 /* Set CS */ 5691 eecd |= E1000_EECD_CS; 5692 E1000_WRITE_REG(hw, EECD, eecd); 5693 } else if (eeprom->type == em_eeprom_spi) { 5694 /* Clear SK and CS */ 5695 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 5696 E1000_WRITE_REG(hw, EECD, eecd); 5697 usec_delay(1); 5698 } 5699 return E1000_SUCCESS; 5700 } 5701 5702 /****************************************************************************** 5703 * Returns EEPROM to a "standby" state 5704 * 5705 * hw - Struct containing variables accessed by shared code 5706 *****************************************************************************/ 5707 static void 5708 em_standby_eeprom(struct em_hw *hw) 5709 { 5710 struct em_eeprom_info *eeprom = &hw->eeprom; 5711 uint32_t eecd; 5712 eecd = E1000_READ_REG(hw, EECD); 5713 5714 if (eeprom->type == em_eeprom_microwire) { 5715 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 5716 E1000_WRITE_REG(hw, EECD, eecd); 5717 E1000_WRITE_FLUSH(hw); 5718 usec_delay(eeprom->delay_usec); 5719 5720 /* Clock high */ 5721 eecd |= E1000_EECD_SK; 5722 E1000_WRITE_REG(hw, EECD, eecd); 5723 E1000_WRITE_FLUSH(hw); 5724 usec_delay(eeprom->delay_usec); 5725 5726 /* Select EEPROM */ 5727 eecd |= E1000_EECD_CS; 5728 E1000_WRITE_REG(hw, EECD, eecd); 5729 E1000_WRITE_FLUSH(hw); 5730 usec_delay(eeprom->delay_usec); 5731 5732 /* Clock low */ 5733 eecd &= ~E1000_EECD_SK; 5734 E1000_WRITE_REG(hw, EECD, eecd); 5735 E1000_WRITE_FLUSH(hw); 5736 usec_delay(eeprom->delay_usec); 5737 } else if (eeprom->type == em_eeprom_spi) { 5738 /* Toggle CS to flush commands */ 5739 eecd |= E1000_EECD_CS; 5740 E1000_WRITE_REG(hw, EECD, eecd); 5741 E1000_WRITE_FLUSH(hw); 5742 usec_delay(eeprom->delay_usec); 5743 eecd &= ~E1000_EECD_CS; 5744 E1000_WRITE_REG(hw, EECD, eecd); 5745 E1000_WRITE_FLUSH(hw); 5746 usec_delay(eeprom->delay_usec); 5747 } 5748 } 5749 5750 /****************************************************************************** 5751 * Terminates a command by inverting the EEPROM's chip select pin 5752 * 5753 * hw - Struct containing variables accessed by shared code 5754 *****************************************************************************/ 5755 static void 5756 em_release_eeprom(struct em_hw *hw) 5757 { 5758 uint32_t eecd; 5759 DEBUGFUNC("em_release_eeprom"); 5760 5761 eecd = E1000_READ_REG(hw, EECD); 5762 5763 if (hw->eeprom.type == em_eeprom_spi) { 5764 eecd |= E1000_EECD_CS; /* Pull CS high */ 5765 eecd &= ~E1000_EECD_SK; /* Lower SCK */ 5766 5767 E1000_WRITE_REG(hw, EECD, eecd); 5768 5769 usec_delay(hw->eeprom.delay_usec); 5770 } else if (hw->eeprom.type == em_eeprom_microwire) { 5771 /* cleanup eeprom */ 5772 5773 /* CS on Microwire is active-high */ 5774 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); 5775 5776 E1000_WRITE_REG(hw, EECD, eecd); 5777 5778 /* Rising edge of clock */ 5779 eecd |= E1000_EECD_SK; 5780 E1000_WRITE_REG(hw, EECD, eecd); 5781 E1000_WRITE_FLUSH(hw); 5782 usec_delay(hw->eeprom.delay_usec); 5783 5784 /* Falling edge of clock */ 5785 eecd &= ~E1000_EECD_SK; 5786 E1000_WRITE_REG(hw, EECD, eecd); 5787 E1000_WRITE_FLUSH(hw); 5788 usec_delay(hw->eeprom.delay_usec); 5789 } 5790 /* Stop requesting EEPROM access */ 5791 if (hw->mac_type > em_82544) { 5792 eecd &= ~E1000_EECD_REQ; 5793 E1000_WRITE_REG(hw, EECD, eecd); 5794 } 5795 em_swfw_sync_release(hw, E1000_SWFW_EEP_SM); 5796 } 5797 5798 /****************************************************************************** 5799 * Reads a 16 bit word from the EEPROM. 5800 * 5801 * hw - Struct containing variables accessed by shared code 5802 *****************************************************************************/ 5803 STATIC int32_t 5804 em_spi_eeprom_ready(struct em_hw *hw) 5805 { 5806 uint16_t retry_count = 0; 5807 uint8_t spi_stat_reg; 5808 DEBUGFUNC("em_spi_eeprom_ready"); 5809 /* 5810 * Read "Status Register" repeatedly until the LSB is cleared. The 5811 * EEPROM will signal that the command has been completed by clearing 5812 * bit 0 of the internal status register. If it's not cleared within 5813 * 5 milliseconds, then error out. 5814 */ 5815 retry_count = 0; 5816 do { 5817 em_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI, 5818 hw->eeprom.opcode_bits); 5819 spi_stat_reg = (uint8_t) em_shift_in_ee_bits(hw, 8); 5820 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI)) 5821 break; 5822 5823 usec_delay(5); 5824 retry_count += 5; 5825 5826 em_standby_eeprom(hw); 5827 } while (retry_count < EEPROM_MAX_RETRY_SPI); 5828 /* 5829 * ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and 5830 * only 0-5mSec on 5V devices) 5831 */ 5832 if (retry_count >= EEPROM_MAX_RETRY_SPI) { 5833 DEBUGOUT("SPI EEPROM Status error\n"); 5834 return -E1000_ERR_EEPROM; 5835 } 5836 return E1000_SUCCESS; 5837 } 5838 5839 /****************************************************************************** 5840 * Reads a 16 bit word from the EEPROM. 5841 * 5842 * hw - Struct containing variables accessed by shared code 5843 * offset - offset of word in the EEPROM to read 5844 * data - word read from the EEPROM 5845 * words - number of words to read 5846 *****************************************************************************/ 5847 int32_t 5848 em_read_eeprom(struct em_hw *hw, uint16_t offset, uint16_t words, 5849 uint16_t *data) 5850 { 5851 struct em_eeprom_info *eeprom = &hw->eeprom; 5852 uint32_t i = 0; 5853 DEBUGFUNC("em_read_eeprom"); 5854 5855 /* If eeprom is not yet detected, do so now */ 5856 if (eeprom->word_size == 0) 5857 em_init_eeprom_params(hw); 5858 /* 5859 * A check for invalid values: offset too large, too many words, and 5860 * not enough words. 5861 */ 5862 if ((offset >= eeprom->word_size) || 5863 (words > eeprom->word_size - offset) || 5864 (words == 0)) { 5865 DEBUGOUT2("\"words\" parameter out of bounds. Words = %d," 5866 " size = %d\n", offset, eeprom->word_size); 5867 return -E1000_ERR_EEPROM; 5868 } 5869 /* 5870 * EEPROM's that don't use EERD to read require us to bit-bang the 5871 * SPI directly. In this case, we need to acquire the EEPROM so that 5872 * FW or other port software does not interrupt. 5873 */ 5874 if (em_is_onboard_nvm_eeprom(hw) == TRUE && 5875 hw->eeprom.use_eerd == FALSE) { 5876 /* Prepare the EEPROM for bit-bang reading */ 5877 if (em_acquire_eeprom(hw) != E1000_SUCCESS) 5878 return -E1000_ERR_EEPROM; 5879 } 5880 /* Eerd register EEPROM access requires no eeprom aquire/release */ 5881 if (eeprom->use_eerd == TRUE) 5882 return em_read_eeprom_eerd(hw, offset, words, data); 5883 5884 /* ICH EEPROM access is done via the ICH flash controller */ 5885 if (eeprom->type == em_eeprom_ich8) 5886 return em_read_eeprom_ich8(hw, offset, words, data); 5887 /* 5888 * Set up the SPI or Microwire EEPROM for bit-bang reading. We have 5889 * acquired the EEPROM at this point, so any returns should relase it 5890 */ 5891 if (eeprom->type == em_eeprom_spi) { 5892 uint16_t word_in; 5893 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI; 5894 if (em_spi_eeprom_ready(hw)) { 5895 em_release_eeprom(hw); 5896 return -E1000_ERR_EEPROM; 5897 } 5898 em_standby_eeprom(hw); 5899 /* 5900 * Some SPI eeproms use the 8th address bit embedded in the 5901 * opcode 5902 */ 5903 if ((eeprom->address_bits == 8) && (offset >= 128)) 5904 read_opcode |= EEPROM_A8_OPCODE_SPI; 5905 5906 /* Send the READ command (opcode + addr) */ 5907 em_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits); 5908 em_shift_out_ee_bits(hw, (uint16_t) (offset * 2), 5909 eeprom->address_bits); 5910 /* 5911 * Read the data. The address of the eeprom internally 5912 * increments with each byte (spi) being read, saving on the 5913 * overhead of eeprom setup and tear-down. The address 5914 * counter will roll over if reading beyond the size of the 5915 * eeprom, thus allowing the entire memory to be read 5916 * starting from any offset. 5917 */ 5918 for (i = 0; i < words; i++) { 5919 word_in = em_shift_in_ee_bits(hw, 16); 5920 data[i] = (word_in >> 8) | (word_in << 8); 5921 } 5922 } else if (eeprom->type == em_eeprom_microwire) { 5923 for (i = 0; i < words; i++) { 5924 /* Send the READ command (opcode + addr) */ 5925 em_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE, 5926 eeprom->opcode_bits); 5927 em_shift_out_ee_bits(hw, (uint16_t) (offset + i), 5928 eeprom->address_bits); 5929 /* 5930 * Read the data. For microwire, each word requires 5931 * the overhead of eeprom setup and tear-down. 5932 */ 5933 data[i] = em_shift_in_ee_bits(hw, 16); 5934 em_standby_eeprom(hw); 5935 } 5936 } 5937 /* End this read operation */ 5938 em_release_eeprom(hw); 5939 5940 return E1000_SUCCESS; 5941 } 5942 5943 /****************************************************************************** 5944 * Reads a 16 bit word from the EEPROM using the EERD register. 5945 * 5946 * hw - Struct containing variables accessed by shared code 5947 * offset - offset of word in the EEPROM to read 5948 * data - word read from the EEPROM 5949 * words - number of words to read 5950 *****************************************************************************/ 5951 STATIC int32_t 5952 em_read_eeprom_eerd(struct em_hw *hw, uint16_t offset, uint16_t words, 5953 uint16_t *data) 5954 { 5955 uint32_t i, eerd = 0; 5956 int32_t error = 0; 5957 for (i = 0; i < words; i++) { 5958 eerd = ((offset + i) << E1000_EEPROM_RW_ADDR_SHIFT) + 5959 E1000_EEPROM_RW_REG_START; 5960 5961 E1000_WRITE_REG(hw, EERD, eerd); 5962 error = em_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ); 5963 5964 if (error) { 5965 break; 5966 } 5967 data[i] = (E1000_READ_REG(hw, EERD) >> 5968 E1000_EEPROM_RW_REG_DATA); 5969 5970 } 5971 5972 return error; 5973 } 5974 5975 /****************************************************************************** 5976 * Writes a 16 bit word from the EEPROM using the EEWR register. 5977 * 5978 * hw - Struct containing variables accessed by shared code 5979 * offset - offset of word in the EEPROM to read 5980 * data - word read from the EEPROM 5981 * words - number of words to read 5982 *****************************************************************************/ 5983 STATIC int32_t 5984 em_write_eeprom_eewr(struct em_hw *hw, uint16_t offset, uint16_t words, 5985 uint16_t *data) 5986 { 5987 uint32_t register_value = 0; 5988 uint32_t i = 0; 5989 int32_t error = 0; 5990 if (em_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM)) 5991 return -E1000_ERR_SWFW_SYNC; 5992 5993 for (i = 0; i < words; i++) { 5994 register_value = (data[i] << E1000_EEPROM_RW_REG_DATA) | 5995 ((offset + i) << E1000_EEPROM_RW_ADDR_SHIFT) | 5996 E1000_EEPROM_RW_REG_START; 5997 5998 error = em_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE); 5999 if (error) { 6000 break; 6001 } 6002 E1000_WRITE_REG(hw, EEWR, register_value); 6003 6004 error = em_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE); 6005 6006 if (error) { 6007 break; 6008 } 6009 } 6010 6011 em_swfw_sync_release(hw, E1000_SWFW_EEP_SM); 6012 return error; 6013 } 6014 6015 /****************************************************************************** 6016 * Polls the status bit (bit 1) of the EERD to determine when the read is done. 6017 * 6018 * hw - Struct containing variables accessed by shared code 6019 *****************************************************************************/ 6020 STATIC int32_t 6021 em_poll_eerd_eewr_done(struct em_hw *hw, int eerd) 6022 { 6023 uint32_t attempts = 100000; 6024 uint32_t i, reg = 0; 6025 int32_t done = E1000_ERR_EEPROM; 6026 for (i = 0; i < attempts; i++) { 6027 if (eerd == E1000_EEPROM_POLL_READ) 6028 reg = E1000_READ_REG(hw, EERD); 6029 else 6030 reg = E1000_READ_REG(hw, EEWR); 6031 6032 if (reg & E1000_EEPROM_RW_REG_DONE) { 6033 done = E1000_SUCCESS; 6034 break; 6035 } 6036 usec_delay(5); 6037 } 6038 6039 return done; 6040 } 6041 6042 /****************************************************************************** 6043 * Description: Determines if the onboard NVM is FLASH or EEPROM. 6044 * 6045 * hw - Struct containing variables accessed by shared code 6046 *****************************************************************************/ 6047 STATIC boolean_t 6048 em_is_onboard_nvm_eeprom(struct em_hw *hw) 6049 { 6050 uint32_t eecd = 0; 6051 DEBUGFUNC("em_is_onboard_nvm_eeprom"); 6052 6053 if (hw->mac_type == em_ich8lan || 6054 hw->mac_type == em_ich9lan || 6055 hw->mac_type == em_ich10lan || 6056 hw->mac_type == em_pchlan || 6057 hw->mac_type == em_pch2lan) 6058 return FALSE; 6059 6060 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) { 6061 eecd = E1000_READ_REG(hw, EECD); 6062 6063 /* Isolate bits 15 & 16 */ 6064 eecd = ((eecd >> 15) & 0x03); 6065 6066 /* If both bits are set, device is Flash type */ 6067 if (eecd == 0x03) { 6068 return FALSE; 6069 } 6070 } 6071 return TRUE; 6072 } 6073 6074 /****************************************************************************** 6075 * Verifies that the EEPROM has a valid checksum 6076 * 6077 * hw - Struct containing variables accessed by shared code 6078 * 6079 * Reads the first 64 16 bit words of the EEPROM and sums the values read. 6080 * If the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is 6081 * valid. 6082 *****************************************************************************/ 6083 int32_t 6084 em_validate_eeprom_checksum(struct em_hw *hw) 6085 { 6086 uint16_t checksum = 0; 6087 uint16_t i, eeprom_data; 6088 uint16_t checksum_reg; 6089 DEBUGFUNC("em_validate_eeprom_checksum"); 6090 6091 checksum_reg = hw->mac_type != em_icp_xxxx ? 6092 EEPROM_CHECKSUM_REG : 6093 EEPROM_CHECKSUM_REG_ICP_xxxx; 6094 6095 if (((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) && 6096 (em_is_onboard_nvm_eeprom(hw) == FALSE)) { 6097 /* 6098 * Check bit 4 of word 10h. If it is 0, firmware is done 6099 * updating 10h-12h. Checksum may need to be fixed. 6100 */ 6101 em_read_eeprom(hw, 0x10, 1, &eeprom_data); 6102 if ((eeprom_data & 0x10) == 0) { 6103 /* 6104 * Read 0x23 and check bit 15. This bit is a 1 when 6105 * the checksum has already been fixed. If the 6106 * checksum is still wrong and this bit is a 1, we 6107 * need to return bad checksum. Otherwise, we need 6108 * to set this bit to a 1 and update the checksum. 6109 */ 6110 em_read_eeprom(hw, 0x23, 1, &eeprom_data); 6111 if ((eeprom_data & 0x8000) == 0) { 6112 eeprom_data |= 0x8000; 6113 em_write_eeprom(hw, 0x23, 1, &eeprom_data); 6114 em_update_eeprom_checksum(hw); 6115 } 6116 } 6117 } 6118 if (hw->mac_type == em_ich8lan || 6119 hw->mac_type == em_ich9lan || 6120 hw->mac_type == em_ich10lan || 6121 hw->mac_type == em_pchlan || 6122 hw->mac_type == em_pch2lan) { 6123 /* 6124 * Drivers must allocate the shadow ram structure for the 6125 * EEPROM checksum to be updated. Otherwise, this bit as 6126 * well as the checksum must both be set correctly for this 6127 * validation to pass. 6128 */ 6129 em_read_eeprom(hw, 0x19, 1, &eeprom_data); 6130 if ((eeprom_data & 0x40) == 0) { 6131 eeprom_data |= 0x40; 6132 em_write_eeprom(hw, 0x19, 1, &eeprom_data); 6133 em_update_eeprom_checksum(hw); 6134 } 6135 } 6136 for (i = 0; i < (checksum_reg + 1); i++) { 6137 if (em_read_eeprom(hw, i, 1, &eeprom_data) < 0) { 6138 DEBUGOUT("EEPROM Read Error\n"); 6139 return -E1000_ERR_EEPROM; 6140 } 6141 checksum += eeprom_data; 6142 } 6143 6144 if (checksum == (uint16_t) EEPROM_SUM) 6145 return E1000_SUCCESS; 6146 else { 6147 DEBUGOUT("EEPROM Checksum Invalid\n"); 6148 return -E1000_ERR_EEPROM; 6149 } 6150 } 6151 6152 /****************************************************************************** 6153 * Calculates the EEPROM checksum and writes it to the EEPROM 6154 * 6155 * hw - Struct containing variables accessed by shared code 6156 * 6157 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA. 6158 * Writes the difference to word offset 63 of the EEPROM. 6159 *****************************************************************************/ 6160 int32_t 6161 em_update_eeprom_checksum(struct em_hw *hw) 6162 { 6163 uint32_t ctrl_ext; 6164 uint16_t checksum = 0; 6165 uint16_t i, eeprom_data; 6166 DEBUGFUNC("em_update_eeprom_checksum"); 6167 6168 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) { 6169 if (em_read_eeprom(hw, i, 1, &eeprom_data) < 0) { 6170 DEBUGOUT("EEPROM Read Error\n"); 6171 return -E1000_ERR_EEPROM; 6172 } 6173 checksum += eeprom_data; 6174 } 6175 checksum = (uint16_t) EEPROM_SUM - checksum; 6176 if (em_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) { 6177 DEBUGOUT("EEPROM Write Error\n"); 6178 return -E1000_ERR_EEPROM; 6179 } else if (hw->eeprom.type == em_eeprom_flash) { 6180 em_commit_shadow_ram(hw); 6181 } else if (hw->eeprom.type == em_eeprom_ich8) { 6182 em_commit_shadow_ram(hw); 6183 /* 6184 * Reload the EEPROM, or else modifications will not appear 6185 * until after next adapter reset. 6186 */ 6187 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 6188 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 6189 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 6190 msec_delay(10); 6191 } 6192 return E1000_SUCCESS; 6193 } 6194 6195 /****************************************************************************** 6196 * Parent function for writing words to the different EEPROM types. 6197 * 6198 * hw - Struct containing variables accessed by shared code 6199 * offset - offset within the EEPROM to be written to 6200 * words - number of words to write 6201 * data - 16 bit word to be written to the EEPROM 6202 * 6203 * If em_update_eeprom_checksum is not called after this function, the 6204 * EEPROM will most likely contain an invalid checksum. 6205 *****************************************************************************/ 6206 int32_t 6207 em_write_eeprom(struct em_hw *hw, uint16_t offset, uint16_t words, 6208 uint16_t *data) 6209 { 6210 struct em_eeprom_info *eeprom = &hw->eeprom; 6211 int32_t status = 0; 6212 DEBUGFUNC("em_write_eeprom"); 6213 6214 /* If eeprom is not yet detected, do so now */ 6215 if (eeprom->word_size == 0) 6216 em_init_eeprom_params(hw); 6217 /* 6218 * A check for invalid values: offset too large, too many words, and 6219 * not enough words. 6220 */ 6221 if ((offset >= eeprom->word_size) || 6222 (words > eeprom->word_size - offset) || 6223 (words == 0)) { 6224 DEBUGOUT("\"words\" parameter out of bounds\n"); 6225 return -E1000_ERR_EEPROM; 6226 } 6227 /* 82573/4 writes only through eewr */ 6228 if (eeprom->use_eewr == TRUE) 6229 return em_write_eeprom_eewr(hw, offset, words, data); 6230 6231 if (eeprom->type == em_eeprom_ich8) 6232 return em_write_eeprom_ich8(hw, offset, words, data); 6233 6234 /* Prepare the EEPROM for writing */ 6235 if (em_acquire_eeprom(hw) != E1000_SUCCESS) 6236 return -E1000_ERR_EEPROM; 6237 6238 if (eeprom->type == em_eeprom_microwire) { 6239 status = em_write_eeprom_microwire(hw, offset, words, data); 6240 } else { 6241 status = em_write_eeprom_spi(hw, offset, words, data); 6242 msec_delay(10); 6243 } 6244 6245 /* Done with writing */ 6246 em_release_eeprom(hw); 6247 6248 return status; 6249 } 6250 6251 /****************************************************************************** 6252 * Writes a 16 bit word to a given offset in an SPI EEPROM. 6253 * 6254 * hw - Struct containing variables accessed by shared code 6255 * offset - offset within the EEPROM to be written to 6256 * words - number of words to write 6257 * data - pointer to array of 8 bit words to be written to the EEPROM 6258 * 6259 *****************************************************************************/ 6260 STATIC int32_t 6261 em_write_eeprom_spi(struct em_hw *hw, uint16_t offset, uint16_t words, 6262 uint16_t *data) 6263 { 6264 struct em_eeprom_info *eeprom = &hw->eeprom; 6265 uint16_t widx = 0; 6266 DEBUGFUNC("em_write_eeprom_spi"); 6267 6268 while (widx < words) { 6269 uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI; 6270 if (em_spi_eeprom_ready(hw)) 6271 return -E1000_ERR_EEPROM; 6272 6273 em_standby_eeprom(hw); 6274 6275 /* Send the WRITE ENABLE command (8 bit opcode ) */ 6276 em_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI, 6277 eeprom->opcode_bits); 6278 6279 em_standby_eeprom(hw); 6280 /* 6281 * Some SPI eeproms use the 8th address bit embedded in the 6282 * opcode 6283 */ 6284 if ((eeprom->address_bits == 8) && (offset >= 128)) 6285 write_opcode |= EEPROM_A8_OPCODE_SPI; 6286 6287 /* Send the Write command (8-bit opcode + addr) */ 6288 em_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits); 6289 6290 em_shift_out_ee_bits(hw, (uint16_t) ((offset + widx) * 2), 6291 eeprom->address_bits); 6292 6293 /* Send the data */ 6294 /* 6295 * Loop to allow for up to whole page write (32 bytes) of 6296 * eeprom 6297 */ 6298 while (widx < words) { 6299 uint16_t word_out = data[widx]; 6300 word_out = (word_out >> 8) | (word_out << 8); 6301 em_shift_out_ee_bits(hw, word_out, 16); 6302 widx++; 6303 /* 6304 * Some larger eeprom sizes are capable of a 32-byte 6305 * PAGE WRITE operation, while the smaller eeproms 6306 * are capable of an 8-byte PAGE WRITE operation. 6307 * Break the inner loop to pass new address 6308 */ 6309 if ((((offset + widx) * 2) % eeprom->page_size) == 0) { 6310 em_standby_eeprom(hw); 6311 break; 6312 } 6313 } 6314 } 6315 6316 return E1000_SUCCESS; 6317 } 6318 6319 /****************************************************************************** 6320 * Writes a 16 bit word to a given offset in a Microwire EEPROM. 6321 * 6322 * hw - Struct containing variables accessed by shared code 6323 * offset - offset within the EEPROM to be written to 6324 * words - number of words to write 6325 * data - pointer to array of 16 bit words to be written to the EEPROM 6326 * 6327 *****************************************************************************/ 6328 STATIC int32_t 6329 em_write_eeprom_microwire(struct em_hw *hw, uint16_t offset, uint16_t words, 6330 uint16_t *data) 6331 { 6332 struct em_eeprom_info *eeprom = &hw->eeprom; 6333 uint32_t eecd; 6334 uint16_t words_written = 0; 6335 uint16_t i = 0; 6336 DEBUGFUNC("em_write_eeprom_microwire"); 6337 /* 6338 * Send the write enable command to the EEPROM (3-bit opcode plus 6339 * 6/8-bit dummy address beginning with 11). It's less work to 6340 * include the 11 of the dummy address as part of the opcode than it 6341 * is to shift it over the correct number of bits for the address. 6342 * This puts the EEPROM into write/erase mode. 6343 */ 6344 em_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE, 6345 (uint16_t) (eeprom->opcode_bits + 2)); 6346 6347 em_shift_out_ee_bits(hw, 0, (uint16_t) (eeprom->address_bits - 2)); 6348 6349 /* Prepare the EEPROM */ 6350 em_standby_eeprom(hw); 6351 6352 while (words_written < words) { 6353 /* Send the Write command (3-bit opcode + addr) */ 6354 em_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE, 6355 eeprom->opcode_bits); 6356 6357 em_shift_out_ee_bits(hw, (uint16_t) (offset + words_written), 6358 eeprom->address_bits); 6359 6360 /* Send the data */ 6361 em_shift_out_ee_bits(hw, data[words_written], 16); 6362 /* 6363 * Toggle the CS line. This in effect tells the EEPROM to 6364 * execute the previous command. 6365 */ 6366 em_standby_eeprom(hw); 6367 /* 6368 * Read DO repeatedly until it is high (equal to '1'). The 6369 * EEPROM will signal that the command has been completed by 6370 * raising the DO signal. If DO does not go high in 10 6371 * milliseconds, then error out. 6372 */ 6373 for (i = 0; i < 200; i++) { 6374 eecd = E1000_READ_REG(hw, EECD); 6375 if (eecd & E1000_EECD_DO) 6376 break; 6377 usec_delay(50); 6378 } 6379 if (i == 200) { 6380 DEBUGOUT("EEPROM Write did not complete\n"); 6381 return -E1000_ERR_EEPROM; 6382 } 6383 /* Recover from write */ 6384 em_standby_eeprom(hw); 6385 6386 words_written++; 6387 } 6388 /* 6389 * Send the write disable command to the EEPROM (3-bit opcode plus 6390 * 6/8-bit dummy address beginning with 10). It's less work to 6391 * include the 10 of the dummy address as part of the opcode than it 6392 * is to shift it over the correct number of bits for the address. 6393 * This takes the EEPROM out of write/erase mode. 6394 */ 6395 em_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE, 6396 (uint16_t) (eeprom->opcode_bits + 2)); 6397 6398 em_shift_out_ee_bits(hw, 0, (uint16_t) (eeprom->address_bits - 2)); 6399 6400 return E1000_SUCCESS; 6401 } 6402 6403 /****************************************************************************** 6404 * Flushes the cached eeprom to NVM. This is done by saving the modified values 6405 * in the eeprom cache and the non modified values in the currently active bank 6406 * to the new bank. 6407 * 6408 * hw - Struct containing variables accessed by shared code 6409 * offset - offset of word in the EEPROM to read 6410 * data - word read from the EEPROM 6411 * words - number of words to read 6412 *****************************************************************************/ 6413 STATIC int32_t 6414 em_commit_shadow_ram(struct em_hw *hw) 6415 { 6416 uint32_t attempts = 100000; 6417 uint32_t eecd = 0; 6418 uint32_t flop = 0; 6419 uint32_t i = 0; 6420 int32_t error = E1000_SUCCESS; 6421 uint32_t old_bank_offset = 0; 6422 uint32_t new_bank_offset = 0; 6423 uint8_t low_byte = 0; 6424 uint8_t high_byte = 0; 6425 boolean_t sector_write_failed = FALSE; 6426 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) { 6427 /* 6428 * The flop register will be used to determine if flash type 6429 * is STM 6430 */ 6431 flop = E1000_READ_REG(hw, FLOP); 6432 for (i = 0; i < attempts; i++) { 6433 eecd = E1000_READ_REG(hw, EECD); 6434 if ((eecd & E1000_EECD_FLUPD) == 0) { 6435 break; 6436 } 6437 usec_delay(5); 6438 } 6439 6440 if (i == attempts) { 6441 return -E1000_ERR_EEPROM; 6442 } 6443 /* 6444 * If STM opcode located in bits 15:8 of flop, reset firmware 6445 */ 6446 if ((flop & 0xFF00) == E1000_STM_OPCODE) { 6447 E1000_WRITE_REG(hw, HICR, E1000_HICR_FW_RESET); 6448 } 6449 /* Perform the flash update */ 6450 E1000_WRITE_REG(hw, EECD, eecd | E1000_EECD_FLUPD); 6451 6452 for (i = 0; i < attempts; i++) { 6453 eecd = E1000_READ_REG(hw, EECD); 6454 if ((eecd & E1000_EECD_FLUPD) == 0) { 6455 break; 6456 } 6457 usec_delay(5); 6458 } 6459 6460 if (i == attempts) { 6461 return -E1000_ERR_EEPROM; 6462 } 6463 } 6464 if ((hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) && 6465 hw->eeprom_shadow_ram != NULL) { 6466 /* 6467 * We're writing to the opposite bank so if we're on bank 1, 6468 * write to bank 0 etc. We also need to erase the segment 6469 * that is going to be written 6470 */ 6471 if (!(E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL)) { 6472 new_bank_offset = hw->flash_bank_size * 2; 6473 old_bank_offset = 0; 6474 em_erase_ich8_4k_segment(hw, 1); 6475 } else { 6476 old_bank_offset = hw->flash_bank_size * 2; 6477 new_bank_offset = 0; 6478 em_erase_ich8_4k_segment(hw, 0); 6479 } 6480 6481 sector_write_failed = FALSE; 6482 /* 6483 * Loop for every byte in the shadow RAM, which is in units 6484 * of words. 6485 */ 6486 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 6487 /* 6488 * Determine whether to write the value stored in the 6489 * other NVM bank or a modified value stored in the 6490 * shadow RAM 6491 */ 6492 if (hw->eeprom_shadow_ram[i].modified == TRUE) { 6493 low_byte = (uint8_t) 6494 hw->eeprom_shadow_ram[i].eeprom_word; 6495 usec_delay(100); 6496 error = em_verify_write_ich8_byte(hw, 6497 (i << 1) + new_bank_offset, low_byte); 6498 6499 if (error != E1000_SUCCESS) 6500 sector_write_failed = TRUE; 6501 else { 6502 high_byte = (uint8_t) 6503 (hw->eeprom_shadow_ram 6504 [i].eeprom_word >> 8); 6505 usec_delay(100); 6506 } 6507 } else { 6508 em_read_ich8_byte(hw, (i << 1) + 6509 old_bank_offset, &low_byte); 6510 usec_delay(100); 6511 error = em_verify_write_ich8_byte(hw, 6512 (i << 1) + new_bank_offset, low_byte); 6513 6514 if (error != E1000_SUCCESS) 6515 sector_write_failed = TRUE; 6516 else { 6517 em_read_ich8_byte(hw, (i << 1) + 6518 old_bank_offset + 1, &high_byte); 6519 usec_delay(100); 6520 } 6521 } 6522 /* 6523 * If the write of the low byte was successful, go 6524 * ahread and write the high byte while checking to 6525 * make sure that if it is the signature byte, then 6526 * it is handled properly 6527 */ 6528 if (sector_write_failed == FALSE) { 6529 /* 6530 * If the word is 0x13, then make sure the 6531 * signature bits (15:14) are 11b until the 6532 * commit has completed. This will allow us 6533 * to write 10b which indicates the signature 6534 * is valid. We want to do this after the 6535 * write has completed so that we don't mark 6536 * the segment valid while the write is still 6537 * in progress 6538 */ 6539 if (i == E1000_ICH_NVM_SIG_WORD) 6540 high_byte = E1000_ICH_NVM_SIG_MASK | 6541 high_byte; 6542 6543 error = em_verify_write_ich8_byte(hw, (i << 1) 6544 + new_bank_offset + 1, high_byte); 6545 if (error != E1000_SUCCESS) 6546 sector_write_failed = TRUE; 6547 6548 } else { 6549 /* 6550 * If the write failed then break from the 6551 * loop and return an error 6552 */ 6553 break; 6554 } 6555 } 6556 /* 6557 * Don't bother writing the segment valid bits if sector 6558 * programming failed. 6559 */ 6560 if (sector_write_failed == FALSE) { 6561 /* 6562 * Finally validate the new segment by setting bit 6563 * 15:14 to 10b in word 0x13 , this can be done 6564 * without an erase as well since these bits are 11 6565 * to start with and we need to change bit 14 to 0b 6566 */ 6567 em_read_ich8_byte(hw, E1000_ICH_NVM_SIG_WORD * 2 + 1 + 6568 new_bank_offset, &high_byte); 6569 high_byte &= 0xBF; 6570 error = em_verify_write_ich8_byte(hw, 6571 E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset, 6572 high_byte); 6573 /* 6574 * And invalidate the previously valid segment by 6575 * setting its signature word (0x13) high_byte to 0b. 6576 * This can be done without an erase because flash 6577 * erase sets all bits to 1's. We can write 1's to 6578 * 0's without an erase 6579 */ 6580 if (error == E1000_SUCCESS) { 6581 error = em_verify_write_ich8_byte(hw, 6582 E1000_ICH_NVM_SIG_WORD * 2 + 1 + 6583 old_bank_offset, 0); 6584 } 6585 /* Clear the now not used entry in the cache */ 6586 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 6587 hw->eeprom_shadow_ram[i].modified = FALSE; 6588 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF; 6589 } 6590 } 6591 } 6592 return error; 6593 } 6594 6595 /****************************************************************************** 6596 * Reads the adapter's part number from the EEPROM 6597 * 6598 * hw - Struct containing variables accessed by shared code 6599 * part_num - Adapter's part number 6600 *****************************************************************************/ 6601 int32_t 6602 em_read_part_num(struct em_hw *hw, uint32_t *part_num) 6603 { 6604 uint16_t offset = EEPROM_PBA_BYTE_1; 6605 uint16_t eeprom_data; 6606 DEBUGFUNC("em_read_part_num"); 6607 6608 /* Get word 0 from EEPROM */ 6609 if (em_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { 6610 DEBUGOUT("EEPROM Read Error\n"); 6611 return -E1000_ERR_EEPROM; 6612 } 6613 /* Save word 0 in upper half of part_num */ 6614 *part_num = (uint32_t) (eeprom_data << 16); 6615 6616 /* Get word 1 from EEPROM */ 6617 if (em_read_eeprom(hw, ++offset, 1, &eeprom_data) < 0) { 6618 DEBUGOUT("EEPROM Read Error\n"); 6619 return -E1000_ERR_EEPROM; 6620 } 6621 /* Save word 1 in lower half of part_num */ 6622 *part_num |= eeprom_data; 6623 6624 return E1000_SUCCESS; 6625 } 6626 6627 /****************************************************************************** 6628 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the 6629 * second function of dual function devices 6630 * 6631 * hw - Struct containing variables accessed by shared code 6632 *****************************************************************************/ 6633 int32_t 6634 em_read_mac_addr(struct em_hw *hw) 6635 { 6636 uint16_t offset; 6637 uint16_t eeprom_data, i; 6638 uint16_t ia_base_addr = 0; 6639 DEBUGFUNC("em_read_mac_addr"); 6640 6641 if (hw->mac_type == em_icp_xxxx) { 6642 ia_base_addr = (uint16_t) 6643 EEPROM_IA_START_ICP_xxxx(hw->icp_xxxx_port_num); 6644 } 6645 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) { 6646 offset = i >> 1; 6647 if (em_read_eeprom(hw, offset + ia_base_addr, 1, &eeprom_data) 6648 < 0) { 6649 DEBUGOUT("EEPROM Read Error\n"); 6650 return -E1000_ERR_EEPROM; 6651 } 6652 hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF); 6653 hw->perm_mac_addr[i + 1] = (uint8_t) (eeprom_data >> 8); 6654 } 6655 6656 switch (hw->mac_type) { 6657 default: 6658 break; 6659 case em_82546: 6660 case em_82546_rev_3: 6661 case em_82571: 6662 case em_82575: 6663 case em_82580: 6664 case em_80003es2lan: 6665 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) 6666 hw->perm_mac_addr[5] ^= 0x01; 6667 break; 6668 } 6669 6670 for (i = 0; i < NODE_ADDRESS_SIZE; i++) 6671 hw->mac_addr[i] = hw->perm_mac_addr[i]; 6672 return E1000_SUCCESS; 6673 } 6674 6675 /****************************************************************************** 6676 * Initializes receive address filters. 6677 * 6678 * hw - Struct containing variables accessed by shared code 6679 * 6680 * Places the MAC address in receive address register 0 and clears the rest 6681 * of the receive addresss registers. Clears the multicast table. Assumes 6682 * the receiver is in reset when the routine is called. 6683 *****************************************************************************/ 6684 STATIC void 6685 em_init_rx_addrs(struct em_hw *hw) 6686 { 6687 uint32_t i; 6688 uint32_t rar_num; 6689 DEBUGFUNC("em_init_rx_addrs"); 6690 6691 /* Setup the receive address. */ 6692 DEBUGOUT("Programming MAC Address into RAR[0]\n"); 6693 6694 em_rar_set(hw, hw->mac_addr, 0); 6695 6696 rar_num = E1000_RAR_ENTRIES; 6697 /* 6698 * Reserve a spot for the Locally Administered Address to work around 6699 * an 82571 issue in which a reset on one port will reload the MAC on 6700 * the other port. 6701 */ 6702 if ((hw->mac_type == em_82571) && (hw->laa_is_present == TRUE)) 6703 rar_num -= 1; 6704 if (hw->mac_type == em_ich8lan || 6705 hw->mac_type == em_ich9lan || 6706 hw->mac_type == em_ich10lan || 6707 hw->mac_type == em_pchlan || 6708 hw->mac_type == em_pch2lan) 6709 rar_num = E1000_RAR_ENTRIES_ICH8LAN; 6710 if (hw->mac_type == em_ich8lan) 6711 rar_num -= 1; 6712 if (hw->mac_type == em_82580) 6713 rar_num = E1000_RAR_ENTRIES_82580; 6714 6715 /* Zero out the other 15 receive addresses. */ 6716 DEBUGOUT("Clearing RAR[1-15]\n"); 6717 for (i = 1; i < rar_num; i++) { 6718 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 6719 E1000_WRITE_FLUSH(hw); 6720 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 6721 E1000_WRITE_FLUSH(hw); 6722 } 6723 } 6724 6725 /****************************************************************************** 6726 * Updates the MAC's list of multicast addresses. 6727 * 6728 * hw - Struct containing variables accessed by shared code 6729 * mc_addr_list - the list of new multicast addresses 6730 * mc_addr_count - number of addresses 6731 * pad - number of bytes between addresses in the list 6732 * rar_used_count - offset where to start adding mc addresses into the RAR's 6733 * 6734 * The given list replaces any existing list. Clears the last 15 receive 6735 * address registers and the multicast table. Uses receive address registers 6736 * for the first 15 multicast addresses, and hashes the rest into the 6737 * multicast table. 6738 *****************************************************************************/ 6739 void 6740 em_mc_addr_list_update(struct em_hw *hw, uint8_t *mc_addr_list, 6741 uint32_t mc_addr_count, uint32_t pad, uint32_t rar_used_count) 6742 { 6743 uint32_t hash_value; 6744 uint32_t i; 6745 uint32_t num_rar_entry; 6746 uint32_t num_mta_entry; 6747 DEBUGFUNC("em_mc_addr_list_update"); 6748 /* 6749 * Set the new number of MC addresses that we are being requested to 6750 * use. 6751 */ 6752 hw->num_mc_addrs = mc_addr_count; 6753 6754 /* Clear RAR[1-15] */ 6755 DEBUGOUT(" Clearing RAR[1-15]\n"); 6756 num_rar_entry = E1000_RAR_ENTRIES; 6757 if (hw->mac_type == em_ich8lan || 6758 hw->mac_type == em_ich9lan || 6759 hw->mac_type == em_ich10lan || 6760 hw->mac_type == em_pchlan || 6761 hw->mac_type == em_pch2lan) 6762 num_rar_entry = E1000_RAR_ENTRIES_ICH8LAN; 6763 if (hw->mac_type == em_ich8lan) 6764 num_rar_entry -= 1; 6765 /* 6766 * Reserve a spot for the Locally Administered Address to work around 6767 * an 82571 issue in which a reset on one port will reload the MAC on 6768 * the other port. 6769 */ 6770 if ((hw->mac_type == em_82571) && (hw->laa_is_present == TRUE)) 6771 num_rar_entry -= 1; 6772 6773 for (i = rar_used_count; i < num_rar_entry; i++) { 6774 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 6775 E1000_WRITE_FLUSH(hw); 6776 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 6777 E1000_WRITE_FLUSH(hw); 6778 } 6779 6780 /* Clear the MTA */ 6781 DEBUGOUT(" Clearing MTA\n"); 6782 num_mta_entry = E1000_NUM_MTA_REGISTERS; 6783 if (hw->mac_type == em_ich8lan || 6784 hw->mac_type == em_ich9lan || 6785 hw->mac_type == em_ich10lan || 6786 hw->mac_type == em_pchlan || 6787 hw->mac_type == em_pch2lan) 6788 num_mta_entry = E1000_NUM_MTA_REGISTERS_ICH8LAN; 6789 6790 for (i = 0; i < num_mta_entry; i++) { 6791 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 6792 E1000_WRITE_FLUSH(hw); 6793 } 6794 6795 /* Add the new addresses */ 6796 for (i = 0; i < mc_addr_count; i++) { 6797 DEBUGOUT(" Adding the multicast addresses:\n"); 6798 DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i, 6799 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad)], 6800 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 1], 6801 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 2], 6802 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 3], 6803 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 4], 6804 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 5]); 6805 6806 hash_value = em_hash_mc_addr(hw, mc_addr_list + 6807 (i * (ETH_LENGTH_OF_ADDRESS + pad))); 6808 6809 DEBUGOUT1(" Hash value = 0x%03X\n", hash_value); 6810 /* 6811 * Place this multicast address in the RAR if there is room, * 6812 * else put it in the MTA 6813 */ 6814 if (rar_used_count < num_rar_entry) { 6815 em_rar_set(hw, mc_addr_list + 6816 (i * (ETH_LENGTH_OF_ADDRESS + pad)), 6817 rar_used_count); 6818 rar_used_count++; 6819 } else { 6820 em_mta_set(hw, hash_value); 6821 } 6822 } 6823 DEBUGOUT("MC Update Complete\n"); 6824 } 6825 6826 /****************************************************************************** 6827 * Hashes an address to determine its location in the multicast table 6828 * 6829 * hw - Struct containing variables accessed by shared code 6830 * mc_addr - the multicast address to hash 6831 *****************************************************************************/ 6832 uint32_t 6833 em_hash_mc_addr(struct em_hw *hw, uint8_t *mc_addr) 6834 { 6835 uint32_t hash_value = 0; 6836 /* 6837 * The portion of the address that is used for the hash table is 6838 * determined by the mc_filter_type setting. 6839 */ 6840 switch (hw->mc_filter_type) { 6841 /* 6842 * [0] [1] [2] [3] [4] [5] 01 AA 00 12 34 56 LSB 6843 * MSB 6844 */ 6845 case 0: 6846 if (hw->mac_type == em_ich8lan || 6847 hw->mac_type == em_ich9lan || 6848 hw->mac_type == em_ich10lan || 6849 hw->mac_type == em_pchlan || 6850 hw->mac_type == em_pch2lan) { 6851 /* [47:38] i.e. 0x158 for above example address */ 6852 hash_value = ((mc_addr[4] >> 6) | 6853 (((uint16_t) mc_addr[5]) << 2)); 6854 } else { 6855 /* [47:36] i.e. 0x563 for above example address */ 6856 hash_value = ((mc_addr[4] >> 4) | 6857 (((uint16_t) mc_addr[5]) << 4)); 6858 } 6859 break; 6860 case 1: 6861 if (hw->mac_type == em_ich8lan || 6862 hw->mac_type == em_ich9lan || 6863 hw->mac_type == em_ich10lan || 6864 hw->mac_type == em_pchlan || 6865 hw->mac_type == em_pch2lan) { 6866 /* [46:37] i.e. 0x2B1 for above example address */ 6867 hash_value = ((mc_addr[4] >> 5) | 6868 (((uint16_t) mc_addr[5]) << 3)); 6869 } else { 6870 /* [46:35] i.e. 0xAC6 for above example address */ 6871 hash_value = ((mc_addr[4] >> 3) | 6872 (((uint16_t) mc_addr[5]) << 5)); 6873 } 6874 break; 6875 case 2: 6876 if (hw->mac_type == em_ich8lan || 6877 hw->mac_type == em_ich9lan || 6878 hw->mac_type == em_ich10lan || 6879 hw->mac_type == em_pchlan || 6880 hw->mac_type == em_pch2lan) { 6881 /* [45:36] i.e. 0x163 for above example address */ 6882 hash_value = ((mc_addr[4] >> 4) | 6883 (((uint16_t) mc_addr[5]) << 4)); 6884 } else { 6885 /* [45:34] i.e. 0x5D8 for above example address */ 6886 hash_value = ((mc_addr[4] >> 2) | 6887 (((uint16_t) mc_addr[5]) << 6)); 6888 } 6889 break; 6890 case 3: 6891 if (hw->mac_type == em_ich8lan || 6892 hw->mac_type == em_ich9lan || 6893 hw->mac_type == em_ich10lan || 6894 hw->mac_type == em_pchlan || 6895 hw->mac_type == em_pch2lan) { 6896 /* [43:34] i.e. 0x18D for above example address */ 6897 hash_value = ((mc_addr[4] >> 2) | 6898 (((uint16_t) mc_addr[5]) << 6)); 6899 } else { 6900 /* [43:32] i.e. 0x634 for above example address */ 6901 hash_value = ((mc_addr[4]) | 6902 (((uint16_t) mc_addr[5]) << 8)); 6903 } 6904 break; 6905 } 6906 6907 hash_value &= 0xFFF; 6908 if (hw->mac_type == em_ich8lan || 6909 hw->mac_type == em_ich9lan || 6910 hw->mac_type == em_ich10lan || 6911 hw->mac_type == em_pchlan || 6912 hw->mac_type == em_pch2lan) 6913 hash_value &= 0x3FF; 6914 6915 return hash_value; 6916 } 6917 6918 /****************************************************************************** 6919 * Sets the bit in the multicast table corresponding to the hash value. 6920 * 6921 * hw - Struct containing variables accessed by shared code 6922 * hash_value - Multicast address hash value 6923 *****************************************************************************/ 6924 void 6925 em_mta_set(struct em_hw *hw, uint32_t hash_value) 6926 { 6927 uint32_t hash_bit, hash_reg; 6928 uint32_t mta; 6929 uint32_t temp; 6930 /* 6931 * The MTA is a register array of 128 32-bit registers. It is treated 6932 * like an array of 4096 bits. We want to set bit 6933 * BitArray[hash_value]. So we figure out what register the bit is 6934 * in, read it, OR in the new bit, then write back the new value. 6935 * The register is determined by the upper 7 bits of the hash value 6936 * and the bit within that register are determined by the lower 5 6937 * bits of the value. 6938 */ 6939 hash_reg = (hash_value >> 5) & 0x7F; 6940 if (hw->mac_type == em_ich8lan || 6941 hw->mac_type == em_ich9lan || 6942 hw->mac_type == em_ich10lan || 6943 hw->mac_type == em_pchlan || 6944 hw->mac_type == em_pch2lan) 6945 hash_reg &= 0x1F; 6946 6947 hash_bit = hash_value & 0x1F; 6948 6949 mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg); 6950 6951 mta |= (1 << hash_bit); 6952 /* 6953 * If we are on an 82544 and we are trying to write an odd offset in 6954 * the MTA, save off the previous entry before writing and restore 6955 * the old value after writing. 6956 */ 6957 if ((hw->mac_type == em_82544) && ((hash_reg & 0x1) == 1)) { 6958 temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1)); 6959 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta); 6960 E1000_WRITE_FLUSH(hw); 6961 E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp); 6962 E1000_WRITE_FLUSH(hw); 6963 } else { 6964 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta); 6965 E1000_WRITE_FLUSH(hw); 6966 } 6967 } 6968 6969 /****************************************************************************** 6970 * Puts an ethernet address into a receive address register. 6971 * 6972 * hw - Struct containing variables accessed by shared code 6973 * addr - Address to put into receive address register 6974 * index - Receive address register to write 6975 *****************************************************************************/ 6976 void 6977 em_rar_set(struct em_hw *hw, uint8_t *addr, uint32_t index) 6978 { 6979 uint32_t rar_low, rar_high; 6980 /* 6981 * HW expects these in little endian so we reverse the byte order 6982 * from network order (big endian) to little endian 6983 */ 6984 rar_low = ((uint32_t) addr[0] | ((uint32_t) addr[1] << 8) | 6985 ((uint32_t) addr[2] << 16) | ((uint32_t) addr[3] << 24)); 6986 rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8)); 6987 /* 6988 * Disable Rx and flush all Rx frames before enabling RSS to avoid Rx 6989 * unit hang. 6990 * 6991 * Description: If there are any Rx frames queued up or otherwise 6992 * present in the HW before RSS is enabled, and then we enable RSS, 6993 * the HW Rx unit will hang. To work around this issue, we have to 6994 * disable receives and flush out all Rx frames before we enable RSS. 6995 * To do so, we modify we redirect all Rx traffic to manageability 6996 * and then reset the HW. This flushes away Rx frames, and (since the 6997 * redirections to manageability persists across resets) keeps new 6998 * ones from coming in while we work. Then, we clear the Address 6999 * Valid AV bit for all MAC addresses and undo the re-direction to 7000 * manageability. Now, frames are coming in again, but the MAC won't 7001 * accept them, so far so good. We now proceed to initialize RSS (if 7002 * necessary) and configure the Rx unit. Last, we re-enable the AV 7003 * bits and continue on our merry way. 7004 */ 7005 switch (hw->mac_type) { 7006 case em_82571: 7007 case em_82572: 7008 case em_80003es2lan: 7009 if (hw->leave_av_bit_off == TRUE) 7010 break; 7011 default: 7012 /* Indicate to hardware the Address is Valid. */ 7013 rar_high |= E1000_RAH_AV; 7014 break; 7015 } 7016 7017 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low); 7018 E1000_WRITE_FLUSH(hw); 7019 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high); 7020 E1000_WRITE_FLUSH(hw); 7021 } 7022 7023 /****************************************************************************** 7024 * Clears the VLAN filer table 7025 * 7026 * hw - Struct containing variables accessed by shared code 7027 *****************************************************************************/ 7028 STATIC void 7029 em_clear_vfta(struct em_hw *hw) 7030 { 7031 uint32_t offset; 7032 uint32_t vfta_value = 0; 7033 uint32_t vfta_offset = 0; 7034 uint32_t vfta_bit_in_reg = 0; 7035 if (hw->mac_type == em_ich8lan || 7036 hw->mac_type == em_ich9lan || 7037 hw->mac_type == em_ich10lan || 7038 hw->mac_type == em_pchlan || 7039 hw->mac_type == em_pch2lan) 7040 return; 7041 7042 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) { 7043 if (hw->mng_cookie.vlan_id != 0) { 7044 /* 7045 * The VFTA is a 4096b bit-field, each identifying a 7046 * single VLAN ID. The following operations 7047 * determine which 32b entry (i.e. offset) into the 7048 * array we want to set the VLAN ID (i.e. bit) of the 7049 * manageability unit. 7050 */ 7051 vfta_offset = (hw->mng_cookie.vlan_id >> 7052 E1000_VFTA_ENTRY_SHIFT) & E1000_VFTA_ENTRY_MASK; 7053 7054 vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id & 7055 E1000_VFTA_ENTRY_BIT_SHIFT_MASK); 7056 } 7057 } 7058 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 7059 /* 7060 * If the offset we want to clear is the same offset of the 7061 * manageability VLAN ID, then clear all bits except that of 7062 * the manageability unit 7063 */ 7064 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; 7065 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value); 7066 E1000_WRITE_FLUSH(hw); 7067 } 7068 } 7069 7070 STATIC int32_t 7071 em_id_led_init(struct em_hw *hw) 7072 { 7073 uint32_t ledctl; 7074 const uint32_t ledctl_mask = 0x000000FF; 7075 const uint32_t ledctl_on = E1000_LEDCTL_MODE_LED_ON; 7076 const uint32_t ledctl_off = E1000_LEDCTL_MODE_LED_OFF; 7077 uint16_t eeprom_data, i, temp; 7078 const uint16_t led_mask = 0x0F; 7079 DEBUGFUNC("em_id_led_init"); 7080 7081 if (hw->mac_type < em_82540 || hw->mac_type == em_icp_xxxx) { 7082 /* Nothing to do */ 7083 return E1000_SUCCESS; 7084 } 7085 ledctl = E1000_READ_REG(hw, LEDCTL); 7086 hw->ledctl_default = ledctl; 7087 hw->ledctl_mode1 = hw->ledctl_default; 7088 hw->ledctl_mode2 = hw->ledctl_default; 7089 7090 if (em_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) { 7091 DEBUGOUT("EEPROM Read Error\n"); 7092 return -E1000_ERR_EEPROM; 7093 } 7094 if ((hw->mac_type == em_82573) && 7095 (eeprom_data == ID_LED_RESERVED_82573)) 7096 eeprom_data = ID_LED_DEFAULT_82573; 7097 else if ((eeprom_data == ID_LED_RESERVED_0000) || 7098 (eeprom_data == ID_LED_RESERVED_FFFF)) { 7099 if (hw->mac_type == em_ich8lan || 7100 hw->mac_type == em_ich9lan || 7101 hw->mac_type == em_ich10lan) // XXX 7102 eeprom_data = ID_LED_DEFAULT_ICH8LAN; 7103 else 7104 eeprom_data = ID_LED_DEFAULT; 7105 } 7106 for (i = 0; i < 4; i++) { 7107 temp = (eeprom_data >> (i << 2)) & led_mask; 7108 switch (temp) { 7109 case ID_LED_ON1_DEF2: 7110 case ID_LED_ON1_ON2: 7111 case ID_LED_ON1_OFF2: 7112 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 7113 hw->ledctl_mode1 |= ledctl_on << (i << 3); 7114 break; 7115 case ID_LED_OFF1_DEF2: 7116 case ID_LED_OFF1_ON2: 7117 case ID_LED_OFF1_OFF2: 7118 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 7119 hw->ledctl_mode1 |= ledctl_off << (i << 3); 7120 break; 7121 default: 7122 /* Do nothing */ 7123 break; 7124 } 7125 switch (temp) { 7126 case ID_LED_DEF1_ON2: 7127 case ID_LED_ON1_ON2: 7128 case ID_LED_OFF1_ON2: 7129 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 7130 hw->ledctl_mode2 |= ledctl_on << (i << 3); 7131 break; 7132 case ID_LED_DEF1_OFF2: 7133 case ID_LED_ON1_OFF2: 7134 case ID_LED_OFF1_OFF2: 7135 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 7136 hw->ledctl_mode2 |= ledctl_off << (i << 3); 7137 break; 7138 default: 7139 /* Do nothing */ 7140 break; 7141 } 7142 } 7143 return E1000_SUCCESS; 7144 } 7145 7146 /****************************************************************************** 7147 * Clears all hardware statistics counters. 7148 * 7149 * hw - Struct containing variables accessed by shared code 7150 *****************************************************************************/ 7151 void 7152 em_clear_hw_cntrs(struct em_hw *hw) 7153 { 7154 volatile uint32_t temp; 7155 temp = E1000_READ_REG(hw, CRCERRS); 7156 temp = E1000_READ_REG(hw, SYMERRS); 7157 temp = E1000_READ_REG(hw, MPC); 7158 temp = E1000_READ_REG(hw, SCC); 7159 temp = E1000_READ_REG(hw, ECOL); 7160 temp = E1000_READ_REG(hw, MCC); 7161 temp = E1000_READ_REG(hw, LATECOL); 7162 temp = E1000_READ_REG(hw, COLC); 7163 temp = E1000_READ_REG(hw, DC); 7164 temp = E1000_READ_REG(hw, SEC); 7165 temp = E1000_READ_REG(hw, RLEC); 7166 temp = E1000_READ_REG(hw, XONRXC); 7167 temp = E1000_READ_REG(hw, XONTXC); 7168 temp = E1000_READ_REG(hw, XOFFRXC); 7169 temp = E1000_READ_REG(hw, XOFFTXC); 7170 temp = E1000_READ_REG(hw, FCRUC); 7171 7172 if (hw->mac_type != em_ich8lan && 7173 hw->mac_type != em_ich9lan && 7174 hw->mac_type != em_ich10lan && 7175 hw->mac_type != em_pchlan && 7176 hw->mac_type != em_pch2lan) { 7177 temp = E1000_READ_REG(hw, PRC64); 7178 temp = E1000_READ_REG(hw, PRC127); 7179 temp = E1000_READ_REG(hw, PRC255); 7180 temp = E1000_READ_REG(hw, PRC511); 7181 temp = E1000_READ_REG(hw, PRC1023); 7182 temp = E1000_READ_REG(hw, PRC1522); 7183 } 7184 temp = E1000_READ_REG(hw, GPRC); 7185 temp = E1000_READ_REG(hw, BPRC); 7186 temp = E1000_READ_REG(hw, MPRC); 7187 temp = E1000_READ_REG(hw, GPTC); 7188 temp = E1000_READ_REG(hw, GORCL); 7189 temp = E1000_READ_REG(hw, GORCH); 7190 temp = E1000_READ_REG(hw, GOTCL); 7191 temp = E1000_READ_REG(hw, GOTCH); 7192 temp = E1000_READ_REG(hw, RNBC); 7193 temp = E1000_READ_REG(hw, RUC); 7194 temp = E1000_READ_REG(hw, RFC); 7195 temp = E1000_READ_REG(hw, ROC); 7196 temp = E1000_READ_REG(hw, RJC); 7197 temp = E1000_READ_REG(hw, TORL); 7198 temp = E1000_READ_REG(hw, TORH); 7199 temp = E1000_READ_REG(hw, TOTL); 7200 temp = E1000_READ_REG(hw, TOTH); 7201 temp = E1000_READ_REG(hw, TPR); 7202 temp = E1000_READ_REG(hw, TPT); 7203 7204 if (hw->mac_type != em_ich8lan && 7205 hw->mac_type != em_ich9lan && 7206 hw->mac_type != em_ich10lan && 7207 hw->mac_type != em_pchlan && 7208 hw->mac_type != em_pch2lan) { 7209 temp = E1000_READ_REG(hw, PTC64); 7210 temp = E1000_READ_REG(hw, PTC127); 7211 temp = E1000_READ_REG(hw, PTC255); 7212 temp = E1000_READ_REG(hw, PTC511); 7213 temp = E1000_READ_REG(hw, PTC1023); 7214 temp = E1000_READ_REG(hw, PTC1522); 7215 } 7216 temp = E1000_READ_REG(hw, MPTC); 7217 temp = E1000_READ_REG(hw, BPTC); 7218 7219 if (hw->mac_type < em_82543) 7220 return; 7221 7222 temp = E1000_READ_REG(hw, ALGNERRC); 7223 temp = E1000_READ_REG(hw, RXERRC); 7224 temp = E1000_READ_REG(hw, TNCRS); 7225 temp = E1000_READ_REG(hw, CEXTERR); 7226 temp = E1000_READ_REG(hw, TSCTC); 7227 temp = E1000_READ_REG(hw, TSCTFC); 7228 7229 if (hw->mac_type <= em_82544 7230 || hw->mac_type == em_icp_xxxx) 7231 return; 7232 7233 temp = E1000_READ_REG(hw, MGTPRC); 7234 temp = E1000_READ_REG(hw, MGTPDC); 7235 temp = E1000_READ_REG(hw, MGTPTC); 7236 7237 if (hw->mac_type <= em_82547_rev_2) 7238 return; 7239 7240 temp = E1000_READ_REG(hw, IAC); 7241 temp = E1000_READ_REG(hw, ICRXOC); 7242 7243 if (hw->phy_type == em_phy_82577 || 7244 hw->phy_type == em_phy_82578 || 7245 hw->phy_type == em_phy_82579) { 7246 uint16_t phy_data; 7247 7248 em_read_phy_reg(hw, HV_SCC_UPPER, &phy_data); 7249 em_read_phy_reg(hw, HV_SCC_LOWER, &phy_data); 7250 em_read_phy_reg(hw, HV_ECOL_UPPER, &phy_data); 7251 em_read_phy_reg(hw, HV_ECOL_LOWER, &phy_data); 7252 em_read_phy_reg(hw, HV_MCC_UPPER, &phy_data); 7253 em_read_phy_reg(hw, HV_MCC_LOWER, &phy_data); 7254 em_read_phy_reg(hw, HV_LATECOL_UPPER, &phy_data); 7255 em_read_phy_reg(hw, HV_LATECOL_LOWER, &phy_data); 7256 em_read_phy_reg(hw, HV_COLC_UPPER, &phy_data); 7257 em_read_phy_reg(hw, HV_COLC_LOWER, &phy_data); 7258 em_read_phy_reg(hw, HV_DC_UPPER, &phy_data); 7259 em_read_phy_reg(hw, HV_DC_LOWER, &phy_data); 7260 em_read_phy_reg(hw, HV_TNCRS_UPPER, &phy_data); 7261 em_read_phy_reg(hw, HV_TNCRS_LOWER, &phy_data); 7262 } 7263 7264 if (hw->mac_type == em_ich8lan || 7265 hw->mac_type == em_ich9lan || 7266 hw->mac_type == em_ich10lan || 7267 hw->mac_type == em_pchlan || 7268 hw->mac_type != em_pch2lan) 7269 return; 7270 7271 temp = E1000_READ_REG(hw, ICRXPTC); 7272 temp = E1000_READ_REG(hw, ICRXATC); 7273 temp = E1000_READ_REG(hw, ICTXPTC); 7274 temp = E1000_READ_REG(hw, ICTXATC); 7275 temp = E1000_READ_REG(hw, ICTXQEC); 7276 temp = E1000_READ_REG(hw, ICTXQMTC); 7277 temp = E1000_READ_REG(hw, ICRXDMTC); 7278 } 7279 7280 #ifndef SMALL_KERNEL 7281 /****************************************************************************** 7282 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT 7283 * 7284 * hw - Struct containing variables accessed by shared code 7285 * frame_len - The length of the frame in question 7286 * mac_addr - The Ethernet destination address of the frame in question 7287 *****************************************************************************/ 7288 void 7289 em_tbi_adjust_stats(struct em_hw *hw, struct em_hw_stats *stats, 7290 uint32_t frame_len, uint8_t *mac_addr) 7291 { 7292 uint64_t carry_bit; 7293 /* First adjust the frame length. */ 7294 frame_len--; 7295 /* 7296 * We need to adjust the statistics counters, since the hardware 7297 * counters overcount this packet as a CRC error and undercount the 7298 * packet as a good packet 7299 */ 7300 /* This packet should not be counted as a CRC error. */ 7301 stats->crcerrs--; 7302 /* This packet does count as a Good Packet Received. */ 7303 stats->gprc++; 7304 7305 /* Adjust the Good Octets received counters */ 7306 carry_bit = 0x80000000 & stats->gorcl; 7307 stats->gorcl += frame_len; 7308 /* 7309 * If the high bit of Gorcl (the low 32 bits of the Good Octets 7310 * Received Count) was one before the addition, AND it is zero after, 7311 * then we lost the carry out, need to add one to Gorch (Good Octets 7312 * Received Count High). This could be simplified if all environments 7313 * supported 64-bit integers. 7314 */ 7315 if (carry_bit && ((stats->gorcl & 0x80000000) == 0)) 7316 stats->gorch++; 7317 /* 7318 * Is this a broadcast or multicast? Check broadcast first, since 7319 * the test for a multicast frame will test positive on a broadcast 7320 * frame. 7321 */ 7322 if ((mac_addr[0] == (uint8_t) 0xff) && (mac_addr[1] == (uint8_t) 0xff)) 7323 /* Broadcast packet */ 7324 stats->bprc++; 7325 else if (*mac_addr & 0x01) 7326 /* Multicast packet */ 7327 stats->mprc++; 7328 7329 if (frame_len == hw->max_frame_size) { 7330 /* 7331 * In this case, the hardware has overcounted the number of 7332 * oversize frames. 7333 */ 7334 if (stats->roc > 0) 7335 stats->roc--; 7336 } 7337 /* 7338 * Adjust the bin counters when the extra byte put the frame in the 7339 * wrong bin. Remember that the frame_len was adjusted above. 7340 */ 7341 if (frame_len == 64) { 7342 stats->prc64++; 7343 stats->prc127--; 7344 } else if (frame_len == 127) { 7345 stats->prc127++; 7346 stats->prc255--; 7347 } else if (frame_len == 255) { 7348 stats->prc255++; 7349 stats->prc511--; 7350 } else if (frame_len == 511) { 7351 stats->prc511++; 7352 stats->prc1023--; 7353 } else if (frame_len == 1023) { 7354 stats->prc1023++; 7355 stats->prc1522--; 7356 } else if (frame_len == 1522) { 7357 stats->prc1522++; 7358 } 7359 } 7360 #endif /* !SMALL_KERNEL */ 7361 7362 /****************************************************************************** 7363 * Gets the current PCI bus type, speed, and width of the hardware 7364 * 7365 * hw - Struct containing variables accessed by shared code 7366 *****************************************************************************/ 7367 void 7368 em_get_bus_info(struct em_hw *hw) 7369 { 7370 int32_t ret_val; 7371 uint16_t pci_ex_link_status; 7372 uint32_t status; 7373 switch (hw->mac_type) { 7374 case em_82542_rev2_0: 7375 case em_82542_rev2_1: 7376 hw->bus_type = em_bus_type_unknown; 7377 hw->bus_speed = em_bus_speed_unknown; 7378 hw->bus_width = em_bus_width_unknown; 7379 break; 7380 case em_icp_xxxx: 7381 hw->bus_type = em_bus_type_cpp; 7382 hw->bus_speed = em_bus_speed_unknown; 7383 hw->bus_width = em_bus_width_unknown; 7384 break; 7385 case em_82571: 7386 case em_82572: 7387 case em_82573: 7388 case em_82574: 7389 case em_82575: 7390 case em_82580: 7391 case em_80003es2lan: 7392 hw->bus_type = em_bus_type_pci_express; 7393 hw->bus_speed = em_bus_speed_2500; 7394 ret_val = em_read_pcie_cap_reg(hw, PCI_EX_LINK_STATUS, 7395 &pci_ex_link_status); 7396 if (ret_val) 7397 hw->bus_width = em_bus_width_unknown; 7398 else 7399 hw->bus_width = (pci_ex_link_status & 7400 PCI_EX_LINK_WIDTH_MASK) >> PCI_EX_LINK_WIDTH_SHIFT; 7401 break; 7402 case em_ich8lan: 7403 case em_ich9lan: 7404 case em_ich10lan: 7405 case em_pchlan: 7406 case em_pch2lan: 7407 hw->bus_type = em_bus_type_pci_express; 7408 hw->bus_speed = em_bus_speed_2500; 7409 hw->bus_width = em_bus_width_pciex_1; 7410 break; 7411 default: 7412 status = E1000_READ_REG(hw, STATUS); 7413 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ? 7414 em_bus_type_pcix : em_bus_type_pci; 7415 7416 if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) { 7417 hw->bus_speed = (hw->bus_type == em_bus_type_pci) ? 7418 em_bus_speed_66 : em_bus_speed_120; 7419 } else if (hw->bus_type == em_bus_type_pci) { 7420 hw->bus_speed = (status & E1000_STATUS_PCI66) ? 7421 em_bus_speed_66 : em_bus_speed_33; 7422 } else { 7423 switch (status & E1000_STATUS_PCIX_SPEED) { 7424 case E1000_STATUS_PCIX_SPEED_66: 7425 hw->bus_speed = em_bus_speed_66; 7426 break; 7427 case E1000_STATUS_PCIX_SPEED_100: 7428 hw->bus_speed = em_bus_speed_100; 7429 break; 7430 case E1000_STATUS_PCIX_SPEED_133: 7431 hw->bus_speed = em_bus_speed_133; 7432 break; 7433 default: 7434 hw->bus_speed = em_bus_speed_reserved; 7435 break; 7436 } 7437 } 7438 hw->bus_width = (status & E1000_STATUS_BUS64) ? 7439 em_bus_width_64 : em_bus_width_32; 7440 break; 7441 } 7442 } 7443 7444 /****************************************************************************** 7445 * Writes a value to one of the devices registers using port I/O (as opposed to 7446 * memory mapped I/O). Only 82544 and newer devices support port I/O. 7447 * 7448 * hw - Struct containing variables accessed by shared code 7449 * offset - offset to write to 7450 * value - value to write 7451 *****************************************************************************/ 7452 STATIC void 7453 em_write_reg_io(struct em_hw *hw, uint32_t offset, uint32_t value) 7454 { 7455 unsigned long io_addr = hw->io_base; 7456 unsigned long io_data = hw->io_base + 4; 7457 em_io_write(hw, io_addr, offset); 7458 em_io_write(hw, io_data, value); 7459 } 7460 7461 /****************************************************************************** 7462 * Estimates the cable length. 7463 * 7464 * hw - Struct containing variables accessed by shared code 7465 * min_length - The estimated minimum length 7466 * max_length - The estimated maximum length 7467 * 7468 * returns: - E1000_ERR_XXX 7469 * E1000_SUCCESS 7470 * 7471 * This function always returns a ranged length (minimum & maximum). 7472 * So for M88 phy's, this function interprets the one value returned from the 7473 * register to the minimum and maximum range. 7474 * For IGP phy's, the function calculates the range by the AGC registers. 7475 *****************************************************************************/ 7476 STATIC int32_t 7477 em_get_cable_length(struct em_hw *hw, uint16_t *min_length, 7478 uint16_t *max_length) 7479 { 7480 int32_t ret_val; 7481 uint16_t agc_value = 0; 7482 uint16_t i, phy_data; 7483 uint16_t cable_length; 7484 DEBUGFUNC("em_get_cable_length"); 7485 7486 *min_length = *max_length = 0; 7487 7488 /* Use old method for Phy older than IGP */ 7489 if (hw->phy_type == em_phy_m88 || 7490 hw->phy_type == em_phy_oem || 7491 hw->phy_type == em_phy_82578) { 7492 7493 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, 7494 &phy_data); 7495 if (ret_val) 7496 return ret_val; 7497 cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 7498 M88E1000_PSSR_CABLE_LENGTH_SHIFT; 7499 7500 /* Convert the enum value to ranged values */ 7501 switch (cable_length) { 7502 case em_cable_length_50: 7503 *min_length = 0; 7504 *max_length = em_igp_cable_length_50; 7505 break; 7506 case em_cable_length_50_80: 7507 *min_length = em_igp_cable_length_50; 7508 *max_length = em_igp_cable_length_80; 7509 break; 7510 case em_cable_length_80_110: 7511 *min_length = em_igp_cable_length_80; 7512 *max_length = em_igp_cable_length_110; 7513 break; 7514 case em_cable_length_110_140: 7515 *min_length = em_igp_cable_length_110; 7516 *max_length = em_igp_cable_length_140; 7517 break; 7518 case em_cable_length_140: 7519 *min_length = em_igp_cable_length_140; 7520 *max_length = em_igp_cable_length_170; 7521 break; 7522 default: 7523 return -E1000_ERR_PHY; 7524 break; 7525 } 7526 } else if (hw->phy_type == em_phy_gg82563) { 7527 ret_val = em_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE, 7528 &phy_data); 7529 if (ret_val) 7530 return ret_val; 7531 cable_length = phy_data & GG82563_DSPD_CABLE_LENGTH; 7532 7533 switch (cable_length) { 7534 case em_gg_cable_length_60: 7535 *min_length = 0; 7536 *max_length = em_igp_cable_length_60; 7537 break; 7538 case em_gg_cable_length_60_115: 7539 *min_length = em_igp_cable_length_60; 7540 *max_length = em_igp_cable_length_115; 7541 break; 7542 case em_gg_cable_length_115_150: 7543 *min_length = em_igp_cable_length_115; 7544 *max_length = em_igp_cable_length_150; 7545 break; 7546 case em_gg_cable_length_150: 7547 *min_length = em_igp_cable_length_150; 7548 *max_length = em_igp_cable_length_180; 7549 break; 7550 default: 7551 return -E1000_ERR_PHY; 7552 break; 7553 } 7554 } else if (hw->phy_type == em_phy_igp) { /* For IGP PHY */ 7555 uint16_t cur_agc_value; 7556 uint16_t min_agc_value = 7557 IGP01E1000_AGC_LENGTH_TABLE_SIZE; 7558 uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = 7559 {IGP01E1000_PHY_AGC_A, IGP01E1000_PHY_AGC_B, 7560 IGP01E1000_PHY_AGC_C, IGP01E1000_PHY_AGC_D}; 7561 7562 /* Read the AGC registers for all channels */ 7563 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 7564 ret_val = em_read_phy_reg(hw, agc_reg_array[i], 7565 &phy_data); 7566 if (ret_val) 7567 return ret_val; 7568 7569 cur_agc_value = phy_data >> 7570 IGP01E1000_AGC_LENGTH_SHIFT; 7571 7572 /* Value bound check. */ 7573 if ((cur_agc_value >= 7574 IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) || 7575 (cur_agc_value == 0)) 7576 return -E1000_ERR_PHY; 7577 7578 agc_value += cur_agc_value; 7579 7580 /* Update minimal AGC value. */ 7581 if (min_agc_value > cur_agc_value) 7582 min_agc_value = cur_agc_value; 7583 } 7584 7585 /* Remove the minimal AGC result for length < 50m */ 7586 if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * 7587 em_igp_cable_length_50) { 7588 agc_value -= min_agc_value; 7589 7590 /* 7591 * Get the average length of the remaining 3 channels 7592 */ 7593 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1); 7594 } else { 7595 /* Get the average length of all the 4 channels. */ 7596 agc_value /= IGP01E1000_PHY_CHANNEL_NUM; 7597 } 7598 7599 /* Set the range of the calculated length. */ 7600 *min_length = ((em_igp_cable_length_table[agc_value] - 7601 IGP01E1000_AGC_RANGE) > 0) ? 7602 (em_igp_cable_length_table[agc_value] - 7603 IGP01E1000_AGC_RANGE) : 0; 7604 *max_length = em_igp_cable_length_table[agc_value] + 7605 IGP01E1000_AGC_RANGE; 7606 } else if (hw->phy_type == em_phy_igp_2 || 7607 hw->phy_type == em_phy_igp_3) { 7608 uint16_t cur_agc_index, max_agc_index = 0; 7609 uint16_t min_agc_index = IGP02E1000_AGC_LENGTH_TABLE_SIZE - 1; 7610 uint16_t agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = 7611 {IGP02E1000_PHY_AGC_A, IGP02E1000_PHY_AGC_B, 7612 IGP02E1000_PHY_AGC_C, IGP02E1000_PHY_AGC_D}; 7613 /* Read the AGC registers for all channels */ 7614 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { 7615 ret_val = em_read_phy_reg(hw, agc_reg_array[i], 7616 &phy_data); 7617 if (ret_val) 7618 return ret_val; 7619 /* 7620 * Getting bits 15:9, which represent the combination 7621 * of course and fine gain values. The result is a 7622 * number that can be put into the lookup table to 7623 * obtain the approximate cable length. 7624 */ 7625 cur_agc_index = (phy_data >> 7626 IGP02E1000_AGC_LENGTH_SHIFT) & 7627 IGP02E1000_AGC_LENGTH_MASK; 7628 7629 /* Array index bound check. */ 7630 if ((cur_agc_index >= IGP02E1000_AGC_LENGTH_TABLE_SIZE) 7631 || (cur_agc_index == 0)) 7632 return -E1000_ERR_PHY; 7633 7634 /* Remove min & max AGC values from calculation. */ 7635 if (em_igp_2_cable_length_table[min_agc_index] > 7636 em_igp_2_cable_length_table[cur_agc_index]) 7637 min_agc_index = cur_agc_index; 7638 if (em_igp_2_cable_length_table[max_agc_index] < 7639 em_igp_2_cable_length_table[cur_agc_index]) 7640 max_agc_index = cur_agc_index; 7641 7642 agc_value += em_igp_2_cable_length_table 7643 [cur_agc_index]; 7644 } 7645 7646 agc_value -= (em_igp_2_cable_length_table[min_agc_index] + 7647 em_igp_2_cable_length_table[max_agc_index]); 7648 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); 7649 /* 7650 * Calculate cable length with the error range of +/- 10 7651 * meters. 7652 */ 7653 *min_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ? 7654 (agc_value - IGP02E1000_AGC_RANGE) : 0; 7655 *max_length = agc_value + IGP02E1000_AGC_RANGE; 7656 } 7657 return E1000_SUCCESS; 7658 } 7659 7660 /****************************************************************************** 7661 * Check if Downshift occured 7662 * 7663 * hw - Struct containing variables accessed by shared code 7664 * downshift - output parameter : 0 - No Downshift ocured. 7665 * 1 - Downshift ocured. 7666 * 7667 * returns: - E1000_ERR_XXX 7668 * E1000_SUCCESS 7669 * 7670 * For phy's older then IGP, this function reads the Downshift bit in the Phy 7671 * Specific Status register. For IGP phy's, it reads the Downgrade bit in the 7672 * Link Health register. In IGP this bit is latched high, so the driver must 7673 * read it immediately after link is established. 7674 *****************************************************************************/ 7675 STATIC int32_t 7676 em_check_downshift(struct em_hw *hw) 7677 { 7678 int32_t ret_val; 7679 uint16_t phy_data; 7680 DEBUGFUNC("em_check_downshift"); 7681 7682 if (hw->phy_type == em_phy_igp || 7683 hw->phy_type == em_phy_igp_3 || 7684 hw->phy_type == em_phy_igp_2) { 7685 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH, 7686 &phy_data); 7687 if (ret_val) 7688 return ret_val; 7689 7690 hw->speed_downgraded = (phy_data & 7691 IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0; 7692 } else if ((hw->phy_type == em_phy_m88) || 7693 (hw->phy_type == em_phy_gg82563) || 7694 (hw->phy_type == em_phy_oem) || 7695 (hw->phy_type == em_phy_82578)) { 7696 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, 7697 &phy_data); 7698 if (ret_val) 7699 return ret_val; 7700 7701 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >> 7702 M88E1000_PSSR_DOWNSHIFT_SHIFT; 7703 } else if (hw->phy_type == em_phy_ife) { 7704 /* em_phy_ife supports 10/100 speed only */ 7705 hw->speed_downgraded = FALSE; 7706 } 7707 return E1000_SUCCESS; 7708 } 7709 7710 /***************************************************************************** 7711 * 7712 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a 7713 * gigabit link is achieved to improve link quality. 7714 * 7715 * hw: Struct containing variables accessed by shared code 7716 * 7717 * returns: - E1000_ERR_PHY if fail to read/write the PHY 7718 * E1000_SUCCESS at any other case. 7719 * 7720 ****************************************************************************/ 7721 STATIC int32_t 7722 em_config_dsp_after_link_change(struct em_hw *hw, boolean_t link_up) 7723 { 7724 int32_t ret_val; 7725 uint16_t phy_data, phy_saved_data, speed, duplex, i; 7726 uint16_t dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = 7727 {IGP01E1000_PHY_AGC_PARAM_A, IGP01E1000_PHY_AGC_PARAM_B, 7728 IGP01E1000_PHY_AGC_PARAM_C, IGP01E1000_PHY_AGC_PARAM_D}; 7729 uint16_t min_length, max_length; 7730 DEBUGFUNC("em_config_dsp_after_link_change"); 7731 7732 if (hw->phy_type != em_phy_igp) 7733 return E1000_SUCCESS; 7734 7735 if (link_up) { 7736 ret_val = em_get_speed_and_duplex(hw, &speed, &duplex); 7737 if (ret_val) { 7738 DEBUGOUT("Error getting link speed and duplex\n"); 7739 return ret_val; 7740 } 7741 if (speed == SPEED_1000) { 7742 7743 ret_val = em_get_cable_length(hw, &min_length, &max_length); 7744 if (ret_val) 7745 return ret_val; 7746 7747 if ((hw->dsp_config_state == em_dsp_config_enabled) && 7748 min_length >= em_igp_cable_length_50) { 7749 7750 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; 7751 i++) { 7752 ret_val = em_read_phy_reg(hw, 7753 dsp_reg_array[i], &phy_data); 7754 if (ret_val) 7755 return ret_val; 7756 7757 phy_data &= 7758 ~IGP01E1000_PHY_EDAC_MU_INDEX; 7759 7760 ret_val = em_write_phy_reg(hw, 7761 dsp_reg_array[i], phy_data); 7762 if (ret_val) 7763 return ret_val; 7764 } 7765 hw->dsp_config_state = em_dsp_config_activated; 7766 } 7767 if ((hw->ffe_config_state == em_ffe_config_enabled) && 7768 (min_length < em_igp_cable_length_50)) { 7769 7770 uint16_t ffe_idle_err_timeout = 7771 FFE_IDLE_ERR_COUNT_TIMEOUT_20; 7772 uint32_t idle_errs = 0; 7773 /* clear previous idle error counts */ 7774 ret_val = em_read_phy_reg(hw, PHY_1000T_STATUS, 7775 &phy_data); 7776 if (ret_val) 7777 return ret_val; 7778 7779 for (i = 0; i < ffe_idle_err_timeout; i++) { 7780 usec_delay(1000); 7781 ret_val = em_read_phy_reg(hw, 7782 PHY_1000T_STATUS, &phy_data); 7783 if (ret_val) 7784 return ret_val; 7785 7786 idle_errs += (phy_data & 7787 SR_1000T_IDLE_ERROR_CNT); 7788 if (idle_errs > 7789 SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) { 7790 hw->ffe_config_state = 7791 em_ffe_config_active; 7792 7793 ret_val = em_write_phy_reg(hw, 7794 IGP01E1000_PHY_DSP_FFE, 7795 IGP01E1000_PHY_DSP_FFE_CM_CP); 7796 if (ret_val) 7797 return ret_val; 7798 break; 7799 } 7800 if (idle_errs) 7801 ffe_idle_err_timeout = 7802 FFE_IDLE_ERR_COUNT_TIMEOUT_100; 7803 } 7804 } 7805 } 7806 } else { 7807 if (hw->dsp_config_state == em_dsp_config_activated) { 7808 /* 7809 * Save off the current value of register 0x2F5B to 7810 * be restored at the end of the routines. 7811 */ 7812 ret_val = em_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 7813 7814 if (ret_val) 7815 return ret_val; 7816 7817 /* Disable the PHY transmitter */ 7818 ret_val = em_write_phy_reg(hw, 0x2F5B, 0x0003); 7819 7820 if (ret_val) 7821 return ret_val; 7822 7823 msec_delay_irq(20); 7824 7825 ret_val = em_write_phy_reg(hw, 0x0000, 7826 IGP01E1000_IEEE_FORCE_GIGA); 7827 if (ret_val) 7828 return ret_val; 7829 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 7830 ret_val = em_read_phy_reg(hw, dsp_reg_array[i], 7831 &phy_data); 7832 if (ret_val) 7833 return ret_val; 7834 7835 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; 7836 phy_data |= 7837 IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS; 7838 7839 ret_val = em_write_phy_reg(hw, 7840 dsp_reg_array[i], phy_data); 7841 if (ret_val) 7842 return ret_val; 7843 } 7844 7845 ret_val = em_write_phy_reg(hw, 0x0000, 7846 IGP01E1000_IEEE_RESTART_AUTONEG); 7847 if (ret_val) 7848 return ret_val; 7849 7850 msec_delay_irq(20); 7851 7852 /* Now enable the transmitter */ 7853 ret_val = em_write_phy_reg(hw, 0x2F5B, phy_saved_data); 7854 7855 if (ret_val) 7856 return ret_val; 7857 7858 hw->dsp_config_state = em_dsp_config_enabled; 7859 } 7860 if (hw->ffe_config_state == em_ffe_config_active) { 7861 /* 7862 * Save off the current value of register 0x2F5B to 7863 * be restored at the end of the routines. 7864 */ 7865 ret_val = em_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 7866 7867 if (ret_val) 7868 return ret_val; 7869 7870 /* Disable the PHY transmitter */ 7871 ret_val = em_write_phy_reg(hw, 0x2F5B, 0x0003); 7872 7873 if (ret_val) 7874 return ret_val; 7875 7876 msec_delay_irq(20); 7877 7878 ret_val = em_write_phy_reg(hw, 0x0000, 7879 IGP01E1000_IEEE_FORCE_GIGA); 7880 if (ret_val) 7881 return ret_val; 7882 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE, 7883 IGP01E1000_PHY_DSP_FFE_DEFAULT); 7884 if (ret_val) 7885 return ret_val; 7886 7887 ret_val = em_write_phy_reg(hw, 0x0000, 7888 IGP01E1000_IEEE_RESTART_AUTONEG); 7889 if (ret_val) 7890 return ret_val; 7891 7892 msec_delay_irq(20); 7893 7894 /* Now enable the transmitter */ 7895 ret_val = em_write_phy_reg(hw, 0x2F5B, phy_saved_data); 7896 7897 if (ret_val) 7898 return ret_val; 7899 7900 hw->ffe_config_state = em_ffe_config_enabled; 7901 } 7902 } 7903 return E1000_SUCCESS; 7904 } 7905 7906 /***************************************************************************** 7907 * Set PHY to class A mode 7908 * Assumes the following operations will follow to enable the new class mode. 7909 * 1. Do a PHY soft reset 7910 * 2. Restart auto-negotiation or force link. 7911 * 7912 * hw - Struct containing variables accessed by shared code 7913 ****************************************************************************/ 7914 static int32_t 7915 em_set_phy_mode(struct em_hw *hw) 7916 { 7917 int32_t ret_val; 7918 uint16_t eeprom_data; 7919 DEBUGFUNC("em_set_phy_mode"); 7920 7921 if ((hw->mac_type == em_82545_rev_3) && 7922 (hw->media_type == em_media_type_copper)) { 7923 ret_val = em_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, 7924 &eeprom_data); 7925 if (ret_val) { 7926 return ret_val; 7927 } 7928 if ((eeprom_data != EEPROM_RESERVED_WORD) && 7929 (eeprom_data & EEPROM_PHY_CLASS_A)) { 7930 ret_val = em_write_phy_reg(hw, 7931 M88E1000_PHY_PAGE_SELECT, 0x000B); 7932 if (ret_val) 7933 return ret_val; 7934 ret_val = em_write_phy_reg(hw, 7935 M88E1000_PHY_GEN_CONTROL, 0x8104); 7936 if (ret_val) 7937 return ret_val; 7938 7939 hw->phy_reset_disable = FALSE; 7940 } 7941 } 7942 return E1000_SUCCESS; 7943 } 7944 7945 /***************************************************************************** 7946 * 7947 * This function sets the lplu state according to the active flag. When 7948 * activating lplu this function also disables smart speed and vise versa. 7949 * lplu will not be activated unless the device autonegotiation advertisement 7950 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. 7951 * hw: Struct containing variables accessed by shared code 7952 * active - true to enable lplu false to disable lplu. 7953 * 7954 * returns: - E1000_ERR_PHY if fail to read/write the PHY 7955 * E1000_SUCCESS at any other case. 7956 * 7957 ****************************************************************************/ 7958 STATIC int32_t 7959 em_set_d3_lplu_state(struct em_hw *hw, boolean_t active) 7960 { 7961 uint32_t phy_ctrl = 0; 7962 int32_t ret_val; 7963 uint16_t phy_data; 7964 DEBUGFUNC("em_set_d3_lplu_state"); 7965 7966 if (hw->phy_type != em_phy_igp && hw->phy_type != em_phy_igp_2 7967 && hw->phy_type != em_phy_igp_3) 7968 return E1000_SUCCESS; 7969 /* 7970 * During driver activity LPLU should not be used or it will attain 7971 * link from the lowest speeds starting from 10Mbps. The capability 7972 * is used for Dx transitions and states 7973 */ 7974 if (hw->mac_type == em_82541_rev_2 || hw->mac_type == em_82547_rev_2) { 7975 ret_val = em_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data); 7976 if (ret_val) 7977 return ret_val; 7978 } else if (hw->mac_type == em_ich8lan || 7979 hw->mac_type == em_ich9lan || 7980 hw->mac_type == em_ich10lan || 7981 hw->mac_type == em_pchlan || 7982 hw->mac_type == em_pch2lan) { 7983 /* 7984 * MAC writes into PHY register based on the state transition 7985 * and start auto-negotiation. SW driver can overwrite the 7986 * settings in CSR PHY power control E1000_PHY_CTRL register. 7987 */ 7988 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); 7989 } else { 7990 ret_val = em_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, 7991 &phy_data); 7992 if (ret_val) 7993 return ret_val; 7994 } 7995 7996 if (!active) { 7997 if (hw->mac_type == em_82541_rev_2 || 7998 hw->mac_type == em_82547_rev_2) { 7999 phy_data &= ~IGP01E1000_GMII_FLEX_SPD; 8000 ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO, 8001 phy_data); 8002 if (ret_val) 8003 return ret_val; 8004 } else { 8005 if (hw->mac_type == em_ich8lan || 8006 hw->mac_type == em_ich9lan || 8007 hw->mac_type == em_ich10lan || 8008 hw->mac_type == em_pchlan || 8009 hw->mac_type == em_pch2lan) { 8010 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; 8011 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 8012 } else { 8013 phy_data &= ~IGP02E1000_PM_D3_LPLU; 8014 ret_val = em_write_phy_reg(hw, 8015 IGP02E1000_PHY_POWER_MGMT, phy_data); 8016 if (ret_val) 8017 return ret_val; 8018 } 8019 } 8020 /* 8021 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 8022 * during Dx states where the power conservation is most 8023 * important. During driver activity we should enable 8024 * SmartSpeed, so performance is maintained. 8025 */ 8026 if (hw->smart_speed == em_smart_speed_on) { 8027 ret_val = em_read_phy_reg(hw, 8028 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 8029 if (ret_val) 8030 return ret_val; 8031 8032 phy_data |= IGP01E1000_PSCFR_SMART_SPEED; 8033 ret_val = em_write_phy_reg(hw, 8034 IGP01E1000_PHY_PORT_CONFIG, phy_data); 8035 if (ret_val) 8036 return ret_val; 8037 } else if (hw->smart_speed == em_smart_speed_off) { 8038 ret_val = em_read_phy_reg(hw, 8039 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 8040 if (ret_val) 8041 return ret_val; 8042 8043 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 8044 ret_val = em_write_phy_reg(hw, 8045 IGP01E1000_PHY_PORT_CONFIG, phy_data); 8046 if (ret_val) 8047 return ret_val; 8048 } 8049 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) 8050 || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) || 8051 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) { 8052 8053 if (hw->mac_type == em_82541_rev_2 || 8054 hw->mac_type == em_82547_rev_2) { 8055 phy_data |= IGP01E1000_GMII_FLEX_SPD; 8056 ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO, 8057 phy_data); 8058 if (ret_val) 8059 return ret_val; 8060 } else { 8061 if (hw->mac_type == em_ich8lan || 8062 hw->mac_type == em_ich9lan || 8063 hw->mac_type == em_ich10lan || 8064 hw->mac_type == em_pchlan || 8065 hw->mac_type == em_pch2lan) { 8066 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; 8067 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 8068 } else { 8069 phy_data |= IGP02E1000_PM_D3_LPLU; 8070 ret_val = em_write_phy_reg(hw, 8071 IGP02E1000_PHY_POWER_MGMT, phy_data); 8072 if (ret_val) 8073 return ret_val; 8074 } 8075 } 8076 8077 /* When LPLU is enabled we should disable SmartSpeed */ 8078 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 8079 &phy_data); 8080 if (ret_val) 8081 return ret_val; 8082 8083 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 8084 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 8085 phy_data); 8086 if (ret_val) 8087 return ret_val; 8088 8089 } 8090 return E1000_SUCCESS; 8091 } 8092 8093 /***************************************************************************** 8094 * 8095 * This function sets the lplu d0 state according to the active flag. When 8096 * activating lplu this function also disables smart speed and vise versa. 8097 * lplu will not be activated unless the device autonegotiation advertisement 8098 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. 8099 * hw: Struct containing variables accessed by shared code 8100 * active - true to enable lplu false to disable lplu. 8101 * 8102 * returns: - E1000_ERR_PHY if fail to read/write the PHY 8103 * E1000_SUCCESS at any other case. 8104 * 8105 ****************************************************************************/ 8106 STATIC int32_t 8107 em_set_d0_lplu_state(struct em_hw *hw, boolean_t active) 8108 { 8109 uint32_t phy_ctrl = 0; 8110 int32_t ret_val; 8111 uint16_t phy_data; 8112 DEBUGFUNC("em_set_d0_lplu_state"); 8113 8114 if (hw->mac_type <= em_82547_rev_2) 8115 return E1000_SUCCESS; 8116 8117 if (hw->mac_type == em_ich8lan || 8118 hw->mac_type == em_ich9lan || 8119 hw->mac_type == em_ich10lan || 8120 hw->mac_type == em_pchlan || 8121 hw->mac_type == em_pch2lan) { 8122 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); 8123 } else { 8124 ret_val = em_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, 8125 &phy_data); 8126 if (ret_val) 8127 return ret_val; 8128 } 8129 8130 if (!active) { 8131 if (hw->mac_type == em_ich8lan || 8132 hw->mac_type == em_ich9lan || 8133 hw->mac_type == em_ich10lan || 8134 hw->mac_type == em_pchlan || 8135 hw->mac_type == em_pch2lan) { 8136 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; 8137 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 8138 } else { 8139 phy_data &= ~IGP02E1000_PM_D0_LPLU; 8140 ret_val = em_write_phy_reg(hw, 8141 IGP02E1000_PHY_POWER_MGMT, phy_data); 8142 if (ret_val) 8143 return ret_val; 8144 } 8145 /* 8146 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 8147 * during Dx states where the power conservation is most 8148 * important. During driver activity we should enable 8149 * SmartSpeed, so performance is maintained. 8150 */ 8151 if (hw->smart_speed == em_smart_speed_on) { 8152 ret_val = em_read_phy_reg(hw, 8153 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 8154 if (ret_val) 8155 return ret_val; 8156 8157 phy_data |= IGP01E1000_PSCFR_SMART_SPEED; 8158 ret_val = em_write_phy_reg(hw, 8159 IGP01E1000_PHY_PORT_CONFIG, phy_data); 8160 if (ret_val) 8161 return ret_val; 8162 } else if (hw->smart_speed == em_smart_speed_off) { 8163 ret_val = em_read_phy_reg(hw, 8164 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 8165 if (ret_val) 8166 return ret_val; 8167 8168 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 8169 ret_val = em_write_phy_reg(hw, 8170 IGP01E1000_PHY_PORT_CONFIG, phy_data); 8171 if (ret_val) 8172 return ret_val; 8173 } 8174 } else { 8175 if (hw->mac_type == em_ich8lan || 8176 hw->mac_type == em_ich9lan || 8177 hw->mac_type == em_ich10lan || 8178 hw->mac_type == em_pchlan || 8179 hw->mac_type == em_pch2lan) { 8180 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; 8181 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 8182 } else { 8183 phy_data |= IGP02E1000_PM_D0_LPLU; 8184 ret_val = em_write_phy_reg(hw, 8185 IGP02E1000_PHY_POWER_MGMT, phy_data); 8186 if (ret_val) 8187 return ret_val; 8188 } 8189 8190 /* When LPLU is enabled we should disable SmartSpeed */ 8191 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 8192 &phy_data); 8193 if (ret_val) 8194 return ret_val; 8195 8196 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 8197 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 8198 phy_data); 8199 if (ret_val) 8200 return ret_val; 8201 8202 } 8203 return E1000_SUCCESS; 8204 } 8205 8206 /*************************************************************************** 8207 * Set Low Power Link Up state 8208 * 8209 * Sets the LPLU state according to the active flag. For PCH, if OEM write 8210 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set 8211 * the phy speed. This function will manually set the LPLU bit and restart 8212 * auto-neg as hw would do. D3 and D0 LPLU will call the same function 8213 * since it configures the same bit. 8214 ***************************************************************************/ 8215 int32_t 8216 em_set_lplu_state_pchlan(struct em_hw *hw, boolean_t active) 8217 { 8218 int32_t ret_val = E1000_SUCCESS; 8219 uint16_t oem_reg; 8220 8221 DEBUGFUNC("e1000_set_lplu_state_pchlan"); 8222 8223 ret_val = em_read_phy_reg(hw, HV_OEM_BITS, &oem_reg); 8224 if (ret_val) 8225 goto out; 8226 8227 if (active) 8228 oem_reg |= HV_OEM_BITS_LPLU; 8229 else 8230 oem_reg &= ~HV_OEM_BITS_LPLU; 8231 8232 oem_reg |= HV_OEM_BITS_RESTART_AN; 8233 ret_val = em_write_phy_reg(hw, HV_OEM_BITS, oem_reg); 8234 8235 out: 8236 return ret_val; 8237 } 8238 8239 /****************************************************************************** 8240 * Change VCO speed register to improve Bit Error Rate performance of SERDES. 8241 * 8242 * hw - Struct containing variables accessed by shared code 8243 *****************************************************************************/ 8244 static int32_t 8245 em_set_vco_speed(struct em_hw *hw) 8246 { 8247 int32_t ret_val; 8248 uint16_t default_page = 0; 8249 uint16_t phy_data; 8250 DEBUGFUNC("em_set_vco_speed"); 8251 8252 switch (hw->mac_type) { 8253 case em_82545_rev_3: 8254 case em_82546_rev_3: 8255 break; 8256 default: 8257 return E1000_SUCCESS; 8258 } 8259 8260 /* Set PHY register 30, page 5, bit 8 to 0 */ 8261 8262 ret_val = em_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page); 8263 if (ret_val) 8264 return ret_val; 8265 8266 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005); 8267 if (ret_val) 8268 return ret_val; 8269 8270 ret_val = em_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); 8271 if (ret_val) 8272 return ret_val; 8273 8274 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8; 8275 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); 8276 if (ret_val) 8277 return ret_val; 8278 8279 /* Set PHY register 30, page 4, bit 11 to 1 */ 8280 8281 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004); 8282 if (ret_val) 8283 return ret_val; 8284 8285 ret_val = em_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); 8286 if (ret_val) 8287 return ret_val; 8288 8289 phy_data |= M88E1000_PHY_VCO_REG_BIT11; 8290 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); 8291 if (ret_val) 8292 return ret_val; 8293 8294 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page); 8295 if (ret_val) 8296 return ret_val; 8297 8298 return E1000_SUCCESS; 8299 } 8300 8301 /***************************************************************************** 8302 * This function reads the cookie from ARC ram. 8303 * 8304 * returns: - E1000_SUCCESS . 8305 ****************************************************************************/ 8306 STATIC int32_t 8307 em_host_if_read_cookie(struct em_hw *hw, uint8_t *buffer) 8308 { 8309 uint8_t i; 8310 uint32_t offset = E1000_MNG_DHCP_COOKIE_OFFSET; 8311 uint8_t length = E1000_MNG_DHCP_COOKIE_LENGTH; 8312 length = (length >> 2); 8313 offset = (offset >> 2); 8314 8315 for (i = 0; i < length; i++) { 8316 *((uint32_t *) buffer + i) = 8317 E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i); 8318 } 8319 return E1000_SUCCESS; 8320 } 8321 8322 /***************************************************************************** 8323 * This function checks whether the HOST IF is enabled for command operaton 8324 * and also checks whether the previous command is completed. 8325 * It busy waits in case of previous command is not completed. 8326 * 8327 * returns: - E1000_ERR_HOST_INTERFACE_COMMAND in case if is not ready or 8328 * timeout 8329 * - E1000_SUCCESS for success. 8330 ****************************************************************************/ 8331 STATIC int32_t 8332 em_mng_enable_host_if(struct em_hw *hw) 8333 { 8334 uint32_t hicr; 8335 uint8_t i; 8336 /* Check that the host interface is enabled. */ 8337 hicr = E1000_READ_REG(hw, HICR); 8338 if ((hicr & E1000_HICR_EN) == 0) { 8339 DEBUGOUT("E1000_HOST_EN bit disabled.\n"); 8340 return -E1000_ERR_HOST_INTERFACE_COMMAND; 8341 } 8342 /* check the previous command is completed */ 8343 for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) { 8344 hicr = E1000_READ_REG(hw, HICR); 8345 if (!(hicr & E1000_HICR_C)) 8346 break; 8347 msec_delay_irq(1); 8348 } 8349 8350 if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) { 8351 DEBUGOUT("Previous command timeout failed .\n"); 8352 return -E1000_ERR_HOST_INTERFACE_COMMAND; 8353 } 8354 return E1000_SUCCESS; 8355 } 8356 8357 /***************************************************************************** 8358 * This function checks the mode of the firmware. 8359 * 8360 * returns - TRUE when the mode is IAMT or FALSE. 8361 ****************************************************************************/ 8362 boolean_t 8363 em_check_mng_mode(struct em_hw *hw) 8364 { 8365 uint32_t fwsm; 8366 fwsm = E1000_READ_REG(hw, FWSM); 8367 8368 if (hw->mac_type == em_ich8lan || 8369 hw->mac_type == em_ich9lan || 8370 hw->mac_type == em_ich10lan || 8371 hw->mac_type == em_pchlan || 8372 hw->mac_type == em_pch2lan) { 8373 if ((fwsm & E1000_FWSM_MODE_MASK) == 8374 (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) 8375 return TRUE; 8376 } else if ((fwsm & E1000_FWSM_MODE_MASK) == 8377 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) 8378 return TRUE; 8379 8380 return FALSE; 8381 } 8382 8383 /***************************************************************************** 8384 * This function calculates the checksum. 8385 * 8386 * returns - checksum of buffer contents. 8387 ****************************************************************************/ 8388 STATIC uint8_t 8389 em_calculate_mng_checksum(char *buffer, uint32_t length) 8390 { 8391 uint8_t sum = 0; 8392 uint32_t i; 8393 if (!buffer) 8394 return 0; 8395 8396 for (i = 0; i < length; i++) 8397 sum += buffer[i]; 8398 8399 return (uint8_t) (0 - sum); 8400 } 8401 8402 /***************************************************************************** 8403 * This function checks whether tx pkt filtering needs to be enabled or not. 8404 * 8405 * returns - TRUE for packet filtering or FALSE. 8406 ****************************************************************************/ 8407 boolean_t 8408 em_enable_tx_pkt_filtering(struct em_hw *hw) 8409 { 8410 /* called in init as well as watchdog timer functions */ 8411 int32_t ret_val, checksum; 8412 boolean_t tx_filter = FALSE; 8413 struct em_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie); 8414 uint8_t *buffer = (uint8_t *) & (hw->mng_cookie); 8415 if (em_check_mng_mode(hw)) { 8416 ret_val = em_mng_enable_host_if(hw); 8417 if (ret_val == E1000_SUCCESS) { 8418 ret_val = em_host_if_read_cookie(hw, buffer); 8419 if (ret_val == E1000_SUCCESS) { 8420 checksum = hdr->checksum; 8421 hdr->checksum = 0; 8422 if ((hdr->signature == E1000_IAMT_SIGNATURE) && 8423 checksum == em_calculate_mng_checksum( 8424 (char *) buffer, 8425 E1000_MNG_DHCP_COOKIE_LENGTH)) { 8426 if (hdr->status & 8427 E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT) 8428 tx_filter = TRUE; 8429 } else 8430 tx_filter = TRUE; 8431 } else 8432 tx_filter = TRUE; 8433 } 8434 } 8435 hw->tx_pkt_filtering = tx_filter; 8436 return tx_filter; 8437 } 8438 8439 static int32_t 8440 em_polarity_reversal_workaround(struct em_hw *hw) 8441 { 8442 int32_t ret_val; 8443 uint16_t mii_status_reg; 8444 uint16_t i; 8445 /* Polarity reversal workaround for forced 10F/10H links. */ 8446 8447 /* Disable the transmitter on the PHY */ 8448 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 8449 if (ret_val) 8450 return ret_val; 8451 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF); 8452 if (ret_val) 8453 return ret_val; 8454 8455 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 8456 if (ret_val) 8457 return ret_val; 8458 8459 /* This loop will early-out if the NO link condition has been met. */ 8460 for (i = PHY_FORCE_TIME; i > 0; i--) { 8461 /* 8462 * Read the MII Status Register and wait for Link Status bit 8463 * to be clear. 8464 */ 8465 8466 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 8467 if (ret_val) 8468 return ret_val; 8469 8470 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 8471 if (ret_val) 8472 return ret_val; 8473 8474 if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) 8475 break; 8476 msec_delay_irq(100); 8477 } 8478 8479 /* Recommended delay time after link has been lost */ 8480 msec_delay_irq(1000); 8481 8482 /* Now we will re-enable the transmitter on the PHY */ 8483 8484 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 8485 if (ret_val) 8486 return ret_val; 8487 msec_delay_irq(50); 8488 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0); 8489 if (ret_val) 8490 return ret_val; 8491 msec_delay_irq(50); 8492 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00); 8493 if (ret_val) 8494 return ret_val; 8495 msec_delay_irq(50); 8496 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000); 8497 if (ret_val) 8498 return ret_val; 8499 8500 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 8501 if (ret_val) 8502 return ret_val; 8503 8504 /* This loop will early-out if the link condition has been met. */ 8505 for (i = PHY_FORCE_TIME; i > 0; i--) { 8506 /* 8507 * Read the MII Status Register and wait for Link Status bit 8508 * to be set. 8509 */ 8510 8511 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 8512 if (ret_val) 8513 return ret_val; 8514 8515 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 8516 if (ret_val) 8517 return ret_val; 8518 8519 if (mii_status_reg & MII_SR_LINK_STATUS) 8520 break; 8521 msec_delay_irq(100); 8522 } 8523 return E1000_SUCCESS; 8524 } 8525 8526 /* 8527 * Set whether the PHY self-configures itself in hardware 8528 */ 8529 static void em_pch2lan_disable_hw_config(struct em_hw *hw, boolean_t sc) 8530 { 8531 uint32_t ctrl_ext; 8532 DEBUGFUNC("em_pch2lan_disable_hw_config"); 8533 8534 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 8535 8536 if (sc) 8537 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA; 8538 else 8539 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA; 8540 8541 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 8542 } 8543 8544 /****************************************************************************** 8545 * 8546 * Disables PCI-Express master access. 8547 * 8548 * hw: Struct containing variables accessed by shared code 8549 * 8550 * returns: - none. 8551 * 8552 *****************************************************************************/ 8553 STATIC void 8554 em_set_pci_express_master_disable(struct em_hw *hw) 8555 { 8556 uint32_t ctrl; 8557 DEBUGFUNC("em_set_pci_express_master_disable"); 8558 8559 if (hw->bus_type != em_bus_type_pci_express) 8560 return; 8561 8562 ctrl = E1000_READ_REG(hw, CTRL); 8563 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; 8564 E1000_WRITE_REG(hw, CTRL, ctrl); 8565 } 8566 8567 /****************************************************************************** 8568 * 8569 * Disables PCI-Express master access and verifies there are no pending 8570 * requests 8571 * 8572 * hw: Struct containing variables accessed by shared code 8573 * 8574 * returns: - E1000_ERR_MASTER_REQUESTS_PENDING if master disable bit hasn't 8575 * caused the master requests to be disabled. 8576 * E1000_SUCCESS master requests disabled. 8577 * 8578 ******************************************************************************/ 8579 int32_t 8580 em_disable_pciex_master(struct em_hw *hw) 8581 { 8582 int32_t timeout = MASTER_DISABLE_TIMEOUT; /* 80ms */ 8583 DEBUGFUNC("em_disable_pciex_master"); 8584 8585 if (hw->bus_type != em_bus_type_pci_express) 8586 return E1000_SUCCESS; 8587 8588 em_set_pci_express_master_disable(hw); 8589 8590 while (timeout) { 8591 if (!(E1000_READ_REG(hw, STATUS) & 8592 E1000_STATUS_GIO_MASTER_ENABLE)) 8593 break; 8594 else 8595 usec_delay(100); 8596 timeout--; 8597 } 8598 8599 if (!timeout) { 8600 DEBUGOUT("Master requests are pending.\n"); 8601 return -E1000_ERR_MASTER_REQUESTS_PENDING; 8602 } 8603 return E1000_SUCCESS; 8604 } 8605 8606 /****************************************************************************** 8607 * 8608 * Check for EEPROM Auto Read bit done. 8609 * 8610 * hw: Struct containing variables accessed by shared code 8611 * 8612 * returns: - E1000_ERR_RESET if fail to reset MAC 8613 * E1000_SUCCESS at any other case. 8614 * 8615 ******************************************************************************/ 8616 STATIC int32_t 8617 em_get_auto_rd_done(struct em_hw *hw) 8618 { 8619 int32_t timeout = AUTO_READ_DONE_TIMEOUT; 8620 DEBUGFUNC("em_get_auto_rd_done"); 8621 8622 switch (hw->mac_type) { 8623 default: 8624 msec_delay(5); 8625 break; 8626 case em_82571: 8627 case em_82572: 8628 case em_82573: 8629 case em_82574: 8630 case em_82575: 8631 case em_82580: 8632 case em_80003es2lan: 8633 case em_ich8lan: 8634 case em_ich9lan: 8635 case em_ich10lan: 8636 case em_pchlan: 8637 case em_pch2lan: 8638 while (timeout) { 8639 if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD) 8640 break; 8641 else 8642 msec_delay(1); 8643 timeout--; 8644 } 8645 8646 if (!timeout) { 8647 DEBUGOUT("Auto read by HW from EEPROM has not" 8648 " completed.\n"); 8649 return -E1000_ERR_RESET; 8650 } 8651 break; 8652 } 8653 /* 8654 * PHY configuration from NVM just starts after EECD_AUTO_RD sets to 8655 * high. Need to wait for PHY configuration completion before 8656 * accessing NVM and PHY. 8657 */ 8658 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) 8659 msec_delay(25); 8660 8661 return E1000_SUCCESS; 8662 } 8663 8664 /*************************************************************************** 8665 * Checks if the PHY configuration is done 8666 * 8667 * hw: Struct containing variables accessed by shared code 8668 * 8669 * returns: - E1000_ERR_RESET if fail to reset MAC 8670 * E1000_SUCCESS at any other case. 8671 * 8672 ***************************************************************************/ 8673 STATIC int32_t 8674 em_get_phy_cfg_done(struct em_hw *hw) 8675 { 8676 int32_t timeout = PHY_CFG_TIMEOUT; 8677 uint32_t cfg_mask = E1000_EEPROM_CFG_DONE; 8678 DEBUGFUNC("em_get_phy_cfg_done"); 8679 8680 switch (hw->mac_type) { 8681 default: 8682 msec_delay_irq(10); 8683 break; 8684 case em_80003es2lan: 8685 case em_82575: 8686 /* Separate *_CFG_DONE_* bit for each port */ 8687 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) 8688 cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1; 8689 /* FALLTHROUGH */ 8690 case em_82571: 8691 case em_82572: 8692 while (timeout) { 8693 if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask) 8694 break; 8695 else 8696 msec_delay(1); 8697 timeout--; 8698 } 8699 if (!timeout) { 8700 DEBUGOUT("MNG configuration cycle has not completed." 8701 "\n"); 8702 } 8703 break; 8704 } 8705 8706 return E1000_SUCCESS; 8707 } 8708 8709 /*************************************************************************** 8710 * 8711 * Using the combination of SMBI and SWESMBI semaphore bits when resetting 8712 * adapter or Eeprom access. 8713 * 8714 * hw: Struct containing variables accessed by shared code 8715 * 8716 * returns: - E1000_ERR_EEPROM if fail to access EEPROM. 8717 * E1000_SUCCESS at any other case. 8718 * 8719 ***************************************************************************/ 8720 STATIC int32_t 8721 em_get_hw_eeprom_semaphore(struct em_hw *hw) 8722 { 8723 int32_t timeout; 8724 uint32_t swsm; 8725 DEBUGFUNC("em_get_hw_eeprom_semaphore"); 8726 8727 if (!hw->eeprom_semaphore_present) 8728 return E1000_SUCCESS; 8729 8730 if (hw->mac_type == em_80003es2lan) { 8731 /* Get the SW semaphore. */ 8732 if (em_get_software_semaphore(hw) != E1000_SUCCESS) 8733 return -E1000_ERR_EEPROM; 8734 } 8735 /* Get the FW semaphore. */ 8736 timeout = hw->eeprom.word_size + 1; 8737 while (timeout) { 8738 swsm = E1000_READ_REG(hw, SWSM); 8739 swsm |= E1000_SWSM_SWESMBI; 8740 E1000_WRITE_REG(hw, SWSM, swsm); 8741 /* if we managed to set the bit we got the semaphore. */ 8742 swsm = E1000_READ_REG(hw, SWSM); 8743 if (swsm & E1000_SWSM_SWESMBI) 8744 break; 8745 8746 usec_delay(50); 8747 timeout--; 8748 } 8749 8750 if (!timeout) { 8751 /* Release semaphores */ 8752 em_put_hw_eeprom_semaphore(hw); 8753 DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set." 8754 "\n"); 8755 return -E1000_ERR_EEPROM; 8756 } 8757 return E1000_SUCCESS; 8758 } 8759 8760 /*************************************************************************** 8761 * This function clears HW semaphore bits. 8762 * 8763 * hw: Struct containing variables accessed by shared code 8764 * 8765 * returns: - None. 8766 * 8767 ***************************************************************************/ 8768 STATIC void 8769 em_put_hw_eeprom_semaphore(struct em_hw *hw) 8770 { 8771 uint32_t swsm; 8772 DEBUGFUNC("em_put_hw_eeprom_semaphore"); 8773 8774 if (!hw->eeprom_semaphore_present) 8775 return; 8776 8777 swsm = E1000_READ_REG(hw, SWSM); 8778 if (hw->mac_type == em_80003es2lan) { 8779 /* Release both semaphores. */ 8780 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 8781 } else 8782 swsm &= ~(E1000_SWSM_SWESMBI); 8783 E1000_WRITE_REG(hw, SWSM, swsm); 8784 } 8785 8786 /*************************************************************************** 8787 * 8788 * Obtaining software semaphore bit (SMBI) before resetting PHY. 8789 * 8790 * hw: Struct containing variables accessed by shared code 8791 * 8792 * returns: - E1000_ERR_RESET if fail to obtain semaphore. 8793 * E1000_SUCCESS at any other case. 8794 * 8795 ***************************************************************************/ 8796 STATIC int32_t 8797 em_get_software_semaphore(struct em_hw *hw) 8798 { 8799 int32_t timeout = hw->eeprom.word_size + 1; 8800 uint32_t swsm; 8801 DEBUGFUNC("em_get_software_semaphore"); 8802 8803 if (hw->mac_type != em_80003es2lan) 8804 return E1000_SUCCESS; 8805 8806 while (timeout) { 8807 swsm = E1000_READ_REG(hw, SWSM); 8808 /* 8809 * If SMBI bit cleared, it is now set and we hold the 8810 * semaphore 8811 */ 8812 if (!(swsm & E1000_SWSM_SMBI)) 8813 break; 8814 msec_delay_irq(1); 8815 timeout--; 8816 } 8817 8818 if (!timeout) { 8819 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 8820 return -E1000_ERR_RESET; 8821 } 8822 return E1000_SUCCESS; 8823 } 8824 8825 /*************************************************************************** 8826 * 8827 * Release semaphore bit (SMBI). 8828 * 8829 * hw: Struct containing variables accessed by shared code 8830 * 8831 ***************************************************************************/ 8832 STATIC void 8833 em_release_software_semaphore(struct em_hw *hw) 8834 { 8835 uint32_t swsm; 8836 DEBUGFUNC("em_release_software_semaphore"); 8837 8838 if (hw->mac_type != em_80003es2lan) 8839 return; 8840 8841 swsm = E1000_READ_REG(hw, SWSM); 8842 /* Release the SW semaphores. */ 8843 swsm &= ~E1000_SWSM_SMBI; 8844 E1000_WRITE_REG(hw, SWSM, swsm); 8845 } 8846 8847 /****************************************************************************** 8848 * Checks if PHY reset is blocked due to SOL/IDER session, for example. 8849 * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to 8850 * the caller to figure out how to deal with it. 8851 * 8852 * hw - Struct containing variables accessed by shared code 8853 * 8854 * returns: - E1000_BLK_PHY_RESET 8855 * E1000_SUCCESS 8856 * 8857 *****************************************************************************/ 8858 int32_t 8859 em_check_phy_reset_block(struct em_hw *hw) 8860 { 8861 uint32_t manc = 0; 8862 uint32_t fwsm = 0; 8863 if (hw->mac_type == em_ich8lan || 8864 hw->mac_type == em_ich9lan || 8865 hw->mac_type == em_ich10lan || 8866 hw->mac_type == em_pchlan || 8867 hw->mac_type == em_pch2lan) { 8868 fwsm = E1000_READ_REG(hw, FWSM); 8869 return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS : 8870 E1000_BLK_PHY_RESET; 8871 } 8872 if (hw->mac_type > em_82547_rev_2) 8873 manc = E1000_READ_REG(hw, MANC); 8874 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? 8875 E1000_BLK_PHY_RESET : E1000_SUCCESS; 8876 } 8877 8878 /****************************************************************************** 8879 * Configure PCI-Ex no-snoop 8880 * 8881 * hw - Struct containing variables accessed by shared code. 8882 * no_snoop - Bitmap of no-snoop events. 8883 * 8884 * returns: E1000_SUCCESS 8885 * 8886 *****************************************************************************/ 8887 STATIC int32_t 8888 em_set_pci_ex_no_snoop(struct em_hw *hw, uint32_t no_snoop) 8889 { 8890 uint32_t gcr_reg = 0; 8891 DEBUGFUNC("em_set_pci_ex_no_snoop"); 8892 8893 if (hw->bus_type == em_bus_type_unknown) 8894 em_get_bus_info(hw); 8895 8896 if (hw->bus_type != em_bus_type_pci_express) 8897 return E1000_SUCCESS; 8898 8899 if (no_snoop) { 8900 gcr_reg = E1000_READ_REG(hw, GCR); 8901 gcr_reg &= ~(PCI_EX_NO_SNOOP_ALL); 8902 gcr_reg |= no_snoop; 8903 E1000_WRITE_REG(hw, GCR, gcr_reg); 8904 } 8905 if (hw->mac_type == em_ich8lan || 8906 hw->mac_type == em_ich9lan || 8907 hw->mac_type == em_ich10lan || 8908 hw->mac_type == em_pchlan || 8909 hw->mac_type == em_pch2lan) { 8910 uint32_t ctrl_ext; 8911 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 8912 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 8913 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 8914 } 8915 return E1000_SUCCESS; 8916 } 8917 8918 /*************************************************************************** 8919 * 8920 * Get software semaphore FLAG bit (SWFLAG). 8921 * SWFLAG is used to synchronize the access to all shared resource between 8922 * SW, FW and HW. 8923 * 8924 * hw: Struct containing variables accessed by shared code 8925 * 8926 ***************************************************************************/ 8927 STATIC int32_t 8928 em_get_software_flag(struct em_hw *hw) 8929 { 8930 int32_t timeout = PHY_CFG_TIMEOUT; 8931 uint32_t extcnf_ctrl; 8932 DEBUGFUNC("em_get_software_flag"); 8933 8934 if (hw->mac_type == em_ich8lan || 8935 hw->mac_type == em_ich9lan || 8936 hw->mac_type == em_ich10lan || 8937 hw->mac_type == em_pchlan || 8938 hw->mac_type == em_pch2lan) { 8939 while (timeout) { 8940 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 8941 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; 8942 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); 8943 8944 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 8945 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) 8946 break; 8947 msec_delay_irq(1); 8948 timeout--; 8949 } 8950 8951 if (!timeout) { 8952 DEBUGOUT("FW or HW locks the resource too long.\n"); 8953 return -E1000_ERR_CONFIG; 8954 } 8955 } 8956 return E1000_SUCCESS; 8957 } 8958 8959 /*************************************************************************** 8960 * 8961 * Release software semaphore FLAG bit (SWFLAG). 8962 * SWFLAG is used to synchronize the access to all shared resource between 8963 * SW, FW and HW. 8964 * 8965 * hw: Struct containing variables accessed by shared code 8966 * 8967 ***************************************************************************/ 8968 STATIC void 8969 em_release_software_flag(struct em_hw *hw) 8970 { 8971 uint32_t extcnf_ctrl; 8972 DEBUGFUNC("em_release_software_flag"); 8973 8974 if (hw->mac_type == em_ich8lan || 8975 hw->mac_type == em_ich9lan || 8976 hw->mac_type == em_ich10lan || 8977 hw->mac_type == em_pchlan || 8978 hw->mac_type == em_pch2lan) { 8979 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 8980 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 8981 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); 8982 } 8983 return; 8984 } 8985 8986 /****************************************************************************** 8987 * Reads a 16 bit word or words from the EEPROM using the ICH8's flash access 8988 * register. 8989 * 8990 * hw - Struct containing variables accessed by shared code 8991 * offset - offset of word in the EEPROM to read 8992 * data - word read from the EEPROM 8993 * words - number of words to read 8994 *****************************************************************************/ 8995 STATIC int32_t 8996 em_read_eeprom_ich8(struct em_hw *hw, uint16_t offset, uint16_t words, 8997 uint16_t *data) 8998 { 8999 int32_t error = E1000_SUCCESS; 9000 uint32_t flash_bank = 0; 9001 uint32_t act_offset = 0; 9002 uint32_t bank_offset = 0; 9003 uint16_t word = 0; 9004 uint16_t i = 0; 9005 /* 9006 * We need to know which is the valid flash bank. In the event that 9007 * we didn't allocate eeprom_shadow_ram, we may not be managing 9008 * flash_bank. So it cannot be trusted and needs to be updated with 9009 * each read. 9010 */ 9011 /* Value of bit 22 corresponds to the flash bank we're on. */ 9012 flash_bank = (E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL) ? 1 : 0; 9013 /* 9014 * Adjust offset appropriately if we're on bank 1 - adjust for word 9015 * size 9016 */ 9017 bank_offset = flash_bank * (hw->flash_bank_size * 2); 9018 9019 error = em_get_software_flag(hw); 9020 if (error != E1000_SUCCESS) 9021 return error; 9022 9023 for (i = 0; i < words; i++) { 9024 if (hw->eeprom_shadow_ram != NULL && 9025 hw->eeprom_shadow_ram[offset + i].modified == TRUE) { 9026 data[i] = 9027 hw->eeprom_shadow_ram[offset + i].eeprom_word; 9028 } else { 9029 /* The NVM part needs a byte offset, hence * 2 */ 9030 act_offset = bank_offset + ((offset + i) * 2); 9031 error = em_read_ich8_word(hw, act_offset, &word); 9032 if (error != E1000_SUCCESS) 9033 break; 9034 data[i] = word; 9035 } 9036 } 9037 9038 em_release_software_flag(hw); 9039 9040 return error; 9041 } 9042 9043 /****************************************************************************** 9044 * Writes a 16 bit word or words to the EEPROM using the ICH8's flash access 9045 * register. Actually, writes are written to the shadow ram cache in the hw 9046 * structure hw->em_shadow_ram. em_commit_shadow_ram flushes this to 9047 * the NVM, which occurs when the NVM checksum is updated. 9048 * 9049 * hw - Struct containing variables accessed by shared code 9050 * offset - offset of word in the EEPROM to write 9051 * words - number of words to write 9052 * data - words to write to the EEPROM 9053 *****************************************************************************/ 9054 STATIC int32_t 9055 em_write_eeprom_ich8(struct em_hw *hw, uint16_t offset, uint16_t words, 9056 uint16_t *data) 9057 { 9058 uint32_t i = 0; 9059 int32_t error = E1000_SUCCESS; 9060 error = em_get_software_flag(hw); 9061 if (error != E1000_SUCCESS) 9062 return error; 9063 /* 9064 * A driver can write to the NVM only if it has eeprom_shadow_ram 9065 * allocated. Subsequent reads to the modified words are read from 9066 * this cached structure as well. Writes will only go into this 9067 * cached structure unless it's followed by a call to 9068 * em_update_eeprom_checksum() where it will commit the changes and 9069 * clear the "modified" field. 9070 */ 9071 if (hw->eeprom_shadow_ram != NULL) { 9072 for (i = 0; i < words; i++) { 9073 if ((offset + i) < E1000_SHADOW_RAM_WORDS) { 9074 hw->eeprom_shadow_ram[offset + i].modified = 9075 TRUE; 9076 hw->eeprom_shadow_ram[offset + i].eeprom_word = 9077 data[i]; 9078 } else { 9079 error = -E1000_ERR_EEPROM; 9080 break; 9081 } 9082 } 9083 } else { 9084 /* 9085 * Drivers have the option to not allocate eeprom_shadow_ram 9086 * as long as they don't perform any NVM writes. An attempt 9087 * in doing so will result in this error. 9088 */ 9089 error = -E1000_ERR_EEPROM; 9090 } 9091 9092 em_release_software_flag(hw); 9093 9094 return error; 9095 } 9096 9097 /****************************************************************************** 9098 * This function does initial flash setup so that a new read/write/erase cycle 9099 * can be started. 9100 * 9101 * hw - The pointer to the hw structure 9102 ****************************************************************************/ 9103 STATIC int32_t 9104 em_ich8_cycle_init(struct em_hw *hw) 9105 { 9106 union ich8_hws_flash_status hsfsts; 9107 int32_t error = E1000_ERR_EEPROM; 9108 int32_t i = 0; 9109 DEBUGFUNC("em_ich8_cycle_init"); 9110 9111 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 9112 9113 /* May be check the Flash Des Valid bit in Hw status */ 9114 if (hsfsts.hsf_status.fldesvalid == 0) { 9115 DEBUGOUT("Flash descriptor invalid. SW Sequencing must be" 9116 " used."); 9117 return error; 9118 } 9119 /* Clear FCERR in Hw status by writing 1 */ 9120 /* Clear DAEL in Hw status by writing a 1 */ 9121 hsfsts.hsf_status.flcerr = 1; 9122 hsfsts.hsf_status.dael = 1; 9123 9124 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval); 9125 /* 9126 * Either we should have a hardware SPI cycle in progress bit to 9127 * check against, in order to start a new cycle or FDONE bit should 9128 * be changed in the hardware so that it is 1 after harware reset, 9129 * which can then be used as an indication whether a cycle is in 9130 * progress or has been completed .. we should also have some 9131 * software semaphore mechanism to guard FDONE or the cycle in 9132 * progress bit so that two threads access to those bits can be 9133 * sequentiallized or a way so that 2 threads dont start the cycle at 9134 * the same time 9135 */ 9136 9137 if (hsfsts.hsf_status.flcinprog == 0) { 9138 /* 9139 * There is no cycle running at present, so we can start a 9140 * cycle 9141 */ 9142 /* Begin by setting Flash Cycle Done. */ 9143 hsfsts.hsf_status.flcdone = 1; 9144 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, 9145 hsfsts.regval); 9146 error = E1000_SUCCESS; 9147 } else { 9148 /* 9149 * otherwise poll for sometime so the current cycle has a 9150 * chance to end before giving up. 9151 */ 9152 for (i = 0; i < ICH_FLASH_COMMAND_TIMEOUT; i++) { 9153 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, 9154 ICH_FLASH_HSFSTS); 9155 if (hsfsts.hsf_status.flcinprog == 0) { 9156 error = E1000_SUCCESS; 9157 break; 9158 } 9159 usec_delay(1); 9160 } 9161 if (error == E1000_SUCCESS) { 9162 /* 9163 * Successful in waiting for previous cycle to 9164 * timeout, now set the Flash Cycle Done. 9165 */ 9166 hsfsts.hsf_status.flcdone = 1; 9167 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, 9168 hsfsts.regval); 9169 } else { 9170 DEBUGOUT("Flash controller busy, cannot get access"); 9171 } 9172 } 9173 return error; 9174 } 9175 9176 /****************************************************************************** 9177 * This function starts a flash cycle and waits for its completion 9178 * 9179 * hw - The pointer to the hw structure 9180 *****************************************************************************/ 9181 STATIC int32_t 9182 em_ich8_flash_cycle(struct em_hw *hw, uint32_t timeout) 9183 { 9184 union ich8_hws_flash_ctrl hsflctl; 9185 union ich8_hws_flash_status hsfsts; 9186 int32_t error = E1000_ERR_EEPROM; 9187 uint32_t i = 0; 9188 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ 9189 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL); 9190 hsflctl.hsf_ctrl.flcgo = 1; 9191 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); 9192 9193 /* wait till FDONE bit is set to 1 */ 9194 do { 9195 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, 9196 ICH_FLASH_HSFSTS); 9197 if (hsfsts.hsf_status.flcdone == 1) 9198 break; 9199 usec_delay(1); 9200 i++; 9201 } while (i < timeout); 9202 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) { 9203 error = E1000_SUCCESS; 9204 } 9205 return error; 9206 } 9207 9208 /****************************************************************************** 9209 * Reads a byte or word from the NVM using the ICH8 flash access registers. 9210 * 9211 * hw - The pointer to the hw structure 9212 * index - The index of the byte or word to read. 9213 * size - Size of data to read, 1=byte 2=word 9214 * data - Pointer to the word to store the value read. 9215 *****************************************************************************/ 9216 STATIC int32_t 9217 em_read_ich8_data(struct em_hw *hw, uint32_t index, uint32_t size, 9218 uint16_t *data) 9219 { 9220 union ich8_hws_flash_status hsfsts; 9221 union ich8_hws_flash_ctrl hsflctl; 9222 uint32_t flash_linear_address; 9223 uint32_t flash_data = 0; 9224 int32_t error = -E1000_ERR_EEPROM; 9225 int32_t count = 0; 9226 DEBUGFUNC("em_read_ich8_data"); 9227 9228 if (size < 1 || size > 2 || data == 0x0 || 9229 index > ICH_FLASH_LINEAR_ADDR_MASK) 9230 return error; 9231 9232 flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) + 9233 hw->flash_base_addr; 9234 9235 do { 9236 usec_delay(1); 9237 /* Steps */ 9238 error = em_ich8_cycle_init(hw); 9239 if (error != E1000_SUCCESS) 9240 break; 9241 9242 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, 9243 ICH_FLASH_HSFCTL); 9244 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 9245 hsflctl.hsf_ctrl.fldbcount = size - 1; 9246 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; 9247 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, 9248 hsflctl.regval); 9249 /* 9250 * Write the last 24 bits of index into Flash Linear address 9251 * field in Flash Address 9252 */ 9253 /* TODO: TBD maybe check the index against the size of flash */ 9254 9255 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, 9256 flash_linear_address); 9257 9258 error = em_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT); 9259 /* 9260 * Check if FCERR is set to 1, if set to 1, clear it and try 9261 * the whole sequence a few more times, else read in (shift 9262 * in) the Flash Data0, the order is least significant byte 9263 * first msb to lsb 9264 */ 9265 if (error == E1000_SUCCESS) { 9266 flash_data = E1000_READ_ICH_FLASH_REG(hw, 9267 ICH_FLASH_FDATA0); 9268 if (size == 1) { 9269 *data = (uint8_t) (flash_data & 0x000000FF); 9270 } else if (size == 2) { 9271 *data = (uint16_t) (flash_data & 0x0000FFFF); 9272 } 9273 break; 9274 } else { 9275 /* 9276 * If we've gotten here, then things are probably 9277 * completely hosed, but if the error condition is 9278 * detected, it won't hurt to give it another 9279 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 9280 */ 9281 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, 9282 ICH_FLASH_HSFSTS); 9283 if (hsfsts.hsf_status.flcerr == 1) { 9284 /* Repeat for some time before giving up. */ 9285 continue; 9286 } else if (hsfsts.hsf_status.flcdone == 0) { 9287 DEBUGOUT("Timeout error - flash cycle did not" 9288 " complete."); 9289 break; 9290 } 9291 } 9292 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 9293 9294 return error; 9295 } 9296 9297 /****************************************************************************** 9298 * Writes One /two bytes to the NVM using the ICH8 flash access registers. 9299 * 9300 * hw - The pointer to the hw structure 9301 * index - The index of the byte/word to read. 9302 * size - Size of data to read, 1=byte 2=word 9303 * data - The byte(s) to write to the NVM. 9304 *****************************************************************************/ 9305 STATIC int32_t 9306 em_write_ich8_data(struct em_hw *hw, uint32_t index, uint32_t size, 9307 uint16_t data) 9308 { 9309 union ich8_hws_flash_status hsfsts; 9310 union ich8_hws_flash_ctrl hsflctl; 9311 uint32_t flash_linear_address; 9312 uint32_t flash_data = 0; 9313 int32_t error = -E1000_ERR_EEPROM; 9314 int32_t count = 0; 9315 DEBUGFUNC("em_write_ich8_data"); 9316 9317 if (size < 1 || size > 2 || data > size * 0xff || 9318 index > ICH_FLASH_LINEAR_ADDR_MASK) 9319 return error; 9320 9321 flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) + 9322 hw->flash_base_addr; 9323 9324 do { 9325 usec_delay(1); 9326 /* Steps */ 9327 error = em_ich8_cycle_init(hw); 9328 if (error != E1000_SUCCESS) 9329 break; 9330 9331 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, 9332 ICH_FLASH_HSFCTL); 9333 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 9334 hsflctl.hsf_ctrl.fldbcount = size - 1; 9335 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; 9336 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, 9337 hsflctl.regval); 9338 /* 9339 * Write the last 24 bits of index into Flash Linear address 9340 * field in Flash Address 9341 */ 9342 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, 9343 flash_linear_address); 9344 9345 if (size == 1) 9346 flash_data = (uint32_t) data & 0x00FF; 9347 else 9348 flash_data = (uint32_t) data; 9349 9350 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data); 9351 /* 9352 * check if FCERR is set to 1 , if set to 1, clear it and try 9353 * the whole sequence a few more times else done 9354 */ 9355 error = em_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT); 9356 if (error == E1000_SUCCESS) { 9357 break; 9358 } else { 9359 /* 9360 * If we're here, then things are most likely 9361 * completely hosed, but if the error condition is 9362 * detected, it won't hurt to give it another 9363 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 9364 */ 9365 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, 9366 ICH_FLASH_HSFSTS); 9367 if (hsfsts.hsf_status.flcerr == 1) { 9368 /* Repeat for some time before giving up. */ 9369 continue; 9370 } else if (hsfsts.hsf_status.flcdone == 0) { 9371 DEBUGOUT("Timeout error - flash cycle did not" 9372 " complete."); 9373 break; 9374 } 9375 } 9376 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 9377 9378 return error; 9379 } 9380 9381 /****************************************************************************** 9382 * Reads a single byte from the NVM using the ICH8 flash access registers. 9383 * 9384 * hw - pointer to em_hw structure 9385 * index - The index of the byte to read. 9386 * data - Pointer to a byte to store the value read. 9387 *****************************************************************************/ 9388 STATIC int32_t 9389 em_read_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t *data) 9390 { 9391 int32_t status = E1000_SUCCESS; 9392 uint16_t word = 0; 9393 status = em_read_ich8_data(hw, index, 1, &word); 9394 if (status == E1000_SUCCESS) { 9395 *data = (uint8_t) word; 9396 } 9397 return status; 9398 } 9399 9400 /****************************************************************************** 9401 * Writes a single byte to the NVM using the ICH8 flash access registers. 9402 * Performs verification by reading back the value and then going through 9403 * a retry algorithm before giving up. 9404 * 9405 * hw - pointer to em_hw structure 9406 * index - The index of the byte to write. 9407 * byte - The byte to write to the NVM. 9408 *****************************************************************************/ 9409 STATIC int32_t 9410 em_verify_write_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t byte) 9411 { 9412 int32_t error = E1000_SUCCESS; 9413 int32_t program_retries = 0; 9414 DEBUGOUT2("Byte := %2.2X Offset := %d\n", byte, index); 9415 9416 error = em_write_ich8_byte(hw, index, byte); 9417 9418 if (error != E1000_SUCCESS) { 9419 for (program_retries = 0; program_retries < 100; 9420 program_retries++) { 9421 DEBUGOUT2("Retrying \t Byte := %2.2X Offset := %d\n", 9422 byte, index); 9423 error = em_write_ich8_byte(hw, index, byte); 9424 usec_delay(100); 9425 if (error == E1000_SUCCESS) 9426 break; 9427 } 9428 } 9429 if (program_retries == 100) 9430 error = E1000_ERR_EEPROM; 9431 9432 return error; 9433 } 9434 9435 /****************************************************************************** 9436 * Writes a single byte to the NVM using the ICH8 flash access registers. 9437 * 9438 * hw - pointer to em_hw structure 9439 * index - The index of the byte to read. 9440 * data - The byte to write to the NVM. 9441 *****************************************************************************/ 9442 STATIC int32_t 9443 em_write_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t data) 9444 { 9445 int32_t status = E1000_SUCCESS; 9446 uint16_t word = (uint16_t) data; 9447 status = em_write_ich8_data(hw, index, 1, word); 9448 9449 return status; 9450 } 9451 9452 /****************************************************************************** 9453 * Reads a word from the NVM using the ICH8 flash access registers. 9454 * 9455 * hw - pointer to em_hw structure 9456 * index - The starting byte index of the word to read. 9457 * data - Pointer to a word to store the value read. 9458 *****************************************************************************/ 9459 STATIC int32_t 9460 em_read_ich8_word(struct em_hw *hw, uint32_t index, uint16_t *data) 9461 { 9462 int32_t status = E1000_SUCCESS; 9463 status = em_read_ich8_data(hw, index, 2, data); 9464 return status; 9465 } 9466 9467 /****************************************************************************** 9468 * Erases the bank specified. Each bank may be a 4, 8 or 64k block. Banks are 0 9469 * based. 9470 * 9471 * hw - pointer to em_hw structure 9472 * bank - 0 for first bank, 1 for second bank 9473 * 9474 * Note that this function may actually erase as much as 8 or 64 KBytes. The 9475 * amount of NVM used in each bank is a *minimum* of 4 KBytes, but in fact the 9476 * bank size may be 4, 8 or 64 KBytes 9477 *****************************************************************************/ 9478 int32_t 9479 em_erase_ich8_4k_segment(struct em_hw *hw, uint32_t bank) 9480 { 9481 union ich8_hws_flash_status hsfsts; 9482 union ich8_hws_flash_ctrl hsflctl; 9483 uint32_t flash_linear_address; 9484 int32_t count = 0; 9485 int32_t error = E1000_ERR_EEPROM; 9486 int32_t iteration; 9487 int32_t sub_sector_size = 0; 9488 int32_t bank_size; 9489 int32_t j = 0; 9490 int32_t error_flag = 0; 9491 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 9492 /* 9493 * Determine HW Sector size: Read BERASE bits of Hw flash Status 9494 * register 9495 */ 9496 /* 9497 * 00: The Hw sector is 256 bytes, hence we need to erase 16 9498 * consecutive sectors. The start index for the nth Hw sector can be 9499 * calculated as bank * 4096 + n * 256 01: The Hw sector is 4K bytes, 9500 * hence we need to erase 1 sector. The start index for the nth Hw 9501 * sector can be calculated as bank * 4096 10: The HW sector is 8K 9502 * bytes 11: The Hw sector size is 64K bytes 9503 */ 9504 if (hsfsts.hsf_status.berasesz == 0x0) { 9505 /* Hw sector size 256 */ 9506 sub_sector_size = ICH_FLASH_SEG_SIZE_256; 9507 bank_size = ICH_FLASH_SECTOR_SIZE; 9508 iteration = ICH_FLASH_SECTOR_SIZE / ICH_FLASH_SEG_SIZE_256; 9509 } else if (hsfsts.hsf_status.berasesz == 0x1) { 9510 bank_size = ICH_FLASH_SEG_SIZE_4K; 9511 iteration = 1; 9512 } else if (hsfsts.hsf_status.berasesz == 0x2) { 9513 if (hw->mac_type == em_ich9lan) { 9514 uint32_t gfpreg, sector_base_addr, sector_end_addr; 9515 gfpreg = E1000_READ_ICH_FLASH_REG(hw, 9516 ICH_FLASH_GFPREG); 9517 /* 9518 * sector_X_addr is a "sector"-aligned address (4096 bytes) 9519 * Add 1 to sector_end_addr since this sector is included in 9520 * the overall size. 9521 */ 9522 sector_base_addr = gfpreg & ICH_GFPREG_BASE_MASK; 9523 sector_end_addr = 9524 ((gfpreg >> 16) & ICH_GFPREG_BASE_MASK) + 1; 9525 9526 /* 9527 * find total size of the NVM, then cut in half since the total 9528 * size represents two separate NVM banks. 9529 */ 9530 bank_size = (sector_end_addr - sector_base_addr) 9531 << ICH_FLASH_SECT_ADDR_SHIFT; 9532 bank_size /= 2; 9533 /* Word align */ 9534 bank_size = 9535 (bank_size / sizeof(uint16_t)) * sizeof(uint16_t); 9536 9537 sub_sector_size = ICH_FLASH_SEG_SIZE_8K; 9538 iteration = bank_size / ICH_FLASH_SEG_SIZE_8K; 9539 } else { 9540 return error; 9541 } 9542 } else if (hsfsts.hsf_status.berasesz == 0x3) { 9543 bank_size = ICH_FLASH_SEG_SIZE_64K; 9544 iteration = 1; 9545 } else { 9546 return error; 9547 } 9548 9549 for (j = 0; j < iteration; j++) { 9550 do { 9551 count++; 9552 /* Steps */ 9553 error = em_ich8_cycle_init(hw); 9554 if (error != E1000_SUCCESS) { 9555 error_flag = 1; 9556 break; 9557 } 9558 /* 9559 * Write a value 11 (block Erase) in Flash Cycle 9560 * field in Hw flash Control 9561 */ 9562 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, 9563 ICH_FLASH_HSFCTL); 9564 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE; 9565 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, 9566 hsflctl.regval); 9567 /* 9568 * Write the last 24 bits of an index within the 9569 * block into Flash Linear address field in Flash 9570 * Address. This probably needs to be calculated 9571 * here based off the on-chip erase sector size and 9572 * the software bank size (4, 8 or 64 KBytes) 9573 */ 9574 flash_linear_address = 9575 bank * bank_size + j * sub_sector_size; 9576 flash_linear_address += hw->flash_base_addr; 9577 flash_linear_address &= ICH_FLASH_LINEAR_ADDR_MASK; 9578 9579 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, 9580 flash_linear_address); 9581 9582 error = 9583 em_ich8_flash_cycle(hw, ICH_FLASH_ERASE_TIMEOUT); 9584 /* 9585 * Check if FCERR is set to 1. If 1, clear it and 9586 * try the whole sequence a few more times else Done 9587 */ 9588 if (error == E1000_SUCCESS) { 9589 break; 9590 } else { 9591 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, 9592 ICH_FLASH_HSFSTS); 9593 if (hsfsts.hsf_status.flcerr == 1) { 9594 /* 9595 * repeat for some time before giving 9596 * up 9597 */ 9598 continue; 9599 } else if (hsfsts.hsf_status.flcdone == 0) { 9600 error_flag = 1; 9601 break; 9602 } 9603 } 9604 } while ((count < ICH_FLASH_CYCLE_REPEAT_COUNT) && !error_flag); 9605 if (error_flag == 1) 9606 break; 9607 } 9608 if (error_flag != 1) 9609 error = E1000_SUCCESS; 9610 return error; 9611 } 9612 9613 STATIC int32_t 9614 em_init_lcd_from_nvm_config_region(struct em_hw *hw, uint32_t cnf_base_addr, 9615 uint32_t cnf_size) 9616 { 9617 uint32_t ret_val = E1000_SUCCESS; 9618 uint16_t word_addr, reg_data, reg_addr; 9619 uint16_t i; 9620 /* cnf_base_addr is in DWORD */ 9621 word_addr = (uint16_t) (cnf_base_addr << 1); 9622 9623 /* cnf_size is returned in size of dwords */ 9624 for (i = 0; i < cnf_size; i++) { 9625 ret_val = 9626 em_read_eeprom(hw, (word_addr + i * 2), 1, ®_data); 9627 if (ret_val) 9628 return ret_val; 9629 9630 ret_val = 9631 em_read_eeprom(hw, (word_addr + i * 2 + 1), 1, ®_addr); 9632 if (ret_val) 9633 return ret_val; 9634 9635 ret_val = em_get_software_flag(hw); 9636 if (ret_val != E1000_SUCCESS) 9637 return ret_val; 9638 9639 ret_val = 9640 em_write_phy_reg_ex(hw, (uint32_t) reg_addr, reg_data); 9641 9642 em_release_software_flag(hw); 9643 } 9644 9645 return ret_val; 9646 } 9647 9648 /****************************************************************************** 9649 * This function initializes the PHY from the NVM on ICH8 platforms. This 9650 * is needed due to an issue where the NVM configuration is not properly 9651 * autoloaded after power transitions. Therefore, after each PHY reset, we 9652 * will load the configuration data out of the NVM manually. 9653 * 9654 * hw: Struct containing variables accessed by shared code 9655 *****************************************************************************/ 9656 STATIC int32_t 9657 em_init_lcd_from_nvm(struct em_hw *hw) 9658 { 9659 uint32_t reg_data, cnf_base_addr, cnf_size, ret_val, loop, sw_cfg_mask; 9660 if (hw->phy_type != em_phy_igp_3) 9661 return E1000_SUCCESS; 9662 9663 /* Check if SW needs configure the PHY */ 9664 if (hw->device_id == E1000_DEV_ID_ICH8_IGP_M_AMT || 9665 hw->device_id == E1000_DEV_ID_ICH8_IGP_M || 9666 hw->mac_type == em_pchlan || 9667 hw->mac_type == em_pch2lan) 9668 sw_cfg_mask = FEXTNVM_SW_CONFIG_ICH8M; 9669 else 9670 sw_cfg_mask = FEXTNVM_SW_CONFIG; 9671 9672 reg_data = E1000_READ_REG(hw, FEXTNVM); 9673 if (!(reg_data & sw_cfg_mask)) 9674 return E1000_SUCCESS; 9675 9676 /* Wait for basic configuration completes before proceeding */ 9677 loop = 0; 9678 do { 9679 reg_data = 9680 E1000_READ_REG(hw, STATUS) & E1000_STATUS_LAN_INIT_DONE; 9681 usec_delay(100); 9682 loop++; 9683 } while ((!reg_data) && (loop < 50)); 9684 9685 /* Clear the Init Done bit for the next init event */ 9686 reg_data = E1000_READ_REG(hw, STATUS); 9687 reg_data &= ~E1000_STATUS_LAN_INIT_DONE; 9688 E1000_WRITE_REG(hw, STATUS, reg_data); 9689 /* 9690 * Make sure HW does not configure LCD from PHY extended 9691 * configuration before SW configuration 9692 */ 9693 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL); 9694 if ((reg_data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) == 0x0000) { 9695 reg_data = E1000_READ_REG(hw, EXTCNF_SIZE); 9696 cnf_size = reg_data & E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH; 9697 cnf_size >>= 16; 9698 if (cnf_size) { 9699 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL); 9700 cnf_base_addr = reg_data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER; 9701 /* cnf_base_addr is in DWORD */ 9702 cnf_base_addr >>= 16; 9703 9704 /* Configure LCD from extended configuration region. */ 9705 ret_val = em_init_lcd_from_nvm_config_region(hw, 9706 cnf_base_addr, cnf_size); 9707 if (ret_val) 9708 return ret_val; 9709 } 9710 } 9711 return E1000_SUCCESS; 9712 } 9713 9714 /****************************************************************************** 9715 * em_set_pciex_completion_timeout - set pci-e completion timeout 9716 * 9717 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms, 9718 * however the hardware default for these parts is 500us to 1ms which is less 9719 * than the 10ms recommended by the pci-e spec. To address this we need to 9720 * increase the value to either 10ms to 200ms for capability version 1 config, 9721 * or 16ms to 55ms for version 2. 9722 * 9723 * * hw - pointer to em_hw structure 9724 *****************************************************************************/ 9725 int32_t 9726 em_set_pciex_completion_timeout(struct em_hw *hw) 9727 { 9728 uint32_t gcr = E1000_READ_REG(hw, GCR); 9729 int32_t ret_val = E1000_SUCCESS; 9730 9731 /* Only take action if timeout value is not set by system BIOS */ 9732 if (gcr & E1000_GCR_CMPL_TMOUT_MASK) 9733 goto out; 9734 9735 DEBUGOUT("PCIe completion timeout not set by system BIOS."); 9736 9737 /* 9738 * If capababilities version is type 1 we can write the 9739 * timeout of 10ms to 200ms through the GCR register 9740 */ 9741 9742 if (!(gcr & E1000_GCR_CAP_VER2)) { 9743 gcr |= E1000_GCR_CMPL_TMOUT_10ms; 9744 DEBUGOUT("PCIe capability version 1 detected, setting \ 9745 completion timeout to 10ms."); 9746 goto out; 9747 } 9748 9749 /* 9750 * For version 2 capabilities we need to write the config space 9751 * directly in order to set the completion timeout value for 9752 * 16ms to 55ms 9753 * 9754 * XXX: Implement em_*_pcie_cap_reg() first. 9755 */ 9756 #if 0 9757 ret_val = em_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 9758 &pciex_devctl2); 9759 9760 if (ret_val) 9761 goto out; 9762 9763 pciex_devctl2 |= PCIE_DEVICE_CONTROL2_16ms; 9764 9765 ret_val = em_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 9766 &pciex_devctl2); 9767 #endif 9768 9769 out: 9770 9771 /* Disable completion timeout resend */ 9772 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND; 9773 9774 DEBUGOUT("PCIe completion timeout resend disabled."); 9775 9776 E1000_WRITE_REG(hw, GCR, gcr); 9777 return ret_val; 9778 } 9779 9780 /*************************************************************************** 9781 * Set slow MDIO access mode 9782 ***************************************************************************/ 9783 static int32_t 9784 em_set_mdio_slow_mode_hv(struct em_hw *hw) 9785 { 9786 int32_t ret_val; 9787 uint16_t data; 9788 DEBUGFUNC("em_set_mdio_slow_mode_hv"); 9789 9790 ret_val = em_read_phy_reg(hw, HV_KMRN_MODE_CTRL, &data); 9791 if (ret_val) 9792 return ret_val; 9793 9794 data |= HV_KMRN_MDIO_SLOW; 9795 9796 ret_val = em_write_phy_reg(hw, HV_KMRN_MODE_CTRL, data); 9797 9798 return ret_val; 9799 } 9800 9801 /*************************************************************************** 9802 * A series of Phy workarounds to be done after every PHY reset. 9803 ***************************************************************************/ 9804 int32_t 9805 em_hv_phy_workarounds_ich8lan(struct em_hw *hw) 9806 { 9807 int32_t ret_val = E1000_SUCCESS; 9808 uint16_t phy_data; 9809 uint16_t swfw; 9810 DEBUGFUNC("em_hv_phy_workarounds_ich8lan"); 9811 9812 if (hw->mac_type != em_pchlan) 9813 goto out; 9814 9815 swfw = E1000_SWFW_PHY0_SM; 9816 9817 /* Set MDIO slow mode before any other MDIO access */ 9818 if (hw->phy_type == em_phy_82577 || 9819 hw->phy_type == em_phy_82578) { 9820 ret_val = em_set_mdio_slow_mode_hv(hw); 9821 if (ret_val) 9822 goto out; 9823 } 9824 9825 /* Hanksville M Phy init for IEEE. */ 9826 if ((hw->revision_id == 2) && 9827 (hw->phy_type == em_phy_82577) && 9828 ((hw->phy_revision == 2) || (hw->phy_revision == 3))) { 9829 em_write_phy_reg(hw, 0x10, 0x8823); 9830 em_write_phy_reg(hw, 0x11, 0x0018); 9831 em_write_phy_reg(hw, 0x10, 0x8824); 9832 em_write_phy_reg(hw, 0x11, 0x0016); 9833 em_write_phy_reg(hw, 0x10, 0x8825); 9834 em_write_phy_reg(hw, 0x11, 0x001A); 9835 em_write_phy_reg(hw, 0x10, 0x888C); 9836 em_write_phy_reg(hw, 0x11, 0x0007); 9837 em_write_phy_reg(hw, 0x10, 0x888D); 9838 em_write_phy_reg(hw, 0x11, 0x0007); 9839 em_write_phy_reg(hw, 0x10, 0x888E); 9840 em_write_phy_reg(hw, 0x11, 0x0007); 9841 em_write_phy_reg(hw, 0x10, 0x8827); 9842 em_write_phy_reg(hw, 0x11, 0x0001); 9843 em_write_phy_reg(hw, 0x10, 0x8835); 9844 em_write_phy_reg(hw, 0x11, 0x0001); 9845 em_write_phy_reg(hw, 0x10, 0x8834); 9846 em_write_phy_reg(hw, 0x11, 0x0001); 9847 em_write_phy_reg(hw, 0x10, 0x8833); 9848 em_write_phy_reg(hw, 0x11, 0x0002); 9849 } 9850 9851 if (((hw->phy_type == em_phy_82577) && 9852 ((hw->phy_revision == 1) || (hw->phy_revision == 2))) || 9853 ((hw->phy_type == em_phy_82578) && (hw->phy_revision == 1))) { 9854 /* Disable generation of early preamble */ 9855 ret_val = em_write_phy_reg(hw, PHY_REG(769, 25), 0x4431); 9856 if (ret_val) 9857 goto out; 9858 9859 /* Preamble tuning for SSC */ 9860 ret_val = em_write_phy_reg(hw, PHY_REG(770, 16), 0xA204); 9861 if (ret_val) 9862 goto out; 9863 } 9864 9865 if (hw->phy_type == em_phy_82578) { 9866 /* 9867 * Return registers to default by doing a soft reset then 9868 * writing 0x3140 to the control register. 9869 */ 9870 if (hw->phy_revision < 2) { 9871 em_phy_reset(hw); 9872 ret_val = em_write_phy_reg(hw, PHY_CTRL, 0x3140); 9873 } 9874 } 9875 9876 if ((hw->revision_id == 2) && 9877 (hw->phy_type == em_phy_82577) && 9878 ((hw->phy_revision == 2) || (hw->phy_revision == 3))) { 9879 /* 9880 * Workaround for OEM (GbE) not operating after reset - 9881 * restart AN (twice) 9882 */ 9883 ret_val = em_write_phy_reg(hw, PHY_REG(0, 25), 0x0400); 9884 if (ret_val) 9885 goto out; 9886 ret_val = em_write_phy_reg(hw, PHY_REG(0, 25), 0x0400); 9887 if (ret_val) 9888 goto out; 9889 } 9890 9891 /* Select page 0 */ 9892 ret_val = em_swfw_sync_acquire(hw, swfw); 9893 if (ret_val) 9894 goto out; 9895 9896 hw->phy_addr = 1; 9897 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT, 0); 9898 em_swfw_sync_release(hw, swfw); 9899 if (ret_val) 9900 goto out; 9901 9902 /* Workaround for link disconnects on a busy hub in half duplex */ 9903 ret_val = em_read_phy_reg(hw, 9904 PHY_REG(BM_PORT_CTRL_PAGE, 17), 9905 &phy_data); 9906 if (ret_val) 9907 goto release; 9908 ret_val = em_write_phy_reg(hw, 9909 PHY_REG(BM_PORT_CTRL_PAGE, 17), 9910 phy_data & 0x00FF); 9911 release: 9912 out: 9913 return ret_val; 9914 } 9915 9916 9917 /*************************************************************************** 9918 * Si workaround 9919 * 9920 * This function works around a Si bug where the link partner can get 9921 * a link up indication before the PHY does. If small packets are sent 9922 * by the link partner they can be placed in the packet buffer without 9923 * being properly accounted for by the PHY and will stall preventing 9924 * further packets from being received. The workaround is to clear the 9925 * packet buffer after the PHY detects link up. 9926 ***************************************************************************/ 9927 int32_t 9928 em_link_stall_workaround_hv(struct em_hw *hw) 9929 { 9930 int32_t ret_val = E1000_SUCCESS; 9931 uint16_t phy_data; 9932 9933 if (hw->phy_type != em_phy_82578) 9934 goto out; 9935 9936 /* Do not apply workaround if in PHY loopback bit 14 set */ 9937 em_read_phy_reg(hw, PHY_CTRL, &phy_data); 9938 if (phy_data & E1000_PHY_CTRL_LOOPBACK) 9939 goto out; 9940 9941 /* check if link is up and at 1Gbps */ 9942 ret_val = em_read_phy_reg(hw, BM_CS_STATUS, &phy_data); 9943 if (ret_val) 9944 goto out; 9945 9946 phy_data &= BM_CS_STATUS_LINK_UP | 9947 BM_CS_STATUS_RESOLVED | 9948 BM_CS_STATUS_SPEED_MASK; 9949 9950 if (phy_data != (BM_CS_STATUS_LINK_UP | 9951 BM_CS_STATUS_RESOLVED | 9952 BM_CS_STATUS_SPEED_1000)) 9953 goto out; 9954 9955 msec_delay(200); 9956 9957 /* flush the packets in the fifo buffer */ 9958 ret_val = em_write_phy_reg(hw, HV_MUX_DATA_CTRL, 9959 HV_MUX_DATA_CTRL_GEN_TO_MAC | HV_MUX_DATA_CTRL_FORCE_SPEED); 9960 if (ret_val) 9961 goto out; 9962 9963 ret_val = em_write_phy_reg(hw, HV_MUX_DATA_CTRL, 9964 HV_MUX_DATA_CTRL_GEN_TO_MAC); 9965 9966 out: 9967 return ret_val; 9968 } 9969 9970 /**************************************************************************** 9971 * K1 Si workaround 9972 * 9973 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning 9974 * from a lower speed. This workaround disables K1 whenever link is at 1Gig. 9975 * If link is down, the function will restore the default K1 setting located 9976 * in the NVM. 9977 ****************************************************************************/ 9978 int32_t 9979 em_k1_gig_workaround_hv(struct em_hw *hw, boolean_t link) 9980 { 9981 int32_t ret_val; 9982 uint16_t phy_data; 9983 boolean_t k1_enable; 9984 9985 DEBUGFUNC("em_k1_gig_workaround_hv"); 9986 9987 if (hw->mac_type != em_pchlan) 9988 return E1000_SUCCESS; 9989 9990 ret_val = em_read_eeprom_ich8(hw, E1000_NVM_K1_CONFIG, 1, &phy_data); 9991 if (ret_val) 9992 return ret_val; 9993 9994 k1_enable = phy_data & E1000_NVM_K1_ENABLE ? TRUE : FALSE; 9995 9996 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */ 9997 if (link) { 9998 if (hw->phy_type == em_phy_82578) { 9999 ret_val = em_read_phy_reg(hw, BM_CS_STATUS, 10000 &phy_data); 10001 if (ret_val) 10002 return ret_val; 10003 10004 phy_data &= BM_CS_STATUS_LINK_UP | 10005 BM_CS_STATUS_RESOLVED | 10006 BM_CS_STATUS_SPEED_MASK; 10007 10008 if (phy_data == (BM_CS_STATUS_LINK_UP | 10009 BM_CS_STATUS_RESOLVED | 10010 BM_CS_STATUS_SPEED_1000)) 10011 k1_enable = FALSE; 10012 } 10013 10014 if (hw->phy_type == em_phy_82577) { 10015 ret_val = em_read_phy_reg(hw, HV_M_STATUS, 10016 &phy_data); 10017 if (ret_val) 10018 return ret_val; 10019 10020 phy_data &= HV_M_STATUS_LINK_UP | 10021 HV_M_STATUS_AUTONEG_COMPLETE | 10022 HV_M_STATUS_SPEED_MASK; 10023 10024 if (phy_data == (HV_M_STATUS_LINK_UP | 10025 HV_M_STATUS_AUTONEG_COMPLETE | 10026 HV_M_STATUS_SPEED_1000)) 10027 k1_enable = FALSE; 10028 } 10029 10030 /* Link stall fix for link up */ 10031 ret_val = em_write_phy_reg(hw, PHY_REG(770, 19), 10032 0x0100); 10033 if (ret_val) 10034 return ret_val; 10035 10036 } else { 10037 /* Link stall fix for link down */ 10038 ret_val = em_write_phy_reg(hw, PHY_REG(770, 19), 10039 0x4100); 10040 if (ret_val) 10041 return ret_val; 10042 } 10043 10044 ret_val = em_configure_k1_ich8lan(hw, k1_enable); 10045 10046 return ret_val; 10047 } 10048 10049 /* Workaround to set the K1 beacon duration for 82579 parts */ 10050 int32_t 10051 em_k1_workaround_lv(struct em_hw *hw) 10052 { 10053 int32_t ret_val; 10054 uint16_t phy_data; 10055 uint32_t mac_reg; 10056 10057 ret_val = em_read_phy_reg(hw, BM_CS_STATUS, &phy_data); 10058 if (ret_val) 10059 return ret_val; 10060 10061 if ((phy_data & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) 10062 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) { 10063 mac_reg = E1000_READ_REG(hw, FEXTNVM4); 10064 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK; 10065 10066 if (phy_data & HV_M_STATUS_SPEED_1000) 10067 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC; 10068 else 10069 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC; 10070 10071 E1000_WRITE_REG(hw, FEXTNVM4, mac_reg); 10072 } 10073 10074 return E1000_SUCCESS; 10075 } 10076 10077 /*************************************************************************** 10078 * Configure K1 power state 10079 * 10080 * Configure the K1 power state based on the provided parameter. 10081 * Assumes semaphore already acquired. 10082 * 10083 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 10084 ***************************************************************************/ 10085 int32_t 10086 em_configure_k1_ich8lan(struct em_hw *hw, boolean_t k1_enable) 10087 { 10088 int32_t ret_val = E1000_SUCCESS; 10089 uint32_t ctrl_reg = 0; 10090 uint32_t ctrl_ext = 0; 10091 uint32_t reg = 0; 10092 uint16_t kmrn_reg = 0; 10093 10094 ret_val = em_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 10095 &kmrn_reg); 10096 if (ret_val) 10097 goto out; 10098 10099 if (k1_enable) 10100 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE; 10101 else 10102 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE; 10103 10104 ret_val = em_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 10105 kmrn_reg); 10106 if (ret_val) 10107 goto out; 10108 10109 usec_delay(20); 10110 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 10111 ctrl_reg = E1000_READ_REG(hw, CTRL); 10112 10113 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 10114 reg |= E1000_CTRL_FRCSPD; 10115 E1000_WRITE_REG(hw, CTRL, reg); 10116 10117 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS); 10118 usec_delay(20); 10119 E1000_WRITE_REG(hw, CTRL, ctrl_reg); 10120 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 10121 usec_delay(20); 10122 10123 out: 10124 return ret_val; 10125 } 10126