1 /******************************************************************************* 2 3 Copyright (c) 2001-2005, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 *******************************************************************************/ 33 34 /* $OpenBSD: if_em_hw.c,v 1.114 2022/01/27 18:28:44 bluhm Exp $ */ 35 /* 36 * if_em_hw.c Shared functions for accessing and configuring the MAC 37 */ 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/sockio.h> 42 #include <sys/mbuf.h> 43 #include <sys/malloc.h> 44 #include <sys/kernel.h> 45 #include <sys/device.h> 46 #include <sys/socket.h> 47 #include <sys/kstat.h> 48 49 #include <net/if.h> 50 #include <net/if_media.h> 51 52 #include <netinet/in.h> 53 #include <netinet/if_ether.h> 54 55 #include <uvm/uvm_extern.h> 56 57 #include <dev/pci/pcireg.h> 58 #include <dev/pci/pcivar.h> 59 60 #include <dev/pci/if_em.h> 61 #include <dev/pci/if_em_hw.h> 62 #include <dev/pci/if_em_soc.h> 63 64 #include <dev/mii/rgephyreg.h> 65 66 #define STATIC 67 68 static int32_t em_swfw_sync_acquire(struct em_hw *, uint16_t); 69 static void em_swfw_sync_release(struct em_hw *, uint16_t); 70 static int32_t em_read_kmrn_reg(struct em_hw *, uint32_t, uint16_t *); 71 static int32_t em_write_kmrn_reg(struct em_hw *hw, uint32_t, uint16_t); 72 static int32_t em_get_software_semaphore(struct em_hw *); 73 static void em_release_software_semaphore(struct em_hw *); 74 75 static int32_t em_check_downshift(struct em_hw *); 76 static void em_clear_vfta(struct em_hw *); 77 void em_clear_vfta_i350(struct em_hw *); 78 static int32_t em_commit_shadow_ram(struct em_hw *); 79 static int32_t em_config_dsp_after_link_change(struct em_hw *, boolean_t); 80 static int32_t em_config_fc_after_link_up(struct em_hw *); 81 static int32_t em_match_gig_phy(struct em_hw *); 82 static int32_t em_detect_gig_phy(struct em_hw *); 83 static int32_t em_erase_ich8_4k_segment(struct em_hw *, uint32_t); 84 static int32_t em_get_auto_rd_done(struct em_hw *); 85 static int32_t em_get_cable_length(struct em_hw *, uint16_t *, uint16_t *); 86 static int32_t em_get_hw_eeprom_semaphore(struct em_hw *); 87 static int32_t em_get_phy_cfg_done(struct em_hw *); 88 static int32_t em_get_software_flag(struct em_hw *); 89 static int32_t em_ich8_cycle_init(struct em_hw *); 90 static int32_t em_ich8_flash_cycle(struct em_hw *, uint32_t); 91 static int32_t em_id_led_init(struct em_hw *); 92 static int32_t em_init_lcd_from_nvm_config_region(struct em_hw *, uint32_t, 93 uint32_t); 94 static int32_t em_init_lcd_from_nvm(struct em_hw *); 95 static int32_t em_phy_no_cable_workaround(struct em_hw *); 96 static void em_init_rx_addrs(struct em_hw *); 97 static void em_initialize_hardware_bits(struct em_softc *); 98 static void em_toggle_lanphypc_pch_lpt(struct em_hw *); 99 static int em_disable_ulp_lpt_lp(struct em_hw *hw, bool force); 100 static boolean_t em_is_onboard_nvm_eeprom(struct em_hw *); 101 static int32_t em_kumeran_lock_loss_workaround(struct em_hw *); 102 static int32_t em_mng_enable_host_if(struct em_hw *); 103 static int32_t em_read_eeprom_eerd(struct em_hw *, uint16_t, uint16_t, 104 uint16_t *); 105 static int32_t em_write_eeprom_eewr(struct em_hw *, uint16_t, uint16_t, 106 uint16_t *data); 107 static int32_t em_poll_eerd_eewr_done(struct em_hw *, int); 108 static void em_put_hw_eeprom_semaphore(struct em_hw *); 109 static int32_t em_read_ich8_byte(struct em_hw *, uint32_t, uint8_t *); 110 static int32_t em_verify_write_ich8_byte(struct em_hw *, uint32_t, uint8_t); 111 static int32_t em_write_ich8_byte(struct em_hw *, uint32_t, uint8_t); 112 static int32_t em_read_ich8_word(struct em_hw *, uint32_t, uint16_t *); 113 static int32_t em_read_ich8_dword(struct em_hw *, uint32_t, uint32_t *); 114 static int32_t em_read_ich8_data(struct em_hw *, uint32_t, uint32_t, 115 uint16_t *); 116 static int32_t em_write_ich8_data(struct em_hw *, uint32_t, uint32_t, 117 uint16_t); 118 static int32_t em_read_eeprom_ich8(struct em_hw *, uint16_t, uint16_t, 119 uint16_t *); 120 static int32_t em_write_eeprom_ich8(struct em_hw *, uint16_t, uint16_t, 121 uint16_t *); 122 static int32_t em_read_invm_i210(struct em_hw *, uint16_t, uint16_t, 123 uint16_t *); 124 static int32_t em_read_invm_word_i210(struct em_hw *, uint16_t, uint16_t *); 125 static void em_release_software_flag(struct em_hw *); 126 static int32_t em_set_d3_lplu_state(struct em_hw *, boolean_t); 127 static int32_t em_set_d0_lplu_state(struct em_hw *, boolean_t); 128 static int32_t em_set_lplu_state_pchlan(struct em_hw *, boolean_t); 129 static int32_t em_set_pci_ex_no_snoop(struct em_hw *, uint32_t); 130 static void em_set_pci_express_master_disable(struct em_hw *); 131 static int32_t em_wait_autoneg(struct em_hw *); 132 static void em_write_reg_io(struct em_hw *, uint32_t, uint32_t); 133 static int32_t em_set_phy_type(struct em_hw *); 134 static void em_phy_init_script(struct em_hw *); 135 static int32_t em_setup_copper_link(struct em_hw *); 136 static int32_t em_setup_fiber_serdes_link(struct em_hw *); 137 static int32_t em_adjust_serdes_amplitude(struct em_hw *); 138 static int32_t em_phy_force_speed_duplex(struct em_hw *); 139 static int32_t em_config_mac_to_phy(struct em_hw *); 140 static void em_raise_mdi_clk(struct em_hw *, uint32_t *); 141 static void em_lower_mdi_clk(struct em_hw *, uint32_t *); 142 static void em_shift_out_mdi_bits(struct em_hw *, uint32_t, uint16_t); 143 static uint16_t em_shift_in_mdi_bits(struct em_hw *); 144 static int32_t em_phy_reset_dsp(struct em_hw *); 145 static int32_t em_write_eeprom_spi(struct em_hw *, uint16_t, uint16_t, 146 uint16_t *); 147 static int32_t em_write_eeprom_microwire(struct em_hw *, uint16_t, uint16_t, 148 uint16_t *); 149 static int32_t em_spi_eeprom_ready(struct em_hw *); 150 static void em_raise_ee_clk(struct em_hw *, uint32_t *); 151 static void em_lower_ee_clk(struct em_hw *, uint32_t *); 152 static void em_shift_out_ee_bits(struct em_hw *, uint16_t, uint16_t); 153 static int32_t em_write_phy_reg_ex(struct em_hw *, uint32_t, uint16_t); 154 static int32_t em_read_phy_reg_ex(struct em_hw *, uint32_t, uint16_t *); 155 static uint16_t em_shift_in_ee_bits(struct em_hw *, uint16_t); 156 static int32_t em_acquire_eeprom(struct em_hw *); 157 static void em_release_eeprom(struct em_hw *); 158 static void em_standby_eeprom(struct em_hw *); 159 static int32_t em_set_vco_speed(struct em_hw *); 160 static int32_t em_polarity_reversal_workaround(struct em_hw *); 161 static int32_t em_set_phy_mode(struct em_hw *); 162 static int32_t em_host_if_read_cookie(struct em_hw *, uint8_t *); 163 static uint8_t em_calculate_mng_checksum(char *, uint32_t); 164 static int32_t em_configure_kmrn_for_10_100(struct em_hw *, uint16_t); 165 static int32_t em_configure_kmrn_for_1000(struct em_hw *); 166 static int32_t em_set_pciex_completion_timeout(struct em_hw *hw); 167 static int32_t em_set_mdio_slow_mode_hv(struct em_hw *); 168 int32_t em_hv_phy_workarounds_ich8lan(struct em_hw *); 169 int32_t em_lv_phy_workarounds_ich8lan(struct em_hw *); 170 int32_t em_link_stall_workaround_hv(struct em_hw *); 171 int32_t em_k1_gig_workaround_hv(struct em_hw *, boolean_t); 172 int32_t em_k1_workaround_lv(struct em_hw *); 173 int32_t em_k1_workaround_lpt_lp(struct em_hw *, boolean_t); 174 int32_t em_configure_k1_ich8lan(struct em_hw *, boolean_t); 175 void em_gate_hw_phy_config_ich8lan(struct em_hw *, boolean_t); 176 int32_t em_access_phy_wakeup_reg_bm(struct em_hw *, uint32_t, 177 uint16_t *, boolean_t); 178 int32_t em_access_phy_debug_regs_hv(struct em_hw *, uint32_t, 179 uint16_t *, boolean_t); 180 int32_t em_access_phy_reg_hv(struct em_hw *, uint32_t, uint16_t *, 181 boolean_t); 182 int32_t em_oem_bits_config_pchlan(struct em_hw *, boolean_t); 183 void em_power_up_serdes_link_82575(struct em_hw *); 184 int32_t em_get_pcs_speed_and_duplex_82575(struct em_hw *, uint16_t *, 185 uint16_t *); 186 int32_t em_set_eee_i350(struct em_hw *); 187 int32_t em_set_eee_pchlan(struct em_hw *); 188 int32_t em_valid_nvm_bank_detect_ich8lan(struct em_hw *, uint32_t *); 189 int32_t em_initialize_M88E1512_phy(struct em_hw *); 190 191 /* IGP cable length table */ 192 static const uint16_t 193 em_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = 194 {5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 195 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25, 196 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40, 197 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60, 198 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90, 199 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 200 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 201 110, 202 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 203 120}; 204 205 static const uint16_t 206 em_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] = 207 {0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 208 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 209 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 210 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 211 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 212 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 213 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 214 121, 124}; 215 216 /****************************************************************************** 217 * Set the phy type member in the hw struct. 218 * 219 * hw - Struct containing variables accessed by shared code 220 *****************************************************************************/ 221 STATIC int32_t 222 em_set_phy_type(struct em_hw *hw) 223 { 224 DEBUGFUNC("em_set_phy_type"); 225 226 if (hw->mac_type == em_undefined) 227 return -E1000_ERR_PHY_TYPE; 228 229 switch (hw->phy_id) { 230 case M88E1000_E_PHY_ID: 231 case M88E1000_I_PHY_ID: 232 case M88E1011_I_PHY_ID: 233 case M88E1111_I_PHY_ID: 234 case M88E1112_E_PHY_ID: 235 case M88E1543_E_PHY_ID: 236 case M88E1512_E_PHY_ID: 237 case I210_I_PHY_ID: 238 case I347AT4_E_PHY_ID: 239 hw->phy_type = em_phy_m88; 240 break; 241 case IGP01E1000_I_PHY_ID: 242 if (hw->mac_type == em_82541 || 243 hw->mac_type == em_82541_rev_2 || 244 hw->mac_type == em_82547 || 245 hw->mac_type == em_82547_rev_2) { 246 hw->phy_type = em_phy_igp; 247 break; 248 } 249 case IGP03E1000_E_PHY_ID: 250 case IGP04E1000_E_PHY_ID: 251 hw->phy_type = em_phy_igp_3; 252 break; 253 case IFE_E_PHY_ID: 254 case IFE_PLUS_E_PHY_ID: 255 case IFE_C_E_PHY_ID: 256 hw->phy_type = em_phy_ife; 257 break; 258 case M88E1141_E_PHY_ID: 259 hw->phy_type = em_phy_oem; 260 break; 261 case I82577_E_PHY_ID: 262 hw->phy_type = em_phy_82577; 263 break; 264 case I82578_E_PHY_ID: 265 hw->phy_type = em_phy_82578; 266 break; 267 case I82579_E_PHY_ID: 268 hw->phy_type = em_phy_82579; 269 break; 270 case I217_E_PHY_ID: 271 hw->phy_type = em_phy_i217; 272 break; 273 case I82580_I_PHY_ID: 274 case I350_I_PHY_ID: 275 hw->phy_type = em_phy_82580; 276 break; 277 case RTL8211_E_PHY_ID: 278 hw->phy_type = em_phy_rtl8211; 279 break; 280 case BME1000_E_PHY_ID: 281 if (hw->phy_revision == 1) { 282 hw->phy_type = em_phy_bm; 283 break; 284 } 285 /* FALLTHROUGH */ 286 case GG82563_E_PHY_ID: 287 if (hw->mac_type == em_80003es2lan) { 288 hw->phy_type = em_phy_gg82563; 289 break; 290 } 291 /* FALLTHROUGH */ 292 default: 293 /* Should never have loaded on this device */ 294 hw->phy_type = em_phy_undefined; 295 return -E1000_ERR_PHY_TYPE; 296 } 297 298 return E1000_SUCCESS; 299 } 300 301 /****************************************************************************** 302 * IGP phy init script - initializes the GbE PHY 303 * 304 * hw - Struct containing variables accessed by shared code 305 *****************************************************************************/ 306 static void 307 em_phy_init_script(struct em_hw *hw) 308 { 309 uint16_t phy_saved_data; 310 DEBUGFUNC("em_phy_init_script"); 311 312 if (hw->phy_init_script) { 313 msec_delay(20); 314 /* 315 * Save off the current value of register 0x2F5B to be 316 * restored at the end of this routine. 317 */ 318 em_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 319 320 /* Disabled the PHY transmitter */ 321 em_write_phy_reg(hw, 0x2F5B, 0x0003); 322 msec_delay(20); 323 em_write_phy_reg(hw, 0x0000, 0x0140); 324 msec_delay(5); 325 326 switch (hw->mac_type) { 327 case em_82541: 328 case em_82547: 329 em_write_phy_reg(hw, 0x1F95, 0x0001); 330 em_write_phy_reg(hw, 0x1F71, 0xBD21); 331 em_write_phy_reg(hw, 0x1F79, 0x0018); 332 em_write_phy_reg(hw, 0x1F30, 0x1600); 333 em_write_phy_reg(hw, 0x1F31, 0x0014); 334 em_write_phy_reg(hw, 0x1F32, 0x161C); 335 em_write_phy_reg(hw, 0x1F94, 0x0003); 336 em_write_phy_reg(hw, 0x1F96, 0x003F); 337 em_write_phy_reg(hw, 0x2010, 0x0008); 338 break; 339 case em_82541_rev_2: 340 case em_82547_rev_2: 341 em_write_phy_reg(hw, 0x1F73, 0x0099); 342 break; 343 default: 344 break; 345 } 346 347 em_write_phy_reg(hw, 0x0000, 0x3300); 348 msec_delay(20); 349 350 /* Now enable the transmitter */ 351 em_write_phy_reg(hw, 0x2F5B, phy_saved_data); 352 353 if (hw->mac_type == em_82547) { 354 uint16_t fused, fine, coarse; 355 /* Move to analog registers page */ 356 em_read_phy_reg(hw, 357 IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused); 358 359 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { 360 em_read_phy_reg(hw, 361 IGP01E1000_ANALOG_FUSE_STATUS, &fused); 362 363 fine = fused & 364 IGP01E1000_ANALOG_FUSE_FINE_MASK; 365 coarse = fused & 366 IGP01E1000_ANALOG_FUSE_COARSE_MASK; 367 368 if (coarse > 369 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { 370 coarse -= 371 IGP01E1000_ANALOG_FUSE_COARSE_10; 372 fine -= 373 IGP01E1000_ANALOG_FUSE_FINE_1; 374 } else if (coarse == 375 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) 376 fine -= IGP01E1000_ANALOG_FUSE_FINE_10; 377 378 fused = (fused & 379 IGP01E1000_ANALOG_FUSE_POLY_MASK) | 380 (fine & 381 IGP01E1000_ANALOG_FUSE_FINE_MASK) | 382 (coarse & 383 IGP01E1000_ANALOG_FUSE_COARSE_MASK); 384 385 em_write_phy_reg(hw, 386 IGP01E1000_ANALOG_FUSE_CONTROL, 387 fused); 388 389 em_write_phy_reg(hw, 390 IGP01E1000_ANALOG_FUSE_BYPASS, 391 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL); 392 } 393 } 394 } 395 } 396 397 /****************************************************************************** 398 * Set the mac type member in the hw struct. 399 * 400 * hw - Struct containing variables accessed by shared code 401 *****************************************************************************/ 402 int32_t 403 em_set_mac_type(struct em_hw *hw) 404 { 405 DEBUGFUNC("em_set_mac_type"); 406 407 switch (hw->device_id) { 408 case E1000_DEV_ID_82542: 409 switch (hw->revision_id) { 410 case E1000_82542_2_0_REV_ID: 411 hw->mac_type = em_82542_rev2_0; 412 break; 413 case E1000_82542_2_1_REV_ID: 414 hw->mac_type = em_82542_rev2_1; 415 break; 416 default: 417 /* Invalid 82542 revision ID */ 418 return -E1000_ERR_MAC_TYPE; 419 } 420 break; 421 case E1000_DEV_ID_82543GC_FIBER: 422 case E1000_DEV_ID_82543GC_COPPER: 423 hw->mac_type = em_82543; 424 break; 425 case E1000_DEV_ID_82544EI_COPPER: 426 case E1000_DEV_ID_82544EI_FIBER: 427 case E1000_DEV_ID_82544GC_COPPER: 428 case E1000_DEV_ID_82544GC_LOM: 429 hw->mac_type = em_82544; 430 break; 431 case E1000_DEV_ID_82540EM: 432 case E1000_DEV_ID_82540EM_LOM: 433 case E1000_DEV_ID_82540EP: 434 case E1000_DEV_ID_82540EP_LOM: 435 case E1000_DEV_ID_82540EP_LP: 436 hw->mac_type = em_82540; 437 break; 438 case E1000_DEV_ID_82545EM_COPPER: 439 case E1000_DEV_ID_82545EM_FIBER: 440 hw->mac_type = em_82545; 441 break; 442 case E1000_DEV_ID_82545GM_COPPER: 443 case E1000_DEV_ID_82545GM_FIBER: 444 case E1000_DEV_ID_82545GM_SERDES: 445 hw->mac_type = em_82545_rev_3; 446 break; 447 case E1000_DEV_ID_82546EB_COPPER: 448 case E1000_DEV_ID_82546EB_FIBER: 449 case E1000_DEV_ID_82546EB_QUAD_COPPER: 450 hw->mac_type = em_82546; 451 break; 452 case E1000_DEV_ID_82546GB_COPPER: 453 case E1000_DEV_ID_82546GB_FIBER: 454 case E1000_DEV_ID_82546GB_SERDES: 455 case E1000_DEV_ID_82546GB_PCIE: 456 case E1000_DEV_ID_82546GB_QUAD_COPPER: 457 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 458 case E1000_DEV_ID_82546GB_2: 459 hw->mac_type = em_82546_rev_3; 460 break; 461 case E1000_DEV_ID_82541EI: 462 case E1000_DEV_ID_82541EI_MOBILE: 463 case E1000_DEV_ID_82541ER_LOM: 464 hw->mac_type = em_82541; 465 break; 466 case E1000_DEV_ID_82541ER: 467 case E1000_DEV_ID_82541GI: 468 case E1000_DEV_ID_82541GI_LF: 469 case E1000_DEV_ID_82541GI_MOBILE: 470 hw->mac_type = em_82541_rev_2; 471 break; 472 case E1000_DEV_ID_82547EI: 473 case E1000_DEV_ID_82547EI_MOBILE: 474 hw->mac_type = em_82547; 475 break; 476 case E1000_DEV_ID_82547GI: 477 hw->mac_type = em_82547_rev_2; 478 break; 479 case E1000_DEV_ID_82571EB_AF: 480 case E1000_DEV_ID_82571EB_AT: 481 case E1000_DEV_ID_82571EB_COPPER: 482 case E1000_DEV_ID_82571EB_FIBER: 483 case E1000_DEV_ID_82571EB_SERDES: 484 case E1000_DEV_ID_82571EB_QUAD_COPPER: 485 case E1000_DEV_ID_82571EB_QUAD_FIBER: 486 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 487 case E1000_DEV_ID_82571EB_SERDES_DUAL: 488 case E1000_DEV_ID_82571EB_SERDES_QUAD: 489 case E1000_DEV_ID_82571PT_QUAD_COPPER: 490 hw->mac_type = em_82571; 491 break; 492 case E1000_DEV_ID_82572EI_COPPER: 493 case E1000_DEV_ID_82572EI_FIBER: 494 case E1000_DEV_ID_82572EI_SERDES: 495 case E1000_DEV_ID_82572EI: 496 hw->mac_type = em_82572; 497 break; 498 case E1000_DEV_ID_82573E: 499 case E1000_DEV_ID_82573E_IAMT: 500 case E1000_DEV_ID_82573E_PM: 501 case E1000_DEV_ID_82573L: 502 case E1000_DEV_ID_82573L_PL_1: 503 case E1000_DEV_ID_82573L_PL_2: 504 case E1000_DEV_ID_82573V_PM: 505 hw->mac_type = em_82573; 506 break; 507 case E1000_DEV_ID_82574L: 508 case E1000_DEV_ID_82574LA: 509 case E1000_DEV_ID_82583V: 510 hw->mac_type = em_82574; 511 break; 512 case E1000_DEV_ID_82575EB_PT: 513 case E1000_DEV_ID_82575EB_PF: 514 case E1000_DEV_ID_82575GB_QP: 515 case E1000_DEV_ID_82575GB_QP_PM: 516 hw->mac_type = em_82575; 517 hw->initialize_hw_bits_disable = 1; 518 break; 519 case E1000_DEV_ID_82576: 520 case E1000_DEV_ID_82576_FIBER: 521 case E1000_DEV_ID_82576_SERDES: 522 case E1000_DEV_ID_82576_QUAD_COPPER: 523 case E1000_DEV_ID_82576_QUAD_CU_ET2: 524 case E1000_DEV_ID_82576_NS: 525 case E1000_DEV_ID_82576_NS_SERDES: 526 case E1000_DEV_ID_82576_SERDES_QUAD: 527 hw->mac_type = em_82576; 528 hw->initialize_hw_bits_disable = 1; 529 break; 530 case E1000_DEV_ID_82580_COPPER: 531 case E1000_DEV_ID_82580_FIBER: 532 case E1000_DEV_ID_82580_QUAD_FIBER: 533 case E1000_DEV_ID_82580_SERDES: 534 case E1000_DEV_ID_82580_SGMII: 535 case E1000_DEV_ID_82580_COPPER_DUAL: 536 case E1000_DEV_ID_DH89XXCC_SGMII: 537 case E1000_DEV_ID_DH89XXCC_SERDES: 538 case E1000_DEV_ID_DH89XXCC_BACKPLANE: 539 case E1000_DEV_ID_DH89XXCC_SFP: 540 hw->mac_type = em_82580; 541 hw->initialize_hw_bits_disable = 1; 542 break; 543 case E1000_DEV_ID_I210_COPPER: 544 case E1000_DEV_ID_I210_COPPER_OEM1: 545 case E1000_DEV_ID_I210_COPPER_IT: 546 case E1000_DEV_ID_I210_FIBER: 547 case E1000_DEV_ID_I210_SERDES: 548 case E1000_DEV_ID_I210_SGMII: 549 case E1000_DEV_ID_I210_COPPER_FLASHLESS: 550 case E1000_DEV_ID_I210_SERDES_FLASHLESS: 551 case E1000_DEV_ID_I211_COPPER: 552 hw->mac_type = em_i210; 553 hw->initialize_hw_bits_disable = 1; 554 hw->eee_enable = 1; 555 break; 556 case E1000_DEV_ID_I350_COPPER: 557 case E1000_DEV_ID_I350_FIBER: 558 case E1000_DEV_ID_I350_SERDES: 559 case E1000_DEV_ID_I350_SGMII: 560 case E1000_DEV_ID_I350_DA4: 561 case E1000_DEV_ID_I354_BACKPLANE_1GBPS: 562 case E1000_DEV_ID_I354_SGMII: 563 case E1000_DEV_ID_I354_BACKPLANE_2_5GBPS: 564 hw->mac_type = em_i350; 565 hw->initialize_hw_bits_disable = 1; 566 hw->eee_enable = 1; 567 break; 568 case E1000_DEV_ID_80003ES2LAN_COPPER_SPT: 569 case E1000_DEV_ID_80003ES2LAN_SERDES_SPT: 570 case E1000_DEV_ID_80003ES2LAN_COPPER_DPT: 571 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: 572 hw->mac_type = em_80003es2lan; 573 break; 574 case E1000_DEV_ID_ICH8_IFE: 575 case E1000_DEV_ID_ICH8_IFE_G: 576 case E1000_DEV_ID_ICH8_IFE_GT: 577 case E1000_DEV_ID_ICH8_IGP_AMT: 578 case E1000_DEV_ID_ICH8_IGP_C: 579 case E1000_DEV_ID_ICH8_IGP_M: 580 case E1000_DEV_ID_ICH8_IGP_M_AMT: 581 case E1000_DEV_ID_ICH8_82567V_3: 582 hw->mac_type = em_ich8lan; 583 break; 584 case E1000_DEV_ID_ICH9_BM: 585 case E1000_DEV_ID_ICH9_IFE: 586 case E1000_DEV_ID_ICH9_IFE_G: 587 case E1000_DEV_ID_ICH9_IFE_GT: 588 case E1000_DEV_ID_ICH9_IGP_AMT: 589 case E1000_DEV_ID_ICH9_IGP_C: 590 case E1000_DEV_ID_ICH9_IGP_M: 591 case E1000_DEV_ID_ICH9_IGP_M_AMT: 592 case E1000_DEV_ID_ICH9_IGP_M_V: 593 case E1000_DEV_ID_ICH10_R_BM_LF: 594 case E1000_DEV_ID_ICH10_R_BM_LM: 595 case E1000_DEV_ID_ICH10_R_BM_V: 596 hw->mac_type = em_ich9lan; 597 break; 598 case E1000_DEV_ID_ICH10_D_BM_LF: 599 case E1000_DEV_ID_ICH10_D_BM_LM: 600 case E1000_DEV_ID_ICH10_D_BM_V: 601 hw->mac_type = em_ich10lan; 602 break; 603 case E1000_DEV_ID_PCH_M_HV_LC: 604 case E1000_DEV_ID_PCH_M_HV_LM: 605 case E1000_DEV_ID_PCH_D_HV_DC: 606 case E1000_DEV_ID_PCH_D_HV_DM: 607 hw->mac_type = em_pchlan; 608 hw->eee_enable = 1; 609 break; 610 case E1000_DEV_ID_PCH2_LV_LM: 611 case E1000_DEV_ID_PCH2_LV_V: 612 hw->mac_type = em_pch2lan; 613 break; 614 case E1000_DEV_ID_PCH_LPT_I217_LM: 615 case E1000_DEV_ID_PCH_LPT_I217_V: 616 case E1000_DEV_ID_PCH_LPTLP_I218_LM: 617 case E1000_DEV_ID_PCH_LPTLP_I218_V: 618 case E1000_DEV_ID_PCH_I218_LM2: 619 case E1000_DEV_ID_PCH_I218_V2: 620 case E1000_DEV_ID_PCH_I218_LM3: 621 case E1000_DEV_ID_PCH_I218_V3: 622 hw->mac_type = em_pch_lpt; 623 break; 624 case E1000_DEV_ID_PCH_SPT_I219_LM: 625 case E1000_DEV_ID_PCH_SPT_I219_V: 626 case E1000_DEV_ID_PCH_SPT_I219_LM2: 627 case E1000_DEV_ID_PCH_SPT_I219_V2: 628 case E1000_DEV_ID_PCH_LBG_I219_LM3: 629 case E1000_DEV_ID_PCH_SPT_I219_LM4: 630 case E1000_DEV_ID_PCH_SPT_I219_V4: 631 case E1000_DEV_ID_PCH_SPT_I219_LM5: 632 case E1000_DEV_ID_PCH_SPT_I219_V5: 633 case E1000_DEV_ID_PCH_CMP_I219_LM12: 634 case E1000_DEV_ID_PCH_CMP_I219_V12: 635 hw->mac_type = em_pch_spt; 636 break; 637 case E1000_DEV_ID_PCH_CNP_I219_LM6: 638 case E1000_DEV_ID_PCH_CNP_I219_V6: 639 case E1000_DEV_ID_PCH_CNP_I219_LM7: 640 case E1000_DEV_ID_PCH_CNP_I219_V7: 641 case E1000_DEV_ID_PCH_ICP_I219_LM8: 642 case E1000_DEV_ID_PCH_ICP_I219_V8: 643 case E1000_DEV_ID_PCH_ICP_I219_LM9: 644 case E1000_DEV_ID_PCH_ICP_I219_V9: 645 case E1000_DEV_ID_PCH_CMP_I219_LM10: 646 case E1000_DEV_ID_PCH_CMP_I219_V10: 647 case E1000_DEV_ID_PCH_CMP_I219_LM11: 648 case E1000_DEV_ID_PCH_CMP_I219_V11: 649 case E1000_DEV_ID_PCH_TGP_I219_LM13: 650 case E1000_DEV_ID_PCH_TGP_I219_V13: 651 case E1000_DEV_ID_PCH_TGP_I219_LM14: 652 case E1000_DEV_ID_PCH_TGP_I219_V14: 653 case E1000_DEV_ID_PCH_TGP_I219_LM15: 654 case E1000_DEV_ID_PCH_TGP_I219_V15: 655 case E1000_DEV_ID_PCH_ADP_I219_LM16: 656 case E1000_DEV_ID_PCH_ADP_I219_V16: 657 case E1000_DEV_ID_PCH_ADP_I219_LM17: 658 case E1000_DEV_ID_PCH_ADP_I219_V17: 659 case E1000_DEV_ID_PCH_MTP_I219_LM18: 660 case E1000_DEV_ID_PCH_MTP_I219_V18: 661 case E1000_DEV_ID_PCH_MTP_I219_LM19: 662 case E1000_DEV_ID_PCH_MTP_I219_V19: 663 hw->mac_type = em_pch_cnp; 664 break; 665 case E1000_DEV_ID_EP80579_LAN_1: 666 hw->mac_type = em_icp_xxxx; 667 hw->icp_xxxx_port_num = 0; 668 break; 669 case E1000_DEV_ID_EP80579_LAN_2: 670 case E1000_DEV_ID_EP80579_LAN_4: 671 hw->mac_type = em_icp_xxxx; 672 hw->icp_xxxx_port_num = 1; 673 break; 674 case E1000_DEV_ID_EP80579_LAN_3: 675 case E1000_DEV_ID_EP80579_LAN_5: 676 hw->mac_type = em_icp_xxxx; 677 hw->icp_xxxx_port_num = 2; 678 break; 679 case E1000_DEV_ID_EP80579_LAN_6: 680 hw->mac_type = em_icp_xxxx; 681 hw->icp_xxxx_port_num = 3; 682 break; 683 default: 684 /* Should never have loaded on this device */ 685 return -E1000_ERR_MAC_TYPE; 686 } 687 688 switch (hw->mac_type) { 689 case em_ich8lan: 690 case em_ich9lan: 691 case em_ich10lan: 692 case em_pchlan: 693 case em_pch2lan: 694 case em_pch_lpt: 695 case em_pch_spt: 696 case em_pch_cnp: 697 hw->swfwhw_semaphore_present = TRUE; 698 hw->asf_firmware_present = TRUE; 699 break; 700 case em_80003es2lan: 701 case em_82575: 702 case em_82576: 703 case em_82580: 704 case em_i210: 705 case em_i350: 706 hw->swfw_sync_present = TRUE; 707 /* FALLTHROUGH */ 708 case em_82571: 709 case em_82572: 710 case em_82573: 711 case em_82574: 712 hw->eeprom_semaphore_present = TRUE; 713 /* FALLTHROUGH */ 714 case em_82541: 715 case em_82547: 716 case em_82541_rev_2: 717 case em_82547_rev_2: 718 hw->asf_firmware_present = TRUE; 719 break; 720 default: 721 break; 722 } 723 724 return E1000_SUCCESS; 725 } 726 727 /** 728 * em_set_sfp_media_type_82575 - derives SFP module media type. 729 * @hw: pointer to the HW structure 730 * 731 * The media type is chosen based on SFP module. 732 * compatibility flags retrieved from SFP ID EEPROM. 733 **/ 734 STATIC int32_t em_set_sfp_media_type_82575(struct em_hw *hw) 735 { 736 struct sfp_e1000_flags eth_flags; 737 int32_t ret_val = E1000_ERR_CONFIG; 738 uint32_t ctrl_ext = 0; 739 uint8_t transceiver_type = 0; 740 int32_t timeout = 3; 741 742 /* Turn I2C interface ON and power on sfp cage */ 743 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 744 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA; 745 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA); 746 747 E1000_WRITE_FLUSH(hw); 748 749 /* Read SFP module data */ 750 while (timeout) { 751 ret_val = em_read_sfp_data_byte(hw, 752 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET), 753 &transceiver_type); 754 if (ret_val == E1000_SUCCESS) 755 break; 756 msec_delay(100); 757 timeout--; 758 } 759 if (ret_val != E1000_SUCCESS) 760 goto out; 761 762 ret_val = em_read_sfp_data_byte(hw, 763 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET), 764 (uint8_t *)ð_flags); 765 if (ret_val != E1000_SUCCESS) 766 goto out; 767 768 /* Check if there is some SFP module plugged and powered */ 769 if ((transceiver_type == E1000_SFF_IDENTIFIER_SFP) || 770 (transceiver_type == E1000_SFF_IDENTIFIER_SFF)) { 771 if (eth_flags.e1000_base_lx || eth_flags.e1000_base_sx) { 772 hw->media_type = em_media_type_internal_serdes; 773 } else if (eth_flags.e100_base_fx || eth_flags.e100_base_lx) { 774 hw->media_type = em_media_type_internal_serdes; 775 hw->sgmii_active = TRUE; 776 } else if (eth_flags.e1000_base_t) { 777 hw->media_type = em_media_type_copper; 778 hw->sgmii_active = TRUE; 779 } else { 780 DEBUGOUT("PHY module has not been recognized\n"); 781 ret_val = E1000_ERR_CONFIG; 782 goto out; 783 } 784 } else { 785 ret_val = E1000_ERR_CONFIG; 786 goto out; 787 } 788 ret_val = E1000_SUCCESS; 789 out: 790 /* Restore I2C interface setting */ 791 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 792 return ret_val; 793 } 794 795 796 /***************************************************************************** 797 * Set media type and TBI compatibility. 798 * 799 * hw - Struct containing variables accessed by shared code 800 * **************************************************************************/ 801 void 802 em_set_media_type(struct em_hw *hw) 803 { 804 uint32_t status, ctrl_ext, mdic; 805 DEBUGFUNC("em_set_media_type"); 806 807 if (hw->mac_type != em_82543) { 808 /* tbi_compatibility is only valid on 82543 */ 809 hw->tbi_compatibility_en = FALSE; 810 } 811 812 if (hw->mac_type == em_82575 || hw->mac_type == em_82580 || 813 hw->mac_type == em_82576 || 814 hw->mac_type == em_i210 || hw->mac_type == em_i350) { 815 hw->media_type = em_media_type_copper; 816 hw->sgmii_active = FALSE; 817 818 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 819 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) { 820 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: 821 hw->media_type = em_media_type_internal_serdes; 822 ctrl_ext |= E1000_CTRL_I2C_ENA; 823 break; 824 case E1000_CTRL_EXT_LINK_MODE_SGMII: 825 mdic = EM_READ_REG(hw, E1000_MDICNFG); 826 ctrl_ext |= E1000_CTRL_I2C_ENA; 827 if (mdic & E1000_MDICNFG_EXT_MDIO) { 828 hw->media_type = em_media_type_copper; 829 hw->sgmii_active = TRUE; 830 break; 831 } 832 /* FALLTHROUGH */ 833 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES: 834 ctrl_ext |= E1000_CTRL_I2C_ENA; 835 if (em_set_sfp_media_type_82575(hw) != 0) { 836 hw->media_type = em_media_type_internal_serdes; 837 if ((ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) == 838 E1000_CTRL_EXT_LINK_MODE_SGMII) { 839 hw->media_type = em_media_type_copper; 840 hw->sgmii_active = TRUE; 841 } 842 } 843 844 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK; 845 if (hw->sgmii_active) 846 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII; 847 else 848 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 849 break; 850 default: 851 ctrl_ext &= ~E1000_CTRL_I2C_ENA; 852 break; 853 } 854 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 855 return; 856 } 857 858 switch (hw->device_id) { 859 case E1000_DEV_ID_82545GM_SERDES: 860 case E1000_DEV_ID_82546GB_SERDES: 861 case E1000_DEV_ID_82571EB_SERDES: 862 case E1000_DEV_ID_82571EB_SERDES_DUAL: 863 case E1000_DEV_ID_82571EB_SERDES_QUAD: 864 case E1000_DEV_ID_82572EI_SERDES: 865 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: 866 hw->media_type = em_media_type_internal_serdes; 867 break; 868 case E1000_DEV_ID_EP80579_LAN_1: 869 case E1000_DEV_ID_EP80579_LAN_2: 870 case E1000_DEV_ID_EP80579_LAN_3: 871 case E1000_DEV_ID_EP80579_LAN_4: 872 case E1000_DEV_ID_EP80579_LAN_5: 873 case E1000_DEV_ID_EP80579_LAN_6: 874 hw->media_type = em_media_type_copper; 875 break; 876 default: 877 switch (hw->mac_type) { 878 case em_82542_rev2_0: 879 case em_82542_rev2_1: 880 hw->media_type = em_media_type_fiber; 881 break; 882 case em_ich8lan: 883 case em_ich9lan: 884 case em_ich10lan: 885 case em_pchlan: 886 case em_pch2lan: 887 case em_pch_lpt: 888 case em_pch_spt: 889 case em_pch_cnp: 890 case em_82573: 891 case em_82574: 892 /* 893 * The STATUS_TBIMODE bit is reserved or reused for 894 * the this device. 895 */ 896 hw->media_type = em_media_type_copper; 897 break; 898 default: 899 status = E1000_READ_REG(hw, STATUS); 900 if (status & E1000_STATUS_TBIMODE) { 901 hw->media_type = em_media_type_fiber; 902 /* tbi_compatibility not valid on fiber */ 903 hw->tbi_compatibility_en = FALSE; 904 } else { 905 hw->media_type = em_media_type_copper; 906 } 907 break; 908 } 909 } 910 } 911 /****************************************************************************** 912 * Reset the transmit and receive units; mask and clear all interrupts. 913 * 914 * hw - Struct containing variables accessed by shared code 915 *****************************************************************************/ 916 int32_t 917 em_reset_hw(struct em_hw *hw) 918 { 919 uint32_t ctrl; 920 uint32_t ctrl_ext; 921 uint32_t icr; 922 uint32_t manc; 923 uint32_t led_ctrl; 924 uint32_t timeout; 925 uint32_t extcnf_ctrl; 926 int32_t ret_val; 927 DEBUGFUNC("em_reset_hw"); 928 929 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ 930 if (hw->mac_type == em_82542_rev2_0) { 931 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 932 em_pci_clear_mwi(hw); 933 } 934 if (hw->bus_type == em_bus_type_pci_express) { 935 /* 936 * Prevent the PCI-E bus from sticking if there is no TLP 937 * connection on the last TLP read/write transaction when MAC 938 * is reset. 939 */ 940 if (em_disable_pciex_master(hw) != E1000_SUCCESS) { 941 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 942 } 943 } 944 945 /* Set the completion timeout for 82575 chips */ 946 if (hw->mac_type == em_82575 || hw->mac_type == em_82580 || 947 hw->mac_type == em_82576 || 948 hw->mac_type == em_i210 || hw->mac_type == em_i350) { 949 ret_val = em_set_pciex_completion_timeout(hw); 950 if (ret_val) { 951 DEBUGOUT("PCI-E Set completion timeout has failed.\n"); 952 } 953 } 954 955 /* Clear interrupt mask to stop board from generating interrupts */ 956 DEBUGOUT("Masking off all interrupts\n"); 957 E1000_WRITE_REG(hw, IMC, 0xffffffff); 958 /* 959 * Disable the Transmit and Receive units. Then delay to allow any 960 * pending transactions to complete before we hit the MAC with the 961 * global reset. 962 */ 963 E1000_WRITE_REG(hw, RCTL, 0); 964 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP); 965 E1000_WRITE_FLUSH(hw); 966 /* 967 * The tbi_compatibility_on Flag must be cleared when Rctl is 968 * cleared. 969 */ 970 hw->tbi_compatibility_on = FALSE; 971 /* 972 * Delay to allow any outstanding PCI transactions to complete before 973 * resetting the device 974 */ 975 msec_delay(10); 976 977 ctrl = E1000_READ_REG(hw, CTRL); 978 979 /* Must reset the PHY before resetting the MAC */ 980 if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) { 981 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST)); 982 msec_delay(5); 983 } 984 /* 985 * Must acquire the MDIO ownership before MAC reset. Ownership 986 * defaults to firmware after a reset. 987 */ 988 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) { 989 timeout = 10; 990 991 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 992 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 993 994 do { 995 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); 996 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 997 998 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) 999 break; 1000 else 1001 extcnf_ctrl |= 1002 E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 1003 1004 msec_delay(2); 1005 timeout--; 1006 } while (timeout); 1007 } 1008 /* Workaround for ICH8 bit corruption issue in FIFO memory */ 1009 if (hw->mac_type == em_ich8lan) { 1010 /* Set Tx and Rx buffer allocation to 8k apiece. */ 1011 E1000_WRITE_REG(hw, PBA, E1000_PBA_8K); 1012 /* Set Packet Buffer Size to 16k. */ 1013 E1000_WRITE_REG(hw, PBS, E1000_PBS_16K); 1014 } 1015 /* 1016 * Issue a global reset to the MAC. This will reset the chip's 1017 * transmit, receive, DMA, and link units. It will not effect the 1018 * current PCI configuration. The global reset bit is self- 1019 * clearing, and should clear within a microsecond. 1020 */ 1021 DEBUGOUT("Issuing a global reset to MAC\n"); 1022 1023 switch (hw->mac_type) { 1024 case em_82544: 1025 case em_82540: 1026 case em_82545: 1027 case em_82546: 1028 case em_82541: 1029 case em_82541_rev_2: 1030 /* 1031 * These controllers can't ack the 64-bit write when issuing 1032 * the reset, so use IO-mapping as a workaround to issue the 1033 * reset 1034 */ 1035 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST)); 1036 break; 1037 case em_82545_rev_3: 1038 case em_82546_rev_3: 1039 /* Reset is performed on a shadow of the control register */ 1040 E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST)); 1041 break; 1042 case em_ich8lan: 1043 case em_ich9lan: 1044 case em_ich10lan: 1045 case em_pchlan: 1046 case em_pch2lan: 1047 case em_pch_lpt: 1048 case em_pch_spt: 1049 case em_pch_cnp: 1050 if (!hw->phy_reset_disable && 1051 em_check_phy_reset_block(hw) == E1000_SUCCESS) { 1052 /* 1053 * PHY HW reset requires MAC CORE reset at the same 1054 * time to make sure the interface between MAC and 1055 * the external PHY is reset. 1056 */ 1057 ctrl |= E1000_CTRL_PHY_RST; 1058 /* 1059 * Gate automatic PHY configuration by hardware on 1060 * non-managed 82579 1061 */ 1062 if ((hw->mac_type == em_pch2lan) && 1063 !(E1000_READ_REG(hw, FWSM) & E1000_FWSM_FW_VALID)) { 1064 em_gate_hw_phy_config_ich8lan(hw, TRUE); 1065 } 1066 } 1067 em_get_software_flag(hw); 1068 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); 1069 /* HW reset releases software_flag */ 1070 hw->sw_flag = 0; 1071 msec_delay(20); 1072 1073 /* Ungate automatic PHY configuration on non-managed 82579 */ 1074 if (hw->mac_type == em_pch2lan && !hw->phy_reset_disable && 1075 !(E1000_READ_REG(hw, FWSM) & E1000_FWSM_FW_VALID)) { 1076 msec_delay(10); 1077 em_gate_hw_phy_config_ich8lan(hw, FALSE); 1078 } 1079 break; 1080 default: 1081 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); 1082 break; 1083 } 1084 1085 if (em_check_phy_reset_block(hw) == E1000_SUCCESS) { 1086 if (hw->mac_type == em_pchlan) { 1087 ret_val = em_hv_phy_workarounds_ich8lan(hw); 1088 if (ret_val) 1089 return ret_val; 1090 } 1091 else if (hw->mac_type == em_pch2lan) { 1092 ret_val = em_lv_phy_workarounds_ich8lan(hw); 1093 if (ret_val) 1094 return ret_val; 1095 } 1096 } 1097 1098 /* 1099 * After MAC reset, force reload of EEPROM to restore power-on 1100 * settings to device. Later controllers reload the EEPROM 1101 * automatically, so just wait for reload to complete. 1102 */ 1103 switch (hw->mac_type) { 1104 case em_82542_rev2_0: 1105 case em_82542_rev2_1: 1106 case em_82543: 1107 case em_82544: 1108 /* Wait for reset to complete */ 1109 usec_delay(10); 1110 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1111 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 1112 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1113 E1000_WRITE_FLUSH(hw); 1114 /* Wait for EEPROM reload */ 1115 msec_delay(2); 1116 break; 1117 case em_82541: 1118 case em_82541_rev_2: 1119 case em_82547: 1120 case em_82547_rev_2: 1121 /* Wait for EEPROM reload */ 1122 msec_delay(20); 1123 break; 1124 case em_82573: 1125 case em_82574: 1126 if (em_is_onboard_nvm_eeprom(hw) == FALSE) { 1127 usec_delay(10); 1128 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1129 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 1130 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1131 E1000_WRITE_FLUSH(hw); 1132 } 1133 /* FALLTHROUGH */ 1134 1135 /* Auto read done will delay 5ms or poll based on mac type */ 1136 ret_val = em_get_auto_rd_done(hw); 1137 if (ret_val) 1138 return ret_val; 1139 break; 1140 default: 1141 /* Wait for EEPROM reload (it happens automatically) */ 1142 msec_delay(5); 1143 break; 1144 } 1145 1146 /* Disable HW ARPs on ASF enabled adapters */ 1147 if (hw->mac_type >= em_82540 && hw->mac_type <= em_82547_rev_2 && 1148 hw->mac_type != em_icp_xxxx) { 1149 manc = E1000_READ_REG(hw, MANC); 1150 manc &= ~(E1000_MANC_ARP_EN); 1151 E1000_WRITE_REG(hw, MANC, manc); 1152 } 1153 if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) { 1154 em_phy_init_script(hw); 1155 1156 /* Configure activity LED after PHY reset */ 1157 led_ctrl = E1000_READ_REG(hw, LEDCTL); 1158 led_ctrl &= IGP_ACTIVITY_LED_MASK; 1159 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 1160 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 1161 } 1162 1163 /* 1164 * For PCH, this write will make sure that any noise 1165 * will be detected as a CRC error and be dropped rather than show up 1166 * as a bad packet to the DMA engine. 1167 */ 1168 if (hw->mac_type == em_pchlan) 1169 E1000_WRITE_REG(hw, CRC_OFFSET, 0x65656565); 1170 1171 /* Clear interrupt mask to stop board from generating interrupts */ 1172 DEBUGOUT("Masking off all interrupts\n"); 1173 E1000_WRITE_REG(hw, IMC, 0xffffffff); 1174 1175 /* Clear any pending interrupt events. */ 1176 icr = E1000_READ_REG(hw, ICR); 1177 1178 /* If MWI was previously enabled, reenable it. */ 1179 if (hw->mac_type == em_82542_rev2_0) { 1180 if (hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1181 em_pci_set_mwi(hw); 1182 } 1183 if (IS_ICH8(hw->mac_type)) { 1184 uint32_t kab = E1000_READ_REG(hw, KABGTXD); 1185 kab |= E1000_KABGTXD_BGSQLBIAS; 1186 E1000_WRITE_REG(hw, KABGTXD, kab); 1187 } 1188 1189 if (hw->mac_type == em_82580 || hw->mac_type == em_i350) { 1190 uint32_t mdicnfg; 1191 uint16_t nvm_data; 1192 1193 /* clear global device reset status bit */ 1194 EM_WRITE_REG(hw, E1000_STATUS, E1000_STATUS_DEV_RST_SET); 1195 1196 em_read_eeprom(hw, EEPROM_INIT_CONTROL3_PORT_A + 1197 NVM_82580_LAN_FUNC_OFFSET(hw->bus_func), 1, 1198 &nvm_data); 1199 1200 mdicnfg = EM_READ_REG(hw, E1000_MDICNFG); 1201 if (nvm_data & NVM_WORD24_EXT_MDIO) 1202 mdicnfg |= E1000_MDICNFG_EXT_MDIO; 1203 if (nvm_data & NVM_WORD24_COM_MDIO) 1204 mdicnfg |= E1000_MDICNFG_COM_MDIO; 1205 EM_WRITE_REG(hw, E1000_MDICNFG, mdicnfg); 1206 } 1207 1208 if (hw->mac_type == em_i210 || hw->mac_type == em_i350) 1209 em_set_eee_i350(hw); 1210 1211 return E1000_SUCCESS; 1212 } 1213 1214 /****************************************************************************** 1215 * 1216 * Initialize a number of hardware-dependent bits 1217 * 1218 * hw: Struct containing variables accessed by shared code 1219 * 1220 *****************************************************************************/ 1221 STATIC void 1222 em_initialize_hardware_bits(struct em_softc *sc) 1223 { 1224 struct em_hw *hw = &sc->hw; 1225 struct em_queue *que; 1226 1227 DEBUGFUNC("em_initialize_hardware_bits"); 1228 1229 if ((hw->mac_type >= em_82571) && (!hw->initialize_hw_bits_disable)) { 1230 /* Settings common to all silicon */ 1231 uint32_t reg_ctrl, reg_ctrl_ext; 1232 uint32_t reg_tarc0, reg_tarc1; 1233 uint32_t reg_tctl; 1234 uint32_t reg_txdctl; 1235 reg_tarc0 = E1000_READ_REG(hw, TARC0); 1236 reg_tarc0 &= ~0x78000000; /* Clear bits 30, 29, 28, and 1237 * 27 */ 1238 FOREACH_QUEUE(sc, que) { 1239 reg_txdctl = E1000_READ_REG(hw, TXDCTL(que->me)); 1240 reg_txdctl |= E1000_TXDCTL_COUNT_DESC; /* Set bit 22 */ 1241 E1000_WRITE_REG(hw, TXDCTL(que->me), reg_txdctl); 1242 } 1243 1244 /* 1245 * Old code always initialized queue 1, 1246 * even when unused, keep behaviour 1247 */ 1248 if (sc->num_queues == 1) { 1249 reg_txdctl = E1000_READ_REG(hw, TXDCTL(1)); 1250 reg_txdctl |= E1000_TXDCTL_COUNT_DESC; 1251 E1000_WRITE_REG(hw, TXDCTL(1), reg_txdctl); 1252 } 1253 1254 switch (hw->mac_type) { 1255 case em_82571: 1256 case em_82572: 1257 reg_tarc1 = E1000_READ_REG(hw, TARC1); 1258 reg_tctl = E1000_READ_REG(hw, TCTL); 1259 1260 /* Set the phy Tx compatible mode bits */ 1261 reg_tarc1 &= ~0x60000000; /* Clear bits 30 and 29 */ 1262 1263 reg_tarc0 |= 0x07800000; /* Set TARC0 bits 23-26 */ 1264 reg_tarc1 |= 0x07000000; /* Set TARC1 bits 24-26 */ 1265 1266 if (reg_tctl & E1000_TCTL_MULR) 1267 /* Clear bit 28 if MULR is 1b */ 1268 reg_tarc1 &= ~0x10000000; 1269 else 1270 /* Set bit 28 if MULR is 0b */ 1271 reg_tarc1 |= 0x10000000; 1272 1273 E1000_WRITE_REG(hw, TARC1, reg_tarc1); 1274 break; 1275 case em_82573: 1276 case em_82574: 1277 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1278 reg_ctrl = E1000_READ_REG(hw, CTRL); 1279 1280 reg_ctrl_ext &= ~0x00800000; /* Clear bit 23 */ 1281 reg_ctrl_ext |= 0x00400000; /* Set bit 22 */ 1282 reg_ctrl &= ~0x20000000; /* Clear bit 29 */ 1283 1284 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); 1285 E1000_WRITE_REG(hw, CTRL, reg_ctrl); 1286 break; 1287 case em_80003es2lan: 1288 if ((hw->media_type == em_media_type_fiber) || 1289 (hw->media_type == em_media_type_internal_serdes)) { 1290 /* Clear bit 20 */ 1291 reg_tarc0 &= ~0x00100000; 1292 } 1293 reg_tctl = E1000_READ_REG(hw, TCTL); 1294 reg_tarc1 = E1000_READ_REG(hw, TARC1); 1295 if (reg_tctl & E1000_TCTL_MULR) 1296 /* Clear bit 28 if MULR is 1b */ 1297 reg_tarc1 &= ~0x10000000; 1298 else 1299 /* Set bit 28 if MULR is 0b */ 1300 reg_tarc1 |= 0x10000000; 1301 1302 E1000_WRITE_REG(hw, TARC1, reg_tarc1); 1303 break; 1304 case em_ich8lan: 1305 case em_ich9lan: 1306 case em_ich10lan: 1307 case em_pchlan: 1308 case em_pch2lan: 1309 case em_pch_lpt: 1310 case em_pch_spt: 1311 case em_pch_cnp: 1312 if (hw->mac_type == em_ich8lan) 1313 /* Set TARC0 bits 29 and 28 */ 1314 reg_tarc0 |= 0x30000000; 1315 1316 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1317 reg_ctrl_ext |= 0x00400000; /* Set bit 22 */ 1318 /* Enable PHY low-power state when MAC is at D3 w/o WoL */ 1319 if (hw->mac_type >= em_pchlan) 1320 reg_ctrl_ext |= E1000_CTRL_EXT_PHYPDEN; 1321 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); 1322 1323 reg_tarc0 |= 0x0d800000; /* Set TARC0 bits 23, 1324 * 24, 26, 27 */ 1325 1326 reg_tarc1 = E1000_READ_REG(hw, TARC1); 1327 reg_tctl = E1000_READ_REG(hw, TCTL); 1328 1329 if (reg_tctl & E1000_TCTL_MULR) 1330 /* Clear bit 28 if MULR is 1b */ 1331 reg_tarc1 &= ~0x10000000; 1332 else 1333 /* Set bit 28 if MULR is 0b */ 1334 reg_tarc1 |= 0x10000000; 1335 1336 reg_tarc1 |= 0x45000000; /* Set bit 24, 26 and 1337 * 30 */ 1338 1339 E1000_WRITE_REG(hw, TARC1, reg_tarc1); 1340 break; 1341 default: 1342 break; 1343 } 1344 1345 E1000_WRITE_REG(hw, TARC0, reg_tarc0); 1346 } 1347 } 1348 1349 /** 1350 * e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value 1351 * @hw: pointer to the HW structure 1352 * 1353 * Toggling the LANPHYPC pin value fully power-cycles the PHY and is 1354 * used to reset the PHY to a quiescent state when necessary. 1355 **/ 1356 static void 1357 em_toggle_lanphypc_pch_lpt(struct em_hw *hw) 1358 { 1359 uint32_t mac_reg; 1360 1361 DEBUGFUNC("e1000_toggle_lanphypc_pch_lpt"); 1362 1363 /* Set Phy Config Counter to 50msec */ 1364 mac_reg = E1000_READ_REG(hw, FEXTNVM3); 1365 mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK; 1366 mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC; 1367 E1000_WRITE_REG(hw, FEXTNVM3, mac_reg); 1368 1369 /* Toggle LANPHYPC Value bit */ 1370 mac_reg = E1000_READ_REG(hw, CTRL); 1371 mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE; 1372 mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE; 1373 E1000_WRITE_REG(hw, CTRL, mac_reg); 1374 E1000_WRITE_FLUSH(hw); 1375 msec_delay(1); 1376 mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE; 1377 E1000_WRITE_REG(hw, CTRL, mac_reg); 1378 E1000_WRITE_FLUSH(hw); 1379 1380 if (hw->mac_type < em_pch_lpt) { 1381 msec_delay(50); 1382 } else { 1383 uint16_t count = 20; 1384 1385 do { 1386 msec_delay(5); 1387 } while (!(E1000_READ_REG(hw, CTRL_EXT) & 1388 E1000_CTRL_EXT_LPCD) && count--); 1389 1390 msec_delay(30); 1391 } 1392 } 1393 1394 /** 1395 * em_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP 1396 * @hw: pointer to the HW structure 1397 * @force: boolean indicating whether or not to force disabling ULP 1398 * 1399 * Un-configure ULP mode when link is up, the system is transitioned from 1400 * Sx or the driver is unloaded. If on a Manageability Engine (ME) enabled 1401 * system, poll for an indication from ME that ULP has been un-configured. 1402 * If not on an ME enabled system, un-configure the ULP mode by software. 1403 * 1404 * During nominal operation, this function is called when link is acquired 1405 * to disable ULP mode (force=FALSE); otherwise, for example when unloading 1406 * the driver or during Sx->S0 transitions, this is called with force=TRUE 1407 * to forcibly disable ULP. 1408 */ 1409 static int 1410 em_disable_ulp_lpt_lp(struct em_hw *hw, bool force) 1411 { 1412 int ret_val = E1000_SUCCESS; 1413 uint32_t mac_reg; 1414 uint16_t phy_reg; 1415 int i = 0; 1416 1417 if ((hw->mac_type < em_pch_lpt) || 1418 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) || 1419 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) || 1420 (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) || 1421 (hw->device_id == E1000_DEV_ID_PCH_I218_V2)) 1422 return 0; 1423 1424 if (E1000_READ_REG(hw, FWSM) & E1000_FWSM_FW_VALID) { 1425 if (force) { 1426 /* Request ME un-configure ULP mode in the PHY */ 1427 mac_reg = E1000_READ_REG(hw, H2ME); 1428 mac_reg &= ~E1000_H2ME_ULP; 1429 mac_reg |= E1000_H2ME_ENFORCE_SETTINGS; 1430 E1000_WRITE_REG(hw, H2ME, mac_reg); 1431 } 1432 1433 /* Poll up to 300msec for ME to clear ULP_CFG_DONE. */ 1434 while (E1000_READ_REG(hw, FWSM) & E1000_FWSM_ULP_CFG_DONE) { 1435 if (i++ == 30) { 1436 ret_val = -E1000_ERR_PHY; 1437 goto out; 1438 } 1439 1440 msec_delay(10); 1441 } 1442 DEBUGOUT1("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10); 1443 1444 if (force) { 1445 mac_reg = E1000_READ_REG(hw, H2ME); 1446 mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS; 1447 E1000_WRITE_REG(hw, H2ME, mac_reg); 1448 } else { 1449 /* Clear H2ME.ULP after ME ULP configuration */ 1450 mac_reg = E1000_READ_REG(hw, H2ME); 1451 mac_reg &= ~E1000_H2ME_ULP; 1452 E1000_WRITE_REG(hw, H2ME, mac_reg); 1453 } 1454 1455 goto out; 1456 } 1457 1458 ret_val = em_get_software_flag(hw); 1459 if (ret_val) 1460 goto out; 1461 1462 if (force) 1463 /* Toggle LANPHYPC Value bit */ 1464 em_toggle_lanphypc_pch_lpt(hw); 1465 1466 /* Unforce SMBus mode in PHY */ 1467 ret_val = em_read_phy_reg(hw, CV_SMB_CTRL, &phy_reg); 1468 if (ret_val) { 1469 /* The MAC might be in PCIe mode, so temporarily force to 1470 * SMBus mode in order to access the PHY. 1471 */ 1472 mac_reg = E1000_READ_REG(hw, CTRL_EXT); 1473 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS; 1474 E1000_WRITE_REG(hw, CTRL_EXT, mac_reg); 1475 1476 msec_delay(50); 1477 1478 ret_val = em_read_phy_reg(hw, CV_SMB_CTRL, &phy_reg); 1479 if (ret_val) 1480 goto release; 1481 } 1482 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS; 1483 em_write_phy_reg(hw, CV_SMB_CTRL, phy_reg); 1484 1485 /* Unforce SMBus mode in MAC */ 1486 mac_reg = E1000_READ_REG(hw, CTRL_EXT); 1487 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; 1488 E1000_WRITE_REG(hw, CTRL_EXT, mac_reg); 1489 1490 /* When ULP mode was previously entered, K1 was disabled by the 1491 * hardware. Re-Enable K1 in the PHY when exiting ULP. 1492 */ 1493 ret_val = em_read_phy_reg(hw, HV_PM_CTRL, &phy_reg); 1494 if (ret_val) 1495 goto release; 1496 phy_reg |= HV_PM_CTRL_K1_ENABLE; 1497 em_write_phy_reg(hw, HV_PM_CTRL, phy_reg); 1498 1499 /* Clear ULP enabled configuration */ 1500 ret_val = em_read_phy_reg(hw, I218_ULP_CONFIG1, &phy_reg); 1501 if (ret_val) 1502 goto release; 1503 phy_reg &= ~(I218_ULP_CONFIG1_IND | 1504 I218_ULP_CONFIG1_STICKY_ULP | 1505 I218_ULP_CONFIG1_RESET_TO_SMBUS | 1506 I218_ULP_CONFIG1_WOL_HOST | 1507 I218_ULP_CONFIG1_INBAND_EXIT | 1508 I218_ULP_CONFIG1_EN_ULP_LANPHYPC | 1509 I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST | 1510 I218_ULP_CONFIG1_DISABLE_SMB_PERST); 1511 em_write_phy_reg(hw, I218_ULP_CONFIG1, phy_reg); 1512 1513 /* Commit ULP changes by starting auto ULP configuration */ 1514 phy_reg |= I218_ULP_CONFIG1_START; 1515 em_write_phy_reg(hw, I218_ULP_CONFIG1, phy_reg); 1516 1517 /* Clear Disable SMBus Release on PERST# in MAC */ 1518 mac_reg = E1000_READ_REG(hw, FEXTNVM7); 1519 mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST; 1520 E1000_WRITE_REG(hw, FEXTNVM7, mac_reg); 1521 1522 release: 1523 em_release_software_flag(hw); 1524 if (force) { 1525 em_phy_reset(hw); 1526 msec_delay(50); 1527 } 1528 out: 1529 if (ret_val) 1530 DEBUGOUT1("Error in ULP disable flow: %d\n", ret_val); 1531 1532 return ret_val; 1533 } 1534 1535 /****************************************************************************** 1536 * Performs basic configuration of the adapter. 1537 * 1538 * hw - Struct containing variables accessed by shared code 1539 * 1540 * Assumes that the controller has previously been reset and is in a 1541 * post-reset uninitialized state. Initializes the receive address registers, 1542 * multicast table, and VLAN filter table. Calls routines to setup link 1543 * configuration and flow control settings. Clears all on-chip counters. Leaves 1544 * the transmit and receive units disabled and uninitialized. 1545 *****************************************************************************/ 1546 int32_t 1547 em_init_hw(struct em_softc *sc) 1548 { 1549 struct em_hw *hw = &sc->hw; 1550 struct em_queue *que; 1551 uint32_t ctrl; 1552 uint32_t i; 1553 int32_t ret_val; 1554 uint16_t pcix_cmd_word; 1555 uint16_t pcix_stat_hi_word; 1556 uint16_t cmd_mmrbc; 1557 uint16_t stat_mmrbc; 1558 uint32_t mta_size; 1559 uint32_t reg_data; 1560 uint32_t ctrl_ext; 1561 uint32_t snoop; 1562 uint32_t fwsm; 1563 DEBUGFUNC("em_init_hw"); 1564 1565 /* force full DMA clock frequency for ICH8 */ 1566 if (hw->mac_type == em_ich8lan) { 1567 reg_data = E1000_READ_REG(hw, STATUS); 1568 reg_data &= ~0x80000000; 1569 E1000_WRITE_REG(hw, STATUS, reg_data); 1570 } 1571 1572 if (hw->mac_type == em_pchlan || 1573 hw->mac_type == em_pch2lan || 1574 hw->mac_type == em_pch_lpt || 1575 hw->mac_type == em_pch_spt || 1576 hw->mac_type == em_pch_cnp) { 1577 /* 1578 * The MAC-PHY interconnect may still be in SMBus mode 1579 * after Sx->S0. Toggle the LANPHYPC Value bit to force 1580 * the interconnect to PCIe mode, but only if there is no 1581 * firmware present otherwise firmware will have done it. 1582 */ 1583 fwsm = E1000_READ_REG(hw, FWSM); 1584 if ((fwsm & E1000_FWSM_FW_VALID) == 0) { 1585 ctrl = E1000_READ_REG(hw, CTRL); 1586 ctrl |= E1000_CTRL_LANPHYPC_OVERRIDE; 1587 ctrl &= ~E1000_CTRL_LANPHYPC_VALUE; 1588 E1000_WRITE_REG(hw, CTRL, ctrl); 1589 usec_delay(10); 1590 ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE; 1591 E1000_WRITE_REG(hw, CTRL, ctrl); 1592 msec_delay(50); 1593 } 1594 1595 /* Gate automatic PHY configuration on non-managed 82579 */ 1596 if (hw->mac_type == em_pch2lan) 1597 em_gate_hw_phy_config_ich8lan(hw, TRUE); 1598 1599 em_disable_ulp_lpt_lp(hw, TRUE); 1600 /* 1601 * Reset the PHY before any access to it. Doing so, 1602 * ensures that the PHY is in a known good state before 1603 * we read/write PHY registers. The generic reset is 1604 * sufficient here, because we haven't determined 1605 * the PHY type yet. 1606 */ 1607 em_phy_reset(hw); 1608 1609 /* Ungate automatic PHY configuration on non-managed 82579 */ 1610 if (hw->mac_type == em_pch2lan && 1611 (fwsm & E1000_FWSM_FW_VALID) == 0) 1612 em_gate_hw_phy_config_ich8lan(hw, FALSE); 1613 1614 /* Set MDIO slow mode before any other MDIO access */ 1615 ret_val = em_set_mdio_slow_mode_hv(hw); 1616 if (ret_val) 1617 return ret_val; 1618 } 1619 1620 /* Initialize Identification LED */ 1621 ret_val = em_id_led_init(hw); 1622 if (ret_val) { 1623 DEBUGOUT("Error Initializing Identification LED\n"); 1624 return ret_val; 1625 } 1626 /* Set the media type and TBI compatibility */ 1627 em_set_media_type(hw); 1628 1629 /* Magic delay that improves problems with i219LM on HP Elitebook */ 1630 msec_delay(1); 1631 /* Must be called after em_set_media_type because media_type is used */ 1632 em_initialize_hardware_bits(sc); 1633 1634 /* Disabling VLAN filtering. */ 1635 DEBUGOUT("Initializing the IEEE VLAN\n"); 1636 /* VET hardcoded to standard value and VFTA removed in ICH8/ICH9 LAN */ 1637 if (!IS_ICH8(hw->mac_type)) { 1638 if (hw->mac_type < em_82545_rev_3) 1639 E1000_WRITE_REG(hw, VET, 0); 1640 if (hw->mac_type == em_i350) 1641 em_clear_vfta_i350(hw); 1642 else 1643 em_clear_vfta(hw); 1644 } 1645 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ 1646 if (hw->mac_type == em_82542_rev2_0) { 1647 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 1648 em_pci_clear_mwi(hw); 1649 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST); 1650 E1000_WRITE_FLUSH(hw); 1651 msec_delay(5); 1652 } 1653 /* 1654 * Setup the receive address. This involves initializing all of the 1655 * Receive Address Registers (RARs 0 - 15). 1656 */ 1657 em_init_rx_addrs(hw); 1658 1659 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI*/ 1660 if (hw->mac_type == em_82542_rev2_0) { 1661 E1000_WRITE_REG(hw, RCTL, 0); 1662 E1000_WRITE_FLUSH(hw); 1663 msec_delay(1); 1664 if (hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1665 em_pci_set_mwi(hw); 1666 } 1667 /* Zero out the Multicast HASH table */ 1668 DEBUGOUT("Zeroing the MTA\n"); 1669 mta_size = E1000_MC_TBL_SIZE; 1670 if (IS_ICH8(hw->mac_type)) 1671 mta_size = E1000_MC_TBL_SIZE_ICH8LAN; 1672 for (i = 0; i < mta_size; i++) { 1673 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 1674 /* 1675 * use write flush to prevent Memory Write Block (MWB) from 1676 * occurring when accessing our register space 1677 */ 1678 E1000_WRITE_FLUSH(hw); 1679 } 1680 /* 1681 * Set the PCI priority bit correctly in the CTRL register. This 1682 * determines if the adapter gives priority to receives, or if it 1683 * gives equal priority to transmits and receives. Valid only on 1684 * 82542 and 82543 silicon. 1685 */ 1686 if (hw->dma_fairness && hw->mac_type <= em_82543) { 1687 ctrl = E1000_READ_REG(hw, CTRL); 1688 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR); 1689 } 1690 switch (hw->mac_type) { 1691 case em_82545_rev_3: 1692 case em_82546_rev_3: 1693 break; 1694 default: 1695 /* 1696 * Workaround for PCI-X problem when BIOS sets MMRBC 1697 * incorrectly. 1698 */ 1699 if (hw->bus_type == em_bus_type_pcix) { 1700 em_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, 1701 &pcix_cmd_word); 1702 em_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, 1703 &pcix_stat_hi_word); 1704 cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) 1705 >> PCIX_COMMAND_MMRBC_SHIFT; 1706 stat_mmrbc = (pcix_stat_hi_word & 1707 PCIX_STATUS_HI_MMRBC_MASK) >> 1708 PCIX_STATUS_HI_MMRBC_SHIFT; 1709 1710 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) 1711 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; 1712 if (cmd_mmrbc > stat_mmrbc) { 1713 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK; 1714 pcix_cmd_word |= stat_mmrbc << 1715 PCIX_COMMAND_MMRBC_SHIFT; 1716 em_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, 1717 &pcix_cmd_word); 1718 } 1719 } 1720 break; 1721 } 1722 1723 /* More time needed for PHY to initialize */ 1724 if (IS_ICH8(hw->mac_type)) 1725 msec_delay(15); 1726 1727 /* 1728 * The 82578 Rx buffer will stall if wakeup is enabled in host and 1729 * the ME. Reading the BM_WUC register will clear the host wakeup bit. 1730 * Reset the phy after disabling host wakeup to reset the Rx buffer. 1731 */ 1732 if (hw->phy_type == em_phy_82578) { 1733 em_read_phy_reg(hw, PHY_REG(BM_WUC_PAGE, 1), 1734 (uint16_t *)®_data); 1735 ret_val = em_phy_reset(hw); 1736 if (ret_val) 1737 return ret_val; 1738 } 1739 1740 /* Call a subroutine to configure the link and setup flow control. */ 1741 ret_val = em_setup_link(hw); 1742 1743 /* Set the transmit descriptor write-back policy */ 1744 if (hw->mac_type > em_82544) { 1745 FOREACH_QUEUE(sc, que) { 1746 ctrl = E1000_READ_REG(hw, TXDCTL(que->me)); 1747 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | 1748 E1000_TXDCTL_FULL_TX_DESC_WB; 1749 E1000_WRITE_REG(hw, TXDCTL(que->me), ctrl); 1750 } 1751 } 1752 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) { 1753 em_enable_tx_pkt_filtering(hw); 1754 } 1755 switch (hw->mac_type) { 1756 default: 1757 break; 1758 case em_80003es2lan: 1759 /* Enable retransmit on late collisions */ 1760 reg_data = E1000_READ_REG(hw, TCTL); 1761 reg_data |= E1000_TCTL_RTLC; 1762 E1000_WRITE_REG(hw, TCTL, reg_data); 1763 1764 /* Configure Gigabit Carry Extend Padding */ 1765 reg_data = E1000_READ_REG(hw, TCTL_EXT); 1766 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK; 1767 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX; 1768 E1000_WRITE_REG(hw, TCTL_EXT, reg_data); 1769 1770 /* Configure Transmit Inter-Packet Gap */ 1771 reg_data = E1000_READ_REG(hw, TIPG); 1772 reg_data &= ~E1000_TIPG_IPGT_MASK; 1773 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; 1774 E1000_WRITE_REG(hw, TIPG, reg_data); 1775 1776 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001); 1777 reg_data &= ~0x00100000; 1778 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data); 1779 /* FALLTHROUGH */ 1780 case em_82571: 1781 case em_82572: 1782 case em_82575: 1783 case em_82576: 1784 case em_82580: 1785 case em_i210: 1786 case em_i350: 1787 case em_ich8lan: 1788 case em_ich9lan: 1789 case em_ich10lan: 1790 case em_pchlan: 1791 case em_pch2lan: 1792 case em_pch_lpt: 1793 case em_pch_spt: 1794 case em_pch_cnp: 1795 /* 1796 * Old code always initialized queue 1, 1797 * even when unused, keep behaviour 1798 */ 1799 if (sc->num_queues == 1) { 1800 ctrl = E1000_READ_REG(hw, TXDCTL(1)); 1801 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | 1802 E1000_TXDCTL_FULL_TX_DESC_WB; 1803 E1000_WRITE_REG(hw, TXDCTL(1), ctrl); 1804 } 1805 break; 1806 } 1807 1808 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) { 1809 uint32_t gcr = E1000_READ_REG(hw, GCR); 1810 gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; 1811 E1000_WRITE_REG(hw, GCR, gcr); 1812 } 1813 /* 1814 * Clear all of the statistics registers (clear on read). It is 1815 * important that we do this after we have tried to establish link 1816 * because the symbol error count will increment wildly if there is 1817 * no link. 1818 */ 1819 em_clear_hw_cntrs(hw); 1820 /* 1821 * ICH8 No-snoop bits are opposite polarity. Set to snoop by default 1822 * after reset. 1823 */ 1824 if (IS_ICH8(hw->mac_type)) { 1825 if (hw->mac_type == em_ich8lan) 1826 snoop = PCI_EX_82566_SNOOP_ALL; 1827 else 1828 snoop = (u_int32_t) ~ (PCI_EX_NO_SNOOP_ALL); 1829 1830 em_set_pci_ex_no_snoop(hw, snoop); 1831 } 1832 1833 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER || 1834 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) { 1835 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1836 /* 1837 * Relaxed ordering must be disabled to avoid a parity error 1838 * crash in a PCI slot. 1839 */ 1840 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 1841 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1842 } 1843 return ret_val; 1844 } 1845 1846 /****************************************************************************** 1847 * Adjust SERDES output amplitude based on EEPROM setting. 1848 * 1849 * hw - Struct containing variables accessed by shared code. 1850 *****************************************************************************/ 1851 static int32_t 1852 em_adjust_serdes_amplitude(struct em_hw *hw) 1853 { 1854 uint16_t eeprom_data; 1855 int32_t ret_val; 1856 DEBUGFUNC("em_adjust_serdes_amplitude"); 1857 1858 if (hw->media_type != em_media_type_internal_serdes || 1859 hw->mac_type >= em_82575) 1860 return E1000_SUCCESS; 1861 1862 switch (hw->mac_type) { 1863 case em_82545_rev_3: 1864 case em_82546_rev_3: 1865 break; 1866 default: 1867 return E1000_SUCCESS; 1868 } 1869 1870 ret_val = em_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data); 1871 if (ret_val) { 1872 return ret_val; 1873 } 1874 if (eeprom_data != EEPROM_RESERVED_WORD) { 1875 /* Adjust SERDES output amplitude only. */ 1876 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK; 1877 ret_val = em_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, 1878 eeprom_data); 1879 if (ret_val) 1880 return ret_val; 1881 } 1882 return E1000_SUCCESS; 1883 } 1884 1885 /****************************************************************************** 1886 * Configures flow control and link settings. 1887 * 1888 * hw - Struct containing variables accessed by shared code 1889 * 1890 * Determines which flow control settings to use. Calls the appropriate media- 1891 * specific link configuration function. Configures the flow control settings. 1892 * Assuming the adapter has a valid link partner, a valid link should be 1893 * established. Assumes the hardware has previously been reset and the 1894 * transmitter and receiver are not enabled. 1895 *****************************************************************************/ 1896 int32_t 1897 em_setup_link(struct em_hw *hw) 1898 { 1899 uint32_t ctrl_ext; 1900 int32_t ret_val; 1901 uint16_t eeprom_data; 1902 uint16_t eeprom_control2_reg_offset; 1903 DEBUGFUNC("em_setup_link"); 1904 1905 eeprom_control2_reg_offset = 1906 (hw->mac_type != em_icp_xxxx) 1907 ? EEPROM_INIT_CONTROL2_REG 1908 : EEPROM_INIT_CONTROL3_ICP_xxxx(hw->icp_xxxx_port_num); 1909 /* 1910 * In the case of the phy reset being blocked, we already have a 1911 * link. We do not have to set it up again. 1912 */ 1913 if (em_check_phy_reset_block(hw)) 1914 return E1000_SUCCESS; 1915 /* 1916 * Read and store word 0x0F of the EEPROM. This word contains bits 1917 * that determine the hardware's default PAUSE (flow control) mode, a 1918 * bit that determines whether the HW defaults to enabling or 1919 * disabling auto-negotiation, and the direction of the SW defined 1920 * pins. If there is no SW over-ride of the flow control setting, 1921 * then the variable hw->fc will be initialized based on a value in 1922 * the EEPROM. 1923 */ 1924 if (hw->fc == E1000_FC_DEFAULT) { 1925 switch (hw->mac_type) { 1926 case em_ich8lan: 1927 case em_ich9lan: 1928 case em_ich10lan: 1929 case em_pchlan: 1930 case em_pch2lan: 1931 case em_pch_lpt: 1932 case em_pch_spt: 1933 case em_pch_cnp: 1934 case em_82573: 1935 case em_82574: 1936 hw->fc = E1000_FC_FULL; 1937 break; 1938 default: 1939 ret_val = em_read_eeprom(hw, 1940 eeprom_control2_reg_offset, 1, &eeprom_data); 1941 if (ret_val) { 1942 DEBUGOUT("EEPROM Read Error\n"); 1943 return -E1000_ERR_EEPROM; 1944 } 1945 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0) 1946 hw->fc = E1000_FC_NONE; 1947 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 1948 EEPROM_WORD0F_ASM_DIR) 1949 hw->fc = E1000_FC_TX_PAUSE; 1950 else 1951 hw->fc = E1000_FC_FULL; 1952 break; 1953 } 1954 } 1955 /* 1956 * We want to save off the original Flow Control configuration just 1957 * in case we get disconnected and then reconnected into a different 1958 * hub or switch with different Flow Control capabilities. 1959 */ 1960 if (hw->mac_type == em_82542_rev2_0) 1961 hw->fc &= (~E1000_FC_TX_PAUSE); 1962 1963 if ((hw->mac_type < em_82543) && (hw->report_tx_early == 1)) 1964 hw->fc &= (~E1000_FC_RX_PAUSE); 1965 1966 hw->original_fc = hw->fc; 1967 1968 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc); 1969 /* 1970 * Take the 4 bits from EEPROM word 0x0F that determine the initial 1971 * polarity value for the SW controlled pins, and setup the Extended 1972 * Device Control reg with that info. This is needed because one of 1973 * the SW controlled pins is used for signal detection. So this 1974 * should be done before em_setup_pcs_link() or em_phy_setup() is 1975 * called. 1976 */ 1977 if (hw->mac_type == em_82543) { 1978 ret_val = em_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1979 1, &eeprom_data); 1980 if (ret_val) { 1981 DEBUGOUT("EEPROM Read Error\n"); 1982 return -E1000_ERR_EEPROM; 1983 } 1984 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << 1985 SWDPIO__EXT_SHIFT); 1986 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1987 } 1988 /* Make sure we have a valid PHY */ 1989 ret_val = em_detect_gig_phy(hw); 1990 if (ret_val) { 1991 DEBUGOUT("Error, did not detect valid phy.\n"); 1992 if (hw->mac_type == em_icp_xxxx) 1993 return E1000_DEFER_INIT; 1994 else 1995 return ret_val; 1996 } 1997 DEBUGOUT1("Phy ID = %x \n", hw->phy_id); 1998 1999 /* Call the necessary subroutine to configure the link. */ 2000 switch (hw->media_type) { 2001 case em_media_type_copper: 2002 case em_media_type_oem: 2003 ret_val = em_setup_copper_link(hw); 2004 break; 2005 default: 2006 ret_val = em_setup_fiber_serdes_link(hw); 2007 break; 2008 } 2009 /* 2010 * Initialize the flow control address, type, and PAUSE timer 2011 * registers to their default values. This is done even if flow 2012 * control is disabled, because it does not hurt anything to 2013 * initialize these registers. 2014 */ 2015 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n" 2016 ); 2017 2018 /* 2019 * FCAL/H and FCT are hardcoded to standard values in 2020 * em_ich8lan / em_ich9lan / em_ich10lan. 2021 */ 2022 if (!IS_ICH8(hw->mac_type)) { 2023 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE); 2024 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH); 2025 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW); 2026 } 2027 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time); 2028 2029 if (hw->phy_type == em_phy_82577 || 2030 hw->phy_type == em_phy_82578 || 2031 hw->phy_type == em_phy_82579 || 2032 hw->phy_type == em_phy_i217) { 2033 E1000_WRITE_REG(hw, FCRTV_PCH, 0x1000); 2034 em_write_phy_reg(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27), 2035 hw->fc_pause_time); 2036 } 2037 2038 /* 2039 * Set the flow control receive threshold registers. Normally, these 2040 * registers will be set to a default threshold that may be adjusted 2041 * later by the driver's runtime code. However, if the ability to 2042 * transmit pause frames in not enabled, then these registers will be 2043 * set to 0. 2044 */ 2045 if (!(hw->fc & E1000_FC_TX_PAUSE)) { 2046 E1000_WRITE_REG(hw, FCRTL, 0); 2047 E1000_WRITE_REG(hw, FCRTH, 0); 2048 } else { 2049 /* 2050 * We need to set up the Receive Threshold high and low water 2051 * marks as well as (optionally) enabling the transmission of 2052 * XON frames. 2053 */ 2054 if (hw->fc_send_xon) { 2055 E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water 2056 | E1000_FCRTL_XONE)); 2057 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); 2058 } else { 2059 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water); 2060 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); 2061 } 2062 } 2063 return ret_val; 2064 } 2065 2066 void 2067 em_power_up_serdes_link_82575(struct em_hw *hw) 2068 { 2069 uint32_t reg; 2070 2071 if (hw->media_type != em_media_type_internal_serdes && 2072 hw->sgmii_active == FALSE) 2073 return; 2074 2075 /* Enable PCS to turn on link */ 2076 reg = E1000_READ_REG(hw, PCS_CFG0); 2077 reg |= E1000_PCS_CFG_PCS_EN; 2078 E1000_WRITE_REG(hw, PCS_CFG0, reg); 2079 2080 /* Power up the laser */ 2081 reg = E1000_READ_REG(hw, CTRL_EXT); 2082 reg &= ~E1000_CTRL_EXT_SDP3_DATA; 2083 E1000_WRITE_REG(hw, CTRL_EXT, reg); 2084 2085 /* flush the write to verify completion */ 2086 E1000_WRITE_FLUSH(hw); 2087 delay(5); 2088 } 2089 2090 /****************************************************************************** 2091 * Sets up link for a fiber based or serdes based adapter 2092 * 2093 * hw - Struct containing variables accessed by shared code 2094 * 2095 * Manipulates Physical Coding Sublayer functions in order to configure 2096 * link. Assumes the hardware has been previously reset and the transmitter 2097 * and receiver are not enabled. 2098 *****************************************************************************/ 2099 static int32_t 2100 em_setup_fiber_serdes_link(struct em_hw *hw) 2101 { 2102 uint32_t ctrl, ctrl_ext, reg; 2103 uint32_t status; 2104 uint32_t txcw = 0; 2105 uint32_t i; 2106 uint32_t signal = 0; 2107 int32_t ret_val; 2108 DEBUGFUNC("em_setup_fiber_serdes_link"); 2109 2110 if (hw->media_type != em_media_type_internal_serdes && 2111 hw->sgmii_active == FALSE) 2112 return -E1000_ERR_CONFIG; 2113 2114 /* 2115 * On 82571 and 82572 Fiber connections, SerDes loopback mode 2116 * persists until explicitly turned off or a power cycle is 2117 * performed. A read to the register does not indicate its status. 2118 * Therefore, we ensure loopback mode is disabled during 2119 * initialization. 2120 */ 2121 if (hw->mac_type == em_82571 || hw->mac_type == em_82572 || 2122 hw->mac_type >= em_82575) 2123 E1000_WRITE_REG(hw, SCTL, E1000_DISABLE_SERDES_LOOPBACK); 2124 2125 if (hw->mac_type >= em_82575) 2126 em_power_up_serdes_link_82575(hw); 2127 2128 /* 2129 * On adapters with a MAC newer than 82544, SWDP 1 will be set when 2130 * the optics detect a signal. On older adapters, it will be cleared 2131 * when there is a signal. This applies to fiber media only. If 2132 * we're on serdes media, adjust the output amplitude to value set in 2133 * the EEPROM. 2134 */ 2135 ctrl = E1000_READ_REG(hw, CTRL); 2136 if (hw->media_type == em_media_type_fiber) 2137 signal = (hw->mac_type > em_82544) ? E1000_CTRL_SWDPIN1 : 0; 2138 2139 ret_val = em_adjust_serdes_amplitude(hw); 2140 if (ret_val) 2141 return ret_val; 2142 2143 /* Take the link out of reset */ 2144 ctrl &= ~(E1000_CTRL_LRST); 2145 2146 if (hw->mac_type >= em_82575) { 2147 /* set both sw defined pins on 82575/82576*/ 2148 ctrl |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1; 2149 2150 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 2151 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) { 2152 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: 2153 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES: 2154 /* the backplane is always connected */ 2155 reg = E1000_READ_REG(hw, PCS_LCTL); 2156 reg |= E1000_PCS_LCTL_FORCE_FCTRL; 2157 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL; 2158 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */ 2159 DEBUGOUT("Configuring Forced Link\n"); 2160 E1000_WRITE_REG(hw, PCS_LCTL, reg); 2161 em_force_mac_fc(hw); 2162 hw->autoneg_failed = 0; 2163 return E1000_SUCCESS; 2164 break; 2165 default: 2166 /* Set switch control to serdes energy detect */ 2167 reg = E1000_READ_REG(hw, CONNSW); 2168 reg |= E1000_CONNSW_ENRGSRC; 2169 E1000_WRITE_REG(hw, CONNSW, reg); 2170 break; 2171 } 2172 } 2173 2174 /* Adjust VCO speed to improve BER performance */ 2175 ret_val = em_set_vco_speed(hw); 2176 if (ret_val) 2177 return ret_val; 2178 2179 em_config_collision_dist(hw); 2180 /* 2181 * Check for a software override of the flow control settings, and 2182 * setup the device accordingly. If auto-negotiation is enabled, 2183 * then software will have to set the "PAUSE" bits to the correct 2184 * value in the Tranmsit Config Word Register (TXCW) and re-start 2185 * auto-negotiation. However, if auto-negotiation is disabled, then 2186 * software will have to manually configure the two flow control 2187 * enable bits in the CTRL register. 2188 * 2189 * The possible values of the "fc" parameter are: 0: Flow control is 2190 * completely disabled 1: Rx flow control is enabled (we can receive 2191 * pause frames, but not send pause frames). 2: Tx flow control is 2192 * enabled (we can send pause frames but we do not support receiving 2193 * pause frames). 3: Both Rx and TX flow control (symmetric) are 2194 * enabled. 2195 */ 2196 switch (hw->fc) { 2197 case E1000_FC_NONE: 2198 /* 2199 * Flow control is completely disabled by a software 2200 * over-ride. 2201 */ 2202 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 2203 break; 2204 case E1000_FC_RX_PAUSE: 2205 /* 2206 * RX Flow control is enabled and TX Flow control is disabled 2207 * by a software over-ride. Since there really isn't a way to 2208 * advertise that we are capable of RX Pause ONLY, we will 2209 * advertise that we support both symmetric and asymmetric RX 2210 * PAUSE. Later, we will disable the adapter's ability to 2211 * send PAUSE frames. 2212 */ 2213 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | 2214 E1000_TXCW_PAUSE_MASK); 2215 break; 2216 case E1000_FC_TX_PAUSE: 2217 /* 2218 * TX Flow control is enabled, and RX Flow control is 2219 * disabled, by a software over-ride. 2220 */ 2221 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 2222 break; 2223 case E1000_FC_FULL: 2224 /* 2225 * Flow control (both RX and TX) is enabled by a software 2226 * over-ride. 2227 */ 2228 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | 2229 E1000_TXCW_PAUSE_MASK); 2230 break; 2231 default: 2232 DEBUGOUT("Flow control param set incorrectly\n"); 2233 return -E1000_ERR_CONFIG; 2234 break; 2235 } 2236 /* 2237 * Since auto-negotiation is enabled, take the link out of reset (the 2238 * link will be in reset, because we previously reset the chip). This 2239 * will restart auto-negotiation. If auto-negotiation is successful 2240 * then the link-up status bit will be set and the flow control 2241 * enable bits (RFCE and TFCE) will be set according to their 2242 * negotiated value. 2243 */ 2244 DEBUGOUT("Auto-negotiation enabled\n"); 2245 2246 E1000_WRITE_REG(hw, TXCW, txcw); 2247 E1000_WRITE_REG(hw, CTRL, ctrl); 2248 E1000_WRITE_FLUSH(hw); 2249 2250 hw->txcw = txcw; 2251 msec_delay(1); 2252 /* 2253 * If we have a signal (the cable is plugged in) then poll for a 2254 * "Link-Up" indication in the Device Status Register. Time-out if a 2255 * link isn't seen in 500 milliseconds seconds (Auto-negotiation 2256 * should complete in less than 500 milliseconds even if the other 2257 * end is doing it in SW). For internal serdes, we just assume a 2258 * signal is present, then poll. 2259 */ 2260 if (hw->media_type == em_media_type_internal_serdes || 2261 (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) { 2262 DEBUGOUT("Looking for Link\n"); 2263 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) { 2264 msec_delay(10); 2265 status = E1000_READ_REG(hw, STATUS); 2266 if (status & E1000_STATUS_LU) 2267 break; 2268 } 2269 if (i == (LINK_UP_TIMEOUT / 10)) { 2270 DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 2271 hw->autoneg_failed = 1; 2272 /* 2273 * AutoNeg failed to achieve a link, so we'll call 2274 * em_check_for_link. This routine will force the 2275 * link up if we detect a signal. This will allow us 2276 * to communicate with non-autonegotiating link 2277 * partners. 2278 */ 2279 ret_val = em_check_for_link(hw); 2280 if (ret_val) { 2281 DEBUGOUT("Error while checking for link\n"); 2282 return ret_val; 2283 } 2284 hw->autoneg_failed = 0; 2285 } else { 2286 hw->autoneg_failed = 0; 2287 DEBUGOUT("Valid Link Found\n"); 2288 } 2289 } else { 2290 DEBUGOUT("No Signal Detected\n"); 2291 } 2292 return E1000_SUCCESS; 2293 } 2294 2295 /****************************************************************************** 2296 * Make sure we have a valid PHY and change PHY mode before link setup. 2297 * 2298 * hw - Struct containing variables accessed by shared code 2299 *****************************************************************************/ 2300 static int32_t 2301 em_copper_link_preconfig(struct em_hw *hw) 2302 { 2303 uint32_t ctrl; 2304 int32_t ret_val; 2305 uint16_t phy_data; 2306 DEBUGFUNC("em_copper_link_preconfig"); 2307 2308 ctrl = E1000_READ_REG(hw, CTRL); 2309 /* 2310 * With 82543, we need to force speed and duplex on the MAC equal to 2311 * what the PHY speed and duplex configuration is. In addition, we 2312 * need to perform a hardware reset on the PHY to take it out of 2313 * reset. 2314 */ 2315 if (hw->mac_type > em_82543) { 2316 ctrl |= E1000_CTRL_SLU; 2317 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 2318 E1000_WRITE_REG(hw, CTRL, ctrl); 2319 } else { 2320 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | 2321 E1000_CTRL_SLU); 2322 E1000_WRITE_REG(hw, CTRL, ctrl); 2323 ret_val = em_phy_hw_reset(hw); 2324 if (ret_val) 2325 return ret_val; 2326 } 2327 2328 /* Set PHY to class A mode (if necessary) */ 2329 ret_val = em_set_phy_mode(hw); 2330 if (ret_val) 2331 return ret_val; 2332 2333 if ((hw->mac_type == em_82545_rev_3) || 2334 (hw->mac_type == em_82546_rev_3)) { 2335 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 2336 &phy_data); 2337 phy_data |= 0x00000008; 2338 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 2339 phy_data); 2340 } 2341 if (hw->mac_type <= em_82543 || 2342 hw->mac_type == em_82541 || hw->mac_type == em_82547 || 2343 hw->mac_type == em_82541_rev_2 || hw->mac_type == em_82547_rev_2) 2344 hw->phy_reset_disable = FALSE; 2345 if ((hw->mac_type == em_82575 || hw->mac_type == em_82580 || 2346 hw->mac_type == em_82576 || 2347 hw->mac_type == em_i210 || hw->mac_type == em_i350) && 2348 hw->sgmii_active) { 2349 /* allow time for SFP cage time to power up phy */ 2350 msec_delay(300); 2351 2352 /* 2353 * SFP documentation requires the following to configure the SFP module 2354 * to work on SGMII. No further documentation is given. 2355 */ 2356 em_write_phy_reg(hw, 0x1B, 0x8084); 2357 em_phy_hw_reset(hw); 2358 } 2359 2360 return E1000_SUCCESS; 2361 } 2362 2363 /****************************************************************************** 2364 * Copper link setup for em_phy_igp series. 2365 * 2366 * hw - Struct containing variables accessed by shared code 2367 *****************************************************************************/ 2368 static int32_t 2369 em_copper_link_igp_setup(struct em_hw *hw) 2370 { 2371 uint32_t led_ctrl; 2372 int32_t ret_val; 2373 uint16_t phy_data; 2374 DEBUGFUNC("em_copper_link_igp_setup"); 2375 2376 if (hw->phy_reset_disable) 2377 return E1000_SUCCESS; 2378 2379 ret_val = em_phy_reset(hw); 2380 if (ret_val) { 2381 DEBUGOUT("Error Resetting the PHY\n"); 2382 return ret_val; 2383 } 2384 /* Wait 15ms for MAC to configure PHY from eeprom settings */ 2385 msec_delay(15); 2386 if (hw->mac_type != em_ich8lan && 2387 hw->mac_type != em_ich9lan && 2388 hw->mac_type != em_ich10lan) { 2389 /* Configure activity LED after PHY reset */ 2390 led_ctrl = E1000_READ_REG(hw, LEDCTL); 2391 led_ctrl &= IGP_ACTIVITY_LED_MASK; 2392 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 2393 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 2394 } 2395 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */ 2396 if (hw->phy_type == em_phy_igp) { 2397 /* disable lplu d3 during driver init */ 2398 ret_val = em_set_d3_lplu_state(hw, FALSE); 2399 if (ret_val) { 2400 DEBUGOUT("Error Disabling LPLU D3\n"); 2401 return ret_val; 2402 } 2403 } 2404 /* disable lplu d0 during driver init */ 2405 if (hw->mac_type == em_pchlan || 2406 hw->mac_type == em_pch2lan || 2407 hw->mac_type == em_pch_lpt || 2408 hw->mac_type == em_pch_spt || 2409 hw->mac_type == em_pch_cnp) 2410 ret_val = em_set_lplu_state_pchlan(hw, FALSE); 2411 else 2412 ret_val = em_set_d0_lplu_state(hw, FALSE); 2413 if (ret_val) { 2414 DEBUGOUT("Error Disabling LPLU D0\n"); 2415 return ret_val; 2416 } 2417 /* Configure mdi-mdix settings */ 2418 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 2419 if (ret_val) 2420 return ret_val; 2421 2422 if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) { 2423 hw->dsp_config_state = em_dsp_config_disabled; 2424 /* Force MDI for earlier revs of the IGP PHY */ 2425 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | 2426 IGP01E1000_PSCR_FORCE_MDI_MDIX); 2427 hw->mdix = 1; 2428 2429 } else { 2430 hw->dsp_config_state = em_dsp_config_enabled; 2431 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 2432 2433 switch (hw->mdix) { 2434 case 1: 2435 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 2436 break; 2437 case 2: 2438 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; 2439 break; 2440 case 0: 2441 default: 2442 phy_data |= IGP01E1000_PSCR_AUTO_MDIX; 2443 break; 2444 } 2445 } 2446 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 2447 if (ret_val) 2448 return ret_val; 2449 2450 /* set auto-master slave resolution settings */ 2451 if (hw->autoneg) { 2452 em_ms_type phy_ms_setting = hw->master_slave; 2453 if (hw->ffe_config_state == em_ffe_config_active) 2454 hw->ffe_config_state = em_ffe_config_enabled; 2455 2456 if (hw->dsp_config_state == em_dsp_config_activated) 2457 hw->dsp_config_state = em_dsp_config_enabled; 2458 /* 2459 * when autonegotiation advertisement is only 1000Mbps then 2460 * we should disable SmartSpeed and enable Auto MasterSlave 2461 * resolution as hardware default. 2462 */ 2463 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) { 2464 /* Disable SmartSpeed */ 2465 ret_val = em_read_phy_reg(hw, 2466 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2467 if (ret_val) 2468 return ret_val; 2469 2470 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2471 ret_val = em_write_phy_reg(hw, 2472 IGP01E1000_PHY_PORT_CONFIG, phy_data); 2473 if (ret_val) 2474 return ret_val; 2475 /* Set auto Master/Slave resolution process */ 2476 ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, 2477 &phy_data); 2478 if (ret_val) 2479 return ret_val; 2480 2481 phy_data &= ~CR_1000T_MS_ENABLE; 2482 ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL, 2483 phy_data); 2484 if (ret_val) 2485 return ret_val; 2486 } 2487 ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); 2488 if (ret_val) 2489 return ret_val; 2490 2491 /* load defaults for future use */ 2492 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ? 2493 ((phy_data & CR_1000T_MS_VALUE) ? em_ms_force_master : 2494 em_ms_force_slave) : em_ms_auto; 2495 2496 switch (phy_ms_setting) { 2497 case em_ms_force_master: 2498 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 2499 break; 2500 case em_ms_force_slave: 2501 phy_data |= CR_1000T_MS_ENABLE; 2502 phy_data &= ~(CR_1000T_MS_VALUE); 2503 break; 2504 case em_ms_auto: 2505 phy_data &= ~CR_1000T_MS_ENABLE; 2506 break; 2507 default: 2508 break; 2509 } 2510 ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); 2511 if (ret_val) 2512 return ret_val; 2513 } 2514 return E1000_SUCCESS; 2515 } 2516 2517 /****************************************************************************** 2518 * Copper link setup for em_phy_gg82563 series. 2519 * 2520 * hw - Struct containing variables accessed by shared code 2521 *****************************************************************************/ 2522 static int32_t 2523 em_copper_link_ggp_setup(struct em_hw *hw) 2524 { 2525 int32_t ret_val; 2526 uint16_t phy_data; 2527 uint32_t reg_data; 2528 DEBUGFUNC("em_copper_link_ggp_setup"); 2529 2530 if (!hw->phy_reset_disable) { 2531 2532 /* Enable CRS on TX for half-duplex operation. */ 2533 ret_val = em_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 2534 &phy_data); 2535 if (ret_val) 2536 return ret_val; 2537 2538 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 2539 /* Use 25MHz for both link down and 1000BASE-T for Tx clock */ 2540 phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ; 2541 2542 ret_val = em_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 2543 phy_data); 2544 if (ret_val) 2545 return ret_val; 2546 /* 2547 * Options: MDI/MDI-X = 0 (default) 0 - Auto for all speeds 1 2548 * - MDI mode 2 - MDI-X mode 3 - Auto for 1000Base-T only 2549 * (MDI-X for 10/100Base-T modes) 2550 */ 2551 ret_val = em_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, 2552 &phy_data); 2553 2554 if (ret_val) 2555 return ret_val; 2556 2557 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK; 2558 2559 switch (hw->mdix) { 2560 case 1: 2561 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI; 2562 break; 2563 case 2: 2564 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX; 2565 break; 2566 case 0: 2567 default: 2568 phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO; 2569 break; 2570 } 2571 /* 2572 * Options: disable_polarity_correction = 0 (default) 2573 * Automatic Correction for Reversed Cable Polarity 0 - 2574 * Disabled 1 - Enabled 2575 */ 2576 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 2577 if (hw->disable_polarity_correction == 1) 2578 phy_data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 2579 ret_val = em_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, 2580 phy_data); 2581 2582 if (ret_val) 2583 return ret_val; 2584 2585 /* SW Reset the PHY so all changes take effect */ 2586 ret_val = em_phy_reset(hw); 2587 if (ret_val) { 2588 DEBUGOUT("Error Resetting the PHY\n"); 2589 return ret_val; 2590 } 2591 } /* phy_reset_disable */ 2592 if (hw->mac_type == em_80003es2lan) { 2593 /* Bypass RX and TX FIFO's */ 2594 ret_val = em_write_kmrn_reg(hw, 2595 E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL, 2596 E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS | 2597 E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS); 2598 if (ret_val) 2599 return ret_val; 2600 2601 ret_val = em_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, 2602 &phy_data); 2603 if (ret_val) 2604 return ret_val; 2605 2606 phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG; 2607 ret_val = em_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, 2608 phy_data); 2609 2610 if (ret_val) 2611 return ret_val; 2612 2613 reg_data = E1000_READ_REG(hw, CTRL_EXT); 2614 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK); 2615 E1000_WRITE_REG(hw, CTRL_EXT, reg_data); 2616 2617 ret_val = em_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, 2618 &phy_data); 2619 if (ret_val) 2620 return ret_val; 2621 /* 2622 * Do not init these registers when the HW is in IAMT mode, 2623 * since the firmware will have already initialized them. We 2624 * only initialize them if the HW is not in IAMT mode. 2625 */ 2626 if (em_check_mng_mode(hw) == FALSE) { 2627 /* Enable Electrical Idle on the PHY */ 2628 phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; 2629 ret_val = em_write_phy_reg(hw, 2630 GG82563_PHY_PWR_MGMT_CTRL, phy_data); 2631 if (ret_val) 2632 return ret_val; 2633 2634 ret_val = em_read_phy_reg(hw, 2635 GG82563_PHY_KMRN_MODE_CTRL, &phy_data); 2636 if (ret_val) 2637 return ret_val; 2638 2639 phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 2640 ret_val = em_write_phy_reg(hw, 2641 GG82563_PHY_KMRN_MODE_CTRL, phy_data); 2642 2643 if (ret_val) 2644 return ret_val; 2645 } 2646 /* 2647 * Workaround: Disable padding in Kumeran interface in the 2648 * MAC and in the PHY to avoid CRC errors. 2649 */ 2650 ret_val = em_read_phy_reg(hw, GG82563_PHY_INBAND_CTRL, 2651 &phy_data); 2652 if (ret_val) 2653 return ret_val; 2654 phy_data |= GG82563_ICR_DIS_PADDING; 2655 ret_val = em_write_phy_reg(hw, GG82563_PHY_INBAND_CTRL, 2656 phy_data); 2657 if (ret_val) 2658 return ret_val; 2659 } 2660 return E1000_SUCCESS; 2661 } 2662 2663 /****************************************************************************** 2664 * Copper link setup for em_phy_m88 series. 2665 * 2666 * hw - Struct containing variables accessed by shared code 2667 *****************************************************************************/ 2668 static int32_t 2669 em_copper_link_mgp_setup(struct em_hw *hw) 2670 { 2671 int32_t ret_val; 2672 uint16_t phy_data; 2673 DEBUGFUNC("em_copper_link_mgp_setup"); 2674 2675 if (hw->phy_reset_disable) 2676 return E1000_SUCCESS; 2677 2678 /* disable lplu d0 during driver init */ 2679 if (hw->mac_type == em_pchlan || 2680 hw->mac_type == em_pch2lan || 2681 hw->mac_type == em_pch_lpt || 2682 hw->mac_type == em_pch_spt || 2683 hw->mac_type == em_pch_cnp) 2684 ret_val = em_set_lplu_state_pchlan(hw, FALSE); 2685 2686 /* Enable CRS on TX. This must be set for half-duplex operation. */ 2687 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 2688 if (ret_val) 2689 return ret_val; 2690 2691 if (hw->phy_id == M88E1141_E_PHY_ID) { 2692 phy_data |= 0x00000008; 2693 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 2694 phy_data); 2695 if (ret_val) 2696 return ret_val; 2697 2698 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 2699 &phy_data); 2700 if (ret_val) 2701 return ret_val; 2702 2703 phy_data &= ~M88E1000_PSCR_ASSERT_CRS_ON_TX; 2704 2705 } 2706 /* For BM PHY this bit is downshift enable */ 2707 else if (hw->phy_type != em_phy_bm) 2708 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 2709 /* 2710 * Options: MDI/MDI-X = 0 (default) 0 - Auto for all speeds 1 - MDI 2711 * mode 2 - MDI-X mode 3 - Auto for 1000Base-T only (MDI-X for 2712 * 10/100Base-T modes) 2713 */ 2714 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 2715 2716 switch (hw->mdix) { 2717 case 1: 2718 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 2719 break; 2720 case 2: 2721 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 2722 break; 2723 case 3: 2724 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 2725 break; 2726 case 0: 2727 default: 2728 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 2729 break; 2730 } 2731 /* 2732 * Options: disable_polarity_correction = 0 (default) Automatic 2733 * Correction for Reversed Cable Polarity 0 - Disabled 1 - Enabled 2734 */ 2735 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 2736 if (hw->disable_polarity_correction == 1) 2737 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 2738 2739 /* Enable downshift on BM (disabled by default) */ 2740 if (hw->phy_type == em_phy_bm) 2741 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT; 2742 2743 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 2744 if (ret_val) 2745 return ret_val; 2746 2747 if (((hw->phy_type == em_phy_m88) && 2748 (hw->phy_revision < M88E1011_I_REV_4) && 2749 (hw->phy_id != BME1000_E_PHY_ID)) || 2750 (hw->phy_type == em_phy_oem)) { 2751 /* 2752 * Force TX_CLK in the Extended PHY Specific Control Register 2753 * to 25MHz clock. 2754 */ 2755 ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 2756 &phy_data); 2757 if (ret_val) 2758 return ret_val; 2759 2760 if (hw->phy_type == em_phy_oem) { 2761 phy_data |= M88E1000_EPSCR_TX_TIME_CTRL; 2762 phy_data |= M88E1000_EPSCR_RX_TIME_CTRL; 2763 } 2764 phy_data |= M88E1000_EPSCR_TX_CLK_25; 2765 2766 if ((hw->phy_revision == E1000_REVISION_2) && 2767 (hw->phy_id == M88E1111_I_PHY_ID)) { 2768 /* Vidalia Phy, set the downshift counter to 5x */ 2769 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK); 2770 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; 2771 ret_val = em_write_phy_reg(hw, 2772 M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 2773 if (ret_val) 2774 return ret_val; 2775 } else { 2776 /* Configure Master and Slave downshift values */ 2777 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 2778 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 2779 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 2780 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 2781 ret_val = em_write_phy_reg(hw, 2782 M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 2783 if (ret_val) 2784 return ret_val; 2785 } 2786 } 2787 if ((hw->phy_type == em_phy_bm) && (hw->phy_revision == 1)) { 2788 /* 2789 * Set PHY page 0, register 29 to 0x0003 2790 * The next two writes are supposed to lower BER for gig 2791 * connection 2792 */ 2793 ret_val = em_write_phy_reg(hw, BM_REG_BIAS1, 0x0003); 2794 if (ret_val) 2795 return ret_val; 2796 2797 /* Set PHY page 0, register 30 to 0x0000 */ 2798 ret_val = em_write_phy_reg(hw, BM_REG_BIAS2, 0x0000); 2799 if (ret_val) 2800 return ret_val; 2801 } 2802 if (hw->phy_type == em_phy_82578) { 2803 ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 2804 &phy_data); 2805 if (ret_val) 2806 return ret_val; 2807 2808 /* 82578 PHY - set the downshift count to 1x. */ 2809 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE; 2810 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK; 2811 ret_val = em_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 2812 phy_data); 2813 if (ret_val) 2814 return ret_val; 2815 } 2816 /* SW Reset the PHY so all changes take effect */ 2817 ret_val = em_phy_reset(hw); 2818 if (ret_val) { 2819 DEBUGOUT("Error Resetting the PHY\n"); 2820 return ret_val; 2821 } 2822 return E1000_SUCCESS; 2823 } 2824 2825 /****************************************************************************** 2826 * Copper link setup for em_phy_82577 series. 2827 * 2828 * hw - Struct containing variables accessed by shared code 2829 *****************************************************************************/ 2830 static int32_t 2831 em_copper_link_82577_setup(struct em_hw *hw) 2832 { 2833 int32_t ret_val; 2834 uint16_t phy_data; 2835 uint32_t led_ctl; 2836 DEBUGFUNC("em_copper_link_82577_setup"); 2837 2838 if (hw->phy_reset_disable) 2839 return E1000_SUCCESS; 2840 2841 /* Enable CRS on TX for half-duplex operation. */ 2842 ret_val = em_read_phy_reg(hw, I82577_PHY_CFG_REG, &phy_data); 2843 if (ret_val) 2844 return ret_val; 2845 2846 phy_data |= I82577_PHY_CFG_ENABLE_CRS_ON_TX | 2847 I82577_PHY_CFG_ENABLE_DOWNSHIFT; 2848 2849 ret_val = em_write_phy_reg(hw, I82577_PHY_CFG_REG, phy_data); 2850 if (ret_val) 2851 return ret_val; 2852 2853 /* Wait 15ms for MAC to configure PHY from eeprom settings */ 2854 msec_delay(15); 2855 led_ctl = hw->ledctl_mode1; 2856 2857 /* disable lplu d0 during driver init */ 2858 ret_val = em_set_lplu_state_pchlan(hw, FALSE); 2859 if (ret_val) { 2860 DEBUGOUT("Error Disabling LPLU D0\n"); 2861 return ret_val; 2862 } 2863 2864 E1000_WRITE_REG(hw, LEDCTL, led_ctl); 2865 2866 return E1000_SUCCESS; 2867 } 2868 2869 static int32_t 2870 em_copper_link_82580_setup(struct em_hw *hw) 2871 { 2872 int32_t ret_val; 2873 uint16_t phy_data; 2874 2875 if (hw->phy_reset_disable) 2876 return E1000_SUCCESS; 2877 2878 ret_val = em_phy_reset(hw); 2879 if (ret_val) 2880 goto out; 2881 2882 /* Enable CRS on TX. This must be set for half-duplex operation. */ 2883 ret_val = em_read_phy_reg(hw, I82580_CFG_REG, &phy_data); 2884 if (ret_val) 2885 goto out; 2886 2887 phy_data |= I82580_CFG_ASSERT_CRS_ON_TX | 2888 I82580_CFG_ENABLE_DOWNSHIFT; 2889 2890 ret_val = em_write_phy_reg(hw, I82580_CFG_REG, phy_data); 2891 2892 out: 2893 return ret_val; 2894 } 2895 2896 static int32_t 2897 em_copper_link_rtl8211_setup(struct em_hw *hw) 2898 { 2899 int32_t ret_val; 2900 uint16_t phy_data; 2901 2902 DEBUGFUNC("em_copper_link_rtl8211_setup: begin"); 2903 2904 if (!hw) { 2905 return -1; 2906 } 2907 /* SW Reset the PHY so all changes take effect */ 2908 em_phy_hw_reset(hw); 2909 2910 /* Enable CRS on TX. This must be set for half-duplex operation. */ 2911 phy_data = 0; 2912 2913 ret_val = em_read_phy_reg_ex(hw, RGEPHY_CR, &phy_data); 2914 if (ret_val) { 2915 printf("Unable to read RGEPHY_CR register\n"); 2916 return ret_val; 2917 } 2918 DEBUGOUT3("RTL8211: Rx phy_id=%X addr=%X SPEC_CTRL=%X\n", hw->phy_id, 2919 hw->phy_addr, phy_data); 2920 phy_data |= RGEPHY_CR_ASSERT_CRS; 2921 2922 ret_val = em_write_phy_reg_ex(hw, RGEPHY_CR, phy_data); 2923 if (ret_val) { 2924 printf("Unable to write RGEPHY_CR register\n"); 2925 return ret_val; 2926 } 2927 2928 phy_data = 0; /* LED Control Register 0x18 */ 2929 ret_val = em_read_phy_reg_ex(hw, RGEPHY_LC, &phy_data); 2930 if (ret_val) { 2931 printf("Unable to read RGEPHY_LC register\n"); 2932 return ret_val; 2933 } 2934 2935 phy_data &= 0x80FF; /* bit-15=0 disable, clear bit 8-10 */ 2936 ret_val = em_write_phy_reg_ex(hw, RGEPHY_LC, phy_data); 2937 if (ret_val) { 2938 printf("Unable to write RGEPHY_LC register\n"); 2939 return ret_val; 2940 } 2941 /* LED Control and Definition Register 0x11, PHY spec status reg */ 2942 phy_data = 0; 2943 ret_val = em_read_phy_reg_ex(hw, RGEPHY_SR, &phy_data); 2944 if (ret_val) { 2945 printf("Unable to read RGEPHY_SR register\n"); 2946 return ret_val; 2947 } 2948 2949 phy_data |= 0x0010; /* LED active Low */ 2950 ret_val = em_write_phy_reg_ex(hw, RGEPHY_SR, phy_data); 2951 if (ret_val) { 2952 printf("Unable to write RGEPHY_SR register\n"); 2953 return ret_val; 2954 } 2955 2956 phy_data = 0; 2957 ret_val = em_read_phy_reg_ex(hw, RGEPHY_SR, &phy_data); 2958 if (ret_val) { 2959 printf("Unable to read RGEPHY_SR register\n"); 2960 return ret_val; 2961 } 2962 2963 /* Switch to Page2 */ 2964 phy_data = RGEPHY_PS_PAGE_2; 2965 ret_val = em_write_phy_reg_ex(hw, RGEPHY_PS, phy_data); 2966 if (ret_val) { 2967 printf("Unable to write PHY RGEPHY_PS register\n"); 2968 return ret_val; 2969 } 2970 2971 phy_data = 0x0000; 2972 ret_val = em_write_phy_reg_ex(hw, RGEPHY_LC_P2, phy_data); 2973 if (ret_val) { 2974 printf("Unable to write RGEPHY_LC_P2 register\n"); 2975 return ret_val; 2976 } 2977 usec_delay(5); 2978 2979 2980 /* LED Configuration Control Reg for setting for 0x1A Register */ 2981 phy_data = 0; 2982 ret_val = em_read_phy_reg_ex(hw, RGEPHY_LC_P2, &phy_data); 2983 if (ret_val) { 2984 printf("Unable to read RGEPHY_LC_P2 register\n"); 2985 return ret_val; 2986 } 2987 2988 phy_data &= 0xF000; 2989 phy_data |= 0x0F24; 2990 ret_val = em_write_phy_reg_ex(hw, RGEPHY_LC_P2, phy_data); 2991 if (ret_val) { 2992 printf("Unable to write RGEPHY_LC_P2 register\n"); 2993 return ret_val; 2994 } 2995 phy_data = 0; 2996 ret_val= em_read_phy_reg_ex(hw, RGEPHY_LC_P2, &phy_data); 2997 if (ret_val) { 2998 printf("Unable to read RGEPHY_LC_P2 register\n"); 2999 return ret_val; 3000 } 3001 DEBUGOUT1("RTL8211:ReadBack for check, LED_CFG->data=%X\n", phy_data); 3002 3003 3004 /* After setting Page2, go back to Page 0 */ 3005 phy_data = 0; 3006 ret_val = em_write_phy_reg_ex(hw, RGEPHY_PS, phy_data); 3007 if (ret_val) { 3008 printf("Unable to write PHY RGEPHY_PS register\n"); 3009 return ret_val; 3010 } 3011 3012 /* pulse streching= 42-84ms, blink rate=84mm */ 3013 phy_data = 0x140 | RGEPHY_LC_PULSE_42MS | RGEPHY_LC_LINK | 3014 RGEPHY_LC_DUPLEX | RGEPHY_LC_RX; 3015 3016 ret_val = em_write_phy_reg_ex(hw, RGEPHY_LC, phy_data); 3017 if (ret_val) { 3018 printf("Unable to write RGEPHY_LC register\n"); 3019 return ret_val; 3020 } 3021 return E1000_SUCCESS; 3022 } 3023 3024 /****************************************************************************** 3025 * Setup auto-negotiation and flow control advertisements, 3026 * and then perform auto-negotiation. 3027 * 3028 * hw - Struct containing variables accessed by shared code 3029 *****************************************************************************/ 3030 int32_t 3031 em_copper_link_autoneg(struct em_hw *hw) 3032 { 3033 int32_t ret_val; 3034 uint16_t phy_data; 3035 DEBUGFUNC("em_copper_link_autoneg"); 3036 /* 3037 * Perform some bounds checking on the hw->autoneg_advertised 3038 * parameter. If this variable is zero, then set it to the default. 3039 */ 3040 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT; 3041 /* 3042 * If autoneg_advertised is zero, we assume it was not defaulted by 3043 * the calling code so we set to advertise full capability. 3044 */ 3045 if (hw->autoneg_advertised == 0) 3046 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 3047 3048 /* IFE phy only supports 10/100 */ 3049 if (hw->phy_type == em_phy_ife) 3050 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL; 3051 3052 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); 3053 ret_val = em_phy_setup_autoneg(hw); 3054 if (ret_val) { 3055 DEBUGOUT("Error Setting up Auto-Negotiation\n"); 3056 return ret_val; 3057 } 3058 DEBUGOUT("Restarting Auto-Neg\n"); 3059 /* 3060 * Restart auto-negotiation by setting the Auto Neg Enable bit and 3061 * the Auto Neg Restart bit in the PHY control register. 3062 */ 3063 ret_val = em_read_phy_reg(hw, PHY_CTRL, &phy_data); 3064 if (ret_val) 3065 return ret_val; 3066 3067 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 3068 ret_val = em_write_phy_reg(hw, PHY_CTRL, phy_data); 3069 if (ret_val) 3070 return ret_val; 3071 /* 3072 * Does the user want to wait for Auto-Neg to complete here, or check 3073 * at a later time (for example, callback routine). 3074 */ 3075 if (hw->wait_autoneg_complete) { 3076 ret_val = em_wait_autoneg(hw); 3077 if (ret_val) { 3078 DEBUGOUT("Error while waiting for autoneg to complete\n" 3079 ); 3080 return ret_val; 3081 } 3082 } 3083 hw->get_link_status = TRUE; 3084 3085 return E1000_SUCCESS; 3086 } 3087 3088 /****************************************************************************** 3089 * Config the MAC and the PHY after link is up. 3090 * 1) Set up the MAC to the current PHY speed/duplex 3091 * if we are on 82543. If we 3092 * are on newer silicon, we only need to configure 3093 * collision distance in the Transmit Control Register. 3094 * 2) Set up flow control on the MAC to that established with 3095 * the link partner. 3096 * 3) Config DSP to improve Gigabit link quality for some PHY revisions. 3097 * 3098 * hw - Struct containing variables accessed by shared code 3099 *****************************************************************************/ 3100 int32_t 3101 em_copper_link_postconfig(struct em_hw *hw) 3102 { 3103 int32_t ret_val; 3104 DEBUGFUNC("em_copper_link_postconfig"); 3105 3106 if (hw->mac_type >= em_82544 && 3107 hw->mac_type != em_icp_xxxx) { 3108 em_config_collision_dist(hw); 3109 } else { 3110 ret_val = em_config_mac_to_phy(hw); 3111 if (ret_val) { 3112 DEBUGOUT("Error configuring MAC to PHY settings\n"); 3113 return ret_val; 3114 } 3115 } 3116 ret_val = em_config_fc_after_link_up(hw); 3117 if (ret_val) { 3118 DEBUGOUT("Error Configuring Flow Control\n"); 3119 return ret_val; 3120 } 3121 /* Config DSP to improve Giga link quality */ 3122 if (hw->phy_type == em_phy_igp) { 3123 ret_val = em_config_dsp_after_link_change(hw, TRUE); 3124 if (ret_val) { 3125 DEBUGOUT("Error Configuring DSP after link up\n"); 3126 return ret_val; 3127 } 3128 } 3129 return E1000_SUCCESS; 3130 } 3131 3132 /****************************************************************************** 3133 * Detects which PHY is present and setup the speed and duplex 3134 * 3135 * hw - Struct containing variables accessed by shared code 3136 *****************************************************************************/ 3137 static int32_t 3138 em_setup_copper_link(struct em_hw *hw) 3139 { 3140 int32_t ret_val; 3141 uint16_t i; 3142 uint16_t phy_data; 3143 uint16_t reg_data; 3144 DEBUGFUNC("em_setup_copper_link"); 3145 3146 switch (hw->mac_type) { 3147 case em_80003es2lan: 3148 case em_ich8lan: 3149 case em_ich9lan: 3150 case em_ich10lan: 3151 case em_pchlan: 3152 case em_pch2lan: 3153 case em_pch_lpt: 3154 case em_pch_spt: 3155 case em_pch_cnp: 3156 /* 3157 * Set the mac to wait the maximum time between each 3158 * iteration and increase the max iterations when polling the 3159 * phy; this fixes erroneous timeouts at 10Mbps. 3160 */ 3161 ret_val = em_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF); 3162 if (ret_val) 3163 return ret_val; 3164 ret_val = em_read_kmrn_reg(hw, GG82563_REG(0x34, 9), 3165 ®_data); 3166 if (ret_val) 3167 return ret_val; 3168 reg_data |= 0x3F; 3169 ret_val = em_write_kmrn_reg(hw, GG82563_REG(0x34, 9), 3170 reg_data); 3171 if (ret_val) 3172 return ret_val; 3173 default: 3174 break; 3175 } 3176 3177 /* Check if it is a valid PHY and set PHY mode if necessary. */ 3178 ret_val = em_copper_link_preconfig(hw); 3179 if (ret_val) 3180 return ret_val; 3181 3182 switch (hw->mac_type) { 3183 case em_80003es2lan: 3184 /* Kumeran registers are written-only */ 3185 reg_data = 3186 E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT; 3187 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING; 3188 ret_val = em_write_kmrn_reg(hw, 3189 E1000_KUMCTRLSTA_OFFSET_INB_CTRL, reg_data); 3190 if (ret_val) 3191 return ret_val; 3192 break; 3193 default: 3194 break; 3195 } 3196 3197 if (hw->phy_type == em_phy_igp || 3198 hw->phy_type == em_phy_igp_3 || 3199 hw->phy_type == em_phy_igp_2) { 3200 ret_val = em_copper_link_igp_setup(hw); 3201 if (ret_val) 3202 return ret_val; 3203 } else if (hw->phy_type == em_phy_m88 || 3204 hw->phy_type == em_phy_bm || 3205 hw->phy_type == em_phy_oem || 3206 hw->phy_type == em_phy_82578) { 3207 ret_val = em_copper_link_mgp_setup(hw); 3208 if (ret_val) 3209 return ret_val; 3210 } else if (hw->phy_type == em_phy_gg82563) { 3211 ret_val = em_copper_link_ggp_setup(hw); 3212 if (ret_val) 3213 return ret_val; 3214 } else if (hw->phy_type == em_phy_82577 || 3215 hw->phy_type == em_phy_82579 || 3216 hw->phy_type == em_phy_i217) { 3217 ret_val = em_copper_link_82577_setup(hw); 3218 if (ret_val) 3219 return ret_val; 3220 } else if (hw->phy_type == em_phy_82580) { 3221 ret_val = em_copper_link_82580_setup(hw); 3222 if (ret_val) 3223 return ret_val; 3224 } else if (hw->phy_type == em_phy_rtl8211) { 3225 ret_val = em_copper_link_rtl8211_setup(hw); 3226 if (ret_val) 3227 return ret_val; 3228 } 3229 if (hw->autoneg) { 3230 /* 3231 * Setup autoneg and flow control advertisement and perform 3232 * autonegotiation 3233 */ 3234 ret_val = em_copper_link_autoneg(hw); 3235 if (ret_val) 3236 return ret_val; 3237 } else { 3238 /* 3239 * PHY will be set to 10H, 10F, 100H,or 100F depending on 3240 * value from forced_speed_duplex. 3241 */ 3242 DEBUGOUT("Forcing speed and duplex\n"); 3243 ret_val = em_phy_force_speed_duplex(hw); 3244 if (ret_val) { 3245 DEBUGOUT("Error Forcing Speed and Duplex\n"); 3246 return ret_val; 3247 } 3248 } 3249 /* 3250 * Check link status. Wait up to 100 microseconds for link to become 3251 * valid. 3252 */ 3253 for (i = 0; i < 10; i++) { 3254 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 3255 if (ret_val) 3256 return ret_val; 3257 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 3258 if (ret_val) 3259 return ret_val; 3260 3261 hw->icp_xxxx_is_link_up = (phy_data & MII_SR_LINK_STATUS) != 0; 3262 3263 if (phy_data & MII_SR_LINK_STATUS) { 3264 /* Config the MAC and PHY after link is up */ 3265 ret_val = em_copper_link_postconfig(hw); 3266 if (ret_val) 3267 return ret_val; 3268 3269 DEBUGOUT("Valid link established!!!\n"); 3270 return E1000_SUCCESS; 3271 } 3272 usec_delay(10); 3273 } 3274 3275 DEBUGOUT("Unable to establish link!!!\n"); 3276 return E1000_SUCCESS; 3277 } 3278 3279 /****************************************************************************** 3280 * Configure the MAC-to-PHY interface for 10/100Mbps 3281 * 3282 * hw - Struct containing variables accessed by shared code 3283 *****************************************************************************/ 3284 static int32_t 3285 em_configure_kmrn_for_10_100(struct em_hw *hw, uint16_t duplex) 3286 { 3287 int32_t ret_val = E1000_SUCCESS; 3288 uint32_t tipg; 3289 uint16_t reg_data; 3290 DEBUGFUNC("em_configure_kmrn_for_10_100"); 3291 3292 reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT; 3293 ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL, 3294 reg_data); 3295 if (ret_val) 3296 return ret_val; 3297 3298 /* Configure Transmit Inter-Packet Gap */ 3299 tipg = E1000_READ_REG(hw, TIPG); 3300 tipg &= ~E1000_TIPG_IPGT_MASK; 3301 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100; 3302 E1000_WRITE_REG(hw, TIPG, tipg); 3303 3304 ret_val = em_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); 3305 3306 if (ret_val) 3307 return ret_val; 3308 3309 if (duplex == HALF_DUPLEX) 3310 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER; 3311 else 3312 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 3313 3314 ret_val = em_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 3315 3316 return ret_val; 3317 } 3318 3319 static int32_t 3320 em_configure_kmrn_for_1000(struct em_hw *hw) 3321 { 3322 int32_t ret_val = E1000_SUCCESS; 3323 uint16_t reg_data; 3324 uint32_t tipg; 3325 DEBUGFUNC("em_configure_kmrn_for_1000"); 3326 3327 reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT; 3328 ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL, 3329 reg_data); 3330 if (ret_val) 3331 return ret_val; 3332 3333 /* Configure Transmit Inter-Packet Gap */ 3334 tipg = E1000_READ_REG(hw, TIPG); 3335 tipg &= ~E1000_TIPG_IPGT_MASK; 3336 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; 3337 E1000_WRITE_REG(hw, TIPG, tipg); 3338 3339 ret_val = em_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); 3340 3341 if (ret_val) 3342 return ret_val; 3343 3344 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 3345 ret_val = em_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 3346 3347 return ret_val; 3348 } 3349 3350 /****************************************************************************** 3351 * Configures PHY autoneg and flow control advertisement settings 3352 * 3353 * hw - Struct containing variables accessed by shared code 3354 *****************************************************************************/ 3355 int32_t 3356 em_phy_setup_autoneg(struct em_hw *hw) 3357 { 3358 int32_t ret_val; 3359 uint16_t mii_autoneg_adv_reg; 3360 uint16_t mii_1000t_ctrl_reg; 3361 DEBUGFUNC("em_phy_setup_autoneg"); 3362 3363 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 3364 ret_val = em_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 3365 if (ret_val) 3366 return ret_val; 3367 3368 if (hw->phy_type != em_phy_ife) { 3369 /* Read the MII 1000Base-T Control Register (Address 9). */ 3370 ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, 3371 &mii_1000t_ctrl_reg); 3372 if (ret_val) 3373 return ret_val; 3374 } else 3375 mii_1000t_ctrl_reg = 0; 3376 /* 3377 * Need to parse both autoneg_advertised and fc and set up the 3378 * appropriate PHY registers. First we will parse for 3379 * autoneg_advertised software override. Since we can advertise a 3380 * plethora of combinations, we need to check each bit individually. 3381 */ 3382 /* 3383 * First we clear all the 10/100 mb speed bits in the Auto-Neg 3384 * Advertisement Register (Address 4) and the 1000 mb speed bits in 3385 * the 1000Base-T Control Register (Address 9). 3386 */ 3387 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK; 3388 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK; 3389 3390 DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised); 3391 3392 /* Do we want to advertise 10 Mb Half Duplex? */ 3393 if (hw->autoneg_advertised & ADVERTISE_10_HALF) { 3394 DEBUGOUT("Advertise 10mb Half duplex\n"); 3395 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 3396 } 3397 /* Do we want to advertise 10 Mb Full Duplex? */ 3398 if (hw->autoneg_advertised & ADVERTISE_10_FULL) { 3399 DEBUGOUT("Advertise 10mb Full duplex\n"); 3400 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 3401 } 3402 /* Do we want to advertise 100 Mb Half Duplex? */ 3403 if (hw->autoneg_advertised & ADVERTISE_100_HALF) { 3404 DEBUGOUT("Advertise 100mb Half duplex\n"); 3405 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 3406 } 3407 /* Do we want to advertise 100 Mb Full Duplex? */ 3408 if (hw->autoneg_advertised & ADVERTISE_100_FULL) { 3409 DEBUGOUT("Advertise 100mb Full duplex\n"); 3410 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 3411 } 3412 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 3413 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) { 3414 DEBUGOUT("Advertise 1000mb Half duplex requested, request" 3415 " denied!\n"); 3416 } 3417 /* Do we want to advertise 1000 Mb Full Duplex? */ 3418 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) { 3419 DEBUGOUT("Advertise 1000mb Full duplex\n"); 3420 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 3421 if (hw->phy_type == em_phy_ife) { 3422 DEBUGOUT("em_phy_ife is a 10/100 PHY. Gigabit speed is" 3423 " not supported.\n"); 3424 } 3425 } 3426 /* 3427 * Check for a software override of the flow control settings, and 3428 * setup the PHY advertisement registers accordingly. If 3429 * auto-negotiation is enabled, then software will have to set the 3430 * "PAUSE" bits to the correct value in the Auto-Negotiation 3431 * Advertisement Register (PHY_AUTONEG_ADV) and re-start 3432 * auto-negotiation. 3433 * 3434 * The possible values of the "fc" parameter are: 0: Flow control is 3435 * completely disabled 1: Rx flow control is enabled (we can receive 3436 * pause frames but not send pause frames). 2: Tx flow control is 3437 * enabled (we can send pause frames but we do not support receiving 3438 * pause frames). 3: Both Rx and TX flow control (symmetric) are 3439 * enabled. other: No software override. The flow control 3440 * configuration in the EEPROM is used. 3441 */ 3442 switch (hw->fc) { 3443 case E1000_FC_NONE: /* 0 */ 3444 /* 3445 * Flow control (RX & TX) is completely disabled by a 3446 * software over-ride. 3447 */ 3448 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 3449 break; 3450 case E1000_FC_RX_PAUSE:/* 1 */ 3451 /* 3452 * RX Flow control is enabled, and TX Flow control is 3453 * disabled, by a software over-ride. 3454 */ 3455 /* 3456 * Since there really isn't a way to advertise that we are 3457 * capable of RX Pause ONLY, we will advertise that we 3458 * support both symmetric and asymmetric RX PAUSE. Later (in 3459 * em_config_fc_after_link_up) we will disable the hw's 3460 * ability to send PAUSE frames. 3461 */ 3462 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 3463 break; 3464 case E1000_FC_TX_PAUSE:/* 2 */ 3465 /* 3466 * TX Flow control is enabled, and RX Flow control is 3467 * disabled, by a software over-ride. 3468 */ 3469 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 3470 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 3471 break; 3472 case E1000_FC_FULL: /* 3 */ 3473 /* 3474 * Flow control (both RX and TX) is enabled by a software 3475 * over-ride. 3476 */ 3477 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 3478 break; 3479 default: 3480 DEBUGOUT("Flow control param set incorrectly\n"); 3481 return -E1000_ERR_CONFIG; 3482 } 3483 3484 ret_val = em_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 3485 if (ret_val) 3486 return ret_val; 3487 3488 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 3489 3490 if (hw->phy_type != em_phy_ife) { 3491 ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL, 3492 mii_1000t_ctrl_reg); 3493 if (ret_val) 3494 return ret_val; 3495 } 3496 return E1000_SUCCESS; 3497 } 3498 /****************************************************************************** 3499 * Force PHY speed and duplex settings to hw->forced_speed_duplex 3500 * 3501 * hw - Struct containing variables accessed by shared code 3502 *****************************************************************************/ 3503 static int32_t 3504 em_phy_force_speed_duplex(struct em_hw *hw) 3505 { 3506 uint32_t ctrl; 3507 int32_t ret_val; 3508 uint16_t mii_ctrl_reg; 3509 uint16_t mii_status_reg; 3510 uint16_t phy_data; 3511 uint16_t i; 3512 DEBUGFUNC("em_phy_force_speed_duplex"); 3513 3514 /* Turn off Flow control if we are forcing speed and duplex. */ 3515 hw->fc = E1000_FC_NONE; 3516 3517 DEBUGOUT1("hw->fc = %d\n", hw->fc); 3518 3519 /* Read the Device Control Register. */ 3520 ctrl = E1000_READ_REG(hw, CTRL); 3521 3522 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */ 3523 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 3524 ctrl &= ~(DEVICE_SPEED_MASK); 3525 3526 /* Clear the Auto Speed Detect Enable bit. */ 3527 ctrl &= ~E1000_CTRL_ASDE; 3528 3529 /* Read the MII Control Register. */ 3530 ret_val = em_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg); 3531 if (ret_val) 3532 return ret_val; 3533 3534 /* We need to disable autoneg in order to force link and duplex. */ 3535 3536 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN; 3537 3538 /* Are we forcing Full or Half Duplex? */ 3539 if (hw->forced_speed_duplex == em_100_full || 3540 hw->forced_speed_duplex == em_10_full) { 3541 /* 3542 * We want to force full duplex so we SET the full duplex 3543 * bits in the Device and MII Control Registers. 3544 */ 3545 ctrl |= E1000_CTRL_FD; 3546 mii_ctrl_reg |= MII_CR_FULL_DUPLEX; 3547 DEBUGOUT("Full Duplex\n"); 3548 } else { 3549 /* 3550 * We want to force half duplex so we CLEAR the full duplex 3551 * bits in the Device and MII Control Registers. 3552 */ 3553 ctrl &= ~E1000_CTRL_FD; 3554 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX; 3555 DEBUGOUT("Half Duplex\n"); 3556 } 3557 3558 /* Are we forcing 100Mbps??? */ 3559 if (hw->forced_speed_duplex == em_100_full || 3560 hw->forced_speed_duplex == em_100_half) { 3561 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */ 3562 ctrl |= E1000_CTRL_SPD_100; 3563 mii_ctrl_reg |= MII_CR_SPEED_100; 3564 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); 3565 DEBUGOUT("Forcing 100mb "); 3566 } else { 3567 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */ 3568 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 3569 mii_ctrl_reg |= MII_CR_SPEED_10; 3570 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); 3571 DEBUGOUT("Forcing 10mb "); 3572 } 3573 3574 em_config_collision_dist(hw); 3575 3576 /* Write the configured values back to the Device Control Reg. */ 3577 E1000_WRITE_REG(hw, CTRL, ctrl); 3578 3579 if ((hw->phy_type == em_phy_m88) || 3580 (hw->phy_type == em_phy_gg82563) || 3581 (hw->phy_type == em_phy_bm) || 3582 (hw->phy_type == em_phy_oem || 3583 (hw->phy_type == em_phy_82578))) { 3584 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 3585 &phy_data); 3586 if (ret_val) 3587 return ret_val; 3588 /* 3589 * Clear Auto-Crossover to force MDI manually. M88E1000 3590 * requires MDI forced whenever speed are duplex are forced. 3591 */ 3592 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 3593 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 3594 phy_data); 3595 if (ret_val) 3596 return ret_val; 3597 3598 DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data); 3599 3600 /* Need to reset the PHY or these changes will be ignored */ 3601 mii_ctrl_reg |= MII_CR_RESET; 3602 3603 } 3604 else if (hw->phy_type == em_phy_rtl8211) { 3605 ret_val = em_read_phy_reg_ex(hw, RGEPHY_CR, &phy_data); 3606 if(ret_val) { 3607 printf("Unable to read RGEPHY_CR register\n" 3608 ); 3609 return ret_val; 3610 } 3611 3612 /* 3613 * Clear Auto-Crossover to force MDI manually. RTL8211 requires 3614 * MDI forced whenever speed are duplex are forced. 3615 */ 3616 3617 phy_data |= RGEPHY_CR_MDI_MASK; // enable MDIX 3618 ret_val = em_write_phy_reg_ex(hw, RGEPHY_CR, phy_data); 3619 if(ret_val) { 3620 printf("Unable to write RGEPHY_CR register\n"); 3621 return ret_val; 3622 } 3623 mii_ctrl_reg |= MII_CR_RESET; 3624 3625 } 3626 /* Disable MDI-X support for 10/100 */ 3627 else if (hw->phy_type == em_phy_ife) { 3628 ret_val = em_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data); 3629 if (ret_val) 3630 return ret_val; 3631 3632 phy_data &= ~IFE_PMC_AUTO_MDIX; 3633 phy_data &= ~IFE_PMC_FORCE_MDIX; 3634 3635 ret_val = em_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, phy_data); 3636 if (ret_val) 3637 return ret_val; 3638 } else { 3639 /* 3640 * Clear Auto-Crossover to force MDI manually. IGP requires 3641 * MDI forced whenever speed or duplex are forced. 3642 */ 3643 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, 3644 &phy_data); 3645 if (ret_val) 3646 return ret_val; 3647 3648 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 3649 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 3650 3651 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, 3652 phy_data); 3653 if (ret_val) 3654 return ret_val; 3655 } 3656 3657 /* Write back the modified PHY MII control register. */ 3658 ret_val = em_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg); 3659 if (ret_val) 3660 return ret_val; 3661 3662 usec_delay(1); 3663 /* 3664 * The wait_autoneg_complete flag may be a little misleading here. 3665 * Since we are forcing speed and duplex, Auto-Neg is not enabled. 3666 * But we do want to delay for a period while forcing only so we 3667 * don't generate false No Link messages. So we will wait here only 3668 * if the user has set wait_autoneg_complete to 1, which is the 3669 * default. 3670 */ 3671 if (hw->wait_autoneg_complete) { 3672 /* We will wait for autoneg to complete. */ 3673 DEBUGOUT("Waiting for forced speed/duplex link.\n"); 3674 mii_status_reg = 0; 3675 /* 3676 * We will wait for autoneg to complete or 4.5 seconds to 3677 * expire. 3678 */ 3679 for (i = PHY_FORCE_TIME; i > 0; i--) { 3680 /* 3681 * Read the MII Status Register and wait for Auto-Neg 3682 * Complete bit to be set. 3683 */ 3684 ret_val = em_read_phy_reg(hw, PHY_STATUS, 3685 &mii_status_reg); 3686 if (ret_val) 3687 return ret_val; 3688 3689 ret_val = em_read_phy_reg(hw, PHY_STATUS, 3690 &mii_status_reg); 3691 if (ret_val) 3692 return ret_val; 3693 3694 if (mii_status_reg & MII_SR_LINK_STATUS) 3695 break; 3696 msec_delay(100); 3697 } 3698 if ((i == 0) && 3699 ((hw->phy_type == em_phy_m88) || 3700 (hw->phy_type == em_phy_gg82563) || 3701 (hw->phy_type == em_phy_bm))) { 3702 /* 3703 * We didn't get link. Reset the DSP and wait again 3704 * for link. 3705 */ 3706 ret_val = em_phy_reset_dsp(hw); 3707 if (ret_val) { 3708 DEBUGOUT("Error Resetting PHY DSP\n"); 3709 return ret_val; 3710 } 3711 } 3712 /* 3713 * This loop will early-out if the link condition has been 3714 * met. 3715 */ 3716 for (i = PHY_FORCE_TIME; i > 0; i--) { 3717 if (mii_status_reg & MII_SR_LINK_STATUS) 3718 break; 3719 msec_delay(100); 3720 /* 3721 * Read the MII Status Register and wait for Auto-Neg 3722 * Complete bit to be set. 3723 */ 3724 ret_val = em_read_phy_reg(hw, PHY_STATUS, 3725 &mii_status_reg); 3726 if (ret_val) 3727 return ret_val; 3728 3729 ret_val = em_read_phy_reg(hw, PHY_STATUS, 3730 &mii_status_reg); 3731 if (ret_val) 3732 return ret_val; 3733 } 3734 } 3735 if (hw->phy_type == em_phy_m88 || 3736 hw->phy_type == em_phy_bm || 3737 hw->phy_type == em_phy_oem) { 3738 /* 3739 * Because we reset the PHY above, we need to re-force TX_CLK 3740 * in the Extended PHY Specific Control Register to 25MHz 3741 * clock. This value defaults back to a 2.5MHz clock when 3742 * the PHY is reset. 3743 */ 3744 ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 3745 &phy_data); 3746 if (ret_val) 3747 return ret_val; 3748 3749 phy_data |= M88E1000_EPSCR_TX_CLK_25; 3750 ret_val = em_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 3751 phy_data); 3752 if (ret_val) 3753 return ret_val; 3754 /* 3755 * In addition, because of the s/w reset above, we need to 3756 * enable CRS on TX. This must be set for both full and half 3757 * duplex operation. 3758 */ 3759 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 3760 &phy_data); 3761 if (ret_val) 3762 return ret_val; 3763 3764 if (hw->phy_id == M88E1141_E_PHY_ID) 3765 phy_data &= ~M88E1000_PSCR_ASSERT_CRS_ON_TX; 3766 else 3767 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 3768 3769 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 3770 phy_data); 3771 if (ret_val) 3772 return ret_val; 3773 3774 if ((hw->mac_type == em_82544 || hw->mac_type == em_82543) && 3775 (!hw->autoneg) && (hw->forced_speed_duplex == em_10_full || 3776 hw->forced_speed_duplex == em_10_half)) { 3777 ret_val = em_polarity_reversal_workaround(hw); 3778 if (ret_val) 3779 return ret_val; 3780 } 3781 } else if (hw->phy_type == em_phy_rtl8211) { 3782 /* 3783 * In addition, because of the s/w reset above, we need to enable 3784 * CRX on TX. This must be set for both full and half duplex 3785 * operation. 3786 */ 3787 3788 ret_val = em_read_phy_reg_ex(hw, RGEPHY_CR, &phy_data); 3789 if(ret_val) { 3790 printf("Unable to read RGEPHY_CR register\n"); 3791 return ret_val; 3792 } 3793 3794 phy_data &= ~RGEPHY_CR_ASSERT_CRS; 3795 ret_val = em_write_phy_reg_ex(hw, RGEPHY_CR, phy_data); 3796 if(ret_val) { 3797 printf("Unable to write RGEPHY_CR register\n"); 3798 return ret_val; 3799 } 3800 } else if (hw->phy_type == em_phy_gg82563) { 3801 /* 3802 * The TX_CLK of the Extended PHY Specific Control Register 3803 * defaults to 2.5MHz on a reset. We need to re-force it 3804 * back to 25MHz, if we're not in a forced 10/duplex 3805 * configuration. 3806 */ 3807 ret_val = em_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 3808 &phy_data); 3809 if (ret_val) 3810 return ret_val; 3811 3812 phy_data &= ~GG82563_MSCR_TX_CLK_MASK; 3813 if ((hw->forced_speed_duplex == em_10_full) || 3814 (hw->forced_speed_duplex == em_10_half)) 3815 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ; 3816 else 3817 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25MHZ; 3818 3819 /* Also due to the reset, we need to enable CRS on Tx. */ 3820 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 3821 3822 ret_val = em_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 3823 phy_data); 3824 if (ret_val) 3825 return ret_val; 3826 } 3827 return E1000_SUCCESS; 3828 } 3829 3830 /****************************************************************************** 3831 * Sets the collision distance in the Transmit Control register 3832 * 3833 * hw - Struct containing variables accessed by shared code 3834 * 3835 * Link should have been established previously. Reads the speed and duplex 3836 * information from the Device Status register. 3837 *****************************************************************************/ 3838 void 3839 em_config_collision_dist(struct em_hw *hw) 3840 { 3841 uint32_t tctl, coll_dist; 3842 DEBUGFUNC("em_config_collision_dist"); 3843 3844 if (hw->mac_type < em_82543) 3845 coll_dist = E1000_COLLISION_DISTANCE_82542; 3846 else 3847 coll_dist = E1000_COLLISION_DISTANCE; 3848 3849 tctl = E1000_READ_REG(hw, TCTL); 3850 3851 tctl &= ~E1000_TCTL_COLD; 3852 tctl |= coll_dist << E1000_COLD_SHIFT; 3853 3854 E1000_WRITE_REG(hw, TCTL, tctl); 3855 E1000_WRITE_FLUSH(hw); 3856 } 3857 3858 /****************************************************************************** 3859 * Sets MAC speed and duplex settings to reflect the those in the PHY 3860 * 3861 * hw - Struct containing variables accessed by shared code 3862 * mii_reg - data to write to the MII control register 3863 * 3864 * The contents of the PHY register containing the needed information need to 3865 * be passed in. 3866 *****************************************************************************/ 3867 static int32_t 3868 em_config_mac_to_phy(struct em_hw *hw) 3869 { 3870 uint32_t ctrl; 3871 int32_t ret_val; 3872 uint16_t phy_data; 3873 DEBUGFUNC("em_config_mac_to_phy"); 3874 /* 3875 * 82544 or newer MAC, Auto Speed Detection takes care of MAC 3876 * speed/duplex configuration. 3877 */ 3878 if (hw->mac_type >= em_82544 3879 && hw->mac_type != em_icp_xxxx) 3880 return E1000_SUCCESS; 3881 /* 3882 * Read the Device Control Register and set the bits to Force Speed 3883 * and Duplex. 3884 */ 3885 ctrl = E1000_READ_REG(hw, CTRL); 3886 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 3887 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); 3888 /* 3889 * Set up duplex in the Device Control and Transmit Control registers 3890 * depending on negotiated values. 3891 */ 3892 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 3893 if (ret_val) 3894 return ret_val; 3895 3896 if (phy_data & M88E1000_PSSR_DPLX) 3897 ctrl |= E1000_CTRL_FD; 3898 else 3899 ctrl &= ~E1000_CTRL_FD; 3900 3901 em_config_collision_dist(hw); 3902 /* 3903 * Set up speed in the Device Control register depending on 3904 * negotiated values. 3905 */ 3906 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) 3907 ctrl |= E1000_CTRL_SPD_1000; 3908 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) 3909 ctrl |= E1000_CTRL_SPD_100; 3910 3911 /* Write the configured values back to the Device Control Reg. */ 3912 E1000_WRITE_REG(hw, CTRL, ctrl); 3913 return E1000_SUCCESS; 3914 } 3915 3916 /****************************************************************************** 3917 * Forces the MAC's flow control settings. 3918 * 3919 * hw - Struct containing variables accessed by shared code 3920 * 3921 * Sets the TFCE and RFCE bits in the device control register to reflect 3922 * the adapter settings. TFCE and RFCE need to be explicitly set by 3923 * software when a Copper PHY is used because autonegotiation is managed 3924 * by the PHY rather than the MAC. Software must also configure these 3925 * bits when link is forced on a fiber connection. 3926 *****************************************************************************/ 3927 int32_t 3928 em_force_mac_fc(struct em_hw *hw) 3929 { 3930 uint32_t ctrl; 3931 DEBUGFUNC("em_force_mac_fc"); 3932 3933 /* Get the current configuration of the Device Control Register */ 3934 ctrl = E1000_READ_REG(hw, CTRL); 3935 /* 3936 * Because we didn't get link via the internal auto-negotiation 3937 * mechanism (we either forced link or we got link via PHY auto-neg), 3938 * we have to manually enable/disable transmit an receive flow 3939 * control. 3940 * 3941 * The "Case" statement below enables/disable flow control according to 3942 * the "hw->fc" parameter. 3943 * 3944 * The possible values of the "fc" parameter are: 0: Flow control is 3945 * completely disabled 1: Rx flow control is enabled (we can receive 3946 * pause frames but not send pause frames). 2: Tx flow control is 3947 * enabled (we can send pause frames frames but we do not receive 3948 * pause frames). 3: Both Rx and TX flow control (symmetric) is 3949 * enabled. other: No other values should be possible at this point. 3950 */ 3951 3952 switch (hw->fc) { 3953 case E1000_FC_NONE: 3954 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 3955 break; 3956 case E1000_FC_RX_PAUSE: 3957 ctrl &= (~E1000_CTRL_TFCE); 3958 ctrl |= E1000_CTRL_RFCE; 3959 break; 3960 case E1000_FC_TX_PAUSE: 3961 ctrl &= (~E1000_CTRL_RFCE); 3962 ctrl |= E1000_CTRL_TFCE; 3963 break; 3964 case E1000_FC_FULL: 3965 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 3966 break; 3967 default: 3968 DEBUGOUT("Flow control param set incorrectly\n"); 3969 return -E1000_ERR_CONFIG; 3970 } 3971 3972 /* Disable TX Flow Control for 82542 (rev 2.0) */ 3973 if (hw->mac_type == em_82542_rev2_0) 3974 ctrl &= (~E1000_CTRL_TFCE); 3975 3976 E1000_WRITE_REG(hw, CTRL, ctrl); 3977 return E1000_SUCCESS; 3978 } 3979 /****************************************************************************** 3980 * Configures flow control settings after link is established 3981 * 3982 * hw - Struct containing variables accessed by shared code 3983 * 3984 * Should be called immediately after a valid link has been established. 3985 * Forces MAC flow control settings if link was forced. When in MII/GMII mode 3986 * and autonegotiation is enabled, the MAC flow control settings will be set 3987 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE 3988 * and RFCE bits will be automatically set to the negotiated flow control mode. 3989 *****************************************************************************/ 3990 STATIC int32_t 3991 em_config_fc_after_link_up(struct em_hw *hw) 3992 { 3993 int32_t ret_val; 3994 uint16_t mii_status_reg; 3995 uint16_t mii_nway_adv_reg; 3996 uint16_t mii_nway_lp_ability_reg; 3997 uint16_t speed; 3998 uint16_t duplex; 3999 DEBUGFUNC("em_config_fc_after_link_up"); 4000 /* 4001 * Check for the case where we have fiber media and auto-neg failed 4002 * so we had to force link. In this case, we need to force the 4003 * configuration of the MAC to match the "fc" parameter. 4004 */ 4005 if (((hw->media_type == em_media_type_fiber) && (hw->autoneg_failed)) 4006 || ((hw->media_type == em_media_type_internal_serdes) && 4007 (hw->autoneg_failed)) || 4008 ((hw->media_type == em_media_type_copper) && (!hw->autoneg)) || 4009 ((hw->media_type == em_media_type_oem) && (!hw->autoneg))) { 4010 ret_val = em_force_mac_fc(hw); 4011 if (ret_val) { 4012 DEBUGOUT("Error forcing flow control settings\n"); 4013 return ret_val; 4014 } 4015 } 4016 /* 4017 * Check for the case where we have copper media and auto-neg is 4018 * enabled. In this case, we need to check and see if Auto-Neg has 4019 * completed, and if so, how the PHY and link partner has flow 4020 * control configured. 4021 */ 4022 if ((hw->media_type == em_media_type_copper || 4023 (hw->media_type == em_media_type_oem)) && 4024 hw->autoneg) { 4025 /* 4026 * Read the MII Status Register and check to see if AutoNeg 4027 * has completed. We read this twice because this reg has 4028 * some "sticky" (latched) bits. 4029 */ 4030 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 4031 if (ret_val) 4032 return ret_val; 4033 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 4034 if (ret_val) 4035 return ret_val; 4036 4037 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) { 4038 /* 4039 * The AutoNeg process has completed, so we now need 4040 * to read both the Auto Negotiation Advertisement 4041 * Register (Address 4) and the Auto_Negotiation Base 4042 * Page Ability Register (Address 5) to determine how 4043 * flow control was negotiated. 4044 */ 4045 ret_val = em_read_phy_reg(hw, PHY_AUTONEG_ADV, 4046 &mii_nway_adv_reg); 4047 if (ret_val) 4048 return ret_val; 4049 ret_val = em_read_phy_reg(hw, PHY_LP_ABILITY, 4050 &mii_nway_lp_ability_reg); 4051 if (ret_val) 4052 return ret_val; 4053 /* 4054 * Two bits in the Auto Negotiation Advertisement 4055 * Register (Address 4) and two bits in the Auto 4056 * Negotiation Base Page Ability Register (Address 5) 4057 * determine flow control for both the PHY and the 4058 * link partner. The following table, taken out of 4059 * the IEEE 802.3ab/D6.0 dated March 25, 1999, 4060 * describes these PAUSE resolution bits and how flow 4061 * control is determined based upon these settings. 4062 * NOTE: DC = Don't Care 4063 * 4064 * LOCAL DEVICE | LINK PARTNER | 4065 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 4066 * -------|---------|-------|---------|--------------- 4067 * 0 | 0 | DC | DC | em_fc_none 4068 * 0 | 1 | 0 | DC | em_fc_none 4069 * 0 | 1 | 1 | 0 | em_fc_none 4070 * 0 | 1 | 1 | 1 | em_fc_tx_pause 4071 * 1 | 0 | 0 | DC | em_fc_none 4072 * 1 | DC | 1 | DC | em_fc_full 4073 * 1 | 1 | 0 | 0 | em_fc_none 4074 * 1 | 1 | 0 | 1 | em_fc_rx_pause 4075 * 4076 */ 4077 /* 4078 * Are both PAUSE bits set to 1? If so, this implies 4079 * Symmetric Flow Control is enabled at both ends. 4080 * The ASM_DIR bits are irrelevant per the spec. 4081 * 4082 * For Symmetric Flow Control: 4083 * 4084 * LOCAL DEVICE | LINK PARTNER 4085 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 4086 * -------|---------|-------|---------|--------------- 4087 * 1 | DC | 1 | DC | em_fc_full 4088 * 4089 */ 4090 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 4091 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 4092 /* 4093 * Now we need to check if the user selected 4094 * RX ONLY of pause frames. In this case, we 4095 * had to advertise FULL flow control because 4096 * we could not advertise RX ONLY. Hence, we 4097 * must now check to see if we need to turn 4098 * OFF the TRANSMISSION of PAUSE frames. 4099 */ 4100 if (hw->original_fc == E1000_FC_FULL) { 4101 hw->fc = E1000_FC_FULL; 4102 DEBUGOUT("Flow Control = FULL.\n"); 4103 } else { 4104 hw->fc = E1000_FC_RX_PAUSE; 4105 DEBUGOUT("Flow Control = RX PAUSE" 4106 " frames only.\n"); 4107 } 4108 } 4109 /* 4110 * For receiving PAUSE frames ONLY. 4111 * 4112 * LOCAL DEVICE | LINK PARTNER PAUSE | ASM_DIR | 4113 * PAUSE | ASM_DIR | Result 4114 * -------|---------|-------|---------|--------------- 4115 * ----- 0 | 1 | 1 | 1 | 4116 * em_fc_tx_pause 4117 * 4118 */ 4119 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 4120 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 4121 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 4122 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 4123 hw->fc = E1000_FC_TX_PAUSE; 4124 DEBUGOUT("Flow Control = TX PAUSE frames only." 4125 "\n"); 4126 } 4127 /* 4128 * For transmitting PAUSE frames ONLY. 4129 * 4130 * LOCAL DEVICE | LINK PARTNER 4131 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 4132 * -------|---------|-------|---------|--------------- 4133 * 1 | 1 | 0 | 1 | em_fc_rx_pause 4134 * 4135 */ 4136 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 4137 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 4138 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 4139 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 4140 hw->fc = E1000_FC_RX_PAUSE; 4141 DEBUGOUT("Flow Control = RX PAUSE frames only." 4142 "\n"); 4143 } 4144 /* 4145 * Per the IEEE spec, at this point flow control 4146 * should be disabled. However, we want to consider 4147 * that we could be connected to a legacy switch that 4148 * doesn't advertise desired flow control, but can be 4149 * forced on the link partner. So if we advertised 4150 * no flow control, that is what we will resolve to. 4151 * If we advertised some kind of receive capability 4152 * (Rx Pause Only or Full Flow Control) and the link 4153 * partner advertised none, we will configure 4154 * ourselves to enable Rx Flow Control only. We can 4155 * do this safely for two reasons: If the link 4156 * partner really didn't want flow control enabled, 4157 * and we enable Rx, no harm done since we won't be 4158 * receiving any PAUSE frames anyway. If the intent 4159 * on the link partner was to have flow control 4160 * enabled, then by us enabling RX only, we can at 4161 * least receive pause frames and process them. This 4162 * is a good idea because in most cases, since we are 4163 * predominantly a server NIC, more times than not we 4164 * will be asked to delay transmission of packets 4165 * than asking our link partner to pause transmission 4166 * of frames. 4167 */ 4168 else if ((hw->original_fc == E1000_FC_NONE || 4169 hw->original_fc == E1000_FC_TX_PAUSE) || 4170 hw->fc_strict_ieee) { 4171 hw->fc = E1000_FC_NONE; 4172 DEBUGOUT("Flow Control = NONE.\n"); 4173 } else { 4174 hw->fc = E1000_FC_RX_PAUSE; 4175 DEBUGOUT("Flow Control = RX PAUSE frames only." 4176 "\n"); 4177 } 4178 /* 4179 * Now we need to do one last check... If we auto- 4180 * negotiated to HALF DUPLEX, flow control should not 4181 * be enabled per IEEE 802.3 spec. 4182 */ 4183 ret_val = em_get_speed_and_duplex(hw, &speed, &duplex); 4184 if (ret_val) { 4185 DEBUGOUT("Error getting link speed and duplex" 4186 "\n"); 4187 return ret_val; 4188 } 4189 if (duplex == HALF_DUPLEX) 4190 hw->fc = E1000_FC_NONE; 4191 /* 4192 * Now we call a subroutine to actually force the MAC 4193 * controller to use the correct flow control 4194 * settings. 4195 */ 4196 ret_val = em_force_mac_fc(hw); 4197 if (ret_val) { 4198 DEBUGOUT("Error forcing flow control settings" 4199 "\n"); 4200 return ret_val; 4201 } 4202 } else { 4203 DEBUGOUT("Copper PHY and Auto Neg has not completed." 4204 "\n"); 4205 } 4206 } 4207 return E1000_SUCCESS; 4208 } 4209 /****************************************************************************** 4210 * Checks to see if the link status of the hardware has changed. 4211 * 4212 * hw - Struct containing variables accessed by shared code 4213 * 4214 * Called by any function that needs to check the link status of the adapter. 4215 *****************************************************************************/ 4216 int32_t 4217 em_check_for_link(struct em_hw *hw) 4218 { 4219 uint32_t rxcw = 0; 4220 uint32_t ctrl; 4221 uint32_t status; 4222 uint32_t rctl; 4223 uint32_t icr; 4224 uint32_t signal = 0; 4225 int32_t ret_val; 4226 uint16_t phy_data; 4227 DEBUGFUNC("em_check_for_link"); 4228 uint16_t speed, duplex; 4229 4230 if (hw->mac_type >= em_82575 && 4231 hw->media_type != em_media_type_copper) { 4232 ret_val = em_get_pcs_speed_and_duplex_82575(hw, &speed, 4233 &duplex); 4234 hw->get_link_status = hw->serdes_link_down; 4235 4236 return (ret_val); 4237 } 4238 4239 ctrl = E1000_READ_REG(hw, CTRL); 4240 status = E1000_READ_REG(hw, STATUS); 4241 /* 4242 * On adapters with a MAC newer than 82544, SW Defineable pin 1 will 4243 * be set when the optics detect a signal. On older adapters, it will 4244 * be cleared when there is a signal. This applies to fiber media 4245 * only. 4246 */ 4247 if ((hw->media_type == em_media_type_fiber) || 4248 (hw->media_type == em_media_type_internal_serdes)) { 4249 rxcw = E1000_READ_REG(hw, RXCW); 4250 4251 if (hw->media_type == em_media_type_fiber) { 4252 signal = (hw->mac_type > em_82544) ? 4253 E1000_CTRL_SWDPIN1 : 0; 4254 if (status & E1000_STATUS_LU) 4255 hw->get_link_status = FALSE; 4256 } 4257 } 4258 /* 4259 * If we have a copper PHY then we only want to go out to the PHY 4260 * registers to see if Auto-Neg has completed and/or if our link 4261 * status has changed. The get_link_status flag will be set if we 4262 * receive a Link Status Change interrupt or we have Rx Sequence 4263 * Errors. 4264 */ 4265 if ((hw->media_type == em_media_type_copper || 4266 (hw->media_type == em_media_type_oem)) && 4267 hw->get_link_status) { 4268 /* 4269 * First we want to see if the MII Status Register reports 4270 * link. If so, then we want to get the current speed/duplex 4271 * of the PHY. Read the register twice since the link bit is 4272 * sticky. 4273 */ 4274 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 4275 if (ret_val) 4276 return ret_val; 4277 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 4278 if (ret_val) 4279 return ret_val; 4280 4281 hw->icp_xxxx_is_link_up = (phy_data & MII_SR_LINK_STATUS) != 0; 4282 4283 if (hw->mac_type == em_pchlan) { 4284 ret_val = em_k1_gig_workaround_hv(hw, 4285 hw->icp_xxxx_is_link_up); 4286 if (ret_val) 4287 return ret_val; 4288 } 4289 4290 if (phy_data & MII_SR_LINK_STATUS) { 4291 hw->get_link_status = FALSE; 4292 4293 if (hw->phy_type == em_phy_82578) { 4294 ret_val = em_link_stall_workaround_hv(hw); 4295 if (ret_val) 4296 return ret_val; 4297 } 4298 4299 if (hw->mac_type == em_pch2lan) { 4300 ret_val = em_k1_workaround_lv(hw); 4301 if (ret_val) 4302 return ret_val; 4303 } 4304 /* Work-around I218 hang issue */ 4305 if ((hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) || 4306 (hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) || 4307 (hw->device_id == E1000_DEV_ID_PCH_I218_LM3) || 4308 (hw->device_id == E1000_DEV_ID_PCH_I218_V3)) { 4309 ret_val = em_k1_workaround_lpt_lp(hw, 4310 hw->icp_xxxx_is_link_up); 4311 if (ret_val) 4312 return ret_val; 4313 } 4314 4315 /* 4316 * Check if there was DownShift, must be checked 4317 * immediately after link-up 4318 */ 4319 em_check_downshift(hw); 4320 4321 /* Enable/Disable EEE after link up */ 4322 if (hw->mac_type == em_pch2lan || 4323 hw->mac_type == em_pch_lpt || 4324 hw->mac_type == em_pch_spt || 4325 hw->mac_type == em_pch_cnp) { 4326 ret_val = em_set_eee_pchlan(hw); 4327 if (ret_val) 4328 return ret_val; 4329 } 4330 4331 /* 4332 * If we are on 82544 or 82543 silicon and 4333 * speed/duplex are forced to 10H or 10F, then we 4334 * will implement the polarity reversal workaround. 4335 * We disable interrupts first, and upon returning, 4336 * place the devices interrupt state to its previous 4337 * value except for the link status change interrupt 4338 * which will happen due to the execution of this 4339 * workaround. 4340 */ 4341 if ((hw->mac_type == em_82544 || 4342 hw->mac_type == em_82543) && (!hw->autoneg) && 4343 (hw->forced_speed_duplex == em_10_full || 4344 hw->forced_speed_duplex == em_10_half)) { 4345 E1000_WRITE_REG(hw, IMC, 0xffffffff); 4346 ret_val = em_polarity_reversal_workaround(hw); 4347 icr = E1000_READ_REG(hw, ICR); 4348 E1000_WRITE_REG(hw, ICS, 4349 (icr & ~E1000_ICS_LSC)); 4350 E1000_WRITE_REG(hw, IMS, IMS_ENABLE_MASK); 4351 } 4352 } else { 4353 /* No link detected */ 4354 em_config_dsp_after_link_change(hw, FALSE); 4355 return 0; 4356 } 4357 /* 4358 * If we are forcing speed/duplex, then we simply return 4359 * since we have already determined whether we have link or 4360 * not. 4361 */ 4362 if (!hw->autoneg) 4363 return -E1000_ERR_CONFIG; 4364 4365 /* optimize the dsp settings for the igp phy */ 4366 em_config_dsp_after_link_change(hw, TRUE); 4367 /* 4368 * We have a M88E1000 PHY and Auto-Neg is enabled. If we 4369 * have Si on board that is 82544 or newer, Auto Speed 4370 * Detection takes care of MAC speed/duplex configuration. 4371 * So we only need to configure Collision Distance in the 4372 * MAC. Otherwise, we need to force speed/duplex on the MAC 4373 * to the current PHY speed/duplex settings. 4374 */ 4375 if (hw->mac_type >= em_82544 && hw->mac_type != em_icp_xxxx) { 4376 em_config_collision_dist(hw); 4377 } else { 4378 ret_val = em_config_mac_to_phy(hw); 4379 if (ret_val) { 4380 DEBUGOUT("Error configuring MAC to PHY" 4381 " settings\n"); 4382 return ret_val; 4383 } 4384 } 4385 /* 4386 * Configure Flow Control now that Auto-Neg has completed. 4387 * First, we need to restore the desired flow control 4388 * settings because we may have had to re-autoneg with a 4389 * different link partner. 4390 */ 4391 ret_val = em_config_fc_after_link_up(hw); 4392 if (ret_val) { 4393 DEBUGOUT("Error configuring flow control\n"); 4394 return ret_val; 4395 } 4396 /* 4397 * At this point we know that we are on copper and we have 4398 * auto-negotiated link. These are conditions for checking 4399 * the link partner capability register. We use the link 4400 * speed to determine if TBI compatibility needs to be turned 4401 * on or off. If the link is not at gigabit speed, then TBI 4402 * compatibility is not needed. If we are at gigabit speed, 4403 * we turn on TBI compatibility. 4404 */ 4405 if (hw->tbi_compatibility_en) { 4406 uint16_t speed, duplex; 4407 ret_val = em_get_speed_and_duplex(hw, &speed, &duplex); 4408 if (ret_val) { 4409 DEBUGOUT("Error getting link speed and duplex" 4410 "\n"); 4411 return ret_val; 4412 } 4413 if (speed != SPEED_1000) { 4414 /* 4415 * If link speed is not set to gigabit speed, 4416 * we do not need to enable TBI 4417 * compatibility. 4418 */ 4419 if (hw->tbi_compatibility_on) { 4420 /* 4421 * If we previously were in the mode, 4422 * turn it off. 4423 */ 4424 rctl = E1000_READ_REG(hw, RCTL); 4425 rctl &= ~E1000_RCTL_SBP; 4426 E1000_WRITE_REG(hw, RCTL, rctl); 4427 hw->tbi_compatibility_on = FALSE; 4428 } 4429 } else { 4430 /* 4431 * If TBI compatibility is was previously 4432 * off, turn it on. For compatibility with a 4433 * TBI link partner, we will store bad 4434 * packets. Some frames have an additional 4435 * byte on the end and will look like CRC 4436 * errors to to the hardware. 4437 */ 4438 if (!hw->tbi_compatibility_on) { 4439 hw->tbi_compatibility_on = TRUE; 4440 rctl = E1000_READ_REG(hw, RCTL); 4441 rctl |= E1000_RCTL_SBP; 4442 E1000_WRITE_REG(hw, RCTL, rctl); 4443 } 4444 } 4445 } 4446 } 4447 /* 4448 * If we don't have link (auto-negotiation failed or link partner 4449 * cannot auto-negotiate), the cable is plugged in (we have signal), 4450 * and our link partner is not trying to auto-negotiate with us (we 4451 * are receiving idles or data), we need to force link up. We also 4452 * need to give auto-negotiation time to complete, in case the cable 4453 * was just plugged in. The autoneg_failed flag does this. 4454 */ 4455 else if ((((hw->media_type == em_media_type_fiber) && 4456 ((ctrl & E1000_CTRL_SWDPIN1) == signal)) || 4457 (hw->media_type == em_media_type_internal_serdes)) && 4458 (!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) { 4459 if (hw->autoneg_failed == 0) { 4460 hw->autoneg_failed = 1; 4461 return 0; 4462 } 4463 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 4464 4465 /* Disable auto-negotiation in the TXCW register */ 4466 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE)); 4467 4468 /* Force link-up and also force full-duplex. */ 4469 ctrl = E1000_READ_REG(hw, CTRL); 4470 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 4471 E1000_WRITE_REG(hw, CTRL, ctrl); 4472 4473 /* Configure Flow Control after forcing link up. */ 4474 ret_val = em_config_fc_after_link_up(hw); 4475 if (ret_val) { 4476 DEBUGOUT("Error configuring flow control\n"); 4477 return ret_val; 4478 } 4479 } 4480 /* 4481 * If we are forcing link and we are receiving /C/ ordered sets, 4482 * re-enable auto-negotiation in the TXCW register and disable forced 4483 * link in the Device Control register in an attempt to 4484 * auto-negotiate with our link partner. 4485 */ 4486 else if (((hw->media_type == em_media_type_fiber) || 4487 (hw->media_type == em_media_type_internal_serdes)) && 4488 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 4489 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 4490 E1000_WRITE_REG(hw, TXCW, hw->txcw); 4491 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU)); 4492 4493 hw->serdes_link_down = FALSE; 4494 } 4495 /* 4496 * If we force link for non-auto-negotiation switch, check link 4497 * status based on MAC synchronization for internal serdes media 4498 * type. 4499 */ 4500 else if ((hw->media_type == em_media_type_internal_serdes) && 4501 !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) { 4502 /* SYNCH bit and IV bit are sticky. */ 4503 usec_delay(10); 4504 if (E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) { 4505 if (!(rxcw & E1000_RXCW_IV)) { 4506 hw->serdes_link_down = FALSE; 4507 DEBUGOUT("SERDES: Link is up.\n"); 4508 } 4509 } else { 4510 hw->serdes_link_down = TRUE; 4511 DEBUGOUT("SERDES: Link is down.\n"); 4512 } 4513 } 4514 if ((hw->media_type == em_media_type_internal_serdes) && 4515 (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) { 4516 hw->serdes_link_down = !(E1000_STATUS_LU & 4517 E1000_READ_REG(hw, STATUS)); 4518 } 4519 return E1000_SUCCESS; 4520 } 4521 4522 int32_t 4523 em_get_pcs_speed_and_duplex_82575(struct em_hw *hw, uint16_t *speed, 4524 uint16_t *duplex) 4525 { 4526 uint32_t pcs; 4527 4528 hw->serdes_link_down = TRUE; 4529 *speed = 0; 4530 *duplex = 0; 4531 4532 /* 4533 * Read the PCS Status register for link state. For non-copper mode, 4534 * the status register is not accurate. The PCS status register is 4535 * used instead. 4536 */ 4537 pcs = E1000_READ_REG(hw, PCS_LSTAT); 4538 4539 /* 4540 * The link up bit determines when link is up on autoneg. The sync ok 4541 * gets set once both sides sync up and agree upon link. Stable link 4542 * can be determined by checking for both link up and link sync ok 4543 */ 4544 if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) { 4545 hw->serdes_link_down = FALSE; 4546 4547 /* Detect and store PCS speed */ 4548 if (pcs & E1000_PCS_LSTS_SPEED_1000) { 4549 *speed = SPEED_1000; 4550 } else if (pcs & E1000_PCS_LSTS_SPEED_100) { 4551 *speed = SPEED_100; 4552 } else { 4553 *speed = SPEED_10; 4554 } 4555 4556 /* Detect and store PCS duplex */ 4557 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) { 4558 *duplex = FULL_DUPLEX; 4559 } else { 4560 *duplex = HALF_DUPLEX; 4561 } 4562 } 4563 4564 return (0); 4565 } 4566 4567 4568 /****************************************************************************** 4569 * Detects the current speed and duplex settings of the hardware. 4570 * 4571 * hw - Struct containing variables accessed by shared code 4572 * speed - Speed of the connection 4573 * duplex - Duplex setting of the connection 4574 *****************************************************************************/ 4575 int32_t 4576 em_get_speed_and_duplex(struct em_hw *hw, uint16_t *speed, uint16_t *duplex) 4577 { 4578 uint32_t status; 4579 int32_t ret_val; 4580 uint16_t phy_data; 4581 DEBUGFUNC("em_get_speed_and_duplex"); 4582 4583 if (hw->mac_type >= em_82575 && hw->media_type != em_media_type_copper) 4584 return em_get_pcs_speed_and_duplex_82575(hw, speed, duplex); 4585 4586 if (hw->mac_type >= em_82543) { 4587 status = E1000_READ_REG(hw, STATUS); 4588 if (status & E1000_STATUS_SPEED_1000) { 4589 *speed = SPEED_1000; 4590 DEBUGOUT("1000 Mbs, "); 4591 } else if (status & E1000_STATUS_SPEED_100) { 4592 *speed = SPEED_100; 4593 DEBUGOUT("100 Mbs, "); 4594 } else { 4595 *speed = SPEED_10; 4596 DEBUGOUT("10 Mbs, "); 4597 } 4598 4599 if (status & E1000_STATUS_FD) { 4600 *duplex = FULL_DUPLEX; 4601 DEBUGOUT("Full Duplex\n"); 4602 } else { 4603 *duplex = HALF_DUPLEX; 4604 DEBUGOUT(" Half Duplex\n"); 4605 } 4606 } else { 4607 DEBUGOUT("1000 Mbs, Full Duplex\n"); 4608 *speed = SPEED_1000; 4609 *duplex = FULL_DUPLEX; 4610 } 4611 /* 4612 * IGP01 PHY may advertise full duplex operation after speed 4613 * downgrade even if it is operating at half duplex. Here we set the 4614 * duplex settings to match the duplex in the link partner's 4615 * capabilities. 4616 */ 4617 if (hw->phy_type == em_phy_igp && hw->speed_downgraded) { 4618 ret_val = em_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data); 4619 if (ret_val) 4620 return ret_val; 4621 4622 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS)) 4623 *duplex = HALF_DUPLEX; 4624 else { 4625 ret_val = em_read_phy_reg(hw, PHY_LP_ABILITY, 4626 &phy_data); 4627 if (ret_val) 4628 return ret_val; 4629 if ((*speed == SPEED_100 && 4630 !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) || 4631 (*speed == SPEED_10 && 4632 !(phy_data & NWAY_LPAR_10T_FD_CAPS))) 4633 *duplex = HALF_DUPLEX; 4634 } 4635 } 4636 if ((hw->mac_type == em_80003es2lan) && 4637 (hw->media_type == em_media_type_copper)) { 4638 if (*speed == SPEED_1000) 4639 ret_val = em_configure_kmrn_for_1000(hw); 4640 else 4641 ret_val = em_configure_kmrn_for_10_100(hw, *duplex); 4642 if (ret_val) 4643 return ret_val; 4644 } 4645 if ((hw->mac_type == em_ich8lan) && 4646 (hw->phy_type == em_phy_igp_3) && 4647 (*speed == SPEED_1000)) { 4648 ret_val = em_kumeran_lock_loss_workaround(hw); 4649 if (ret_val) 4650 return ret_val; 4651 } 4652 return E1000_SUCCESS; 4653 } 4654 4655 /****************************************************************************** 4656 * Blocks until autoneg completes or times out (~4.5 seconds) 4657 * 4658 * hw - Struct containing variables accessed by shared code 4659 *****************************************************************************/ 4660 STATIC int32_t 4661 em_wait_autoneg(struct em_hw *hw) 4662 { 4663 int32_t ret_val; 4664 uint16_t i; 4665 uint16_t phy_data; 4666 DEBUGFUNC("em_wait_autoneg"); 4667 DEBUGOUT("Waiting for Auto-Neg to complete.\n"); 4668 4669 /* We will wait for autoneg to complete or 4.5 seconds to expire. */ 4670 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) { 4671 /* 4672 * Read the MII Status Register and wait for Auto-Neg 4673 * Complete bit to be set. 4674 */ 4675 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 4676 if (ret_val) 4677 return ret_val; 4678 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 4679 if (ret_val) 4680 return ret_val; 4681 if (phy_data & MII_SR_AUTONEG_COMPLETE) { 4682 return E1000_SUCCESS; 4683 } 4684 msec_delay(100); 4685 } 4686 return E1000_SUCCESS; 4687 } 4688 4689 /****************************************************************************** 4690 * Raises the Management Data Clock 4691 * 4692 * hw - Struct containing variables accessed by shared code 4693 * ctrl - Device control register's current value 4694 *****************************************************************************/ 4695 static void 4696 em_raise_mdi_clk(struct em_hw *hw, uint32_t *ctrl) 4697 { 4698 /* 4699 * Raise the clock input to the Management Data Clock (by setting the 4700 * MDC bit), and then delay 10 microseconds. 4701 */ 4702 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC)); 4703 E1000_WRITE_FLUSH(hw); 4704 usec_delay(10); 4705 } 4706 4707 /****************************************************************************** 4708 * Lowers the Management Data Clock 4709 * 4710 * hw - Struct containing variables accessed by shared code 4711 * ctrl - Device control register's current value 4712 *****************************************************************************/ 4713 static void 4714 em_lower_mdi_clk(struct em_hw *hw, uint32_t *ctrl) 4715 { 4716 /* 4717 * Lower the clock input to the Management Data Clock (by clearing 4718 * the MDC bit), and then delay 10 microseconds. 4719 */ 4720 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC)); 4721 E1000_WRITE_FLUSH(hw); 4722 usec_delay(10); 4723 } 4724 4725 /****************************************************************************** 4726 * Shifts data bits out to the PHY 4727 * 4728 * hw - Struct containing variables accessed by shared code 4729 * data - Data to send out to the PHY 4730 * count - Number of bits to shift out 4731 * 4732 * Bits are shifted out in MSB to LSB order. 4733 *****************************************************************************/ 4734 static void 4735 em_shift_out_mdi_bits(struct em_hw *hw, uint32_t data, uint16_t count) 4736 { 4737 uint32_t ctrl; 4738 uint32_t mask; 4739 /* 4740 * We need to shift "count" number of bits out to the PHY. So, the 4741 * value in the "data" parameter will be shifted out to the PHY one 4742 * bit at a time. In order to do this, "data" must be broken down 4743 * into bits. 4744 */ 4745 mask = 0x01; 4746 mask <<= (count - 1); 4747 4748 ctrl = E1000_READ_REG(hw, CTRL); 4749 4750 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output 4751 * pins. 4752 */ 4753 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); 4754 4755 while (mask) { 4756 /* 4757 * A "1" is shifted out to the PHY by setting the MDIO bit to 4758 * "1" and then raising and lowering the Management Data 4759 * Clock. A "0" is shifted out to the PHY by setting the MDIO 4760 * bit to "0" and then raising and lowering the clock. 4761 */ 4762 if (data & mask) 4763 ctrl |= E1000_CTRL_MDIO; 4764 else 4765 ctrl &= ~E1000_CTRL_MDIO; 4766 4767 E1000_WRITE_REG(hw, CTRL, ctrl); 4768 E1000_WRITE_FLUSH(hw); 4769 4770 usec_delay(10); 4771 4772 em_raise_mdi_clk(hw, &ctrl); 4773 em_lower_mdi_clk(hw, &ctrl); 4774 4775 mask = mask >> 1; 4776 } 4777 } 4778 4779 /****************************************************************************** 4780 * Shifts data bits in from the PHY 4781 * 4782 * hw - Struct containing variables accessed by shared code 4783 * 4784 * Bits are shifted in in MSB to LSB order. 4785 *****************************************************************************/ 4786 static uint16_t 4787 em_shift_in_mdi_bits(struct em_hw *hw) 4788 { 4789 uint32_t ctrl; 4790 uint16_t data = 0; 4791 uint8_t i; 4792 /* 4793 * In order to read a register from the PHY, we need to shift in a 4794 * total of 18 bits from the PHY. The first two bit (turnaround) 4795 * times are used to avoid contention on the MDIO pin when a read 4796 * operation is performed. These two bits are ignored by us and 4797 * thrown away. Bits are "shifted in" by raising the input to the 4798 * Management Data Clock (setting the MDC bit), and then reading the 4799 * value of the MDIO bit. 4800 */ 4801 ctrl = E1000_READ_REG(hw, CTRL); 4802 /* 4803 * Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as 4804 * input. 4805 */ 4806 ctrl &= ~E1000_CTRL_MDIO_DIR; 4807 ctrl &= ~E1000_CTRL_MDIO; 4808 4809 E1000_WRITE_REG(hw, CTRL, ctrl); 4810 E1000_WRITE_FLUSH(hw); 4811 /* 4812 * Raise and Lower the clock before reading in the data. This 4813 * accounts for the turnaround bits. The first clock occurred when we 4814 * clocked out the last bit of the Register Address. 4815 */ 4816 em_raise_mdi_clk(hw, &ctrl); 4817 em_lower_mdi_clk(hw, &ctrl); 4818 4819 for (data = 0, i = 0; i < 16; i++) { 4820 data = data << 1; 4821 em_raise_mdi_clk(hw, &ctrl); 4822 ctrl = E1000_READ_REG(hw, CTRL); 4823 /* Check to see if we shifted in a "1". */ 4824 if (ctrl & E1000_CTRL_MDIO) 4825 data |= 1; 4826 em_lower_mdi_clk(hw, &ctrl); 4827 } 4828 4829 em_raise_mdi_clk(hw, &ctrl); 4830 em_lower_mdi_clk(hw, &ctrl); 4831 4832 return data; 4833 } 4834 4835 STATIC int32_t 4836 em_swfw_sync_acquire(struct em_hw *hw, uint16_t mask) 4837 { 4838 uint32_t swfw_sync = 0; 4839 uint32_t swmask = mask; 4840 uint32_t fwmask = mask << 16; 4841 int32_t timeout = 200; 4842 DEBUGFUNC("em_swfw_sync_acquire"); 4843 4844 if (hw->swfwhw_semaphore_present) 4845 return em_get_software_flag(hw); 4846 4847 if (!hw->swfw_sync_present) 4848 return em_get_hw_eeprom_semaphore(hw); 4849 4850 while (timeout) { 4851 if (em_get_hw_eeprom_semaphore(hw)) 4852 return -E1000_ERR_SWFW_SYNC; 4853 4854 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); 4855 if (!(swfw_sync & (fwmask | swmask))) { 4856 break; 4857 } 4858 /* 4859 * firmware currently using resource (fwmask) 4860 * or other software thread currently using resource (swmask) 4861 */ 4862 em_put_hw_eeprom_semaphore(hw); 4863 msec_delay_irq(5); 4864 timeout--; 4865 } 4866 4867 if (!timeout) { 4868 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout." 4869 "\n"); 4870 return -E1000_ERR_SWFW_SYNC; 4871 } 4872 swfw_sync |= swmask; 4873 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync); 4874 4875 em_put_hw_eeprom_semaphore(hw); 4876 return E1000_SUCCESS; 4877 } 4878 4879 STATIC void 4880 em_swfw_sync_release(struct em_hw *hw, uint16_t mask) 4881 { 4882 uint32_t swfw_sync; 4883 uint32_t swmask = mask; 4884 DEBUGFUNC("em_swfw_sync_release"); 4885 4886 if (hw->swfwhw_semaphore_present) { 4887 em_release_software_flag(hw); 4888 return; 4889 } 4890 if (!hw->swfw_sync_present) { 4891 em_put_hw_eeprom_semaphore(hw); 4892 return; 4893 } 4894 /* 4895 * if (em_get_hw_eeprom_semaphore(hw)) return -E1000_ERR_SWFW_SYNC; 4896 */ 4897 while (em_get_hw_eeprom_semaphore(hw) != E1000_SUCCESS); 4898 /* empty */ 4899 4900 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); 4901 swfw_sync &= ~swmask; 4902 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync); 4903 4904 em_put_hw_eeprom_semaphore(hw); 4905 } 4906 4907 /**************************************************************************** 4908 * Read BM PHY wakeup register. It works as such: 4909 * 1) Set page 769, register 17, bit 2 = 1 4910 * 2) Set page to 800 for host (801 if we were manageability) 4911 * 3) Write the address using the address opcode (0x11) 4912 * 4) Read or write the data using the data opcode (0x12) 4913 * 5) Restore 769_17.2 to its original value 4914 ****************************************************************************/ 4915 int32_t 4916 em_access_phy_wakeup_reg_bm(struct em_hw *hw, uint32_t reg_addr, 4917 uint16_t *phy_data, boolean_t read) 4918 { 4919 int32_t ret_val; 4920 uint16_t reg = BM_PHY_REG_NUM(reg_addr); 4921 uint16_t phy_reg = 0; 4922 4923 /* All operations in this function are phy address 1 */ 4924 hw->phy_addr = 1; 4925 4926 /* Set page 769 */ 4927 em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 4928 (BM_WUC_ENABLE_PAGE << PHY_PAGE_SHIFT)); 4929 4930 ret_val = em_read_phy_reg_ex(hw, BM_WUC_ENABLE_REG, &phy_reg); 4931 if (ret_val) 4932 goto out; 4933 4934 /* First clear bit 4 to avoid a power state change */ 4935 phy_reg &= ~(BM_WUC_HOST_WU_BIT); 4936 ret_val = em_write_phy_reg_ex(hw, BM_WUC_ENABLE_REG, phy_reg); 4937 if (ret_val) 4938 goto out; 4939 4940 /* Write bit 2 = 1, and clear bit 4 to 769_17 */ 4941 ret_val = em_write_phy_reg_ex(hw, BM_WUC_ENABLE_REG, 4942 phy_reg | BM_WUC_ENABLE_BIT); 4943 if (ret_val) 4944 goto out; 4945 4946 /* Select page 800 */ 4947 ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 4948 (BM_WUC_PAGE << PHY_PAGE_SHIFT)); 4949 4950 /* Write the page 800 offset value using opcode 0x11 */ 4951 ret_val = em_write_phy_reg_ex(hw, BM_WUC_ADDRESS_OPCODE, reg); 4952 if (ret_val) 4953 goto out; 4954 4955 if (read) 4956 /* Read the page 800 value using opcode 0x12 */ 4957 ret_val = em_read_phy_reg_ex(hw, BM_WUC_DATA_OPCODE, 4958 phy_data); 4959 else 4960 /* Write the page 800 value using opcode 0x12 */ 4961 ret_val = em_write_phy_reg_ex(hw, BM_WUC_DATA_OPCODE, 4962 *phy_data); 4963 4964 if (ret_val) 4965 goto out; 4966 4967 /* 4968 * Restore 769_17.2 to its original value 4969 * Set page 769 4970 */ 4971 em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 4972 (BM_WUC_ENABLE_PAGE << PHY_PAGE_SHIFT)); 4973 4974 /* Clear 769_17.2 */ 4975 ret_val = em_write_phy_reg_ex(hw, BM_WUC_ENABLE_REG, phy_reg); 4976 if (ret_val) 4977 goto out; 4978 4979 out: 4980 return ret_val; 4981 } 4982 4983 /*************************************************************************** 4984 * Read HV PHY vendor specific high registers 4985 ***************************************************************************/ 4986 int32_t 4987 em_access_phy_debug_regs_hv(struct em_hw *hw, uint32_t reg_addr, 4988 uint16_t *phy_data, boolean_t read) 4989 { 4990 int32_t ret_val; 4991 uint32_t addr_reg = 0; 4992 uint32_t data_reg = 0; 4993 4994 /* This takes care of the difference with desktop vs mobile phy */ 4995 addr_reg = (hw->phy_type == em_phy_82578) ? 4996 I82578_PHY_ADDR_REG : I82577_PHY_ADDR_REG; 4997 data_reg = addr_reg + 1; 4998 4999 /* All operations in this function are phy address 2 */ 5000 hw->phy_addr = 2; 5001 5002 /* masking with 0x3F to remove the page from offset */ 5003 ret_val = em_write_phy_reg_ex(hw, addr_reg, (uint16_t)reg_addr & 0x3F); 5004 if (ret_val) { 5005 printf("Could not write PHY the HV address register\n"); 5006 goto out; 5007 } 5008 5009 /* Read or write the data value next */ 5010 if (read) 5011 ret_val = em_read_phy_reg_ex(hw, data_reg, phy_data); 5012 else 5013 ret_val = em_write_phy_reg_ex(hw, data_reg, *phy_data); 5014 5015 if (ret_val) { 5016 printf("Could not read data value from HV data register\n"); 5017 goto out; 5018 } 5019 5020 out: 5021 return ret_val; 5022 } 5023 5024 /****************************************************************************** 5025 * Reads or writes the value from a PHY register, if the value is on a specific 5026 * non zero page, sets the page first. 5027 * hw - Struct containing variables accessed by shared code 5028 * reg_addr - address of the PHY register to read 5029 *****************************************************************************/ 5030 int32_t 5031 em_access_phy_reg_hv(struct em_hw *hw, uint32_t reg_addr, uint16_t *phy_data, 5032 boolean_t read) 5033 { 5034 uint32_t ret_val; 5035 uint16_t swfw; 5036 uint16_t page = BM_PHY_REG_PAGE(reg_addr); 5037 uint16_t reg = BM_PHY_REG_NUM(reg_addr); 5038 5039 DEBUGFUNC("em_access_phy_reg_hv"); 5040 5041 swfw = E1000_SWFW_PHY0_SM; 5042 5043 if (em_swfw_sync_acquire(hw, swfw)) 5044 return -E1000_ERR_SWFW_SYNC; 5045 5046 if (page == BM_WUC_PAGE) { 5047 ret_val = em_access_phy_wakeup_reg_bm(hw, reg_addr, 5048 phy_data, read); 5049 goto release; 5050 } 5051 5052 if (page >= HV_INTC_FC_PAGE_START) 5053 hw->phy_addr = 1; 5054 else 5055 hw->phy_addr = 2; 5056 5057 if (page == HV_INTC_FC_PAGE_START) 5058 page = 0; 5059 5060 /* 5061 * Workaround MDIO accesses being disabled after entering IEEE Power 5062 * Down (whenever bit 11 of the PHY Control register is set) 5063 */ 5064 if (!read && 5065 (hw->phy_type == em_phy_82578) && 5066 (hw->phy_revision >= 1) && 5067 (hw->phy_addr == 2) && 5068 ((MAX_PHY_REG_ADDRESS & reg) == 0) && 5069 (*phy_data & (1 << 11))) { 5070 uint16_t data2 = 0x7EFF; 5071 5072 ret_val = em_access_phy_debug_regs_hv(hw, (1 << 6) | 0x3, 5073 &data2, FALSE); 5074 if (ret_val) 5075 return ret_val; 5076 } 5077 5078 if (reg_addr > MAX_PHY_MULTI_PAGE_REG) { 5079 ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 5080 (page << PHY_PAGE_SHIFT)); 5081 if (ret_val) 5082 return ret_val; 5083 } 5084 if (read) 5085 ret_val = em_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg, 5086 phy_data); 5087 else 5088 ret_val = em_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg, 5089 *phy_data); 5090 release: 5091 em_swfw_sync_release(hw, swfw); 5092 return ret_val; 5093 } 5094 5095 /****************************************************************************** 5096 * Reads the value from a PHY register, if the value is on a specific non zero 5097 * page, sets the page first. 5098 * hw - Struct containing variables accessed by shared code 5099 * reg_addr - address of the PHY register to read 5100 *****************************************************************************/ 5101 int32_t 5102 em_read_phy_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t *phy_data) 5103 { 5104 uint32_t ret_val; 5105 uint16_t swfw; 5106 DEBUGFUNC("em_read_phy_reg"); 5107 5108 if (hw->mac_type == em_pchlan || 5109 hw->mac_type == em_pch2lan || 5110 hw->mac_type == em_pch_lpt || 5111 hw->mac_type == em_pch_spt || 5112 hw->mac_type == em_pch_cnp) 5113 return (em_access_phy_reg_hv(hw, reg_addr, phy_data, TRUE)); 5114 5115 if (((hw->mac_type == em_80003es2lan) || (hw->mac_type == em_82575) || 5116 (hw->mac_type == em_82576)) && 5117 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { 5118 swfw = E1000_SWFW_PHY1_SM; 5119 } else { 5120 swfw = E1000_SWFW_PHY0_SM; 5121 } 5122 if (em_swfw_sync_acquire(hw, swfw)) 5123 return -E1000_ERR_SWFW_SYNC; 5124 5125 if ((hw->phy_type == em_phy_igp || 5126 hw->phy_type == em_phy_igp_3 || 5127 hw->phy_type == em_phy_igp_2) && 5128 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { 5129 ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 5130 (uint16_t) reg_addr); 5131 if (ret_val) { 5132 em_swfw_sync_release(hw, swfw); 5133 return ret_val; 5134 } 5135 } else if (hw->phy_type == em_phy_gg82563) { 5136 if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) || 5137 (hw->mac_type == em_80003es2lan)) { 5138 /* Select Configuration Page */ 5139 if ((reg_addr & MAX_PHY_REG_ADDRESS) < 5140 GG82563_MIN_ALT_REG) { 5141 ret_val = em_write_phy_reg_ex(hw, 5142 GG82563_PHY_PAGE_SELECT, 5143 (uint16_t) ((uint16_t) reg_addr >> 5144 GG82563_PAGE_SHIFT)); 5145 } else { 5146 /* 5147 * Use Alternative Page Select register to 5148 * access registers 30 and 31 5149 */ 5150 ret_val = em_write_phy_reg_ex(hw, 5151 GG82563_PHY_PAGE_SELECT_ALT, 5152 (uint16_t) ((uint16_t) reg_addr >> 5153 GG82563_PAGE_SHIFT)); 5154 } 5155 5156 if (ret_val) { 5157 em_swfw_sync_release(hw, swfw); 5158 return ret_val; 5159 } 5160 } 5161 } else if ((hw->phy_type == em_phy_bm) && (hw->phy_revision == 1)) { 5162 if (reg_addr > MAX_PHY_MULTI_PAGE_REG) { 5163 ret_val = em_write_phy_reg_ex(hw, BM_PHY_PAGE_SELECT, 5164 (uint16_t) ((uint16_t) reg_addr >> 5165 PHY_PAGE_SHIFT)); 5166 if (ret_val) 5167 return ret_val; 5168 } 5169 } 5170 ret_val = em_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, 5171 phy_data); 5172 5173 em_swfw_sync_release(hw, swfw); 5174 return ret_val; 5175 } 5176 5177 STATIC int32_t 5178 em_read_phy_reg_ex(struct em_hw *hw, uint32_t reg_addr, uint16_t *phy_data) 5179 { 5180 uint32_t i; 5181 uint32_t mdic = 0; 5182 DEBUGFUNC("em_read_phy_reg_ex"); 5183 5184 /* SGMII active is only set on some specific chips */ 5185 if (hw->sgmii_active && !em_sgmii_uses_mdio_82575(hw)) { 5186 if (reg_addr > E1000_MAX_SGMII_PHY_REG_ADDR) { 5187 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); 5188 return -E1000_ERR_PARAM; 5189 } 5190 return em_read_phy_reg_i2c(hw, reg_addr, phy_data); 5191 } 5192 if (reg_addr > MAX_PHY_REG_ADDRESS) { 5193 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); 5194 return -E1000_ERR_PARAM; 5195 } 5196 if (hw->mac_type == em_icp_xxxx) { 5197 *phy_data = gcu_miibus_readreg(hw, hw->icp_xxxx_port_num, 5198 reg_addr); 5199 return E1000_SUCCESS; 5200 } 5201 if (hw->mac_type > em_82543) { 5202 /* 5203 * Set up Op-code, Phy Address, and register address in the 5204 * MDI Control register. The MAC will take care of 5205 * interfacing with the PHY to retrieve the desired data. 5206 */ 5207 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) | 5208 (hw->phy_addr << E1000_MDIC_PHY_SHIFT) | 5209 (E1000_MDIC_OP_READ)); 5210 5211 E1000_WRITE_REG(hw, MDIC, mdic); 5212 5213 /* 5214 * Poll the ready bit to see if the MDI read completed 5215 * Increasing the time out as testing showed failures with 5216 * the lower time out (from FreeBSD driver) 5217 */ 5218 for (i = 0; i < 1960; i++) { 5219 usec_delay(50); 5220 mdic = E1000_READ_REG(hw, MDIC); 5221 if (mdic & E1000_MDIC_READY) 5222 break; 5223 } 5224 if (!(mdic & E1000_MDIC_READY)) { 5225 DEBUGOUT("MDI Read did not complete\n"); 5226 return -E1000_ERR_PHY; 5227 } 5228 if (mdic & E1000_MDIC_ERROR) { 5229 DEBUGOUT("MDI Error\n"); 5230 return -E1000_ERR_PHY; 5231 } 5232 *phy_data = (uint16_t) mdic; 5233 5234 if (hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt || 5235 hw->mac_type == em_pch_spt || hw->mac_type == em_pch_cnp) 5236 usec_delay(100); 5237 } else { 5238 /* 5239 * We must first send a preamble through the MDIO pin to 5240 * signal the beginning of an MII instruction. This is done 5241 * by sending 32 consecutive "1" bits. 5242 */ 5243 em_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 5244 /* 5245 * Now combine the next few fields that are required for a 5246 * read operation. We use this method instead of calling the 5247 * em_shift_out_mdi_bits routine five different times. The 5248 * format of a MII read instruction consists of a shift out 5249 * of 14 bits and is defined as follows: <Preamble><SOF><Op 5250 * Code><Phy Addr><Reg Addr> followed by a shift in of 18 5251 * bits. This first two bits shifted in are TurnAround bits 5252 * used to avoid contention on the MDIO pin when a READ 5253 * operation is performed. These two bits are thrown away 5254 * followed by a shift in of 16 bits which contains the 5255 * desired data. 5256 */ 5257 mdic = ((reg_addr) | (hw->phy_addr << 5) | 5258 (PHY_OP_READ << 10) | (PHY_SOF << 12)); 5259 5260 em_shift_out_mdi_bits(hw, mdic, 14); 5261 /* 5262 * Now that we've shifted out the read command to the MII, we 5263 * need to "shift in" the 16-bit value (18 total bits) of the 5264 * requested PHY register address. 5265 */ 5266 *phy_data = em_shift_in_mdi_bits(hw); 5267 } 5268 return E1000_SUCCESS; 5269 } 5270 5271 /****************************************************************************** 5272 * Writes a value to a PHY register 5273 * 5274 * hw - Struct containing variables accessed by shared code 5275 * reg_addr - address of the PHY register to write 5276 * data - data to write to the PHY 5277 *****************************************************************************/ 5278 int32_t 5279 em_write_phy_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t phy_data) 5280 { 5281 uint32_t ret_val; 5282 DEBUGFUNC("em_write_phy_reg"); 5283 5284 if (hw->mac_type == em_pchlan || 5285 hw->mac_type == em_pch2lan || 5286 hw->mac_type == em_pch_lpt || 5287 hw->mac_type == em_pch_spt || 5288 hw->mac_type == em_pch_cnp) 5289 return (em_access_phy_reg_hv(hw, reg_addr, &phy_data, FALSE)); 5290 5291 if (em_swfw_sync_acquire(hw, hw->swfw)) 5292 return -E1000_ERR_SWFW_SYNC; 5293 5294 if ((hw->phy_type == em_phy_igp || 5295 hw->phy_type == em_phy_igp_3 || 5296 hw->phy_type == em_phy_igp_2) && 5297 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { 5298 ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 5299 (uint16_t) reg_addr); 5300 if (ret_val) { 5301 em_swfw_sync_release(hw, hw->swfw); 5302 return ret_val; 5303 } 5304 } else if (hw->phy_type == em_phy_gg82563) { 5305 if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) || 5306 (hw->mac_type == em_80003es2lan)) { 5307 /* Select Configuration Page */ 5308 if ((reg_addr & MAX_PHY_REG_ADDRESS) < 5309 GG82563_MIN_ALT_REG) { 5310 ret_val = em_write_phy_reg_ex(hw, 5311 GG82563_PHY_PAGE_SELECT, 5312 (uint16_t) ((uint16_t) reg_addr >> 5313 GG82563_PAGE_SHIFT)); 5314 } else { 5315 /* 5316 * Use Alternative Page Select register to 5317 * access registers 30 and 31 5318 */ 5319 ret_val = em_write_phy_reg_ex(hw, 5320 GG82563_PHY_PAGE_SELECT_ALT, 5321 (uint16_t) ((uint16_t) reg_addr >> 5322 GG82563_PAGE_SHIFT)); 5323 } 5324 5325 if (ret_val) { 5326 em_swfw_sync_release(hw, hw->swfw); 5327 return ret_val; 5328 } 5329 } 5330 } else if ((hw->phy_type == em_phy_bm) && (hw->phy_revision == 1)) { 5331 if (reg_addr > MAX_PHY_MULTI_PAGE_REG) { 5332 ret_val = em_write_phy_reg_ex(hw, BM_PHY_PAGE_SELECT, 5333 (uint16_t) ((uint16_t) reg_addr >> 5334 PHY_PAGE_SHIFT)); 5335 if (ret_val) 5336 return ret_val; 5337 } 5338 } 5339 ret_val = em_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, 5340 phy_data); 5341 5342 em_swfw_sync_release(hw, hw->swfw); 5343 return ret_val; 5344 } 5345 5346 STATIC int32_t 5347 em_write_phy_reg_ex(struct em_hw *hw, uint32_t reg_addr, uint16_t phy_data) 5348 { 5349 uint32_t i; 5350 uint32_t mdic = 0; 5351 DEBUGFUNC("em_write_phy_reg_ex"); 5352 5353 /* SGMII active is only set on some specific chips */ 5354 if (hw->sgmii_active && !em_sgmii_uses_mdio_82575(hw)) { 5355 if (reg_addr > E1000_MAX_SGMII_PHY_REG_ADDR) { 5356 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); 5357 return -E1000_ERR_PARAM; 5358 } 5359 return em_write_phy_reg_i2c(hw, reg_addr, phy_data); 5360 } 5361 if (reg_addr > MAX_PHY_REG_ADDRESS) { 5362 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); 5363 return -E1000_ERR_PARAM; 5364 } 5365 if (hw->mac_type == em_icp_xxxx) { 5366 gcu_miibus_writereg(hw, hw->icp_xxxx_port_num, 5367 reg_addr, phy_data); 5368 return E1000_SUCCESS; 5369 } 5370 if (hw->mac_type > em_82543) { 5371 /* 5372 * Set up Op-code, Phy Address, register address, and data 5373 * intended for the PHY register in the MDI Control register. 5374 * The MAC will take care of interfacing with the PHY to send 5375 * the desired data. 5376 */ 5377 mdic = (((uint32_t) phy_data) | 5378 (reg_addr << E1000_MDIC_REG_SHIFT) | 5379 (hw->phy_addr << E1000_MDIC_PHY_SHIFT) | 5380 (E1000_MDIC_OP_WRITE)); 5381 5382 E1000_WRITE_REG(hw, MDIC, mdic); 5383 5384 /* Poll the ready bit to see if the MDI read completed */ 5385 for (i = 0; i < 641; i++) { 5386 usec_delay(5); 5387 mdic = E1000_READ_REG(hw, MDIC); 5388 if (mdic & E1000_MDIC_READY) 5389 break; 5390 } 5391 if (!(mdic & E1000_MDIC_READY)) { 5392 DEBUGOUT("MDI Write did not complete\n"); 5393 return -E1000_ERR_PHY; 5394 } 5395 5396 if (hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt || 5397 hw->mac_type == em_pch_spt || hw->mac_type == em_pch_cnp) 5398 usec_delay(100); 5399 } else { 5400 /* 5401 * We'll need to use the SW defined pins to shift the write 5402 * command out to the PHY. We first send a preamble to the 5403 * PHY to signal the beginning of the MII instruction. This 5404 * is done by sending 32 consecutive "1" bits. 5405 */ 5406 em_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 5407 /* 5408 * Now combine the remaining required fields that will 5409 * indicate a write operation. We use this method instead of 5410 * calling the em_shift_out_mdi_bits routine for each field 5411 * in the command. The format of a MII write instruction is 5412 * as follows: <Preamble><SOF><Op Code><Phy Addr><Reg 5413 * Addr><Turnaround><Data>. 5414 */ 5415 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | 5416 (hw->phy_addr << 7) | (PHY_OP_WRITE << 12) | 5417 (PHY_SOF << 14)); 5418 mdic <<= 16; 5419 mdic |= (uint32_t) phy_data; 5420 5421 em_shift_out_mdi_bits(hw, mdic, 32); 5422 } 5423 5424 return E1000_SUCCESS; 5425 } 5426 5427 STATIC int32_t 5428 em_read_kmrn_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t *data) 5429 { 5430 uint32_t reg_val; 5431 DEBUGFUNC("em_read_kmrn_reg"); 5432 5433 if (em_swfw_sync_acquire(hw, hw->swfw)) 5434 return -E1000_ERR_SWFW_SYNC; 5435 5436 /* Write register address */ 5437 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) & 5438 E1000_KUMCTRLSTA_OFFSET) | 5439 E1000_KUMCTRLSTA_REN; 5440 5441 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); 5442 usec_delay(2); 5443 5444 /* Read the data returned */ 5445 reg_val = E1000_READ_REG(hw, KUMCTRLSTA); 5446 *data = (uint16_t) reg_val; 5447 5448 em_swfw_sync_release(hw, hw->swfw); 5449 return E1000_SUCCESS; 5450 } 5451 5452 STATIC int32_t 5453 em_write_kmrn_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t data) 5454 { 5455 uint32_t reg_val; 5456 DEBUGFUNC("em_write_kmrn_reg"); 5457 5458 if (em_swfw_sync_acquire(hw, hw->swfw)) 5459 return -E1000_ERR_SWFW_SYNC; 5460 5461 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) & 5462 E1000_KUMCTRLSTA_OFFSET) | data; 5463 5464 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); 5465 usec_delay(2); 5466 5467 em_swfw_sync_release(hw, hw->swfw); 5468 return E1000_SUCCESS; 5469 } 5470 5471 /** 5472 * em_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO 5473 * @hw: pointer to the HW structure 5474 * 5475 * Called to determine if the I2C pins are being used for I2C or as an 5476 * external MDIO interface since the two options are mutually exclusive. 5477 **/ 5478 int em_sgmii_uses_mdio_82575(struct em_hw *hw) 5479 { 5480 uint32_t reg = 0; 5481 int ext_mdio = 0; 5482 5483 DEBUGFUNC("em_sgmii_uses_mdio_82575"); 5484 5485 switch (hw->mac_type) { 5486 case em_82575: 5487 case em_82576: 5488 reg = E1000_READ_REG(hw, MDIC); 5489 ext_mdio = !!(reg & E1000_MDIC_DEST); 5490 break; 5491 case em_82580: 5492 case em_i350: 5493 case em_i210: 5494 reg = E1000_READ_REG(hw, MDICNFG); 5495 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO); 5496 break; 5497 default: 5498 break; 5499 } 5500 return ext_mdio; 5501 } 5502 5503 /** 5504 * em_read_phy_reg_i2c - Read PHY register using i2c 5505 * @hw: pointer to the HW structure 5506 * @offset: register offset to be read 5507 * @data: pointer to the read data 5508 * 5509 * Reads the PHY register at offset using the i2c interface and stores the 5510 * retrieved information in data. 5511 **/ 5512 int32_t em_read_phy_reg_i2c(struct em_hw *hw, uint32_t offset, uint16_t *data) 5513 { 5514 uint32_t i, i2ccmd = 0; 5515 5516 DEBUGFUNC("em_read_phy_reg_i2c"); 5517 5518 /* Set up Op-code, Phy Address, and register address in the I2CCMD 5519 * register. The MAC will take care of interfacing with the 5520 * PHY to retrieve the desired data. 5521 */ 5522 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 5523 (hw->phy_addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | 5524 (E1000_I2CCMD_OPCODE_READ)); 5525 5526 E1000_WRITE_REG(hw, I2CCMD, i2ccmd); 5527 5528 /* Poll the ready bit to see if the I2C read completed */ 5529 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 5530 usec_delay(50); 5531 i2ccmd = E1000_READ_REG(hw, I2CCMD); 5532 if (i2ccmd & E1000_I2CCMD_READY) 5533 break; 5534 } 5535 if (!(i2ccmd & E1000_I2CCMD_READY)) { 5536 DEBUGOUT("I2CCMD Read did not complete\n"); 5537 return -E1000_ERR_PHY; 5538 } 5539 if (i2ccmd & E1000_I2CCMD_ERROR) { 5540 DEBUGOUT("I2CCMD Error bit set\n"); 5541 return -E1000_ERR_PHY; 5542 } 5543 5544 /* Need to byte-swap the 16-bit value. */ 5545 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00); 5546 5547 return E1000_SUCCESS; 5548 } 5549 5550 /** 5551 * em_write_phy_reg_i2c - Write PHY register using i2c 5552 * @hw: pointer to the HW structure 5553 * @offset: register offset to write to 5554 * @data: data to write at register offset 5555 * 5556 * Writes the data to PHY register at the offset using the i2c interface. 5557 **/ 5558 int32_t em_write_phy_reg_i2c(struct em_hw *hw, uint32_t offset, uint16_t data) 5559 { 5560 uint32_t i, i2ccmd = 0; 5561 uint16_t phy_data_swapped; 5562 5563 DEBUGFUNC("em_write_phy_reg_i2c"); 5564 5565 /* Prevent overwriting SFP I2C EEPROM which is at A0 address.*/ 5566 if ((hw->phy_addr == 0) || (hw->phy_addr > 7)) { 5567 DEBUGOUT1("PHY I2C Address %d is out of range.\n", 5568 hw->phy_addr); 5569 return -E1000_ERR_CONFIG; 5570 } 5571 5572 /* Swap the data bytes for the I2C interface */ 5573 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00); 5574 5575 /* Set up Op-code, Phy Address, and register address in the I2CCMD 5576 * register. The MAC will take care of interfacing with the 5577 * PHY to retrieve the desired data. 5578 */ 5579 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 5580 (hw->phy_addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | 5581 E1000_I2CCMD_OPCODE_WRITE | 5582 phy_data_swapped); 5583 5584 E1000_WRITE_REG(hw, I2CCMD, i2ccmd); 5585 5586 /* Poll the ready bit to see if the I2C read completed */ 5587 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 5588 usec_delay(50); 5589 i2ccmd = E1000_READ_REG(hw, I2CCMD); 5590 if (i2ccmd & E1000_I2CCMD_READY) 5591 break; 5592 } 5593 if (!(i2ccmd & E1000_I2CCMD_READY)) { 5594 DEBUGOUT("I2CCMD Write did not complete\n"); 5595 return -E1000_ERR_PHY; 5596 } 5597 if (i2ccmd & E1000_I2CCMD_ERROR) { 5598 DEBUGOUT("I2CCMD Error bit set\n"); 5599 return -E1000_ERR_PHY; 5600 } 5601 5602 return E1000_SUCCESS; 5603 } 5604 5605 /** 5606 * em_read_sfp_data_byte - Reads SFP module data. 5607 * @hw: pointer to the HW structure 5608 * @offset: byte location offset to be read 5609 * @data: read data buffer pointer 5610 * 5611 * Reads one byte from SFP module data stored 5612 * in SFP resided EEPROM memory or SFP diagnostic area. 5613 * Function should be called with 5614 * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access 5615 * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters 5616 * access 5617 **/ 5618 int32_t em_read_sfp_data_byte(struct em_hw *hw, uint16_t offset, uint8_t *data) 5619 { 5620 uint32_t i = 0; 5621 uint32_t i2ccmd = 0; 5622 uint32_t data_local = 0; 5623 5624 DEBUGFUNC("em_read_sfp_data_byte"); 5625 5626 if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) { 5627 DEBUGOUT("I2CCMD command address exceeds upper limit\n"); 5628 return -E1000_ERR_PHY; 5629 } 5630 5631 /* Set up Op-code, EEPROM Address,in the I2CCMD 5632 * register. The MAC will take care of interfacing with the 5633 * EEPROM to retrieve the desired data. 5634 */ 5635 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 5636 E1000_I2CCMD_OPCODE_READ); 5637 5638 E1000_WRITE_REG(hw, I2CCMD, i2ccmd); 5639 5640 /* Poll the ready bit to see if the I2C read completed */ 5641 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 5642 usec_delay(50); 5643 data_local = E1000_READ_REG(hw, I2CCMD); 5644 if (data_local & E1000_I2CCMD_READY) 5645 break; 5646 } 5647 if (!(data_local & E1000_I2CCMD_READY)) { 5648 DEBUGOUT("I2CCMD Read did not complete\n"); 5649 return -E1000_ERR_PHY; 5650 } 5651 if (data_local & E1000_I2CCMD_ERROR) { 5652 DEBUGOUT("I2CCMD Error bit set\n"); 5653 return -E1000_ERR_PHY; 5654 } 5655 *data = (uint8_t) data_local & 0xFF; 5656 5657 return E1000_SUCCESS; 5658 } 5659 5660 /****************************************************************************** 5661 * Returns the PHY to the power-on reset state 5662 * 5663 * hw - Struct containing variables accessed by shared code 5664 *****************************************************************************/ 5665 int32_t 5666 em_phy_hw_reset(struct em_hw *hw) 5667 { 5668 uint32_t ctrl, ctrl_ext; 5669 uint32_t led_ctrl; 5670 int32_t ret_val; 5671 DEBUGFUNC("em_phy_hw_reset"); 5672 /* 5673 * In the case of the phy reset being blocked, it's not an error, we 5674 * simply return success without performing the reset. 5675 */ 5676 ret_val = em_check_phy_reset_block(hw); 5677 if (ret_val) 5678 return E1000_SUCCESS; 5679 5680 DEBUGOUT("Resetting Phy...\n"); 5681 5682 if (hw->mac_type > em_82543 && hw->mac_type != em_icp_xxxx) { 5683 if (em_swfw_sync_acquire(hw, hw->swfw)) { 5684 DEBUGOUT("Unable to acquire swfw sync\n"); 5685 return -E1000_ERR_SWFW_SYNC; 5686 } 5687 /* 5688 * Read the device control register and assert the 5689 * E1000_CTRL_PHY_RST bit. Then, take it out of reset. For 5690 * pre-em_82571 hardware, we delay for 10ms between the 5691 * assert and deassert. For em_82571 hardware and later, we 5692 * instead delay for 50us between and 10ms after the 5693 * deassertion. 5694 */ 5695 ctrl = E1000_READ_REG(hw, CTRL); 5696 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST); 5697 E1000_WRITE_FLUSH(hw); 5698 5699 if (hw->mac_type < em_82571) 5700 msec_delay(10); 5701 else 5702 usec_delay(100); 5703 5704 E1000_WRITE_REG(hw, CTRL, ctrl); 5705 E1000_WRITE_FLUSH(hw); 5706 5707 if (hw->mac_type >= em_82571) 5708 msec_delay_irq(10); 5709 em_swfw_sync_release(hw, hw->swfw); 5710 /* 5711 * the M88E1141_E_PHY_ID might need reset here, but nothing 5712 * proves it 5713 */ 5714 } else { 5715 /* 5716 * Read the Extended Device Control Register, assert the 5717 * PHY_RESET_DIR bit to put the PHY into reset. Then, take it 5718 * out of reset. 5719 */ 5720 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 5721 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; 5722 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; 5723 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 5724 E1000_WRITE_FLUSH(hw); 5725 msec_delay(10); 5726 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; 5727 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 5728 E1000_WRITE_FLUSH(hw); 5729 } 5730 usec_delay(150); 5731 5732 if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) { 5733 /* Configure activity LED after PHY reset */ 5734 led_ctrl = E1000_READ_REG(hw, LEDCTL); 5735 led_ctrl &= IGP_ACTIVITY_LED_MASK; 5736 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 5737 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 5738 } 5739 /* Wait for FW to finish PHY configuration. */ 5740 ret_val = em_get_phy_cfg_done(hw); 5741 if (ret_val != E1000_SUCCESS) 5742 return ret_val; 5743 em_release_software_semaphore(hw); 5744 5745 if ((hw->mac_type == em_ich8lan) && (hw->phy_type == em_phy_igp_3)) 5746 ret_val = em_init_lcd_from_nvm(hw); 5747 5748 return ret_val; 5749 } 5750 5751 /***************************************************************************** 5752 * SW-based LCD Configuration. 5753 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are 5754 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit 5755 * in NVM determines whether HW should configure LPLU and Gbe Disable. 5756 *****************************************************************************/ 5757 int32_t 5758 em_oem_bits_config_pchlan(struct em_hw *hw, boolean_t d0_state) 5759 { 5760 int32_t ret_val = E1000_SUCCESS; 5761 uint32_t mac_reg; 5762 uint16_t oem_reg; 5763 uint16_t swfw = E1000_SWFW_PHY0_SM; 5764 5765 if (hw->mac_type < em_pchlan) 5766 return ret_val; 5767 5768 ret_val = em_swfw_sync_acquire(hw, swfw); 5769 if (ret_val) 5770 return ret_val; 5771 5772 if (hw->mac_type == em_pchlan) { 5773 mac_reg = E1000_READ_REG(hw, EXTCNF_CTRL); 5774 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) 5775 goto out; 5776 } 5777 5778 mac_reg = E1000_READ_REG(hw, FEXTNVM); 5779 if (!(mac_reg & FEXTNVM_SW_CONFIG_ICH8M)) 5780 goto out; 5781 5782 mac_reg = E1000_READ_REG(hw, PHY_CTRL); 5783 5784 ret_val = em_read_phy_reg(hw, HV_OEM_BITS, &oem_reg); 5785 if (ret_val) 5786 goto out; 5787 5788 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU); 5789 5790 if (d0_state) { 5791 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE) 5792 oem_reg |= HV_OEM_BITS_GBE_DIS; 5793 5794 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU) 5795 oem_reg |= HV_OEM_BITS_LPLU; 5796 /* Restart auto-neg to activate the bits */ 5797 if (!em_check_phy_reset_block(hw)) 5798 oem_reg |= HV_OEM_BITS_RESTART_AN; 5799 5800 } else { 5801 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE | 5802 E1000_PHY_CTRL_NOND0A_GBE_DISABLE)) 5803 oem_reg |= HV_OEM_BITS_GBE_DIS; 5804 5805 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU | 5806 E1000_PHY_CTRL_NOND0A_LPLU)) 5807 oem_reg |= HV_OEM_BITS_LPLU; 5808 } 5809 5810 ret_val = em_write_phy_reg(hw, HV_OEM_BITS, oem_reg); 5811 5812 out: 5813 em_swfw_sync_release(hw, swfw); 5814 5815 return ret_val; 5816 } 5817 5818 5819 /****************************************************************************** 5820 * Resets the PHY 5821 * 5822 * hw - Struct containing variables accessed by shared code 5823 * 5824 * Sets bit 15 of the MII Control register 5825 *****************************************************************************/ 5826 int32_t 5827 em_phy_reset(struct em_hw *hw) 5828 { 5829 int32_t ret_val; 5830 uint16_t phy_data; 5831 DEBUGFUNC("em_phy_reset"); 5832 /* 5833 * In the case of the phy reset being blocked, it's not an error, we 5834 * simply return success without performing the reset. 5835 */ 5836 ret_val = em_check_phy_reset_block(hw); 5837 if (ret_val) 5838 return E1000_SUCCESS; 5839 5840 switch (hw->phy_type) { 5841 case em_phy_igp: 5842 case em_phy_igp_2: 5843 case em_phy_igp_3: 5844 case em_phy_ife: 5845 ret_val = em_phy_hw_reset(hw); 5846 if (ret_val) 5847 return ret_val; 5848 break; 5849 default: 5850 ret_val = em_read_phy_reg(hw, PHY_CTRL, &phy_data); 5851 if (ret_val) 5852 return ret_val; 5853 5854 phy_data |= MII_CR_RESET; 5855 ret_val = em_write_phy_reg(hw, PHY_CTRL, phy_data); 5856 if (ret_val) 5857 return ret_val; 5858 5859 usec_delay(1); 5860 break; 5861 } 5862 5863 /* Allow time for h/w to get to a quiescent state after reset */ 5864 msec_delay(10); 5865 5866 if (hw->phy_type == em_phy_igp || hw->phy_type == em_phy_igp_2) 5867 em_phy_init_script(hw); 5868 5869 if (hw->mac_type == em_pchlan) { 5870 ret_val = em_hv_phy_workarounds_ich8lan(hw); 5871 if (ret_val) 5872 return ret_val; 5873 } else if (hw->mac_type == em_pch2lan) { 5874 ret_val = em_lv_phy_workarounds_ich8lan(hw); 5875 if (ret_val) 5876 return ret_val; 5877 } 5878 5879 if (hw->mac_type >= em_pchlan) { 5880 ret_val = em_oem_bits_config_pchlan(hw, TRUE); 5881 if (ret_val) 5882 return ret_val; 5883 } 5884 5885 /* Ungate automatic PHY configuration on non-managed 82579 */ 5886 if ((hw->mac_type == em_pch2lan) && 5887 !(E1000_READ_REG(hw, FWSM) & E1000_FWSM_FW_VALID)) { 5888 msec_delay(10); 5889 em_gate_hw_phy_config_ich8lan(hw, FALSE); 5890 } 5891 5892 if (hw->phy_id == M88E1512_E_PHY_ID) { 5893 ret_val = em_initialize_M88E1512_phy(hw); 5894 if (ret_val) 5895 return ret_val; 5896 } 5897 5898 return E1000_SUCCESS; 5899 } 5900 5901 /****************************************************************************** 5902 * Work-around for 82566 Kumeran PCS lock loss: 5903 * On link status change (i.e. PCI reset, speed change) and link is up and 5904 * speed is gigabit- 5905 * 0) if workaround is optionally disabled do nothing 5906 * 1) wait 1ms for Kumeran link to come up 5907 * 2) check Kumeran Diagnostic register PCS lock loss bit 5908 * 3) if not set the link is locked (all is good), otherwise... 5909 * 4) reset the PHY 5910 * 5) repeat up to 10 times 5911 * Note: this is only called for IGP3 copper when speed is 1gb. 5912 * 5913 * hw - struct containing variables accessed by shared code 5914 *****************************************************************************/ 5915 STATIC int32_t 5916 em_kumeran_lock_loss_workaround(struct em_hw *hw) 5917 { 5918 int32_t ret_val; 5919 int32_t reg; 5920 int32_t cnt; 5921 uint16_t phy_data; 5922 if (hw->kmrn_lock_loss_workaround_disabled) 5923 return E1000_SUCCESS; 5924 /* 5925 * Make sure link is up before proceeding. If not just return. 5926 * Attempting this while link is negotiating fouled up link stability 5927 */ 5928 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 5929 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 5930 5931 if (phy_data & MII_SR_LINK_STATUS) { 5932 for (cnt = 0; cnt < 10; cnt++) { 5933 /* read once to clear */ 5934 ret_val = em_read_phy_reg(hw, IGP3_KMRN_DIAG, 5935 &phy_data); 5936 if (ret_val) 5937 return ret_val; 5938 /* and again to get new status */ 5939 ret_val = em_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data); 5940 if (ret_val) 5941 return ret_val; 5942 5943 /* check for PCS lock */ 5944 if (!(phy_data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) 5945 return E1000_SUCCESS; 5946 5947 /* Issue PHY reset */ 5948 em_phy_hw_reset(hw); 5949 msec_delay_irq(5); 5950 } 5951 /* Disable GigE link negotiation */ 5952 reg = E1000_READ_REG(hw, PHY_CTRL); 5953 E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE 5954 | E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 5955 5956 /* unable to acquire PCS lock */ 5957 return E1000_ERR_PHY; 5958 } 5959 return E1000_SUCCESS; 5960 } 5961 5962 /****************************************************************************** 5963 * Reads and matches the expected PHY address for known PHY IDs 5964 * 5965 * hw - Struct containing variables accessed by shared code 5966 *****************************************************************************/ 5967 STATIC int32_t 5968 em_match_gig_phy(struct em_hw *hw) 5969 { 5970 int32_t phy_init_status, ret_val; 5971 uint16_t phy_id_high, phy_id_low; 5972 boolean_t match = FALSE; 5973 DEBUGFUNC("em_match_gig_phy"); 5974 5975 ret_val = em_read_phy_reg(hw, PHY_ID1, &phy_id_high); 5976 if (ret_val) 5977 return ret_val; 5978 5979 hw->phy_id = (uint32_t) (phy_id_high << 16); 5980 usec_delay(20); 5981 ret_val = em_read_phy_reg(hw, PHY_ID2, &phy_id_low); 5982 if (ret_val) 5983 return ret_val; 5984 5985 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK); 5986 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK; 5987 5988 switch (hw->mac_type) { 5989 case em_82543: 5990 if (hw->phy_id == M88E1000_E_PHY_ID) 5991 match = TRUE; 5992 break; 5993 case em_82544: 5994 if (hw->phy_id == M88E1000_I_PHY_ID) 5995 match = TRUE; 5996 break; 5997 case em_82540: 5998 case em_82545: 5999 case em_82545_rev_3: 6000 case em_82546: 6001 case em_82546_rev_3: 6002 if (hw->phy_id == M88E1011_I_PHY_ID) 6003 match = TRUE; 6004 break; 6005 case em_82541: 6006 case em_82541_rev_2: 6007 case em_82547: 6008 case em_82547_rev_2: 6009 if (hw->phy_id == IGP01E1000_I_PHY_ID) 6010 match = TRUE; 6011 break; 6012 case em_82573: 6013 if (hw->phy_id == M88E1111_I_PHY_ID) 6014 match = TRUE; 6015 break; 6016 case em_82574: 6017 if (hw->phy_id == BME1000_E_PHY_ID) 6018 match = TRUE; 6019 break; 6020 case em_82575: 6021 case em_82576: 6022 if (hw->phy_id == M88E1000_E_PHY_ID) 6023 match = TRUE; 6024 if (hw->phy_id == IGP01E1000_I_PHY_ID) 6025 match = TRUE; 6026 if (hw->phy_id == IGP03E1000_E_PHY_ID) 6027 match = TRUE; 6028 break; 6029 case em_82580: 6030 case em_i210: 6031 case em_i350: 6032 if (hw->phy_id == I82580_I_PHY_ID || 6033 hw->phy_id == I210_I_PHY_ID || 6034 hw->phy_id == I347AT4_E_PHY_ID || 6035 hw->phy_id == I350_I_PHY_ID || 6036 hw->phy_id == M88E1111_I_PHY_ID || 6037 hw->phy_id == M88E1112_E_PHY_ID || 6038 hw->phy_id == M88E1543_E_PHY_ID || 6039 hw->phy_id == M88E1512_E_PHY_ID) { 6040 uint32_t mdic; 6041 6042 mdic = EM_READ_REG(hw, E1000_MDICNFG); 6043 if (mdic & E1000_MDICNFG_EXT_MDIO) { 6044 mdic &= E1000_MDICNFG_PHY_MASK; 6045 hw->phy_addr = mdic >> E1000_MDICNFG_PHY_SHIFT; 6046 DEBUGOUT1("MDICNFG PHY ADDR %d", 6047 mdic >> E1000_MDICNFG_PHY_SHIFT); 6048 } 6049 match = TRUE; 6050 } 6051 break; 6052 case em_80003es2lan: 6053 if (hw->phy_id == GG82563_E_PHY_ID) 6054 match = TRUE; 6055 break; 6056 case em_ich8lan: 6057 case em_ich9lan: 6058 case em_ich10lan: 6059 case em_pchlan: 6060 case em_pch2lan: 6061 if (hw->phy_id == IGP03E1000_E_PHY_ID) 6062 match = TRUE; 6063 if (hw->phy_id == IFE_E_PHY_ID) 6064 match = TRUE; 6065 if (hw->phy_id == IFE_PLUS_E_PHY_ID) 6066 match = TRUE; 6067 if (hw->phy_id == IFE_C_E_PHY_ID) 6068 match = TRUE; 6069 if (hw->phy_id == BME1000_E_PHY_ID) 6070 match = TRUE; 6071 if (hw->phy_id == I82577_E_PHY_ID) 6072 match = TRUE; 6073 if (hw->phy_id == I82578_E_PHY_ID) 6074 match = TRUE; 6075 if (hw->phy_id == I82579_E_PHY_ID) 6076 match = TRUE; 6077 break; 6078 case em_pch_lpt: 6079 case em_pch_spt: 6080 case em_pch_cnp: 6081 if (hw->phy_id == I217_E_PHY_ID) 6082 match = TRUE; 6083 break; 6084 case em_icp_xxxx: 6085 if (hw->phy_id == M88E1141_E_PHY_ID) 6086 match = TRUE; 6087 if (hw->phy_id == RTL8211_E_PHY_ID) 6088 match = TRUE; 6089 break; 6090 default: 6091 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type); 6092 return -E1000_ERR_CONFIG; 6093 } 6094 phy_init_status = em_set_phy_type(hw); 6095 6096 if ((match) && (phy_init_status == E1000_SUCCESS)) { 6097 DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id); 6098 return E1000_SUCCESS; 6099 } 6100 DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id); 6101 return -E1000_ERR_PHY; 6102 } 6103 6104 /****************************************************************************** 6105 * Probes the expected PHY address for known PHY IDs 6106 * 6107 * hw - Struct containing variables accessed by shared code 6108 *****************************************************************************/ 6109 STATIC int32_t 6110 em_detect_gig_phy(struct em_hw *hw) 6111 { 6112 int32_t ret_val, i; 6113 DEBUGFUNC("em_detect_gig_phy"); 6114 6115 if (hw->phy_id != 0) 6116 return E1000_SUCCESS; 6117 6118 /* default phy address, most phys reside here, but not all (ICH10) */ 6119 if (hw->mac_type != em_icp_xxxx) 6120 hw->phy_addr = 1; 6121 else 6122 hw->phy_addr = 0; /* There is a phy at phy_addr 0 on EP80579 */ 6123 6124 /* 6125 * The 82571 firmware may still be configuring the PHY. In this 6126 * case, we cannot access the PHY until the configuration is done. 6127 * So we explicitly set the PHY values. 6128 */ 6129 if (hw->mac_type == em_82571 || 6130 hw->mac_type == em_82572) { 6131 hw->phy_id = IGP01E1000_I_PHY_ID; 6132 hw->phy_type = em_phy_igp_2; 6133 return E1000_SUCCESS; 6134 } 6135 6136 /* 6137 * Some of the fiber cards dont have a phy, so we must exit cleanly 6138 * here 6139 */ 6140 if ((hw->media_type == em_media_type_fiber) && 6141 (hw->mac_type == em_82542_rev2_0 || 6142 hw->mac_type == em_82542_rev2_1 || 6143 hw->mac_type == em_82543 || 6144 hw->mac_type == em_82573 || 6145 hw->mac_type == em_82574 || 6146 hw->mac_type == em_80003es2lan)) { 6147 hw->phy_type = em_phy_undefined; 6148 return E1000_SUCCESS; 6149 } 6150 6151 if ((hw->media_type == em_media_type_internal_serdes || 6152 hw->media_type == em_media_type_fiber) && 6153 hw->mac_type >= em_82575) { 6154 hw->phy_type = em_phy_undefined; 6155 return E1000_SUCCESS; 6156 } 6157 6158 /* 6159 * Up to 82543 (incl), we need reset the phy, or it might not get 6160 * detected 6161 */ 6162 if (hw->mac_type <= em_82543) { 6163 ret_val = em_phy_hw_reset(hw); 6164 if (ret_val) 6165 return ret_val; 6166 } 6167 /* 6168 * ESB-2 PHY reads require em_phy_gg82563 to be set because of a 6169 * work- around that forces PHY page 0 to be set or the reads fail. 6170 * The rest of the code in this routine uses em_read_phy_reg to read 6171 * the PHY ID. So for ESB-2 we need to have this set so our reads 6172 * won't fail. If the attached PHY is not a em_phy_gg82563, the 6173 * routines below will figure this out as well. 6174 */ 6175 if (hw->mac_type == em_80003es2lan) 6176 hw->phy_type = em_phy_gg82563; 6177 6178 /* Power on SGMII phy if it is disabled */ 6179 if (hw->mac_type == em_82580 || hw->mac_type == em_i210 || 6180 hw->mac_type == em_i350) { 6181 uint32_t ctrl_ext = EM_READ_REG(hw, E1000_CTRL_EXT); 6182 EM_WRITE_REG(hw, E1000_CTRL_EXT, 6183 ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA); 6184 E1000_WRITE_FLUSH(hw); 6185 msec_delay(300); 6186 } 6187 6188 /* Read the PHY ID Registers to identify which PHY is onboard. */ 6189 for (i = 1; i < 8; i++) { 6190 /* 6191 * hw->phy_addr may be modified down in the call stack, 6192 * we can't use it as loop variable. 6193 */ 6194 hw->phy_addr = i; 6195 ret_val = em_match_gig_phy(hw); 6196 if (ret_val == E1000_SUCCESS) 6197 return E1000_SUCCESS; 6198 } 6199 return -E1000_ERR_PHY; 6200 } 6201 6202 /****************************************************************************** 6203 * Resets the PHY's DSP 6204 * 6205 * hw - Struct containing variables accessed by shared code 6206 *****************************************************************************/ 6207 static int32_t 6208 em_phy_reset_dsp(struct em_hw *hw) 6209 { 6210 int32_t ret_val; 6211 DEBUGFUNC("em_phy_reset_dsp"); 6212 6213 do { 6214 if (hw->phy_type != em_phy_gg82563) { 6215 ret_val = em_write_phy_reg(hw, 29, 0x001d); 6216 if (ret_val) 6217 break; 6218 } 6219 ret_val = em_write_phy_reg(hw, 30, 0x00c1); 6220 if (ret_val) 6221 break; 6222 ret_val = em_write_phy_reg(hw, 30, 0x0000); 6223 if (ret_val) 6224 break; 6225 ret_val = E1000_SUCCESS; 6226 } while (0); 6227 6228 return ret_val; 6229 } 6230 6231 /****************************************************************************** 6232 * Sets up eeprom variables in the hw struct. Must be called after mac_type 6233 * is configured. Additionally, if this is ICH8, the flash controller GbE 6234 * registers must be mapped, or this will crash. 6235 * 6236 * hw - Struct containing variables accessed by shared code 6237 *****************************************************************************/ 6238 int32_t 6239 em_init_eeprom_params(struct em_hw *hw) 6240 { 6241 struct em_eeprom_info *eeprom = &hw->eeprom; 6242 uint32_t eecd = E1000_READ_REG(hw, EECD); 6243 int32_t ret_val = E1000_SUCCESS; 6244 uint16_t eeprom_size; 6245 DEBUGFUNC("em_init_eeprom_params"); 6246 6247 switch (hw->mac_type) { 6248 case em_82542_rev2_0: 6249 case em_82542_rev2_1: 6250 case em_82543: 6251 case em_82544: 6252 eeprom->type = em_eeprom_microwire; 6253 eeprom->word_size = 64; 6254 eeprom->opcode_bits = 3; 6255 eeprom->address_bits = 6; 6256 eeprom->delay_usec = 50; 6257 eeprom->use_eerd = FALSE; 6258 eeprom->use_eewr = FALSE; 6259 break; 6260 case em_82540: 6261 case em_82545: 6262 case em_82545_rev_3: 6263 case em_icp_xxxx: 6264 case em_82546: 6265 case em_82546_rev_3: 6266 eeprom->type = em_eeprom_microwire; 6267 eeprom->opcode_bits = 3; 6268 eeprom->delay_usec = 50; 6269 if (eecd & E1000_EECD_SIZE) { 6270 eeprom->word_size = 256; 6271 eeprom->address_bits = 8; 6272 } else { 6273 eeprom->word_size = 64; 6274 eeprom->address_bits = 6; 6275 } 6276 eeprom->use_eerd = FALSE; 6277 eeprom->use_eewr = FALSE; 6278 break; 6279 case em_82541: 6280 case em_82541_rev_2: 6281 case em_82547: 6282 case em_82547_rev_2: 6283 if (eecd & E1000_EECD_TYPE) { 6284 eeprom->type = em_eeprom_spi; 6285 eeprom->opcode_bits = 8; 6286 eeprom->delay_usec = 1; 6287 if (eecd & E1000_EECD_ADDR_BITS) { 6288 eeprom->page_size = 32; 6289 eeprom->address_bits = 16; 6290 } else { 6291 eeprom->page_size = 8; 6292 eeprom->address_bits = 8; 6293 } 6294 } else { 6295 eeprom->type = em_eeprom_microwire; 6296 eeprom->opcode_bits = 3; 6297 eeprom->delay_usec = 50; 6298 if (eecd & E1000_EECD_ADDR_BITS) { 6299 eeprom->word_size = 256; 6300 eeprom->address_bits = 8; 6301 } else { 6302 eeprom->word_size = 64; 6303 eeprom->address_bits = 6; 6304 } 6305 } 6306 eeprom->use_eerd = FALSE; 6307 eeprom->use_eewr = FALSE; 6308 break; 6309 case em_82571: 6310 case em_82572: 6311 eeprom->type = em_eeprom_spi; 6312 eeprom->opcode_bits = 8; 6313 eeprom->delay_usec = 1; 6314 if (eecd & E1000_EECD_ADDR_BITS) { 6315 eeprom->page_size = 32; 6316 eeprom->address_bits = 16; 6317 } else { 6318 eeprom->page_size = 8; 6319 eeprom->address_bits = 8; 6320 } 6321 eeprom->use_eerd = FALSE; 6322 eeprom->use_eewr = FALSE; 6323 break; 6324 case em_82573: 6325 case em_82574: 6326 case em_82575: 6327 case em_82576: 6328 case em_82580: 6329 case em_i210: 6330 case em_i350: 6331 eeprom->type = em_eeprom_spi; 6332 eeprom->opcode_bits = 8; 6333 eeprom->delay_usec = 1; 6334 if (eecd & E1000_EECD_ADDR_BITS) { 6335 eeprom->page_size = 32; 6336 eeprom->address_bits = 16; 6337 } else { 6338 eeprom->page_size = 8; 6339 eeprom->address_bits = 8; 6340 } 6341 eeprom->use_eerd = TRUE; 6342 eeprom->use_eewr = TRUE; 6343 if (em_is_onboard_nvm_eeprom(hw) == FALSE) { 6344 eeprom->type = em_eeprom_flash; 6345 eeprom->word_size = 2048; 6346 /* 6347 * Ensure that the Autonomous FLASH update bit is 6348 * cleared due to Flash update issue on parts which 6349 * use a FLASH for NVM. 6350 */ 6351 eecd &= ~E1000_EECD_AUPDEN; 6352 E1000_WRITE_REG(hw, EECD, eecd); 6353 } 6354 if (em_get_flash_presence_i210(hw) == FALSE) { 6355 eeprom->type = em_eeprom_invm; 6356 eeprom->word_size = INVM_SIZE; 6357 eeprom->use_eerd = FALSE; 6358 eeprom->use_eewr = FALSE; 6359 } 6360 break; 6361 case em_80003es2lan: 6362 eeprom->type = em_eeprom_spi; 6363 eeprom->opcode_bits = 8; 6364 eeprom->delay_usec = 1; 6365 if (eecd & E1000_EECD_ADDR_BITS) { 6366 eeprom->page_size = 32; 6367 eeprom->address_bits = 16; 6368 } else { 6369 eeprom->page_size = 8; 6370 eeprom->address_bits = 8; 6371 } 6372 eeprom->use_eerd = TRUE; 6373 eeprom->use_eewr = FALSE; 6374 break; 6375 case em_ich8lan: 6376 case em_ich9lan: 6377 case em_ich10lan: 6378 case em_pchlan: 6379 case em_pch2lan: 6380 case em_pch_lpt: 6381 { 6382 int32_t i = 0; 6383 uint32_t flash_size = 6384 E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_GFPREG); 6385 eeprom->type = em_eeprom_ich8; 6386 eeprom->use_eerd = FALSE; 6387 eeprom->use_eewr = FALSE; 6388 eeprom->word_size = E1000_SHADOW_RAM_WORDS; 6389 /* 6390 * Zero the shadow RAM structure. But don't load it 6391 * from NVM so as to save time for driver init 6392 */ 6393 if (hw->eeprom_shadow_ram != NULL) { 6394 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 6395 hw->eeprom_shadow_ram[i].modified = 6396 FALSE; 6397 hw->eeprom_shadow_ram[i].eeprom_word = 6398 0xFFFF; 6399 } 6400 } 6401 hw->flash_base_addr = (flash_size & 6402 ICH_GFPREG_BASE_MASK) * ICH_FLASH_SECTOR_SIZE; 6403 6404 hw->flash_bank_size = ((flash_size >> 16) & 6405 ICH_GFPREG_BASE_MASK) + 1; 6406 hw->flash_bank_size -= (flash_size & 6407 ICH_GFPREG_BASE_MASK); 6408 6409 hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE; 6410 6411 hw->flash_bank_size /= 2 * sizeof(uint16_t); 6412 6413 break; 6414 } 6415 case em_pch_spt: 6416 case em_pch_cnp: 6417 { 6418 int32_t i = 0; 6419 uint32_t flash_size = EM_READ_REG(hw, 0xc /* STRAP */); 6420 6421 eeprom->type = em_eeprom_ich8; 6422 eeprom->use_eerd = FALSE; 6423 eeprom->use_eewr = FALSE; 6424 eeprom->word_size = E1000_SHADOW_RAM_WORDS; 6425 /* 6426 * Zero the shadow RAM structure. But don't load it 6427 * from NVM so as to save time for driver init 6428 */ 6429 if (hw->eeprom_shadow_ram != NULL) { 6430 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 6431 hw->eeprom_shadow_ram[i].modified = 6432 FALSE; 6433 hw->eeprom_shadow_ram[i].eeprom_word = 6434 0xFFFF; 6435 } 6436 } 6437 hw->flash_base_addr = 0; 6438 flash_size = ((flash_size >> 1) & 0x1f) + 1; 6439 flash_size *= 4096; 6440 hw->flash_bank_size = flash_size / 4; 6441 } 6442 break; 6443 default: 6444 break; 6445 } 6446 6447 if (eeprom->type == em_eeprom_spi) { 6448 /* 6449 * eeprom_size will be an enum [0..8] that maps to eeprom 6450 * sizes 128B to 32KB (incremented by powers of 2). 6451 */ 6452 if (hw->mac_type <= em_82547_rev_2) { 6453 /* Set to default value for initial eeprom read. */ 6454 eeprom->word_size = 64; 6455 ret_val = em_read_eeprom(hw, EEPROM_CFG, 1, 6456 &eeprom_size); 6457 if (ret_val) 6458 return ret_val; 6459 eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> 6460 EEPROM_SIZE_SHIFT; 6461 /* 6462 * 256B eeprom size was not supported in earlier 6463 * hardware, so we bump eeprom_size up one to ensure 6464 * that "1" (which maps to 256B) is never the result 6465 * used in the shifting logic below. 6466 */ 6467 if (eeprom_size) 6468 eeprom_size++; 6469 } else { 6470 eeprom_size = (uint16_t) ( 6471 (eecd & E1000_EECD_SIZE_EX_MASK) >> 6472 E1000_EECD_SIZE_EX_SHIFT); 6473 } 6474 6475 /* EEPROM access above 16k is unsupported */ 6476 if (eeprom_size + EEPROM_WORD_SIZE_SHIFT > 6477 EEPROM_WORD_SIZE_SHIFT_MAX) { 6478 eeprom->word_size = 1 << EEPROM_WORD_SIZE_SHIFT_MAX; 6479 } else { 6480 eeprom->word_size = 1 << 6481 (eeprom_size + EEPROM_WORD_SIZE_SHIFT); 6482 } 6483 } 6484 return ret_val; 6485 } 6486 6487 /****************************************************************************** 6488 * Raises the EEPROM's clock input. 6489 * 6490 * hw - Struct containing variables accessed by shared code 6491 * eecd - EECD's current value 6492 *****************************************************************************/ 6493 static void 6494 em_raise_ee_clk(struct em_hw *hw, uint32_t *eecd) 6495 { 6496 /* 6497 * Raise the clock input to the EEPROM (by setting the SK bit), and 6498 * then wait <delay> microseconds. 6499 */ 6500 *eecd = *eecd | E1000_EECD_SK; 6501 E1000_WRITE_REG(hw, EECD, *eecd); 6502 E1000_WRITE_FLUSH(hw); 6503 usec_delay(hw->eeprom.delay_usec); 6504 } 6505 6506 /****************************************************************************** 6507 * Lowers the EEPROM's clock input. 6508 * 6509 * hw - Struct containing variables accessed by shared code 6510 * eecd - EECD's current value 6511 *****************************************************************************/ 6512 static void 6513 em_lower_ee_clk(struct em_hw *hw, uint32_t *eecd) 6514 { 6515 /* 6516 * Lower the clock input to the EEPROM (by clearing the SK bit), and 6517 * then wait 50 microseconds. 6518 */ 6519 *eecd = *eecd & ~E1000_EECD_SK; 6520 E1000_WRITE_REG(hw, EECD, *eecd); 6521 E1000_WRITE_FLUSH(hw); 6522 usec_delay(hw->eeprom.delay_usec); 6523 } 6524 6525 /****************************************************************************** 6526 * Shift data bits out to the EEPROM. 6527 * 6528 * hw - Struct containing variables accessed by shared code 6529 * data - data to send to the EEPROM 6530 * count - number of bits to shift out 6531 *****************************************************************************/ 6532 static void 6533 em_shift_out_ee_bits(struct em_hw *hw, uint16_t data, uint16_t count) 6534 { 6535 struct em_eeprom_info *eeprom = &hw->eeprom; 6536 uint32_t eecd; 6537 uint32_t mask; 6538 /* 6539 * We need to shift "count" bits out to the EEPROM. So, value in the 6540 * "data" parameter will be shifted out to the EEPROM one bit at a 6541 * time. In order to do this, "data" must be broken down into bits. 6542 */ 6543 mask = 0x01 << (count - 1); 6544 eecd = E1000_READ_REG(hw, EECD); 6545 if (eeprom->type == em_eeprom_microwire) { 6546 eecd &= ~E1000_EECD_DO; 6547 } else if (eeprom->type == em_eeprom_spi) { 6548 eecd |= E1000_EECD_DO; 6549 } 6550 do { 6551 /* 6552 * A "1" is shifted out to the EEPROM by setting bit "DI" to 6553 * a "1", and then raising and then lowering the clock (the 6554 * SK bit controls the clock input to the EEPROM). A "0" is 6555 * shifted out to the EEPROM by setting "DI" to "0" and then 6556 * raising and then lowering the clock. 6557 */ 6558 eecd &= ~E1000_EECD_DI; 6559 6560 if (data & mask) 6561 eecd |= E1000_EECD_DI; 6562 6563 E1000_WRITE_REG(hw, EECD, eecd); 6564 E1000_WRITE_FLUSH(hw); 6565 6566 usec_delay(eeprom->delay_usec); 6567 6568 em_raise_ee_clk(hw, &eecd); 6569 em_lower_ee_clk(hw, &eecd); 6570 6571 mask = mask >> 1; 6572 6573 } while (mask); 6574 6575 /* We leave the "DI" bit set to "0" when we leave this routine. */ 6576 eecd &= ~E1000_EECD_DI; 6577 E1000_WRITE_REG(hw, EECD, eecd); 6578 } 6579 6580 /****************************************************************************** 6581 * Shift data bits in from the EEPROM 6582 * 6583 * hw - Struct containing variables accessed by shared code 6584 *****************************************************************************/ 6585 static uint16_t 6586 em_shift_in_ee_bits(struct em_hw *hw, uint16_t count) 6587 { 6588 uint32_t eecd; 6589 uint32_t i; 6590 uint16_t data; 6591 /* 6592 * In order to read a register from the EEPROM, we need to shift 6593 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising 6594 * the clock input to the EEPROM (setting the SK bit), and then 6595 * reading the value of the "DO" bit. During this "shifting in" 6596 * process the "DI" bit should always be clear. 6597 */ 6598 6599 eecd = E1000_READ_REG(hw, EECD); 6600 6601 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 6602 data = 0; 6603 6604 for (i = 0; i < count; i++) { 6605 data = data << 1; 6606 em_raise_ee_clk(hw, &eecd); 6607 6608 eecd = E1000_READ_REG(hw, EECD); 6609 6610 eecd &= ~(E1000_EECD_DI); 6611 if (eecd & E1000_EECD_DO) 6612 data |= 1; 6613 6614 em_lower_ee_clk(hw, &eecd); 6615 } 6616 6617 return data; 6618 } 6619 /****************************************************************************** 6620 * Prepares EEPROM for access 6621 * 6622 * hw - Struct containing variables accessed by shared code 6623 * 6624 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This 6625 * function should be called before issuing a command to the EEPROM. 6626 *****************************************************************************/ 6627 static int32_t 6628 em_acquire_eeprom(struct em_hw *hw) 6629 { 6630 struct em_eeprom_info *eeprom = &hw->eeprom; 6631 uint32_t eecd, i = 0; 6632 DEBUGFUNC("em_acquire_eeprom"); 6633 6634 if (em_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM)) 6635 return -E1000_ERR_SWFW_SYNC; 6636 eecd = E1000_READ_REG(hw, EECD); 6637 6638 if ((hw->mac_type != em_82573) && (hw->mac_type != em_82574)) { 6639 /* Request EEPROM Access */ 6640 if (hw->mac_type > em_82544) { 6641 eecd |= E1000_EECD_REQ; 6642 E1000_WRITE_REG(hw, EECD, eecd); 6643 eecd = E1000_READ_REG(hw, EECD); 6644 while ((!(eecd & E1000_EECD_GNT)) && 6645 (i < E1000_EEPROM_GRANT_ATTEMPTS)) { 6646 i++; 6647 usec_delay(5); 6648 eecd = E1000_READ_REG(hw, EECD); 6649 } 6650 if (!(eecd & E1000_EECD_GNT)) { 6651 eecd &= ~E1000_EECD_REQ; 6652 E1000_WRITE_REG(hw, EECD, eecd); 6653 DEBUGOUT("Could not acquire EEPROM grant\n"); 6654 em_swfw_sync_release(hw, E1000_SWFW_EEP_SM); 6655 return -E1000_ERR_EEPROM; 6656 } 6657 } 6658 } 6659 6660 /* Setup EEPROM for Read/Write */ 6661 if (eeprom->type == em_eeprom_microwire) { 6662 /* Clear SK and DI */ 6663 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK); 6664 E1000_WRITE_REG(hw, EECD, eecd); 6665 6666 /* Set CS */ 6667 eecd |= E1000_EECD_CS; 6668 E1000_WRITE_REG(hw, EECD, eecd); 6669 } else if (eeprom->type == em_eeprom_spi) { 6670 /* Clear SK and CS */ 6671 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 6672 E1000_WRITE_REG(hw, EECD, eecd); 6673 usec_delay(1); 6674 } 6675 return E1000_SUCCESS; 6676 } 6677 6678 /****************************************************************************** 6679 * Returns EEPROM to a "standby" state 6680 * 6681 * hw - Struct containing variables accessed by shared code 6682 *****************************************************************************/ 6683 static void 6684 em_standby_eeprom(struct em_hw *hw) 6685 { 6686 struct em_eeprom_info *eeprom = &hw->eeprom; 6687 uint32_t eecd; 6688 eecd = E1000_READ_REG(hw, EECD); 6689 6690 if (eeprom->type == em_eeprom_microwire) { 6691 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 6692 E1000_WRITE_REG(hw, EECD, eecd); 6693 E1000_WRITE_FLUSH(hw); 6694 usec_delay(eeprom->delay_usec); 6695 6696 /* Clock high */ 6697 eecd |= E1000_EECD_SK; 6698 E1000_WRITE_REG(hw, EECD, eecd); 6699 E1000_WRITE_FLUSH(hw); 6700 usec_delay(eeprom->delay_usec); 6701 6702 /* Select EEPROM */ 6703 eecd |= E1000_EECD_CS; 6704 E1000_WRITE_REG(hw, EECD, eecd); 6705 E1000_WRITE_FLUSH(hw); 6706 usec_delay(eeprom->delay_usec); 6707 6708 /* Clock low */ 6709 eecd &= ~E1000_EECD_SK; 6710 E1000_WRITE_REG(hw, EECD, eecd); 6711 E1000_WRITE_FLUSH(hw); 6712 usec_delay(eeprom->delay_usec); 6713 } else if (eeprom->type == em_eeprom_spi) { 6714 /* Toggle CS to flush commands */ 6715 eecd |= E1000_EECD_CS; 6716 E1000_WRITE_REG(hw, EECD, eecd); 6717 E1000_WRITE_FLUSH(hw); 6718 usec_delay(eeprom->delay_usec); 6719 eecd &= ~E1000_EECD_CS; 6720 E1000_WRITE_REG(hw, EECD, eecd); 6721 E1000_WRITE_FLUSH(hw); 6722 usec_delay(eeprom->delay_usec); 6723 } 6724 } 6725 6726 /****************************************************************************** 6727 * Terminates a command by inverting the EEPROM's chip select pin 6728 * 6729 * hw - Struct containing variables accessed by shared code 6730 *****************************************************************************/ 6731 static void 6732 em_release_eeprom(struct em_hw *hw) 6733 { 6734 uint32_t eecd; 6735 DEBUGFUNC("em_release_eeprom"); 6736 6737 eecd = E1000_READ_REG(hw, EECD); 6738 6739 if (hw->eeprom.type == em_eeprom_spi) { 6740 eecd |= E1000_EECD_CS; /* Pull CS high */ 6741 eecd &= ~E1000_EECD_SK; /* Lower SCK */ 6742 6743 E1000_WRITE_REG(hw, EECD, eecd); 6744 6745 usec_delay(hw->eeprom.delay_usec); 6746 } else if (hw->eeprom.type == em_eeprom_microwire) { 6747 /* cleanup eeprom */ 6748 6749 /* CS on Microwire is active-high */ 6750 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); 6751 6752 E1000_WRITE_REG(hw, EECD, eecd); 6753 6754 /* Rising edge of clock */ 6755 eecd |= E1000_EECD_SK; 6756 E1000_WRITE_REG(hw, EECD, eecd); 6757 E1000_WRITE_FLUSH(hw); 6758 usec_delay(hw->eeprom.delay_usec); 6759 6760 /* Falling edge of clock */ 6761 eecd &= ~E1000_EECD_SK; 6762 E1000_WRITE_REG(hw, EECD, eecd); 6763 E1000_WRITE_FLUSH(hw); 6764 usec_delay(hw->eeprom.delay_usec); 6765 } 6766 /* Stop requesting EEPROM access */ 6767 if (hw->mac_type > em_82544) { 6768 eecd &= ~E1000_EECD_REQ; 6769 E1000_WRITE_REG(hw, EECD, eecd); 6770 } 6771 em_swfw_sync_release(hw, E1000_SWFW_EEP_SM); 6772 } 6773 6774 /****************************************************************************** 6775 * Reads a 16 bit word from the EEPROM. 6776 * 6777 * hw - Struct containing variables accessed by shared code 6778 *****************************************************************************/ 6779 STATIC int32_t 6780 em_spi_eeprom_ready(struct em_hw *hw) 6781 { 6782 uint16_t retry_count = 0; 6783 uint8_t spi_stat_reg; 6784 DEBUGFUNC("em_spi_eeprom_ready"); 6785 /* 6786 * Read "Status Register" repeatedly until the LSB is cleared. The 6787 * EEPROM will signal that the command has been completed by clearing 6788 * bit 0 of the internal status register. If it's not cleared within 6789 * 5 milliseconds, then error out. 6790 */ 6791 retry_count = 0; 6792 do { 6793 em_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI, 6794 hw->eeprom.opcode_bits); 6795 spi_stat_reg = (uint8_t) em_shift_in_ee_bits(hw, 8); 6796 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI)) 6797 break; 6798 6799 usec_delay(5); 6800 retry_count += 5; 6801 6802 em_standby_eeprom(hw); 6803 } while (retry_count < EEPROM_MAX_RETRY_SPI); 6804 /* 6805 * ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and 6806 * only 0-5mSec on 5V devices) 6807 */ 6808 if (retry_count >= EEPROM_MAX_RETRY_SPI) { 6809 DEBUGOUT("SPI EEPROM Status error\n"); 6810 return -E1000_ERR_EEPROM; 6811 } 6812 return E1000_SUCCESS; 6813 } 6814 6815 /****************************************************************************** 6816 * Reads a 16 bit word from the EEPROM. 6817 * 6818 * hw - Struct containing variables accessed by shared code 6819 * offset - offset of word in the EEPROM to read 6820 * data - word read from the EEPROM 6821 * words - number of words to read 6822 *****************************************************************************/ 6823 int32_t 6824 em_read_eeprom(struct em_hw *hw, uint16_t offset, uint16_t words, 6825 uint16_t *data) 6826 { 6827 struct em_eeprom_info *eeprom = &hw->eeprom; 6828 uint32_t i = 0; 6829 DEBUGFUNC("em_read_eeprom"); 6830 6831 /* If eeprom is not yet detected, do so now */ 6832 if (eeprom->word_size == 0) 6833 em_init_eeprom_params(hw); 6834 /* 6835 * A check for invalid values: offset too large, too many words, and 6836 * not enough words. 6837 */ 6838 if ((offset >= eeprom->word_size) || 6839 (words > eeprom->word_size - offset) || 6840 (words == 0)) { 6841 DEBUGOUT2("\"words\" parameter out of bounds. Words = %d," 6842 " size = %d\n", offset, eeprom->word_size); 6843 return -E1000_ERR_EEPROM; 6844 } 6845 /* 6846 * EEPROM's that don't use EERD to read require us to bit-bang the 6847 * SPI directly. In this case, we need to acquire the EEPROM so that 6848 * FW or other port software does not interrupt. 6849 */ 6850 if (em_is_onboard_nvm_eeprom(hw) == TRUE && 6851 em_get_flash_presence_i210(hw) == TRUE && 6852 hw->eeprom.use_eerd == FALSE) { 6853 /* Prepare the EEPROM for bit-bang reading */ 6854 if (em_acquire_eeprom(hw) != E1000_SUCCESS) 6855 return -E1000_ERR_EEPROM; 6856 } 6857 /* Eerd register EEPROM access requires no eeprom acquire/release */ 6858 if (eeprom->use_eerd == TRUE) 6859 return em_read_eeprom_eerd(hw, offset, words, data); 6860 6861 /* ICH EEPROM access is done via the ICH flash controller */ 6862 if (eeprom->type == em_eeprom_ich8) 6863 return em_read_eeprom_ich8(hw, offset, words, data); 6864 6865 /* Some i210/i211 have a special OTP chip */ 6866 if (eeprom->type == em_eeprom_invm) 6867 return em_read_invm_i210(hw, offset, words, data); 6868 6869 /* 6870 * Set up the SPI or Microwire EEPROM for bit-bang reading. We have 6871 * acquired the EEPROM at this point, so any returns should release it 6872 */ 6873 if (eeprom->type == em_eeprom_spi) { 6874 uint16_t word_in; 6875 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI; 6876 if (em_spi_eeprom_ready(hw)) { 6877 em_release_eeprom(hw); 6878 return -E1000_ERR_EEPROM; 6879 } 6880 em_standby_eeprom(hw); 6881 /* 6882 * Some SPI eeproms use the 8th address bit embedded in the 6883 * opcode 6884 */ 6885 if ((eeprom->address_bits == 8) && (offset >= 128)) 6886 read_opcode |= EEPROM_A8_OPCODE_SPI; 6887 6888 /* Send the READ command (opcode + addr) */ 6889 em_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits); 6890 em_shift_out_ee_bits(hw, (uint16_t) (offset * 2), 6891 eeprom->address_bits); 6892 /* 6893 * Read the data. The address of the eeprom internally 6894 * increments with each byte (spi) being read, saving on the 6895 * overhead of eeprom setup and tear-down. The address 6896 * counter will roll over if reading beyond the size of the 6897 * eeprom, thus allowing the entire memory to be read 6898 * starting from any offset. 6899 */ 6900 for (i = 0; i < words; i++) { 6901 word_in = em_shift_in_ee_bits(hw, 16); 6902 data[i] = (word_in >> 8) | (word_in << 8); 6903 } 6904 } else if (eeprom->type == em_eeprom_microwire) { 6905 for (i = 0; i < words; i++) { 6906 /* Send the READ command (opcode + addr) */ 6907 em_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE, 6908 eeprom->opcode_bits); 6909 em_shift_out_ee_bits(hw, (uint16_t) (offset + i), 6910 eeprom->address_bits); 6911 /* 6912 * Read the data. For microwire, each word requires 6913 * the overhead of eeprom setup and tear-down. 6914 */ 6915 data[i] = em_shift_in_ee_bits(hw, 16); 6916 em_standby_eeprom(hw); 6917 } 6918 } 6919 /* End this read operation */ 6920 em_release_eeprom(hw); 6921 6922 return E1000_SUCCESS; 6923 } 6924 6925 /****************************************************************************** 6926 * Reads a 16 bit word from the EEPROM using the EERD register. 6927 * 6928 * hw - Struct containing variables accessed by shared code 6929 * offset - offset of word in the EEPROM to read 6930 * data - word read from the EEPROM 6931 * words - number of words to read 6932 *****************************************************************************/ 6933 STATIC int32_t 6934 em_read_eeprom_eerd(struct em_hw *hw, uint16_t offset, uint16_t words, 6935 uint16_t *data) 6936 { 6937 uint32_t i, eerd = 0; 6938 int32_t error = 0; 6939 for (i = 0; i < words; i++) { 6940 eerd = ((offset + i) << E1000_EEPROM_RW_ADDR_SHIFT) + 6941 E1000_EEPROM_RW_REG_START; 6942 6943 E1000_WRITE_REG(hw, EERD, eerd); 6944 error = em_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ); 6945 6946 if (error) { 6947 break; 6948 } 6949 data[i] = (E1000_READ_REG(hw, EERD) >> 6950 E1000_EEPROM_RW_REG_DATA); 6951 6952 } 6953 6954 return error; 6955 } 6956 6957 /****************************************************************************** 6958 * Writes a 16 bit word from the EEPROM using the EEWR register. 6959 * 6960 * hw - Struct containing variables accessed by shared code 6961 * offset - offset of word in the EEPROM to read 6962 * data - word read from the EEPROM 6963 * words - number of words to read 6964 *****************************************************************************/ 6965 STATIC int32_t 6966 em_write_eeprom_eewr(struct em_hw *hw, uint16_t offset, uint16_t words, 6967 uint16_t *data) 6968 { 6969 uint32_t register_value = 0; 6970 uint32_t i = 0; 6971 int32_t error = 0; 6972 if (em_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM)) 6973 return -E1000_ERR_SWFW_SYNC; 6974 6975 for (i = 0; i < words; i++) { 6976 register_value = (data[i] << E1000_EEPROM_RW_REG_DATA) | 6977 ((offset + i) << E1000_EEPROM_RW_ADDR_SHIFT) | 6978 E1000_EEPROM_RW_REG_START; 6979 6980 error = em_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE); 6981 if (error) { 6982 break; 6983 } 6984 E1000_WRITE_REG(hw, EEWR, register_value); 6985 6986 error = em_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE); 6987 6988 if (error) { 6989 break; 6990 } 6991 } 6992 6993 em_swfw_sync_release(hw, E1000_SWFW_EEP_SM); 6994 return error; 6995 } 6996 6997 /****************************************************************************** 6998 * Polls the status bit (bit 1) of the EERD to determine when the read is done. 6999 * 7000 * hw - Struct containing variables accessed by shared code 7001 *****************************************************************************/ 7002 STATIC int32_t 7003 em_poll_eerd_eewr_done(struct em_hw *hw, int eerd) 7004 { 7005 uint32_t attempts = 100000; 7006 uint32_t i, reg = 0; 7007 int32_t done = E1000_ERR_EEPROM; 7008 for (i = 0; i < attempts; i++) { 7009 if (eerd == E1000_EEPROM_POLL_READ) 7010 reg = E1000_READ_REG(hw, EERD); 7011 else 7012 reg = E1000_READ_REG(hw, EEWR); 7013 7014 if (reg & E1000_EEPROM_RW_REG_DONE) { 7015 done = E1000_SUCCESS; 7016 break; 7017 } 7018 usec_delay(5); 7019 } 7020 7021 return done; 7022 } 7023 7024 /****************************************************************************** 7025 * Description: Determines if the onboard NVM is FLASH or EEPROM. 7026 * 7027 * hw - Struct containing variables accessed by shared code 7028 *****************************************************************************/ 7029 STATIC boolean_t 7030 em_is_onboard_nvm_eeprom(struct em_hw *hw) 7031 { 7032 uint32_t eecd = 0; 7033 DEBUGFUNC("em_is_onboard_nvm_eeprom"); 7034 7035 if (IS_ICH8(hw->mac_type)) 7036 return FALSE; 7037 7038 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) { 7039 eecd = E1000_READ_REG(hw, EECD); 7040 7041 /* Isolate bits 15 & 16 */ 7042 eecd = ((eecd >> 15) & 0x03); 7043 7044 /* If both bits are set, device is Flash type */ 7045 if (eecd == 0x03) { 7046 return FALSE; 7047 } 7048 } 7049 return TRUE; 7050 } 7051 7052 /****************************************************************************** 7053 * Check if flash device is detected. 7054 * 7055 * hw - Struct containing variables accessed by shared code 7056 *****************************************************************************/ 7057 boolean_t 7058 em_get_flash_presence_i210(struct em_hw *hw) 7059 { 7060 uint32_t eecd; 7061 DEBUGFUNC("em_get_flash_presence_i210"); 7062 7063 if (hw->mac_type != em_i210) 7064 return TRUE; 7065 7066 eecd = E1000_READ_REG(hw, EECD); 7067 7068 if (eecd & E1000_EECD_FLUPD) 7069 return TRUE; 7070 7071 return FALSE; 7072 } 7073 7074 /****************************************************************************** 7075 * Verifies that the EEPROM has a valid checksum 7076 * 7077 * hw - Struct containing variables accessed by shared code 7078 * 7079 * Reads the first 64 16 bit words of the EEPROM and sums the values read. 7080 * If the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is 7081 * valid. 7082 *****************************************************************************/ 7083 int32_t 7084 em_validate_eeprom_checksum(struct em_hw *hw) 7085 { 7086 uint16_t checksum = 0; 7087 uint16_t i, eeprom_data; 7088 uint16_t checksum_reg; 7089 DEBUGFUNC("em_validate_eeprom_checksum"); 7090 7091 checksum_reg = hw->mac_type != em_icp_xxxx ? 7092 EEPROM_CHECKSUM_REG : 7093 EEPROM_CHECKSUM_REG_ICP_xxxx; 7094 7095 if (((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) && 7096 (em_is_onboard_nvm_eeprom(hw) == FALSE)) { 7097 /* 7098 * Check bit 4 of word 10h. If it is 0, firmware is done 7099 * updating 10h-12h. Checksum may need to be fixed. 7100 */ 7101 em_read_eeprom(hw, 0x10, 1, &eeprom_data); 7102 if ((eeprom_data & 0x10) == 0) { 7103 /* 7104 * Read 0x23 and check bit 15. This bit is a 1 when 7105 * the checksum has already been fixed. If the 7106 * checksum is still wrong and this bit is a 1, we 7107 * need to return bad checksum. Otherwise, we need 7108 * to set this bit to a 1 and update the checksum. 7109 */ 7110 em_read_eeprom(hw, 0x23, 1, &eeprom_data); 7111 if ((eeprom_data & 0x8000) == 0) { 7112 eeprom_data |= 0x8000; 7113 em_write_eeprom(hw, 0x23, 1, &eeprom_data); 7114 em_update_eeprom_checksum(hw); 7115 } 7116 } 7117 } 7118 if (IS_ICH8(hw->mac_type)) { 7119 uint16_t word; 7120 uint16_t valid_csum_mask; 7121 7122 /* 7123 * Drivers must allocate the shadow ram structure for the 7124 * EEPROM checksum to be updated. Otherwise, this bit as 7125 * well as the checksum must both be set correctly for this 7126 * validation to pass. 7127 */ 7128 switch (hw->mac_type) { 7129 case em_pch_lpt: 7130 case em_pch_spt: 7131 case em_pch_cnp: 7132 word = EEPROM_COMPAT; 7133 valid_csum_mask = EEPROM_COMPAT_VALID_CSUM; 7134 break; 7135 default: 7136 word = EEPROM_FUTURE_INIT_WORD1; 7137 valid_csum_mask = EEPROM_FUTURE_INIT_WORD1_VALID_CSUM; 7138 break; 7139 } 7140 em_read_eeprom(hw, word, 1, &eeprom_data); 7141 if ((eeprom_data & valid_csum_mask) == 0) { 7142 eeprom_data |= valid_csum_mask; 7143 em_write_eeprom(hw, word, 1, &eeprom_data); 7144 em_update_eeprom_checksum(hw); 7145 } 7146 } 7147 for (i = 0; i < (checksum_reg + 1); i++) { 7148 if (em_read_eeprom(hw, i, 1, &eeprom_data) < 0) { 7149 DEBUGOUT("EEPROM Read Error\n"); 7150 return -E1000_ERR_EEPROM; 7151 } 7152 checksum += eeprom_data; 7153 } 7154 7155 if (checksum == (uint16_t) EEPROM_SUM) 7156 return E1000_SUCCESS; 7157 else { 7158 DEBUGOUT("EEPROM Checksum Invalid\n"); 7159 return -E1000_ERR_EEPROM; 7160 } 7161 } 7162 7163 /****************************************************************************** 7164 * Calculates the EEPROM checksum and writes it to the EEPROM 7165 * 7166 * hw - Struct containing variables accessed by shared code 7167 * 7168 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA. 7169 * Writes the difference to word offset 63 of the EEPROM. 7170 *****************************************************************************/ 7171 int32_t 7172 em_update_eeprom_checksum(struct em_hw *hw) 7173 { 7174 uint32_t ctrl_ext; 7175 uint16_t checksum = 0; 7176 uint16_t i, eeprom_data; 7177 DEBUGFUNC("em_update_eeprom_checksum"); 7178 7179 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) { 7180 if (em_read_eeprom(hw, i, 1, &eeprom_data) < 0) { 7181 DEBUGOUT("EEPROM Read Error\n"); 7182 return -E1000_ERR_EEPROM; 7183 } 7184 checksum += eeprom_data; 7185 } 7186 checksum = (uint16_t) EEPROM_SUM - checksum; 7187 if (em_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) { 7188 DEBUGOUT("EEPROM Write Error\n"); 7189 return -E1000_ERR_EEPROM; 7190 } else if (hw->eeprom.type == em_eeprom_flash) { 7191 em_commit_shadow_ram(hw); 7192 } else if (hw->eeprom.type == em_eeprom_ich8) { 7193 em_commit_shadow_ram(hw); 7194 /* 7195 * Reload the EEPROM, or else modifications will not appear 7196 * until after next adapter reset. 7197 */ 7198 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 7199 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 7200 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 7201 msec_delay(10); 7202 } 7203 return E1000_SUCCESS; 7204 } 7205 7206 /****************************************************************************** 7207 * Parent function for writing words to the different EEPROM types. 7208 * 7209 * hw - Struct containing variables accessed by shared code 7210 * offset - offset within the EEPROM to be written to 7211 * words - number of words to write 7212 * data - 16 bit word to be written to the EEPROM 7213 * 7214 * If em_update_eeprom_checksum is not called after this function, the 7215 * EEPROM will most likely contain an invalid checksum. 7216 *****************************************************************************/ 7217 int32_t 7218 em_write_eeprom(struct em_hw *hw, uint16_t offset, uint16_t words, 7219 uint16_t *data) 7220 { 7221 struct em_eeprom_info *eeprom = &hw->eeprom; 7222 int32_t status = 0; 7223 DEBUGFUNC("em_write_eeprom"); 7224 7225 /* If eeprom is not yet detected, do so now */ 7226 if (eeprom->word_size == 0) 7227 em_init_eeprom_params(hw); 7228 /* 7229 * A check for invalid values: offset too large, too many words, and 7230 * not enough words. 7231 */ 7232 if ((offset >= eeprom->word_size) || 7233 (words > eeprom->word_size - offset) || 7234 (words == 0)) { 7235 DEBUGOUT("\"words\" parameter out of bounds\n"); 7236 return -E1000_ERR_EEPROM; 7237 } 7238 /* 82573/4 writes only through eewr */ 7239 if (eeprom->use_eewr == TRUE) 7240 return em_write_eeprom_eewr(hw, offset, words, data); 7241 7242 if (eeprom->type == em_eeprom_ich8) 7243 return em_write_eeprom_ich8(hw, offset, words, data); 7244 7245 /* Prepare the EEPROM for writing */ 7246 if (em_acquire_eeprom(hw) != E1000_SUCCESS) 7247 return -E1000_ERR_EEPROM; 7248 7249 if (eeprom->type == em_eeprom_microwire) { 7250 status = em_write_eeprom_microwire(hw, offset, words, data); 7251 } else { 7252 status = em_write_eeprom_spi(hw, offset, words, data); 7253 msec_delay(10); 7254 } 7255 7256 /* Done with writing */ 7257 em_release_eeprom(hw); 7258 7259 return status; 7260 } 7261 7262 /****************************************************************************** 7263 * Writes a 16 bit word to a given offset in an SPI EEPROM. 7264 * 7265 * hw - Struct containing variables accessed by shared code 7266 * offset - offset within the EEPROM to be written to 7267 * words - number of words to write 7268 * data - pointer to array of 8 bit words to be written to the EEPROM 7269 * 7270 *****************************************************************************/ 7271 STATIC int32_t 7272 em_write_eeprom_spi(struct em_hw *hw, uint16_t offset, uint16_t words, 7273 uint16_t *data) 7274 { 7275 struct em_eeprom_info *eeprom = &hw->eeprom; 7276 uint16_t widx = 0; 7277 DEBUGFUNC("em_write_eeprom_spi"); 7278 7279 while (widx < words) { 7280 uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI; 7281 if (em_spi_eeprom_ready(hw)) 7282 return -E1000_ERR_EEPROM; 7283 7284 em_standby_eeprom(hw); 7285 7286 /* Send the WRITE ENABLE command (8 bit opcode ) */ 7287 em_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI, 7288 eeprom->opcode_bits); 7289 7290 em_standby_eeprom(hw); 7291 /* 7292 * Some SPI eeproms use the 8th address bit embedded in the 7293 * opcode 7294 */ 7295 if ((eeprom->address_bits == 8) && (offset >= 128)) 7296 write_opcode |= EEPROM_A8_OPCODE_SPI; 7297 7298 /* Send the Write command (8-bit opcode + addr) */ 7299 em_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits); 7300 7301 em_shift_out_ee_bits(hw, (uint16_t) ((offset + widx) * 2), 7302 eeprom->address_bits); 7303 7304 /* Send the data */ 7305 /* 7306 * Loop to allow for up to whole page write (32 bytes) of 7307 * eeprom 7308 */ 7309 while (widx < words) { 7310 uint16_t word_out = data[widx]; 7311 word_out = (word_out >> 8) | (word_out << 8); 7312 em_shift_out_ee_bits(hw, word_out, 16); 7313 widx++; 7314 /* 7315 * Some larger eeprom sizes are capable of a 32-byte 7316 * PAGE WRITE operation, while the smaller eeproms 7317 * are capable of an 8-byte PAGE WRITE operation. 7318 * Break the inner loop to pass new address 7319 */ 7320 if ((((offset + widx) * 2) % eeprom->page_size) == 0) { 7321 em_standby_eeprom(hw); 7322 break; 7323 } 7324 } 7325 } 7326 7327 return E1000_SUCCESS; 7328 } 7329 7330 /****************************************************************************** 7331 * Writes a 16 bit word to a given offset in a Microwire EEPROM. 7332 * 7333 * hw - Struct containing variables accessed by shared code 7334 * offset - offset within the EEPROM to be written to 7335 * words - number of words to write 7336 * data - pointer to array of 16 bit words to be written to the EEPROM 7337 * 7338 *****************************************************************************/ 7339 STATIC int32_t 7340 em_write_eeprom_microwire(struct em_hw *hw, uint16_t offset, uint16_t words, 7341 uint16_t *data) 7342 { 7343 struct em_eeprom_info *eeprom = &hw->eeprom; 7344 uint32_t eecd; 7345 uint16_t words_written = 0; 7346 uint16_t i = 0; 7347 DEBUGFUNC("em_write_eeprom_microwire"); 7348 /* 7349 * Send the write enable command to the EEPROM (3-bit opcode plus 7350 * 6/8-bit dummy address beginning with 11). It's less work to 7351 * include the 11 of the dummy address as part of the opcode than it 7352 * is to shift it over the correct number of bits for the address. 7353 * This puts the EEPROM into write/erase mode. 7354 */ 7355 em_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE, 7356 (uint16_t) (eeprom->opcode_bits + 2)); 7357 7358 em_shift_out_ee_bits(hw, 0, (uint16_t) (eeprom->address_bits - 2)); 7359 7360 /* Prepare the EEPROM */ 7361 em_standby_eeprom(hw); 7362 7363 while (words_written < words) { 7364 /* Send the Write command (3-bit opcode + addr) */ 7365 em_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE, 7366 eeprom->opcode_bits); 7367 7368 em_shift_out_ee_bits(hw, (uint16_t) (offset + words_written), 7369 eeprom->address_bits); 7370 7371 /* Send the data */ 7372 em_shift_out_ee_bits(hw, data[words_written], 16); 7373 /* 7374 * Toggle the CS line. This in effect tells the EEPROM to 7375 * execute the previous command. 7376 */ 7377 em_standby_eeprom(hw); 7378 /* 7379 * Read DO repeatedly until it is high (equal to '1'). The 7380 * EEPROM will signal that the command has been completed by 7381 * raising the DO signal. If DO does not go high in 10 7382 * milliseconds, then error out. 7383 */ 7384 for (i = 0; i < 200; i++) { 7385 eecd = E1000_READ_REG(hw, EECD); 7386 if (eecd & E1000_EECD_DO) 7387 break; 7388 usec_delay(50); 7389 } 7390 if (i == 200) { 7391 DEBUGOUT("EEPROM Write did not complete\n"); 7392 return -E1000_ERR_EEPROM; 7393 } 7394 /* Recover from write */ 7395 em_standby_eeprom(hw); 7396 7397 words_written++; 7398 } 7399 /* 7400 * Send the write disable command to the EEPROM (3-bit opcode plus 7401 * 6/8-bit dummy address beginning with 10). It's less work to 7402 * include the 10 of the dummy address as part of the opcode than it 7403 * is to shift it over the correct number of bits for the address. 7404 * This takes the EEPROM out of write/erase mode. 7405 */ 7406 em_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE, 7407 (uint16_t) (eeprom->opcode_bits + 2)); 7408 7409 em_shift_out_ee_bits(hw, 0, (uint16_t) (eeprom->address_bits - 2)); 7410 7411 return E1000_SUCCESS; 7412 } 7413 7414 /****************************************************************************** 7415 * Flushes the cached eeprom to NVM. This is done by saving the modified values 7416 * in the eeprom cache and the non modified values in the currently active bank 7417 * to the new bank. 7418 * 7419 * hw - Struct containing variables accessed by shared code 7420 * offset - offset of word in the EEPROM to read 7421 * data - word read from the EEPROM 7422 * words - number of words to read 7423 *****************************************************************************/ 7424 STATIC int32_t 7425 em_commit_shadow_ram(struct em_hw *hw) 7426 { 7427 uint32_t attempts = 100000; 7428 uint32_t eecd = 0; 7429 uint32_t flop = 0; 7430 uint32_t i = 0; 7431 int32_t error = E1000_SUCCESS; 7432 uint32_t old_bank_offset = 0; 7433 uint32_t new_bank_offset = 0; 7434 uint8_t low_byte = 0; 7435 uint8_t high_byte = 0; 7436 boolean_t sector_write_failed = FALSE; 7437 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) { 7438 /* 7439 * The flop register will be used to determine if flash type 7440 * is STM 7441 */ 7442 flop = E1000_READ_REG(hw, FLOP); 7443 for (i = 0; i < attempts; i++) { 7444 eecd = E1000_READ_REG(hw, EECD); 7445 if ((eecd & E1000_EECD_FLUPD) == 0) { 7446 break; 7447 } 7448 usec_delay(5); 7449 } 7450 7451 if (i == attempts) { 7452 return -E1000_ERR_EEPROM; 7453 } 7454 /* 7455 * If STM opcode located in bits 15:8 of flop, reset firmware 7456 */ 7457 if ((flop & 0xFF00) == E1000_STM_OPCODE) { 7458 E1000_WRITE_REG(hw, HICR, E1000_HICR_FW_RESET); 7459 } 7460 /* Perform the flash update */ 7461 E1000_WRITE_REG(hw, EECD, eecd | E1000_EECD_FLUPD); 7462 7463 for (i = 0; i < attempts; i++) { 7464 eecd = E1000_READ_REG(hw, EECD); 7465 if ((eecd & E1000_EECD_FLUPD) == 0) { 7466 break; 7467 } 7468 usec_delay(5); 7469 } 7470 7471 if (i == attempts) { 7472 return -E1000_ERR_EEPROM; 7473 } 7474 } 7475 if ((hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) && 7476 hw->eeprom_shadow_ram != NULL) { 7477 /* 7478 * We're writing to the opposite bank so if we're on bank 1, 7479 * write to bank 0 etc. We also need to erase the segment 7480 * that is going to be written 7481 */ 7482 if (!(E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL)) { 7483 new_bank_offset = hw->flash_bank_size * 2; 7484 old_bank_offset = 0; 7485 em_erase_ich8_4k_segment(hw, 1); 7486 } else { 7487 old_bank_offset = hw->flash_bank_size * 2; 7488 new_bank_offset = 0; 7489 em_erase_ich8_4k_segment(hw, 0); 7490 } 7491 7492 sector_write_failed = FALSE; 7493 /* 7494 * Loop for every byte in the shadow RAM, which is in units 7495 * of words. 7496 */ 7497 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 7498 /* 7499 * Determine whether to write the value stored in the 7500 * other NVM bank or a modified value stored in the 7501 * shadow RAM 7502 */ 7503 if (hw->eeprom_shadow_ram[i].modified == TRUE) { 7504 low_byte = (uint8_t) 7505 hw->eeprom_shadow_ram[i].eeprom_word; 7506 usec_delay(100); 7507 error = em_verify_write_ich8_byte(hw, 7508 (i << 1) + new_bank_offset, low_byte); 7509 7510 if (error != E1000_SUCCESS) 7511 sector_write_failed = TRUE; 7512 else { 7513 high_byte = (uint8_t) 7514 (hw->eeprom_shadow_ram 7515 [i].eeprom_word >> 8); 7516 usec_delay(100); 7517 } 7518 } else { 7519 em_read_ich8_byte(hw, (i << 1) + 7520 old_bank_offset, &low_byte); 7521 usec_delay(100); 7522 error = em_verify_write_ich8_byte(hw, 7523 (i << 1) + new_bank_offset, low_byte); 7524 7525 if (error != E1000_SUCCESS) 7526 sector_write_failed = TRUE; 7527 else { 7528 em_read_ich8_byte(hw, (i << 1) + 7529 old_bank_offset + 1, &high_byte); 7530 usec_delay(100); 7531 } 7532 } 7533 /* 7534 * If the write of the low byte was successful, go 7535 * ahread and write the high byte while checking to 7536 * make sure that if it is the signature byte, then 7537 * it is handled properly 7538 */ 7539 if (sector_write_failed == FALSE) { 7540 /* 7541 * If the word is 0x13, then make sure the 7542 * signature bits (15:14) are 11b until the 7543 * commit has completed. This will allow us 7544 * to write 10b which indicates the signature 7545 * is valid. We want to do this after the 7546 * write has completed so that we don't mark 7547 * the segment valid while the write is still 7548 * in progress 7549 */ 7550 if (i == E1000_ICH_NVM_SIG_WORD) 7551 high_byte = E1000_ICH_NVM_VALID_SIG_MASK | 7552 high_byte; 7553 7554 error = em_verify_write_ich8_byte(hw, (i << 1) 7555 + new_bank_offset + 1, high_byte); 7556 if (error != E1000_SUCCESS) 7557 sector_write_failed = TRUE; 7558 7559 } else { 7560 /* 7561 * If the write failed then break from the 7562 * loop and return an error 7563 */ 7564 break; 7565 } 7566 } 7567 /* 7568 * Don't bother writing the segment valid bits if sector 7569 * programming failed. 7570 */ 7571 if (sector_write_failed == FALSE) { 7572 /* 7573 * Finally validate the new segment by setting bit 7574 * 15:14 to 10b in word 0x13 , this can be done 7575 * without an erase as well since these bits are 11 7576 * to start with and we need to change bit 14 to 0b 7577 */ 7578 em_read_ich8_byte(hw, E1000_ICH_NVM_SIG_WORD * 2 + 1 + 7579 new_bank_offset, &high_byte); 7580 high_byte &= 0xBF; 7581 error = em_verify_write_ich8_byte(hw, 7582 E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset, 7583 high_byte); 7584 /* 7585 * And invalidate the previously valid segment by 7586 * setting its signature word (0x13) high_byte to 0b. 7587 * This can be done without an erase because flash 7588 * erase sets all bits to 1's. We can write 1's to 7589 * 0's without an erase 7590 */ 7591 if (error == E1000_SUCCESS) { 7592 error = em_verify_write_ich8_byte(hw, 7593 E1000_ICH_NVM_SIG_WORD * 2 + 1 + 7594 old_bank_offset, 0); 7595 } 7596 /* Clear the now not used entry in the cache */ 7597 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 7598 hw->eeprom_shadow_ram[i].modified = FALSE; 7599 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF; 7600 } 7601 } 7602 } 7603 return error; 7604 } 7605 7606 /****************************************************************************** 7607 * Reads the adapter's part number from the EEPROM 7608 * 7609 * hw - Struct containing variables accessed by shared code 7610 * part_num - Adapter's part number 7611 *****************************************************************************/ 7612 int32_t 7613 em_read_part_num(struct em_hw *hw, uint32_t *part_num) 7614 { 7615 uint16_t offset = EEPROM_PBA_BYTE_1; 7616 uint16_t eeprom_data; 7617 DEBUGFUNC("em_read_part_num"); 7618 7619 /* Get word 0 from EEPROM */ 7620 if (em_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { 7621 DEBUGOUT("EEPROM Read Error\n"); 7622 return -E1000_ERR_EEPROM; 7623 } 7624 /* Save word 0 in upper half of part_num */ 7625 *part_num = (uint32_t)eeprom_data << 16; 7626 7627 /* Get word 1 from EEPROM */ 7628 if (em_read_eeprom(hw, ++offset, 1, &eeprom_data) < 0) { 7629 DEBUGOUT("EEPROM Read Error\n"); 7630 return -E1000_ERR_EEPROM; 7631 } 7632 /* Save word 1 in lower half of part_num */ 7633 *part_num |= eeprom_data; 7634 7635 return E1000_SUCCESS; 7636 } 7637 7638 /****************************************************************************** 7639 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the 7640 * second function of dual function devices 7641 * 7642 * hw - Struct containing variables accessed by shared code 7643 *****************************************************************************/ 7644 int32_t 7645 em_read_mac_addr(struct em_hw *hw) 7646 { 7647 uint16_t offset; 7648 uint16_t eeprom_data, i; 7649 uint16_t ia_base_addr = 0; 7650 DEBUGFUNC("em_read_mac_addr"); 7651 7652 if (hw->mac_type == em_icp_xxxx) { 7653 ia_base_addr = (uint16_t) 7654 EEPROM_IA_START_ICP_xxxx(hw->icp_xxxx_port_num); 7655 } else if (hw->mac_type == em_82580 || hw->mac_type == em_i350) { 7656 ia_base_addr = NVM_82580_LAN_FUNC_OFFSET(hw->bus_func); 7657 } 7658 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) { 7659 offset = i >> 1; 7660 if (em_read_eeprom(hw, offset + ia_base_addr, 1, &eeprom_data) 7661 < 0) { 7662 DEBUGOUT("EEPROM Read Error\n"); 7663 return -E1000_ERR_EEPROM; 7664 } 7665 hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF); 7666 hw->perm_mac_addr[i + 1] = (uint8_t) (eeprom_data >> 8); 7667 } 7668 7669 switch (hw->mac_type) { 7670 default: 7671 break; 7672 case em_82546: 7673 case em_82546_rev_3: 7674 case em_82571: 7675 case em_82575: 7676 case em_82576: 7677 case em_80003es2lan: 7678 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) 7679 hw->perm_mac_addr[5] ^= 0x01; 7680 break; 7681 } 7682 7683 for (i = 0; i < NODE_ADDRESS_SIZE; i++) 7684 hw->mac_addr[i] = hw->perm_mac_addr[i]; 7685 return E1000_SUCCESS; 7686 } 7687 7688 /****************************************************************************** 7689 * Explicitly disables jumbo frames and resets some PHY registers back to hw- 7690 * defaults. This is necessary in case the ethernet cable was inserted AFTER 7691 * the firmware initialized the PHY. Otherwise it is left in a state where 7692 * it is possible to transmit but not receive packets. Observed on I217-LM and 7693 * fixed in FreeBSD's sys/dev/e1000/e1000_ich8lan.c. 7694 * 7695 * hw - Struct containing variables accessed by shared code 7696 *****************************************************************************/ 7697 STATIC int32_t 7698 em_phy_no_cable_workaround(struct em_hw *hw) { 7699 int32_t ret_val, dft_ret_val; 7700 uint32_t mac_reg; 7701 uint16_t data, phy_reg; 7702 7703 /* disable Rx path while enabling workaround */ 7704 em_read_phy_reg(hw, I2_DFT_CTRL, &phy_reg); 7705 ret_val = em_write_phy_reg(hw, I2_DFT_CTRL, phy_reg | (1 << 14)); 7706 if (ret_val) 7707 return ret_val; 7708 7709 /* Write MAC register values back to h/w defaults */ 7710 mac_reg = E1000_READ_REG(hw, FFLT_DBG); 7711 mac_reg &= ~(0xF << 14); 7712 E1000_WRITE_REG(hw, FFLT_DBG, mac_reg); 7713 7714 mac_reg = E1000_READ_REG(hw, RCTL); 7715 mac_reg &= ~E1000_RCTL_SECRC; 7716 E1000_WRITE_REG(hw, RCTL, mac_reg); 7717 7718 ret_val = em_read_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_CTRL, &data); 7719 if (ret_val) 7720 goto out; 7721 ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_CTRL, 7722 data & ~(1 << 0)); 7723 if (ret_val) 7724 goto out; 7725 7726 ret_val = em_read_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL, &data); 7727 if (ret_val) 7728 goto out; 7729 7730 data &= ~(0xF << 8); 7731 data |= (0xB << 8); 7732 ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL, data); 7733 if (ret_val) 7734 goto out; 7735 7736 /* Write PHY register values back to h/w defaults */ 7737 em_read_phy_reg(hw, I2_SMBUS_CTRL, &data); 7738 data &= ~(0x7F << 5); 7739 ret_val = em_write_phy_reg(hw, I2_SMBUS_CTRL, data); 7740 if (ret_val) 7741 goto out; 7742 7743 em_read_phy_reg(hw, I2_MODE_CTRL, &data); 7744 data |= (1 << 13); 7745 ret_val = em_write_phy_reg(hw, I2_MODE_CTRL, data); 7746 if (ret_val) 7747 goto out; 7748 7749 /* 7750 * 776.20 and 776.23 are not documented in 7751 * i217-ethernet-controller-datasheet.pdf... 7752 */ 7753 em_read_phy_reg(hw, PHY_REG(776, 20), &data); 7754 data &= ~(0x3FF << 2); 7755 data |= (0x8 << 2); 7756 ret_val = em_write_phy_reg(hw, PHY_REG(776, 20), data); 7757 if (ret_val) 7758 goto out; 7759 7760 ret_val = em_write_phy_reg(hw, PHY_REG(776, 23), 0x7E00); 7761 if (ret_val) 7762 goto out; 7763 7764 em_read_phy_reg(hw, I2_PCIE_POWER_CTRL, &data); 7765 ret_val = em_write_phy_reg(hw, I2_PCIE_POWER_CTRL, data & ~(1 << 10)); 7766 if (ret_val) 7767 goto out; 7768 7769 out: 7770 /* re-enable Rx path after enabling workaround */ 7771 dft_ret_val = em_write_phy_reg(hw, I2_DFT_CTRL, phy_reg & ~(1 << 14)); 7772 if (ret_val) 7773 return ret_val; 7774 else 7775 return dft_ret_val; 7776 } 7777 7778 /****************************************************************************** 7779 * Initializes receive address filters. 7780 * 7781 * hw - Struct containing variables accessed by shared code 7782 * 7783 * Places the MAC address in receive address register 0 and clears the rest 7784 * of the receive address registers. Clears the multicast table. Assumes 7785 * the receiver is in reset when the routine is called. 7786 *****************************************************************************/ 7787 STATIC void 7788 em_init_rx_addrs(struct em_hw *hw) 7789 { 7790 uint32_t i; 7791 uint32_t rar_num; 7792 DEBUGFUNC("em_init_rx_addrs"); 7793 7794 if (hw->mac_type == em_pch_lpt || hw->mac_type == em_pch_spt || 7795 hw->mac_type == em_pch_cnp || hw->mac_type == em_pch2lan) 7796 if (em_phy_no_cable_workaround(hw)) 7797 printf(" ...failed to apply em_phy_no_cable_" 7798 "workaround.\n"); 7799 7800 /* Setup the receive address. */ 7801 DEBUGOUT("Programming MAC Address into RAR[0]\n"); 7802 7803 em_rar_set(hw, hw->mac_addr, 0); 7804 7805 rar_num = E1000_RAR_ENTRIES; 7806 /* 7807 * Reserve a spot for the Locally Administered Address to work around 7808 * an 82571 issue in which a reset on one port will reload the MAC on 7809 * the other port. 7810 */ 7811 if ((hw->mac_type == em_82571) && (hw->laa_is_present == TRUE)) 7812 rar_num -= 1; 7813 if (IS_ICH8(hw->mac_type)) 7814 rar_num = E1000_RAR_ENTRIES_ICH8LAN; 7815 if (hw->mac_type == em_ich8lan) 7816 rar_num -= 1; 7817 if (hw->mac_type == em_82580) 7818 rar_num = E1000_RAR_ENTRIES_82580; 7819 if (hw->mac_type == em_i210) 7820 rar_num = E1000_RAR_ENTRIES_82575; 7821 if (hw->mac_type == em_i350) 7822 rar_num = E1000_RAR_ENTRIES_I350; 7823 7824 /* Zero out the other 15 receive addresses. */ 7825 DEBUGOUT("Clearing RAR[1-15]\n"); 7826 for (i = 1; i < rar_num; i++) { 7827 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 7828 E1000_WRITE_FLUSH(hw); 7829 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 7830 E1000_WRITE_FLUSH(hw); 7831 } 7832 } 7833 7834 /****************************************************************************** 7835 * Updates the MAC's list of multicast addresses. 7836 * 7837 * hw - Struct containing variables accessed by shared code 7838 * mc_addr_list - the list of new multicast addresses 7839 * mc_addr_count - number of addresses 7840 * pad - number of bytes between addresses in the list 7841 * rar_used_count - offset where to start adding mc addresses into the RAR's 7842 * 7843 * The given list replaces any existing list. Clears the last 15 receive 7844 * address registers and the multicast table. Uses receive address registers 7845 * for the first 15 multicast addresses, and hashes the rest into the 7846 * multicast table. 7847 *****************************************************************************/ 7848 void 7849 em_mc_addr_list_update(struct em_hw *hw, uint8_t *mc_addr_list, 7850 uint32_t mc_addr_count, uint32_t pad, uint32_t rar_used_count) 7851 { 7852 uint32_t hash_value; 7853 uint32_t i; 7854 uint32_t num_rar_entry; 7855 uint32_t num_mta_entry; 7856 DEBUGFUNC("em_mc_addr_list_update"); 7857 /* 7858 * Set the new number of MC addresses that we are being requested to 7859 * use. 7860 */ 7861 hw->num_mc_addrs = mc_addr_count; 7862 7863 /* Clear RAR[1-15] */ 7864 DEBUGOUT(" Clearing RAR[1-15]\n"); 7865 num_rar_entry = E1000_RAR_ENTRIES; 7866 if (IS_ICH8(hw->mac_type)) 7867 num_rar_entry = E1000_RAR_ENTRIES_ICH8LAN; 7868 if (hw->mac_type == em_ich8lan) 7869 num_rar_entry -= 1; 7870 /* 7871 * Reserve a spot for the Locally Administered Address to work around 7872 * an 82571 issue in which a reset on one port will reload the MAC on 7873 * the other port. 7874 */ 7875 if ((hw->mac_type == em_82571) && (hw->laa_is_present == TRUE)) 7876 num_rar_entry -= 1; 7877 7878 for (i = rar_used_count; i < num_rar_entry; i++) { 7879 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 7880 E1000_WRITE_FLUSH(hw); 7881 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 7882 E1000_WRITE_FLUSH(hw); 7883 } 7884 7885 /* Clear the MTA */ 7886 DEBUGOUT(" Clearing MTA\n"); 7887 num_mta_entry = E1000_NUM_MTA_REGISTERS; 7888 if (IS_ICH8(hw->mac_type)) 7889 num_mta_entry = E1000_NUM_MTA_REGISTERS_ICH8LAN; 7890 7891 for (i = 0; i < num_mta_entry; i++) { 7892 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 7893 E1000_WRITE_FLUSH(hw); 7894 } 7895 7896 /* Add the new addresses */ 7897 for (i = 0; i < mc_addr_count; i++) { 7898 DEBUGOUT(" Adding the multicast addresses:\n"); 7899 DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i, 7900 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad)], 7901 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 1], 7902 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 2], 7903 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 3], 7904 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 4], 7905 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 5]); 7906 7907 hash_value = em_hash_mc_addr(hw, mc_addr_list + 7908 (i * (ETH_LENGTH_OF_ADDRESS + pad))); 7909 7910 DEBUGOUT1(" Hash value = 0x%03X\n", hash_value); 7911 /* 7912 * Place this multicast address in the RAR if there is room, * 7913 * else put it in the MTA 7914 */ 7915 if (rar_used_count < num_rar_entry) { 7916 em_rar_set(hw, mc_addr_list + 7917 (i * (ETH_LENGTH_OF_ADDRESS + pad)), 7918 rar_used_count); 7919 rar_used_count++; 7920 } else { 7921 em_mta_set(hw, hash_value); 7922 } 7923 } 7924 DEBUGOUT("MC Update Complete\n"); 7925 } 7926 7927 /****************************************************************************** 7928 * Hashes an address to determine its location in the multicast table 7929 * 7930 * hw - Struct containing variables accessed by shared code 7931 * mc_addr - the multicast address to hash 7932 *****************************************************************************/ 7933 uint32_t 7934 em_hash_mc_addr(struct em_hw *hw, uint8_t *mc_addr) 7935 { 7936 uint32_t hash_value = 0; 7937 /* 7938 * The portion of the address that is used for the hash table is 7939 * determined by the mc_filter_type setting. 7940 */ 7941 switch (hw->mc_filter_type) { 7942 /* 7943 * [0] [1] [2] [3] [4] [5] 01 AA 00 12 34 56 LSB 7944 * MSB 7945 */ 7946 case 0: 7947 if (IS_ICH8(hw->mac_type)) { 7948 /* [47:38] i.e. 0x158 for above example address */ 7949 hash_value = ((mc_addr[4] >> 6) | 7950 (((uint16_t) mc_addr[5]) << 2)); 7951 } else { 7952 /* [47:36] i.e. 0x563 for above example address */ 7953 hash_value = ((mc_addr[4] >> 4) | 7954 (((uint16_t) mc_addr[5]) << 4)); 7955 } 7956 break; 7957 case 1: 7958 if (IS_ICH8(hw->mac_type)) { 7959 /* [46:37] i.e. 0x2B1 for above example address */ 7960 hash_value = ((mc_addr[4] >> 5) | 7961 (((uint16_t) mc_addr[5]) << 3)); 7962 } else { 7963 /* [46:35] i.e. 0xAC6 for above example address */ 7964 hash_value = ((mc_addr[4] >> 3) | 7965 (((uint16_t) mc_addr[5]) << 5)); 7966 } 7967 break; 7968 case 2: 7969 if (IS_ICH8(hw->mac_type)) { 7970 /* [45:36] i.e. 0x163 for above example address */ 7971 hash_value = ((mc_addr[4] >> 4) | 7972 (((uint16_t) mc_addr[5]) << 4)); 7973 } else { 7974 /* [45:34] i.e. 0x5D8 for above example address */ 7975 hash_value = ((mc_addr[4] >> 2) | 7976 (((uint16_t) mc_addr[5]) << 6)); 7977 } 7978 break; 7979 case 3: 7980 if (IS_ICH8(hw->mac_type)) { 7981 /* [43:34] i.e. 0x18D for above example address */ 7982 hash_value = ((mc_addr[4] >> 2) | 7983 (((uint16_t) mc_addr[5]) << 6)); 7984 } else { 7985 /* [43:32] i.e. 0x634 for above example address */ 7986 hash_value = ((mc_addr[4]) | 7987 (((uint16_t) mc_addr[5]) << 8)); 7988 } 7989 break; 7990 } 7991 7992 hash_value &= 0xFFF; 7993 if (IS_ICH8(hw->mac_type)) 7994 hash_value &= 0x3FF; 7995 7996 return hash_value; 7997 } 7998 7999 /****************************************************************************** 8000 * Sets the bit in the multicast table corresponding to the hash value. 8001 * 8002 * hw - Struct containing variables accessed by shared code 8003 * hash_value - Multicast address hash value 8004 *****************************************************************************/ 8005 void 8006 em_mta_set(struct em_hw *hw, uint32_t hash_value) 8007 { 8008 uint32_t hash_bit, hash_reg; 8009 uint32_t mta; 8010 uint32_t temp; 8011 /* 8012 * The MTA is a register array of 128 32-bit registers. It is treated 8013 * like an array of 4096 bits. We want to set bit 8014 * BitArray[hash_value]. So we figure out what register the bit is 8015 * in, read it, OR in the new bit, then write back the new value. 8016 * The register is determined by the upper 7 bits of the hash value 8017 * and the bit within that register are determined by the lower 5 8018 * bits of the value. 8019 */ 8020 hash_reg = (hash_value >> 5) & 0x7F; 8021 if (IS_ICH8(hw->mac_type)) 8022 hash_reg &= 0x1F; 8023 8024 hash_bit = hash_value & 0x1F; 8025 8026 mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg); 8027 8028 mta |= (1 << hash_bit); 8029 /* 8030 * If we are on an 82544 and we are trying to write an odd offset in 8031 * the MTA, save off the previous entry before writing and restore 8032 * the old value after writing. 8033 */ 8034 if ((hw->mac_type == em_82544) && ((hash_reg & 0x1) == 1)) { 8035 temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1)); 8036 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta); 8037 E1000_WRITE_FLUSH(hw); 8038 E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp); 8039 E1000_WRITE_FLUSH(hw); 8040 } else { 8041 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta); 8042 E1000_WRITE_FLUSH(hw); 8043 } 8044 } 8045 8046 /****************************************************************************** 8047 * Puts an ethernet address into a receive address register. 8048 * 8049 * hw - Struct containing variables accessed by shared code 8050 * addr - Address to put into receive address register 8051 * index - Receive address register to write 8052 *****************************************************************************/ 8053 void 8054 em_rar_set(struct em_hw *hw, uint8_t *addr, uint32_t index) 8055 { 8056 uint32_t rar_low, rar_high; 8057 /* 8058 * HW expects these in little endian so we reverse the byte order 8059 * from network order (big endian) to little endian 8060 */ 8061 rar_low = ((uint32_t) addr[0] | ((uint32_t) addr[1] << 8) | 8062 ((uint32_t) addr[2] << 16) | ((uint32_t) addr[3] << 24)); 8063 rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8)); 8064 /* 8065 * Disable Rx and flush all Rx frames before enabling RSS to avoid Rx 8066 * unit hang. 8067 * 8068 * Description: If there are any Rx frames queued up or otherwise 8069 * present in the HW before RSS is enabled, and then we enable RSS, 8070 * the HW Rx unit will hang. To work around this issue, we have to 8071 * disable receives and flush out all Rx frames before we enable RSS. 8072 * To do so, we modify we redirect all Rx traffic to manageability 8073 * and then reset the HW. This flushes away Rx frames, and (since the 8074 * redirections to manageability persists across resets) keeps new 8075 * ones from coming in while we work. Then, we clear the Address 8076 * Valid AV bit for all MAC addresses and undo the re-direction to 8077 * manageability. Now, frames are coming in again, but the MAC won't 8078 * accept them, so far so good. We now proceed to initialize RSS (if 8079 * necessary) and configure the Rx unit. Last, we re-enable the AV 8080 * bits and continue on our merry way. 8081 */ 8082 switch (hw->mac_type) { 8083 case em_82571: 8084 case em_82572: 8085 case em_80003es2lan: 8086 if (hw->leave_av_bit_off == TRUE) 8087 break; 8088 default: 8089 /* Indicate to hardware the Address is Valid. */ 8090 rar_high |= E1000_RAH_AV; 8091 break; 8092 } 8093 8094 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low); 8095 E1000_WRITE_FLUSH(hw); 8096 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high); 8097 E1000_WRITE_FLUSH(hw); 8098 } 8099 8100 /****************************************************************************** 8101 * Clears the VLAN filer table 8102 * 8103 * hw - Struct containing variables accessed by shared code 8104 *****************************************************************************/ 8105 STATIC void 8106 em_clear_vfta(struct em_hw *hw) 8107 { 8108 uint32_t offset; 8109 uint32_t vfta_value = 0; 8110 uint32_t vfta_offset = 0; 8111 uint32_t vfta_bit_in_reg = 0; 8112 if (IS_ICH8(hw->mac_type)) 8113 return; 8114 8115 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) { 8116 if (hw->mng_cookie.vlan_id != 0) { 8117 /* 8118 * The VFTA is a 4096b bit-field, each identifying a 8119 * single VLAN ID. The following operations 8120 * determine which 32b entry (i.e. offset) into the 8121 * array we want to set the VLAN ID (i.e. bit) of the 8122 * manageability unit. 8123 */ 8124 vfta_offset = (hw->mng_cookie.vlan_id >> 8125 E1000_VFTA_ENTRY_SHIFT) & E1000_VFTA_ENTRY_MASK; 8126 8127 vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id & 8128 E1000_VFTA_ENTRY_BIT_SHIFT_MASK); 8129 } 8130 } 8131 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 8132 /* 8133 * If the offset we want to clear is the same offset of the 8134 * manageability VLAN ID, then clear all bits except that of 8135 * the manageability unit 8136 */ 8137 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; 8138 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value); 8139 E1000_WRITE_FLUSH(hw); 8140 } 8141 } 8142 8143 /* 8144 * Due to hw errata, if the host tries to configure the VFTA register 8145 * while performing queries from the BMC or DMA, then the VFTA in some 8146 * cases won't be written. 8147 */ 8148 void 8149 em_clear_vfta_i350(struct em_hw *hw) 8150 { 8151 uint32_t offset; 8152 int i; 8153 8154 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 8155 for (i = 0; i < 10; i++) 8156 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0); 8157 E1000_WRITE_FLUSH(hw); 8158 } 8159 } 8160 8161 STATIC int32_t 8162 em_id_led_init(struct em_hw *hw) 8163 { 8164 uint32_t ledctl; 8165 const uint32_t ledctl_mask = 0x000000FF; 8166 const uint32_t ledctl_on = E1000_LEDCTL_MODE_LED_ON; 8167 const uint32_t ledctl_off = E1000_LEDCTL_MODE_LED_OFF; 8168 uint16_t eeprom_data, i, temp; 8169 const uint16_t led_mask = 0x0F; 8170 DEBUGFUNC("em_id_led_init"); 8171 8172 if (hw->mac_type < em_82540 || hw->mac_type == em_icp_xxxx) { 8173 /* Nothing to do */ 8174 return E1000_SUCCESS; 8175 } 8176 ledctl = E1000_READ_REG(hw, LEDCTL); 8177 hw->ledctl_default = ledctl; 8178 hw->ledctl_mode1 = hw->ledctl_default; 8179 hw->ledctl_mode2 = hw->ledctl_default; 8180 8181 if (em_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) { 8182 DEBUGOUT("EEPROM Read Error\n"); 8183 return -E1000_ERR_EEPROM; 8184 } 8185 if ((hw->mac_type == em_82573) && 8186 (eeprom_data == ID_LED_RESERVED_82573)) 8187 eeprom_data = ID_LED_DEFAULT_82573; 8188 else if ((eeprom_data == ID_LED_RESERVED_0000) || 8189 (eeprom_data == ID_LED_RESERVED_FFFF)) { 8190 if (hw->mac_type == em_ich8lan || 8191 hw->mac_type == em_ich9lan || 8192 hw->mac_type == em_ich10lan) // XXX 8193 eeprom_data = ID_LED_DEFAULT_ICH8LAN; 8194 else 8195 eeprom_data = ID_LED_DEFAULT; 8196 } 8197 for (i = 0; i < 4; i++) { 8198 temp = (eeprom_data >> (i << 2)) & led_mask; 8199 switch (temp) { 8200 case ID_LED_ON1_DEF2: 8201 case ID_LED_ON1_ON2: 8202 case ID_LED_ON1_OFF2: 8203 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 8204 hw->ledctl_mode1 |= ledctl_on << (i << 3); 8205 break; 8206 case ID_LED_OFF1_DEF2: 8207 case ID_LED_OFF1_ON2: 8208 case ID_LED_OFF1_OFF2: 8209 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 8210 hw->ledctl_mode1 |= ledctl_off << (i << 3); 8211 break; 8212 default: 8213 /* Do nothing */ 8214 break; 8215 } 8216 switch (temp) { 8217 case ID_LED_DEF1_ON2: 8218 case ID_LED_ON1_ON2: 8219 case ID_LED_OFF1_ON2: 8220 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 8221 hw->ledctl_mode2 |= ledctl_on << (i << 3); 8222 break; 8223 case ID_LED_DEF1_OFF2: 8224 case ID_LED_ON1_OFF2: 8225 case ID_LED_OFF1_OFF2: 8226 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 8227 hw->ledctl_mode2 |= ledctl_off << (i << 3); 8228 break; 8229 default: 8230 /* Do nothing */ 8231 break; 8232 } 8233 } 8234 return E1000_SUCCESS; 8235 } 8236 8237 /****************************************************************************** 8238 * Clears all hardware statistics counters. 8239 * 8240 * hw - Struct containing variables accessed by shared code 8241 *****************************************************************************/ 8242 void 8243 em_clear_hw_cntrs(struct em_hw *hw) 8244 { 8245 volatile uint32_t temp; 8246 temp = E1000_READ_REG(hw, CRCERRS); 8247 temp = E1000_READ_REG(hw, SYMERRS); 8248 temp = E1000_READ_REG(hw, MPC); 8249 temp = E1000_READ_REG(hw, SCC); 8250 temp = E1000_READ_REG(hw, ECOL); 8251 temp = E1000_READ_REG(hw, MCC); 8252 temp = E1000_READ_REG(hw, LATECOL); 8253 temp = E1000_READ_REG(hw, COLC); 8254 temp = E1000_READ_REG(hw, DC); 8255 temp = E1000_READ_REG(hw, SEC); 8256 temp = E1000_READ_REG(hw, RLEC); 8257 temp = E1000_READ_REG(hw, XONRXC); 8258 temp = E1000_READ_REG(hw, XONTXC); 8259 temp = E1000_READ_REG(hw, XOFFRXC); 8260 temp = E1000_READ_REG(hw, XOFFTXC); 8261 temp = E1000_READ_REG(hw, FCRUC); 8262 8263 if (!IS_ICH8(hw->mac_type)) { 8264 temp = E1000_READ_REG(hw, PRC64); 8265 temp = E1000_READ_REG(hw, PRC127); 8266 temp = E1000_READ_REG(hw, PRC255); 8267 temp = E1000_READ_REG(hw, PRC511); 8268 temp = E1000_READ_REG(hw, PRC1023); 8269 temp = E1000_READ_REG(hw, PRC1522); 8270 } 8271 temp = E1000_READ_REG(hw, GPRC); 8272 temp = E1000_READ_REG(hw, BPRC); 8273 temp = E1000_READ_REG(hw, MPRC); 8274 temp = E1000_READ_REG(hw, GPTC); 8275 temp = E1000_READ_REG(hw, GORCL); 8276 temp = E1000_READ_REG(hw, GORCH); 8277 temp = E1000_READ_REG(hw, GOTCL); 8278 temp = E1000_READ_REG(hw, GOTCH); 8279 temp = E1000_READ_REG(hw, RNBC); 8280 temp = E1000_READ_REG(hw, RUC); 8281 temp = E1000_READ_REG(hw, RFC); 8282 temp = E1000_READ_REG(hw, ROC); 8283 temp = E1000_READ_REG(hw, RJC); 8284 temp = E1000_READ_REG(hw, TORL); 8285 temp = E1000_READ_REG(hw, TORH); 8286 temp = E1000_READ_REG(hw, TOTL); 8287 temp = E1000_READ_REG(hw, TOTH); 8288 temp = E1000_READ_REG(hw, TPR); 8289 temp = E1000_READ_REG(hw, TPT); 8290 8291 if (!IS_ICH8(hw->mac_type)) { 8292 temp = E1000_READ_REG(hw, PTC64); 8293 temp = E1000_READ_REG(hw, PTC127); 8294 temp = E1000_READ_REG(hw, PTC255); 8295 temp = E1000_READ_REG(hw, PTC511); 8296 temp = E1000_READ_REG(hw, PTC1023); 8297 temp = E1000_READ_REG(hw, PTC1522); 8298 } 8299 temp = E1000_READ_REG(hw, MPTC); 8300 temp = E1000_READ_REG(hw, BPTC); 8301 8302 if (hw->mac_type < em_82543) 8303 return; 8304 8305 temp = E1000_READ_REG(hw, ALGNERRC); 8306 temp = E1000_READ_REG(hw, RXERRC); 8307 temp = E1000_READ_REG(hw, TNCRS); 8308 temp = E1000_READ_REG(hw, CEXTERR); 8309 temp = E1000_READ_REG(hw, TSCTC); 8310 temp = E1000_READ_REG(hw, TSCTFC); 8311 8312 if (hw->mac_type <= em_82544 8313 || hw->mac_type == em_icp_xxxx) 8314 return; 8315 8316 temp = E1000_READ_REG(hw, MGTPRC); 8317 temp = E1000_READ_REG(hw, MGTPDC); 8318 temp = E1000_READ_REG(hw, MGTPTC); 8319 8320 if (hw->mac_type <= em_82547_rev_2) 8321 return; 8322 8323 temp = E1000_READ_REG(hw, IAC); 8324 temp = E1000_READ_REG(hw, ICRXOC); 8325 8326 if (hw->phy_type == em_phy_82577 || 8327 hw->phy_type == em_phy_82578 || 8328 hw->phy_type == em_phy_82579 || 8329 hw->phy_type == em_phy_i217) { 8330 uint16_t phy_data; 8331 8332 em_read_phy_reg(hw, HV_SCC_UPPER, &phy_data); 8333 em_read_phy_reg(hw, HV_SCC_LOWER, &phy_data); 8334 em_read_phy_reg(hw, HV_ECOL_UPPER, &phy_data); 8335 em_read_phy_reg(hw, HV_ECOL_LOWER, &phy_data); 8336 em_read_phy_reg(hw, HV_MCC_UPPER, &phy_data); 8337 em_read_phy_reg(hw, HV_MCC_LOWER, &phy_data); 8338 em_read_phy_reg(hw, HV_LATECOL_UPPER, &phy_data); 8339 em_read_phy_reg(hw, HV_LATECOL_LOWER, &phy_data); 8340 em_read_phy_reg(hw, HV_COLC_UPPER, &phy_data); 8341 em_read_phy_reg(hw, HV_COLC_LOWER, &phy_data); 8342 em_read_phy_reg(hw, HV_DC_UPPER, &phy_data); 8343 em_read_phy_reg(hw, HV_DC_LOWER, &phy_data); 8344 em_read_phy_reg(hw, HV_TNCRS_UPPER, &phy_data); 8345 em_read_phy_reg(hw, HV_TNCRS_LOWER, &phy_data); 8346 } 8347 8348 if (hw->mac_type == em_ich8lan || 8349 hw->mac_type == em_ich9lan || 8350 hw->mac_type == em_ich10lan || 8351 hw->mac_type == em_pchlan || 8352 (hw->mac_type != em_pch2lan && hw->mac_type != em_pch_lpt && 8353 hw->mac_type != em_pch_spt && hw->mac_type != em_pch_cnp)) 8354 return; 8355 8356 temp = E1000_READ_REG(hw, ICRXPTC); 8357 temp = E1000_READ_REG(hw, ICRXATC); 8358 temp = E1000_READ_REG(hw, ICTXPTC); 8359 temp = E1000_READ_REG(hw, ICTXATC); 8360 temp = E1000_READ_REG(hw, ICTXQEC); 8361 temp = E1000_READ_REG(hw, ICTXQMTC); 8362 temp = E1000_READ_REG(hw, ICRXDMTC); 8363 } 8364 8365 /****************************************************************************** 8366 * Gets the current PCI bus type, speed, and width of the hardware 8367 * 8368 * hw - Struct containing variables accessed by shared code 8369 *****************************************************************************/ 8370 void 8371 em_get_bus_info(struct em_hw *hw) 8372 { 8373 int32_t ret_val; 8374 uint16_t pci_ex_link_status; 8375 uint32_t status; 8376 switch (hw->mac_type) { 8377 case em_82542_rev2_0: 8378 case em_82542_rev2_1: 8379 hw->bus_type = em_bus_type_unknown; 8380 hw->bus_speed = em_bus_speed_unknown; 8381 hw->bus_width = em_bus_width_unknown; 8382 break; 8383 case em_icp_xxxx: 8384 hw->bus_type = em_bus_type_cpp; 8385 hw->bus_speed = em_bus_speed_unknown; 8386 hw->bus_width = em_bus_width_unknown; 8387 break; 8388 case em_82571: 8389 case em_82572: 8390 case em_82573: 8391 case em_82574: 8392 case em_82575: 8393 case em_82576: 8394 case em_82580: 8395 case em_80003es2lan: 8396 case em_i210: 8397 case em_i350: 8398 hw->bus_type = em_bus_type_pci_express; 8399 hw->bus_speed = em_bus_speed_2500; 8400 ret_val = em_read_pcie_cap_reg(hw, PCI_EX_LINK_STATUS, 8401 &pci_ex_link_status); 8402 if (ret_val) 8403 hw->bus_width = em_bus_width_unknown; 8404 else 8405 hw->bus_width = (pci_ex_link_status & 8406 PCI_EX_LINK_WIDTH_MASK) >> PCI_EX_LINK_WIDTH_SHIFT; 8407 break; 8408 case em_ich8lan: 8409 case em_ich9lan: 8410 case em_ich10lan: 8411 case em_pchlan: 8412 case em_pch2lan: 8413 case em_pch_lpt: 8414 case em_pch_spt: 8415 case em_pch_cnp: 8416 hw->bus_type = em_bus_type_pci_express; 8417 hw->bus_speed = em_bus_speed_2500; 8418 hw->bus_width = em_bus_width_pciex_1; 8419 break; 8420 default: 8421 status = E1000_READ_REG(hw, STATUS); 8422 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ? 8423 em_bus_type_pcix : em_bus_type_pci; 8424 8425 if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) { 8426 hw->bus_speed = (hw->bus_type == em_bus_type_pci) ? 8427 em_bus_speed_66 : em_bus_speed_120; 8428 } else if (hw->bus_type == em_bus_type_pci) { 8429 hw->bus_speed = (status & E1000_STATUS_PCI66) ? 8430 em_bus_speed_66 : em_bus_speed_33; 8431 } else { 8432 switch (status & E1000_STATUS_PCIX_SPEED) { 8433 case E1000_STATUS_PCIX_SPEED_66: 8434 hw->bus_speed = em_bus_speed_66; 8435 break; 8436 case E1000_STATUS_PCIX_SPEED_100: 8437 hw->bus_speed = em_bus_speed_100; 8438 break; 8439 case E1000_STATUS_PCIX_SPEED_133: 8440 hw->bus_speed = em_bus_speed_133; 8441 break; 8442 default: 8443 hw->bus_speed = em_bus_speed_reserved; 8444 break; 8445 } 8446 } 8447 hw->bus_width = (status & E1000_STATUS_BUS64) ? 8448 em_bus_width_64 : em_bus_width_32; 8449 break; 8450 } 8451 } 8452 8453 /****************************************************************************** 8454 * Writes a value to one of the devices registers using port I/O (as opposed to 8455 * memory mapped I/O). Only 82544 and newer devices support port I/O. 8456 * 8457 * hw - Struct containing variables accessed by shared code 8458 * offset - offset to write to 8459 * value - value to write 8460 *****************************************************************************/ 8461 STATIC void 8462 em_write_reg_io(struct em_hw *hw, uint32_t offset, uint32_t value) 8463 { 8464 unsigned long io_addr = hw->io_base; 8465 unsigned long io_data = hw->io_base + 4; 8466 em_io_write(hw, io_addr, offset); 8467 em_io_write(hw, io_data, value); 8468 } 8469 8470 /****************************************************************************** 8471 * Estimates the cable length. 8472 * 8473 * hw - Struct containing variables accessed by shared code 8474 * min_length - The estimated minimum length 8475 * max_length - The estimated maximum length 8476 * 8477 * returns: - E1000_ERR_XXX 8478 * E1000_SUCCESS 8479 * 8480 * This function always returns a ranged length (minimum & maximum). 8481 * So for M88 phy's, this function interprets the one value returned from the 8482 * register to the minimum and maximum range. 8483 * For IGP phy's, the function calculates the range by the AGC registers. 8484 *****************************************************************************/ 8485 STATIC int32_t 8486 em_get_cable_length(struct em_hw *hw, uint16_t *min_length, 8487 uint16_t *max_length) 8488 { 8489 int32_t ret_val; 8490 uint16_t agc_value = 0; 8491 uint16_t i, phy_data; 8492 uint16_t cable_length; 8493 DEBUGFUNC("em_get_cable_length"); 8494 8495 *min_length = *max_length = 0; 8496 8497 /* Use old method for Phy older than IGP */ 8498 if (hw->phy_type == em_phy_m88 || 8499 hw->phy_type == em_phy_oem || 8500 hw->phy_type == em_phy_82578) { 8501 8502 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, 8503 &phy_data); 8504 if (ret_val) 8505 return ret_val; 8506 cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 8507 M88E1000_PSSR_CABLE_LENGTH_SHIFT; 8508 8509 /* Convert the enum value to ranged values */ 8510 switch (cable_length) { 8511 case em_cable_length_50: 8512 *min_length = 0; 8513 *max_length = em_igp_cable_length_50; 8514 break; 8515 case em_cable_length_50_80: 8516 *min_length = em_igp_cable_length_50; 8517 *max_length = em_igp_cable_length_80; 8518 break; 8519 case em_cable_length_80_110: 8520 *min_length = em_igp_cable_length_80; 8521 *max_length = em_igp_cable_length_110; 8522 break; 8523 case em_cable_length_110_140: 8524 *min_length = em_igp_cable_length_110; 8525 *max_length = em_igp_cable_length_140; 8526 break; 8527 case em_cable_length_140: 8528 *min_length = em_igp_cable_length_140; 8529 *max_length = em_igp_cable_length_170; 8530 break; 8531 default: 8532 return -E1000_ERR_PHY; 8533 break; 8534 } 8535 } else if (hw->phy_type == em_phy_rtl8211) { 8536 /* no cable length info on RTL8211, fake */ 8537 *min_length = 0; 8538 *max_length = em_igp_cable_length_50; 8539 } else if (hw->phy_type == em_phy_gg82563) { 8540 ret_val = em_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE, 8541 &phy_data); 8542 if (ret_val) 8543 return ret_val; 8544 cable_length = phy_data & GG82563_DSPD_CABLE_LENGTH; 8545 8546 switch (cable_length) { 8547 case em_gg_cable_length_60: 8548 *min_length = 0; 8549 *max_length = em_igp_cable_length_60; 8550 break; 8551 case em_gg_cable_length_60_115: 8552 *min_length = em_igp_cable_length_60; 8553 *max_length = em_igp_cable_length_115; 8554 break; 8555 case em_gg_cable_length_115_150: 8556 *min_length = em_igp_cable_length_115; 8557 *max_length = em_igp_cable_length_150; 8558 break; 8559 case em_gg_cable_length_150: 8560 *min_length = em_igp_cable_length_150; 8561 *max_length = em_igp_cable_length_180; 8562 break; 8563 default: 8564 return -E1000_ERR_PHY; 8565 break; 8566 } 8567 } else if (hw->phy_type == em_phy_igp) { /* For IGP PHY */ 8568 uint16_t cur_agc_value; 8569 uint16_t min_agc_value = 8570 IGP01E1000_AGC_LENGTH_TABLE_SIZE; 8571 uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = 8572 {IGP01E1000_PHY_AGC_A, IGP01E1000_PHY_AGC_B, 8573 IGP01E1000_PHY_AGC_C, IGP01E1000_PHY_AGC_D}; 8574 8575 /* Read the AGC registers for all channels */ 8576 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 8577 ret_val = em_read_phy_reg(hw, agc_reg_array[i], 8578 &phy_data); 8579 if (ret_val) 8580 return ret_val; 8581 8582 cur_agc_value = phy_data >> 8583 IGP01E1000_AGC_LENGTH_SHIFT; 8584 8585 /* Value bound check. */ 8586 if ((cur_agc_value >= 8587 IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) || 8588 (cur_agc_value == 0)) 8589 return -E1000_ERR_PHY; 8590 8591 agc_value += cur_agc_value; 8592 8593 /* Update minimal AGC value. */ 8594 if (min_agc_value > cur_agc_value) 8595 min_agc_value = cur_agc_value; 8596 } 8597 8598 /* Remove the minimal AGC result for length < 50m */ 8599 if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * 8600 em_igp_cable_length_50) { 8601 agc_value -= min_agc_value; 8602 8603 /* 8604 * Get the average length of the remaining 3 channels 8605 */ 8606 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1); 8607 } else { 8608 /* Get the average length of all the 4 channels. */ 8609 agc_value /= IGP01E1000_PHY_CHANNEL_NUM; 8610 } 8611 8612 /* Set the range of the calculated length. */ 8613 *min_length = ((em_igp_cable_length_table[agc_value] - 8614 IGP01E1000_AGC_RANGE) > 0) ? 8615 (em_igp_cable_length_table[agc_value] - 8616 IGP01E1000_AGC_RANGE) : 0; 8617 *max_length = em_igp_cable_length_table[agc_value] + 8618 IGP01E1000_AGC_RANGE; 8619 } else if (hw->phy_type == em_phy_igp_2 || 8620 hw->phy_type == em_phy_igp_3) { 8621 uint16_t cur_agc_index, max_agc_index = 0; 8622 uint16_t min_agc_index = IGP02E1000_AGC_LENGTH_TABLE_SIZE - 1; 8623 uint16_t agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = 8624 {IGP02E1000_PHY_AGC_A, IGP02E1000_PHY_AGC_B, 8625 IGP02E1000_PHY_AGC_C, IGP02E1000_PHY_AGC_D}; 8626 /* Read the AGC registers for all channels */ 8627 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { 8628 ret_val = em_read_phy_reg(hw, agc_reg_array[i], 8629 &phy_data); 8630 if (ret_val) 8631 return ret_val; 8632 /* 8633 * Getting bits 15:9, which represent the combination 8634 * of course and fine gain values. The result is a 8635 * number that can be put into the lookup table to 8636 * obtain the approximate cable length. 8637 */ 8638 cur_agc_index = (phy_data >> 8639 IGP02E1000_AGC_LENGTH_SHIFT) & 8640 IGP02E1000_AGC_LENGTH_MASK; 8641 8642 /* Array index bound check. */ 8643 if ((cur_agc_index >= IGP02E1000_AGC_LENGTH_TABLE_SIZE) 8644 || (cur_agc_index == 0)) 8645 return -E1000_ERR_PHY; 8646 8647 /* Remove min & max AGC values from calculation. */ 8648 if (em_igp_2_cable_length_table[min_agc_index] > 8649 em_igp_2_cable_length_table[cur_agc_index]) 8650 min_agc_index = cur_agc_index; 8651 if (em_igp_2_cable_length_table[max_agc_index] < 8652 em_igp_2_cable_length_table[cur_agc_index]) 8653 max_agc_index = cur_agc_index; 8654 8655 agc_value += em_igp_2_cable_length_table 8656 [cur_agc_index]; 8657 } 8658 8659 agc_value -= (em_igp_2_cable_length_table[min_agc_index] + 8660 em_igp_2_cable_length_table[max_agc_index]); 8661 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); 8662 /* 8663 * Calculate cable length with the error range of +/- 10 8664 * meters. 8665 */ 8666 *min_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ? 8667 (agc_value - IGP02E1000_AGC_RANGE) : 0; 8668 *max_length = agc_value + IGP02E1000_AGC_RANGE; 8669 } 8670 return E1000_SUCCESS; 8671 } 8672 8673 /****************************************************************************** 8674 * Check if Downshift occurred 8675 * 8676 * hw - Struct containing variables accessed by shared code 8677 * downshift - output parameter : 0 - No Downshift occurred. 8678 * 1 - Downshift occurred. 8679 * 8680 * returns: - E1000_ERR_XXX 8681 * E1000_SUCCESS 8682 * 8683 * For phy's older then IGP, this function reads the Downshift bit in the Phy 8684 * Specific Status register. For IGP phy's, it reads the Downgrade bit in the 8685 * Link Health register. In IGP this bit is latched high, so the driver must 8686 * read it immediately after link is established. 8687 *****************************************************************************/ 8688 STATIC int32_t 8689 em_check_downshift(struct em_hw *hw) 8690 { 8691 int32_t ret_val; 8692 uint16_t phy_data; 8693 DEBUGFUNC("em_check_downshift"); 8694 8695 if (hw->phy_type == em_phy_igp || 8696 hw->phy_type == em_phy_igp_3 || 8697 hw->phy_type == em_phy_igp_2) { 8698 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH, 8699 &phy_data); 8700 if (ret_val) 8701 return ret_val; 8702 8703 hw->speed_downgraded = (phy_data & 8704 IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0; 8705 } else if ((hw->phy_type == em_phy_m88) || 8706 (hw->phy_type == em_phy_gg82563) || 8707 (hw->phy_type == em_phy_oem) || 8708 (hw->phy_type == em_phy_82578)) { 8709 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, 8710 &phy_data); 8711 if (ret_val) 8712 return ret_val; 8713 8714 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >> 8715 M88E1000_PSSR_DOWNSHIFT_SHIFT; 8716 } else if (hw->phy_type == em_phy_ife) { 8717 /* em_phy_ife supports 10/100 speed only */ 8718 hw->speed_downgraded = FALSE; 8719 } 8720 return E1000_SUCCESS; 8721 } 8722 8723 /***************************************************************************** 8724 * 8725 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a 8726 * gigabit link is achieved to improve link quality. 8727 * 8728 * hw: Struct containing variables accessed by shared code 8729 * 8730 * returns: - E1000_ERR_PHY if fail to read/write the PHY 8731 * E1000_SUCCESS at any other case. 8732 * 8733 ****************************************************************************/ 8734 STATIC int32_t 8735 em_config_dsp_after_link_change(struct em_hw *hw, boolean_t link_up) 8736 { 8737 int32_t ret_val; 8738 uint16_t phy_data, phy_saved_data, speed, duplex, i; 8739 uint16_t dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = 8740 {IGP01E1000_PHY_AGC_PARAM_A, IGP01E1000_PHY_AGC_PARAM_B, 8741 IGP01E1000_PHY_AGC_PARAM_C, IGP01E1000_PHY_AGC_PARAM_D}; 8742 uint16_t min_length, max_length; 8743 DEBUGFUNC("em_config_dsp_after_link_change"); 8744 8745 if (hw->phy_type != em_phy_igp) 8746 return E1000_SUCCESS; 8747 8748 if (link_up) { 8749 ret_val = em_get_speed_and_duplex(hw, &speed, &duplex); 8750 if (ret_val) { 8751 DEBUGOUT("Error getting link speed and duplex\n"); 8752 return ret_val; 8753 } 8754 if (speed == SPEED_1000) { 8755 8756 ret_val = em_get_cable_length(hw, &min_length, &max_length); 8757 if (ret_val) 8758 return ret_val; 8759 8760 if ((hw->dsp_config_state == em_dsp_config_enabled) && 8761 min_length >= em_igp_cable_length_50) { 8762 8763 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; 8764 i++) { 8765 ret_val = em_read_phy_reg(hw, 8766 dsp_reg_array[i], &phy_data); 8767 if (ret_val) 8768 return ret_val; 8769 8770 phy_data &= 8771 ~IGP01E1000_PHY_EDAC_MU_INDEX; 8772 8773 ret_val = em_write_phy_reg(hw, 8774 dsp_reg_array[i], phy_data); 8775 if (ret_val) 8776 return ret_val; 8777 } 8778 hw->dsp_config_state = em_dsp_config_activated; 8779 } 8780 if ((hw->ffe_config_state == em_ffe_config_enabled) && 8781 (min_length < em_igp_cable_length_50)) { 8782 8783 uint16_t ffe_idle_err_timeout = 8784 FFE_IDLE_ERR_COUNT_TIMEOUT_20; 8785 uint32_t idle_errs = 0; 8786 /* clear previous idle error counts */ 8787 ret_val = em_read_phy_reg(hw, PHY_1000T_STATUS, 8788 &phy_data); 8789 if (ret_val) 8790 return ret_val; 8791 8792 for (i = 0; i < ffe_idle_err_timeout; i++) { 8793 usec_delay(1000); 8794 ret_val = em_read_phy_reg(hw, 8795 PHY_1000T_STATUS, &phy_data); 8796 if (ret_val) 8797 return ret_val; 8798 8799 idle_errs += (phy_data & 8800 SR_1000T_IDLE_ERROR_CNT); 8801 if (idle_errs > 8802 SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) { 8803 hw->ffe_config_state = 8804 em_ffe_config_active; 8805 8806 ret_val = em_write_phy_reg(hw, 8807 IGP01E1000_PHY_DSP_FFE, 8808 IGP01E1000_PHY_DSP_FFE_CM_CP); 8809 if (ret_val) 8810 return ret_val; 8811 break; 8812 } 8813 if (idle_errs) 8814 ffe_idle_err_timeout = 8815 FFE_IDLE_ERR_COUNT_TIMEOUT_100; 8816 } 8817 } 8818 } 8819 } else { 8820 if (hw->dsp_config_state == em_dsp_config_activated) { 8821 /* 8822 * Save off the current value of register 0x2F5B to 8823 * be restored at the end of the routines. 8824 */ 8825 ret_val = em_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 8826 8827 if (ret_val) 8828 return ret_val; 8829 8830 /* Disable the PHY transmitter */ 8831 ret_val = em_write_phy_reg(hw, 0x2F5B, 0x0003); 8832 8833 if (ret_val) 8834 return ret_val; 8835 8836 msec_delay_irq(20); 8837 8838 ret_val = em_write_phy_reg(hw, 0x0000, 8839 IGP01E1000_IEEE_FORCE_GIGA); 8840 if (ret_val) 8841 return ret_val; 8842 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 8843 ret_val = em_read_phy_reg(hw, dsp_reg_array[i], 8844 &phy_data); 8845 if (ret_val) 8846 return ret_val; 8847 8848 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; 8849 phy_data |= 8850 IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS; 8851 8852 ret_val = em_write_phy_reg(hw, 8853 dsp_reg_array[i], phy_data); 8854 if (ret_val) 8855 return ret_val; 8856 } 8857 8858 ret_val = em_write_phy_reg(hw, 0x0000, 8859 IGP01E1000_IEEE_RESTART_AUTONEG); 8860 if (ret_val) 8861 return ret_val; 8862 8863 msec_delay_irq(20); 8864 8865 /* Now enable the transmitter */ 8866 ret_val = em_write_phy_reg(hw, 0x2F5B, phy_saved_data); 8867 8868 if (ret_val) 8869 return ret_val; 8870 8871 hw->dsp_config_state = em_dsp_config_enabled; 8872 } 8873 if (hw->ffe_config_state == em_ffe_config_active) { 8874 /* 8875 * Save off the current value of register 0x2F5B to 8876 * be restored at the end of the routines. 8877 */ 8878 ret_val = em_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 8879 8880 if (ret_val) 8881 return ret_val; 8882 8883 /* Disable the PHY transmitter */ 8884 ret_val = em_write_phy_reg(hw, 0x2F5B, 0x0003); 8885 8886 if (ret_val) 8887 return ret_val; 8888 8889 msec_delay_irq(20); 8890 8891 ret_val = em_write_phy_reg(hw, 0x0000, 8892 IGP01E1000_IEEE_FORCE_GIGA); 8893 if (ret_val) 8894 return ret_val; 8895 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE, 8896 IGP01E1000_PHY_DSP_FFE_DEFAULT); 8897 if (ret_val) 8898 return ret_val; 8899 8900 ret_val = em_write_phy_reg(hw, 0x0000, 8901 IGP01E1000_IEEE_RESTART_AUTONEG); 8902 if (ret_val) 8903 return ret_val; 8904 8905 msec_delay_irq(20); 8906 8907 /* Now enable the transmitter */ 8908 ret_val = em_write_phy_reg(hw, 0x2F5B, phy_saved_data); 8909 8910 if (ret_val) 8911 return ret_val; 8912 8913 hw->ffe_config_state = em_ffe_config_enabled; 8914 } 8915 } 8916 return E1000_SUCCESS; 8917 } 8918 8919 /***************************************************************************** 8920 * Set PHY to class A mode 8921 * Assumes the following operations will follow to enable the new class mode. 8922 * 1. Do a PHY soft reset 8923 * 2. Restart auto-negotiation or force link. 8924 * 8925 * hw - Struct containing variables accessed by shared code 8926 ****************************************************************************/ 8927 static int32_t 8928 em_set_phy_mode(struct em_hw *hw) 8929 { 8930 int32_t ret_val; 8931 uint16_t eeprom_data; 8932 DEBUGFUNC("em_set_phy_mode"); 8933 8934 if ((hw->mac_type == em_82545_rev_3) && 8935 (hw->media_type == em_media_type_copper)) { 8936 ret_val = em_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, 8937 &eeprom_data); 8938 if (ret_val) { 8939 return ret_val; 8940 } 8941 if ((eeprom_data != EEPROM_RESERVED_WORD) && 8942 (eeprom_data & EEPROM_PHY_CLASS_A)) { 8943 ret_val = em_write_phy_reg(hw, 8944 M88E1000_PHY_PAGE_SELECT, 0x000B); 8945 if (ret_val) 8946 return ret_val; 8947 ret_val = em_write_phy_reg(hw, 8948 M88E1000_PHY_GEN_CONTROL, 0x8104); 8949 if (ret_val) 8950 return ret_val; 8951 8952 hw->phy_reset_disable = FALSE; 8953 } 8954 } 8955 return E1000_SUCCESS; 8956 } 8957 8958 /***************************************************************************** 8959 * 8960 * This function sets the lplu state according to the active flag. When 8961 * activating lplu this function also disables smart speed and vise versa. 8962 * lplu will not be activated unless the device autonegotiation advertisement 8963 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. 8964 * hw: Struct containing variables accessed by shared code 8965 * active - true to enable lplu false to disable lplu. 8966 * 8967 * returns: - E1000_ERR_PHY if fail to read/write the PHY 8968 * E1000_SUCCESS at any other case. 8969 * 8970 ****************************************************************************/ 8971 STATIC int32_t 8972 em_set_d3_lplu_state(struct em_hw *hw, boolean_t active) 8973 { 8974 uint32_t phy_ctrl = 0; 8975 int32_t ret_val; 8976 uint16_t phy_data; 8977 DEBUGFUNC("em_set_d3_lplu_state"); 8978 8979 if (hw->phy_type != em_phy_igp && hw->phy_type != em_phy_igp_2 8980 && hw->phy_type != em_phy_igp_3) 8981 return E1000_SUCCESS; 8982 /* 8983 * During driver activity LPLU should not be used or it will attain 8984 * link from the lowest speeds starting from 10Mbps. The capability 8985 * is used for Dx transitions and states 8986 */ 8987 if (hw->mac_type == em_82541_rev_2 || hw->mac_type == em_82547_rev_2) { 8988 ret_val = em_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data); 8989 if (ret_val) 8990 return ret_val; 8991 } else if (IS_ICH8(hw->mac_type)) { 8992 /* 8993 * MAC writes into PHY register based on the state transition 8994 * and start auto-negotiation. SW driver can overwrite the 8995 * settings in CSR PHY power control E1000_PHY_CTRL register. 8996 */ 8997 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); 8998 } else { 8999 ret_val = em_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, 9000 &phy_data); 9001 if (ret_val) 9002 return ret_val; 9003 } 9004 9005 if (!active) { 9006 if (hw->mac_type == em_82541_rev_2 || 9007 hw->mac_type == em_82547_rev_2) { 9008 phy_data &= ~IGP01E1000_GMII_FLEX_SPD; 9009 ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO, 9010 phy_data); 9011 if (ret_val) 9012 return ret_val; 9013 } else { 9014 if (IS_ICH8(hw->mac_type)) { 9015 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; 9016 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 9017 } else { 9018 phy_data &= ~IGP02E1000_PM_D3_LPLU; 9019 ret_val = em_write_phy_reg(hw, 9020 IGP02E1000_PHY_POWER_MGMT, phy_data); 9021 if (ret_val) 9022 return ret_val; 9023 } 9024 } 9025 /* 9026 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 9027 * during Dx states where the power conservation is most 9028 * important. During driver activity we should enable 9029 * SmartSpeed, so performance is maintained. 9030 */ 9031 if (hw->smart_speed == em_smart_speed_on) { 9032 ret_val = em_read_phy_reg(hw, 9033 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 9034 if (ret_val) 9035 return ret_val; 9036 9037 phy_data |= IGP01E1000_PSCFR_SMART_SPEED; 9038 ret_val = em_write_phy_reg(hw, 9039 IGP01E1000_PHY_PORT_CONFIG, phy_data); 9040 if (ret_val) 9041 return ret_val; 9042 } else if (hw->smart_speed == em_smart_speed_off) { 9043 ret_val = em_read_phy_reg(hw, 9044 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 9045 if (ret_val) 9046 return ret_val; 9047 9048 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 9049 ret_val = em_write_phy_reg(hw, 9050 IGP01E1000_PHY_PORT_CONFIG, phy_data); 9051 if (ret_val) 9052 return ret_val; 9053 } 9054 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) 9055 || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) || 9056 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) { 9057 9058 if (hw->mac_type == em_82541_rev_2 || 9059 hw->mac_type == em_82547_rev_2) { 9060 phy_data |= IGP01E1000_GMII_FLEX_SPD; 9061 ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO, 9062 phy_data); 9063 if (ret_val) 9064 return ret_val; 9065 } else { 9066 if (IS_ICH8(hw->mac_type)) { 9067 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; 9068 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 9069 } else { 9070 phy_data |= IGP02E1000_PM_D3_LPLU; 9071 ret_val = em_write_phy_reg(hw, 9072 IGP02E1000_PHY_POWER_MGMT, phy_data); 9073 if (ret_val) 9074 return ret_val; 9075 } 9076 } 9077 9078 /* When LPLU is enabled we should disable SmartSpeed */ 9079 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 9080 &phy_data); 9081 if (ret_val) 9082 return ret_val; 9083 9084 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 9085 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 9086 phy_data); 9087 if (ret_val) 9088 return ret_val; 9089 9090 } 9091 return E1000_SUCCESS; 9092 } 9093 9094 /***************************************************************************** 9095 * 9096 * This function sets the lplu d0 state according to the active flag. When 9097 * activating lplu this function also disables smart speed and vise versa. 9098 * lplu will not be activated unless the device autonegotiation advertisement 9099 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. 9100 * hw: Struct containing variables accessed by shared code 9101 * active - true to enable lplu false to disable lplu. 9102 * 9103 * returns: - E1000_ERR_PHY if fail to read/write the PHY 9104 * E1000_SUCCESS at any other case. 9105 * 9106 ****************************************************************************/ 9107 STATIC int32_t 9108 em_set_d0_lplu_state(struct em_hw *hw, boolean_t active) 9109 { 9110 uint32_t phy_ctrl = 0; 9111 int32_t ret_val; 9112 uint16_t phy_data; 9113 DEBUGFUNC("em_set_d0_lplu_state"); 9114 9115 if (hw->mac_type <= em_82547_rev_2) 9116 return E1000_SUCCESS; 9117 9118 if (IS_ICH8(hw->mac_type)) { 9119 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); 9120 } else { 9121 ret_val = em_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, 9122 &phy_data); 9123 if (ret_val) 9124 return ret_val; 9125 } 9126 9127 if (!active) { 9128 if (IS_ICH8(hw->mac_type)) { 9129 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; 9130 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 9131 } else { 9132 phy_data &= ~IGP02E1000_PM_D0_LPLU; 9133 ret_val = em_write_phy_reg(hw, 9134 IGP02E1000_PHY_POWER_MGMT, phy_data); 9135 if (ret_val) 9136 return ret_val; 9137 } 9138 /* 9139 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 9140 * during Dx states where the power conservation is most 9141 * important. During driver activity we should enable 9142 * SmartSpeed, so performance is maintained. 9143 */ 9144 if (hw->smart_speed == em_smart_speed_on) { 9145 ret_val = em_read_phy_reg(hw, 9146 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 9147 if (ret_val) 9148 return ret_val; 9149 9150 phy_data |= IGP01E1000_PSCFR_SMART_SPEED; 9151 ret_val = em_write_phy_reg(hw, 9152 IGP01E1000_PHY_PORT_CONFIG, phy_data); 9153 if (ret_val) 9154 return ret_val; 9155 } else if (hw->smart_speed == em_smart_speed_off) { 9156 ret_val = em_read_phy_reg(hw, 9157 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 9158 if (ret_val) 9159 return ret_val; 9160 9161 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 9162 ret_val = em_write_phy_reg(hw, 9163 IGP01E1000_PHY_PORT_CONFIG, phy_data); 9164 if (ret_val) 9165 return ret_val; 9166 } 9167 } else { 9168 if (IS_ICH8(hw->mac_type)) { 9169 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; 9170 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 9171 } else { 9172 phy_data |= IGP02E1000_PM_D0_LPLU; 9173 ret_val = em_write_phy_reg(hw, 9174 IGP02E1000_PHY_POWER_MGMT, phy_data); 9175 if (ret_val) 9176 return ret_val; 9177 } 9178 9179 /* When LPLU is enabled we should disable SmartSpeed */ 9180 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 9181 &phy_data); 9182 if (ret_val) 9183 return ret_val; 9184 9185 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 9186 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 9187 phy_data); 9188 if (ret_val) 9189 return ret_val; 9190 9191 } 9192 return E1000_SUCCESS; 9193 } 9194 9195 /*************************************************************************** 9196 * Set Low Power Link Up state 9197 * 9198 * Sets the LPLU state according to the active flag. For PCH, if OEM write 9199 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set 9200 * the phy speed. This function will manually set the LPLU bit and restart 9201 * auto-neg as hw would do. D3 and D0 LPLU will call the same function 9202 * since it configures the same bit. 9203 ***************************************************************************/ 9204 int32_t 9205 em_set_lplu_state_pchlan(struct em_hw *hw, boolean_t active) 9206 { 9207 int32_t ret_val = E1000_SUCCESS; 9208 uint16_t oem_reg; 9209 9210 DEBUGFUNC("e1000_set_lplu_state_pchlan"); 9211 9212 ret_val = em_read_phy_reg(hw, HV_OEM_BITS, &oem_reg); 9213 if (ret_val) 9214 goto out; 9215 9216 if (active) 9217 oem_reg |= HV_OEM_BITS_LPLU; 9218 else 9219 oem_reg &= ~HV_OEM_BITS_LPLU; 9220 9221 oem_reg |= HV_OEM_BITS_RESTART_AN; 9222 ret_val = em_write_phy_reg(hw, HV_OEM_BITS, oem_reg); 9223 9224 out: 9225 return ret_val; 9226 } 9227 9228 /****************************************************************************** 9229 * Change VCO speed register to improve Bit Error Rate performance of SERDES. 9230 * 9231 * hw - Struct containing variables accessed by shared code 9232 *****************************************************************************/ 9233 static int32_t 9234 em_set_vco_speed(struct em_hw *hw) 9235 { 9236 int32_t ret_val; 9237 uint16_t default_page = 0; 9238 uint16_t phy_data; 9239 DEBUGFUNC("em_set_vco_speed"); 9240 9241 switch (hw->mac_type) { 9242 case em_82545_rev_3: 9243 case em_82546_rev_3: 9244 break; 9245 default: 9246 return E1000_SUCCESS; 9247 } 9248 9249 /* Set PHY register 30, page 5, bit 8 to 0 */ 9250 9251 ret_val = em_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page); 9252 if (ret_val) 9253 return ret_val; 9254 9255 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005); 9256 if (ret_val) 9257 return ret_val; 9258 9259 ret_val = em_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); 9260 if (ret_val) 9261 return ret_val; 9262 9263 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8; 9264 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); 9265 if (ret_val) 9266 return ret_val; 9267 9268 /* Set PHY register 30, page 4, bit 11 to 1 */ 9269 9270 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004); 9271 if (ret_val) 9272 return ret_val; 9273 9274 ret_val = em_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); 9275 if (ret_val) 9276 return ret_val; 9277 9278 phy_data |= M88E1000_PHY_VCO_REG_BIT11; 9279 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); 9280 if (ret_val) 9281 return ret_val; 9282 9283 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page); 9284 if (ret_val) 9285 return ret_val; 9286 9287 return E1000_SUCCESS; 9288 } 9289 9290 /***************************************************************************** 9291 * This function reads the cookie from ARC ram. 9292 * 9293 * returns: - E1000_SUCCESS . 9294 ****************************************************************************/ 9295 STATIC int32_t 9296 em_host_if_read_cookie(struct em_hw *hw, uint8_t *buffer) 9297 { 9298 uint8_t i; 9299 uint32_t offset = E1000_MNG_DHCP_COOKIE_OFFSET; 9300 uint8_t length = E1000_MNG_DHCP_COOKIE_LENGTH; 9301 length = (length >> 2); 9302 offset = (offset >> 2); 9303 9304 for (i = 0; i < length; i++) { 9305 *((uint32_t *) buffer + i) = 9306 E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i); 9307 } 9308 return E1000_SUCCESS; 9309 } 9310 9311 /***************************************************************************** 9312 * This function checks whether the HOST IF is enabled for command operation 9313 * and also checks whether the previous command is completed. 9314 * It busy waits in case of previous command is not completed. 9315 * 9316 * returns: - E1000_ERR_HOST_INTERFACE_COMMAND in case if is not ready or 9317 * timeout 9318 * - E1000_SUCCESS for success. 9319 ****************************************************************************/ 9320 STATIC int32_t 9321 em_mng_enable_host_if(struct em_hw *hw) 9322 { 9323 uint32_t hicr; 9324 uint8_t i; 9325 /* Check that the host interface is enabled. */ 9326 hicr = E1000_READ_REG(hw, HICR); 9327 if ((hicr & E1000_HICR_EN) == 0) { 9328 DEBUGOUT("E1000_HOST_EN bit disabled.\n"); 9329 return -E1000_ERR_HOST_INTERFACE_COMMAND; 9330 } 9331 /* check the previous command is completed */ 9332 for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) { 9333 hicr = E1000_READ_REG(hw, HICR); 9334 if (!(hicr & E1000_HICR_C)) 9335 break; 9336 msec_delay_irq(1); 9337 } 9338 9339 if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) { 9340 DEBUGOUT("Previous command timeout failed .\n"); 9341 return -E1000_ERR_HOST_INTERFACE_COMMAND; 9342 } 9343 return E1000_SUCCESS; 9344 } 9345 9346 /***************************************************************************** 9347 * This function checks the mode of the firmware. 9348 * 9349 * returns - TRUE when the mode is IAMT or FALSE. 9350 ****************************************************************************/ 9351 boolean_t 9352 em_check_mng_mode(struct em_hw *hw) 9353 { 9354 uint32_t fwsm; 9355 fwsm = E1000_READ_REG(hw, FWSM); 9356 9357 if (IS_ICH8(hw->mac_type)) { 9358 if ((fwsm & E1000_FWSM_MODE_MASK) == 9359 (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) 9360 return TRUE; 9361 } else if ((fwsm & E1000_FWSM_MODE_MASK) == 9362 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) 9363 return TRUE; 9364 9365 return FALSE; 9366 } 9367 9368 /***************************************************************************** 9369 * This function calculates the checksum. 9370 * 9371 * returns - checksum of buffer contents. 9372 ****************************************************************************/ 9373 STATIC uint8_t 9374 em_calculate_mng_checksum(char *buffer, uint32_t length) 9375 { 9376 uint8_t sum = 0; 9377 uint32_t i; 9378 if (!buffer) 9379 return 0; 9380 9381 for (i = 0; i < length; i++) 9382 sum += buffer[i]; 9383 9384 return (uint8_t) (0 - sum); 9385 } 9386 9387 /***************************************************************************** 9388 * This function checks whether tx pkt filtering needs to be enabled or not. 9389 * 9390 * returns - TRUE for packet filtering or FALSE. 9391 ****************************************************************************/ 9392 boolean_t 9393 em_enable_tx_pkt_filtering(struct em_hw *hw) 9394 { 9395 /* called in init as well as watchdog timer functions */ 9396 int32_t ret_val, checksum; 9397 boolean_t tx_filter = FALSE; 9398 struct em_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie); 9399 uint8_t *buffer = (uint8_t *) & (hw->mng_cookie); 9400 if (em_check_mng_mode(hw)) { 9401 ret_val = em_mng_enable_host_if(hw); 9402 if (ret_val == E1000_SUCCESS) { 9403 ret_val = em_host_if_read_cookie(hw, buffer); 9404 if (ret_val == E1000_SUCCESS) { 9405 checksum = hdr->checksum; 9406 hdr->checksum = 0; 9407 if ((hdr->signature == E1000_IAMT_SIGNATURE) && 9408 checksum == em_calculate_mng_checksum( 9409 (char *) buffer, 9410 E1000_MNG_DHCP_COOKIE_LENGTH)) { 9411 if (hdr->status & 9412 E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT) 9413 tx_filter = TRUE; 9414 } else 9415 tx_filter = TRUE; 9416 } else 9417 tx_filter = TRUE; 9418 } 9419 } 9420 hw->tx_pkt_filtering = tx_filter; 9421 return tx_filter; 9422 } 9423 9424 static int32_t 9425 em_polarity_reversal_workaround(struct em_hw *hw) 9426 { 9427 int32_t ret_val; 9428 uint16_t mii_status_reg; 9429 uint16_t i; 9430 /* Polarity reversal workaround for forced 10F/10H links. */ 9431 9432 /* Disable the transmitter on the PHY */ 9433 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 9434 if (ret_val) 9435 return ret_val; 9436 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF); 9437 if (ret_val) 9438 return ret_val; 9439 9440 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 9441 if (ret_val) 9442 return ret_val; 9443 9444 /* This loop will early-out if the NO link condition has been met. */ 9445 for (i = PHY_FORCE_TIME; i > 0; i--) { 9446 /* 9447 * Read the MII Status Register and wait for Link Status bit 9448 * to be clear. 9449 */ 9450 9451 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 9452 if (ret_val) 9453 return ret_val; 9454 9455 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 9456 if (ret_val) 9457 return ret_val; 9458 9459 if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) 9460 break; 9461 msec_delay_irq(100); 9462 } 9463 9464 /* Recommended delay time after link has been lost */ 9465 msec_delay_irq(1000); 9466 9467 /* Now we will re-enable the transmitter on the PHY */ 9468 9469 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 9470 if (ret_val) 9471 return ret_val; 9472 msec_delay_irq(50); 9473 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0); 9474 if (ret_val) 9475 return ret_val; 9476 msec_delay_irq(50); 9477 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00); 9478 if (ret_val) 9479 return ret_val; 9480 msec_delay_irq(50); 9481 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000); 9482 if (ret_val) 9483 return ret_val; 9484 9485 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 9486 if (ret_val) 9487 return ret_val; 9488 9489 /* This loop will early-out if the link condition has been met. */ 9490 for (i = PHY_FORCE_TIME; i > 0; i--) { 9491 /* 9492 * Read the MII Status Register and wait for Link Status bit 9493 * to be set. 9494 */ 9495 9496 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 9497 if (ret_val) 9498 return ret_val; 9499 9500 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 9501 if (ret_val) 9502 return ret_val; 9503 9504 if (mii_status_reg & MII_SR_LINK_STATUS) 9505 break; 9506 msec_delay_irq(100); 9507 } 9508 return E1000_SUCCESS; 9509 } 9510 9511 /****************************************************************************** 9512 * 9513 * Disables PCI-Express master access. 9514 * 9515 * hw: Struct containing variables accessed by shared code 9516 * 9517 * returns: - none. 9518 * 9519 *****************************************************************************/ 9520 STATIC void 9521 em_set_pci_express_master_disable(struct em_hw *hw) 9522 { 9523 uint32_t ctrl; 9524 DEBUGFUNC("em_set_pci_express_master_disable"); 9525 9526 if (hw->bus_type != em_bus_type_pci_express) 9527 return; 9528 9529 ctrl = E1000_READ_REG(hw, CTRL); 9530 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; 9531 E1000_WRITE_REG(hw, CTRL, ctrl); 9532 } 9533 9534 /****************************************************************************** 9535 * 9536 * Disables PCI-Express master access and verifies there are no pending 9537 * requests 9538 * 9539 * hw: Struct containing variables accessed by shared code 9540 * 9541 * returns: - E1000_ERR_MASTER_REQUESTS_PENDING if master disable bit hasn't 9542 * caused the master requests to be disabled. 9543 * E1000_SUCCESS master requests disabled. 9544 * 9545 ******************************************************************************/ 9546 int32_t 9547 em_disable_pciex_master(struct em_hw *hw) 9548 { 9549 int32_t timeout = MASTER_DISABLE_TIMEOUT; /* 80ms */ 9550 DEBUGFUNC("em_disable_pciex_master"); 9551 9552 if (hw->bus_type != em_bus_type_pci_express) 9553 return E1000_SUCCESS; 9554 9555 em_set_pci_express_master_disable(hw); 9556 9557 while (timeout) { 9558 if (!(E1000_READ_REG(hw, STATUS) & 9559 E1000_STATUS_GIO_MASTER_ENABLE)) 9560 break; 9561 else 9562 usec_delay(100); 9563 timeout--; 9564 } 9565 9566 if (!timeout) { 9567 DEBUGOUT("Master requests are pending.\n"); 9568 return -E1000_ERR_MASTER_REQUESTS_PENDING; 9569 } 9570 return E1000_SUCCESS; 9571 } 9572 9573 /****************************************************************************** 9574 * 9575 * Check for EEPROM Auto Read bit done. 9576 * 9577 * hw: Struct containing variables accessed by shared code 9578 * 9579 * returns: - E1000_ERR_RESET if fail to reset MAC 9580 * E1000_SUCCESS at any other case. 9581 * 9582 ******************************************************************************/ 9583 STATIC int32_t 9584 em_get_auto_rd_done(struct em_hw *hw) 9585 { 9586 int32_t timeout = AUTO_READ_DONE_TIMEOUT; 9587 DEBUGFUNC("em_get_auto_rd_done"); 9588 9589 switch (hw->mac_type) { 9590 default: 9591 msec_delay(5); 9592 break; 9593 case em_82571: 9594 case em_82572: 9595 case em_82573: 9596 case em_82574: 9597 case em_82575: 9598 case em_82576: 9599 case em_82580: 9600 case em_80003es2lan: 9601 case em_i210: 9602 case em_i350: 9603 case em_ich8lan: 9604 case em_ich9lan: 9605 case em_ich10lan: 9606 case em_pchlan: 9607 case em_pch2lan: 9608 case em_pch_lpt: 9609 case em_pch_spt: 9610 case em_pch_cnp: 9611 while (timeout) { 9612 if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD) 9613 break; 9614 else 9615 msec_delay(1); 9616 timeout--; 9617 } 9618 9619 if (!timeout) { 9620 DEBUGOUT("Auto read by HW from EEPROM has not" 9621 " completed.\n"); 9622 return -E1000_ERR_RESET; 9623 } 9624 break; 9625 } 9626 /* 9627 * PHY configuration from NVM just starts after EECD_AUTO_RD sets to 9628 * high. Need to wait for PHY configuration completion before 9629 * accessing NVM and PHY. 9630 */ 9631 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) 9632 msec_delay(25); 9633 9634 return E1000_SUCCESS; 9635 } 9636 9637 /*************************************************************************** 9638 * Checks if the PHY configuration is done 9639 * 9640 * hw: Struct containing variables accessed by shared code 9641 * 9642 * returns: - E1000_ERR_RESET if fail to reset MAC 9643 * E1000_SUCCESS at any other case. 9644 * 9645 ***************************************************************************/ 9646 STATIC int32_t 9647 em_get_phy_cfg_done(struct em_hw *hw) 9648 { 9649 int32_t timeout = PHY_CFG_TIMEOUT; 9650 uint32_t cfg_mask = E1000_NVM_CFG_DONE_PORT_0; 9651 DEBUGFUNC("em_get_phy_cfg_done"); 9652 9653 switch (hw->mac_type) { 9654 default: 9655 msec_delay_irq(10); 9656 break; 9657 case em_80003es2lan: 9658 case em_82575: 9659 case em_82576: 9660 case em_82580: 9661 case em_i350: 9662 switch (hw->bus_func) { 9663 case 1: 9664 cfg_mask = E1000_NVM_CFG_DONE_PORT_1; 9665 break; 9666 case 2: 9667 cfg_mask = E1000_NVM_CFG_DONE_PORT_2; 9668 break; 9669 case 3: 9670 cfg_mask = E1000_NVM_CFG_DONE_PORT_3; 9671 break; 9672 } 9673 /* FALLTHROUGH */ 9674 case em_82571: 9675 case em_82572: 9676 while (timeout) { 9677 if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask) 9678 break; 9679 else 9680 msec_delay(1); 9681 timeout--; 9682 } 9683 if (!timeout) { 9684 DEBUGOUT("MNG configuration cycle has not completed." 9685 "\n"); 9686 } 9687 break; 9688 } 9689 9690 return E1000_SUCCESS; 9691 } 9692 9693 /*************************************************************************** 9694 * 9695 * Using the combination of SMBI and SWESMBI semaphore bits when resetting 9696 * adapter or Eeprom access. 9697 * 9698 * hw: Struct containing variables accessed by shared code 9699 * 9700 * returns: - E1000_ERR_EEPROM if fail to access EEPROM. 9701 * E1000_SUCCESS at any other case. 9702 * 9703 ***************************************************************************/ 9704 STATIC int32_t 9705 em_get_hw_eeprom_semaphore(struct em_hw *hw) 9706 { 9707 int32_t timeout; 9708 uint32_t swsm; 9709 DEBUGFUNC("em_get_hw_eeprom_semaphore"); 9710 9711 if (!hw->eeprom_semaphore_present) 9712 return E1000_SUCCESS; 9713 9714 if (hw->mac_type == em_80003es2lan) { 9715 /* Get the SW semaphore. */ 9716 if (em_get_software_semaphore(hw) != E1000_SUCCESS) 9717 return -E1000_ERR_EEPROM; 9718 } 9719 /* Get the FW semaphore. */ 9720 timeout = hw->eeprom.word_size + 1; 9721 while (timeout) { 9722 swsm = E1000_READ_REG(hw, SWSM); 9723 swsm |= E1000_SWSM_SWESMBI; 9724 E1000_WRITE_REG(hw, SWSM, swsm); 9725 /* if we managed to set the bit we got the semaphore. */ 9726 swsm = E1000_READ_REG(hw, SWSM); 9727 if (swsm & E1000_SWSM_SWESMBI) 9728 break; 9729 9730 usec_delay(50); 9731 timeout--; 9732 } 9733 9734 if (!timeout) { 9735 /* Release semaphores */ 9736 em_put_hw_eeprom_semaphore(hw); 9737 DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set." 9738 "\n"); 9739 return -E1000_ERR_EEPROM; 9740 } 9741 return E1000_SUCCESS; 9742 } 9743 9744 /*************************************************************************** 9745 * This function clears HW semaphore bits. 9746 * 9747 * hw: Struct containing variables accessed by shared code 9748 * 9749 * returns: - None. 9750 * 9751 ***************************************************************************/ 9752 STATIC void 9753 em_put_hw_eeprom_semaphore(struct em_hw *hw) 9754 { 9755 uint32_t swsm; 9756 DEBUGFUNC("em_put_hw_eeprom_semaphore"); 9757 9758 if (!hw->eeprom_semaphore_present) 9759 return; 9760 9761 swsm = E1000_READ_REG(hw, SWSM); 9762 if (hw->mac_type == em_80003es2lan) { 9763 /* Release both semaphores. */ 9764 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 9765 } else 9766 swsm &= ~(E1000_SWSM_SWESMBI); 9767 E1000_WRITE_REG(hw, SWSM, swsm); 9768 } 9769 9770 /*************************************************************************** 9771 * 9772 * Obtaining software semaphore bit (SMBI) before resetting PHY. 9773 * 9774 * hw: Struct containing variables accessed by shared code 9775 * 9776 * returns: - E1000_ERR_RESET if fail to obtain semaphore. 9777 * E1000_SUCCESS at any other case. 9778 * 9779 ***************************************************************************/ 9780 STATIC int32_t 9781 em_get_software_semaphore(struct em_hw *hw) 9782 { 9783 int32_t timeout = hw->eeprom.word_size + 1; 9784 uint32_t swsm; 9785 DEBUGFUNC("em_get_software_semaphore"); 9786 9787 if (hw->mac_type != em_80003es2lan) 9788 return E1000_SUCCESS; 9789 9790 while (timeout) { 9791 swsm = E1000_READ_REG(hw, SWSM); 9792 /* 9793 * If SMBI bit cleared, it is now set and we hold the 9794 * semaphore 9795 */ 9796 if (!(swsm & E1000_SWSM_SMBI)) 9797 break; 9798 msec_delay_irq(1); 9799 timeout--; 9800 } 9801 9802 if (!timeout) { 9803 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 9804 return -E1000_ERR_RESET; 9805 } 9806 return E1000_SUCCESS; 9807 } 9808 9809 /*************************************************************************** 9810 * 9811 * Release semaphore bit (SMBI). 9812 * 9813 * hw: Struct containing variables accessed by shared code 9814 * 9815 ***************************************************************************/ 9816 STATIC void 9817 em_release_software_semaphore(struct em_hw *hw) 9818 { 9819 uint32_t swsm; 9820 DEBUGFUNC("em_release_software_semaphore"); 9821 9822 if (hw->mac_type != em_80003es2lan) 9823 return; 9824 9825 swsm = E1000_READ_REG(hw, SWSM); 9826 /* Release the SW semaphores. */ 9827 swsm &= ~E1000_SWSM_SMBI; 9828 E1000_WRITE_REG(hw, SWSM, swsm); 9829 } 9830 9831 /****************************************************************************** 9832 * Checks if PHY reset is blocked due to SOL/IDER session, for example. 9833 * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to 9834 * the caller to figure out how to deal with it. 9835 * 9836 * hw - Struct containing variables accessed by shared code 9837 * 9838 * returns: - E1000_BLK_PHY_RESET 9839 * E1000_SUCCESS 9840 * 9841 *****************************************************************************/ 9842 int32_t 9843 em_check_phy_reset_block(struct em_hw *hw) 9844 { 9845 uint32_t manc = 0; 9846 uint32_t fwsm = 0; 9847 DEBUGFUNC("em_check_phy_reset_block\n"); 9848 9849 if (IS_ICH8(hw->mac_type)) { 9850 int i = 0; 9851 int blocked = 0; 9852 do { 9853 fwsm = E1000_READ_REG(hw, FWSM); 9854 if (!(fwsm & E1000_FWSM_RSPCIPHY)) { 9855 blocked = 1; 9856 msec_delay(10); 9857 continue; 9858 } 9859 blocked = 0; 9860 } while (blocked && (i++ < 30)); 9861 return blocked ? E1000_BLK_PHY_RESET : E1000_SUCCESS; 9862 } 9863 if (hw->mac_type > em_82547_rev_2) 9864 manc = E1000_READ_REG(hw, MANC); 9865 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? 9866 E1000_BLK_PHY_RESET : E1000_SUCCESS; 9867 } 9868 9869 /****************************************************************************** 9870 * Configure PCI-Ex no-snoop 9871 * 9872 * hw - Struct containing variables accessed by shared code. 9873 * no_snoop - Bitmap of no-snoop events. 9874 * 9875 * returns: E1000_SUCCESS 9876 * 9877 *****************************************************************************/ 9878 STATIC int32_t 9879 em_set_pci_ex_no_snoop(struct em_hw *hw, uint32_t no_snoop) 9880 { 9881 uint32_t gcr_reg = 0; 9882 DEBUGFUNC("em_set_pci_ex_no_snoop"); 9883 9884 if (hw->bus_type == em_bus_type_unknown) 9885 em_get_bus_info(hw); 9886 9887 if (hw->bus_type != em_bus_type_pci_express) 9888 return E1000_SUCCESS; 9889 9890 if (no_snoop) { 9891 gcr_reg = E1000_READ_REG(hw, GCR); 9892 gcr_reg &= ~(PCI_EX_NO_SNOOP_ALL); 9893 gcr_reg |= no_snoop; 9894 E1000_WRITE_REG(hw, GCR, gcr_reg); 9895 } 9896 if (IS_ICH8(hw->mac_type)) { 9897 uint32_t ctrl_ext; 9898 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 9899 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 9900 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 9901 } 9902 return E1000_SUCCESS; 9903 } 9904 9905 /*************************************************************************** 9906 * 9907 * Get software semaphore FLAG bit (SWFLAG). 9908 * SWFLAG is used to synchronize the access to all shared resource between 9909 * SW, FW and HW. 9910 * 9911 * hw: Struct containing variables accessed by shared code 9912 * 9913 ***************************************************************************/ 9914 STATIC int32_t 9915 em_get_software_flag(struct em_hw *hw) 9916 { 9917 int32_t timeout = PHY_CFG_TIMEOUT; 9918 uint32_t extcnf_ctrl; 9919 DEBUGFUNC("em_get_software_flag"); 9920 9921 if (IS_ICH8(hw->mac_type)) { 9922 if (hw->sw_flag) { 9923 hw->sw_flag++; 9924 return E1000_SUCCESS; 9925 } 9926 while (timeout) { 9927 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 9928 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)) 9929 break; 9930 msec_delay_irq(1); 9931 timeout--; 9932 } 9933 if (!timeout) { 9934 printf("%s: SW has already locked the resource?\n", 9935 __func__); 9936 return -E1000_ERR_CONFIG; 9937 } 9938 timeout = SW_FLAG_TIMEOUT; 9939 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; 9940 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); 9941 9942 while (timeout) { 9943 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 9944 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) 9945 break; 9946 msec_delay_irq(1); 9947 timeout--; 9948 } 9949 9950 if (!timeout) { 9951 printf("Failed to acquire the semaphore, FW or HW " 9952 "has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n", 9953 E1000_READ_REG(hw, FWSM), extcnf_ctrl); 9954 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 9955 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); 9956 return -E1000_ERR_CONFIG; 9957 } 9958 } 9959 hw->sw_flag++; 9960 return E1000_SUCCESS; 9961 } 9962 9963 /*************************************************************************** 9964 * 9965 * Release software semaphore FLAG bit (SWFLAG). 9966 * SWFLAG is used to synchronize the access to all shared resource between 9967 * SW, FW and HW. 9968 * 9969 * hw: Struct containing variables accessed by shared code 9970 * 9971 ***************************************************************************/ 9972 STATIC void 9973 em_release_software_flag(struct em_hw *hw) 9974 { 9975 uint32_t extcnf_ctrl; 9976 DEBUGFUNC("em_release_software_flag"); 9977 9978 if (IS_ICH8(hw->mac_type)) { 9979 KASSERT(hw->sw_flag > 0); 9980 if (--hw->sw_flag > 0) 9981 return; 9982 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 9983 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 9984 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); 9985 } 9986 return; 9987 } 9988 9989 /** 9990 * em_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1 9991 * @hw: pointer to the HW structure 9992 * @bank: pointer to the variable that returns the active bank 9993 * 9994 * Reads signature byte from the NVM using the flash access registers. 9995 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank. 9996 **/ 9997 int32_t 9998 em_valid_nvm_bank_detect_ich8lan(struct em_hw *hw, uint32_t *bank) 9999 { 10000 uint32_t eecd; 10001 uint32_t bank1_offset = hw->flash_bank_size * sizeof(uint16_t); 10002 uint32_t act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1; 10003 uint32_t nvm_dword = 0; 10004 uint8_t sig_byte = 0; 10005 int32_t ret_val; 10006 10007 DEBUGFUNC("em_valid_nvm_bank_detect_ich8lan"); 10008 10009 switch (hw->mac_type) { 10010 case em_pch_spt: 10011 case em_pch_cnp: 10012 bank1_offset = hw->flash_bank_size * 2; 10013 act_offset = E1000_ICH_NVM_SIG_WORD * 2; 10014 10015 /* set bank to 0 in case flash read fails. */ 10016 *bank = 0; 10017 10018 /* Check bank 0 */ 10019 ret_val = em_read_ich8_dword(hw, act_offset, &nvm_dword); 10020 if (ret_val) 10021 return ret_val; 10022 sig_byte = (uint8_t)((nvm_dword & 0xFF00) >> 8); 10023 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 10024 E1000_ICH_NVM_SIG_VALUE) { 10025 *bank = 0; 10026 return 0; 10027 } 10028 10029 /* Check bank 1 */ 10030 ret_val = em_read_ich8_dword(hw, act_offset + bank1_offset, 10031 &nvm_dword); 10032 if (ret_val) 10033 return ret_val; 10034 sig_byte = (uint8_t)((nvm_dword & 0xFF00) >> 8); 10035 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 10036 E1000_ICH_NVM_SIG_VALUE) { 10037 *bank = 1; 10038 return 0; 10039 } 10040 10041 DEBUGOUT("ERROR: No valid NVM bank present\n"); 10042 return -1; 10043 case em_ich8lan: 10044 case em_ich9lan: 10045 eecd = E1000_READ_REG(hw, EECD); 10046 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) == 10047 E1000_EECD_SEC1VAL_VALID_MASK) { 10048 if (eecd & E1000_EECD_SEC1VAL) 10049 *bank = 1; 10050 else 10051 *bank = 0; 10052 10053 return E1000_SUCCESS; 10054 } 10055 DEBUGOUT("Unable to determine valid NVM bank via EEC - reading flash signature\n"); 10056 /* fall-thru */ 10057 default: 10058 /* set bank to 0 in case flash read fails */ 10059 *bank = 0; 10060 10061 /* Check bank 0 */ 10062 ret_val = em_read_ich8_byte(hw, act_offset, 10063 &sig_byte); 10064 if (ret_val) 10065 return ret_val; 10066 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 10067 E1000_ICH_NVM_SIG_VALUE) { 10068 *bank = 0; 10069 return E1000_SUCCESS; 10070 } 10071 10072 /* Check bank 1 */ 10073 ret_val = em_read_ich8_byte(hw, act_offset + 10074 bank1_offset, 10075 &sig_byte); 10076 if (ret_val) 10077 return ret_val; 10078 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 10079 E1000_ICH_NVM_SIG_VALUE) { 10080 *bank = 1; 10081 return E1000_SUCCESS; 10082 } 10083 10084 DEBUGOUT("ERROR: No valid NVM bank present\n"); 10085 return -1; 10086 } 10087 } 10088 10089 STATIC int32_t 10090 em_read_eeprom_spt(struct em_hw *hw, uint16_t offset, uint16_t words, 10091 uint16_t *data) 10092 { 10093 int32_t error = E1000_SUCCESS; 10094 uint32_t flash_bank = 0; 10095 uint32_t act_offset = 0; 10096 uint32_t bank_offset = 0; 10097 uint32_t dword = 0; 10098 uint16_t i = 0, add; 10099 10100 /* 10101 * We need to know which is the valid flash bank. In the event that 10102 * we didn't allocate eeprom_shadow_ram, we may not be managing 10103 * flash_bank. So it cannot be trusted and needs to be updated with 10104 * each read. 10105 */ 10106 10107 if (hw->mac_type < em_pch_spt) 10108 return -E1000_ERR_EEPROM; 10109 10110 error = em_get_software_flag(hw); 10111 if (error != E1000_SUCCESS) 10112 return error; 10113 10114 error = em_valid_nvm_bank_detect_ich8lan(hw, &flash_bank); 10115 if (error != E1000_SUCCESS) { 10116 DEBUGOUT("Could not detect valid bank, assuming bank 0\n"); 10117 flash_bank = 0; 10118 } 10119 10120 /* 10121 * Adjust offset appropriately if we're on bank 1 - adjust for word 10122 * size 10123 */ 10124 bank_offset = flash_bank * (hw->flash_bank_size * 2); 10125 10126 for (i = add = 0; i < words; i += add) { 10127 if ((offset + i) % 2) { 10128 add = 1; 10129 if (hw->eeprom_shadow_ram != NULL 10130 && hw->eeprom_shadow_ram[offset + i].modified) { 10131 data[i] = 10132 hw->eeprom_shadow_ram[offset+i].eeprom_word; 10133 continue; 10134 } 10135 act_offset = bank_offset + (offset + i - 1) * 2; 10136 } else { 10137 add = 2; 10138 if (hw->eeprom_shadow_ram != NULL 10139 && hw->eeprom_shadow_ram[offset+i].modified 10140 && hw->eeprom_shadow_ram[offset+i+1].modified) { 10141 data[i] = hw->eeprom_shadow_ram[offset+i].eeprom_word; 10142 data[i+1] = hw->eeprom_shadow_ram[offset+i+1].eeprom_word; 10143 continue; 10144 } 10145 act_offset = bank_offset + (offset + i) * 2; 10146 } 10147 error = em_read_ich8_dword(hw, act_offset, &dword); 10148 if (error != E1000_SUCCESS) 10149 break; 10150 if (hw->eeprom_shadow_ram != NULL 10151 && hw->eeprom_shadow_ram[offset+i].modified) { 10152 data[i] = hw->eeprom_shadow_ram[offset+i].eeprom_word; 10153 } else { 10154 if (add == 1) 10155 data[i] = dword >> 16; 10156 else 10157 data[i] = dword & 0xFFFFUL; 10158 } 10159 if (add == 1 || words-i == 1) 10160 continue; 10161 if (hw->eeprom_shadow_ram != NULL 10162 && hw->eeprom_shadow_ram[offset+i+1].modified) { 10163 data[i+1] = 10164 hw->eeprom_shadow_ram[offset+i+1].eeprom_word; 10165 } else { 10166 data[i+1] = dword >> 16; 10167 } 10168 } 10169 10170 em_release_software_flag(hw); 10171 10172 return error; 10173 } 10174 10175 /****************************************************************************** 10176 * Reads a 16 bit word or words from the EEPROM using the ICH8's flash access 10177 * register. 10178 * 10179 * hw - Struct containing variables accessed by shared code 10180 * offset - offset of word in the EEPROM to read 10181 * data - word read from the EEPROM 10182 * words - number of words to read 10183 *****************************************************************************/ 10184 STATIC int32_t 10185 em_read_eeprom_ich8(struct em_hw *hw, uint16_t offset, uint16_t words, 10186 uint16_t *data) 10187 { 10188 int32_t error = E1000_SUCCESS; 10189 uint32_t flash_bank = 0; 10190 uint32_t act_offset = 0; 10191 uint32_t bank_offset = 0; 10192 uint16_t word = 0; 10193 uint16_t i = 0; 10194 /* 10195 * We need to know which is the valid flash bank. In the event that 10196 * we didn't allocate eeprom_shadow_ram, we may not be managing 10197 * flash_bank. So it cannot be trusted and needs to be updated with 10198 * each read. 10199 */ 10200 10201 if (hw->mac_type >= em_pch_spt) 10202 return em_read_eeprom_spt(hw, offset, words, data); 10203 10204 error = em_get_software_flag(hw); 10205 if (error != E1000_SUCCESS) 10206 return error; 10207 10208 error = em_valid_nvm_bank_detect_ich8lan(hw, &flash_bank); 10209 if (error != E1000_SUCCESS) { 10210 DEBUGOUT("Could not detect valid bank, assuming bank 0\n"); 10211 flash_bank = 0; 10212 } 10213 10214 /* 10215 * Adjust offset appropriately if we're on bank 1 - adjust for word 10216 * size 10217 */ 10218 bank_offset = flash_bank * (hw->flash_bank_size * 2); 10219 10220 for (i = 0; i < words; i++) { 10221 if (hw->eeprom_shadow_ram != NULL && 10222 hw->eeprom_shadow_ram[offset + i].modified == TRUE) { 10223 data[i] = 10224 hw->eeprom_shadow_ram[offset + i].eeprom_word; 10225 } else { 10226 /* The NVM part needs a byte offset, hence * 2 */ 10227 act_offset = bank_offset + ((offset + i) * 2); 10228 error = em_read_ich8_word(hw, act_offset, &word); 10229 if (error != E1000_SUCCESS) 10230 break; 10231 data[i] = word; 10232 } 10233 } 10234 10235 em_release_software_flag(hw); 10236 10237 return error; 10238 } 10239 10240 /****************************************************************************** 10241 * Writes a 16 bit word or words to the EEPROM using the ICH8's flash access 10242 * register. Actually, writes are written to the shadow ram cache in the hw 10243 * structure hw->em_shadow_ram. em_commit_shadow_ram flushes this to 10244 * the NVM, which occurs when the NVM checksum is updated. 10245 * 10246 * hw - Struct containing variables accessed by shared code 10247 * offset - offset of word in the EEPROM to write 10248 * words - number of words to write 10249 * data - words to write to the EEPROM 10250 *****************************************************************************/ 10251 STATIC int32_t 10252 em_write_eeprom_ich8(struct em_hw *hw, uint16_t offset, uint16_t words, 10253 uint16_t *data) 10254 { 10255 uint32_t i = 0; 10256 int32_t error = E1000_SUCCESS; 10257 error = em_get_software_flag(hw); 10258 if (error != E1000_SUCCESS) 10259 return error; 10260 /* 10261 * A driver can write to the NVM only if it has eeprom_shadow_ram 10262 * allocated. Subsequent reads to the modified words are read from 10263 * this cached structure as well. Writes will only go into this 10264 * cached structure unless it's followed by a call to 10265 * em_update_eeprom_checksum() where it will commit the changes and 10266 * clear the "modified" field. 10267 */ 10268 if (hw->eeprom_shadow_ram != NULL) { 10269 for (i = 0; i < words; i++) { 10270 if ((offset + i) < E1000_SHADOW_RAM_WORDS) { 10271 hw->eeprom_shadow_ram[offset + i].modified = 10272 TRUE; 10273 hw->eeprom_shadow_ram[offset + i].eeprom_word = 10274 data[i]; 10275 } else { 10276 error = -E1000_ERR_EEPROM; 10277 break; 10278 } 10279 } 10280 } else { 10281 /* 10282 * Drivers have the option to not allocate eeprom_shadow_ram 10283 * as long as they don't perform any NVM writes. An attempt 10284 * in doing so will result in this error. 10285 */ 10286 error = -E1000_ERR_EEPROM; 10287 } 10288 10289 em_release_software_flag(hw); 10290 10291 return error; 10292 } 10293 10294 /****************************************************************************** 10295 * This function does initial flash setup so that a new read/write/erase cycle 10296 * can be started. 10297 * 10298 * hw - The pointer to the hw structure 10299 ****************************************************************************/ 10300 STATIC int32_t 10301 em_ich8_cycle_init(struct em_hw *hw) 10302 { 10303 union ich8_hws_flash_status hsfsts; 10304 int32_t error = E1000_ERR_EEPROM; 10305 int32_t i = 0; 10306 DEBUGFUNC("em_ich8_cycle_init"); 10307 10308 if (hw->mac_type >= em_pch_spt) 10309 hsfsts.regval = E1000_READ_ICH_FLASH_REG32(hw, 10310 ICH_FLASH_HSFSTS) & 0xFFFFUL; 10311 else 10312 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, 10313 ICH_FLASH_HSFSTS); 10314 10315 /* May be check the Flash Des Valid bit in Hw status */ 10316 if (hsfsts.hsf_status.fldesvalid == 0) { 10317 DEBUGOUT("Flash descriptor invalid. SW Sequencing must be" 10318 " used."); 10319 return error; 10320 } 10321 /* Clear FCERR in Hw status by writing 1 */ 10322 /* Clear DAEL in Hw status by writing a 1 */ 10323 hsfsts.hsf_status.flcerr = 1; 10324 hsfsts.hsf_status.dael = 1; 10325 if (hw->mac_type >= em_pch_spt) 10326 E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_HSFSTS, 10327 hsfsts.regval & 0xFFFFUL); 10328 else 10329 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, 10330 hsfsts.regval); 10331 /* 10332 * Either we should have a hardware SPI cycle in progress bit to 10333 * check against, in order to start a new cycle or FDONE bit should 10334 * be changed in the hardware so that it is 1 after hardware reset, 10335 * which can then be used as an indication whether a cycle is in 10336 * progress or has been completed .. we should also have some 10337 * software semaphore mechanism to guard FDONE or the cycle in 10338 * progress bit so that two threads access to those bits can be 10339 * sequentiallized or a way so that 2 threads dont start the cycle at 10340 * the same time 10341 */ 10342 10343 if (hsfsts.hsf_status.flcinprog == 0) { 10344 /* 10345 * There is no cycle running at present, so we can start a 10346 * cycle 10347 */ 10348 /* Begin by setting Flash Cycle Done. */ 10349 hsfsts.hsf_status.flcdone = 1; 10350 if (hw->mac_type >= em_pch_spt) 10351 E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_HSFSTS, 10352 hsfsts.regval & 0xFFFFUL); 10353 else 10354 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, 10355 hsfsts.regval); 10356 error = E1000_SUCCESS; 10357 } else { 10358 /* 10359 * otherwise poll for sometime so the current cycle has a 10360 * chance to end before giving up. 10361 */ 10362 for (i = 0; i < ICH_FLASH_COMMAND_TIMEOUT; i++) { 10363 if (hw->mac_type >= em_pch_spt) 10364 hsfsts.regval = E1000_READ_ICH_FLASH_REG32( 10365 hw, ICH_FLASH_HSFSTS) & 0xFFFFUL; 10366 else 10367 hsfsts.regval = E1000_READ_ICH_FLASH_REG16( 10368 hw, ICH_FLASH_HSFSTS); 10369 if (hsfsts.hsf_status.flcinprog == 0) { 10370 error = E1000_SUCCESS; 10371 break; 10372 } 10373 usec_delay(1); 10374 } 10375 if (error == E1000_SUCCESS) { 10376 /* 10377 * Successful in waiting for previous cycle to 10378 * timeout, now set the Flash Cycle Done. 10379 */ 10380 hsfsts.hsf_status.flcdone = 1; 10381 if (hw->mac_type >= em_pch_spt) 10382 E1000_WRITE_ICH_FLASH_REG32(hw, 10383 ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFFUL); 10384 else 10385 E1000_WRITE_ICH_FLASH_REG16(hw, 10386 ICH_FLASH_HSFSTS, hsfsts.regval); 10387 } else { 10388 DEBUGOUT("Flash controller busy, cannot get access"); 10389 } 10390 } 10391 return error; 10392 } 10393 10394 /****************************************************************************** 10395 * This function starts a flash cycle and waits for its completion 10396 * 10397 * hw - The pointer to the hw structure 10398 *****************************************************************************/ 10399 STATIC int32_t 10400 em_ich8_flash_cycle(struct em_hw *hw, uint32_t timeout) 10401 { 10402 union ich8_hws_flash_ctrl hsflctl; 10403 union ich8_hws_flash_status hsfsts; 10404 int32_t error = E1000_ERR_EEPROM; 10405 uint32_t i = 0; 10406 10407 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ 10408 if (hw->mac_type >= em_pch_spt) 10409 hsflctl.regval = E1000_READ_ICH_FLASH_REG32(hw, 10410 ICH_FLASH_HSFSTS) >> 16; 10411 else 10412 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, 10413 ICH_FLASH_HSFCTL); 10414 hsflctl.hsf_ctrl.flcgo = 1; 10415 10416 if (hw->mac_type >= em_pch_spt) 10417 E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_HSFSTS, 10418 (uint32_t)hsflctl.regval << 16); 10419 else 10420 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, 10421 hsflctl.regval); 10422 10423 /* wait till FDONE bit is set to 1 */ 10424 do { 10425 if (hw->mac_type >= em_pch_spt) 10426 hsfsts.regval = E1000_READ_ICH_FLASH_REG32(hw, 10427 ICH_FLASH_HSFSTS) & 0xFFFFUL; 10428 else 10429 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, 10430 ICH_FLASH_HSFSTS); 10431 if (hsfsts.hsf_status.flcdone == 1) 10432 break; 10433 usec_delay(1); 10434 i++; 10435 } while (i < timeout); 10436 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) { 10437 error = E1000_SUCCESS; 10438 } 10439 return error; 10440 } 10441 10442 /****************************************************************************** 10443 * Reads a byte or word from the NVM using the ICH8 flash access registers. 10444 * 10445 * hw - The pointer to the hw structure 10446 * index - The index of the byte or word to read. 10447 * size - Size of data to read, 1=byte 2=word 10448 * data - Pointer to the word to store the value read. 10449 *****************************************************************************/ 10450 STATIC int32_t 10451 em_read_ich8_data(struct em_hw *hw, uint32_t index, uint32_t size, 10452 uint16_t *data) 10453 { 10454 union ich8_hws_flash_status hsfsts; 10455 union ich8_hws_flash_ctrl hsflctl; 10456 uint32_t flash_linear_address; 10457 uint32_t flash_data = 0; 10458 int32_t error = -E1000_ERR_EEPROM; 10459 int32_t count = 0; 10460 DEBUGFUNC("em_read_ich8_data"); 10461 10462 if (size < 1 || size > 2 || data == 0x0 || 10463 index > ICH_FLASH_LINEAR_ADDR_MASK) 10464 return error; 10465 10466 flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) + 10467 hw->flash_base_addr; 10468 10469 do { 10470 usec_delay(1); 10471 /* Steps */ 10472 error = em_ich8_cycle_init(hw); 10473 if (error != E1000_SUCCESS) 10474 break; 10475 10476 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, 10477 ICH_FLASH_HSFCTL); 10478 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 10479 hsflctl.hsf_ctrl.fldbcount = size - 1; 10480 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; 10481 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, 10482 hsflctl.regval); 10483 /* 10484 * Write the last 24 bits of index into Flash Linear address 10485 * field in Flash Address 10486 */ 10487 /* TODO: TBD maybe check the index against the size of flash */ 10488 10489 E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_FADDR, 10490 flash_linear_address); 10491 10492 error = em_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT); 10493 /* 10494 * Check if FCERR is set to 1, if set to 1, clear it and try 10495 * the whole sequence a few more times, else read in (shift 10496 * in) the Flash Data0, the order is least significant byte 10497 * first msb to lsb 10498 */ 10499 if (error == E1000_SUCCESS) { 10500 flash_data = E1000_READ_ICH_FLASH_REG(hw, 10501 ICH_FLASH_FDATA0); 10502 if (size == 1) { 10503 *data = (uint8_t) (flash_data & 0x000000FF); 10504 } else if (size == 2) { 10505 *data = (uint16_t) (flash_data & 0x0000FFFF); 10506 } 10507 break; 10508 } else { 10509 /* 10510 * If we've gotten here, then things are probably 10511 * completely hosed, but if the error condition is 10512 * detected, it won't hurt to give it another 10513 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 10514 */ 10515 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, 10516 ICH_FLASH_HSFSTS); 10517 if (hsfsts.hsf_status.flcerr == 1) { 10518 /* Repeat for some time before giving up. */ 10519 continue; 10520 } else if (hsfsts.hsf_status.flcdone == 0) { 10521 DEBUGOUT("Timeout error - flash cycle did not" 10522 " complete."); 10523 break; 10524 } 10525 } 10526 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 10527 10528 return error; 10529 } 10530 10531 STATIC int32_t 10532 em_read_ich8_data32(struct em_hw *hw, uint32_t offset, uint32_t *data) 10533 { 10534 union ich8_hws_flash_status hsfsts; 10535 union ich8_hws_flash_ctrl hsflctl; 10536 uint32_t flash_linear_address; 10537 int32_t error = -E1000_ERR_EEPROM; 10538 uint32_t count = 0; 10539 DEBUGFUNC("em_read_ich8_data32"); 10540 10541 if (hw->mac_type < em_pch_spt) 10542 return error; 10543 if (offset > ICH_FLASH_LINEAR_ADDR_MASK) 10544 return error; 10545 flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & offset) + 10546 hw->flash_base_addr; 10547 10548 do { 10549 usec_delay(1); 10550 /* Steps */ 10551 error = em_ich8_cycle_init(hw); 10552 if (error != E1000_SUCCESS) 10553 break; 10554 10555 /* 32 bit accesses in SPT. */ 10556 hsflctl.regval = E1000_READ_ICH_FLASH_REG32(hw, 10557 ICH_FLASH_HSFSTS) >> 16; 10558 10559 hsflctl.hsf_ctrl.fldbcount = sizeof(uint32_t) - 1; 10560 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; 10561 10562 E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_HSFSTS, 10563 (uint32_t)hsflctl.regval << 16); 10564 /* 10565 * Write the last 24 bits of offset into Flash Linear address 10566 * field in Flash Address 10567 */ 10568 /* TODO: TBD maybe check the offset against the size of flash */ 10569 10570 E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_FADDR, 10571 flash_linear_address); 10572 10573 error = em_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT); 10574 /* 10575 * Check if FCERR is set to 1, if set to 1, clear it and try 10576 * the whole sequence a few more times, else read in (shift 10577 * in) the Flash Data0, the order is least significant byte 10578 * first msb to lsb 10579 */ 10580 if (error == E1000_SUCCESS) { 10581 (*data) = (uint32_t)E1000_READ_ICH_FLASH_REG32(hw, 10582 ICH_FLASH_FDATA0); 10583 break; 10584 } else { 10585 /* 10586 * If we've gotten here, then things are probably 10587 * completely hosed, but if the error condition is 10588 * detected, it won't hurt to give it another 10589 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 10590 */ 10591 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, 10592 ICH_FLASH_HSFSTS); 10593 if (hsfsts.hsf_status.flcerr == 1) { 10594 /* Repeat for some time before giving up. */ 10595 continue; 10596 } else if (hsfsts.hsf_status.flcdone == 0) { 10597 DEBUGOUT("Timeout error - flash cycle did not" 10598 " complete."); 10599 break; 10600 } 10601 } 10602 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 10603 10604 return error; 10605 } 10606 10607 10608 /****************************************************************************** 10609 * Writes One /two bytes to the NVM using the ICH8 flash access registers. 10610 * 10611 * hw - The pointer to the hw structure 10612 * index - The index of the byte/word to write. 10613 * size - Size of data to read, 1=byte 2=word 10614 * data - The byte(s) to write to the NVM. 10615 *****************************************************************************/ 10616 STATIC int32_t 10617 em_write_ich8_data(struct em_hw *hw, uint32_t index, uint32_t size, 10618 uint16_t data) 10619 { 10620 union ich8_hws_flash_status hsfsts; 10621 union ich8_hws_flash_ctrl hsflctl; 10622 uint32_t flash_linear_address; 10623 uint32_t flash_data = 0; 10624 int32_t error = -E1000_ERR_EEPROM; 10625 int32_t count = 0; 10626 DEBUGFUNC("em_write_ich8_data"); 10627 10628 if (hw->mac_type >= em_pch_spt) 10629 return -E1000_ERR_EEPROM; 10630 if (size < 1 || size > 2 || data > size * 0xff || 10631 index > ICH_FLASH_LINEAR_ADDR_MASK) 10632 return error; 10633 10634 flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) + 10635 hw->flash_base_addr; 10636 10637 do { 10638 usec_delay(1); 10639 /* Steps */ 10640 error = em_ich8_cycle_init(hw); 10641 if (error != E1000_SUCCESS) 10642 break; 10643 10644 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, 10645 ICH_FLASH_HSFCTL); 10646 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 10647 hsflctl.hsf_ctrl.fldbcount = size - 1; 10648 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; 10649 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, 10650 hsflctl.regval); 10651 /* 10652 * Write the last 24 bits of index into Flash Linear address 10653 * field in Flash Address 10654 */ 10655 E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_FADDR, 10656 flash_linear_address); 10657 10658 if (size == 1) 10659 flash_data = (uint32_t) data & 0x00FF; 10660 else 10661 flash_data = (uint32_t) data; 10662 10663 E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_FDATA0, flash_data); 10664 /* 10665 * check if FCERR is set to 1 , if set to 1, clear it and try 10666 * the whole sequence a few more times else done 10667 */ 10668 error = em_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT); 10669 if (error == E1000_SUCCESS) { 10670 break; 10671 } else { 10672 /* 10673 * If we're here, then things are most likely 10674 * completely hosed, but if the error condition is 10675 * detected, it won't hurt to give it another 10676 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 10677 */ 10678 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, 10679 ICH_FLASH_HSFSTS); 10680 if (hsfsts.hsf_status.flcerr == 1) { 10681 /* Repeat for some time before giving up. */ 10682 continue; 10683 } else if (hsfsts.hsf_status.flcdone == 0) { 10684 DEBUGOUT("Timeout error - flash cycle did not" 10685 " complete."); 10686 break; 10687 } 10688 } 10689 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 10690 10691 return error; 10692 } 10693 10694 /****************************************************************************** 10695 * Reads a single byte from the NVM using the ICH8 flash access registers. 10696 * 10697 * hw - pointer to em_hw structure 10698 * index - The index of the byte to read. 10699 * data - Pointer to a byte to store the value read. 10700 *****************************************************************************/ 10701 STATIC int32_t 10702 em_read_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t *data) 10703 { 10704 int32_t status = E1000_SUCCESS; 10705 uint16_t word = 0; 10706 10707 if (hw->mac_type >= em_pch_spt) 10708 return -E1000_ERR_EEPROM; 10709 else 10710 status = em_read_ich8_data(hw, index, 1, &word); 10711 if (status == E1000_SUCCESS) { 10712 *data = (uint8_t) word; 10713 } 10714 return status; 10715 } 10716 10717 /****************************************************************************** 10718 * Writes a single byte to the NVM using the ICH8 flash access registers. 10719 * Performs verification by reading back the value and then going through 10720 * a retry algorithm before giving up. 10721 * 10722 * hw - pointer to em_hw structure 10723 * index - The index of the byte to write. 10724 * byte - The byte to write to the NVM. 10725 *****************************************************************************/ 10726 STATIC int32_t 10727 em_verify_write_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t byte) 10728 { 10729 int32_t error = E1000_SUCCESS; 10730 int32_t program_retries = 0; 10731 DEBUGOUT2("Byte := %2.2X Offset := %d\n", byte, index); 10732 10733 error = em_write_ich8_byte(hw, index, byte); 10734 10735 if (error != E1000_SUCCESS) { 10736 for (program_retries = 0; program_retries < 100; 10737 program_retries++) { 10738 DEBUGOUT2("Retrying \t Byte := %2.2X Offset := %d\n", 10739 byte, index); 10740 error = em_write_ich8_byte(hw, index, byte); 10741 usec_delay(100); 10742 if (error == E1000_SUCCESS) 10743 break; 10744 } 10745 } 10746 if (program_retries == 100) 10747 error = E1000_ERR_EEPROM; 10748 10749 return error; 10750 } 10751 10752 /****************************************************************************** 10753 * Writes a single byte to the NVM using the ICH8 flash access registers. 10754 * 10755 * hw - pointer to em_hw structure 10756 * index - The index of the byte to read. 10757 * data - The byte to write to the NVM. 10758 *****************************************************************************/ 10759 STATIC int32_t 10760 em_write_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t data) 10761 { 10762 int32_t status = E1000_SUCCESS; 10763 uint16_t word = (uint16_t) data; 10764 status = em_write_ich8_data(hw, index, 1, word); 10765 10766 return status; 10767 } 10768 10769 /****************************************************************************** 10770 * Reads a dword from the NVM using the ICH8 flash access registers. 10771 * 10772 * hw - pointer to em_hw structure 10773 * index - The starting BYTE index of the word to read. 10774 * data - Pointer to a word to store the value read. 10775 *****************************************************************************/ 10776 STATIC int32_t 10777 em_read_ich8_dword(struct em_hw *hw, uint32_t index, uint32_t *data) 10778 { 10779 int32_t status = E1000_SUCCESS; 10780 status = em_read_ich8_data32(hw, index, data); 10781 return status; 10782 } 10783 10784 /****************************************************************************** 10785 * Reads a word from the NVM using the ICH8 flash access registers. 10786 * 10787 * hw - pointer to em_hw structure 10788 * index - The starting byte index of the word to read. 10789 * data - Pointer to a word to store the value read. 10790 *****************************************************************************/ 10791 STATIC int32_t 10792 em_read_ich8_word(struct em_hw *hw, uint32_t index, uint16_t *data) 10793 { 10794 int32_t status = E1000_SUCCESS; 10795 status = em_read_ich8_data(hw, index, 2, data); 10796 return status; 10797 } 10798 10799 /****************************************************************************** 10800 * Erases the bank specified. Each bank may be a 4, 8 or 64k block. Banks are 0 10801 * based. 10802 * 10803 * hw - pointer to em_hw structure 10804 * bank - 0 for first bank, 1 for second bank 10805 * 10806 * Note that this function may actually erase as much as 8 or 64 KBytes. The 10807 * amount of NVM used in each bank is a *minimum* of 4 KBytes, but in fact the 10808 * bank size may be 4, 8 or 64 KBytes 10809 *****************************************************************************/ 10810 int32_t 10811 em_erase_ich8_4k_segment(struct em_hw *hw, uint32_t bank) 10812 { 10813 union ich8_hws_flash_status hsfsts; 10814 union ich8_hws_flash_ctrl hsflctl; 10815 uint32_t flash_linear_address; 10816 int32_t count = 0; 10817 int32_t error = E1000_ERR_EEPROM; 10818 int32_t iteration; 10819 int32_t sub_sector_size = 0; 10820 int32_t bank_size; 10821 int32_t j = 0; 10822 int32_t error_flag = 0; 10823 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 10824 /* 10825 * Determine HW Sector size: Read BERASE bits of Hw flash Status 10826 * register 10827 */ 10828 /* 10829 * 00: The Hw sector is 256 bytes, hence we need to erase 16 10830 * consecutive sectors. The start index for the nth Hw sector can be 10831 * calculated as bank * 4096 + n * 256 01: The Hw sector is 4K bytes, 10832 * hence we need to erase 1 sector. The start index for the nth Hw 10833 * sector can be calculated as bank * 4096 10: The HW sector is 8K 10834 * bytes 11: The Hw sector size is 64K bytes 10835 */ 10836 if (hsfsts.hsf_status.berasesz == 0x0) { 10837 /* Hw sector size 256 */ 10838 sub_sector_size = ICH_FLASH_SEG_SIZE_256; 10839 bank_size = ICH_FLASH_SECTOR_SIZE; 10840 iteration = ICH_FLASH_SECTOR_SIZE / ICH_FLASH_SEG_SIZE_256; 10841 } else if (hsfsts.hsf_status.berasesz == 0x1) { 10842 bank_size = ICH_FLASH_SEG_SIZE_4K; 10843 iteration = 1; 10844 } else if (hsfsts.hsf_status.berasesz == 0x2) { 10845 if (hw->mac_type == em_ich9lan) { 10846 uint32_t gfpreg, sector_base_addr, sector_end_addr; 10847 gfpreg = E1000_READ_ICH_FLASH_REG(hw, 10848 ICH_FLASH_GFPREG); 10849 /* 10850 * sector_X_addr is a "sector"-aligned address (4096 bytes) 10851 * Add 1 to sector_end_addr since this sector is included in 10852 * the overall size. 10853 */ 10854 sector_base_addr = gfpreg & ICH_GFPREG_BASE_MASK; 10855 sector_end_addr = 10856 ((gfpreg >> 16) & ICH_GFPREG_BASE_MASK) + 1; 10857 10858 /* 10859 * find total size of the NVM, then cut in half since the total 10860 * size represents two separate NVM banks. 10861 */ 10862 bank_size = (sector_end_addr - sector_base_addr) 10863 << ICH_FLASH_SECT_ADDR_SHIFT; 10864 bank_size /= 2; 10865 /* Word align */ 10866 bank_size = 10867 (bank_size / sizeof(uint16_t)) * sizeof(uint16_t); 10868 10869 sub_sector_size = ICH_FLASH_SEG_SIZE_8K; 10870 iteration = bank_size / ICH_FLASH_SEG_SIZE_8K; 10871 } else { 10872 return error; 10873 } 10874 } else if (hsfsts.hsf_status.berasesz == 0x3) { 10875 bank_size = ICH_FLASH_SEG_SIZE_64K; 10876 iteration = 1; 10877 } else { 10878 return error; 10879 } 10880 10881 for (j = 0; j < iteration; j++) { 10882 do { 10883 count++; 10884 /* Steps */ 10885 error = em_ich8_cycle_init(hw); 10886 if (error != E1000_SUCCESS) { 10887 error_flag = 1; 10888 break; 10889 } 10890 /* 10891 * Write a value 11 (block Erase) in Flash Cycle 10892 * field in Hw flash Control 10893 */ 10894 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, 10895 ICH_FLASH_HSFCTL); 10896 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE; 10897 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, 10898 hsflctl.regval); 10899 /* 10900 * Write the last 24 bits of an index within the 10901 * block into Flash Linear address field in Flash 10902 * Address. This probably needs to be calculated 10903 * here based off the on-chip erase sector size and 10904 * the software bank size (4, 8 or 64 KBytes) 10905 */ 10906 flash_linear_address = 10907 bank * bank_size + j * sub_sector_size; 10908 flash_linear_address += hw->flash_base_addr; 10909 flash_linear_address &= ICH_FLASH_LINEAR_ADDR_MASK; 10910 10911 E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_FADDR, 10912 flash_linear_address); 10913 10914 error = 10915 em_ich8_flash_cycle(hw, ICH_FLASH_ERASE_TIMEOUT); 10916 /* 10917 * Check if FCERR is set to 1. If 1, clear it and 10918 * try the whole sequence a few more times else Done 10919 */ 10920 if (error == E1000_SUCCESS) { 10921 break; 10922 } else { 10923 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, 10924 ICH_FLASH_HSFSTS); 10925 if (hsfsts.hsf_status.flcerr == 1) { 10926 /* 10927 * repeat for some time before giving 10928 * up 10929 */ 10930 continue; 10931 } else if (hsfsts.hsf_status.flcdone == 0) { 10932 error_flag = 1; 10933 break; 10934 } 10935 } 10936 } while ((count < ICH_FLASH_CYCLE_REPEAT_COUNT) && !error_flag); 10937 if (error_flag == 1) 10938 break; 10939 } 10940 if (error_flag != 1) 10941 error = E1000_SUCCESS; 10942 return error; 10943 } 10944 10945 /****************************************************************************** 10946 * Reads 16-bit words from the OTP. Return error when the word is not 10947 * stored in OTP. 10948 * 10949 * hw - Struct containing variables accessed by shared code 10950 * offset - offset of word in the OTP to read 10951 * data - word read from the OTP 10952 * words - number of words to read 10953 *****************************************************************************/ 10954 STATIC int32_t 10955 em_read_invm_i210(struct em_hw *hw, uint16_t offset, uint16_t words, 10956 uint16_t *data) 10957 { 10958 int32_t ret_val = E1000_SUCCESS; 10959 10960 switch (offset) 10961 { 10962 case EEPROM_MAC_ADDR_WORD0: 10963 case EEPROM_MAC_ADDR_WORD1: 10964 case EEPROM_MAC_ADDR_WORD2: 10965 /* Generate random MAC address if there's none. */ 10966 ret_val = em_read_invm_word_i210(hw, offset, data); 10967 if (ret_val != E1000_SUCCESS) { 10968 DEBUGOUT("MAC Addr not found in iNVM\n"); 10969 *data = 0xFFFF; 10970 ret_val = E1000_SUCCESS; 10971 } 10972 break; 10973 case EEPROM_INIT_CONTROL2_REG: 10974 ret_val = em_read_invm_word_i210(hw, offset, data); 10975 if (ret_val != E1000_SUCCESS) { 10976 *data = NVM_INIT_CTRL_2_DEFAULT_I211; 10977 ret_val = E1000_SUCCESS; 10978 } 10979 break; 10980 case EEPROM_INIT_CONTROL4_REG: 10981 ret_val = em_read_invm_word_i210(hw, offset, data); 10982 if (ret_val != E1000_SUCCESS) { 10983 *data = NVM_INIT_CTRL_4_DEFAULT_I211; 10984 ret_val = E1000_SUCCESS; 10985 } 10986 break; 10987 case EEPROM_LED_1_CFG: 10988 ret_val = em_read_invm_word_i210(hw, offset, data); 10989 if (ret_val != E1000_SUCCESS) { 10990 *data = NVM_LED_1_CFG_DEFAULT_I211; 10991 ret_val = E1000_SUCCESS; 10992 } 10993 break; 10994 case EEPROM_LED_0_2_CFG: 10995 ret_val = em_read_invm_word_i210(hw, offset, data); 10996 if (ret_val != E1000_SUCCESS) { 10997 *data = NVM_LED_0_2_CFG_DEFAULT_I211; 10998 ret_val = E1000_SUCCESS; 10999 } 11000 break; 11001 case EEPROM_ID_LED_SETTINGS: 11002 ret_val = em_read_invm_word_i210(hw, offset, data); 11003 if (ret_val != E1000_SUCCESS) { 11004 *data = ID_LED_RESERVED_FFFF; 11005 ret_val = E1000_SUCCESS; 11006 } 11007 break; 11008 default: 11009 DEBUGOUT1("NVM word 0x%02x is not mapped.\n", offset); 11010 *data = NVM_RESERVED_WORD; 11011 break; 11012 } 11013 11014 return ret_val; 11015 } 11016 11017 /****************************************************************************** 11018 * Reads 16-bit words from the OTP. Return error when the word is not 11019 * stored in OTP. 11020 * 11021 * hw - Struct containing variables accessed by shared code 11022 * offset - offset of word in the OTP to read 11023 * data - word read from the OTP 11024 *****************************************************************************/ 11025 STATIC int32_t 11026 em_read_invm_word_i210(struct em_hw *hw, uint16_t address, uint16_t *data) 11027 { 11028 int32_t error = -E1000_NOT_IMPLEMENTED; 11029 uint32_t invm_dword; 11030 uint16_t i; 11031 uint8_t record_type, word_address; 11032 11033 for (i = 0; i < INVM_SIZE; i++) { 11034 invm_dword = EM_READ_REG(hw, E1000_INVM_DATA_REG(i)); 11035 /* Get record type */ 11036 record_type = INVM_DWORD_TO_RECORD_TYPE(invm_dword); 11037 if (record_type == INVM_UNINITIALIZED_STRUCTURE) 11038 break; 11039 if (record_type == INVM_CSR_AUTOLOAD_STRUCTURE) 11040 i += INVM_CSR_AUTOLOAD_DATA_SIZE_IN_DWORDS; 11041 if (record_type == INVM_RSA_KEY_SHA256_STRUCTURE) 11042 i += INVM_RSA_KEY_SHA256_DATA_SIZE_IN_DWORDS; 11043 if (record_type == INVM_WORD_AUTOLOAD_STRUCTURE) { 11044 word_address = INVM_DWORD_TO_WORD_ADDRESS(invm_dword); 11045 if (word_address == address) { 11046 *data = INVM_DWORD_TO_WORD_DATA(invm_dword); 11047 error = E1000_SUCCESS; 11048 break; 11049 } 11050 } 11051 } 11052 11053 return error; 11054 } 11055 11056 STATIC int32_t 11057 em_init_lcd_from_nvm_config_region(struct em_hw *hw, uint32_t cnf_base_addr, 11058 uint32_t cnf_size) 11059 { 11060 uint32_t ret_val = E1000_SUCCESS; 11061 uint16_t word_addr, reg_data, reg_addr; 11062 uint16_t i; 11063 /* cnf_base_addr is in DWORD */ 11064 word_addr = (uint16_t) (cnf_base_addr << 1); 11065 11066 /* cnf_size is returned in size of dwords */ 11067 for (i = 0; i < cnf_size; i++) { 11068 ret_val = 11069 em_read_eeprom(hw, (word_addr + i * 2), 1, ®_data); 11070 if (ret_val) 11071 return ret_val; 11072 11073 ret_val = 11074 em_read_eeprom(hw, (word_addr + i * 2 + 1), 1, ®_addr); 11075 if (ret_val) 11076 return ret_val; 11077 11078 ret_val = em_get_software_flag(hw); 11079 if (ret_val != E1000_SUCCESS) 11080 return ret_val; 11081 11082 ret_val = 11083 em_write_phy_reg_ex(hw, (uint32_t) reg_addr, reg_data); 11084 11085 em_release_software_flag(hw); 11086 } 11087 11088 return ret_val; 11089 } 11090 11091 /****************************************************************************** 11092 * This function initializes the PHY from the NVM on ICH8 platforms. This 11093 * is needed due to an issue where the NVM configuration is not properly 11094 * autoloaded after power transitions. Therefore, after each PHY reset, we 11095 * will load the configuration data out of the NVM manually. 11096 * 11097 * hw: Struct containing variables accessed by shared code 11098 *****************************************************************************/ 11099 STATIC int32_t 11100 em_init_lcd_from_nvm(struct em_hw *hw) 11101 { 11102 uint32_t reg_data, cnf_base_addr, cnf_size, ret_val, loop, sw_cfg_mask; 11103 if (hw->phy_type != em_phy_igp_3) 11104 return E1000_SUCCESS; 11105 11106 /* Check if SW needs configure the PHY */ 11107 if (hw->device_id == E1000_DEV_ID_ICH8_IGP_M_AMT || 11108 hw->device_id == E1000_DEV_ID_ICH8_IGP_M || 11109 hw->mac_type == em_pchlan || 11110 hw->mac_type == em_pch2lan || 11111 hw->mac_type == em_pch_lpt || 11112 hw->mac_type == em_pch_spt || 11113 hw->mac_type == em_pch_cnp) 11114 sw_cfg_mask = FEXTNVM_SW_CONFIG_ICH8M; 11115 else 11116 sw_cfg_mask = FEXTNVM_SW_CONFIG; 11117 11118 reg_data = E1000_READ_REG(hw, FEXTNVM); 11119 if (!(reg_data & sw_cfg_mask)) 11120 return E1000_SUCCESS; 11121 11122 /* Wait for basic configuration completes before proceeding */ 11123 loop = 0; 11124 do { 11125 reg_data = 11126 E1000_READ_REG(hw, STATUS) & E1000_STATUS_LAN_INIT_DONE; 11127 usec_delay(100); 11128 loop++; 11129 } while ((!reg_data) && (loop < 50)); 11130 11131 /* Clear the Init Done bit for the next init event */ 11132 reg_data = E1000_READ_REG(hw, STATUS); 11133 reg_data &= ~E1000_STATUS_LAN_INIT_DONE; 11134 E1000_WRITE_REG(hw, STATUS, reg_data); 11135 /* 11136 * Make sure HW does not configure LCD from PHY extended 11137 * configuration before SW configuration 11138 */ 11139 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL); 11140 if ((reg_data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) == 0x0000) { 11141 reg_data = E1000_READ_REG(hw, EXTCNF_SIZE); 11142 cnf_size = reg_data & E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH; 11143 cnf_size >>= 16; 11144 if (cnf_size) { 11145 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL); 11146 cnf_base_addr = reg_data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER; 11147 /* cnf_base_addr is in DWORD */ 11148 cnf_base_addr >>= 16; 11149 11150 /* Configure LCD from extended configuration region. */ 11151 ret_val = em_init_lcd_from_nvm_config_region(hw, 11152 cnf_base_addr, cnf_size); 11153 if (ret_val) 11154 return ret_val; 11155 } 11156 } 11157 return E1000_SUCCESS; 11158 } 11159 11160 /****************************************************************************** 11161 * em_set_pciex_completion_timeout - set pci-e completion timeout 11162 * 11163 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms, 11164 * however the hardware default for these parts is 500us to 1ms which is less 11165 * than the 10ms recommended by the pci-e spec. To address this we need to 11166 * increase the value to either 10ms to 200ms for capability version 1 config, 11167 * or 16ms to 55ms for version 2. 11168 * 11169 * * hw - pointer to em_hw structure 11170 *****************************************************************************/ 11171 int32_t 11172 em_set_pciex_completion_timeout(struct em_hw *hw) 11173 { 11174 uint32_t gcr = E1000_READ_REG(hw, GCR); 11175 int32_t ret_val = E1000_SUCCESS; 11176 11177 /* Only take action if timeout value is not set by system BIOS */ 11178 if (gcr & E1000_GCR_CMPL_TMOUT_MASK) 11179 goto out; 11180 11181 DEBUGOUT("PCIe completion timeout not set by system BIOS."); 11182 11183 /* 11184 * If capabilities version is type 1 we can write the 11185 * timeout of 10ms to 200ms through the GCR register 11186 */ 11187 11188 if (!(gcr & E1000_GCR_CAP_VER2)) { 11189 gcr |= E1000_GCR_CMPL_TMOUT_10ms; 11190 DEBUGOUT("PCIe capability version 1 detected, setting \ 11191 completion timeout to 10ms."); 11192 goto out; 11193 } 11194 11195 /* 11196 * For version 2 capabilities we need to write the config space 11197 * directly in order to set the completion timeout value for 11198 * 16ms to 55ms 11199 * 11200 * XXX: Implement em_*_pcie_cap_reg() first. 11201 */ 11202 #if 0 11203 ret_val = em_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 11204 &pciex_devctl2); 11205 11206 if (ret_val) 11207 goto out; 11208 11209 pciex_devctl2 |= PCIE_DEVICE_CONTROL2_16ms; 11210 11211 ret_val = em_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 11212 &pciex_devctl2); 11213 #endif 11214 11215 out: 11216 11217 /* Disable completion timeout resend */ 11218 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND; 11219 11220 DEBUGOUT("PCIe completion timeout resend disabled."); 11221 11222 E1000_WRITE_REG(hw, GCR, gcr); 11223 return ret_val; 11224 } 11225 11226 /*************************************************************************** 11227 * Set slow MDIO access mode 11228 ***************************************************************************/ 11229 static int32_t 11230 em_set_mdio_slow_mode_hv(struct em_hw *hw) 11231 { 11232 int32_t ret_val; 11233 uint16_t data; 11234 DEBUGFUNC("em_set_mdio_slow_mode_hv"); 11235 11236 ret_val = em_read_phy_reg(hw, HV_KMRN_MODE_CTRL, &data); 11237 if (ret_val) 11238 return ret_val; 11239 11240 data |= HV_KMRN_MDIO_SLOW; 11241 11242 ret_val = em_write_phy_reg(hw, HV_KMRN_MODE_CTRL, data); 11243 11244 return ret_val; 11245 } 11246 11247 /*************************************************************************** 11248 * A series of Phy workarounds to be done after every PHY reset. 11249 ***************************************************************************/ 11250 int32_t 11251 em_hv_phy_workarounds_ich8lan(struct em_hw *hw) 11252 { 11253 int32_t ret_val = E1000_SUCCESS; 11254 uint16_t phy_data; 11255 uint16_t swfw; 11256 DEBUGFUNC("em_hv_phy_workarounds_ich8lan"); 11257 11258 if (hw->mac_type != em_pchlan) 11259 goto out; 11260 11261 swfw = E1000_SWFW_PHY0_SM; 11262 11263 /* Set MDIO slow mode before any other MDIO access */ 11264 if (hw->phy_type == em_phy_82577 || 11265 hw->phy_type == em_phy_82578) { 11266 ret_val = em_set_mdio_slow_mode_hv(hw); 11267 if (ret_val) 11268 goto out; 11269 } 11270 11271 /* Hanksville M Phy init for IEEE. */ 11272 if ((hw->revision_id == 2) && 11273 (hw->phy_type == em_phy_82577) && 11274 ((hw->phy_revision == 2) || (hw->phy_revision == 3))) { 11275 em_write_phy_reg(hw, 0x10, 0x8823); 11276 em_write_phy_reg(hw, 0x11, 0x0018); 11277 em_write_phy_reg(hw, 0x10, 0x8824); 11278 em_write_phy_reg(hw, 0x11, 0x0016); 11279 em_write_phy_reg(hw, 0x10, 0x8825); 11280 em_write_phy_reg(hw, 0x11, 0x001A); 11281 em_write_phy_reg(hw, 0x10, 0x888C); 11282 em_write_phy_reg(hw, 0x11, 0x0007); 11283 em_write_phy_reg(hw, 0x10, 0x888D); 11284 em_write_phy_reg(hw, 0x11, 0x0007); 11285 em_write_phy_reg(hw, 0x10, 0x888E); 11286 em_write_phy_reg(hw, 0x11, 0x0007); 11287 em_write_phy_reg(hw, 0x10, 0x8827); 11288 em_write_phy_reg(hw, 0x11, 0x0001); 11289 em_write_phy_reg(hw, 0x10, 0x8835); 11290 em_write_phy_reg(hw, 0x11, 0x0001); 11291 em_write_phy_reg(hw, 0x10, 0x8834); 11292 em_write_phy_reg(hw, 0x11, 0x0001); 11293 em_write_phy_reg(hw, 0x10, 0x8833); 11294 em_write_phy_reg(hw, 0x11, 0x0002); 11295 } 11296 11297 if (((hw->phy_type == em_phy_82577) && 11298 ((hw->phy_revision == 1) || (hw->phy_revision == 2))) || 11299 ((hw->phy_type == em_phy_82578) && (hw->phy_revision == 1))) { 11300 /* Disable generation of early preamble */ 11301 ret_val = em_write_phy_reg(hw, PHY_REG(769, 25), 0x4431); 11302 if (ret_val) 11303 goto out; 11304 11305 /* Preamble tuning for SSC */ 11306 ret_val = em_write_phy_reg(hw, PHY_REG(770, 16), 0xA204); 11307 if (ret_val) 11308 goto out; 11309 } 11310 11311 if (hw->phy_type == em_phy_82578) { 11312 /* 11313 * Return registers to default by doing a soft reset then 11314 * writing 0x3140 to the control register. 11315 */ 11316 if (hw->phy_revision < 2) { 11317 em_phy_reset(hw); 11318 ret_val = em_write_phy_reg(hw, PHY_CTRL, 0x3140); 11319 } 11320 } 11321 11322 if ((hw->revision_id == 2) && 11323 (hw->phy_type == em_phy_82577) && 11324 ((hw->phy_revision == 2) || (hw->phy_revision == 3))) { 11325 /* 11326 * Workaround for OEM (GbE) not operating after reset - 11327 * restart AN (twice) 11328 */ 11329 ret_val = em_write_phy_reg(hw, PHY_REG(0, 25), 0x0400); 11330 if (ret_val) 11331 goto out; 11332 ret_val = em_write_phy_reg(hw, PHY_REG(0, 25), 0x0400); 11333 if (ret_val) 11334 goto out; 11335 } 11336 11337 /* Select page 0 */ 11338 ret_val = em_swfw_sync_acquire(hw, swfw); 11339 if (ret_val) 11340 goto out; 11341 11342 hw->phy_addr = 1; 11343 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT, 0); 11344 em_swfw_sync_release(hw, swfw); 11345 if (ret_val) 11346 goto out; 11347 11348 /* Workaround for link disconnects on a busy hub in half duplex */ 11349 ret_val = em_read_phy_reg(hw, 11350 PHY_REG(BM_PORT_CTRL_PAGE, 17), 11351 &phy_data); 11352 if (ret_val) 11353 goto release; 11354 ret_val = em_write_phy_reg(hw, 11355 PHY_REG(BM_PORT_CTRL_PAGE, 17), 11356 phy_data & 0x00FF); 11357 release: 11358 out: 11359 return ret_val; 11360 } 11361 11362 11363 /*************************************************************************** 11364 * Si workaround 11365 * 11366 * This function works around a Si bug where the link partner can get 11367 * a link up indication before the PHY does. If small packets are sent 11368 * by the link partner they can be placed in the packet buffer without 11369 * being properly accounted for by the PHY and will stall preventing 11370 * further packets from being received. The workaround is to clear the 11371 * packet buffer after the PHY detects link up. 11372 ***************************************************************************/ 11373 int32_t 11374 em_link_stall_workaround_hv(struct em_hw *hw) 11375 { 11376 int32_t ret_val = E1000_SUCCESS; 11377 uint16_t phy_data; 11378 11379 if (hw->phy_type != em_phy_82578) 11380 goto out; 11381 11382 /* Do not apply workaround if in PHY loopback bit 14 set */ 11383 em_read_phy_reg(hw, PHY_CTRL, &phy_data); 11384 if (phy_data & E1000_PHY_CTRL_LOOPBACK) 11385 goto out; 11386 11387 /* check if link is up and at 1Gbps */ 11388 ret_val = em_read_phy_reg(hw, BM_CS_STATUS, &phy_data); 11389 if (ret_val) 11390 goto out; 11391 11392 phy_data &= BM_CS_STATUS_LINK_UP | 11393 BM_CS_STATUS_RESOLVED | 11394 BM_CS_STATUS_SPEED_MASK; 11395 11396 if (phy_data != (BM_CS_STATUS_LINK_UP | 11397 BM_CS_STATUS_RESOLVED | 11398 BM_CS_STATUS_SPEED_1000)) 11399 goto out; 11400 11401 msec_delay(200); 11402 11403 /* flush the packets in the fifo buffer */ 11404 ret_val = em_write_phy_reg(hw, HV_MUX_DATA_CTRL, 11405 HV_MUX_DATA_CTRL_GEN_TO_MAC | HV_MUX_DATA_CTRL_FORCE_SPEED); 11406 if (ret_val) 11407 goto out; 11408 11409 ret_val = em_write_phy_reg(hw, HV_MUX_DATA_CTRL, 11410 HV_MUX_DATA_CTRL_GEN_TO_MAC); 11411 11412 out: 11413 return ret_val; 11414 } 11415 11416 /**************************************************************************** 11417 * K1 Si workaround 11418 * 11419 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning 11420 * from a lower speed. This workaround disables K1 whenever link is at 1Gig. 11421 * If link is down, the function will restore the default K1 setting located 11422 * in the NVM. 11423 ****************************************************************************/ 11424 int32_t 11425 em_k1_gig_workaround_hv(struct em_hw *hw, boolean_t link) 11426 { 11427 int32_t ret_val; 11428 uint16_t phy_data; 11429 boolean_t k1_enable; 11430 11431 DEBUGFUNC("em_k1_gig_workaround_hv"); 11432 11433 if (hw->mac_type != em_pchlan) 11434 return E1000_SUCCESS; 11435 11436 ret_val = em_read_eeprom_ich8(hw, E1000_NVM_K1_CONFIG, 1, &phy_data); 11437 if (ret_val) 11438 return ret_val; 11439 11440 k1_enable = phy_data & E1000_NVM_K1_ENABLE ? TRUE : FALSE; 11441 11442 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */ 11443 if (link) { 11444 if (hw->phy_type == em_phy_82578) { 11445 ret_val = em_read_phy_reg(hw, BM_CS_STATUS, 11446 &phy_data); 11447 if (ret_val) 11448 return ret_val; 11449 11450 phy_data &= BM_CS_STATUS_LINK_UP | 11451 BM_CS_STATUS_RESOLVED | 11452 BM_CS_STATUS_SPEED_MASK; 11453 11454 if (phy_data == (BM_CS_STATUS_LINK_UP | 11455 BM_CS_STATUS_RESOLVED | 11456 BM_CS_STATUS_SPEED_1000)) 11457 k1_enable = FALSE; 11458 } 11459 11460 if (hw->phy_type == em_phy_82577) { 11461 ret_val = em_read_phy_reg(hw, HV_M_STATUS, 11462 &phy_data); 11463 if (ret_val) 11464 return ret_val; 11465 11466 phy_data &= HV_M_STATUS_LINK_UP | 11467 HV_M_STATUS_AUTONEG_COMPLETE | 11468 HV_M_STATUS_SPEED_MASK; 11469 11470 if (phy_data == (HV_M_STATUS_LINK_UP | 11471 HV_M_STATUS_AUTONEG_COMPLETE | 11472 HV_M_STATUS_SPEED_1000)) 11473 k1_enable = FALSE; 11474 } 11475 11476 /* Link stall fix for link up */ 11477 ret_val = em_write_phy_reg(hw, PHY_REG(770, 19), 11478 0x0100); 11479 if (ret_val) 11480 return ret_val; 11481 11482 } else { 11483 /* Link stall fix for link down */ 11484 ret_val = em_write_phy_reg(hw, PHY_REG(770, 19), 11485 0x4100); 11486 if (ret_val) 11487 return ret_val; 11488 } 11489 11490 ret_val = em_configure_k1_ich8lan(hw, k1_enable); 11491 11492 return ret_val; 11493 } 11494 11495 /* Workaround to set the K1 beacon duration for 82579 parts */ 11496 int32_t 11497 em_k1_workaround_lv(struct em_hw *hw) 11498 { 11499 int32_t ret_val; 11500 uint16_t phy_data; 11501 uint32_t mac_reg; 11502 11503 ret_val = em_read_phy_reg(hw, BM_CS_STATUS, &phy_data); 11504 if (ret_val) 11505 return ret_val; 11506 11507 if ((phy_data & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) 11508 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) { 11509 mac_reg = E1000_READ_REG(hw, FEXTNVM4); 11510 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK; 11511 11512 if (phy_data & HV_M_STATUS_SPEED_1000) 11513 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC; 11514 else 11515 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC; 11516 11517 E1000_WRITE_REG(hw, FEXTNVM4, mac_reg); 11518 } 11519 11520 return E1000_SUCCESS; 11521 } 11522 11523 /** 11524 * em_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP 11525 * 11526 * When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications 11527 * preventing further DMA write requests. Workaround the issue by disabling 11528 * the de-assertion of the clock request when in 1Gbps mode. 11529 * Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link 11530 * speeds in order to avoid Tx hangs. 11531 **/ 11532 int32_t 11533 em_k1_workaround_lpt_lp(struct em_hw *hw, boolean_t link) 11534 { 11535 uint32_t fextnvm6 = E1000_READ_REG(hw, FEXTNVM6); 11536 uint32_t status = E1000_READ_REG(hw, STATUS); 11537 int32_t ret_val = E1000_SUCCESS; 11538 uint16_t reg; 11539 11540 if (link && (status & E1000_STATUS_SPEED_1000)) { 11541 ret_val = em_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 11542 ®); 11543 if (ret_val) 11544 return ret_val; 11545 11546 ret_val = em_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 11547 reg & ~E1000_KMRNCTRLSTA_K1_ENABLE); 11548 if (ret_val) 11549 return ret_val; 11550 11551 usec_delay(10); 11552 11553 E1000_WRITE_REG(hw, FEXTNVM6, 11554 fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK); 11555 11556 ret_val = em_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 11557 reg); 11558 } else { 11559 /* clear FEXTNVM6 bit 8 on link down or 10/100 */ 11560 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK; 11561 11562 if (!link || ((status & E1000_STATUS_SPEED_100) && 11563 (status & E1000_STATUS_FD))) 11564 goto update_fextnvm6; 11565 11566 ret_val = em_read_phy_reg(hw, I217_INBAND_CTRL, ®); 11567 if (ret_val) 11568 return ret_val; 11569 11570 /* Clear link status transmit timeout */ 11571 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK; 11572 11573 if (status & E1000_STATUS_SPEED_100) { 11574 /* Set inband Tx timeout to 5x10us for 100Half */ 11575 reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT; 11576 11577 /* Do not extend the K1 entry latency for 100Half */ 11578 fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION; 11579 } else { 11580 /* Set inband Tx timeout to 50x10us for 10Full/Half */ 11581 reg |= 50 << 11582 I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT; 11583 11584 /* Extend the K1 entry latency for 10 Mbps */ 11585 fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION; 11586 } 11587 11588 ret_val = em_write_phy_reg(hw, I217_INBAND_CTRL, reg); 11589 if (ret_val) 11590 return ret_val; 11591 11592 update_fextnvm6: 11593 E1000_WRITE_REG(hw, FEXTNVM6, fextnvm6); 11594 } 11595 11596 return ret_val; 11597 11598 } 11599 11600 11601 /*************************************************************************** 11602 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware 11603 * @hw: pointer to the HW structure 11604 * @gate: boolean set to TRUE to gate, FALSE to ungate 11605 * 11606 * Gate/ungate the automatic PHY configuration via hardware; perform 11607 * the configuration via software instead. 11608 ***************************************************************************/ 11609 void 11610 em_gate_hw_phy_config_ich8lan(struct em_hw *hw, boolean_t gate) 11611 { 11612 uint32_t extcnf_ctrl; 11613 11614 DEBUGFUNC("em_gate_hw_phy_config_ich8lan"); 11615 11616 if (hw->mac_type != em_pch2lan) 11617 return; 11618 11619 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 11620 11621 if (gate) 11622 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG; 11623 else 11624 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG; 11625 11626 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); 11627 } 11628 11629 /*************************************************************************** 11630 * Configure K1 power state 11631 * 11632 * Configure the K1 power state based on the provided parameter. 11633 * Assumes semaphore already acquired. 11634 * 11635 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 11636 ***************************************************************************/ 11637 int32_t 11638 em_configure_k1_ich8lan(struct em_hw *hw, boolean_t k1_enable) 11639 { 11640 int32_t ret_val = E1000_SUCCESS; 11641 uint32_t ctrl_reg = 0; 11642 uint32_t ctrl_ext = 0; 11643 uint32_t reg = 0; 11644 uint16_t kmrn_reg = 0; 11645 11646 ret_val = em_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 11647 &kmrn_reg); 11648 if (ret_val) 11649 goto out; 11650 11651 if (k1_enable) 11652 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE; 11653 else 11654 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE; 11655 11656 ret_val = em_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 11657 kmrn_reg); 11658 if (ret_val) 11659 goto out; 11660 11661 usec_delay(20); 11662 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 11663 ctrl_reg = E1000_READ_REG(hw, CTRL); 11664 11665 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 11666 reg |= E1000_CTRL_FRCSPD; 11667 E1000_WRITE_REG(hw, CTRL, reg); 11668 11669 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS); 11670 usec_delay(20); 11671 E1000_WRITE_REG(hw, CTRL, ctrl_reg); 11672 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 11673 usec_delay(20); 11674 11675 out: 11676 return ret_val; 11677 } 11678 11679 /*************************************************************************** 11680 * em_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be 11681 * done after every PHY reset. 11682 ***************************************************************************/ 11683 int32_t 11684 em_lv_phy_workarounds_ich8lan(struct em_hw *hw) 11685 { 11686 int32_t ret_val = E1000_SUCCESS; 11687 uint16_t swfw; 11688 11689 DEBUGFUNC("e1000_lv_phy_workarounds_ich8lan"); 11690 11691 if (hw->mac_type != em_pch2lan) 11692 goto out; 11693 11694 /* Set MDIO slow mode before any other MDIO access */ 11695 ret_val = em_set_mdio_slow_mode_hv(hw); 11696 11697 swfw = E1000_SWFW_PHY0_SM; 11698 ret_val = em_swfw_sync_acquire(hw, swfw); 11699 if (ret_val) 11700 goto out; 11701 ret_val = em_write_phy_reg(hw, I82579_EMI_ADDR, 11702 I82579_MSE_THRESHOLD); 11703 if (ret_val) 11704 goto release; 11705 /* set MSE higher to enable link to stay up when noise is high */ 11706 ret_val = em_write_phy_reg(hw, I82579_EMI_DATA, 11707 0x0034); 11708 if (ret_val) 11709 goto release; 11710 ret_val = em_write_phy_reg(hw, I82579_EMI_ADDR, 11711 I82579_MSE_LINK_DOWN); 11712 if (ret_val) 11713 goto release; 11714 /* drop link after 5 times MSE threshold was reached */ 11715 ret_val = em_write_phy_reg(hw, I82579_EMI_DATA, 11716 0x0005); 11717 release: 11718 em_swfw_sync_release(hw, swfw); 11719 11720 out: 11721 return ret_val; 11722 } 11723 11724 int32_t 11725 em_set_eee_i350(struct em_hw *hw) 11726 { 11727 int32_t ret_val = E1000_SUCCESS; 11728 uint32_t ipcnfg, eeer; 11729 11730 if ((hw->mac_type < em_i350) || 11731 (hw->media_type != em_media_type_copper)) 11732 goto out; 11733 ipcnfg = EM_READ_REG(hw, E1000_IPCNFG); 11734 eeer = EM_READ_REG(hw, E1000_EEER); 11735 11736 if (hw->eee_enable) { 11737 ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN); 11738 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN | 11739 E1000_EEER_LPI_FC); 11740 } else { 11741 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN); 11742 eeer &= ~(E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN | 11743 E1000_EEER_LPI_FC); 11744 } 11745 EM_WRITE_REG(hw, E1000_IPCNFG, ipcnfg); 11746 EM_WRITE_REG(hw, E1000_EEER, eeer); 11747 EM_READ_REG(hw, E1000_IPCNFG); 11748 EM_READ_REG(hw, E1000_EEER); 11749 out: 11750 return ret_val; 11751 } 11752 11753 /*************************************************************************** 11754 * em_set_eee_pchlan - Enable/disable EEE support 11755 * @hw: pointer to the HW structure 11756 * 11757 * Enable/disable EEE based on setting in dev_spec structure. The bits in 11758 * the LPI Control register will remain set only if/when link is up. 11759 ***************************************************************************/ 11760 int32_t 11761 em_set_eee_pchlan(struct em_hw *hw) 11762 { 11763 int32_t ret_val = E1000_SUCCESS; 11764 uint16_t phy_reg; 11765 11766 DEBUGFUNC("em_set_eee_pchlan"); 11767 11768 if (hw->phy_type != em_phy_82579 && 11769 hw->phy_type != em_phy_i217) 11770 goto out; 11771 11772 ret_val = em_read_phy_reg(hw, I82579_LPI_CTRL, &phy_reg); 11773 if (ret_val) 11774 goto out; 11775 11776 if (hw->eee_enable) 11777 phy_reg &= ~I82579_LPI_CTRL_ENABLE_MASK; 11778 else 11779 phy_reg |= I82579_LPI_CTRL_ENABLE_MASK; 11780 11781 ret_val = em_write_phy_reg(hw, I82579_LPI_CTRL, phy_reg); 11782 out: 11783 return ret_val; 11784 } 11785 11786 /** 11787 * em_initialize_M88E1512_phy - Initialize M88E1512 PHY 11788 * @hw: pointer to the HW structure 11789 * 11790 * Initialize Marvell 1512 to work correctly with Avoton. 11791 **/ 11792 int32_t 11793 em_initialize_M88E1512_phy(struct em_hw *hw) 11794 { 11795 int32_t ret_val = E1000_SUCCESS; 11796 11797 DEBUGFUNC("e1000_initialize_M88E1512_phy"); 11798 11799 /* Check if this is correct PHY. */ 11800 if (hw->phy_id != M88E1512_E_PHY_ID) 11801 goto out; 11802 11803 /* Switch to PHY page 0xFF. */ 11804 ret_val = em_write_phy_reg(hw, M88E1543_PAGE_ADDR, 0x00FF); 11805 if (ret_val) 11806 goto out; 11807 11808 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_2, 0x214B); 11809 if (ret_val) 11810 goto out; 11811 11812 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_1, 0x2144); 11813 if (ret_val) 11814 goto out; 11815 11816 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_2, 0x0C28); 11817 if (ret_val) 11818 goto out; 11819 11820 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_1, 0x2146); 11821 if (ret_val) 11822 goto out; 11823 11824 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_2, 0xB233); 11825 if (ret_val) 11826 goto out; 11827 11828 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_1, 0x214D); 11829 if (ret_val) 11830 goto out; 11831 11832 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_2, 0xCC0C); 11833 if (ret_val) 11834 goto out; 11835 11836 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_1, 0x2159); 11837 if (ret_val) 11838 goto out; 11839 11840 /* Switch to PHY page 0xFB. */ 11841 ret_val = em_write_phy_reg(hw, M88E1543_PAGE_ADDR, 0x00FB); 11842 if (ret_val) 11843 goto out; 11844 11845 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_3, 0x000D); 11846 if (ret_val) 11847 goto out; 11848 11849 /* Switch to PHY page 0x12. */ 11850 ret_val = em_write_phy_reg(hw, M88E1543_PAGE_ADDR, 0x12); 11851 if (ret_val) 11852 goto out; 11853 11854 /* Change mode to SGMII-to-Copper */ 11855 ret_val = em_write_phy_reg(hw, M88E1512_MODE, 0x8001); 11856 if (ret_val) 11857 goto out; 11858 11859 /* Return the PHY to page 0. */ 11860 ret_val = em_write_phy_reg(hw, M88E1543_PAGE_ADDR, 0); 11861 if (ret_val) 11862 goto out; 11863 11864 ret_val = em_phy_hw_reset(hw); 11865 if (ret_val) { 11866 DEBUGOUT("Error committing the PHY changes\n"); 11867 return ret_val; 11868 } 11869 11870 msec_delay(1000); 11871 out: 11872 return ret_val; 11873 } 11874 11875 uint32_t 11876 em_translate_82542_register(uint32_t reg) 11877 { 11878 /* 11879 * Some of the 82542 registers are located at different 11880 * offsets than they are in newer adapters. 11881 * Despite the difference in location, the registers 11882 * function in the same manner. 11883 */ 11884 switch (reg) { 11885 case E1000_RA: 11886 reg = 0x00040; 11887 break; 11888 case E1000_RDTR: 11889 reg = 0x00108; 11890 break; 11891 case E1000_RDBAL(0): 11892 reg = 0x00110; 11893 break; 11894 case E1000_RDBAH(0): 11895 reg = 0x00114; 11896 break; 11897 case E1000_RDLEN(0): 11898 reg = 0x00118; 11899 break; 11900 case E1000_RDH(0): 11901 reg = 0x00120; 11902 break; 11903 case E1000_RDT(0): 11904 reg = 0x00128; 11905 break; 11906 case E1000_RDBAL(1): 11907 reg = 0x00138; 11908 break; 11909 case E1000_RDBAH(1): 11910 reg = 0x0013C; 11911 break; 11912 case E1000_RDLEN(1): 11913 reg = 0x00140; 11914 break; 11915 case E1000_RDH(1): 11916 reg = 0x00148; 11917 break; 11918 case E1000_RDT(1): 11919 reg = 0x00150; 11920 break; 11921 case E1000_FCRTH: 11922 reg = 0x00160; 11923 break; 11924 case E1000_FCRTL: 11925 reg = 0x00168; 11926 break; 11927 case E1000_MTA: 11928 reg = 0x00200; 11929 break; 11930 case E1000_TDBAL(0): 11931 reg = 0x00420; 11932 break; 11933 case E1000_TDBAH(0): 11934 reg = 0x00424; 11935 break; 11936 case E1000_TDLEN(0): 11937 reg = 0x00428; 11938 break; 11939 case E1000_TDH(0): 11940 reg = 0x00430; 11941 break; 11942 case E1000_TDT(0): 11943 reg = 0x00438; 11944 break; 11945 case E1000_TIDV: 11946 reg = 0x00440; 11947 break; 11948 case E1000_VFTA: 11949 reg = 0x00600; 11950 break; 11951 case E1000_TDFH: 11952 reg = 0x08010; 11953 break; 11954 case E1000_TDFT: 11955 reg = 0x08018; 11956 break; 11957 default: 11958 break; 11959 } 11960 11961 return (reg); 11962 } 11963