1 /******************************************************************************* 2 3 Copyright (c) 2001-2005, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 *******************************************************************************/ 33 34 /* $OpenBSD: if_em_hw.c,v 1.31 2008/12/04 02:36:52 brad Exp $ */ 35 36 /* if_em_hw.c 37 * Shared functions for accessing and configuring the MAC 38 */ 39 40 #if 0 41 #include <sys/cdefs.h> 42 __FBSDID("$FreeBSD: if_em_hw.c,v 1.16 2005/05/26 23:32:02 tackerman Exp $"); 43 #endif 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/sockio.h> 48 #include <sys/mbuf.h> 49 #include <sys/malloc.h> 50 #include <sys/kernel.h> 51 #include <sys/device.h> 52 #include <sys/socket.h> 53 54 #include <net/if.h> 55 #include <net/if_dl.h> 56 #include <net/if_media.h> 57 58 #ifdef INET 59 #include <netinet/in.h> 60 #include <netinet/in_systm.h> 61 #include <netinet/in_var.h> 62 #include <netinet/ip.h> 63 #include <netinet/if_ether.h> 64 #endif 65 66 #include <uvm/uvm_extern.h> 67 68 #include <dev/pci/pcireg.h> 69 #include <dev/pci/pcivar.h> 70 #include <dev/pci/pcidevs.h> 71 72 #include <dev/pci/if_em_hw.h> 73 74 #define STATIC 75 76 static int32_t em_swfw_sync_acquire(struct em_hw *hw, uint16_t mask); 77 static void em_swfw_sync_release(struct em_hw *hw, uint16_t mask); 78 static int32_t em_read_kmrn_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t *data); 79 static int32_t em_write_kmrn_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t data); 80 static int32_t em_get_software_semaphore(struct em_hw *hw); 81 static void em_release_software_semaphore(struct em_hw *hw); 82 83 static int32_t em_check_downshift(struct em_hw *hw); 84 static void em_clear_vfta(struct em_hw *hw); 85 static int32_t em_commit_shadow_ram(struct em_hw *hw); 86 static int32_t em_config_dsp_after_link_change(struct em_hw *hw, boolean_t link_up); 87 static int32_t em_config_fc_after_link_up(struct em_hw *hw); 88 static int32_t em_detect_gig_phy(struct em_hw *hw); 89 static int32_t em_erase_ich8_4k_segment(struct em_hw *hw, uint32_t bank); 90 static int32_t em_get_auto_rd_done(struct em_hw *hw); 91 static int32_t em_get_cable_length(struct em_hw *hw, uint16_t *min_length, uint16_t *max_length); 92 static int32_t em_get_hw_eeprom_semaphore(struct em_hw *hw); 93 static int32_t em_get_phy_cfg_done(struct em_hw *hw); 94 static int32_t em_get_software_flag(struct em_hw *hw); 95 static int32_t em_ich8_cycle_init(struct em_hw *hw); 96 static int32_t em_ich8_flash_cycle(struct em_hw *hw, uint32_t timeout); 97 static int32_t em_id_led_init(struct em_hw *hw); 98 static int32_t em_init_lcd_from_nvm_config_region(struct em_hw *hw, uint32_t cnf_base_addr, uint32_t cnf_size); 99 static int32_t em_init_lcd_from_nvm(struct em_hw *hw); 100 static void em_init_rx_addrs(struct em_hw *hw); 101 static void em_initialize_hardware_bits(struct em_hw *hw); 102 static boolean_t em_is_onboard_nvm_eeprom(struct em_hw *hw); 103 static int32_t em_kumeran_lock_loss_workaround(struct em_hw *hw); 104 static int32_t em_mng_enable_host_if(struct em_hw *hw); 105 static int32_t em_read_eeprom_eerd(struct em_hw *hw, uint16_t offset, uint16_t words, uint16_t *data); 106 static int32_t em_write_eeprom_eewr(struct em_hw *hw, uint16_t offset, uint16_t words, uint16_t *data); 107 static int32_t em_poll_eerd_eewr_done(struct em_hw *hw, int eerd); 108 static void em_put_hw_eeprom_semaphore(struct em_hw *hw); 109 static int32_t em_read_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t *data); 110 static int32_t em_verify_write_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t byte); 111 static int32_t em_write_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t byte); 112 static int32_t em_read_ich8_word(struct em_hw *hw, uint32_t index, uint16_t *data); 113 static int32_t em_read_ich8_data(struct em_hw *hw, uint32_t index, uint32_t size, uint16_t *data); 114 static int32_t em_write_ich8_data(struct em_hw *hw, uint32_t index, uint32_t size, uint16_t data); 115 static int32_t em_read_eeprom_ich8(struct em_hw *hw, uint16_t offset, uint16_t words, uint16_t *data); 116 static int32_t em_write_eeprom_ich8(struct em_hw *hw, uint16_t offset, uint16_t words, uint16_t *data); 117 static void em_release_software_flag(struct em_hw *hw); 118 static int32_t em_set_d3_lplu_state(struct em_hw *hw, boolean_t active); 119 static int32_t em_set_d0_lplu_state(struct em_hw *hw, boolean_t active); 120 static int32_t em_set_pci_ex_no_snoop(struct em_hw *hw, uint32_t no_snoop); 121 static void em_set_pci_express_master_disable(struct em_hw *hw); 122 static int32_t em_wait_autoneg(struct em_hw *hw); 123 static void em_write_reg_io(struct em_hw *hw, uint32_t offset, uint32_t value); 124 static int32_t em_set_phy_type(struct em_hw *hw); 125 static void em_phy_init_script(struct em_hw *hw); 126 static int32_t em_setup_copper_link(struct em_hw *hw); 127 static int32_t em_setup_fiber_serdes_link(struct em_hw *hw); 128 static int32_t em_adjust_serdes_amplitude(struct em_hw *hw); 129 static int32_t em_phy_force_speed_duplex(struct em_hw *hw); 130 static int32_t em_config_mac_to_phy(struct em_hw *hw); 131 static void em_raise_mdi_clk(struct em_hw *hw, uint32_t *ctrl); 132 static void em_lower_mdi_clk(struct em_hw *hw, uint32_t *ctrl); 133 static void em_shift_out_mdi_bits(struct em_hw *hw, uint32_t data, 134 uint16_t count); 135 static uint16_t em_shift_in_mdi_bits(struct em_hw *hw); 136 static int32_t em_phy_reset_dsp(struct em_hw *hw); 137 static int32_t em_write_eeprom_spi(struct em_hw *hw, uint16_t offset, 138 uint16_t words, uint16_t *data); 139 static int32_t em_write_eeprom_microwire(struct em_hw *hw, 140 uint16_t offset, uint16_t words, 141 uint16_t *data); 142 static int32_t em_spi_eeprom_ready(struct em_hw *hw); 143 static void em_raise_ee_clk(struct em_hw *hw, uint32_t *eecd); 144 static void em_lower_ee_clk(struct em_hw *hw, uint32_t *eecd); 145 static void em_shift_out_ee_bits(struct em_hw *hw, uint16_t data, 146 uint16_t count); 147 static int32_t em_write_phy_reg_ex(struct em_hw *hw, uint32_t reg_addr, 148 uint16_t phy_data); 149 static int32_t em_read_phy_reg_ex(struct em_hw *hw,uint32_t reg_addr, 150 uint16_t *phy_data); 151 static uint16_t em_shift_in_ee_bits(struct em_hw *hw, uint16_t count); 152 static int32_t em_acquire_eeprom(struct em_hw *hw); 153 static void em_release_eeprom(struct em_hw *hw); 154 static void em_standby_eeprom(struct em_hw *hw); 155 static int32_t em_set_vco_speed(struct em_hw *hw); 156 static int32_t em_polarity_reversal_workaround(struct em_hw *hw); 157 static int32_t em_set_phy_mode(struct em_hw *hw); 158 static int32_t em_host_if_read_cookie(struct em_hw *hw, uint8_t *buffer); 159 static uint8_t em_calculate_mng_checksum(char *buffer, uint32_t length); 160 static int32_t em_configure_kmrn_for_10_100(struct em_hw *hw, 161 uint16_t duplex); 162 static int32_t em_configure_kmrn_for_1000(struct em_hw *hw); 163 164 /* IGP cable length table */ 165 static const 166 uint16_t em_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = 167 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 168 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25, 169 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40, 170 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60, 171 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90, 172 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 173 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 174 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120}; 175 176 static const 177 uint16_t em_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] = 178 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 179 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 180 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 181 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 182 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 183 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 184 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124, 185 104, 109, 114, 118, 121, 124}; 186 187 /****************************************************************************** 188 * Set the phy type member in the hw struct. 189 * 190 * hw - Struct containing variables accessed by shared code 191 *****************************************************************************/ 192 STATIC int32_t 193 em_set_phy_type(struct em_hw *hw) 194 { 195 DEBUGFUNC("em_set_phy_type"); 196 197 if (hw->mac_type == em_undefined) 198 return -E1000_ERR_PHY_TYPE; 199 200 switch (hw->phy_id) { 201 case M88E1000_E_PHY_ID: 202 case M88E1000_I_PHY_ID: 203 case M88E1011_I_PHY_ID: 204 case M88E1111_I_PHY_ID: 205 hw->phy_type = em_phy_m88; 206 break; 207 case IGP01E1000_I_PHY_ID: 208 if (hw->mac_type == em_82541 || 209 hw->mac_type == em_82541_rev_2 || 210 hw->mac_type == em_82547 || 211 hw->mac_type == em_82547_rev_2) { 212 hw->phy_type = em_phy_igp; 213 break; 214 } 215 case IGP03E1000_E_PHY_ID: 216 hw->phy_type = em_phy_igp_3; 217 break; 218 case IFE_E_PHY_ID: 219 case IFE_PLUS_E_PHY_ID: 220 case IFE_C_E_PHY_ID: 221 hw->phy_type = em_phy_ife; 222 break; 223 case GG82563_E_PHY_ID: 224 if (hw->mac_type == em_80003es2lan) { 225 hw->phy_type = em_phy_gg82563; 226 break; 227 } 228 /* FALLTHROUGH */ 229 default: 230 /* Should never have loaded on this device */ 231 hw->phy_type = em_phy_undefined; 232 return -E1000_ERR_PHY_TYPE; 233 } 234 235 return E1000_SUCCESS; 236 } 237 238 /****************************************************************************** 239 * IGP phy init script - initializes the GbE PHY 240 * 241 * hw - Struct containing variables accessed by shared code 242 *****************************************************************************/ 243 static void 244 em_phy_init_script(struct em_hw *hw) 245 { 246 uint16_t phy_saved_data; 247 248 DEBUGFUNC("em_phy_init_script"); 249 250 if (hw->phy_init_script) { 251 msec_delay(20); 252 253 /* Save off the current value of register 0x2F5B to be restored at 254 * the end of this routine. */ 255 em_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 256 257 /* Disabled the PHY transmitter */ 258 em_write_phy_reg(hw, 0x2F5B, 0x0003); 259 260 msec_delay(20); 261 262 em_write_phy_reg(hw,0x0000,0x0140); 263 264 msec_delay(5); 265 266 switch (hw->mac_type) { 267 case em_82541: 268 case em_82547: 269 em_write_phy_reg(hw, 0x1F95, 0x0001); 270 271 em_write_phy_reg(hw, 0x1F71, 0xBD21); 272 273 em_write_phy_reg(hw, 0x1F79, 0x0018); 274 275 em_write_phy_reg(hw, 0x1F30, 0x1600); 276 277 em_write_phy_reg(hw, 0x1F31, 0x0014); 278 279 em_write_phy_reg(hw, 0x1F32, 0x161C); 280 281 em_write_phy_reg(hw, 0x1F94, 0x0003); 282 283 em_write_phy_reg(hw, 0x1F96, 0x003F); 284 285 em_write_phy_reg(hw, 0x2010, 0x0008); 286 break; 287 288 case em_82541_rev_2: 289 case em_82547_rev_2: 290 em_write_phy_reg(hw, 0x1F73, 0x0099); 291 break; 292 default: 293 break; 294 } 295 296 em_write_phy_reg(hw, 0x0000, 0x3300); 297 298 msec_delay(20); 299 300 /* Now enable the transmitter */ 301 em_write_phy_reg(hw, 0x2F5B, phy_saved_data); 302 303 if (hw->mac_type == em_82547) { 304 uint16_t fused, fine, coarse; 305 306 /* Move to analog registers page */ 307 em_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused); 308 309 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { 310 em_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused); 311 312 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK; 313 coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK; 314 315 if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { 316 coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10; 317 fine -= IGP01E1000_ANALOG_FUSE_FINE_1; 318 } else if (coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH) 319 fine -= IGP01E1000_ANALOG_FUSE_FINE_10; 320 321 fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) | 322 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) | 323 (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK); 324 325 em_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused); 326 em_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS, 327 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL); 328 } 329 } 330 } 331 } 332 333 /****************************************************************************** 334 * Set the mac type member in the hw struct. 335 * 336 * hw - Struct containing variables accessed by shared code 337 *****************************************************************************/ 338 int32_t 339 em_set_mac_type(struct em_hw *hw) 340 { 341 DEBUGFUNC("em_set_mac_type"); 342 343 switch (hw->device_id) { 344 case E1000_DEV_ID_82542: 345 switch (hw->revision_id) { 346 case E1000_82542_2_0_REV_ID: 347 hw->mac_type = em_82542_rev2_0; 348 break; 349 case E1000_82542_2_1_REV_ID: 350 hw->mac_type = em_82542_rev2_1; 351 break; 352 default: 353 /* Invalid 82542 revision ID */ 354 return -E1000_ERR_MAC_TYPE; 355 } 356 break; 357 case E1000_DEV_ID_82543GC_FIBER: 358 case E1000_DEV_ID_82543GC_COPPER: 359 hw->mac_type = em_82543; 360 break; 361 case E1000_DEV_ID_82544EI_COPPER: 362 case E1000_DEV_ID_82544EI_FIBER: 363 case E1000_DEV_ID_82544GC_COPPER: 364 case E1000_DEV_ID_82544GC_LOM: 365 hw->mac_type = em_82544; 366 break; 367 case E1000_DEV_ID_82540EM: 368 case E1000_DEV_ID_82540EM_LOM: 369 case E1000_DEV_ID_82540EP: 370 case E1000_DEV_ID_82540EP_LOM: 371 case E1000_DEV_ID_82540EP_LP: 372 hw->mac_type = em_82540; 373 break; 374 case E1000_DEV_ID_82545EM_COPPER: 375 case E1000_DEV_ID_82545EM_FIBER: 376 hw->mac_type = em_82545; 377 break; 378 case E1000_DEV_ID_82545GM_COPPER: 379 case E1000_DEV_ID_82545GM_FIBER: 380 case E1000_DEV_ID_82545GM_SERDES: 381 hw->mac_type = em_82545_rev_3; 382 break; 383 case E1000_DEV_ID_82546EB_COPPER: 384 case E1000_DEV_ID_82546EB_FIBER: 385 case E1000_DEV_ID_82546EB_QUAD_COPPER: 386 hw->mac_type = em_82546; 387 break; 388 case E1000_DEV_ID_82546GB_COPPER: 389 case E1000_DEV_ID_82546GB_FIBER: 390 case E1000_DEV_ID_82546GB_SERDES: 391 case E1000_DEV_ID_82546GB_PCIE: 392 case E1000_DEV_ID_82546GB_QUAD_COPPER: 393 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 394 case E1000_DEV_ID_82546GB_2: 395 hw->mac_type = em_82546_rev_3; 396 break; 397 case E1000_DEV_ID_82541EI: 398 case E1000_DEV_ID_82541EI_MOBILE: 399 case E1000_DEV_ID_82541ER_LOM: 400 hw->mac_type = em_82541; 401 break; 402 case E1000_DEV_ID_82541ER: 403 case E1000_DEV_ID_82541GI: 404 case E1000_DEV_ID_82541GI_LF: 405 case E1000_DEV_ID_82541GI_MOBILE: 406 hw->mac_type = em_82541_rev_2; 407 break; 408 case E1000_DEV_ID_82547EI: 409 case E1000_DEV_ID_82547EI_MOBILE: 410 hw->mac_type = em_82547; 411 break; 412 case E1000_DEV_ID_82547GI: 413 hw->mac_type = em_82547_rev_2; 414 break; 415 case E1000_DEV_ID_82571EB_AF: 416 case E1000_DEV_ID_82571EB_AT: 417 case E1000_DEV_ID_82571EB_COPPER: 418 case E1000_DEV_ID_82571EB_FIBER: 419 case E1000_DEV_ID_82571EB_SERDES: 420 case E1000_DEV_ID_82571EB_QUAD_COPPER: 421 case E1000_DEV_ID_82571EB_QUAD_FIBER: 422 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 423 case E1000_DEV_ID_82571EB_SERDES_DUAL: 424 case E1000_DEV_ID_82571EB_SERDES_QUAD: 425 case E1000_DEV_ID_82571PT_QUAD_COPPER: 426 hw->mac_type = em_82571; 427 break; 428 case E1000_DEV_ID_82572EI_COPPER: 429 case E1000_DEV_ID_82572EI_FIBER: 430 case E1000_DEV_ID_82572EI_SERDES: 431 case E1000_DEV_ID_82572EI: 432 hw->mac_type = em_82572; 433 break; 434 case E1000_DEV_ID_82573E: 435 case E1000_DEV_ID_82573E_IAMT: 436 case E1000_DEV_ID_82573E_PM: 437 case E1000_DEV_ID_82573L: 438 case E1000_DEV_ID_82573L_PL_1: 439 case E1000_DEV_ID_82573L_PL_2: 440 case E1000_DEV_ID_82573V_PM: 441 hw->mac_type = em_82573; 442 break; 443 case E1000_DEV_ID_80003ES2LAN_COPPER_SPT: 444 case E1000_DEV_ID_80003ES2LAN_SERDES_SPT: 445 case E1000_DEV_ID_80003ES2LAN_COPPER_DPT: 446 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: 447 hw->mac_type = em_80003es2lan; 448 break; 449 case E1000_DEV_ID_ICH8_IFE: 450 case E1000_DEV_ID_ICH8_IFE_G: 451 case E1000_DEV_ID_ICH8_IFE_GT: 452 case E1000_DEV_ID_ICH8_IGP_AMT: 453 case E1000_DEV_ID_ICH8_IGP_C: 454 case E1000_DEV_ID_ICH8_IGP_M: 455 case E1000_DEV_ID_ICH8_IGP_M_AMT: 456 hw->mac_type = em_ich8lan; 457 break; 458 case E1000_DEV_ID_ICH9_IFE: 459 case E1000_DEV_ID_ICH9_IFE_G: 460 case E1000_DEV_ID_ICH9_IFE_GT: 461 case E1000_DEV_ID_ICH9_IGP_AMT: 462 case E1000_DEV_ID_ICH9_IGP_C: 463 case E1000_DEV_ID_ICH9_IGP_M: 464 case E1000_DEV_ID_ICH9_IGP_M_AMT: 465 hw->mac_type = em_ich9lan; 466 break; 467 default: 468 /* Should never have loaded on this device */ 469 return -E1000_ERR_MAC_TYPE; 470 } 471 472 switch (hw->mac_type) { 473 case em_ich8lan: 474 case em_ich9lan: 475 hw->swfwhw_semaphore_present = TRUE; 476 hw->asf_firmware_present = TRUE; 477 break; 478 case em_80003es2lan: 479 hw->swfw_sync_present = TRUE; 480 /* FALLTHROUGH */ 481 case em_82571: 482 case em_82572: 483 case em_82573: 484 hw->eeprom_semaphore_present = TRUE; 485 /* FALLTHROUGH */ 486 case em_82541: 487 case em_82547: 488 case em_82541_rev_2: 489 case em_82547_rev_2: 490 hw->asf_firmware_present = TRUE; 491 break; 492 default: 493 break; 494 } 495 496 return E1000_SUCCESS; 497 } 498 499 /***************************************************************************** 500 * Set media type and TBI compatibility. 501 * 502 * hw - Struct containing variables accessed by shared code 503 * **************************************************************************/ 504 void 505 em_set_media_type(struct em_hw *hw) 506 { 507 uint32_t status; 508 509 DEBUGFUNC("em_set_media_type"); 510 511 if (hw->mac_type != em_82543) { 512 /* tbi_compatibility is only valid on 82543 */ 513 hw->tbi_compatibility_en = FALSE; 514 } 515 516 switch (hw->device_id) { 517 case E1000_DEV_ID_82545GM_SERDES: 518 case E1000_DEV_ID_82546GB_SERDES: 519 case E1000_DEV_ID_82571EB_SERDES: 520 case E1000_DEV_ID_82571EB_SERDES_DUAL: 521 case E1000_DEV_ID_82571EB_SERDES_QUAD: 522 case E1000_DEV_ID_82572EI_SERDES: 523 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: 524 hw->media_type = em_media_type_internal_serdes; 525 break; 526 default: 527 switch (hw->mac_type) { 528 case em_82542_rev2_0: 529 case em_82542_rev2_1: 530 hw->media_type = em_media_type_fiber; 531 break; 532 case em_ich8lan: 533 case em_ich9lan: 534 case em_82573: 535 /* The STATUS_TBIMODE bit is reserved or reused for the this 536 * device. 537 */ 538 hw->media_type = em_media_type_copper; 539 break; 540 default: 541 status = E1000_READ_REG(hw, STATUS); 542 if (status & E1000_STATUS_TBIMODE) { 543 hw->media_type = em_media_type_fiber; 544 /* tbi_compatibility not valid on fiber */ 545 hw->tbi_compatibility_en = FALSE; 546 } else { 547 hw->media_type = em_media_type_copper; 548 } 549 break; 550 } 551 } 552 } 553 554 /****************************************************************************** 555 * Reset the transmit and receive units; mask and clear all interrupts. 556 * 557 * hw - Struct containing variables accessed by shared code 558 *****************************************************************************/ 559 int32_t 560 em_reset_hw(struct em_hw *hw) 561 { 562 uint32_t ctrl; 563 uint32_t ctrl_ext; 564 uint32_t icr; 565 uint32_t manc; 566 uint32_t led_ctrl; 567 uint32_t timeout; 568 uint32_t extcnf_ctrl; 569 int32_t ret_val; 570 571 DEBUGFUNC("em_reset_hw"); 572 573 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ 574 if (hw->mac_type == em_82542_rev2_0) { 575 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 576 em_pci_clear_mwi(hw); 577 } 578 579 if (hw->bus_type == em_bus_type_pci_express) { 580 /* Prevent the PCI-E bus from sticking if there is no TLP connection 581 * on the last TLP read/write transaction when MAC is reset. 582 */ 583 if (em_disable_pciex_master(hw) != E1000_SUCCESS) { 584 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 585 } 586 } 587 588 /* Clear interrupt mask to stop board from generating interrupts */ 589 DEBUGOUT("Masking off all interrupts\n"); 590 E1000_WRITE_REG(hw, IMC, 0xffffffff); 591 592 /* Disable the Transmit and Receive units. Then delay to allow 593 * any pending transactions to complete before we hit the MAC with 594 * the global reset. 595 */ 596 E1000_WRITE_REG(hw, RCTL, 0); 597 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP); 598 E1000_WRITE_FLUSH(hw); 599 600 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */ 601 hw->tbi_compatibility_on = FALSE; 602 603 /* Delay to allow any outstanding PCI transactions to complete before 604 * resetting the device 605 */ 606 msec_delay(10); 607 608 ctrl = E1000_READ_REG(hw, CTRL); 609 610 /* Must reset the PHY before resetting the MAC */ 611 if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) { 612 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST)); 613 msec_delay(5); 614 } 615 616 /* Must acquire the MDIO ownership before MAC reset. 617 * Ownership defaults to firmware after a reset. */ 618 if (hw->mac_type == em_82573) { 619 timeout = 10; 620 621 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 622 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 623 624 do { 625 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); 626 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 627 628 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) 629 break; 630 else 631 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 632 633 msec_delay(2); 634 timeout--; 635 } while (timeout); 636 } 637 638 /* Workaround for ICH8 bit corruption issue in FIFO memory */ 639 if (hw->mac_type == em_ich8lan) { 640 /* Set Tx and Rx buffer allocation to 8k apiece. */ 641 E1000_WRITE_REG(hw, PBA, E1000_PBA_8K); 642 /* Set Packet Buffer Size to 16k. */ 643 E1000_WRITE_REG(hw, PBS, E1000_PBS_16K); 644 } 645 646 /* Issue a global reset to the MAC. This will reset the chip's 647 * transmit, receive, DMA, and link units. It will not effect 648 * the current PCI configuration. The global reset bit is self- 649 * clearing, and should clear within a microsecond. 650 */ 651 DEBUGOUT("Issuing a global reset to MAC\n"); 652 653 switch (hw->mac_type) { 654 case em_82544: 655 case em_82540: 656 case em_82545: 657 case em_82546: 658 case em_82541: 659 case em_82541_rev_2: 660 /* These controllers can't ack the 64-bit write when issuing the 661 * reset, so use IO-mapping as a workaround to issue the reset */ 662 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST)); 663 break; 664 case em_82545_rev_3: 665 case em_82546_rev_3: 666 /* Reset is performed on a shadow of the control register */ 667 E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST)); 668 break; 669 case em_ich8lan: 670 case em_ich9lan: 671 if (!hw->phy_reset_disable && 672 em_check_phy_reset_block(hw) == E1000_SUCCESS) { 673 /* PHY HW reset requires MAC CORE reset at the same 674 * time to make sure the interface between MAC and the 675 * external PHY is reset. 676 */ 677 ctrl |= E1000_CTRL_PHY_RST; 678 } 679 680 em_get_software_flag(hw); 681 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); 682 msec_delay(5); 683 break; 684 default: 685 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); 686 break; 687 } 688 689 /* After MAC reset, force reload of EEPROM to restore power-on settings to 690 * device. Later controllers reload the EEPROM automatically, so just wait 691 * for reload to complete. 692 */ 693 switch (hw->mac_type) { 694 case em_82542_rev2_0: 695 case em_82542_rev2_1: 696 case em_82543: 697 case em_82544: 698 /* Wait for reset to complete */ 699 usec_delay(10); 700 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 701 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 702 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 703 E1000_WRITE_FLUSH(hw); 704 /* Wait for EEPROM reload */ 705 msec_delay(2); 706 break; 707 case em_82541: 708 case em_82541_rev_2: 709 case em_82547: 710 case em_82547_rev_2: 711 /* Wait for EEPROM reload */ 712 msec_delay(20); 713 break; 714 case em_82573: 715 if (em_is_onboard_nvm_eeprom(hw) == FALSE) { 716 usec_delay(10); 717 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 718 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 719 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 720 E1000_WRITE_FLUSH(hw); 721 } 722 /* FALLTHROUGH */ 723 default: 724 /* Auto read done will delay 5ms or poll based on mac type */ 725 ret_val = em_get_auto_rd_done(hw); 726 if (ret_val) 727 return ret_val; 728 break; 729 } 730 731 /* Disable HW ARPs on ASF enabled adapters */ 732 if (hw->mac_type >= em_82540 && hw->mac_type <= em_82547_rev_2) { 733 manc = E1000_READ_REG(hw, MANC); 734 manc &= ~(E1000_MANC_ARP_EN); 735 E1000_WRITE_REG(hw, MANC, manc); 736 } 737 738 if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) { 739 em_phy_init_script(hw); 740 741 /* Configure activity LED after PHY reset */ 742 led_ctrl = E1000_READ_REG(hw, LEDCTL); 743 led_ctrl &= IGP_ACTIVITY_LED_MASK; 744 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 745 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 746 } 747 748 /* Clear interrupt mask to stop board from generating interrupts */ 749 DEBUGOUT("Masking off all interrupts\n"); 750 E1000_WRITE_REG(hw, IMC, 0xffffffff); 751 752 /* Clear any pending interrupt events. */ 753 icr = E1000_READ_REG(hw, ICR); 754 755 /* If MWI was previously enabled, reenable it. */ 756 if (hw->mac_type == em_82542_rev2_0) { 757 if (hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 758 em_pci_set_mwi(hw); 759 } 760 761 if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) { 762 uint32_t kab = E1000_READ_REG(hw, KABGTXD); 763 kab |= E1000_KABGTXD_BGSQLBIAS; 764 E1000_WRITE_REG(hw, KABGTXD, kab); 765 } 766 767 return E1000_SUCCESS; 768 } 769 770 /****************************************************************************** 771 * 772 * Initialize a number of hardware-dependent bits 773 * 774 * hw: Struct containing variables accessed by shared code 775 * 776 *****************************************************************************/ 777 STATIC void 778 em_initialize_hardware_bits(struct em_hw *hw) 779 { 780 if ((hw->mac_type >= em_82571) && (!hw->initialize_hw_bits_disable)) { 781 /* Settings common to all silicon */ 782 uint32_t reg_ctrl, reg_ctrl_ext; 783 uint32_t reg_tarc0, reg_tarc1; 784 uint32_t reg_tctl; 785 uint32_t reg_txdctl, reg_txdctl1; 786 787 reg_tarc0 = E1000_READ_REG(hw, TARC0); 788 reg_tarc0 &= ~0x78000000; /* Clear bits 30, 29, 28, and 27 */ 789 790 reg_txdctl = E1000_READ_REG(hw, TXDCTL); 791 reg_txdctl |= E1000_TXDCTL_COUNT_DESC; /* Set bit 22 */ 792 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl); 793 794 reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1); 795 reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC; /* Set bit 22 */ 796 E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1); 797 798 switch (hw->mac_type) { 799 case em_82571: 800 case em_82572: 801 reg_tarc1 = E1000_READ_REG(hw, TARC1); 802 reg_tctl = E1000_READ_REG(hw, TCTL); 803 804 /* Set the phy Tx compatible mode bits */ 805 reg_tarc1 &= ~0x60000000; /* Clear bits 30 and 29 */ 806 807 reg_tarc0 |= 0x07800000; /* Set TARC0 bits 23-26 */ 808 reg_tarc1 |= 0x07000000; /* Set TARC1 bits 24-26 */ 809 810 if (reg_tctl & E1000_TCTL_MULR) 811 reg_tarc1 &= ~0x10000000; /* Clear bit 28 if MULR is 1b */ 812 else 813 reg_tarc1 |= 0x10000000; /* Set bit 28 if MULR is 0b */ 814 815 E1000_WRITE_REG(hw, TARC1, reg_tarc1); 816 break; 817 case em_82573: 818 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 819 reg_ctrl = E1000_READ_REG(hw, CTRL); 820 821 reg_ctrl_ext &= ~0x00800000; /* Clear bit 23 */ 822 reg_ctrl_ext |= 0x00400000; /* Set bit 22 */ 823 reg_ctrl &= ~0x20000000; /* Clear bit 29 */ 824 825 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); 826 E1000_WRITE_REG(hw, CTRL, reg_ctrl); 827 break; 828 case em_80003es2lan: 829 if ((hw->media_type == em_media_type_fiber) || 830 (hw->media_type == em_media_type_internal_serdes)) { 831 reg_tarc0 &= ~0x00100000; /* Clear bit 20 */ 832 } 833 834 reg_tctl = E1000_READ_REG(hw, TCTL); 835 reg_tarc1 = E1000_READ_REG(hw, TARC1); 836 if (reg_tctl & E1000_TCTL_MULR) 837 reg_tarc1 &= ~0x10000000; /* Clear bit 28 if MULR is 1b */ 838 else 839 reg_tarc1 |= 0x10000000; /* Set bit 28 if MULR is 0b */ 840 841 E1000_WRITE_REG(hw, TARC1, reg_tarc1); 842 break; 843 case em_ich8lan: 844 case em_ich9lan: 845 if (hw->mac_type == em_ich8lan) 846 reg_tarc0 |= 0x30000000; /* Set TARC0 bits 29 and 28 */ 847 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 848 reg_ctrl_ext |= 0x00400000; /* Set bit 22 */ 849 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); 850 851 reg_tarc0 |= 0x0d800000; /* Set TARC0 bits 23, 24, 26, 27 */ 852 853 reg_tarc1 = E1000_READ_REG(hw, TARC1); 854 reg_tctl = E1000_READ_REG(hw, TCTL); 855 856 if (reg_tctl & E1000_TCTL_MULR) 857 reg_tarc1 &= ~0x10000000; /* Clear bit 28 if MULR is 1b */ 858 else 859 reg_tarc1 |= 0x10000000; /* Set bit 28 if MULR is 0b */ 860 861 reg_tarc1 |= 0x45000000; /* Set bit 24, 26 and 30 */ 862 863 E1000_WRITE_REG(hw, TARC1, reg_tarc1); 864 break; 865 default: 866 break; 867 } 868 869 E1000_WRITE_REG(hw, TARC0, reg_tarc0); 870 } 871 } 872 873 /****************************************************************************** 874 * Performs basic configuration of the adapter. 875 * 876 * hw - Struct containing variables accessed by shared code 877 * 878 * Assumes that the controller has previously been reset and is in a 879 * post-reset uninitialized state. Initializes the receive address registers, 880 * multicast table, and VLAN filter table. Calls routines to setup link 881 * configuration and flow control settings. Clears all on-chip counters. Leaves 882 * the transmit and receive units disabled and uninitialized. 883 *****************************************************************************/ 884 int32_t 885 em_init_hw(struct em_hw *hw) 886 { 887 uint32_t ctrl; 888 uint32_t i; 889 int32_t ret_val; 890 uint16_t pcix_cmd_word; 891 uint16_t pcix_stat_hi_word; 892 uint16_t cmd_mmrbc; 893 uint16_t stat_mmrbc; 894 uint32_t mta_size; 895 uint32_t reg_data; 896 uint32_t ctrl_ext; 897 uint32_t snoop; 898 899 DEBUGFUNC("em_init_hw"); 900 901 /* force full DMA clock frequency for ICH8 */ 902 if (hw->mac_type == em_ich8lan) { 903 reg_data = E1000_READ_REG(hw, STATUS); 904 reg_data &= ~0x80000000; 905 E1000_WRITE_REG(hw, STATUS, reg_data); 906 } 907 908 /* Initialize Identification LED */ 909 ret_val = em_id_led_init(hw); 910 if (ret_val) { 911 DEBUGOUT("Error Initializing Identification LED\n"); 912 return ret_val; 913 } 914 915 /* Set the media type and TBI compatibility */ 916 em_set_media_type(hw); 917 918 /* Must be called after em_set_media_type because media_type is used */ 919 em_initialize_hardware_bits(hw); 920 921 /* Disabling VLAN filtering. */ 922 DEBUGOUT("Initializing the IEEE VLAN\n"); 923 /* VET hardcoded to standard value and VFTA removed in ICH8/ICH9 LAN */ 924 if (hw->mac_type != em_ich8lan && hw->mac_type != em_ich9lan) { 925 if (hw->mac_type < em_82545_rev_3) 926 E1000_WRITE_REG(hw, VET, 0); 927 em_clear_vfta(hw); 928 } 929 930 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ 931 if (hw->mac_type == em_82542_rev2_0) { 932 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 933 em_pci_clear_mwi(hw); 934 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST); 935 E1000_WRITE_FLUSH(hw); 936 msec_delay(5); 937 } 938 939 /* Setup the receive address. This involves initializing all of the Receive 940 * Address Registers (RARs 0 - 15). 941 */ 942 em_init_rx_addrs(hw); 943 944 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */ 945 if (hw->mac_type == em_82542_rev2_0) { 946 E1000_WRITE_REG(hw, RCTL, 0); 947 E1000_WRITE_FLUSH(hw); 948 msec_delay(1); 949 if (hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 950 em_pci_set_mwi(hw); 951 } 952 953 /* Zero out the Multicast HASH table */ 954 DEBUGOUT("Zeroing the MTA\n"); 955 mta_size = E1000_MC_TBL_SIZE; 956 if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) 957 mta_size = E1000_MC_TBL_SIZE_ICH8LAN; 958 for (i = 0; i < mta_size; i++) { 959 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 960 /* use write flush to prevent Memory Write Block (MWB) from 961 * occuring when accessing our register space */ 962 E1000_WRITE_FLUSH(hw); 963 } 964 965 /* Set the PCI priority bit correctly in the CTRL register. This 966 * determines if the adapter gives priority to receives, or if it 967 * gives equal priority to transmits and receives. Valid only on 968 * 82542 and 82543 silicon. 969 */ 970 if (hw->dma_fairness && hw->mac_type <= em_82543) { 971 ctrl = E1000_READ_REG(hw, CTRL); 972 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR); 973 } 974 975 switch (hw->mac_type) { 976 case em_82545_rev_3: 977 case em_82546_rev_3: 978 break; 979 default: 980 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */ 981 if (hw->bus_type == em_bus_type_pcix) { 982 em_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word); 983 em_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, 984 &pcix_stat_hi_word); 985 cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >> 986 PCIX_COMMAND_MMRBC_SHIFT; 987 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> 988 PCIX_STATUS_HI_MMRBC_SHIFT; 989 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) 990 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; 991 if (cmd_mmrbc > stat_mmrbc) { 992 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK; 993 pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; 994 em_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, 995 &pcix_cmd_word); 996 } 997 } 998 break; 999 } 1000 1001 /* More time needed for PHY to initialize */ 1002 if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) 1003 msec_delay(15); 1004 1005 /* Call a subroutine to configure the link and setup flow control. */ 1006 ret_val = em_setup_link(hw); 1007 1008 /* Set the transmit descriptor write-back policy */ 1009 if (hw->mac_type > em_82544) { 1010 ctrl = E1000_READ_REG(hw, TXDCTL); 1011 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB; 1012 E1000_WRITE_REG(hw, TXDCTL, ctrl); 1013 } 1014 1015 if (hw->mac_type == em_82573) { 1016 em_enable_tx_pkt_filtering(hw); 1017 } 1018 1019 switch (hw->mac_type) { 1020 default: 1021 break; 1022 case em_80003es2lan: 1023 /* Enable retransmit on late collisions */ 1024 reg_data = E1000_READ_REG(hw, TCTL); 1025 reg_data |= E1000_TCTL_RTLC; 1026 E1000_WRITE_REG(hw, TCTL, reg_data); 1027 1028 /* Configure Gigabit Carry Extend Padding */ 1029 reg_data = E1000_READ_REG(hw, TCTL_EXT); 1030 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK; 1031 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX; 1032 E1000_WRITE_REG(hw, TCTL_EXT, reg_data); 1033 1034 /* Configure Transmit Inter-Packet Gap */ 1035 reg_data = E1000_READ_REG(hw, TIPG); 1036 reg_data &= ~E1000_TIPG_IPGT_MASK; 1037 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; 1038 E1000_WRITE_REG(hw, TIPG, reg_data); 1039 1040 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001); 1041 reg_data &= ~0x00100000; 1042 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data); 1043 /* FALLTHROUGH */ 1044 case em_82571: 1045 case em_82572: 1046 case em_ich8lan: 1047 case em_ich9lan: 1048 ctrl = E1000_READ_REG(hw, TXDCTL1); 1049 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB; 1050 E1000_WRITE_REG(hw, TXDCTL1, ctrl); 1051 break; 1052 } 1053 1054 if (hw->mac_type == em_82573) { 1055 uint32_t gcr = E1000_READ_REG(hw, GCR); 1056 gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; 1057 E1000_WRITE_REG(hw, GCR, gcr); 1058 } 1059 1060 /* Clear all of the statistics registers (clear on read). It is 1061 * important that we do this after we have tried to establish link 1062 * because the symbol error count will increment wildly if there 1063 * is no link. 1064 */ 1065 em_clear_hw_cntrs(hw); 1066 1067 /* ICH8 No-snoop bits are opposite polarity. 1068 * Set to snoop by default after reset. */ 1069 if (hw->mac_type == em_ich8lan) 1070 snoop = PCI_EX_82566_SNOOP_ALL; 1071 else if (hw->mac_type == em_ich9lan) 1072 snoop = (u_int32_t)~(PCI_EX_NO_SNOOP_ALL); 1073 if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) 1074 em_set_pci_ex_no_snoop(hw, snoop); 1075 1076 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER || 1077 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) { 1078 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1079 /* Relaxed ordering must be disabled to avoid a parity 1080 * error crash in a PCI slot. */ 1081 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 1082 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1083 } 1084 1085 return ret_val; 1086 } 1087 1088 /****************************************************************************** 1089 * Adjust SERDES output amplitude based on EEPROM setting. 1090 * 1091 * hw - Struct containing variables accessed by shared code. 1092 *****************************************************************************/ 1093 static int32_t 1094 em_adjust_serdes_amplitude(struct em_hw *hw) 1095 { 1096 uint16_t eeprom_data; 1097 int32_t ret_val; 1098 1099 DEBUGFUNC("em_adjust_serdes_amplitude"); 1100 1101 if (hw->media_type != em_media_type_internal_serdes) 1102 return E1000_SUCCESS; 1103 1104 switch (hw->mac_type) { 1105 case em_82545_rev_3: 1106 case em_82546_rev_3: 1107 break; 1108 default: 1109 return E1000_SUCCESS; 1110 } 1111 1112 ret_val = em_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data); 1113 if (ret_val) { 1114 return ret_val; 1115 } 1116 1117 if (eeprom_data != EEPROM_RESERVED_WORD) { 1118 /* Adjust SERDES output amplitude only. */ 1119 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK; 1120 ret_val = em_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data); 1121 if (ret_val) 1122 return ret_val; 1123 } 1124 1125 return E1000_SUCCESS; 1126 } 1127 1128 /****************************************************************************** 1129 * Configures flow control and link settings. 1130 * 1131 * hw - Struct containing variables accessed by shared code 1132 * 1133 * Determines which flow control settings to use. Calls the appropriate media- 1134 * specific link configuration function. Configures the flow control settings. 1135 * Assuming the adapter has a valid link partner, a valid link should be 1136 * established. Assumes the hardware has previously been reset and the 1137 * transmitter and receiver are not enabled. 1138 *****************************************************************************/ 1139 int32_t 1140 em_setup_link(struct em_hw *hw) 1141 { 1142 uint32_t ctrl_ext; 1143 int32_t ret_val; 1144 uint16_t eeprom_data; 1145 1146 DEBUGFUNC("em_setup_link"); 1147 1148 /* In the case of the phy reset being blocked, we already have a link. 1149 * We do not have to set it up again. */ 1150 if (em_check_phy_reset_block(hw)) 1151 return E1000_SUCCESS; 1152 1153 /* Read and store word 0x0F of the EEPROM. This word contains bits 1154 * that determine the hardware's default PAUSE (flow control) mode, 1155 * a bit that determines whether the HW defaults to enabling or 1156 * disabling auto-negotiation, and the direction of the 1157 * SW defined pins. If there is no SW over-ride of the flow 1158 * control setting, then the variable hw->fc will 1159 * be initialized based on a value in the EEPROM. 1160 */ 1161 if (hw->fc == E1000_FC_DEFAULT) { 1162 switch (hw->mac_type) { 1163 case em_ich8lan: 1164 case em_ich9lan: 1165 case em_82573: 1166 hw->fc = E1000_FC_FULL; 1167 break; 1168 default: 1169 ret_val = em_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1170 1, &eeprom_data); 1171 if (ret_val) { 1172 DEBUGOUT("EEPROM Read Error\n"); 1173 return -E1000_ERR_EEPROM; 1174 } 1175 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0) 1176 hw->fc = E1000_FC_NONE; 1177 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 1178 EEPROM_WORD0F_ASM_DIR) 1179 hw->fc = E1000_FC_TX_PAUSE; 1180 else 1181 hw->fc = E1000_FC_FULL; 1182 break; 1183 } 1184 } 1185 1186 /* We want to save off the original Flow Control configuration just 1187 * in case we get disconnected and then reconnected into a different 1188 * hub or switch with different Flow Control capabilities. 1189 */ 1190 if (hw->mac_type == em_82542_rev2_0) 1191 hw->fc &= (~E1000_FC_TX_PAUSE); 1192 1193 if ((hw->mac_type < em_82543) && (hw->report_tx_early == 1)) 1194 hw->fc &= (~E1000_FC_RX_PAUSE); 1195 1196 hw->original_fc = hw->fc; 1197 1198 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc); 1199 1200 /* Take the 4 bits from EEPROM word 0x0F that determine the initial 1201 * polarity value for the SW controlled pins, and setup the 1202 * Extended Device Control reg with that info. 1203 * This is needed because one of the SW controlled pins is used for 1204 * signal detection. So this should be done before em_setup_pcs_link() 1205 * or em_phy_setup() is called. 1206 */ 1207 if (hw->mac_type == em_82543) { 1208 ret_val = em_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1209 1, &eeprom_data); 1210 if (ret_val) { 1211 DEBUGOUT("EEPROM Read Error\n"); 1212 return -E1000_ERR_EEPROM; 1213 } 1214 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << 1215 SWDPIO__EXT_SHIFT); 1216 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1217 } 1218 1219 /* Call the necessary subroutine to configure the link. */ 1220 ret_val = (hw->media_type == em_media_type_copper) ? 1221 em_setup_copper_link(hw) : 1222 em_setup_fiber_serdes_link(hw); 1223 1224 /* Initialize the flow control address, type, and PAUSE timer 1225 * registers to their default values. This is done even if flow 1226 * control is disabled, because it does not hurt anything to 1227 * initialize these registers. 1228 */ 1229 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"); 1230 1231 /* FCAL/H and FCT are hardcoded to standard values in em_ich8lan/em_ich9lan. */ 1232 if (hw->mac_type != em_ich8lan && hw->mac_type != em_ich9lan) { 1233 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE); 1234 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH); 1235 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW); 1236 } 1237 1238 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time); 1239 1240 /* Set the flow control receive threshold registers. Normally, 1241 * these registers will be set to a default threshold that may be 1242 * adjusted later by the driver's runtime code. However, if the 1243 * ability to transmit pause frames in not enabled, then these 1244 * registers will be set to 0. 1245 */ 1246 if (!(hw->fc & E1000_FC_TX_PAUSE)) { 1247 E1000_WRITE_REG(hw, FCRTL, 0); 1248 E1000_WRITE_REG(hw, FCRTH, 0); 1249 } else { 1250 /* We need to set up the Receive Threshold high and low water marks 1251 * as well as (optionally) enabling the transmission of XON frames. 1252 */ 1253 if (hw->fc_send_xon) { 1254 E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE)); 1255 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); 1256 } else { 1257 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water); 1258 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); 1259 } 1260 } 1261 return ret_val; 1262 } 1263 1264 /****************************************************************************** 1265 * Sets up link for a fiber based or serdes based adapter 1266 * 1267 * hw - Struct containing variables accessed by shared code 1268 * 1269 * Manipulates Physical Coding Sublayer functions in order to configure 1270 * link. Assumes the hardware has been previously reset and the transmitter 1271 * and receiver are not enabled. 1272 *****************************************************************************/ 1273 static int32_t 1274 em_setup_fiber_serdes_link(struct em_hw *hw) 1275 { 1276 uint32_t ctrl; 1277 uint32_t status; 1278 uint32_t txcw = 0; 1279 uint32_t i; 1280 uint32_t signal = 0; 1281 int32_t ret_val; 1282 1283 DEBUGFUNC("em_setup_fiber_serdes_link"); 1284 1285 /* On 82571 and 82572 Fiber connections, SerDes loopback mode persists 1286 * until explicitly turned off or a power cycle is performed. A read to 1287 * the register does not indicate its status. Therefore, we ensure 1288 * loopback mode is disabled during initialization. 1289 */ 1290 if (hw->mac_type == em_82571 || hw->mac_type == em_82572) 1291 E1000_WRITE_REG(hw, SCTL, E1000_DISABLE_SERDES_LOOPBACK); 1292 1293 /* On adapters with a MAC newer than 82544, SWDP 1 will be 1294 * set when the optics detect a signal. On older adapters, it will be 1295 * cleared when there is a signal. This applies to fiber media only. 1296 * If we're on serdes media, adjust the output amplitude to value 1297 * set in the EEPROM. 1298 */ 1299 ctrl = E1000_READ_REG(hw, CTRL); 1300 if (hw->media_type == em_media_type_fiber) 1301 signal = (hw->mac_type > em_82544) ? E1000_CTRL_SWDPIN1 : 0; 1302 1303 ret_val = em_adjust_serdes_amplitude(hw); 1304 if (ret_val) 1305 return ret_val; 1306 1307 /* Take the link out of reset */ 1308 ctrl &= ~(E1000_CTRL_LRST); 1309 1310 /* Adjust VCO speed to improve BER performance */ 1311 ret_val = em_set_vco_speed(hw); 1312 if (ret_val) 1313 return ret_val; 1314 1315 em_config_collision_dist(hw); 1316 1317 /* Check for a software override of the flow control settings, and setup 1318 * the device accordingly. If auto-negotiation is enabled, then software 1319 * will have to set the "PAUSE" bits to the correct value in the Tranmsit 1320 * Config Word Register (TXCW) and re-start auto-negotiation. However, if 1321 * auto-negotiation is disabled, then software will have to manually 1322 * configure the two flow control enable bits in the CTRL register. 1323 * 1324 * The possible values of the "fc" parameter are: 1325 * 0: Flow control is completely disabled 1326 * 1: Rx flow control is enabled (we can receive pause frames, but 1327 * not send pause frames). 1328 * 2: Tx flow control is enabled (we can send pause frames but we do 1329 * not support receiving pause frames). 1330 * 3: Both Rx and TX flow control (symmetric) are enabled. 1331 */ 1332 switch (hw->fc) { 1333 case E1000_FC_NONE: 1334 /* Flow control is completely disabled by a software over-ride. */ 1335 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 1336 break; 1337 case E1000_FC_RX_PAUSE: 1338 /* RX Flow control is enabled and TX Flow control is disabled by a 1339 * software over-ride. Since there really isn't a way to advertise 1340 * that we are capable of RX Pause ONLY, we will advertise that we 1341 * support both symmetric and asymmetric RX PAUSE. Later, we will 1342 * disable the adapter's ability to send PAUSE frames. 1343 */ 1344 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1345 break; 1346 case E1000_FC_TX_PAUSE: 1347 /* TX Flow control is enabled, and RX Flow control is disabled, by a 1348 * software over-ride. 1349 */ 1350 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 1351 break; 1352 case E1000_FC_FULL: 1353 /* Flow control (both RX and TX) is enabled by a software over-ride. */ 1354 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1355 break; 1356 default: 1357 DEBUGOUT("Flow control param set incorrectly\n"); 1358 return -E1000_ERR_CONFIG; 1359 break; 1360 } 1361 1362 /* Since auto-negotiation is enabled, take the link out of reset (the link 1363 * will be in reset, because we previously reset the chip). This will 1364 * restart auto-negotiation. If auto-neogtiation is successful then the 1365 * link-up status bit will be set and the flow control enable bits (RFCE 1366 * and TFCE) will be set according to their negotiated value. 1367 */ 1368 DEBUGOUT("Auto-negotiation enabled\n"); 1369 1370 E1000_WRITE_REG(hw, TXCW, txcw); 1371 E1000_WRITE_REG(hw, CTRL, ctrl); 1372 E1000_WRITE_FLUSH(hw); 1373 1374 hw->txcw = txcw; 1375 msec_delay(1); 1376 1377 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up" 1378 * indication in the Device Status Register. Time-out if a link isn't 1379 * seen in 500 milliseconds seconds (Auto-negotiation should complete in 1380 * less than 500 milliseconds even if the other end is doing it in SW). 1381 * For internal serdes, we just assume a signal is present, then poll. 1382 */ 1383 if (hw->media_type == em_media_type_internal_serdes || 1384 (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) { 1385 DEBUGOUT("Looking for Link\n"); 1386 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) { 1387 msec_delay(10); 1388 status = E1000_READ_REG(hw, STATUS); 1389 if (status & E1000_STATUS_LU) break; 1390 } 1391 if (i == (LINK_UP_TIMEOUT / 10)) { 1392 DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 1393 hw->autoneg_failed = 1; 1394 /* AutoNeg failed to achieve a link, so we'll call 1395 * em_check_for_link. This routine will force the link up if 1396 * we detect a signal. This will allow us to communicate with 1397 * non-autonegotiating link partners. 1398 */ 1399 ret_val = em_check_for_link(hw); 1400 if (ret_val) { 1401 DEBUGOUT("Error while checking for link\n"); 1402 return ret_val; 1403 } 1404 hw->autoneg_failed = 0; 1405 } else { 1406 hw->autoneg_failed = 0; 1407 DEBUGOUT("Valid Link Found\n"); 1408 } 1409 } else { 1410 DEBUGOUT("No Signal Detected\n"); 1411 } 1412 return E1000_SUCCESS; 1413 } 1414 1415 /****************************************************************************** 1416 * Make sure we have a valid PHY and change PHY mode before link setup. 1417 * 1418 * hw - Struct containing variables accessed by shared code 1419 ******************************************************************************/ 1420 static int32_t 1421 em_copper_link_preconfig(struct em_hw *hw) 1422 { 1423 uint32_t ctrl; 1424 int32_t ret_val; 1425 uint16_t phy_data; 1426 1427 DEBUGFUNC("em_copper_link_preconfig"); 1428 1429 ctrl = E1000_READ_REG(hw, CTRL); 1430 /* With 82543, we need to force speed and duplex on the MAC equal to what 1431 * the PHY speed and duplex configuration is. In addition, we need to 1432 * perform a hardware reset on the PHY to take it out of reset. 1433 */ 1434 if (hw->mac_type > em_82543) { 1435 ctrl |= E1000_CTRL_SLU; 1436 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1437 E1000_WRITE_REG(hw, CTRL, ctrl); 1438 } else { 1439 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU); 1440 E1000_WRITE_REG(hw, CTRL, ctrl); 1441 ret_val = em_phy_hw_reset(hw); 1442 if (ret_val) 1443 return ret_val; 1444 } 1445 1446 /* Make sure we have a valid PHY */ 1447 ret_val = em_detect_gig_phy(hw); 1448 if (ret_val) { 1449 DEBUGOUT("Error, did not detect valid phy.\n"); 1450 return ret_val; 1451 } 1452 DEBUGOUT1("Phy ID = %x \n", hw->phy_id); 1453 1454 /* Set PHY to class A mode (if necessary) */ 1455 ret_val = em_set_phy_mode(hw); 1456 if (ret_val) 1457 return ret_val; 1458 1459 if ((hw->mac_type == em_82545_rev_3) || 1460 (hw->mac_type == em_82546_rev_3)) { 1461 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1462 phy_data |= 0x00000008; 1463 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1464 } 1465 1466 if (hw->mac_type <= em_82543 || 1467 hw->mac_type == em_82541 || hw->mac_type == em_82547 || 1468 hw->mac_type == em_82541_rev_2 || hw->mac_type == em_82547_rev_2) 1469 hw->phy_reset_disable = FALSE; 1470 1471 return E1000_SUCCESS; 1472 } 1473 1474 1475 /******************************************************************** 1476 * Copper link setup for em_phy_igp series. 1477 * 1478 * hw - Struct containing variables accessed by shared code 1479 *********************************************************************/ 1480 static int32_t 1481 em_copper_link_igp_setup(struct em_hw *hw) 1482 { 1483 uint32_t led_ctrl; 1484 int32_t ret_val; 1485 uint16_t phy_data; 1486 1487 DEBUGFUNC("em_copper_link_igp_setup"); 1488 1489 if (hw->phy_reset_disable) 1490 return E1000_SUCCESS; 1491 1492 ret_val = em_phy_reset(hw); 1493 if (ret_val) { 1494 DEBUGOUT("Error Resetting the PHY\n"); 1495 return ret_val; 1496 } 1497 1498 /* Wait 15ms for MAC to configure PHY from eeprom settings */ 1499 msec_delay(15); 1500 if (hw->mac_type != em_ich8lan && hw->mac_type != em_ich9lan) { 1501 /* Configure activity LED after PHY reset */ 1502 led_ctrl = E1000_READ_REG(hw, LEDCTL); 1503 led_ctrl &= IGP_ACTIVITY_LED_MASK; 1504 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 1505 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 1506 } 1507 1508 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */ 1509 if (hw->phy_type == em_phy_igp) { 1510 /* disable lplu d3 during driver init */ 1511 ret_val = em_set_d3_lplu_state(hw, FALSE); 1512 if (ret_val) { 1513 DEBUGOUT("Error Disabling LPLU D3\n"); 1514 return ret_val; 1515 } 1516 } 1517 1518 /* disable lplu d0 during driver init */ 1519 ret_val = em_set_d0_lplu_state(hw, FALSE); 1520 if (ret_val) { 1521 DEBUGOUT("Error Disabling LPLU D0\n"); 1522 return ret_val; 1523 } 1524 /* Configure mdi-mdix settings */ 1525 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 1526 if (ret_val) 1527 return ret_val; 1528 1529 if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) { 1530 hw->dsp_config_state = em_dsp_config_disabled; 1531 /* Force MDI for earlier revs of the IGP PHY */ 1532 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | IGP01E1000_PSCR_FORCE_MDI_MDIX); 1533 hw->mdix = 1; 1534 1535 } else { 1536 hw->dsp_config_state = em_dsp_config_enabled; 1537 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 1538 1539 switch (hw->mdix) { 1540 case 1: 1541 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 1542 break; 1543 case 2: 1544 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; 1545 break; 1546 case 0: 1547 default: 1548 phy_data |= IGP01E1000_PSCR_AUTO_MDIX; 1549 break; 1550 } 1551 } 1552 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 1553 if (ret_val) 1554 return ret_val; 1555 1556 /* set auto-master slave resolution settings */ 1557 if (hw->autoneg) { 1558 em_ms_type phy_ms_setting = hw->master_slave; 1559 1560 if (hw->ffe_config_state == em_ffe_config_active) 1561 hw->ffe_config_state = em_ffe_config_enabled; 1562 1563 if (hw->dsp_config_state == em_dsp_config_activated) 1564 hw->dsp_config_state = em_dsp_config_enabled; 1565 1566 /* when autonegotiation advertisement is only 1000Mbps then we 1567 * should disable SmartSpeed and enable Auto MasterSlave 1568 * resolution as hardware default. */ 1569 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) { 1570 /* Disable SmartSpeed */ 1571 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 1572 &phy_data); 1573 if (ret_val) 1574 return ret_val; 1575 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1576 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 1577 phy_data); 1578 if (ret_val) 1579 return ret_val; 1580 /* Set auto Master/Slave resolution process */ 1581 ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); 1582 if (ret_val) 1583 return ret_val; 1584 phy_data &= ~CR_1000T_MS_ENABLE; 1585 ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); 1586 if (ret_val) 1587 return ret_val; 1588 } 1589 1590 ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); 1591 if (ret_val) 1592 return ret_val; 1593 1594 /* load defaults for future use */ 1595 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ? 1596 ((phy_data & CR_1000T_MS_VALUE) ? 1597 em_ms_force_master : 1598 em_ms_force_slave) : 1599 em_ms_auto; 1600 1601 switch (phy_ms_setting) { 1602 case em_ms_force_master: 1603 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 1604 break; 1605 case em_ms_force_slave: 1606 phy_data |= CR_1000T_MS_ENABLE; 1607 phy_data &= ~(CR_1000T_MS_VALUE); 1608 break; 1609 case em_ms_auto: 1610 phy_data &= ~CR_1000T_MS_ENABLE; 1611 break; 1612 default: 1613 break; 1614 } 1615 ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); 1616 if (ret_val) 1617 return ret_val; 1618 } 1619 1620 return E1000_SUCCESS; 1621 } 1622 1623 /******************************************************************** 1624 * Copper link setup for em_phy_gg82563 series. 1625 * 1626 * hw - Struct containing variables accessed by shared code 1627 *********************************************************************/ 1628 static int32_t 1629 em_copper_link_ggp_setup(struct em_hw *hw) 1630 { 1631 int32_t ret_val; 1632 uint16_t phy_data; 1633 uint32_t reg_data; 1634 1635 DEBUGFUNC("em_copper_link_ggp_setup"); 1636 1637 if (!hw->phy_reset_disable) { 1638 1639 /* Enable CRS on TX for half-duplex operation. */ 1640 ret_val = em_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 1641 &phy_data); 1642 if (ret_val) 1643 return ret_val; 1644 1645 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 1646 /* Use 25MHz for both link down and 1000BASE-T for Tx clock */ 1647 phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ; 1648 1649 ret_val = em_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 1650 phy_data); 1651 if (ret_val) 1652 return ret_val; 1653 1654 /* Options: 1655 * MDI/MDI-X = 0 (default) 1656 * 0 - Auto for all speeds 1657 * 1 - MDI mode 1658 * 2 - MDI-X mode 1659 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 1660 */ 1661 ret_val = em_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, &phy_data); 1662 if (ret_val) 1663 return ret_val; 1664 1665 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK; 1666 1667 switch (hw->mdix) { 1668 case 1: 1669 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI; 1670 break; 1671 case 2: 1672 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX; 1673 break; 1674 case 0: 1675 default: 1676 phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO; 1677 break; 1678 } 1679 1680 /* Options: 1681 * disable_polarity_correction = 0 (default) 1682 * Automatic Correction for Reversed Cable Polarity 1683 * 0 - Disabled 1684 * 1 - Enabled 1685 */ 1686 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 1687 if (hw->disable_polarity_correction == 1) 1688 phy_data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 1689 ret_val = em_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data); 1690 1691 if (ret_val) 1692 return ret_val; 1693 1694 /* SW Reset the PHY so all changes take effect */ 1695 ret_val = em_phy_reset(hw); 1696 if (ret_val) { 1697 DEBUGOUT("Error Resetting the PHY\n"); 1698 return ret_val; 1699 } 1700 } /* phy_reset_disable */ 1701 1702 if (hw->mac_type == em_80003es2lan) { 1703 /* Bypass RX and TX FIFO's */ 1704 ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL, 1705 E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS | 1706 E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS); 1707 if (ret_val) 1708 return ret_val; 1709 1710 ret_val = em_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, &phy_data); 1711 if (ret_val) 1712 return ret_val; 1713 1714 phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG; 1715 ret_val = em_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, phy_data); 1716 1717 if (ret_val) 1718 return ret_val; 1719 1720 reg_data = E1000_READ_REG(hw, CTRL_EXT); 1721 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK); 1722 E1000_WRITE_REG(hw, CTRL_EXT, reg_data); 1723 1724 ret_val = em_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, 1725 &phy_data); 1726 if (ret_val) 1727 return ret_val; 1728 1729 /* Do not init these registers when the HW is in IAMT mode, since the 1730 * firmware will have already initialized them. We only initialize 1731 * them if the HW is not in IAMT mode. 1732 */ 1733 if (em_check_mng_mode(hw) == FALSE) { 1734 /* Enable Electrical Idle on the PHY */ 1735 phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; 1736 ret_val = em_write_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, 1737 phy_data); 1738 if (ret_val) 1739 return ret_val; 1740 1741 ret_val = em_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1742 &phy_data); 1743 if (ret_val) 1744 return ret_val; 1745 1746 phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 1747 ret_val = em_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1748 phy_data); 1749 1750 if (ret_val) 1751 return ret_val; 1752 } 1753 1754 /* Workaround: Disable padding in Kumeran interface in the MAC 1755 * and in the PHY to avoid CRC errors. 1756 */ 1757 ret_val = em_read_phy_reg(hw, GG82563_PHY_INBAND_CTRL, 1758 &phy_data); 1759 if (ret_val) 1760 return ret_val; 1761 phy_data |= GG82563_ICR_DIS_PADDING; 1762 ret_val = em_write_phy_reg(hw, GG82563_PHY_INBAND_CTRL, 1763 phy_data); 1764 if (ret_val) 1765 return ret_val; 1766 } 1767 1768 return E1000_SUCCESS; 1769 } 1770 1771 /******************************************************************** 1772 * Copper link setup for em_phy_m88 series. 1773 * 1774 * hw - Struct containing variables accessed by shared code 1775 *********************************************************************/ 1776 static int32_t 1777 em_copper_link_mgp_setup(struct em_hw *hw) 1778 { 1779 int32_t ret_val; 1780 uint16_t phy_data; 1781 1782 DEBUGFUNC("em_copper_link_mgp_setup"); 1783 1784 if (hw->phy_reset_disable) 1785 return E1000_SUCCESS; 1786 1787 /* Enable CRS on TX. This must be set for half-duplex operation. */ 1788 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1789 if (ret_val) 1790 return ret_val; 1791 1792 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 1793 1794 /* Options: 1795 * MDI/MDI-X = 0 (default) 1796 * 0 - Auto for all speeds 1797 * 1 - MDI mode 1798 * 2 - MDI-X mode 1799 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 1800 */ 1801 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1802 1803 switch (hw->mdix) { 1804 case 1: 1805 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 1806 break; 1807 case 2: 1808 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 1809 break; 1810 case 3: 1811 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 1812 break; 1813 case 0: 1814 default: 1815 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 1816 break; 1817 } 1818 1819 /* Options: 1820 * disable_polarity_correction = 0 (default) 1821 * Automatic Correction for Reversed Cable Polarity 1822 * 0 - Disabled 1823 * 1 - Enabled 1824 */ 1825 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 1826 if (hw->disable_polarity_correction == 1) 1827 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 1828 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1829 if (ret_val) 1830 return ret_val; 1831 1832 if (hw->phy_revision < M88E1011_I_REV_4) { 1833 /* Force TX_CLK in the Extended PHY Specific Control Register 1834 * to 25MHz clock. 1835 */ 1836 ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); 1837 if (ret_val) 1838 return ret_val; 1839 1840 phy_data |= M88E1000_EPSCR_TX_CLK_25; 1841 1842 if ((hw->phy_revision == E1000_REVISION_2) && 1843 (hw->phy_id == M88E1111_I_PHY_ID)) { 1844 /* Vidalia Phy, set the downshift counter to 5x */ 1845 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK); 1846 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; 1847 ret_val = em_write_phy_reg(hw, 1848 M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 1849 if (ret_val) 1850 return ret_val; 1851 } else { 1852 /* Configure Master and Slave downshift values */ 1853 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 1854 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 1855 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 1856 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 1857 ret_val = em_write_phy_reg(hw, 1858 M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 1859 if (ret_val) 1860 return ret_val; 1861 } 1862 } 1863 1864 /* SW Reset the PHY so all changes take effect */ 1865 ret_val = em_phy_reset(hw); 1866 if (ret_val) { 1867 DEBUGOUT("Error Resetting the PHY\n"); 1868 return ret_val; 1869 } 1870 1871 return E1000_SUCCESS; 1872 } 1873 1874 /******************************************************************** 1875 * Setup auto-negotiation and flow control advertisements, 1876 * and then perform auto-negotiation. 1877 * 1878 * hw - Struct containing variables accessed by shared code 1879 *********************************************************************/ 1880 static int32_t 1881 em_copper_link_autoneg(struct em_hw *hw) 1882 { 1883 int32_t ret_val; 1884 uint16_t phy_data; 1885 1886 DEBUGFUNC("em_copper_link_autoneg"); 1887 1888 /* Perform some bounds checking on the hw->autoneg_advertised 1889 * parameter. If this variable is zero, then set it to the default. 1890 */ 1891 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT; 1892 1893 /* If autoneg_advertised is zero, we assume it was not defaulted 1894 * by the calling code so we set to advertise full capability. 1895 */ 1896 if (hw->autoneg_advertised == 0) 1897 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 1898 1899 /* IFE phy only supports 10/100 */ 1900 if (hw->phy_type == em_phy_ife) 1901 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL; 1902 1903 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); 1904 ret_val = em_phy_setup_autoneg(hw); 1905 if (ret_val) { 1906 DEBUGOUT("Error Setting up Auto-Negotiation\n"); 1907 return ret_val; 1908 } 1909 DEBUGOUT("Restarting Auto-Neg\n"); 1910 1911 /* Restart auto-negotiation by setting the Auto Neg Enable bit and 1912 * the Auto Neg Restart bit in the PHY control register. 1913 */ 1914 ret_val = em_read_phy_reg(hw, PHY_CTRL, &phy_data); 1915 if (ret_val) 1916 return ret_val; 1917 1918 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 1919 ret_val = em_write_phy_reg(hw, PHY_CTRL, phy_data); 1920 if (ret_val) 1921 return ret_val; 1922 1923 /* Does the user want to wait for Auto-Neg to complete here, or 1924 * check at a later time (for example, callback routine). 1925 */ 1926 if (hw->wait_autoneg_complete) { 1927 ret_val = em_wait_autoneg(hw); 1928 if (ret_val) { 1929 DEBUGOUT("Error while waiting for autoneg to complete\n"); 1930 return ret_val; 1931 } 1932 } 1933 1934 hw->get_link_status = TRUE; 1935 1936 return E1000_SUCCESS; 1937 } 1938 1939 /****************************************************************************** 1940 * Config the MAC and the PHY after link is up. 1941 * 1) Set up the MAC to the current PHY speed/duplex 1942 * if we are on 82543. If we 1943 * are on newer silicon, we only need to configure 1944 * collision distance in the Transmit Control Register. 1945 * 2) Set up flow control on the MAC to that established with 1946 * the link partner. 1947 * 3) Config DSP to improve Gigabit link quality for some PHY revisions. 1948 * 1949 * hw - Struct containing variables accessed by shared code 1950 ******************************************************************************/ 1951 static int32_t 1952 em_copper_link_postconfig(struct em_hw *hw) 1953 { 1954 int32_t ret_val; 1955 DEBUGFUNC("em_copper_link_postconfig"); 1956 1957 if (hw->mac_type >= em_82544) { 1958 em_config_collision_dist(hw); 1959 } else { 1960 ret_val = em_config_mac_to_phy(hw); 1961 if (ret_val) { 1962 DEBUGOUT("Error configuring MAC to PHY settings\n"); 1963 return ret_val; 1964 } 1965 } 1966 ret_val = em_config_fc_after_link_up(hw); 1967 if (ret_val) { 1968 DEBUGOUT("Error Configuring Flow Control\n"); 1969 return ret_val; 1970 } 1971 1972 /* Config DSP to improve Giga link quality */ 1973 if (hw->phy_type == em_phy_igp) { 1974 ret_val = em_config_dsp_after_link_change(hw, TRUE); 1975 if (ret_val) { 1976 DEBUGOUT("Error Configuring DSP after link up\n"); 1977 return ret_val; 1978 } 1979 } 1980 1981 return E1000_SUCCESS; 1982 } 1983 1984 /****************************************************************************** 1985 * Detects which PHY is present and setup the speed and duplex 1986 * 1987 * hw - Struct containing variables accessed by shared code 1988 ******************************************************************************/ 1989 static int32_t 1990 em_setup_copper_link(struct em_hw *hw) 1991 { 1992 int32_t ret_val; 1993 uint16_t i; 1994 uint16_t phy_data; 1995 uint16_t reg_data; 1996 1997 DEBUGFUNC("em_setup_copper_link"); 1998 1999 switch (hw->mac_type) { 2000 case em_80003es2lan: 2001 case em_ich8lan: 2002 case em_ich9lan: 2003 /* Set the mac to wait the maximum time between each 2004 * iteration and increase the max iterations when 2005 * polling the phy; this fixes erroneous timeouts at 10Mbps. */ 2006 ret_val = em_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF); 2007 if (ret_val) 2008 return ret_val; 2009 ret_val = em_read_kmrn_reg(hw, GG82563_REG(0x34, 9), ®_data); 2010 if (ret_val) 2011 return ret_val; 2012 reg_data |= 0x3F; 2013 ret_val = em_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data); 2014 if (ret_val) 2015 return ret_val; 2016 default: 2017 break; 2018 } 2019 2020 /* Check if it is a valid PHY and set PHY mode if necessary. */ 2021 ret_val = em_copper_link_preconfig(hw); 2022 if (ret_val) 2023 return ret_val; 2024 2025 switch (hw->mac_type) { 2026 case em_80003es2lan: 2027 /* Kumeran registers are written-only */ 2028 reg_data = E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT; 2029 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING; 2030 ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_INB_CTRL, 2031 reg_data); 2032 if (ret_val) 2033 return ret_val; 2034 break; 2035 default: 2036 break; 2037 } 2038 2039 if (hw->phy_type == em_phy_igp || 2040 hw->phy_type == em_phy_igp_3 || 2041 hw->phy_type == em_phy_igp_2) { 2042 ret_val = em_copper_link_igp_setup(hw); 2043 if (ret_val) 2044 return ret_val; 2045 } else if (hw->phy_type == em_phy_m88) { 2046 ret_val = em_copper_link_mgp_setup(hw); 2047 if (ret_val) 2048 return ret_val; 2049 } else if (hw->phy_type == em_phy_gg82563) { 2050 ret_val = em_copper_link_ggp_setup(hw); 2051 if (ret_val) 2052 return ret_val; 2053 } 2054 2055 if (hw->autoneg) { 2056 /* Setup autoneg and flow control advertisement 2057 * and perform autonegotiation */ 2058 ret_val = em_copper_link_autoneg(hw); 2059 if (ret_val) 2060 return ret_val; 2061 } else { 2062 /* PHY will be set to 10H, 10F, 100H,or 100F 2063 * depending on value from forced_speed_duplex. */ 2064 DEBUGOUT("Forcing speed and duplex\n"); 2065 ret_val = em_phy_force_speed_duplex(hw); 2066 if (ret_val) { 2067 DEBUGOUT("Error Forcing Speed and Duplex\n"); 2068 return ret_val; 2069 } 2070 } 2071 2072 /* Check link status. Wait up to 100 microseconds for link to become 2073 * valid. 2074 */ 2075 for (i = 0; i < 10; i++) { 2076 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 2077 if (ret_val) 2078 return ret_val; 2079 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 2080 if (ret_val) 2081 return ret_val; 2082 2083 if (phy_data & MII_SR_LINK_STATUS) { 2084 /* Config the MAC and PHY after link is up */ 2085 ret_val = em_copper_link_postconfig(hw); 2086 if (ret_val) 2087 return ret_val; 2088 2089 DEBUGOUT("Valid link established!!!\n"); 2090 return E1000_SUCCESS; 2091 } 2092 usec_delay(10); 2093 } 2094 2095 DEBUGOUT("Unable to establish link!!!\n"); 2096 return E1000_SUCCESS; 2097 } 2098 2099 /****************************************************************************** 2100 * Configure the MAC-to-PHY interface for 10/100Mbps 2101 * 2102 * hw - Struct containing variables accessed by shared code 2103 ******************************************************************************/ 2104 static int32_t 2105 em_configure_kmrn_for_10_100(struct em_hw *hw, uint16_t duplex) 2106 { 2107 int32_t ret_val = E1000_SUCCESS; 2108 uint32_t tipg; 2109 uint16_t reg_data; 2110 2111 DEBUGFUNC("em_configure_kmrn_for_10_100"); 2112 2113 reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT; 2114 ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL, 2115 reg_data); 2116 if (ret_val) 2117 return ret_val; 2118 2119 /* Configure Transmit Inter-Packet Gap */ 2120 tipg = E1000_READ_REG(hw, TIPG); 2121 tipg &= ~E1000_TIPG_IPGT_MASK; 2122 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100; 2123 E1000_WRITE_REG(hw, TIPG, tipg); 2124 2125 ret_val = em_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); 2126 2127 if (ret_val) 2128 return ret_val; 2129 2130 if (duplex == HALF_DUPLEX) 2131 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER; 2132 else 2133 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 2134 2135 ret_val = em_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 2136 2137 return ret_val; 2138 } 2139 2140 static int32_t 2141 em_configure_kmrn_for_1000(struct em_hw *hw) 2142 { 2143 int32_t ret_val = E1000_SUCCESS; 2144 uint16_t reg_data; 2145 uint32_t tipg; 2146 2147 DEBUGFUNC("em_configure_kmrn_for_1000"); 2148 2149 reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT; 2150 ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL, 2151 reg_data); 2152 if (ret_val) 2153 return ret_val; 2154 2155 /* Configure Transmit Inter-Packet Gap */ 2156 tipg = E1000_READ_REG(hw, TIPG); 2157 tipg &= ~E1000_TIPG_IPGT_MASK; 2158 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; 2159 E1000_WRITE_REG(hw, TIPG, tipg); 2160 2161 ret_val = em_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); 2162 2163 if (ret_val) 2164 return ret_val; 2165 2166 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 2167 ret_val = em_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 2168 2169 return ret_val; 2170 } 2171 2172 /****************************************************************************** 2173 * Configures PHY autoneg and flow control advertisement settings 2174 * 2175 * hw - Struct containing variables accessed by shared code 2176 ******************************************************************************/ 2177 int32_t 2178 em_phy_setup_autoneg(struct em_hw *hw) 2179 { 2180 int32_t ret_val; 2181 uint16_t mii_autoneg_adv_reg; 2182 uint16_t mii_1000t_ctrl_reg; 2183 2184 DEBUGFUNC("em_phy_setup_autoneg"); 2185 2186 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 2187 ret_val = em_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 2188 if (ret_val) 2189 return ret_val; 2190 2191 if (hw->phy_type != em_phy_ife) { 2192 /* Read the MII 1000Base-T Control Register (Address 9). */ 2193 ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg); 2194 if (ret_val) 2195 return ret_val; 2196 } else 2197 mii_1000t_ctrl_reg=0; 2198 2199 /* Need to parse both autoneg_advertised and fc and set up 2200 * the appropriate PHY registers. First we will parse for 2201 * autoneg_advertised software override. Since we can advertise 2202 * a plethora of combinations, we need to check each bit 2203 * individually. 2204 */ 2205 2206 /* First we clear all the 10/100 mb speed bits in the Auto-Neg 2207 * Advertisement Register (Address 4) and the 1000 mb speed bits in 2208 * the 1000Base-T Control Register (Address 9). 2209 */ 2210 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK; 2211 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK; 2212 2213 DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised); 2214 2215 /* Do we want to advertise 10 Mb Half Duplex? */ 2216 if (hw->autoneg_advertised & ADVERTISE_10_HALF) { 2217 DEBUGOUT("Advertise 10mb Half duplex\n"); 2218 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 2219 } 2220 2221 /* Do we want to advertise 10 Mb Full Duplex? */ 2222 if (hw->autoneg_advertised & ADVERTISE_10_FULL) { 2223 DEBUGOUT("Advertise 10mb Full duplex\n"); 2224 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 2225 } 2226 2227 /* Do we want to advertise 100 Mb Half Duplex? */ 2228 if (hw->autoneg_advertised & ADVERTISE_100_HALF) { 2229 DEBUGOUT("Advertise 100mb Half duplex\n"); 2230 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 2231 } 2232 2233 /* Do we want to advertise 100 Mb Full Duplex? */ 2234 if (hw->autoneg_advertised & ADVERTISE_100_FULL) { 2235 DEBUGOUT("Advertise 100mb Full duplex\n"); 2236 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 2237 } 2238 2239 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 2240 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) { 2241 DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n"); 2242 } 2243 2244 /* Do we want to advertise 1000 Mb Full Duplex? */ 2245 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) { 2246 DEBUGOUT("Advertise 1000mb Full duplex\n"); 2247 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 2248 if (hw->phy_type == em_phy_ife) { 2249 DEBUGOUT("em_phy_ife is a 10/100 PHY. Gigabit speed is not supported.\n"); 2250 } 2251 } 2252 2253 /* Check for a software override of the flow control settings, and 2254 * setup the PHY advertisement registers accordingly. If 2255 * auto-negotiation is enabled, then software will have to set the 2256 * "PAUSE" bits to the correct value in the Auto-Negotiation 2257 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation. 2258 * 2259 * The possible values of the "fc" parameter are: 2260 * 0: Flow control is completely disabled 2261 * 1: Rx flow control is enabled (we can receive pause frames 2262 * but not send pause frames). 2263 * 2: Tx flow control is enabled (we can send pause frames 2264 * but we do not support receiving pause frames). 2265 * 3: Both Rx and TX flow control (symmetric) are enabled. 2266 * other: No software override. The flow control configuration 2267 * in the EEPROM is used. 2268 */ 2269 switch (hw->fc) { 2270 case E1000_FC_NONE: /* 0 */ 2271 /* Flow control (RX & TX) is completely disabled by a 2272 * software over-ride. 2273 */ 2274 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 2275 break; 2276 case E1000_FC_RX_PAUSE: /* 1 */ 2277 /* RX Flow control is enabled, and TX Flow control is 2278 * disabled, by a software over-ride. 2279 */ 2280 /* Since there really isn't a way to advertise that we are 2281 * capable of RX Pause ONLY, we will advertise that we 2282 * support both symmetric and asymmetric RX PAUSE. Later 2283 * (in em_config_fc_after_link_up) we will disable the 2284 *hw's ability to send PAUSE frames. 2285 */ 2286 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 2287 break; 2288 case E1000_FC_TX_PAUSE: /* 2 */ 2289 /* TX Flow control is enabled, and RX Flow control is 2290 * disabled, by a software over-ride. 2291 */ 2292 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 2293 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 2294 break; 2295 case E1000_FC_FULL: /* 3 */ 2296 /* Flow control (both RX and TX) is enabled by a software 2297 * over-ride. 2298 */ 2299 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 2300 break; 2301 default: 2302 DEBUGOUT("Flow control param set incorrectly\n"); 2303 return -E1000_ERR_CONFIG; 2304 } 2305 2306 ret_val = em_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 2307 if (ret_val) 2308 return ret_val; 2309 2310 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 2311 2312 if (hw->phy_type != em_phy_ife) { 2313 ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg); 2314 if (ret_val) 2315 return ret_val; 2316 } 2317 2318 return E1000_SUCCESS; 2319 } 2320 2321 /****************************************************************************** 2322 * Force PHY speed and duplex settings to hw->forced_speed_duplex 2323 * 2324 * hw - Struct containing variables accessed by shared code 2325 ******************************************************************************/ 2326 static int32_t 2327 em_phy_force_speed_duplex(struct em_hw *hw) 2328 { 2329 uint32_t ctrl; 2330 int32_t ret_val; 2331 uint16_t mii_ctrl_reg; 2332 uint16_t mii_status_reg; 2333 uint16_t phy_data; 2334 uint16_t i; 2335 2336 DEBUGFUNC("em_phy_force_speed_duplex"); 2337 2338 /* Turn off Flow control if we are forcing speed and duplex. */ 2339 hw->fc = E1000_FC_NONE; 2340 2341 DEBUGOUT1("hw->fc = %d\n", hw->fc); 2342 2343 /* Read the Device Control Register. */ 2344 ctrl = E1000_READ_REG(hw, CTRL); 2345 2346 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */ 2347 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 2348 ctrl &= ~(DEVICE_SPEED_MASK); 2349 2350 /* Clear the Auto Speed Detect Enable bit. */ 2351 ctrl &= ~E1000_CTRL_ASDE; 2352 2353 /* Read the MII Control Register. */ 2354 ret_val = em_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg); 2355 if (ret_val) 2356 return ret_val; 2357 2358 /* We need to disable autoneg in order to force link and duplex. */ 2359 2360 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN; 2361 2362 /* Are we forcing Full or Half Duplex? */ 2363 if (hw->forced_speed_duplex == em_100_full || 2364 hw->forced_speed_duplex == em_10_full) { 2365 /* We want to force full duplex so we SET the full duplex bits in the 2366 * Device and MII Control Registers. 2367 */ 2368 ctrl |= E1000_CTRL_FD; 2369 mii_ctrl_reg |= MII_CR_FULL_DUPLEX; 2370 DEBUGOUT("Full Duplex\n"); 2371 } else { 2372 /* We want to force half duplex so we CLEAR the full duplex bits in 2373 * the Device and MII Control Registers. 2374 */ 2375 ctrl &= ~E1000_CTRL_FD; 2376 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX; 2377 DEBUGOUT("Half Duplex\n"); 2378 } 2379 2380 /* Are we forcing 100Mbps??? */ 2381 if (hw->forced_speed_duplex == em_100_full || 2382 hw->forced_speed_duplex == em_100_half) { 2383 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */ 2384 ctrl |= E1000_CTRL_SPD_100; 2385 mii_ctrl_reg |= MII_CR_SPEED_100; 2386 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); 2387 DEBUGOUT("Forcing 100mb "); 2388 } else { 2389 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */ 2390 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 2391 mii_ctrl_reg |= MII_CR_SPEED_10; 2392 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); 2393 DEBUGOUT("Forcing 10mb "); 2394 } 2395 2396 em_config_collision_dist(hw); 2397 2398 /* Write the configured values back to the Device Control Reg. */ 2399 E1000_WRITE_REG(hw, CTRL, ctrl); 2400 2401 if ((hw->phy_type == em_phy_m88) || 2402 (hw->phy_type == em_phy_gg82563)) { 2403 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 2404 if (ret_val) 2405 return ret_val; 2406 2407 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI 2408 * forced whenever speed are duplex are forced. 2409 */ 2410 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 2411 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 2412 if (ret_val) 2413 return ret_val; 2414 2415 DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data); 2416 2417 /* Need to reset the PHY or these changes will be ignored */ 2418 mii_ctrl_reg |= MII_CR_RESET; 2419 /* Disable MDI-X support for 10/100 */ 2420 } else if (hw->phy_type == em_phy_ife) { 2421 ret_val = em_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data); 2422 if (ret_val) 2423 return ret_val; 2424 2425 phy_data &= ~IFE_PMC_AUTO_MDIX; 2426 phy_data &= ~IFE_PMC_FORCE_MDIX; 2427 2428 ret_val = em_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, phy_data); 2429 if (ret_val) 2430 return ret_val; 2431 } else { 2432 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI 2433 * forced whenever speed or duplex are forced. 2434 */ 2435 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 2436 if (ret_val) 2437 return ret_val; 2438 2439 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 2440 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 2441 2442 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 2443 if (ret_val) 2444 return ret_val; 2445 } 2446 2447 /* Write back the modified PHY MII control register. */ 2448 ret_val = em_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg); 2449 if (ret_val) 2450 return ret_val; 2451 2452 usec_delay(1); 2453 2454 /* The wait_autoneg_complete flag may be a little misleading here. 2455 * Since we are forcing speed and duplex, Auto-Neg is not enabled. 2456 * But we do want to delay for a period while forcing only so we 2457 * don't generate false No Link messages. So we will wait here 2458 * only if the user has set wait_autoneg_complete to 1, which is 2459 * the default. 2460 */ 2461 if (hw->wait_autoneg_complete) { 2462 /* We will wait for autoneg to complete. */ 2463 DEBUGOUT("Waiting for forced speed/duplex link.\n"); 2464 mii_status_reg = 0; 2465 2466 /* We will wait for autoneg to complete or 4.5 seconds to expire. */ 2467 for (i = PHY_FORCE_TIME; i > 0; i--) { 2468 /* Read the MII Status Register and wait for Auto-Neg Complete bit 2469 * to be set. 2470 */ 2471 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 2472 if (ret_val) 2473 return ret_val; 2474 2475 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 2476 if (ret_val) 2477 return ret_val; 2478 2479 if (mii_status_reg & MII_SR_LINK_STATUS) break; 2480 msec_delay(100); 2481 } 2482 if ((i == 0) && 2483 ((hw->phy_type == em_phy_m88) || 2484 (hw->phy_type == em_phy_gg82563))) { 2485 /* We didn't get link. Reset the DSP and wait again for link. */ 2486 ret_val = em_phy_reset_dsp(hw); 2487 if (ret_val) { 2488 DEBUGOUT("Error Resetting PHY DSP\n"); 2489 return ret_val; 2490 } 2491 } 2492 /* This loop will early-out if the link condition has been met. */ 2493 for (i = PHY_FORCE_TIME; i > 0; i--) { 2494 if (mii_status_reg & MII_SR_LINK_STATUS) break; 2495 msec_delay(100); 2496 /* Read the MII Status Register and wait for Auto-Neg Complete bit 2497 * to be set. 2498 */ 2499 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 2500 if (ret_val) 2501 return ret_val; 2502 2503 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 2504 if (ret_val) 2505 return ret_val; 2506 } 2507 } 2508 2509 if (hw->phy_type == em_phy_m88) { 2510 /* Because we reset the PHY above, we need to re-force TX_CLK in the 2511 * Extended PHY Specific Control Register to 25MHz clock. This value 2512 * defaults back to a 2.5MHz clock when the PHY is reset. 2513 */ 2514 ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); 2515 if (ret_val) 2516 return ret_val; 2517 2518 phy_data |= M88E1000_EPSCR_TX_CLK_25; 2519 ret_val = em_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 2520 if (ret_val) 2521 return ret_val; 2522 2523 /* In addition, because of the s/w reset above, we need to enable CRS on 2524 * TX. This must be set for both full and half duplex operation. 2525 */ 2526 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 2527 if (ret_val) 2528 return ret_val; 2529 2530 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 2531 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 2532 if (ret_val) 2533 return ret_val; 2534 2535 if ((hw->mac_type == em_82544 || hw->mac_type == em_82543) && 2536 (!hw->autoneg) && (hw->forced_speed_duplex == em_10_full || 2537 hw->forced_speed_duplex == em_10_half)) { 2538 ret_val = em_polarity_reversal_workaround(hw); 2539 if (ret_val) 2540 return ret_val; 2541 } 2542 } else if (hw->phy_type == em_phy_gg82563) { 2543 /* The TX_CLK of the Extended PHY Specific Control Register defaults 2544 * to 2.5MHz on a reset. We need to re-force it back to 25MHz, if 2545 * we're not in a forced 10/duplex configuration. */ 2546 ret_val = em_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data); 2547 if (ret_val) 2548 return ret_val; 2549 2550 phy_data &= ~GG82563_MSCR_TX_CLK_MASK; 2551 if ((hw->forced_speed_duplex == em_10_full) || 2552 (hw->forced_speed_duplex == em_10_half)) 2553 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ; 2554 else 2555 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25MHZ; 2556 2557 /* Also due to the reset, we need to enable CRS on Tx. */ 2558 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 2559 2560 ret_val = em_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data); 2561 if (ret_val) 2562 return ret_val; 2563 } 2564 return E1000_SUCCESS; 2565 } 2566 2567 /****************************************************************************** 2568 * Sets the collision distance in the Transmit Control register 2569 * 2570 * hw - Struct containing variables accessed by shared code 2571 * 2572 * Link should have been established previously. Reads the speed and duplex 2573 * information from the Device Status register. 2574 ******************************************************************************/ 2575 void 2576 em_config_collision_dist(struct em_hw *hw) 2577 { 2578 uint32_t tctl, coll_dist; 2579 2580 DEBUGFUNC("em_config_collision_dist"); 2581 2582 if (hw->mac_type < em_82543) 2583 coll_dist = E1000_COLLISION_DISTANCE_82542; 2584 else 2585 coll_dist = E1000_COLLISION_DISTANCE; 2586 2587 tctl = E1000_READ_REG(hw, TCTL); 2588 2589 tctl &= ~E1000_TCTL_COLD; 2590 tctl |= coll_dist << E1000_COLD_SHIFT; 2591 2592 E1000_WRITE_REG(hw, TCTL, tctl); 2593 E1000_WRITE_FLUSH(hw); 2594 } 2595 2596 /****************************************************************************** 2597 * Sets MAC speed and duplex settings to reflect the those in the PHY 2598 * 2599 * hw - Struct containing variables accessed by shared code 2600 * mii_reg - data to write to the MII control register 2601 * 2602 * The contents of the PHY register containing the needed information need to 2603 * be passed in. 2604 ******************************************************************************/ 2605 static int32_t 2606 em_config_mac_to_phy(struct em_hw *hw) 2607 { 2608 uint32_t ctrl; 2609 int32_t ret_val; 2610 uint16_t phy_data; 2611 2612 DEBUGFUNC("em_config_mac_to_phy"); 2613 2614 /* 82544 or newer MAC, Auto Speed Detection takes care of 2615 * MAC speed/duplex configuration.*/ 2616 if (hw->mac_type >= em_82544) 2617 return E1000_SUCCESS; 2618 2619 /* Read the Device Control Register and set the bits to Force Speed 2620 * and Duplex. 2621 */ 2622 ctrl = E1000_READ_REG(hw, CTRL); 2623 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 2624 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); 2625 2626 /* Set up duplex in the Device Control and Transmit Control 2627 * registers depending on negotiated values. 2628 */ 2629 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 2630 if (ret_val) 2631 return ret_val; 2632 2633 if (phy_data & M88E1000_PSSR_DPLX) 2634 ctrl |= E1000_CTRL_FD; 2635 else 2636 ctrl &= ~E1000_CTRL_FD; 2637 2638 em_config_collision_dist(hw); 2639 2640 /* Set up speed in the Device Control register depending on 2641 * negotiated values. 2642 */ 2643 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) 2644 ctrl |= E1000_CTRL_SPD_1000; 2645 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) 2646 ctrl |= E1000_CTRL_SPD_100; 2647 2648 /* Write the configured values back to the Device Control Reg. */ 2649 E1000_WRITE_REG(hw, CTRL, ctrl); 2650 return E1000_SUCCESS; 2651 } 2652 2653 /****************************************************************************** 2654 * Forces the MAC's flow control settings. 2655 * 2656 * hw - Struct containing variables accessed by shared code 2657 * 2658 * Sets the TFCE and RFCE bits in the device control register to reflect 2659 * the adapter settings. TFCE and RFCE need to be explicitly set by 2660 * software when a Copper PHY is used because autonegotiation is managed 2661 * by the PHY rather than the MAC. Software must also configure these 2662 * bits when link is forced on a fiber connection. 2663 *****************************************************************************/ 2664 int32_t 2665 em_force_mac_fc(struct em_hw *hw) 2666 { 2667 uint32_t ctrl; 2668 2669 DEBUGFUNC("em_force_mac_fc"); 2670 2671 /* Get the current configuration of the Device Control Register */ 2672 ctrl = E1000_READ_REG(hw, CTRL); 2673 2674 /* Because we didn't get link via the internal auto-negotiation 2675 * mechanism (we either forced link or we got link via PHY 2676 * auto-neg), we have to manually enable/disable transmit an 2677 * receive flow control. 2678 * 2679 * The "Case" statement below enables/disable flow control 2680 * according to the "hw->fc" parameter. 2681 * 2682 * The possible values of the "fc" parameter are: 2683 * 0: Flow control is completely disabled 2684 * 1: Rx flow control is enabled (we can receive pause 2685 * frames but not send pause frames). 2686 * 2: Tx flow control is enabled (we can send pause frames 2687 * frames but we do not receive pause frames). 2688 * 3: Both Rx and TX flow control (symmetric) is enabled. 2689 * other: No other values should be possible at this point. 2690 */ 2691 2692 switch (hw->fc) { 2693 case E1000_FC_NONE: 2694 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 2695 break; 2696 case E1000_FC_RX_PAUSE: 2697 ctrl &= (~E1000_CTRL_TFCE); 2698 ctrl |= E1000_CTRL_RFCE; 2699 break; 2700 case E1000_FC_TX_PAUSE: 2701 ctrl &= (~E1000_CTRL_RFCE); 2702 ctrl |= E1000_CTRL_TFCE; 2703 break; 2704 case E1000_FC_FULL: 2705 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 2706 break; 2707 default: 2708 DEBUGOUT("Flow control param set incorrectly\n"); 2709 return -E1000_ERR_CONFIG; 2710 } 2711 2712 /* Disable TX Flow Control for 82542 (rev 2.0) */ 2713 if (hw->mac_type == em_82542_rev2_0) 2714 ctrl &= (~E1000_CTRL_TFCE); 2715 2716 E1000_WRITE_REG(hw, CTRL, ctrl); 2717 return E1000_SUCCESS; 2718 } 2719 2720 /****************************************************************************** 2721 * Configures flow control settings after link is established 2722 * 2723 * hw - Struct containing variables accessed by shared code 2724 * 2725 * Should be called immediately after a valid link has been established. 2726 * Forces MAC flow control settings if link was forced. When in MII/GMII mode 2727 * and autonegotiation is enabled, the MAC flow control settings will be set 2728 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE 2729 * and RFCE bits will be automaticaly set to the negotiated flow control mode. 2730 *****************************************************************************/ 2731 STATIC int32_t 2732 em_config_fc_after_link_up(struct em_hw *hw) 2733 { 2734 int32_t ret_val; 2735 uint16_t mii_status_reg; 2736 uint16_t mii_nway_adv_reg; 2737 uint16_t mii_nway_lp_ability_reg; 2738 uint16_t speed; 2739 uint16_t duplex; 2740 2741 DEBUGFUNC("em_config_fc_after_link_up"); 2742 2743 /* Check for the case where we have fiber media and auto-neg failed 2744 * so we had to force link. In this case, we need to force the 2745 * configuration of the MAC to match the "fc" parameter. 2746 */ 2747 if (((hw->media_type == em_media_type_fiber) && (hw->autoneg_failed)) || 2748 ((hw->media_type == em_media_type_internal_serdes) && 2749 (hw->autoneg_failed)) || 2750 ((hw->media_type == em_media_type_copper) && (!hw->autoneg))) { 2751 ret_val = em_force_mac_fc(hw); 2752 if (ret_val) { 2753 DEBUGOUT("Error forcing flow control settings\n"); 2754 return ret_val; 2755 } 2756 } 2757 2758 /* Check for the case where we have copper media and auto-neg is 2759 * enabled. In this case, we need to check and see if Auto-Neg 2760 * has completed, and if so, how the PHY and link partner has 2761 * flow control configured. 2762 */ 2763 if ((hw->media_type == em_media_type_copper) && hw->autoneg) { 2764 /* Read the MII Status Register and check to see if AutoNeg 2765 * has completed. We read this twice because this reg has 2766 * some "sticky" (latched) bits. 2767 */ 2768 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 2769 if (ret_val) 2770 return ret_val; 2771 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 2772 if (ret_val) 2773 return ret_val; 2774 2775 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) { 2776 /* The AutoNeg process has completed, so we now need to 2777 * read both the Auto Negotiation Advertisement Register 2778 * (Address 4) and the Auto_Negotiation Base Page Ability 2779 * Register (Address 5) to determine how flow control was 2780 * negotiated. 2781 */ 2782 ret_val = em_read_phy_reg(hw, PHY_AUTONEG_ADV, 2783 &mii_nway_adv_reg); 2784 if (ret_val) 2785 return ret_val; 2786 ret_val = em_read_phy_reg(hw, PHY_LP_ABILITY, 2787 &mii_nway_lp_ability_reg); 2788 if (ret_val) 2789 return ret_val; 2790 2791 /* Two bits in the Auto Negotiation Advertisement Register 2792 * (Address 4) and two bits in the Auto Negotiation Base 2793 * Page Ability Register (Address 5) determine flow control 2794 * for both the PHY and the link partner. The following 2795 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 2796 * 1999, describes these PAUSE resolution bits and how flow 2797 * control is determined based upon these settings. 2798 * NOTE: DC = Don't Care 2799 * 2800 * LOCAL DEVICE | LINK PARTNER 2801 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 2802 *-------|---------|-------|---------|-------------------- 2803 * 0 | 0 | DC | DC | em_fc_none 2804 * 0 | 1 | 0 | DC | em_fc_none 2805 * 0 | 1 | 1 | 0 | em_fc_none 2806 * 0 | 1 | 1 | 1 | em_fc_tx_pause 2807 * 1 | 0 | 0 | DC | em_fc_none 2808 * 1 | DC | 1 | DC | em_fc_full 2809 * 1 | 1 | 0 | 0 | em_fc_none 2810 * 1 | 1 | 0 | 1 | em_fc_rx_pause 2811 * 2812 */ 2813 /* Are both PAUSE bits set to 1? If so, this implies 2814 * Symmetric Flow Control is enabled at both ends. The 2815 * ASM_DIR bits are irrelevant per the spec. 2816 * 2817 * For Symmetric Flow Control: 2818 * 2819 * LOCAL DEVICE | LINK PARTNER 2820 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 2821 *-------|---------|-------|---------|-------------------- 2822 * 1 | DC | 1 | DC | em_fc_full 2823 * 2824 */ 2825 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 2826 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 2827 /* Now we need to check if the user selected RX ONLY 2828 * of pause frames. In this case, we had to advertise 2829 * FULL flow control because we could not advertise RX 2830 * ONLY. Hence, we must now check to see if we need to 2831 * turn OFF the TRANSMISSION of PAUSE frames. 2832 */ 2833 if (hw->original_fc == E1000_FC_FULL) { 2834 hw->fc = E1000_FC_FULL; 2835 DEBUGOUT("Flow Control = FULL.\n"); 2836 } else { 2837 hw->fc = E1000_FC_RX_PAUSE; 2838 DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); 2839 } 2840 } 2841 /* For receiving PAUSE frames ONLY. 2842 * 2843 * LOCAL DEVICE | LINK PARTNER 2844 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 2845 *-------|---------|-------|---------|-------------------- 2846 * 0 | 1 | 1 | 1 | em_fc_tx_pause 2847 * 2848 */ 2849 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 2850 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 2851 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 2852 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 2853 hw->fc = E1000_FC_TX_PAUSE; 2854 DEBUGOUT("Flow Control = TX PAUSE frames only.\n"); 2855 } 2856 /* For transmitting PAUSE frames ONLY. 2857 * 2858 * LOCAL DEVICE | LINK PARTNER 2859 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 2860 *-------|---------|-------|---------|-------------------- 2861 * 1 | 1 | 0 | 1 | em_fc_rx_pause 2862 * 2863 */ 2864 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 2865 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 2866 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 2867 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 2868 hw->fc = E1000_FC_RX_PAUSE; 2869 DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); 2870 } 2871 /* Per the IEEE spec, at this point flow control should be 2872 * disabled. However, we want to consider that we could 2873 * be connected to a legacy switch that doesn't advertise 2874 * desired flow control, but can be forced on the link 2875 * partner. So if we advertised no flow control, that is 2876 * what we will resolve to. If we advertised some kind of 2877 * receive capability (Rx Pause Only or Full Flow Control) 2878 * and the link partner advertised none, we will configure 2879 * ourselves to enable Rx Flow Control only. We can do 2880 * this safely for two reasons: If the link partner really 2881 * didn't want flow control enabled, and we enable Rx, no 2882 * harm done since we won't be receiving any PAUSE frames 2883 * anyway. If the intent on the link partner was to have 2884 * flow control enabled, then by us enabling RX only, we 2885 * can at least receive pause frames and process them. 2886 * This is a good idea because in most cases, since we are 2887 * predominantly a server NIC, more times than not we will 2888 * be asked to delay transmission of packets than asking 2889 * our link partner to pause transmission of frames. 2890 */ 2891 else if ((hw->original_fc == E1000_FC_NONE|| 2892 hw->original_fc == E1000_FC_TX_PAUSE) || 2893 hw->fc_strict_ieee) { 2894 hw->fc = E1000_FC_NONE; 2895 DEBUGOUT("Flow Control = NONE.\n"); 2896 } else { 2897 hw->fc = E1000_FC_RX_PAUSE; 2898 DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); 2899 } 2900 2901 /* Now we need to do one last check... If we auto- 2902 * negotiated to HALF DUPLEX, flow control should not be 2903 * enabled per IEEE 802.3 spec. 2904 */ 2905 ret_val = em_get_speed_and_duplex(hw, &speed, &duplex); 2906 if (ret_val) { 2907 DEBUGOUT("Error getting link speed and duplex\n"); 2908 return ret_val; 2909 } 2910 2911 if (duplex == HALF_DUPLEX) 2912 hw->fc = E1000_FC_NONE; 2913 2914 /* Now we call a subroutine to actually force the MAC 2915 * controller to use the correct flow control settings. 2916 */ 2917 ret_val = em_force_mac_fc(hw); 2918 if (ret_val) { 2919 DEBUGOUT("Error forcing flow control settings\n"); 2920 return ret_val; 2921 } 2922 } else { 2923 DEBUGOUT("Copper PHY and Auto Neg has not completed.\n"); 2924 } 2925 } 2926 return E1000_SUCCESS; 2927 } 2928 2929 /****************************************************************************** 2930 * Checks to see if the link status of the hardware has changed. 2931 * 2932 * hw - Struct containing variables accessed by shared code 2933 * 2934 * Called by any function that needs to check the link status of the adapter. 2935 *****************************************************************************/ 2936 int32_t 2937 em_check_for_link(struct em_hw *hw) 2938 { 2939 uint32_t rxcw = 0; 2940 uint32_t ctrl; 2941 uint32_t status; 2942 uint32_t rctl; 2943 uint32_t icr; 2944 uint32_t signal = 0; 2945 int32_t ret_val; 2946 uint16_t phy_data; 2947 2948 DEBUGFUNC("em_check_for_link"); 2949 2950 ctrl = E1000_READ_REG(hw, CTRL); 2951 status = E1000_READ_REG(hw, STATUS); 2952 2953 /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be 2954 * set when the optics detect a signal. On older adapters, it will be 2955 * cleared when there is a signal. This applies to fiber media only. 2956 */ 2957 if ((hw->media_type == em_media_type_fiber) || 2958 (hw->media_type == em_media_type_internal_serdes)) { 2959 rxcw = E1000_READ_REG(hw, RXCW); 2960 2961 if (hw->media_type == em_media_type_fiber) { 2962 signal = (hw->mac_type > em_82544) ? E1000_CTRL_SWDPIN1 : 0; 2963 if (status & E1000_STATUS_LU) 2964 hw->get_link_status = FALSE; 2965 } 2966 } 2967 2968 /* If we have a copper PHY then we only want to go out to the PHY 2969 * registers to see if Auto-Neg has completed and/or if our link 2970 * status has changed. The get_link_status flag will be set if we 2971 * receive a Link Status Change interrupt or we have Rx Sequence 2972 * Errors. 2973 */ 2974 if ((hw->media_type == em_media_type_copper) && hw->get_link_status) { 2975 /* First we want to see if the MII Status Register reports 2976 * link. If so, then we want to get the current speed/duplex 2977 * of the PHY. 2978 * Read the register twice since the link bit is sticky. 2979 */ 2980 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 2981 if (ret_val) 2982 return ret_val; 2983 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 2984 if (ret_val) 2985 return ret_val; 2986 2987 if (phy_data & MII_SR_LINK_STATUS) { 2988 hw->get_link_status = FALSE; 2989 /* Check if there was DownShift, must be checked immediately after 2990 * link-up */ 2991 em_check_downshift(hw); 2992 2993 /* If we are on 82544 or 82543 silicon and speed/duplex 2994 * are forced to 10H or 10F, then we will implement the polarity 2995 * reversal workaround. We disable interrupts first, and upon 2996 * returning, place the devices interrupt state to its previous 2997 * value except for the link status change interrupt which will 2998 * happen due to the execution of this workaround. 2999 */ 3000 3001 if ((hw->mac_type == em_82544 || hw->mac_type == em_82543) && 3002 (!hw->autoneg) && 3003 (hw->forced_speed_duplex == em_10_full || 3004 hw->forced_speed_duplex == em_10_half)) { 3005 E1000_WRITE_REG(hw, IMC, 0xffffffff); 3006 ret_val = em_polarity_reversal_workaround(hw); 3007 icr = E1000_READ_REG(hw, ICR); 3008 E1000_WRITE_REG(hw, ICS, (icr & ~E1000_ICS_LSC)); 3009 E1000_WRITE_REG(hw, IMS, IMS_ENABLE_MASK); 3010 } 3011 3012 } else { 3013 /* No link detected */ 3014 em_config_dsp_after_link_change(hw, FALSE); 3015 return 0; 3016 } 3017 3018 /* If we are forcing speed/duplex, then we simply return since 3019 * we have already determined whether we have link or not. 3020 */ 3021 if (!hw->autoneg) return -E1000_ERR_CONFIG; 3022 3023 /* optimize the dsp settings for the igp phy */ 3024 em_config_dsp_after_link_change(hw, TRUE); 3025 3026 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we 3027 * have Si on board that is 82544 or newer, Auto 3028 * Speed Detection takes care of MAC speed/duplex 3029 * configuration. So we only need to configure Collision 3030 * Distance in the MAC. Otherwise, we need to force 3031 * speed/duplex on the MAC to the current PHY speed/duplex 3032 * settings. 3033 */ 3034 if (hw->mac_type >= em_82544) 3035 em_config_collision_dist(hw); 3036 else { 3037 ret_val = em_config_mac_to_phy(hw); 3038 if (ret_val) { 3039 DEBUGOUT("Error configuring MAC to PHY settings\n"); 3040 return ret_val; 3041 } 3042 } 3043 3044 /* Configure Flow Control now that Auto-Neg has completed. First, we 3045 * need to restore the desired flow control settings because we may 3046 * have had to re-autoneg with a different link partner. 3047 */ 3048 ret_val = em_config_fc_after_link_up(hw); 3049 if (ret_val) { 3050 DEBUGOUT("Error configuring flow control\n"); 3051 return ret_val; 3052 } 3053 3054 /* At this point we know that we are on copper and we have 3055 * auto-negotiated link. These are conditions for checking the link 3056 * partner capability register. We use the link speed to determine if 3057 * TBI compatibility needs to be turned on or off. If the link is not 3058 * at gigabit speed, then TBI compatibility is not needed. If we are 3059 * at gigabit speed, we turn on TBI compatibility. 3060 */ 3061 if (hw->tbi_compatibility_en) { 3062 uint16_t speed, duplex; 3063 ret_val = em_get_speed_and_duplex(hw, &speed, &duplex); 3064 if (ret_val) { 3065 DEBUGOUT("Error getting link speed and duplex\n"); 3066 return ret_val; 3067 } 3068 if (speed != SPEED_1000) { 3069 /* If link speed is not set to gigabit speed, we do not need 3070 * to enable TBI compatibility. 3071 */ 3072 if (hw->tbi_compatibility_on) { 3073 /* If we previously were in the mode, turn it off. */ 3074 rctl = E1000_READ_REG(hw, RCTL); 3075 rctl &= ~E1000_RCTL_SBP; 3076 E1000_WRITE_REG(hw, RCTL, rctl); 3077 hw->tbi_compatibility_on = FALSE; 3078 } 3079 } else { 3080 /* If TBI compatibility is was previously off, turn it on. For 3081 * compatibility with a TBI link partner, we will store bad 3082 * packets. Some frames have an additional byte on the end and 3083 * will look like CRC errors to to the hardware. 3084 */ 3085 if (!hw->tbi_compatibility_on) { 3086 hw->tbi_compatibility_on = TRUE; 3087 rctl = E1000_READ_REG(hw, RCTL); 3088 rctl |= E1000_RCTL_SBP; 3089 E1000_WRITE_REG(hw, RCTL, rctl); 3090 } 3091 } 3092 } 3093 } 3094 /* If we don't have link (auto-negotiation failed or link partner cannot 3095 * auto-negotiate), the cable is plugged in (we have signal), and our 3096 * link partner is not trying to auto-negotiate with us (we are receiving 3097 * idles or data), we need to force link up. We also need to give 3098 * auto-negotiation time to complete, in case the cable was just plugged 3099 * in. The autoneg_failed flag does this. 3100 */ 3101 else if ((((hw->media_type == em_media_type_fiber) && 3102 ((ctrl & E1000_CTRL_SWDPIN1) == signal)) || 3103 (hw->media_type == em_media_type_internal_serdes)) && 3104 (!(status & E1000_STATUS_LU)) && 3105 (!(rxcw & E1000_RXCW_C))) { 3106 if (hw->autoneg_failed == 0) { 3107 hw->autoneg_failed = 1; 3108 return 0; 3109 } 3110 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 3111 3112 /* Disable auto-negotiation in the TXCW register */ 3113 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE)); 3114 3115 /* Force link-up and also force full-duplex. */ 3116 ctrl = E1000_READ_REG(hw, CTRL); 3117 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 3118 E1000_WRITE_REG(hw, CTRL, ctrl); 3119 3120 /* Configure Flow Control after forcing link up. */ 3121 ret_val = em_config_fc_after_link_up(hw); 3122 if (ret_val) { 3123 DEBUGOUT("Error configuring flow control\n"); 3124 return ret_val; 3125 } 3126 } 3127 /* If we are forcing link and we are receiving /C/ ordered sets, re-enable 3128 * auto-negotiation in the TXCW register and disable forced link in the 3129 * Device Control register in an attempt to auto-negotiate with our link 3130 * partner. 3131 */ 3132 else if (((hw->media_type == em_media_type_fiber) || 3133 (hw->media_type == em_media_type_internal_serdes)) && 3134 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 3135 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 3136 E1000_WRITE_REG(hw, TXCW, hw->txcw); 3137 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU)); 3138 3139 hw->serdes_link_down = FALSE; 3140 } 3141 /* If we force link for non-auto-negotiation switch, check link status 3142 * based on MAC synchronization for internal serdes media type. 3143 */ 3144 else if ((hw->media_type == em_media_type_internal_serdes) && 3145 !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) { 3146 /* SYNCH bit and IV bit are sticky. */ 3147 usec_delay(10); 3148 if (E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) { 3149 if (!(rxcw & E1000_RXCW_IV)) { 3150 hw->serdes_link_down = FALSE; 3151 DEBUGOUT("SERDES: Link is up.\n"); 3152 } 3153 } else { 3154 hw->serdes_link_down = TRUE; 3155 DEBUGOUT("SERDES: Link is down.\n"); 3156 } 3157 } 3158 if ((hw->media_type == em_media_type_internal_serdes) && 3159 (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) { 3160 hw->serdes_link_down = !(E1000_STATUS_LU & E1000_READ_REG(hw, STATUS)); 3161 } 3162 return E1000_SUCCESS; 3163 } 3164 3165 /****************************************************************************** 3166 * Detects the current speed and duplex settings of the hardware. 3167 * 3168 * hw - Struct containing variables accessed by shared code 3169 * speed - Speed of the connection 3170 * duplex - Duplex setting of the connection 3171 *****************************************************************************/ 3172 int32_t 3173 em_get_speed_and_duplex(struct em_hw *hw, 3174 uint16_t *speed, 3175 uint16_t *duplex) 3176 { 3177 uint32_t status; 3178 int32_t ret_val; 3179 uint16_t phy_data; 3180 3181 DEBUGFUNC("em_get_speed_and_duplex"); 3182 3183 if (hw->mac_type >= em_82543) { 3184 status = E1000_READ_REG(hw, STATUS); 3185 if (status & E1000_STATUS_SPEED_1000) { 3186 *speed = SPEED_1000; 3187 DEBUGOUT("1000 Mbs, "); 3188 } else if (status & E1000_STATUS_SPEED_100) { 3189 *speed = SPEED_100; 3190 DEBUGOUT("100 Mbs, "); 3191 } else { 3192 *speed = SPEED_10; 3193 DEBUGOUT("10 Mbs, "); 3194 } 3195 3196 if (status & E1000_STATUS_FD) { 3197 *duplex = FULL_DUPLEX; 3198 DEBUGOUT("Full Duplex\n"); 3199 } else { 3200 *duplex = HALF_DUPLEX; 3201 DEBUGOUT(" Half Duplex\n"); 3202 } 3203 } else { 3204 DEBUGOUT("1000 Mbs, Full Duplex\n"); 3205 *speed = SPEED_1000; 3206 *duplex = FULL_DUPLEX; 3207 } 3208 3209 /* IGP01 PHY may advertise full duplex operation after speed downgrade even 3210 * if it is operating at half duplex. Here we set the duplex settings to 3211 * match the duplex in the link partner's capabilities. 3212 */ 3213 if (hw->phy_type == em_phy_igp && hw->speed_downgraded) { 3214 ret_val = em_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data); 3215 if (ret_val) 3216 return ret_val; 3217 3218 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS)) 3219 *duplex = HALF_DUPLEX; 3220 else { 3221 ret_val = em_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data); 3222 if (ret_val) 3223 return ret_val; 3224 if ((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) || 3225 (*speed == SPEED_10 && !(phy_data & NWAY_LPAR_10T_FD_CAPS))) 3226 *duplex = HALF_DUPLEX; 3227 } 3228 } 3229 3230 if ((hw->mac_type == em_80003es2lan) && 3231 (hw->media_type == em_media_type_copper)) { 3232 if (*speed == SPEED_1000) 3233 ret_val = em_configure_kmrn_for_1000(hw); 3234 else 3235 ret_val = em_configure_kmrn_for_10_100(hw, *duplex); 3236 if (ret_val) 3237 return ret_val; 3238 } 3239 3240 if ((hw->phy_type == em_phy_igp_3) && (*speed == SPEED_1000)) { 3241 ret_val = em_kumeran_lock_loss_workaround(hw); 3242 if (ret_val) 3243 return ret_val; 3244 } 3245 3246 return E1000_SUCCESS; 3247 } 3248 3249 /****************************************************************************** 3250 * Blocks until autoneg completes or times out (~4.5 seconds) 3251 * 3252 * hw - Struct containing variables accessed by shared code 3253 ******************************************************************************/ 3254 STATIC int32_t 3255 em_wait_autoneg(struct em_hw *hw) 3256 { 3257 int32_t ret_val; 3258 uint16_t i; 3259 uint16_t phy_data; 3260 3261 DEBUGFUNC("em_wait_autoneg"); 3262 DEBUGOUT("Waiting for Auto-Neg to complete.\n"); 3263 3264 /* We will wait for autoneg to complete or 4.5 seconds to expire. */ 3265 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) { 3266 /* Read the MII Status Register and wait for Auto-Neg 3267 * Complete bit to be set. 3268 */ 3269 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 3270 if (ret_val) 3271 return ret_val; 3272 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 3273 if (ret_val) 3274 return ret_val; 3275 if (phy_data & MII_SR_AUTONEG_COMPLETE) { 3276 return E1000_SUCCESS; 3277 } 3278 msec_delay(100); 3279 } 3280 return E1000_SUCCESS; 3281 } 3282 3283 /****************************************************************************** 3284 * Raises the Management Data Clock 3285 * 3286 * hw - Struct containing variables accessed by shared code 3287 * ctrl - Device control register's current value 3288 ******************************************************************************/ 3289 static void 3290 em_raise_mdi_clk(struct em_hw *hw, 3291 uint32_t *ctrl) 3292 { 3293 /* Raise the clock input to the Management Data Clock (by setting the MDC 3294 * bit), and then delay 10 microseconds. 3295 */ 3296 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC)); 3297 E1000_WRITE_FLUSH(hw); 3298 usec_delay(10); 3299 } 3300 3301 /****************************************************************************** 3302 * Lowers the Management Data Clock 3303 * 3304 * hw - Struct containing variables accessed by shared code 3305 * ctrl - Device control register's current value 3306 ******************************************************************************/ 3307 static void 3308 em_lower_mdi_clk(struct em_hw *hw, 3309 uint32_t *ctrl) 3310 { 3311 /* Lower the clock input to the Management Data Clock (by clearing the MDC 3312 * bit), and then delay 10 microseconds. 3313 */ 3314 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC)); 3315 E1000_WRITE_FLUSH(hw); 3316 usec_delay(10); 3317 } 3318 3319 /****************************************************************************** 3320 * Shifts data bits out to the PHY 3321 * 3322 * hw - Struct containing variables accessed by shared code 3323 * data - Data to send out to the PHY 3324 * count - Number of bits to shift out 3325 * 3326 * Bits are shifted out in MSB to LSB order. 3327 ******************************************************************************/ 3328 static void 3329 em_shift_out_mdi_bits(struct em_hw *hw, 3330 uint32_t data, 3331 uint16_t count) 3332 { 3333 uint32_t ctrl; 3334 uint32_t mask; 3335 3336 /* We need to shift "count" number of bits out to the PHY. So, the value 3337 * in the "data" parameter will be shifted out to the PHY one bit at a 3338 * time. In order to do this, "data" must be broken down into bits. 3339 */ 3340 mask = 0x01; 3341 mask <<= (count - 1); 3342 3343 ctrl = E1000_READ_REG(hw, CTRL); 3344 3345 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ 3346 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); 3347 3348 while (mask) { 3349 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and 3350 * then raising and lowering the Management Data Clock. A "0" is 3351 * shifted out to the PHY by setting the MDIO bit to "0" and then 3352 * raising and lowering the clock. 3353 */ 3354 if (data & mask) 3355 ctrl |= E1000_CTRL_MDIO; 3356 else 3357 ctrl &= ~E1000_CTRL_MDIO; 3358 3359 E1000_WRITE_REG(hw, CTRL, ctrl); 3360 E1000_WRITE_FLUSH(hw); 3361 3362 usec_delay(10); 3363 3364 em_raise_mdi_clk(hw, &ctrl); 3365 em_lower_mdi_clk(hw, &ctrl); 3366 3367 mask = mask >> 1; 3368 } 3369 } 3370 3371 /****************************************************************************** 3372 * Shifts data bits in from the PHY 3373 * 3374 * hw - Struct containing variables accessed by shared code 3375 * 3376 * Bits are shifted in in MSB to LSB order. 3377 ******************************************************************************/ 3378 static uint16_t 3379 em_shift_in_mdi_bits(struct em_hw *hw) 3380 { 3381 uint32_t ctrl; 3382 uint16_t data = 0; 3383 uint8_t i; 3384 3385 /* In order to read a register from the PHY, we need to shift in a total 3386 * of 18 bits from the PHY. The first two bit (turnaround) times are used 3387 * to avoid contention on the MDIO pin when a read operation is performed. 3388 * These two bits are ignored by us and thrown away. Bits are "shifted in" 3389 * by raising the input to the Management Data Clock (setting the MDC bit), 3390 * and then reading the value of the MDIO bit. 3391 */ 3392 ctrl = E1000_READ_REG(hw, CTRL); 3393 3394 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */ 3395 ctrl &= ~E1000_CTRL_MDIO_DIR; 3396 ctrl &= ~E1000_CTRL_MDIO; 3397 3398 E1000_WRITE_REG(hw, CTRL, ctrl); 3399 E1000_WRITE_FLUSH(hw); 3400 3401 /* Raise and Lower the clock before reading in the data. This accounts for 3402 * the turnaround bits. The first clock occurred when we clocked out the 3403 * last bit of the Register Address. 3404 */ 3405 em_raise_mdi_clk(hw, &ctrl); 3406 em_lower_mdi_clk(hw, &ctrl); 3407 3408 for (data = 0, i = 0; i < 16; i++) { 3409 data = data << 1; 3410 em_raise_mdi_clk(hw, &ctrl); 3411 ctrl = E1000_READ_REG(hw, CTRL); 3412 /* Check to see if we shifted in a "1". */ 3413 if (ctrl & E1000_CTRL_MDIO) 3414 data |= 1; 3415 em_lower_mdi_clk(hw, &ctrl); 3416 } 3417 3418 em_raise_mdi_clk(hw, &ctrl); 3419 em_lower_mdi_clk(hw, &ctrl); 3420 3421 return data; 3422 } 3423 3424 STATIC int32_t 3425 em_swfw_sync_acquire(struct em_hw *hw, uint16_t mask) 3426 { 3427 uint32_t swfw_sync = 0; 3428 uint32_t swmask = mask; 3429 uint32_t fwmask = mask << 16; 3430 int32_t timeout = 200; 3431 3432 DEBUGFUNC("em_swfw_sync_acquire"); 3433 3434 if (hw->swfwhw_semaphore_present) 3435 return em_get_software_flag(hw); 3436 3437 if (!hw->swfw_sync_present) 3438 return em_get_hw_eeprom_semaphore(hw); 3439 3440 while (timeout) { 3441 if (em_get_hw_eeprom_semaphore(hw)) 3442 return -E1000_ERR_SWFW_SYNC; 3443 3444 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); 3445 if (!(swfw_sync & (fwmask | swmask))) { 3446 break; 3447 } 3448 3449 /* firmware currently using resource (fwmask) */ 3450 /* or other software thread currently using resource (swmask) */ 3451 em_put_hw_eeprom_semaphore(hw); 3452 msec_delay_irq(5); 3453 timeout--; 3454 } 3455 3456 if (!timeout) { 3457 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); 3458 return -E1000_ERR_SWFW_SYNC; 3459 } 3460 3461 swfw_sync |= swmask; 3462 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync); 3463 3464 em_put_hw_eeprom_semaphore(hw); 3465 return E1000_SUCCESS; 3466 } 3467 3468 STATIC void 3469 em_swfw_sync_release(struct em_hw *hw, uint16_t mask) 3470 { 3471 uint32_t swfw_sync; 3472 uint32_t swmask = mask; 3473 3474 DEBUGFUNC("em_swfw_sync_release"); 3475 3476 if (hw->swfwhw_semaphore_present) { 3477 em_release_software_flag(hw); 3478 return; 3479 } 3480 3481 if (!hw->swfw_sync_present) { 3482 em_put_hw_eeprom_semaphore(hw); 3483 return; 3484 } 3485 3486 /* if (em_get_hw_eeprom_semaphore(hw)) 3487 * return -E1000_ERR_SWFW_SYNC; */ 3488 while (em_get_hw_eeprom_semaphore(hw) != E1000_SUCCESS); 3489 /* empty */ 3490 3491 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); 3492 swfw_sync &= ~swmask; 3493 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync); 3494 3495 em_put_hw_eeprom_semaphore(hw); 3496 } 3497 3498 /***************************************************************************** 3499 * Reads the value from a PHY register, if the value is on a specific non zero 3500 * page, sets the page first. 3501 * hw - Struct containing variables accessed by shared code 3502 * reg_addr - address of the PHY register to read 3503 ******************************************************************************/ 3504 int32_t 3505 em_read_phy_reg(struct em_hw *hw, 3506 uint32_t reg_addr, 3507 uint16_t *phy_data) 3508 { 3509 uint32_t ret_val; 3510 uint16_t swfw; 3511 3512 DEBUGFUNC("em_read_phy_reg"); 3513 3514 if ((hw->mac_type == em_80003es2lan) && 3515 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { 3516 swfw = E1000_SWFW_PHY1_SM; 3517 } else { 3518 swfw = E1000_SWFW_PHY0_SM; 3519 } 3520 if (em_swfw_sync_acquire(hw, swfw)) 3521 return -E1000_ERR_SWFW_SYNC; 3522 3523 if ((hw->phy_type == em_phy_igp || 3524 hw->phy_type == em_phy_igp_3 || 3525 hw->phy_type == em_phy_igp_2) && 3526 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { 3527 ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 3528 (uint16_t)reg_addr); 3529 if (ret_val) { 3530 em_swfw_sync_release(hw, swfw); 3531 return ret_val; 3532 } 3533 } else if (hw->phy_type == em_phy_gg82563) { 3534 if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) || 3535 (hw->mac_type == em_80003es2lan)) { 3536 /* Select Configuration Page */ 3537 if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { 3538 ret_val = em_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT, 3539 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT)); 3540 } else { 3541 /* Use Alternative Page Select register to access 3542 * registers 30 and 31 3543 */ 3544 ret_val = em_write_phy_reg_ex(hw, 3545 GG82563_PHY_PAGE_SELECT_ALT, 3546 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT)); 3547 } 3548 3549 if (ret_val) { 3550 em_swfw_sync_release(hw, swfw); 3551 return ret_val; 3552 } 3553 } 3554 } 3555 3556 ret_val = em_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, 3557 phy_data); 3558 3559 em_swfw_sync_release(hw, swfw); 3560 return ret_val; 3561 } 3562 3563 STATIC int32_t 3564 em_read_phy_reg_ex(struct em_hw *hw, uint32_t reg_addr, 3565 uint16_t *phy_data) 3566 { 3567 uint32_t i; 3568 uint32_t mdic = 0; 3569 const uint32_t phy_addr = 1; 3570 3571 DEBUGFUNC("em_read_phy_reg_ex"); 3572 3573 if (reg_addr > MAX_PHY_REG_ADDRESS) { 3574 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); 3575 return -E1000_ERR_PARAM; 3576 } 3577 3578 if (hw->mac_type > em_82543) { 3579 /* Set up Op-code, Phy Address, and register address in the MDI 3580 * Control register. The MAC will take care of interfacing with the 3581 * PHY to retrieve the desired data. 3582 */ 3583 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) | 3584 (phy_addr << E1000_MDIC_PHY_SHIFT) | 3585 (E1000_MDIC_OP_READ)); 3586 3587 E1000_WRITE_REG(hw, MDIC, mdic); 3588 3589 /* Poll the ready bit to see if the MDI read completed */ 3590 for (i = 0; i < 64; i++) { 3591 usec_delay(50); 3592 mdic = E1000_READ_REG(hw, MDIC); 3593 if (mdic & E1000_MDIC_READY) break; 3594 } 3595 if (!(mdic & E1000_MDIC_READY)) { 3596 DEBUGOUT("MDI Read did not complete\n"); 3597 return -E1000_ERR_PHY; 3598 } 3599 if (mdic & E1000_MDIC_ERROR) { 3600 DEBUGOUT("MDI Error\n"); 3601 return -E1000_ERR_PHY; 3602 } 3603 *phy_data = (uint16_t) mdic; 3604 } else { 3605 /* We must first send a preamble through the MDIO pin to signal the 3606 * beginning of an MII instruction. This is done by sending 32 3607 * consecutive "1" bits. 3608 */ 3609 em_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 3610 3611 /* Now combine the next few fields that are required for a read 3612 * operation. We use this method instead of calling the 3613 * em_shift_out_mdi_bits routine five different times. The format of 3614 * a MII read instruction consists of a shift out of 14 bits and is 3615 * defined as follows: 3616 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr> 3617 * followed by a shift in of 18 bits. This first two bits shifted in 3618 * are TurnAround bits used to avoid contention on the MDIO pin when a 3619 * READ operation is performed. These two bits are thrown away 3620 * followed by a shift in of 16 bits which contains the desired data. 3621 */ 3622 mdic = ((reg_addr) | (phy_addr << 5) | 3623 (PHY_OP_READ << 10) | (PHY_SOF << 12)); 3624 3625 em_shift_out_mdi_bits(hw, mdic, 14); 3626 3627 /* Now that we've shifted out the read command to the MII, we need to 3628 * "shift in" the 16-bit value (18 total bits) of the requested PHY 3629 * register address. 3630 */ 3631 *phy_data = em_shift_in_mdi_bits(hw); 3632 } 3633 return E1000_SUCCESS; 3634 } 3635 3636 /****************************************************************************** 3637 * Writes a value to a PHY register 3638 * 3639 * hw - Struct containing variables accessed by shared code 3640 * reg_addr - address of the PHY register to write 3641 * data - data to write to the PHY 3642 ******************************************************************************/ 3643 int32_t 3644 em_write_phy_reg(struct em_hw *hw, uint32_t reg_addr, 3645 uint16_t phy_data) 3646 { 3647 uint32_t ret_val; 3648 uint16_t swfw; 3649 3650 DEBUGFUNC("em_write_phy_reg"); 3651 3652 if ((hw->mac_type == em_80003es2lan) && 3653 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { 3654 swfw = E1000_SWFW_PHY1_SM; 3655 } else { 3656 swfw = E1000_SWFW_PHY0_SM; 3657 } 3658 if (em_swfw_sync_acquire(hw, swfw)) 3659 return -E1000_ERR_SWFW_SYNC; 3660 3661 if ((hw->phy_type == em_phy_igp || 3662 hw->phy_type == em_phy_igp_3 || 3663 hw->phy_type == em_phy_igp_2) && 3664 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { 3665 ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 3666 (uint16_t)reg_addr); 3667 if (ret_val) { 3668 em_swfw_sync_release(hw, swfw); 3669 return ret_val; 3670 } 3671 } else if (hw->phy_type == em_phy_gg82563) { 3672 if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) || 3673 (hw->mac_type == em_80003es2lan)) { 3674 /* Select Configuration Page */ 3675 if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { 3676 ret_val = em_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT, 3677 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT)); 3678 } else { 3679 /* Use Alternative Page Select register to access 3680 * registers 30 and 31 3681 */ 3682 ret_val = em_write_phy_reg_ex(hw, 3683 GG82563_PHY_PAGE_SELECT_ALT, 3684 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT)); 3685 } 3686 3687 if (ret_val) { 3688 em_swfw_sync_release(hw, swfw); 3689 return ret_val; 3690 } 3691 } 3692 } 3693 3694 ret_val = em_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, 3695 phy_data); 3696 3697 em_swfw_sync_release(hw, swfw); 3698 return ret_val; 3699 } 3700 3701 STATIC int32_t 3702 em_write_phy_reg_ex(struct em_hw *hw, uint32_t reg_addr, 3703 uint16_t phy_data) 3704 { 3705 uint32_t i; 3706 uint32_t mdic = 0; 3707 const uint32_t phy_addr = 1; 3708 3709 DEBUGFUNC("em_write_phy_reg_ex"); 3710 3711 if (reg_addr > MAX_PHY_REG_ADDRESS) { 3712 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); 3713 return -E1000_ERR_PARAM; 3714 } 3715 3716 if (hw->mac_type > em_82543) { 3717 /* Set up Op-code, Phy Address, register address, and data intended 3718 * for the PHY register in the MDI Control register. The MAC will take 3719 * care of interfacing with the PHY to send the desired data. 3720 */ 3721 mdic = (((uint32_t) phy_data) | 3722 (reg_addr << E1000_MDIC_REG_SHIFT) | 3723 (phy_addr << E1000_MDIC_PHY_SHIFT) | 3724 (E1000_MDIC_OP_WRITE)); 3725 3726 E1000_WRITE_REG(hw, MDIC, mdic); 3727 3728 /* Poll the ready bit to see if the MDI read completed */ 3729 for (i = 0; i < 641; i++) { 3730 usec_delay(5); 3731 mdic = E1000_READ_REG(hw, MDIC); 3732 if (mdic & E1000_MDIC_READY) break; 3733 } 3734 if (!(mdic & E1000_MDIC_READY)) { 3735 DEBUGOUT("MDI Write did not complete\n"); 3736 return -E1000_ERR_PHY; 3737 } 3738 } else { 3739 /* We'll need to use the SW defined pins to shift the write command 3740 * out to the PHY. We first send a preamble to the PHY to signal the 3741 * beginning of the MII instruction. This is done by sending 32 3742 * consecutive "1" bits. 3743 */ 3744 em_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 3745 3746 /* Now combine the remaining required fields that will indicate a 3747 * write operation. We use this method instead of calling the 3748 * em_shift_out_mdi_bits routine for each field in the command. The 3749 * format of a MII write instruction is as follows: 3750 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>. 3751 */ 3752 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) | 3753 (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); 3754 mdic <<= 16; 3755 mdic |= (uint32_t) phy_data; 3756 3757 em_shift_out_mdi_bits(hw, mdic, 32); 3758 } 3759 3760 return E1000_SUCCESS; 3761 } 3762 3763 STATIC int32_t 3764 em_read_kmrn_reg(struct em_hw *hw, 3765 uint32_t reg_addr, 3766 uint16_t *data) 3767 { 3768 uint32_t reg_val; 3769 uint16_t swfw; 3770 DEBUGFUNC("em_read_kmrn_reg"); 3771 3772 if ((hw->mac_type == em_80003es2lan) && 3773 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { 3774 swfw = E1000_SWFW_PHY1_SM; 3775 } else { 3776 swfw = E1000_SWFW_PHY0_SM; 3777 } 3778 if (em_swfw_sync_acquire(hw, swfw)) 3779 return -E1000_ERR_SWFW_SYNC; 3780 3781 /* Write register address */ 3782 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) & 3783 E1000_KUMCTRLSTA_OFFSET) | 3784 E1000_KUMCTRLSTA_REN; 3785 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); 3786 usec_delay(2); 3787 3788 /* Read the data returned */ 3789 reg_val = E1000_READ_REG(hw, KUMCTRLSTA); 3790 *data = (uint16_t)reg_val; 3791 3792 em_swfw_sync_release(hw, swfw); 3793 return E1000_SUCCESS; 3794 } 3795 3796 STATIC int32_t 3797 em_write_kmrn_reg(struct em_hw *hw, 3798 uint32_t reg_addr, 3799 uint16_t data) 3800 { 3801 uint32_t reg_val; 3802 uint16_t swfw; 3803 DEBUGFUNC("em_write_kmrn_reg"); 3804 3805 if ((hw->mac_type == em_80003es2lan) && 3806 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { 3807 swfw = E1000_SWFW_PHY1_SM; 3808 } else { 3809 swfw = E1000_SWFW_PHY0_SM; 3810 } 3811 if (em_swfw_sync_acquire(hw, swfw)) 3812 return -E1000_ERR_SWFW_SYNC; 3813 3814 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) & 3815 E1000_KUMCTRLSTA_OFFSET) | data; 3816 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); 3817 usec_delay(2); 3818 3819 em_swfw_sync_release(hw, swfw); 3820 return E1000_SUCCESS; 3821 } 3822 3823 /****************************************************************************** 3824 * Returns the PHY to the power-on reset state 3825 * 3826 * hw - Struct containing variables accessed by shared code 3827 ******************************************************************************/ 3828 int32_t 3829 em_phy_hw_reset(struct em_hw *hw) 3830 { 3831 uint32_t ctrl, ctrl_ext; 3832 uint32_t led_ctrl; 3833 int32_t ret_val; 3834 uint16_t swfw; 3835 3836 DEBUGFUNC("em_phy_hw_reset"); 3837 3838 /* In the case of the phy reset being blocked, it's not an error, we 3839 * simply return success without performing the reset. */ 3840 ret_val = em_check_phy_reset_block(hw); 3841 if (ret_val) 3842 return E1000_SUCCESS; 3843 3844 DEBUGOUT("Resetting Phy...\n"); 3845 3846 if (hw->mac_type > em_82543) { 3847 if ((hw->mac_type == em_80003es2lan) && 3848 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { 3849 swfw = E1000_SWFW_PHY1_SM; 3850 } else { 3851 swfw = E1000_SWFW_PHY0_SM; 3852 } 3853 if (em_swfw_sync_acquire(hw, swfw)) { 3854 DEBUGOUT("Unable to acquire swfw sync\n"); 3855 return -E1000_ERR_SWFW_SYNC; 3856 } 3857 /* Read the device control register and assert the E1000_CTRL_PHY_RST 3858 * bit. Then, take it out of reset. 3859 * For pre-em_82571 hardware, we delay for 10ms between the assert 3860 * and deassert. For em_82571 hardware and later, we instead delay 3861 * for 50us between and 10ms after the deassertion. 3862 */ 3863 ctrl = E1000_READ_REG(hw, CTRL); 3864 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST); 3865 E1000_WRITE_FLUSH(hw); 3866 3867 if (hw->mac_type < em_82571) 3868 msec_delay(10); 3869 else 3870 usec_delay(100); 3871 3872 E1000_WRITE_REG(hw, CTRL, ctrl); 3873 E1000_WRITE_FLUSH(hw); 3874 3875 if (hw->mac_type >= em_82571) 3876 msec_delay_irq(10); 3877 em_swfw_sync_release(hw, swfw); 3878 } else { 3879 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR 3880 * bit to put the PHY into reset. Then, take it out of reset. 3881 */ 3882 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 3883 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; 3884 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; 3885 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 3886 E1000_WRITE_FLUSH(hw); 3887 msec_delay(10); 3888 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; 3889 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 3890 E1000_WRITE_FLUSH(hw); 3891 } 3892 usec_delay(150); 3893 3894 if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) { 3895 /* Configure activity LED after PHY reset */ 3896 led_ctrl = E1000_READ_REG(hw, LEDCTL); 3897 led_ctrl &= IGP_ACTIVITY_LED_MASK; 3898 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 3899 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 3900 } 3901 3902 /* Wait for FW to finish PHY configuration. */ 3903 ret_val = em_get_phy_cfg_done(hw); 3904 if (ret_val != E1000_SUCCESS) 3905 return ret_val; 3906 em_release_software_semaphore(hw); 3907 3908 if ((hw->mac_type == em_ich8lan) && (hw->phy_type == em_phy_igp_3)) 3909 ret_val = em_init_lcd_from_nvm(hw); 3910 3911 return ret_val; 3912 } 3913 3914 /****************************************************************************** 3915 * Resets the PHY 3916 * 3917 * hw - Struct containing variables accessed by shared code 3918 * 3919 * Sets bit 15 of the MII Control regiser 3920 ******************************************************************************/ 3921 int32_t 3922 em_phy_reset(struct em_hw *hw) 3923 { 3924 int32_t ret_val; 3925 uint16_t phy_data; 3926 3927 DEBUGFUNC("em_phy_reset"); 3928 3929 /* In the case of the phy reset being blocked, it's not an error, we 3930 * simply return success without performing the reset. */ 3931 ret_val = em_check_phy_reset_block(hw); 3932 if (ret_val) 3933 return E1000_SUCCESS; 3934 3935 switch (hw->phy_type) { 3936 case em_phy_igp: 3937 case em_phy_igp_2: 3938 case em_phy_igp_3: 3939 case em_phy_ife: 3940 ret_val = em_phy_hw_reset(hw); 3941 if (ret_val) 3942 return ret_val; 3943 break; 3944 default: 3945 ret_val = em_read_phy_reg(hw, PHY_CTRL, &phy_data); 3946 if (ret_val) 3947 return ret_val; 3948 3949 phy_data |= MII_CR_RESET; 3950 ret_val = em_write_phy_reg(hw, PHY_CTRL, phy_data); 3951 if (ret_val) 3952 return ret_val; 3953 3954 usec_delay(1); 3955 break; 3956 } 3957 3958 if (hw->phy_type == em_phy_igp || hw->phy_type == em_phy_igp_2) 3959 em_phy_init_script(hw); 3960 3961 return E1000_SUCCESS; 3962 } 3963 3964 /****************************************************************************** 3965 * Work-around for 82566 Kumeran PCS lock loss: 3966 * On link status change (i.e. PCI reset, speed change) and link is up and 3967 * speed is gigabit- 3968 * 0) if workaround is optionally disabled do nothing 3969 * 1) wait 1ms for Kumeran link to come up 3970 * 2) check Kumeran Diagnostic register PCS lock loss bit 3971 * 3) if not set the link is locked (all is good), otherwise... 3972 * 4) reset the PHY 3973 * 5) repeat up to 10 times 3974 * Note: this is only called for IGP3 copper when speed is 1gb. 3975 * 3976 * hw - struct containing variables accessed by shared code 3977 ******************************************************************************/ 3978 STATIC int32_t 3979 em_kumeran_lock_loss_workaround(struct em_hw *hw) 3980 { 3981 int32_t ret_val; 3982 int32_t reg; 3983 int32_t cnt; 3984 uint16_t phy_data; 3985 3986 if (hw->kmrn_lock_loss_workaround_disabled) 3987 return E1000_SUCCESS; 3988 3989 /* Make sure link is up before proceeding. If not just return. 3990 * Attempting this while link is negotiating fouled up link 3991 * stability */ 3992 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 3993 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 3994 3995 if (phy_data & MII_SR_LINK_STATUS) { 3996 for (cnt = 0; cnt < 10; cnt++) { 3997 /* read once to clear */ 3998 ret_val = em_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data); 3999 if (ret_val) 4000 return ret_val; 4001 /* and again to get new status */ 4002 ret_val = em_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data); 4003 if (ret_val) 4004 return ret_val; 4005 4006 /* check for PCS lock */ 4007 if (!(phy_data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) 4008 return E1000_SUCCESS; 4009 4010 /* Issue PHY reset */ 4011 em_phy_hw_reset(hw); 4012 msec_delay_irq(5); 4013 } 4014 /* Disable GigE link negotiation */ 4015 reg = E1000_READ_REG(hw, PHY_CTRL); 4016 E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE | 4017 E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 4018 4019 /* unable to acquire PCS lock */ 4020 return E1000_ERR_PHY; 4021 } 4022 4023 return E1000_SUCCESS; 4024 } 4025 4026 /****************************************************************************** 4027 * Probes the expected PHY address for known PHY IDs 4028 * 4029 * hw - Struct containing variables accessed by shared code 4030 ******************************************************************************/ 4031 STATIC int32_t 4032 em_detect_gig_phy(struct em_hw *hw) 4033 { 4034 int32_t phy_init_status, ret_val; 4035 uint16_t phy_id_high, phy_id_low; 4036 boolean_t match = FALSE; 4037 4038 DEBUGFUNC("em_detect_gig_phy"); 4039 4040 if (hw->phy_id != 0) 4041 return E1000_SUCCESS; 4042 4043 /* The 82571 firmware may still be configuring the PHY. In this 4044 * case, we cannot access the PHY until the configuration is done. So 4045 * we explicitly set the PHY values. */ 4046 if (hw->mac_type == em_82571 || 4047 hw->mac_type == em_82572) { 4048 hw->phy_id = IGP01E1000_I_PHY_ID; 4049 hw->phy_type = em_phy_igp_2; 4050 return E1000_SUCCESS; 4051 } 4052 4053 /* until something better comes along... makes the Lenovo X200 work */ 4054 if (hw->mac_type == em_ich9lan && 4055 (hw->device_id == E1000_DEV_ID_ICH9_IGP_M || 4056 hw->device_id == E1000_DEV_ID_ICH9_IGP_M_AMT)) { 4057 hw->phy_id = IGP03E1000_E_PHY_ID; 4058 hw->phy_type = em_phy_igp_3; 4059 return E1000_SUCCESS; 4060 } 4061 4062 /* ESB-2 PHY reads require em_phy_gg82563 to be set because of a work- 4063 * around that forces PHY page 0 to be set or the reads fail. The rest of 4064 * the code in this routine uses em_read_phy_reg to read the PHY ID. 4065 * So for ESB-2 we need to have this set so our reads won't fail. If the 4066 * attached PHY is not a em_phy_gg82563, the routines below will figure 4067 * this out as well. */ 4068 if (hw->mac_type == em_80003es2lan) 4069 hw->phy_type = em_phy_gg82563; 4070 4071 /* Read the PHY ID Registers to identify which PHY is onboard. */ 4072 ret_val = em_read_phy_reg(hw, PHY_ID1, &phy_id_high); 4073 if (ret_val) 4074 return ret_val; 4075 4076 hw->phy_id = (uint32_t) (phy_id_high << 16); 4077 usec_delay(20); 4078 ret_val = em_read_phy_reg(hw, PHY_ID2, &phy_id_low); 4079 if (ret_val) 4080 return ret_val; 4081 4082 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK); 4083 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK; 4084 4085 switch (hw->mac_type) { 4086 case em_82543: 4087 if (hw->phy_id == M88E1000_E_PHY_ID) match = TRUE; 4088 break; 4089 case em_82544: 4090 if (hw->phy_id == M88E1000_I_PHY_ID) match = TRUE; 4091 break; 4092 case em_82540: 4093 case em_82545: 4094 case em_82545_rev_3: 4095 case em_82546: 4096 case em_82546_rev_3: 4097 if (hw->phy_id == M88E1011_I_PHY_ID) match = TRUE; 4098 break; 4099 case em_82541: 4100 case em_82541_rev_2: 4101 case em_82547: 4102 case em_82547_rev_2: 4103 if (hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE; 4104 break; 4105 case em_82573: 4106 if (hw->phy_id == M88E1111_I_PHY_ID) match = TRUE; 4107 break; 4108 case em_80003es2lan: 4109 if (hw->phy_id == GG82563_E_PHY_ID) match = TRUE; 4110 break; 4111 case em_ich8lan: 4112 case em_ich9lan: 4113 if (hw->phy_id == IGP03E1000_E_PHY_ID) match = TRUE; 4114 if (hw->phy_id == IFE_E_PHY_ID) match = TRUE; 4115 if (hw->phy_id == IFE_PLUS_E_PHY_ID) match = TRUE; 4116 if (hw->phy_id == IFE_C_E_PHY_ID) match = TRUE; 4117 break; 4118 default: 4119 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type); 4120 return -E1000_ERR_CONFIG; 4121 } 4122 phy_init_status = em_set_phy_type(hw); 4123 4124 if ((match) && (phy_init_status == E1000_SUCCESS)) { 4125 DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id); 4126 return E1000_SUCCESS; 4127 } 4128 DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id); 4129 return -E1000_ERR_PHY; 4130 } 4131 4132 /****************************************************************************** 4133 * Resets the PHY's DSP 4134 * 4135 * hw - Struct containing variables accessed by shared code 4136 ******************************************************************************/ 4137 static int32_t 4138 em_phy_reset_dsp(struct em_hw *hw) 4139 { 4140 int32_t ret_val; 4141 DEBUGFUNC("em_phy_reset_dsp"); 4142 4143 do { 4144 if (hw->phy_type != em_phy_gg82563) { 4145 ret_val = em_write_phy_reg(hw, 29, 0x001d); 4146 if (ret_val) break; 4147 } 4148 ret_val = em_write_phy_reg(hw, 30, 0x00c1); 4149 if (ret_val) break; 4150 ret_val = em_write_phy_reg(hw, 30, 0x0000); 4151 if (ret_val) break; 4152 ret_val = E1000_SUCCESS; 4153 } while (0); 4154 4155 return ret_val; 4156 } 4157 4158 /****************************************************************************** 4159 * Sets up eeprom variables in the hw struct. Must be called after mac_type 4160 * is configured. Additionally, if this is ICH8, the flash controller GbE 4161 * registers must be mapped, or this will crash. 4162 * 4163 * hw - Struct containing variables accessed by shared code 4164 *****************************************************************************/ 4165 int32_t 4166 em_init_eeprom_params(struct em_hw *hw) 4167 { 4168 struct em_eeprom_info *eeprom = &hw->eeprom; 4169 uint32_t eecd = E1000_READ_REG(hw, EECD); 4170 int32_t ret_val = E1000_SUCCESS; 4171 uint16_t eeprom_size; 4172 4173 DEBUGFUNC("em_init_eeprom_params"); 4174 4175 switch (hw->mac_type) { 4176 case em_82542_rev2_0: 4177 case em_82542_rev2_1: 4178 case em_82543: 4179 case em_82544: 4180 eeprom->type = em_eeprom_microwire; 4181 eeprom->word_size = 64; 4182 eeprom->opcode_bits = 3; 4183 eeprom->address_bits = 6; 4184 eeprom->delay_usec = 50; 4185 eeprom->use_eerd = FALSE; 4186 eeprom->use_eewr = FALSE; 4187 break; 4188 case em_82540: 4189 case em_82545: 4190 case em_82545_rev_3: 4191 case em_82546: 4192 case em_82546_rev_3: 4193 eeprom->type = em_eeprom_microwire; 4194 eeprom->opcode_bits = 3; 4195 eeprom->delay_usec = 50; 4196 if (eecd & E1000_EECD_SIZE) { 4197 eeprom->word_size = 256; 4198 eeprom->address_bits = 8; 4199 } else { 4200 eeprom->word_size = 64; 4201 eeprom->address_bits = 6; 4202 } 4203 eeprom->use_eerd = FALSE; 4204 eeprom->use_eewr = FALSE; 4205 break; 4206 case em_82541: 4207 case em_82541_rev_2: 4208 case em_82547: 4209 case em_82547_rev_2: 4210 if (eecd & E1000_EECD_TYPE) { 4211 eeprom->type = em_eeprom_spi; 4212 eeprom->opcode_bits = 8; 4213 eeprom->delay_usec = 1; 4214 if (eecd & E1000_EECD_ADDR_BITS) { 4215 eeprom->page_size = 32; 4216 eeprom->address_bits = 16; 4217 } else { 4218 eeprom->page_size = 8; 4219 eeprom->address_bits = 8; 4220 } 4221 } else { 4222 eeprom->type = em_eeprom_microwire; 4223 eeprom->opcode_bits = 3; 4224 eeprom->delay_usec = 50; 4225 if (eecd & E1000_EECD_ADDR_BITS) { 4226 eeprom->word_size = 256; 4227 eeprom->address_bits = 8; 4228 } else { 4229 eeprom->word_size = 64; 4230 eeprom->address_bits = 6; 4231 } 4232 } 4233 eeprom->use_eerd = FALSE; 4234 eeprom->use_eewr = FALSE; 4235 break; 4236 case em_82571: 4237 case em_82572: 4238 eeprom->type = em_eeprom_spi; 4239 eeprom->opcode_bits = 8; 4240 eeprom->delay_usec = 1; 4241 if (eecd & E1000_EECD_ADDR_BITS) { 4242 eeprom->page_size = 32; 4243 eeprom->address_bits = 16; 4244 } else { 4245 eeprom->page_size = 8; 4246 eeprom->address_bits = 8; 4247 } 4248 eeprom->use_eerd = FALSE; 4249 eeprom->use_eewr = FALSE; 4250 break; 4251 case em_82573: 4252 eeprom->type = em_eeprom_spi; 4253 eeprom->opcode_bits = 8; 4254 eeprom->delay_usec = 1; 4255 if (eecd & E1000_EECD_ADDR_BITS) { 4256 eeprom->page_size = 32; 4257 eeprom->address_bits = 16; 4258 } else { 4259 eeprom->page_size = 8; 4260 eeprom->address_bits = 8; 4261 } 4262 eeprom->use_eerd = TRUE; 4263 eeprom->use_eewr = TRUE; 4264 if (em_is_onboard_nvm_eeprom(hw) == FALSE) { 4265 eeprom->type = em_eeprom_flash; 4266 eeprom->word_size = 2048; 4267 4268 /* Ensure that the Autonomous FLASH update bit is cleared due to 4269 * Flash update issue on parts which use a FLASH for NVM. */ 4270 eecd &= ~E1000_EECD_AUPDEN; 4271 E1000_WRITE_REG(hw, EECD, eecd); 4272 } 4273 break; 4274 case em_80003es2lan: 4275 eeprom->type = em_eeprom_spi; 4276 eeprom->opcode_bits = 8; 4277 eeprom->delay_usec = 1; 4278 if (eecd & E1000_EECD_ADDR_BITS) { 4279 eeprom->page_size = 32; 4280 eeprom->address_bits = 16; 4281 } else { 4282 eeprom->page_size = 8; 4283 eeprom->address_bits = 8; 4284 } 4285 eeprom->use_eerd = TRUE; 4286 eeprom->use_eewr = FALSE; 4287 break; 4288 case em_ich8lan: 4289 case em_ich9lan: 4290 { 4291 int32_t i = 0; 4292 uint32_t flash_size = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_GFPREG); 4293 4294 eeprom->type = em_eeprom_ich8; 4295 eeprom->use_eerd = FALSE; 4296 eeprom->use_eewr = FALSE; 4297 eeprom->word_size = E1000_SHADOW_RAM_WORDS; 4298 4299 /* Zero the shadow RAM structure. But don't load it from NVM 4300 * so as to save time for driver init */ 4301 if (hw->eeprom_shadow_ram != NULL) { 4302 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 4303 hw->eeprom_shadow_ram[i].modified = FALSE; 4304 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF; 4305 } 4306 } 4307 4308 hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) * 4309 ICH_FLASH_SECTOR_SIZE; 4310 4311 hw->flash_bank_size = ((flash_size >> 16) & ICH_GFPREG_BASE_MASK) + 1; 4312 hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK); 4313 4314 hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE; 4315 4316 hw->flash_bank_size /= 2 * sizeof(uint16_t); 4317 4318 break; 4319 } 4320 default: 4321 break; 4322 } 4323 4324 if (eeprom->type == em_eeprom_spi) { 4325 /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to 4326 * 32KB (incremented by powers of 2). 4327 */ 4328 if (hw->mac_type <= em_82547_rev_2) { 4329 /* Set to default value for initial eeprom read. */ 4330 eeprom->word_size = 64; 4331 ret_val = em_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size); 4332 if (ret_val) 4333 return ret_val; 4334 eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT; 4335 /* 256B eeprom size was not supported in earlier hardware, so we 4336 * bump eeprom_size up one to ensure that "1" (which maps to 256B) 4337 * is never the result used in the shifting logic below. */ 4338 if (eeprom_size) 4339 eeprom_size++; 4340 } else { 4341 eeprom_size = (uint16_t)((eecd & E1000_EECD_SIZE_EX_MASK) >> 4342 E1000_EECD_SIZE_EX_SHIFT); 4343 } 4344 4345 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT); 4346 } 4347 return ret_val; 4348 } 4349 4350 /****************************************************************************** 4351 * Raises the EEPROM's clock input. 4352 * 4353 * hw - Struct containing variables accessed by shared code 4354 * eecd - EECD's current value 4355 *****************************************************************************/ 4356 static void 4357 em_raise_ee_clk(struct em_hw *hw, 4358 uint32_t *eecd) 4359 { 4360 /* Raise the clock input to the EEPROM (by setting the SK bit), and then 4361 * wait <delay> microseconds. 4362 */ 4363 *eecd = *eecd | E1000_EECD_SK; 4364 E1000_WRITE_REG(hw, EECD, *eecd); 4365 E1000_WRITE_FLUSH(hw); 4366 usec_delay(hw->eeprom.delay_usec); 4367 } 4368 4369 /****************************************************************************** 4370 * Lowers the EEPROM's clock input. 4371 * 4372 * hw - Struct containing variables accessed by shared code 4373 * eecd - EECD's current value 4374 *****************************************************************************/ 4375 static void 4376 em_lower_ee_clk(struct em_hw *hw, 4377 uint32_t *eecd) 4378 { 4379 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then 4380 * wait 50 microseconds. 4381 */ 4382 *eecd = *eecd & ~E1000_EECD_SK; 4383 E1000_WRITE_REG(hw, EECD, *eecd); 4384 E1000_WRITE_FLUSH(hw); 4385 usec_delay(hw->eeprom.delay_usec); 4386 } 4387 4388 /****************************************************************************** 4389 * Shift data bits out to the EEPROM. 4390 * 4391 * hw - Struct containing variables accessed by shared code 4392 * data - data to send to the EEPROM 4393 * count - number of bits to shift out 4394 *****************************************************************************/ 4395 static void 4396 em_shift_out_ee_bits(struct em_hw *hw, 4397 uint16_t data, 4398 uint16_t count) 4399 { 4400 struct em_eeprom_info *eeprom = &hw->eeprom; 4401 uint32_t eecd; 4402 uint32_t mask; 4403 4404 /* We need to shift "count" bits out to the EEPROM. So, value in the 4405 * "data" parameter will be shifted out to the EEPROM one bit at a time. 4406 * In order to do this, "data" must be broken down into bits. 4407 */ 4408 mask = 0x01 << (count - 1); 4409 eecd = E1000_READ_REG(hw, EECD); 4410 if (eeprom->type == em_eeprom_microwire) { 4411 eecd &= ~E1000_EECD_DO; 4412 } else if (eeprom->type == em_eeprom_spi) { 4413 eecd |= E1000_EECD_DO; 4414 } 4415 do { 4416 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1", 4417 * and then raising and then lowering the clock (the SK bit controls 4418 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM 4419 * by setting "DI" to "0" and then raising and then lowering the clock. 4420 */ 4421 eecd &= ~E1000_EECD_DI; 4422 4423 if (data & mask) 4424 eecd |= E1000_EECD_DI; 4425 4426 E1000_WRITE_REG(hw, EECD, eecd); 4427 E1000_WRITE_FLUSH(hw); 4428 4429 usec_delay(eeprom->delay_usec); 4430 4431 em_raise_ee_clk(hw, &eecd); 4432 em_lower_ee_clk(hw, &eecd); 4433 4434 mask = mask >> 1; 4435 4436 } while (mask); 4437 4438 /* We leave the "DI" bit set to "0" when we leave this routine. */ 4439 eecd &= ~E1000_EECD_DI; 4440 E1000_WRITE_REG(hw, EECD, eecd); 4441 } 4442 4443 /****************************************************************************** 4444 * Shift data bits in from the EEPROM 4445 * 4446 * hw - Struct containing variables accessed by shared code 4447 *****************************************************************************/ 4448 static uint16_t 4449 em_shift_in_ee_bits(struct em_hw *hw, 4450 uint16_t count) 4451 { 4452 uint32_t eecd; 4453 uint32_t i; 4454 uint16_t data; 4455 4456 /* In order to read a register from the EEPROM, we need to shift 'count' 4457 * bits in from the EEPROM. Bits are "shifted in" by raising the clock 4458 * input to the EEPROM (setting the SK bit), and then reading the value of 4459 * the "DO" bit. During this "shifting in" process the "DI" bit should 4460 * always be clear. 4461 */ 4462 4463 eecd = E1000_READ_REG(hw, EECD); 4464 4465 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 4466 data = 0; 4467 4468 for (i = 0; i < count; i++) { 4469 data = data << 1; 4470 em_raise_ee_clk(hw, &eecd); 4471 4472 eecd = E1000_READ_REG(hw, EECD); 4473 4474 eecd &= ~(E1000_EECD_DI); 4475 if (eecd & E1000_EECD_DO) 4476 data |= 1; 4477 4478 em_lower_ee_clk(hw, &eecd); 4479 } 4480 4481 return data; 4482 } 4483 4484 /****************************************************************************** 4485 * Prepares EEPROM for access 4486 * 4487 * hw - Struct containing variables accessed by shared code 4488 * 4489 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This 4490 * function should be called before issuing a command to the EEPROM. 4491 *****************************************************************************/ 4492 static int32_t 4493 em_acquire_eeprom(struct em_hw *hw) 4494 { 4495 struct em_eeprom_info *eeprom = &hw->eeprom; 4496 uint32_t eecd, i=0; 4497 4498 DEBUGFUNC("em_acquire_eeprom"); 4499 4500 if (em_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM)) 4501 return -E1000_ERR_SWFW_SYNC; 4502 eecd = E1000_READ_REG(hw, EECD); 4503 4504 if (hw->mac_type != em_82573) { 4505 /* Request EEPROM Access */ 4506 if (hw->mac_type > em_82544) { 4507 eecd |= E1000_EECD_REQ; 4508 E1000_WRITE_REG(hw, EECD, eecd); 4509 eecd = E1000_READ_REG(hw, EECD); 4510 while ((!(eecd & E1000_EECD_GNT)) && 4511 (i < E1000_EEPROM_GRANT_ATTEMPTS)) { 4512 i++; 4513 usec_delay(5); 4514 eecd = E1000_READ_REG(hw, EECD); 4515 } 4516 if (!(eecd & E1000_EECD_GNT)) { 4517 eecd &= ~E1000_EECD_REQ; 4518 E1000_WRITE_REG(hw, EECD, eecd); 4519 DEBUGOUT("Could not acquire EEPROM grant\n"); 4520 em_swfw_sync_release(hw, E1000_SWFW_EEP_SM); 4521 return -E1000_ERR_EEPROM; 4522 } 4523 } 4524 } 4525 4526 /* Setup EEPROM for Read/Write */ 4527 4528 if (eeprom->type == em_eeprom_microwire) { 4529 /* Clear SK and DI */ 4530 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK); 4531 E1000_WRITE_REG(hw, EECD, eecd); 4532 4533 /* Set CS */ 4534 eecd |= E1000_EECD_CS; 4535 E1000_WRITE_REG(hw, EECD, eecd); 4536 } else if (eeprom->type == em_eeprom_spi) { 4537 /* Clear SK and CS */ 4538 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 4539 E1000_WRITE_REG(hw, EECD, eecd); 4540 usec_delay(1); 4541 } 4542 4543 return E1000_SUCCESS; 4544 } 4545 4546 /****************************************************************************** 4547 * Returns EEPROM to a "standby" state 4548 * 4549 * hw - Struct containing variables accessed by shared code 4550 *****************************************************************************/ 4551 static void 4552 em_standby_eeprom(struct em_hw *hw) 4553 { 4554 struct em_eeprom_info *eeprom = &hw->eeprom; 4555 uint32_t eecd; 4556 4557 eecd = E1000_READ_REG(hw, EECD); 4558 4559 if (eeprom->type == em_eeprom_microwire) { 4560 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 4561 E1000_WRITE_REG(hw, EECD, eecd); 4562 E1000_WRITE_FLUSH(hw); 4563 usec_delay(eeprom->delay_usec); 4564 4565 /* Clock high */ 4566 eecd |= E1000_EECD_SK; 4567 E1000_WRITE_REG(hw, EECD, eecd); 4568 E1000_WRITE_FLUSH(hw); 4569 usec_delay(eeprom->delay_usec); 4570 4571 /* Select EEPROM */ 4572 eecd |= E1000_EECD_CS; 4573 E1000_WRITE_REG(hw, EECD, eecd); 4574 E1000_WRITE_FLUSH(hw); 4575 usec_delay(eeprom->delay_usec); 4576 4577 /* Clock low */ 4578 eecd &= ~E1000_EECD_SK; 4579 E1000_WRITE_REG(hw, EECD, eecd); 4580 E1000_WRITE_FLUSH(hw); 4581 usec_delay(eeprom->delay_usec); 4582 } else if (eeprom->type == em_eeprom_spi) { 4583 /* Toggle CS to flush commands */ 4584 eecd |= E1000_EECD_CS; 4585 E1000_WRITE_REG(hw, EECD, eecd); 4586 E1000_WRITE_FLUSH(hw); 4587 usec_delay(eeprom->delay_usec); 4588 eecd &= ~E1000_EECD_CS; 4589 E1000_WRITE_REG(hw, EECD, eecd); 4590 E1000_WRITE_FLUSH(hw); 4591 usec_delay(eeprom->delay_usec); 4592 } 4593 } 4594 4595 /****************************************************************************** 4596 * Terminates a command by inverting the EEPROM's chip select pin 4597 * 4598 * hw - Struct containing variables accessed by shared code 4599 *****************************************************************************/ 4600 static void 4601 em_release_eeprom(struct em_hw *hw) 4602 { 4603 uint32_t eecd; 4604 4605 DEBUGFUNC("em_release_eeprom"); 4606 4607 eecd = E1000_READ_REG(hw, EECD); 4608 4609 if (hw->eeprom.type == em_eeprom_spi) { 4610 eecd |= E1000_EECD_CS; /* Pull CS high */ 4611 eecd &= ~E1000_EECD_SK; /* Lower SCK */ 4612 4613 E1000_WRITE_REG(hw, EECD, eecd); 4614 4615 usec_delay(hw->eeprom.delay_usec); 4616 } else if (hw->eeprom.type == em_eeprom_microwire) { 4617 /* cleanup eeprom */ 4618 4619 /* CS on Microwire is active-high */ 4620 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); 4621 4622 E1000_WRITE_REG(hw, EECD, eecd); 4623 4624 /* Rising edge of clock */ 4625 eecd |= E1000_EECD_SK; 4626 E1000_WRITE_REG(hw, EECD, eecd); 4627 E1000_WRITE_FLUSH(hw); 4628 usec_delay(hw->eeprom.delay_usec); 4629 4630 /* Falling edge of clock */ 4631 eecd &= ~E1000_EECD_SK; 4632 E1000_WRITE_REG(hw, EECD, eecd); 4633 E1000_WRITE_FLUSH(hw); 4634 usec_delay(hw->eeprom.delay_usec); 4635 } 4636 4637 /* Stop requesting EEPROM access */ 4638 if (hw->mac_type > em_82544) { 4639 eecd &= ~E1000_EECD_REQ; 4640 E1000_WRITE_REG(hw, EECD, eecd); 4641 } 4642 4643 em_swfw_sync_release(hw, E1000_SWFW_EEP_SM); 4644 } 4645 4646 /****************************************************************************** 4647 * Reads a 16 bit word from the EEPROM. 4648 * 4649 * hw - Struct containing variables accessed by shared code 4650 *****************************************************************************/ 4651 STATIC int32_t 4652 em_spi_eeprom_ready(struct em_hw *hw) 4653 { 4654 uint16_t retry_count = 0; 4655 uint8_t spi_stat_reg; 4656 4657 DEBUGFUNC("em_spi_eeprom_ready"); 4658 4659 /* Read "Status Register" repeatedly until the LSB is cleared. The 4660 * EEPROM will signal that the command has been completed by clearing 4661 * bit 0 of the internal status register. If it's not cleared within 4662 * 5 milliseconds, then error out. 4663 */ 4664 retry_count = 0; 4665 do { 4666 em_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI, 4667 hw->eeprom.opcode_bits); 4668 spi_stat_reg = (uint8_t)em_shift_in_ee_bits(hw, 8); 4669 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI)) 4670 break; 4671 4672 usec_delay(5); 4673 retry_count += 5; 4674 4675 em_standby_eeprom(hw); 4676 } while (retry_count < EEPROM_MAX_RETRY_SPI); 4677 4678 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and 4679 * only 0-5mSec on 5V devices) 4680 */ 4681 if (retry_count >= EEPROM_MAX_RETRY_SPI) { 4682 DEBUGOUT("SPI EEPROM Status error\n"); 4683 return -E1000_ERR_EEPROM; 4684 } 4685 4686 return E1000_SUCCESS; 4687 } 4688 4689 /****************************************************************************** 4690 * Reads a 16 bit word from the EEPROM. 4691 * 4692 * hw - Struct containing variables accessed by shared code 4693 * offset - offset of word in the EEPROM to read 4694 * data - word read from the EEPROM 4695 * words - number of words to read 4696 *****************************************************************************/ 4697 int32_t 4698 em_read_eeprom(struct em_hw *hw, 4699 uint16_t offset, 4700 uint16_t words, 4701 uint16_t *data) 4702 { 4703 struct em_eeprom_info *eeprom = &hw->eeprom; 4704 uint32_t i = 0; 4705 4706 DEBUGFUNC("em_read_eeprom"); 4707 4708 /* If eeprom is not yet detected, do so now */ 4709 if (eeprom->word_size == 0) 4710 em_init_eeprom_params(hw); 4711 4712 /* A check for invalid values: offset too large, too many words, and not 4713 * enough words. 4714 */ 4715 if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) || 4716 (words == 0)) { 4717 DEBUGOUT2("\"words\" parameter out of bounds. Words = %d, size = %d\n", offset, eeprom->word_size); 4718 return -E1000_ERR_EEPROM; 4719 } 4720 4721 /* EEPROM's that don't use EERD to read require us to bit-bang the SPI 4722 * directly. In this case, we need to acquire the EEPROM so that 4723 * FW or other port software does not interrupt. 4724 */ 4725 if (em_is_onboard_nvm_eeprom(hw) == TRUE && 4726 hw->eeprom.use_eerd == FALSE) { 4727 /* Prepare the EEPROM for bit-bang reading */ 4728 if (em_acquire_eeprom(hw) != E1000_SUCCESS) 4729 return -E1000_ERR_EEPROM; 4730 } 4731 4732 /* Eerd register EEPROM access requires no eeprom aquire/release */ 4733 if (eeprom->use_eerd == TRUE) 4734 return em_read_eeprom_eerd(hw, offset, words, data); 4735 4736 /* ICH EEPROM access is done via the ICH flash controller */ 4737 if (eeprom->type == em_eeprom_ich8) 4738 return em_read_eeprom_ich8(hw, offset, words, data); 4739 4740 /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have 4741 * acquired the EEPROM at this point, so any returns should relase it */ 4742 if (eeprom->type == em_eeprom_spi) { 4743 uint16_t word_in; 4744 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI; 4745 4746 if (em_spi_eeprom_ready(hw)) { 4747 em_release_eeprom(hw); 4748 return -E1000_ERR_EEPROM; 4749 } 4750 4751 em_standby_eeprom(hw); 4752 4753 /* Some SPI eeproms use the 8th address bit embedded in the opcode */ 4754 if ((eeprom->address_bits == 8) && (offset >= 128)) 4755 read_opcode |= EEPROM_A8_OPCODE_SPI; 4756 4757 /* Send the READ command (opcode + addr) */ 4758 em_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits); 4759 em_shift_out_ee_bits(hw, (uint16_t)(offset*2), eeprom->address_bits); 4760 4761 /* Read the data. The address of the eeprom internally increments with 4762 * each byte (spi) being read, saving on the overhead of eeprom setup 4763 * and tear-down. The address counter will roll over if reading beyond 4764 * the size of the eeprom, thus allowing the entire memory to be read 4765 * starting from any offset. */ 4766 for (i = 0; i < words; i++) { 4767 word_in = em_shift_in_ee_bits(hw, 16); 4768 data[i] = (word_in >> 8) | (word_in << 8); 4769 } 4770 } else if (eeprom->type == em_eeprom_microwire) { 4771 for (i = 0; i < words; i++) { 4772 /* Send the READ command (opcode + addr) */ 4773 em_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE, 4774 eeprom->opcode_bits); 4775 em_shift_out_ee_bits(hw, (uint16_t)(offset + i), 4776 eeprom->address_bits); 4777 4778 /* Read the data. For microwire, each word requires the overhead 4779 * of eeprom setup and tear-down. */ 4780 data[i] = em_shift_in_ee_bits(hw, 16); 4781 em_standby_eeprom(hw); 4782 } 4783 } 4784 4785 /* End this read operation */ 4786 em_release_eeprom(hw); 4787 4788 return E1000_SUCCESS; 4789 } 4790 4791 /****************************************************************************** 4792 * Reads a 16 bit word from the EEPROM using the EERD register. 4793 * 4794 * hw - Struct containing variables accessed by shared code 4795 * offset - offset of word in the EEPROM to read 4796 * data - word read from the EEPROM 4797 * words - number of words to read 4798 *****************************************************************************/ 4799 STATIC int32_t 4800 em_read_eeprom_eerd(struct em_hw *hw, 4801 uint16_t offset, 4802 uint16_t words, 4803 uint16_t *data) 4804 { 4805 uint32_t i, eerd = 0; 4806 int32_t error = 0; 4807 4808 for (i = 0; i < words; i++) { 4809 eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) + 4810 E1000_EEPROM_RW_REG_START; 4811 4812 E1000_WRITE_REG(hw, EERD, eerd); 4813 error = em_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ); 4814 4815 if (error) { 4816 break; 4817 } 4818 data[i] = (E1000_READ_REG(hw, EERD) >> E1000_EEPROM_RW_REG_DATA); 4819 4820 } 4821 4822 return error; 4823 } 4824 4825 /****************************************************************************** 4826 * Writes a 16 bit word from the EEPROM using the EEWR register. 4827 * 4828 * hw - Struct containing variables accessed by shared code 4829 * offset - offset of word in the EEPROM to read 4830 * data - word read from the EEPROM 4831 * words - number of words to read 4832 *****************************************************************************/ 4833 STATIC int32_t 4834 em_write_eeprom_eewr(struct em_hw *hw, 4835 uint16_t offset, 4836 uint16_t words, 4837 uint16_t *data) 4838 { 4839 uint32_t register_value = 0; 4840 uint32_t i = 0; 4841 int32_t error = 0; 4842 4843 if (em_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM)) 4844 return -E1000_ERR_SWFW_SYNC; 4845 4846 for (i = 0; i < words; i++) { 4847 register_value = (data[i] << E1000_EEPROM_RW_REG_DATA) | 4848 ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) | 4849 E1000_EEPROM_RW_REG_START; 4850 4851 error = em_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE); 4852 if (error) { 4853 break; 4854 } 4855 4856 E1000_WRITE_REG(hw, EEWR, register_value); 4857 4858 error = em_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE); 4859 4860 if (error) { 4861 break; 4862 } 4863 } 4864 4865 em_swfw_sync_release(hw, E1000_SWFW_EEP_SM); 4866 return error; 4867 } 4868 4869 /****************************************************************************** 4870 * Polls the status bit (bit 1) of the EERD to determine when the read is done. 4871 * 4872 * hw - Struct containing variables accessed by shared code 4873 *****************************************************************************/ 4874 STATIC int32_t 4875 em_poll_eerd_eewr_done(struct em_hw *hw, int eerd) 4876 { 4877 uint32_t attempts = 100000; 4878 uint32_t i, reg = 0; 4879 int32_t done = E1000_ERR_EEPROM; 4880 4881 for (i = 0; i < attempts; i++) { 4882 if (eerd == E1000_EEPROM_POLL_READ) 4883 reg = E1000_READ_REG(hw, EERD); 4884 else 4885 reg = E1000_READ_REG(hw, EEWR); 4886 4887 if (reg & E1000_EEPROM_RW_REG_DONE) { 4888 done = E1000_SUCCESS; 4889 break; 4890 } 4891 usec_delay(5); 4892 } 4893 4894 return done; 4895 } 4896 4897 /*************************************************************************** 4898 * Description: Determines if the onboard NVM is FLASH or EEPROM. 4899 * 4900 * hw - Struct containing variables accessed by shared code 4901 ****************************************************************************/ 4902 STATIC boolean_t 4903 em_is_onboard_nvm_eeprom(struct em_hw *hw) 4904 { 4905 uint32_t eecd = 0; 4906 4907 DEBUGFUNC("em_is_onboard_nvm_eeprom"); 4908 4909 if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) 4910 return FALSE; 4911 4912 if (hw->mac_type == em_82573) { 4913 eecd = E1000_READ_REG(hw, EECD); 4914 4915 /* Isolate bits 15 & 16 */ 4916 eecd = ((eecd >> 15) & 0x03); 4917 4918 /* If both bits are set, device is Flash type */ 4919 if (eecd == 0x03) { 4920 return FALSE; 4921 } 4922 } 4923 return TRUE; 4924 } 4925 4926 /****************************************************************************** 4927 * Verifies that the EEPROM has a valid checksum 4928 * 4929 * hw - Struct containing variables accessed by shared code 4930 * 4931 * Reads the first 64 16 bit words of the EEPROM and sums the values read. 4932 * If the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is 4933 * valid. 4934 *****************************************************************************/ 4935 int32_t 4936 em_validate_eeprom_checksum(struct em_hw *hw) 4937 { 4938 uint16_t checksum = 0; 4939 uint16_t i, eeprom_data; 4940 4941 DEBUGFUNC("em_validate_eeprom_checksum"); 4942 4943 if ((hw->mac_type == em_82573) && 4944 (em_is_onboard_nvm_eeprom(hw) == FALSE)) { 4945 /* Check bit 4 of word 10h. If it is 0, firmware is done updating 4946 * 10h-12h. Checksum may need to be fixed. */ 4947 em_read_eeprom(hw, 0x10, 1, &eeprom_data); 4948 if ((eeprom_data & 0x10) == 0) { 4949 /* Read 0x23 and check bit 15. This bit is a 1 when the checksum 4950 * has already been fixed. If the checksum is still wrong and this 4951 * bit is a 1, we need to return bad checksum. Otherwise, we need 4952 * to set this bit to a 1 and update the checksum. */ 4953 em_read_eeprom(hw, 0x23, 1, &eeprom_data); 4954 if ((eeprom_data & 0x8000) == 0) { 4955 eeprom_data |= 0x8000; 4956 em_write_eeprom(hw, 0x23, 1, &eeprom_data); 4957 em_update_eeprom_checksum(hw); 4958 } 4959 } 4960 } 4961 4962 if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) { 4963 /* Drivers must allocate the shadow ram structure for the 4964 * EEPROM checksum to be updated. Otherwise, this bit as well 4965 * as the checksum must both be set correctly for this 4966 * validation to pass. 4967 */ 4968 em_read_eeprom(hw, 0x19, 1, &eeprom_data); 4969 if ((eeprom_data & 0x40) == 0) { 4970 eeprom_data |= 0x40; 4971 em_write_eeprom(hw, 0x19, 1, &eeprom_data); 4972 em_update_eeprom_checksum(hw); 4973 } 4974 } 4975 4976 for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) { 4977 if (em_read_eeprom(hw, i, 1, &eeprom_data) < 0) { 4978 DEBUGOUT("EEPROM Read Error\n"); 4979 return -E1000_ERR_EEPROM; 4980 } 4981 checksum += eeprom_data; 4982 } 4983 4984 if (checksum == (uint16_t) EEPROM_SUM) 4985 return E1000_SUCCESS; 4986 else { 4987 DEBUGOUT("EEPROM Checksum Invalid\n"); 4988 return -E1000_ERR_EEPROM; 4989 } 4990 } 4991 4992 /****************************************************************************** 4993 * Calculates the EEPROM checksum and writes it to the EEPROM 4994 * 4995 * hw - Struct containing variables accessed by shared code 4996 * 4997 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA. 4998 * Writes the difference to word offset 63 of the EEPROM. 4999 *****************************************************************************/ 5000 int32_t 5001 em_update_eeprom_checksum(struct em_hw *hw) 5002 { 5003 uint32_t ctrl_ext; 5004 uint16_t checksum = 0; 5005 uint16_t i, eeprom_data; 5006 5007 DEBUGFUNC("em_update_eeprom_checksum"); 5008 5009 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) { 5010 if (em_read_eeprom(hw, i, 1, &eeprom_data) < 0) { 5011 DEBUGOUT("EEPROM Read Error\n"); 5012 return -E1000_ERR_EEPROM; 5013 } 5014 checksum += eeprom_data; 5015 } 5016 checksum = (uint16_t) EEPROM_SUM - checksum; 5017 if (em_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) { 5018 DEBUGOUT("EEPROM Write Error\n"); 5019 return -E1000_ERR_EEPROM; 5020 } else if (hw->eeprom.type == em_eeprom_flash) { 5021 em_commit_shadow_ram(hw); 5022 } else if (hw->eeprom.type == em_eeprom_ich8) { 5023 em_commit_shadow_ram(hw); 5024 /* Reload the EEPROM, or else modifications will not appear 5025 * until after next adapter reset. */ 5026 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 5027 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 5028 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 5029 msec_delay(10); 5030 } 5031 return E1000_SUCCESS; 5032 } 5033 5034 /****************************************************************************** 5035 * Parent function for writing words to the different EEPROM types. 5036 * 5037 * hw - Struct containing variables accessed by shared code 5038 * offset - offset within the EEPROM to be written to 5039 * words - number of words to write 5040 * data - 16 bit word to be written to the EEPROM 5041 * 5042 * If em_update_eeprom_checksum is not called after this function, the 5043 * EEPROM will most likely contain an invalid checksum. 5044 *****************************************************************************/ 5045 int32_t 5046 em_write_eeprom(struct em_hw *hw, 5047 uint16_t offset, 5048 uint16_t words, 5049 uint16_t *data) 5050 { 5051 struct em_eeprom_info *eeprom = &hw->eeprom; 5052 int32_t status = 0; 5053 5054 DEBUGFUNC("em_write_eeprom"); 5055 5056 /* If eeprom is not yet detected, do so now */ 5057 if (eeprom->word_size == 0) 5058 em_init_eeprom_params(hw); 5059 5060 /* A check for invalid values: offset too large, too many words, and not 5061 * enough words. 5062 */ 5063 if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) || 5064 (words == 0)) { 5065 DEBUGOUT("\"words\" parameter out of bounds\n"); 5066 return -E1000_ERR_EEPROM; 5067 } 5068 5069 /* 82573 writes only through eewr */ 5070 if (eeprom->use_eewr == TRUE) 5071 return em_write_eeprom_eewr(hw, offset, words, data); 5072 5073 if (eeprom->type == em_eeprom_ich8) 5074 return em_write_eeprom_ich8(hw, offset, words, data); 5075 5076 /* Prepare the EEPROM for writing */ 5077 if (em_acquire_eeprom(hw) != E1000_SUCCESS) 5078 return -E1000_ERR_EEPROM; 5079 5080 if (eeprom->type == em_eeprom_microwire) { 5081 status = em_write_eeprom_microwire(hw, offset, words, data); 5082 } else { 5083 status = em_write_eeprom_spi(hw, offset, words, data); 5084 msec_delay(10); 5085 } 5086 5087 /* Done with writing */ 5088 em_release_eeprom(hw); 5089 5090 return status; 5091 } 5092 5093 /****************************************************************************** 5094 * Writes a 16 bit word to a given offset in an SPI EEPROM. 5095 * 5096 * hw - Struct containing variables accessed by shared code 5097 * offset - offset within the EEPROM to be written to 5098 * words - number of words to write 5099 * data - pointer to array of 8 bit words to be written to the EEPROM 5100 * 5101 *****************************************************************************/ 5102 STATIC int32_t 5103 em_write_eeprom_spi(struct em_hw *hw, 5104 uint16_t offset, 5105 uint16_t words, 5106 uint16_t *data) 5107 { 5108 struct em_eeprom_info *eeprom = &hw->eeprom; 5109 uint16_t widx = 0; 5110 5111 DEBUGFUNC("em_write_eeprom_spi"); 5112 5113 while (widx < words) { 5114 uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI; 5115 5116 if (em_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM; 5117 5118 em_standby_eeprom(hw); 5119 5120 /* Send the WRITE ENABLE command (8 bit opcode ) */ 5121 em_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI, 5122 eeprom->opcode_bits); 5123 5124 em_standby_eeprom(hw); 5125 5126 /* Some SPI eeproms use the 8th address bit embedded in the opcode */ 5127 if ((eeprom->address_bits == 8) && (offset >= 128)) 5128 write_opcode |= EEPROM_A8_OPCODE_SPI; 5129 5130 /* Send the Write command (8-bit opcode + addr) */ 5131 em_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits); 5132 5133 em_shift_out_ee_bits(hw, (uint16_t)((offset + widx)*2), 5134 eeprom->address_bits); 5135 5136 /* Send the data */ 5137 5138 /* Loop to allow for up to whole page write (32 bytes) of eeprom */ 5139 while (widx < words) { 5140 uint16_t word_out = data[widx]; 5141 word_out = (word_out >> 8) | (word_out << 8); 5142 em_shift_out_ee_bits(hw, word_out, 16); 5143 widx++; 5144 5145 /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE 5146 * operation, while the smaller eeproms are capable of an 8-byte 5147 * PAGE WRITE operation. Break the inner loop to pass new address 5148 */ 5149 if ((((offset + widx)*2) % eeprom->page_size) == 0) { 5150 em_standby_eeprom(hw); 5151 break; 5152 } 5153 } 5154 } 5155 5156 return E1000_SUCCESS; 5157 } 5158 5159 /****************************************************************************** 5160 * Writes a 16 bit word to a given offset in a Microwire EEPROM. 5161 * 5162 * hw - Struct containing variables accessed by shared code 5163 * offset - offset within the EEPROM to be written to 5164 * words - number of words to write 5165 * data - pointer to array of 16 bit words to be written to the EEPROM 5166 * 5167 *****************************************************************************/ 5168 STATIC int32_t 5169 em_write_eeprom_microwire(struct em_hw *hw, 5170 uint16_t offset, 5171 uint16_t words, 5172 uint16_t *data) 5173 { 5174 struct em_eeprom_info *eeprom = &hw->eeprom; 5175 uint32_t eecd; 5176 uint16_t words_written = 0; 5177 uint16_t i = 0; 5178 5179 DEBUGFUNC("em_write_eeprom_microwire"); 5180 5181 /* Send the write enable command to the EEPROM (3-bit opcode plus 5182 * 6/8-bit dummy address beginning with 11). It's less work to include 5183 * the 11 of the dummy address as part of the opcode than it is to shift 5184 * it over the correct number of bits for the address. This puts the 5185 * EEPROM into write/erase mode. 5186 */ 5187 em_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE, 5188 (uint16_t)(eeprom->opcode_bits + 2)); 5189 5190 em_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2)); 5191 5192 /* Prepare the EEPROM */ 5193 em_standby_eeprom(hw); 5194 5195 while (words_written < words) { 5196 /* Send the Write command (3-bit opcode + addr) */ 5197 em_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE, 5198 eeprom->opcode_bits); 5199 5200 em_shift_out_ee_bits(hw, (uint16_t)(offset + words_written), 5201 eeprom->address_bits); 5202 5203 /* Send the data */ 5204 em_shift_out_ee_bits(hw, data[words_written], 16); 5205 5206 /* Toggle the CS line. This in effect tells the EEPROM to execute 5207 * the previous command. 5208 */ 5209 em_standby_eeprom(hw); 5210 5211 /* Read DO repeatedly until it is high (equal to '1'). The EEPROM will 5212 * signal that the command has been completed by raising the DO signal. 5213 * If DO does not go high in 10 milliseconds, then error out. 5214 */ 5215 for (i = 0; i < 200; i++) { 5216 eecd = E1000_READ_REG(hw, EECD); 5217 if (eecd & E1000_EECD_DO) break; 5218 usec_delay(50); 5219 } 5220 if (i == 200) { 5221 DEBUGOUT("EEPROM Write did not complete\n"); 5222 return -E1000_ERR_EEPROM; 5223 } 5224 5225 /* Recover from write */ 5226 em_standby_eeprom(hw); 5227 5228 words_written++; 5229 } 5230 5231 /* Send the write disable command to the EEPROM (3-bit opcode plus 5232 * 6/8-bit dummy address beginning with 10). It's less work to include 5233 * the 10 of the dummy address as part of the opcode than it is to shift 5234 * it over the correct number of bits for the address. This takes the 5235 * EEPROM out of write/erase mode. 5236 */ 5237 em_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE, 5238 (uint16_t)(eeprom->opcode_bits + 2)); 5239 5240 em_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2)); 5241 5242 return E1000_SUCCESS; 5243 } 5244 5245 /****************************************************************************** 5246 * Flushes the cached eeprom to NVM. This is done by saving the modified values 5247 * in the eeprom cache and the non modified values in the currently active bank 5248 * to the new bank. 5249 * 5250 * hw - Struct containing variables accessed by shared code 5251 * offset - offset of word in the EEPROM to read 5252 * data - word read from the EEPROM 5253 * words - number of words to read 5254 *****************************************************************************/ 5255 STATIC int32_t 5256 em_commit_shadow_ram(struct em_hw *hw) 5257 { 5258 uint32_t attempts = 100000; 5259 uint32_t eecd = 0; 5260 uint32_t flop = 0; 5261 uint32_t i = 0; 5262 int32_t error = E1000_SUCCESS; 5263 uint32_t old_bank_offset = 0; 5264 uint32_t new_bank_offset = 0; 5265 uint8_t low_byte = 0; 5266 uint8_t high_byte = 0; 5267 boolean_t sector_write_failed = FALSE; 5268 5269 if (hw->mac_type == em_82573) { 5270 /* The flop register will be used to determine if flash type is STM */ 5271 flop = E1000_READ_REG(hw, FLOP); 5272 for (i=0; i < attempts; i++) { 5273 eecd = E1000_READ_REG(hw, EECD); 5274 if ((eecd & E1000_EECD_FLUPD) == 0) { 5275 break; 5276 } 5277 usec_delay(5); 5278 } 5279 5280 if (i == attempts) { 5281 return -E1000_ERR_EEPROM; 5282 } 5283 5284 /* If STM opcode located in bits 15:8 of flop, reset firmware */ 5285 if ((flop & 0xFF00) == E1000_STM_OPCODE) { 5286 E1000_WRITE_REG(hw, HICR, E1000_HICR_FW_RESET); 5287 } 5288 5289 /* Perform the flash update */ 5290 E1000_WRITE_REG(hw, EECD, eecd | E1000_EECD_FLUPD); 5291 5292 for (i=0; i < attempts; i++) { 5293 eecd = E1000_READ_REG(hw, EECD); 5294 if ((eecd & E1000_EECD_FLUPD) == 0) { 5295 break; 5296 } 5297 usec_delay(5); 5298 } 5299 5300 if (i == attempts) { 5301 return -E1000_ERR_EEPROM; 5302 } 5303 } 5304 5305 if ((hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) && 5306 hw->eeprom_shadow_ram != NULL) { 5307 /* We're writing to the opposite bank so if we're on bank 1, 5308 * write to bank 0 etc. We also need to erase the segment that 5309 * is going to be written */ 5310 if (!(E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL)) { 5311 new_bank_offset = hw->flash_bank_size * 2; 5312 old_bank_offset = 0; 5313 em_erase_ich8_4k_segment(hw, 1); 5314 } else { 5315 old_bank_offset = hw->flash_bank_size * 2; 5316 new_bank_offset = 0; 5317 em_erase_ich8_4k_segment(hw, 0); 5318 } 5319 5320 sector_write_failed = FALSE; 5321 /* Loop for every byte in the shadow RAM, 5322 * which is in units of words. */ 5323 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 5324 /* Determine whether to write the value stored 5325 * in the other NVM bank or a modified value stored 5326 * in the shadow RAM */ 5327 if (hw->eeprom_shadow_ram[i].modified == TRUE) { 5328 low_byte = (uint8_t)hw->eeprom_shadow_ram[i].eeprom_word; 5329 usec_delay(100); 5330 error = em_verify_write_ich8_byte(hw, 5331 (i << 1) + new_bank_offset, low_byte); 5332 5333 if (error != E1000_SUCCESS) 5334 sector_write_failed = TRUE; 5335 else { 5336 high_byte = 5337 (uint8_t)(hw->eeprom_shadow_ram[i].eeprom_word >> 8); 5338 usec_delay(100); 5339 } 5340 } else { 5341 em_read_ich8_byte(hw, (i << 1) + old_bank_offset, 5342 &low_byte); 5343 usec_delay(100); 5344 error = em_verify_write_ich8_byte(hw, 5345 (i << 1) + new_bank_offset, low_byte); 5346 5347 if (error != E1000_SUCCESS) 5348 sector_write_failed = TRUE; 5349 else { 5350 em_read_ich8_byte(hw, (i << 1) + old_bank_offset + 1, 5351 &high_byte); 5352 usec_delay(100); 5353 } 5354 } 5355 5356 /* If the write of the low byte was successful, go ahread and 5357 * write the high byte while checking to make sure that if it 5358 * is the signature byte, then it is handled properly */ 5359 if (sector_write_failed == FALSE) { 5360 /* If the word is 0x13, then make sure the signature bits 5361 * (15:14) are 11b until the commit has completed. 5362 * This will allow us to write 10b which indicates the 5363 * signature is valid. We want to do this after the write 5364 * has completed so that we don't mark the segment valid 5365 * while the write is still in progress */ 5366 if (i == E1000_ICH_NVM_SIG_WORD) 5367 high_byte = E1000_ICH_NVM_SIG_MASK | high_byte; 5368 5369 error = em_verify_write_ich8_byte(hw, 5370 (i << 1) + new_bank_offset + 1, high_byte); 5371 if (error != E1000_SUCCESS) 5372 sector_write_failed = TRUE; 5373 5374 } else { 5375 /* If the write failed then break from the loop and 5376 * return an error */ 5377 break; 5378 } 5379 } 5380 5381 /* Don't bother writing the segment valid bits if sector 5382 * programming failed. */ 5383 if (sector_write_failed == FALSE) { 5384 /* Finally validate the new segment by setting bit 15:14 5385 * to 10b in word 0x13 , this can be done without an 5386 * erase as well since these bits are 11 to start with 5387 * and we need to change bit 14 to 0b */ 5388 em_read_ich8_byte(hw, 5389 E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset, 5390 &high_byte); 5391 high_byte &= 0xBF; 5392 error = em_verify_write_ich8_byte(hw, 5393 E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset, high_byte); 5394 /* And invalidate the previously valid segment by setting 5395 * its signature word (0x13) high_byte to 0b. This can be 5396 * done without an erase because flash erase sets all bits 5397 * to 1's. We can write 1's to 0's without an erase */ 5398 if (error == E1000_SUCCESS) { 5399 error = em_verify_write_ich8_byte(hw, 5400 E1000_ICH_NVM_SIG_WORD * 2 + 1 + old_bank_offset, 0); 5401 } 5402 5403 /* Clear the now not used entry in the cache */ 5404 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 5405 hw->eeprom_shadow_ram[i].modified = FALSE; 5406 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF; 5407 } 5408 } 5409 } 5410 5411 return error; 5412 } 5413 5414 /****************************************************************************** 5415 * Reads the adapter's part number from the EEPROM 5416 * 5417 * hw - Struct containing variables accessed by shared code 5418 * part_num - Adapter's part number 5419 *****************************************************************************/ 5420 int32_t 5421 em_read_part_num(struct em_hw *hw, 5422 uint32_t *part_num) 5423 { 5424 uint16_t offset = EEPROM_PBA_BYTE_1; 5425 uint16_t eeprom_data; 5426 5427 DEBUGFUNC("em_read_part_num"); 5428 5429 /* Get word 0 from EEPROM */ 5430 if (em_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { 5431 DEBUGOUT("EEPROM Read Error\n"); 5432 return -E1000_ERR_EEPROM; 5433 } 5434 /* Save word 0 in upper half of part_num */ 5435 *part_num = (uint32_t) (eeprom_data << 16); 5436 5437 /* Get word 1 from EEPROM */ 5438 if (em_read_eeprom(hw, ++offset, 1, &eeprom_data) < 0) { 5439 DEBUGOUT("EEPROM Read Error\n"); 5440 return -E1000_ERR_EEPROM; 5441 } 5442 /* Save word 1 in lower half of part_num */ 5443 *part_num |= eeprom_data; 5444 5445 return E1000_SUCCESS; 5446 } 5447 5448 /****************************************************************************** 5449 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the 5450 * second function of dual function devices 5451 * 5452 * hw - Struct containing variables accessed by shared code 5453 *****************************************************************************/ 5454 int32_t 5455 em_read_mac_addr(struct em_hw * hw) 5456 { 5457 uint16_t offset; 5458 uint16_t eeprom_data, i; 5459 5460 DEBUGFUNC("em_read_mac_addr"); 5461 5462 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) { 5463 offset = i >> 1; 5464 if (em_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { 5465 DEBUGOUT("EEPROM Read Error\n"); 5466 return -E1000_ERR_EEPROM; 5467 } 5468 hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF); 5469 hw->perm_mac_addr[i+1] = (uint8_t) (eeprom_data >> 8); 5470 } 5471 5472 switch (hw->mac_type) { 5473 default: 5474 break; 5475 case em_82546: 5476 case em_82546_rev_3: 5477 case em_82571: 5478 case em_80003es2lan: 5479 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) 5480 hw->perm_mac_addr[5] ^= 0x01; 5481 break; 5482 } 5483 5484 for (i = 0; i < NODE_ADDRESS_SIZE; i++) 5485 hw->mac_addr[i] = hw->perm_mac_addr[i]; 5486 return E1000_SUCCESS; 5487 } 5488 5489 /****************************************************************************** 5490 * Initializes receive address filters. 5491 * 5492 * hw - Struct containing variables accessed by shared code 5493 * 5494 * Places the MAC address in receive address register 0 and clears the rest 5495 * of the receive addresss registers. Clears the multicast table. Assumes 5496 * the receiver is in reset when the routine is called. 5497 *****************************************************************************/ 5498 STATIC void 5499 em_init_rx_addrs(struct em_hw *hw) 5500 { 5501 uint32_t i; 5502 uint32_t rar_num; 5503 5504 DEBUGFUNC("em_init_rx_addrs"); 5505 5506 /* Setup the receive address. */ 5507 DEBUGOUT("Programming MAC Address into RAR[0]\n"); 5508 5509 em_rar_set(hw, hw->mac_addr, 0); 5510 5511 rar_num = E1000_RAR_ENTRIES; 5512 5513 /* Reserve a spot for the Locally Administered Address to work around 5514 * an 82571 issue in which a reset on one port will reload the MAC on 5515 * the other port. */ 5516 if ((hw->mac_type == em_82571) && (hw->laa_is_present == TRUE)) 5517 rar_num -= 1; 5518 if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) 5519 rar_num = E1000_RAR_ENTRIES_ICH8LAN; 5520 if (hw->mac_type == em_ich8lan) 5521 rar_num -= 1; 5522 5523 /* Zero out the other 15 receive addresses. */ 5524 DEBUGOUT("Clearing RAR[1-15]\n"); 5525 for (i = 1; i < rar_num; i++) { 5526 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 5527 E1000_WRITE_FLUSH(hw); 5528 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 5529 E1000_WRITE_FLUSH(hw); 5530 } 5531 } 5532 5533 /****************************************************************************** 5534 * Updates the MAC's list of multicast addresses. 5535 * 5536 * hw - Struct containing variables accessed by shared code 5537 * mc_addr_list - the list of new multicast addresses 5538 * mc_addr_count - number of addresses 5539 * pad - number of bytes between addresses in the list 5540 * rar_used_count - offset where to start adding mc addresses into the RAR's 5541 * 5542 * The given list replaces any existing list. Clears the last 15 receive 5543 * address registers and the multicast table. Uses receive address registers 5544 * for the first 15 multicast addresses, and hashes the rest into the 5545 * multicast table. 5546 *****************************************************************************/ 5547 void 5548 em_mc_addr_list_update(struct em_hw *hw, 5549 uint8_t *mc_addr_list, 5550 uint32_t mc_addr_count, 5551 uint32_t pad, 5552 uint32_t rar_used_count) 5553 { 5554 uint32_t hash_value; 5555 uint32_t i; 5556 uint32_t num_rar_entry; 5557 uint32_t num_mta_entry; 5558 5559 DEBUGFUNC("em_mc_addr_list_update"); 5560 5561 /* Set the new number of MC addresses that we are being requested to use. */ 5562 hw->num_mc_addrs = mc_addr_count; 5563 5564 /* Clear RAR[1-15] */ 5565 DEBUGOUT(" Clearing RAR[1-15]\n"); 5566 num_rar_entry = E1000_RAR_ENTRIES; 5567 if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) 5568 num_rar_entry = E1000_RAR_ENTRIES_ICH8LAN; 5569 if (hw->mac_type == em_ich8lan) 5570 num_rar_entry -= 1; 5571 5572 /* Reserve a spot for the Locally Administered Address to work around 5573 * an 82571 issue in which a reset on one port will reload the MAC on 5574 * the other port. */ 5575 if ((hw->mac_type == em_82571) && (hw->laa_is_present == TRUE)) 5576 num_rar_entry -= 1; 5577 5578 for (i = rar_used_count; i < num_rar_entry; i++) { 5579 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 5580 E1000_WRITE_FLUSH(hw); 5581 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 5582 E1000_WRITE_FLUSH(hw); 5583 } 5584 5585 /* Clear the MTA */ 5586 DEBUGOUT(" Clearing MTA\n"); 5587 num_mta_entry = E1000_NUM_MTA_REGISTERS; 5588 if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) 5589 num_mta_entry = E1000_NUM_MTA_REGISTERS_ICH8LAN; 5590 5591 for (i = 0; i < num_mta_entry; i++) { 5592 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 5593 E1000_WRITE_FLUSH(hw); 5594 } 5595 5596 /* Add the new addresses */ 5597 for (i = 0; i < mc_addr_count; i++) { 5598 DEBUGOUT(" Adding the multicast addresses:\n"); 5599 DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i, 5600 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad)], 5601 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 1], 5602 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 2], 5603 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 3], 5604 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 4], 5605 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 5]); 5606 5607 hash_value = em_hash_mc_addr(hw, 5608 mc_addr_list + 5609 (i * (ETH_LENGTH_OF_ADDRESS + pad))); 5610 5611 DEBUGOUT1(" Hash value = 0x%03X\n", hash_value); 5612 5613 /* Place this multicast address in the RAR if there is room, * 5614 * else put it in the MTA 5615 */ 5616 if (rar_used_count < num_rar_entry) { 5617 em_rar_set(hw, 5618 mc_addr_list + (i * (ETH_LENGTH_OF_ADDRESS + pad)), 5619 rar_used_count); 5620 rar_used_count++; 5621 } else { 5622 em_mta_set(hw, hash_value); 5623 } 5624 } 5625 DEBUGOUT("MC Update Complete\n"); 5626 } 5627 5628 /****************************************************************************** 5629 * Hashes an address to determine its location in the multicast table 5630 * 5631 * hw - Struct containing variables accessed by shared code 5632 * mc_addr - the multicast address to hash 5633 *****************************************************************************/ 5634 uint32_t 5635 em_hash_mc_addr(struct em_hw *hw, 5636 uint8_t *mc_addr) 5637 { 5638 uint32_t hash_value = 0; 5639 5640 /* The portion of the address that is used for the hash table is 5641 * determined by the mc_filter_type setting. 5642 */ 5643 switch (hw->mc_filter_type) { 5644 /* [0] [1] [2] [3] [4] [5] 5645 * 01 AA 00 12 34 56 5646 * LSB MSB 5647 */ 5648 case 0: 5649 if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) { 5650 /* [47:38] i.e. 0x158 for above example address */ 5651 hash_value = ((mc_addr[4] >> 6) | (((uint16_t) mc_addr[5]) << 2)); 5652 } else { 5653 /* [47:36] i.e. 0x563 for above example address */ 5654 hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4)); 5655 } 5656 break; 5657 case 1: 5658 if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) { 5659 /* [46:37] i.e. 0x2B1 for above example address */ 5660 hash_value = ((mc_addr[4] >> 5) | (((uint16_t) mc_addr[5]) << 3)); 5661 } else { 5662 /* [46:35] i.e. 0xAC6 for above example address */ 5663 hash_value = ((mc_addr[4] >> 3) | (((uint16_t) mc_addr[5]) << 5)); 5664 } 5665 break; 5666 case 2: 5667 if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) { 5668 /*[45:36] i.e. 0x163 for above example address */ 5669 hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4)); 5670 } else { 5671 /* [45:34] i.e. 0x5D8 for above example address */ 5672 hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6)); 5673 } 5674 break; 5675 case 3: 5676 if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) { 5677 /* [43:34] i.e. 0x18D for above example address */ 5678 hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6)); 5679 } else { 5680 /* [43:32] i.e. 0x634 for above example address */ 5681 hash_value = ((mc_addr[4]) | (((uint16_t) mc_addr[5]) << 8)); 5682 } 5683 break; 5684 } 5685 5686 hash_value &= 0xFFF; 5687 if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) 5688 hash_value &= 0x3FF; 5689 5690 return hash_value; 5691 } 5692 5693 /****************************************************************************** 5694 * Sets the bit in the multicast table corresponding to the hash value. 5695 * 5696 * hw - Struct containing variables accessed by shared code 5697 * hash_value - Multicast address hash value 5698 *****************************************************************************/ 5699 void 5700 em_mta_set(struct em_hw *hw, 5701 uint32_t hash_value) 5702 { 5703 uint32_t hash_bit, hash_reg; 5704 uint32_t mta; 5705 uint32_t temp; 5706 5707 /* The MTA is a register array of 128 32-bit registers. 5708 * It is treated like an array of 4096 bits. We want to set 5709 * bit BitArray[hash_value]. So we figure out what register 5710 * the bit is in, read it, OR in the new bit, then write 5711 * back the new value. The register is determined by the 5712 * upper 7 bits of the hash value and the bit within that 5713 * register are determined by the lower 5 bits of the value. 5714 */ 5715 hash_reg = (hash_value >> 5) & 0x7F; 5716 if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) 5717 hash_reg &= 0x1F; 5718 5719 hash_bit = hash_value & 0x1F; 5720 5721 mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg); 5722 5723 mta |= (1 << hash_bit); 5724 5725 /* If we are on an 82544 and we are trying to write an odd offset 5726 * in the MTA, save off the previous entry before writing and 5727 * restore the old value after writing. 5728 */ 5729 if ((hw->mac_type == em_82544) && ((hash_reg & 0x1) == 1)) { 5730 temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1)); 5731 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta); 5732 E1000_WRITE_FLUSH(hw); 5733 E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp); 5734 E1000_WRITE_FLUSH(hw); 5735 } else { 5736 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta); 5737 E1000_WRITE_FLUSH(hw); 5738 } 5739 } 5740 5741 /****************************************************************************** 5742 * Puts an ethernet address into a receive address register. 5743 * 5744 * hw - Struct containing variables accessed by shared code 5745 * addr - Address to put into receive address register 5746 * index - Receive address register to write 5747 *****************************************************************************/ 5748 void 5749 em_rar_set(struct em_hw *hw, 5750 uint8_t *addr, 5751 uint32_t index) 5752 { 5753 uint32_t rar_low, rar_high; 5754 5755 /* HW expects these in little endian so we reverse the byte order 5756 * from network order (big endian) to little endian 5757 */ 5758 rar_low = ((uint32_t) addr[0] | 5759 ((uint32_t) addr[1] << 8) | 5760 ((uint32_t) addr[2] << 16) | ((uint32_t) addr[3] << 24)); 5761 rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8)); 5762 5763 /* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx 5764 * unit hang. 5765 * 5766 * Description: 5767 * If there are any Rx frames queued up or otherwise present in the HW 5768 * before RSS is enabled, and then we enable RSS, the HW Rx unit will 5769 * hang. To work around this issue, we have to disable receives and 5770 * flush out all Rx frames before we enable RSS. To do so, we modify we 5771 * redirect all Rx traffic to manageability and then reset the HW. 5772 * This flushes away Rx frames, and (since the redirections to 5773 * manageability persists across resets) keeps new ones from coming in 5774 * while we work. Then, we clear the Address Valid AV bit for all MAC 5775 * addresses and undo the re-direction to manageability. 5776 * Now, frames are coming in again, but the MAC won't accept them, so 5777 * far so good. We now proceed to initialize RSS (if necessary) and 5778 * configure the Rx unit. Last, we re-enable the AV bits and continue 5779 * on our merry way. 5780 */ 5781 switch (hw->mac_type) { 5782 case em_82571: 5783 case em_82572: 5784 case em_80003es2lan: 5785 if (hw->leave_av_bit_off == TRUE) 5786 break; 5787 default: 5788 /* Indicate to hardware the Address is Valid. */ 5789 rar_high |= E1000_RAH_AV; 5790 break; 5791 } 5792 5793 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low); 5794 E1000_WRITE_FLUSH(hw); 5795 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high); 5796 E1000_WRITE_FLUSH(hw); 5797 } 5798 5799 /****************************************************************************** 5800 * Clears the VLAN filer table 5801 * 5802 * hw - Struct containing variables accessed by shared code 5803 *****************************************************************************/ 5804 STATIC void 5805 em_clear_vfta(struct em_hw *hw) 5806 { 5807 uint32_t offset; 5808 uint32_t vfta_value = 0; 5809 uint32_t vfta_offset = 0; 5810 uint32_t vfta_bit_in_reg = 0; 5811 5812 if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) 5813 return; 5814 5815 if (hw->mac_type == em_82573) { 5816 if (hw->mng_cookie.vlan_id != 0) { 5817 /* The VFTA is a 4096b bit-field, each identifying a single VLAN 5818 * ID. The following operations determine which 32b entry 5819 * (i.e. offset) into the array we want to set the VLAN ID 5820 * (i.e. bit) of the manageability unit. */ 5821 vfta_offset = (hw->mng_cookie.vlan_id >> 5822 E1000_VFTA_ENTRY_SHIFT) & 5823 E1000_VFTA_ENTRY_MASK; 5824 vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id & 5825 E1000_VFTA_ENTRY_BIT_SHIFT_MASK); 5826 } 5827 } 5828 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 5829 /* If the offset we want to clear is the same offset of the 5830 * manageability VLAN ID, then clear all bits except that of the 5831 * manageability unit */ 5832 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; 5833 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value); 5834 E1000_WRITE_FLUSH(hw); 5835 } 5836 } 5837 5838 STATIC int32_t 5839 em_id_led_init(struct em_hw * hw) 5840 { 5841 uint32_t ledctl; 5842 const uint32_t ledctl_mask = 0x000000FF; 5843 const uint32_t ledctl_on = E1000_LEDCTL_MODE_LED_ON; 5844 const uint32_t ledctl_off = E1000_LEDCTL_MODE_LED_OFF; 5845 uint16_t eeprom_data, i, temp; 5846 const uint16_t led_mask = 0x0F; 5847 5848 DEBUGFUNC("em_id_led_init"); 5849 5850 if (hw->mac_type < em_82540) { 5851 /* Nothing to do */ 5852 return E1000_SUCCESS; 5853 } 5854 5855 ledctl = E1000_READ_REG(hw, LEDCTL); 5856 hw->ledctl_default = ledctl; 5857 hw->ledctl_mode1 = hw->ledctl_default; 5858 hw->ledctl_mode2 = hw->ledctl_default; 5859 5860 if (em_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) { 5861 DEBUGOUT("EEPROM Read Error\n"); 5862 return -E1000_ERR_EEPROM; 5863 } 5864 5865 if ((hw->mac_type == em_82573) && 5866 (eeprom_data == ID_LED_RESERVED_82573)) 5867 eeprom_data = ID_LED_DEFAULT_82573; 5868 else if ((eeprom_data == ID_LED_RESERVED_0000) || 5869 (eeprom_data == ID_LED_RESERVED_FFFF)) { 5870 if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) 5871 eeprom_data = ID_LED_DEFAULT_ICH8LAN; 5872 else 5873 eeprom_data = ID_LED_DEFAULT; 5874 } 5875 5876 for (i = 0; i < 4; i++) { 5877 temp = (eeprom_data >> (i << 2)) & led_mask; 5878 switch (temp) { 5879 case ID_LED_ON1_DEF2: 5880 case ID_LED_ON1_ON2: 5881 case ID_LED_ON1_OFF2: 5882 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 5883 hw->ledctl_mode1 |= ledctl_on << (i << 3); 5884 break; 5885 case ID_LED_OFF1_DEF2: 5886 case ID_LED_OFF1_ON2: 5887 case ID_LED_OFF1_OFF2: 5888 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 5889 hw->ledctl_mode1 |= ledctl_off << (i << 3); 5890 break; 5891 default: 5892 /* Do nothing */ 5893 break; 5894 } 5895 switch (temp) { 5896 case ID_LED_DEF1_ON2: 5897 case ID_LED_ON1_ON2: 5898 case ID_LED_OFF1_ON2: 5899 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 5900 hw->ledctl_mode2 |= ledctl_on << (i << 3); 5901 break; 5902 case ID_LED_DEF1_OFF2: 5903 case ID_LED_ON1_OFF2: 5904 case ID_LED_OFF1_OFF2: 5905 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 5906 hw->ledctl_mode2 |= ledctl_off << (i << 3); 5907 break; 5908 default: 5909 /* Do nothing */ 5910 break; 5911 } 5912 } 5913 return E1000_SUCCESS; 5914 } 5915 5916 /****************************************************************************** 5917 * Clears all hardware statistics counters. 5918 * 5919 * hw - Struct containing variables accessed by shared code 5920 *****************************************************************************/ 5921 void 5922 em_clear_hw_cntrs(struct em_hw *hw) 5923 { 5924 volatile uint32_t temp; 5925 5926 temp = E1000_READ_REG(hw, CRCERRS); 5927 temp = E1000_READ_REG(hw, SYMERRS); 5928 temp = E1000_READ_REG(hw, MPC); 5929 temp = E1000_READ_REG(hw, SCC); 5930 temp = E1000_READ_REG(hw, ECOL); 5931 temp = E1000_READ_REG(hw, MCC); 5932 temp = E1000_READ_REG(hw, LATECOL); 5933 temp = E1000_READ_REG(hw, COLC); 5934 temp = E1000_READ_REG(hw, DC); 5935 temp = E1000_READ_REG(hw, SEC); 5936 temp = E1000_READ_REG(hw, RLEC); 5937 temp = E1000_READ_REG(hw, XONRXC); 5938 temp = E1000_READ_REG(hw, XONTXC); 5939 temp = E1000_READ_REG(hw, XOFFRXC); 5940 temp = E1000_READ_REG(hw, XOFFTXC); 5941 temp = E1000_READ_REG(hw, FCRUC); 5942 5943 if (hw->mac_type != em_ich8lan && hw->mac_type != em_ich9lan) { 5944 temp = E1000_READ_REG(hw, PRC64); 5945 temp = E1000_READ_REG(hw, PRC127); 5946 temp = E1000_READ_REG(hw, PRC255); 5947 temp = E1000_READ_REG(hw, PRC511); 5948 temp = E1000_READ_REG(hw, PRC1023); 5949 temp = E1000_READ_REG(hw, PRC1522); 5950 } 5951 5952 temp = E1000_READ_REG(hw, GPRC); 5953 temp = E1000_READ_REG(hw, BPRC); 5954 temp = E1000_READ_REG(hw, MPRC); 5955 temp = E1000_READ_REG(hw, GPTC); 5956 temp = E1000_READ_REG(hw, GORCL); 5957 temp = E1000_READ_REG(hw, GORCH); 5958 temp = E1000_READ_REG(hw, GOTCL); 5959 temp = E1000_READ_REG(hw, GOTCH); 5960 temp = E1000_READ_REG(hw, RNBC); 5961 temp = E1000_READ_REG(hw, RUC); 5962 temp = E1000_READ_REG(hw, RFC); 5963 temp = E1000_READ_REG(hw, ROC); 5964 temp = E1000_READ_REG(hw, RJC); 5965 temp = E1000_READ_REG(hw, TORL); 5966 temp = E1000_READ_REG(hw, TORH); 5967 temp = E1000_READ_REG(hw, TOTL); 5968 temp = E1000_READ_REG(hw, TOTH); 5969 temp = E1000_READ_REG(hw, TPR); 5970 temp = E1000_READ_REG(hw, TPT); 5971 5972 if (hw->mac_type != em_ich8lan && hw->mac_type != em_ich9lan) { 5973 temp = E1000_READ_REG(hw, PTC64); 5974 temp = E1000_READ_REG(hw, PTC127); 5975 temp = E1000_READ_REG(hw, PTC255); 5976 temp = E1000_READ_REG(hw, PTC511); 5977 temp = E1000_READ_REG(hw, PTC1023); 5978 temp = E1000_READ_REG(hw, PTC1522); 5979 } 5980 5981 temp = E1000_READ_REG(hw, MPTC); 5982 temp = E1000_READ_REG(hw, BPTC); 5983 5984 if (hw->mac_type < em_82543) return; 5985 5986 temp = E1000_READ_REG(hw, ALGNERRC); 5987 temp = E1000_READ_REG(hw, RXERRC); 5988 temp = E1000_READ_REG(hw, TNCRS); 5989 temp = E1000_READ_REG(hw, CEXTERR); 5990 temp = E1000_READ_REG(hw, TSCTC); 5991 temp = E1000_READ_REG(hw, TSCTFC); 5992 5993 if (hw->mac_type <= em_82544) return; 5994 5995 temp = E1000_READ_REG(hw, MGTPRC); 5996 temp = E1000_READ_REG(hw, MGTPDC); 5997 temp = E1000_READ_REG(hw, MGTPTC); 5998 5999 if (hw->mac_type <= em_82547_rev_2) return; 6000 6001 temp = E1000_READ_REG(hw, IAC); 6002 temp = E1000_READ_REG(hw, ICRXOC); 6003 6004 if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) 6005 return; 6006 6007 temp = E1000_READ_REG(hw, ICRXPTC); 6008 temp = E1000_READ_REG(hw, ICRXATC); 6009 temp = E1000_READ_REG(hw, ICTXPTC); 6010 temp = E1000_READ_REG(hw, ICTXATC); 6011 temp = E1000_READ_REG(hw, ICTXQEC); 6012 temp = E1000_READ_REG(hw, ICTXQMTC); 6013 temp = E1000_READ_REG(hw, ICRXDMTC); 6014 } 6015 6016 /****************************************************************************** 6017 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT 6018 * 6019 * hw - Struct containing variables accessed by shared code 6020 * frame_len - The length of the frame in question 6021 * mac_addr - The Ethernet destination address of the frame in question 6022 *****************************************************************************/ 6023 void 6024 em_tbi_adjust_stats(struct em_hw *hw, 6025 struct em_hw_stats *stats, 6026 uint32_t frame_len, 6027 uint8_t *mac_addr) 6028 { 6029 uint64_t carry_bit; 6030 6031 /* First adjust the frame length. */ 6032 frame_len--; 6033 /* We need to adjust the statistics counters, since the hardware 6034 * counters overcount this packet as a CRC error and undercount 6035 * the packet as a good packet 6036 */ 6037 /* This packet should not be counted as a CRC error. */ 6038 stats->crcerrs--; 6039 /* This packet does count as a Good Packet Received. */ 6040 stats->gprc++; 6041 6042 /* Adjust the Good Octets received counters */ 6043 carry_bit = 0x80000000 & stats->gorcl; 6044 stats->gorcl += frame_len; 6045 /* If the high bit of Gorcl (the low 32 bits of the Good Octets 6046 * Received Count) was one before the addition, 6047 * AND it is zero after, then we lost the carry out, 6048 * need to add one to Gorch (Good Octets Received Count High). 6049 * This could be simplified if all environments supported 6050 * 64-bit integers. 6051 */ 6052 if (carry_bit && ((stats->gorcl & 0x80000000) == 0)) 6053 stats->gorch++; 6054 /* Is this a broadcast or multicast? Check broadcast first, 6055 * since the test for a multicast frame will test positive on 6056 * a broadcast frame. 6057 */ 6058 if ((mac_addr[0] == (uint8_t) 0xff) && (mac_addr[1] == (uint8_t) 0xff)) 6059 /* Broadcast packet */ 6060 stats->bprc++; 6061 else if (*mac_addr & 0x01) 6062 /* Multicast packet */ 6063 stats->mprc++; 6064 6065 if (frame_len == hw->max_frame_size) { 6066 /* In this case, the hardware has overcounted the number of 6067 * oversize frames. 6068 */ 6069 if (stats->roc > 0) 6070 stats->roc--; 6071 } 6072 6073 /* Adjust the bin counters when the extra byte put the frame in the 6074 * wrong bin. Remember that the frame_len was adjusted above. 6075 */ 6076 if (frame_len == 64) { 6077 stats->prc64++; 6078 stats->prc127--; 6079 } else if (frame_len == 127) { 6080 stats->prc127++; 6081 stats->prc255--; 6082 } else if (frame_len == 255) { 6083 stats->prc255++; 6084 stats->prc511--; 6085 } else if (frame_len == 511) { 6086 stats->prc511++; 6087 stats->prc1023--; 6088 } else if (frame_len == 1023) { 6089 stats->prc1023++; 6090 stats->prc1522--; 6091 } else if (frame_len == 1522) { 6092 stats->prc1522++; 6093 } 6094 } 6095 6096 /****************************************************************************** 6097 * Gets the current PCI bus type, speed, and width of the hardware 6098 * 6099 * hw - Struct containing variables accessed by shared code 6100 *****************************************************************************/ 6101 void 6102 em_get_bus_info(struct em_hw *hw) 6103 { 6104 int32_t ret_val; 6105 uint16_t pci_ex_link_status; 6106 uint32_t status; 6107 6108 switch (hw->mac_type) { 6109 case em_82542_rev2_0: 6110 case em_82542_rev2_1: 6111 hw->bus_type = em_bus_type_unknown; 6112 hw->bus_speed = em_bus_speed_unknown; 6113 hw->bus_width = em_bus_width_unknown; 6114 break; 6115 case em_82571: 6116 case em_82572: 6117 case em_82573: 6118 case em_80003es2lan: 6119 hw->bus_type = em_bus_type_pci_express; 6120 hw->bus_speed = em_bus_speed_2500; 6121 ret_val = em_read_pcie_cap_reg(hw, 6122 PCI_EX_LINK_STATUS, 6123 &pci_ex_link_status); 6124 if (ret_val) 6125 hw->bus_width = em_bus_width_unknown; 6126 else 6127 hw->bus_width = (pci_ex_link_status & PCI_EX_LINK_WIDTH_MASK) >> 6128 PCI_EX_LINK_WIDTH_SHIFT; 6129 break; 6130 case em_ich8lan: 6131 case em_ich9lan: 6132 hw->bus_type = em_bus_type_pci_express; 6133 hw->bus_speed = em_bus_speed_2500; 6134 hw->bus_width = em_bus_width_pciex_1; 6135 break; 6136 default: 6137 status = E1000_READ_REG(hw, STATUS); 6138 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ? 6139 em_bus_type_pcix : em_bus_type_pci; 6140 6141 if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) { 6142 hw->bus_speed = (hw->bus_type == em_bus_type_pci) ? 6143 em_bus_speed_66 : em_bus_speed_120; 6144 } else if (hw->bus_type == em_bus_type_pci) { 6145 hw->bus_speed = (status & E1000_STATUS_PCI66) ? 6146 em_bus_speed_66 : em_bus_speed_33; 6147 } else { 6148 switch (status & E1000_STATUS_PCIX_SPEED) { 6149 case E1000_STATUS_PCIX_SPEED_66: 6150 hw->bus_speed = em_bus_speed_66; 6151 break; 6152 case E1000_STATUS_PCIX_SPEED_100: 6153 hw->bus_speed = em_bus_speed_100; 6154 break; 6155 case E1000_STATUS_PCIX_SPEED_133: 6156 hw->bus_speed = em_bus_speed_133; 6157 break; 6158 default: 6159 hw->bus_speed = em_bus_speed_reserved; 6160 break; 6161 } 6162 } 6163 hw->bus_width = (status & E1000_STATUS_BUS64) ? 6164 em_bus_width_64 : em_bus_width_32; 6165 break; 6166 } 6167 } 6168 6169 /****************************************************************************** 6170 * Writes a value to one of the devices registers using port I/O (as opposed to 6171 * memory mapped I/O). Only 82544 and newer devices support port I/O. 6172 * 6173 * hw - Struct containing variables accessed by shared code 6174 * offset - offset to write to 6175 * value - value to write 6176 *****************************************************************************/ 6177 STATIC void 6178 em_write_reg_io(struct em_hw *hw, 6179 uint32_t offset, 6180 uint32_t value) 6181 { 6182 unsigned long io_addr = hw->io_base; 6183 unsigned long io_data = hw->io_base + 4; 6184 6185 em_io_write(hw, io_addr, offset); 6186 em_io_write(hw, io_data, value); 6187 } 6188 6189 /****************************************************************************** 6190 * Estimates the cable length. 6191 * 6192 * hw - Struct containing variables accessed by shared code 6193 * min_length - The estimated minimum length 6194 * max_length - The estimated maximum length 6195 * 6196 * returns: - E1000_ERR_XXX 6197 * E1000_SUCCESS 6198 * 6199 * This function always returns a ranged length (minimum & maximum). 6200 * So for M88 phy's, this function interprets the one value returned from the 6201 * register to the minimum and maximum range. 6202 * For IGP phy's, the function calculates the range by the AGC registers. 6203 *****************************************************************************/ 6204 STATIC int32_t 6205 em_get_cable_length(struct em_hw *hw, 6206 uint16_t *min_length, 6207 uint16_t *max_length) 6208 { 6209 int32_t ret_val; 6210 uint16_t agc_value = 0; 6211 uint16_t i, phy_data; 6212 uint16_t cable_length; 6213 6214 DEBUGFUNC("em_get_cable_length"); 6215 6216 *min_length = *max_length = 0; 6217 6218 /* Use old method for Phy older than IGP */ 6219 if (hw->phy_type == em_phy_m88) { 6220 6221 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, 6222 &phy_data); 6223 if (ret_val) 6224 return ret_val; 6225 cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 6226 M88E1000_PSSR_CABLE_LENGTH_SHIFT; 6227 6228 /* Convert the enum value to ranged values */ 6229 switch (cable_length) { 6230 case em_cable_length_50: 6231 *min_length = 0; 6232 *max_length = em_igp_cable_length_50; 6233 break; 6234 case em_cable_length_50_80: 6235 *min_length = em_igp_cable_length_50; 6236 *max_length = em_igp_cable_length_80; 6237 break; 6238 case em_cable_length_80_110: 6239 *min_length = em_igp_cable_length_80; 6240 *max_length = em_igp_cable_length_110; 6241 break; 6242 case em_cable_length_110_140: 6243 *min_length = em_igp_cable_length_110; 6244 *max_length = em_igp_cable_length_140; 6245 break; 6246 case em_cable_length_140: 6247 *min_length = em_igp_cable_length_140; 6248 *max_length = em_igp_cable_length_170; 6249 break; 6250 default: 6251 return -E1000_ERR_PHY; 6252 break; 6253 } 6254 } else if (hw->phy_type == em_phy_gg82563) { 6255 ret_val = em_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE, 6256 &phy_data); 6257 if (ret_val) 6258 return ret_val; 6259 cable_length = phy_data & GG82563_DSPD_CABLE_LENGTH; 6260 6261 switch (cable_length) { 6262 case em_gg_cable_length_60: 6263 *min_length = 0; 6264 *max_length = em_igp_cable_length_60; 6265 break; 6266 case em_gg_cable_length_60_115: 6267 *min_length = em_igp_cable_length_60; 6268 *max_length = em_igp_cable_length_115; 6269 break; 6270 case em_gg_cable_length_115_150: 6271 *min_length = em_igp_cable_length_115; 6272 *max_length = em_igp_cable_length_150; 6273 break; 6274 case em_gg_cable_length_150: 6275 *min_length = em_igp_cable_length_150; 6276 *max_length = em_igp_cable_length_180; 6277 break; 6278 default: 6279 return -E1000_ERR_PHY; 6280 break; 6281 } 6282 } else if (hw->phy_type == em_phy_igp) { /* For IGP PHY */ 6283 uint16_t cur_agc_value; 6284 uint16_t min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE; 6285 uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = 6286 {IGP01E1000_PHY_AGC_A, 6287 IGP01E1000_PHY_AGC_B, 6288 IGP01E1000_PHY_AGC_C, 6289 IGP01E1000_PHY_AGC_D}; 6290 /* Read the AGC registers for all channels */ 6291 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 6292 6293 ret_val = em_read_phy_reg(hw, agc_reg_array[i], &phy_data); 6294 if (ret_val) 6295 return ret_val; 6296 6297 cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT; 6298 6299 /* Value bound check. */ 6300 if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) || 6301 (cur_agc_value == 0)) 6302 return -E1000_ERR_PHY; 6303 6304 agc_value += cur_agc_value; 6305 6306 /* Update minimal AGC value. */ 6307 if (min_agc_value > cur_agc_value) 6308 min_agc_value = cur_agc_value; 6309 } 6310 6311 /* Remove the minimal AGC result for length < 50m */ 6312 if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * em_igp_cable_length_50) { 6313 agc_value -= min_agc_value; 6314 6315 /* Get the average length of the remaining 3 channels */ 6316 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1); 6317 } else { 6318 /* Get the average length of all the 4 channels. */ 6319 agc_value /= IGP01E1000_PHY_CHANNEL_NUM; 6320 } 6321 6322 /* Set the range of the calculated length. */ 6323 *min_length = ((em_igp_cable_length_table[agc_value] - 6324 IGP01E1000_AGC_RANGE) > 0) ? 6325 (em_igp_cable_length_table[agc_value] - 6326 IGP01E1000_AGC_RANGE) : 0; 6327 *max_length = em_igp_cable_length_table[agc_value] + 6328 IGP01E1000_AGC_RANGE; 6329 } else if (hw->phy_type == em_phy_igp_2 || 6330 hw->phy_type == em_phy_igp_3) { 6331 uint16_t cur_agc_index, max_agc_index = 0; 6332 uint16_t min_agc_index = IGP02E1000_AGC_LENGTH_TABLE_SIZE - 1; 6333 uint16_t agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = 6334 {IGP02E1000_PHY_AGC_A, 6335 IGP02E1000_PHY_AGC_B, 6336 IGP02E1000_PHY_AGC_C, 6337 IGP02E1000_PHY_AGC_D}; 6338 /* Read the AGC registers for all channels */ 6339 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { 6340 ret_val = em_read_phy_reg(hw, agc_reg_array[i], &phy_data); 6341 if (ret_val) 6342 return ret_val; 6343 6344 /* Getting bits 15:9, which represent the combination of course and 6345 * fine gain values. The result is a number that can be put into 6346 * the lookup table to obtain the approximate cable length. */ 6347 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & 6348 IGP02E1000_AGC_LENGTH_MASK; 6349 6350 /* Array index bound check. */ 6351 if ((cur_agc_index >= IGP02E1000_AGC_LENGTH_TABLE_SIZE) || 6352 (cur_agc_index == 0)) 6353 return -E1000_ERR_PHY; 6354 6355 /* Remove min & max AGC values from calculation. */ 6356 if (em_igp_2_cable_length_table[min_agc_index] > 6357 em_igp_2_cable_length_table[cur_agc_index]) 6358 min_agc_index = cur_agc_index; 6359 if (em_igp_2_cable_length_table[max_agc_index] < 6360 em_igp_2_cable_length_table[cur_agc_index]) 6361 max_agc_index = cur_agc_index; 6362 6363 agc_value += em_igp_2_cable_length_table[cur_agc_index]; 6364 } 6365 6366 agc_value -= (em_igp_2_cable_length_table[min_agc_index] + 6367 em_igp_2_cable_length_table[max_agc_index]); 6368 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); 6369 6370 /* Calculate cable length with the error range of +/- 10 meters. */ 6371 *min_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ? 6372 (agc_value - IGP02E1000_AGC_RANGE) : 0; 6373 *max_length = agc_value + IGP02E1000_AGC_RANGE; 6374 } 6375 6376 return E1000_SUCCESS; 6377 } 6378 6379 /****************************************************************************** 6380 * Check if Downshift occured 6381 * 6382 * hw - Struct containing variables accessed by shared code 6383 * downshift - output parameter : 0 - No Downshift ocured. 6384 * 1 - Downshift ocured. 6385 * 6386 * returns: - E1000_ERR_XXX 6387 * E1000_SUCCESS 6388 * 6389 * For phy's older then IGP, this function reads the Downshift bit in the Phy 6390 * Specific Status register. For IGP phy's, it reads the Downgrade bit in the 6391 * Link Health register. In IGP this bit is latched high, so the driver must 6392 * read it immediately after link is established. 6393 *****************************************************************************/ 6394 STATIC int32_t 6395 em_check_downshift(struct em_hw *hw) 6396 { 6397 int32_t ret_val; 6398 uint16_t phy_data; 6399 6400 DEBUGFUNC("em_check_downshift"); 6401 6402 if (hw->phy_type == em_phy_igp || 6403 hw->phy_type == em_phy_igp_3 || 6404 hw->phy_type == em_phy_igp_2) { 6405 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH, 6406 &phy_data); 6407 if (ret_val) 6408 return ret_val; 6409 6410 hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0; 6411 } else if ((hw->phy_type == em_phy_m88) || 6412 (hw->phy_type == em_phy_gg82563)) { 6413 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, 6414 &phy_data); 6415 if (ret_val) 6416 return ret_val; 6417 6418 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >> 6419 M88E1000_PSSR_DOWNSHIFT_SHIFT; 6420 } else if (hw->phy_type == em_phy_ife) { 6421 /* em_phy_ife supports 10/100 speed only */ 6422 hw->speed_downgraded = FALSE; 6423 } 6424 6425 return E1000_SUCCESS; 6426 } 6427 6428 /***************************************************************************** 6429 * 6430 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a 6431 * gigabit link is achieved to improve link quality. 6432 * 6433 * hw: Struct containing variables accessed by shared code 6434 * 6435 * returns: - E1000_ERR_PHY if fail to read/write the PHY 6436 * E1000_SUCCESS at any other case. 6437 * 6438 ****************************************************************************/ 6439 6440 STATIC int32_t 6441 em_config_dsp_after_link_change(struct em_hw *hw, 6442 boolean_t link_up) 6443 { 6444 int32_t ret_val; 6445 uint16_t phy_data, phy_saved_data, speed, duplex, i; 6446 uint16_t dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = 6447 {IGP01E1000_PHY_AGC_PARAM_A, 6448 IGP01E1000_PHY_AGC_PARAM_B, 6449 IGP01E1000_PHY_AGC_PARAM_C, 6450 IGP01E1000_PHY_AGC_PARAM_D}; 6451 uint16_t min_length, max_length; 6452 6453 DEBUGFUNC("em_config_dsp_after_link_change"); 6454 6455 if (hw->phy_type != em_phy_igp) 6456 return E1000_SUCCESS; 6457 6458 if (link_up) { 6459 ret_val = em_get_speed_and_duplex(hw, &speed, &duplex); 6460 if (ret_val) { 6461 DEBUGOUT("Error getting link speed and duplex\n"); 6462 return ret_val; 6463 } 6464 6465 if (speed == SPEED_1000) { 6466 6467 ret_val = em_get_cable_length(hw, &min_length, &max_length); 6468 if (ret_val) 6469 return ret_val; 6470 6471 if ((hw->dsp_config_state == em_dsp_config_enabled) && 6472 min_length >= em_igp_cable_length_50) { 6473 6474 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 6475 ret_val = em_read_phy_reg(hw, dsp_reg_array[i], 6476 &phy_data); 6477 if (ret_val) 6478 return ret_val; 6479 6480 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; 6481 6482 ret_val = em_write_phy_reg(hw, dsp_reg_array[i], 6483 phy_data); 6484 if (ret_val) 6485 return ret_val; 6486 } 6487 hw->dsp_config_state = em_dsp_config_activated; 6488 } 6489 6490 if ((hw->ffe_config_state == em_ffe_config_enabled) && 6491 (min_length < em_igp_cable_length_50)) { 6492 6493 uint16_t ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20; 6494 uint32_t idle_errs = 0; 6495 6496 /* clear previous idle error counts */ 6497 ret_val = em_read_phy_reg(hw, PHY_1000T_STATUS, 6498 &phy_data); 6499 if (ret_val) 6500 return ret_val; 6501 6502 for (i = 0; i < ffe_idle_err_timeout; i++) { 6503 usec_delay(1000); 6504 ret_val = em_read_phy_reg(hw, PHY_1000T_STATUS, 6505 &phy_data); 6506 if (ret_val) 6507 return ret_val; 6508 6509 idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT); 6510 if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) { 6511 hw->ffe_config_state = em_ffe_config_active; 6512 6513 ret_val = em_write_phy_reg(hw, 6514 IGP01E1000_PHY_DSP_FFE, 6515 IGP01E1000_PHY_DSP_FFE_CM_CP); 6516 if (ret_val) 6517 return ret_val; 6518 break; 6519 } 6520 6521 if (idle_errs) 6522 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_100; 6523 } 6524 } 6525 } 6526 } else { 6527 if (hw->dsp_config_state == em_dsp_config_activated) { 6528 /* Save off the current value of register 0x2F5B to be restored at 6529 * the end of the routines. */ 6530 ret_val = em_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 6531 6532 if (ret_val) 6533 return ret_val; 6534 6535 /* Disable the PHY transmitter */ 6536 ret_val = em_write_phy_reg(hw, 0x2F5B, 0x0003); 6537 6538 if (ret_val) 6539 return ret_val; 6540 6541 msec_delay_irq(20); 6542 6543 ret_val = em_write_phy_reg(hw, 0x0000, 6544 IGP01E1000_IEEE_FORCE_GIGA); 6545 if (ret_val) 6546 return ret_val; 6547 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 6548 ret_val = em_read_phy_reg(hw, dsp_reg_array[i], &phy_data); 6549 if (ret_val) 6550 return ret_val; 6551 6552 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; 6553 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS; 6554 6555 ret_val = em_write_phy_reg(hw,dsp_reg_array[i], phy_data); 6556 if (ret_val) 6557 return ret_val; 6558 } 6559 6560 ret_val = em_write_phy_reg(hw, 0x0000, 6561 IGP01E1000_IEEE_RESTART_AUTONEG); 6562 if (ret_val) 6563 return ret_val; 6564 6565 msec_delay_irq(20); 6566 6567 /* Now enable the transmitter */ 6568 ret_val = em_write_phy_reg(hw, 0x2F5B, phy_saved_data); 6569 6570 if (ret_val) 6571 return ret_val; 6572 6573 hw->dsp_config_state = em_dsp_config_enabled; 6574 } 6575 6576 if (hw->ffe_config_state == em_ffe_config_active) { 6577 /* Save off the current value of register 0x2F5B to be restored at 6578 * the end of the routines. */ 6579 ret_val = em_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 6580 6581 if (ret_val) 6582 return ret_val; 6583 6584 /* Disable the PHY transmitter */ 6585 ret_val = em_write_phy_reg(hw, 0x2F5B, 0x0003); 6586 6587 if (ret_val) 6588 return ret_val; 6589 6590 msec_delay_irq(20); 6591 6592 ret_val = em_write_phy_reg(hw, 0x0000, 6593 IGP01E1000_IEEE_FORCE_GIGA); 6594 if (ret_val) 6595 return ret_val; 6596 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE, 6597 IGP01E1000_PHY_DSP_FFE_DEFAULT); 6598 if (ret_val) 6599 return ret_val; 6600 6601 ret_val = em_write_phy_reg(hw, 0x0000, 6602 IGP01E1000_IEEE_RESTART_AUTONEG); 6603 if (ret_val) 6604 return ret_val; 6605 6606 msec_delay_irq(20); 6607 6608 /* Now enable the transmitter */ 6609 ret_val = em_write_phy_reg(hw, 0x2F5B, phy_saved_data); 6610 6611 if (ret_val) 6612 return ret_val; 6613 6614 hw->ffe_config_state = em_ffe_config_enabled; 6615 } 6616 } 6617 return E1000_SUCCESS; 6618 } 6619 6620 /***************************************************************************** 6621 * Set PHY to class A mode 6622 * Assumes the following operations will follow to enable the new class mode. 6623 * 1. Do a PHY soft reset 6624 * 2. Restart auto-negotiation or force link. 6625 * 6626 * hw - Struct containing variables accessed by shared code 6627 ****************************************************************************/ 6628 static int32_t 6629 em_set_phy_mode(struct em_hw *hw) 6630 { 6631 int32_t ret_val; 6632 uint16_t eeprom_data; 6633 6634 DEBUGFUNC("em_set_phy_mode"); 6635 6636 if ((hw->mac_type == em_82545_rev_3) && 6637 (hw->media_type == em_media_type_copper)) { 6638 ret_val = em_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, &eeprom_data); 6639 if (ret_val) { 6640 return ret_val; 6641 } 6642 6643 if ((eeprom_data != EEPROM_RESERVED_WORD) && 6644 (eeprom_data & EEPROM_PHY_CLASS_A)) { 6645 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x000B); 6646 if (ret_val) 6647 return ret_val; 6648 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x8104); 6649 if (ret_val) 6650 return ret_val; 6651 6652 hw->phy_reset_disable = FALSE; 6653 } 6654 } 6655 6656 return E1000_SUCCESS; 6657 } 6658 6659 /***************************************************************************** 6660 * 6661 * This function sets the lplu state according to the active flag. When 6662 * activating lplu this function also disables smart speed and vise versa. 6663 * lplu will not be activated unless the device autonegotiation advertisement 6664 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. 6665 * hw: Struct containing variables accessed by shared code 6666 * active - true to enable lplu false to disable lplu. 6667 * 6668 * returns: - E1000_ERR_PHY if fail to read/write the PHY 6669 * E1000_SUCCESS at any other case. 6670 * 6671 ****************************************************************************/ 6672 6673 STATIC int32_t 6674 em_set_d3_lplu_state(struct em_hw *hw, 6675 boolean_t active) 6676 { 6677 uint32_t phy_ctrl = 0; 6678 int32_t ret_val; 6679 uint16_t phy_data; 6680 DEBUGFUNC("em_set_d3_lplu_state"); 6681 6682 if (hw->phy_type != em_phy_igp && hw->phy_type != em_phy_igp_2 6683 && hw->phy_type != em_phy_igp_3) 6684 return E1000_SUCCESS; 6685 6686 /* During driver activity LPLU should not be used or it will attain link 6687 * from the lowest speeds starting from 10Mbps. The capability is used for 6688 * Dx transitions and states */ 6689 if (hw->mac_type == em_82541_rev_2 || hw->mac_type == em_82547_rev_2) { 6690 ret_val = em_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data); 6691 if (ret_val) 6692 return ret_val; 6693 } else if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) { 6694 /* MAC writes into PHY register based on the state transition 6695 * and start auto-negotiation. SW driver can overwrite the settings 6696 * in CSR PHY power control E1000_PHY_CTRL register. */ 6697 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); 6698 } else { 6699 ret_val = em_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); 6700 if (ret_val) 6701 return ret_val; 6702 } 6703 6704 if (!active) { 6705 if (hw->mac_type == em_82541_rev_2 || 6706 hw->mac_type == em_82547_rev_2) { 6707 phy_data &= ~IGP01E1000_GMII_FLEX_SPD; 6708 ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data); 6709 if (ret_val) 6710 return ret_val; 6711 } else { 6712 if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) { 6713 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; 6714 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 6715 } else { 6716 phy_data &= ~IGP02E1000_PM_D3_LPLU; 6717 ret_val = em_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, 6718 phy_data); 6719 if (ret_val) 6720 return ret_val; 6721 } 6722 } 6723 6724 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during 6725 * Dx states where the power conservation is most important. During 6726 * driver activity we should enable SmartSpeed, so performance is 6727 * maintained. */ 6728 if (hw->smart_speed == em_smart_speed_on) { 6729 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 6730 &phy_data); 6731 if (ret_val) 6732 return ret_val; 6733 6734 phy_data |= IGP01E1000_PSCFR_SMART_SPEED; 6735 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 6736 phy_data); 6737 if (ret_val) 6738 return ret_val; 6739 } else if (hw->smart_speed == em_smart_speed_off) { 6740 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 6741 &phy_data); 6742 if (ret_val) 6743 return ret_val; 6744 6745 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 6746 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 6747 phy_data); 6748 if (ret_val) 6749 return ret_val; 6750 } 6751 6752 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) || 6753 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) || 6754 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) { 6755 6756 if (hw->mac_type == em_82541_rev_2 || 6757 hw->mac_type == em_82547_rev_2) { 6758 phy_data |= IGP01E1000_GMII_FLEX_SPD; 6759 ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data); 6760 if (ret_val) 6761 return ret_val; 6762 } else { 6763 if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) { 6764 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; 6765 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 6766 } else { 6767 phy_data |= IGP02E1000_PM_D3_LPLU; 6768 ret_val = em_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, 6769 phy_data); 6770 if (ret_val) 6771 return ret_val; 6772 } 6773 } 6774 6775 /* When LPLU is enabled we should disable SmartSpeed */ 6776 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data); 6777 if (ret_val) 6778 return ret_val; 6779 6780 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 6781 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data); 6782 if (ret_val) 6783 return ret_val; 6784 6785 } 6786 return E1000_SUCCESS; 6787 } 6788 6789 /***************************************************************************** 6790 * 6791 * This function sets the lplu d0 state according to the active flag. When 6792 * activating lplu this function also disables smart speed and vise versa. 6793 * lplu will not be activated unless the device autonegotiation advertisement 6794 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. 6795 * hw: Struct containing variables accessed by shared code 6796 * active - true to enable lplu false to disable lplu. 6797 * 6798 * returns: - E1000_ERR_PHY if fail to read/write the PHY 6799 * E1000_SUCCESS at any other case. 6800 * 6801 ****************************************************************************/ 6802 6803 STATIC int32_t 6804 em_set_d0_lplu_state(struct em_hw *hw, 6805 boolean_t active) 6806 { 6807 uint32_t phy_ctrl = 0; 6808 int32_t ret_val; 6809 uint16_t phy_data; 6810 DEBUGFUNC("em_set_d0_lplu_state"); 6811 6812 if (hw->mac_type <= em_82547_rev_2) 6813 return E1000_SUCCESS; 6814 6815 if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) { 6816 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); 6817 } else { 6818 ret_val = em_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); 6819 if (ret_val) 6820 return ret_val; 6821 } 6822 6823 if (!active) { 6824 if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) { 6825 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; 6826 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 6827 } else { 6828 phy_data &= ~IGP02E1000_PM_D0_LPLU; 6829 ret_val = em_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data); 6830 if (ret_val) 6831 return ret_val; 6832 } 6833 6834 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during 6835 * Dx states where the power conservation is most important. During 6836 * driver activity we should enable SmartSpeed, so performance is 6837 * maintained. */ 6838 if (hw->smart_speed == em_smart_speed_on) { 6839 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 6840 &phy_data); 6841 if (ret_val) 6842 return ret_val; 6843 6844 phy_data |= IGP01E1000_PSCFR_SMART_SPEED; 6845 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 6846 phy_data); 6847 if (ret_val) 6848 return ret_val; 6849 } else if (hw->smart_speed == em_smart_speed_off) { 6850 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 6851 &phy_data); 6852 if (ret_val) 6853 return ret_val; 6854 6855 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 6856 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 6857 phy_data); 6858 if (ret_val) 6859 return ret_val; 6860 } 6861 6862 6863 } else { 6864 6865 if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) { 6866 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; 6867 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 6868 } else { 6869 phy_data |= IGP02E1000_PM_D0_LPLU; 6870 ret_val = em_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data); 6871 if (ret_val) 6872 return ret_val; 6873 } 6874 6875 /* When LPLU is enabled we should disable SmartSpeed */ 6876 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data); 6877 if (ret_val) 6878 return ret_val; 6879 6880 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 6881 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data); 6882 if (ret_val) 6883 return ret_val; 6884 6885 } 6886 return E1000_SUCCESS; 6887 } 6888 6889 /****************************************************************************** 6890 * Change VCO speed register to improve Bit Error Rate performance of SERDES. 6891 * 6892 * hw - Struct containing variables accessed by shared code 6893 *****************************************************************************/ 6894 static int32_t 6895 em_set_vco_speed(struct em_hw *hw) 6896 { 6897 int32_t ret_val; 6898 uint16_t default_page = 0; 6899 uint16_t phy_data; 6900 6901 DEBUGFUNC("em_set_vco_speed"); 6902 6903 switch (hw->mac_type) { 6904 case em_82545_rev_3: 6905 case em_82546_rev_3: 6906 break; 6907 default: 6908 return E1000_SUCCESS; 6909 } 6910 6911 /* Set PHY register 30, page 5, bit 8 to 0 */ 6912 6913 ret_val = em_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page); 6914 if (ret_val) 6915 return ret_val; 6916 6917 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005); 6918 if (ret_val) 6919 return ret_val; 6920 6921 ret_val = em_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); 6922 if (ret_val) 6923 return ret_val; 6924 6925 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8; 6926 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); 6927 if (ret_val) 6928 return ret_val; 6929 6930 /* Set PHY register 30, page 4, bit 11 to 1 */ 6931 6932 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004); 6933 if (ret_val) 6934 return ret_val; 6935 6936 ret_val = em_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); 6937 if (ret_val) 6938 return ret_val; 6939 6940 phy_data |= M88E1000_PHY_VCO_REG_BIT11; 6941 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); 6942 if (ret_val) 6943 return ret_val; 6944 6945 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page); 6946 if (ret_val) 6947 return ret_val; 6948 6949 return E1000_SUCCESS; 6950 } 6951 6952 6953 /***************************************************************************** 6954 * This function reads the cookie from ARC ram. 6955 * 6956 * returns: - E1000_SUCCESS . 6957 ****************************************************************************/ 6958 STATIC int32_t 6959 em_host_if_read_cookie(struct em_hw * hw, uint8_t *buffer) 6960 { 6961 uint8_t i; 6962 uint32_t offset = E1000_MNG_DHCP_COOKIE_OFFSET; 6963 uint8_t length = E1000_MNG_DHCP_COOKIE_LENGTH; 6964 6965 length = (length >> 2); 6966 offset = (offset >> 2); 6967 6968 for (i = 0; i < length; i++) { 6969 *((uint32_t *) buffer + i) = 6970 E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i); 6971 } 6972 return E1000_SUCCESS; 6973 } 6974 6975 6976 /***************************************************************************** 6977 * This function checks whether the HOST IF is enabled for command operaton 6978 * and also checks whether the previous command is completed. 6979 * It busy waits in case of previous command is not completed. 6980 * 6981 * returns: - E1000_ERR_HOST_INTERFACE_COMMAND in case if is not ready or 6982 * timeout 6983 * - E1000_SUCCESS for success. 6984 ****************************************************************************/ 6985 STATIC int32_t 6986 em_mng_enable_host_if(struct em_hw * hw) 6987 { 6988 uint32_t hicr; 6989 uint8_t i; 6990 6991 /* Check that the host interface is enabled. */ 6992 hicr = E1000_READ_REG(hw, HICR); 6993 if ((hicr & E1000_HICR_EN) == 0) { 6994 DEBUGOUT("E1000_HOST_EN bit disabled.\n"); 6995 return -E1000_ERR_HOST_INTERFACE_COMMAND; 6996 } 6997 /* check the previous command is completed */ 6998 for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) { 6999 hicr = E1000_READ_REG(hw, HICR); 7000 if (!(hicr & E1000_HICR_C)) 7001 break; 7002 msec_delay_irq(1); 7003 } 7004 7005 if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) { 7006 DEBUGOUT("Previous command timeout failed .\n"); 7007 return -E1000_ERR_HOST_INTERFACE_COMMAND; 7008 } 7009 return E1000_SUCCESS; 7010 } 7011 7012 /***************************************************************************** 7013 * This function checks the mode of the firmware. 7014 * 7015 * returns - TRUE when the mode is IAMT or FALSE. 7016 ****************************************************************************/ 7017 boolean_t 7018 em_check_mng_mode(struct em_hw *hw) 7019 { 7020 uint32_t fwsm; 7021 7022 fwsm = E1000_READ_REG(hw, FWSM); 7023 7024 if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) { 7025 if ((fwsm & E1000_FWSM_MODE_MASK) == 7026 (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) 7027 return TRUE; 7028 } else if ((fwsm & E1000_FWSM_MODE_MASK) == 7029 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) 7030 return TRUE; 7031 7032 return FALSE; 7033 } 7034 7035 /***************************************************************************** 7036 * This function calculates the checksum. 7037 * 7038 * returns - checksum of buffer contents. 7039 ****************************************************************************/ 7040 STATIC uint8_t 7041 em_calculate_mng_checksum(char *buffer, uint32_t length) 7042 { 7043 uint8_t sum = 0; 7044 uint32_t i; 7045 7046 if (!buffer) 7047 return 0; 7048 7049 for (i=0; i < length; i++) 7050 sum += buffer[i]; 7051 7052 return (uint8_t) (0 - sum); 7053 } 7054 7055 /***************************************************************************** 7056 * This function checks whether tx pkt filtering needs to be enabled or not. 7057 * 7058 * returns - TRUE for packet filtering or FALSE. 7059 ****************************************************************************/ 7060 boolean_t 7061 em_enable_tx_pkt_filtering(struct em_hw *hw) 7062 { 7063 /* called in init as well as watchdog timer functions */ 7064 7065 int32_t ret_val, checksum; 7066 boolean_t tx_filter = FALSE; 7067 struct em_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie); 7068 uint8_t *buffer = (uint8_t *) &(hw->mng_cookie); 7069 7070 if (em_check_mng_mode(hw)) { 7071 ret_val = em_mng_enable_host_if(hw); 7072 if (ret_val == E1000_SUCCESS) { 7073 ret_val = em_host_if_read_cookie(hw, buffer); 7074 if (ret_val == E1000_SUCCESS) { 7075 checksum = hdr->checksum; 7076 hdr->checksum = 0; 7077 if ((hdr->signature == E1000_IAMT_SIGNATURE) && 7078 checksum == em_calculate_mng_checksum((char *)buffer, 7079 E1000_MNG_DHCP_COOKIE_LENGTH)) { 7080 if (hdr->status & 7081 E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT) 7082 tx_filter = TRUE; 7083 } else 7084 tx_filter = TRUE; 7085 } else 7086 tx_filter = TRUE; 7087 } 7088 } 7089 7090 hw->tx_pkt_filtering = tx_filter; 7091 return tx_filter; 7092 } 7093 7094 7095 static int32_t 7096 em_polarity_reversal_workaround(struct em_hw *hw) 7097 { 7098 int32_t ret_val; 7099 uint16_t mii_status_reg; 7100 uint16_t i; 7101 7102 /* Polarity reversal workaround for forced 10F/10H links. */ 7103 7104 /* Disable the transmitter on the PHY */ 7105 7106 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 7107 if (ret_val) 7108 return ret_val; 7109 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF); 7110 if (ret_val) 7111 return ret_val; 7112 7113 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 7114 if (ret_val) 7115 return ret_val; 7116 7117 /* This loop will early-out if the NO link condition has been met. */ 7118 for (i = PHY_FORCE_TIME; i > 0; i--) { 7119 /* Read the MII Status Register and wait for Link Status bit 7120 * to be clear. 7121 */ 7122 7123 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 7124 if (ret_val) 7125 return ret_val; 7126 7127 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 7128 if (ret_val) 7129 return ret_val; 7130 7131 if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) break; 7132 msec_delay_irq(100); 7133 } 7134 7135 /* Recommended delay time after link has been lost */ 7136 msec_delay_irq(1000); 7137 7138 /* Now we will re-enable the transmitter on the PHY */ 7139 7140 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 7141 if (ret_val) 7142 return ret_val; 7143 msec_delay_irq(50); 7144 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0); 7145 if (ret_val) 7146 return ret_val; 7147 msec_delay_irq(50); 7148 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00); 7149 if (ret_val) 7150 return ret_val; 7151 msec_delay_irq(50); 7152 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000); 7153 if (ret_val) 7154 return ret_val; 7155 7156 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 7157 if (ret_val) 7158 return ret_val; 7159 7160 /* This loop will early-out if the link condition has been met. */ 7161 for (i = PHY_FORCE_TIME; i > 0; i--) { 7162 /* Read the MII Status Register and wait for Link Status bit 7163 * to be set. 7164 */ 7165 7166 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 7167 if (ret_val) 7168 return ret_val; 7169 7170 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 7171 if (ret_val) 7172 return ret_val; 7173 7174 if (mii_status_reg & MII_SR_LINK_STATUS) break; 7175 msec_delay_irq(100); 7176 } 7177 return E1000_SUCCESS; 7178 } 7179 7180 /*************************************************************************** 7181 * 7182 * Disables PCI-Express master access. 7183 * 7184 * hw: Struct containing variables accessed by shared code 7185 * 7186 * returns: - none. 7187 * 7188 ***************************************************************************/ 7189 STATIC void 7190 em_set_pci_express_master_disable(struct em_hw *hw) 7191 { 7192 uint32_t ctrl; 7193 7194 DEBUGFUNC("em_set_pci_express_master_disable"); 7195 7196 if (hw->bus_type != em_bus_type_pci_express) 7197 return; 7198 7199 ctrl = E1000_READ_REG(hw, CTRL); 7200 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; 7201 E1000_WRITE_REG(hw, CTRL, ctrl); 7202 } 7203 7204 /******************************************************************************* 7205 * 7206 * Disables PCI-Express master access and verifies there are no pending requests 7207 * 7208 * hw: Struct containing variables accessed by shared code 7209 * 7210 * returns: - E1000_ERR_MASTER_REQUESTS_PENDING if master disable bit hasn't 7211 * caused the master requests to be disabled. 7212 * E1000_SUCCESS master requests disabled. 7213 * 7214 ******************************************************************************/ 7215 int32_t 7216 em_disable_pciex_master(struct em_hw *hw) 7217 { 7218 int32_t timeout = MASTER_DISABLE_TIMEOUT; /* 80ms */ 7219 7220 DEBUGFUNC("em_disable_pciex_master"); 7221 7222 if (hw->bus_type != em_bus_type_pci_express) 7223 return E1000_SUCCESS; 7224 7225 em_set_pci_express_master_disable(hw); 7226 7227 while (timeout) { 7228 if (!(E1000_READ_REG(hw, STATUS) & E1000_STATUS_GIO_MASTER_ENABLE)) 7229 break; 7230 else 7231 usec_delay(100); 7232 timeout--; 7233 } 7234 7235 if (!timeout) { 7236 DEBUGOUT("Master requests are pending.\n"); 7237 return -E1000_ERR_MASTER_REQUESTS_PENDING; 7238 } 7239 7240 return E1000_SUCCESS; 7241 } 7242 7243 /******************************************************************************* 7244 * 7245 * Check for EEPROM Auto Read bit done. 7246 * 7247 * hw: Struct containing variables accessed by shared code 7248 * 7249 * returns: - E1000_ERR_RESET if fail to reset MAC 7250 * E1000_SUCCESS at any other case. 7251 * 7252 ******************************************************************************/ 7253 STATIC int32_t 7254 em_get_auto_rd_done(struct em_hw *hw) 7255 { 7256 int32_t timeout = AUTO_READ_DONE_TIMEOUT; 7257 7258 DEBUGFUNC("em_get_auto_rd_done"); 7259 7260 switch (hw->mac_type) { 7261 default: 7262 msec_delay(5); 7263 break; 7264 case em_82571: 7265 case em_82572: 7266 case em_82573: 7267 case em_80003es2lan: 7268 case em_ich8lan: 7269 case em_ich9lan: 7270 while (timeout) { 7271 if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD) 7272 break; 7273 else msec_delay(1); 7274 timeout--; 7275 } 7276 7277 if (!timeout) { 7278 DEBUGOUT("Auto read by HW from EEPROM has not completed.\n"); 7279 return -E1000_ERR_RESET; 7280 } 7281 break; 7282 } 7283 7284 /* PHY configuration from NVM just starts after EECD_AUTO_RD sets to high. 7285 * Need to wait for PHY configuration completion before accessing NVM 7286 * and PHY. */ 7287 if (hw->mac_type == em_82573) 7288 msec_delay(25); 7289 7290 return E1000_SUCCESS; 7291 } 7292 7293 /*************************************************************************** 7294 * Checks if the PHY configuration is done 7295 * 7296 * hw: Struct containing variables accessed by shared code 7297 * 7298 * returns: - E1000_ERR_RESET if fail to reset MAC 7299 * E1000_SUCCESS at any other case. 7300 * 7301 ***************************************************************************/ 7302 STATIC int32_t 7303 em_get_phy_cfg_done(struct em_hw *hw) 7304 { 7305 int32_t timeout = PHY_CFG_TIMEOUT; 7306 uint32_t cfg_mask = E1000_EEPROM_CFG_DONE; 7307 7308 DEBUGFUNC("em_get_phy_cfg_done"); 7309 7310 switch (hw->mac_type) { 7311 default: 7312 msec_delay_irq(10); 7313 break; 7314 case em_80003es2lan: 7315 /* Separate *_CFG_DONE_* bit for each port */ 7316 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) 7317 cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1; 7318 /* FALLTHROUGH */ 7319 case em_82571: 7320 case em_82572: 7321 while (timeout) { 7322 if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask) 7323 break; 7324 else 7325 msec_delay(1); 7326 timeout--; 7327 } 7328 if (!timeout) { 7329 DEBUGOUT("MNG configuration cycle has not completed.\n"); 7330 return -E1000_ERR_RESET; 7331 } 7332 break; 7333 } 7334 7335 return E1000_SUCCESS; 7336 } 7337 7338 /*************************************************************************** 7339 * 7340 * Using the combination of SMBI and SWESMBI semaphore bits when resetting 7341 * adapter or Eeprom access. 7342 * 7343 * hw: Struct containing variables accessed by shared code 7344 * 7345 * returns: - E1000_ERR_EEPROM if fail to access EEPROM. 7346 * E1000_SUCCESS at any other case. 7347 * 7348 ***************************************************************************/ 7349 STATIC int32_t 7350 em_get_hw_eeprom_semaphore(struct em_hw *hw) 7351 { 7352 int32_t timeout; 7353 uint32_t swsm; 7354 7355 DEBUGFUNC("em_get_hw_eeprom_semaphore"); 7356 7357 if (!hw->eeprom_semaphore_present) 7358 return E1000_SUCCESS; 7359 7360 if (hw->mac_type == em_80003es2lan) { 7361 /* Get the SW semaphore. */ 7362 if (em_get_software_semaphore(hw) != E1000_SUCCESS) 7363 return -E1000_ERR_EEPROM; 7364 } 7365 7366 /* Get the FW semaphore. */ 7367 timeout = hw->eeprom.word_size + 1; 7368 while (timeout) { 7369 swsm = E1000_READ_REG(hw, SWSM); 7370 swsm |= E1000_SWSM_SWESMBI; 7371 E1000_WRITE_REG(hw, SWSM, swsm); 7372 /* if we managed to set the bit we got the semaphore. */ 7373 swsm = E1000_READ_REG(hw, SWSM); 7374 if (swsm & E1000_SWSM_SWESMBI) 7375 break; 7376 7377 usec_delay(50); 7378 timeout--; 7379 } 7380 7381 if (!timeout) { 7382 /* Release semaphores */ 7383 em_put_hw_eeprom_semaphore(hw); 7384 DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set.\n"); 7385 return -E1000_ERR_EEPROM; 7386 } 7387 7388 return E1000_SUCCESS; 7389 } 7390 7391 /*************************************************************************** 7392 * This function clears HW semaphore bits. 7393 * 7394 * hw: Struct containing variables accessed by shared code 7395 * 7396 * returns: - None. 7397 * 7398 ***************************************************************************/ 7399 STATIC void 7400 em_put_hw_eeprom_semaphore(struct em_hw *hw) 7401 { 7402 uint32_t swsm; 7403 7404 DEBUGFUNC("em_put_hw_eeprom_semaphore"); 7405 7406 if (!hw->eeprom_semaphore_present) 7407 return; 7408 7409 swsm = E1000_READ_REG(hw, SWSM); 7410 if (hw->mac_type == em_80003es2lan) { 7411 /* Release both semaphores. */ 7412 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 7413 } else 7414 swsm &= ~(E1000_SWSM_SWESMBI); 7415 E1000_WRITE_REG(hw, SWSM, swsm); 7416 } 7417 7418 /*************************************************************************** 7419 * 7420 * Obtaining software semaphore bit (SMBI) before resetting PHY. 7421 * 7422 * hw: Struct containing variables accessed by shared code 7423 * 7424 * returns: - E1000_ERR_RESET if fail to obtain semaphore. 7425 * E1000_SUCCESS at any other case. 7426 * 7427 ***************************************************************************/ 7428 STATIC int32_t 7429 em_get_software_semaphore(struct em_hw *hw) 7430 { 7431 int32_t timeout = hw->eeprom.word_size + 1; 7432 uint32_t swsm; 7433 7434 DEBUGFUNC("em_get_software_semaphore"); 7435 7436 if (hw->mac_type != em_80003es2lan) 7437 return E1000_SUCCESS; 7438 7439 while (timeout) { 7440 swsm = E1000_READ_REG(hw, SWSM); 7441 /* If SMBI bit cleared, it is now set and we hold the semaphore */ 7442 if (!(swsm & E1000_SWSM_SMBI)) 7443 break; 7444 msec_delay_irq(1); 7445 timeout--; 7446 } 7447 7448 if (!timeout) { 7449 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 7450 return -E1000_ERR_RESET; 7451 } 7452 7453 return E1000_SUCCESS; 7454 } 7455 7456 /*************************************************************************** 7457 * 7458 * Release semaphore bit (SMBI). 7459 * 7460 * hw: Struct containing variables accessed by shared code 7461 * 7462 ***************************************************************************/ 7463 STATIC void 7464 em_release_software_semaphore(struct em_hw *hw) 7465 { 7466 uint32_t swsm; 7467 7468 DEBUGFUNC("em_release_software_semaphore"); 7469 7470 if (hw->mac_type != em_80003es2lan) 7471 return; 7472 7473 swsm = E1000_READ_REG(hw, SWSM); 7474 /* Release the SW semaphores.*/ 7475 swsm &= ~E1000_SWSM_SMBI; 7476 E1000_WRITE_REG(hw, SWSM, swsm); 7477 } 7478 7479 /****************************************************************************** 7480 * Checks if PHY reset is blocked due to SOL/IDER session, for example. 7481 * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to 7482 * the caller to figure out how to deal with it. 7483 * 7484 * hw - Struct containing variables accessed by shared code 7485 * 7486 * returns: - E1000_BLK_PHY_RESET 7487 * E1000_SUCCESS 7488 * 7489 *****************************************************************************/ 7490 int32_t 7491 em_check_phy_reset_block(struct em_hw *hw) 7492 { 7493 uint32_t manc = 0; 7494 uint32_t fwsm = 0; 7495 7496 if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) { 7497 fwsm = E1000_READ_REG(hw, FWSM); 7498 return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS 7499 : E1000_BLK_PHY_RESET; 7500 } 7501 7502 if (hw->mac_type > em_82547_rev_2) 7503 manc = E1000_READ_REG(hw, MANC); 7504 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? 7505 E1000_BLK_PHY_RESET : E1000_SUCCESS; 7506 } 7507 7508 /****************************************************************************** 7509 * Configure PCI-Ex no-snoop 7510 * 7511 * hw - Struct containing variables accessed by shared code. 7512 * no_snoop - Bitmap of no-snoop events. 7513 * 7514 * returns: E1000_SUCCESS 7515 * 7516 *****************************************************************************/ 7517 STATIC int32_t 7518 em_set_pci_ex_no_snoop(struct em_hw *hw, uint32_t no_snoop) 7519 { 7520 uint32_t gcr_reg = 0; 7521 7522 DEBUGFUNC("em_set_pci_ex_no_snoop"); 7523 7524 if (hw->bus_type == em_bus_type_unknown) 7525 em_get_bus_info(hw); 7526 7527 if (hw->bus_type != em_bus_type_pci_express) 7528 return E1000_SUCCESS; 7529 7530 if (no_snoop) { 7531 gcr_reg = E1000_READ_REG(hw, GCR); 7532 gcr_reg &= ~(PCI_EX_NO_SNOOP_ALL); 7533 gcr_reg |= no_snoop; 7534 E1000_WRITE_REG(hw, GCR, gcr_reg); 7535 } 7536 7537 if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) { 7538 uint32_t ctrl_ext; 7539 7540 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 7541 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 7542 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 7543 } 7544 7545 return E1000_SUCCESS; 7546 } 7547 7548 /*************************************************************************** 7549 * 7550 * Get software semaphore FLAG bit (SWFLAG). 7551 * SWFLAG is used to synchronize the access to all shared resource between 7552 * SW, FW and HW. 7553 * 7554 * hw: Struct containing variables accessed by shared code 7555 * 7556 ***************************************************************************/ 7557 STATIC int32_t 7558 em_get_software_flag(struct em_hw *hw) 7559 { 7560 int32_t timeout = PHY_CFG_TIMEOUT; 7561 uint32_t extcnf_ctrl; 7562 7563 DEBUGFUNC("em_get_software_flag"); 7564 7565 if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) { 7566 while (timeout) { 7567 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 7568 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; 7569 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); 7570 7571 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 7572 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) 7573 break; 7574 msec_delay_irq(1); 7575 timeout--; 7576 } 7577 7578 if (!timeout) { 7579 DEBUGOUT("FW or HW locks the resource too long.\n"); 7580 return -E1000_ERR_CONFIG; 7581 } 7582 } 7583 7584 return E1000_SUCCESS; 7585 } 7586 7587 /*************************************************************************** 7588 * 7589 * Release software semaphore FLAG bit (SWFLAG). 7590 * SWFLAG is used to synchronize the access to all shared resource between 7591 * SW, FW and HW. 7592 * 7593 * hw: Struct containing variables accessed by shared code 7594 * 7595 ***************************************************************************/ 7596 STATIC void 7597 em_release_software_flag(struct em_hw *hw) 7598 { 7599 uint32_t extcnf_ctrl; 7600 7601 DEBUGFUNC("em_release_software_flag"); 7602 7603 if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) { 7604 extcnf_ctrl= E1000_READ_REG(hw, EXTCNF_CTRL); 7605 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 7606 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); 7607 } 7608 7609 return; 7610 } 7611 7612 7613 /****************************************************************************** 7614 * Reads a 16 bit word or words from the EEPROM using the ICH8's flash access 7615 * register. 7616 * 7617 * hw - Struct containing variables accessed by shared code 7618 * offset - offset of word in the EEPROM to read 7619 * data - word read from the EEPROM 7620 * words - number of words to read 7621 *****************************************************************************/ 7622 STATIC int32_t 7623 em_read_eeprom_ich8(struct em_hw *hw, uint16_t offset, uint16_t words, 7624 uint16_t *data) 7625 { 7626 int32_t error = E1000_SUCCESS; 7627 uint32_t flash_bank = 0; 7628 uint32_t act_offset = 0; 7629 uint32_t bank_offset = 0; 7630 uint16_t word = 0; 7631 uint16_t i = 0; 7632 7633 /* We need to know which is the valid flash bank. In the event 7634 * that we didn't allocate eeprom_shadow_ram, we may not be 7635 * managing flash_bank. So it cannot be trusted and needs 7636 * to be updated with each read. 7637 */ 7638 /* Value of bit 22 corresponds to the flash bank we're on. */ 7639 flash_bank = (E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL) ? 1 : 0; 7640 7641 /* Adjust offset appropriately if we're on bank 1 - adjust for word size */ 7642 bank_offset = flash_bank * (hw->flash_bank_size * 2); 7643 7644 error = em_get_software_flag(hw); 7645 if (error != E1000_SUCCESS) 7646 return error; 7647 7648 for (i = 0; i < words; i++) { 7649 if (hw->eeprom_shadow_ram != NULL && 7650 hw->eeprom_shadow_ram[offset+i].modified == TRUE) { 7651 data[i] = hw->eeprom_shadow_ram[offset+i].eeprom_word; 7652 } else { 7653 /* The NVM part needs a byte offset, hence * 2 */ 7654 act_offset = bank_offset + ((offset + i) * 2); 7655 error = em_read_ich8_word(hw, act_offset, &word); 7656 if (error != E1000_SUCCESS) 7657 break; 7658 data[i] = word; 7659 } 7660 } 7661 7662 em_release_software_flag(hw); 7663 7664 return error; 7665 } 7666 7667 /****************************************************************************** 7668 * Writes a 16 bit word or words to the EEPROM using the ICH8's flash access 7669 * register. Actually, writes are written to the shadow ram cache in the hw 7670 * structure hw->em_shadow_ram. em_commit_shadow_ram flushes this to 7671 * the NVM, which occurs when the NVM checksum is updated. 7672 * 7673 * hw - Struct containing variables accessed by shared code 7674 * offset - offset of word in the EEPROM to write 7675 * words - number of words to write 7676 * data - words to write to the EEPROM 7677 *****************************************************************************/ 7678 STATIC int32_t 7679 em_write_eeprom_ich8(struct em_hw *hw, uint16_t offset, uint16_t words, 7680 uint16_t *data) 7681 { 7682 uint32_t i = 0; 7683 int32_t error = E1000_SUCCESS; 7684 7685 error = em_get_software_flag(hw); 7686 if (error != E1000_SUCCESS) 7687 return error; 7688 7689 /* A driver can write to the NVM only if it has eeprom_shadow_ram 7690 * allocated. Subsequent reads to the modified words are read from 7691 * this cached structure as well. Writes will only go into this 7692 * cached structure unless it's followed by a call to 7693 * em_update_eeprom_checksum() where it will commit the changes 7694 * and clear the "modified" field. 7695 */ 7696 if (hw->eeprom_shadow_ram != NULL) { 7697 for (i = 0; i < words; i++) { 7698 if ((offset + i) < E1000_SHADOW_RAM_WORDS) { 7699 hw->eeprom_shadow_ram[offset+i].modified = TRUE; 7700 hw->eeprom_shadow_ram[offset+i].eeprom_word = data[i]; 7701 } else { 7702 error = -E1000_ERR_EEPROM; 7703 break; 7704 } 7705 } 7706 } else { 7707 /* Drivers have the option to not allocate eeprom_shadow_ram as long 7708 * as they don't perform any NVM writes. An attempt in doing so 7709 * will result in this error. 7710 */ 7711 error = -E1000_ERR_EEPROM; 7712 } 7713 7714 em_release_software_flag(hw); 7715 7716 return error; 7717 } 7718 7719 /****************************************************************************** 7720 * This function does initial flash setup so that a new read/write/erase cycle 7721 * can be started. 7722 * 7723 * hw - The pointer to the hw structure 7724 ****************************************************************************/ 7725 STATIC int32_t 7726 em_ich8_cycle_init(struct em_hw *hw) 7727 { 7728 union ich8_hws_flash_status hsfsts; 7729 int32_t error = E1000_ERR_EEPROM; 7730 int32_t i = 0; 7731 7732 DEBUGFUNC("em_ich8_cycle_init"); 7733 7734 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 7735 7736 /* May be check the Flash Des Valid bit in Hw status */ 7737 if (hsfsts.hsf_status.fldesvalid == 0) { 7738 DEBUGOUT("Flash descriptor invalid. SW Sequencing must be used."); 7739 return error; 7740 } 7741 7742 /* Clear FCERR in Hw status by writing 1 */ 7743 /* Clear DAEL in Hw status by writing a 1 */ 7744 hsfsts.hsf_status.flcerr = 1; 7745 hsfsts.hsf_status.dael = 1; 7746 7747 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval); 7748 7749 /* Either we should have a hardware SPI cycle in progress bit to check 7750 * against, in order to start a new cycle or FDONE bit should be changed 7751 * in the hardware so that it is 1 after harware reset, which can then be 7752 * used as an indication whether a cycle is in progress or has been 7753 * completed .. we should also have some software semaphore mechanism to 7754 * guard FDONE or the cycle in progress bit so that two threads access to 7755 * those bits can be sequentiallized or a way so that 2 threads dont 7756 * start the cycle at the same time */ 7757 7758 if (hsfsts.hsf_status.flcinprog == 0) { 7759 /* There is no cycle running at present, so we can start a cycle */ 7760 /* Begin by setting Flash Cycle Done. */ 7761 hsfsts.hsf_status.flcdone = 1; 7762 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval); 7763 error = E1000_SUCCESS; 7764 } else { 7765 /* otherwise poll for sometime so the current cycle has a chance 7766 * to end before giving up. */ 7767 for (i = 0; i < ICH_FLASH_COMMAND_TIMEOUT; i++) { 7768 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 7769 if (hsfsts.hsf_status.flcinprog == 0) { 7770 error = E1000_SUCCESS; 7771 break; 7772 } 7773 usec_delay(1); 7774 } 7775 if (error == E1000_SUCCESS) { 7776 /* Successful in waiting for previous cycle to timeout, 7777 * now set the Flash Cycle Done. */ 7778 hsfsts.hsf_status.flcdone = 1; 7779 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval); 7780 } else { 7781 DEBUGOUT("Flash controller busy, cannot get access"); 7782 } 7783 } 7784 return error; 7785 } 7786 7787 /****************************************************************************** 7788 * This function starts a flash cycle and waits for its completion 7789 * 7790 * hw - The pointer to the hw structure 7791 ****************************************************************************/ 7792 STATIC int32_t 7793 em_ich8_flash_cycle(struct em_hw *hw, uint32_t timeout) 7794 { 7795 union ich8_hws_flash_ctrl hsflctl; 7796 union ich8_hws_flash_status hsfsts; 7797 int32_t error = E1000_ERR_EEPROM; 7798 uint32_t i = 0; 7799 7800 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ 7801 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL); 7802 hsflctl.hsf_ctrl.flcgo = 1; 7803 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); 7804 7805 /* wait till FDONE bit is set to 1 */ 7806 do { 7807 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 7808 if (hsfsts.hsf_status.flcdone == 1) 7809 break; 7810 usec_delay(1); 7811 i++; 7812 } while (i < timeout); 7813 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) { 7814 error = E1000_SUCCESS; 7815 } 7816 return error; 7817 } 7818 7819 /****************************************************************************** 7820 * Reads a byte or word from the NVM using the ICH8 flash access registers. 7821 * 7822 * hw - The pointer to the hw structure 7823 * index - The index of the byte or word to read. 7824 * size - Size of data to read, 1=byte 2=word 7825 * data - Pointer to the word to store the value read. 7826 *****************************************************************************/ 7827 STATIC int32_t 7828 em_read_ich8_data(struct em_hw *hw, uint32_t index, 7829 uint32_t size, uint16_t* data) 7830 { 7831 union ich8_hws_flash_status hsfsts; 7832 union ich8_hws_flash_ctrl hsflctl; 7833 uint32_t flash_linear_address; 7834 uint32_t flash_data = 0; 7835 int32_t error = -E1000_ERR_EEPROM; 7836 int32_t count = 0; 7837 7838 DEBUGFUNC("em_read_ich8_data"); 7839 7840 if (size < 1 || size > 2 || data == 0x0 || 7841 index > ICH_FLASH_LINEAR_ADDR_MASK) 7842 return error; 7843 7844 flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) + 7845 hw->flash_base_addr; 7846 7847 do { 7848 usec_delay(1); 7849 /* Steps */ 7850 error = em_ich8_cycle_init(hw); 7851 if (error != E1000_SUCCESS) 7852 break; 7853 7854 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL); 7855 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 7856 hsflctl.hsf_ctrl.fldbcount = size - 1; 7857 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; 7858 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); 7859 7860 /* Write the last 24 bits of index into Flash Linear address field in 7861 * Flash Address */ 7862 /* TODO: TBD maybe check the index against the size of flash */ 7863 7864 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address); 7865 7866 error = em_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT); 7867 7868 /* Check if FCERR is set to 1, if set to 1, clear it and try the whole 7869 * sequence a few more times, else read in (shift in) the Flash Data0, 7870 * the order is least significant byte first msb to lsb */ 7871 if (error == E1000_SUCCESS) { 7872 flash_data = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0); 7873 if (size == 1) { 7874 *data = (uint8_t)(flash_data & 0x000000FF); 7875 } else if (size == 2) { 7876 *data = (uint16_t)(flash_data & 0x0000FFFF); 7877 } 7878 break; 7879 } else { 7880 /* If we've gotten here, then things are probably completely hosed, 7881 * but if the error condition is detected, it won't hurt to give 7882 * it another try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 7883 */ 7884 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 7885 if (hsfsts.hsf_status.flcerr == 1) { 7886 /* Repeat for some time before giving up. */ 7887 continue; 7888 } else if (hsfsts.hsf_status.flcdone == 0) { 7889 DEBUGOUT("Timeout error - flash cycle did not complete."); 7890 break; 7891 } 7892 } 7893 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 7894 7895 return error; 7896 } 7897 7898 /****************************************************************************** 7899 * Writes One /two bytes to the NVM using the ICH8 flash access registers. 7900 * 7901 * hw - The pointer to the hw structure 7902 * index - The index of the byte/word to read. 7903 * size - Size of data to read, 1=byte 2=word 7904 * data - The byte(s) to write to the NVM. 7905 *****************************************************************************/ 7906 STATIC int32_t 7907 em_write_ich8_data(struct em_hw *hw, uint32_t index, uint32_t size, 7908 uint16_t data) 7909 { 7910 union ich8_hws_flash_status hsfsts; 7911 union ich8_hws_flash_ctrl hsflctl; 7912 uint32_t flash_linear_address; 7913 uint32_t flash_data = 0; 7914 int32_t error = -E1000_ERR_EEPROM; 7915 int32_t count = 0; 7916 7917 DEBUGFUNC("em_write_ich8_data"); 7918 7919 if (size < 1 || size > 2 || data > size * 0xff || 7920 index > ICH_FLASH_LINEAR_ADDR_MASK) 7921 return error; 7922 7923 flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) + 7924 hw->flash_base_addr; 7925 7926 do { 7927 usec_delay(1); 7928 /* Steps */ 7929 error = em_ich8_cycle_init(hw); 7930 if (error != E1000_SUCCESS) 7931 break; 7932 7933 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL); 7934 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 7935 hsflctl.hsf_ctrl.fldbcount = size -1; 7936 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; 7937 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); 7938 7939 /* Write the last 24 bits of index into Flash Linear address field in 7940 * Flash Address */ 7941 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address); 7942 7943 if (size == 1) 7944 flash_data = (uint32_t)data & 0x00FF; 7945 else 7946 flash_data = (uint32_t)data; 7947 7948 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data); 7949 7950 /* check if FCERR is set to 1 , if set to 1, clear it and try the whole 7951 * sequence a few more times else done */ 7952 error = em_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT); 7953 if (error == E1000_SUCCESS) { 7954 break; 7955 } else { 7956 /* If we're here, then things are most likely completely hosed, 7957 * but if the error condition is detected, it won't hurt to give 7958 * it another try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 7959 */ 7960 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 7961 if (hsfsts.hsf_status.flcerr == 1) { 7962 /* Repeat for some time before giving up. */ 7963 continue; 7964 } else if (hsfsts.hsf_status.flcdone == 0) { 7965 DEBUGOUT("Timeout error - flash cycle did not complete."); 7966 break; 7967 } 7968 } 7969 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 7970 7971 return error; 7972 } 7973 7974 /****************************************************************************** 7975 * Reads a single byte from the NVM using the ICH8 flash access registers. 7976 * 7977 * hw - pointer to em_hw structure 7978 * index - The index of the byte to read. 7979 * data - Pointer to a byte to store the value read. 7980 *****************************************************************************/ 7981 STATIC int32_t 7982 em_read_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t* data) 7983 { 7984 int32_t status = E1000_SUCCESS; 7985 uint16_t word = 0; 7986 7987 status = em_read_ich8_data(hw, index, 1, &word); 7988 if (status == E1000_SUCCESS) { 7989 *data = (uint8_t)word; 7990 } 7991 7992 return status; 7993 } 7994 7995 /****************************************************************************** 7996 * Writes a single byte to the NVM using the ICH8 flash access registers. 7997 * Performs verification by reading back the value and then going through 7998 * a retry algorithm before giving up. 7999 * 8000 * hw - pointer to em_hw structure 8001 * index - The index of the byte to write. 8002 * byte - The byte to write to the NVM. 8003 *****************************************************************************/ 8004 STATIC int32_t 8005 em_verify_write_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t byte) 8006 { 8007 int32_t error = E1000_SUCCESS; 8008 int32_t program_retries = 0; 8009 8010 DEBUGOUT2("Byte := %2.2X Offset := %d\n", byte, index); 8011 8012 error = em_write_ich8_byte(hw, index, byte); 8013 8014 if (error != E1000_SUCCESS) { 8015 for (program_retries = 0; program_retries < 100; program_retries++) { 8016 DEBUGOUT2("Retrying \t Byte := %2.2X Offset := %d\n", byte, index); 8017 error = em_write_ich8_byte(hw, index, byte); 8018 usec_delay(100); 8019 if (error == E1000_SUCCESS) 8020 break; 8021 } 8022 } 8023 8024 if (program_retries == 100) 8025 error = E1000_ERR_EEPROM; 8026 8027 return error; 8028 } 8029 8030 /****************************************************************************** 8031 * Writes a single byte to the NVM using the ICH8 flash access registers. 8032 * 8033 * hw - pointer to em_hw structure 8034 * index - The index of the byte to read. 8035 * data - The byte to write to the NVM. 8036 *****************************************************************************/ 8037 STATIC int32_t 8038 em_write_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t data) 8039 { 8040 int32_t status = E1000_SUCCESS; 8041 uint16_t word = (uint16_t)data; 8042 8043 status = em_write_ich8_data(hw, index, 1, word); 8044 8045 return status; 8046 } 8047 8048 /****************************************************************************** 8049 * Reads a word from the NVM using the ICH8 flash access registers. 8050 * 8051 * hw - pointer to em_hw structure 8052 * index - The starting byte index of the word to read. 8053 * data - Pointer to a word to store the value read. 8054 *****************************************************************************/ 8055 STATIC int32_t 8056 em_read_ich8_word(struct em_hw *hw, uint32_t index, uint16_t *data) 8057 { 8058 int32_t status = E1000_SUCCESS; 8059 status = em_read_ich8_data(hw, index, 2, data); 8060 return status; 8061 } 8062 8063 8064 /****************************************************************************** 8065 * Erases the bank specified. Each bank may be a 4, 8 or 64k block. Banks are 0 8066 * based. 8067 * 8068 * hw - pointer to em_hw structure 8069 * bank - 0 for first bank, 1 for second bank 8070 * 8071 * Note that this function may actually erase as much as 8 or 64 KBytes. The 8072 * amount of NVM used in each bank is a *minimum* of 4 KBytes, but in fact the 8073 * bank size may be 4, 8 or 64 KBytes 8074 *****************************************************************************/ 8075 int32_t 8076 em_erase_ich8_4k_segment(struct em_hw *hw, uint32_t bank) 8077 { 8078 union ich8_hws_flash_status hsfsts; 8079 union ich8_hws_flash_ctrl hsflctl; 8080 uint32_t flash_linear_address; 8081 int32_t count = 0; 8082 int32_t error = E1000_ERR_EEPROM; 8083 int32_t iteration; 8084 int32_t sub_sector_size = 0; 8085 int32_t bank_size; 8086 int32_t j = 0; 8087 int32_t error_flag = 0; 8088 8089 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 8090 8091 /* Determine HW Sector size: Read BERASE bits of Hw flash Status register */ 8092 /* 00: The Hw sector is 256 bytes, hence we need to erase 16 8093 * consecutive sectors. The start index for the nth Hw sector can be 8094 * calculated as bank * 4096 + n * 256 8095 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector. 8096 * The start index for the nth Hw sector can be calculated 8097 * as bank * 4096 8098 * 10: The HW sector is 8K bytes 8099 * 11: The Hw sector size is 64K bytes */ 8100 if (hsfsts.hsf_status.berasesz == 0x0) { 8101 /* Hw sector size 256 */ 8102 sub_sector_size = ICH_FLASH_SEG_SIZE_256; 8103 bank_size = ICH_FLASH_SECTOR_SIZE; 8104 iteration = ICH_FLASH_SECTOR_SIZE / ICH_FLASH_SEG_SIZE_256; 8105 } else if (hsfsts.hsf_status.berasesz == 0x1) { 8106 bank_size = ICH_FLASH_SEG_SIZE_4K; 8107 iteration = 1; 8108 } else if (hsfsts.hsf_status.berasesz == 0x2) { 8109 if (hw->mac_type == em_ich9lan) { 8110 uint32_t gfpreg, sector_base_addr, sector_end_addr; 8111 8112 gfpreg = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_GFPREG); 8113 8114 /* 8115 * sector_X_addr is a "sector"-aligned address (4096 bytes) 8116 * Add 1 to sector_end_addr since this sector is included in 8117 * the overall size. 8118 */ 8119 sector_base_addr = gfpreg & ICH_GFPREG_BASE_MASK; 8120 sector_end_addr = ((gfpreg >> 16) & ICH_GFPREG_BASE_MASK) + 1; 8121 8122 /* 8123 * find total size of the NVM, then cut in half since the total 8124 * size represents two separate NVM banks. 8125 */ 8126 bank_size = (sector_end_addr - sector_base_addr) 8127 << ICH_FLASH_SECT_ADDR_SHIFT; 8128 bank_size /= 2; 8129 /* Word align */ 8130 bank_size = (bank_size / sizeof(uint16_t)) * sizeof(uint16_t); 8131 8132 sub_sector_size = ICH_FLASH_SEG_SIZE_8K; 8133 iteration = bank_size / ICH_FLASH_SEG_SIZE_8K; 8134 } else { 8135 return error; 8136 } 8137 } else if (hsfsts.hsf_status.berasesz == 0x3) { 8138 bank_size = ICH_FLASH_SEG_SIZE_64K; 8139 iteration = 1; 8140 } else { 8141 return error; 8142 } 8143 8144 for (j = 0; j < iteration ; j++) { 8145 do { 8146 count++; 8147 /* Steps */ 8148 error = em_ich8_cycle_init(hw); 8149 if (error != E1000_SUCCESS) { 8150 error_flag = 1; 8151 break; 8152 } 8153 8154 /* Write a value 11 (block Erase) in Flash Cycle field in Hw flash 8155 * Control */ 8156 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL); 8157 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE; 8158 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); 8159 8160 /* Write the last 24 bits of an index within the block into Flash 8161 * Linear address field in Flash Address. This probably needs to 8162 * be calculated here based off the on-chip erase sector size and 8163 * the software bank size (4, 8 or 64 KBytes) */ 8164 flash_linear_address = bank * bank_size + j * sub_sector_size; 8165 flash_linear_address += hw->flash_base_addr; 8166 flash_linear_address &= ICH_FLASH_LINEAR_ADDR_MASK; 8167 8168 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address); 8169 8170 error = em_ich8_flash_cycle(hw, ICH_FLASH_ERASE_TIMEOUT); 8171 /* Check if FCERR is set to 1. If 1, clear it and try the whole 8172 * sequence a few more times else Done */ 8173 if (error == E1000_SUCCESS) { 8174 break; 8175 } else { 8176 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 8177 if (hsfsts.hsf_status.flcerr == 1) { 8178 /* repeat for some time before giving up */ 8179 continue; 8180 } else if (hsfsts.hsf_status.flcdone == 0) { 8181 error_flag = 1; 8182 break; 8183 } 8184 } 8185 } while ((count < ICH_FLASH_CYCLE_REPEAT_COUNT) && !error_flag); 8186 if (error_flag == 1) 8187 break; 8188 } 8189 if (error_flag != 1) 8190 error = E1000_SUCCESS; 8191 return error; 8192 } 8193 8194 8195 STATIC int32_t 8196 em_init_lcd_from_nvm_config_region(struct em_hw *hw, 8197 uint32_t cnf_base_addr, uint32_t cnf_size) 8198 { 8199 uint32_t ret_val = E1000_SUCCESS; 8200 uint16_t word_addr, reg_data, reg_addr; 8201 uint16_t i; 8202 8203 /* cnf_base_addr is in DWORD */ 8204 word_addr = (uint16_t)(cnf_base_addr << 1); 8205 8206 /* cnf_size is returned in size of dwords */ 8207 for (i = 0; i < cnf_size; i++) { 8208 ret_val = em_read_eeprom(hw, (word_addr + i*2), 1, ®_data); 8209 if (ret_val) 8210 return ret_val; 8211 8212 ret_val = em_read_eeprom(hw, (word_addr + i*2 + 1), 1, ®_addr); 8213 if (ret_val) 8214 return ret_val; 8215 8216 ret_val = em_get_software_flag(hw); 8217 if (ret_val != E1000_SUCCESS) 8218 return ret_val; 8219 8220 ret_val = em_write_phy_reg_ex(hw, (uint32_t)reg_addr, reg_data); 8221 8222 em_release_software_flag(hw); 8223 } 8224 8225 return ret_val; 8226 } 8227 8228 /****************************************************************************** 8229 * This function initializes the PHY from the NVM on ICH8 platforms. This 8230 * is needed due to an issue where the NVM configuration is not properly 8231 * autoloaded after power transitions. Therefore, after each PHY reset, we 8232 * will load the configuration data out of the NVM manually. 8233 * 8234 * hw: Struct containing variables accessed by shared code 8235 *****************************************************************************/ 8236 STATIC int32_t 8237 em_init_lcd_from_nvm(struct em_hw *hw) 8238 { 8239 uint32_t reg_data, cnf_base_addr, cnf_size, ret_val, loop, sw_cfg_mask; 8240 8241 if (hw->phy_type != em_phy_igp_3) 8242 return E1000_SUCCESS; 8243 8244 /* Check if SW needs configure the PHY */ 8245 if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_M_AMT) || 8246 (hw->device_id == E1000_DEV_ID_ICH8_IGP_M)) 8247 sw_cfg_mask = FEXTNVM_SW_CONFIG_ICH8M; 8248 else 8249 sw_cfg_mask = FEXTNVM_SW_CONFIG; 8250 8251 reg_data = E1000_READ_REG(hw, FEXTNVM); 8252 if (!(reg_data & sw_cfg_mask)) 8253 return E1000_SUCCESS; 8254 8255 /* Wait for basic configuration completes before proceeding*/ 8256 loop = 0; 8257 do { 8258 reg_data = E1000_READ_REG(hw, STATUS) & E1000_STATUS_LAN_INIT_DONE; 8259 usec_delay(100); 8260 loop++; 8261 } while ((!reg_data) && (loop < 50)); 8262 8263 /* Clear the Init Done bit for the next init event */ 8264 reg_data = E1000_READ_REG(hw, STATUS); 8265 reg_data &= ~E1000_STATUS_LAN_INIT_DONE; 8266 E1000_WRITE_REG(hw, STATUS, reg_data); 8267 8268 /* Make sure HW does not configure LCD from PHY extended configuration 8269 before SW configuration */ 8270 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL); 8271 if ((reg_data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) == 0x0000) { 8272 reg_data = E1000_READ_REG(hw, EXTCNF_SIZE); 8273 cnf_size = reg_data & E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH; 8274 cnf_size >>= 16; 8275 if (cnf_size) { 8276 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL); 8277 cnf_base_addr = reg_data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER; 8278 /* cnf_base_addr is in DWORD */ 8279 cnf_base_addr >>= 16; 8280 8281 /* Configure LCD from extended configuration region. */ 8282 ret_val = em_init_lcd_from_nvm_config_region(hw, cnf_base_addr, 8283 cnf_size); 8284 if (ret_val) 8285 return ret_val; 8286 } 8287 } 8288 8289 return E1000_SUCCESS; 8290 } 8291