1 /******************************************************************************* 2 3 Copyright (c) 2001-2005, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 *******************************************************************************/ 33 34 /* $OpenBSD: if_em_hw.c,v 1.106 2020/02/04 10:59:23 mpi Exp $ */ 35 /* 36 * if_em_hw.c Shared functions for accessing and configuring the MAC 37 */ 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/sockio.h> 42 #include <sys/mbuf.h> 43 #include <sys/malloc.h> 44 #include <sys/kernel.h> 45 #include <sys/device.h> 46 #include <sys/socket.h> 47 48 #include <net/if.h> 49 #include <net/if_media.h> 50 51 #include <netinet/in.h> 52 #include <netinet/if_ether.h> 53 54 #include <uvm/uvm_extern.h> 55 56 #include <dev/pci/pcireg.h> 57 #include <dev/pci/pcivar.h> 58 59 #include <dev/pci/if_em_hw.h> 60 #include <dev/pci/if_em_soc.h> 61 62 #include <dev/mii/rgephyreg.h> 63 64 #define STATIC 65 66 static int32_t em_swfw_sync_acquire(struct em_hw *, uint16_t); 67 static void em_swfw_sync_release(struct em_hw *, uint16_t); 68 static int32_t em_read_kmrn_reg(struct em_hw *, uint32_t, uint16_t *); 69 static int32_t em_write_kmrn_reg(struct em_hw *hw, uint32_t, uint16_t); 70 static int32_t em_get_software_semaphore(struct em_hw *); 71 static void em_release_software_semaphore(struct em_hw *); 72 73 static int32_t em_check_downshift(struct em_hw *); 74 static void em_clear_vfta(struct em_hw *); 75 void em_clear_vfta_i350(struct em_hw *); 76 static int32_t em_commit_shadow_ram(struct em_hw *); 77 static int32_t em_config_dsp_after_link_change(struct em_hw *, boolean_t); 78 static int32_t em_config_fc_after_link_up(struct em_hw *); 79 static int32_t em_match_gig_phy(struct em_hw *); 80 static int32_t em_detect_gig_phy(struct em_hw *); 81 static int32_t em_erase_ich8_4k_segment(struct em_hw *, uint32_t); 82 static int32_t em_get_auto_rd_done(struct em_hw *); 83 static int32_t em_get_cable_length(struct em_hw *, uint16_t *, uint16_t *); 84 static int32_t em_get_hw_eeprom_semaphore(struct em_hw *); 85 static int32_t em_get_phy_cfg_done(struct em_hw *); 86 static int32_t em_get_software_flag(struct em_hw *); 87 static int32_t em_ich8_cycle_init(struct em_hw *); 88 static int32_t em_ich8_flash_cycle(struct em_hw *, uint32_t); 89 static int32_t em_id_led_init(struct em_hw *); 90 static int32_t em_init_lcd_from_nvm_config_region(struct em_hw *, uint32_t, 91 uint32_t); 92 static int32_t em_init_lcd_from_nvm(struct em_hw *); 93 static int32_t em_phy_no_cable_workaround(struct em_hw *); 94 static void em_init_rx_addrs(struct em_hw *); 95 static void em_initialize_hardware_bits(struct em_hw *); 96 static void em_toggle_lanphypc_pch_lpt(struct em_hw *); 97 static int em_disable_ulp_lpt_lp(struct em_hw *hw, bool force); 98 static boolean_t em_is_onboard_nvm_eeprom(struct em_hw *); 99 static int32_t em_kumeran_lock_loss_workaround(struct em_hw *); 100 static int32_t em_mng_enable_host_if(struct em_hw *); 101 static int32_t em_read_eeprom_eerd(struct em_hw *, uint16_t, uint16_t, 102 uint16_t *); 103 static int32_t em_write_eeprom_eewr(struct em_hw *, uint16_t, uint16_t, 104 uint16_t *data); 105 static int32_t em_poll_eerd_eewr_done(struct em_hw *, int); 106 static void em_put_hw_eeprom_semaphore(struct em_hw *); 107 static int32_t em_read_ich8_byte(struct em_hw *, uint32_t, uint8_t *); 108 static int32_t em_verify_write_ich8_byte(struct em_hw *, uint32_t, uint8_t); 109 static int32_t em_write_ich8_byte(struct em_hw *, uint32_t, uint8_t); 110 static int32_t em_read_ich8_word(struct em_hw *, uint32_t, uint16_t *); 111 static int32_t em_read_ich8_dword(struct em_hw *, uint32_t, uint32_t *); 112 static int32_t em_read_ich8_data(struct em_hw *, uint32_t, uint32_t, 113 uint16_t *); 114 static int32_t em_write_ich8_data(struct em_hw *, uint32_t, uint32_t, 115 uint16_t); 116 static int32_t em_read_eeprom_ich8(struct em_hw *, uint16_t, uint16_t, 117 uint16_t *); 118 static int32_t em_write_eeprom_ich8(struct em_hw *, uint16_t, uint16_t, 119 uint16_t *); 120 static int32_t em_read_invm_i210(struct em_hw *, uint16_t, uint16_t, 121 uint16_t *); 122 static int32_t em_read_invm_word_i210(struct em_hw *, uint16_t, uint16_t *); 123 static void em_release_software_flag(struct em_hw *); 124 static int32_t em_set_d3_lplu_state(struct em_hw *, boolean_t); 125 static int32_t em_set_d0_lplu_state(struct em_hw *, boolean_t); 126 static int32_t em_set_lplu_state_pchlan(struct em_hw *, boolean_t); 127 static int32_t em_set_pci_ex_no_snoop(struct em_hw *, uint32_t); 128 static void em_set_pci_express_master_disable(struct em_hw *); 129 static int32_t em_wait_autoneg(struct em_hw *); 130 static void em_write_reg_io(struct em_hw *, uint32_t, uint32_t); 131 static int32_t em_set_phy_type(struct em_hw *); 132 static void em_phy_init_script(struct em_hw *); 133 static int32_t em_setup_copper_link(struct em_hw *); 134 static int32_t em_setup_fiber_serdes_link(struct em_hw *); 135 static int32_t em_adjust_serdes_amplitude(struct em_hw *); 136 static int32_t em_phy_force_speed_duplex(struct em_hw *); 137 static int32_t em_config_mac_to_phy(struct em_hw *); 138 static void em_raise_mdi_clk(struct em_hw *, uint32_t *); 139 static void em_lower_mdi_clk(struct em_hw *, uint32_t *); 140 static void em_shift_out_mdi_bits(struct em_hw *, uint32_t, uint16_t); 141 static uint16_t em_shift_in_mdi_bits(struct em_hw *); 142 static int32_t em_phy_reset_dsp(struct em_hw *); 143 static int32_t em_write_eeprom_spi(struct em_hw *, uint16_t, uint16_t, 144 uint16_t *); 145 static int32_t em_write_eeprom_microwire(struct em_hw *, uint16_t, uint16_t, 146 uint16_t *); 147 static int32_t em_spi_eeprom_ready(struct em_hw *); 148 static void em_raise_ee_clk(struct em_hw *, uint32_t *); 149 static void em_lower_ee_clk(struct em_hw *, uint32_t *); 150 static void em_shift_out_ee_bits(struct em_hw *, uint16_t, uint16_t); 151 static int32_t em_write_phy_reg_ex(struct em_hw *, uint32_t, uint16_t); 152 static int32_t em_read_phy_reg_ex(struct em_hw *, uint32_t, uint16_t *); 153 static uint16_t em_shift_in_ee_bits(struct em_hw *, uint16_t); 154 static int32_t em_acquire_eeprom(struct em_hw *); 155 static void em_release_eeprom(struct em_hw *); 156 static void em_standby_eeprom(struct em_hw *); 157 static int32_t em_set_vco_speed(struct em_hw *); 158 static int32_t em_polarity_reversal_workaround(struct em_hw *); 159 static int32_t em_set_phy_mode(struct em_hw *); 160 static int32_t em_host_if_read_cookie(struct em_hw *, uint8_t *); 161 static uint8_t em_calculate_mng_checksum(char *, uint32_t); 162 static int32_t em_configure_kmrn_for_10_100(struct em_hw *, uint16_t); 163 static int32_t em_configure_kmrn_for_1000(struct em_hw *); 164 static int32_t em_set_pciex_completion_timeout(struct em_hw *hw); 165 static int32_t em_set_mdio_slow_mode_hv(struct em_hw *); 166 int32_t em_hv_phy_workarounds_ich8lan(struct em_hw *); 167 int32_t em_lv_phy_workarounds_ich8lan(struct em_hw *); 168 int32_t em_link_stall_workaround_hv(struct em_hw *); 169 int32_t em_k1_gig_workaround_hv(struct em_hw *, boolean_t); 170 int32_t em_k1_workaround_lv(struct em_hw *); 171 int32_t em_k1_workaround_lpt_lp(struct em_hw *, boolean_t); 172 int32_t em_configure_k1_ich8lan(struct em_hw *, boolean_t); 173 void em_gate_hw_phy_config_ich8lan(struct em_hw *, boolean_t); 174 int32_t em_access_phy_wakeup_reg_bm(struct em_hw *, uint32_t, 175 uint16_t *, boolean_t); 176 int32_t em_access_phy_debug_regs_hv(struct em_hw *, uint32_t, 177 uint16_t *, boolean_t); 178 int32_t em_access_phy_reg_hv(struct em_hw *, uint32_t, uint16_t *, 179 boolean_t); 180 int32_t em_oem_bits_config_pchlan(struct em_hw *, boolean_t); 181 void em_power_up_serdes_link_82575(struct em_hw *); 182 int32_t em_get_pcs_speed_and_duplex_82575(struct em_hw *, uint16_t *, 183 uint16_t *); 184 int32_t em_set_eee_i350(struct em_hw *); 185 int32_t em_set_eee_pchlan(struct em_hw *); 186 int32_t em_valid_nvm_bank_detect_ich8lan(struct em_hw *, uint32_t *); 187 int32_t em_initialize_M88E1512_phy(struct em_hw *); 188 189 /* IGP cable length table */ 190 static const uint16_t 191 em_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = 192 {5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 193 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25, 194 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40, 195 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60, 196 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90, 197 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 198 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 199 110, 200 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 201 120}; 202 203 static const uint16_t 204 em_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] = 205 {0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 206 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 207 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 208 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 209 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 210 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 211 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 212 121, 124}; 213 214 /****************************************************************************** 215 * Set the phy type member in the hw struct. 216 * 217 * hw - Struct containing variables accessed by shared code 218 *****************************************************************************/ 219 STATIC int32_t 220 em_set_phy_type(struct em_hw *hw) 221 { 222 DEBUGFUNC("em_set_phy_type"); 223 224 if (hw->mac_type == em_undefined) 225 return -E1000_ERR_PHY_TYPE; 226 227 switch (hw->phy_id) { 228 case M88E1000_E_PHY_ID: 229 case M88E1000_I_PHY_ID: 230 case M88E1011_I_PHY_ID: 231 case M88E1111_I_PHY_ID: 232 case M88E1112_E_PHY_ID: 233 case M88E1543_E_PHY_ID: 234 case M88E1512_E_PHY_ID: 235 case I210_I_PHY_ID: 236 case I347AT4_E_PHY_ID: 237 hw->phy_type = em_phy_m88; 238 break; 239 case IGP01E1000_I_PHY_ID: 240 if (hw->mac_type == em_82541 || 241 hw->mac_type == em_82541_rev_2 || 242 hw->mac_type == em_82547 || 243 hw->mac_type == em_82547_rev_2) { 244 hw->phy_type = em_phy_igp; 245 break; 246 } 247 case IGP03E1000_E_PHY_ID: 248 case IGP04E1000_E_PHY_ID: 249 hw->phy_type = em_phy_igp_3; 250 break; 251 case IFE_E_PHY_ID: 252 case IFE_PLUS_E_PHY_ID: 253 case IFE_C_E_PHY_ID: 254 hw->phy_type = em_phy_ife; 255 break; 256 case M88E1141_E_PHY_ID: 257 hw->phy_type = em_phy_oem; 258 break; 259 case I82577_E_PHY_ID: 260 hw->phy_type = em_phy_82577; 261 break; 262 case I82578_E_PHY_ID: 263 hw->phy_type = em_phy_82578; 264 break; 265 case I82579_E_PHY_ID: 266 hw->phy_type = em_phy_82579; 267 break; 268 case I217_E_PHY_ID: 269 hw->phy_type = em_phy_i217; 270 break; 271 case I82580_I_PHY_ID: 272 case I350_I_PHY_ID: 273 hw->phy_type = em_phy_82580; 274 break; 275 case RTL8211_E_PHY_ID: 276 hw->phy_type = em_phy_rtl8211; 277 break; 278 case BME1000_E_PHY_ID: 279 if (hw->phy_revision == 1) { 280 hw->phy_type = em_phy_bm; 281 break; 282 } 283 /* FALLTHROUGH */ 284 case GG82563_E_PHY_ID: 285 if (hw->mac_type == em_80003es2lan) { 286 hw->phy_type = em_phy_gg82563; 287 break; 288 } 289 /* FALLTHROUGH */ 290 default: 291 /* Should never have loaded on this device */ 292 hw->phy_type = em_phy_undefined; 293 return -E1000_ERR_PHY_TYPE; 294 } 295 296 return E1000_SUCCESS; 297 } 298 299 /****************************************************************************** 300 * IGP phy init script - initializes the GbE PHY 301 * 302 * hw - Struct containing variables accessed by shared code 303 *****************************************************************************/ 304 static void 305 em_phy_init_script(struct em_hw *hw) 306 { 307 uint16_t phy_saved_data; 308 DEBUGFUNC("em_phy_init_script"); 309 310 if (hw->phy_init_script) { 311 msec_delay(20); 312 /* 313 * Save off the current value of register 0x2F5B to be 314 * restored at the end of this routine. 315 */ 316 em_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 317 318 /* Disabled the PHY transmitter */ 319 em_write_phy_reg(hw, 0x2F5B, 0x0003); 320 msec_delay(20); 321 em_write_phy_reg(hw, 0x0000, 0x0140); 322 msec_delay(5); 323 324 switch (hw->mac_type) { 325 case em_82541: 326 case em_82547: 327 em_write_phy_reg(hw, 0x1F95, 0x0001); 328 em_write_phy_reg(hw, 0x1F71, 0xBD21); 329 em_write_phy_reg(hw, 0x1F79, 0x0018); 330 em_write_phy_reg(hw, 0x1F30, 0x1600); 331 em_write_phy_reg(hw, 0x1F31, 0x0014); 332 em_write_phy_reg(hw, 0x1F32, 0x161C); 333 em_write_phy_reg(hw, 0x1F94, 0x0003); 334 em_write_phy_reg(hw, 0x1F96, 0x003F); 335 em_write_phy_reg(hw, 0x2010, 0x0008); 336 break; 337 case em_82541_rev_2: 338 case em_82547_rev_2: 339 em_write_phy_reg(hw, 0x1F73, 0x0099); 340 break; 341 default: 342 break; 343 } 344 345 em_write_phy_reg(hw, 0x0000, 0x3300); 346 msec_delay(20); 347 348 /* Now enable the transmitter */ 349 em_write_phy_reg(hw, 0x2F5B, phy_saved_data); 350 351 if (hw->mac_type == em_82547) { 352 uint16_t fused, fine, coarse; 353 /* Move to analog registers page */ 354 em_read_phy_reg(hw, 355 IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused); 356 357 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { 358 em_read_phy_reg(hw, 359 IGP01E1000_ANALOG_FUSE_STATUS, &fused); 360 361 fine = fused & 362 IGP01E1000_ANALOG_FUSE_FINE_MASK; 363 coarse = fused & 364 IGP01E1000_ANALOG_FUSE_COARSE_MASK; 365 366 if (coarse > 367 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { 368 coarse -= 369 IGP01E1000_ANALOG_FUSE_COARSE_10; 370 fine -= 371 IGP01E1000_ANALOG_FUSE_FINE_1; 372 } else if (coarse == 373 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) 374 fine -= IGP01E1000_ANALOG_FUSE_FINE_10; 375 376 fused = (fused & 377 IGP01E1000_ANALOG_FUSE_POLY_MASK) | 378 (fine & 379 IGP01E1000_ANALOG_FUSE_FINE_MASK) | 380 (coarse & 381 IGP01E1000_ANALOG_FUSE_COARSE_MASK); 382 383 em_write_phy_reg(hw, 384 IGP01E1000_ANALOG_FUSE_CONTROL, 385 fused); 386 387 em_write_phy_reg(hw, 388 IGP01E1000_ANALOG_FUSE_BYPASS, 389 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL); 390 } 391 } 392 } 393 } 394 395 /****************************************************************************** 396 * Set the mac type member in the hw struct. 397 * 398 * hw - Struct containing variables accessed by shared code 399 *****************************************************************************/ 400 int32_t 401 em_set_mac_type(struct em_hw *hw) 402 { 403 DEBUGFUNC("em_set_mac_type"); 404 405 switch (hw->device_id) { 406 case E1000_DEV_ID_82542: 407 switch (hw->revision_id) { 408 case E1000_82542_2_0_REV_ID: 409 hw->mac_type = em_82542_rev2_0; 410 break; 411 case E1000_82542_2_1_REV_ID: 412 hw->mac_type = em_82542_rev2_1; 413 break; 414 default: 415 /* Invalid 82542 revision ID */ 416 return -E1000_ERR_MAC_TYPE; 417 } 418 break; 419 case E1000_DEV_ID_82543GC_FIBER: 420 case E1000_DEV_ID_82543GC_COPPER: 421 hw->mac_type = em_82543; 422 break; 423 case E1000_DEV_ID_82544EI_COPPER: 424 case E1000_DEV_ID_82544EI_FIBER: 425 case E1000_DEV_ID_82544GC_COPPER: 426 case E1000_DEV_ID_82544GC_LOM: 427 hw->mac_type = em_82544; 428 break; 429 case E1000_DEV_ID_82540EM: 430 case E1000_DEV_ID_82540EM_LOM: 431 case E1000_DEV_ID_82540EP: 432 case E1000_DEV_ID_82540EP_LOM: 433 case E1000_DEV_ID_82540EP_LP: 434 hw->mac_type = em_82540; 435 break; 436 case E1000_DEV_ID_82545EM_COPPER: 437 case E1000_DEV_ID_82545EM_FIBER: 438 hw->mac_type = em_82545; 439 break; 440 case E1000_DEV_ID_82545GM_COPPER: 441 case E1000_DEV_ID_82545GM_FIBER: 442 case E1000_DEV_ID_82545GM_SERDES: 443 hw->mac_type = em_82545_rev_3; 444 break; 445 case E1000_DEV_ID_82546EB_COPPER: 446 case E1000_DEV_ID_82546EB_FIBER: 447 case E1000_DEV_ID_82546EB_QUAD_COPPER: 448 hw->mac_type = em_82546; 449 break; 450 case E1000_DEV_ID_82546GB_COPPER: 451 case E1000_DEV_ID_82546GB_FIBER: 452 case E1000_DEV_ID_82546GB_SERDES: 453 case E1000_DEV_ID_82546GB_PCIE: 454 case E1000_DEV_ID_82546GB_QUAD_COPPER: 455 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 456 case E1000_DEV_ID_82546GB_2: 457 hw->mac_type = em_82546_rev_3; 458 break; 459 case E1000_DEV_ID_82541EI: 460 case E1000_DEV_ID_82541EI_MOBILE: 461 case E1000_DEV_ID_82541ER_LOM: 462 hw->mac_type = em_82541; 463 break; 464 case E1000_DEV_ID_82541ER: 465 case E1000_DEV_ID_82541GI: 466 case E1000_DEV_ID_82541GI_LF: 467 case E1000_DEV_ID_82541GI_MOBILE: 468 hw->mac_type = em_82541_rev_2; 469 break; 470 case E1000_DEV_ID_82547EI: 471 case E1000_DEV_ID_82547EI_MOBILE: 472 hw->mac_type = em_82547; 473 break; 474 case E1000_DEV_ID_82547GI: 475 hw->mac_type = em_82547_rev_2; 476 break; 477 case E1000_DEV_ID_82571EB_AF: 478 case E1000_DEV_ID_82571EB_AT: 479 case E1000_DEV_ID_82571EB_COPPER: 480 case E1000_DEV_ID_82571EB_FIBER: 481 case E1000_DEV_ID_82571EB_SERDES: 482 case E1000_DEV_ID_82571EB_QUAD_COPPER: 483 case E1000_DEV_ID_82571EB_QUAD_FIBER: 484 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 485 case E1000_DEV_ID_82571EB_SERDES_DUAL: 486 case E1000_DEV_ID_82571EB_SERDES_QUAD: 487 case E1000_DEV_ID_82571PT_QUAD_COPPER: 488 hw->mac_type = em_82571; 489 break; 490 case E1000_DEV_ID_82572EI_COPPER: 491 case E1000_DEV_ID_82572EI_FIBER: 492 case E1000_DEV_ID_82572EI_SERDES: 493 case E1000_DEV_ID_82572EI: 494 hw->mac_type = em_82572; 495 break; 496 case E1000_DEV_ID_82573E: 497 case E1000_DEV_ID_82573E_IAMT: 498 case E1000_DEV_ID_82573E_PM: 499 case E1000_DEV_ID_82573L: 500 case E1000_DEV_ID_82573L_PL_1: 501 case E1000_DEV_ID_82573L_PL_2: 502 case E1000_DEV_ID_82573V_PM: 503 hw->mac_type = em_82573; 504 break; 505 case E1000_DEV_ID_82574L: 506 case E1000_DEV_ID_82574LA: 507 case E1000_DEV_ID_82583V: 508 hw->mac_type = em_82574; 509 break; 510 case E1000_DEV_ID_82575EB_PT: 511 case E1000_DEV_ID_82575EB_PF: 512 case E1000_DEV_ID_82575GB_QP: 513 case E1000_DEV_ID_82575GB_QP_PM: 514 hw->mac_type = em_82575; 515 hw->initialize_hw_bits_disable = 1; 516 break; 517 case E1000_DEV_ID_82576: 518 case E1000_DEV_ID_82576_FIBER: 519 case E1000_DEV_ID_82576_SERDES: 520 case E1000_DEV_ID_82576_QUAD_COPPER: 521 case E1000_DEV_ID_82576_QUAD_CU_ET2: 522 case E1000_DEV_ID_82576_NS: 523 case E1000_DEV_ID_82576_NS_SERDES: 524 case E1000_DEV_ID_82576_SERDES_QUAD: 525 hw->mac_type = em_82576; 526 hw->initialize_hw_bits_disable = 1; 527 break; 528 case E1000_DEV_ID_82580_COPPER: 529 case E1000_DEV_ID_82580_FIBER: 530 case E1000_DEV_ID_82580_QUAD_FIBER: 531 case E1000_DEV_ID_82580_SERDES: 532 case E1000_DEV_ID_82580_SGMII: 533 case E1000_DEV_ID_82580_COPPER_DUAL: 534 case E1000_DEV_ID_DH89XXCC_SGMII: 535 case E1000_DEV_ID_DH89XXCC_SERDES: 536 case E1000_DEV_ID_DH89XXCC_BACKPLANE: 537 case E1000_DEV_ID_DH89XXCC_SFP: 538 hw->mac_type = em_82580; 539 hw->initialize_hw_bits_disable = 1; 540 break; 541 case E1000_DEV_ID_I210_COPPER: 542 case E1000_DEV_ID_I210_COPPER_OEM1: 543 case E1000_DEV_ID_I210_COPPER_IT: 544 case E1000_DEV_ID_I210_FIBER: 545 case E1000_DEV_ID_I210_SERDES: 546 case E1000_DEV_ID_I210_SGMII: 547 case E1000_DEV_ID_I210_COPPER_FLASHLESS: 548 case E1000_DEV_ID_I210_SERDES_FLASHLESS: 549 case E1000_DEV_ID_I211_COPPER: 550 hw->mac_type = em_i210; 551 hw->initialize_hw_bits_disable = 1; 552 hw->eee_enable = 1; 553 break; 554 case E1000_DEV_ID_I350_COPPER: 555 case E1000_DEV_ID_I350_FIBER: 556 case E1000_DEV_ID_I350_SERDES: 557 case E1000_DEV_ID_I350_SGMII: 558 case E1000_DEV_ID_I350_DA4: 559 case E1000_DEV_ID_I354_BACKPLANE_1GBPS: 560 case E1000_DEV_ID_I354_SGMII: 561 case E1000_DEV_ID_I354_BACKPLANE_2_5GBPS: 562 hw->mac_type = em_i350; 563 hw->initialize_hw_bits_disable = 1; 564 hw->eee_enable = 1; 565 break; 566 case E1000_DEV_ID_80003ES2LAN_COPPER_SPT: 567 case E1000_DEV_ID_80003ES2LAN_SERDES_SPT: 568 case E1000_DEV_ID_80003ES2LAN_COPPER_DPT: 569 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: 570 hw->mac_type = em_80003es2lan; 571 break; 572 case E1000_DEV_ID_ICH8_IFE: 573 case E1000_DEV_ID_ICH8_IFE_G: 574 case E1000_DEV_ID_ICH8_IFE_GT: 575 case E1000_DEV_ID_ICH8_IGP_AMT: 576 case E1000_DEV_ID_ICH8_IGP_C: 577 case E1000_DEV_ID_ICH8_IGP_M: 578 case E1000_DEV_ID_ICH8_IGP_M_AMT: 579 case E1000_DEV_ID_ICH8_82567V_3: 580 hw->mac_type = em_ich8lan; 581 break; 582 case E1000_DEV_ID_ICH9_BM: 583 case E1000_DEV_ID_ICH9_IFE: 584 case E1000_DEV_ID_ICH9_IFE_G: 585 case E1000_DEV_ID_ICH9_IFE_GT: 586 case E1000_DEV_ID_ICH9_IGP_AMT: 587 case E1000_DEV_ID_ICH9_IGP_C: 588 case E1000_DEV_ID_ICH9_IGP_M: 589 case E1000_DEV_ID_ICH9_IGP_M_AMT: 590 case E1000_DEV_ID_ICH9_IGP_M_V: 591 case E1000_DEV_ID_ICH10_R_BM_LF: 592 case E1000_DEV_ID_ICH10_R_BM_LM: 593 case E1000_DEV_ID_ICH10_R_BM_V: 594 hw->mac_type = em_ich9lan; 595 break; 596 case E1000_DEV_ID_ICH10_D_BM_LF: 597 case E1000_DEV_ID_ICH10_D_BM_LM: 598 case E1000_DEV_ID_ICH10_D_BM_V: 599 hw->mac_type = em_ich10lan; 600 break; 601 case E1000_DEV_ID_PCH_M_HV_LC: 602 case E1000_DEV_ID_PCH_M_HV_LM: 603 case E1000_DEV_ID_PCH_D_HV_DC: 604 case E1000_DEV_ID_PCH_D_HV_DM: 605 hw->mac_type = em_pchlan; 606 hw->eee_enable = 1; 607 break; 608 case E1000_DEV_ID_PCH2_LV_LM: 609 case E1000_DEV_ID_PCH2_LV_V: 610 hw->mac_type = em_pch2lan; 611 break; 612 case E1000_DEV_ID_PCH_LPT_I217_LM: 613 case E1000_DEV_ID_PCH_LPT_I217_V: 614 case E1000_DEV_ID_PCH_LPTLP_I218_LM: 615 case E1000_DEV_ID_PCH_LPTLP_I218_V: 616 case E1000_DEV_ID_PCH_I218_LM2: 617 case E1000_DEV_ID_PCH_I218_V2: 618 case E1000_DEV_ID_PCH_I218_LM3: 619 case E1000_DEV_ID_PCH_I218_V3: 620 hw->mac_type = em_pch_lpt; 621 break; 622 case E1000_DEV_ID_PCH_SPT_I219_LM: 623 case E1000_DEV_ID_PCH_SPT_I219_V: 624 case E1000_DEV_ID_PCH_SPT_I219_LM2: 625 case E1000_DEV_ID_PCH_SPT_I219_V2: 626 case E1000_DEV_ID_PCH_LBG_I219_LM3: 627 case E1000_DEV_ID_PCH_SPT_I219_LM4: 628 case E1000_DEV_ID_PCH_SPT_I219_V4: 629 case E1000_DEV_ID_PCH_SPT_I219_LM5: 630 case E1000_DEV_ID_PCH_SPT_I219_V5: 631 case E1000_DEV_ID_PCH_CMP_I219_LM12: 632 case E1000_DEV_ID_PCH_CMP_I219_V12: 633 hw->mac_type = em_pch_spt; 634 break; 635 case E1000_DEV_ID_PCH_CNP_I219_LM6: 636 case E1000_DEV_ID_PCH_CNP_I219_V6: 637 case E1000_DEV_ID_PCH_CNP_I219_LM7: 638 case E1000_DEV_ID_PCH_CNP_I219_V7: 639 case E1000_DEV_ID_PCH_ICP_I219_LM8: 640 case E1000_DEV_ID_PCH_ICP_I219_V8: 641 case E1000_DEV_ID_PCH_ICP_I219_LM9: 642 case E1000_DEV_ID_PCH_ICP_I219_V9: 643 case E1000_DEV_ID_PCH_CMP_I219_LM10: 644 case E1000_DEV_ID_PCH_CMP_I219_V10: 645 case E1000_DEV_ID_PCH_CMP_I219_LM11: 646 case E1000_DEV_ID_PCH_CMP_I219_V11: 647 case E1000_DEV_ID_PCH_TGP_I219_LM13: 648 case E1000_DEV_ID_PCH_TGP_I219_V13: 649 case E1000_DEV_ID_PCH_TGP_I219_LM14: 650 case E1000_DEV_ID_PCH_TGP_I219_V14: 651 case E1000_DEV_ID_PCH_TGP_I219_LM15: 652 hw->mac_type = em_pch_cnp; 653 break; 654 case E1000_DEV_ID_EP80579_LAN_1: 655 hw->mac_type = em_icp_xxxx; 656 hw->icp_xxxx_port_num = 0; 657 break; 658 case E1000_DEV_ID_EP80579_LAN_2: 659 case E1000_DEV_ID_EP80579_LAN_4: 660 hw->mac_type = em_icp_xxxx; 661 hw->icp_xxxx_port_num = 1; 662 break; 663 case E1000_DEV_ID_EP80579_LAN_3: 664 case E1000_DEV_ID_EP80579_LAN_5: 665 hw->mac_type = em_icp_xxxx; 666 hw->icp_xxxx_port_num = 2; 667 break; 668 case E1000_DEV_ID_EP80579_LAN_6: 669 hw->mac_type = em_icp_xxxx; 670 hw->icp_xxxx_port_num = 3; 671 break; 672 default: 673 /* Should never have loaded on this device */ 674 return -E1000_ERR_MAC_TYPE; 675 } 676 677 switch (hw->mac_type) { 678 case em_ich8lan: 679 case em_ich9lan: 680 case em_ich10lan: 681 case em_pchlan: 682 case em_pch2lan: 683 case em_pch_lpt: 684 case em_pch_spt: 685 case em_pch_cnp: 686 hw->swfwhw_semaphore_present = TRUE; 687 hw->asf_firmware_present = TRUE; 688 break; 689 case em_80003es2lan: 690 case em_82575: 691 case em_82576: 692 case em_82580: 693 case em_i210: 694 case em_i350: 695 hw->swfw_sync_present = TRUE; 696 /* FALLTHROUGH */ 697 case em_82571: 698 case em_82572: 699 case em_82573: 700 case em_82574: 701 hw->eeprom_semaphore_present = TRUE; 702 /* FALLTHROUGH */ 703 case em_82541: 704 case em_82547: 705 case em_82541_rev_2: 706 case em_82547_rev_2: 707 hw->asf_firmware_present = TRUE; 708 break; 709 default: 710 break; 711 } 712 713 return E1000_SUCCESS; 714 } 715 /***************************************************************************** 716 * Set media type and TBI compatibility. 717 * 718 * hw - Struct containing variables accessed by shared code 719 * **************************************************************************/ 720 void 721 em_set_media_type(struct em_hw *hw) 722 { 723 uint32_t status, ctrl_ext; 724 DEBUGFUNC("em_set_media_type"); 725 726 if (hw->mac_type != em_82543) { 727 /* tbi_compatibility is only valid on 82543 */ 728 hw->tbi_compatibility_en = FALSE; 729 } 730 731 if (hw->mac_type == em_82575 || hw->mac_type == em_82580 || 732 hw->mac_type == em_82576 || 733 hw->mac_type == em_i210 || hw->mac_type == em_i350) { 734 hw->media_type = em_media_type_copper; 735 736 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 737 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) { 738 case E1000_CTRL_EXT_LINK_MODE_SGMII: 739 ctrl_ext |= E1000_CTRL_I2C_ENA; 740 break; 741 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: 742 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES: 743 hw->media_type = em_media_type_internal_serdes; 744 ctrl_ext |= E1000_CTRL_I2C_ENA; 745 break; 746 default: 747 ctrl_ext &= ~E1000_CTRL_I2C_ENA; 748 break; 749 } 750 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 751 return; 752 } 753 754 switch (hw->device_id) { 755 case E1000_DEV_ID_82545GM_SERDES: 756 case E1000_DEV_ID_82546GB_SERDES: 757 case E1000_DEV_ID_82571EB_SERDES: 758 case E1000_DEV_ID_82571EB_SERDES_DUAL: 759 case E1000_DEV_ID_82571EB_SERDES_QUAD: 760 case E1000_DEV_ID_82572EI_SERDES: 761 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: 762 hw->media_type = em_media_type_internal_serdes; 763 break; 764 case E1000_DEV_ID_EP80579_LAN_1: 765 case E1000_DEV_ID_EP80579_LAN_2: 766 case E1000_DEV_ID_EP80579_LAN_3: 767 case E1000_DEV_ID_EP80579_LAN_4: 768 case E1000_DEV_ID_EP80579_LAN_5: 769 case E1000_DEV_ID_EP80579_LAN_6: 770 hw->media_type = em_media_type_copper; 771 break; 772 default: 773 switch (hw->mac_type) { 774 case em_82542_rev2_0: 775 case em_82542_rev2_1: 776 hw->media_type = em_media_type_fiber; 777 break; 778 case em_ich8lan: 779 case em_ich9lan: 780 case em_ich10lan: 781 case em_pchlan: 782 case em_pch2lan: 783 case em_pch_lpt: 784 case em_pch_spt: 785 case em_pch_cnp: 786 case em_82573: 787 case em_82574: 788 /* 789 * The STATUS_TBIMODE bit is reserved or reused for 790 * the this device. 791 */ 792 hw->media_type = em_media_type_copper; 793 break; 794 default: 795 status = E1000_READ_REG(hw, STATUS); 796 if (status & E1000_STATUS_TBIMODE) { 797 hw->media_type = em_media_type_fiber; 798 /* tbi_compatibility not valid on fiber */ 799 hw->tbi_compatibility_en = FALSE; 800 } else { 801 hw->media_type = em_media_type_copper; 802 } 803 break; 804 } 805 } 806 } 807 /****************************************************************************** 808 * Reset the transmit and receive units; mask and clear all interrupts. 809 * 810 * hw - Struct containing variables accessed by shared code 811 *****************************************************************************/ 812 int32_t 813 em_reset_hw(struct em_hw *hw) 814 { 815 uint32_t ctrl; 816 uint32_t ctrl_ext; 817 uint32_t icr; 818 uint32_t manc; 819 uint32_t led_ctrl; 820 uint32_t timeout; 821 uint32_t extcnf_ctrl; 822 int32_t ret_val; 823 DEBUGFUNC("em_reset_hw"); 824 825 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ 826 if (hw->mac_type == em_82542_rev2_0) { 827 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 828 em_pci_clear_mwi(hw); 829 } 830 if (hw->bus_type == em_bus_type_pci_express) { 831 /* 832 * Prevent the PCI-E bus from sticking if there is no TLP 833 * connection on the last TLP read/write transaction when MAC 834 * is reset. 835 */ 836 if (em_disable_pciex_master(hw) != E1000_SUCCESS) { 837 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 838 } 839 } 840 841 /* Set the completion timeout for 82575 chips */ 842 if (hw->mac_type == em_82575 || hw->mac_type == em_82580 || 843 hw->mac_type == em_82576 || 844 hw->mac_type == em_i210 || hw->mac_type == em_i350) { 845 ret_val = em_set_pciex_completion_timeout(hw); 846 if (ret_val) { 847 DEBUGOUT("PCI-E Set completion timeout has failed.\n"); 848 } 849 } 850 851 /* Clear interrupt mask to stop board from generating interrupts */ 852 DEBUGOUT("Masking off all interrupts\n"); 853 E1000_WRITE_REG(hw, IMC, 0xffffffff); 854 /* 855 * Disable the Transmit and Receive units. Then delay to allow any 856 * pending transactions to complete before we hit the MAC with the 857 * global reset. 858 */ 859 E1000_WRITE_REG(hw, RCTL, 0); 860 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP); 861 E1000_WRITE_FLUSH(hw); 862 /* 863 * The tbi_compatibility_on Flag must be cleared when Rctl is 864 * cleared. 865 */ 866 hw->tbi_compatibility_on = FALSE; 867 /* 868 * Delay to allow any outstanding PCI transactions to complete before 869 * resetting the device 870 */ 871 msec_delay(10); 872 873 ctrl = E1000_READ_REG(hw, CTRL); 874 875 /* Must reset the PHY before resetting the MAC */ 876 if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) { 877 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST)); 878 msec_delay(5); 879 } 880 /* 881 * Must acquire the MDIO ownership before MAC reset. Ownership 882 * defaults to firmware after a reset. 883 */ 884 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) { 885 timeout = 10; 886 887 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 888 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 889 890 do { 891 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); 892 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 893 894 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) 895 break; 896 else 897 extcnf_ctrl |= 898 E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 899 900 msec_delay(2); 901 timeout--; 902 } while (timeout); 903 } 904 /* Workaround for ICH8 bit corruption issue in FIFO memory */ 905 if (hw->mac_type == em_ich8lan) { 906 /* Set Tx and Rx buffer allocation to 8k apiece. */ 907 E1000_WRITE_REG(hw, PBA, E1000_PBA_8K); 908 /* Set Packet Buffer Size to 16k. */ 909 E1000_WRITE_REG(hw, PBS, E1000_PBS_16K); 910 } 911 /* 912 * Issue a global reset to the MAC. This will reset the chip's 913 * transmit, receive, DMA, and link units. It will not effect the 914 * current PCI configuration. The global reset bit is self- 915 * clearing, and should clear within a microsecond. 916 */ 917 DEBUGOUT("Issuing a global reset to MAC\n"); 918 919 switch (hw->mac_type) { 920 case em_82544: 921 case em_82540: 922 case em_82545: 923 case em_82546: 924 case em_82541: 925 case em_82541_rev_2: 926 /* 927 * These controllers can't ack the 64-bit write when issuing 928 * the reset, so use IO-mapping as a workaround to issue the 929 * reset 930 */ 931 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST)); 932 break; 933 case em_82545_rev_3: 934 case em_82546_rev_3: 935 /* Reset is performed on a shadow of the control register */ 936 E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST)); 937 break; 938 case em_ich8lan: 939 case em_ich9lan: 940 case em_ich10lan: 941 case em_pchlan: 942 case em_pch2lan: 943 case em_pch_lpt: 944 case em_pch_spt: 945 case em_pch_cnp: 946 if (!hw->phy_reset_disable && 947 em_check_phy_reset_block(hw) == E1000_SUCCESS) { 948 /* 949 * PHY HW reset requires MAC CORE reset at the same 950 * time to make sure the interface between MAC and 951 * the external PHY is reset. 952 */ 953 ctrl |= E1000_CTRL_PHY_RST; 954 /* 955 * Gate automatic PHY configuration by hardware on 956 * non-managed 82579 957 */ 958 if ((hw->mac_type == em_pch2lan) && 959 !(E1000_READ_REG(hw, FWSM) & E1000_FWSM_FW_VALID)) { 960 em_gate_hw_phy_config_ich8lan(hw, TRUE); 961 } 962 } 963 em_get_software_flag(hw); 964 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); 965 /* HW reset releases software_flag */ 966 hw->sw_flag = 0; 967 msec_delay(20); 968 969 /* Ungate automatic PHY configuration on non-managed 82579 */ 970 if (hw->mac_type == em_pch2lan && !hw->phy_reset_disable && 971 !(E1000_READ_REG(hw, FWSM) & E1000_FWSM_FW_VALID)) { 972 msec_delay(10); 973 em_gate_hw_phy_config_ich8lan(hw, FALSE); 974 } 975 break; 976 default: 977 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); 978 break; 979 } 980 981 if (em_check_phy_reset_block(hw) == E1000_SUCCESS) { 982 if (hw->mac_type == em_pchlan) { 983 ret_val = em_hv_phy_workarounds_ich8lan(hw); 984 if (ret_val) 985 return ret_val; 986 } 987 else if (hw->mac_type == em_pch2lan) { 988 ret_val = em_lv_phy_workarounds_ich8lan(hw); 989 if (ret_val) 990 return ret_val; 991 } 992 } 993 994 /* 995 * After MAC reset, force reload of EEPROM to restore power-on 996 * settings to device. Later controllers reload the EEPROM 997 * automatically, so just wait for reload to complete. 998 */ 999 switch (hw->mac_type) { 1000 case em_82542_rev2_0: 1001 case em_82542_rev2_1: 1002 case em_82543: 1003 case em_82544: 1004 /* Wait for reset to complete */ 1005 usec_delay(10); 1006 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1007 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 1008 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1009 E1000_WRITE_FLUSH(hw); 1010 /* Wait for EEPROM reload */ 1011 msec_delay(2); 1012 break; 1013 case em_82541: 1014 case em_82541_rev_2: 1015 case em_82547: 1016 case em_82547_rev_2: 1017 /* Wait for EEPROM reload */ 1018 msec_delay(20); 1019 break; 1020 case em_82573: 1021 case em_82574: 1022 if (em_is_onboard_nvm_eeprom(hw) == FALSE) { 1023 usec_delay(10); 1024 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1025 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 1026 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1027 E1000_WRITE_FLUSH(hw); 1028 } 1029 /* FALLTHROUGH */ 1030 1031 /* Auto read done will delay 5ms or poll based on mac type */ 1032 ret_val = em_get_auto_rd_done(hw); 1033 if (ret_val) 1034 return ret_val; 1035 break; 1036 default: 1037 /* Wait for EEPROM reload (it happens automatically) */ 1038 msec_delay(5); 1039 break; 1040 } 1041 1042 /* Disable HW ARPs on ASF enabled adapters */ 1043 if (hw->mac_type >= em_82540 && hw->mac_type <= em_82547_rev_2 && 1044 hw->mac_type != em_icp_xxxx) { 1045 manc = E1000_READ_REG(hw, MANC); 1046 manc &= ~(E1000_MANC_ARP_EN); 1047 E1000_WRITE_REG(hw, MANC, manc); 1048 } 1049 if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) { 1050 em_phy_init_script(hw); 1051 1052 /* Configure activity LED after PHY reset */ 1053 led_ctrl = E1000_READ_REG(hw, LEDCTL); 1054 led_ctrl &= IGP_ACTIVITY_LED_MASK; 1055 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 1056 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 1057 } 1058 1059 /* 1060 * For PCH, this write will make sure that any noise 1061 * will be detected as a CRC error and be dropped rather than show up 1062 * as a bad packet to the DMA engine. 1063 */ 1064 if (hw->mac_type == em_pchlan) 1065 E1000_WRITE_REG(hw, CRC_OFFSET, 0x65656565); 1066 1067 /* Clear interrupt mask to stop board from generating interrupts */ 1068 DEBUGOUT("Masking off all interrupts\n"); 1069 E1000_WRITE_REG(hw, IMC, 0xffffffff); 1070 1071 /* Clear any pending interrupt events. */ 1072 icr = E1000_READ_REG(hw, ICR); 1073 1074 /* If MWI was previously enabled, reenable it. */ 1075 if (hw->mac_type == em_82542_rev2_0) { 1076 if (hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1077 em_pci_set_mwi(hw); 1078 } 1079 if (IS_ICH8(hw->mac_type)) { 1080 uint32_t kab = E1000_READ_REG(hw, KABGTXD); 1081 kab |= E1000_KABGTXD_BGSQLBIAS; 1082 E1000_WRITE_REG(hw, KABGTXD, kab); 1083 } 1084 1085 if (hw->mac_type == em_82580 || hw->mac_type == em_i350) { 1086 uint32_t mdicnfg; 1087 uint16_t nvm_data; 1088 1089 /* clear global device reset status bit */ 1090 EM_WRITE_REG(hw, E1000_STATUS, E1000_STATUS_DEV_RST_SET); 1091 1092 em_read_eeprom(hw, EEPROM_INIT_CONTROL3_PORT_A + 1093 NVM_82580_LAN_FUNC_OFFSET(hw->bus_func), 1, 1094 &nvm_data); 1095 1096 mdicnfg = EM_READ_REG(hw, E1000_MDICNFG); 1097 if (nvm_data & NVM_WORD24_EXT_MDIO) 1098 mdicnfg |= E1000_MDICNFG_EXT_MDIO; 1099 if (nvm_data & NVM_WORD24_COM_MDIO) 1100 mdicnfg |= E1000_MDICNFG_COM_MDIO; 1101 EM_WRITE_REG(hw, E1000_MDICNFG, mdicnfg); 1102 } 1103 1104 if (hw->mac_type == em_i210 || hw->mac_type == em_i350) 1105 em_set_eee_i350(hw); 1106 1107 return E1000_SUCCESS; 1108 } 1109 1110 /****************************************************************************** 1111 * 1112 * Initialize a number of hardware-dependent bits 1113 * 1114 * hw: Struct containing variables accessed by shared code 1115 * 1116 *****************************************************************************/ 1117 STATIC void 1118 em_initialize_hardware_bits(struct em_hw *hw) 1119 { 1120 DEBUGFUNC("em_initialize_hardware_bits"); 1121 1122 if ((hw->mac_type >= em_82571) && (!hw->initialize_hw_bits_disable)) { 1123 /* Settings common to all silicon */ 1124 uint32_t reg_ctrl, reg_ctrl_ext; 1125 uint32_t reg_tarc0, reg_tarc1; 1126 uint32_t reg_tctl; 1127 uint32_t reg_txdctl, reg_txdctl1; 1128 reg_tarc0 = E1000_READ_REG(hw, TARC0); 1129 reg_tarc0 &= ~0x78000000; /* Clear bits 30, 29, 28, and 1130 * 27 */ 1131 1132 reg_txdctl = E1000_READ_REG(hw, TXDCTL(0)); 1133 reg_txdctl |= E1000_TXDCTL_COUNT_DESC; /* Set bit 22 */ 1134 E1000_WRITE_REG(hw, TXDCTL(0), reg_txdctl); 1135 1136 reg_txdctl1 = E1000_READ_REG(hw, TXDCTL(1)); 1137 reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC; /* Set bit 22 */ 1138 E1000_WRITE_REG(hw, TXDCTL(1), reg_txdctl1); 1139 1140 switch (hw->mac_type) { 1141 case em_82571: 1142 case em_82572: 1143 reg_tarc1 = E1000_READ_REG(hw, TARC1); 1144 reg_tctl = E1000_READ_REG(hw, TCTL); 1145 1146 /* Set the phy Tx compatible mode bits */ 1147 reg_tarc1 &= ~0x60000000; /* Clear bits 30 and 29 */ 1148 1149 reg_tarc0 |= 0x07800000; /* Set TARC0 bits 23-26 */ 1150 reg_tarc1 |= 0x07000000; /* Set TARC1 bits 24-26 */ 1151 1152 if (reg_tctl & E1000_TCTL_MULR) 1153 /* Clear bit 28 if MULR is 1b */ 1154 reg_tarc1 &= ~0x10000000; 1155 else 1156 /* Set bit 28 if MULR is 0b */ 1157 reg_tarc1 |= 0x10000000; 1158 1159 E1000_WRITE_REG(hw, TARC1, reg_tarc1); 1160 break; 1161 case em_82573: 1162 case em_82574: 1163 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1164 reg_ctrl = E1000_READ_REG(hw, CTRL); 1165 1166 reg_ctrl_ext &= ~0x00800000; /* Clear bit 23 */ 1167 reg_ctrl_ext |= 0x00400000; /* Set bit 22 */ 1168 reg_ctrl &= ~0x20000000; /* Clear bit 29 */ 1169 1170 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); 1171 E1000_WRITE_REG(hw, CTRL, reg_ctrl); 1172 break; 1173 case em_80003es2lan: 1174 if ((hw->media_type == em_media_type_fiber) || 1175 (hw->media_type == em_media_type_internal_serdes)) { 1176 /* Clear bit 20 */ 1177 reg_tarc0 &= ~0x00100000; 1178 } 1179 reg_tctl = E1000_READ_REG(hw, TCTL); 1180 reg_tarc1 = E1000_READ_REG(hw, TARC1); 1181 if (reg_tctl & E1000_TCTL_MULR) 1182 /* Clear bit 28 if MULR is 1b */ 1183 reg_tarc1 &= ~0x10000000; 1184 else 1185 /* Set bit 28 if MULR is 0b */ 1186 reg_tarc1 |= 0x10000000; 1187 1188 E1000_WRITE_REG(hw, TARC1, reg_tarc1); 1189 break; 1190 case em_ich8lan: 1191 case em_ich9lan: 1192 case em_ich10lan: 1193 case em_pchlan: 1194 case em_pch2lan: 1195 case em_pch_lpt: 1196 case em_pch_spt: 1197 case em_pch_cnp: 1198 if (hw->mac_type == em_ich8lan) 1199 /* Set TARC0 bits 29 and 28 */ 1200 reg_tarc0 |= 0x30000000; 1201 1202 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1203 reg_ctrl_ext |= 0x00400000; /* Set bit 22 */ 1204 /* Enable PHY low-power state when MAC is at D3 w/o WoL */ 1205 if (hw->mac_type >= em_pchlan) 1206 reg_ctrl_ext |= E1000_CTRL_EXT_PHYPDEN; 1207 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); 1208 1209 reg_tarc0 |= 0x0d800000; /* Set TARC0 bits 23, 1210 * 24, 26, 27 */ 1211 1212 reg_tarc1 = E1000_READ_REG(hw, TARC1); 1213 reg_tctl = E1000_READ_REG(hw, TCTL); 1214 1215 if (reg_tctl & E1000_TCTL_MULR) 1216 /* Clear bit 28 if MULR is 1b */ 1217 reg_tarc1 &= ~0x10000000; 1218 else 1219 /* Set bit 28 if MULR is 0b */ 1220 reg_tarc1 |= 0x10000000; 1221 1222 reg_tarc1 |= 0x45000000; /* Set bit 24, 26 and 1223 * 30 */ 1224 1225 E1000_WRITE_REG(hw, TARC1, reg_tarc1); 1226 break; 1227 default: 1228 break; 1229 } 1230 1231 E1000_WRITE_REG(hw, TARC0, reg_tarc0); 1232 } 1233 } 1234 1235 /** 1236 * e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value 1237 * @hw: pointer to the HW structure 1238 * 1239 * Toggling the LANPHYPC pin value fully power-cycles the PHY and is 1240 * used to reset the PHY to a quiescent state when necessary. 1241 **/ 1242 static void 1243 em_toggle_lanphypc_pch_lpt(struct em_hw *hw) 1244 { 1245 uint32_t mac_reg; 1246 1247 DEBUGFUNC("e1000_toggle_lanphypc_pch_lpt"); 1248 1249 /* Set Phy Config Counter to 50msec */ 1250 mac_reg = E1000_READ_REG(hw, FEXTNVM3); 1251 mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK; 1252 mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC; 1253 E1000_WRITE_REG(hw, FEXTNVM3, mac_reg); 1254 1255 /* Toggle LANPHYPC Value bit */ 1256 mac_reg = E1000_READ_REG(hw, CTRL); 1257 mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE; 1258 mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE; 1259 E1000_WRITE_REG(hw, CTRL, mac_reg); 1260 E1000_WRITE_FLUSH(hw); 1261 msec_delay(1); 1262 mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE; 1263 E1000_WRITE_REG(hw, CTRL, mac_reg); 1264 E1000_WRITE_FLUSH(hw); 1265 1266 if (hw->mac_type < em_pch_lpt) { 1267 msec_delay(50); 1268 } else { 1269 uint16_t count = 20; 1270 1271 do { 1272 msec_delay(5); 1273 } while (!(E1000_READ_REG(hw, CTRL_EXT) & 1274 E1000_CTRL_EXT_LPCD) && count--); 1275 1276 msec_delay(30); 1277 } 1278 } 1279 1280 /** 1281 * em_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP 1282 * @hw: pointer to the HW structure 1283 * @force: boolean indicating whether or not to force disabling ULP 1284 * 1285 * Un-configure ULP mode when link is up, the system is transitioned from 1286 * Sx or the driver is unloaded. If on a Manageability Engine (ME) enabled 1287 * system, poll for an indication from ME that ULP has been un-configured. 1288 * If not on an ME enabled system, un-configure the ULP mode by software. 1289 * 1290 * During nominal operation, this function is called when link is acquired 1291 * to disable ULP mode (force=FALSE); otherwise, for example when unloading 1292 * the driver or during Sx->S0 transitions, this is called with force=TRUE 1293 * to forcibly disable ULP. 1294 */ 1295 static int 1296 em_disable_ulp_lpt_lp(struct em_hw *hw, bool force) 1297 { 1298 int ret_val = E1000_SUCCESS; 1299 uint32_t mac_reg; 1300 uint16_t phy_reg; 1301 int i = 0; 1302 1303 if ((hw->mac_type < em_pch_lpt) || 1304 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) || 1305 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) || 1306 (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) || 1307 (hw->device_id == E1000_DEV_ID_PCH_I218_V2)) 1308 return 0; 1309 1310 if (E1000_READ_REG(hw, FWSM) & E1000_FWSM_FW_VALID) { 1311 if (force) { 1312 /* Request ME un-configure ULP mode in the PHY */ 1313 mac_reg = E1000_READ_REG(hw, H2ME); 1314 mac_reg &= ~E1000_H2ME_ULP; 1315 mac_reg |= E1000_H2ME_ENFORCE_SETTINGS; 1316 E1000_WRITE_REG(hw, H2ME, mac_reg); 1317 } 1318 1319 /* Poll up to 300msec for ME to clear ULP_CFG_DONE. */ 1320 while (E1000_READ_REG(hw, FWSM) & E1000_FWSM_ULP_CFG_DONE) { 1321 if (i++ == 30) { 1322 ret_val = -E1000_ERR_PHY; 1323 goto out; 1324 } 1325 1326 msec_delay(10); 1327 } 1328 DEBUGOUT1("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10); 1329 1330 if (force) { 1331 mac_reg = E1000_READ_REG(hw, H2ME); 1332 mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS; 1333 E1000_WRITE_REG(hw, H2ME, mac_reg); 1334 } else { 1335 /* Clear H2ME.ULP after ME ULP configuration */ 1336 mac_reg = E1000_READ_REG(hw, H2ME); 1337 mac_reg &= ~E1000_H2ME_ULP; 1338 E1000_WRITE_REG(hw, H2ME, mac_reg); 1339 } 1340 1341 goto out; 1342 } 1343 1344 ret_val = em_get_software_flag(hw); 1345 if (ret_val) 1346 goto out; 1347 1348 if (force) 1349 /* Toggle LANPHYPC Value bit */ 1350 em_toggle_lanphypc_pch_lpt(hw); 1351 1352 /* Unforce SMBus mode in PHY */ 1353 ret_val = em_read_phy_reg(hw, CV_SMB_CTRL, &phy_reg); 1354 if (ret_val) { 1355 /* The MAC might be in PCIe mode, so temporarily force to 1356 * SMBus mode in order to access the PHY. 1357 */ 1358 mac_reg = E1000_READ_REG(hw, CTRL_EXT); 1359 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS; 1360 E1000_WRITE_REG(hw, CTRL_EXT, mac_reg); 1361 1362 msec_delay(50); 1363 1364 ret_val = em_read_phy_reg(hw, CV_SMB_CTRL, &phy_reg); 1365 if (ret_val) 1366 goto release; 1367 } 1368 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS; 1369 em_write_phy_reg(hw, CV_SMB_CTRL, phy_reg); 1370 1371 /* Unforce SMBus mode in MAC */ 1372 mac_reg = E1000_READ_REG(hw, CTRL_EXT); 1373 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; 1374 E1000_WRITE_REG(hw, CTRL_EXT, mac_reg); 1375 1376 /* When ULP mode was previously entered, K1 was disabled by the 1377 * hardware. Re-Enable K1 in the PHY when exiting ULP. 1378 */ 1379 ret_val = em_read_phy_reg(hw, HV_PM_CTRL, &phy_reg); 1380 if (ret_val) 1381 goto release; 1382 phy_reg |= HV_PM_CTRL_K1_ENABLE; 1383 em_write_phy_reg(hw, HV_PM_CTRL, phy_reg); 1384 1385 /* Clear ULP enabled configuration */ 1386 ret_val = em_read_phy_reg(hw, I218_ULP_CONFIG1, &phy_reg); 1387 if (ret_val) 1388 goto release; 1389 phy_reg &= ~(I218_ULP_CONFIG1_IND | 1390 I218_ULP_CONFIG1_STICKY_ULP | 1391 I218_ULP_CONFIG1_RESET_TO_SMBUS | 1392 I218_ULP_CONFIG1_WOL_HOST | 1393 I218_ULP_CONFIG1_INBAND_EXIT | 1394 I218_ULP_CONFIG1_EN_ULP_LANPHYPC | 1395 I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST | 1396 I218_ULP_CONFIG1_DISABLE_SMB_PERST); 1397 em_write_phy_reg(hw, I218_ULP_CONFIG1, phy_reg); 1398 1399 /* Commit ULP changes by starting auto ULP configuration */ 1400 phy_reg |= I218_ULP_CONFIG1_START; 1401 em_write_phy_reg(hw, I218_ULP_CONFIG1, phy_reg); 1402 1403 /* Clear Disable SMBus Release on PERST# in MAC */ 1404 mac_reg = E1000_READ_REG(hw, FEXTNVM7); 1405 mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST; 1406 E1000_WRITE_REG(hw, FEXTNVM7, mac_reg); 1407 1408 release: 1409 em_release_software_flag(hw); 1410 if (force) { 1411 em_phy_reset(hw); 1412 msec_delay(50); 1413 } 1414 out: 1415 if (ret_val) 1416 DEBUGOUT1("Error in ULP disable flow: %d\n", ret_val); 1417 1418 return ret_val; 1419 } 1420 1421 /****************************************************************************** 1422 * Performs basic configuration of the adapter. 1423 * 1424 * hw - Struct containing variables accessed by shared code 1425 * 1426 * Assumes that the controller has previously been reset and is in a 1427 * post-reset uninitialized state. Initializes the receive address registers, 1428 * multicast table, and VLAN filter table. Calls routines to setup link 1429 * configuration and flow control settings. Clears all on-chip counters. Leaves 1430 * the transmit and receive units disabled and uninitialized. 1431 *****************************************************************************/ 1432 int32_t 1433 em_init_hw(struct em_hw *hw) 1434 { 1435 uint32_t ctrl; 1436 uint32_t i; 1437 int32_t ret_val; 1438 uint16_t pcix_cmd_word; 1439 uint16_t pcix_stat_hi_word; 1440 uint16_t cmd_mmrbc; 1441 uint16_t stat_mmrbc; 1442 uint32_t mta_size; 1443 uint32_t reg_data; 1444 uint32_t ctrl_ext; 1445 uint32_t snoop; 1446 uint32_t fwsm; 1447 DEBUGFUNC("em_init_hw"); 1448 1449 /* force full DMA clock frequency for ICH8 */ 1450 if (hw->mac_type == em_ich8lan) { 1451 reg_data = E1000_READ_REG(hw, STATUS); 1452 reg_data &= ~0x80000000; 1453 E1000_WRITE_REG(hw, STATUS, reg_data); 1454 } 1455 1456 if (hw->mac_type == em_pchlan || 1457 hw->mac_type == em_pch2lan || 1458 hw->mac_type == em_pch_lpt || 1459 hw->mac_type == em_pch_spt || 1460 hw->mac_type == em_pch_cnp) { 1461 /* 1462 * The MAC-PHY interconnect may still be in SMBus mode 1463 * after Sx->S0. Toggle the LANPHYPC Value bit to force 1464 * the interconnect to PCIe mode, but only if there is no 1465 * firmware present otherwise firmware will have done it. 1466 */ 1467 fwsm = E1000_READ_REG(hw, FWSM); 1468 if ((fwsm & E1000_FWSM_FW_VALID) == 0) { 1469 ctrl = E1000_READ_REG(hw, CTRL); 1470 ctrl |= E1000_CTRL_LANPHYPC_OVERRIDE; 1471 ctrl &= ~E1000_CTRL_LANPHYPC_VALUE; 1472 E1000_WRITE_REG(hw, CTRL, ctrl); 1473 usec_delay(10); 1474 ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE; 1475 E1000_WRITE_REG(hw, CTRL, ctrl); 1476 msec_delay(50); 1477 } 1478 1479 /* Gate automatic PHY configuration on non-managed 82579 */ 1480 if (hw->mac_type == em_pch2lan) 1481 em_gate_hw_phy_config_ich8lan(hw, TRUE); 1482 1483 em_disable_ulp_lpt_lp(hw, TRUE); 1484 /* 1485 * Reset the PHY before any acccess to it. Doing so, 1486 * ensures that the PHY is in a known good state before 1487 * we read/write PHY registers. The generic reset is 1488 * sufficient here, because we haven't determined 1489 * the PHY type yet. 1490 */ 1491 em_phy_reset(hw); 1492 1493 /* Ungate automatic PHY configuration on non-managed 82579 */ 1494 if (hw->mac_type == em_pch2lan && 1495 (fwsm & E1000_FWSM_FW_VALID) == 0) 1496 em_gate_hw_phy_config_ich8lan(hw, FALSE); 1497 1498 /* Set MDIO slow mode before any other MDIO access */ 1499 ret_val = em_set_mdio_slow_mode_hv(hw); 1500 if (ret_val) 1501 return ret_val; 1502 } 1503 1504 /* Initialize Identification LED */ 1505 ret_val = em_id_led_init(hw); 1506 if (ret_val) { 1507 DEBUGOUT("Error Initializing Identification LED\n"); 1508 return ret_val; 1509 } 1510 /* Set the media type and TBI compatibility */ 1511 em_set_media_type(hw); 1512 1513 /* Magic delay that improves problems with i219LM on HP Elitebook */ 1514 msec_delay(1); 1515 /* Must be called after em_set_media_type because media_type is used */ 1516 em_initialize_hardware_bits(hw); 1517 1518 /* Disabling VLAN filtering. */ 1519 DEBUGOUT("Initializing the IEEE VLAN\n"); 1520 /* VET hardcoded to standard value and VFTA removed in ICH8/ICH9 LAN */ 1521 if (!IS_ICH8(hw->mac_type)) { 1522 if (hw->mac_type < em_82545_rev_3) 1523 E1000_WRITE_REG(hw, VET, 0); 1524 if (hw->mac_type == em_i350) 1525 em_clear_vfta_i350(hw); 1526 else 1527 em_clear_vfta(hw); 1528 } 1529 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ 1530 if (hw->mac_type == em_82542_rev2_0) { 1531 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 1532 em_pci_clear_mwi(hw); 1533 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST); 1534 E1000_WRITE_FLUSH(hw); 1535 msec_delay(5); 1536 } 1537 /* 1538 * Setup the receive address. This involves initializing all of the 1539 * Receive Address Registers (RARs 0 - 15). 1540 */ 1541 em_init_rx_addrs(hw); 1542 1543 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI*/ 1544 if (hw->mac_type == em_82542_rev2_0) { 1545 E1000_WRITE_REG(hw, RCTL, 0); 1546 E1000_WRITE_FLUSH(hw); 1547 msec_delay(1); 1548 if (hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1549 em_pci_set_mwi(hw); 1550 } 1551 /* Zero out the Multicast HASH table */ 1552 DEBUGOUT("Zeroing the MTA\n"); 1553 mta_size = E1000_MC_TBL_SIZE; 1554 if (IS_ICH8(hw->mac_type)) 1555 mta_size = E1000_MC_TBL_SIZE_ICH8LAN; 1556 for (i = 0; i < mta_size; i++) { 1557 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 1558 /* 1559 * use write flush to prevent Memory Write Block (MWB) from 1560 * occuring when accessing our register space 1561 */ 1562 E1000_WRITE_FLUSH(hw); 1563 } 1564 /* 1565 * Set the PCI priority bit correctly in the CTRL register. This 1566 * determines if the adapter gives priority to receives, or if it 1567 * gives equal priority to transmits and receives. Valid only on 1568 * 82542 and 82543 silicon. 1569 */ 1570 if (hw->dma_fairness && hw->mac_type <= em_82543) { 1571 ctrl = E1000_READ_REG(hw, CTRL); 1572 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR); 1573 } 1574 switch (hw->mac_type) { 1575 case em_82545_rev_3: 1576 case em_82546_rev_3: 1577 break; 1578 default: 1579 /* 1580 * Workaround for PCI-X problem when BIOS sets MMRBC 1581 * incorrectly. 1582 */ 1583 if (hw->bus_type == em_bus_type_pcix) { 1584 em_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, 1585 &pcix_cmd_word); 1586 em_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, 1587 &pcix_stat_hi_word); 1588 cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) 1589 >> PCIX_COMMAND_MMRBC_SHIFT; 1590 stat_mmrbc = (pcix_stat_hi_word & 1591 PCIX_STATUS_HI_MMRBC_MASK) >> 1592 PCIX_STATUS_HI_MMRBC_SHIFT; 1593 1594 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) 1595 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; 1596 if (cmd_mmrbc > stat_mmrbc) { 1597 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK; 1598 pcix_cmd_word |= stat_mmrbc << 1599 PCIX_COMMAND_MMRBC_SHIFT; 1600 em_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, 1601 &pcix_cmd_word); 1602 } 1603 } 1604 break; 1605 } 1606 1607 /* More time needed for PHY to initialize */ 1608 if (IS_ICH8(hw->mac_type)) 1609 msec_delay(15); 1610 1611 /* 1612 * The 82578 Rx buffer will stall if wakeup is enabled in host and 1613 * the ME. Reading the BM_WUC register will clear the host wakeup bit. 1614 * Reset the phy after disabling host wakeup to reset the Rx buffer. 1615 */ 1616 if (hw->phy_type == em_phy_82578) { 1617 em_read_phy_reg(hw, PHY_REG(BM_WUC_PAGE, 1), 1618 (uint16_t *)®_data); 1619 ret_val = em_phy_reset(hw); 1620 if (ret_val) 1621 return ret_val; 1622 } 1623 1624 /* Call a subroutine to configure the link and setup flow control. */ 1625 ret_val = em_setup_link(hw); 1626 1627 /* Set the transmit descriptor write-back policy */ 1628 if (hw->mac_type > em_82544) { 1629 ctrl = E1000_READ_REG(hw, TXDCTL(0)); 1630 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | 1631 E1000_TXDCTL_FULL_TX_DESC_WB; 1632 E1000_WRITE_REG(hw, TXDCTL(0), ctrl); 1633 } 1634 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) { 1635 em_enable_tx_pkt_filtering(hw); 1636 } 1637 switch (hw->mac_type) { 1638 default: 1639 break; 1640 case em_80003es2lan: 1641 /* Enable retransmit on late collisions */ 1642 reg_data = E1000_READ_REG(hw, TCTL); 1643 reg_data |= E1000_TCTL_RTLC; 1644 E1000_WRITE_REG(hw, TCTL, reg_data); 1645 1646 /* Configure Gigabit Carry Extend Padding */ 1647 reg_data = E1000_READ_REG(hw, TCTL_EXT); 1648 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK; 1649 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX; 1650 E1000_WRITE_REG(hw, TCTL_EXT, reg_data); 1651 1652 /* Configure Transmit Inter-Packet Gap */ 1653 reg_data = E1000_READ_REG(hw, TIPG); 1654 reg_data &= ~E1000_TIPG_IPGT_MASK; 1655 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; 1656 E1000_WRITE_REG(hw, TIPG, reg_data); 1657 1658 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001); 1659 reg_data &= ~0x00100000; 1660 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data); 1661 /* FALLTHROUGH */ 1662 case em_82571: 1663 case em_82572: 1664 case em_82575: 1665 case em_82576: 1666 case em_82580: 1667 case em_i210: 1668 case em_i350: 1669 case em_ich8lan: 1670 case em_ich9lan: 1671 case em_ich10lan: 1672 case em_pchlan: 1673 case em_pch2lan: 1674 case em_pch_lpt: 1675 case em_pch_spt: 1676 case em_pch_cnp: 1677 ctrl = E1000_READ_REG(hw, TXDCTL(1)); 1678 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | 1679 E1000_TXDCTL_FULL_TX_DESC_WB; 1680 E1000_WRITE_REG(hw, TXDCTL(1), ctrl); 1681 break; 1682 } 1683 1684 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) { 1685 uint32_t gcr = E1000_READ_REG(hw, GCR); 1686 gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; 1687 E1000_WRITE_REG(hw, GCR, gcr); 1688 } 1689 /* 1690 * Clear all of the statistics registers (clear on read). It is 1691 * important that we do this after we have tried to establish link 1692 * because the symbol error count will increment wildly if there is 1693 * no link. 1694 */ 1695 em_clear_hw_cntrs(hw); 1696 /* 1697 * ICH8 No-snoop bits are opposite polarity. Set to snoop by default 1698 * after reset. 1699 */ 1700 if (IS_ICH8(hw->mac_type)) { 1701 if (hw->mac_type == em_ich8lan) 1702 snoop = PCI_EX_82566_SNOOP_ALL; 1703 else 1704 snoop = (u_int32_t) ~ (PCI_EX_NO_SNOOP_ALL); 1705 1706 em_set_pci_ex_no_snoop(hw, snoop); 1707 } 1708 1709 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER || 1710 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) { 1711 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1712 /* 1713 * Relaxed ordering must be disabled to avoid a parity error 1714 * crash in a PCI slot. 1715 */ 1716 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 1717 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1718 } 1719 return ret_val; 1720 } 1721 1722 /****************************************************************************** 1723 * Adjust SERDES output amplitude based on EEPROM setting. 1724 * 1725 * hw - Struct containing variables accessed by shared code. 1726 *****************************************************************************/ 1727 static int32_t 1728 em_adjust_serdes_amplitude(struct em_hw *hw) 1729 { 1730 uint16_t eeprom_data; 1731 int32_t ret_val; 1732 DEBUGFUNC("em_adjust_serdes_amplitude"); 1733 1734 if (hw->media_type != em_media_type_internal_serdes || 1735 hw->mac_type >= em_82575) 1736 return E1000_SUCCESS; 1737 1738 switch (hw->mac_type) { 1739 case em_82545_rev_3: 1740 case em_82546_rev_3: 1741 break; 1742 default: 1743 return E1000_SUCCESS; 1744 } 1745 1746 ret_val = em_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data); 1747 if (ret_val) { 1748 return ret_val; 1749 } 1750 if (eeprom_data != EEPROM_RESERVED_WORD) { 1751 /* Adjust SERDES output amplitude only. */ 1752 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK; 1753 ret_val = em_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, 1754 eeprom_data); 1755 if (ret_val) 1756 return ret_val; 1757 } 1758 return E1000_SUCCESS; 1759 } 1760 1761 /****************************************************************************** 1762 * Configures flow control and link settings. 1763 * 1764 * hw - Struct containing variables accessed by shared code 1765 * 1766 * Determines which flow control settings to use. Calls the appropriate media- 1767 * specific link configuration function. Configures the flow control settings. 1768 * Assuming the adapter has a valid link partner, a valid link should be 1769 * established. Assumes the hardware has previously been reset and the 1770 * transmitter and receiver are not enabled. 1771 *****************************************************************************/ 1772 int32_t 1773 em_setup_link(struct em_hw *hw) 1774 { 1775 uint32_t ctrl_ext; 1776 int32_t ret_val; 1777 uint16_t eeprom_data; 1778 uint16_t eeprom_control2_reg_offset; 1779 DEBUGFUNC("em_setup_link"); 1780 1781 eeprom_control2_reg_offset = 1782 (hw->mac_type != em_icp_xxxx) 1783 ? EEPROM_INIT_CONTROL2_REG 1784 : EEPROM_INIT_CONTROL3_ICP_xxxx(hw->icp_xxxx_port_num); 1785 /* 1786 * In the case of the phy reset being blocked, we already have a 1787 * link. We do not have to set it up again. 1788 */ 1789 if (em_check_phy_reset_block(hw)) 1790 return E1000_SUCCESS; 1791 /* 1792 * Read and store word 0x0F of the EEPROM. This word contains bits 1793 * that determine the hardware's default PAUSE (flow control) mode, a 1794 * bit that determines whether the HW defaults to enabling or 1795 * disabling auto-negotiation, and the direction of the SW defined 1796 * pins. If there is no SW over-ride of the flow control setting, 1797 * then the variable hw->fc will be initialized based on a value in 1798 * the EEPROM. 1799 */ 1800 if (hw->fc == E1000_FC_DEFAULT) { 1801 switch (hw->mac_type) { 1802 case em_ich8lan: 1803 case em_ich9lan: 1804 case em_ich10lan: 1805 case em_pchlan: 1806 case em_pch2lan: 1807 case em_pch_lpt: 1808 case em_pch_spt: 1809 case em_pch_cnp: 1810 case em_82573: 1811 case em_82574: 1812 hw->fc = E1000_FC_FULL; 1813 break; 1814 default: 1815 ret_val = em_read_eeprom(hw, 1816 eeprom_control2_reg_offset, 1, &eeprom_data); 1817 if (ret_val) { 1818 DEBUGOUT("EEPROM Read Error\n"); 1819 return -E1000_ERR_EEPROM; 1820 } 1821 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0) 1822 hw->fc = E1000_FC_NONE; 1823 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 1824 EEPROM_WORD0F_ASM_DIR) 1825 hw->fc = E1000_FC_TX_PAUSE; 1826 else 1827 hw->fc = E1000_FC_FULL; 1828 break; 1829 } 1830 } 1831 /* 1832 * We want to save off the original Flow Control configuration just 1833 * in case we get disconnected and then reconnected into a different 1834 * hub or switch with different Flow Control capabilities. 1835 */ 1836 if (hw->mac_type == em_82542_rev2_0) 1837 hw->fc &= (~E1000_FC_TX_PAUSE); 1838 1839 if ((hw->mac_type < em_82543) && (hw->report_tx_early == 1)) 1840 hw->fc &= (~E1000_FC_RX_PAUSE); 1841 1842 hw->original_fc = hw->fc; 1843 1844 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc); 1845 /* 1846 * Take the 4 bits from EEPROM word 0x0F that determine the initial 1847 * polarity value for the SW controlled pins, and setup the Extended 1848 * Device Control reg with that info. This is needed because one of 1849 * the SW controlled pins is used for signal detection. So this 1850 * should be done before em_setup_pcs_link() or em_phy_setup() is 1851 * called. 1852 */ 1853 if (hw->mac_type == em_82543) { 1854 ret_val = em_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1855 1, &eeprom_data); 1856 if (ret_val) { 1857 DEBUGOUT("EEPROM Read Error\n"); 1858 return -E1000_ERR_EEPROM; 1859 } 1860 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << 1861 SWDPIO__EXT_SHIFT); 1862 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1863 } 1864 /* Make sure we have a valid PHY */ 1865 ret_val = em_detect_gig_phy(hw); 1866 if (ret_val) { 1867 DEBUGOUT("Error, did not detect valid phy.\n"); 1868 if (hw->mac_type == em_icp_xxxx) 1869 return E1000_DEFER_INIT; 1870 else 1871 return ret_val; 1872 } 1873 DEBUGOUT1("Phy ID = %x \n", hw->phy_id); 1874 1875 /* Call the necessary subroutine to configure the link. */ 1876 switch (hw->media_type) { 1877 case em_media_type_copper: 1878 case em_media_type_oem: 1879 ret_val = em_setup_copper_link(hw); 1880 break; 1881 default: 1882 ret_val = em_setup_fiber_serdes_link(hw); 1883 break; 1884 } 1885 /* 1886 * Initialize the flow control address, type, and PAUSE timer 1887 * registers to their default values. This is done even if flow 1888 * control is disabled, because it does not hurt anything to 1889 * initialize these registers. 1890 */ 1891 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n" 1892 ); 1893 1894 /* 1895 * FCAL/H and FCT are hardcoded to standard values in 1896 * em_ich8lan / em_ich9lan / em_ich10lan. 1897 */ 1898 if (!IS_ICH8(hw->mac_type)) { 1899 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE); 1900 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH); 1901 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW); 1902 } 1903 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time); 1904 1905 if (hw->phy_type == em_phy_82577 || 1906 hw->phy_type == em_phy_82578 || 1907 hw->phy_type == em_phy_82579 || 1908 hw->phy_type == em_phy_i217) { 1909 E1000_WRITE_REG(hw, FCRTV_PCH, 0x1000); 1910 em_write_phy_reg(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27), 1911 hw->fc_pause_time); 1912 } 1913 1914 /* 1915 * Set the flow control receive threshold registers. Normally, these 1916 * registers will be set to a default threshold that may be adjusted 1917 * later by the driver's runtime code. However, if the ability to 1918 * transmit pause frames in not enabled, then these registers will be 1919 * set to 0. 1920 */ 1921 if (!(hw->fc & E1000_FC_TX_PAUSE)) { 1922 E1000_WRITE_REG(hw, FCRTL, 0); 1923 E1000_WRITE_REG(hw, FCRTH, 0); 1924 } else { 1925 /* 1926 * We need to set up the Receive Threshold high and low water 1927 * marks as well as (optionally) enabling the transmission of 1928 * XON frames. 1929 */ 1930 if (hw->fc_send_xon) { 1931 E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water 1932 | E1000_FCRTL_XONE)); 1933 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); 1934 } else { 1935 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water); 1936 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); 1937 } 1938 } 1939 return ret_val; 1940 } 1941 1942 void 1943 em_power_up_serdes_link_82575(struct em_hw *hw) 1944 { 1945 uint32_t reg; 1946 1947 /* Enable PCS to turn on link */ 1948 reg = E1000_READ_REG(hw, PCS_CFG0); 1949 reg |= E1000_PCS_CFG_PCS_EN; 1950 E1000_WRITE_REG(hw, PCS_CFG0, reg); 1951 1952 /* Power up the laser */ 1953 reg = E1000_READ_REG(hw, CTRL_EXT); 1954 reg &= ~E1000_CTRL_EXT_SDP3_DATA; 1955 E1000_WRITE_REG(hw, CTRL_EXT, reg); 1956 1957 /* flush the write to verify completion */ 1958 E1000_WRITE_FLUSH(hw); 1959 delay(5); 1960 } 1961 1962 /****************************************************************************** 1963 * Sets up link for a fiber based or serdes based adapter 1964 * 1965 * hw - Struct containing variables accessed by shared code 1966 * 1967 * Manipulates Physical Coding Sublayer functions in order to configure 1968 * link. Assumes the hardware has been previously reset and the transmitter 1969 * and receiver are not enabled. 1970 *****************************************************************************/ 1971 static int32_t 1972 em_setup_fiber_serdes_link(struct em_hw *hw) 1973 { 1974 uint32_t ctrl, ctrl_ext, reg; 1975 uint32_t status; 1976 uint32_t txcw = 0; 1977 uint32_t i; 1978 uint32_t signal = 0; 1979 int32_t ret_val; 1980 DEBUGFUNC("em_setup_fiber_serdes_link"); 1981 /* 1982 * On 82571 and 82572 Fiber connections, SerDes loopback mode 1983 * persists until explicitly turned off or a power cycle is 1984 * performed. A read to the register does not indicate its status. 1985 * Therefore, we ensure loopback mode is disabled during 1986 * initialization. 1987 */ 1988 if (hw->mac_type == em_82571 || hw->mac_type == em_82572 || 1989 hw->mac_type >= em_82575) 1990 E1000_WRITE_REG(hw, SCTL, E1000_DISABLE_SERDES_LOOPBACK); 1991 1992 if (hw->mac_type >= em_82575) 1993 em_power_up_serdes_link_82575(hw); 1994 1995 /* 1996 * On adapters with a MAC newer than 82544, SWDP 1 will be set when 1997 * the optics detect a signal. On older adapters, it will be cleared 1998 * when there is a signal. This applies to fiber media only. If 1999 * we're on serdes media, adjust the output amplitude to value set in 2000 * the EEPROM. 2001 */ 2002 ctrl = E1000_READ_REG(hw, CTRL); 2003 if (hw->media_type == em_media_type_fiber) 2004 signal = (hw->mac_type > em_82544) ? E1000_CTRL_SWDPIN1 : 0; 2005 2006 ret_val = em_adjust_serdes_amplitude(hw); 2007 if (ret_val) 2008 return ret_val; 2009 2010 /* Take the link out of reset */ 2011 ctrl &= ~(E1000_CTRL_LRST); 2012 2013 if (hw->mac_type >= em_82575) { 2014 /* set both sw defined pins on 82575/82576*/ 2015 ctrl |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1; 2016 2017 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 2018 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) { 2019 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: 2020 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES: 2021 /* the backplane is always connected */ 2022 reg = E1000_READ_REG(hw, PCS_LCTL); 2023 reg |= E1000_PCS_LCTL_FORCE_FCTRL; 2024 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL; 2025 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */ 2026 DEBUGOUT("Configuring Forced Link\n"); 2027 E1000_WRITE_REG(hw, PCS_LCTL, reg); 2028 em_force_mac_fc(hw); 2029 hw->autoneg_failed = 0; 2030 return E1000_SUCCESS; 2031 break; 2032 default: 2033 /* Set switch control to serdes energy detect */ 2034 reg = E1000_READ_REG(hw, CONNSW); 2035 reg |= E1000_CONNSW_ENRGSRC; 2036 E1000_WRITE_REG(hw, CONNSW, reg); 2037 break; 2038 } 2039 } 2040 2041 /* Adjust VCO speed to improve BER performance */ 2042 ret_val = em_set_vco_speed(hw); 2043 if (ret_val) 2044 return ret_val; 2045 2046 em_config_collision_dist(hw); 2047 /* 2048 * Check for a software override of the flow control settings, and 2049 * setup the device accordingly. If auto-negotiation is enabled, 2050 * then software will have to set the "PAUSE" bits to the correct 2051 * value in the Tranmsit Config Word Register (TXCW) and re-start 2052 * auto-negotiation. However, if auto-negotiation is disabled, then 2053 * software will have to manually configure the two flow control 2054 * enable bits in the CTRL register. 2055 * 2056 * The possible values of the "fc" parameter are: 0: Flow control is 2057 * completely disabled 1: Rx flow control is enabled (we can receive 2058 * pause frames, but not send pause frames). 2: Tx flow control is 2059 * enabled (we can send pause frames but we do not support receiving 2060 * pause frames). 3: Both Rx and TX flow control (symmetric) are 2061 * enabled. 2062 */ 2063 switch (hw->fc) { 2064 case E1000_FC_NONE: 2065 /* 2066 * Flow control is completely disabled by a software 2067 * over-ride. 2068 */ 2069 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 2070 break; 2071 case E1000_FC_RX_PAUSE: 2072 /* 2073 * RX Flow control is enabled and TX Flow control is disabled 2074 * by a software over-ride. Since there really isn't a way to 2075 * advertise that we are capable of RX Pause ONLY, we will 2076 * advertise that we support both symmetric and asymmetric RX 2077 * PAUSE. Later, we will disable the adapter's ability to 2078 * send PAUSE frames. 2079 */ 2080 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | 2081 E1000_TXCW_PAUSE_MASK); 2082 break; 2083 case E1000_FC_TX_PAUSE: 2084 /* 2085 * TX Flow control is enabled, and RX Flow control is 2086 * disabled, by a software over-ride. 2087 */ 2088 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 2089 break; 2090 case E1000_FC_FULL: 2091 /* 2092 * Flow control (both RX and TX) is enabled by a software 2093 * over-ride. 2094 */ 2095 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | 2096 E1000_TXCW_PAUSE_MASK); 2097 break; 2098 default: 2099 DEBUGOUT("Flow control param set incorrectly\n"); 2100 return -E1000_ERR_CONFIG; 2101 break; 2102 } 2103 /* 2104 * Since auto-negotiation is enabled, take the link out of reset (the 2105 * link will be in reset, because we previously reset the chip). This 2106 * will restart auto-negotiation. If auto-neogtiation is successful 2107 * then the link-up status bit will be set and the flow control 2108 * enable bits (RFCE and TFCE) will be set according to their 2109 * negotiated value. 2110 */ 2111 DEBUGOUT("Auto-negotiation enabled\n"); 2112 2113 E1000_WRITE_REG(hw, TXCW, txcw); 2114 E1000_WRITE_REG(hw, CTRL, ctrl); 2115 E1000_WRITE_FLUSH(hw); 2116 2117 hw->txcw = txcw; 2118 msec_delay(1); 2119 /* 2120 * If we have a signal (the cable is plugged in) then poll for a 2121 * "Link-Up" indication in the Device Status Register. Time-out if a 2122 * link isn't seen in 500 milliseconds seconds (Auto-negotiation 2123 * should complete in less than 500 milliseconds even if the other 2124 * end is doing it in SW). For internal serdes, we just assume a 2125 * signal is present, then poll. 2126 */ 2127 if (hw->media_type == em_media_type_internal_serdes || 2128 (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) { 2129 DEBUGOUT("Looking for Link\n"); 2130 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) { 2131 msec_delay(10); 2132 status = E1000_READ_REG(hw, STATUS); 2133 if (status & E1000_STATUS_LU) 2134 break; 2135 } 2136 if (i == (LINK_UP_TIMEOUT / 10)) { 2137 DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 2138 hw->autoneg_failed = 1; 2139 /* 2140 * AutoNeg failed to achieve a link, so we'll call 2141 * em_check_for_link. This routine will force the 2142 * link up if we detect a signal. This will allow us 2143 * to communicate with non-autonegotiating link 2144 * partners. 2145 */ 2146 ret_val = em_check_for_link(hw); 2147 if (ret_val) { 2148 DEBUGOUT("Error while checking for link\n"); 2149 return ret_val; 2150 } 2151 hw->autoneg_failed = 0; 2152 } else { 2153 hw->autoneg_failed = 0; 2154 DEBUGOUT("Valid Link Found\n"); 2155 } 2156 } else { 2157 DEBUGOUT("No Signal Detected\n"); 2158 } 2159 return E1000_SUCCESS; 2160 } 2161 2162 /****************************************************************************** 2163 * Make sure we have a valid PHY and change PHY mode before link setup. 2164 * 2165 * hw - Struct containing variables accessed by shared code 2166 *****************************************************************************/ 2167 static int32_t 2168 em_copper_link_preconfig(struct em_hw *hw) 2169 { 2170 uint32_t ctrl; 2171 int32_t ret_val; 2172 uint16_t phy_data; 2173 DEBUGFUNC("em_copper_link_preconfig"); 2174 2175 ctrl = E1000_READ_REG(hw, CTRL); 2176 /* 2177 * With 82543, we need to force speed and duplex on the MAC equal to 2178 * what the PHY speed and duplex configuration is. In addition, we 2179 * need to perform a hardware reset on the PHY to take it out of 2180 * reset. 2181 */ 2182 if (hw->mac_type > em_82543) { 2183 ctrl |= E1000_CTRL_SLU; 2184 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 2185 E1000_WRITE_REG(hw, CTRL, ctrl); 2186 } else { 2187 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | 2188 E1000_CTRL_SLU); 2189 E1000_WRITE_REG(hw, CTRL, ctrl); 2190 ret_val = em_phy_hw_reset(hw); 2191 if (ret_val) 2192 return ret_val; 2193 } 2194 2195 /* Set PHY to class A mode (if necessary) */ 2196 ret_val = em_set_phy_mode(hw); 2197 if (ret_val) 2198 return ret_val; 2199 2200 if ((hw->mac_type == em_82545_rev_3) || 2201 (hw->mac_type == em_82546_rev_3)) { 2202 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 2203 &phy_data); 2204 phy_data |= 0x00000008; 2205 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 2206 phy_data); 2207 } 2208 if (hw->mac_type <= em_82543 || 2209 hw->mac_type == em_82541 || hw->mac_type == em_82547 || 2210 hw->mac_type == em_82541_rev_2 || hw->mac_type == em_82547_rev_2) 2211 hw->phy_reset_disable = FALSE; 2212 2213 return E1000_SUCCESS; 2214 } 2215 2216 /****************************************************************************** 2217 * Copper link setup for em_phy_igp series. 2218 * 2219 * hw - Struct containing variables accessed by shared code 2220 *****************************************************************************/ 2221 static int32_t 2222 em_copper_link_igp_setup(struct em_hw *hw) 2223 { 2224 uint32_t led_ctrl; 2225 int32_t ret_val; 2226 uint16_t phy_data; 2227 DEBUGFUNC("em_copper_link_igp_setup"); 2228 2229 if (hw->phy_reset_disable) 2230 return E1000_SUCCESS; 2231 2232 ret_val = em_phy_reset(hw); 2233 if (ret_val) { 2234 DEBUGOUT("Error Resetting the PHY\n"); 2235 return ret_val; 2236 } 2237 /* Wait 15ms for MAC to configure PHY from eeprom settings */ 2238 msec_delay(15); 2239 if (hw->mac_type != em_ich8lan && 2240 hw->mac_type != em_ich9lan && 2241 hw->mac_type != em_ich10lan) { 2242 /* Configure activity LED after PHY reset */ 2243 led_ctrl = E1000_READ_REG(hw, LEDCTL); 2244 led_ctrl &= IGP_ACTIVITY_LED_MASK; 2245 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 2246 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 2247 } 2248 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */ 2249 if (hw->phy_type == em_phy_igp) { 2250 /* disable lplu d3 during driver init */ 2251 ret_val = em_set_d3_lplu_state(hw, FALSE); 2252 if (ret_val) { 2253 DEBUGOUT("Error Disabling LPLU D3\n"); 2254 return ret_val; 2255 } 2256 } 2257 /* disable lplu d0 during driver init */ 2258 if (hw->mac_type == em_pchlan || 2259 hw->mac_type == em_pch2lan || 2260 hw->mac_type == em_pch_lpt || 2261 hw->mac_type == em_pch_spt || 2262 hw->mac_type == em_pch_cnp) 2263 ret_val = em_set_lplu_state_pchlan(hw, FALSE); 2264 else 2265 ret_val = em_set_d0_lplu_state(hw, FALSE); 2266 if (ret_val) { 2267 DEBUGOUT("Error Disabling LPLU D0\n"); 2268 return ret_val; 2269 } 2270 /* Configure mdi-mdix settings */ 2271 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 2272 if (ret_val) 2273 return ret_val; 2274 2275 if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) { 2276 hw->dsp_config_state = em_dsp_config_disabled; 2277 /* Force MDI for earlier revs of the IGP PHY */ 2278 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | 2279 IGP01E1000_PSCR_FORCE_MDI_MDIX); 2280 hw->mdix = 1; 2281 2282 } else { 2283 hw->dsp_config_state = em_dsp_config_enabled; 2284 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 2285 2286 switch (hw->mdix) { 2287 case 1: 2288 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 2289 break; 2290 case 2: 2291 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; 2292 break; 2293 case 0: 2294 default: 2295 phy_data |= IGP01E1000_PSCR_AUTO_MDIX; 2296 break; 2297 } 2298 } 2299 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 2300 if (ret_val) 2301 return ret_val; 2302 2303 /* set auto-master slave resolution settings */ 2304 if (hw->autoneg) { 2305 em_ms_type phy_ms_setting = hw->master_slave; 2306 if (hw->ffe_config_state == em_ffe_config_active) 2307 hw->ffe_config_state = em_ffe_config_enabled; 2308 2309 if (hw->dsp_config_state == em_dsp_config_activated) 2310 hw->dsp_config_state = em_dsp_config_enabled; 2311 /* 2312 * when autonegotiation advertisement is only 1000Mbps then 2313 * we should disable SmartSpeed and enable Auto MasterSlave 2314 * resolution as hardware default. 2315 */ 2316 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) { 2317 /* Disable SmartSpeed */ 2318 ret_val = em_read_phy_reg(hw, 2319 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2320 if (ret_val) 2321 return ret_val; 2322 2323 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2324 ret_val = em_write_phy_reg(hw, 2325 IGP01E1000_PHY_PORT_CONFIG, phy_data); 2326 if (ret_val) 2327 return ret_val; 2328 /* Set auto Master/Slave resolution process */ 2329 ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, 2330 &phy_data); 2331 if (ret_val) 2332 return ret_val; 2333 2334 phy_data &= ~CR_1000T_MS_ENABLE; 2335 ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL, 2336 phy_data); 2337 if (ret_val) 2338 return ret_val; 2339 } 2340 ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); 2341 if (ret_val) 2342 return ret_val; 2343 2344 /* load defaults for future use */ 2345 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ? 2346 ((phy_data & CR_1000T_MS_VALUE) ? em_ms_force_master : 2347 em_ms_force_slave) : em_ms_auto; 2348 2349 switch (phy_ms_setting) { 2350 case em_ms_force_master: 2351 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 2352 break; 2353 case em_ms_force_slave: 2354 phy_data |= CR_1000T_MS_ENABLE; 2355 phy_data &= ~(CR_1000T_MS_VALUE); 2356 break; 2357 case em_ms_auto: 2358 phy_data &= ~CR_1000T_MS_ENABLE; 2359 break; 2360 default: 2361 break; 2362 } 2363 ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); 2364 if (ret_val) 2365 return ret_val; 2366 } 2367 return E1000_SUCCESS; 2368 } 2369 2370 /****************************************************************************** 2371 * Copper link setup for em_phy_gg82563 series. 2372 * 2373 * hw - Struct containing variables accessed by shared code 2374 *****************************************************************************/ 2375 static int32_t 2376 em_copper_link_ggp_setup(struct em_hw *hw) 2377 { 2378 int32_t ret_val; 2379 uint16_t phy_data; 2380 uint32_t reg_data; 2381 DEBUGFUNC("em_copper_link_ggp_setup"); 2382 2383 if (!hw->phy_reset_disable) { 2384 2385 /* Enable CRS on TX for half-duplex operation. */ 2386 ret_val = em_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 2387 &phy_data); 2388 if (ret_val) 2389 return ret_val; 2390 2391 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 2392 /* Use 25MHz for both link down and 1000BASE-T for Tx clock */ 2393 phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ; 2394 2395 ret_val = em_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 2396 phy_data); 2397 if (ret_val) 2398 return ret_val; 2399 /* 2400 * Options: MDI/MDI-X = 0 (default) 0 - Auto for all speeds 1 2401 * - MDI mode 2 - MDI-X mode 3 - Auto for 1000Base-T only 2402 * (MDI-X for 10/100Base-T modes) 2403 */ 2404 ret_val = em_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, 2405 &phy_data); 2406 2407 if (ret_val) 2408 return ret_val; 2409 2410 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK; 2411 2412 switch (hw->mdix) { 2413 case 1: 2414 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI; 2415 break; 2416 case 2: 2417 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX; 2418 break; 2419 case 0: 2420 default: 2421 phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO; 2422 break; 2423 } 2424 /* 2425 * Options: disable_polarity_correction = 0 (default) 2426 * Automatic Correction for Reversed Cable Polarity 0 - 2427 * Disabled 1 - Enabled 2428 */ 2429 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 2430 if (hw->disable_polarity_correction == 1) 2431 phy_data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 2432 ret_val = em_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, 2433 phy_data); 2434 2435 if (ret_val) 2436 return ret_val; 2437 2438 /* SW Reset the PHY so all changes take effect */ 2439 ret_val = em_phy_reset(hw); 2440 if (ret_val) { 2441 DEBUGOUT("Error Resetting the PHY\n"); 2442 return ret_val; 2443 } 2444 } /* phy_reset_disable */ 2445 if (hw->mac_type == em_80003es2lan) { 2446 /* Bypass RX and TX FIFO's */ 2447 ret_val = em_write_kmrn_reg(hw, 2448 E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL, 2449 E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS | 2450 E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS); 2451 if (ret_val) 2452 return ret_val; 2453 2454 ret_val = em_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, 2455 &phy_data); 2456 if (ret_val) 2457 return ret_val; 2458 2459 phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG; 2460 ret_val = em_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, 2461 phy_data); 2462 2463 if (ret_val) 2464 return ret_val; 2465 2466 reg_data = E1000_READ_REG(hw, CTRL_EXT); 2467 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK); 2468 E1000_WRITE_REG(hw, CTRL_EXT, reg_data); 2469 2470 ret_val = em_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, 2471 &phy_data); 2472 if (ret_val) 2473 return ret_val; 2474 /* 2475 * Do not init these registers when the HW is in IAMT mode, 2476 * since the firmware will have already initialized them. We 2477 * only initialize them if the HW is not in IAMT mode. 2478 */ 2479 if (em_check_mng_mode(hw) == FALSE) { 2480 /* Enable Electrical Idle on the PHY */ 2481 phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; 2482 ret_val = em_write_phy_reg(hw, 2483 GG82563_PHY_PWR_MGMT_CTRL, phy_data); 2484 if (ret_val) 2485 return ret_val; 2486 2487 ret_val = em_read_phy_reg(hw, 2488 GG82563_PHY_KMRN_MODE_CTRL, &phy_data); 2489 if (ret_val) 2490 return ret_val; 2491 2492 phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 2493 ret_val = em_write_phy_reg(hw, 2494 GG82563_PHY_KMRN_MODE_CTRL, phy_data); 2495 2496 if (ret_val) 2497 return ret_val; 2498 } 2499 /* 2500 * Workaround: Disable padding in Kumeran interface in the 2501 * MAC and in the PHY to avoid CRC errors. 2502 */ 2503 ret_val = em_read_phy_reg(hw, GG82563_PHY_INBAND_CTRL, 2504 &phy_data); 2505 if (ret_val) 2506 return ret_val; 2507 phy_data |= GG82563_ICR_DIS_PADDING; 2508 ret_val = em_write_phy_reg(hw, GG82563_PHY_INBAND_CTRL, 2509 phy_data); 2510 if (ret_val) 2511 return ret_val; 2512 } 2513 return E1000_SUCCESS; 2514 } 2515 2516 /****************************************************************************** 2517 * Copper link setup for em_phy_m88 series. 2518 * 2519 * hw - Struct containing variables accessed by shared code 2520 *****************************************************************************/ 2521 static int32_t 2522 em_copper_link_mgp_setup(struct em_hw *hw) 2523 { 2524 int32_t ret_val; 2525 uint16_t phy_data; 2526 DEBUGFUNC("em_copper_link_mgp_setup"); 2527 2528 if (hw->phy_reset_disable) 2529 return E1000_SUCCESS; 2530 2531 /* disable lplu d0 during driver init */ 2532 if (hw->mac_type == em_pchlan || 2533 hw->mac_type == em_pch2lan || 2534 hw->mac_type == em_pch_lpt || 2535 hw->mac_type == em_pch_spt || 2536 hw->mac_type == em_pch_cnp) 2537 ret_val = em_set_lplu_state_pchlan(hw, FALSE); 2538 2539 /* Enable CRS on TX. This must be set for half-duplex operation. */ 2540 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 2541 if (ret_val) 2542 return ret_val; 2543 2544 if (hw->phy_id == M88E1141_E_PHY_ID) { 2545 phy_data |= 0x00000008; 2546 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 2547 phy_data); 2548 if (ret_val) 2549 return ret_val; 2550 2551 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 2552 &phy_data); 2553 if (ret_val) 2554 return ret_val; 2555 2556 phy_data &= ~M88E1000_PSCR_ASSERT_CRS_ON_TX; 2557 2558 } 2559 /* For BM PHY this bit is downshift enable */ 2560 else if (hw->phy_type != em_phy_bm) 2561 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 2562 /* 2563 * Options: MDI/MDI-X = 0 (default) 0 - Auto for all speeds 1 - MDI 2564 * mode 2 - MDI-X mode 3 - Auto for 1000Base-T only (MDI-X for 2565 * 10/100Base-T modes) 2566 */ 2567 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 2568 2569 switch (hw->mdix) { 2570 case 1: 2571 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 2572 break; 2573 case 2: 2574 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 2575 break; 2576 case 3: 2577 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 2578 break; 2579 case 0: 2580 default: 2581 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 2582 break; 2583 } 2584 /* 2585 * Options: disable_polarity_correction = 0 (default) Automatic 2586 * Correction for Reversed Cable Polarity 0 - Disabled 1 - Enabled 2587 */ 2588 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 2589 if (hw->disable_polarity_correction == 1) 2590 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 2591 2592 /* Enable downshift on BM (disabled by default) */ 2593 if (hw->phy_type == em_phy_bm) 2594 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT; 2595 2596 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 2597 if (ret_val) 2598 return ret_val; 2599 2600 if (((hw->phy_type == em_phy_m88) && 2601 (hw->phy_revision < M88E1011_I_REV_4) && 2602 (hw->phy_id != BME1000_E_PHY_ID)) || 2603 (hw->phy_type == em_phy_oem)) { 2604 /* 2605 * Force TX_CLK in the Extended PHY Specific Control Register 2606 * to 25MHz clock. 2607 */ 2608 ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 2609 &phy_data); 2610 if (ret_val) 2611 return ret_val; 2612 2613 if (hw->phy_type == em_phy_oem) { 2614 phy_data |= M88E1000_EPSCR_TX_TIME_CTRL; 2615 phy_data |= M88E1000_EPSCR_RX_TIME_CTRL; 2616 } 2617 phy_data |= M88E1000_EPSCR_TX_CLK_25; 2618 2619 if ((hw->phy_revision == E1000_REVISION_2) && 2620 (hw->phy_id == M88E1111_I_PHY_ID)) { 2621 /* Vidalia Phy, set the downshift counter to 5x */ 2622 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK); 2623 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; 2624 ret_val = em_write_phy_reg(hw, 2625 M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 2626 if (ret_val) 2627 return ret_val; 2628 } else { 2629 /* Configure Master and Slave downshift values */ 2630 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 2631 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 2632 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 2633 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 2634 ret_val = em_write_phy_reg(hw, 2635 M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 2636 if (ret_val) 2637 return ret_val; 2638 } 2639 } 2640 if ((hw->phy_type == em_phy_bm) && (hw->phy_revision == 1)) { 2641 /* 2642 * Set PHY page 0, register 29 to 0x0003 2643 * The next two writes are supposed to lower BER for gig 2644 * conection 2645 */ 2646 ret_val = em_write_phy_reg(hw, BM_REG_BIAS1, 0x0003); 2647 if (ret_val) 2648 return ret_val; 2649 2650 /* Set PHY page 0, register 30 to 0x0000 */ 2651 ret_val = em_write_phy_reg(hw, BM_REG_BIAS2, 0x0000); 2652 if (ret_val) 2653 return ret_val; 2654 } 2655 if (hw->phy_type == em_phy_82578) { 2656 ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 2657 &phy_data); 2658 if (ret_val) 2659 return ret_val; 2660 2661 /* 82578 PHY - set the downshift count to 1x. */ 2662 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE; 2663 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK; 2664 ret_val = em_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 2665 phy_data); 2666 if (ret_val) 2667 return ret_val; 2668 } 2669 /* SW Reset the PHY so all changes take effect */ 2670 ret_val = em_phy_reset(hw); 2671 if (ret_val) { 2672 DEBUGOUT("Error Resetting the PHY\n"); 2673 return ret_val; 2674 } 2675 return E1000_SUCCESS; 2676 } 2677 2678 /****************************************************************************** 2679 * Copper link setup for em_phy_82577 series. 2680 * 2681 * hw - Struct containing variables accessed by shared code 2682 *****************************************************************************/ 2683 static int32_t 2684 em_copper_link_82577_setup(struct em_hw *hw) 2685 { 2686 int32_t ret_val; 2687 uint16_t phy_data; 2688 uint32_t led_ctl; 2689 DEBUGFUNC("em_copper_link_82577_setup"); 2690 2691 if (hw->phy_reset_disable) 2692 return E1000_SUCCESS; 2693 2694 /* Enable CRS on TX for half-duplex operation. */ 2695 ret_val = em_read_phy_reg(hw, I82577_PHY_CFG_REG, &phy_data); 2696 if (ret_val) 2697 return ret_val; 2698 2699 phy_data |= I82577_PHY_CFG_ENABLE_CRS_ON_TX | 2700 I82577_PHY_CFG_ENABLE_DOWNSHIFT; 2701 2702 ret_val = em_write_phy_reg(hw, I82577_PHY_CFG_REG, phy_data); 2703 if (ret_val) 2704 return ret_val; 2705 2706 /* Wait 15ms for MAC to configure PHY from eeprom settings */ 2707 msec_delay(15); 2708 led_ctl = hw->ledctl_mode1; 2709 2710 /* disable lplu d0 during driver init */ 2711 ret_val = em_set_lplu_state_pchlan(hw, FALSE); 2712 if (ret_val) { 2713 DEBUGOUT("Error Disabling LPLU D0\n"); 2714 return ret_val; 2715 } 2716 2717 E1000_WRITE_REG(hw, LEDCTL, led_ctl); 2718 2719 return E1000_SUCCESS; 2720 } 2721 2722 static int32_t 2723 em_copper_link_82580_setup(struct em_hw *hw) 2724 { 2725 int32_t ret_val; 2726 uint16_t phy_data; 2727 2728 if (hw->phy_reset_disable) 2729 return E1000_SUCCESS; 2730 2731 ret_val = em_phy_reset(hw); 2732 if (ret_val) 2733 goto out; 2734 2735 /* Enable CRS on TX. This must be set for half-duplex operation. */ 2736 ret_val = em_read_phy_reg(hw, I82580_CFG_REG, &phy_data); 2737 if (ret_val) 2738 goto out; 2739 2740 phy_data |= I82580_CFG_ASSERT_CRS_ON_TX | 2741 I82580_CFG_ENABLE_DOWNSHIFT; 2742 2743 ret_val = em_write_phy_reg(hw, I82580_CFG_REG, phy_data); 2744 2745 out: 2746 return ret_val; 2747 } 2748 2749 static int32_t 2750 em_copper_link_rtl8211_setup(struct em_hw *hw) 2751 { 2752 int32_t ret_val; 2753 uint16_t phy_data; 2754 2755 DEBUGFUNC("em_copper_link_rtl8211_setup: begin"); 2756 2757 if (!hw) { 2758 return -1; 2759 } 2760 /* SW Reset the PHY so all changes take effect */ 2761 em_phy_hw_reset(hw); 2762 2763 /* Enable CRS on TX. This must be set for half-duplex operation. */ 2764 phy_data = 0; 2765 2766 ret_val = em_read_phy_reg_ex(hw, RGEPHY_CR, &phy_data); 2767 if (ret_val) { 2768 printf("Unable to read RGEPHY_CR register\n"); 2769 return ret_val; 2770 } 2771 DEBUGOUT3("RTL8211: Rx phy_id=%X addr=%X SPEC_CTRL=%X\n", hw->phy_id, 2772 hw->phy_addr, phy_data); 2773 phy_data |= RGEPHY_CR_ASSERT_CRS; 2774 2775 ret_val = em_write_phy_reg_ex(hw, RGEPHY_CR, phy_data); 2776 if (ret_val) { 2777 printf("Unable to write RGEPHY_CR register\n"); 2778 return ret_val; 2779 } 2780 2781 phy_data = 0; /* LED Control Register 0x18 */ 2782 ret_val = em_read_phy_reg_ex(hw, RGEPHY_LC, &phy_data); 2783 if (ret_val) { 2784 printf("Unable to read RGEPHY_LC register\n"); 2785 return ret_val; 2786 } 2787 2788 phy_data &= 0x80FF; /* bit-15=0 disable, clear bit 8-10 */ 2789 ret_val = em_write_phy_reg_ex(hw, RGEPHY_LC, phy_data); 2790 if (ret_val) { 2791 printf("Unable to write RGEPHY_LC register\n"); 2792 return ret_val; 2793 } 2794 /* LED Control and Definition Register 0x11, PHY spec status reg */ 2795 phy_data = 0; 2796 ret_val = em_read_phy_reg_ex(hw, RGEPHY_SR, &phy_data); 2797 if (ret_val) { 2798 printf("Unable to read RGEPHY_SR register\n"); 2799 return ret_val; 2800 } 2801 2802 phy_data |= 0x0010; /* LED active Low */ 2803 ret_val = em_write_phy_reg_ex(hw, RGEPHY_SR, phy_data); 2804 if (ret_val) { 2805 printf("Unable to write RGEPHY_SR register\n"); 2806 return ret_val; 2807 } 2808 2809 phy_data = 0; 2810 ret_val = em_read_phy_reg_ex(hw, RGEPHY_SR, &phy_data); 2811 if (ret_val) { 2812 printf("Unable to read RGEPHY_SR register\n"); 2813 return ret_val; 2814 } 2815 2816 /* Switch to Page2 */ 2817 phy_data = RGEPHY_PS_PAGE_2; 2818 ret_val = em_write_phy_reg_ex(hw, RGEPHY_PS, phy_data); 2819 if (ret_val) { 2820 printf("Unable to write PHY RGEPHY_PS register\n"); 2821 return ret_val; 2822 } 2823 2824 phy_data = 0x0000; 2825 ret_val = em_write_phy_reg_ex(hw, RGEPHY_LC_P2, phy_data); 2826 if (ret_val) { 2827 printf("Unable to write RGEPHY_LC_P2 register\n"); 2828 return ret_val; 2829 } 2830 usec_delay(5); 2831 2832 2833 /* LED Configuration Control Reg for setting for 0x1A Register */ 2834 phy_data = 0; 2835 ret_val = em_read_phy_reg_ex(hw, RGEPHY_LC_P2, &phy_data); 2836 if (ret_val) { 2837 printf("Unable to read RGEPHY_LC_P2 register\n"); 2838 return ret_val; 2839 } 2840 2841 phy_data &= 0xF000; 2842 phy_data |= 0x0F24; 2843 ret_val = em_write_phy_reg_ex(hw, RGEPHY_LC_P2, phy_data); 2844 if (ret_val) { 2845 printf("Unable to write RGEPHY_LC_P2 register\n"); 2846 return ret_val; 2847 } 2848 phy_data = 0; 2849 ret_val= em_read_phy_reg_ex(hw, RGEPHY_LC_P2, &phy_data); 2850 if (ret_val) { 2851 printf("Unable to read RGEPHY_LC_P2 register\n"); 2852 return ret_val; 2853 } 2854 DEBUGOUT1("RTL8211:ReadBack for check, LED_CFG->data=%X\n", phy_data); 2855 2856 2857 /* After setting Page2, go back to Page 0 */ 2858 phy_data = 0; 2859 ret_val = em_write_phy_reg_ex(hw, RGEPHY_PS, phy_data); 2860 if (ret_val) { 2861 printf("Unable to write PHY RGEPHY_PS register\n"); 2862 return ret_val; 2863 } 2864 2865 /* pulse streching= 42-84ms, blink rate=84mm */ 2866 phy_data = 0x140 | RGEPHY_LC_PULSE_42MS | RGEPHY_LC_LINK | 2867 RGEPHY_LC_DUPLEX | RGEPHY_LC_RX; 2868 2869 ret_val = em_write_phy_reg_ex(hw, RGEPHY_LC, phy_data); 2870 if (ret_val) { 2871 printf("Unable to write RGEPHY_LC register\n"); 2872 return ret_val; 2873 } 2874 return E1000_SUCCESS; 2875 } 2876 2877 /****************************************************************************** 2878 * Setup auto-negotiation and flow control advertisements, 2879 * and then perform auto-negotiation. 2880 * 2881 * hw - Struct containing variables accessed by shared code 2882 *****************************************************************************/ 2883 int32_t 2884 em_copper_link_autoneg(struct em_hw *hw) 2885 { 2886 int32_t ret_val; 2887 uint16_t phy_data; 2888 DEBUGFUNC("em_copper_link_autoneg"); 2889 /* 2890 * Perform some bounds checking on the hw->autoneg_advertised 2891 * parameter. If this variable is zero, then set it to the default. 2892 */ 2893 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT; 2894 /* 2895 * If autoneg_advertised is zero, we assume it was not defaulted by 2896 * the calling code so we set to advertise full capability. 2897 */ 2898 if (hw->autoneg_advertised == 0) 2899 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 2900 2901 /* IFE phy only supports 10/100 */ 2902 if (hw->phy_type == em_phy_ife) 2903 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL; 2904 2905 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); 2906 ret_val = em_phy_setup_autoneg(hw); 2907 if (ret_val) { 2908 DEBUGOUT("Error Setting up Auto-Negotiation\n"); 2909 return ret_val; 2910 } 2911 DEBUGOUT("Restarting Auto-Neg\n"); 2912 /* 2913 * Restart auto-negotiation by setting the Auto Neg Enable bit and 2914 * the Auto Neg Restart bit in the PHY control register. 2915 */ 2916 ret_val = em_read_phy_reg(hw, PHY_CTRL, &phy_data); 2917 if (ret_val) 2918 return ret_val; 2919 2920 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 2921 ret_val = em_write_phy_reg(hw, PHY_CTRL, phy_data); 2922 if (ret_val) 2923 return ret_val; 2924 /* 2925 * Does the user want to wait for Auto-Neg to complete here, or check 2926 * at a later time (for example, callback routine). 2927 */ 2928 if (hw->wait_autoneg_complete) { 2929 ret_val = em_wait_autoneg(hw); 2930 if (ret_val) { 2931 DEBUGOUT("Error while waiting for autoneg to complete\n" 2932 ); 2933 return ret_val; 2934 } 2935 } 2936 hw->get_link_status = TRUE; 2937 2938 return E1000_SUCCESS; 2939 } 2940 2941 /****************************************************************************** 2942 * Config the MAC and the PHY after link is up. 2943 * 1) Set up the MAC to the current PHY speed/duplex 2944 * if we are on 82543. If we 2945 * are on newer silicon, we only need to configure 2946 * collision distance in the Transmit Control Register. 2947 * 2) Set up flow control on the MAC to that established with 2948 * the link partner. 2949 * 3) Config DSP to improve Gigabit link quality for some PHY revisions. 2950 * 2951 * hw - Struct containing variables accessed by shared code 2952 *****************************************************************************/ 2953 int32_t 2954 em_copper_link_postconfig(struct em_hw *hw) 2955 { 2956 int32_t ret_val; 2957 DEBUGFUNC("em_copper_link_postconfig"); 2958 2959 if (hw->mac_type >= em_82544 && 2960 hw->mac_type != em_icp_xxxx) { 2961 em_config_collision_dist(hw); 2962 } else { 2963 ret_val = em_config_mac_to_phy(hw); 2964 if (ret_val) { 2965 DEBUGOUT("Error configuring MAC to PHY settings\n"); 2966 return ret_val; 2967 } 2968 } 2969 ret_val = em_config_fc_after_link_up(hw); 2970 if (ret_val) { 2971 DEBUGOUT("Error Configuring Flow Control\n"); 2972 return ret_val; 2973 } 2974 /* Config DSP to improve Giga link quality */ 2975 if (hw->phy_type == em_phy_igp) { 2976 ret_val = em_config_dsp_after_link_change(hw, TRUE); 2977 if (ret_val) { 2978 DEBUGOUT("Error Configuring DSP after link up\n"); 2979 return ret_val; 2980 } 2981 } 2982 return E1000_SUCCESS; 2983 } 2984 2985 /****************************************************************************** 2986 * Detects which PHY is present and setup the speed and duplex 2987 * 2988 * hw - Struct containing variables accessed by shared code 2989 *****************************************************************************/ 2990 static int32_t 2991 em_setup_copper_link(struct em_hw *hw) 2992 { 2993 int32_t ret_val; 2994 uint16_t i; 2995 uint16_t phy_data; 2996 uint16_t reg_data; 2997 DEBUGFUNC("em_setup_copper_link"); 2998 2999 switch (hw->mac_type) { 3000 case em_80003es2lan: 3001 case em_ich8lan: 3002 case em_ich9lan: 3003 case em_ich10lan: 3004 case em_pchlan: 3005 case em_pch2lan: 3006 case em_pch_lpt: 3007 case em_pch_spt: 3008 case em_pch_cnp: 3009 /* 3010 * Set the mac to wait the maximum time between each 3011 * iteration and increase the max iterations when polling the 3012 * phy; this fixes erroneous timeouts at 10Mbps. 3013 */ 3014 ret_val = em_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF); 3015 if (ret_val) 3016 return ret_val; 3017 ret_val = em_read_kmrn_reg(hw, GG82563_REG(0x34, 9), 3018 ®_data); 3019 if (ret_val) 3020 return ret_val; 3021 reg_data |= 0x3F; 3022 ret_val = em_write_kmrn_reg(hw, GG82563_REG(0x34, 9), 3023 reg_data); 3024 if (ret_val) 3025 return ret_val; 3026 default: 3027 break; 3028 } 3029 3030 /* Check if it is a valid PHY and set PHY mode if necessary. */ 3031 ret_val = em_copper_link_preconfig(hw); 3032 if (ret_val) 3033 return ret_val; 3034 3035 switch (hw->mac_type) { 3036 case em_80003es2lan: 3037 /* Kumeran registers are written-only */ 3038 reg_data = 3039 E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT; 3040 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING; 3041 ret_val = em_write_kmrn_reg(hw, 3042 E1000_KUMCTRLSTA_OFFSET_INB_CTRL, reg_data); 3043 if (ret_val) 3044 return ret_val; 3045 break; 3046 default: 3047 break; 3048 } 3049 3050 if (hw->phy_type == em_phy_igp || 3051 hw->phy_type == em_phy_igp_3 || 3052 hw->phy_type == em_phy_igp_2) { 3053 ret_val = em_copper_link_igp_setup(hw); 3054 if (ret_val) 3055 return ret_val; 3056 } else if (hw->phy_type == em_phy_m88 || 3057 hw->phy_type == em_phy_bm || 3058 hw->phy_type == em_phy_oem || 3059 hw->phy_type == em_phy_82578) { 3060 ret_val = em_copper_link_mgp_setup(hw); 3061 if (ret_val) 3062 return ret_val; 3063 } else if (hw->phy_type == em_phy_gg82563) { 3064 ret_val = em_copper_link_ggp_setup(hw); 3065 if (ret_val) 3066 return ret_val; 3067 } else if (hw->phy_type == em_phy_82577 || 3068 hw->phy_type == em_phy_82579 || 3069 hw->phy_type == em_phy_i217) { 3070 ret_val = em_copper_link_82577_setup(hw); 3071 if (ret_val) 3072 return ret_val; 3073 } else if (hw->phy_type == em_phy_82580) { 3074 ret_val = em_copper_link_82580_setup(hw); 3075 if (ret_val) 3076 return ret_val; 3077 } else if (hw->phy_type == em_phy_rtl8211) { 3078 ret_val = em_copper_link_rtl8211_setup(hw); 3079 if (ret_val) 3080 return ret_val; 3081 } 3082 if (hw->autoneg) { 3083 /* 3084 * Setup autoneg and flow control advertisement and perform 3085 * autonegotiation 3086 */ 3087 ret_val = em_copper_link_autoneg(hw); 3088 if (ret_val) 3089 return ret_val; 3090 } else { 3091 /* 3092 * PHY will be set to 10H, 10F, 100H,or 100F depending on 3093 * value from forced_speed_duplex. 3094 */ 3095 DEBUGOUT("Forcing speed and duplex\n"); 3096 ret_val = em_phy_force_speed_duplex(hw); 3097 if (ret_val) { 3098 DEBUGOUT("Error Forcing Speed and Duplex\n"); 3099 return ret_val; 3100 } 3101 } 3102 /* 3103 * Check link status. Wait up to 100 microseconds for link to become 3104 * valid. 3105 */ 3106 for (i = 0; i < 10; i++) { 3107 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 3108 if (ret_val) 3109 return ret_val; 3110 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 3111 if (ret_val) 3112 return ret_val; 3113 3114 hw->icp_xxxx_is_link_up = (phy_data & MII_SR_LINK_STATUS) != 0; 3115 3116 if (phy_data & MII_SR_LINK_STATUS) { 3117 /* Config the MAC and PHY after link is up */ 3118 ret_val = em_copper_link_postconfig(hw); 3119 if (ret_val) 3120 return ret_val; 3121 3122 DEBUGOUT("Valid link established!!!\n"); 3123 return E1000_SUCCESS; 3124 } 3125 usec_delay(10); 3126 } 3127 3128 DEBUGOUT("Unable to establish link!!!\n"); 3129 return E1000_SUCCESS; 3130 } 3131 3132 /****************************************************************************** 3133 * Configure the MAC-to-PHY interface for 10/100Mbps 3134 * 3135 * hw - Struct containing variables accessed by shared code 3136 *****************************************************************************/ 3137 static int32_t 3138 em_configure_kmrn_for_10_100(struct em_hw *hw, uint16_t duplex) 3139 { 3140 int32_t ret_val = E1000_SUCCESS; 3141 uint32_t tipg; 3142 uint16_t reg_data; 3143 DEBUGFUNC("em_configure_kmrn_for_10_100"); 3144 3145 reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT; 3146 ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL, 3147 reg_data); 3148 if (ret_val) 3149 return ret_val; 3150 3151 /* Configure Transmit Inter-Packet Gap */ 3152 tipg = E1000_READ_REG(hw, TIPG); 3153 tipg &= ~E1000_TIPG_IPGT_MASK; 3154 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100; 3155 E1000_WRITE_REG(hw, TIPG, tipg); 3156 3157 ret_val = em_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); 3158 3159 if (ret_val) 3160 return ret_val; 3161 3162 if (duplex == HALF_DUPLEX) 3163 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER; 3164 else 3165 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 3166 3167 ret_val = em_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 3168 3169 return ret_val; 3170 } 3171 3172 static int32_t 3173 em_configure_kmrn_for_1000(struct em_hw *hw) 3174 { 3175 int32_t ret_val = E1000_SUCCESS; 3176 uint16_t reg_data; 3177 uint32_t tipg; 3178 DEBUGFUNC("em_configure_kmrn_for_1000"); 3179 3180 reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT; 3181 ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL, 3182 reg_data); 3183 if (ret_val) 3184 return ret_val; 3185 3186 /* Configure Transmit Inter-Packet Gap */ 3187 tipg = E1000_READ_REG(hw, TIPG); 3188 tipg &= ~E1000_TIPG_IPGT_MASK; 3189 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; 3190 E1000_WRITE_REG(hw, TIPG, tipg); 3191 3192 ret_val = em_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); 3193 3194 if (ret_val) 3195 return ret_val; 3196 3197 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 3198 ret_val = em_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 3199 3200 return ret_val; 3201 } 3202 3203 /****************************************************************************** 3204 * Configures PHY autoneg and flow control advertisement settings 3205 * 3206 * hw - Struct containing variables accessed by shared code 3207 *****************************************************************************/ 3208 int32_t 3209 em_phy_setup_autoneg(struct em_hw *hw) 3210 { 3211 int32_t ret_val; 3212 uint16_t mii_autoneg_adv_reg; 3213 uint16_t mii_1000t_ctrl_reg; 3214 DEBUGFUNC("em_phy_setup_autoneg"); 3215 3216 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 3217 ret_val = em_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 3218 if (ret_val) 3219 return ret_val; 3220 3221 if (hw->phy_type != em_phy_ife) { 3222 /* Read the MII 1000Base-T Control Register (Address 9). */ 3223 ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, 3224 &mii_1000t_ctrl_reg); 3225 if (ret_val) 3226 return ret_val; 3227 } else 3228 mii_1000t_ctrl_reg = 0; 3229 /* 3230 * Need to parse both autoneg_advertised and fc and set up the 3231 * appropriate PHY registers. First we will parse for 3232 * autoneg_advertised software override. Since we can advertise a 3233 * plethora of combinations, we need to check each bit individually. 3234 */ 3235 /* 3236 * First we clear all the 10/100 mb speed bits in the Auto-Neg 3237 * Advertisement Register (Address 4) and the 1000 mb speed bits in 3238 * the 1000Base-T Control Register (Address 9). 3239 */ 3240 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK; 3241 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK; 3242 3243 DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised); 3244 3245 /* Do we want to advertise 10 Mb Half Duplex? */ 3246 if (hw->autoneg_advertised & ADVERTISE_10_HALF) { 3247 DEBUGOUT("Advertise 10mb Half duplex\n"); 3248 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 3249 } 3250 /* Do we want to advertise 10 Mb Full Duplex? */ 3251 if (hw->autoneg_advertised & ADVERTISE_10_FULL) { 3252 DEBUGOUT("Advertise 10mb Full duplex\n"); 3253 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 3254 } 3255 /* Do we want to advertise 100 Mb Half Duplex? */ 3256 if (hw->autoneg_advertised & ADVERTISE_100_HALF) { 3257 DEBUGOUT("Advertise 100mb Half duplex\n"); 3258 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 3259 } 3260 /* Do we want to advertise 100 Mb Full Duplex? */ 3261 if (hw->autoneg_advertised & ADVERTISE_100_FULL) { 3262 DEBUGOUT("Advertise 100mb Full duplex\n"); 3263 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 3264 } 3265 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 3266 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) { 3267 DEBUGOUT("Advertise 1000mb Half duplex requested, request" 3268 " denied!\n"); 3269 } 3270 /* Do we want to advertise 1000 Mb Full Duplex? */ 3271 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) { 3272 DEBUGOUT("Advertise 1000mb Full duplex\n"); 3273 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 3274 if (hw->phy_type == em_phy_ife) { 3275 DEBUGOUT("em_phy_ife is a 10/100 PHY. Gigabit speed is" 3276 " not supported.\n"); 3277 } 3278 } 3279 /* 3280 * Check for a software override of the flow control settings, and 3281 * setup the PHY advertisement registers accordingly. If 3282 * auto-negotiation is enabled, then software will have to set the 3283 * "PAUSE" bits to the correct value in the Auto-Negotiation 3284 * Advertisement Register (PHY_AUTONEG_ADV) and re-start 3285 * auto-negotiation. 3286 * 3287 * The possible values of the "fc" parameter are: 0: Flow control is 3288 * completely disabled 1: Rx flow control is enabled (we can receive 3289 * pause frames but not send pause frames). 2: Tx flow control is 3290 * enabled (we can send pause frames but we do not support receiving 3291 * pause frames). 3: Both Rx and TX flow control (symmetric) are 3292 * enabled. other: No software override. The flow control 3293 * configuration in the EEPROM is used. 3294 */ 3295 switch (hw->fc) { 3296 case E1000_FC_NONE: /* 0 */ 3297 /* 3298 * Flow control (RX & TX) is completely disabled by a 3299 * software over-ride. 3300 */ 3301 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 3302 break; 3303 case E1000_FC_RX_PAUSE:/* 1 */ 3304 /* 3305 * RX Flow control is enabled, and TX Flow control is 3306 * disabled, by a software over-ride. 3307 */ 3308 /* 3309 * Since there really isn't a way to advertise that we are 3310 * capable of RX Pause ONLY, we will advertise that we 3311 * support both symmetric and asymmetric RX PAUSE. Later (in 3312 * em_config_fc_after_link_up) we will disable the hw's 3313 * ability to send PAUSE frames. 3314 */ 3315 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 3316 break; 3317 case E1000_FC_TX_PAUSE:/* 2 */ 3318 /* 3319 * TX Flow control is enabled, and RX Flow control is 3320 * disabled, by a software over-ride. 3321 */ 3322 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 3323 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 3324 break; 3325 case E1000_FC_FULL: /* 3 */ 3326 /* 3327 * Flow control (both RX and TX) is enabled by a software 3328 * over-ride. 3329 */ 3330 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 3331 break; 3332 default: 3333 DEBUGOUT("Flow control param set incorrectly\n"); 3334 return -E1000_ERR_CONFIG; 3335 } 3336 3337 ret_val = em_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 3338 if (ret_val) 3339 return ret_val; 3340 3341 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 3342 3343 if (hw->phy_type != em_phy_ife) { 3344 ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL, 3345 mii_1000t_ctrl_reg); 3346 if (ret_val) 3347 return ret_val; 3348 } 3349 return E1000_SUCCESS; 3350 } 3351 /****************************************************************************** 3352 * Force PHY speed and duplex settings to hw->forced_speed_duplex 3353 * 3354 * hw - Struct containing variables accessed by shared code 3355 *****************************************************************************/ 3356 static int32_t 3357 em_phy_force_speed_duplex(struct em_hw *hw) 3358 { 3359 uint32_t ctrl; 3360 int32_t ret_val; 3361 uint16_t mii_ctrl_reg; 3362 uint16_t mii_status_reg; 3363 uint16_t phy_data; 3364 uint16_t i; 3365 DEBUGFUNC("em_phy_force_speed_duplex"); 3366 3367 /* Turn off Flow control if we are forcing speed and duplex. */ 3368 hw->fc = E1000_FC_NONE; 3369 3370 DEBUGOUT1("hw->fc = %d\n", hw->fc); 3371 3372 /* Read the Device Control Register. */ 3373 ctrl = E1000_READ_REG(hw, CTRL); 3374 3375 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */ 3376 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 3377 ctrl &= ~(DEVICE_SPEED_MASK); 3378 3379 /* Clear the Auto Speed Detect Enable bit. */ 3380 ctrl &= ~E1000_CTRL_ASDE; 3381 3382 /* Read the MII Control Register. */ 3383 ret_val = em_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg); 3384 if (ret_val) 3385 return ret_val; 3386 3387 /* We need to disable autoneg in order to force link and duplex. */ 3388 3389 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN; 3390 3391 /* Are we forcing Full or Half Duplex? */ 3392 if (hw->forced_speed_duplex == em_100_full || 3393 hw->forced_speed_duplex == em_10_full) { 3394 /* 3395 * We want to force full duplex so we SET the full duplex 3396 * bits in the Device and MII Control Registers. 3397 */ 3398 ctrl |= E1000_CTRL_FD; 3399 mii_ctrl_reg |= MII_CR_FULL_DUPLEX; 3400 DEBUGOUT("Full Duplex\n"); 3401 } else { 3402 /* 3403 * We want to force half duplex so we CLEAR the full duplex 3404 * bits in the Device and MII Control Registers. 3405 */ 3406 ctrl &= ~E1000_CTRL_FD; 3407 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX; 3408 DEBUGOUT("Half Duplex\n"); 3409 } 3410 3411 /* Are we forcing 100Mbps??? */ 3412 if (hw->forced_speed_duplex == em_100_full || 3413 hw->forced_speed_duplex == em_100_half) { 3414 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */ 3415 ctrl |= E1000_CTRL_SPD_100; 3416 mii_ctrl_reg |= MII_CR_SPEED_100; 3417 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); 3418 DEBUGOUT("Forcing 100mb "); 3419 } else { 3420 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */ 3421 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 3422 mii_ctrl_reg |= MII_CR_SPEED_10; 3423 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); 3424 DEBUGOUT("Forcing 10mb "); 3425 } 3426 3427 em_config_collision_dist(hw); 3428 3429 /* Write the configured values back to the Device Control Reg. */ 3430 E1000_WRITE_REG(hw, CTRL, ctrl); 3431 3432 if ((hw->phy_type == em_phy_m88) || 3433 (hw->phy_type == em_phy_gg82563) || 3434 (hw->phy_type == em_phy_bm) || 3435 (hw->phy_type == em_phy_oem || 3436 (hw->phy_type == em_phy_82578))) { 3437 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 3438 &phy_data); 3439 if (ret_val) 3440 return ret_val; 3441 /* 3442 * Clear Auto-Crossover to force MDI manually. M88E1000 3443 * requires MDI forced whenever speed are duplex are forced. 3444 */ 3445 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 3446 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 3447 phy_data); 3448 if (ret_val) 3449 return ret_val; 3450 3451 DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data); 3452 3453 /* Need to reset the PHY or these changes will be ignored */ 3454 mii_ctrl_reg |= MII_CR_RESET; 3455 3456 } 3457 else if (hw->phy_type == em_phy_rtl8211) { 3458 ret_val = em_read_phy_reg_ex(hw, RGEPHY_CR, &phy_data); 3459 if(ret_val) { 3460 printf("Unable to read RGEPHY_CR register\n" 3461 ); 3462 return ret_val; 3463 } 3464 3465 /* 3466 * Clear Auto-Crossover to force MDI manually. RTL8211 requires 3467 * MDI forced whenever speed are duplex are forced. 3468 */ 3469 3470 phy_data |= RGEPHY_CR_MDI_MASK; // enable MDIX 3471 ret_val = em_write_phy_reg_ex(hw, RGEPHY_CR, phy_data); 3472 if(ret_val) { 3473 printf("Unable to write RGEPHY_CR register\n"); 3474 return ret_val; 3475 } 3476 mii_ctrl_reg |= MII_CR_RESET; 3477 3478 } 3479 /* Disable MDI-X support for 10/100 */ 3480 else if (hw->phy_type == em_phy_ife) { 3481 ret_val = em_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data); 3482 if (ret_val) 3483 return ret_val; 3484 3485 phy_data &= ~IFE_PMC_AUTO_MDIX; 3486 phy_data &= ~IFE_PMC_FORCE_MDIX; 3487 3488 ret_val = em_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, phy_data); 3489 if (ret_val) 3490 return ret_val; 3491 } else { 3492 /* 3493 * Clear Auto-Crossover to force MDI manually. IGP requires 3494 * MDI forced whenever speed or duplex are forced. 3495 */ 3496 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, 3497 &phy_data); 3498 if (ret_val) 3499 return ret_val; 3500 3501 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 3502 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 3503 3504 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, 3505 phy_data); 3506 if (ret_val) 3507 return ret_val; 3508 } 3509 3510 /* Write back the modified PHY MII control register. */ 3511 ret_val = em_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg); 3512 if (ret_val) 3513 return ret_val; 3514 3515 usec_delay(1); 3516 /* 3517 * The wait_autoneg_complete flag may be a little misleading here. 3518 * Since we are forcing speed and duplex, Auto-Neg is not enabled. 3519 * But we do want to delay for a period while forcing only so we 3520 * don't generate false No Link messages. So we will wait here only 3521 * if the user has set wait_autoneg_complete to 1, which is the 3522 * default. 3523 */ 3524 if (hw->wait_autoneg_complete) { 3525 /* We will wait for autoneg to complete. */ 3526 DEBUGOUT("Waiting for forced speed/duplex link.\n"); 3527 mii_status_reg = 0; 3528 /* 3529 * We will wait for autoneg to complete or 4.5 seconds to 3530 * expire. 3531 */ 3532 for (i = PHY_FORCE_TIME; i > 0; i--) { 3533 /* 3534 * Read the MII Status Register and wait for Auto-Neg 3535 * Complete bit to be set. 3536 */ 3537 ret_val = em_read_phy_reg(hw, PHY_STATUS, 3538 &mii_status_reg); 3539 if (ret_val) 3540 return ret_val; 3541 3542 ret_val = em_read_phy_reg(hw, PHY_STATUS, 3543 &mii_status_reg); 3544 if (ret_val) 3545 return ret_val; 3546 3547 if (mii_status_reg & MII_SR_LINK_STATUS) 3548 break; 3549 msec_delay(100); 3550 } 3551 if ((i == 0) && 3552 ((hw->phy_type == em_phy_m88) || 3553 (hw->phy_type == em_phy_gg82563) || 3554 (hw->phy_type == em_phy_bm))) { 3555 /* 3556 * We didn't get link. Reset the DSP and wait again 3557 * for link. 3558 */ 3559 ret_val = em_phy_reset_dsp(hw); 3560 if (ret_val) { 3561 DEBUGOUT("Error Resetting PHY DSP\n"); 3562 return ret_val; 3563 } 3564 } 3565 /* 3566 * This loop will early-out if the link condition has been 3567 * met. 3568 */ 3569 for (i = PHY_FORCE_TIME; i > 0; i--) { 3570 if (mii_status_reg & MII_SR_LINK_STATUS) 3571 break; 3572 msec_delay(100); 3573 /* 3574 * Read the MII Status Register and wait for Auto-Neg 3575 * Complete bit to be set. 3576 */ 3577 ret_val = em_read_phy_reg(hw, PHY_STATUS, 3578 &mii_status_reg); 3579 if (ret_val) 3580 return ret_val; 3581 3582 ret_val = em_read_phy_reg(hw, PHY_STATUS, 3583 &mii_status_reg); 3584 if (ret_val) 3585 return ret_val; 3586 } 3587 } 3588 if (hw->phy_type == em_phy_m88 || 3589 hw->phy_type == em_phy_bm || 3590 hw->phy_type == em_phy_oem) { 3591 /* 3592 * Because we reset the PHY above, we need to re-force TX_CLK 3593 * in the Extended PHY Specific Control Register to 25MHz 3594 * clock. This value defaults back to a 2.5MHz clock when 3595 * the PHY is reset. 3596 */ 3597 ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 3598 &phy_data); 3599 if (ret_val) 3600 return ret_val; 3601 3602 phy_data |= M88E1000_EPSCR_TX_CLK_25; 3603 ret_val = em_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 3604 phy_data); 3605 if (ret_val) 3606 return ret_val; 3607 /* 3608 * In addition, because of the s/w reset above, we need to 3609 * enable CRS on TX. This must be set for both full and half 3610 * duplex operation. 3611 */ 3612 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 3613 &phy_data); 3614 if (ret_val) 3615 return ret_val; 3616 3617 if (hw->phy_id == M88E1141_E_PHY_ID) 3618 phy_data &= ~M88E1000_PSCR_ASSERT_CRS_ON_TX; 3619 else 3620 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 3621 3622 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 3623 phy_data); 3624 if (ret_val) 3625 return ret_val; 3626 3627 if ((hw->mac_type == em_82544 || hw->mac_type == em_82543) && 3628 (!hw->autoneg) && (hw->forced_speed_duplex == em_10_full || 3629 hw->forced_speed_duplex == em_10_half)) { 3630 ret_val = em_polarity_reversal_workaround(hw); 3631 if (ret_val) 3632 return ret_val; 3633 } 3634 } else if (hw->phy_type == em_phy_rtl8211) { 3635 /* 3636 * In addition, because of the s/w reset above, we need to enable 3637 * CRX on TX. This must be set for both full and half duplex 3638 * operation. 3639 */ 3640 3641 ret_val = em_read_phy_reg_ex(hw, RGEPHY_CR, &phy_data); 3642 if(ret_val) { 3643 printf("Unable to read RGEPHY_CR register\n"); 3644 return ret_val; 3645 } 3646 3647 phy_data &= ~RGEPHY_CR_ASSERT_CRS; 3648 ret_val = em_write_phy_reg_ex(hw, RGEPHY_CR, phy_data); 3649 if(ret_val) { 3650 printf("Unable to write RGEPHY_CR register\n"); 3651 return ret_val; 3652 } 3653 } else if (hw->phy_type == em_phy_gg82563) { 3654 /* 3655 * The TX_CLK of the Extended PHY Specific Control Register 3656 * defaults to 2.5MHz on a reset. We need to re-force it 3657 * back to 25MHz, if we're not in a forced 10/duplex 3658 * configuration. 3659 */ 3660 ret_val = em_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 3661 &phy_data); 3662 if (ret_val) 3663 return ret_val; 3664 3665 phy_data &= ~GG82563_MSCR_TX_CLK_MASK; 3666 if ((hw->forced_speed_duplex == em_10_full) || 3667 (hw->forced_speed_duplex == em_10_half)) 3668 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ; 3669 else 3670 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25MHZ; 3671 3672 /* Also due to the reset, we need to enable CRS on Tx. */ 3673 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 3674 3675 ret_val = em_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 3676 phy_data); 3677 if (ret_val) 3678 return ret_val; 3679 } 3680 return E1000_SUCCESS; 3681 } 3682 3683 /****************************************************************************** 3684 * Sets the collision distance in the Transmit Control register 3685 * 3686 * hw - Struct containing variables accessed by shared code 3687 * 3688 * Link should have been established previously. Reads the speed and duplex 3689 * information from the Device Status register. 3690 *****************************************************************************/ 3691 void 3692 em_config_collision_dist(struct em_hw *hw) 3693 { 3694 uint32_t tctl, coll_dist; 3695 DEBUGFUNC("em_config_collision_dist"); 3696 3697 if (hw->mac_type < em_82543) 3698 coll_dist = E1000_COLLISION_DISTANCE_82542; 3699 else 3700 coll_dist = E1000_COLLISION_DISTANCE; 3701 3702 tctl = E1000_READ_REG(hw, TCTL); 3703 3704 tctl &= ~E1000_TCTL_COLD; 3705 tctl |= coll_dist << E1000_COLD_SHIFT; 3706 3707 E1000_WRITE_REG(hw, TCTL, tctl); 3708 E1000_WRITE_FLUSH(hw); 3709 } 3710 3711 /****************************************************************************** 3712 * Sets MAC speed and duplex settings to reflect the those in the PHY 3713 * 3714 * hw - Struct containing variables accessed by shared code 3715 * mii_reg - data to write to the MII control register 3716 * 3717 * The contents of the PHY register containing the needed information need to 3718 * be passed in. 3719 *****************************************************************************/ 3720 static int32_t 3721 em_config_mac_to_phy(struct em_hw *hw) 3722 { 3723 uint32_t ctrl; 3724 int32_t ret_val; 3725 uint16_t phy_data; 3726 DEBUGFUNC("em_config_mac_to_phy"); 3727 /* 3728 * 82544 or newer MAC, Auto Speed Detection takes care of MAC 3729 * speed/duplex configuration. 3730 */ 3731 if (hw->mac_type >= em_82544 3732 && hw->mac_type != em_icp_xxxx) 3733 return E1000_SUCCESS; 3734 /* 3735 * Read the Device Control Register and set the bits to Force Speed 3736 * and Duplex. 3737 */ 3738 ctrl = E1000_READ_REG(hw, CTRL); 3739 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 3740 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); 3741 /* 3742 * Set up duplex in the Device Control and Transmit Control registers 3743 * depending on negotiated values. 3744 */ 3745 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 3746 if (ret_val) 3747 return ret_val; 3748 3749 if (phy_data & M88E1000_PSSR_DPLX) 3750 ctrl |= E1000_CTRL_FD; 3751 else 3752 ctrl &= ~E1000_CTRL_FD; 3753 3754 em_config_collision_dist(hw); 3755 /* 3756 * Set up speed in the Device Control register depending on 3757 * negotiated values. 3758 */ 3759 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) 3760 ctrl |= E1000_CTRL_SPD_1000; 3761 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) 3762 ctrl |= E1000_CTRL_SPD_100; 3763 3764 /* Write the configured values back to the Device Control Reg. */ 3765 E1000_WRITE_REG(hw, CTRL, ctrl); 3766 return E1000_SUCCESS; 3767 } 3768 3769 /****************************************************************************** 3770 * Forces the MAC's flow control settings. 3771 * 3772 * hw - Struct containing variables accessed by shared code 3773 * 3774 * Sets the TFCE and RFCE bits in the device control register to reflect 3775 * the adapter settings. TFCE and RFCE need to be explicitly set by 3776 * software when a Copper PHY is used because autonegotiation is managed 3777 * by the PHY rather than the MAC. Software must also configure these 3778 * bits when link is forced on a fiber connection. 3779 *****************************************************************************/ 3780 int32_t 3781 em_force_mac_fc(struct em_hw *hw) 3782 { 3783 uint32_t ctrl; 3784 DEBUGFUNC("em_force_mac_fc"); 3785 3786 /* Get the current configuration of the Device Control Register */ 3787 ctrl = E1000_READ_REG(hw, CTRL); 3788 /* 3789 * Because we didn't get link via the internal auto-negotiation 3790 * mechanism (we either forced link or we got link via PHY auto-neg), 3791 * we have to manually enable/disable transmit an receive flow 3792 * control. 3793 * 3794 * The "Case" statement below enables/disable flow control according to 3795 * the "hw->fc" parameter. 3796 * 3797 * The possible values of the "fc" parameter are: 0: Flow control is 3798 * completely disabled 1: Rx flow control is enabled (we can receive 3799 * pause frames but not send pause frames). 2: Tx flow control is 3800 * enabled (we can send pause frames frames but we do not receive 3801 * pause frames). 3: Both Rx and TX flow control (symmetric) is 3802 * enabled. other: No other values should be possible at this point. 3803 */ 3804 3805 switch (hw->fc) { 3806 case E1000_FC_NONE: 3807 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 3808 break; 3809 case E1000_FC_RX_PAUSE: 3810 ctrl &= (~E1000_CTRL_TFCE); 3811 ctrl |= E1000_CTRL_RFCE; 3812 break; 3813 case E1000_FC_TX_PAUSE: 3814 ctrl &= (~E1000_CTRL_RFCE); 3815 ctrl |= E1000_CTRL_TFCE; 3816 break; 3817 case E1000_FC_FULL: 3818 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 3819 break; 3820 default: 3821 DEBUGOUT("Flow control param set incorrectly\n"); 3822 return -E1000_ERR_CONFIG; 3823 } 3824 3825 /* Disable TX Flow Control for 82542 (rev 2.0) */ 3826 if (hw->mac_type == em_82542_rev2_0) 3827 ctrl &= (~E1000_CTRL_TFCE); 3828 3829 E1000_WRITE_REG(hw, CTRL, ctrl); 3830 return E1000_SUCCESS; 3831 } 3832 /****************************************************************************** 3833 * Configures flow control settings after link is established 3834 * 3835 * hw - Struct containing variables accessed by shared code 3836 * 3837 * Should be called immediately after a valid link has been established. 3838 * Forces MAC flow control settings if link was forced. When in MII/GMII mode 3839 * and autonegotiation is enabled, the MAC flow control settings will be set 3840 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE 3841 * and RFCE bits will be automaticaly set to the negotiated flow control mode. 3842 *****************************************************************************/ 3843 STATIC int32_t 3844 em_config_fc_after_link_up(struct em_hw *hw) 3845 { 3846 int32_t ret_val; 3847 uint16_t mii_status_reg; 3848 uint16_t mii_nway_adv_reg; 3849 uint16_t mii_nway_lp_ability_reg; 3850 uint16_t speed; 3851 uint16_t duplex; 3852 DEBUGFUNC("em_config_fc_after_link_up"); 3853 /* 3854 * Check for the case where we have fiber media and auto-neg failed 3855 * so we had to force link. In this case, we need to force the 3856 * configuration of the MAC to match the "fc" parameter. 3857 */ 3858 if (((hw->media_type == em_media_type_fiber) && (hw->autoneg_failed)) 3859 || ((hw->media_type == em_media_type_internal_serdes) && 3860 (hw->autoneg_failed)) || 3861 ((hw->media_type == em_media_type_copper) && (!hw->autoneg)) || 3862 ((hw->media_type == em_media_type_oem) && (!hw->autoneg))) { 3863 ret_val = em_force_mac_fc(hw); 3864 if (ret_val) { 3865 DEBUGOUT("Error forcing flow control settings\n"); 3866 return ret_val; 3867 } 3868 } 3869 /* 3870 * Check for the case where we have copper media and auto-neg is 3871 * enabled. In this case, we need to check and see if Auto-Neg has 3872 * completed, and if so, how the PHY and link partner has flow 3873 * control configured. 3874 */ 3875 if ((hw->media_type == em_media_type_copper || 3876 (hw->media_type == em_media_type_oem)) && 3877 hw->autoneg) { 3878 /* 3879 * Read the MII Status Register and check to see if AutoNeg 3880 * has completed. We read this twice because this reg has 3881 * some "sticky" (latched) bits. 3882 */ 3883 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 3884 if (ret_val) 3885 return ret_val; 3886 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 3887 if (ret_val) 3888 return ret_val; 3889 3890 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) { 3891 /* 3892 * The AutoNeg process has completed, so we now need 3893 * to read both the Auto Negotiation Advertisement 3894 * Register (Address 4) and the Auto_Negotiation Base 3895 * Page Ability Register (Address 5) to determine how 3896 * flow control was negotiated. 3897 */ 3898 ret_val = em_read_phy_reg(hw, PHY_AUTONEG_ADV, 3899 &mii_nway_adv_reg); 3900 if (ret_val) 3901 return ret_val; 3902 ret_val = em_read_phy_reg(hw, PHY_LP_ABILITY, 3903 &mii_nway_lp_ability_reg); 3904 if (ret_val) 3905 return ret_val; 3906 /* 3907 * Two bits in the Auto Negotiation Advertisement 3908 * Register (Address 4) and two bits in the Auto 3909 * Negotiation Base Page Ability Register (Address 5) 3910 * determine flow control for both the PHY and the 3911 * link partner. The following table, taken out of 3912 * the IEEE 802.3ab/D6.0 dated March 25, 1999, 3913 * describes these PAUSE resolution bits and how flow 3914 * control is determined based upon these settings. 3915 * NOTE: DC = Don't Care 3916 * 3917 * LOCAL DEVICE | LINK PARTNER | 3918 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 3919 * -------|---------|-------|---------|--------------- 3920 * 0 | 0 | DC | DC | em_fc_none 3921 * 0 | 1 | 0 | DC | em_fc_none 3922 * 0 | 1 | 1 | 0 | em_fc_none 3923 * 0 | 1 | 1 | 1 | em_fc_tx_pause 3924 * 1 | 0 | 0 | DC | em_fc_none 3925 * 1 | DC | 1 | DC | em_fc_full 3926 * 1 | 1 | 0 | 0 | em_fc_none 3927 * 1 | 1 | 0 | 1 | em_fc_rx_pause 3928 * 3929 */ 3930 /* 3931 * Are both PAUSE bits set to 1? If so, this implies 3932 * Symmetric Flow Control is enabled at both ends. 3933 * The ASM_DIR bits are irrelevant per the spec. 3934 * 3935 * For Symmetric Flow Control: 3936 * 3937 * LOCAL DEVICE | LINK PARTNER 3938 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 3939 * -------|---------|-------|---------|--------------- 3940 * 1 | DC | 1 | DC | em_fc_full 3941 * 3942 */ 3943 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 3944 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 3945 /* 3946 * Now we need to check if the user selected 3947 * RX ONLY of pause frames. In this case, we 3948 * had to advertise FULL flow control because 3949 * we could not advertise RX ONLY. Hence, we 3950 * must now check to see if we need to turn 3951 * OFF the TRANSMISSION of PAUSE frames. 3952 */ 3953 if (hw->original_fc == E1000_FC_FULL) { 3954 hw->fc = E1000_FC_FULL; 3955 DEBUGOUT("Flow Control = FULL.\n"); 3956 } else { 3957 hw->fc = E1000_FC_RX_PAUSE; 3958 DEBUGOUT("Flow Control = RX PAUSE" 3959 " frames only.\n"); 3960 } 3961 } 3962 /* 3963 * For receiving PAUSE frames ONLY. 3964 * 3965 * LOCAL DEVICE | LINK PARTNER PAUSE | ASM_DIR | 3966 * PAUSE | ASM_DIR | Result 3967 * -------|---------|-------|---------|--------------- 3968 * ----- 0 | 1 | 1 | 1 | 3969 * em_fc_tx_pause 3970 * 3971 */ 3972 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 3973 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 3974 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 3975 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 3976 hw->fc = E1000_FC_TX_PAUSE; 3977 DEBUGOUT("Flow Control = TX PAUSE frames only." 3978 "\n"); 3979 } 3980 /* 3981 * For transmitting PAUSE frames ONLY. 3982 * 3983 * LOCAL DEVICE | LINK PARTNER 3984 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 3985 * -------|---------|-------|---------|--------------- 3986 * 1 | 1 | 0 | 1 | em_fc_rx_pause 3987 * 3988 */ 3989 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 3990 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 3991 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 3992 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 3993 hw->fc = E1000_FC_RX_PAUSE; 3994 DEBUGOUT("Flow Control = RX PAUSE frames only." 3995 "\n"); 3996 } 3997 /* 3998 * Per the IEEE spec, at this point flow control 3999 * should be disabled. However, we want to consider 4000 * that we could be connected to a legacy switch that 4001 * doesn't advertise desired flow control, but can be 4002 * forced on the link partner. So if we advertised 4003 * no flow control, that is what we will resolve to. 4004 * If we advertised some kind of receive capability 4005 * (Rx Pause Only or Full Flow Control) and the link 4006 * partner advertised none, we will configure 4007 * ourselves to enable Rx Flow Control only. We can 4008 * do this safely for two reasons: If the link 4009 * partner really didn't want flow control enabled, 4010 * and we enable Rx, no harm done since we won't be 4011 * receiving any PAUSE frames anyway. If the intent 4012 * on the link partner was to have flow control 4013 * enabled, then by us enabling RX only, we can at 4014 * least receive pause frames and process them. This 4015 * is a good idea because in most cases, since we are 4016 * predominantly a server NIC, more times than not we 4017 * will be asked to delay transmission of packets 4018 * than asking our link partner to pause transmission 4019 * of frames. 4020 */ 4021 else if ((hw->original_fc == E1000_FC_NONE || 4022 hw->original_fc == E1000_FC_TX_PAUSE) || 4023 hw->fc_strict_ieee) { 4024 hw->fc = E1000_FC_NONE; 4025 DEBUGOUT("Flow Control = NONE.\n"); 4026 } else { 4027 hw->fc = E1000_FC_RX_PAUSE; 4028 DEBUGOUT("Flow Control = RX PAUSE frames only." 4029 "\n"); 4030 } 4031 /* 4032 * Now we need to do one last check... If we auto- 4033 * negotiated to HALF DUPLEX, flow control should not 4034 * be enabled per IEEE 802.3 spec. 4035 */ 4036 ret_val = em_get_speed_and_duplex(hw, &speed, &duplex); 4037 if (ret_val) { 4038 DEBUGOUT("Error getting link speed and duplex" 4039 "\n"); 4040 return ret_val; 4041 } 4042 if (duplex == HALF_DUPLEX) 4043 hw->fc = E1000_FC_NONE; 4044 /* 4045 * Now we call a subroutine to actually force the MAC 4046 * controller to use the correct flow control 4047 * settings. 4048 */ 4049 ret_val = em_force_mac_fc(hw); 4050 if (ret_val) { 4051 DEBUGOUT("Error forcing flow control settings" 4052 "\n"); 4053 return ret_val; 4054 } 4055 } else { 4056 DEBUGOUT("Copper PHY and Auto Neg has not completed." 4057 "\n"); 4058 } 4059 } 4060 return E1000_SUCCESS; 4061 } 4062 /****************************************************************************** 4063 * Checks to see if the link status of the hardware has changed. 4064 * 4065 * hw - Struct containing variables accessed by shared code 4066 * 4067 * Called by any function that needs to check the link status of the adapter. 4068 *****************************************************************************/ 4069 int32_t 4070 em_check_for_link(struct em_hw *hw) 4071 { 4072 uint32_t rxcw = 0; 4073 uint32_t ctrl; 4074 uint32_t status; 4075 uint32_t rctl; 4076 uint32_t icr; 4077 uint32_t signal = 0; 4078 int32_t ret_val; 4079 uint16_t phy_data; 4080 DEBUGFUNC("em_check_for_link"); 4081 uint16_t speed, duplex; 4082 4083 if (hw->mac_type >= em_82575 && 4084 hw->media_type != em_media_type_copper) { 4085 ret_val = em_get_pcs_speed_and_duplex_82575(hw, &speed, 4086 &duplex); 4087 hw->get_link_status = hw->serdes_link_down; 4088 4089 return (ret_val); 4090 } 4091 4092 ctrl = E1000_READ_REG(hw, CTRL); 4093 status = E1000_READ_REG(hw, STATUS); 4094 /* 4095 * On adapters with a MAC newer than 82544, SW Defineable pin 1 will 4096 * be set when the optics detect a signal. On older adapters, it will 4097 * be cleared when there is a signal. This applies to fiber media 4098 * only. 4099 */ 4100 if ((hw->media_type == em_media_type_fiber) || 4101 (hw->media_type == em_media_type_internal_serdes)) { 4102 rxcw = E1000_READ_REG(hw, RXCW); 4103 4104 if (hw->media_type == em_media_type_fiber) { 4105 signal = (hw->mac_type > em_82544) ? 4106 E1000_CTRL_SWDPIN1 : 0; 4107 if (status & E1000_STATUS_LU) 4108 hw->get_link_status = FALSE; 4109 } 4110 } 4111 /* 4112 * If we have a copper PHY then we only want to go out to the PHY 4113 * registers to see if Auto-Neg has completed and/or if our link 4114 * status has changed. The get_link_status flag will be set if we 4115 * receive a Link Status Change interrupt or we have Rx Sequence 4116 * Errors. 4117 */ 4118 if ((hw->media_type == em_media_type_copper || 4119 (hw->media_type == em_media_type_oem)) && 4120 hw->get_link_status) { 4121 /* 4122 * First we want to see if the MII Status Register reports 4123 * link. If so, then we want to get the current speed/duplex 4124 * of the PHY. Read the register twice since the link bit is 4125 * sticky. 4126 */ 4127 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 4128 if (ret_val) 4129 return ret_val; 4130 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 4131 if (ret_val) 4132 return ret_val; 4133 4134 hw->icp_xxxx_is_link_up = (phy_data & MII_SR_LINK_STATUS) != 0; 4135 4136 if (hw->mac_type == em_pchlan) { 4137 ret_val = em_k1_gig_workaround_hv(hw, 4138 hw->icp_xxxx_is_link_up); 4139 if (ret_val) 4140 return ret_val; 4141 } 4142 4143 if (phy_data & MII_SR_LINK_STATUS) { 4144 hw->get_link_status = FALSE; 4145 4146 if (hw->phy_type == em_phy_82578) { 4147 ret_val = em_link_stall_workaround_hv(hw); 4148 if (ret_val) 4149 return ret_val; 4150 } 4151 4152 if (hw->mac_type == em_pch2lan) { 4153 ret_val = em_k1_workaround_lv(hw); 4154 if (ret_val) 4155 return ret_val; 4156 } 4157 /* Work-around I218 hang issue */ 4158 if ((hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) || 4159 (hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) || 4160 (hw->device_id == E1000_DEV_ID_PCH_I218_LM3) || 4161 (hw->device_id == E1000_DEV_ID_PCH_I218_V3)) { 4162 ret_val = em_k1_workaround_lpt_lp(hw, 4163 hw->icp_xxxx_is_link_up); 4164 if (ret_val) 4165 return ret_val; 4166 } 4167 4168 /* 4169 * Check if there was DownShift, must be checked 4170 * immediately after link-up 4171 */ 4172 em_check_downshift(hw); 4173 4174 /* Enable/Disable EEE after link up */ 4175 if (hw->mac_type == em_pch2lan || 4176 hw->mac_type == em_pch_lpt || 4177 hw->mac_type == em_pch_spt || 4178 hw->mac_type == em_pch_cnp) { 4179 ret_val = em_set_eee_pchlan(hw); 4180 if (ret_val) 4181 return ret_val; 4182 } 4183 4184 /* 4185 * If we are on 82544 or 82543 silicon and 4186 * speed/duplex are forced to 10H or 10F, then we 4187 * will implement the polarity reversal workaround. 4188 * We disable interrupts first, and upon returning, 4189 * place the devices interrupt state to its previous 4190 * value except for the link status change interrupt 4191 * which will happen due to the execution of this 4192 * workaround. 4193 */ 4194 if ((hw->mac_type == em_82544 || 4195 hw->mac_type == em_82543) && (!hw->autoneg) && 4196 (hw->forced_speed_duplex == em_10_full || 4197 hw->forced_speed_duplex == em_10_half)) { 4198 E1000_WRITE_REG(hw, IMC, 0xffffffff); 4199 ret_val = em_polarity_reversal_workaround(hw); 4200 icr = E1000_READ_REG(hw, ICR); 4201 E1000_WRITE_REG(hw, ICS, 4202 (icr & ~E1000_ICS_LSC)); 4203 E1000_WRITE_REG(hw, IMS, IMS_ENABLE_MASK); 4204 } 4205 } else { 4206 /* No link detected */ 4207 em_config_dsp_after_link_change(hw, FALSE); 4208 return 0; 4209 } 4210 /* 4211 * If we are forcing speed/duplex, then we simply return 4212 * since we have already determined whether we have link or 4213 * not. 4214 */ 4215 if (!hw->autoneg) 4216 return -E1000_ERR_CONFIG; 4217 4218 /* optimize the dsp settings for the igp phy */ 4219 em_config_dsp_after_link_change(hw, TRUE); 4220 /* 4221 * We have a M88E1000 PHY and Auto-Neg is enabled. If we 4222 * have Si on board that is 82544 or newer, Auto Speed 4223 * Detection takes care of MAC speed/duplex configuration. 4224 * So we only need to configure Collision Distance in the 4225 * MAC. Otherwise, we need to force speed/duplex on the MAC 4226 * to the current PHY speed/duplex settings. 4227 */ 4228 if (hw->mac_type >= em_82544 && hw->mac_type != em_icp_xxxx) { 4229 em_config_collision_dist(hw); 4230 } else { 4231 ret_val = em_config_mac_to_phy(hw); 4232 if (ret_val) { 4233 DEBUGOUT("Error configuring MAC to PHY" 4234 " settings\n"); 4235 return ret_val; 4236 } 4237 } 4238 /* 4239 * Configure Flow Control now that Auto-Neg has completed. 4240 * First, we need to restore the desired flow control 4241 * settings because we may have had to re-autoneg with a 4242 * different link partner. 4243 */ 4244 ret_val = em_config_fc_after_link_up(hw); 4245 if (ret_val) { 4246 DEBUGOUT("Error configuring flow control\n"); 4247 return ret_val; 4248 } 4249 /* 4250 * At this point we know that we are on copper and we have 4251 * auto-negotiated link. These are conditions for checking 4252 * the link partner capability register. We use the link 4253 * speed to determine if TBI compatibility needs to be turned 4254 * on or off. If the link is not at gigabit speed, then TBI 4255 * compatibility is not needed. If we are at gigabit speed, 4256 * we turn on TBI compatibility. 4257 */ 4258 if (hw->tbi_compatibility_en) { 4259 uint16_t speed, duplex; 4260 ret_val = em_get_speed_and_duplex(hw, &speed, &duplex); 4261 if (ret_val) { 4262 DEBUGOUT("Error getting link speed and duplex" 4263 "\n"); 4264 return ret_val; 4265 } 4266 if (speed != SPEED_1000) { 4267 /* 4268 * If link speed is not set to gigabit speed, 4269 * we do not need to enable TBI 4270 * compatibility. 4271 */ 4272 if (hw->tbi_compatibility_on) { 4273 /* 4274 * If we previously were in the mode, 4275 * turn it off. 4276 */ 4277 rctl = E1000_READ_REG(hw, RCTL); 4278 rctl &= ~E1000_RCTL_SBP; 4279 E1000_WRITE_REG(hw, RCTL, rctl); 4280 hw->tbi_compatibility_on = FALSE; 4281 } 4282 } else { 4283 /* 4284 * If TBI compatibility is was previously 4285 * off, turn it on. For compatibility with a 4286 * TBI link partner, we will store bad 4287 * packets. Some frames have an additional 4288 * byte on the end and will look like CRC 4289 * errors to to the hardware. 4290 */ 4291 if (!hw->tbi_compatibility_on) { 4292 hw->tbi_compatibility_on = TRUE; 4293 rctl = E1000_READ_REG(hw, RCTL); 4294 rctl |= E1000_RCTL_SBP; 4295 E1000_WRITE_REG(hw, RCTL, rctl); 4296 } 4297 } 4298 } 4299 } 4300 /* 4301 * If we don't have link (auto-negotiation failed or link partner 4302 * cannot auto-negotiate), the cable is plugged in (we have signal), 4303 * and our link partner is not trying to auto-negotiate with us (we 4304 * are receiving idles or data), we need to force link up. We also 4305 * need to give auto-negotiation time to complete, in case the cable 4306 * was just plugged in. The autoneg_failed flag does this. 4307 */ 4308 else if ((((hw->media_type == em_media_type_fiber) && 4309 ((ctrl & E1000_CTRL_SWDPIN1) == signal)) || 4310 (hw->media_type == em_media_type_internal_serdes)) && 4311 (!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) { 4312 if (hw->autoneg_failed == 0) { 4313 hw->autoneg_failed = 1; 4314 return 0; 4315 } 4316 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 4317 4318 /* Disable auto-negotiation in the TXCW register */ 4319 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE)); 4320 4321 /* Force link-up and also force full-duplex. */ 4322 ctrl = E1000_READ_REG(hw, CTRL); 4323 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 4324 E1000_WRITE_REG(hw, CTRL, ctrl); 4325 4326 /* Configure Flow Control after forcing link up. */ 4327 ret_val = em_config_fc_after_link_up(hw); 4328 if (ret_val) { 4329 DEBUGOUT("Error configuring flow control\n"); 4330 return ret_val; 4331 } 4332 } 4333 /* 4334 * If we are forcing link and we are receiving /C/ ordered sets, 4335 * re-enable auto-negotiation in the TXCW register and disable forced 4336 * link in the Device Control register in an attempt to 4337 * auto-negotiate with our link partner. 4338 */ 4339 else if (((hw->media_type == em_media_type_fiber) || 4340 (hw->media_type == em_media_type_internal_serdes)) && 4341 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 4342 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 4343 E1000_WRITE_REG(hw, TXCW, hw->txcw); 4344 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU)); 4345 4346 hw->serdes_link_down = FALSE; 4347 } 4348 /* 4349 * If we force link for non-auto-negotiation switch, check link 4350 * status based on MAC synchronization for internal serdes media 4351 * type. 4352 */ 4353 else if ((hw->media_type == em_media_type_internal_serdes) && 4354 !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) { 4355 /* SYNCH bit and IV bit are sticky. */ 4356 usec_delay(10); 4357 if (E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) { 4358 if (!(rxcw & E1000_RXCW_IV)) { 4359 hw->serdes_link_down = FALSE; 4360 DEBUGOUT("SERDES: Link is up.\n"); 4361 } 4362 } else { 4363 hw->serdes_link_down = TRUE; 4364 DEBUGOUT("SERDES: Link is down.\n"); 4365 } 4366 } 4367 if ((hw->media_type == em_media_type_internal_serdes) && 4368 (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) { 4369 hw->serdes_link_down = !(E1000_STATUS_LU & 4370 E1000_READ_REG(hw, STATUS)); 4371 } 4372 return E1000_SUCCESS; 4373 } 4374 4375 int32_t 4376 em_get_pcs_speed_and_duplex_82575(struct em_hw *hw, uint16_t *speed, 4377 uint16_t *duplex) 4378 { 4379 uint32_t pcs; 4380 4381 hw->serdes_link_down = TRUE; 4382 *speed = 0; 4383 *duplex = 0; 4384 4385 /* 4386 * Read the PCS Status register for link state. For non-copper mode, 4387 * the status register is not accurate. The PCS status register is 4388 * used instead. 4389 */ 4390 pcs = E1000_READ_REG(hw, PCS_LSTAT); 4391 4392 /* 4393 * The link up bit determines when link is up on autoneg. The sync ok 4394 * gets set once both sides sync up and agree upon link. Stable link 4395 * can be determined by checking for both link up and link sync ok 4396 */ 4397 if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) { 4398 hw->serdes_link_down = FALSE; 4399 4400 /* Detect and store PCS speed */ 4401 if (pcs & E1000_PCS_LSTS_SPEED_1000) { 4402 *speed = SPEED_1000; 4403 } else if (pcs & E1000_PCS_LSTS_SPEED_100) { 4404 *speed = SPEED_100; 4405 } else { 4406 *speed = SPEED_10; 4407 } 4408 4409 /* Detect and store PCS duplex */ 4410 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) { 4411 *duplex = FULL_DUPLEX; 4412 } else { 4413 *duplex = HALF_DUPLEX; 4414 } 4415 } 4416 4417 return (0); 4418 } 4419 4420 4421 /****************************************************************************** 4422 * Detects the current speed and duplex settings of the hardware. 4423 * 4424 * hw - Struct containing variables accessed by shared code 4425 * speed - Speed of the connection 4426 * duplex - Duplex setting of the connection 4427 *****************************************************************************/ 4428 int32_t 4429 em_get_speed_and_duplex(struct em_hw *hw, uint16_t *speed, uint16_t *duplex) 4430 { 4431 uint32_t status; 4432 int32_t ret_val; 4433 uint16_t phy_data; 4434 DEBUGFUNC("em_get_speed_and_duplex"); 4435 4436 if (hw->mac_type >= em_82575 && hw->media_type != em_media_type_copper) 4437 return em_get_pcs_speed_and_duplex_82575(hw, speed, duplex); 4438 4439 if (hw->mac_type >= em_82543) { 4440 status = E1000_READ_REG(hw, STATUS); 4441 if (status & E1000_STATUS_SPEED_1000) { 4442 *speed = SPEED_1000; 4443 DEBUGOUT("1000 Mbs, "); 4444 } else if (status & E1000_STATUS_SPEED_100) { 4445 *speed = SPEED_100; 4446 DEBUGOUT("100 Mbs, "); 4447 } else { 4448 *speed = SPEED_10; 4449 DEBUGOUT("10 Mbs, "); 4450 } 4451 4452 if (status & E1000_STATUS_FD) { 4453 *duplex = FULL_DUPLEX; 4454 DEBUGOUT("Full Duplex\n"); 4455 } else { 4456 *duplex = HALF_DUPLEX; 4457 DEBUGOUT(" Half Duplex\n"); 4458 } 4459 } else { 4460 DEBUGOUT("1000 Mbs, Full Duplex\n"); 4461 *speed = SPEED_1000; 4462 *duplex = FULL_DUPLEX; 4463 } 4464 /* 4465 * IGP01 PHY may advertise full duplex operation after speed 4466 * downgrade even if it is operating at half duplex. Here we set the 4467 * duplex settings to match the duplex in the link partner's 4468 * capabilities. 4469 */ 4470 if (hw->phy_type == em_phy_igp && hw->speed_downgraded) { 4471 ret_val = em_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data); 4472 if (ret_val) 4473 return ret_val; 4474 4475 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS)) 4476 *duplex = HALF_DUPLEX; 4477 else { 4478 ret_val = em_read_phy_reg(hw, PHY_LP_ABILITY, 4479 &phy_data); 4480 if (ret_val) 4481 return ret_val; 4482 if ((*speed == SPEED_100 && 4483 !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) || 4484 (*speed == SPEED_10 && 4485 !(phy_data & NWAY_LPAR_10T_FD_CAPS))) 4486 *duplex = HALF_DUPLEX; 4487 } 4488 } 4489 if ((hw->mac_type == em_80003es2lan) && 4490 (hw->media_type == em_media_type_copper)) { 4491 if (*speed == SPEED_1000) 4492 ret_val = em_configure_kmrn_for_1000(hw); 4493 else 4494 ret_val = em_configure_kmrn_for_10_100(hw, *duplex); 4495 if (ret_val) 4496 return ret_val; 4497 } 4498 if ((hw->mac_type == em_ich8lan) && 4499 (hw->phy_type == em_phy_igp_3) && 4500 (*speed == SPEED_1000)) { 4501 ret_val = em_kumeran_lock_loss_workaround(hw); 4502 if (ret_val) 4503 return ret_val; 4504 } 4505 return E1000_SUCCESS; 4506 } 4507 4508 /****************************************************************************** 4509 * Blocks until autoneg completes or times out (~4.5 seconds) 4510 * 4511 * hw - Struct containing variables accessed by shared code 4512 *****************************************************************************/ 4513 STATIC int32_t 4514 em_wait_autoneg(struct em_hw *hw) 4515 { 4516 int32_t ret_val; 4517 uint16_t i; 4518 uint16_t phy_data; 4519 DEBUGFUNC("em_wait_autoneg"); 4520 DEBUGOUT("Waiting for Auto-Neg to complete.\n"); 4521 4522 /* We will wait for autoneg to complete or 4.5 seconds to expire. */ 4523 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) { 4524 /* 4525 * Read the MII Status Register and wait for Auto-Neg 4526 * Complete bit to be set. 4527 */ 4528 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 4529 if (ret_val) 4530 return ret_val; 4531 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 4532 if (ret_val) 4533 return ret_val; 4534 if (phy_data & MII_SR_AUTONEG_COMPLETE) { 4535 return E1000_SUCCESS; 4536 } 4537 msec_delay(100); 4538 } 4539 return E1000_SUCCESS; 4540 } 4541 4542 /****************************************************************************** 4543 * Raises the Management Data Clock 4544 * 4545 * hw - Struct containing variables accessed by shared code 4546 * ctrl - Device control register's current value 4547 *****************************************************************************/ 4548 static void 4549 em_raise_mdi_clk(struct em_hw *hw, uint32_t *ctrl) 4550 { 4551 /* 4552 * Raise the clock input to the Management Data Clock (by setting the 4553 * MDC bit), and then delay 10 microseconds. 4554 */ 4555 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC)); 4556 E1000_WRITE_FLUSH(hw); 4557 usec_delay(10); 4558 } 4559 4560 /****************************************************************************** 4561 * Lowers the Management Data Clock 4562 * 4563 * hw - Struct containing variables accessed by shared code 4564 * ctrl - Device control register's current value 4565 *****************************************************************************/ 4566 static void 4567 em_lower_mdi_clk(struct em_hw *hw, uint32_t *ctrl) 4568 { 4569 /* 4570 * Lower the clock input to the Management Data Clock (by clearing 4571 * the MDC bit), and then delay 10 microseconds. 4572 */ 4573 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC)); 4574 E1000_WRITE_FLUSH(hw); 4575 usec_delay(10); 4576 } 4577 4578 /****************************************************************************** 4579 * Shifts data bits out to the PHY 4580 * 4581 * hw - Struct containing variables accessed by shared code 4582 * data - Data to send out to the PHY 4583 * count - Number of bits to shift out 4584 * 4585 * Bits are shifted out in MSB to LSB order. 4586 *****************************************************************************/ 4587 static void 4588 em_shift_out_mdi_bits(struct em_hw *hw, uint32_t data, uint16_t count) 4589 { 4590 uint32_t ctrl; 4591 uint32_t mask; 4592 /* 4593 * We need to shift "count" number of bits out to the PHY. So, the 4594 * value in the "data" parameter will be shifted out to the PHY one 4595 * bit at a time. In order to do this, "data" must be broken down 4596 * into bits. 4597 */ 4598 mask = 0x01; 4599 mask <<= (count - 1); 4600 4601 ctrl = E1000_READ_REG(hw, CTRL); 4602 4603 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output 4604 * pins. 4605 */ 4606 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); 4607 4608 while (mask) { 4609 /* 4610 * A "1" is shifted out to the PHY by setting the MDIO bit to 4611 * "1" and then raising and lowering the Management Data 4612 * Clock. A "0" is shifted out to the PHY by setting the MDIO 4613 * bit to "0" and then raising and lowering the clock. 4614 */ 4615 if (data & mask) 4616 ctrl |= E1000_CTRL_MDIO; 4617 else 4618 ctrl &= ~E1000_CTRL_MDIO; 4619 4620 E1000_WRITE_REG(hw, CTRL, ctrl); 4621 E1000_WRITE_FLUSH(hw); 4622 4623 usec_delay(10); 4624 4625 em_raise_mdi_clk(hw, &ctrl); 4626 em_lower_mdi_clk(hw, &ctrl); 4627 4628 mask = mask >> 1; 4629 } 4630 } 4631 4632 /****************************************************************************** 4633 * Shifts data bits in from the PHY 4634 * 4635 * hw - Struct containing variables accessed by shared code 4636 * 4637 * Bits are shifted in in MSB to LSB order. 4638 *****************************************************************************/ 4639 static uint16_t 4640 em_shift_in_mdi_bits(struct em_hw *hw) 4641 { 4642 uint32_t ctrl; 4643 uint16_t data = 0; 4644 uint8_t i; 4645 /* 4646 * In order to read a register from the PHY, we need to shift in a 4647 * total of 18 bits from the PHY. The first two bit (turnaround) 4648 * times are used to avoid contention on the MDIO pin when a read 4649 * operation is performed. These two bits are ignored by us and 4650 * thrown away. Bits are "shifted in" by raising the input to the 4651 * Management Data Clock (setting the MDC bit), and then reading the 4652 * value of the MDIO bit. 4653 */ 4654 ctrl = E1000_READ_REG(hw, CTRL); 4655 /* 4656 * Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as 4657 * input. 4658 */ 4659 ctrl &= ~E1000_CTRL_MDIO_DIR; 4660 ctrl &= ~E1000_CTRL_MDIO; 4661 4662 E1000_WRITE_REG(hw, CTRL, ctrl); 4663 E1000_WRITE_FLUSH(hw); 4664 /* 4665 * Raise and Lower the clock before reading in the data. This 4666 * accounts for the turnaround bits. The first clock occurred when we 4667 * clocked out the last bit of the Register Address. 4668 */ 4669 em_raise_mdi_clk(hw, &ctrl); 4670 em_lower_mdi_clk(hw, &ctrl); 4671 4672 for (data = 0, i = 0; i < 16; i++) { 4673 data = data << 1; 4674 em_raise_mdi_clk(hw, &ctrl); 4675 ctrl = E1000_READ_REG(hw, CTRL); 4676 /* Check to see if we shifted in a "1". */ 4677 if (ctrl & E1000_CTRL_MDIO) 4678 data |= 1; 4679 em_lower_mdi_clk(hw, &ctrl); 4680 } 4681 4682 em_raise_mdi_clk(hw, &ctrl); 4683 em_lower_mdi_clk(hw, &ctrl); 4684 4685 return data; 4686 } 4687 4688 STATIC int32_t 4689 em_swfw_sync_acquire(struct em_hw *hw, uint16_t mask) 4690 { 4691 uint32_t swfw_sync = 0; 4692 uint32_t swmask = mask; 4693 uint32_t fwmask = mask << 16; 4694 int32_t timeout = 200; 4695 DEBUGFUNC("em_swfw_sync_acquire"); 4696 4697 if (hw->swfwhw_semaphore_present) 4698 return em_get_software_flag(hw); 4699 4700 if (!hw->swfw_sync_present) 4701 return em_get_hw_eeprom_semaphore(hw); 4702 4703 while (timeout) { 4704 if (em_get_hw_eeprom_semaphore(hw)) 4705 return -E1000_ERR_SWFW_SYNC; 4706 4707 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); 4708 if (!(swfw_sync & (fwmask | swmask))) { 4709 break; 4710 } 4711 /* 4712 * firmware currently using resource (fwmask) 4713 * or other software thread currently using resource (swmask) 4714 */ 4715 em_put_hw_eeprom_semaphore(hw); 4716 msec_delay_irq(5); 4717 timeout--; 4718 } 4719 4720 if (!timeout) { 4721 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout." 4722 "\n"); 4723 return -E1000_ERR_SWFW_SYNC; 4724 } 4725 swfw_sync |= swmask; 4726 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync); 4727 4728 em_put_hw_eeprom_semaphore(hw); 4729 return E1000_SUCCESS; 4730 } 4731 4732 STATIC void 4733 em_swfw_sync_release(struct em_hw *hw, uint16_t mask) 4734 { 4735 uint32_t swfw_sync; 4736 uint32_t swmask = mask; 4737 DEBUGFUNC("em_swfw_sync_release"); 4738 4739 if (hw->swfwhw_semaphore_present) { 4740 em_release_software_flag(hw); 4741 return; 4742 } 4743 if (!hw->swfw_sync_present) { 4744 em_put_hw_eeprom_semaphore(hw); 4745 return; 4746 } 4747 /* 4748 * if (em_get_hw_eeprom_semaphore(hw)) return -E1000_ERR_SWFW_SYNC; 4749 */ 4750 while (em_get_hw_eeprom_semaphore(hw) != E1000_SUCCESS); 4751 /* empty */ 4752 4753 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); 4754 swfw_sync &= ~swmask; 4755 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync); 4756 4757 em_put_hw_eeprom_semaphore(hw); 4758 } 4759 4760 /**************************************************************************** 4761 * Read BM PHY wakeup register. It works as such: 4762 * 1) Set page 769, register 17, bit 2 = 1 4763 * 2) Set page to 800 for host (801 if we were manageability) 4764 * 3) Write the address using the address opcode (0x11) 4765 * 4) Read or write the data using the data opcode (0x12) 4766 * 5) Restore 769_17.2 to its original value 4767 ****************************************************************************/ 4768 int32_t 4769 em_access_phy_wakeup_reg_bm(struct em_hw *hw, uint32_t reg_addr, 4770 uint16_t *phy_data, boolean_t read) 4771 { 4772 int32_t ret_val; 4773 uint16_t reg = BM_PHY_REG_NUM(reg_addr); 4774 uint16_t phy_reg = 0; 4775 4776 /* All operations in this function are phy address 1 */ 4777 hw->phy_addr = 1; 4778 4779 /* Set page 769 */ 4780 em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 4781 (BM_WUC_ENABLE_PAGE << PHY_PAGE_SHIFT)); 4782 4783 ret_val = em_read_phy_reg_ex(hw, BM_WUC_ENABLE_REG, &phy_reg); 4784 if (ret_val) 4785 goto out; 4786 4787 /* First clear bit 4 to avoid a power state change */ 4788 phy_reg &= ~(BM_WUC_HOST_WU_BIT); 4789 ret_val = em_write_phy_reg_ex(hw, BM_WUC_ENABLE_REG, phy_reg); 4790 if (ret_val) 4791 goto out; 4792 4793 /* Write bit 2 = 1, and clear bit 4 to 769_17 */ 4794 ret_val = em_write_phy_reg_ex(hw, BM_WUC_ENABLE_REG, 4795 phy_reg | BM_WUC_ENABLE_BIT); 4796 if (ret_val) 4797 goto out; 4798 4799 /* Select page 800 */ 4800 ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 4801 (BM_WUC_PAGE << PHY_PAGE_SHIFT)); 4802 4803 /* Write the page 800 offset value using opcode 0x11 */ 4804 ret_val = em_write_phy_reg_ex(hw, BM_WUC_ADDRESS_OPCODE, reg); 4805 if (ret_val) 4806 goto out; 4807 4808 if (read) 4809 /* Read the page 800 value using opcode 0x12 */ 4810 ret_val = em_read_phy_reg_ex(hw, BM_WUC_DATA_OPCODE, 4811 phy_data); 4812 else 4813 /* Write the page 800 value using opcode 0x12 */ 4814 ret_val = em_write_phy_reg_ex(hw, BM_WUC_DATA_OPCODE, 4815 *phy_data); 4816 4817 if (ret_val) 4818 goto out; 4819 4820 /* 4821 * Restore 769_17.2 to its original value 4822 * Set page 769 4823 */ 4824 em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 4825 (BM_WUC_ENABLE_PAGE << PHY_PAGE_SHIFT)); 4826 4827 /* Clear 769_17.2 */ 4828 ret_val = em_write_phy_reg_ex(hw, BM_WUC_ENABLE_REG, phy_reg); 4829 if (ret_val) 4830 goto out; 4831 4832 out: 4833 return ret_val; 4834 } 4835 4836 /*************************************************************************** 4837 * Read HV PHY vendor specific high registers 4838 ***************************************************************************/ 4839 int32_t 4840 em_access_phy_debug_regs_hv(struct em_hw *hw, uint32_t reg_addr, 4841 uint16_t *phy_data, boolean_t read) 4842 { 4843 int32_t ret_val; 4844 uint32_t addr_reg = 0; 4845 uint32_t data_reg = 0; 4846 4847 /* This takes care of the difference with desktop vs mobile phy */ 4848 addr_reg = (hw->phy_type == em_phy_82578) ? 4849 I82578_PHY_ADDR_REG : I82577_PHY_ADDR_REG; 4850 data_reg = addr_reg + 1; 4851 4852 /* All operations in this function are phy address 2 */ 4853 hw->phy_addr = 2; 4854 4855 /* masking with 0x3F to remove the page from offset */ 4856 ret_val = em_write_phy_reg_ex(hw, addr_reg, (uint16_t)reg_addr & 0x3F); 4857 if (ret_val) { 4858 printf("Could not write PHY the HV address register\n"); 4859 goto out; 4860 } 4861 4862 /* Read or write the data value next */ 4863 if (read) 4864 ret_val = em_read_phy_reg_ex(hw, data_reg, phy_data); 4865 else 4866 ret_val = em_write_phy_reg_ex(hw, data_reg, *phy_data); 4867 4868 if (ret_val) { 4869 printf("Could not read data value from HV data register\n"); 4870 goto out; 4871 } 4872 4873 out: 4874 return ret_val; 4875 } 4876 4877 /****************************************************************************** 4878 * Reads or writes the value from a PHY register, if the value is on a specific 4879 * non zero page, sets the page first. 4880 * hw - Struct containing variables accessed by shared code 4881 * reg_addr - address of the PHY register to read 4882 *****************************************************************************/ 4883 int32_t 4884 em_access_phy_reg_hv(struct em_hw *hw, uint32_t reg_addr, uint16_t *phy_data, 4885 boolean_t read) 4886 { 4887 uint32_t ret_val; 4888 uint16_t swfw; 4889 uint16_t page = BM_PHY_REG_PAGE(reg_addr); 4890 uint16_t reg = BM_PHY_REG_NUM(reg_addr); 4891 4892 DEBUGFUNC("em_access_phy_reg_hv"); 4893 4894 swfw = E1000_SWFW_PHY0_SM; 4895 4896 if (em_swfw_sync_acquire(hw, swfw)) 4897 return -E1000_ERR_SWFW_SYNC; 4898 4899 if (page == BM_WUC_PAGE) { 4900 ret_val = em_access_phy_wakeup_reg_bm(hw, reg_addr, 4901 phy_data, read); 4902 goto release; 4903 } 4904 4905 if (page >= HV_INTC_FC_PAGE_START) 4906 hw->phy_addr = 1; 4907 else 4908 hw->phy_addr = 2; 4909 4910 if (page == HV_INTC_FC_PAGE_START) 4911 page = 0; 4912 4913 /* 4914 * Workaround MDIO accesses being disabled after entering IEEE Power 4915 * Down (whenever bit 11 of the PHY Control register is set) 4916 */ 4917 if (!read && 4918 (hw->phy_type == em_phy_82578) && 4919 (hw->phy_revision >= 1) && 4920 (hw->phy_addr == 2) && 4921 ((MAX_PHY_REG_ADDRESS & reg) == 0) && 4922 (*phy_data & (1 << 11))) { 4923 uint16_t data2 = 0x7EFF; 4924 4925 ret_val = em_access_phy_debug_regs_hv(hw, (1 << 6) | 0x3, 4926 &data2, FALSE); 4927 if (ret_val) 4928 return ret_val; 4929 } 4930 4931 if (reg_addr > MAX_PHY_MULTI_PAGE_REG) { 4932 ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 4933 (page << PHY_PAGE_SHIFT)); 4934 if (ret_val) 4935 return ret_val; 4936 } 4937 if (read) 4938 ret_val = em_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg, 4939 phy_data); 4940 else 4941 ret_val = em_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg, 4942 *phy_data); 4943 release: 4944 em_swfw_sync_release(hw, swfw); 4945 return ret_val; 4946 } 4947 4948 /****************************************************************************** 4949 * Reads the value from a PHY register, if the value is on a specific non zero 4950 * page, sets the page first. 4951 * hw - Struct containing variables accessed by shared code 4952 * reg_addr - address of the PHY register to read 4953 *****************************************************************************/ 4954 int32_t 4955 em_read_phy_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t *phy_data) 4956 { 4957 uint32_t ret_val; 4958 uint16_t swfw; 4959 DEBUGFUNC("em_read_phy_reg"); 4960 4961 if (hw->mac_type == em_pchlan || 4962 hw->mac_type == em_pch2lan || 4963 hw->mac_type == em_pch_lpt || 4964 hw->mac_type == em_pch_spt || 4965 hw->mac_type == em_pch_cnp) 4966 return (em_access_phy_reg_hv(hw, reg_addr, phy_data, TRUE)); 4967 4968 if (((hw->mac_type == em_80003es2lan) || (hw->mac_type == em_82575) || 4969 (hw->mac_type == em_82576)) && 4970 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { 4971 swfw = E1000_SWFW_PHY1_SM; 4972 } else { 4973 swfw = E1000_SWFW_PHY0_SM; 4974 } 4975 if (em_swfw_sync_acquire(hw, swfw)) 4976 return -E1000_ERR_SWFW_SYNC; 4977 4978 if ((hw->phy_type == em_phy_igp || 4979 hw->phy_type == em_phy_igp_3 || 4980 hw->phy_type == em_phy_igp_2) && 4981 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { 4982 ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 4983 (uint16_t) reg_addr); 4984 if (ret_val) { 4985 em_swfw_sync_release(hw, swfw); 4986 return ret_val; 4987 } 4988 } else if (hw->phy_type == em_phy_gg82563) { 4989 if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) || 4990 (hw->mac_type == em_80003es2lan)) { 4991 /* Select Configuration Page */ 4992 if ((reg_addr & MAX_PHY_REG_ADDRESS) < 4993 GG82563_MIN_ALT_REG) { 4994 ret_val = em_write_phy_reg_ex(hw, 4995 GG82563_PHY_PAGE_SELECT, 4996 (uint16_t) ((uint16_t) reg_addr >> 4997 GG82563_PAGE_SHIFT)); 4998 } else { 4999 /* 5000 * Use Alternative Page Select register to 5001 * access registers 30 and 31 5002 */ 5003 ret_val = em_write_phy_reg_ex(hw, 5004 GG82563_PHY_PAGE_SELECT_ALT, 5005 (uint16_t) ((uint16_t) reg_addr >> 5006 GG82563_PAGE_SHIFT)); 5007 } 5008 5009 if (ret_val) { 5010 em_swfw_sync_release(hw, swfw); 5011 return ret_val; 5012 } 5013 } 5014 } else if ((hw->phy_type == em_phy_bm) && (hw->phy_revision == 1)) { 5015 if (reg_addr > MAX_PHY_MULTI_PAGE_REG) { 5016 ret_val = em_write_phy_reg_ex(hw, BM_PHY_PAGE_SELECT, 5017 (uint16_t) ((uint16_t) reg_addr >> 5018 PHY_PAGE_SHIFT)); 5019 if (ret_val) 5020 return ret_val; 5021 } 5022 } 5023 ret_val = em_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, 5024 phy_data); 5025 5026 em_swfw_sync_release(hw, swfw); 5027 return ret_val; 5028 } 5029 5030 STATIC int32_t 5031 em_read_phy_reg_ex(struct em_hw *hw, uint32_t reg_addr, uint16_t *phy_data) 5032 { 5033 uint32_t i; 5034 uint32_t mdic = 0; 5035 DEBUGFUNC("em_read_phy_reg_ex"); 5036 5037 if (reg_addr > MAX_PHY_REG_ADDRESS) { 5038 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); 5039 return -E1000_ERR_PARAM; 5040 } 5041 if (hw->mac_type == em_icp_xxxx) { 5042 *phy_data = gcu_miibus_readreg(hw, hw->icp_xxxx_port_num, 5043 reg_addr); 5044 return E1000_SUCCESS; 5045 } 5046 if (hw->mac_type > em_82543) { 5047 /* 5048 * Set up Op-code, Phy Address, and register address in the 5049 * MDI Control register. The MAC will take care of 5050 * interfacing with the PHY to retrieve the desired data. 5051 */ 5052 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) | 5053 (hw->phy_addr << E1000_MDIC_PHY_SHIFT) | 5054 (E1000_MDIC_OP_READ)); 5055 5056 E1000_WRITE_REG(hw, MDIC, mdic); 5057 5058 /* 5059 * Poll the ready bit to see if the MDI read completed 5060 * Increasing the time out as testing showed failures with 5061 * the lower time out (from FreeBSD driver) 5062 */ 5063 for (i = 0; i < 1960; i++) { 5064 usec_delay(50); 5065 mdic = E1000_READ_REG(hw, MDIC); 5066 if (mdic & E1000_MDIC_READY) 5067 break; 5068 } 5069 if (!(mdic & E1000_MDIC_READY)) { 5070 DEBUGOUT("MDI Read did not complete\n"); 5071 return -E1000_ERR_PHY; 5072 } 5073 if (mdic & E1000_MDIC_ERROR) { 5074 DEBUGOUT("MDI Error\n"); 5075 return -E1000_ERR_PHY; 5076 } 5077 *phy_data = (uint16_t) mdic; 5078 5079 if (hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt || 5080 hw->mac_type == em_pch_spt || hw->mac_type == em_pch_cnp) 5081 usec_delay(100); 5082 } else { 5083 /* 5084 * We must first send a preamble through the MDIO pin to 5085 * signal the beginning of an MII instruction. This is done 5086 * by sending 32 consecutive "1" bits. 5087 */ 5088 em_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 5089 /* 5090 * Now combine the next few fields that are required for a 5091 * read operation. We use this method instead of calling the 5092 * em_shift_out_mdi_bits routine five different times. The 5093 * format of a MII read instruction consists of a shift out 5094 * of 14 bits and is defined as follows: <Preamble><SOF><Op 5095 * Code><Phy Addr><Reg Addr> followed by a shift in of 18 5096 * bits. This first two bits shifted in are TurnAround bits 5097 * used to avoid contention on the MDIO pin when a READ 5098 * operation is performed. These two bits are thrown away 5099 * followed by a shift in of 16 bits which contains the 5100 * desired data. 5101 */ 5102 mdic = ((reg_addr) | (hw->phy_addr << 5) | 5103 (PHY_OP_READ << 10) | (PHY_SOF << 12)); 5104 5105 em_shift_out_mdi_bits(hw, mdic, 14); 5106 /* 5107 * Now that we've shifted out the read command to the MII, we 5108 * need to "shift in" the 16-bit value (18 total bits) of the 5109 * requested PHY register address. 5110 */ 5111 *phy_data = em_shift_in_mdi_bits(hw); 5112 } 5113 return E1000_SUCCESS; 5114 } 5115 5116 /****************************************************************************** 5117 * Writes a value to a PHY register 5118 * 5119 * hw - Struct containing variables accessed by shared code 5120 * reg_addr - address of the PHY register to write 5121 * data - data to write to the PHY 5122 *****************************************************************************/ 5123 int32_t 5124 em_write_phy_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t phy_data) 5125 { 5126 uint32_t ret_val; 5127 DEBUGFUNC("em_write_phy_reg"); 5128 5129 if (hw->mac_type == em_pchlan || 5130 hw->mac_type == em_pch2lan || 5131 hw->mac_type == em_pch_lpt || 5132 hw->mac_type == em_pch_spt || 5133 hw->mac_type == em_pch_cnp) 5134 return (em_access_phy_reg_hv(hw, reg_addr, &phy_data, FALSE)); 5135 5136 if (em_swfw_sync_acquire(hw, hw->swfw)) 5137 return -E1000_ERR_SWFW_SYNC; 5138 5139 if ((hw->phy_type == em_phy_igp || 5140 hw->phy_type == em_phy_igp_3 || 5141 hw->phy_type == em_phy_igp_2) && 5142 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { 5143 ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 5144 (uint16_t) reg_addr); 5145 if (ret_val) { 5146 em_swfw_sync_release(hw, hw->swfw); 5147 return ret_val; 5148 } 5149 } else if (hw->phy_type == em_phy_gg82563) { 5150 if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) || 5151 (hw->mac_type == em_80003es2lan)) { 5152 /* Select Configuration Page */ 5153 if ((reg_addr & MAX_PHY_REG_ADDRESS) < 5154 GG82563_MIN_ALT_REG) { 5155 ret_val = em_write_phy_reg_ex(hw, 5156 GG82563_PHY_PAGE_SELECT, 5157 (uint16_t) ((uint16_t) reg_addr >> 5158 GG82563_PAGE_SHIFT)); 5159 } else { 5160 /* 5161 * Use Alternative Page Select register to 5162 * access registers 30 and 31 5163 */ 5164 ret_val = em_write_phy_reg_ex(hw, 5165 GG82563_PHY_PAGE_SELECT_ALT, 5166 (uint16_t) ((uint16_t) reg_addr >> 5167 GG82563_PAGE_SHIFT)); 5168 } 5169 5170 if (ret_val) { 5171 em_swfw_sync_release(hw, hw->swfw); 5172 return ret_val; 5173 } 5174 } 5175 } else if ((hw->phy_type == em_phy_bm) && (hw->phy_revision == 1)) { 5176 if (reg_addr > MAX_PHY_MULTI_PAGE_REG) { 5177 ret_val = em_write_phy_reg_ex(hw, BM_PHY_PAGE_SELECT, 5178 (uint16_t) ((uint16_t) reg_addr >> 5179 PHY_PAGE_SHIFT)); 5180 if (ret_val) 5181 return ret_val; 5182 } 5183 } 5184 ret_val = em_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, 5185 phy_data); 5186 5187 em_swfw_sync_release(hw, hw->swfw); 5188 return ret_val; 5189 } 5190 5191 STATIC int32_t 5192 em_write_phy_reg_ex(struct em_hw *hw, uint32_t reg_addr, uint16_t phy_data) 5193 { 5194 uint32_t i; 5195 uint32_t mdic = 0; 5196 DEBUGFUNC("em_write_phy_reg_ex"); 5197 5198 if (reg_addr > MAX_PHY_REG_ADDRESS) { 5199 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); 5200 return -E1000_ERR_PARAM; 5201 } 5202 if (hw->mac_type == em_icp_xxxx) { 5203 gcu_miibus_writereg(hw, hw->icp_xxxx_port_num, 5204 reg_addr, phy_data); 5205 return E1000_SUCCESS; 5206 } 5207 if (hw->mac_type > em_82543) { 5208 /* 5209 * Set up Op-code, Phy Address, register address, and data 5210 * intended for the PHY register in the MDI Control register. 5211 * The MAC will take care of interfacing with the PHY to send 5212 * the desired data. 5213 */ 5214 mdic = (((uint32_t) phy_data) | 5215 (reg_addr << E1000_MDIC_REG_SHIFT) | 5216 (hw->phy_addr << E1000_MDIC_PHY_SHIFT) | 5217 (E1000_MDIC_OP_WRITE)); 5218 5219 E1000_WRITE_REG(hw, MDIC, mdic); 5220 5221 /* Poll the ready bit to see if the MDI read completed */ 5222 for (i = 0; i < 641; i++) { 5223 usec_delay(5); 5224 mdic = E1000_READ_REG(hw, MDIC); 5225 if (mdic & E1000_MDIC_READY) 5226 break; 5227 } 5228 if (!(mdic & E1000_MDIC_READY)) { 5229 DEBUGOUT("MDI Write did not complete\n"); 5230 return -E1000_ERR_PHY; 5231 } 5232 5233 if (hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt || 5234 hw->mac_type == em_pch_spt || hw->mac_type == em_pch_cnp) 5235 usec_delay(100); 5236 } else { 5237 /* 5238 * We'll need to use the SW defined pins to shift the write 5239 * command out to the PHY. We first send a preamble to the 5240 * PHY to signal the beginning of the MII instruction. This 5241 * is done by sending 32 consecutive "1" bits. 5242 */ 5243 em_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 5244 /* 5245 * Now combine the remaining required fields that will 5246 * indicate a write operation. We use this method instead of 5247 * calling the em_shift_out_mdi_bits routine for each field 5248 * in the command. The format of a MII write instruction is 5249 * as follows: <Preamble><SOF><Op Code><Phy Addr><Reg 5250 * Addr><Turnaround><Data>. 5251 */ 5252 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | 5253 (hw->phy_addr << 7) | (PHY_OP_WRITE << 12) | 5254 (PHY_SOF << 14)); 5255 mdic <<= 16; 5256 mdic |= (uint32_t) phy_data; 5257 5258 em_shift_out_mdi_bits(hw, mdic, 32); 5259 } 5260 5261 return E1000_SUCCESS; 5262 } 5263 5264 STATIC int32_t 5265 em_read_kmrn_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t *data) 5266 { 5267 uint32_t reg_val; 5268 DEBUGFUNC("em_read_kmrn_reg"); 5269 5270 if (em_swfw_sync_acquire(hw, hw->swfw)) 5271 return -E1000_ERR_SWFW_SYNC; 5272 5273 /* Write register address */ 5274 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) & 5275 E1000_KUMCTRLSTA_OFFSET) | 5276 E1000_KUMCTRLSTA_REN; 5277 5278 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); 5279 usec_delay(2); 5280 5281 /* Read the data returned */ 5282 reg_val = E1000_READ_REG(hw, KUMCTRLSTA); 5283 *data = (uint16_t) reg_val; 5284 5285 em_swfw_sync_release(hw, hw->swfw); 5286 return E1000_SUCCESS; 5287 } 5288 5289 STATIC int32_t 5290 em_write_kmrn_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t data) 5291 { 5292 uint32_t reg_val; 5293 DEBUGFUNC("em_write_kmrn_reg"); 5294 5295 if (em_swfw_sync_acquire(hw, hw->swfw)) 5296 return -E1000_ERR_SWFW_SYNC; 5297 5298 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) & 5299 E1000_KUMCTRLSTA_OFFSET) | data; 5300 5301 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); 5302 usec_delay(2); 5303 5304 em_swfw_sync_release(hw, hw->swfw); 5305 return E1000_SUCCESS; 5306 } 5307 5308 /****************************************************************************** 5309 * Returns the PHY to the power-on reset state 5310 * 5311 * hw - Struct containing variables accessed by shared code 5312 *****************************************************************************/ 5313 int32_t 5314 em_phy_hw_reset(struct em_hw *hw) 5315 { 5316 uint32_t ctrl, ctrl_ext; 5317 uint32_t led_ctrl; 5318 int32_t ret_val; 5319 DEBUGFUNC("em_phy_hw_reset"); 5320 /* 5321 * In the case of the phy reset being blocked, it's not an error, we 5322 * simply return success without performing the reset. 5323 */ 5324 ret_val = em_check_phy_reset_block(hw); 5325 if (ret_val) 5326 return E1000_SUCCESS; 5327 5328 DEBUGOUT("Resetting Phy...\n"); 5329 5330 if (hw->mac_type > em_82543 && hw->mac_type != em_icp_xxxx) { 5331 if (em_swfw_sync_acquire(hw, hw->swfw)) { 5332 DEBUGOUT("Unable to acquire swfw sync\n"); 5333 return -E1000_ERR_SWFW_SYNC; 5334 } 5335 /* 5336 * Read the device control register and assert the 5337 * E1000_CTRL_PHY_RST bit. Then, take it out of reset. For 5338 * pre-em_82571 hardware, we delay for 10ms between the 5339 * assert and deassert. For em_82571 hardware and later, we 5340 * instead delay for 50us between and 10ms after the 5341 * deassertion. 5342 */ 5343 ctrl = E1000_READ_REG(hw, CTRL); 5344 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST); 5345 E1000_WRITE_FLUSH(hw); 5346 5347 if (hw->mac_type < em_82571) 5348 msec_delay(10); 5349 else 5350 usec_delay(100); 5351 5352 E1000_WRITE_REG(hw, CTRL, ctrl); 5353 E1000_WRITE_FLUSH(hw); 5354 5355 if (hw->mac_type >= em_82571) 5356 msec_delay_irq(10); 5357 em_swfw_sync_release(hw, hw->swfw); 5358 /* 5359 * the M88E1141_E_PHY_ID might need reset here, but nothing 5360 * proves it 5361 */ 5362 } else { 5363 /* 5364 * Read the Extended Device Control Register, assert the 5365 * PHY_RESET_DIR bit to put the PHY into reset. Then, take it 5366 * out of reset. 5367 */ 5368 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 5369 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; 5370 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; 5371 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 5372 E1000_WRITE_FLUSH(hw); 5373 msec_delay(10); 5374 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; 5375 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 5376 E1000_WRITE_FLUSH(hw); 5377 } 5378 usec_delay(150); 5379 5380 if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) { 5381 /* Configure activity LED after PHY reset */ 5382 led_ctrl = E1000_READ_REG(hw, LEDCTL); 5383 led_ctrl &= IGP_ACTIVITY_LED_MASK; 5384 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 5385 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 5386 } 5387 /* Wait for FW to finish PHY configuration. */ 5388 ret_val = em_get_phy_cfg_done(hw); 5389 if (ret_val != E1000_SUCCESS) 5390 return ret_val; 5391 em_release_software_semaphore(hw); 5392 5393 if ((hw->mac_type == em_ich8lan) && (hw->phy_type == em_phy_igp_3)) 5394 ret_val = em_init_lcd_from_nvm(hw); 5395 5396 return ret_val; 5397 } 5398 5399 /***************************************************************************** 5400 * SW-based LCD Configuration. 5401 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are 5402 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit 5403 * in NVM determines whether HW should configure LPLU and Gbe Disable. 5404 *****************************************************************************/ 5405 int32_t 5406 em_oem_bits_config_pchlan(struct em_hw *hw, boolean_t d0_state) 5407 { 5408 int32_t ret_val = E1000_SUCCESS; 5409 uint32_t mac_reg; 5410 uint16_t oem_reg; 5411 uint16_t swfw = E1000_SWFW_PHY0_SM; 5412 5413 if (hw->mac_type < em_pchlan) 5414 return ret_val; 5415 5416 ret_val = em_swfw_sync_acquire(hw, swfw); 5417 if (ret_val) 5418 return ret_val; 5419 5420 if (hw->mac_type == em_pchlan) { 5421 mac_reg = E1000_READ_REG(hw, EXTCNF_CTRL); 5422 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) 5423 goto out; 5424 } 5425 5426 mac_reg = E1000_READ_REG(hw, FEXTNVM); 5427 if (!(mac_reg & FEXTNVM_SW_CONFIG_ICH8M)) 5428 goto out; 5429 5430 mac_reg = E1000_READ_REG(hw, PHY_CTRL); 5431 5432 ret_val = em_read_phy_reg(hw, HV_OEM_BITS, &oem_reg); 5433 if (ret_val) 5434 goto out; 5435 5436 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU); 5437 5438 if (d0_state) { 5439 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE) 5440 oem_reg |= HV_OEM_BITS_GBE_DIS; 5441 5442 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU) 5443 oem_reg |= HV_OEM_BITS_LPLU; 5444 /* Restart auto-neg to activate the bits */ 5445 if (!em_check_phy_reset_block(hw)) 5446 oem_reg |= HV_OEM_BITS_RESTART_AN; 5447 5448 } else { 5449 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE | 5450 E1000_PHY_CTRL_NOND0A_GBE_DISABLE)) 5451 oem_reg |= HV_OEM_BITS_GBE_DIS; 5452 5453 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU | 5454 E1000_PHY_CTRL_NOND0A_LPLU)) 5455 oem_reg |= HV_OEM_BITS_LPLU; 5456 } 5457 5458 ret_val = em_write_phy_reg(hw, HV_OEM_BITS, oem_reg); 5459 5460 out: 5461 em_swfw_sync_release(hw, swfw); 5462 5463 return ret_val; 5464 } 5465 5466 5467 /****************************************************************************** 5468 * Resets the PHY 5469 * 5470 * hw - Struct containing variables accessed by shared code 5471 * 5472 * Sets bit 15 of the MII Control regiser 5473 *****************************************************************************/ 5474 int32_t 5475 em_phy_reset(struct em_hw *hw) 5476 { 5477 int32_t ret_val; 5478 uint16_t phy_data; 5479 DEBUGFUNC("em_phy_reset"); 5480 /* 5481 * In the case of the phy reset being blocked, it's not an error, we 5482 * simply return success without performing the reset. 5483 */ 5484 ret_val = em_check_phy_reset_block(hw); 5485 if (ret_val) 5486 return E1000_SUCCESS; 5487 5488 switch (hw->phy_type) { 5489 case em_phy_igp: 5490 case em_phy_igp_2: 5491 case em_phy_igp_3: 5492 case em_phy_ife: 5493 ret_val = em_phy_hw_reset(hw); 5494 if (ret_val) 5495 return ret_val; 5496 break; 5497 default: 5498 ret_val = em_read_phy_reg(hw, PHY_CTRL, &phy_data); 5499 if (ret_val) 5500 return ret_val; 5501 5502 phy_data |= MII_CR_RESET; 5503 ret_val = em_write_phy_reg(hw, PHY_CTRL, phy_data); 5504 if (ret_val) 5505 return ret_val; 5506 5507 usec_delay(1); 5508 break; 5509 } 5510 5511 /* Allow time for h/w to get to a quiescent state after reset */ 5512 msec_delay(10); 5513 5514 if (hw->phy_type == em_phy_igp || hw->phy_type == em_phy_igp_2) 5515 em_phy_init_script(hw); 5516 5517 if (hw->mac_type == em_pchlan) { 5518 ret_val = em_hv_phy_workarounds_ich8lan(hw); 5519 if (ret_val) 5520 return ret_val; 5521 } else if (hw->mac_type == em_pch2lan) { 5522 ret_val = em_lv_phy_workarounds_ich8lan(hw); 5523 if (ret_val) 5524 return ret_val; 5525 } 5526 5527 if (hw->mac_type >= em_pchlan) { 5528 ret_val = em_oem_bits_config_pchlan(hw, TRUE); 5529 if (ret_val) 5530 return ret_val; 5531 } 5532 5533 /* Ungate automatic PHY configuration on non-managed 82579 */ 5534 if ((hw->mac_type == em_pch2lan) && 5535 !(E1000_READ_REG(hw, FWSM) & E1000_FWSM_FW_VALID)) { 5536 msec_delay(10); 5537 em_gate_hw_phy_config_ich8lan(hw, FALSE); 5538 } 5539 5540 if (hw->phy_id == M88E1512_E_PHY_ID) { 5541 ret_val = em_initialize_M88E1512_phy(hw); 5542 if (ret_val) 5543 return ret_val; 5544 } 5545 5546 return E1000_SUCCESS; 5547 } 5548 5549 /****************************************************************************** 5550 * Work-around for 82566 Kumeran PCS lock loss: 5551 * On link status change (i.e. PCI reset, speed change) and link is up and 5552 * speed is gigabit- 5553 * 0) if workaround is optionally disabled do nothing 5554 * 1) wait 1ms for Kumeran link to come up 5555 * 2) check Kumeran Diagnostic register PCS lock loss bit 5556 * 3) if not set the link is locked (all is good), otherwise... 5557 * 4) reset the PHY 5558 * 5) repeat up to 10 times 5559 * Note: this is only called for IGP3 copper when speed is 1gb. 5560 * 5561 * hw - struct containing variables accessed by shared code 5562 *****************************************************************************/ 5563 STATIC int32_t 5564 em_kumeran_lock_loss_workaround(struct em_hw *hw) 5565 { 5566 int32_t ret_val; 5567 int32_t reg; 5568 int32_t cnt; 5569 uint16_t phy_data; 5570 if (hw->kmrn_lock_loss_workaround_disabled) 5571 return E1000_SUCCESS; 5572 /* 5573 * Make sure link is up before proceeding. If not just return. 5574 * Attempting this while link is negotiating fouled up link stability 5575 */ 5576 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 5577 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 5578 5579 if (phy_data & MII_SR_LINK_STATUS) { 5580 for (cnt = 0; cnt < 10; cnt++) { 5581 /* read once to clear */ 5582 ret_val = em_read_phy_reg(hw, IGP3_KMRN_DIAG, 5583 &phy_data); 5584 if (ret_val) 5585 return ret_val; 5586 /* and again to get new status */ 5587 ret_val = em_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data); 5588 if (ret_val) 5589 return ret_val; 5590 5591 /* check for PCS lock */ 5592 if (!(phy_data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) 5593 return E1000_SUCCESS; 5594 5595 /* Issue PHY reset */ 5596 em_phy_hw_reset(hw); 5597 msec_delay_irq(5); 5598 } 5599 /* Disable GigE link negotiation */ 5600 reg = E1000_READ_REG(hw, PHY_CTRL); 5601 E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE 5602 | E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 5603 5604 /* unable to acquire PCS lock */ 5605 return E1000_ERR_PHY; 5606 } 5607 return E1000_SUCCESS; 5608 } 5609 5610 /****************************************************************************** 5611 * Reads and matches the expected PHY address for known PHY IDs 5612 * 5613 * hw - Struct containing variables accessed by shared code 5614 *****************************************************************************/ 5615 STATIC int32_t 5616 em_match_gig_phy(struct em_hw *hw) 5617 { 5618 int32_t phy_init_status, ret_val; 5619 uint16_t phy_id_high, phy_id_low; 5620 boolean_t match = FALSE; 5621 DEBUGFUNC("em_match_gig_phy"); 5622 5623 ret_val = em_read_phy_reg(hw, PHY_ID1, &phy_id_high); 5624 if (ret_val) 5625 return ret_val; 5626 5627 hw->phy_id = (uint32_t) (phy_id_high << 16); 5628 usec_delay(20); 5629 ret_val = em_read_phy_reg(hw, PHY_ID2, &phy_id_low); 5630 if (ret_val) 5631 return ret_val; 5632 5633 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK); 5634 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK; 5635 5636 switch (hw->mac_type) { 5637 case em_82543: 5638 if (hw->phy_id == M88E1000_E_PHY_ID) 5639 match = TRUE; 5640 break; 5641 case em_82544: 5642 if (hw->phy_id == M88E1000_I_PHY_ID) 5643 match = TRUE; 5644 break; 5645 case em_82540: 5646 case em_82545: 5647 case em_82545_rev_3: 5648 case em_82546: 5649 case em_82546_rev_3: 5650 if (hw->phy_id == M88E1011_I_PHY_ID) 5651 match = TRUE; 5652 break; 5653 case em_82541: 5654 case em_82541_rev_2: 5655 case em_82547: 5656 case em_82547_rev_2: 5657 if (hw->phy_id == IGP01E1000_I_PHY_ID) 5658 match = TRUE; 5659 break; 5660 case em_82573: 5661 if (hw->phy_id == M88E1111_I_PHY_ID) 5662 match = TRUE; 5663 break; 5664 case em_82574: 5665 if (hw->phy_id == BME1000_E_PHY_ID) 5666 match = TRUE; 5667 break; 5668 case em_82575: 5669 case em_82576: 5670 if (hw->phy_id == M88E1000_E_PHY_ID) 5671 match = TRUE; 5672 if (hw->phy_id == IGP01E1000_I_PHY_ID) 5673 match = TRUE; 5674 if (hw->phy_id == IGP03E1000_E_PHY_ID) 5675 match = TRUE; 5676 break; 5677 case em_82580: 5678 case em_i210: 5679 case em_i350: 5680 if (hw->phy_id == I82580_I_PHY_ID || 5681 hw->phy_id == I210_I_PHY_ID || 5682 hw->phy_id == I347AT4_E_PHY_ID || 5683 hw->phy_id == I350_I_PHY_ID || 5684 hw->phy_id == M88E1112_E_PHY_ID || 5685 hw->phy_id == M88E1543_E_PHY_ID || 5686 hw->phy_id == M88E1512_E_PHY_ID) { 5687 uint32_t mdic; 5688 5689 mdic = EM_READ_REG(hw, E1000_MDICNFG); 5690 mdic &= E1000_MDICNFG_PHY_MASK; 5691 hw->phy_addr = mdic >> E1000_MDICNFG_PHY_SHIFT; 5692 DEBUGOUT1("MDICNFG PHY ADDR %d", 5693 mdic >> E1000_MDICNFG_PHY_SHIFT); 5694 match = TRUE; 5695 } 5696 break; 5697 case em_80003es2lan: 5698 if (hw->phy_id == GG82563_E_PHY_ID) 5699 match = TRUE; 5700 break; 5701 case em_ich8lan: 5702 case em_ich9lan: 5703 case em_ich10lan: 5704 case em_pchlan: 5705 case em_pch2lan: 5706 if (hw->phy_id == IGP03E1000_E_PHY_ID) 5707 match = TRUE; 5708 if (hw->phy_id == IFE_E_PHY_ID) 5709 match = TRUE; 5710 if (hw->phy_id == IFE_PLUS_E_PHY_ID) 5711 match = TRUE; 5712 if (hw->phy_id == IFE_C_E_PHY_ID) 5713 match = TRUE; 5714 if (hw->phy_id == BME1000_E_PHY_ID) 5715 match = TRUE; 5716 if (hw->phy_id == I82577_E_PHY_ID) 5717 match = TRUE; 5718 if (hw->phy_id == I82578_E_PHY_ID) 5719 match = TRUE; 5720 if (hw->phy_id == I82579_E_PHY_ID) 5721 match = TRUE; 5722 break; 5723 case em_pch_lpt: 5724 case em_pch_spt: 5725 case em_pch_cnp: 5726 if (hw->phy_id == I217_E_PHY_ID) 5727 match = TRUE; 5728 break; 5729 case em_icp_xxxx: 5730 if (hw->phy_id == M88E1141_E_PHY_ID) 5731 match = TRUE; 5732 if (hw->phy_id == RTL8211_E_PHY_ID) 5733 match = TRUE; 5734 break; 5735 default: 5736 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type); 5737 return -E1000_ERR_CONFIG; 5738 } 5739 phy_init_status = em_set_phy_type(hw); 5740 5741 if ((match) && (phy_init_status == E1000_SUCCESS)) { 5742 DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id); 5743 return E1000_SUCCESS; 5744 } 5745 DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id); 5746 return -E1000_ERR_PHY; 5747 } 5748 5749 /****************************************************************************** 5750 * Probes the expected PHY address for known PHY IDs 5751 * 5752 * hw - Struct containing variables accessed by shared code 5753 *****************************************************************************/ 5754 STATIC int32_t 5755 em_detect_gig_phy(struct em_hw *hw) 5756 { 5757 int32_t ret_val, i; 5758 DEBUGFUNC("em_detect_gig_phy"); 5759 5760 if (hw->phy_id != 0) 5761 return E1000_SUCCESS; 5762 5763 /* default phy address, most phys reside here, but not all (ICH10) */ 5764 if (hw->mac_type != em_icp_xxxx) 5765 hw->phy_addr = 1; 5766 else 5767 hw->phy_addr = 0; /* There is a phy at phy_addr 0 on EP80579 */ 5768 5769 /* 5770 * The 82571 firmware may still be configuring the PHY. In this 5771 * case, we cannot access the PHY until the configuration is done. 5772 * So we explicitly set the PHY values. 5773 */ 5774 if (hw->mac_type == em_82571 || 5775 hw->mac_type == em_82572) { 5776 hw->phy_id = IGP01E1000_I_PHY_ID; 5777 hw->phy_type = em_phy_igp_2; 5778 return E1000_SUCCESS; 5779 } 5780 5781 /* 5782 * Some of the fiber cards dont have a phy, so we must exit cleanly 5783 * here 5784 */ 5785 if ((hw->media_type == em_media_type_fiber) && 5786 (hw->mac_type == em_82542_rev2_0 || 5787 hw->mac_type == em_82542_rev2_1 || 5788 hw->mac_type == em_82543 || 5789 hw->mac_type == em_82573 || 5790 hw->mac_type == em_82574 || 5791 hw->mac_type == em_80003es2lan)) { 5792 hw->phy_type = em_phy_undefined; 5793 return E1000_SUCCESS; 5794 } 5795 5796 if ((hw->media_type == em_media_type_internal_serdes || 5797 hw->media_type == em_media_type_fiber) && 5798 hw->mac_type >= em_82575) { 5799 hw->phy_type = em_phy_undefined; 5800 return E1000_SUCCESS; 5801 } 5802 5803 /* 5804 * Up to 82543 (incl), we need reset the phy, or it might not get 5805 * detected 5806 */ 5807 if (hw->mac_type <= em_82543) { 5808 ret_val = em_phy_hw_reset(hw); 5809 if (ret_val) 5810 return ret_val; 5811 } 5812 /* 5813 * ESB-2 PHY reads require em_phy_gg82563 to be set because of a 5814 * work- around that forces PHY page 0 to be set or the reads fail. 5815 * The rest of the code in this routine uses em_read_phy_reg to read 5816 * the PHY ID. So for ESB-2 we need to have this set so our reads 5817 * won't fail. If the attached PHY is not a em_phy_gg82563, the 5818 * routines below will figure this out as well. 5819 */ 5820 if (hw->mac_type == em_80003es2lan) 5821 hw->phy_type = em_phy_gg82563; 5822 5823 /* Power on SGMII phy if it is disabled */ 5824 if (hw->mac_type == em_82580 || hw->mac_type == em_i210 || 5825 hw->mac_type == em_i350) { 5826 uint32_t ctrl_ext = EM_READ_REG(hw, E1000_CTRL_EXT); 5827 EM_WRITE_REG(hw, E1000_CTRL_EXT, 5828 ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA); 5829 delay(300); 5830 } 5831 5832 /* Read the PHY ID Registers to identify which PHY is onboard. */ 5833 for (i = 1; i < 4; i++) { 5834 /* 5835 * hw->phy_addr may be modified down in the call stack, 5836 * we can't use it as loop variable. 5837 */ 5838 hw->phy_addr = i; 5839 ret_val = em_match_gig_phy(hw); 5840 if (ret_val == E1000_SUCCESS) 5841 return E1000_SUCCESS; 5842 } 5843 return -E1000_ERR_PHY; 5844 } 5845 5846 /****************************************************************************** 5847 * Resets the PHY's DSP 5848 * 5849 * hw - Struct containing variables accessed by shared code 5850 *****************************************************************************/ 5851 static int32_t 5852 em_phy_reset_dsp(struct em_hw *hw) 5853 { 5854 int32_t ret_val; 5855 DEBUGFUNC("em_phy_reset_dsp"); 5856 5857 do { 5858 if (hw->phy_type != em_phy_gg82563) { 5859 ret_val = em_write_phy_reg(hw, 29, 0x001d); 5860 if (ret_val) 5861 break; 5862 } 5863 ret_val = em_write_phy_reg(hw, 30, 0x00c1); 5864 if (ret_val) 5865 break; 5866 ret_val = em_write_phy_reg(hw, 30, 0x0000); 5867 if (ret_val) 5868 break; 5869 ret_val = E1000_SUCCESS; 5870 } while (0); 5871 5872 return ret_val; 5873 } 5874 5875 /****************************************************************************** 5876 * Sets up eeprom variables in the hw struct. Must be called after mac_type 5877 * is configured. Additionally, if this is ICH8, the flash controller GbE 5878 * registers must be mapped, or this will crash. 5879 * 5880 * hw - Struct containing variables accessed by shared code 5881 *****************************************************************************/ 5882 int32_t 5883 em_init_eeprom_params(struct em_hw *hw) 5884 { 5885 struct em_eeprom_info *eeprom = &hw->eeprom; 5886 uint32_t eecd = E1000_READ_REG(hw, EECD); 5887 int32_t ret_val = E1000_SUCCESS; 5888 uint16_t eeprom_size; 5889 DEBUGFUNC("em_init_eeprom_params"); 5890 5891 switch (hw->mac_type) { 5892 case em_82542_rev2_0: 5893 case em_82542_rev2_1: 5894 case em_82543: 5895 case em_82544: 5896 eeprom->type = em_eeprom_microwire; 5897 eeprom->word_size = 64; 5898 eeprom->opcode_bits = 3; 5899 eeprom->address_bits = 6; 5900 eeprom->delay_usec = 50; 5901 eeprom->use_eerd = FALSE; 5902 eeprom->use_eewr = FALSE; 5903 break; 5904 case em_82540: 5905 case em_82545: 5906 case em_82545_rev_3: 5907 case em_icp_xxxx: 5908 case em_82546: 5909 case em_82546_rev_3: 5910 eeprom->type = em_eeprom_microwire; 5911 eeprom->opcode_bits = 3; 5912 eeprom->delay_usec = 50; 5913 if (eecd & E1000_EECD_SIZE) { 5914 eeprom->word_size = 256; 5915 eeprom->address_bits = 8; 5916 } else { 5917 eeprom->word_size = 64; 5918 eeprom->address_bits = 6; 5919 } 5920 eeprom->use_eerd = FALSE; 5921 eeprom->use_eewr = FALSE; 5922 break; 5923 case em_82541: 5924 case em_82541_rev_2: 5925 case em_82547: 5926 case em_82547_rev_2: 5927 if (eecd & E1000_EECD_TYPE) { 5928 eeprom->type = em_eeprom_spi; 5929 eeprom->opcode_bits = 8; 5930 eeprom->delay_usec = 1; 5931 if (eecd & E1000_EECD_ADDR_BITS) { 5932 eeprom->page_size = 32; 5933 eeprom->address_bits = 16; 5934 } else { 5935 eeprom->page_size = 8; 5936 eeprom->address_bits = 8; 5937 } 5938 } else { 5939 eeprom->type = em_eeprom_microwire; 5940 eeprom->opcode_bits = 3; 5941 eeprom->delay_usec = 50; 5942 if (eecd & E1000_EECD_ADDR_BITS) { 5943 eeprom->word_size = 256; 5944 eeprom->address_bits = 8; 5945 } else { 5946 eeprom->word_size = 64; 5947 eeprom->address_bits = 6; 5948 } 5949 } 5950 eeprom->use_eerd = FALSE; 5951 eeprom->use_eewr = FALSE; 5952 break; 5953 case em_82571: 5954 case em_82572: 5955 eeprom->type = em_eeprom_spi; 5956 eeprom->opcode_bits = 8; 5957 eeprom->delay_usec = 1; 5958 if (eecd & E1000_EECD_ADDR_BITS) { 5959 eeprom->page_size = 32; 5960 eeprom->address_bits = 16; 5961 } else { 5962 eeprom->page_size = 8; 5963 eeprom->address_bits = 8; 5964 } 5965 eeprom->use_eerd = FALSE; 5966 eeprom->use_eewr = FALSE; 5967 break; 5968 case em_82573: 5969 case em_82574: 5970 case em_82575: 5971 case em_82576: 5972 case em_82580: 5973 case em_i210: 5974 case em_i350: 5975 eeprom->type = em_eeprom_spi; 5976 eeprom->opcode_bits = 8; 5977 eeprom->delay_usec = 1; 5978 if (eecd & E1000_EECD_ADDR_BITS) { 5979 eeprom->page_size = 32; 5980 eeprom->address_bits = 16; 5981 } else { 5982 eeprom->page_size = 8; 5983 eeprom->address_bits = 8; 5984 } 5985 eeprom->use_eerd = TRUE; 5986 eeprom->use_eewr = TRUE; 5987 if (em_is_onboard_nvm_eeprom(hw) == FALSE) { 5988 eeprom->type = em_eeprom_flash; 5989 eeprom->word_size = 2048; 5990 /* 5991 * Ensure that the Autonomous FLASH update bit is 5992 * cleared due to Flash update issue on parts which 5993 * use a FLASH for NVM. 5994 */ 5995 eecd &= ~E1000_EECD_AUPDEN; 5996 E1000_WRITE_REG(hw, EECD, eecd); 5997 } 5998 if (em_get_flash_presence_i210(hw) == FALSE) { 5999 eeprom->type = em_eeprom_invm; 6000 eeprom->word_size = INVM_SIZE; 6001 eeprom->use_eerd = FALSE; 6002 eeprom->use_eewr = FALSE; 6003 } 6004 break; 6005 case em_80003es2lan: 6006 eeprom->type = em_eeprom_spi; 6007 eeprom->opcode_bits = 8; 6008 eeprom->delay_usec = 1; 6009 if (eecd & E1000_EECD_ADDR_BITS) { 6010 eeprom->page_size = 32; 6011 eeprom->address_bits = 16; 6012 } else { 6013 eeprom->page_size = 8; 6014 eeprom->address_bits = 8; 6015 } 6016 eeprom->use_eerd = TRUE; 6017 eeprom->use_eewr = FALSE; 6018 break; 6019 case em_ich8lan: 6020 case em_ich9lan: 6021 case em_ich10lan: 6022 case em_pchlan: 6023 case em_pch2lan: 6024 case em_pch_lpt: 6025 { 6026 int32_t i = 0; 6027 uint32_t flash_size = 6028 E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_GFPREG); 6029 eeprom->type = em_eeprom_ich8; 6030 eeprom->use_eerd = FALSE; 6031 eeprom->use_eewr = FALSE; 6032 eeprom->word_size = E1000_SHADOW_RAM_WORDS; 6033 /* 6034 * Zero the shadow RAM structure. But don't load it 6035 * from NVM so as to save time for driver init 6036 */ 6037 if (hw->eeprom_shadow_ram != NULL) { 6038 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 6039 hw->eeprom_shadow_ram[i].modified = 6040 FALSE; 6041 hw->eeprom_shadow_ram[i].eeprom_word = 6042 0xFFFF; 6043 } 6044 } 6045 hw->flash_base_addr = (flash_size & 6046 ICH_GFPREG_BASE_MASK) * ICH_FLASH_SECTOR_SIZE; 6047 6048 hw->flash_bank_size = ((flash_size >> 16) & 6049 ICH_GFPREG_BASE_MASK) + 1; 6050 hw->flash_bank_size -= (flash_size & 6051 ICH_GFPREG_BASE_MASK); 6052 6053 hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE; 6054 6055 hw->flash_bank_size /= 2 * sizeof(uint16_t); 6056 6057 break; 6058 } 6059 case em_pch_spt: 6060 case em_pch_cnp: 6061 { 6062 int32_t i = 0; 6063 uint32_t flash_size = EM_READ_REG(hw, 0xc /* STRAP */); 6064 6065 eeprom->type = em_eeprom_ich8; 6066 eeprom->use_eerd = FALSE; 6067 eeprom->use_eewr = FALSE; 6068 eeprom->word_size = E1000_SHADOW_RAM_WORDS; 6069 /* 6070 * Zero the shadow RAM structure. But don't load it 6071 * from NVM so as to save time for driver init 6072 */ 6073 if (hw->eeprom_shadow_ram != NULL) { 6074 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 6075 hw->eeprom_shadow_ram[i].modified = 6076 FALSE; 6077 hw->eeprom_shadow_ram[i].eeprom_word = 6078 0xFFFF; 6079 } 6080 } 6081 hw->flash_base_addr = 0; 6082 flash_size = ((flash_size >> 1) & 0x1f) + 1; 6083 flash_size *= 4096; 6084 hw->flash_bank_size = flash_size / 4; 6085 } 6086 break; 6087 default: 6088 break; 6089 } 6090 6091 if (eeprom->type == em_eeprom_spi) { 6092 /* 6093 * eeprom_size will be an enum [0..8] that maps to eeprom 6094 * sizes 128B to 32KB (incremented by powers of 2). 6095 */ 6096 if (hw->mac_type <= em_82547_rev_2) { 6097 /* Set to default value for initial eeprom read. */ 6098 eeprom->word_size = 64; 6099 ret_val = em_read_eeprom(hw, EEPROM_CFG, 1, 6100 &eeprom_size); 6101 if (ret_val) 6102 return ret_val; 6103 eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> 6104 EEPROM_SIZE_SHIFT; 6105 /* 6106 * 256B eeprom size was not supported in earlier 6107 * hardware, so we bump eeprom_size up one to ensure 6108 * that "1" (which maps to 256B) is never the result 6109 * used in the shifting logic below. 6110 */ 6111 if (eeprom_size) 6112 eeprom_size++; 6113 } else { 6114 eeprom_size = (uint16_t) ( 6115 (eecd & E1000_EECD_SIZE_EX_MASK) >> 6116 E1000_EECD_SIZE_EX_SHIFT); 6117 } 6118 6119 /* EEPROM access above 16k is unsupported */ 6120 if (eeprom_size + EEPROM_WORD_SIZE_SHIFT > 6121 EEPROM_WORD_SIZE_SHIFT_MAX) { 6122 eeprom->word_size = 1 << EEPROM_WORD_SIZE_SHIFT_MAX; 6123 } else { 6124 eeprom->word_size = 1 << 6125 (eeprom_size + EEPROM_WORD_SIZE_SHIFT); 6126 } 6127 } 6128 return ret_val; 6129 } 6130 6131 /****************************************************************************** 6132 * Raises the EEPROM's clock input. 6133 * 6134 * hw - Struct containing variables accessed by shared code 6135 * eecd - EECD's current value 6136 *****************************************************************************/ 6137 static void 6138 em_raise_ee_clk(struct em_hw *hw, uint32_t *eecd) 6139 { 6140 /* 6141 * Raise the clock input to the EEPROM (by setting the SK bit), and 6142 * then wait <delay> microseconds. 6143 */ 6144 *eecd = *eecd | E1000_EECD_SK; 6145 E1000_WRITE_REG(hw, EECD, *eecd); 6146 E1000_WRITE_FLUSH(hw); 6147 usec_delay(hw->eeprom.delay_usec); 6148 } 6149 6150 /****************************************************************************** 6151 * Lowers the EEPROM's clock input. 6152 * 6153 * hw - Struct containing variables accessed by shared code 6154 * eecd - EECD's current value 6155 *****************************************************************************/ 6156 static void 6157 em_lower_ee_clk(struct em_hw *hw, uint32_t *eecd) 6158 { 6159 /* 6160 * Lower the clock input to the EEPROM (by clearing the SK bit), and 6161 * then wait 50 microseconds. 6162 */ 6163 *eecd = *eecd & ~E1000_EECD_SK; 6164 E1000_WRITE_REG(hw, EECD, *eecd); 6165 E1000_WRITE_FLUSH(hw); 6166 usec_delay(hw->eeprom.delay_usec); 6167 } 6168 6169 /****************************************************************************** 6170 * Shift data bits out to the EEPROM. 6171 * 6172 * hw - Struct containing variables accessed by shared code 6173 * data - data to send to the EEPROM 6174 * count - number of bits to shift out 6175 *****************************************************************************/ 6176 static void 6177 em_shift_out_ee_bits(struct em_hw *hw, uint16_t data, uint16_t count) 6178 { 6179 struct em_eeprom_info *eeprom = &hw->eeprom; 6180 uint32_t eecd; 6181 uint32_t mask; 6182 /* 6183 * We need to shift "count" bits out to the EEPROM. So, value in the 6184 * "data" parameter will be shifted out to the EEPROM one bit at a 6185 * time. In order to do this, "data" must be broken down into bits. 6186 */ 6187 mask = 0x01 << (count - 1); 6188 eecd = E1000_READ_REG(hw, EECD); 6189 if (eeprom->type == em_eeprom_microwire) { 6190 eecd &= ~E1000_EECD_DO; 6191 } else if (eeprom->type == em_eeprom_spi) { 6192 eecd |= E1000_EECD_DO; 6193 } 6194 do { 6195 /* 6196 * A "1" is shifted out to the EEPROM by setting bit "DI" to 6197 * a "1", and then raising and then lowering the clock (the 6198 * SK bit controls the clock input to the EEPROM). A "0" is 6199 * shifted out to the EEPROM by setting "DI" to "0" and then 6200 * raising and then lowering the clock. 6201 */ 6202 eecd &= ~E1000_EECD_DI; 6203 6204 if (data & mask) 6205 eecd |= E1000_EECD_DI; 6206 6207 E1000_WRITE_REG(hw, EECD, eecd); 6208 E1000_WRITE_FLUSH(hw); 6209 6210 usec_delay(eeprom->delay_usec); 6211 6212 em_raise_ee_clk(hw, &eecd); 6213 em_lower_ee_clk(hw, &eecd); 6214 6215 mask = mask >> 1; 6216 6217 } while (mask); 6218 6219 /* We leave the "DI" bit set to "0" when we leave this routine. */ 6220 eecd &= ~E1000_EECD_DI; 6221 E1000_WRITE_REG(hw, EECD, eecd); 6222 } 6223 6224 /****************************************************************************** 6225 * Shift data bits in from the EEPROM 6226 * 6227 * hw - Struct containing variables accessed by shared code 6228 *****************************************************************************/ 6229 static uint16_t 6230 em_shift_in_ee_bits(struct em_hw *hw, uint16_t count) 6231 { 6232 uint32_t eecd; 6233 uint32_t i; 6234 uint16_t data; 6235 /* 6236 * In order to read a register from the EEPROM, we need to shift 6237 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising 6238 * the clock input to the EEPROM (setting the SK bit), and then 6239 * reading the value of the "DO" bit. During this "shifting in" 6240 * process the "DI" bit should always be clear. 6241 */ 6242 6243 eecd = E1000_READ_REG(hw, EECD); 6244 6245 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 6246 data = 0; 6247 6248 for (i = 0; i < count; i++) { 6249 data = data << 1; 6250 em_raise_ee_clk(hw, &eecd); 6251 6252 eecd = E1000_READ_REG(hw, EECD); 6253 6254 eecd &= ~(E1000_EECD_DI); 6255 if (eecd & E1000_EECD_DO) 6256 data |= 1; 6257 6258 em_lower_ee_clk(hw, &eecd); 6259 } 6260 6261 return data; 6262 } 6263 /****************************************************************************** 6264 * Prepares EEPROM for access 6265 * 6266 * hw - Struct containing variables accessed by shared code 6267 * 6268 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This 6269 * function should be called before issuing a command to the EEPROM. 6270 *****************************************************************************/ 6271 static int32_t 6272 em_acquire_eeprom(struct em_hw *hw) 6273 { 6274 struct em_eeprom_info *eeprom = &hw->eeprom; 6275 uint32_t eecd, i = 0; 6276 DEBUGFUNC("em_acquire_eeprom"); 6277 6278 if (em_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM)) 6279 return -E1000_ERR_SWFW_SYNC; 6280 eecd = E1000_READ_REG(hw, EECD); 6281 6282 if ((hw->mac_type != em_82573) && (hw->mac_type != em_82574)) { 6283 /* Request EEPROM Access */ 6284 if (hw->mac_type > em_82544) { 6285 eecd |= E1000_EECD_REQ; 6286 E1000_WRITE_REG(hw, EECD, eecd); 6287 eecd = E1000_READ_REG(hw, EECD); 6288 while ((!(eecd & E1000_EECD_GNT)) && 6289 (i < E1000_EEPROM_GRANT_ATTEMPTS)) { 6290 i++; 6291 usec_delay(5); 6292 eecd = E1000_READ_REG(hw, EECD); 6293 } 6294 if (!(eecd & E1000_EECD_GNT)) { 6295 eecd &= ~E1000_EECD_REQ; 6296 E1000_WRITE_REG(hw, EECD, eecd); 6297 DEBUGOUT("Could not acquire EEPROM grant\n"); 6298 em_swfw_sync_release(hw, E1000_SWFW_EEP_SM); 6299 return -E1000_ERR_EEPROM; 6300 } 6301 } 6302 } 6303 6304 /* Setup EEPROM for Read/Write */ 6305 if (eeprom->type == em_eeprom_microwire) { 6306 /* Clear SK and DI */ 6307 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK); 6308 E1000_WRITE_REG(hw, EECD, eecd); 6309 6310 /* Set CS */ 6311 eecd |= E1000_EECD_CS; 6312 E1000_WRITE_REG(hw, EECD, eecd); 6313 } else if (eeprom->type == em_eeprom_spi) { 6314 /* Clear SK and CS */ 6315 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 6316 E1000_WRITE_REG(hw, EECD, eecd); 6317 usec_delay(1); 6318 } 6319 return E1000_SUCCESS; 6320 } 6321 6322 /****************************************************************************** 6323 * Returns EEPROM to a "standby" state 6324 * 6325 * hw - Struct containing variables accessed by shared code 6326 *****************************************************************************/ 6327 static void 6328 em_standby_eeprom(struct em_hw *hw) 6329 { 6330 struct em_eeprom_info *eeprom = &hw->eeprom; 6331 uint32_t eecd; 6332 eecd = E1000_READ_REG(hw, EECD); 6333 6334 if (eeprom->type == em_eeprom_microwire) { 6335 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 6336 E1000_WRITE_REG(hw, EECD, eecd); 6337 E1000_WRITE_FLUSH(hw); 6338 usec_delay(eeprom->delay_usec); 6339 6340 /* Clock high */ 6341 eecd |= E1000_EECD_SK; 6342 E1000_WRITE_REG(hw, EECD, eecd); 6343 E1000_WRITE_FLUSH(hw); 6344 usec_delay(eeprom->delay_usec); 6345 6346 /* Select EEPROM */ 6347 eecd |= E1000_EECD_CS; 6348 E1000_WRITE_REG(hw, EECD, eecd); 6349 E1000_WRITE_FLUSH(hw); 6350 usec_delay(eeprom->delay_usec); 6351 6352 /* Clock low */ 6353 eecd &= ~E1000_EECD_SK; 6354 E1000_WRITE_REG(hw, EECD, eecd); 6355 E1000_WRITE_FLUSH(hw); 6356 usec_delay(eeprom->delay_usec); 6357 } else if (eeprom->type == em_eeprom_spi) { 6358 /* Toggle CS to flush commands */ 6359 eecd |= E1000_EECD_CS; 6360 E1000_WRITE_REG(hw, EECD, eecd); 6361 E1000_WRITE_FLUSH(hw); 6362 usec_delay(eeprom->delay_usec); 6363 eecd &= ~E1000_EECD_CS; 6364 E1000_WRITE_REG(hw, EECD, eecd); 6365 E1000_WRITE_FLUSH(hw); 6366 usec_delay(eeprom->delay_usec); 6367 } 6368 } 6369 6370 /****************************************************************************** 6371 * Terminates a command by inverting the EEPROM's chip select pin 6372 * 6373 * hw - Struct containing variables accessed by shared code 6374 *****************************************************************************/ 6375 static void 6376 em_release_eeprom(struct em_hw *hw) 6377 { 6378 uint32_t eecd; 6379 DEBUGFUNC("em_release_eeprom"); 6380 6381 eecd = E1000_READ_REG(hw, EECD); 6382 6383 if (hw->eeprom.type == em_eeprom_spi) { 6384 eecd |= E1000_EECD_CS; /* Pull CS high */ 6385 eecd &= ~E1000_EECD_SK; /* Lower SCK */ 6386 6387 E1000_WRITE_REG(hw, EECD, eecd); 6388 6389 usec_delay(hw->eeprom.delay_usec); 6390 } else if (hw->eeprom.type == em_eeprom_microwire) { 6391 /* cleanup eeprom */ 6392 6393 /* CS on Microwire is active-high */ 6394 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); 6395 6396 E1000_WRITE_REG(hw, EECD, eecd); 6397 6398 /* Rising edge of clock */ 6399 eecd |= E1000_EECD_SK; 6400 E1000_WRITE_REG(hw, EECD, eecd); 6401 E1000_WRITE_FLUSH(hw); 6402 usec_delay(hw->eeprom.delay_usec); 6403 6404 /* Falling edge of clock */ 6405 eecd &= ~E1000_EECD_SK; 6406 E1000_WRITE_REG(hw, EECD, eecd); 6407 E1000_WRITE_FLUSH(hw); 6408 usec_delay(hw->eeprom.delay_usec); 6409 } 6410 /* Stop requesting EEPROM access */ 6411 if (hw->mac_type > em_82544) { 6412 eecd &= ~E1000_EECD_REQ; 6413 E1000_WRITE_REG(hw, EECD, eecd); 6414 } 6415 em_swfw_sync_release(hw, E1000_SWFW_EEP_SM); 6416 } 6417 6418 /****************************************************************************** 6419 * Reads a 16 bit word from the EEPROM. 6420 * 6421 * hw - Struct containing variables accessed by shared code 6422 *****************************************************************************/ 6423 STATIC int32_t 6424 em_spi_eeprom_ready(struct em_hw *hw) 6425 { 6426 uint16_t retry_count = 0; 6427 uint8_t spi_stat_reg; 6428 DEBUGFUNC("em_spi_eeprom_ready"); 6429 /* 6430 * Read "Status Register" repeatedly until the LSB is cleared. The 6431 * EEPROM will signal that the command has been completed by clearing 6432 * bit 0 of the internal status register. If it's not cleared within 6433 * 5 milliseconds, then error out. 6434 */ 6435 retry_count = 0; 6436 do { 6437 em_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI, 6438 hw->eeprom.opcode_bits); 6439 spi_stat_reg = (uint8_t) em_shift_in_ee_bits(hw, 8); 6440 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI)) 6441 break; 6442 6443 usec_delay(5); 6444 retry_count += 5; 6445 6446 em_standby_eeprom(hw); 6447 } while (retry_count < EEPROM_MAX_RETRY_SPI); 6448 /* 6449 * ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and 6450 * only 0-5mSec on 5V devices) 6451 */ 6452 if (retry_count >= EEPROM_MAX_RETRY_SPI) { 6453 DEBUGOUT("SPI EEPROM Status error\n"); 6454 return -E1000_ERR_EEPROM; 6455 } 6456 return E1000_SUCCESS; 6457 } 6458 6459 /****************************************************************************** 6460 * Reads a 16 bit word from the EEPROM. 6461 * 6462 * hw - Struct containing variables accessed by shared code 6463 * offset - offset of word in the EEPROM to read 6464 * data - word read from the EEPROM 6465 * words - number of words to read 6466 *****************************************************************************/ 6467 int32_t 6468 em_read_eeprom(struct em_hw *hw, uint16_t offset, uint16_t words, 6469 uint16_t *data) 6470 { 6471 struct em_eeprom_info *eeprom = &hw->eeprom; 6472 uint32_t i = 0; 6473 DEBUGFUNC("em_read_eeprom"); 6474 6475 /* If eeprom is not yet detected, do so now */ 6476 if (eeprom->word_size == 0) 6477 em_init_eeprom_params(hw); 6478 /* 6479 * A check for invalid values: offset too large, too many words, and 6480 * not enough words. 6481 */ 6482 if ((offset >= eeprom->word_size) || 6483 (words > eeprom->word_size - offset) || 6484 (words == 0)) { 6485 DEBUGOUT2("\"words\" parameter out of bounds. Words = %d," 6486 " size = %d\n", offset, eeprom->word_size); 6487 return -E1000_ERR_EEPROM; 6488 } 6489 /* 6490 * EEPROM's that don't use EERD to read require us to bit-bang the 6491 * SPI directly. In this case, we need to acquire the EEPROM so that 6492 * FW or other port software does not interrupt. 6493 */ 6494 if (em_is_onboard_nvm_eeprom(hw) == TRUE && 6495 em_get_flash_presence_i210(hw) == TRUE && 6496 hw->eeprom.use_eerd == FALSE) { 6497 /* Prepare the EEPROM for bit-bang reading */ 6498 if (em_acquire_eeprom(hw) != E1000_SUCCESS) 6499 return -E1000_ERR_EEPROM; 6500 } 6501 /* Eerd register EEPROM access requires no eeprom aquire/release */ 6502 if (eeprom->use_eerd == TRUE) 6503 return em_read_eeprom_eerd(hw, offset, words, data); 6504 6505 /* ICH EEPROM access is done via the ICH flash controller */ 6506 if (eeprom->type == em_eeprom_ich8) 6507 return em_read_eeprom_ich8(hw, offset, words, data); 6508 6509 /* Some i210/i211 have a special OTP chip */ 6510 if (eeprom->type == em_eeprom_invm) 6511 return em_read_invm_i210(hw, offset, words, data); 6512 6513 /* 6514 * Set up the SPI or Microwire EEPROM for bit-bang reading. We have 6515 * acquired the EEPROM at this point, so any returns should relase it 6516 */ 6517 if (eeprom->type == em_eeprom_spi) { 6518 uint16_t word_in; 6519 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI; 6520 if (em_spi_eeprom_ready(hw)) { 6521 em_release_eeprom(hw); 6522 return -E1000_ERR_EEPROM; 6523 } 6524 em_standby_eeprom(hw); 6525 /* 6526 * Some SPI eeproms use the 8th address bit embedded in the 6527 * opcode 6528 */ 6529 if ((eeprom->address_bits == 8) && (offset >= 128)) 6530 read_opcode |= EEPROM_A8_OPCODE_SPI; 6531 6532 /* Send the READ command (opcode + addr) */ 6533 em_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits); 6534 em_shift_out_ee_bits(hw, (uint16_t) (offset * 2), 6535 eeprom->address_bits); 6536 /* 6537 * Read the data. The address of the eeprom internally 6538 * increments with each byte (spi) being read, saving on the 6539 * overhead of eeprom setup and tear-down. The address 6540 * counter will roll over if reading beyond the size of the 6541 * eeprom, thus allowing the entire memory to be read 6542 * starting from any offset. 6543 */ 6544 for (i = 0; i < words; i++) { 6545 word_in = em_shift_in_ee_bits(hw, 16); 6546 data[i] = (word_in >> 8) | (word_in << 8); 6547 } 6548 } else if (eeprom->type == em_eeprom_microwire) { 6549 for (i = 0; i < words; i++) { 6550 /* Send the READ command (opcode + addr) */ 6551 em_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE, 6552 eeprom->opcode_bits); 6553 em_shift_out_ee_bits(hw, (uint16_t) (offset + i), 6554 eeprom->address_bits); 6555 /* 6556 * Read the data. For microwire, each word requires 6557 * the overhead of eeprom setup and tear-down. 6558 */ 6559 data[i] = em_shift_in_ee_bits(hw, 16); 6560 em_standby_eeprom(hw); 6561 } 6562 } 6563 /* End this read operation */ 6564 em_release_eeprom(hw); 6565 6566 return E1000_SUCCESS; 6567 } 6568 6569 /****************************************************************************** 6570 * Reads a 16 bit word from the EEPROM using the EERD register. 6571 * 6572 * hw - Struct containing variables accessed by shared code 6573 * offset - offset of word in the EEPROM to read 6574 * data - word read from the EEPROM 6575 * words - number of words to read 6576 *****************************************************************************/ 6577 STATIC int32_t 6578 em_read_eeprom_eerd(struct em_hw *hw, uint16_t offset, uint16_t words, 6579 uint16_t *data) 6580 { 6581 uint32_t i, eerd = 0; 6582 int32_t error = 0; 6583 for (i = 0; i < words; i++) { 6584 eerd = ((offset + i) << E1000_EEPROM_RW_ADDR_SHIFT) + 6585 E1000_EEPROM_RW_REG_START; 6586 6587 E1000_WRITE_REG(hw, EERD, eerd); 6588 error = em_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ); 6589 6590 if (error) { 6591 break; 6592 } 6593 data[i] = (E1000_READ_REG(hw, EERD) >> 6594 E1000_EEPROM_RW_REG_DATA); 6595 6596 } 6597 6598 return error; 6599 } 6600 6601 /****************************************************************************** 6602 * Writes a 16 bit word from the EEPROM using the EEWR register. 6603 * 6604 * hw - Struct containing variables accessed by shared code 6605 * offset - offset of word in the EEPROM to read 6606 * data - word read from the EEPROM 6607 * words - number of words to read 6608 *****************************************************************************/ 6609 STATIC int32_t 6610 em_write_eeprom_eewr(struct em_hw *hw, uint16_t offset, uint16_t words, 6611 uint16_t *data) 6612 { 6613 uint32_t register_value = 0; 6614 uint32_t i = 0; 6615 int32_t error = 0; 6616 if (em_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM)) 6617 return -E1000_ERR_SWFW_SYNC; 6618 6619 for (i = 0; i < words; i++) { 6620 register_value = (data[i] << E1000_EEPROM_RW_REG_DATA) | 6621 ((offset + i) << E1000_EEPROM_RW_ADDR_SHIFT) | 6622 E1000_EEPROM_RW_REG_START; 6623 6624 error = em_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE); 6625 if (error) { 6626 break; 6627 } 6628 E1000_WRITE_REG(hw, EEWR, register_value); 6629 6630 error = em_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE); 6631 6632 if (error) { 6633 break; 6634 } 6635 } 6636 6637 em_swfw_sync_release(hw, E1000_SWFW_EEP_SM); 6638 return error; 6639 } 6640 6641 /****************************************************************************** 6642 * Polls the status bit (bit 1) of the EERD to determine when the read is done. 6643 * 6644 * hw - Struct containing variables accessed by shared code 6645 *****************************************************************************/ 6646 STATIC int32_t 6647 em_poll_eerd_eewr_done(struct em_hw *hw, int eerd) 6648 { 6649 uint32_t attempts = 100000; 6650 uint32_t i, reg = 0; 6651 int32_t done = E1000_ERR_EEPROM; 6652 for (i = 0; i < attempts; i++) { 6653 if (eerd == E1000_EEPROM_POLL_READ) 6654 reg = E1000_READ_REG(hw, EERD); 6655 else 6656 reg = E1000_READ_REG(hw, EEWR); 6657 6658 if (reg & E1000_EEPROM_RW_REG_DONE) { 6659 done = E1000_SUCCESS; 6660 break; 6661 } 6662 usec_delay(5); 6663 } 6664 6665 return done; 6666 } 6667 6668 /****************************************************************************** 6669 * Description: Determines if the onboard NVM is FLASH or EEPROM. 6670 * 6671 * hw - Struct containing variables accessed by shared code 6672 *****************************************************************************/ 6673 STATIC boolean_t 6674 em_is_onboard_nvm_eeprom(struct em_hw *hw) 6675 { 6676 uint32_t eecd = 0; 6677 DEBUGFUNC("em_is_onboard_nvm_eeprom"); 6678 6679 if (IS_ICH8(hw->mac_type)) 6680 return FALSE; 6681 6682 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) { 6683 eecd = E1000_READ_REG(hw, EECD); 6684 6685 /* Isolate bits 15 & 16 */ 6686 eecd = ((eecd >> 15) & 0x03); 6687 6688 /* If both bits are set, device is Flash type */ 6689 if (eecd == 0x03) { 6690 return FALSE; 6691 } 6692 } 6693 return TRUE; 6694 } 6695 6696 /****************************************************************************** 6697 * Check if flash device is detected. 6698 * 6699 * hw - Struct containing variables accessed by shared code 6700 *****************************************************************************/ 6701 boolean_t 6702 em_get_flash_presence_i210(struct em_hw *hw) 6703 { 6704 uint32_t eecd; 6705 DEBUGFUNC("em_get_flash_presence_i210"); 6706 6707 if (hw->mac_type != em_i210) 6708 return TRUE; 6709 6710 eecd = E1000_READ_REG(hw, EECD); 6711 6712 if (eecd & E1000_EECD_FLUPD) 6713 return TRUE; 6714 6715 return FALSE; 6716 } 6717 6718 /****************************************************************************** 6719 * Verifies that the EEPROM has a valid checksum 6720 * 6721 * hw - Struct containing variables accessed by shared code 6722 * 6723 * Reads the first 64 16 bit words of the EEPROM and sums the values read. 6724 * If the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is 6725 * valid. 6726 *****************************************************************************/ 6727 int32_t 6728 em_validate_eeprom_checksum(struct em_hw *hw) 6729 { 6730 uint16_t checksum = 0; 6731 uint16_t i, eeprom_data; 6732 uint16_t checksum_reg; 6733 DEBUGFUNC("em_validate_eeprom_checksum"); 6734 6735 checksum_reg = hw->mac_type != em_icp_xxxx ? 6736 EEPROM_CHECKSUM_REG : 6737 EEPROM_CHECKSUM_REG_ICP_xxxx; 6738 6739 if (((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) && 6740 (em_is_onboard_nvm_eeprom(hw) == FALSE)) { 6741 /* 6742 * Check bit 4 of word 10h. If it is 0, firmware is done 6743 * updating 10h-12h. Checksum may need to be fixed. 6744 */ 6745 em_read_eeprom(hw, 0x10, 1, &eeprom_data); 6746 if ((eeprom_data & 0x10) == 0) { 6747 /* 6748 * Read 0x23 and check bit 15. This bit is a 1 when 6749 * the checksum has already been fixed. If the 6750 * checksum is still wrong and this bit is a 1, we 6751 * need to return bad checksum. Otherwise, we need 6752 * to set this bit to a 1 and update the checksum. 6753 */ 6754 em_read_eeprom(hw, 0x23, 1, &eeprom_data); 6755 if ((eeprom_data & 0x8000) == 0) { 6756 eeprom_data |= 0x8000; 6757 em_write_eeprom(hw, 0x23, 1, &eeprom_data); 6758 em_update_eeprom_checksum(hw); 6759 } 6760 } 6761 } 6762 if (IS_ICH8(hw->mac_type)) { 6763 uint16_t word; 6764 uint16_t valid_csum_mask; 6765 6766 /* 6767 * Drivers must allocate the shadow ram structure for the 6768 * EEPROM checksum to be updated. Otherwise, this bit as 6769 * well as the checksum must both be set correctly for this 6770 * validation to pass. 6771 */ 6772 switch (hw->mac_type) { 6773 case em_pch_lpt: 6774 case em_pch_spt: 6775 case em_pch_cnp: 6776 word = EEPROM_COMPAT; 6777 valid_csum_mask = EEPROM_COMPAT_VALID_CSUM; 6778 break; 6779 default: 6780 word = EEPROM_FUTURE_INIT_WORD1; 6781 valid_csum_mask = EEPROM_FUTURE_INIT_WORD1_VALID_CSUM; 6782 break; 6783 } 6784 em_read_eeprom(hw, word, 1, &eeprom_data); 6785 if ((eeprom_data & valid_csum_mask) == 0) { 6786 eeprom_data |= valid_csum_mask; 6787 em_write_eeprom(hw, word, 1, &eeprom_data); 6788 em_update_eeprom_checksum(hw); 6789 } 6790 } 6791 for (i = 0; i < (checksum_reg + 1); i++) { 6792 if (em_read_eeprom(hw, i, 1, &eeprom_data) < 0) { 6793 DEBUGOUT("EEPROM Read Error\n"); 6794 return -E1000_ERR_EEPROM; 6795 } 6796 checksum += eeprom_data; 6797 } 6798 6799 if (checksum == (uint16_t) EEPROM_SUM) 6800 return E1000_SUCCESS; 6801 else { 6802 DEBUGOUT("EEPROM Checksum Invalid\n"); 6803 return -E1000_ERR_EEPROM; 6804 } 6805 } 6806 6807 /****************************************************************************** 6808 * Calculates the EEPROM checksum and writes it to the EEPROM 6809 * 6810 * hw - Struct containing variables accessed by shared code 6811 * 6812 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA. 6813 * Writes the difference to word offset 63 of the EEPROM. 6814 *****************************************************************************/ 6815 int32_t 6816 em_update_eeprom_checksum(struct em_hw *hw) 6817 { 6818 uint32_t ctrl_ext; 6819 uint16_t checksum = 0; 6820 uint16_t i, eeprom_data; 6821 DEBUGFUNC("em_update_eeprom_checksum"); 6822 6823 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) { 6824 if (em_read_eeprom(hw, i, 1, &eeprom_data) < 0) { 6825 DEBUGOUT("EEPROM Read Error\n"); 6826 return -E1000_ERR_EEPROM; 6827 } 6828 checksum += eeprom_data; 6829 } 6830 checksum = (uint16_t) EEPROM_SUM - checksum; 6831 if (em_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) { 6832 DEBUGOUT("EEPROM Write Error\n"); 6833 return -E1000_ERR_EEPROM; 6834 } else if (hw->eeprom.type == em_eeprom_flash) { 6835 em_commit_shadow_ram(hw); 6836 } else if (hw->eeprom.type == em_eeprom_ich8) { 6837 em_commit_shadow_ram(hw); 6838 /* 6839 * Reload the EEPROM, or else modifications will not appear 6840 * until after next adapter reset. 6841 */ 6842 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 6843 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 6844 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 6845 msec_delay(10); 6846 } 6847 return E1000_SUCCESS; 6848 } 6849 6850 /****************************************************************************** 6851 * Parent function for writing words to the different EEPROM types. 6852 * 6853 * hw - Struct containing variables accessed by shared code 6854 * offset - offset within the EEPROM to be written to 6855 * words - number of words to write 6856 * data - 16 bit word to be written to the EEPROM 6857 * 6858 * If em_update_eeprom_checksum is not called after this function, the 6859 * EEPROM will most likely contain an invalid checksum. 6860 *****************************************************************************/ 6861 int32_t 6862 em_write_eeprom(struct em_hw *hw, uint16_t offset, uint16_t words, 6863 uint16_t *data) 6864 { 6865 struct em_eeprom_info *eeprom = &hw->eeprom; 6866 int32_t status = 0; 6867 DEBUGFUNC("em_write_eeprom"); 6868 6869 /* If eeprom is not yet detected, do so now */ 6870 if (eeprom->word_size == 0) 6871 em_init_eeprom_params(hw); 6872 /* 6873 * A check for invalid values: offset too large, too many words, and 6874 * not enough words. 6875 */ 6876 if ((offset >= eeprom->word_size) || 6877 (words > eeprom->word_size - offset) || 6878 (words == 0)) { 6879 DEBUGOUT("\"words\" parameter out of bounds\n"); 6880 return -E1000_ERR_EEPROM; 6881 } 6882 /* 82573/4 writes only through eewr */ 6883 if (eeprom->use_eewr == TRUE) 6884 return em_write_eeprom_eewr(hw, offset, words, data); 6885 6886 if (eeprom->type == em_eeprom_ich8) 6887 return em_write_eeprom_ich8(hw, offset, words, data); 6888 6889 /* Prepare the EEPROM for writing */ 6890 if (em_acquire_eeprom(hw) != E1000_SUCCESS) 6891 return -E1000_ERR_EEPROM; 6892 6893 if (eeprom->type == em_eeprom_microwire) { 6894 status = em_write_eeprom_microwire(hw, offset, words, data); 6895 } else { 6896 status = em_write_eeprom_spi(hw, offset, words, data); 6897 msec_delay(10); 6898 } 6899 6900 /* Done with writing */ 6901 em_release_eeprom(hw); 6902 6903 return status; 6904 } 6905 6906 /****************************************************************************** 6907 * Writes a 16 bit word to a given offset in an SPI EEPROM. 6908 * 6909 * hw - Struct containing variables accessed by shared code 6910 * offset - offset within the EEPROM to be written to 6911 * words - number of words to write 6912 * data - pointer to array of 8 bit words to be written to the EEPROM 6913 * 6914 *****************************************************************************/ 6915 STATIC int32_t 6916 em_write_eeprom_spi(struct em_hw *hw, uint16_t offset, uint16_t words, 6917 uint16_t *data) 6918 { 6919 struct em_eeprom_info *eeprom = &hw->eeprom; 6920 uint16_t widx = 0; 6921 DEBUGFUNC("em_write_eeprom_spi"); 6922 6923 while (widx < words) { 6924 uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI; 6925 if (em_spi_eeprom_ready(hw)) 6926 return -E1000_ERR_EEPROM; 6927 6928 em_standby_eeprom(hw); 6929 6930 /* Send the WRITE ENABLE command (8 bit opcode ) */ 6931 em_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI, 6932 eeprom->opcode_bits); 6933 6934 em_standby_eeprom(hw); 6935 /* 6936 * Some SPI eeproms use the 8th address bit embedded in the 6937 * opcode 6938 */ 6939 if ((eeprom->address_bits == 8) && (offset >= 128)) 6940 write_opcode |= EEPROM_A8_OPCODE_SPI; 6941 6942 /* Send the Write command (8-bit opcode + addr) */ 6943 em_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits); 6944 6945 em_shift_out_ee_bits(hw, (uint16_t) ((offset + widx) * 2), 6946 eeprom->address_bits); 6947 6948 /* Send the data */ 6949 /* 6950 * Loop to allow for up to whole page write (32 bytes) of 6951 * eeprom 6952 */ 6953 while (widx < words) { 6954 uint16_t word_out = data[widx]; 6955 word_out = (word_out >> 8) | (word_out << 8); 6956 em_shift_out_ee_bits(hw, word_out, 16); 6957 widx++; 6958 /* 6959 * Some larger eeprom sizes are capable of a 32-byte 6960 * PAGE WRITE operation, while the smaller eeproms 6961 * are capable of an 8-byte PAGE WRITE operation. 6962 * Break the inner loop to pass new address 6963 */ 6964 if ((((offset + widx) * 2) % eeprom->page_size) == 0) { 6965 em_standby_eeprom(hw); 6966 break; 6967 } 6968 } 6969 } 6970 6971 return E1000_SUCCESS; 6972 } 6973 6974 /****************************************************************************** 6975 * Writes a 16 bit word to a given offset in a Microwire EEPROM. 6976 * 6977 * hw - Struct containing variables accessed by shared code 6978 * offset - offset within the EEPROM to be written to 6979 * words - number of words to write 6980 * data - pointer to array of 16 bit words to be written to the EEPROM 6981 * 6982 *****************************************************************************/ 6983 STATIC int32_t 6984 em_write_eeprom_microwire(struct em_hw *hw, uint16_t offset, uint16_t words, 6985 uint16_t *data) 6986 { 6987 struct em_eeprom_info *eeprom = &hw->eeprom; 6988 uint32_t eecd; 6989 uint16_t words_written = 0; 6990 uint16_t i = 0; 6991 DEBUGFUNC("em_write_eeprom_microwire"); 6992 /* 6993 * Send the write enable command to the EEPROM (3-bit opcode plus 6994 * 6/8-bit dummy address beginning with 11). It's less work to 6995 * include the 11 of the dummy address as part of the opcode than it 6996 * is to shift it over the correct number of bits for the address. 6997 * This puts the EEPROM into write/erase mode. 6998 */ 6999 em_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE, 7000 (uint16_t) (eeprom->opcode_bits + 2)); 7001 7002 em_shift_out_ee_bits(hw, 0, (uint16_t) (eeprom->address_bits - 2)); 7003 7004 /* Prepare the EEPROM */ 7005 em_standby_eeprom(hw); 7006 7007 while (words_written < words) { 7008 /* Send the Write command (3-bit opcode + addr) */ 7009 em_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE, 7010 eeprom->opcode_bits); 7011 7012 em_shift_out_ee_bits(hw, (uint16_t) (offset + words_written), 7013 eeprom->address_bits); 7014 7015 /* Send the data */ 7016 em_shift_out_ee_bits(hw, data[words_written], 16); 7017 /* 7018 * Toggle the CS line. This in effect tells the EEPROM to 7019 * execute the previous command. 7020 */ 7021 em_standby_eeprom(hw); 7022 /* 7023 * Read DO repeatedly until it is high (equal to '1'). The 7024 * EEPROM will signal that the command has been completed by 7025 * raising the DO signal. If DO does not go high in 10 7026 * milliseconds, then error out. 7027 */ 7028 for (i = 0; i < 200; i++) { 7029 eecd = E1000_READ_REG(hw, EECD); 7030 if (eecd & E1000_EECD_DO) 7031 break; 7032 usec_delay(50); 7033 } 7034 if (i == 200) { 7035 DEBUGOUT("EEPROM Write did not complete\n"); 7036 return -E1000_ERR_EEPROM; 7037 } 7038 /* Recover from write */ 7039 em_standby_eeprom(hw); 7040 7041 words_written++; 7042 } 7043 /* 7044 * Send the write disable command to the EEPROM (3-bit opcode plus 7045 * 6/8-bit dummy address beginning with 10). It's less work to 7046 * include the 10 of the dummy address as part of the opcode than it 7047 * is to shift it over the correct number of bits for the address. 7048 * This takes the EEPROM out of write/erase mode. 7049 */ 7050 em_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE, 7051 (uint16_t) (eeprom->opcode_bits + 2)); 7052 7053 em_shift_out_ee_bits(hw, 0, (uint16_t) (eeprom->address_bits - 2)); 7054 7055 return E1000_SUCCESS; 7056 } 7057 7058 /****************************************************************************** 7059 * Flushes the cached eeprom to NVM. This is done by saving the modified values 7060 * in the eeprom cache and the non modified values in the currently active bank 7061 * to the new bank. 7062 * 7063 * hw - Struct containing variables accessed by shared code 7064 * offset - offset of word in the EEPROM to read 7065 * data - word read from the EEPROM 7066 * words - number of words to read 7067 *****************************************************************************/ 7068 STATIC int32_t 7069 em_commit_shadow_ram(struct em_hw *hw) 7070 { 7071 uint32_t attempts = 100000; 7072 uint32_t eecd = 0; 7073 uint32_t flop = 0; 7074 uint32_t i = 0; 7075 int32_t error = E1000_SUCCESS; 7076 uint32_t old_bank_offset = 0; 7077 uint32_t new_bank_offset = 0; 7078 uint8_t low_byte = 0; 7079 uint8_t high_byte = 0; 7080 boolean_t sector_write_failed = FALSE; 7081 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) { 7082 /* 7083 * The flop register will be used to determine if flash type 7084 * is STM 7085 */ 7086 flop = E1000_READ_REG(hw, FLOP); 7087 for (i = 0; i < attempts; i++) { 7088 eecd = E1000_READ_REG(hw, EECD); 7089 if ((eecd & E1000_EECD_FLUPD) == 0) { 7090 break; 7091 } 7092 usec_delay(5); 7093 } 7094 7095 if (i == attempts) { 7096 return -E1000_ERR_EEPROM; 7097 } 7098 /* 7099 * If STM opcode located in bits 15:8 of flop, reset firmware 7100 */ 7101 if ((flop & 0xFF00) == E1000_STM_OPCODE) { 7102 E1000_WRITE_REG(hw, HICR, E1000_HICR_FW_RESET); 7103 } 7104 /* Perform the flash update */ 7105 E1000_WRITE_REG(hw, EECD, eecd | E1000_EECD_FLUPD); 7106 7107 for (i = 0; i < attempts; i++) { 7108 eecd = E1000_READ_REG(hw, EECD); 7109 if ((eecd & E1000_EECD_FLUPD) == 0) { 7110 break; 7111 } 7112 usec_delay(5); 7113 } 7114 7115 if (i == attempts) { 7116 return -E1000_ERR_EEPROM; 7117 } 7118 } 7119 if ((hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) && 7120 hw->eeprom_shadow_ram != NULL) { 7121 /* 7122 * We're writing to the opposite bank so if we're on bank 1, 7123 * write to bank 0 etc. We also need to erase the segment 7124 * that is going to be written 7125 */ 7126 if (!(E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL)) { 7127 new_bank_offset = hw->flash_bank_size * 2; 7128 old_bank_offset = 0; 7129 em_erase_ich8_4k_segment(hw, 1); 7130 } else { 7131 old_bank_offset = hw->flash_bank_size * 2; 7132 new_bank_offset = 0; 7133 em_erase_ich8_4k_segment(hw, 0); 7134 } 7135 7136 sector_write_failed = FALSE; 7137 /* 7138 * Loop for every byte in the shadow RAM, which is in units 7139 * of words. 7140 */ 7141 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 7142 /* 7143 * Determine whether to write the value stored in the 7144 * other NVM bank or a modified value stored in the 7145 * shadow RAM 7146 */ 7147 if (hw->eeprom_shadow_ram[i].modified == TRUE) { 7148 low_byte = (uint8_t) 7149 hw->eeprom_shadow_ram[i].eeprom_word; 7150 usec_delay(100); 7151 error = em_verify_write_ich8_byte(hw, 7152 (i << 1) + new_bank_offset, low_byte); 7153 7154 if (error != E1000_SUCCESS) 7155 sector_write_failed = TRUE; 7156 else { 7157 high_byte = (uint8_t) 7158 (hw->eeprom_shadow_ram 7159 [i].eeprom_word >> 8); 7160 usec_delay(100); 7161 } 7162 } else { 7163 em_read_ich8_byte(hw, (i << 1) + 7164 old_bank_offset, &low_byte); 7165 usec_delay(100); 7166 error = em_verify_write_ich8_byte(hw, 7167 (i << 1) + new_bank_offset, low_byte); 7168 7169 if (error != E1000_SUCCESS) 7170 sector_write_failed = TRUE; 7171 else { 7172 em_read_ich8_byte(hw, (i << 1) + 7173 old_bank_offset + 1, &high_byte); 7174 usec_delay(100); 7175 } 7176 } 7177 /* 7178 * If the write of the low byte was successful, go 7179 * ahread and write the high byte while checking to 7180 * make sure that if it is the signature byte, then 7181 * it is handled properly 7182 */ 7183 if (sector_write_failed == FALSE) { 7184 /* 7185 * If the word is 0x13, then make sure the 7186 * signature bits (15:14) are 11b until the 7187 * commit has completed. This will allow us 7188 * to write 10b which indicates the signature 7189 * is valid. We want to do this after the 7190 * write has completed so that we don't mark 7191 * the segment valid while the write is still 7192 * in progress 7193 */ 7194 if (i == E1000_ICH_NVM_SIG_WORD) 7195 high_byte = E1000_ICH_NVM_VALID_SIG_MASK | 7196 high_byte; 7197 7198 error = em_verify_write_ich8_byte(hw, (i << 1) 7199 + new_bank_offset + 1, high_byte); 7200 if (error != E1000_SUCCESS) 7201 sector_write_failed = TRUE; 7202 7203 } else { 7204 /* 7205 * If the write failed then break from the 7206 * loop and return an error 7207 */ 7208 break; 7209 } 7210 } 7211 /* 7212 * Don't bother writing the segment valid bits if sector 7213 * programming failed. 7214 */ 7215 if (sector_write_failed == FALSE) { 7216 /* 7217 * Finally validate the new segment by setting bit 7218 * 15:14 to 10b in word 0x13 , this can be done 7219 * without an erase as well since these bits are 11 7220 * to start with and we need to change bit 14 to 0b 7221 */ 7222 em_read_ich8_byte(hw, E1000_ICH_NVM_SIG_WORD * 2 + 1 + 7223 new_bank_offset, &high_byte); 7224 high_byte &= 0xBF; 7225 error = em_verify_write_ich8_byte(hw, 7226 E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset, 7227 high_byte); 7228 /* 7229 * And invalidate the previously valid segment by 7230 * setting its signature word (0x13) high_byte to 0b. 7231 * This can be done without an erase because flash 7232 * erase sets all bits to 1's. We can write 1's to 7233 * 0's without an erase 7234 */ 7235 if (error == E1000_SUCCESS) { 7236 error = em_verify_write_ich8_byte(hw, 7237 E1000_ICH_NVM_SIG_WORD * 2 + 1 + 7238 old_bank_offset, 0); 7239 } 7240 /* Clear the now not used entry in the cache */ 7241 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 7242 hw->eeprom_shadow_ram[i].modified = FALSE; 7243 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF; 7244 } 7245 } 7246 } 7247 return error; 7248 } 7249 7250 /****************************************************************************** 7251 * Reads the adapter's part number from the EEPROM 7252 * 7253 * hw - Struct containing variables accessed by shared code 7254 * part_num - Adapter's part number 7255 *****************************************************************************/ 7256 int32_t 7257 em_read_part_num(struct em_hw *hw, uint32_t *part_num) 7258 { 7259 uint16_t offset = EEPROM_PBA_BYTE_1; 7260 uint16_t eeprom_data; 7261 DEBUGFUNC("em_read_part_num"); 7262 7263 /* Get word 0 from EEPROM */ 7264 if (em_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { 7265 DEBUGOUT("EEPROM Read Error\n"); 7266 return -E1000_ERR_EEPROM; 7267 } 7268 /* Save word 0 in upper half of part_num */ 7269 *part_num = (uint32_t) (eeprom_data << 16); 7270 7271 /* Get word 1 from EEPROM */ 7272 if (em_read_eeprom(hw, ++offset, 1, &eeprom_data) < 0) { 7273 DEBUGOUT("EEPROM Read Error\n"); 7274 return -E1000_ERR_EEPROM; 7275 } 7276 /* Save word 1 in lower half of part_num */ 7277 *part_num |= eeprom_data; 7278 7279 return E1000_SUCCESS; 7280 } 7281 7282 /****************************************************************************** 7283 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the 7284 * second function of dual function devices 7285 * 7286 * hw - Struct containing variables accessed by shared code 7287 *****************************************************************************/ 7288 int32_t 7289 em_read_mac_addr(struct em_hw *hw) 7290 { 7291 uint16_t offset; 7292 uint16_t eeprom_data, i; 7293 uint16_t ia_base_addr = 0; 7294 DEBUGFUNC("em_read_mac_addr"); 7295 7296 if (hw->mac_type == em_icp_xxxx) { 7297 ia_base_addr = (uint16_t) 7298 EEPROM_IA_START_ICP_xxxx(hw->icp_xxxx_port_num); 7299 } else if (hw->mac_type == em_82580 || hw->mac_type == em_i350) { 7300 ia_base_addr = NVM_82580_LAN_FUNC_OFFSET(hw->bus_func); 7301 } 7302 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) { 7303 offset = i >> 1; 7304 if (em_read_eeprom(hw, offset + ia_base_addr, 1, &eeprom_data) 7305 < 0) { 7306 DEBUGOUT("EEPROM Read Error\n"); 7307 return -E1000_ERR_EEPROM; 7308 } 7309 hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF); 7310 hw->perm_mac_addr[i + 1] = (uint8_t) (eeprom_data >> 8); 7311 } 7312 7313 switch (hw->mac_type) { 7314 default: 7315 break; 7316 case em_82546: 7317 case em_82546_rev_3: 7318 case em_82571: 7319 case em_82575: 7320 case em_82576: 7321 case em_80003es2lan: 7322 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) 7323 hw->perm_mac_addr[5] ^= 0x01; 7324 break; 7325 } 7326 7327 for (i = 0; i < NODE_ADDRESS_SIZE; i++) 7328 hw->mac_addr[i] = hw->perm_mac_addr[i]; 7329 return E1000_SUCCESS; 7330 } 7331 7332 /****************************************************************************** 7333 * Explicitly disables jumbo frames and resets some PHY registers back to hw- 7334 * defaults. This is necessary in case the ethernet cable was inserted AFTER 7335 * the firmware initialized the PHY. Otherwise it is left in a state where 7336 * it is possible to transmit but not receive packets. Observed on I217-LM and 7337 * fixed in FreeBSD's sys/dev/e1000/e1000_ich8lan.c. 7338 * 7339 * hw - Struct containing variables accessed by shared code 7340 *****************************************************************************/ 7341 STATIC int32_t 7342 em_phy_no_cable_workaround(struct em_hw *hw) { 7343 int32_t ret_val, dft_ret_val; 7344 uint32_t mac_reg; 7345 uint16_t data, phy_reg; 7346 7347 /* disable Rx path while enabling workaround */ 7348 em_read_phy_reg(hw, I2_DFT_CTRL, &phy_reg); 7349 ret_val = em_write_phy_reg(hw, I2_DFT_CTRL, phy_reg | (1 << 14)); 7350 if (ret_val) 7351 return ret_val; 7352 7353 /* Write MAC register values back to h/w defaults */ 7354 mac_reg = E1000_READ_REG(hw, FFLT_DBG); 7355 mac_reg &= ~(0xF << 14); 7356 E1000_WRITE_REG(hw, FFLT_DBG, mac_reg); 7357 7358 mac_reg = E1000_READ_REG(hw, RCTL); 7359 mac_reg &= ~E1000_RCTL_SECRC; 7360 E1000_WRITE_REG(hw, RCTL, mac_reg); 7361 7362 ret_val = em_read_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_CTRL, &data); 7363 if (ret_val) 7364 goto out; 7365 ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_CTRL, 7366 data & ~(1 << 0)); 7367 if (ret_val) 7368 goto out; 7369 7370 ret_val = em_read_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL, &data); 7371 if (ret_val) 7372 goto out; 7373 7374 data &= ~(0xF << 8); 7375 data |= (0xB << 8); 7376 ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL, data); 7377 if (ret_val) 7378 goto out; 7379 7380 /* Write PHY register values back to h/w defaults */ 7381 em_read_phy_reg(hw, I2_SMBUS_CTRL, &data); 7382 data &= ~(0x7F << 5); 7383 ret_val = em_write_phy_reg(hw, I2_SMBUS_CTRL, data); 7384 if (ret_val) 7385 goto out; 7386 7387 em_read_phy_reg(hw, I2_MODE_CTRL, &data); 7388 data |= (1 << 13); 7389 ret_val = em_write_phy_reg(hw, I2_MODE_CTRL, data); 7390 if (ret_val) 7391 goto out; 7392 7393 /* 7394 * 776.20 and 776.23 are not documented in 7395 * i217-ethernet-controller-datasheet.pdf... 7396 */ 7397 em_read_phy_reg(hw, PHY_REG(776, 20), &data); 7398 data &= ~(0x3FF << 2); 7399 data |= (0x8 << 2); 7400 ret_val = em_write_phy_reg(hw, PHY_REG(776, 20), data); 7401 if (ret_val) 7402 goto out; 7403 7404 ret_val = em_write_phy_reg(hw, PHY_REG(776, 23), 0x7E00); 7405 if (ret_val) 7406 goto out; 7407 7408 em_read_phy_reg(hw, I2_PCIE_POWER_CTRL, &data); 7409 ret_val = em_write_phy_reg(hw, I2_PCIE_POWER_CTRL, data & ~(1 << 10)); 7410 if (ret_val) 7411 goto out; 7412 7413 out: 7414 /* re-enable Rx path after enabling workaround */ 7415 dft_ret_val = em_write_phy_reg(hw, I2_DFT_CTRL, phy_reg & ~(1 << 14)); 7416 if (ret_val) 7417 return ret_val; 7418 else 7419 return dft_ret_val; 7420 } 7421 7422 /****************************************************************************** 7423 * Initializes receive address filters. 7424 * 7425 * hw - Struct containing variables accessed by shared code 7426 * 7427 * Places the MAC address in receive address register 0 and clears the rest 7428 * of the receive addresss registers. Clears the multicast table. Assumes 7429 * the receiver is in reset when the routine is called. 7430 *****************************************************************************/ 7431 STATIC void 7432 em_init_rx_addrs(struct em_hw *hw) 7433 { 7434 uint32_t i; 7435 uint32_t rar_num; 7436 DEBUGFUNC("em_init_rx_addrs"); 7437 7438 if (hw->mac_type == em_pch_lpt || hw->mac_type == em_pch_spt || 7439 hw->mac_type == em_pch_cnp || hw->mac_type == em_pch2lan) 7440 if (em_phy_no_cable_workaround(hw)) 7441 printf(" ...failed to apply em_phy_no_cable_" 7442 "workaround.\n"); 7443 7444 /* Setup the receive address. */ 7445 DEBUGOUT("Programming MAC Address into RAR[0]\n"); 7446 7447 em_rar_set(hw, hw->mac_addr, 0); 7448 7449 rar_num = E1000_RAR_ENTRIES; 7450 /* 7451 * Reserve a spot for the Locally Administered Address to work around 7452 * an 82571 issue in which a reset on one port will reload the MAC on 7453 * the other port. 7454 */ 7455 if ((hw->mac_type == em_82571) && (hw->laa_is_present == TRUE)) 7456 rar_num -= 1; 7457 if (IS_ICH8(hw->mac_type)) 7458 rar_num = E1000_RAR_ENTRIES_ICH8LAN; 7459 if (hw->mac_type == em_ich8lan) 7460 rar_num -= 1; 7461 if (hw->mac_type == em_82580) 7462 rar_num = E1000_RAR_ENTRIES_82580; 7463 if (hw->mac_type == em_i210) 7464 rar_num = E1000_RAR_ENTRIES_82575; 7465 if (hw->mac_type == em_i350) 7466 rar_num = E1000_RAR_ENTRIES_I350; 7467 7468 /* Zero out the other 15 receive addresses. */ 7469 DEBUGOUT("Clearing RAR[1-15]\n"); 7470 for (i = 1; i < rar_num; i++) { 7471 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 7472 E1000_WRITE_FLUSH(hw); 7473 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 7474 E1000_WRITE_FLUSH(hw); 7475 } 7476 } 7477 7478 /****************************************************************************** 7479 * Updates the MAC's list of multicast addresses. 7480 * 7481 * hw - Struct containing variables accessed by shared code 7482 * mc_addr_list - the list of new multicast addresses 7483 * mc_addr_count - number of addresses 7484 * pad - number of bytes between addresses in the list 7485 * rar_used_count - offset where to start adding mc addresses into the RAR's 7486 * 7487 * The given list replaces any existing list. Clears the last 15 receive 7488 * address registers and the multicast table. Uses receive address registers 7489 * for the first 15 multicast addresses, and hashes the rest into the 7490 * multicast table. 7491 *****************************************************************************/ 7492 void 7493 em_mc_addr_list_update(struct em_hw *hw, uint8_t *mc_addr_list, 7494 uint32_t mc_addr_count, uint32_t pad, uint32_t rar_used_count) 7495 { 7496 uint32_t hash_value; 7497 uint32_t i; 7498 uint32_t num_rar_entry; 7499 uint32_t num_mta_entry; 7500 DEBUGFUNC("em_mc_addr_list_update"); 7501 /* 7502 * Set the new number of MC addresses that we are being requested to 7503 * use. 7504 */ 7505 hw->num_mc_addrs = mc_addr_count; 7506 7507 /* Clear RAR[1-15] */ 7508 DEBUGOUT(" Clearing RAR[1-15]\n"); 7509 num_rar_entry = E1000_RAR_ENTRIES; 7510 if (IS_ICH8(hw->mac_type)) 7511 num_rar_entry = E1000_RAR_ENTRIES_ICH8LAN; 7512 if (hw->mac_type == em_ich8lan) 7513 num_rar_entry -= 1; 7514 /* 7515 * Reserve a spot for the Locally Administered Address to work around 7516 * an 82571 issue in which a reset on one port will reload the MAC on 7517 * the other port. 7518 */ 7519 if ((hw->mac_type == em_82571) && (hw->laa_is_present == TRUE)) 7520 num_rar_entry -= 1; 7521 7522 for (i = rar_used_count; i < num_rar_entry; i++) { 7523 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 7524 E1000_WRITE_FLUSH(hw); 7525 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 7526 E1000_WRITE_FLUSH(hw); 7527 } 7528 7529 /* Clear the MTA */ 7530 DEBUGOUT(" Clearing MTA\n"); 7531 num_mta_entry = E1000_NUM_MTA_REGISTERS; 7532 if (IS_ICH8(hw->mac_type)) 7533 num_mta_entry = E1000_NUM_MTA_REGISTERS_ICH8LAN; 7534 7535 for (i = 0; i < num_mta_entry; i++) { 7536 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 7537 E1000_WRITE_FLUSH(hw); 7538 } 7539 7540 /* Add the new addresses */ 7541 for (i = 0; i < mc_addr_count; i++) { 7542 DEBUGOUT(" Adding the multicast addresses:\n"); 7543 DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i, 7544 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad)], 7545 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 1], 7546 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 2], 7547 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 3], 7548 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 4], 7549 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 5]); 7550 7551 hash_value = em_hash_mc_addr(hw, mc_addr_list + 7552 (i * (ETH_LENGTH_OF_ADDRESS + pad))); 7553 7554 DEBUGOUT1(" Hash value = 0x%03X\n", hash_value); 7555 /* 7556 * Place this multicast address in the RAR if there is room, * 7557 * else put it in the MTA 7558 */ 7559 if (rar_used_count < num_rar_entry) { 7560 em_rar_set(hw, mc_addr_list + 7561 (i * (ETH_LENGTH_OF_ADDRESS + pad)), 7562 rar_used_count); 7563 rar_used_count++; 7564 } else { 7565 em_mta_set(hw, hash_value); 7566 } 7567 } 7568 DEBUGOUT("MC Update Complete\n"); 7569 } 7570 7571 /****************************************************************************** 7572 * Hashes an address to determine its location in the multicast table 7573 * 7574 * hw - Struct containing variables accessed by shared code 7575 * mc_addr - the multicast address to hash 7576 *****************************************************************************/ 7577 uint32_t 7578 em_hash_mc_addr(struct em_hw *hw, uint8_t *mc_addr) 7579 { 7580 uint32_t hash_value = 0; 7581 /* 7582 * The portion of the address that is used for the hash table is 7583 * determined by the mc_filter_type setting. 7584 */ 7585 switch (hw->mc_filter_type) { 7586 /* 7587 * [0] [1] [2] [3] [4] [5] 01 AA 00 12 34 56 LSB 7588 * MSB 7589 */ 7590 case 0: 7591 if (IS_ICH8(hw->mac_type)) { 7592 /* [47:38] i.e. 0x158 for above example address */ 7593 hash_value = ((mc_addr[4] >> 6) | 7594 (((uint16_t) mc_addr[5]) << 2)); 7595 } else { 7596 /* [47:36] i.e. 0x563 for above example address */ 7597 hash_value = ((mc_addr[4] >> 4) | 7598 (((uint16_t) mc_addr[5]) << 4)); 7599 } 7600 break; 7601 case 1: 7602 if (IS_ICH8(hw->mac_type)) { 7603 /* [46:37] i.e. 0x2B1 for above example address */ 7604 hash_value = ((mc_addr[4] >> 5) | 7605 (((uint16_t) mc_addr[5]) << 3)); 7606 } else { 7607 /* [46:35] i.e. 0xAC6 for above example address */ 7608 hash_value = ((mc_addr[4] >> 3) | 7609 (((uint16_t) mc_addr[5]) << 5)); 7610 } 7611 break; 7612 case 2: 7613 if (IS_ICH8(hw->mac_type)) { 7614 /* [45:36] i.e. 0x163 for above example address */ 7615 hash_value = ((mc_addr[4] >> 4) | 7616 (((uint16_t) mc_addr[5]) << 4)); 7617 } else { 7618 /* [45:34] i.e. 0x5D8 for above example address */ 7619 hash_value = ((mc_addr[4] >> 2) | 7620 (((uint16_t) mc_addr[5]) << 6)); 7621 } 7622 break; 7623 case 3: 7624 if (IS_ICH8(hw->mac_type)) { 7625 /* [43:34] i.e. 0x18D for above example address */ 7626 hash_value = ((mc_addr[4] >> 2) | 7627 (((uint16_t) mc_addr[5]) << 6)); 7628 } else { 7629 /* [43:32] i.e. 0x634 for above example address */ 7630 hash_value = ((mc_addr[4]) | 7631 (((uint16_t) mc_addr[5]) << 8)); 7632 } 7633 break; 7634 } 7635 7636 hash_value &= 0xFFF; 7637 if (IS_ICH8(hw->mac_type)) 7638 hash_value &= 0x3FF; 7639 7640 return hash_value; 7641 } 7642 7643 /****************************************************************************** 7644 * Sets the bit in the multicast table corresponding to the hash value. 7645 * 7646 * hw - Struct containing variables accessed by shared code 7647 * hash_value - Multicast address hash value 7648 *****************************************************************************/ 7649 void 7650 em_mta_set(struct em_hw *hw, uint32_t hash_value) 7651 { 7652 uint32_t hash_bit, hash_reg; 7653 uint32_t mta; 7654 uint32_t temp; 7655 /* 7656 * The MTA is a register array of 128 32-bit registers. It is treated 7657 * like an array of 4096 bits. We want to set bit 7658 * BitArray[hash_value]. So we figure out what register the bit is 7659 * in, read it, OR in the new bit, then write back the new value. 7660 * The register is determined by the upper 7 bits of the hash value 7661 * and the bit within that register are determined by the lower 5 7662 * bits of the value. 7663 */ 7664 hash_reg = (hash_value >> 5) & 0x7F; 7665 if (IS_ICH8(hw->mac_type)) 7666 hash_reg &= 0x1F; 7667 7668 hash_bit = hash_value & 0x1F; 7669 7670 mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg); 7671 7672 mta |= (1 << hash_bit); 7673 /* 7674 * If we are on an 82544 and we are trying to write an odd offset in 7675 * the MTA, save off the previous entry before writing and restore 7676 * the old value after writing. 7677 */ 7678 if ((hw->mac_type == em_82544) && ((hash_reg & 0x1) == 1)) { 7679 temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1)); 7680 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta); 7681 E1000_WRITE_FLUSH(hw); 7682 E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp); 7683 E1000_WRITE_FLUSH(hw); 7684 } else { 7685 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta); 7686 E1000_WRITE_FLUSH(hw); 7687 } 7688 } 7689 7690 /****************************************************************************** 7691 * Puts an ethernet address into a receive address register. 7692 * 7693 * hw - Struct containing variables accessed by shared code 7694 * addr - Address to put into receive address register 7695 * index - Receive address register to write 7696 *****************************************************************************/ 7697 void 7698 em_rar_set(struct em_hw *hw, uint8_t *addr, uint32_t index) 7699 { 7700 uint32_t rar_low, rar_high; 7701 /* 7702 * HW expects these in little endian so we reverse the byte order 7703 * from network order (big endian) to little endian 7704 */ 7705 rar_low = ((uint32_t) addr[0] | ((uint32_t) addr[1] << 8) | 7706 ((uint32_t) addr[2] << 16) | ((uint32_t) addr[3] << 24)); 7707 rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8)); 7708 /* 7709 * Disable Rx and flush all Rx frames before enabling RSS to avoid Rx 7710 * unit hang. 7711 * 7712 * Description: If there are any Rx frames queued up or otherwise 7713 * present in the HW before RSS is enabled, and then we enable RSS, 7714 * the HW Rx unit will hang. To work around this issue, we have to 7715 * disable receives and flush out all Rx frames before we enable RSS. 7716 * To do so, we modify we redirect all Rx traffic to manageability 7717 * and then reset the HW. This flushes away Rx frames, and (since the 7718 * redirections to manageability persists across resets) keeps new 7719 * ones from coming in while we work. Then, we clear the Address 7720 * Valid AV bit for all MAC addresses and undo the re-direction to 7721 * manageability. Now, frames are coming in again, but the MAC won't 7722 * accept them, so far so good. We now proceed to initialize RSS (if 7723 * necessary) and configure the Rx unit. Last, we re-enable the AV 7724 * bits and continue on our merry way. 7725 */ 7726 switch (hw->mac_type) { 7727 case em_82571: 7728 case em_82572: 7729 case em_80003es2lan: 7730 if (hw->leave_av_bit_off == TRUE) 7731 break; 7732 default: 7733 /* Indicate to hardware the Address is Valid. */ 7734 rar_high |= E1000_RAH_AV; 7735 break; 7736 } 7737 7738 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low); 7739 E1000_WRITE_FLUSH(hw); 7740 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high); 7741 E1000_WRITE_FLUSH(hw); 7742 } 7743 7744 /****************************************************************************** 7745 * Clears the VLAN filer table 7746 * 7747 * hw - Struct containing variables accessed by shared code 7748 *****************************************************************************/ 7749 STATIC void 7750 em_clear_vfta(struct em_hw *hw) 7751 { 7752 uint32_t offset; 7753 uint32_t vfta_value = 0; 7754 uint32_t vfta_offset = 0; 7755 uint32_t vfta_bit_in_reg = 0; 7756 if (IS_ICH8(hw->mac_type)) 7757 return; 7758 7759 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) { 7760 if (hw->mng_cookie.vlan_id != 0) { 7761 /* 7762 * The VFTA is a 4096b bit-field, each identifying a 7763 * single VLAN ID. The following operations 7764 * determine which 32b entry (i.e. offset) into the 7765 * array we want to set the VLAN ID (i.e. bit) of the 7766 * manageability unit. 7767 */ 7768 vfta_offset = (hw->mng_cookie.vlan_id >> 7769 E1000_VFTA_ENTRY_SHIFT) & E1000_VFTA_ENTRY_MASK; 7770 7771 vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id & 7772 E1000_VFTA_ENTRY_BIT_SHIFT_MASK); 7773 } 7774 } 7775 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 7776 /* 7777 * If the offset we want to clear is the same offset of the 7778 * manageability VLAN ID, then clear all bits except that of 7779 * the manageability unit 7780 */ 7781 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; 7782 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value); 7783 E1000_WRITE_FLUSH(hw); 7784 } 7785 } 7786 7787 /* 7788 * Due to hw errata, if the host tries to configure the VFTA register 7789 * while performing queries from the BMC or DMA, then the VFTA in some 7790 * cases won't be written. 7791 */ 7792 void 7793 em_clear_vfta_i350(struct em_hw *hw) 7794 { 7795 uint32_t offset; 7796 int i; 7797 7798 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 7799 for (i = 0; i < 10; i++) 7800 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0); 7801 E1000_WRITE_FLUSH(hw); 7802 } 7803 } 7804 7805 STATIC int32_t 7806 em_id_led_init(struct em_hw *hw) 7807 { 7808 uint32_t ledctl; 7809 const uint32_t ledctl_mask = 0x000000FF; 7810 const uint32_t ledctl_on = E1000_LEDCTL_MODE_LED_ON; 7811 const uint32_t ledctl_off = E1000_LEDCTL_MODE_LED_OFF; 7812 uint16_t eeprom_data, i, temp; 7813 const uint16_t led_mask = 0x0F; 7814 DEBUGFUNC("em_id_led_init"); 7815 7816 if (hw->mac_type < em_82540 || hw->mac_type == em_icp_xxxx) { 7817 /* Nothing to do */ 7818 return E1000_SUCCESS; 7819 } 7820 ledctl = E1000_READ_REG(hw, LEDCTL); 7821 hw->ledctl_default = ledctl; 7822 hw->ledctl_mode1 = hw->ledctl_default; 7823 hw->ledctl_mode2 = hw->ledctl_default; 7824 7825 if (em_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) { 7826 DEBUGOUT("EEPROM Read Error\n"); 7827 return -E1000_ERR_EEPROM; 7828 } 7829 if ((hw->mac_type == em_82573) && 7830 (eeprom_data == ID_LED_RESERVED_82573)) 7831 eeprom_data = ID_LED_DEFAULT_82573; 7832 else if ((eeprom_data == ID_LED_RESERVED_0000) || 7833 (eeprom_data == ID_LED_RESERVED_FFFF)) { 7834 if (hw->mac_type == em_ich8lan || 7835 hw->mac_type == em_ich9lan || 7836 hw->mac_type == em_ich10lan) // XXX 7837 eeprom_data = ID_LED_DEFAULT_ICH8LAN; 7838 else 7839 eeprom_data = ID_LED_DEFAULT; 7840 } 7841 for (i = 0; i < 4; i++) { 7842 temp = (eeprom_data >> (i << 2)) & led_mask; 7843 switch (temp) { 7844 case ID_LED_ON1_DEF2: 7845 case ID_LED_ON1_ON2: 7846 case ID_LED_ON1_OFF2: 7847 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 7848 hw->ledctl_mode1 |= ledctl_on << (i << 3); 7849 break; 7850 case ID_LED_OFF1_DEF2: 7851 case ID_LED_OFF1_ON2: 7852 case ID_LED_OFF1_OFF2: 7853 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 7854 hw->ledctl_mode1 |= ledctl_off << (i << 3); 7855 break; 7856 default: 7857 /* Do nothing */ 7858 break; 7859 } 7860 switch (temp) { 7861 case ID_LED_DEF1_ON2: 7862 case ID_LED_ON1_ON2: 7863 case ID_LED_OFF1_ON2: 7864 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 7865 hw->ledctl_mode2 |= ledctl_on << (i << 3); 7866 break; 7867 case ID_LED_DEF1_OFF2: 7868 case ID_LED_ON1_OFF2: 7869 case ID_LED_OFF1_OFF2: 7870 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 7871 hw->ledctl_mode2 |= ledctl_off << (i << 3); 7872 break; 7873 default: 7874 /* Do nothing */ 7875 break; 7876 } 7877 } 7878 return E1000_SUCCESS; 7879 } 7880 7881 /****************************************************************************** 7882 * Clears all hardware statistics counters. 7883 * 7884 * hw - Struct containing variables accessed by shared code 7885 *****************************************************************************/ 7886 void 7887 em_clear_hw_cntrs(struct em_hw *hw) 7888 { 7889 volatile uint32_t temp; 7890 temp = E1000_READ_REG(hw, CRCERRS); 7891 temp = E1000_READ_REG(hw, SYMERRS); 7892 temp = E1000_READ_REG(hw, MPC); 7893 temp = E1000_READ_REG(hw, SCC); 7894 temp = E1000_READ_REG(hw, ECOL); 7895 temp = E1000_READ_REG(hw, MCC); 7896 temp = E1000_READ_REG(hw, LATECOL); 7897 temp = E1000_READ_REG(hw, COLC); 7898 temp = E1000_READ_REG(hw, DC); 7899 temp = E1000_READ_REG(hw, SEC); 7900 temp = E1000_READ_REG(hw, RLEC); 7901 temp = E1000_READ_REG(hw, XONRXC); 7902 temp = E1000_READ_REG(hw, XONTXC); 7903 temp = E1000_READ_REG(hw, XOFFRXC); 7904 temp = E1000_READ_REG(hw, XOFFTXC); 7905 temp = E1000_READ_REG(hw, FCRUC); 7906 7907 if (!IS_ICH8(hw->mac_type)) { 7908 temp = E1000_READ_REG(hw, PRC64); 7909 temp = E1000_READ_REG(hw, PRC127); 7910 temp = E1000_READ_REG(hw, PRC255); 7911 temp = E1000_READ_REG(hw, PRC511); 7912 temp = E1000_READ_REG(hw, PRC1023); 7913 temp = E1000_READ_REG(hw, PRC1522); 7914 } 7915 temp = E1000_READ_REG(hw, GPRC); 7916 temp = E1000_READ_REG(hw, BPRC); 7917 temp = E1000_READ_REG(hw, MPRC); 7918 temp = E1000_READ_REG(hw, GPTC); 7919 temp = E1000_READ_REG(hw, GORCL); 7920 temp = E1000_READ_REG(hw, GORCH); 7921 temp = E1000_READ_REG(hw, GOTCL); 7922 temp = E1000_READ_REG(hw, GOTCH); 7923 temp = E1000_READ_REG(hw, RNBC); 7924 temp = E1000_READ_REG(hw, RUC); 7925 temp = E1000_READ_REG(hw, RFC); 7926 temp = E1000_READ_REG(hw, ROC); 7927 temp = E1000_READ_REG(hw, RJC); 7928 temp = E1000_READ_REG(hw, TORL); 7929 temp = E1000_READ_REG(hw, TORH); 7930 temp = E1000_READ_REG(hw, TOTL); 7931 temp = E1000_READ_REG(hw, TOTH); 7932 temp = E1000_READ_REG(hw, TPR); 7933 temp = E1000_READ_REG(hw, TPT); 7934 7935 if (!IS_ICH8(hw->mac_type)) { 7936 temp = E1000_READ_REG(hw, PTC64); 7937 temp = E1000_READ_REG(hw, PTC127); 7938 temp = E1000_READ_REG(hw, PTC255); 7939 temp = E1000_READ_REG(hw, PTC511); 7940 temp = E1000_READ_REG(hw, PTC1023); 7941 temp = E1000_READ_REG(hw, PTC1522); 7942 } 7943 temp = E1000_READ_REG(hw, MPTC); 7944 temp = E1000_READ_REG(hw, BPTC); 7945 7946 if (hw->mac_type < em_82543) 7947 return; 7948 7949 temp = E1000_READ_REG(hw, ALGNERRC); 7950 temp = E1000_READ_REG(hw, RXERRC); 7951 temp = E1000_READ_REG(hw, TNCRS); 7952 temp = E1000_READ_REG(hw, CEXTERR); 7953 temp = E1000_READ_REG(hw, TSCTC); 7954 temp = E1000_READ_REG(hw, TSCTFC); 7955 7956 if (hw->mac_type <= em_82544 7957 || hw->mac_type == em_icp_xxxx) 7958 return; 7959 7960 temp = E1000_READ_REG(hw, MGTPRC); 7961 temp = E1000_READ_REG(hw, MGTPDC); 7962 temp = E1000_READ_REG(hw, MGTPTC); 7963 7964 if (hw->mac_type <= em_82547_rev_2) 7965 return; 7966 7967 temp = E1000_READ_REG(hw, IAC); 7968 temp = E1000_READ_REG(hw, ICRXOC); 7969 7970 if (hw->phy_type == em_phy_82577 || 7971 hw->phy_type == em_phy_82578 || 7972 hw->phy_type == em_phy_82579 || 7973 hw->phy_type == em_phy_i217) { 7974 uint16_t phy_data; 7975 7976 em_read_phy_reg(hw, HV_SCC_UPPER, &phy_data); 7977 em_read_phy_reg(hw, HV_SCC_LOWER, &phy_data); 7978 em_read_phy_reg(hw, HV_ECOL_UPPER, &phy_data); 7979 em_read_phy_reg(hw, HV_ECOL_LOWER, &phy_data); 7980 em_read_phy_reg(hw, HV_MCC_UPPER, &phy_data); 7981 em_read_phy_reg(hw, HV_MCC_LOWER, &phy_data); 7982 em_read_phy_reg(hw, HV_LATECOL_UPPER, &phy_data); 7983 em_read_phy_reg(hw, HV_LATECOL_LOWER, &phy_data); 7984 em_read_phy_reg(hw, HV_COLC_UPPER, &phy_data); 7985 em_read_phy_reg(hw, HV_COLC_LOWER, &phy_data); 7986 em_read_phy_reg(hw, HV_DC_UPPER, &phy_data); 7987 em_read_phy_reg(hw, HV_DC_LOWER, &phy_data); 7988 em_read_phy_reg(hw, HV_TNCRS_UPPER, &phy_data); 7989 em_read_phy_reg(hw, HV_TNCRS_LOWER, &phy_data); 7990 } 7991 7992 if (hw->mac_type == em_ich8lan || 7993 hw->mac_type == em_ich9lan || 7994 hw->mac_type == em_ich10lan || 7995 hw->mac_type == em_pchlan || 7996 (hw->mac_type != em_pch2lan && hw->mac_type != em_pch_lpt && 7997 hw->mac_type != em_pch_spt && hw->mac_type != em_pch_cnp)) 7998 return; 7999 8000 temp = E1000_READ_REG(hw, ICRXPTC); 8001 temp = E1000_READ_REG(hw, ICRXATC); 8002 temp = E1000_READ_REG(hw, ICTXPTC); 8003 temp = E1000_READ_REG(hw, ICTXATC); 8004 temp = E1000_READ_REG(hw, ICTXQEC); 8005 temp = E1000_READ_REG(hw, ICTXQMTC); 8006 temp = E1000_READ_REG(hw, ICRXDMTC); 8007 } 8008 8009 #ifndef SMALL_KERNEL 8010 /****************************************************************************** 8011 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT 8012 * 8013 * hw - Struct containing variables accessed by shared code 8014 * frame_len - The length of the frame in question 8015 * mac_addr - The Ethernet destination address of the frame in question 8016 *****************************************************************************/ 8017 void 8018 em_tbi_adjust_stats(struct em_hw *hw, struct em_hw_stats *stats, 8019 uint32_t frame_len, uint8_t *mac_addr) 8020 { 8021 uint64_t carry_bit; 8022 /* First adjust the frame length. */ 8023 frame_len--; 8024 /* 8025 * We need to adjust the statistics counters, since the hardware 8026 * counters overcount this packet as a CRC error and undercount the 8027 * packet as a good packet 8028 */ 8029 /* This packet should not be counted as a CRC error. */ 8030 stats->crcerrs--; 8031 /* This packet does count as a Good Packet Received. */ 8032 stats->gprc++; 8033 8034 /* Adjust the Good Octets received counters */ 8035 carry_bit = 0x80000000 & stats->gorcl; 8036 stats->gorcl += frame_len; 8037 /* 8038 * If the high bit of Gorcl (the low 32 bits of the Good Octets 8039 * Received Count) was one before the addition, AND it is zero after, 8040 * then we lost the carry out, need to add one to Gorch (Good Octets 8041 * Received Count High). This could be simplified if all environments 8042 * supported 64-bit integers. 8043 */ 8044 if (carry_bit && ((stats->gorcl & 0x80000000) == 0)) 8045 stats->gorch++; 8046 /* 8047 * Is this a broadcast or multicast? Check broadcast first, since 8048 * the test for a multicast frame will test positive on a broadcast 8049 * frame. 8050 */ 8051 if ((mac_addr[0] == (uint8_t) 0xff) && (mac_addr[1] == (uint8_t) 0xff)) 8052 /* Broadcast packet */ 8053 stats->bprc++; 8054 else if (*mac_addr & 0x01) 8055 /* Multicast packet */ 8056 stats->mprc++; 8057 8058 if (frame_len == hw->max_frame_size) { 8059 /* 8060 * In this case, the hardware has overcounted the number of 8061 * oversize frames. 8062 */ 8063 if (stats->roc > 0) 8064 stats->roc--; 8065 } 8066 /* 8067 * Adjust the bin counters when the extra byte put the frame in the 8068 * wrong bin. Remember that the frame_len was adjusted above. 8069 */ 8070 if (frame_len == 64) { 8071 stats->prc64++; 8072 stats->prc127--; 8073 } else if (frame_len == 127) { 8074 stats->prc127++; 8075 stats->prc255--; 8076 } else if (frame_len == 255) { 8077 stats->prc255++; 8078 stats->prc511--; 8079 } else if (frame_len == 511) { 8080 stats->prc511++; 8081 stats->prc1023--; 8082 } else if (frame_len == 1023) { 8083 stats->prc1023++; 8084 stats->prc1522--; 8085 } else if (frame_len == 1522) { 8086 stats->prc1522++; 8087 } 8088 } 8089 #endif /* !SMALL_KERNEL */ 8090 8091 /****************************************************************************** 8092 * Gets the current PCI bus type, speed, and width of the hardware 8093 * 8094 * hw - Struct containing variables accessed by shared code 8095 *****************************************************************************/ 8096 void 8097 em_get_bus_info(struct em_hw *hw) 8098 { 8099 int32_t ret_val; 8100 uint16_t pci_ex_link_status; 8101 uint32_t status; 8102 switch (hw->mac_type) { 8103 case em_82542_rev2_0: 8104 case em_82542_rev2_1: 8105 hw->bus_type = em_bus_type_unknown; 8106 hw->bus_speed = em_bus_speed_unknown; 8107 hw->bus_width = em_bus_width_unknown; 8108 break; 8109 case em_icp_xxxx: 8110 hw->bus_type = em_bus_type_cpp; 8111 hw->bus_speed = em_bus_speed_unknown; 8112 hw->bus_width = em_bus_width_unknown; 8113 break; 8114 case em_82571: 8115 case em_82572: 8116 case em_82573: 8117 case em_82574: 8118 case em_82575: 8119 case em_82576: 8120 case em_82580: 8121 case em_80003es2lan: 8122 case em_i210: 8123 case em_i350: 8124 hw->bus_type = em_bus_type_pci_express; 8125 hw->bus_speed = em_bus_speed_2500; 8126 ret_val = em_read_pcie_cap_reg(hw, PCI_EX_LINK_STATUS, 8127 &pci_ex_link_status); 8128 if (ret_val) 8129 hw->bus_width = em_bus_width_unknown; 8130 else 8131 hw->bus_width = (pci_ex_link_status & 8132 PCI_EX_LINK_WIDTH_MASK) >> PCI_EX_LINK_WIDTH_SHIFT; 8133 break; 8134 case em_ich8lan: 8135 case em_ich9lan: 8136 case em_ich10lan: 8137 case em_pchlan: 8138 case em_pch2lan: 8139 case em_pch_lpt: 8140 case em_pch_spt: 8141 case em_pch_cnp: 8142 hw->bus_type = em_bus_type_pci_express; 8143 hw->bus_speed = em_bus_speed_2500; 8144 hw->bus_width = em_bus_width_pciex_1; 8145 break; 8146 default: 8147 status = E1000_READ_REG(hw, STATUS); 8148 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ? 8149 em_bus_type_pcix : em_bus_type_pci; 8150 8151 if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) { 8152 hw->bus_speed = (hw->bus_type == em_bus_type_pci) ? 8153 em_bus_speed_66 : em_bus_speed_120; 8154 } else if (hw->bus_type == em_bus_type_pci) { 8155 hw->bus_speed = (status & E1000_STATUS_PCI66) ? 8156 em_bus_speed_66 : em_bus_speed_33; 8157 } else { 8158 switch (status & E1000_STATUS_PCIX_SPEED) { 8159 case E1000_STATUS_PCIX_SPEED_66: 8160 hw->bus_speed = em_bus_speed_66; 8161 break; 8162 case E1000_STATUS_PCIX_SPEED_100: 8163 hw->bus_speed = em_bus_speed_100; 8164 break; 8165 case E1000_STATUS_PCIX_SPEED_133: 8166 hw->bus_speed = em_bus_speed_133; 8167 break; 8168 default: 8169 hw->bus_speed = em_bus_speed_reserved; 8170 break; 8171 } 8172 } 8173 hw->bus_width = (status & E1000_STATUS_BUS64) ? 8174 em_bus_width_64 : em_bus_width_32; 8175 break; 8176 } 8177 } 8178 8179 /****************************************************************************** 8180 * Writes a value to one of the devices registers using port I/O (as opposed to 8181 * memory mapped I/O). Only 82544 and newer devices support port I/O. 8182 * 8183 * hw - Struct containing variables accessed by shared code 8184 * offset - offset to write to 8185 * value - value to write 8186 *****************************************************************************/ 8187 STATIC void 8188 em_write_reg_io(struct em_hw *hw, uint32_t offset, uint32_t value) 8189 { 8190 unsigned long io_addr = hw->io_base; 8191 unsigned long io_data = hw->io_base + 4; 8192 em_io_write(hw, io_addr, offset); 8193 em_io_write(hw, io_data, value); 8194 } 8195 8196 /****************************************************************************** 8197 * Estimates the cable length. 8198 * 8199 * hw - Struct containing variables accessed by shared code 8200 * min_length - The estimated minimum length 8201 * max_length - The estimated maximum length 8202 * 8203 * returns: - E1000_ERR_XXX 8204 * E1000_SUCCESS 8205 * 8206 * This function always returns a ranged length (minimum & maximum). 8207 * So for M88 phy's, this function interprets the one value returned from the 8208 * register to the minimum and maximum range. 8209 * For IGP phy's, the function calculates the range by the AGC registers. 8210 *****************************************************************************/ 8211 STATIC int32_t 8212 em_get_cable_length(struct em_hw *hw, uint16_t *min_length, 8213 uint16_t *max_length) 8214 { 8215 int32_t ret_val; 8216 uint16_t agc_value = 0; 8217 uint16_t i, phy_data; 8218 uint16_t cable_length; 8219 DEBUGFUNC("em_get_cable_length"); 8220 8221 *min_length = *max_length = 0; 8222 8223 /* Use old method for Phy older than IGP */ 8224 if (hw->phy_type == em_phy_m88 || 8225 hw->phy_type == em_phy_oem || 8226 hw->phy_type == em_phy_82578) { 8227 8228 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, 8229 &phy_data); 8230 if (ret_val) 8231 return ret_val; 8232 cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 8233 M88E1000_PSSR_CABLE_LENGTH_SHIFT; 8234 8235 /* Convert the enum value to ranged values */ 8236 switch (cable_length) { 8237 case em_cable_length_50: 8238 *min_length = 0; 8239 *max_length = em_igp_cable_length_50; 8240 break; 8241 case em_cable_length_50_80: 8242 *min_length = em_igp_cable_length_50; 8243 *max_length = em_igp_cable_length_80; 8244 break; 8245 case em_cable_length_80_110: 8246 *min_length = em_igp_cable_length_80; 8247 *max_length = em_igp_cable_length_110; 8248 break; 8249 case em_cable_length_110_140: 8250 *min_length = em_igp_cable_length_110; 8251 *max_length = em_igp_cable_length_140; 8252 break; 8253 case em_cable_length_140: 8254 *min_length = em_igp_cable_length_140; 8255 *max_length = em_igp_cable_length_170; 8256 break; 8257 default: 8258 return -E1000_ERR_PHY; 8259 break; 8260 } 8261 } else if (hw->phy_type == em_phy_rtl8211) { 8262 /* no cable length info on RTL8211, fake */ 8263 *min_length = 0; 8264 *max_length = em_igp_cable_length_50; 8265 } else if (hw->phy_type == em_phy_gg82563) { 8266 ret_val = em_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE, 8267 &phy_data); 8268 if (ret_val) 8269 return ret_val; 8270 cable_length = phy_data & GG82563_DSPD_CABLE_LENGTH; 8271 8272 switch (cable_length) { 8273 case em_gg_cable_length_60: 8274 *min_length = 0; 8275 *max_length = em_igp_cable_length_60; 8276 break; 8277 case em_gg_cable_length_60_115: 8278 *min_length = em_igp_cable_length_60; 8279 *max_length = em_igp_cable_length_115; 8280 break; 8281 case em_gg_cable_length_115_150: 8282 *min_length = em_igp_cable_length_115; 8283 *max_length = em_igp_cable_length_150; 8284 break; 8285 case em_gg_cable_length_150: 8286 *min_length = em_igp_cable_length_150; 8287 *max_length = em_igp_cable_length_180; 8288 break; 8289 default: 8290 return -E1000_ERR_PHY; 8291 break; 8292 } 8293 } else if (hw->phy_type == em_phy_igp) { /* For IGP PHY */ 8294 uint16_t cur_agc_value; 8295 uint16_t min_agc_value = 8296 IGP01E1000_AGC_LENGTH_TABLE_SIZE; 8297 uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = 8298 {IGP01E1000_PHY_AGC_A, IGP01E1000_PHY_AGC_B, 8299 IGP01E1000_PHY_AGC_C, IGP01E1000_PHY_AGC_D}; 8300 8301 /* Read the AGC registers for all channels */ 8302 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 8303 ret_val = em_read_phy_reg(hw, agc_reg_array[i], 8304 &phy_data); 8305 if (ret_val) 8306 return ret_val; 8307 8308 cur_agc_value = phy_data >> 8309 IGP01E1000_AGC_LENGTH_SHIFT; 8310 8311 /* Value bound check. */ 8312 if ((cur_agc_value >= 8313 IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) || 8314 (cur_agc_value == 0)) 8315 return -E1000_ERR_PHY; 8316 8317 agc_value += cur_agc_value; 8318 8319 /* Update minimal AGC value. */ 8320 if (min_agc_value > cur_agc_value) 8321 min_agc_value = cur_agc_value; 8322 } 8323 8324 /* Remove the minimal AGC result for length < 50m */ 8325 if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * 8326 em_igp_cable_length_50) { 8327 agc_value -= min_agc_value; 8328 8329 /* 8330 * Get the average length of the remaining 3 channels 8331 */ 8332 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1); 8333 } else { 8334 /* Get the average length of all the 4 channels. */ 8335 agc_value /= IGP01E1000_PHY_CHANNEL_NUM; 8336 } 8337 8338 /* Set the range of the calculated length. */ 8339 *min_length = ((em_igp_cable_length_table[agc_value] - 8340 IGP01E1000_AGC_RANGE) > 0) ? 8341 (em_igp_cable_length_table[agc_value] - 8342 IGP01E1000_AGC_RANGE) : 0; 8343 *max_length = em_igp_cable_length_table[agc_value] + 8344 IGP01E1000_AGC_RANGE; 8345 } else if (hw->phy_type == em_phy_igp_2 || 8346 hw->phy_type == em_phy_igp_3) { 8347 uint16_t cur_agc_index, max_agc_index = 0; 8348 uint16_t min_agc_index = IGP02E1000_AGC_LENGTH_TABLE_SIZE - 1; 8349 uint16_t agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = 8350 {IGP02E1000_PHY_AGC_A, IGP02E1000_PHY_AGC_B, 8351 IGP02E1000_PHY_AGC_C, IGP02E1000_PHY_AGC_D}; 8352 /* Read the AGC registers for all channels */ 8353 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { 8354 ret_val = em_read_phy_reg(hw, agc_reg_array[i], 8355 &phy_data); 8356 if (ret_val) 8357 return ret_val; 8358 /* 8359 * Getting bits 15:9, which represent the combination 8360 * of course and fine gain values. The result is a 8361 * number that can be put into the lookup table to 8362 * obtain the approximate cable length. 8363 */ 8364 cur_agc_index = (phy_data >> 8365 IGP02E1000_AGC_LENGTH_SHIFT) & 8366 IGP02E1000_AGC_LENGTH_MASK; 8367 8368 /* Array index bound check. */ 8369 if ((cur_agc_index >= IGP02E1000_AGC_LENGTH_TABLE_SIZE) 8370 || (cur_agc_index == 0)) 8371 return -E1000_ERR_PHY; 8372 8373 /* Remove min & max AGC values from calculation. */ 8374 if (em_igp_2_cable_length_table[min_agc_index] > 8375 em_igp_2_cable_length_table[cur_agc_index]) 8376 min_agc_index = cur_agc_index; 8377 if (em_igp_2_cable_length_table[max_agc_index] < 8378 em_igp_2_cable_length_table[cur_agc_index]) 8379 max_agc_index = cur_agc_index; 8380 8381 agc_value += em_igp_2_cable_length_table 8382 [cur_agc_index]; 8383 } 8384 8385 agc_value -= (em_igp_2_cable_length_table[min_agc_index] + 8386 em_igp_2_cable_length_table[max_agc_index]); 8387 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); 8388 /* 8389 * Calculate cable length with the error range of +/- 10 8390 * meters. 8391 */ 8392 *min_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ? 8393 (agc_value - IGP02E1000_AGC_RANGE) : 0; 8394 *max_length = agc_value + IGP02E1000_AGC_RANGE; 8395 } 8396 return E1000_SUCCESS; 8397 } 8398 8399 /****************************************************************************** 8400 * Check if Downshift occured 8401 * 8402 * hw - Struct containing variables accessed by shared code 8403 * downshift - output parameter : 0 - No Downshift ocured. 8404 * 1 - Downshift ocured. 8405 * 8406 * returns: - E1000_ERR_XXX 8407 * E1000_SUCCESS 8408 * 8409 * For phy's older then IGP, this function reads the Downshift bit in the Phy 8410 * Specific Status register. For IGP phy's, it reads the Downgrade bit in the 8411 * Link Health register. In IGP this bit is latched high, so the driver must 8412 * read it immediately after link is established. 8413 *****************************************************************************/ 8414 STATIC int32_t 8415 em_check_downshift(struct em_hw *hw) 8416 { 8417 int32_t ret_val; 8418 uint16_t phy_data; 8419 DEBUGFUNC("em_check_downshift"); 8420 8421 if (hw->phy_type == em_phy_igp || 8422 hw->phy_type == em_phy_igp_3 || 8423 hw->phy_type == em_phy_igp_2) { 8424 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH, 8425 &phy_data); 8426 if (ret_val) 8427 return ret_val; 8428 8429 hw->speed_downgraded = (phy_data & 8430 IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0; 8431 } else if ((hw->phy_type == em_phy_m88) || 8432 (hw->phy_type == em_phy_gg82563) || 8433 (hw->phy_type == em_phy_oem) || 8434 (hw->phy_type == em_phy_82578)) { 8435 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, 8436 &phy_data); 8437 if (ret_val) 8438 return ret_val; 8439 8440 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >> 8441 M88E1000_PSSR_DOWNSHIFT_SHIFT; 8442 } else if (hw->phy_type == em_phy_ife) { 8443 /* em_phy_ife supports 10/100 speed only */ 8444 hw->speed_downgraded = FALSE; 8445 } 8446 return E1000_SUCCESS; 8447 } 8448 8449 /***************************************************************************** 8450 * 8451 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a 8452 * gigabit link is achieved to improve link quality. 8453 * 8454 * hw: Struct containing variables accessed by shared code 8455 * 8456 * returns: - E1000_ERR_PHY if fail to read/write the PHY 8457 * E1000_SUCCESS at any other case. 8458 * 8459 ****************************************************************************/ 8460 STATIC int32_t 8461 em_config_dsp_after_link_change(struct em_hw *hw, boolean_t link_up) 8462 { 8463 int32_t ret_val; 8464 uint16_t phy_data, phy_saved_data, speed, duplex, i; 8465 uint16_t dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = 8466 {IGP01E1000_PHY_AGC_PARAM_A, IGP01E1000_PHY_AGC_PARAM_B, 8467 IGP01E1000_PHY_AGC_PARAM_C, IGP01E1000_PHY_AGC_PARAM_D}; 8468 uint16_t min_length, max_length; 8469 DEBUGFUNC("em_config_dsp_after_link_change"); 8470 8471 if (hw->phy_type != em_phy_igp) 8472 return E1000_SUCCESS; 8473 8474 if (link_up) { 8475 ret_val = em_get_speed_and_duplex(hw, &speed, &duplex); 8476 if (ret_val) { 8477 DEBUGOUT("Error getting link speed and duplex\n"); 8478 return ret_val; 8479 } 8480 if (speed == SPEED_1000) { 8481 8482 ret_val = em_get_cable_length(hw, &min_length, &max_length); 8483 if (ret_val) 8484 return ret_val; 8485 8486 if ((hw->dsp_config_state == em_dsp_config_enabled) && 8487 min_length >= em_igp_cable_length_50) { 8488 8489 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; 8490 i++) { 8491 ret_val = em_read_phy_reg(hw, 8492 dsp_reg_array[i], &phy_data); 8493 if (ret_val) 8494 return ret_val; 8495 8496 phy_data &= 8497 ~IGP01E1000_PHY_EDAC_MU_INDEX; 8498 8499 ret_val = em_write_phy_reg(hw, 8500 dsp_reg_array[i], phy_data); 8501 if (ret_val) 8502 return ret_val; 8503 } 8504 hw->dsp_config_state = em_dsp_config_activated; 8505 } 8506 if ((hw->ffe_config_state == em_ffe_config_enabled) && 8507 (min_length < em_igp_cable_length_50)) { 8508 8509 uint16_t ffe_idle_err_timeout = 8510 FFE_IDLE_ERR_COUNT_TIMEOUT_20; 8511 uint32_t idle_errs = 0; 8512 /* clear previous idle error counts */ 8513 ret_val = em_read_phy_reg(hw, PHY_1000T_STATUS, 8514 &phy_data); 8515 if (ret_val) 8516 return ret_val; 8517 8518 for (i = 0; i < ffe_idle_err_timeout; i++) { 8519 usec_delay(1000); 8520 ret_val = em_read_phy_reg(hw, 8521 PHY_1000T_STATUS, &phy_data); 8522 if (ret_val) 8523 return ret_val; 8524 8525 idle_errs += (phy_data & 8526 SR_1000T_IDLE_ERROR_CNT); 8527 if (idle_errs > 8528 SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) { 8529 hw->ffe_config_state = 8530 em_ffe_config_active; 8531 8532 ret_val = em_write_phy_reg(hw, 8533 IGP01E1000_PHY_DSP_FFE, 8534 IGP01E1000_PHY_DSP_FFE_CM_CP); 8535 if (ret_val) 8536 return ret_val; 8537 break; 8538 } 8539 if (idle_errs) 8540 ffe_idle_err_timeout = 8541 FFE_IDLE_ERR_COUNT_TIMEOUT_100; 8542 } 8543 } 8544 } 8545 } else { 8546 if (hw->dsp_config_state == em_dsp_config_activated) { 8547 /* 8548 * Save off the current value of register 0x2F5B to 8549 * be restored at the end of the routines. 8550 */ 8551 ret_val = em_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 8552 8553 if (ret_val) 8554 return ret_val; 8555 8556 /* Disable the PHY transmitter */ 8557 ret_val = em_write_phy_reg(hw, 0x2F5B, 0x0003); 8558 8559 if (ret_val) 8560 return ret_val; 8561 8562 msec_delay_irq(20); 8563 8564 ret_val = em_write_phy_reg(hw, 0x0000, 8565 IGP01E1000_IEEE_FORCE_GIGA); 8566 if (ret_val) 8567 return ret_val; 8568 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 8569 ret_val = em_read_phy_reg(hw, dsp_reg_array[i], 8570 &phy_data); 8571 if (ret_val) 8572 return ret_val; 8573 8574 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; 8575 phy_data |= 8576 IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS; 8577 8578 ret_val = em_write_phy_reg(hw, 8579 dsp_reg_array[i], phy_data); 8580 if (ret_val) 8581 return ret_val; 8582 } 8583 8584 ret_val = em_write_phy_reg(hw, 0x0000, 8585 IGP01E1000_IEEE_RESTART_AUTONEG); 8586 if (ret_val) 8587 return ret_val; 8588 8589 msec_delay_irq(20); 8590 8591 /* Now enable the transmitter */ 8592 ret_val = em_write_phy_reg(hw, 0x2F5B, phy_saved_data); 8593 8594 if (ret_val) 8595 return ret_val; 8596 8597 hw->dsp_config_state = em_dsp_config_enabled; 8598 } 8599 if (hw->ffe_config_state == em_ffe_config_active) { 8600 /* 8601 * Save off the current value of register 0x2F5B to 8602 * be restored at the end of the routines. 8603 */ 8604 ret_val = em_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 8605 8606 if (ret_val) 8607 return ret_val; 8608 8609 /* Disable the PHY transmitter */ 8610 ret_val = em_write_phy_reg(hw, 0x2F5B, 0x0003); 8611 8612 if (ret_val) 8613 return ret_val; 8614 8615 msec_delay_irq(20); 8616 8617 ret_val = em_write_phy_reg(hw, 0x0000, 8618 IGP01E1000_IEEE_FORCE_GIGA); 8619 if (ret_val) 8620 return ret_val; 8621 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE, 8622 IGP01E1000_PHY_DSP_FFE_DEFAULT); 8623 if (ret_val) 8624 return ret_val; 8625 8626 ret_val = em_write_phy_reg(hw, 0x0000, 8627 IGP01E1000_IEEE_RESTART_AUTONEG); 8628 if (ret_val) 8629 return ret_val; 8630 8631 msec_delay_irq(20); 8632 8633 /* Now enable the transmitter */ 8634 ret_val = em_write_phy_reg(hw, 0x2F5B, phy_saved_data); 8635 8636 if (ret_val) 8637 return ret_val; 8638 8639 hw->ffe_config_state = em_ffe_config_enabled; 8640 } 8641 } 8642 return E1000_SUCCESS; 8643 } 8644 8645 /***************************************************************************** 8646 * Set PHY to class A mode 8647 * Assumes the following operations will follow to enable the new class mode. 8648 * 1. Do a PHY soft reset 8649 * 2. Restart auto-negotiation or force link. 8650 * 8651 * hw - Struct containing variables accessed by shared code 8652 ****************************************************************************/ 8653 static int32_t 8654 em_set_phy_mode(struct em_hw *hw) 8655 { 8656 int32_t ret_val; 8657 uint16_t eeprom_data; 8658 DEBUGFUNC("em_set_phy_mode"); 8659 8660 if ((hw->mac_type == em_82545_rev_3) && 8661 (hw->media_type == em_media_type_copper)) { 8662 ret_val = em_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, 8663 &eeprom_data); 8664 if (ret_val) { 8665 return ret_val; 8666 } 8667 if ((eeprom_data != EEPROM_RESERVED_WORD) && 8668 (eeprom_data & EEPROM_PHY_CLASS_A)) { 8669 ret_val = em_write_phy_reg(hw, 8670 M88E1000_PHY_PAGE_SELECT, 0x000B); 8671 if (ret_val) 8672 return ret_val; 8673 ret_val = em_write_phy_reg(hw, 8674 M88E1000_PHY_GEN_CONTROL, 0x8104); 8675 if (ret_val) 8676 return ret_val; 8677 8678 hw->phy_reset_disable = FALSE; 8679 } 8680 } 8681 return E1000_SUCCESS; 8682 } 8683 8684 /***************************************************************************** 8685 * 8686 * This function sets the lplu state according to the active flag. When 8687 * activating lplu this function also disables smart speed and vise versa. 8688 * lplu will not be activated unless the device autonegotiation advertisement 8689 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. 8690 * hw: Struct containing variables accessed by shared code 8691 * active - true to enable lplu false to disable lplu. 8692 * 8693 * returns: - E1000_ERR_PHY if fail to read/write the PHY 8694 * E1000_SUCCESS at any other case. 8695 * 8696 ****************************************************************************/ 8697 STATIC int32_t 8698 em_set_d3_lplu_state(struct em_hw *hw, boolean_t active) 8699 { 8700 uint32_t phy_ctrl = 0; 8701 int32_t ret_val; 8702 uint16_t phy_data; 8703 DEBUGFUNC("em_set_d3_lplu_state"); 8704 8705 if (hw->phy_type != em_phy_igp && hw->phy_type != em_phy_igp_2 8706 && hw->phy_type != em_phy_igp_3) 8707 return E1000_SUCCESS; 8708 /* 8709 * During driver activity LPLU should not be used or it will attain 8710 * link from the lowest speeds starting from 10Mbps. The capability 8711 * is used for Dx transitions and states 8712 */ 8713 if (hw->mac_type == em_82541_rev_2 || hw->mac_type == em_82547_rev_2) { 8714 ret_val = em_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data); 8715 if (ret_val) 8716 return ret_val; 8717 } else if (IS_ICH8(hw->mac_type)) { 8718 /* 8719 * MAC writes into PHY register based on the state transition 8720 * and start auto-negotiation. SW driver can overwrite the 8721 * settings in CSR PHY power control E1000_PHY_CTRL register. 8722 */ 8723 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); 8724 } else { 8725 ret_val = em_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, 8726 &phy_data); 8727 if (ret_val) 8728 return ret_val; 8729 } 8730 8731 if (!active) { 8732 if (hw->mac_type == em_82541_rev_2 || 8733 hw->mac_type == em_82547_rev_2) { 8734 phy_data &= ~IGP01E1000_GMII_FLEX_SPD; 8735 ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO, 8736 phy_data); 8737 if (ret_val) 8738 return ret_val; 8739 } else { 8740 if (IS_ICH8(hw->mac_type)) { 8741 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; 8742 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 8743 } else { 8744 phy_data &= ~IGP02E1000_PM_D3_LPLU; 8745 ret_val = em_write_phy_reg(hw, 8746 IGP02E1000_PHY_POWER_MGMT, phy_data); 8747 if (ret_val) 8748 return ret_val; 8749 } 8750 } 8751 /* 8752 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 8753 * during Dx states where the power conservation is most 8754 * important. During driver activity we should enable 8755 * SmartSpeed, so performance is maintained. 8756 */ 8757 if (hw->smart_speed == em_smart_speed_on) { 8758 ret_val = em_read_phy_reg(hw, 8759 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 8760 if (ret_val) 8761 return ret_val; 8762 8763 phy_data |= IGP01E1000_PSCFR_SMART_SPEED; 8764 ret_val = em_write_phy_reg(hw, 8765 IGP01E1000_PHY_PORT_CONFIG, phy_data); 8766 if (ret_val) 8767 return ret_val; 8768 } else if (hw->smart_speed == em_smart_speed_off) { 8769 ret_val = em_read_phy_reg(hw, 8770 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 8771 if (ret_val) 8772 return ret_val; 8773 8774 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 8775 ret_val = em_write_phy_reg(hw, 8776 IGP01E1000_PHY_PORT_CONFIG, phy_data); 8777 if (ret_val) 8778 return ret_val; 8779 } 8780 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) 8781 || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) || 8782 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) { 8783 8784 if (hw->mac_type == em_82541_rev_2 || 8785 hw->mac_type == em_82547_rev_2) { 8786 phy_data |= IGP01E1000_GMII_FLEX_SPD; 8787 ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO, 8788 phy_data); 8789 if (ret_val) 8790 return ret_val; 8791 } else { 8792 if (IS_ICH8(hw->mac_type)) { 8793 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; 8794 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 8795 } else { 8796 phy_data |= IGP02E1000_PM_D3_LPLU; 8797 ret_val = em_write_phy_reg(hw, 8798 IGP02E1000_PHY_POWER_MGMT, phy_data); 8799 if (ret_val) 8800 return ret_val; 8801 } 8802 } 8803 8804 /* When LPLU is enabled we should disable SmartSpeed */ 8805 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 8806 &phy_data); 8807 if (ret_val) 8808 return ret_val; 8809 8810 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 8811 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 8812 phy_data); 8813 if (ret_val) 8814 return ret_val; 8815 8816 } 8817 return E1000_SUCCESS; 8818 } 8819 8820 /***************************************************************************** 8821 * 8822 * This function sets the lplu d0 state according to the active flag. When 8823 * activating lplu this function also disables smart speed and vise versa. 8824 * lplu will not be activated unless the device autonegotiation advertisement 8825 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. 8826 * hw: Struct containing variables accessed by shared code 8827 * active - true to enable lplu false to disable lplu. 8828 * 8829 * returns: - E1000_ERR_PHY if fail to read/write the PHY 8830 * E1000_SUCCESS at any other case. 8831 * 8832 ****************************************************************************/ 8833 STATIC int32_t 8834 em_set_d0_lplu_state(struct em_hw *hw, boolean_t active) 8835 { 8836 uint32_t phy_ctrl = 0; 8837 int32_t ret_val; 8838 uint16_t phy_data; 8839 DEBUGFUNC("em_set_d0_lplu_state"); 8840 8841 if (hw->mac_type <= em_82547_rev_2) 8842 return E1000_SUCCESS; 8843 8844 if (IS_ICH8(hw->mac_type)) { 8845 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); 8846 } else { 8847 ret_val = em_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, 8848 &phy_data); 8849 if (ret_val) 8850 return ret_val; 8851 } 8852 8853 if (!active) { 8854 if (IS_ICH8(hw->mac_type)) { 8855 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; 8856 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 8857 } else { 8858 phy_data &= ~IGP02E1000_PM_D0_LPLU; 8859 ret_val = em_write_phy_reg(hw, 8860 IGP02E1000_PHY_POWER_MGMT, phy_data); 8861 if (ret_val) 8862 return ret_val; 8863 } 8864 /* 8865 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 8866 * during Dx states where the power conservation is most 8867 * important. During driver activity we should enable 8868 * SmartSpeed, so performance is maintained. 8869 */ 8870 if (hw->smart_speed == em_smart_speed_on) { 8871 ret_val = em_read_phy_reg(hw, 8872 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 8873 if (ret_val) 8874 return ret_val; 8875 8876 phy_data |= IGP01E1000_PSCFR_SMART_SPEED; 8877 ret_val = em_write_phy_reg(hw, 8878 IGP01E1000_PHY_PORT_CONFIG, phy_data); 8879 if (ret_val) 8880 return ret_val; 8881 } else if (hw->smart_speed == em_smart_speed_off) { 8882 ret_val = em_read_phy_reg(hw, 8883 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 8884 if (ret_val) 8885 return ret_val; 8886 8887 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 8888 ret_val = em_write_phy_reg(hw, 8889 IGP01E1000_PHY_PORT_CONFIG, phy_data); 8890 if (ret_val) 8891 return ret_val; 8892 } 8893 } else { 8894 if (IS_ICH8(hw->mac_type)) { 8895 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; 8896 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 8897 } else { 8898 phy_data |= IGP02E1000_PM_D0_LPLU; 8899 ret_val = em_write_phy_reg(hw, 8900 IGP02E1000_PHY_POWER_MGMT, phy_data); 8901 if (ret_val) 8902 return ret_val; 8903 } 8904 8905 /* When LPLU is enabled we should disable SmartSpeed */ 8906 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 8907 &phy_data); 8908 if (ret_val) 8909 return ret_val; 8910 8911 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 8912 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 8913 phy_data); 8914 if (ret_val) 8915 return ret_val; 8916 8917 } 8918 return E1000_SUCCESS; 8919 } 8920 8921 /*************************************************************************** 8922 * Set Low Power Link Up state 8923 * 8924 * Sets the LPLU state according to the active flag. For PCH, if OEM write 8925 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set 8926 * the phy speed. This function will manually set the LPLU bit and restart 8927 * auto-neg as hw would do. D3 and D0 LPLU will call the same function 8928 * since it configures the same bit. 8929 ***************************************************************************/ 8930 int32_t 8931 em_set_lplu_state_pchlan(struct em_hw *hw, boolean_t active) 8932 { 8933 int32_t ret_val = E1000_SUCCESS; 8934 uint16_t oem_reg; 8935 8936 DEBUGFUNC("e1000_set_lplu_state_pchlan"); 8937 8938 ret_val = em_read_phy_reg(hw, HV_OEM_BITS, &oem_reg); 8939 if (ret_val) 8940 goto out; 8941 8942 if (active) 8943 oem_reg |= HV_OEM_BITS_LPLU; 8944 else 8945 oem_reg &= ~HV_OEM_BITS_LPLU; 8946 8947 oem_reg |= HV_OEM_BITS_RESTART_AN; 8948 ret_val = em_write_phy_reg(hw, HV_OEM_BITS, oem_reg); 8949 8950 out: 8951 return ret_val; 8952 } 8953 8954 /****************************************************************************** 8955 * Change VCO speed register to improve Bit Error Rate performance of SERDES. 8956 * 8957 * hw - Struct containing variables accessed by shared code 8958 *****************************************************************************/ 8959 static int32_t 8960 em_set_vco_speed(struct em_hw *hw) 8961 { 8962 int32_t ret_val; 8963 uint16_t default_page = 0; 8964 uint16_t phy_data; 8965 DEBUGFUNC("em_set_vco_speed"); 8966 8967 switch (hw->mac_type) { 8968 case em_82545_rev_3: 8969 case em_82546_rev_3: 8970 break; 8971 default: 8972 return E1000_SUCCESS; 8973 } 8974 8975 /* Set PHY register 30, page 5, bit 8 to 0 */ 8976 8977 ret_val = em_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page); 8978 if (ret_val) 8979 return ret_val; 8980 8981 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005); 8982 if (ret_val) 8983 return ret_val; 8984 8985 ret_val = em_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); 8986 if (ret_val) 8987 return ret_val; 8988 8989 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8; 8990 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); 8991 if (ret_val) 8992 return ret_val; 8993 8994 /* Set PHY register 30, page 4, bit 11 to 1 */ 8995 8996 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004); 8997 if (ret_val) 8998 return ret_val; 8999 9000 ret_val = em_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); 9001 if (ret_val) 9002 return ret_val; 9003 9004 phy_data |= M88E1000_PHY_VCO_REG_BIT11; 9005 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); 9006 if (ret_val) 9007 return ret_val; 9008 9009 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page); 9010 if (ret_val) 9011 return ret_val; 9012 9013 return E1000_SUCCESS; 9014 } 9015 9016 /***************************************************************************** 9017 * This function reads the cookie from ARC ram. 9018 * 9019 * returns: - E1000_SUCCESS . 9020 ****************************************************************************/ 9021 STATIC int32_t 9022 em_host_if_read_cookie(struct em_hw *hw, uint8_t *buffer) 9023 { 9024 uint8_t i; 9025 uint32_t offset = E1000_MNG_DHCP_COOKIE_OFFSET; 9026 uint8_t length = E1000_MNG_DHCP_COOKIE_LENGTH; 9027 length = (length >> 2); 9028 offset = (offset >> 2); 9029 9030 for (i = 0; i < length; i++) { 9031 *((uint32_t *) buffer + i) = 9032 E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i); 9033 } 9034 return E1000_SUCCESS; 9035 } 9036 9037 /***************************************************************************** 9038 * This function checks whether the HOST IF is enabled for command operaton 9039 * and also checks whether the previous command is completed. 9040 * It busy waits in case of previous command is not completed. 9041 * 9042 * returns: - E1000_ERR_HOST_INTERFACE_COMMAND in case if is not ready or 9043 * timeout 9044 * - E1000_SUCCESS for success. 9045 ****************************************************************************/ 9046 STATIC int32_t 9047 em_mng_enable_host_if(struct em_hw *hw) 9048 { 9049 uint32_t hicr; 9050 uint8_t i; 9051 /* Check that the host interface is enabled. */ 9052 hicr = E1000_READ_REG(hw, HICR); 9053 if ((hicr & E1000_HICR_EN) == 0) { 9054 DEBUGOUT("E1000_HOST_EN bit disabled.\n"); 9055 return -E1000_ERR_HOST_INTERFACE_COMMAND; 9056 } 9057 /* check the previous command is completed */ 9058 for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) { 9059 hicr = E1000_READ_REG(hw, HICR); 9060 if (!(hicr & E1000_HICR_C)) 9061 break; 9062 msec_delay_irq(1); 9063 } 9064 9065 if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) { 9066 DEBUGOUT("Previous command timeout failed .\n"); 9067 return -E1000_ERR_HOST_INTERFACE_COMMAND; 9068 } 9069 return E1000_SUCCESS; 9070 } 9071 9072 /***************************************************************************** 9073 * This function checks the mode of the firmware. 9074 * 9075 * returns - TRUE when the mode is IAMT or FALSE. 9076 ****************************************************************************/ 9077 boolean_t 9078 em_check_mng_mode(struct em_hw *hw) 9079 { 9080 uint32_t fwsm; 9081 fwsm = E1000_READ_REG(hw, FWSM); 9082 9083 if (IS_ICH8(hw->mac_type)) { 9084 if ((fwsm & E1000_FWSM_MODE_MASK) == 9085 (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) 9086 return TRUE; 9087 } else if ((fwsm & E1000_FWSM_MODE_MASK) == 9088 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) 9089 return TRUE; 9090 9091 return FALSE; 9092 } 9093 9094 /***************************************************************************** 9095 * This function calculates the checksum. 9096 * 9097 * returns - checksum of buffer contents. 9098 ****************************************************************************/ 9099 STATIC uint8_t 9100 em_calculate_mng_checksum(char *buffer, uint32_t length) 9101 { 9102 uint8_t sum = 0; 9103 uint32_t i; 9104 if (!buffer) 9105 return 0; 9106 9107 for (i = 0; i < length; i++) 9108 sum += buffer[i]; 9109 9110 return (uint8_t) (0 - sum); 9111 } 9112 9113 /***************************************************************************** 9114 * This function checks whether tx pkt filtering needs to be enabled or not. 9115 * 9116 * returns - TRUE for packet filtering or FALSE. 9117 ****************************************************************************/ 9118 boolean_t 9119 em_enable_tx_pkt_filtering(struct em_hw *hw) 9120 { 9121 /* called in init as well as watchdog timer functions */ 9122 int32_t ret_val, checksum; 9123 boolean_t tx_filter = FALSE; 9124 struct em_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie); 9125 uint8_t *buffer = (uint8_t *) & (hw->mng_cookie); 9126 if (em_check_mng_mode(hw)) { 9127 ret_val = em_mng_enable_host_if(hw); 9128 if (ret_val == E1000_SUCCESS) { 9129 ret_val = em_host_if_read_cookie(hw, buffer); 9130 if (ret_val == E1000_SUCCESS) { 9131 checksum = hdr->checksum; 9132 hdr->checksum = 0; 9133 if ((hdr->signature == E1000_IAMT_SIGNATURE) && 9134 checksum == em_calculate_mng_checksum( 9135 (char *) buffer, 9136 E1000_MNG_DHCP_COOKIE_LENGTH)) { 9137 if (hdr->status & 9138 E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT) 9139 tx_filter = TRUE; 9140 } else 9141 tx_filter = TRUE; 9142 } else 9143 tx_filter = TRUE; 9144 } 9145 } 9146 hw->tx_pkt_filtering = tx_filter; 9147 return tx_filter; 9148 } 9149 9150 static int32_t 9151 em_polarity_reversal_workaround(struct em_hw *hw) 9152 { 9153 int32_t ret_val; 9154 uint16_t mii_status_reg; 9155 uint16_t i; 9156 /* Polarity reversal workaround for forced 10F/10H links. */ 9157 9158 /* Disable the transmitter on the PHY */ 9159 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 9160 if (ret_val) 9161 return ret_val; 9162 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF); 9163 if (ret_val) 9164 return ret_val; 9165 9166 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 9167 if (ret_val) 9168 return ret_val; 9169 9170 /* This loop will early-out if the NO link condition has been met. */ 9171 for (i = PHY_FORCE_TIME; i > 0; i--) { 9172 /* 9173 * Read the MII Status Register and wait for Link Status bit 9174 * to be clear. 9175 */ 9176 9177 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 9178 if (ret_val) 9179 return ret_val; 9180 9181 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 9182 if (ret_val) 9183 return ret_val; 9184 9185 if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) 9186 break; 9187 msec_delay_irq(100); 9188 } 9189 9190 /* Recommended delay time after link has been lost */ 9191 msec_delay_irq(1000); 9192 9193 /* Now we will re-enable the transmitter on the PHY */ 9194 9195 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 9196 if (ret_val) 9197 return ret_val; 9198 msec_delay_irq(50); 9199 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0); 9200 if (ret_val) 9201 return ret_val; 9202 msec_delay_irq(50); 9203 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00); 9204 if (ret_val) 9205 return ret_val; 9206 msec_delay_irq(50); 9207 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000); 9208 if (ret_val) 9209 return ret_val; 9210 9211 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 9212 if (ret_val) 9213 return ret_val; 9214 9215 /* This loop will early-out if the link condition has been met. */ 9216 for (i = PHY_FORCE_TIME; i > 0; i--) { 9217 /* 9218 * Read the MII Status Register and wait for Link Status bit 9219 * to be set. 9220 */ 9221 9222 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 9223 if (ret_val) 9224 return ret_val; 9225 9226 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 9227 if (ret_val) 9228 return ret_val; 9229 9230 if (mii_status_reg & MII_SR_LINK_STATUS) 9231 break; 9232 msec_delay_irq(100); 9233 } 9234 return E1000_SUCCESS; 9235 } 9236 9237 /****************************************************************************** 9238 * 9239 * Disables PCI-Express master access. 9240 * 9241 * hw: Struct containing variables accessed by shared code 9242 * 9243 * returns: - none. 9244 * 9245 *****************************************************************************/ 9246 STATIC void 9247 em_set_pci_express_master_disable(struct em_hw *hw) 9248 { 9249 uint32_t ctrl; 9250 DEBUGFUNC("em_set_pci_express_master_disable"); 9251 9252 if (hw->bus_type != em_bus_type_pci_express) 9253 return; 9254 9255 ctrl = E1000_READ_REG(hw, CTRL); 9256 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; 9257 E1000_WRITE_REG(hw, CTRL, ctrl); 9258 } 9259 9260 /****************************************************************************** 9261 * 9262 * Disables PCI-Express master access and verifies there are no pending 9263 * requests 9264 * 9265 * hw: Struct containing variables accessed by shared code 9266 * 9267 * returns: - E1000_ERR_MASTER_REQUESTS_PENDING if master disable bit hasn't 9268 * caused the master requests to be disabled. 9269 * E1000_SUCCESS master requests disabled. 9270 * 9271 ******************************************************************************/ 9272 int32_t 9273 em_disable_pciex_master(struct em_hw *hw) 9274 { 9275 int32_t timeout = MASTER_DISABLE_TIMEOUT; /* 80ms */ 9276 DEBUGFUNC("em_disable_pciex_master"); 9277 9278 if (hw->bus_type != em_bus_type_pci_express) 9279 return E1000_SUCCESS; 9280 9281 em_set_pci_express_master_disable(hw); 9282 9283 while (timeout) { 9284 if (!(E1000_READ_REG(hw, STATUS) & 9285 E1000_STATUS_GIO_MASTER_ENABLE)) 9286 break; 9287 else 9288 usec_delay(100); 9289 timeout--; 9290 } 9291 9292 if (!timeout) { 9293 DEBUGOUT("Master requests are pending.\n"); 9294 return -E1000_ERR_MASTER_REQUESTS_PENDING; 9295 } 9296 return E1000_SUCCESS; 9297 } 9298 9299 /****************************************************************************** 9300 * 9301 * Check for EEPROM Auto Read bit done. 9302 * 9303 * hw: Struct containing variables accessed by shared code 9304 * 9305 * returns: - E1000_ERR_RESET if fail to reset MAC 9306 * E1000_SUCCESS at any other case. 9307 * 9308 ******************************************************************************/ 9309 STATIC int32_t 9310 em_get_auto_rd_done(struct em_hw *hw) 9311 { 9312 int32_t timeout = AUTO_READ_DONE_TIMEOUT; 9313 DEBUGFUNC("em_get_auto_rd_done"); 9314 9315 switch (hw->mac_type) { 9316 default: 9317 msec_delay(5); 9318 break; 9319 case em_82571: 9320 case em_82572: 9321 case em_82573: 9322 case em_82574: 9323 case em_82575: 9324 case em_82576: 9325 case em_82580: 9326 case em_80003es2lan: 9327 case em_i210: 9328 case em_i350: 9329 case em_ich8lan: 9330 case em_ich9lan: 9331 case em_ich10lan: 9332 case em_pchlan: 9333 case em_pch2lan: 9334 case em_pch_lpt: 9335 case em_pch_spt: 9336 case em_pch_cnp: 9337 while (timeout) { 9338 if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD) 9339 break; 9340 else 9341 msec_delay(1); 9342 timeout--; 9343 } 9344 9345 if (!timeout) { 9346 DEBUGOUT("Auto read by HW from EEPROM has not" 9347 " completed.\n"); 9348 return -E1000_ERR_RESET; 9349 } 9350 break; 9351 } 9352 /* 9353 * PHY configuration from NVM just starts after EECD_AUTO_RD sets to 9354 * high. Need to wait for PHY configuration completion before 9355 * accessing NVM and PHY. 9356 */ 9357 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) 9358 msec_delay(25); 9359 9360 return E1000_SUCCESS; 9361 } 9362 9363 /*************************************************************************** 9364 * Checks if the PHY configuration is done 9365 * 9366 * hw: Struct containing variables accessed by shared code 9367 * 9368 * returns: - E1000_ERR_RESET if fail to reset MAC 9369 * E1000_SUCCESS at any other case. 9370 * 9371 ***************************************************************************/ 9372 STATIC int32_t 9373 em_get_phy_cfg_done(struct em_hw *hw) 9374 { 9375 int32_t timeout = PHY_CFG_TIMEOUT; 9376 uint32_t cfg_mask = E1000_NVM_CFG_DONE_PORT_0; 9377 DEBUGFUNC("em_get_phy_cfg_done"); 9378 9379 switch (hw->mac_type) { 9380 default: 9381 msec_delay_irq(10); 9382 break; 9383 case em_80003es2lan: 9384 case em_82575: 9385 case em_82576: 9386 case em_82580: 9387 case em_i350: 9388 switch (hw->bus_func) { 9389 case 1: 9390 cfg_mask = E1000_NVM_CFG_DONE_PORT_1; 9391 break; 9392 case 2: 9393 cfg_mask = E1000_NVM_CFG_DONE_PORT_2; 9394 break; 9395 case 3: 9396 cfg_mask = E1000_NVM_CFG_DONE_PORT_3; 9397 break; 9398 } 9399 /* FALLTHROUGH */ 9400 case em_82571: 9401 case em_82572: 9402 while (timeout) { 9403 if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask) 9404 break; 9405 else 9406 msec_delay(1); 9407 timeout--; 9408 } 9409 if (!timeout) { 9410 DEBUGOUT("MNG configuration cycle has not completed." 9411 "\n"); 9412 } 9413 break; 9414 } 9415 9416 return E1000_SUCCESS; 9417 } 9418 9419 /*************************************************************************** 9420 * 9421 * Using the combination of SMBI and SWESMBI semaphore bits when resetting 9422 * adapter or Eeprom access. 9423 * 9424 * hw: Struct containing variables accessed by shared code 9425 * 9426 * returns: - E1000_ERR_EEPROM if fail to access EEPROM. 9427 * E1000_SUCCESS at any other case. 9428 * 9429 ***************************************************************************/ 9430 STATIC int32_t 9431 em_get_hw_eeprom_semaphore(struct em_hw *hw) 9432 { 9433 int32_t timeout; 9434 uint32_t swsm; 9435 DEBUGFUNC("em_get_hw_eeprom_semaphore"); 9436 9437 if (!hw->eeprom_semaphore_present) 9438 return E1000_SUCCESS; 9439 9440 if (hw->mac_type == em_80003es2lan) { 9441 /* Get the SW semaphore. */ 9442 if (em_get_software_semaphore(hw) != E1000_SUCCESS) 9443 return -E1000_ERR_EEPROM; 9444 } 9445 /* Get the FW semaphore. */ 9446 timeout = hw->eeprom.word_size + 1; 9447 while (timeout) { 9448 swsm = E1000_READ_REG(hw, SWSM); 9449 swsm |= E1000_SWSM_SWESMBI; 9450 E1000_WRITE_REG(hw, SWSM, swsm); 9451 /* if we managed to set the bit we got the semaphore. */ 9452 swsm = E1000_READ_REG(hw, SWSM); 9453 if (swsm & E1000_SWSM_SWESMBI) 9454 break; 9455 9456 usec_delay(50); 9457 timeout--; 9458 } 9459 9460 if (!timeout) { 9461 /* Release semaphores */ 9462 em_put_hw_eeprom_semaphore(hw); 9463 DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set." 9464 "\n"); 9465 return -E1000_ERR_EEPROM; 9466 } 9467 return E1000_SUCCESS; 9468 } 9469 9470 /*************************************************************************** 9471 * This function clears HW semaphore bits. 9472 * 9473 * hw: Struct containing variables accessed by shared code 9474 * 9475 * returns: - None. 9476 * 9477 ***************************************************************************/ 9478 STATIC void 9479 em_put_hw_eeprom_semaphore(struct em_hw *hw) 9480 { 9481 uint32_t swsm; 9482 DEBUGFUNC("em_put_hw_eeprom_semaphore"); 9483 9484 if (!hw->eeprom_semaphore_present) 9485 return; 9486 9487 swsm = E1000_READ_REG(hw, SWSM); 9488 if (hw->mac_type == em_80003es2lan) { 9489 /* Release both semaphores. */ 9490 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 9491 } else 9492 swsm &= ~(E1000_SWSM_SWESMBI); 9493 E1000_WRITE_REG(hw, SWSM, swsm); 9494 } 9495 9496 /*************************************************************************** 9497 * 9498 * Obtaining software semaphore bit (SMBI) before resetting PHY. 9499 * 9500 * hw: Struct containing variables accessed by shared code 9501 * 9502 * returns: - E1000_ERR_RESET if fail to obtain semaphore. 9503 * E1000_SUCCESS at any other case. 9504 * 9505 ***************************************************************************/ 9506 STATIC int32_t 9507 em_get_software_semaphore(struct em_hw *hw) 9508 { 9509 int32_t timeout = hw->eeprom.word_size + 1; 9510 uint32_t swsm; 9511 DEBUGFUNC("em_get_software_semaphore"); 9512 9513 if (hw->mac_type != em_80003es2lan) 9514 return E1000_SUCCESS; 9515 9516 while (timeout) { 9517 swsm = E1000_READ_REG(hw, SWSM); 9518 /* 9519 * If SMBI bit cleared, it is now set and we hold the 9520 * semaphore 9521 */ 9522 if (!(swsm & E1000_SWSM_SMBI)) 9523 break; 9524 msec_delay_irq(1); 9525 timeout--; 9526 } 9527 9528 if (!timeout) { 9529 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 9530 return -E1000_ERR_RESET; 9531 } 9532 return E1000_SUCCESS; 9533 } 9534 9535 /*************************************************************************** 9536 * 9537 * Release semaphore bit (SMBI). 9538 * 9539 * hw: Struct containing variables accessed by shared code 9540 * 9541 ***************************************************************************/ 9542 STATIC void 9543 em_release_software_semaphore(struct em_hw *hw) 9544 { 9545 uint32_t swsm; 9546 DEBUGFUNC("em_release_software_semaphore"); 9547 9548 if (hw->mac_type != em_80003es2lan) 9549 return; 9550 9551 swsm = E1000_READ_REG(hw, SWSM); 9552 /* Release the SW semaphores. */ 9553 swsm &= ~E1000_SWSM_SMBI; 9554 E1000_WRITE_REG(hw, SWSM, swsm); 9555 } 9556 9557 /****************************************************************************** 9558 * Checks if PHY reset is blocked due to SOL/IDER session, for example. 9559 * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to 9560 * the caller to figure out how to deal with it. 9561 * 9562 * hw - Struct containing variables accessed by shared code 9563 * 9564 * returns: - E1000_BLK_PHY_RESET 9565 * E1000_SUCCESS 9566 * 9567 *****************************************************************************/ 9568 int32_t 9569 em_check_phy_reset_block(struct em_hw *hw) 9570 { 9571 uint32_t manc = 0; 9572 uint32_t fwsm = 0; 9573 DEBUGFUNC("em_check_phy_reset_block\n"); 9574 9575 if (IS_ICH8(hw->mac_type)) { 9576 int i = 0; 9577 int blocked = 0; 9578 do { 9579 fwsm = E1000_READ_REG(hw, FWSM); 9580 if (!(fwsm & E1000_FWSM_RSPCIPHY)) { 9581 blocked = 1; 9582 msec_delay(10); 9583 continue; 9584 } 9585 blocked = 0; 9586 } while (blocked && (i++ < 30)); 9587 return blocked ? E1000_BLK_PHY_RESET : E1000_SUCCESS; 9588 } 9589 if (hw->mac_type > em_82547_rev_2) 9590 manc = E1000_READ_REG(hw, MANC); 9591 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? 9592 E1000_BLK_PHY_RESET : E1000_SUCCESS; 9593 } 9594 9595 /****************************************************************************** 9596 * Configure PCI-Ex no-snoop 9597 * 9598 * hw - Struct containing variables accessed by shared code. 9599 * no_snoop - Bitmap of no-snoop events. 9600 * 9601 * returns: E1000_SUCCESS 9602 * 9603 *****************************************************************************/ 9604 STATIC int32_t 9605 em_set_pci_ex_no_snoop(struct em_hw *hw, uint32_t no_snoop) 9606 { 9607 uint32_t gcr_reg = 0; 9608 DEBUGFUNC("em_set_pci_ex_no_snoop"); 9609 9610 if (hw->bus_type == em_bus_type_unknown) 9611 em_get_bus_info(hw); 9612 9613 if (hw->bus_type != em_bus_type_pci_express) 9614 return E1000_SUCCESS; 9615 9616 if (no_snoop) { 9617 gcr_reg = E1000_READ_REG(hw, GCR); 9618 gcr_reg &= ~(PCI_EX_NO_SNOOP_ALL); 9619 gcr_reg |= no_snoop; 9620 E1000_WRITE_REG(hw, GCR, gcr_reg); 9621 } 9622 if (IS_ICH8(hw->mac_type)) { 9623 uint32_t ctrl_ext; 9624 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 9625 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 9626 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 9627 } 9628 return E1000_SUCCESS; 9629 } 9630 9631 /*************************************************************************** 9632 * 9633 * Get software semaphore FLAG bit (SWFLAG). 9634 * SWFLAG is used to synchronize the access to all shared resource between 9635 * SW, FW and HW. 9636 * 9637 * hw: Struct containing variables accessed by shared code 9638 * 9639 ***************************************************************************/ 9640 STATIC int32_t 9641 em_get_software_flag(struct em_hw *hw) 9642 { 9643 int32_t timeout = PHY_CFG_TIMEOUT; 9644 uint32_t extcnf_ctrl; 9645 DEBUGFUNC("em_get_software_flag"); 9646 9647 if (IS_ICH8(hw->mac_type)) { 9648 if (hw->sw_flag) { 9649 hw->sw_flag++; 9650 return E1000_SUCCESS; 9651 } 9652 while (timeout) { 9653 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 9654 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)) 9655 break; 9656 msec_delay_irq(1); 9657 timeout--; 9658 } 9659 if (!timeout) { 9660 printf("%s: SW has already locked the resource?\n", 9661 __func__); 9662 return -E1000_ERR_CONFIG; 9663 } 9664 timeout = SW_FLAG_TIMEOUT; 9665 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; 9666 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); 9667 9668 while (timeout) { 9669 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 9670 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) 9671 break; 9672 msec_delay_irq(1); 9673 timeout--; 9674 } 9675 9676 if (!timeout) { 9677 printf("Failed to acquire the semaphore, FW or HW " 9678 "has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n", 9679 E1000_READ_REG(hw, FWSM), extcnf_ctrl); 9680 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 9681 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); 9682 return -E1000_ERR_CONFIG; 9683 } 9684 } 9685 hw->sw_flag++; 9686 return E1000_SUCCESS; 9687 } 9688 9689 /*************************************************************************** 9690 * 9691 * Release software semaphore FLAG bit (SWFLAG). 9692 * SWFLAG is used to synchronize the access to all shared resource between 9693 * SW, FW and HW. 9694 * 9695 * hw: Struct containing variables accessed by shared code 9696 * 9697 ***************************************************************************/ 9698 STATIC void 9699 em_release_software_flag(struct em_hw *hw) 9700 { 9701 uint32_t extcnf_ctrl; 9702 DEBUGFUNC("em_release_software_flag"); 9703 9704 if (IS_ICH8(hw->mac_type)) { 9705 KASSERT(hw->sw_flag > 0); 9706 if (--hw->sw_flag > 0) 9707 return; 9708 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 9709 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 9710 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); 9711 } 9712 return; 9713 } 9714 9715 /** 9716 * em_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1 9717 * @hw: pointer to the HW structure 9718 * @bank: pointer to the variable that returns the active bank 9719 * 9720 * Reads signature byte from the NVM using the flash access registers. 9721 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank. 9722 **/ 9723 int32_t 9724 em_valid_nvm_bank_detect_ich8lan(struct em_hw *hw, uint32_t *bank) 9725 { 9726 uint32_t eecd; 9727 uint32_t bank1_offset = hw->flash_bank_size * sizeof(uint16_t); 9728 uint32_t act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1; 9729 uint32_t nvm_dword = 0; 9730 uint8_t sig_byte = 0; 9731 int32_t ret_val; 9732 9733 DEBUGFUNC("em_valid_nvm_bank_detect_ich8lan"); 9734 9735 switch (hw->mac_type) { 9736 case em_pch_spt: 9737 case em_pch_cnp: 9738 bank1_offset = hw->flash_bank_size * 2; 9739 act_offset = E1000_ICH_NVM_SIG_WORD * 2; 9740 9741 /* set bank to 0 in case flash read fails. */ 9742 *bank = 0; 9743 9744 /* Check bank 0 */ 9745 ret_val = em_read_ich8_dword(hw, act_offset, &nvm_dword); 9746 if (ret_val) 9747 return ret_val; 9748 sig_byte = (uint8_t)((nvm_dword & 0xFF00) >> 8); 9749 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 9750 E1000_ICH_NVM_SIG_VALUE) { 9751 *bank = 0; 9752 return 0; 9753 } 9754 9755 /* Check bank 1 */ 9756 ret_val = em_read_ich8_dword(hw, act_offset + bank1_offset, 9757 &nvm_dword); 9758 if (ret_val) 9759 return ret_val; 9760 sig_byte = (uint8_t)((nvm_dword & 0xFF00) >> 8); 9761 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 9762 E1000_ICH_NVM_SIG_VALUE) { 9763 *bank = 1; 9764 return 0; 9765 } 9766 9767 DEBUGOUT("ERROR: No valid NVM bank present\n"); 9768 return -1; 9769 case em_ich8lan: 9770 case em_ich9lan: 9771 eecd = E1000_READ_REG(hw, EECD); 9772 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) == 9773 E1000_EECD_SEC1VAL_VALID_MASK) { 9774 if (eecd & E1000_EECD_SEC1VAL) 9775 *bank = 1; 9776 else 9777 *bank = 0; 9778 9779 return E1000_SUCCESS; 9780 } 9781 DEBUGOUT("Unable to determine valid NVM bank via EEC - reading flash signature\n"); 9782 /* fall-thru */ 9783 default: 9784 /* set bank to 0 in case flash read fails */ 9785 *bank = 0; 9786 9787 /* Check bank 0 */ 9788 ret_val = em_read_ich8_byte(hw, act_offset, 9789 &sig_byte); 9790 if (ret_val) 9791 return ret_val; 9792 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 9793 E1000_ICH_NVM_SIG_VALUE) { 9794 *bank = 0; 9795 return E1000_SUCCESS; 9796 } 9797 9798 /* Check bank 1 */ 9799 ret_val = em_read_ich8_byte(hw, act_offset + 9800 bank1_offset, 9801 &sig_byte); 9802 if (ret_val) 9803 return ret_val; 9804 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 9805 E1000_ICH_NVM_SIG_VALUE) { 9806 *bank = 1; 9807 return E1000_SUCCESS; 9808 } 9809 9810 DEBUGOUT("ERROR: No valid NVM bank present\n"); 9811 return -1; 9812 } 9813 } 9814 9815 STATIC int32_t 9816 em_read_eeprom_spt(struct em_hw *hw, uint16_t offset, uint16_t words, 9817 uint16_t *data) 9818 { 9819 int32_t error = E1000_SUCCESS; 9820 uint32_t flash_bank = 0; 9821 uint32_t act_offset = 0; 9822 uint32_t bank_offset = 0; 9823 uint32_t dword = 0; 9824 uint16_t i = 0, add; 9825 9826 /* 9827 * We need to know which is the valid flash bank. In the event that 9828 * we didn't allocate eeprom_shadow_ram, we may not be managing 9829 * flash_bank. So it cannot be trusted and needs to be updated with 9830 * each read. 9831 */ 9832 9833 if (hw->mac_type < em_pch_spt) 9834 return -E1000_ERR_EEPROM; 9835 9836 error = em_get_software_flag(hw); 9837 if (error != E1000_SUCCESS) 9838 return error; 9839 9840 error = em_valid_nvm_bank_detect_ich8lan(hw, &flash_bank); 9841 if (error != E1000_SUCCESS) { 9842 DEBUGOUT("Could not detect valid bank, assuming bank 0\n"); 9843 flash_bank = 0; 9844 } 9845 9846 /* 9847 * Adjust offset appropriately if we're on bank 1 - adjust for word 9848 * size 9849 */ 9850 bank_offset = flash_bank * (hw->flash_bank_size * 2); 9851 9852 for (i = add = 0; i < words; i += add) { 9853 if ((offset + i) % 2) { 9854 add = 1; 9855 if (hw->eeprom_shadow_ram != NULL 9856 && hw->eeprom_shadow_ram[offset + i].modified) { 9857 data[i] = 9858 hw->eeprom_shadow_ram[offset+i].eeprom_word; 9859 continue; 9860 } 9861 act_offset = bank_offset + (offset + i - 1) * 2; 9862 } else { 9863 add = 2; 9864 if (hw->eeprom_shadow_ram != NULL 9865 && hw->eeprom_shadow_ram[offset+i].modified 9866 && hw->eeprom_shadow_ram[offset+i+1].modified) { 9867 data[i] = hw->eeprom_shadow_ram[offset+i].eeprom_word; 9868 data[i+1] = hw->eeprom_shadow_ram[offset+i+1].eeprom_word; 9869 continue; 9870 } 9871 act_offset = bank_offset + (offset + i) * 2; 9872 } 9873 error = em_read_ich8_dword(hw, act_offset, &dword); 9874 if (error != E1000_SUCCESS) 9875 break; 9876 if (hw->eeprom_shadow_ram != NULL 9877 && hw->eeprom_shadow_ram[offset+i].modified) { 9878 data[i] = hw->eeprom_shadow_ram[offset+i].eeprom_word; 9879 } else { 9880 if (add == 1) 9881 data[i] = dword >> 16; 9882 else 9883 data[i] = dword & 0xFFFFUL; 9884 } 9885 if (add == 1 || words-i == 1) 9886 continue; 9887 if (hw->eeprom_shadow_ram != NULL 9888 && hw->eeprom_shadow_ram[offset+i+1].modified) { 9889 data[i+1] = 9890 hw->eeprom_shadow_ram[offset+i+1].eeprom_word; 9891 } else { 9892 data[i+1] = dword >> 16; 9893 } 9894 } 9895 9896 em_release_software_flag(hw); 9897 9898 return error; 9899 } 9900 9901 /****************************************************************************** 9902 * Reads a 16 bit word or words from the EEPROM using the ICH8's flash access 9903 * register. 9904 * 9905 * hw - Struct containing variables accessed by shared code 9906 * offset - offset of word in the EEPROM to read 9907 * data - word read from the EEPROM 9908 * words - number of words to read 9909 *****************************************************************************/ 9910 STATIC int32_t 9911 em_read_eeprom_ich8(struct em_hw *hw, uint16_t offset, uint16_t words, 9912 uint16_t *data) 9913 { 9914 int32_t error = E1000_SUCCESS; 9915 uint32_t flash_bank = 0; 9916 uint32_t act_offset = 0; 9917 uint32_t bank_offset = 0; 9918 uint16_t word = 0; 9919 uint16_t i = 0; 9920 /* 9921 * We need to know which is the valid flash bank. In the event that 9922 * we didn't allocate eeprom_shadow_ram, we may not be managing 9923 * flash_bank. So it cannot be trusted and needs to be updated with 9924 * each read. 9925 */ 9926 9927 if (hw->mac_type >= em_pch_spt) 9928 return em_read_eeprom_spt(hw, offset, words, data); 9929 9930 error = em_get_software_flag(hw); 9931 if (error != E1000_SUCCESS) 9932 return error; 9933 9934 error = em_valid_nvm_bank_detect_ich8lan(hw, &flash_bank); 9935 if (error != E1000_SUCCESS) { 9936 DEBUGOUT("Could not detect valid bank, assuming bank 0\n"); 9937 flash_bank = 0; 9938 } 9939 9940 /* 9941 * Adjust offset appropriately if we're on bank 1 - adjust for word 9942 * size 9943 */ 9944 bank_offset = flash_bank * (hw->flash_bank_size * 2); 9945 9946 for (i = 0; i < words; i++) { 9947 if (hw->eeprom_shadow_ram != NULL && 9948 hw->eeprom_shadow_ram[offset + i].modified == TRUE) { 9949 data[i] = 9950 hw->eeprom_shadow_ram[offset + i].eeprom_word; 9951 } else { 9952 /* The NVM part needs a byte offset, hence * 2 */ 9953 act_offset = bank_offset + ((offset + i) * 2); 9954 error = em_read_ich8_word(hw, act_offset, &word); 9955 if (error != E1000_SUCCESS) 9956 break; 9957 data[i] = word; 9958 } 9959 } 9960 9961 em_release_software_flag(hw); 9962 9963 return error; 9964 } 9965 9966 /****************************************************************************** 9967 * Writes a 16 bit word or words to the EEPROM using the ICH8's flash access 9968 * register. Actually, writes are written to the shadow ram cache in the hw 9969 * structure hw->em_shadow_ram. em_commit_shadow_ram flushes this to 9970 * the NVM, which occurs when the NVM checksum is updated. 9971 * 9972 * hw - Struct containing variables accessed by shared code 9973 * offset - offset of word in the EEPROM to write 9974 * words - number of words to write 9975 * data - words to write to the EEPROM 9976 *****************************************************************************/ 9977 STATIC int32_t 9978 em_write_eeprom_ich8(struct em_hw *hw, uint16_t offset, uint16_t words, 9979 uint16_t *data) 9980 { 9981 uint32_t i = 0; 9982 int32_t error = E1000_SUCCESS; 9983 error = em_get_software_flag(hw); 9984 if (error != E1000_SUCCESS) 9985 return error; 9986 /* 9987 * A driver can write to the NVM only if it has eeprom_shadow_ram 9988 * allocated. Subsequent reads to the modified words are read from 9989 * this cached structure as well. Writes will only go into this 9990 * cached structure unless it's followed by a call to 9991 * em_update_eeprom_checksum() where it will commit the changes and 9992 * clear the "modified" field. 9993 */ 9994 if (hw->eeprom_shadow_ram != NULL) { 9995 for (i = 0; i < words; i++) { 9996 if ((offset + i) < E1000_SHADOW_RAM_WORDS) { 9997 hw->eeprom_shadow_ram[offset + i].modified = 9998 TRUE; 9999 hw->eeprom_shadow_ram[offset + i].eeprom_word = 10000 data[i]; 10001 } else { 10002 error = -E1000_ERR_EEPROM; 10003 break; 10004 } 10005 } 10006 } else { 10007 /* 10008 * Drivers have the option to not allocate eeprom_shadow_ram 10009 * as long as they don't perform any NVM writes. An attempt 10010 * in doing so will result in this error. 10011 */ 10012 error = -E1000_ERR_EEPROM; 10013 } 10014 10015 em_release_software_flag(hw); 10016 10017 return error; 10018 } 10019 10020 /****************************************************************************** 10021 * This function does initial flash setup so that a new read/write/erase cycle 10022 * can be started. 10023 * 10024 * hw - The pointer to the hw structure 10025 ****************************************************************************/ 10026 STATIC int32_t 10027 em_ich8_cycle_init(struct em_hw *hw) 10028 { 10029 union ich8_hws_flash_status hsfsts; 10030 int32_t error = E1000_ERR_EEPROM; 10031 int32_t i = 0; 10032 DEBUGFUNC("em_ich8_cycle_init"); 10033 10034 if (hw->mac_type >= em_pch_spt) 10035 hsfsts.regval = E1000_READ_ICH_FLASH_REG32(hw, 10036 ICH_FLASH_HSFSTS) & 0xFFFFUL; 10037 else 10038 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, 10039 ICH_FLASH_HSFSTS); 10040 10041 /* May be check the Flash Des Valid bit in Hw status */ 10042 if (hsfsts.hsf_status.fldesvalid == 0) { 10043 DEBUGOUT("Flash descriptor invalid. SW Sequencing must be" 10044 " used."); 10045 return error; 10046 } 10047 /* Clear FCERR in Hw status by writing 1 */ 10048 /* Clear DAEL in Hw status by writing a 1 */ 10049 hsfsts.hsf_status.flcerr = 1; 10050 hsfsts.hsf_status.dael = 1; 10051 if (hw->mac_type >= em_pch_spt) 10052 E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_HSFSTS, 10053 hsfsts.regval & 0xFFFFUL); 10054 else 10055 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, 10056 hsfsts.regval); 10057 /* 10058 * Either we should have a hardware SPI cycle in progress bit to 10059 * check against, in order to start a new cycle or FDONE bit should 10060 * be changed in the hardware so that it is 1 after hardware reset, 10061 * which can then be used as an indication whether a cycle is in 10062 * progress or has been completed .. we should also have some 10063 * software semaphore mechanism to guard FDONE or the cycle in 10064 * progress bit so that two threads access to those bits can be 10065 * sequentiallized or a way so that 2 threads dont start the cycle at 10066 * the same time 10067 */ 10068 10069 if (hsfsts.hsf_status.flcinprog == 0) { 10070 /* 10071 * There is no cycle running at present, so we can start a 10072 * cycle 10073 */ 10074 /* Begin by setting Flash Cycle Done. */ 10075 hsfsts.hsf_status.flcdone = 1; 10076 if (hw->mac_type >= em_pch_spt) 10077 E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_HSFSTS, 10078 hsfsts.regval & 0xFFFFUL); 10079 else 10080 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, 10081 hsfsts.regval); 10082 error = E1000_SUCCESS; 10083 } else { 10084 /* 10085 * otherwise poll for sometime so the current cycle has a 10086 * chance to end before giving up. 10087 */ 10088 for (i = 0; i < ICH_FLASH_COMMAND_TIMEOUT; i++) { 10089 if (hw->mac_type >= em_pch_spt) 10090 hsfsts.regval = E1000_READ_ICH_FLASH_REG32( 10091 hw, ICH_FLASH_HSFSTS) & 0xFFFFUL; 10092 else 10093 hsfsts.regval = E1000_READ_ICH_FLASH_REG16( 10094 hw, ICH_FLASH_HSFSTS); 10095 if (hsfsts.hsf_status.flcinprog == 0) { 10096 error = E1000_SUCCESS; 10097 break; 10098 } 10099 usec_delay(1); 10100 } 10101 if (error == E1000_SUCCESS) { 10102 /* 10103 * Successful in waiting for previous cycle to 10104 * timeout, now set the Flash Cycle Done. 10105 */ 10106 hsfsts.hsf_status.flcdone = 1; 10107 if (hw->mac_type >= em_pch_spt) 10108 E1000_WRITE_ICH_FLASH_REG32(hw, 10109 ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFFUL); 10110 else 10111 E1000_WRITE_ICH_FLASH_REG16(hw, 10112 ICH_FLASH_HSFSTS, hsfsts.regval); 10113 } else { 10114 DEBUGOUT("Flash controller busy, cannot get access"); 10115 } 10116 } 10117 return error; 10118 } 10119 10120 /****************************************************************************** 10121 * This function starts a flash cycle and waits for its completion 10122 * 10123 * hw - The pointer to the hw structure 10124 *****************************************************************************/ 10125 STATIC int32_t 10126 em_ich8_flash_cycle(struct em_hw *hw, uint32_t timeout) 10127 { 10128 union ich8_hws_flash_ctrl hsflctl; 10129 union ich8_hws_flash_status hsfsts; 10130 int32_t error = E1000_ERR_EEPROM; 10131 uint32_t i = 0; 10132 10133 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ 10134 if (hw->mac_type >= em_pch_spt) 10135 hsflctl.regval = E1000_READ_ICH_FLASH_REG32(hw, 10136 ICH_FLASH_HSFSTS) >> 16; 10137 else 10138 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, 10139 ICH_FLASH_HSFCTL); 10140 hsflctl.hsf_ctrl.flcgo = 1; 10141 10142 if (hw->mac_type >= em_pch_spt) 10143 E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_HSFSTS, 10144 (uint32_t)hsflctl.regval << 16); 10145 else 10146 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, 10147 hsflctl.regval); 10148 10149 /* wait till FDONE bit is set to 1 */ 10150 do { 10151 if (hw->mac_type >= em_pch_spt) 10152 hsfsts.regval = E1000_READ_ICH_FLASH_REG32(hw, 10153 ICH_FLASH_HSFSTS) & 0xFFFFUL; 10154 else 10155 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, 10156 ICH_FLASH_HSFSTS); 10157 if (hsfsts.hsf_status.flcdone == 1) 10158 break; 10159 usec_delay(1); 10160 i++; 10161 } while (i < timeout); 10162 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) { 10163 error = E1000_SUCCESS; 10164 } 10165 return error; 10166 } 10167 10168 /****************************************************************************** 10169 * Reads a byte or word from the NVM using the ICH8 flash access registers. 10170 * 10171 * hw - The pointer to the hw structure 10172 * index - The index of the byte or word to read. 10173 * size - Size of data to read, 1=byte 2=word 10174 * data - Pointer to the word to store the value read. 10175 *****************************************************************************/ 10176 STATIC int32_t 10177 em_read_ich8_data(struct em_hw *hw, uint32_t index, uint32_t size, 10178 uint16_t *data) 10179 { 10180 union ich8_hws_flash_status hsfsts; 10181 union ich8_hws_flash_ctrl hsflctl; 10182 uint32_t flash_linear_address; 10183 uint32_t flash_data = 0; 10184 int32_t error = -E1000_ERR_EEPROM; 10185 int32_t count = 0; 10186 DEBUGFUNC("em_read_ich8_data"); 10187 10188 if (size < 1 || size > 2 || data == 0x0 || 10189 index > ICH_FLASH_LINEAR_ADDR_MASK) 10190 return error; 10191 10192 flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) + 10193 hw->flash_base_addr; 10194 10195 do { 10196 usec_delay(1); 10197 /* Steps */ 10198 error = em_ich8_cycle_init(hw); 10199 if (error != E1000_SUCCESS) 10200 break; 10201 10202 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, 10203 ICH_FLASH_HSFCTL); 10204 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 10205 hsflctl.hsf_ctrl.fldbcount = size - 1; 10206 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; 10207 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, 10208 hsflctl.regval); 10209 /* 10210 * Write the last 24 bits of index into Flash Linear address 10211 * field in Flash Address 10212 */ 10213 /* TODO: TBD maybe check the index against the size of flash */ 10214 10215 E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_FADDR, 10216 flash_linear_address); 10217 10218 error = em_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT); 10219 /* 10220 * Check if FCERR is set to 1, if set to 1, clear it and try 10221 * the whole sequence a few more times, else read in (shift 10222 * in) the Flash Data0, the order is least significant byte 10223 * first msb to lsb 10224 */ 10225 if (error == E1000_SUCCESS) { 10226 flash_data = E1000_READ_ICH_FLASH_REG(hw, 10227 ICH_FLASH_FDATA0); 10228 if (size == 1) { 10229 *data = (uint8_t) (flash_data & 0x000000FF); 10230 } else if (size == 2) { 10231 *data = (uint16_t) (flash_data & 0x0000FFFF); 10232 } 10233 break; 10234 } else { 10235 /* 10236 * If we've gotten here, then things are probably 10237 * completely hosed, but if the error condition is 10238 * detected, it won't hurt to give it another 10239 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 10240 */ 10241 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, 10242 ICH_FLASH_HSFSTS); 10243 if (hsfsts.hsf_status.flcerr == 1) { 10244 /* Repeat for some time before giving up. */ 10245 continue; 10246 } else if (hsfsts.hsf_status.flcdone == 0) { 10247 DEBUGOUT("Timeout error - flash cycle did not" 10248 " complete."); 10249 break; 10250 } 10251 } 10252 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 10253 10254 return error; 10255 } 10256 10257 STATIC int32_t 10258 em_read_ich8_data32(struct em_hw *hw, uint32_t offset, uint32_t *data) 10259 { 10260 union ich8_hws_flash_status hsfsts; 10261 union ich8_hws_flash_ctrl hsflctl; 10262 uint32_t flash_linear_address; 10263 int32_t error = -E1000_ERR_EEPROM; 10264 uint32_t count = 0; 10265 DEBUGFUNC("em_read_ich8_data32"); 10266 10267 if (hw->mac_type < em_pch_spt) 10268 return error; 10269 if (offset > ICH_FLASH_LINEAR_ADDR_MASK) 10270 return error; 10271 flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & offset) + 10272 hw->flash_base_addr; 10273 10274 do { 10275 usec_delay(1); 10276 /* Steps */ 10277 error = em_ich8_cycle_init(hw); 10278 if (error != E1000_SUCCESS) 10279 break; 10280 10281 /* 32 bit accesses in SPT. */ 10282 hsflctl.regval = E1000_READ_ICH_FLASH_REG32(hw, 10283 ICH_FLASH_HSFSTS) >> 16; 10284 10285 hsflctl.hsf_ctrl.fldbcount = sizeof(uint32_t) - 1; 10286 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; 10287 10288 E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_HSFSTS, 10289 (uint32_t)hsflctl.regval << 16); 10290 /* 10291 * Write the last 24 bits of offset into Flash Linear address 10292 * field in Flash Address 10293 */ 10294 /* TODO: TBD maybe check the offset against the size of flash */ 10295 10296 E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_FADDR, 10297 flash_linear_address); 10298 10299 error = em_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT); 10300 /* 10301 * Check if FCERR is set to 1, if set to 1, clear it and try 10302 * the whole sequence a few more times, else read in (shift 10303 * in) the Flash Data0, the order is least significant byte 10304 * first msb to lsb 10305 */ 10306 if (error == E1000_SUCCESS) { 10307 (*data) = (uint32_t)E1000_READ_ICH_FLASH_REG32(hw, 10308 ICH_FLASH_FDATA0); 10309 break; 10310 } else { 10311 /* 10312 * If we've gotten here, then things are probably 10313 * completely hosed, but if the error condition is 10314 * detected, it won't hurt to give it another 10315 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 10316 */ 10317 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, 10318 ICH_FLASH_HSFSTS); 10319 if (hsfsts.hsf_status.flcerr == 1) { 10320 /* Repeat for some time before giving up. */ 10321 continue; 10322 } else if (hsfsts.hsf_status.flcdone == 0) { 10323 DEBUGOUT("Timeout error - flash cycle did not" 10324 " complete."); 10325 break; 10326 } 10327 } 10328 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 10329 10330 return error; 10331 } 10332 10333 10334 /****************************************************************************** 10335 * Writes One /two bytes to the NVM using the ICH8 flash access registers. 10336 * 10337 * hw - The pointer to the hw structure 10338 * index - The index of the byte/word to write. 10339 * size - Size of data to read, 1=byte 2=word 10340 * data - The byte(s) to write to the NVM. 10341 *****************************************************************************/ 10342 STATIC int32_t 10343 em_write_ich8_data(struct em_hw *hw, uint32_t index, uint32_t size, 10344 uint16_t data) 10345 { 10346 union ich8_hws_flash_status hsfsts; 10347 union ich8_hws_flash_ctrl hsflctl; 10348 uint32_t flash_linear_address; 10349 uint32_t flash_data = 0; 10350 int32_t error = -E1000_ERR_EEPROM; 10351 int32_t count = 0; 10352 DEBUGFUNC("em_write_ich8_data"); 10353 10354 if (hw->mac_type >= em_pch_spt) 10355 return -E1000_ERR_EEPROM; 10356 if (size < 1 || size > 2 || data > size * 0xff || 10357 index > ICH_FLASH_LINEAR_ADDR_MASK) 10358 return error; 10359 10360 flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) + 10361 hw->flash_base_addr; 10362 10363 do { 10364 usec_delay(1); 10365 /* Steps */ 10366 error = em_ich8_cycle_init(hw); 10367 if (error != E1000_SUCCESS) 10368 break; 10369 10370 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, 10371 ICH_FLASH_HSFCTL); 10372 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 10373 hsflctl.hsf_ctrl.fldbcount = size - 1; 10374 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; 10375 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, 10376 hsflctl.regval); 10377 /* 10378 * Write the last 24 bits of index into Flash Linear address 10379 * field in Flash Address 10380 */ 10381 E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_FADDR, 10382 flash_linear_address); 10383 10384 if (size == 1) 10385 flash_data = (uint32_t) data & 0x00FF; 10386 else 10387 flash_data = (uint32_t) data; 10388 10389 E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_FDATA0, flash_data); 10390 /* 10391 * check if FCERR is set to 1 , if set to 1, clear it and try 10392 * the whole sequence a few more times else done 10393 */ 10394 error = em_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT); 10395 if (error == E1000_SUCCESS) { 10396 break; 10397 } else { 10398 /* 10399 * If we're here, then things are most likely 10400 * completely hosed, but if the error condition is 10401 * detected, it won't hurt to give it another 10402 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 10403 */ 10404 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, 10405 ICH_FLASH_HSFSTS); 10406 if (hsfsts.hsf_status.flcerr == 1) { 10407 /* Repeat for some time before giving up. */ 10408 continue; 10409 } else if (hsfsts.hsf_status.flcdone == 0) { 10410 DEBUGOUT("Timeout error - flash cycle did not" 10411 " complete."); 10412 break; 10413 } 10414 } 10415 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 10416 10417 return error; 10418 } 10419 10420 /****************************************************************************** 10421 * Reads a single byte from the NVM using the ICH8 flash access registers. 10422 * 10423 * hw - pointer to em_hw structure 10424 * index - The index of the byte to read. 10425 * data - Pointer to a byte to store the value read. 10426 *****************************************************************************/ 10427 STATIC int32_t 10428 em_read_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t *data) 10429 { 10430 int32_t status = E1000_SUCCESS; 10431 uint16_t word = 0; 10432 10433 if (hw->mac_type >= em_pch_spt) 10434 return -E1000_ERR_EEPROM; 10435 else 10436 status = em_read_ich8_data(hw, index, 1, &word); 10437 if (status == E1000_SUCCESS) { 10438 *data = (uint8_t) word; 10439 } 10440 return status; 10441 } 10442 10443 /****************************************************************************** 10444 * Writes a single byte to the NVM using the ICH8 flash access registers. 10445 * Performs verification by reading back the value and then going through 10446 * a retry algorithm before giving up. 10447 * 10448 * hw - pointer to em_hw structure 10449 * index - The index of the byte to write. 10450 * byte - The byte to write to the NVM. 10451 *****************************************************************************/ 10452 STATIC int32_t 10453 em_verify_write_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t byte) 10454 { 10455 int32_t error = E1000_SUCCESS; 10456 int32_t program_retries = 0; 10457 DEBUGOUT2("Byte := %2.2X Offset := %d\n", byte, index); 10458 10459 error = em_write_ich8_byte(hw, index, byte); 10460 10461 if (error != E1000_SUCCESS) { 10462 for (program_retries = 0; program_retries < 100; 10463 program_retries++) { 10464 DEBUGOUT2("Retrying \t Byte := %2.2X Offset := %d\n", 10465 byte, index); 10466 error = em_write_ich8_byte(hw, index, byte); 10467 usec_delay(100); 10468 if (error == E1000_SUCCESS) 10469 break; 10470 } 10471 } 10472 if (program_retries == 100) 10473 error = E1000_ERR_EEPROM; 10474 10475 return error; 10476 } 10477 10478 /****************************************************************************** 10479 * Writes a single byte to the NVM using the ICH8 flash access registers. 10480 * 10481 * hw - pointer to em_hw structure 10482 * index - The index of the byte to read. 10483 * data - The byte to write to the NVM. 10484 *****************************************************************************/ 10485 STATIC int32_t 10486 em_write_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t data) 10487 { 10488 int32_t status = E1000_SUCCESS; 10489 uint16_t word = (uint16_t) data; 10490 status = em_write_ich8_data(hw, index, 1, word); 10491 10492 return status; 10493 } 10494 10495 /****************************************************************************** 10496 * Reads a dword from the NVM using the ICH8 flash access registers. 10497 * 10498 * hw - pointer to em_hw structure 10499 * index - The starting BYTE index of the word to read. 10500 * data - Pointer to a word to store the value read. 10501 *****************************************************************************/ 10502 STATIC int32_t 10503 em_read_ich8_dword(struct em_hw *hw, uint32_t index, uint32_t *data) 10504 { 10505 int32_t status = E1000_SUCCESS; 10506 status = em_read_ich8_data32(hw, index, data); 10507 return status; 10508 } 10509 10510 /****************************************************************************** 10511 * Reads a word from the NVM using the ICH8 flash access registers. 10512 * 10513 * hw - pointer to em_hw structure 10514 * index - The starting byte index of the word to read. 10515 * data - Pointer to a word to store the value read. 10516 *****************************************************************************/ 10517 STATIC int32_t 10518 em_read_ich8_word(struct em_hw *hw, uint32_t index, uint16_t *data) 10519 { 10520 int32_t status = E1000_SUCCESS; 10521 status = em_read_ich8_data(hw, index, 2, data); 10522 return status; 10523 } 10524 10525 /****************************************************************************** 10526 * Erases the bank specified. Each bank may be a 4, 8 or 64k block. Banks are 0 10527 * based. 10528 * 10529 * hw - pointer to em_hw structure 10530 * bank - 0 for first bank, 1 for second bank 10531 * 10532 * Note that this function may actually erase as much as 8 or 64 KBytes. The 10533 * amount of NVM used in each bank is a *minimum* of 4 KBytes, but in fact the 10534 * bank size may be 4, 8 or 64 KBytes 10535 *****************************************************************************/ 10536 int32_t 10537 em_erase_ich8_4k_segment(struct em_hw *hw, uint32_t bank) 10538 { 10539 union ich8_hws_flash_status hsfsts; 10540 union ich8_hws_flash_ctrl hsflctl; 10541 uint32_t flash_linear_address; 10542 int32_t count = 0; 10543 int32_t error = E1000_ERR_EEPROM; 10544 int32_t iteration; 10545 int32_t sub_sector_size = 0; 10546 int32_t bank_size; 10547 int32_t j = 0; 10548 int32_t error_flag = 0; 10549 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 10550 /* 10551 * Determine HW Sector size: Read BERASE bits of Hw flash Status 10552 * register 10553 */ 10554 /* 10555 * 00: The Hw sector is 256 bytes, hence we need to erase 16 10556 * consecutive sectors. The start index for the nth Hw sector can be 10557 * calculated as bank * 4096 + n * 256 01: The Hw sector is 4K bytes, 10558 * hence we need to erase 1 sector. The start index for the nth Hw 10559 * sector can be calculated as bank * 4096 10: The HW sector is 8K 10560 * bytes 11: The Hw sector size is 64K bytes 10561 */ 10562 if (hsfsts.hsf_status.berasesz == 0x0) { 10563 /* Hw sector size 256 */ 10564 sub_sector_size = ICH_FLASH_SEG_SIZE_256; 10565 bank_size = ICH_FLASH_SECTOR_SIZE; 10566 iteration = ICH_FLASH_SECTOR_SIZE / ICH_FLASH_SEG_SIZE_256; 10567 } else if (hsfsts.hsf_status.berasesz == 0x1) { 10568 bank_size = ICH_FLASH_SEG_SIZE_4K; 10569 iteration = 1; 10570 } else if (hsfsts.hsf_status.berasesz == 0x2) { 10571 if (hw->mac_type == em_ich9lan) { 10572 uint32_t gfpreg, sector_base_addr, sector_end_addr; 10573 gfpreg = E1000_READ_ICH_FLASH_REG(hw, 10574 ICH_FLASH_GFPREG); 10575 /* 10576 * sector_X_addr is a "sector"-aligned address (4096 bytes) 10577 * Add 1 to sector_end_addr since this sector is included in 10578 * the overall size. 10579 */ 10580 sector_base_addr = gfpreg & ICH_GFPREG_BASE_MASK; 10581 sector_end_addr = 10582 ((gfpreg >> 16) & ICH_GFPREG_BASE_MASK) + 1; 10583 10584 /* 10585 * find total size of the NVM, then cut in half since the total 10586 * size represents two separate NVM banks. 10587 */ 10588 bank_size = (sector_end_addr - sector_base_addr) 10589 << ICH_FLASH_SECT_ADDR_SHIFT; 10590 bank_size /= 2; 10591 /* Word align */ 10592 bank_size = 10593 (bank_size / sizeof(uint16_t)) * sizeof(uint16_t); 10594 10595 sub_sector_size = ICH_FLASH_SEG_SIZE_8K; 10596 iteration = bank_size / ICH_FLASH_SEG_SIZE_8K; 10597 } else { 10598 return error; 10599 } 10600 } else if (hsfsts.hsf_status.berasesz == 0x3) { 10601 bank_size = ICH_FLASH_SEG_SIZE_64K; 10602 iteration = 1; 10603 } else { 10604 return error; 10605 } 10606 10607 for (j = 0; j < iteration; j++) { 10608 do { 10609 count++; 10610 /* Steps */ 10611 error = em_ich8_cycle_init(hw); 10612 if (error != E1000_SUCCESS) { 10613 error_flag = 1; 10614 break; 10615 } 10616 /* 10617 * Write a value 11 (block Erase) in Flash Cycle 10618 * field in Hw flash Control 10619 */ 10620 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, 10621 ICH_FLASH_HSFCTL); 10622 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE; 10623 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, 10624 hsflctl.regval); 10625 /* 10626 * Write the last 24 bits of an index within the 10627 * block into Flash Linear address field in Flash 10628 * Address. This probably needs to be calculated 10629 * here based off the on-chip erase sector size and 10630 * the software bank size (4, 8 or 64 KBytes) 10631 */ 10632 flash_linear_address = 10633 bank * bank_size + j * sub_sector_size; 10634 flash_linear_address += hw->flash_base_addr; 10635 flash_linear_address &= ICH_FLASH_LINEAR_ADDR_MASK; 10636 10637 E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_FADDR, 10638 flash_linear_address); 10639 10640 error = 10641 em_ich8_flash_cycle(hw, ICH_FLASH_ERASE_TIMEOUT); 10642 /* 10643 * Check if FCERR is set to 1. If 1, clear it and 10644 * try the whole sequence a few more times else Done 10645 */ 10646 if (error == E1000_SUCCESS) { 10647 break; 10648 } else { 10649 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, 10650 ICH_FLASH_HSFSTS); 10651 if (hsfsts.hsf_status.flcerr == 1) { 10652 /* 10653 * repeat for some time before giving 10654 * up 10655 */ 10656 continue; 10657 } else if (hsfsts.hsf_status.flcdone == 0) { 10658 error_flag = 1; 10659 break; 10660 } 10661 } 10662 } while ((count < ICH_FLASH_CYCLE_REPEAT_COUNT) && !error_flag); 10663 if (error_flag == 1) 10664 break; 10665 } 10666 if (error_flag != 1) 10667 error = E1000_SUCCESS; 10668 return error; 10669 } 10670 10671 /****************************************************************************** 10672 * Reads 16-bit words from the OTP. Return error when the word is not 10673 * stored in OTP. 10674 * 10675 * hw - Struct containing variables accessed by shared code 10676 * offset - offset of word in the OTP to read 10677 * data - word read from the OTP 10678 * words - number of words to read 10679 *****************************************************************************/ 10680 STATIC int32_t 10681 em_read_invm_i210(struct em_hw *hw, uint16_t offset, uint16_t words, 10682 uint16_t *data) 10683 { 10684 int32_t ret_val = E1000_SUCCESS; 10685 10686 switch (offset) 10687 { 10688 case EEPROM_MAC_ADDR_WORD0: 10689 case EEPROM_MAC_ADDR_WORD1: 10690 case EEPROM_MAC_ADDR_WORD2: 10691 /* Generate random MAC address if there's none. */ 10692 ret_val = em_read_invm_word_i210(hw, offset, data); 10693 if (ret_val != E1000_SUCCESS) { 10694 DEBUGOUT("MAC Addr not found in iNVM\n"); 10695 *data = 0xFFFF; 10696 ret_val = E1000_SUCCESS; 10697 } 10698 break; 10699 case EEPROM_INIT_CONTROL2_REG: 10700 ret_val = em_read_invm_word_i210(hw, offset, data); 10701 if (ret_val != E1000_SUCCESS) { 10702 *data = NVM_INIT_CTRL_2_DEFAULT_I211; 10703 ret_val = E1000_SUCCESS; 10704 } 10705 break; 10706 case EEPROM_INIT_CONTROL4_REG: 10707 ret_val = em_read_invm_word_i210(hw, offset, data); 10708 if (ret_val != E1000_SUCCESS) { 10709 *data = NVM_INIT_CTRL_4_DEFAULT_I211; 10710 ret_val = E1000_SUCCESS; 10711 } 10712 break; 10713 case EEPROM_LED_1_CFG: 10714 ret_val = em_read_invm_word_i210(hw, offset, data); 10715 if (ret_val != E1000_SUCCESS) { 10716 *data = NVM_LED_1_CFG_DEFAULT_I211; 10717 ret_val = E1000_SUCCESS; 10718 } 10719 break; 10720 case EEPROM_LED_0_2_CFG: 10721 ret_val = em_read_invm_word_i210(hw, offset, data); 10722 if (ret_val != E1000_SUCCESS) { 10723 *data = NVM_LED_0_2_CFG_DEFAULT_I211; 10724 ret_val = E1000_SUCCESS; 10725 } 10726 break; 10727 case EEPROM_ID_LED_SETTINGS: 10728 ret_val = em_read_invm_word_i210(hw, offset, data); 10729 if (ret_val != E1000_SUCCESS) { 10730 *data = ID_LED_RESERVED_FFFF; 10731 ret_val = E1000_SUCCESS; 10732 } 10733 break; 10734 default: 10735 DEBUGOUT1("NVM word 0x%02x is not mapped.\n", offset); 10736 *data = NVM_RESERVED_WORD; 10737 break; 10738 } 10739 10740 return ret_val; 10741 } 10742 10743 /****************************************************************************** 10744 * Reads 16-bit words from the OTP. Return error when the word is not 10745 * stored in OTP. 10746 * 10747 * hw - Struct containing variables accessed by shared code 10748 * offset - offset of word in the OTP to read 10749 * data - word read from the OTP 10750 *****************************************************************************/ 10751 STATIC int32_t 10752 em_read_invm_word_i210(struct em_hw *hw, uint16_t address, uint16_t *data) 10753 { 10754 int32_t error = -E1000_NOT_IMPLEMENTED; 10755 uint32_t invm_dword; 10756 uint16_t i; 10757 uint8_t record_type, word_address; 10758 10759 for (i = 0; i < INVM_SIZE; i++) { 10760 invm_dword = EM_READ_REG(hw, E1000_INVM_DATA_REG(i)); 10761 /* Get record type */ 10762 record_type = INVM_DWORD_TO_RECORD_TYPE(invm_dword); 10763 if (record_type == INVM_UNINITIALIZED_STRUCTURE) 10764 break; 10765 if (record_type == INVM_CSR_AUTOLOAD_STRUCTURE) 10766 i += INVM_CSR_AUTOLOAD_DATA_SIZE_IN_DWORDS; 10767 if (record_type == INVM_RSA_KEY_SHA256_STRUCTURE) 10768 i += INVM_RSA_KEY_SHA256_DATA_SIZE_IN_DWORDS; 10769 if (record_type == INVM_WORD_AUTOLOAD_STRUCTURE) { 10770 word_address = INVM_DWORD_TO_WORD_ADDRESS(invm_dword); 10771 if (word_address == address) { 10772 *data = INVM_DWORD_TO_WORD_DATA(invm_dword); 10773 error = E1000_SUCCESS; 10774 break; 10775 } 10776 } 10777 } 10778 10779 return error; 10780 } 10781 10782 STATIC int32_t 10783 em_init_lcd_from_nvm_config_region(struct em_hw *hw, uint32_t cnf_base_addr, 10784 uint32_t cnf_size) 10785 { 10786 uint32_t ret_val = E1000_SUCCESS; 10787 uint16_t word_addr, reg_data, reg_addr; 10788 uint16_t i; 10789 /* cnf_base_addr is in DWORD */ 10790 word_addr = (uint16_t) (cnf_base_addr << 1); 10791 10792 /* cnf_size is returned in size of dwords */ 10793 for (i = 0; i < cnf_size; i++) { 10794 ret_val = 10795 em_read_eeprom(hw, (word_addr + i * 2), 1, ®_data); 10796 if (ret_val) 10797 return ret_val; 10798 10799 ret_val = 10800 em_read_eeprom(hw, (word_addr + i * 2 + 1), 1, ®_addr); 10801 if (ret_val) 10802 return ret_val; 10803 10804 ret_val = em_get_software_flag(hw); 10805 if (ret_val != E1000_SUCCESS) 10806 return ret_val; 10807 10808 ret_val = 10809 em_write_phy_reg_ex(hw, (uint32_t) reg_addr, reg_data); 10810 10811 em_release_software_flag(hw); 10812 } 10813 10814 return ret_val; 10815 } 10816 10817 /****************************************************************************** 10818 * This function initializes the PHY from the NVM on ICH8 platforms. This 10819 * is needed due to an issue where the NVM configuration is not properly 10820 * autoloaded after power transitions. Therefore, after each PHY reset, we 10821 * will load the configuration data out of the NVM manually. 10822 * 10823 * hw: Struct containing variables accessed by shared code 10824 *****************************************************************************/ 10825 STATIC int32_t 10826 em_init_lcd_from_nvm(struct em_hw *hw) 10827 { 10828 uint32_t reg_data, cnf_base_addr, cnf_size, ret_val, loop, sw_cfg_mask; 10829 if (hw->phy_type != em_phy_igp_3) 10830 return E1000_SUCCESS; 10831 10832 /* Check if SW needs configure the PHY */ 10833 if (hw->device_id == E1000_DEV_ID_ICH8_IGP_M_AMT || 10834 hw->device_id == E1000_DEV_ID_ICH8_IGP_M || 10835 hw->mac_type == em_pchlan || 10836 hw->mac_type == em_pch2lan || 10837 hw->mac_type == em_pch_lpt || 10838 hw->mac_type == em_pch_spt || 10839 hw->mac_type == em_pch_cnp) 10840 sw_cfg_mask = FEXTNVM_SW_CONFIG_ICH8M; 10841 else 10842 sw_cfg_mask = FEXTNVM_SW_CONFIG; 10843 10844 reg_data = E1000_READ_REG(hw, FEXTNVM); 10845 if (!(reg_data & sw_cfg_mask)) 10846 return E1000_SUCCESS; 10847 10848 /* Wait for basic configuration completes before proceeding */ 10849 loop = 0; 10850 do { 10851 reg_data = 10852 E1000_READ_REG(hw, STATUS) & E1000_STATUS_LAN_INIT_DONE; 10853 usec_delay(100); 10854 loop++; 10855 } while ((!reg_data) && (loop < 50)); 10856 10857 /* Clear the Init Done bit for the next init event */ 10858 reg_data = E1000_READ_REG(hw, STATUS); 10859 reg_data &= ~E1000_STATUS_LAN_INIT_DONE; 10860 E1000_WRITE_REG(hw, STATUS, reg_data); 10861 /* 10862 * Make sure HW does not configure LCD from PHY extended 10863 * configuration before SW configuration 10864 */ 10865 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL); 10866 if ((reg_data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) == 0x0000) { 10867 reg_data = E1000_READ_REG(hw, EXTCNF_SIZE); 10868 cnf_size = reg_data & E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH; 10869 cnf_size >>= 16; 10870 if (cnf_size) { 10871 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL); 10872 cnf_base_addr = reg_data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER; 10873 /* cnf_base_addr is in DWORD */ 10874 cnf_base_addr >>= 16; 10875 10876 /* Configure LCD from extended configuration region. */ 10877 ret_val = em_init_lcd_from_nvm_config_region(hw, 10878 cnf_base_addr, cnf_size); 10879 if (ret_val) 10880 return ret_val; 10881 } 10882 } 10883 return E1000_SUCCESS; 10884 } 10885 10886 /****************************************************************************** 10887 * em_set_pciex_completion_timeout - set pci-e completion timeout 10888 * 10889 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms, 10890 * however the hardware default for these parts is 500us to 1ms which is less 10891 * than the 10ms recommended by the pci-e spec. To address this we need to 10892 * increase the value to either 10ms to 200ms for capability version 1 config, 10893 * or 16ms to 55ms for version 2. 10894 * 10895 * * hw - pointer to em_hw structure 10896 *****************************************************************************/ 10897 int32_t 10898 em_set_pciex_completion_timeout(struct em_hw *hw) 10899 { 10900 uint32_t gcr = E1000_READ_REG(hw, GCR); 10901 int32_t ret_val = E1000_SUCCESS; 10902 10903 /* Only take action if timeout value is not set by system BIOS */ 10904 if (gcr & E1000_GCR_CMPL_TMOUT_MASK) 10905 goto out; 10906 10907 DEBUGOUT("PCIe completion timeout not set by system BIOS."); 10908 10909 /* 10910 * If capababilities version is type 1 we can write the 10911 * timeout of 10ms to 200ms through the GCR register 10912 */ 10913 10914 if (!(gcr & E1000_GCR_CAP_VER2)) { 10915 gcr |= E1000_GCR_CMPL_TMOUT_10ms; 10916 DEBUGOUT("PCIe capability version 1 detected, setting \ 10917 completion timeout to 10ms."); 10918 goto out; 10919 } 10920 10921 /* 10922 * For version 2 capabilities we need to write the config space 10923 * directly in order to set the completion timeout value for 10924 * 16ms to 55ms 10925 * 10926 * XXX: Implement em_*_pcie_cap_reg() first. 10927 */ 10928 #if 0 10929 ret_val = em_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 10930 &pciex_devctl2); 10931 10932 if (ret_val) 10933 goto out; 10934 10935 pciex_devctl2 |= PCIE_DEVICE_CONTROL2_16ms; 10936 10937 ret_val = em_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 10938 &pciex_devctl2); 10939 #endif 10940 10941 out: 10942 10943 /* Disable completion timeout resend */ 10944 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND; 10945 10946 DEBUGOUT("PCIe completion timeout resend disabled."); 10947 10948 E1000_WRITE_REG(hw, GCR, gcr); 10949 return ret_val; 10950 } 10951 10952 /*************************************************************************** 10953 * Set slow MDIO access mode 10954 ***************************************************************************/ 10955 static int32_t 10956 em_set_mdio_slow_mode_hv(struct em_hw *hw) 10957 { 10958 int32_t ret_val; 10959 uint16_t data; 10960 DEBUGFUNC("em_set_mdio_slow_mode_hv"); 10961 10962 ret_val = em_read_phy_reg(hw, HV_KMRN_MODE_CTRL, &data); 10963 if (ret_val) 10964 return ret_val; 10965 10966 data |= HV_KMRN_MDIO_SLOW; 10967 10968 ret_val = em_write_phy_reg(hw, HV_KMRN_MODE_CTRL, data); 10969 10970 return ret_val; 10971 } 10972 10973 /*************************************************************************** 10974 * A series of Phy workarounds to be done after every PHY reset. 10975 ***************************************************************************/ 10976 int32_t 10977 em_hv_phy_workarounds_ich8lan(struct em_hw *hw) 10978 { 10979 int32_t ret_val = E1000_SUCCESS; 10980 uint16_t phy_data; 10981 uint16_t swfw; 10982 DEBUGFUNC("em_hv_phy_workarounds_ich8lan"); 10983 10984 if (hw->mac_type != em_pchlan) 10985 goto out; 10986 10987 swfw = E1000_SWFW_PHY0_SM; 10988 10989 /* Set MDIO slow mode before any other MDIO access */ 10990 if (hw->phy_type == em_phy_82577 || 10991 hw->phy_type == em_phy_82578) { 10992 ret_val = em_set_mdio_slow_mode_hv(hw); 10993 if (ret_val) 10994 goto out; 10995 } 10996 10997 /* Hanksville M Phy init for IEEE. */ 10998 if ((hw->revision_id == 2) && 10999 (hw->phy_type == em_phy_82577) && 11000 ((hw->phy_revision == 2) || (hw->phy_revision == 3))) { 11001 em_write_phy_reg(hw, 0x10, 0x8823); 11002 em_write_phy_reg(hw, 0x11, 0x0018); 11003 em_write_phy_reg(hw, 0x10, 0x8824); 11004 em_write_phy_reg(hw, 0x11, 0x0016); 11005 em_write_phy_reg(hw, 0x10, 0x8825); 11006 em_write_phy_reg(hw, 0x11, 0x001A); 11007 em_write_phy_reg(hw, 0x10, 0x888C); 11008 em_write_phy_reg(hw, 0x11, 0x0007); 11009 em_write_phy_reg(hw, 0x10, 0x888D); 11010 em_write_phy_reg(hw, 0x11, 0x0007); 11011 em_write_phy_reg(hw, 0x10, 0x888E); 11012 em_write_phy_reg(hw, 0x11, 0x0007); 11013 em_write_phy_reg(hw, 0x10, 0x8827); 11014 em_write_phy_reg(hw, 0x11, 0x0001); 11015 em_write_phy_reg(hw, 0x10, 0x8835); 11016 em_write_phy_reg(hw, 0x11, 0x0001); 11017 em_write_phy_reg(hw, 0x10, 0x8834); 11018 em_write_phy_reg(hw, 0x11, 0x0001); 11019 em_write_phy_reg(hw, 0x10, 0x8833); 11020 em_write_phy_reg(hw, 0x11, 0x0002); 11021 } 11022 11023 if (((hw->phy_type == em_phy_82577) && 11024 ((hw->phy_revision == 1) || (hw->phy_revision == 2))) || 11025 ((hw->phy_type == em_phy_82578) && (hw->phy_revision == 1))) { 11026 /* Disable generation of early preamble */ 11027 ret_val = em_write_phy_reg(hw, PHY_REG(769, 25), 0x4431); 11028 if (ret_val) 11029 goto out; 11030 11031 /* Preamble tuning for SSC */ 11032 ret_val = em_write_phy_reg(hw, PHY_REG(770, 16), 0xA204); 11033 if (ret_val) 11034 goto out; 11035 } 11036 11037 if (hw->phy_type == em_phy_82578) { 11038 /* 11039 * Return registers to default by doing a soft reset then 11040 * writing 0x3140 to the control register. 11041 */ 11042 if (hw->phy_revision < 2) { 11043 em_phy_reset(hw); 11044 ret_val = em_write_phy_reg(hw, PHY_CTRL, 0x3140); 11045 } 11046 } 11047 11048 if ((hw->revision_id == 2) && 11049 (hw->phy_type == em_phy_82577) && 11050 ((hw->phy_revision == 2) || (hw->phy_revision == 3))) { 11051 /* 11052 * Workaround for OEM (GbE) not operating after reset - 11053 * restart AN (twice) 11054 */ 11055 ret_val = em_write_phy_reg(hw, PHY_REG(0, 25), 0x0400); 11056 if (ret_val) 11057 goto out; 11058 ret_val = em_write_phy_reg(hw, PHY_REG(0, 25), 0x0400); 11059 if (ret_val) 11060 goto out; 11061 } 11062 11063 /* Select page 0 */ 11064 ret_val = em_swfw_sync_acquire(hw, swfw); 11065 if (ret_val) 11066 goto out; 11067 11068 hw->phy_addr = 1; 11069 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT, 0); 11070 em_swfw_sync_release(hw, swfw); 11071 if (ret_val) 11072 goto out; 11073 11074 /* Workaround for link disconnects on a busy hub in half duplex */ 11075 ret_val = em_read_phy_reg(hw, 11076 PHY_REG(BM_PORT_CTRL_PAGE, 17), 11077 &phy_data); 11078 if (ret_val) 11079 goto release; 11080 ret_val = em_write_phy_reg(hw, 11081 PHY_REG(BM_PORT_CTRL_PAGE, 17), 11082 phy_data & 0x00FF); 11083 release: 11084 out: 11085 return ret_val; 11086 } 11087 11088 11089 /*************************************************************************** 11090 * Si workaround 11091 * 11092 * This function works around a Si bug where the link partner can get 11093 * a link up indication before the PHY does. If small packets are sent 11094 * by the link partner they can be placed in the packet buffer without 11095 * being properly accounted for by the PHY and will stall preventing 11096 * further packets from being received. The workaround is to clear the 11097 * packet buffer after the PHY detects link up. 11098 ***************************************************************************/ 11099 int32_t 11100 em_link_stall_workaround_hv(struct em_hw *hw) 11101 { 11102 int32_t ret_val = E1000_SUCCESS; 11103 uint16_t phy_data; 11104 11105 if (hw->phy_type != em_phy_82578) 11106 goto out; 11107 11108 /* Do not apply workaround if in PHY loopback bit 14 set */ 11109 em_read_phy_reg(hw, PHY_CTRL, &phy_data); 11110 if (phy_data & E1000_PHY_CTRL_LOOPBACK) 11111 goto out; 11112 11113 /* check if link is up and at 1Gbps */ 11114 ret_val = em_read_phy_reg(hw, BM_CS_STATUS, &phy_data); 11115 if (ret_val) 11116 goto out; 11117 11118 phy_data &= BM_CS_STATUS_LINK_UP | 11119 BM_CS_STATUS_RESOLVED | 11120 BM_CS_STATUS_SPEED_MASK; 11121 11122 if (phy_data != (BM_CS_STATUS_LINK_UP | 11123 BM_CS_STATUS_RESOLVED | 11124 BM_CS_STATUS_SPEED_1000)) 11125 goto out; 11126 11127 msec_delay(200); 11128 11129 /* flush the packets in the fifo buffer */ 11130 ret_val = em_write_phy_reg(hw, HV_MUX_DATA_CTRL, 11131 HV_MUX_DATA_CTRL_GEN_TO_MAC | HV_MUX_DATA_CTRL_FORCE_SPEED); 11132 if (ret_val) 11133 goto out; 11134 11135 ret_val = em_write_phy_reg(hw, HV_MUX_DATA_CTRL, 11136 HV_MUX_DATA_CTRL_GEN_TO_MAC); 11137 11138 out: 11139 return ret_val; 11140 } 11141 11142 /**************************************************************************** 11143 * K1 Si workaround 11144 * 11145 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning 11146 * from a lower speed. This workaround disables K1 whenever link is at 1Gig. 11147 * If link is down, the function will restore the default K1 setting located 11148 * in the NVM. 11149 ****************************************************************************/ 11150 int32_t 11151 em_k1_gig_workaround_hv(struct em_hw *hw, boolean_t link) 11152 { 11153 int32_t ret_val; 11154 uint16_t phy_data; 11155 boolean_t k1_enable; 11156 11157 DEBUGFUNC("em_k1_gig_workaround_hv"); 11158 11159 if (hw->mac_type != em_pchlan) 11160 return E1000_SUCCESS; 11161 11162 ret_val = em_read_eeprom_ich8(hw, E1000_NVM_K1_CONFIG, 1, &phy_data); 11163 if (ret_val) 11164 return ret_val; 11165 11166 k1_enable = phy_data & E1000_NVM_K1_ENABLE ? TRUE : FALSE; 11167 11168 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */ 11169 if (link) { 11170 if (hw->phy_type == em_phy_82578) { 11171 ret_val = em_read_phy_reg(hw, BM_CS_STATUS, 11172 &phy_data); 11173 if (ret_val) 11174 return ret_val; 11175 11176 phy_data &= BM_CS_STATUS_LINK_UP | 11177 BM_CS_STATUS_RESOLVED | 11178 BM_CS_STATUS_SPEED_MASK; 11179 11180 if (phy_data == (BM_CS_STATUS_LINK_UP | 11181 BM_CS_STATUS_RESOLVED | 11182 BM_CS_STATUS_SPEED_1000)) 11183 k1_enable = FALSE; 11184 } 11185 11186 if (hw->phy_type == em_phy_82577) { 11187 ret_val = em_read_phy_reg(hw, HV_M_STATUS, 11188 &phy_data); 11189 if (ret_val) 11190 return ret_val; 11191 11192 phy_data &= HV_M_STATUS_LINK_UP | 11193 HV_M_STATUS_AUTONEG_COMPLETE | 11194 HV_M_STATUS_SPEED_MASK; 11195 11196 if (phy_data == (HV_M_STATUS_LINK_UP | 11197 HV_M_STATUS_AUTONEG_COMPLETE | 11198 HV_M_STATUS_SPEED_1000)) 11199 k1_enable = FALSE; 11200 } 11201 11202 /* Link stall fix for link up */ 11203 ret_val = em_write_phy_reg(hw, PHY_REG(770, 19), 11204 0x0100); 11205 if (ret_val) 11206 return ret_val; 11207 11208 } else { 11209 /* Link stall fix for link down */ 11210 ret_val = em_write_phy_reg(hw, PHY_REG(770, 19), 11211 0x4100); 11212 if (ret_val) 11213 return ret_val; 11214 } 11215 11216 ret_val = em_configure_k1_ich8lan(hw, k1_enable); 11217 11218 return ret_val; 11219 } 11220 11221 /* Workaround to set the K1 beacon duration for 82579 parts */ 11222 int32_t 11223 em_k1_workaround_lv(struct em_hw *hw) 11224 { 11225 int32_t ret_val; 11226 uint16_t phy_data; 11227 uint32_t mac_reg; 11228 11229 ret_val = em_read_phy_reg(hw, BM_CS_STATUS, &phy_data); 11230 if (ret_val) 11231 return ret_val; 11232 11233 if ((phy_data & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) 11234 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) { 11235 mac_reg = E1000_READ_REG(hw, FEXTNVM4); 11236 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK; 11237 11238 if (phy_data & HV_M_STATUS_SPEED_1000) 11239 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC; 11240 else 11241 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC; 11242 11243 E1000_WRITE_REG(hw, FEXTNVM4, mac_reg); 11244 } 11245 11246 return E1000_SUCCESS; 11247 } 11248 11249 /** 11250 * em_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP 11251 * 11252 * When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications 11253 * preventing further DMA write requests. Workaround the issue by disabling 11254 * the de-assertion of the clock request when in 1Gbps mode. 11255 * Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link 11256 * speeds in order to avoid Tx hangs. 11257 **/ 11258 int32_t 11259 em_k1_workaround_lpt_lp(struct em_hw *hw, boolean_t link) 11260 { 11261 uint32_t fextnvm6 = E1000_READ_REG(hw, FEXTNVM6); 11262 uint32_t status = E1000_READ_REG(hw, STATUS); 11263 int32_t ret_val = E1000_SUCCESS; 11264 uint16_t reg; 11265 11266 if (link && (status & E1000_STATUS_SPEED_1000)) { 11267 ret_val = em_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 11268 ®); 11269 if (ret_val) 11270 return ret_val; 11271 11272 ret_val = em_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 11273 reg & ~E1000_KMRNCTRLSTA_K1_ENABLE); 11274 if (ret_val) 11275 return ret_val; 11276 11277 usec_delay(10); 11278 11279 E1000_WRITE_REG(hw, FEXTNVM6, 11280 fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK); 11281 11282 ret_val = em_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 11283 reg); 11284 } else { 11285 /* clear FEXTNVM6 bit 8 on link down or 10/100 */ 11286 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK; 11287 11288 if (!link || ((status & E1000_STATUS_SPEED_100) && 11289 (status & E1000_STATUS_FD))) 11290 goto update_fextnvm6; 11291 11292 ret_val = em_read_phy_reg(hw, I217_INBAND_CTRL, ®); 11293 if (ret_val) 11294 return ret_val; 11295 11296 /* Clear link status transmit timeout */ 11297 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK; 11298 11299 if (status & E1000_STATUS_SPEED_100) { 11300 /* Set inband Tx timeout to 5x10us for 100Half */ 11301 reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT; 11302 11303 /* Do not extend the K1 entry latency for 100Half */ 11304 fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION; 11305 } else { 11306 /* Set inband Tx timeout to 50x10us for 10Full/Half */ 11307 reg |= 50 << 11308 I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT; 11309 11310 /* Extend the K1 entry latency for 10 Mbps */ 11311 fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION; 11312 } 11313 11314 ret_val = em_write_phy_reg(hw, I217_INBAND_CTRL, reg); 11315 if (ret_val) 11316 return ret_val; 11317 11318 update_fextnvm6: 11319 E1000_WRITE_REG(hw, FEXTNVM6, fextnvm6); 11320 } 11321 11322 return ret_val; 11323 11324 } 11325 11326 11327 /*************************************************************************** 11328 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware 11329 * @hw: pointer to the HW structure 11330 * @gate: boolean set to TRUE to gate, FALSE to ungate 11331 * 11332 * Gate/ungate the automatic PHY configuration via hardware; perform 11333 * the configuration via software instead. 11334 ***************************************************************************/ 11335 void 11336 em_gate_hw_phy_config_ich8lan(struct em_hw *hw, boolean_t gate) 11337 { 11338 uint32_t extcnf_ctrl; 11339 11340 DEBUGFUNC("em_gate_hw_phy_config_ich8lan"); 11341 11342 if (hw->mac_type != em_pch2lan) 11343 return; 11344 11345 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 11346 11347 if (gate) 11348 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG; 11349 else 11350 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG; 11351 11352 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); 11353 } 11354 11355 /*************************************************************************** 11356 * Configure K1 power state 11357 * 11358 * Configure the K1 power state based on the provided parameter. 11359 * Assumes semaphore already acquired. 11360 * 11361 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 11362 ***************************************************************************/ 11363 int32_t 11364 em_configure_k1_ich8lan(struct em_hw *hw, boolean_t k1_enable) 11365 { 11366 int32_t ret_val = E1000_SUCCESS; 11367 uint32_t ctrl_reg = 0; 11368 uint32_t ctrl_ext = 0; 11369 uint32_t reg = 0; 11370 uint16_t kmrn_reg = 0; 11371 11372 ret_val = em_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 11373 &kmrn_reg); 11374 if (ret_val) 11375 goto out; 11376 11377 if (k1_enable) 11378 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE; 11379 else 11380 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE; 11381 11382 ret_val = em_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 11383 kmrn_reg); 11384 if (ret_val) 11385 goto out; 11386 11387 usec_delay(20); 11388 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 11389 ctrl_reg = E1000_READ_REG(hw, CTRL); 11390 11391 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 11392 reg |= E1000_CTRL_FRCSPD; 11393 E1000_WRITE_REG(hw, CTRL, reg); 11394 11395 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS); 11396 usec_delay(20); 11397 E1000_WRITE_REG(hw, CTRL, ctrl_reg); 11398 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 11399 usec_delay(20); 11400 11401 out: 11402 return ret_val; 11403 } 11404 11405 /*************************************************************************** 11406 * em_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be 11407 * done after every PHY reset. 11408 ***************************************************************************/ 11409 int32_t 11410 em_lv_phy_workarounds_ich8lan(struct em_hw *hw) 11411 { 11412 int32_t ret_val = E1000_SUCCESS; 11413 uint16_t swfw; 11414 11415 DEBUGFUNC("e1000_lv_phy_workarounds_ich8lan"); 11416 11417 if (hw->mac_type != em_pch2lan) 11418 goto out; 11419 11420 /* Set MDIO slow mode before any other MDIO access */ 11421 ret_val = em_set_mdio_slow_mode_hv(hw); 11422 11423 swfw = E1000_SWFW_PHY0_SM; 11424 ret_val = em_swfw_sync_acquire(hw, swfw); 11425 if (ret_val) 11426 goto out; 11427 ret_val = em_write_phy_reg(hw, I82579_EMI_ADDR, 11428 I82579_MSE_THRESHOLD); 11429 if (ret_val) 11430 goto release; 11431 /* set MSE higher to enable link to stay up when noise is high */ 11432 ret_val = em_write_phy_reg(hw, I82579_EMI_DATA, 11433 0x0034); 11434 if (ret_val) 11435 goto release; 11436 ret_val = em_write_phy_reg(hw, I82579_EMI_ADDR, 11437 I82579_MSE_LINK_DOWN); 11438 if (ret_val) 11439 goto release; 11440 /* drop link after 5 times MSE threshold was reached */ 11441 ret_val = em_write_phy_reg(hw, I82579_EMI_DATA, 11442 0x0005); 11443 release: 11444 em_swfw_sync_release(hw, swfw); 11445 11446 out: 11447 return ret_val; 11448 } 11449 11450 int32_t 11451 em_set_eee_i350(struct em_hw *hw) 11452 { 11453 int32_t ret_val = E1000_SUCCESS; 11454 uint32_t ipcnfg, eeer; 11455 11456 if ((hw->mac_type < em_i350) || 11457 (hw->media_type != em_media_type_copper)) 11458 goto out; 11459 ipcnfg = EM_READ_REG(hw, E1000_IPCNFG); 11460 eeer = EM_READ_REG(hw, E1000_EEER); 11461 11462 if (hw->eee_enable) { 11463 ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN); 11464 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN | 11465 E1000_EEER_LPI_FC); 11466 } else { 11467 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN); 11468 eeer &= ~(E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN | 11469 E1000_EEER_LPI_FC); 11470 } 11471 EM_WRITE_REG(hw, E1000_IPCNFG, ipcnfg); 11472 EM_WRITE_REG(hw, E1000_EEER, eeer); 11473 EM_READ_REG(hw, E1000_IPCNFG); 11474 EM_READ_REG(hw, E1000_EEER); 11475 out: 11476 return ret_val; 11477 } 11478 11479 /*************************************************************************** 11480 * em_set_eee_pchlan - Enable/disable EEE support 11481 * @hw: pointer to the HW structure 11482 * 11483 * Enable/disable EEE based on setting in dev_spec structure. The bits in 11484 * the LPI Control register will remain set only if/when link is up. 11485 ***************************************************************************/ 11486 int32_t 11487 em_set_eee_pchlan(struct em_hw *hw) 11488 { 11489 int32_t ret_val = E1000_SUCCESS; 11490 uint16_t phy_reg; 11491 11492 DEBUGFUNC("em_set_eee_pchlan"); 11493 11494 if (hw->phy_type != em_phy_82579 && 11495 hw->phy_type != em_phy_i217) 11496 goto out; 11497 11498 ret_val = em_read_phy_reg(hw, I82579_LPI_CTRL, &phy_reg); 11499 if (ret_val) 11500 goto out; 11501 11502 if (hw->eee_enable) 11503 phy_reg &= ~I82579_LPI_CTRL_ENABLE_MASK; 11504 else 11505 phy_reg |= I82579_LPI_CTRL_ENABLE_MASK; 11506 11507 ret_val = em_write_phy_reg(hw, I82579_LPI_CTRL, phy_reg); 11508 out: 11509 return ret_val; 11510 } 11511 11512 /** 11513 * em_initialize_M88E1512_phy - Initialize M88E1512 PHY 11514 * @hw: pointer to the HW structure 11515 * 11516 * Initialize Marvell 1512 to work correctly with Avoton. 11517 **/ 11518 int32_t 11519 em_initialize_M88E1512_phy(struct em_hw *hw) 11520 { 11521 int32_t ret_val = E1000_SUCCESS; 11522 11523 DEBUGFUNC("e1000_initialize_M88E1512_phy"); 11524 11525 /* Check if this is correct PHY. */ 11526 if (hw->phy_id != M88E1512_E_PHY_ID) 11527 goto out; 11528 11529 /* Switch to PHY page 0xFF. */ 11530 ret_val = em_write_phy_reg(hw, M88E1543_PAGE_ADDR, 0x00FF); 11531 if (ret_val) 11532 goto out; 11533 11534 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_2, 0x214B); 11535 if (ret_val) 11536 goto out; 11537 11538 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_1, 0x2144); 11539 if (ret_val) 11540 goto out; 11541 11542 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_2, 0x0C28); 11543 if (ret_val) 11544 goto out; 11545 11546 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_1, 0x2146); 11547 if (ret_val) 11548 goto out; 11549 11550 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_2, 0xB233); 11551 if (ret_val) 11552 goto out; 11553 11554 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_1, 0x214D); 11555 if (ret_val) 11556 goto out; 11557 11558 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_2, 0xCC0C); 11559 if (ret_val) 11560 goto out; 11561 11562 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_1, 0x2159); 11563 if (ret_val) 11564 goto out; 11565 11566 /* Switch to PHY page 0xFB. */ 11567 ret_val = em_write_phy_reg(hw, M88E1543_PAGE_ADDR, 0x00FB); 11568 if (ret_val) 11569 goto out; 11570 11571 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_3, 0x000D); 11572 if (ret_val) 11573 goto out; 11574 11575 /* Switch to PHY page 0x12. */ 11576 ret_val = em_write_phy_reg(hw, M88E1543_PAGE_ADDR, 0x12); 11577 if (ret_val) 11578 goto out; 11579 11580 /* Change mode to SGMII-to-Copper */ 11581 ret_val = em_write_phy_reg(hw, M88E1512_MODE, 0x8001); 11582 if (ret_val) 11583 goto out; 11584 11585 /* Return the PHY to page 0. */ 11586 ret_val = em_write_phy_reg(hw, M88E1543_PAGE_ADDR, 0); 11587 if (ret_val) 11588 goto out; 11589 11590 ret_val = em_phy_hw_reset(hw); 11591 if (ret_val) { 11592 DEBUGOUT("Error committing the PHY changes\n"); 11593 return ret_val; 11594 } 11595 11596 msec_delay(1000); 11597 out: 11598 return ret_val; 11599 } 11600 11601 uint32_t 11602 em_translate_82542_register(uint32_t reg) 11603 { 11604 /* 11605 * Some of the 82542 registers are located at different 11606 * offsets than they are in newer adapters. 11607 * Despite the difference in location, the registers 11608 * function in the same manner. 11609 */ 11610 switch (reg) { 11611 case E1000_RA: 11612 reg = 0x00040; 11613 break; 11614 case E1000_RDTR: 11615 reg = 0x00108; 11616 break; 11617 case E1000_RDBAL(0): 11618 reg = 0x00110; 11619 break; 11620 case E1000_RDBAH(0): 11621 reg = 0x00114; 11622 break; 11623 case E1000_RDLEN(0): 11624 reg = 0x00118; 11625 break; 11626 case E1000_RDH(0): 11627 reg = 0x00120; 11628 break; 11629 case E1000_RDT(0): 11630 reg = 0x00128; 11631 break; 11632 case E1000_RDBAL(1): 11633 reg = 0x00138; 11634 break; 11635 case E1000_RDBAH(1): 11636 reg = 0x0013C; 11637 break; 11638 case E1000_RDLEN(1): 11639 reg = 0x00140; 11640 break; 11641 case E1000_RDH(1): 11642 reg = 0x00148; 11643 break; 11644 case E1000_RDT(1): 11645 reg = 0x00150; 11646 break; 11647 case E1000_FCRTH: 11648 reg = 0x00160; 11649 break; 11650 case E1000_FCRTL: 11651 reg = 0x00168; 11652 break; 11653 case E1000_MTA: 11654 reg = 0x00200; 11655 break; 11656 case E1000_TDBAL(0): 11657 reg = 0x00420; 11658 break; 11659 case E1000_TDBAH(0): 11660 reg = 0x00424; 11661 break; 11662 case E1000_TDLEN(0): 11663 reg = 0x00428; 11664 break; 11665 case E1000_TDH(0): 11666 reg = 0x00430; 11667 break; 11668 case E1000_TDT(0): 11669 reg = 0x00438; 11670 break; 11671 case E1000_TIDV: 11672 reg = 0x00440; 11673 break; 11674 case E1000_VFTA: 11675 reg = 0x00600; 11676 break; 11677 case E1000_TDFH: 11678 reg = 0x08010; 11679 break; 11680 case E1000_TDFT: 11681 reg = 0x08018; 11682 break; 11683 default: 11684 break; 11685 } 11686 11687 return (reg); 11688 } 11689