1 /******************************************************************************* 2 3 Copyright (c) 2001-2005, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 *******************************************************************************/ 33 34 /* $OpenBSD: if_em_hw.c,v 1.79 2014/03/10 04:09:53 jsg Exp $ */ 35 /* 36 * if_em_hw.c Shared functions for accessing and configuring the MAC 37 */ 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/sockio.h> 42 #include <sys/mbuf.h> 43 #include <sys/malloc.h> 44 #include <sys/kernel.h> 45 #include <sys/device.h> 46 #include <sys/socket.h> 47 48 #include <net/if.h> 49 #include <net/if_dl.h> 50 #include <net/if_media.h> 51 52 #ifdef INET 53 #include <netinet/in.h> 54 #include <netinet/in_systm.h> 55 #include <netinet/ip.h> 56 #include <netinet/if_ether.h> 57 #endif 58 59 #include <uvm/uvm_extern.h> 60 61 #include <dev/pci/pcireg.h> 62 #include <dev/pci/pcivar.h> 63 #include <dev/pci/pcidevs.h> 64 65 #include <dev/pci/if_em_hw.h> 66 #include <dev/pci/if_em_soc.h> 67 68 #define STATIC 69 70 static int32_t em_swfw_sync_acquire(struct em_hw *, uint16_t); 71 static void em_swfw_sync_release(struct em_hw *, uint16_t); 72 static int32_t em_read_kmrn_reg(struct em_hw *, uint32_t, uint16_t *); 73 static int32_t em_write_kmrn_reg(struct em_hw *hw, uint32_t, uint16_t); 74 static int32_t em_get_software_semaphore(struct em_hw *); 75 static void em_release_software_semaphore(struct em_hw *); 76 77 static int32_t em_check_downshift(struct em_hw *); 78 static void em_clear_vfta(struct em_hw *); 79 void em_clear_vfta_i350(struct em_hw *); 80 static int32_t em_commit_shadow_ram(struct em_hw *); 81 static int32_t em_config_dsp_after_link_change(struct em_hw *, boolean_t); 82 static int32_t em_config_fc_after_link_up(struct em_hw *); 83 static int32_t em_match_gig_phy(struct em_hw *); 84 static int32_t em_detect_gig_phy(struct em_hw *); 85 static int32_t em_erase_ich8_4k_segment(struct em_hw *, uint32_t); 86 static int32_t em_get_auto_rd_done(struct em_hw *); 87 static int32_t em_get_cable_length(struct em_hw *, uint16_t *, uint16_t *); 88 static int32_t em_get_hw_eeprom_semaphore(struct em_hw *); 89 static int32_t em_get_phy_cfg_done(struct em_hw *); 90 static int32_t em_get_software_flag(struct em_hw *); 91 static int32_t em_ich8_cycle_init(struct em_hw *); 92 static int32_t em_ich8_flash_cycle(struct em_hw *, uint32_t); 93 static int32_t em_id_led_init(struct em_hw *); 94 static int32_t em_init_lcd_from_nvm_config_region(struct em_hw *, uint32_t, 95 uint32_t); 96 static int32_t em_init_lcd_from_nvm(struct em_hw *); 97 static void em_init_rx_addrs(struct em_hw *); 98 static void em_initialize_hardware_bits(struct em_hw *); 99 static boolean_t em_is_onboard_nvm_eeprom(struct em_hw *); 100 static int32_t em_kumeran_lock_loss_workaround(struct em_hw *); 101 static int32_t em_mng_enable_host_if(struct em_hw *); 102 static int32_t em_read_eeprom_eerd(struct em_hw *, uint16_t, uint16_t, 103 uint16_t *); 104 static int32_t em_write_eeprom_eewr(struct em_hw *, uint16_t, uint16_t, 105 uint16_t *data); 106 static int32_t em_poll_eerd_eewr_done(struct em_hw *, int); 107 static void em_put_hw_eeprom_semaphore(struct em_hw *); 108 static int32_t em_read_ich8_byte(struct em_hw *, uint32_t, uint8_t *); 109 static int32_t em_verify_write_ich8_byte(struct em_hw *, uint32_t, uint8_t); 110 static int32_t em_write_ich8_byte(struct em_hw *, uint32_t, uint8_t); 111 static int32_t em_read_ich8_word(struct em_hw *, uint32_t, uint16_t *); 112 static int32_t em_read_ich8_data(struct em_hw *, uint32_t, uint32_t, 113 uint16_t *); 114 static int32_t em_write_ich8_data(struct em_hw *, uint32_t, uint32_t, 115 uint16_t); 116 static int32_t em_read_eeprom_ich8(struct em_hw *, uint16_t, uint16_t, 117 uint16_t *); 118 static int32_t em_write_eeprom_ich8(struct em_hw *, uint16_t, uint16_t, 119 uint16_t *); 120 static void em_release_software_flag(struct em_hw *); 121 static int32_t em_set_d3_lplu_state(struct em_hw *, boolean_t); 122 static int32_t em_set_d0_lplu_state(struct em_hw *, boolean_t); 123 static int32_t em_set_lplu_state_pchlan(struct em_hw *, boolean_t); 124 static int32_t em_set_pci_ex_no_snoop(struct em_hw *, uint32_t); 125 static void em_set_pci_express_master_disable(struct em_hw *); 126 static int32_t em_wait_autoneg(struct em_hw *); 127 static void em_write_reg_io(struct em_hw *, uint32_t, uint32_t); 128 static int32_t em_set_phy_type(struct em_hw *); 129 static void em_phy_init_script(struct em_hw *); 130 static int32_t em_setup_copper_link(struct em_hw *); 131 static int32_t em_setup_fiber_serdes_link(struct em_hw *); 132 static int32_t em_adjust_serdes_amplitude(struct em_hw *); 133 static int32_t em_phy_force_speed_duplex(struct em_hw *); 134 static int32_t em_config_mac_to_phy(struct em_hw *); 135 static void em_raise_mdi_clk(struct em_hw *, uint32_t *); 136 static void em_lower_mdi_clk(struct em_hw *, uint32_t *); 137 static void em_shift_out_mdi_bits(struct em_hw *, uint32_t, uint16_t); 138 static uint16_t em_shift_in_mdi_bits(struct em_hw *); 139 static int32_t em_phy_reset_dsp(struct em_hw *); 140 static int32_t em_write_eeprom_spi(struct em_hw *, uint16_t, uint16_t, 141 uint16_t *); 142 static int32_t em_write_eeprom_microwire(struct em_hw *, uint16_t, uint16_t, 143 uint16_t *); 144 static int32_t em_spi_eeprom_ready(struct em_hw *); 145 static void em_raise_ee_clk(struct em_hw *, uint32_t *); 146 static void em_lower_ee_clk(struct em_hw *, uint32_t *); 147 static void em_shift_out_ee_bits(struct em_hw *, uint16_t, uint16_t); 148 static int32_t em_write_phy_reg_ex(struct em_hw *, uint32_t, uint16_t); 149 static int32_t em_read_phy_reg_ex(struct em_hw *, uint32_t, uint16_t *); 150 static uint16_t em_shift_in_ee_bits(struct em_hw *, uint16_t); 151 static int32_t em_acquire_eeprom(struct em_hw *); 152 static void em_release_eeprom(struct em_hw *); 153 static void em_standby_eeprom(struct em_hw *); 154 static int32_t em_set_vco_speed(struct em_hw *); 155 static int32_t em_polarity_reversal_workaround(struct em_hw *); 156 static int32_t em_set_phy_mode(struct em_hw *); 157 static int32_t em_host_if_read_cookie(struct em_hw *, uint8_t *); 158 static uint8_t em_calculate_mng_checksum(char *, uint32_t); 159 static int32_t em_configure_kmrn_for_10_100(struct em_hw *, uint16_t); 160 static int32_t em_configure_kmrn_for_1000(struct em_hw *); 161 static int32_t em_set_pciex_completion_timeout(struct em_hw *hw); 162 static int32_t em_set_mdio_slow_mode_hv(struct em_hw *); 163 int32_t em_hv_phy_workarounds_ich8lan(struct em_hw *); 164 int32_t em_lv_phy_workarounds_ich8lan(struct em_hw *); 165 int32_t em_link_stall_workaround_hv(struct em_hw *); 166 int32_t em_k1_gig_workaround_hv(struct em_hw *, boolean_t); 167 int32_t em_k1_workaround_lv(struct em_hw *); 168 int32_t em_configure_k1_ich8lan(struct em_hw *, boolean_t); 169 void em_gate_hw_phy_config_ich8lan(struct em_hw *, boolean_t); 170 int32_t em_access_phy_wakeup_reg_bm(struct em_hw *, uint32_t, 171 uint16_t *, boolean_t); 172 int32_t em_access_phy_debug_regs_hv(struct em_hw *, uint32_t, 173 uint16_t *, boolean_t); 174 int32_t em_access_phy_reg_hv(struct em_hw *, uint32_t, uint16_t *, 175 boolean_t); 176 int32_t em_oem_bits_config_pchlan(struct em_hw *, boolean_t); 177 void em_power_up_serdes_link_82575(struct em_hw *); 178 int32_t em_get_pcs_speed_and_duplex_82575(struct em_hw *, uint16_t *, 179 uint16_t *); 180 int32_t em_set_eee_i350(struct em_hw *); 181 int32_t em_set_eee_pchlan(struct em_hw *); 182 int32_t em_valid_nvm_bank_detect_ich8lan(struct em_hw *, uint32_t *); 183 184 185 /* IGP cable length table */ 186 static const uint16_t 187 em_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = 188 {5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 189 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25, 190 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40, 191 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60, 192 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90, 193 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 194 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 195 110, 196 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 197 120}; 198 199 static const uint16_t 200 em_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] = 201 {0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 202 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 203 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 204 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 205 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 206 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 207 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 208 121, 124}; 209 210 /****************************************************************************** 211 * Set the phy type member in the hw struct. 212 * 213 * hw - Struct containing variables accessed by shared code 214 *****************************************************************************/ 215 STATIC int32_t 216 em_set_phy_type(struct em_hw *hw) 217 { 218 DEBUGFUNC("em_set_phy_type"); 219 220 if (hw->mac_type == em_undefined) 221 return -E1000_ERR_PHY_TYPE; 222 223 switch (hw->phy_id) { 224 case M88E1000_E_PHY_ID: 225 case M88E1000_I_PHY_ID: 226 case M88E1011_I_PHY_ID: 227 case M88E1111_I_PHY_ID: 228 case M88E1112_E_PHY_ID: 229 case M88E1543_E_PHY_ID: 230 case I210_I_PHY_ID: 231 case I347AT4_E_PHY_ID: 232 hw->phy_type = em_phy_m88; 233 break; 234 case IGP01E1000_I_PHY_ID: 235 if (hw->mac_type == em_82541 || 236 hw->mac_type == em_82541_rev_2 || 237 hw->mac_type == em_82547 || 238 hw->mac_type == em_82547_rev_2) { 239 hw->phy_type = em_phy_igp; 240 break; 241 } 242 case IGP03E1000_E_PHY_ID: 243 case IGP04E1000_E_PHY_ID: 244 hw->phy_type = em_phy_igp_3; 245 break; 246 case IFE_E_PHY_ID: 247 case IFE_PLUS_E_PHY_ID: 248 case IFE_C_E_PHY_ID: 249 hw->phy_type = em_phy_ife; 250 break; 251 case M88E1141_E_PHY_ID: 252 hw->phy_type = em_phy_oem; 253 break; 254 case I82577_E_PHY_ID: 255 hw->phy_type = em_phy_82577; 256 break; 257 case I82578_E_PHY_ID: 258 hw->phy_type = em_phy_82578; 259 break; 260 case I82579_E_PHY_ID: 261 hw->phy_type = em_phy_82579; 262 break; 263 case I217_E_PHY_ID: 264 hw->phy_type = em_phy_i217; 265 break; 266 case I82580_I_PHY_ID: 267 case I350_I_PHY_ID: 268 hw->phy_type = em_phy_82580; 269 break; 270 case BME1000_E_PHY_ID: 271 if (hw->phy_revision == 1) { 272 hw->phy_type = em_phy_bm; 273 break; 274 } 275 /* FALLTHROUGH */ 276 case GG82563_E_PHY_ID: 277 if (hw->mac_type == em_80003es2lan) { 278 hw->phy_type = em_phy_gg82563; 279 break; 280 } 281 /* FALLTHROUGH */ 282 default: 283 /* Should never have loaded on this device */ 284 hw->phy_type = em_phy_undefined; 285 return -E1000_ERR_PHY_TYPE; 286 } 287 288 return E1000_SUCCESS; 289 } 290 291 /****************************************************************************** 292 * IGP phy init script - initializes the GbE PHY 293 * 294 * hw - Struct containing variables accessed by shared code 295 *****************************************************************************/ 296 static void 297 em_phy_init_script(struct em_hw *hw) 298 { 299 uint16_t phy_saved_data; 300 DEBUGFUNC("em_phy_init_script"); 301 302 if (hw->phy_init_script) { 303 msec_delay(20); 304 /* 305 * Save off the current value of register 0x2F5B to be 306 * restored at the end of this routine. 307 */ 308 em_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 309 310 /* Disabled the PHY transmitter */ 311 em_write_phy_reg(hw, 0x2F5B, 0x0003); 312 msec_delay(20); 313 em_write_phy_reg(hw, 0x0000, 0x0140); 314 msec_delay(5); 315 316 switch (hw->mac_type) { 317 case em_82541: 318 case em_82547: 319 em_write_phy_reg(hw, 0x1F95, 0x0001); 320 em_write_phy_reg(hw, 0x1F71, 0xBD21); 321 em_write_phy_reg(hw, 0x1F79, 0x0018); 322 em_write_phy_reg(hw, 0x1F30, 0x1600); 323 em_write_phy_reg(hw, 0x1F31, 0x0014); 324 em_write_phy_reg(hw, 0x1F32, 0x161C); 325 em_write_phy_reg(hw, 0x1F94, 0x0003); 326 em_write_phy_reg(hw, 0x1F96, 0x003F); 327 em_write_phy_reg(hw, 0x2010, 0x0008); 328 break; 329 case em_82541_rev_2: 330 case em_82547_rev_2: 331 em_write_phy_reg(hw, 0x1F73, 0x0099); 332 break; 333 default: 334 break; 335 } 336 337 em_write_phy_reg(hw, 0x0000, 0x3300); 338 msec_delay(20); 339 340 /* Now enable the transmitter */ 341 em_write_phy_reg(hw, 0x2F5B, phy_saved_data); 342 343 if (hw->mac_type == em_82547) { 344 uint16_t fused, fine, coarse; 345 /* Move to analog registers page */ 346 em_read_phy_reg(hw, 347 IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused); 348 349 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { 350 em_read_phy_reg(hw, 351 IGP01E1000_ANALOG_FUSE_STATUS, &fused); 352 353 fine = fused & 354 IGP01E1000_ANALOG_FUSE_FINE_MASK; 355 coarse = fused & 356 IGP01E1000_ANALOG_FUSE_COARSE_MASK; 357 358 if (coarse > 359 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { 360 coarse -= 361 IGP01E1000_ANALOG_FUSE_COARSE_10; 362 fine -= 363 IGP01E1000_ANALOG_FUSE_FINE_1; 364 } else if (coarse == 365 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) 366 fine -= IGP01E1000_ANALOG_FUSE_FINE_10; 367 368 fused = (fused & 369 IGP01E1000_ANALOG_FUSE_POLY_MASK) | 370 (fine & 371 IGP01E1000_ANALOG_FUSE_FINE_MASK) | 372 (coarse & 373 IGP01E1000_ANALOG_FUSE_COARSE_MASK); 374 375 em_write_phy_reg(hw, 376 IGP01E1000_ANALOG_FUSE_CONTROL, 377 fused); 378 379 em_write_phy_reg(hw, 380 IGP01E1000_ANALOG_FUSE_BYPASS, 381 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL); 382 } 383 } 384 } 385 } 386 387 /****************************************************************************** 388 * Set the mac type member in the hw struct. 389 * 390 * hw - Struct containing variables accessed by shared code 391 *****************************************************************************/ 392 int32_t 393 em_set_mac_type(struct em_hw *hw) 394 { 395 DEBUGFUNC("em_set_mac_type"); 396 397 switch (hw->device_id) { 398 case E1000_DEV_ID_82542: 399 switch (hw->revision_id) { 400 case E1000_82542_2_0_REV_ID: 401 hw->mac_type = em_82542_rev2_0; 402 break; 403 case E1000_82542_2_1_REV_ID: 404 hw->mac_type = em_82542_rev2_1; 405 break; 406 default: 407 /* Invalid 82542 revision ID */ 408 return -E1000_ERR_MAC_TYPE; 409 } 410 break; 411 case E1000_DEV_ID_82543GC_FIBER: 412 case E1000_DEV_ID_82543GC_COPPER: 413 hw->mac_type = em_82543; 414 break; 415 case E1000_DEV_ID_82544EI_COPPER: 416 case E1000_DEV_ID_82544EI_FIBER: 417 case E1000_DEV_ID_82544GC_COPPER: 418 case E1000_DEV_ID_82544GC_LOM: 419 hw->mac_type = em_82544; 420 break; 421 case E1000_DEV_ID_82540EM: 422 case E1000_DEV_ID_82540EM_LOM: 423 case E1000_DEV_ID_82540EP: 424 case E1000_DEV_ID_82540EP_LOM: 425 case E1000_DEV_ID_82540EP_LP: 426 hw->mac_type = em_82540; 427 break; 428 case E1000_DEV_ID_82545EM_COPPER: 429 case E1000_DEV_ID_82545EM_FIBER: 430 hw->mac_type = em_82545; 431 break; 432 case E1000_DEV_ID_82545GM_COPPER: 433 case E1000_DEV_ID_82545GM_FIBER: 434 case E1000_DEV_ID_82545GM_SERDES: 435 hw->mac_type = em_82545_rev_3; 436 break; 437 case E1000_DEV_ID_82546EB_COPPER: 438 case E1000_DEV_ID_82546EB_FIBER: 439 case E1000_DEV_ID_82546EB_QUAD_COPPER: 440 hw->mac_type = em_82546; 441 break; 442 case E1000_DEV_ID_82546GB_COPPER: 443 case E1000_DEV_ID_82546GB_FIBER: 444 case E1000_DEV_ID_82546GB_SERDES: 445 case E1000_DEV_ID_82546GB_PCIE: 446 case E1000_DEV_ID_82546GB_QUAD_COPPER: 447 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 448 case E1000_DEV_ID_82546GB_2: 449 hw->mac_type = em_82546_rev_3; 450 break; 451 case E1000_DEV_ID_82541EI: 452 case E1000_DEV_ID_82541EI_MOBILE: 453 case E1000_DEV_ID_82541ER_LOM: 454 hw->mac_type = em_82541; 455 break; 456 case E1000_DEV_ID_82541ER: 457 case E1000_DEV_ID_82541GI: 458 case E1000_DEV_ID_82541GI_LF: 459 case E1000_DEV_ID_82541GI_MOBILE: 460 hw->mac_type = em_82541_rev_2; 461 break; 462 case E1000_DEV_ID_82547EI: 463 case E1000_DEV_ID_82547EI_MOBILE: 464 hw->mac_type = em_82547; 465 break; 466 case E1000_DEV_ID_82547GI: 467 hw->mac_type = em_82547_rev_2; 468 break; 469 case E1000_DEV_ID_82571EB_AF: 470 case E1000_DEV_ID_82571EB_AT: 471 case E1000_DEV_ID_82571EB_COPPER: 472 case E1000_DEV_ID_82571EB_FIBER: 473 case E1000_DEV_ID_82571EB_SERDES: 474 case E1000_DEV_ID_82571EB_QUAD_COPPER: 475 case E1000_DEV_ID_82571EB_QUAD_FIBER: 476 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 477 case E1000_DEV_ID_82571EB_SERDES_DUAL: 478 case E1000_DEV_ID_82571EB_SERDES_QUAD: 479 case E1000_DEV_ID_82571PT_QUAD_COPPER: 480 hw->mac_type = em_82571; 481 break; 482 case E1000_DEV_ID_82572EI_COPPER: 483 case E1000_DEV_ID_82572EI_FIBER: 484 case E1000_DEV_ID_82572EI_SERDES: 485 case E1000_DEV_ID_82572EI: 486 hw->mac_type = em_82572; 487 break; 488 case E1000_DEV_ID_82573E: 489 case E1000_DEV_ID_82573E_IAMT: 490 case E1000_DEV_ID_82573E_PM: 491 case E1000_DEV_ID_82573L: 492 case E1000_DEV_ID_82573L_PL_1: 493 case E1000_DEV_ID_82573L_PL_2: 494 case E1000_DEV_ID_82573V_PM: 495 hw->mac_type = em_82573; 496 break; 497 case E1000_DEV_ID_82574L: 498 case E1000_DEV_ID_82574LA: 499 case E1000_DEV_ID_82583V: 500 hw->mac_type = em_82574; 501 break; 502 case E1000_DEV_ID_82575EB_PT: 503 case E1000_DEV_ID_82575EB_PF: 504 case E1000_DEV_ID_82575GB_QP: 505 case E1000_DEV_ID_82575GB_QP_PM: 506 case E1000_DEV_ID_82576: 507 case E1000_DEV_ID_82576_FIBER: 508 case E1000_DEV_ID_82576_SERDES: 509 case E1000_DEV_ID_82576_QUAD_COPPER: 510 case E1000_DEV_ID_82576_QUAD_CU_ET2: 511 case E1000_DEV_ID_82576_NS: 512 case E1000_DEV_ID_82576_NS_SERDES: 513 case E1000_DEV_ID_82576_SERDES_QUAD: 514 hw->mac_type = em_82575; 515 hw->initialize_hw_bits_disable = 1; 516 break; 517 case E1000_DEV_ID_82580_COPPER: 518 case E1000_DEV_ID_82580_FIBER: 519 case E1000_DEV_ID_82580_QUAD_FIBER: 520 case E1000_DEV_ID_82580_SERDES: 521 case E1000_DEV_ID_82580_SGMII: 522 case E1000_DEV_ID_82580_COPPER_DUAL: 523 case E1000_DEV_ID_DH89XXCC_SGMII: 524 case E1000_DEV_ID_DH89XXCC_SERDES: 525 case E1000_DEV_ID_DH89XXCC_BACKPLANE: 526 case E1000_DEV_ID_DH89XXCC_SFP: 527 hw->mac_type = em_82580; 528 hw->initialize_hw_bits_disable = 1; 529 break; 530 case E1000_DEV_ID_I210_COPPER: 531 case E1000_DEV_ID_I210_FIBER: 532 case E1000_DEV_ID_I210_SERDES: 533 case E1000_DEV_ID_I210_SGMII: 534 case E1000_DEV_ID_I210_COPPER_FLASHLESS: 535 case E1000_DEV_ID_I210_SERDES_FLASHLESS: 536 case E1000_DEV_ID_I211_COPPER: 537 hw->mac_type = em_i210; 538 hw->initialize_hw_bits_disable = 1; 539 hw->eee_enable = 1; 540 break; 541 case E1000_DEV_ID_I350_COPPER: 542 case E1000_DEV_ID_I350_FIBER: 543 case E1000_DEV_ID_I350_SERDES: 544 case E1000_DEV_ID_I350_SGMII: 545 case E1000_DEV_ID_I350_DA4: 546 case E1000_DEV_ID_I354_BACKPLANE_1GBPS: 547 case E1000_DEV_ID_I354_SGMII: 548 case E1000_DEV_ID_I354_BACKPLANE_2_5GBPS: 549 hw->mac_type = em_i350; 550 hw->initialize_hw_bits_disable = 1; 551 hw->eee_enable = 1; 552 break; 553 case E1000_DEV_ID_80003ES2LAN_COPPER_SPT: 554 case E1000_DEV_ID_80003ES2LAN_SERDES_SPT: 555 case E1000_DEV_ID_80003ES2LAN_COPPER_DPT: 556 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: 557 hw->mac_type = em_80003es2lan; 558 break; 559 case E1000_DEV_ID_ICH8_IFE: 560 case E1000_DEV_ID_ICH8_IFE_G: 561 case E1000_DEV_ID_ICH8_IFE_GT: 562 case E1000_DEV_ID_ICH8_IGP_AMT: 563 case E1000_DEV_ID_ICH8_IGP_C: 564 case E1000_DEV_ID_ICH8_IGP_M: 565 case E1000_DEV_ID_ICH8_IGP_M_AMT: 566 case E1000_DEV_ID_ICH8_82567V_3: 567 hw->mac_type = em_ich8lan; 568 break; 569 case E1000_DEV_ID_ICH9_BM: 570 case E1000_DEV_ID_ICH9_IFE: 571 case E1000_DEV_ID_ICH9_IFE_G: 572 case E1000_DEV_ID_ICH9_IFE_GT: 573 case E1000_DEV_ID_ICH9_IGP_AMT: 574 case E1000_DEV_ID_ICH9_IGP_C: 575 case E1000_DEV_ID_ICH9_IGP_M: 576 case E1000_DEV_ID_ICH9_IGP_M_AMT: 577 case E1000_DEV_ID_ICH9_IGP_M_V: 578 case E1000_DEV_ID_ICH10_R_BM_LF: 579 case E1000_DEV_ID_ICH10_R_BM_LM: 580 case E1000_DEV_ID_ICH10_R_BM_V: 581 hw->mac_type = em_ich9lan; 582 break; 583 case E1000_DEV_ID_ICH10_D_BM_LF: 584 case E1000_DEV_ID_ICH10_D_BM_LM: 585 hw->mac_type = em_ich10lan; 586 break; 587 case E1000_DEV_ID_PCH_M_HV_LC: 588 case E1000_DEV_ID_PCH_M_HV_LM: 589 case E1000_DEV_ID_PCH_D_HV_DC: 590 case E1000_DEV_ID_PCH_D_HV_DM: 591 hw->mac_type = em_pchlan; 592 hw->eee_enable = 1; 593 break; 594 case E1000_DEV_ID_PCH2_LV_LM: 595 case E1000_DEV_ID_PCH2_LV_V: 596 hw->mac_type = em_pch2lan; 597 break; 598 case E1000_DEV_ID_PCH_LPT_I217_LM: 599 case E1000_DEV_ID_PCH_LPT_I217_V: 600 case E1000_DEV_ID_PCH_LPTLP_I218_LM: 601 case E1000_DEV_ID_PCH_LPTLP_I218_V: 602 case E1000_DEV_ID_PCH_I218_LM2: 603 case E1000_DEV_ID_PCH_I218_V2: 604 case E1000_DEV_ID_PCH_I218_LM3: 605 case E1000_DEV_ID_PCH_I218_V3: 606 hw->mac_type = em_pch_lpt; 607 break; 608 case E1000_DEV_ID_EP80579_LAN_1: 609 hw->mac_type = em_icp_xxxx; 610 hw->icp_xxxx_port_num = 0; 611 break; 612 case E1000_DEV_ID_EP80579_LAN_2: 613 hw->mac_type = em_icp_xxxx; 614 hw->icp_xxxx_port_num = 1; 615 break; 616 case E1000_DEV_ID_EP80579_LAN_3: 617 hw->mac_type = em_icp_xxxx; 618 hw->icp_xxxx_port_num = 2; 619 break; 620 default: 621 /* Should never have loaded on this device */ 622 return -E1000_ERR_MAC_TYPE; 623 } 624 625 switch (hw->mac_type) { 626 case em_ich8lan: 627 case em_ich9lan: 628 case em_ich10lan: 629 case em_pchlan: 630 case em_pch2lan: 631 case em_pch_lpt: 632 hw->swfwhw_semaphore_present = TRUE; 633 hw->asf_firmware_present = TRUE; 634 break; 635 case em_80003es2lan: 636 case em_82575: 637 case em_82580: 638 case em_i210: 639 case em_i350: 640 hw->swfw_sync_present = TRUE; 641 /* FALLTHROUGH */ 642 case em_82571: 643 case em_82572: 644 case em_82573: 645 case em_82574: 646 hw->eeprom_semaphore_present = TRUE; 647 /* FALLTHROUGH */ 648 case em_82541: 649 case em_82547: 650 case em_82541_rev_2: 651 case em_82547_rev_2: 652 hw->asf_firmware_present = TRUE; 653 break; 654 default: 655 break; 656 } 657 658 return E1000_SUCCESS; 659 } 660 /***************************************************************************** 661 * Set media type and TBI compatibility. 662 * 663 * hw - Struct containing variables accessed by shared code 664 * **************************************************************************/ 665 void 666 em_set_media_type(struct em_hw *hw) 667 { 668 uint32_t status, ctrl_ext; 669 DEBUGFUNC("em_set_media_type"); 670 671 if (hw->mac_type != em_82543) { 672 /* tbi_compatibility is only valid on 82543 */ 673 hw->tbi_compatibility_en = FALSE; 674 } 675 676 if (hw->mac_type == em_82575 || hw->mac_type == em_82580 || 677 hw->mac_type == em_i210 || hw->mac_type == em_i350) { 678 hw->media_type = em_media_type_copper; 679 680 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 681 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) { 682 case E1000_CTRL_EXT_LINK_MODE_SGMII: 683 ctrl_ext |= E1000_CTRL_I2C_ENA; 684 break; 685 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: 686 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES: 687 hw->media_type = em_media_type_internal_serdes; 688 ctrl_ext |= E1000_CTRL_I2C_ENA; 689 break; 690 default: 691 ctrl_ext &= ~E1000_CTRL_I2C_ENA; 692 break; 693 } 694 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 695 return; 696 } 697 698 switch (hw->device_id) { 699 case E1000_DEV_ID_82545GM_SERDES: 700 case E1000_DEV_ID_82546GB_SERDES: 701 case E1000_DEV_ID_82571EB_SERDES: 702 case E1000_DEV_ID_82571EB_SERDES_DUAL: 703 case E1000_DEV_ID_82571EB_SERDES_QUAD: 704 case E1000_DEV_ID_82572EI_SERDES: 705 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: 706 hw->media_type = em_media_type_internal_serdes; 707 break; 708 case E1000_DEV_ID_EP80579_LAN_1: 709 case E1000_DEV_ID_EP80579_LAN_2: 710 case E1000_DEV_ID_EP80579_LAN_3: 711 hw->media_type = em_media_type_oem; 712 break; 713 default: 714 switch (hw->mac_type) { 715 case em_82542_rev2_0: 716 case em_82542_rev2_1: 717 hw->media_type = em_media_type_fiber; 718 break; 719 case em_ich8lan: 720 case em_ich9lan: 721 case em_ich10lan: 722 case em_pchlan: 723 case em_pch2lan: 724 case em_pch_lpt: 725 case em_82573: 726 case em_82574: 727 /* 728 * The STATUS_TBIMODE bit is reserved or reused for 729 * the this device. 730 */ 731 hw->media_type = em_media_type_copper; 732 break; 733 default: 734 status = E1000_READ_REG(hw, STATUS); 735 if (status & E1000_STATUS_TBIMODE) { 736 hw->media_type = em_media_type_fiber; 737 /* tbi_compatibility not valid on fiber */ 738 hw->tbi_compatibility_en = FALSE; 739 } else { 740 hw->media_type = em_media_type_copper; 741 } 742 break; 743 } 744 } 745 } 746 /****************************************************************************** 747 * Reset the transmit and receive units; mask and clear all interrupts. 748 * 749 * hw - Struct containing variables accessed by shared code 750 *****************************************************************************/ 751 int32_t 752 em_reset_hw(struct em_hw *hw) 753 { 754 uint32_t ctrl; 755 uint32_t ctrl_ext; 756 uint32_t icr; 757 uint32_t manc; 758 uint32_t led_ctrl; 759 uint32_t timeout; 760 uint32_t extcnf_ctrl; 761 int32_t ret_val; 762 DEBUGFUNC("em_reset_hw"); 763 764 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ 765 if (hw->mac_type == em_82542_rev2_0) { 766 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 767 em_pci_clear_mwi(hw); 768 } 769 if (hw->bus_type == em_bus_type_pci_express) { 770 /* 771 * Prevent the PCI-E bus from sticking if there is no TLP 772 * connection on the last TLP read/write transaction when MAC 773 * is reset. 774 */ 775 if (em_disable_pciex_master(hw) != E1000_SUCCESS) { 776 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 777 } 778 } 779 780 /* Set the completion timeout for 82575 chips */ 781 if (hw->mac_type == em_82575 || hw->mac_type == em_82580 || 782 hw->mac_type == em_i210 || hw->mac_type == em_i350) { 783 ret_val = em_set_pciex_completion_timeout(hw); 784 if (ret_val) { 785 DEBUGOUT("PCI-E Set completion timeout has failed.\n"); 786 } 787 } 788 789 /* Clear interrupt mask to stop board from generating interrupts */ 790 DEBUGOUT("Masking off all interrupts\n"); 791 E1000_WRITE_REG(hw, IMC, 0xffffffff); 792 /* 793 * Disable the Transmit and Receive units. Then delay to allow any 794 * pending transactions to complete before we hit the MAC with the 795 * global reset. 796 */ 797 E1000_WRITE_REG(hw, RCTL, 0); 798 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP); 799 E1000_WRITE_FLUSH(hw); 800 /* 801 * The tbi_compatibility_on Flag must be cleared when Rctl is 802 * cleared. 803 */ 804 hw->tbi_compatibility_on = FALSE; 805 /* 806 * Delay to allow any outstanding PCI transactions to complete before 807 * resetting the device 808 */ 809 msec_delay(10); 810 811 ctrl = E1000_READ_REG(hw, CTRL); 812 813 /* Must reset the PHY before resetting the MAC */ 814 if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) { 815 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST)); 816 msec_delay(5); 817 } 818 /* 819 * Must acquire the MDIO ownership before MAC reset. Ownership 820 * defaults to firmware after a reset. 821 */ 822 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) { 823 timeout = 10; 824 825 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 826 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 827 828 do { 829 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); 830 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 831 832 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) 833 break; 834 else 835 extcnf_ctrl |= 836 E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 837 838 msec_delay(2); 839 timeout--; 840 } while (timeout); 841 } 842 /* Workaround for ICH8 bit corruption issue in FIFO memory */ 843 if (hw->mac_type == em_ich8lan) { 844 /* Set Tx and Rx buffer allocation to 8k apiece. */ 845 E1000_WRITE_REG(hw, PBA, E1000_PBA_8K); 846 /* Set Packet Buffer Size to 16k. */ 847 E1000_WRITE_REG(hw, PBS, E1000_PBS_16K); 848 } 849 /* 850 * Issue a global reset to the MAC. This will reset the chip's 851 * transmit, receive, DMA, and link units. It will not effect the 852 * current PCI configuration. The global reset bit is self- 853 * clearing, and should clear within a microsecond. 854 */ 855 DEBUGOUT("Issuing a global reset to MAC\n"); 856 857 switch (hw->mac_type) { 858 case em_82544: 859 case em_82540: 860 case em_82545: 861 case em_82546: 862 case em_82541: 863 case em_82541_rev_2: 864 /* 865 * These controllers can't ack the 64-bit write when issuing 866 * the reset, so use IO-mapping as a workaround to issue the 867 * reset 868 */ 869 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST)); 870 break; 871 case em_82545_rev_3: 872 case em_82546_rev_3: 873 /* Reset is performed on a shadow of the control register */ 874 E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST)); 875 break; 876 case em_ich8lan: 877 case em_ich9lan: 878 case em_ich10lan: 879 case em_pchlan: 880 case em_pch2lan: 881 case em_pch_lpt: 882 if (!hw->phy_reset_disable && 883 em_check_phy_reset_block(hw) == E1000_SUCCESS) { 884 /* 885 * PHY HW reset requires MAC CORE reset at the same 886 * time to make sure the interface between MAC and 887 * the external PHY is reset. 888 */ 889 ctrl |= E1000_CTRL_PHY_RST; 890 /* 891 * Gate automatic PHY configuration by hardware on 892 * non-managed 82579 893 */ 894 if ((hw->mac_type == em_pch2lan) && 895 !(E1000_READ_REG(hw, FWSM) & E1000_FWSM_FW_VALID)) { 896 em_gate_hw_phy_config_ich8lan(hw, TRUE); 897 } 898 } 899 em_get_software_flag(hw); 900 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); 901 msec_delay(5); 902 903 /* Ungate automatic PHY configuration on non-managed 82579 */ 904 if (hw->mac_type == em_pch2lan && !hw->phy_reset_disable && 905 !(E1000_READ_REG(hw, FWSM) & E1000_FWSM_FW_VALID)) { 906 msec_delay(10); 907 em_gate_hw_phy_config_ich8lan(hw, FALSE); 908 } 909 break; 910 default: 911 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); 912 break; 913 } 914 915 if (em_check_phy_reset_block(hw) == E1000_SUCCESS) { 916 if (hw->mac_type == em_pchlan) { 917 ret_val = em_hv_phy_workarounds_ich8lan(hw); 918 if (ret_val) 919 return ret_val; 920 } 921 else if (hw->mac_type == em_pch2lan) { 922 ret_val = em_lv_phy_workarounds_ich8lan(hw); 923 if (ret_val) 924 return ret_val; 925 } 926 } 927 928 /* 929 * After MAC reset, force reload of EEPROM to restore power-on 930 * settings to device. Later controllers reload the EEPROM 931 * automatically, so just wait for reload to complete. 932 */ 933 switch (hw->mac_type) { 934 case em_82542_rev2_0: 935 case em_82542_rev2_1: 936 case em_82543: 937 case em_82544: 938 /* Wait for reset to complete */ 939 usec_delay(10); 940 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 941 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 942 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 943 E1000_WRITE_FLUSH(hw); 944 /* Wait for EEPROM reload */ 945 msec_delay(2); 946 break; 947 case em_82541: 948 case em_82541_rev_2: 949 case em_82547: 950 case em_82547_rev_2: 951 /* Wait for EEPROM reload */ 952 msec_delay(20); 953 break; 954 case em_82573: 955 case em_82574: 956 if (em_is_onboard_nvm_eeprom(hw) == FALSE) { 957 usec_delay(10); 958 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 959 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 960 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 961 E1000_WRITE_FLUSH(hw); 962 } 963 /* FALLTHROUGH */ 964 965 /* Auto read done will delay 5ms or poll based on mac type */ 966 ret_val = em_get_auto_rd_done(hw); 967 if (ret_val) 968 return ret_val; 969 break; 970 default: 971 /* Wait for EEPROM reload (it happens automatically) */ 972 msec_delay(5); 973 break; 974 } 975 976 /* Disable HW ARPs on ASF enabled adapters */ 977 if (hw->mac_type >= em_82540 && hw->mac_type <= em_82547_rev_2 && 978 hw->mac_type != em_icp_xxxx) { 979 manc = E1000_READ_REG(hw, MANC); 980 manc &= ~(E1000_MANC_ARP_EN); 981 E1000_WRITE_REG(hw, MANC, manc); 982 } 983 if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) { 984 em_phy_init_script(hw); 985 986 /* Configure activity LED after PHY reset */ 987 led_ctrl = E1000_READ_REG(hw, LEDCTL); 988 led_ctrl &= IGP_ACTIVITY_LED_MASK; 989 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 990 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 991 } 992 993 /* 994 * For PCH, this write will make sure that any noise 995 * will be detected as a CRC error and be dropped rather than show up 996 * as a bad packet to the DMA engine. 997 */ 998 if (hw->mac_type == em_pchlan) 999 E1000_WRITE_REG(hw, CRC_OFFSET, 0x65656565); 1000 1001 /* Clear interrupt mask to stop board from generating interrupts */ 1002 DEBUGOUT("Masking off all interrupts\n"); 1003 E1000_WRITE_REG(hw, IMC, 0xffffffff); 1004 1005 /* Clear any pending interrupt events. */ 1006 icr = E1000_READ_REG(hw, ICR); 1007 1008 /* If MWI was previously enabled, reenable it. */ 1009 if (hw->mac_type == em_82542_rev2_0) { 1010 if (hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1011 em_pci_set_mwi(hw); 1012 } 1013 if (IS_ICH8(hw->mac_type)) { 1014 uint32_t kab = E1000_READ_REG(hw, KABGTXD); 1015 kab |= E1000_KABGTXD_BGSQLBIAS; 1016 E1000_WRITE_REG(hw, KABGTXD, kab); 1017 } 1018 1019 if (hw->mac_type == em_82580 || hw->mac_type == em_i350) { 1020 uint32_t mdicnfg; 1021 uint16_t nvm_data; 1022 1023 /* clear global device reset status bit */ 1024 EM_WRITE_REG(hw, E1000_STATUS, E1000_STATUS_DEV_RST_SET); 1025 1026 em_read_eeprom(hw, EEPROM_INIT_CONTROL3_PORT_A + 1027 NVM_82580_LAN_FUNC_OFFSET(hw->bus_func), 1, 1028 &nvm_data); 1029 1030 mdicnfg = EM_READ_REG(hw, E1000_MDICNFG); 1031 if (nvm_data & NVM_WORD24_EXT_MDIO) 1032 mdicnfg |= E1000_MDICNFG_EXT_MDIO; 1033 if (nvm_data & NVM_WORD24_COM_MDIO) 1034 mdicnfg |= E1000_MDICNFG_COM_MDIO; 1035 EM_WRITE_REG(hw, E1000_MDICNFG, mdicnfg); 1036 } 1037 1038 if (hw->mac_type == em_i210 || hw->mac_type == em_i350) 1039 em_set_eee_i350(hw); 1040 1041 return E1000_SUCCESS; 1042 } 1043 1044 /****************************************************************************** 1045 * 1046 * Initialize a number of hardware-dependent bits 1047 * 1048 * hw: Struct containing variables accessed by shared code 1049 * 1050 *****************************************************************************/ 1051 STATIC void 1052 em_initialize_hardware_bits(struct em_hw *hw) 1053 { 1054 DEBUGFUNC("em_initialize_hardware_bits"); 1055 1056 if ((hw->mac_type >= em_82571) && (!hw->initialize_hw_bits_disable)) { 1057 /* Settings common to all silicon */ 1058 uint32_t reg_ctrl, reg_ctrl_ext; 1059 uint32_t reg_tarc0, reg_tarc1; 1060 uint32_t reg_tctl; 1061 uint32_t reg_txdctl, reg_txdctl1; 1062 reg_tarc0 = E1000_READ_REG(hw, TARC0); 1063 reg_tarc0 &= ~0x78000000; /* Clear bits 30, 29, 28, and 1064 * 27 */ 1065 1066 reg_txdctl = E1000_READ_REG(hw, TXDCTL); 1067 reg_txdctl |= E1000_TXDCTL_COUNT_DESC; /* Set bit 22 */ 1068 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl); 1069 1070 reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1); 1071 reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC; /* Set bit 22 */ 1072 E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1); 1073 1074 switch (hw->mac_type) { 1075 case em_82571: 1076 case em_82572: 1077 reg_tarc1 = E1000_READ_REG(hw, TARC1); 1078 reg_tctl = E1000_READ_REG(hw, TCTL); 1079 1080 /* Set the phy Tx compatible mode bits */ 1081 reg_tarc1 &= ~0x60000000; /* Clear bits 30 and 29 */ 1082 1083 reg_tarc0 |= 0x07800000; /* Set TARC0 bits 23-26 */ 1084 reg_tarc1 |= 0x07000000; /* Set TARC1 bits 24-26 */ 1085 1086 if (reg_tctl & E1000_TCTL_MULR) 1087 /* Clear bit 28 if MULR is 1b */ 1088 reg_tarc1 &= ~0x10000000; 1089 else 1090 /* Set bit 28 if MULR is 0b */ 1091 reg_tarc1 |= 0x10000000; 1092 1093 E1000_WRITE_REG(hw, TARC1, reg_tarc1); 1094 break; 1095 case em_82573: 1096 case em_82574: 1097 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1098 reg_ctrl = E1000_READ_REG(hw, CTRL); 1099 1100 reg_ctrl_ext &= ~0x00800000; /* Clear bit 23 */ 1101 reg_ctrl_ext |= 0x00400000; /* Set bit 22 */ 1102 reg_ctrl &= ~0x20000000; /* Clear bit 29 */ 1103 1104 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); 1105 E1000_WRITE_REG(hw, CTRL, reg_ctrl); 1106 break; 1107 case em_80003es2lan: 1108 if ((hw->media_type == em_media_type_fiber) || 1109 (hw->media_type == em_media_type_internal_serdes)) { 1110 /* Clear bit 20 */ 1111 reg_tarc0 &= ~0x00100000; 1112 } 1113 reg_tctl = E1000_READ_REG(hw, TCTL); 1114 reg_tarc1 = E1000_READ_REG(hw, TARC1); 1115 if (reg_tctl & E1000_TCTL_MULR) 1116 /* Clear bit 28 if MULR is 1b */ 1117 reg_tarc1 &= ~0x10000000; 1118 else 1119 /* Set bit 28 if MULR is 0b */ 1120 reg_tarc1 |= 0x10000000; 1121 1122 E1000_WRITE_REG(hw, TARC1, reg_tarc1); 1123 break; 1124 case em_ich8lan: 1125 case em_ich9lan: 1126 case em_ich10lan: 1127 case em_pchlan: 1128 case em_pch2lan: 1129 case em_pch_lpt: 1130 if (hw->mac_type == em_ich8lan) 1131 /* Set TARC0 bits 29 and 28 */ 1132 reg_tarc0 |= 0x30000000; 1133 1134 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1135 reg_ctrl_ext |= 0x00400000; /* Set bit 22 */ 1136 /* Enable PHY low-power state when MAC is at D3 w/o WoL */ 1137 if (hw->mac_type >= em_pchlan) 1138 reg_ctrl_ext |= E1000_CTRL_EXT_PHYPDEN; 1139 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); 1140 1141 reg_tarc0 |= 0x0d800000; /* Set TARC0 bits 23, 1142 * 24, 26, 27 */ 1143 1144 reg_tarc1 = E1000_READ_REG(hw, TARC1); 1145 reg_tctl = E1000_READ_REG(hw, TCTL); 1146 1147 if (reg_tctl & E1000_TCTL_MULR) 1148 /* Clear bit 28 if MULR is 1b */ 1149 reg_tarc1 &= ~0x10000000; 1150 else 1151 /* Set bit 28 if MULR is 0b */ 1152 reg_tarc1 |= 0x10000000; 1153 1154 reg_tarc1 |= 0x45000000; /* Set bit 24, 26 and 1155 * 30 */ 1156 1157 E1000_WRITE_REG(hw, TARC1, reg_tarc1); 1158 break; 1159 default: 1160 break; 1161 } 1162 1163 E1000_WRITE_REG(hw, TARC0, reg_tarc0); 1164 } 1165 } 1166 1167 /****************************************************************************** 1168 * Performs basic configuration of the adapter. 1169 * 1170 * hw - Struct containing variables accessed by shared code 1171 * 1172 * Assumes that the controller has previously been reset and is in a 1173 * post-reset uninitialized state. Initializes the receive address registers, 1174 * multicast table, and VLAN filter table. Calls routines to setup link 1175 * configuration and flow control settings. Clears all on-chip counters. Leaves 1176 * the transmit and receive units disabled and uninitialized. 1177 *****************************************************************************/ 1178 int32_t 1179 em_init_hw(struct em_hw *hw) 1180 { 1181 uint32_t ctrl; 1182 uint32_t i; 1183 int32_t ret_val; 1184 uint16_t pcix_cmd_word; 1185 uint16_t pcix_stat_hi_word; 1186 uint16_t cmd_mmrbc; 1187 uint16_t stat_mmrbc; 1188 uint32_t mta_size; 1189 uint32_t reg_data; 1190 uint32_t ctrl_ext; 1191 uint32_t snoop; 1192 uint32_t fwsm; 1193 DEBUGFUNC("em_init_hw"); 1194 1195 /* force full DMA clock frequency for ICH8 */ 1196 if (hw->mac_type == em_ich8lan) { 1197 reg_data = E1000_READ_REG(hw, STATUS); 1198 reg_data &= ~0x80000000; 1199 E1000_WRITE_REG(hw, STATUS, reg_data); 1200 } 1201 1202 if (hw->mac_type == em_pchlan || 1203 hw->mac_type == em_pch2lan || 1204 hw->mac_type == em_pch_lpt) { 1205 /* 1206 * The MAC-PHY interconnect may still be in SMBus mode 1207 * after Sx->S0. Toggle the LANPHYPC Value bit to force 1208 * the interconnect to PCIe mode, but only if there is no 1209 * firmware present otherwise firmware will have done it. 1210 */ 1211 fwsm = E1000_READ_REG(hw, FWSM); 1212 if ((fwsm & E1000_FWSM_FW_VALID) == 0) { 1213 ctrl = E1000_READ_REG(hw, CTRL); 1214 ctrl |= E1000_CTRL_LANPHYPC_OVERRIDE; 1215 ctrl &= ~E1000_CTRL_LANPHYPC_VALUE; 1216 E1000_WRITE_REG(hw, CTRL, ctrl); 1217 usec_delay(10); 1218 ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE; 1219 E1000_WRITE_REG(hw, CTRL, ctrl); 1220 msec_delay(50); 1221 } 1222 1223 /* Gate automatic PHY configuration on non-managed 82579 */ 1224 if (hw->mac_type == em_pch2lan) 1225 em_gate_hw_phy_config_ich8lan(hw, TRUE); 1226 1227 /* 1228 * Reset the PHY before any acccess to it. Doing so, 1229 * ensures that the PHY is in a known good state before 1230 * we read/write PHY registers. The generic reset is 1231 * sufficient here, because we haven't determined 1232 * the PHY type yet. 1233 */ 1234 em_phy_reset(hw); 1235 1236 /* Ungate automatic PHY configuration on non-managed 82579 */ 1237 if (hw->mac_type == em_pch2lan && 1238 (fwsm & E1000_FWSM_FW_VALID) == 0) 1239 em_gate_hw_phy_config_ich8lan(hw, FALSE); 1240 1241 /* Set MDIO slow mode before any other MDIO access */ 1242 ret_val = em_set_mdio_slow_mode_hv(hw); 1243 if (ret_val) 1244 return ret_val; 1245 } 1246 1247 /* Initialize Identification LED */ 1248 ret_val = em_id_led_init(hw); 1249 if (ret_val) { 1250 DEBUGOUT("Error Initializing Identification LED\n"); 1251 return ret_val; 1252 } 1253 /* Set the media type and TBI compatibility */ 1254 em_set_media_type(hw); 1255 1256 /* Must be called after em_set_media_type because media_type is used */ 1257 em_initialize_hardware_bits(hw); 1258 1259 /* Disabling VLAN filtering. */ 1260 DEBUGOUT("Initializing the IEEE VLAN\n"); 1261 /* VET hardcoded to standard value and VFTA removed in ICH8/ICH9 LAN */ 1262 if (!IS_ICH8(hw->mac_type)) { 1263 if (hw->mac_type < em_82545_rev_3) 1264 E1000_WRITE_REG(hw, VET, 0); 1265 if (hw->mac_type == em_i350) 1266 em_clear_vfta_i350(hw); 1267 else 1268 em_clear_vfta(hw); 1269 } 1270 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ 1271 if (hw->mac_type == em_82542_rev2_0) { 1272 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 1273 em_pci_clear_mwi(hw); 1274 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST); 1275 E1000_WRITE_FLUSH(hw); 1276 msec_delay(5); 1277 } 1278 /* 1279 * Setup the receive address. This involves initializing all of the 1280 * Receive Address Registers (RARs 0 - 15). 1281 */ 1282 em_init_rx_addrs(hw); 1283 1284 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI*/ 1285 if (hw->mac_type == em_82542_rev2_0) { 1286 E1000_WRITE_REG(hw, RCTL, 0); 1287 E1000_WRITE_FLUSH(hw); 1288 msec_delay(1); 1289 if (hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1290 em_pci_set_mwi(hw); 1291 } 1292 /* Zero out the Multicast HASH table */ 1293 DEBUGOUT("Zeroing the MTA\n"); 1294 mta_size = E1000_MC_TBL_SIZE; 1295 if (IS_ICH8(hw->mac_type)) 1296 mta_size = E1000_MC_TBL_SIZE_ICH8LAN; 1297 for (i = 0; i < mta_size; i++) { 1298 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 1299 /* 1300 * use write flush to prevent Memory Write Block (MWB) from 1301 * occuring when accessing our register space 1302 */ 1303 E1000_WRITE_FLUSH(hw); 1304 } 1305 /* 1306 * Set the PCI priority bit correctly in the CTRL register. This 1307 * determines if the adapter gives priority to receives, or if it 1308 * gives equal priority to transmits and receives. Valid only on 1309 * 82542 and 82543 silicon. 1310 */ 1311 if (hw->dma_fairness && hw->mac_type <= em_82543) { 1312 ctrl = E1000_READ_REG(hw, CTRL); 1313 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR); 1314 } 1315 switch (hw->mac_type) { 1316 case em_82545_rev_3: 1317 case em_82546_rev_3: 1318 break; 1319 default: 1320 /* 1321 * Workaround for PCI-X problem when BIOS sets MMRBC 1322 * incorrectly. 1323 */ 1324 if (hw->bus_type == em_bus_type_pcix) { 1325 em_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, 1326 &pcix_cmd_word); 1327 em_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, 1328 &pcix_stat_hi_word); 1329 cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) 1330 >> PCIX_COMMAND_MMRBC_SHIFT; 1331 stat_mmrbc = (pcix_stat_hi_word & 1332 PCIX_STATUS_HI_MMRBC_MASK) >> 1333 PCIX_STATUS_HI_MMRBC_SHIFT; 1334 1335 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) 1336 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; 1337 if (cmd_mmrbc > stat_mmrbc) { 1338 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK; 1339 pcix_cmd_word |= stat_mmrbc << 1340 PCIX_COMMAND_MMRBC_SHIFT; 1341 em_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, 1342 &pcix_cmd_word); 1343 } 1344 } 1345 break; 1346 } 1347 1348 /* More time needed for PHY to initialize */ 1349 if (IS_ICH8(hw->mac_type)) 1350 msec_delay(15); 1351 1352 /* 1353 * The 82578 Rx buffer will stall if wakeup is enabled in host and 1354 * the ME. Reading the BM_WUC register will clear the host wakeup bit. 1355 * Reset the phy after disabling host wakeup to reset the Rx buffer. 1356 */ 1357 if (hw->phy_type == em_phy_82578) { 1358 em_read_phy_reg(hw, PHY_REG(BM_WUC_PAGE, 1), 1359 (uint16_t *)®_data); 1360 ret_val = em_phy_reset(hw); 1361 if (ret_val) 1362 return ret_val; 1363 } 1364 1365 /* Call a subroutine to configure the link and setup flow control. */ 1366 ret_val = em_setup_link(hw); 1367 1368 /* Set the transmit descriptor write-back policy */ 1369 if (hw->mac_type > em_82544) { 1370 ctrl = E1000_READ_REG(hw, TXDCTL); 1371 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | 1372 E1000_TXDCTL_FULL_TX_DESC_WB; 1373 E1000_WRITE_REG(hw, TXDCTL, ctrl); 1374 } 1375 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) { 1376 em_enable_tx_pkt_filtering(hw); 1377 } 1378 switch (hw->mac_type) { 1379 default: 1380 break; 1381 case em_80003es2lan: 1382 /* Enable retransmit on late collisions */ 1383 reg_data = E1000_READ_REG(hw, TCTL); 1384 reg_data |= E1000_TCTL_RTLC; 1385 E1000_WRITE_REG(hw, TCTL, reg_data); 1386 1387 /* Configure Gigabit Carry Extend Padding */ 1388 reg_data = E1000_READ_REG(hw, TCTL_EXT); 1389 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK; 1390 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX; 1391 E1000_WRITE_REG(hw, TCTL_EXT, reg_data); 1392 1393 /* Configure Transmit Inter-Packet Gap */ 1394 reg_data = E1000_READ_REG(hw, TIPG); 1395 reg_data &= ~E1000_TIPG_IPGT_MASK; 1396 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; 1397 E1000_WRITE_REG(hw, TIPG, reg_data); 1398 1399 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001); 1400 reg_data &= ~0x00100000; 1401 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data); 1402 /* FALLTHROUGH */ 1403 case em_82571: 1404 case em_82572: 1405 case em_82575: 1406 case em_82580: 1407 case em_i210: 1408 case em_i350: 1409 case em_ich8lan: 1410 case em_ich9lan: 1411 case em_ich10lan: 1412 case em_pchlan: 1413 case em_pch2lan: 1414 case em_pch_lpt: 1415 ctrl = E1000_READ_REG(hw, TXDCTL1); 1416 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | 1417 E1000_TXDCTL_FULL_TX_DESC_WB; 1418 E1000_WRITE_REG(hw, TXDCTL1, ctrl); 1419 break; 1420 } 1421 1422 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) { 1423 uint32_t gcr = E1000_READ_REG(hw, GCR); 1424 gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; 1425 E1000_WRITE_REG(hw, GCR, gcr); 1426 } 1427 /* 1428 * Clear all of the statistics registers (clear on read). It is 1429 * important that we do this after we have tried to establish link 1430 * because the symbol error count will increment wildly if there is 1431 * no link. 1432 */ 1433 em_clear_hw_cntrs(hw); 1434 /* 1435 * ICH8 No-snoop bits are opposite polarity. Set to snoop by default 1436 * after reset. 1437 */ 1438 if (IS_ICH8(hw->mac_type)) { 1439 if (hw->mac_type == em_ich8lan) 1440 snoop = PCI_EX_82566_SNOOP_ALL; 1441 else 1442 snoop = (u_int32_t) ~ (PCI_EX_NO_SNOOP_ALL); 1443 1444 em_set_pci_ex_no_snoop(hw, snoop); 1445 } 1446 1447 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER || 1448 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) { 1449 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1450 /* 1451 * Relaxed ordering must be disabled to avoid a parity error 1452 * crash in a PCI slot. 1453 */ 1454 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 1455 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1456 } 1457 return ret_val; 1458 } 1459 1460 /****************************************************************************** 1461 * Adjust SERDES output amplitude based on EEPROM setting. 1462 * 1463 * hw - Struct containing variables accessed by shared code. 1464 *****************************************************************************/ 1465 static int32_t 1466 em_adjust_serdes_amplitude(struct em_hw *hw) 1467 { 1468 uint16_t eeprom_data; 1469 int32_t ret_val; 1470 DEBUGFUNC("em_adjust_serdes_amplitude"); 1471 1472 if (hw->media_type != em_media_type_internal_serdes || 1473 hw->mac_type >= em_82575) 1474 return E1000_SUCCESS; 1475 1476 switch (hw->mac_type) { 1477 case em_82545_rev_3: 1478 case em_82546_rev_3: 1479 break; 1480 default: 1481 return E1000_SUCCESS; 1482 } 1483 1484 ret_val = em_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data); 1485 if (ret_val) { 1486 return ret_val; 1487 } 1488 if (eeprom_data != EEPROM_RESERVED_WORD) { 1489 /* Adjust SERDES output amplitude only. */ 1490 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK; 1491 ret_val = em_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, 1492 eeprom_data); 1493 if (ret_val) 1494 return ret_val; 1495 } 1496 return E1000_SUCCESS; 1497 } 1498 1499 /****************************************************************************** 1500 * Configures flow control and link settings. 1501 * 1502 * hw - Struct containing variables accessed by shared code 1503 * 1504 * Determines which flow control settings to use. Calls the appropriate media- 1505 * specific link configuration function. Configures the flow control settings. 1506 * Assuming the adapter has a valid link partner, a valid link should be 1507 * established. Assumes the hardware has previously been reset and the 1508 * transmitter and receiver are not enabled. 1509 *****************************************************************************/ 1510 int32_t 1511 em_setup_link(struct em_hw *hw) 1512 { 1513 uint32_t ctrl_ext; 1514 int32_t ret_val; 1515 uint16_t eeprom_data; 1516 uint16_t eeprom_control2_reg_offset; 1517 DEBUGFUNC("em_setup_link"); 1518 1519 eeprom_control2_reg_offset = 1520 (hw->mac_type != em_icp_xxxx) 1521 ? EEPROM_INIT_CONTROL2_REG 1522 : EEPROM_INIT_CONTROL3_ICP_xxxx(hw->icp_xxxx_port_num); 1523 /* 1524 * In the case of the phy reset being blocked, we already have a 1525 * link. We do not have to set it up again. 1526 */ 1527 if (em_check_phy_reset_block(hw)) 1528 return E1000_SUCCESS; 1529 /* 1530 * Read and store word 0x0F of the EEPROM. This word contains bits 1531 * that determine the hardware's default PAUSE (flow control) mode, a 1532 * bit that determines whether the HW defaults to enabling or 1533 * disabling auto-negotiation, and the direction of the SW defined 1534 * pins. If there is no SW over-ride of the flow control setting, 1535 * then the variable hw->fc will be initialized based on a value in 1536 * the EEPROM. 1537 */ 1538 if (hw->fc == E1000_FC_DEFAULT) { 1539 switch (hw->mac_type) { 1540 case em_ich8lan: 1541 case em_ich9lan: 1542 case em_ich10lan: 1543 case em_pchlan: 1544 case em_pch2lan: 1545 case em_pch_lpt: 1546 case em_82573: 1547 case em_82574: 1548 hw->fc = E1000_FC_FULL; 1549 break; 1550 default: 1551 ret_val = em_read_eeprom(hw, 1552 eeprom_control2_reg_offset, 1, &eeprom_data); 1553 if (ret_val) { 1554 DEBUGOUT("EEPROM Read Error\n"); 1555 return -E1000_ERR_EEPROM; 1556 } 1557 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0) 1558 hw->fc = E1000_FC_NONE; 1559 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 1560 EEPROM_WORD0F_ASM_DIR) 1561 hw->fc = E1000_FC_TX_PAUSE; 1562 else 1563 hw->fc = E1000_FC_FULL; 1564 break; 1565 } 1566 } 1567 /* 1568 * We want to save off the original Flow Control configuration just 1569 * in case we get disconnected and then reconnected into a different 1570 * hub or switch with different Flow Control capabilities. 1571 */ 1572 if (hw->mac_type == em_82542_rev2_0) 1573 hw->fc &= (~E1000_FC_TX_PAUSE); 1574 1575 if ((hw->mac_type < em_82543) && (hw->report_tx_early == 1)) 1576 hw->fc &= (~E1000_FC_RX_PAUSE); 1577 1578 hw->original_fc = hw->fc; 1579 1580 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc); 1581 /* 1582 * Take the 4 bits from EEPROM word 0x0F that determine the initial 1583 * polarity value for the SW controlled pins, and setup the Extended 1584 * Device Control reg with that info. This is needed because one of 1585 * the SW controlled pins is used for signal detection. So this 1586 * should be done before em_setup_pcs_link() or em_phy_setup() is 1587 * called. 1588 */ 1589 if (hw->mac_type == em_82543) { 1590 ret_val = em_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1591 1, &eeprom_data); 1592 if (ret_val) { 1593 DEBUGOUT("EEPROM Read Error\n"); 1594 return -E1000_ERR_EEPROM; 1595 } 1596 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << 1597 SWDPIO__EXT_SHIFT); 1598 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1599 } 1600 /* Make sure we have a valid PHY */ 1601 ret_val = em_detect_gig_phy(hw); 1602 if (ret_val) { 1603 DEBUGOUT("Error, did not detect valid phy.\n"); 1604 if (hw->mac_type == em_icp_xxxx) 1605 return E1000_DEFER_INIT; 1606 else 1607 return ret_val; 1608 } 1609 DEBUGOUT1("Phy ID = %x \n", hw->phy_id); 1610 1611 /* Call the necessary subroutine to configure the link. */ 1612 switch (hw->media_type) { 1613 case em_media_type_copper: 1614 case em_media_type_oem: 1615 ret_val = em_setup_copper_link(hw); 1616 break; 1617 default: 1618 ret_val = em_setup_fiber_serdes_link(hw); 1619 break; 1620 } 1621 /* 1622 * Initialize the flow control address, type, and PAUSE timer 1623 * registers to their default values. This is done even if flow 1624 * control is disabled, because it does not hurt anything to 1625 * initialize these registers. 1626 */ 1627 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n" 1628 ); 1629 1630 /* 1631 * FCAL/H and FCT are hardcoded to standard values in 1632 * em_ich8lan / em_ich9lan / em_ich10lan. 1633 */ 1634 if (!IS_ICH8(hw->mac_type)) { 1635 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE); 1636 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH); 1637 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW); 1638 } 1639 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time); 1640 1641 if (hw->phy_type == em_phy_82577 || 1642 hw->phy_type == em_phy_82578 || 1643 hw->phy_type == em_phy_82579 || 1644 hw->phy_type == em_phy_i217) { 1645 E1000_WRITE_REG(hw, FCRTV_PCH, 0x1000); 1646 em_write_phy_reg(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27), 1647 hw->fc_pause_time); 1648 } 1649 1650 /* 1651 * Set the flow control receive threshold registers. Normally, these 1652 * registers will be set to a default threshold that may be adjusted 1653 * later by the driver's runtime code. However, if the ability to 1654 * transmit pause frames in not enabled, then these registers will be 1655 * set to 0. 1656 */ 1657 if (!(hw->fc & E1000_FC_TX_PAUSE)) { 1658 E1000_WRITE_REG(hw, FCRTL, 0); 1659 E1000_WRITE_REG(hw, FCRTH, 0); 1660 } else { 1661 /* 1662 * We need to set up the Receive Threshold high and low water 1663 * marks as well as (optionally) enabling the transmission of 1664 * XON frames. 1665 */ 1666 if (hw->fc_send_xon) { 1667 E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water 1668 | E1000_FCRTL_XONE)); 1669 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); 1670 } else { 1671 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water); 1672 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); 1673 } 1674 } 1675 return ret_val; 1676 } 1677 1678 void 1679 em_power_up_serdes_link_82575(struct em_hw *hw) 1680 { 1681 uint32_t reg; 1682 1683 /* Enable PCS to turn on link */ 1684 reg = E1000_READ_REG(hw, PCS_CFG0); 1685 reg |= E1000_PCS_CFG_PCS_EN; 1686 E1000_WRITE_REG(hw, PCS_CFG0, reg); 1687 1688 /* Power up the laser */ 1689 reg = E1000_READ_REG(hw, CTRL_EXT); 1690 reg &= ~E1000_CTRL_EXT_SDP3_DATA; 1691 E1000_WRITE_REG(hw, CTRL_EXT, reg); 1692 1693 /* flush the write to verify completion */ 1694 E1000_WRITE_FLUSH(hw); 1695 delay(5); 1696 } 1697 1698 /****************************************************************************** 1699 * Sets up link for a fiber based or serdes based adapter 1700 * 1701 * hw - Struct containing variables accessed by shared code 1702 * 1703 * Manipulates Physical Coding Sublayer functions in order to configure 1704 * link. Assumes the hardware has been previously reset and the transmitter 1705 * and receiver are not enabled. 1706 *****************************************************************************/ 1707 static int32_t 1708 em_setup_fiber_serdes_link(struct em_hw *hw) 1709 { 1710 uint32_t ctrl, ctrl_ext, reg; 1711 uint32_t status; 1712 uint32_t txcw = 0; 1713 uint32_t i; 1714 uint32_t signal = 0; 1715 int32_t ret_val; 1716 DEBUGFUNC("em_setup_fiber_serdes_link"); 1717 /* 1718 * On 82571 and 82572 Fiber connections, SerDes loopback mode 1719 * persists until explicitly turned off or a power cycle is 1720 * performed. A read to the register does not indicate its status. 1721 * Therefore, we ensure loopback mode is disabled during 1722 * initialization. 1723 */ 1724 if (hw->mac_type == em_82571 || hw->mac_type == em_82572 || 1725 hw->mac_type >= em_82575) 1726 E1000_WRITE_REG(hw, SCTL, E1000_DISABLE_SERDES_LOOPBACK); 1727 1728 if (hw->mac_type >= em_82575) 1729 em_power_up_serdes_link_82575(hw); 1730 1731 /* 1732 * On adapters with a MAC newer than 82544, SWDP 1 will be set when 1733 * the optics detect a signal. On older adapters, it will be cleared 1734 * when there is a signal. This applies to fiber media only. If 1735 * we're on serdes media, adjust the output amplitude to value set in 1736 * the EEPROM. 1737 */ 1738 ctrl = E1000_READ_REG(hw, CTRL); 1739 if (hw->media_type == em_media_type_fiber) 1740 signal = (hw->mac_type > em_82544) ? E1000_CTRL_SWDPIN1 : 0; 1741 1742 ret_val = em_adjust_serdes_amplitude(hw); 1743 if (ret_val) 1744 return ret_val; 1745 1746 /* Take the link out of reset */ 1747 ctrl &= ~(E1000_CTRL_LRST); 1748 1749 if (hw->mac_type >= em_82575) { 1750 /* set both sw defined pins on 82575/82576*/ 1751 ctrl |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1; 1752 1753 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1754 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) { 1755 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: 1756 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES: 1757 /* the backplane is always connected */ 1758 reg = E1000_READ_REG(hw, PCS_LCTL); 1759 reg |= E1000_PCS_LCTL_FORCE_FCTRL; 1760 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL; 1761 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */ 1762 DEBUGOUT("Configuring Forced Link\n"); 1763 E1000_WRITE_REG(hw, PCS_LCTL, reg); 1764 em_force_mac_fc(hw); 1765 hw->autoneg_failed = 0; 1766 return E1000_SUCCESS; 1767 break; 1768 default: 1769 /* Set switch control to serdes energy detect */ 1770 reg = E1000_READ_REG(hw, CONNSW); 1771 reg |= E1000_CONNSW_ENRGSRC; 1772 E1000_WRITE_REG(hw, CONNSW, reg); 1773 break; 1774 } 1775 } 1776 1777 /* Adjust VCO speed to improve BER performance */ 1778 ret_val = em_set_vco_speed(hw); 1779 if (ret_val) 1780 return ret_val; 1781 1782 em_config_collision_dist(hw); 1783 /* 1784 * Check for a software override of the flow control settings, and 1785 * setup the device accordingly. If auto-negotiation is enabled, 1786 * then software will have to set the "PAUSE" bits to the correct 1787 * value in the Tranmsit Config Word Register (TXCW) and re-start 1788 * auto-negotiation. However, if auto-negotiation is disabled, then 1789 * software will have to manually configure the two flow control 1790 * enable bits in the CTRL register. 1791 * 1792 * The possible values of the "fc" parameter are: 0: Flow control is 1793 * completely disabled 1: Rx flow control is enabled (we can receive 1794 * pause frames, but not send pause frames). 2: Tx flow control is 1795 * enabled (we can send pause frames but we do not support receiving 1796 * pause frames). 3: Both Rx and TX flow control (symmetric) are 1797 * enabled. 1798 */ 1799 switch (hw->fc) { 1800 case E1000_FC_NONE: 1801 /* 1802 * Flow control is completely disabled by a software 1803 * over-ride. 1804 */ 1805 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 1806 break; 1807 case E1000_FC_RX_PAUSE: 1808 /* 1809 * RX Flow control is enabled and TX Flow control is disabled 1810 * by a software over-ride. Since there really isn't a way to 1811 * advertise that we are capable of RX Pause ONLY, we will 1812 * advertise that we support both symmetric and asymmetric RX 1813 * PAUSE. Later, we will disable the adapter's ability to 1814 * send PAUSE frames. 1815 */ 1816 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | 1817 E1000_TXCW_PAUSE_MASK); 1818 break; 1819 case E1000_FC_TX_PAUSE: 1820 /* 1821 * TX Flow control is enabled, and RX Flow control is 1822 * disabled, by a software over-ride. 1823 */ 1824 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 1825 break; 1826 case E1000_FC_FULL: 1827 /* 1828 * Flow control (both RX and TX) is enabled by a software 1829 * over-ride. 1830 */ 1831 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | 1832 E1000_TXCW_PAUSE_MASK); 1833 break; 1834 default: 1835 DEBUGOUT("Flow control param set incorrectly\n"); 1836 return -E1000_ERR_CONFIG; 1837 break; 1838 } 1839 /* 1840 * Since auto-negotiation is enabled, take the link out of reset (the 1841 * link will be in reset, because we previously reset the chip). This 1842 * will restart auto-negotiation. If auto-neogtiation is successful 1843 * then the link-up status bit will be set and the flow control 1844 * enable bits (RFCE and TFCE) will be set according to their 1845 * negotiated value. 1846 */ 1847 DEBUGOUT("Auto-negotiation enabled\n"); 1848 1849 E1000_WRITE_REG(hw, TXCW, txcw); 1850 E1000_WRITE_REG(hw, CTRL, ctrl); 1851 E1000_WRITE_FLUSH(hw); 1852 1853 hw->txcw = txcw; 1854 msec_delay(1); 1855 /* 1856 * If we have a signal (the cable is plugged in) then poll for a 1857 * "Link-Up" indication in the Device Status Register. Time-out if a 1858 * link isn't seen in 500 milliseconds seconds (Auto-negotiation 1859 * should complete in less than 500 milliseconds even if the other 1860 * end is doing it in SW). For internal serdes, we just assume a 1861 * signal is present, then poll. 1862 */ 1863 if (hw->media_type == em_media_type_internal_serdes || 1864 (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) { 1865 DEBUGOUT("Looking for Link\n"); 1866 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) { 1867 msec_delay(10); 1868 status = E1000_READ_REG(hw, STATUS); 1869 if (status & E1000_STATUS_LU) 1870 break; 1871 } 1872 if (i == (LINK_UP_TIMEOUT / 10)) { 1873 DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 1874 hw->autoneg_failed = 1; 1875 /* 1876 * AutoNeg failed to achieve a link, so we'll call 1877 * em_check_for_link. This routine will force the 1878 * link up if we detect a signal. This will allow us 1879 * to communicate with non-autonegotiating link 1880 * partners. 1881 */ 1882 ret_val = em_check_for_link(hw); 1883 if (ret_val) { 1884 DEBUGOUT("Error while checking for link\n"); 1885 return ret_val; 1886 } 1887 hw->autoneg_failed = 0; 1888 } else { 1889 hw->autoneg_failed = 0; 1890 DEBUGOUT("Valid Link Found\n"); 1891 } 1892 } else { 1893 DEBUGOUT("No Signal Detected\n"); 1894 } 1895 return E1000_SUCCESS; 1896 } 1897 1898 /****************************************************************************** 1899 * Make sure we have a valid PHY and change PHY mode before link setup. 1900 * 1901 * hw - Struct containing variables accessed by shared code 1902 *****************************************************************************/ 1903 static int32_t 1904 em_copper_link_preconfig(struct em_hw *hw) 1905 { 1906 uint32_t ctrl; 1907 int32_t ret_val; 1908 uint16_t phy_data; 1909 DEBUGFUNC("em_copper_link_preconfig"); 1910 1911 ctrl = E1000_READ_REG(hw, CTRL); 1912 /* 1913 * With 82543, we need to force speed and duplex on the MAC equal to 1914 * what the PHY speed and duplex configuration is. In addition, we 1915 * need to perform a hardware reset on the PHY to take it out of 1916 * reset. 1917 */ 1918 if (hw->mac_type > em_82543) { 1919 ctrl |= E1000_CTRL_SLU; 1920 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1921 E1000_WRITE_REG(hw, CTRL, ctrl); 1922 } else { 1923 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | 1924 E1000_CTRL_SLU); 1925 E1000_WRITE_REG(hw, CTRL, ctrl); 1926 ret_val = em_phy_hw_reset(hw); 1927 if (ret_val) 1928 return ret_val; 1929 } 1930 1931 /* Set PHY to class A mode (if necessary) */ 1932 ret_val = em_set_phy_mode(hw); 1933 if (ret_val) 1934 return ret_val; 1935 1936 if ((hw->mac_type == em_82545_rev_3) || 1937 (hw->mac_type == em_82546_rev_3)) { 1938 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 1939 &phy_data); 1940 phy_data |= 0x00000008; 1941 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 1942 phy_data); 1943 } 1944 if (hw->mac_type <= em_82543 || 1945 hw->mac_type == em_82541 || hw->mac_type == em_82547 || 1946 hw->mac_type == em_82541_rev_2 || hw->mac_type == em_82547_rev_2) 1947 hw->phy_reset_disable = FALSE; 1948 1949 return E1000_SUCCESS; 1950 } 1951 1952 /****************************************************************************** 1953 * Copper link setup for em_phy_igp series. 1954 * 1955 * hw - Struct containing variables accessed by shared code 1956 *****************************************************************************/ 1957 static int32_t 1958 em_copper_link_igp_setup(struct em_hw *hw) 1959 { 1960 uint32_t led_ctrl; 1961 int32_t ret_val; 1962 uint16_t phy_data; 1963 DEBUGFUNC("em_copper_link_igp_setup"); 1964 1965 if (hw->phy_reset_disable) 1966 return E1000_SUCCESS; 1967 1968 ret_val = em_phy_reset(hw); 1969 if (ret_val) { 1970 DEBUGOUT("Error Resetting the PHY\n"); 1971 return ret_val; 1972 } 1973 /* Wait 15ms for MAC to configure PHY from eeprom settings */ 1974 msec_delay(15); 1975 if (hw->mac_type != em_ich8lan && 1976 hw->mac_type != em_ich9lan && 1977 hw->mac_type != em_ich10lan) { 1978 /* Configure activity LED after PHY reset */ 1979 led_ctrl = E1000_READ_REG(hw, LEDCTL); 1980 led_ctrl &= IGP_ACTIVITY_LED_MASK; 1981 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 1982 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 1983 } 1984 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */ 1985 if (hw->phy_type == em_phy_igp) { 1986 /* disable lplu d3 during driver init */ 1987 ret_val = em_set_d3_lplu_state(hw, FALSE); 1988 if (ret_val) { 1989 DEBUGOUT("Error Disabling LPLU D3\n"); 1990 return ret_val; 1991 } 1992 } 1993 /* disable lplu d0 during driver init */ 1994 if (hw->mac_type == em_pchlan || 1995 hw->mac_type == em_pch2lan || 1996 hw->mac_type == em_pch_lpt) 1997 ret_val = em_set_lplu_state_pchlan(hw, FALSE); 1998 else 1999 ret_val = em_set_d0_lplu_state(hw, FALSE); 2000 if (ret_val) { 2001 DEBUGOUT("Error Disabling LPLU D0\n"); 2002 return ret_val; 2003 } 2004 /* Configure mdi-mdix settings */ 2005 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 2006 if (ret_val) 2007 return ret_val; 2008 2009 if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) { 2010 hw->dsp_config_state = em_dsp_config_disabled; 2011 /* Force MDI for earlier revs of the IGP PHY */ 2012 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | 2013 IGP01E1000_PSCR_FORCE_MDI_MDIX); 2014 hw->mdix = 1; 2015 2016 } else { 2017 hw->dsp_config_state = em_dsp_config_enabled; 2018 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 2019 2020 switch (hw->mdix) { 2021 case 1: 2022 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 2023 break; 2024 case 2: 2025 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; 2026 break; 2027 case 0: 2028 default: 2029 phy_data |= IGP01E1000_PSCR_AUTO_MDIX; 2030 break; 2031 } 2032 } 2033 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 2034 if (ret_val) 2035 return ret_val; 2036 2037 /* set auto-master slave resolution settings */ 2038 if (hw->autoneg) { 2039 em_ms_type phy_ms_setting = hw->master_slave; 2040 if (hw->ffe_config_state == em_ffe_config_active) 2041 hw->ffe_config_state = em_ffe_config_enabled; 2042 2043 if (hw->dsp_config_state == em_dsp_config_activated) 2044 hw->dsp_config_state = em_dsp_config_enabled; 2045 /* 2046 * when autonegotiation advertisement is only 1000Mbps then 2047 * we should disable SmartSpeed and enable Auto MasterSlave 2048 * resolution as hardware default. 2049 */ 2050 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) { 2051 /* Disable SmartSpeed */ 2052 ret_val = em_read_phy_reg(hw, 2053 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2054 if (ret_val) 2055 return ret_val; 2056 2057 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2058 ret_val = em_write_phy_reg(hw, 2059 IGP01E1000_PHY_PORT_CONFIG, phy_data); 2060 if (ret_val) 2061 return ret_val; 2062 /* Set auto Master/Slave resolution process */ 2063 ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, 2064 &phy_data); 2065 if (ret_val) 2066 return ret_val; 2067 2068 phy_data &= ~CR_1000T_MS_ENABLE; 2069 ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL, 2070 phy_data); 2071 if (ret_val) 2072 return ret_val; 2073 } 2074 ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); 2075 if (ret_val) 2076 return ret_val; 2077 2078 /* load defaults for future use */ 2079 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ? 2080 ((phy_data & CR_1000T_MS_VALUE) ? em_ms_force_master : 2081 em_ms_force_slave) : em_ms_auto; 2082 2083 switch (phy_ms_setting) { 2084 case em_ms_force_master: 2085 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 2086 break; 2087 case em_ms_force_slave: 2088 phy_data |= CR_1000T_MS_ENABLE; 2089 phy_data &= ~(CR_1000T_MS_VALUE); 2090 break; 2091 case em_ms_auto: 2092 phy_data &= ~CR_1000T_MS_ENABLE; 2093 break; 2094 default: 2095 break; 2096 } 2097 ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); 2098 if (ret_val) 2099 return ret_val; 2100 } 2101 return E1000_SUCCESS; 2102 } 2103 2104 /****************************************************************************** 2105 * Copper link setup for em_phy_gg82563 series. 2106 * 2107 * hw - Struct containing variables accessed by shared code 2108 *****************************************************************************/ 2109 static int32_t 2110 em_copper_link_ggp_setup(struct em_hw *hw) 2111 { 2112 int32_t ret_val; 2113 uint16_t phy_data; 2114 uint32_t reg_data; 2115 DEBUGFUNC("em_copper_link_ggp_setup"); 2116 2117 if (!hw->phy_reset_disable) { 2118 2119 /* Enable CRS on TX for half-duplex operation. */ 2120 ret_val = em_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 2121 &phy_data); 2122 if (ret_val) 2123 return ret_val; 2124 2125 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 2126 /* Use 25MHz for both link down and 1000BASE-T for Tx clock */ 2127 phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ; 2128 2129 ret_val = em_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 2130 phy_data); 2131 if (ret_val) 2132 return ret_val; 2133 /* 2134 * Options: MDI/MDI-X = 0 (default) 0 - Auto for all speeds 1 2135 * - MDI mode 2 - MDI-X mode 3 - Auto for 1000Base-T only 2136 * (MDI-X for 10/100Base-T modes) 2137 */ 2138 ret_val = em_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, 2139 &phy_data); 2140 2141 if (ret_val) 2142 return ret_val; 2143 2144 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK; 2145 2146 switch (hw->mdix) { 2147 case 1: 2148 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI; 2149 break; 2150 case 2: 2151 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX; 2152 break; 2153 case 0: 2154 default: 2155 phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO; 2156 break; 2157 } 2158 /* 2159 * Options: disable_polarity_correction = 0 (default) 2160 * Automatic Correction for Reversed Cable Polarity 0 - 2161 * Disabled 1 - Enabled 2162 */ 2163 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 2164 if (hw->disable_polarity_correction == 1) 2165 phy_data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 2166 ret_val = em_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, 2167 phy_data); 2168 2169 if (ret_val) 2170 return ret_val; 2171 2172 /* SW Reset the PHY so all changes take effect */ 2173 ret_val = em_phy_reset(hw); 2174 if (ret_val) { 2175 DEBUGOUT("Error Resetting the PHY\n"); 2176 return ret_val; 2177 } 2178 } /* phy_reset_disable */ 2179 if (hw->mac_type == em_80003es2lan) { 2180 /* Bypass RX and TX FIFO's */ 2181 ret_val = em_write_kmrn_reg(hw, 2182 E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL, 2183 E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS | 2184 E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS); 2185 if (ret_val) 2186 return ret_val; 2187 2188 ret_val = em_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, 2189 &phy_data); 2190 if (ret_val) 2191 return ret_val; 2192 2193 phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG; 2194 ret_val = em_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, 2195 phy_data); 2196 2197 if (ret_val) 2198 return ret_val; 2199 2200 reg_data = E1000_READ_REG(hw, CTRL_EXT); 2201 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK); 2202 E1000_WRITE_REG(hw, CTRL_EXT, reg_data); 2203 2204 ret_val = em_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, 2205 &phy_data); 2206 if (ret_val) 2207 return ret_val; 2208 /* 2209 * Do not init these registers when the HW is in IAMT mode, 2210 * since the firmware will have already initialized them. We 2211 * only initialize them if the HW is not in IAMT mode. 2212 */ 2213 if (em_check_mng_mode(hw) == FALSE) { 2214 /* Enable Electrical Idle on the PHY */ 2215 phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; 2216 ret_val = em_write_phy_reg(hw, 2217 GG82563_PHY_PWR_MGMT_CTRL, phy_data); 2218 if (ret_val) 2219 return ret_val; 2220 2221 ret_val = em_read_phy_reg(hw, 2222 GG82563_PHY_KMRN_MODE_CTRL, &phy_data); 2223 if (ret_val) 2224 return ret_val; 2225 2226 phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 2227 ret_val = em_write_phy_reg(hw, 2228 GG82563_PHY_KMRN_MODE_CTRL, phy_data); 2229 2230 if (ret_val) 2231 return ret_val; 2232 } 2233 /* 2234 * Workaround: Disable padding in Kumeran interface in the 2235 * MAC and in the PHY to avoid CRC errors. 2236 */ 2237 ret_val = em_read_phy_reg(hw, GG82563_PHY_INBAND_CTRL, 2238 &phy_data); 2239 if (ret_val) 2240 return ret_val; 2241 phy_data |= GG82563_ICR_DIS_PADDING; 2242 ret_val = em_write_phy_reg(hw, GG82563_PHY_INBAND_CTRL, 2243 phy_data); 2244 if (ret_val) 2245 return ret_val; 2246 } 2247 return E1000_SUCCESS; 2248 } 2249 2250 /****************************************************************************** 2251 * Copper link setup for em_phy_m88 series. 2252 * 2253 * hw - Struct containing variables accessed by shared code 2254 *****************************************************************************/ 2255 static int32_t 2256 em_copper_link_mgp_setup(struct em_hw *hw) 2257 { 2258 int32_t ret_val; 2259 uint16_t phy_data; 2260 DEBUGFUNC("em_copper_link_mgp_setup"); 2261 2262 if (hw->phy_reset_disable) 2263 return E1000_SUCCESS; 2264 2265 /* disable lplu d0 during driver init */ 2266 if (hw->mac_type == em_pchlan || 2267 hw->mac_type == em_pch2lan || 2268 hw->mac_type == em_pch_lpt) 2269 ret_val = em_set_lplu_state_pchlan(hw, FALSE); 2270 2271 /* Enable CRS on TX. This must be set for half-duplex operation. */ 2272 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 2273 if (ret_val) 2274 return ret_val; 2275 2276 if (hw->phy_id == M88E1141_E_PHY_ID) { 2277 phy_data |= 0x00000008; 2278 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 2279 phy_data); 2280 if (ret_val) 2281 return ret_val; 2282 2283 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 2284 &phy_data); 2285 if (ret_val) 2286 return ret_val; 2287 2288 phy_data &= ~M88E1000_PSCR_ASSERT_CRS_ON_TX; 2289 2290 } 2291 /* For BM PHY this bit is downshift enable */ 2292 else if (hw->phy_type != em_phy_bm) 2293 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 2294 /* 2295 * Options: MDI/MDI-X = 0 (default) 0 - Auto for all speeds 1 - MDI 2296 * mode 2 - MDI-X mode 3 - Auto for 1000Base-T only (MDI-X for 2297 * 10/100Base-T modes) 2298 */ 2299 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 2300 2301 switch (hw->mdix) { 2302 case 1: 2303 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 2304 break; 2305 case 2: 2306 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 2307 break; 2308 case 3: 2309 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 2310 break; 2311 case 0: 2312 default: 2313 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 2314 break; 2315 } 2316 /* 2317 * Options: disable_polarity_correction = 0 (default) Automatic 2318 * Correction for Reversed Cable Polarity 0 - Disabled 1 - Enabled 2319 */ 2320 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 2321 if (hw->disable_polarity_correction == 1) 2322 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 2323 2324 /* Enable downshift on BM (disabled by default) */ 2325 if (hw->phy_type == em_phy_bm) 2326 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT; 2327 2328 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 2329 if (ret_val) 2330 return ret_val; 2331 2332 if (((hw->phy_type == em_phy_m88) && 2333 (hw->phy_revision < M88E1011_I_REV_4) && 2334 (hw->phy_id != BME1000_E_PHY_ID)) || 2335 (hw->phy_type == em_phy_oem)) { 2336 /* 2337 * Force TX_CLK in the Extended PHY Specific Control Register 2338 * to 25MHz clock. 2339 */ 2340 ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 2341 &phy_data); 2342 if (ret_val) 2343 return ret_val; 2344 2345 if (hw->phy_type == em_phy_oem) { 2346 phy_data |= M88E1000_EPSCR_TX_TIME_CTRL; 2347 phy_data |= M88E1000_EPSCR_RX_TIME_CTRL; 2348 } 2349 phy_data |= M88E1000_EPSCR_TX_CLK_25; 2350 2351 if ((hw->phy_revision == E1000_REVISION_2) && 2352 (hw->phy_id == M88E1111_I_PHY_ID)) { 2353 /* Vidalia Phy, set the downshift counter to 5x */ 2354 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK); 2355 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; 2356 ret_val = em_write_phy_reg(hw, 2357 M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 2358 if (ret_val) 2359 return ret_val; 2360 } else { 2361 /* Configure Master and Slave downshift values */ 2362 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 2363 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 2364 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 2365 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 2366 ret_val = em_write_phy_reg(hw, 2367 M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 2368 if (ret_val) 2369 return ret_val; 2370 } 2371 } 2372 if ((hw->phy_type == em_phy_bm) && (hw->phy_revision == 1)) { 2373 /* 2374 * Set PHY page 0, register 29 to 0x0003 2375 * The next two writes are supposed to lower BER for gig 2376 * conection 2377 */ 2378 ret_val = em_write_phy_reg(hw, BM_REG_BIAS1, 0x0003); 2379 if (ret_val) 2380 return ret_val; 2381 2382 /* Set PHY page 0, register 30 to 0x0000 */ 2383 ret_val = em_write_phy_reg(hw, BM_REG_BIAS2, 0x0000); 2384 if (ret_val) 2385 return ret_val; 2386 } 2387 if (hw->phy_type == em_phy_82578) { 2388 ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 2389 &phy_data); 2390 if (ret_val) 2391 return ret_val; 2392 2393 /* 82578 PHY - set the downshift count to 1x. */ 2394 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE; 2395 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK; 2396 ret_val = em_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 2397 phy_data); 2398 if (ret_val) 2399 return ret_val; 2400 } 2401 /* SW Reset the PHY so all changes take effect */ 2402 ret_val = em_phy_reset(hw); 2403 if (ret_val) { 2404 DEBUGOUT("Error Resetting the PHY\n"); 2405 return ret_val; 2406 } 2407 return E1000_SUCCESS; 2408 } 2409 2410 /****************************************************************************** 2411 * Copper link setup for em_phy_82577 series. 2412 * 2413 * hw - Struct containing variables accessed by shared code 2414 *****************************************************************************/ 2415 static int32_t 2416 em_copper_link_82577_setup(struct em_hw *hw) 2417 { 2418 int32_t ret_val; 2419 uint16_t phy_data; 2420 uint32_t led_ctl; 2421 DEBUGFUNC("em_copper_link_82577_setup"); 2422 2423 if (hw->phy_reset_disable) 2424 return E1000_SUCCESS; 2425 2426 /* Enable CRS on TX for half-duplex operation. */ 2427 ret_val = em_read_phy_reg(hw, I82577_PHY_CFG_REG, &phy_data); 2428 if (ret_val) 2429 return ret_val; 2430 2431 phy_data |= I82577_PHY_CFG_ENABLE_CRS_ON_TX | 2432 I82577_PHY_CFG_ENABLE_DOWNSHIFT; 2433 2434 ret_val = em_write_phy_reg(hw, I82577_PHY_CFG_REG, phy_data); 2435 if (ret_val) 2436 return ret_val; 2437 2438 /* Wait 15ms for MAC to configure PHY from eeprom settings */ 2439 msec_delay(15); 2440 led_ctl = hw->ledctl_mode1; 2441 2442 /* disable lplu d0 during driver init */ 2443 ret_val = em_set_lplu_state_pchlan(hw, FALSE); 2444 if (ret_val) { 2445 DEBUGOUT("Error Disabling LPLU D0\n"); 2446 return ret_val; 2447 } 2448 2449 E1000_WRITE_REG(hw, LEDCTL, led_ctl); 2450 2451 return E1000_SUCCESS; 2452 } 2453 2454 static int32_t 2455 em_copper_link_82580_setup(struct em_hw *hw) 2456 { 2457 int32_t ret_val; 2458 uint16_t phy_data; 2459 2460 if (hw->phy_reset_disable) 2461 return E1000_SUCCESS; 2462 2463 ret_val = em_phy_reset(hw); 2464 if (ret_val) 2465 goto out; 2466 2467 /* Enable CRS on TX. This must be set for half-duplex operation. */ 2468 ret_val = em_read_phy_reg(hw, I82580_CFG_REG, &phy_data); 2469 if (ret_val) 2470 goto out; 2471 2472 phy_data |= I82580_CFG_ASSERT_CRS_ON_TX | 2473 I82580_CFG_ENABLE_DOWNSHIFT; 2474 2475 ret_val = em_write_phy_reg(hw, I82580_CFG_REG, phy_data); 2476 2477 out: 2478 return ret_val; 2479 } 2480 2481 /****************************************************************************** 2482 * Setup auto-negotiation and flow control advertisements, 2483 * and then perform auto-negotiation. 2484 * 2485 * hw - Struct containing variables accessed by shared code 2486 *****************************************************************************/ 2487 int32_t 2488 em_copper_link_autoneg(struct em_hw *hw) 2489 { 2490 int32_t ret_val; 2491 uint16_t phy_data; 2492 DEBUGFUNC("em_copper_link_autoneg"); 2493 /* 2494 * Perform some bounds checking on the hw->autoneg_advertised 2495 * parameter. If this variable is zero, then set it to the default. 2496 */ 2497 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT; 2498 /* 2499 * If autoneg_advertised is zero, we assume it was not defaulted by 2500 * the calling code so we set to advertise full capability. 2501 */ 2502 if (hw->autoneg_advertised == 0) 2503 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 2504 2505 /* IFE phy only supports 10/100 */ 2506 if (hw->phy_type == em_phy_ife) 2507 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL; 2508 2509 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); 2510 ret_val = em_phy_setup_autoneg(hw); 2511 if (ret_val) { 2512 DEBUGOUT("Error Setting up Auto-Negotiation\n"); 2513 return ret_val; 2514 } 2515 DEBUGOUT("Restarting Auto-Neg\n"); 2516 /* 2517 * Restart auto-negotiation by setting the Auto Neg Enable bit and 2518 * the Auto Neg Restart bit in the PHY control register. 2519 */ 2520 ret_val = em_read_phy_reg(hw, PHY_CTRL, &phy_data); 2521 if (ret_val) 2522 return ret_val; 2523 2524 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 2525 ret_val = em_write_phy_reg(hw, PHY_CTRL, phy_data); 2526 if (ret_val) 2527 return ret_val; 2528 /* 2529 * Does the user want to wait for Auto-Neg to complete here, or check 2530 * at a later time (for example, callback routine). 2531 */ 2532 if (hw->wait_autoneg_complete) { 2533 ret_val = em_wait_autoneg(hw); 2534 if (ret_val) { 2535 DEBUGOUT("Error while waiting for autoneg to complete\n" 2536 ); 2537 return ret_val; 2538 } 2539 } 2540 hw->get_link_status = TRUE; 2541 2542 return E1000_SUCCESS; 2543 } 2544 2545 /****************************************************************************** 2546 * Config the MAC and the PHY after link is up. 2547 * 1) Set up the MAC to the current PHY speed/duplex 2548 * if we are on 82543. If we 2549 * are on newer silicon, we only need to configure 2550 * collision distance in the Transmit Control Register. 2551 * 2) Set up flow control on the MAC to that established with 2552 * the link partner. 2553 * 3) Config DSP to improve Gigabit link quality for some PHY revisions. 2554 * 2555 * hw - Struct containing variables accessed by shared code 2556 *****************************************************************************/ 2557 int32_t 2558 em_copper_link_postconfig(struct em_hw *hw) 2559 { 2560 int32_t ret_val; 2561 DEBUGFUNC("em_copper_link_postconfig"); 2562 2563 if (hw->mac_type >= em_82544 && 2564 hw->mac_type != em_icp_xxxx) { 2565 em_config_collision_dist(hw); 2566 } else { 2567 ret_val = em_config_mac_to_phy(hw); 2568 if (ret_val) { 2569 DEBUGOUT("Error configuring MAC to PHY settings\n"); 2570 return ret_val; 2571 } 2572 } 2573 ret_val = em_config_fc_after_link_up(hw); 2574 if (ret_val) { 2575 DEBUGOUT("Error Configuring Flow Control\n"); 2576 return ret_val; 2577 } 2578 /* Config DSP to improve Giga link quality */ 2579 if (hw->phy_type == em_phy_igp) { 2580 ret_val = em_config_dsp_after_link_change(hw, TRUE); 2581 if (ret_val) { 2582 DEBUGOUT("Error Configuring DSP after link up\n"); 2583 return ret_val; 2584 } 2585 } 2586 return E1000_SUCCESS; 2587 } 2588 2589 /****************************************************************************** 2590 * Detects which PHY is present and setup the speed and duplex 2591 * 2592 * hw - Struct containing variables accessed by shared code 2593 *****************************************************************************/ 2594 static int32_t 2595 em_setup_copper_link(struct em_hw *hw) 2596 { 2597 int32_t ret_val; 2598 uint16_t i; 2599 uint16_t phy_data; 2600 uint16_t reg_data; 2601 DEBUGFUNC("em_setup_copper_link"); 2602 2603 switch (hw->mac_type) { 2604 case em_80003es2lan: 2605 case em_ich8lan: 2606 case em_ich9lan: 2607 case em_ich10lan: 2608 case em_pchlan: 2609 case em_pch2lan: 2610 case em_pch_lpt: 2611 /* 2612 * Set the mac to wait the maximum time between each 2613 * iteration and increase the max iterations when polling the 2614 * phy; this fixes erroneous timeouts at 10Mbps. 2615 */ 2616 ret_val = em_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF); 2617 if (ret_val) 2618 return ret_val; 2619 ret_val = em_read_kmrn_reg(hw, GG82563_REG(0x34, 9), 2620 ®_data); 2621 if (ret_val) 2622 return ret_val; 2623 reg_data |= 0x3F; 2624 ret_val = em_write_kmrn_reg(hw, GG82563_REG(0x34, 9), 2625 reg_data); 2626 if (ret_val) 2627 return ret_val; 2628 default: 2629 break; 2630 } 2631 2632 /* Check if it is a valid PHY and set PHY mode if necessary. */ 2633 ret_val = em_copper_link_preconfig(hw); 2634 if (ret_val) 2635 return ret_val; 2636 2637 switch (hw->mac_type) { 2638 case em_80003es2lan: 2639 /* Kumeran registers are written-only */ 2640 reg_data = 2641 E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT; 2642 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING; 2643 ret_val = em_write_kmrn_reg(hw, 2644 E1000_KUMCTRLSTA_OFFSET_INB_CTRL, reg_data); 2645 if (ret_val) 2646 return ret_val; 2647 break; 2648 default: 2649 break; 2650 } 2651 2652 if (hw->phy_type == em_phy_igp || 2653 hw->phy_type == em_phy_igp_3 || 2654 hw->phy_type == em_phy_igp_2) { 2655 ret_val = em_copper_link_igp_setup(hw); 2656 if (ret_val) 2657 return ret_val; 2658 } else if (hw->phy_type == em_phy_m88 || 2659 hw->phy_type == em_phy_bm || 2660 hw->phy_type == em_phy_oem || 2661 hw->phy_type == em_phy_82578) { 2662 ret_val = em_copper_link_mgp_setup(hw); 2663 if (ret_val) 2664 return ret_val; 2665 } else if (hw->phy_type == em_phy_gg82563) { 2666 ret_val = em_copper_link_ggp_setup(hw); 2667 if (ret_val) 2668 return ret_val; 2669 } else if (hw->phy_type == em_phy_82577 || 2670 hw->phy_type == em_phy_82579 || 2671 hw->phy_type == em_phy_i217) { 2672 ret_val = em_copper_link_82577_setup(hw); 2673 if (ret_val) 2674 return ret_val; 2675 } else if (hw->phy_type == em_phy_82580) { 2676 ret_val = em_copper_link_82580_setup(hw); 2677 if (ret_val) 2678 return ret_val; 2679 } 2680 if (hw->autoneg) { 2681 /* 2682 * Setup autoneg and flow control advertisement and perform 2683 * autonegotiation 2684 */ 2685 ret_val = em_copper_link_autoneg(hw); 2686 if (ret_val) 2687 return ret_val; 2688 } else { 2689 /* 2690 * PHY will be set to 10H, 10F, 100H,or 100F depending on 2691 * value from forced_speed_duplex. 2692 */ 2693 DEBUGOUT("Forcing speed and duplex\n"); 2694 ret_val = em_phy_force_speed_duplex(hw); 2695 if (ret_val) { 2696 DEBUGOUT("Error Forcing Speed and Duplex\n"); 2697 return ret_val; 2698 } 2699 } 2700 /* 2701 * Check link status. Wait up to 100 microseconds for link to become 2702 * valid. 2703 */ 2704 for (i = 0; i < 10; i++) { 2705 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 2706 if (ret_val) 2707 return ret_val; 2708 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 2709 if (ret_val) 2710 return ret_val; 2711 2712 hw->icp_xxxx_is_link_up = (phy_data & MII_SR_LINK_STATUS) != 0; 2713 2714 if (phy_data & MII_SR_LINK_STATUS) { 2715 /* Config the MAC and PHY after link is up */ 2716 ret_val = em_copper_link_postconfig(hw); 2717 if (ret_val) 2718 return ret_val; 2719 2720 DEBUGOUT("Valid link established!!!\n"); 2721 return E1000_SUCCESS; 2722 } 2723 usec_delay(10); 2724 } 2725 2726 DEBUGOUT("Unable to establish link!!!\n"); 2727 return E1000_SUCCESS; 2728 } 2729 2730 /****************************************************************************** 2731 * Configure the MAC-to-PHY interface for 10/100Mbps 2732 * 2733 * hw - Struct containing variables accessed by shared code 2734 *****************************************************************************/ 2735 static int32_t 2736 em_configure_kmrn_for_10_100(struct em_hw *hw, uint16_t duplex) 2737 { 2738 int32_t ret_val = E1000_SUCCESS; 2739 uint32_t tipg; 2740 uint16_t reg_data; 2741 DEBUGFUNC("em_configure_kmrn_for_10_100"); 2742 2743 reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT; 2744 ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL, 2745 reg_data); 2746 if (ret_val) 2747 return ret_val; 2748 2749 /* Configure Transmit Inter-Packet Gap */ 2750 tipg = E1000_READ_REG(hw, TIPG); 2751 tipg &= ~E1000_TIPG_IPGT_MASK; 2752 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100; 2753 E1000_WRITE_REG(hw, TIPG, tipg); 2754 2755 ret_val = em_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); 2756 2757 if (ret_val) 2758 return ret_val; 2759 2760 if (duplex == HALF_DUPLEX) 2761 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER; 2762 else 2763 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 2764 2765 ret_val = em_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 2766 2767 return ret_val; 2768 } 2769 2770 static int32_t 2771 em_configure_kmrn_for_1000(struct em_hw *hw) 2772 { 2773 int32_t ret_val = E1000_SUCCESS; 2774 uint16_t reg_data; 2775 uint32_t tipg; 2776 DEBUGFUNC("em_configure_kmrn_for_1000"); 2777 2778 reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT; 2779 ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL, 2780 reg_data); 2781 if (ret_val) 2782 return ret_val; 2783 2784 /* Configure Transmit Inter-Packet Gap */ 2785 tipg = E1000_READ_REG(hw, TIPG); 2786 tipg &= ~E1000_TIPG_IPGT_MASK; 2787 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; 2788 E1000_WRITE_REG(hw, TIPG, tipg); 2789 2790 ret_val = em_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); 2791 2792 if (ret_val) 2793 return ret_val; 2794 2795 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 2796 ret_val = em_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 2797 2798 return ret_val; 2799 } 2800 2801 /****************************************************************************** 2802 * Configures PHY autoneg and flow control advertisement settings 2803 * 2804 * hw - Struct containing variables accessed by shared code 2805 *****************************************************************************/ 2806 int32_t 2807 em_phy_setup_autoneg(struct em_hw *hw) 2808 { 2809 int32_t ret_val; 2810 uint16_t mii_autoneg_adv_reg; 2811 uint16_t mii_1000t_ctrl_reg; 2812 DEBUGFUNC("em_phy_setup_autoneg"); 2813 2814 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 2815 ret_val = em_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 2816 if (ret_val) 2817 return ret_val; 2818 2819 if (hw->phy_type != em_phy_ife) { 2820 /* Read the MII 1000Base-T Control Register (Address 9). */ 2821 ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, 2822 &mii_1000t_ctrl_reg); 2823 if (ret_val) 2824 return ret_val; 2825 } else 2826 mii_1000t_ctrl_reg = 0; 2827 /* 2828 * Need to parse both autoneg_advertised and fc and set up the 2829 * appropriate PHY registers. First we will parse for 2830 * autoneg_advertised software override. Since we can advertise a 2831 * plethora of combinations, we need to check each bit individually. 2832 */ 2833 /* 2834 * First we clear all the 10/100 mb speed bits in the Auto-Neg 2835 * Advertisement Register (Address 4) and the 1000 mb speed bits in 2836 * the 1000Base-T Control Register (Address 9). 2837 */ 2838 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK; 2839 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK; 2840 2841 DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised); 2842 2843 /* Do we want to advertise 10 Mb Half Duplex? */ 2844 if (hw->autoneg_advertised & ADVERTISE_10_HALF) { 2845 DEBUGOUT("Advertise 10mb Half duplex\n"); 2846 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 2847 } 2848 /* Do we want to advertise 10 Mb Full Duplex? */ 2849 if (hw->autoneg_advertised & ADVERTISE_10_FULL) { 2850 DEBUGOUT("Advertise 10mb Full duplex\n"); 2851 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 2852 } 2853 /* Do we want to advertise 100 Mb Half Duplex? */ 2854 if (hw->autoneg_advertised & ADVERTISE_100_HALF) { 2855 DEBUGOUT("Advertise 100mb Half duplex\n"); 2856 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 2857 } 2858 /* Do we want to advertise 100 Mb Full Duplex? */ 2859 if (hw->autoneg_advertised & ADVERTISE_100_FULL) { 2860 DEBUGOUT("Advertise 100mb Full duplex\n"); 2861 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 2862 } 2863 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 2864 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) { 2865 DEBUGOUT("Advertise 1000mb Half duplex requested, request" 2866 " denied!\n"); 2867 } 2868 /* Do we want to advertise 1000 Mb Full Duplex? */ 2869 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) { 2870 DEBUGOUT("Advertise 1000mb Full duplex\n"); 2871 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 2872 if (hw->phy_type == em_phy_ife) { 2873 DEBUGOUT("em_phy_ife is a 10/100 PHY. Gigabit speed is" 2874 " not supported.\n"); 2875 } 2876 } 2877 /* 2878 * Check for a software override of the flow control settings, and 2879 * setup the PHY advertisement registers accordingly. If 2880 * auto-negotiation is enabled, then software will have to set the 2881 * "PAUSE" bits to the correct value in the Auto-Negotiation 2882 * Advertisement Register (PHY_AUTONEG_ADV) and re-start 2883 * auto-negotiation. 2884 * 2885 * The possible values of the "fc" parameter are: 0: Flow control is 2886 * completely disabled 1: Rx flow control is enabled (we can receive 2887 * pause frames but not send pause frames). 2: Tx flow control is 2888 * enabled (we can send pause frames but we do not support receiving 2889 * pause frames). 3: Both Rx and TX flow control (symmetric) are 2890 * enabled. other: No software override. The flow control 2891 * configuration in the EEPROM is used. 2892 */ 2893 switch (hw->fc) { 2894 case E1000_FC_NONE: /* 0 */ 2895 /* 2896 * Flow control (RX & TX) is completely disabled by a 2897 * software over-ride. 2898 */ 2899 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 2900 break; 2901 case E1000_FC_RX_PAUSE:/* 1 */ 2902 /* 2903 * RX Flow control is enabled, and TX Flow control is 2904 * disabled, by a software over-ride. 2905 */ 2906 /* 2907 * Since there really isn't a way to advertise that we are 2908 * capable of RX Pause ONLY, we will advertise that we 2909 * support both symmetric and asymmetric RX PAUSE. Later (in 2910 * em_config_fc_after_link_up) we will disable the hw's 2911 * ability to send PAUSE frames. 2912 */ 2913 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 2914 break; 2915 case E1000_FC_TX_PAUSE:/* 2 */ 2916 /* 2917 * TX Flow control is enabled, and RX Flow control is 2918 * disabled, by a software over-ride. 2919 */ 2920 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 2921 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 2922 break; 2923 case E1000_FC_FULL: /* 3 */ 2924 /* 2925 * Flow control (both RX and TX) is enabled by a software 2926 * over-ride. 2927 */ 2928 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 2929 break; 2930 default: 2931 DEBUGOUT("Flow control param set incorrectly\n"); 2932 return -E1000_ERR_CONFIG; 2933 } 2934 2935 ret_val = em_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 2936 if (ret_val) 2937 return ret_val; 2938 2939 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 2940 2941 if (hw->phy_type != em_phy_ife) { 2942 ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL, 2943 mii_1000t_ctrl_reg); 2944 if (ret_val) 2945 return ret_val; 2946 } 2947 return E1000_SUCCESS; 2948 } 2949 /****************************************************************************** 2950 * Force PHY speed and duplex settings to hw->forced_speed_duplex 2951 * 2952 * hw - Struct containing variables accessed by shared code 2953 *****************************************************************************/ 2954 static int32_t 2955 em_phy_force_speed_duplex(struct em_hw *hw) 2956 { 2957 uint32_t ctrl; 2958 int32_t ret_val; 2959 uint16_t mii_ctrl_reg; 2960 uint16_t mii_status_reg; 2961 uint16_t phy_data; 2962 uint16_t i; 2963 DEBUGFUNC("em_phy_force_speed_duplex"); 2964 2965 /* Turn off Flow control if we are forcing speed and duplex. */ 2966 hw->fc = E1000_FC_NONE; 2967 2968 DEBUGOUT1("hw->fc = %d\n", hw->fc); 2969 2970 /* Read the Device Control Register. */ 2971 ctrl = E1000_READ_REG(hw, CTRL); 2972 2973 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */ 2974 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 2975 ctrl &= ~(DEVICE_SPEED_MASK); 2976 2977 /* Clear the Auto Speed Detect Enable bit. */ 2978 ctrl &= ~E1000_CTRL_ASDE; 2979 2980 /* Read the MII Control Register. */ 2981 ret_val = em_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg); 2982 if (ret_val) 2983 return ret_val; 2984 2985 /* We need to disable autoneg in order to force link and duplex. */ 2986 2987 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN; 2988 2989 /* Are we forcing Full or Half Duplex? */ 2990 if (hw->forced_speed_duplex == em_100_full || 2991 hw->forced_speed_duplex == em_10_full) { 2992 /* 2993 * We want to force full duplex so we SET the full duplex 2994 * bits in the Device and MII Control Registers. 2995 */ 2996 ctrl |= E1000_CTRL_FD; 2997 mii_ctrl_reg |= MII_CR_FULL_DUPLEX; 2998 DEBUGOUT("Full Duplex\n"); 2999 } else { 3000 /* 3001 * We want to force half duplex so we CLEAR the full duplex 3002 * bits in the Device and MII Control Registers. 3003 */ 3004 ctrl &= ~E1000_CTRL_FD; 3005 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX; 3006 DEBUGOUT("Half Duplex\n"); 3007 } 3008 3009 /* Are we forcing 100Mbps??? */ 3010 if (hw->forced_speed_duplex == em_100_full || 3011 hw->forced_speed_duplex == em_100_half) { 3012 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */ 3013 ctrl |= E1000_CTRL_SPD_100; 3014 mii_ctrl_reg |= MII_CR_SPEED_100; 3015 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); 3016 DEBUGOUT("Forcing 100mb "); 3017 } else { 3018 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */ 3019 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 3020 mii_ctrl_reg |= MII_CR_SPEED_10; 3021 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); 3022 DEBUGOUT("Forcing 10mb "); 3023 } 3024 3025 em_config_collision_dist(hw); 3026 3027 /* Write the configured values back to the Device Control Reg. */ 3028 E1000_WRITE_REG(hw, CTRL, ctrl); 3029 3030 if ((hw->phy_type == em_phy_m88) || 3031 (hw->phy_type == em_phy_gg82563) || 3032 (hw->phy_type == em_phy_bm) || 3033 (hw->phy_type == em_phy_oem || 3034 (hw->phy_type == em_phy_82578))) { 3035 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 3036 &phy_data); 3037 if (ret_val) 3038 return ret_val; 3039 /* 3040 * Clear Auto-Crossover to force MDI manually. M88E1000 3041 * requires MDI forced whenever speed are duplex are forced. 3042 */ 3043 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 3044 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 3045 phy_data); 3046 if (ret_val) 3047 return ret_val; 3048 3049 DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data); 3050 3051 /* Need to reset the PHY or these changes will be ignored */ 3052 mii_ctrl_reg |= MII_CR_RESET; 3053 3054 } 3055 /* Disable MDI-X support for 10/100 */ 3056 else if (hw->phy_type == em_phy_ife) { 3057 ret_val = em_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data); 3058 if (ret_val) 3059 return ret_val; 3060 3061 phy_data &= ~IFE_PMC_AUTO_MDIX; 3062 phy_data &= ~IFE_PMC_FORCE_MDIX; 3063 3064 ret_val = em_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, phy_data); 3065 if (ret_val) 3066 return ret_val; 3067 } else { 3068 /* 3069 * Clear Auto-Crossover to force MDI manually. IGP requires 3070 * MDI forced whenever speed or duplex are forced. 3071 */ 3072 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, 3073 &phy_data); 3074 if (ret_val) 3075 return ret_val; 3076 3077 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 3078 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 3079 3080 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, 3081 phy_data); 3082 if (ret_val) 3083 return ret_val; 3084 } 3085 3086 /* Write back the modified PHY MII control register. */ 3087 ret_val = em_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg); 3088 if (ret_val) 3089 return ret_val; 3090 3091 usec_delay(1); 3092 /* 3093 * The wait_autoneg_complete flag may be a little misleading here. 3094 * Since we are forcing speed and duplex, Auto-Neg is not enabled. 3095 * But we do want to delay for a period while forcing only so we 3096 * don't generate false No Link messages. So we will wait here only 3097 * if the user has set wait_autoneg_complete to 1, which is the 3098 * default. 3099 */ 3100 if (hw->wait_autoneg_complete) { 3101 /* We will wait for autoneg to complete. */ 3102 DEBUGOUT("Waiting for forced speed/duplex link.\n"); 3103 mii_status_reg = 0; 3104 /* 3105 * We will wait for autoneg to complete or 4.5 seconds to 3106 * expire. 3107 */ 3108 for (i = PHY_FORCE_TIME; i > 0; i--) { 3109 /* 3110 * Read the MII Status Register and wait for Auto-Neg 3111 * Complete bit to be set. 3112 */ 3113 ret_val = em_read_phy_reg(hw, PHY_STATUS, 3114 &mii_status_reg); 3115 if (ret_val) 3116 return ret_val; 3117 3118 ret_val = em_read_phy_reg(hw, PHY_STATUS, 3119 &mii_status_reg); 3120 if (ret_val) 3121 return ret_val; 3122 3123 if (mii_status_reg & MII_SR_LINK_STATUS) 3124 break; 3125 msec_delay(100); 3126 } 3127 if ((i == 0) && 3128 ((hw->phy_type == em_phy_m88) || 3129 (hw->phy_type == em_phy_gg82563) || 3130 (hw->phy_type == em_phy_bm))) { 3131 /* 3132 * We didn't get link. Reset the DSP and wait again 3133 * for link. 3134 */ 3135 ret_val = em_phy_reset_dsp(hw); 3136 if (ret_val) { 3137 DEBUGOUT("Error Resetting PHY DSP\n"); 3138 return ret_val; 3139 } 3140 } 3141 /* 3142 * This loop will early-out if the link condition has been 3143 * met. 3144 */ 3145 for (i = PHY_FORCE_TIME; i > 0; i--) { 3146 if (mii_status_reg & MII_SR_LINK_STATUS) 3147 break; 3148 msec_delay(100); 3149 /* 3150 * Read the MII Status Register and wait for Auto-Neg 3151 * Complete bit to be set. 3152 */ 3153 ret_val = em_read_phy_reg(hw, PHY_STATUS, 3154 &mii_status_reg); 3155 if (ret_val) 3156 return ret_val; 3157 3158 ret_val = em_read_phy_reg(hw, PHY_STATUS, 3159 &mii_status_reg); 3160 if (ret_val) 3161 return ret_val; 3162 } 3163 } 3164 if (hw->phy_type == em_phy_m88 || 3165 hw->phy_type == em_phy_bm || 3166 hw->phy_type == em_phy_oem) { 3167 /* 3168 * Because we reset the PHY above, we need to re-force TX_CLK 3169 * in the Extended PHY Specific Control Register to 25MHz 3170 * clock. This value defaults back to a 2.5MHz clock when 3171 * the PHY is reset. 3172 */ 3173 ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 3174 &phy_data); 3175 if (ret_val) 3176 return ret_val; 3177 3178 phy_data |= M88E1000_EPSCR_TX_CLK_25; 3179 ret_val = em_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 3180 phy_data); 3181 if (ret_val) 3182 return ret_val; 3183 /* 3184 * In addition, because of the s/w reset above, we need to 3185 * enable CRS on TX. This must be set for both full and half 3186 * duplex operation. 3187 */ 3188 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 3189 &phy_data); 3190 if (ret_val) 3191 return ret_val; 3192 3193 if (hw->phy_id == M88E1141_E_PHY_ID) 3194 phy_data &= ~M88E1000_PSCR_ASSERT_CRS_ON_TX; 3195 else 3196 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 3197 3198 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 3199 phy_data); 3200 if (ret_val) 3201 return ret_val; 3202 3203 if ((hw->mac_type == em_82544 || hw->mac_type == em_82543) && 3204 (!hw->autoneg) && (hw->forced_speed_duplex == em_10_full || 3205 hw->forced_speed_duplex == em_10_half)) { 3206 ret_val = em_polarity_reversal_workaround(hw); 3207 if (ret_val) 3208 return ret_val; 3209 } 3210 } else if (hw->phy_type == em_phy_gg82563) { 3211 /* 3212 * The TX_CLK of the Extended PHY Specific Control Register 3213 * defaults to 2.5MHz on a reset. We need to re-force it 3214 * back to 25MHz, if we're not in a forced 10/duplex 3215 * configuration. 3216 */ 3217 ret_val = em_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 3218 &phy_data); 3219 if (ret_val) 3220 return ret_val; 3221 3222 phy_data &= ~GG82563_MSCR_TX_CLK_MASK; 3223 if ((hw->forced_speed_duplex == em_10_full) || 3224 (hw->forced_speed_duplex == em_10_half)) 3225 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ; 3226 else 3227 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25MHZ; 3228 3229 /* Also due to the reset, we need to enable CRS on Tx. */ 3230 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 3231 3232 ret_val = em_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 3233 phy_data); 3234 if (ret_val) 3235 return ret_val; 3236 } 3237 return E1000_SUCCESS; 3238 } 3239 3240 /****************************************************************************** 3241 * Sets the collision distance in the Transmit Control register 3242 * 3243 * hw - Struct containing variables accessed by shared code 3244 * 3245 * Link should have been established previously. Reads the speed and duplex 3246 * information from the Device Status register. 3247 *****************************************************************************/ 3248 void 3249 em_config_collision_dist(struct em_hw *hw) 3250 { 3251 uint32_t tctl, coll_dist; 3252 DEBUGFUNC("em_config_collision_dist"); 3253 3254 if (hw->mac_type < em_82543) 3255 coll_dist = E1000_COLLISION_DISTANCE_82542; 3256 else 3257 coll_dist = E1000_COLLISION_DISTANCE; 3258 3259 tctl = E1000_READ_REG(hw, TCTL); 3260 3261 tctl &= ~E1000_TCTL_COLD; 3262 tctl |= coll_dist << E1000_COLD_SHIFT; 3263 3264 E1000_WRITE_REG(hw, TCTL, tctl); 3265 E1000_WRITE_FLUSH(hw); 3266 } 3267 3268 /****************************************************************************** 3269 * Sets MAC speed and duplex settings to reflect the those in the PHY 3270 * 3271 * hw - Struct containing variables accessed by shared code 3272 * mii_reg - data to write to the MII control register 3273 * 3274 * The contents of the PHY register containing the needed information need to 3275 * be passed in. 3276 *****************************************************************************/ 3277 static int32_t 3278 em_config_mac_to_phy(struct em_hw *hw) 3279 { 3280 uint32_t ctrl; 3281 int32_t ret_val; 3282 uint16_t phy_data; 3283 DEBUGFUNC("em_config_mac_to_phy"); 3284 /* 3285 * 82544 or newer MAC, Auto Speed Detection takes care of MAC 3286 * speed/duplex configuration. 3287 */ 3288 if (hw->mac_type >= em_82544 3289 && hw->mac_type != em_icp_xxxx) 3290 return E1000_SUCCESS; 3291 /* 3292 * Read the Device Control Register and set the bits to Force Speed 3293 * and Duplex. 3294 */ 3295 ctrl = E1000_READ_REG(hw, CTRL); 3296 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 3297 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); 3298 /* 3299 * Set up duplex in the Device Control and Transmit Control registers 3300 * depending on negotiated values. 3301 */ 3302 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 3303 if (ret_val) 3304 return ret_val; 3305 3306 if (phy_data & M88E1000_PSSR_DPLX) 3307 ctrl |= E1000_CTRL_FD; 3308 else 3309 ctrl &= ~E1000_CTRL_FD; 3310 3311 em_config_collision_dist(hw); 3312 /* 3313 * Set up speed in the Device Control register depending on 3314 * negotiated values. 3315 */ 3316 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) 3317 ctrl |= E1000_CTRL_SPD_1000; 3318 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) 3319 ctrl |= E1000_CTRL_SPD_100; 3320 3321 /* Write the configured values back to the Device Control Reg. */ 3322 E1000_WRITE_REG(hw, CTRL, ctrl); 3323 return E1000_SUCCESS; 3324 } 3325 3326 /****************************************************************************** 3327 * Forces the MAC's flow control settings. 3328 * 3329 * hw - Struct containing variables accessed by shared code 3330 * 3331 * Sets the TFCE and RFCE bits in the device control register to reflect 3332 * the adapter settings. TFCE and RFCE need to be explicitly set by 3333 * software when a Copper PHY is used because autonegotiation is managed 3334 * by the PHY rather than the MAC. Software must also configure these 3335 * bits when link is forced on a fiber connection. 3336 *****************************************************************************/ 3337 int32_t 3338 em_force_mac_fc(struct em_hw *hw) 3339 { 3340 uint32_t ctrl; 3341 DEBUGFUNC("em_force_mac_fc"); 3342 3343 /* Get the current configuration of the Device Control Register */ 3344 ctrl = E1000_READ_REG(hw, CTRL); 3345 /* 3346 * Because we didn't get link via the internal auto-negotiation 3347 * mechanism (we either forced link or we got link via PHY auto-neg), 3348 * we have to manually enable/disable transmit an receive flow 3349 * control. 3350 * 3351 * The "Case" statement below enables/disable flow control according to 3352 * the "hw->fc" parameter. 3353 * 3354 * The possible values of the "fc" parameter are: 0: Flow control is 3355 * completely disabled 1: Rx flow control is enabled (we can receive 3356 * pause frames but not send pause frames). 2: Tx flow control is 3357 * enabled (we can send pause frames frames but we do not receive 3358 * pause frames). 3: Both Rx and TX flow control (symmetric) is 3359 * enabled. other: No other values should be possible at this point. 3360 */ 3361 3362 switch (hw->fc) { 3363 case E1000_FC_NONE: 3364 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 3365 break; 3366 case E1000_FC_RX_PAUSE: 3367 ctrl &= (~E1000_CTRL_TFCE); 3368 ctrl |= E1000_CTRL_RFCE; 3369 break; 3370 case E1000_FC_TX_PAUSE: 3371 ctrl &= (~E1000_CTRL_RFCE); 3372 ctrl |= E1000_CTRL_TFCE; 3373 break; 3374 case E1000_FC_FULL: 3375 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 3376 break; 3377 default: 3378 DEBUGOUT("Flow control param set incorrectly\n"); 3379 return -E1000_ERR_CONFIG; 3380 } 3381 3382 /* Disable TX Flow Control for 82542 (rev 2.0) */ 3383 if (hw->mac_type == em_82542_rev2_0) 3384 ctrl &= (~E1000_CTRL_TFCE); 3385 3386 E1000_WRITE_REG(hw, CTRL, ctrl); 3387 return E1000_SUCCESS; 3388 } 3389 /****************************************************************************** 3390 * Configures flow control settings after link is established 3391 * 3392 * hw - Struct containing variables accessed by shared code 3393 * 3394 * Should be called immediately after a valid link has been established. 3395 * Forces MAC flow control settings if link was forced. When in MII/GMII mode 3396 * and autonegotiation is enabled, the MAC flow control settings will be set 3397 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE 3398 * and RFCE bits will be automaticaly set to the negotiated flow control mode. 3399 *****************************************************************************/ 3400 STATIC int32_t 3401 em_config_fc_after_link_up(struct em_hw *hw) 3402 { 3403 int32_t ret_val; 3404 uint16_t mii_status_reg; 3405 uint16_t mii_nway_adv_reg; 3406 uint16_t mii_nway_lp_ability_reg; 3407 uint16_t speed; 3408 uint16_t duplex; 3409 DEBUGFUNC("em_config_fc_after_link_up"); 3410 /* 3411 * Check for the case where we have fiber media and auto-neg failed 3412 * so we had to force link. In this case, we need to force the 3413 * configuration of the MAC to match the "fc" parameter. 3414 */ 3415 if (((hw->media_type == em_media_type_fiber) && (hw->autoneg_failed)) 3416 || ((hw->media_type == em_media_type_internal_serdes) && 3417 (hw->autoneg_failed)) || 3418 ((hw->media_type == em_media_type_copper) && (!hw->autoneg)) || 3419 ((hw->media_type == em_media_type_oem) && (!hw->autoneg))) { 3420 ret_val = em_force_mac_fc(hw); 3421 if (ret_val) { 3422 DEBUGOUT("Error forcing flow control settings\n"); 3423 return ret_val; 3424 } 3425 } 3426 /* 3427 * Check for the case where we have copper media and auto-neg is 3428 * enabled. In this case, we need to check and see if Auto-Neg has 3429 * completed, and if so, how the PHY and link partner has flow 3430 * control configured. 3431 */ 3432 if ((hw->media_type == em_media_type_copper || 3433 (hw->media_type == em_media_type_oem)) && 3434 hw->autoneg) { 3435 /* 3436 * Read the MII Status Register and check to see if AutoNeg 3437 * has completed. We read this twice because this reg has 3438 * some "sticky" (latched) bits. 3439 */ 3440 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 3441 if (ret_val) 3442 return ret_val; 3443 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 3444 if (ret_val) 3445 return ret_val; 3446 3447 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) { 3448 /* 3449 * The AutoNeg process has completed, so we now need 3450 * to read both the Auto Negotiation Advertisement 3451 * Register (Address 4) and the Auto_Negotiation Base 3452 * Page Ability Register (Address 5) to determine how 3453 * flow control was negotiated. 3454 */ 3455 ret_val = em_read_phy_reg(hw, PHY_AUTONEG_ADV, 3456 &mii_nway_adv_reg); 3457 if (ret_val) 3458 return ret_val; 3459 ret_val = em_read_phy_reg(hw, PHY_LP_ABILITY, 3460 &mii_nway_lp_ability_reg); 3461 if (ret_val) 3462 return ret_val; 3463 /* 3464 * Two bits in the Auto Negotiation Advertisement 3465 * Register (Address 4) and two bits in the Auto 3466 * Negotiation Base Page Ability Register (Address 5) 3467 * determine flow control for both the PHY and the 3468 * link partner. The following table, taken out of 3469 * the IEEE 802.3ab/D6.0 dated March 25, 1999, 3470 * describes these PAUSE resolution bits and how flow 3471 * control is determined based upon these settings. 3472 * NOTE: DC = Don't Care 3473 * 3474 * LOCAL DEVICE | LINK PARTNER | 3475 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 3476 * -------|---------|-------|---------|--------------- 3477 * 0 | 0 | DC | DC | em_fc_none 3478 * 0 | 1 | 0 | DC | em_fc_none 3479 * 0 | 1 | 1 | 0 | em_fc_none 3480 * 0 | 1 | 1 | 1 | em_fc_tx_pause 3481 * 1 | 0 | 0 | DC | em_fc_none 3482 * 1 | DC | 1 | DC | em_fc_full 3483 * 1 | 1 | 0 | 0 | em_fc_none 3484 * 1 | 1 | 0 | 1 | em_fc_rx_pause 3485 * 3486 */ 3487 /* 3488 * Are both PAUSE bits set to 1? If so, this implies 3489 * Symmetric Flow Control is enabled at both ends. 3490 * The ASM_DIR bits are irrelevant per the spec. 3491 * 3492 * For Symmetric Flow Control: 3493 * 3494 * LOCAL DEVICE | LINK PARTNER 3495 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 3496 * -------|---------|-------|---------|--------------- 3497 * 1 | DC | 1 | DC | em_fc_full 3498 * 3499 */ 3500 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 3501 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 3502 /* 3503 * Now we need to check if the user selected 3504 * RX ONLY of pause frames. In this case, we 3505 * had to advertise FULL flow control because 3506 * we could not advertise RX ONLY. Hence, we 3507 * must now check to see if we need to turn 3508 * OFF the TRANSMISSION of PAUSE frames. 3509 */ 3510 if (hw->original_fc == E1000_FC_FULL) { 3511 hw->fc = E1000_FC_FULL; 3512 DEBUGOUT("Flow Control = FULL.\n"); 3513 } else { 3514 hw->fc = E1000_FC_RX_PAUSE; 3515 DEBUGOUT("Flow Control = RX PAUSE" 3516 " frames only.\n"); 3517 } 3518 } 3519 /* 3520 * For receiving PAUSE frames ONLY. 3521 * 3522 * LOCAL DEVICE | LINK PARTNER PAUSE | ASM_DIR | 3523 * PAUSE | ASM_DIR | Result 3524 * -------|---------|-------|---------|--------------- 3525 * ----- 0 | 1 | 1 | 1 | 3526 * em_fc_tx_pause 3527 * 3528 */ 3529 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 3530 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 3531 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 3532 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 3533 hw->fc = E1000_FC_TX_PAUSE; 3534 DEBUGOUT("Flow Control = TX PAUSE frames only." 3535 "\n"); 3536 } 3537 /* 3538 * For transmitting PAUSE frames ONLY. 3539 * 3540 * LOCAL DEVICE | LINK PARTNER 3541 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 3542 * -------|---------|-------|---------|--------------- 3543 * 1 | 1 | 0 | 1 | em_fc_rx_pause 3544 * 3545 */ 3546 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 3547 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 3548 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 3549 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 3550 hw->fc = E1000_FC_RX_PAUSE; 3551 DEBUGOUT("Flow Control = RX PAUSE frames only." 3552 "\n"); 3553 } 3554 /* 3555 * Per the IEEE spec, at this point flow control 3556 * should be disabled. However, we want to consider 3557 * that we could be connected to a legacy switch that 3558 * doesn't advertise desired flow control, but can be 3559 * forced on the link partner. So if we advertised 3560 * no flow control, that is what we will resolve to. 3561 * If we advertised some kind of receive capability 3562 * (Rx Pause Only or Full Flow Control) and the link 3563 * partner advertised none, we will configure 3564 * ourselves to enable Rx Flow Control only. We can 3565 * do this safely for two reasons: If the link 3566 * partner really didn't want flow control enabled, 3567 * and we enable Rx, no harm done since we won't be 3568 * receiving any PAUSE frames anyway. If the intent 3569 * on the link partner was to have flow control 3570 * enabled, then by us enabling RX only, we can at 3571 * least receive pause frames and process them. This 3572 * is a good idea because in most cases, since we are 3573 * predominantly a server NIC, more times than not we 3574 * will be asked to delay transmission of packets 3575 * than asking our link partner to pause transmission 3576 * of frames. 3577 */ 3578 else if ((hw->original_fc == E1000_FC_NONE || 3579 hw->original_fc == E1000_FC_TX_PAUSE) || 3580 hw->fc_strict_ieee) { 3581 hw->fc = E1000_FC_NONE; 3582 DEBUGOUT("Flow Control = NONE.\n"); 3583 } else { 3584 hw->fc = E1000_FC_RX_PAUSE; 3585 DEBUGOUT("Flow Control = RX PAUSE frames only." 3586 "\n"); 3587 } 3588 /* 3589 * Now we need to do one last check... If we auto- 3590 * negotiated to HALF DUPLEX, flow control should not 3591 * be enabled per IEEE 802.3 spec. 3592 */ 3593 ret_val = em_get_speed_and_duplex(hw, &speed, &duplex); 3594 if (ret_val) { 3595 DEBUGOUT("Error getting link speed and duplex" 3596 "\n"); 3597 return ret_val; 3598 } 3599 if (duplex == HALF_DUPLEX) 3600 hw->fc = E1000_FC_NONE; 3601 /* 3602 * Now we call a subroutine to actually force the MAC 3603 * controller to use the correct flow control 3604 * settings. 3605 */ 3606 ret_val = em_force_mac_fc(hw); 3607 if (ret_val) { 3608 DEBUGOUT("Error forcing flow control settings" 3609 "\n"); 3610 return ret_val; 3611 } 3612 } else { 3613 DEBUGOUT("Copper PHY and Auto Neg has not completed." 3614 "\n"); 3615 } 3616 } 3617 return E1000_SUCCESS; 3618 } 3619 /****************************************************************************** 3620 * Checks to see if the link status of the hardware has changed. 3621 * 3622 * hw - Struct containing variables accessed by shared code 3623 * 3624 * Called by any function that needs to check the link status of the adapter. 3625 *****************************************************************************/ 3626 int32_t 3627 em_check_for_link(struct em_hw *hw) 3628 { 3629 uint32_t rxcw = 0; 3630 uint32_t ctrl; 3631 uint32_t status; 3632 uint32_t rctl; 3633 uint32_t icr; 3634 uint32_t signal = 0; 3635 int32_t ret_val; 3636 uint16_t phy_data; 3637 DEBUGFUNC("em_check_for_link"); 3638 uint16_t speed, duplex; 3639 3640 if (hw->mac_type >= em_82575 && 3641 hw->media_type != em_media_type_copper) { 3642 ret_val = em_get_pcs_speed_and_duplex_82575(hw, &speed, 3643 &duplex); 3644 hw->get_link_status = hw->serdes_link_down; 3645 3646 return (ret_val); 3647 } 3648 3649 ctrl = E1000_READ_REG(hw, CTRL); 3650 status = E1000_READ_REG(hw, STATUS); 3651 /* 3652 * On adapters with a MAC newer than 82544, SW Defineable pin 1 will 3653 * be set when the optics detect a signal. On older adapters, it will 3654 * be cleared when there is a signal. This applies to fiber media 3655 * only. 3656 */ 3657 if ((hw->media_type == em_media_type_fiber) || 3658 (hw->media_type == em_media_type_internal_serdes)) { 3659 rxcw = E1000_READ_REG(hw, RXCW); 3660 3661 if (hw->media_type == em_media_type_fiber) { 3662 signal = (hw->mac_type > em_82544) ? 3663 E1000_CTRL_SWDPIN1 : 0; 3664 if (status & E1000_STATUS_LU) 3665 hw->get_link_status = FALSE; 3666 } 3667 } 3668 /* 3669 * If we have a copper PHY then we only want to go out to the PHY 3670 * registers to see if Auto-Neg has completed and/or if our link 3671 * status has changed. The get_link_status flag will be set if we 3672 * receive a Link Status Change interrupt or we have Rx Sequence 3673 * Errors. 3674 */ 3675 if ((hw->media_type == em_media_type_copper || 3676 (hw->media_type == em_media_type_oem)) && 3677 hw->get_link_status) { 3678 /* 3679 * First we want to see if the MII Status Register reports 3680 * link. If so, then we want to get the current speed/duplex 3681 * of the PHY. Read the register twice since the link bit is 3682 * sticky. 3683 */ 3684 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 3685 if (ret_val) 3686 return ret_val; 3687 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 3688 if (ret_val) 3689 return ret_val; 3690 3691 hw->icp_xxxx_is_link_up = (phy_data & MII_SR_LINK_STATUS) != 0; 3692 3693 if (hw->mac_type == em_pchlan) { 3694 ret_val = em_k1_gig_workaround_hv(hw, 3695 hw->icp_xxxx_is_link_up); 3696 if (ret_val) 3697 return ret_val; 3698 } 3699 3700 if (phy_data & MII_SR_LINK_STATUS) { 3701 hw->get_link_status = FALSE; 3702 3703 if (hw->phy_type == em_phy_82578) { 3704 ret_val = em_link_stall_workaround_hv(hw); 3705 if (ret_val) 3706 return ret_val; 3707 } 3708 3709 if (hw->mac_type == em_pch2lan) { 3710 ret_val = em_k1_workaround_lv(hw); 3711 if (ret_val) 3712 return ret_val; 3713 } 3714 3715 /* 3716 * Check if there was DownShift, must be checked 3717 * immediately after link-up 3718 */ 3719 em_check_downshift(hw); 3720 3721 /* Enable/Disable EEE after link up */ 3722 if (hw->mac_type == em_pch2lan || 3723 hw->mac_type == em_pch_lpt) { 3724 ret_val = em_set_eee_pchlan(hw); 3725 if (ret_val) 3726 return ret_val; 3727 } 3728 3729 /* 3730 * If we are on 82544 or 82543 silicon and 3731 * speed/duplex are forced to 10H or 10F, then we 3732 * will implement the polarity reversal workaround. 3733 * We disable interrupts first, and upon returning, 3734 * place the devices interrupt state to its previous 3735 * value except for the link status change interrupt 3736 * which will happen due to the execution of this 3737 * workaround. 3738 */ 3739 if ((hw->mac_type == em_82544 || 3740 hw->mac_type == em_82543) && (!hw->autoneg) && 3741 (hw->forced_speed_duplex == em_10_full || 3742 hw->forced_speed_duplex == em_10_half)) { 3743 E1000_WRITE_REG(hw, IMC, 0xffffffff); 3744 ret_val = em_polarity_reversal_workaround(hw); 3745 icr = E1000_READ_REG(hw, ICR); 3746 E1000_WRITE_REG(hw, ICS, 3747 (icr & ~E1000_ICS_LSC)); 3748 E1000_WRITE_REG(hw, IMS, IMS_ENABLE_MASK); 3749 } 3750 } else { 3751 /* No link detected */ 3752 em_config_dsp_after_link_change(hw, FALSE); 3753 return 0; 3754 } 3755 /* 3756 * If we are forcing speed/duplex, then we simply return 3757 * since we have already determined whether we have link or 3758 * not. 3759 */ 3760 if (!hw->autoneg) 3761 return -E1000_ERR_CONFIG; 3762 3763 /* optimize the dsp settings for the igp phy */ 3764 em_config_dsp_after_link_change(hw, TRUE); 3765 /* 3766 * We have a M88E1000 PHY and Auto-Neg is enabled. If we 3767 * have Si on board that is 82544 or newer, Auto Speed 3768 * Detection takes care of MAC speed/duplex configuration. 3769 * So we only need to configure Collision Distance in the 3770 * MAC. Otherwise, we need to force speed/duplex on the MAC 3771 * to the current PHY speed/duplex settings. 3772 */ 3773 if (hw->mac_type >= em_82544 && hw->mac_type != em_icp_xxxx) 3774 em_config_collision_dist(hw); 3775 else { 3776 ret_val = em_config_mac_to_phy(hw); 3777 if (ret_val) { 3778 DEBUGOUT("Error configuring MAC to PHY" 3779 " settings\n"); 3780 return ret_val; 3781 } 3782 } 3783 /* 3784 * Configure Flow Control now that Auto-Neg has completed. 3785 * First, we need to restore the desired flow control 3786 * settings because we may have had to re-autoneg with a 3787 * different link partner. 3788 */ 3789 ret_val = em_config_fc_after_link_up(hw); 3790 if (ret_val) { 3791 DEBUGOUT("Error configuring flow control\n"); 3792 return ret_val; 3793 } 3794 /* 3795 * At this point we know that we are on copper and we have 3796 * auto-negotiated link. These are conditions for checking 3797 * the link partner capability register. We use the link 3798 * speed to determine if TBI compatibility needs to be turned 3799 * on or off. If the link is not at gigabit speed, then TBI 3800 * compatibility is not needed. If we are at gigabit speed, 3801 * we turn on TBI compatibility. 3802 */ 3803 if (hw->tbi_compatibility_en) { 3804 uint16_t speed, duplex; 3805 ret_val = em_get_speed_and_duplex(hw, &speed, &duplex); 3806 if (ret_val) { 3807 DEBUGOUT("Error getting link speed and duplex" 3808 "\n"); 3809 return ret_val; 3810 } 3811 if (speed != SPEED_1000) { 3812 /* 3813 * If link speed is not set to gigabit speed, 3814 * we do not need to enable TBI 3815 * compatibility. 3816 */ 3817 if (hw->tbi_compatibility_on) { 3818 /* 3819 * If we previously were in the mode, 3820 * turn it off. 3821 */ 3822 rctl = E1000_READ_REG(hw, RCTL); 3823 rctl &= ~E1000_RCTL_SBP; 3824 E1000_WRITE_REG(hw, RCTL, rctl); 3825 hw->tbi_compatibility_on = FALSE; 3826 } 3827 } else { 3828 /* 3829 * If TBI compatibility is was previously 3830 * off, turn it on. For compatibility with a 3831 * TBI link partner, we will store bad 3832 * packets. Some frames have an additional 3833 * byte on the end and will look like CRC 3834 * errors to to the hardware. 3835 */ 3836 if (!hw->tbi_compatibility_on) { 3837 hw->tbi_compatibility_on = TRUE; 3838 rctl = E1000_READ_REG(hw, RCTL); 3839 rctl |= E1000_RCTL_SBP; 3840 E1000_WRITE_REG(hw, RCTL, rctl); 3841 } 3842 } 3843 } 3844 } 3845 /* 3846 * If we don't have link (auto-negotiation failed or link partner 3847 * cannot auto-negotiate), the cable is plugged in (we have signal), 3848 * and our link partner is not trying to auto-negotiate with us (we 3849 * are receiving idles or data), we need to force link up. We also 3850 * need to give auto-negotiation time to complete, in case the cable 3851 * was just plugged in. The autoneg_failed flag does this. 3852 */ 3853 else if ((((hw->media_type == em_media_type_fiber) && 3854 ((ctrl & E1000_CTRL_SWDPIN1) == signal)) || 3855 (hw->media_type == em_media_type_internal_serdes)) && 3856 (!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) { 3857 if (hw->autoneg_failed == 0) { 3858 hw->autoneg_failed = 1; 3859 return 0; 3860 } 3861 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 3862 3863 /* Disable auto-negotiation in the TXCW register */ 3864 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE)); 3865 3866 /* Force link-up and also force full-duplex. */ 3867 ctrl = E1000_READ_REG(hw, CTRL); 3868 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 3869 E1000_WRITE_REG(hw, CTRL, ctrl); 3870 3871 /* Configure Flow Control after forcing link up. */ 3872 ret_val = em_config_fc_after_link_up(hw); 3873 if (ret_val) { 3874 DEBUGOUT("Error configuring flow control\n"); 3875 return ret_val; 3876 } 3877 } 3878 /* 3879 * If we are forcing link and we are receiving /C/ ordered sets, 3880 * re-enable auto-negotiation in the TXCW register and disable forced 3881 * link in the Device Control register in an attempt to 3882 * auto-negotiate with our link partner. 3883 */ 3884 else if (((hw->media_type == em_media_type_fiber) || 3885 (hw->media_type == em_media_type_internal_serdes)) && 3886 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 3887 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 3888 E1000_WRITE_REG(hw, TXCW, hw->txcw); 3889 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU)); 3890 3891 hw->serdes_link_down = FALSE; 3892 } 3893 /* 3894 * If we force link for non-auto-negotiation switch, check link 3895 * status based on MAC synchronization for internal serdes media 3896 * type. 3897 */ 3898 else if ((hw->media_type == em_media_type_internal_serdes) && 3899 !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) { 3900 /* SYNCH bit and IV bit are sticky. */ 3901 usec_delay(10); 3902 if (E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) { 3903 if (!(rxcw & E1000_RXCW_IV)) { 3904 hw->serdes_link_down = FALSE; 3905 DEBUGOUT("SERDES: Link is up.\n"); 3906 } 3907 } else { 3908 hw->serdes_link_down = TRUE; 3909 DEBUGOUT("SERDES: Link is down.\n"); 3910 } 3911 } 3912 if ((hw->media_type == em_media_type_internal_serdes) && 3913 (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) { 3914 hw->serdes_link_down = !(E1000_STATUS_LU & 3915 E1000_READ_REG(hw, STATUS)); 3916 } 3917 return E1000_SUCCESS; 3918 } 3919 3920 int32_t 3921 em_get_pcs_speed_and_duplex_82575(struct em_hw *hw, uint16_t *speed, 3922 uint16_t *duplex) 3923 { 3924 uint32_t pcs; 3925 3926 hw->serdes_link_down = TRUE; 3927 *speed = 0; 3928 *duplex = 0; 3929 3930 /* 3931 * Read the PCS Status register for link state. For non-copper mode, 3932 * the status register is not accurate. The PCS status register is 3933 * used instead. 3934 */ 3935 pcs = E1000_READ_REG(hw, PCS_LSTAT); 3936 3937 /* 3938 * The link up bit determines when link is up on autoneg. The sync ok 3939 * gets set once both sides sync up and agree upon link. Stable link 3940 * can be determined by checking for both link up and link sync ok 3941 */ 3942 if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) { 3943 hw->serdes_link_down = FALSE; 3944 3945 /* Detect and store PCS speed */ 3946 if (pcs & E1000_PCS_LSTS_SPEED_1000) { 3947 *speed = SPEED_1000; 3948 } else if (pcs & E1000_PCS_LSTS_SPEED_100) { 3949 *speed = SPEED_100; 3950 } else { 3951 *speed = SPEED_10; 3952 } 3953 3954 /* Detect and store PCS duplex */ 3955 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) { 3956 *duplex = FULL_DUPLEX; 3957 } else { 3958 *duplex = HALF_DUPLEX; 3959 } 3960 } 3961 3962 return (0); 3963 } 3964 3965 3966 /****************************************************************************** 3967 * Detects the current speed and duplex settings of the hardware. 3968 * 3969 * hw - Struct containing variables accessed by shared code 3970 * speed - Speed of the connection 3971 * duplex - Duplex setting of the connection 3972 *****************************************************************************/ 3973 int32_t 3974 em_get_speed_and_duplex(struct em_hw *hw, uint16_t *speed, uint16_t *duplex) 3975 { 3976 uint32_t status; 3977 int32_t ret_val; 3978 uint16_t phy_data; 3979 DEBUGFUNC("em_get_speed_and_duplex"); 3980 3981 if (hw->mac_type >= em_82575 && hw->media_type != em_media_type_copper) 3982 return em_get_pcs_speed_and_duplex_82575(hw, speed, duplex); 3983 3984 if (hw->mac_type >= em_82543) { 3985 status = E1000_READ_REG(hw, STATUS); 3986 if (status & E1000_STATUS_SPEED_1000) { 3987 *speed = SPEED_1000; 3988 DEBUGOUT("1000 Mbs, "); 3989 } else if (status & E1000_STATUS_SPEED_100) { 3990 *speed = SPEED_100; 3991 DEBUGOUT("100 Mbs, "); 3992 } else { 3993 *speed = SPEED_10; 3994 DEBUGOUT("10 Mbs, "); 3995 } 3996 3997 if (status & E1000_STATUS_FD) { 3998 *duplex = FULL_DUPLEX; 3999 DEBUGOUT("Full Duplex\n"); 4000 } else { 4001 *duplex = HALF_DUPLEX; 4002 DEBUGOUT(" Half Duplex\n"); 4003 } 4004 } else { 4005 DEBUGOUT("1000 Mbs, Full Duplex\n"); 4006 *speed = SPEED_1000; 4007 *duplex = FULL_DUPLEX; 4008 } 4009 /* 4010 * IGP01 PHY may advertise full duplex operation after speed 4011 * downgrade even if it is operating at half duplex. Here we set the 4012 * duplex settings to match the duplex in the link partner's 4013 * capabilities. 4014 */ 4015 if (hw->phy_type == em_phy_igp && hw->speed_downgraded) { 4016 ret_val = em_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data); 4017 if (ret_val) 4018 return ret_val; 4019 4020 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS)) 4021 *duplex = HALF_DUPLEX; 4022 else { 4023 ret_val = em_read_phy_reg(hw, PHY_LP_ABILITY, 4024 &phy_data); 4025 if (ret_val) 4026 return ret_val; 4027 if ((*speed == SPEED_100 && 4028 !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) || 4029 (*speed == SPEED_10 && 4030 !(phy_data & NWAY_LPAR_10T_FD_CAPS))) 4031 *duplex = HALF_DUPLEX; 4032 } 4033 } 4034 if ((hw->mac_type == em_80003es2lan) && 4035 (hw->media_type == em_media_type_copper)) { 4036 if (*speed == SPEED_1000) 4037 ret_val = em_configure_kmrn_for_1000(hw); 4038 else 4039 ret_val = em_configure_kmrn_for_10_100(hw, *duplex); 4040 if (ret_val) 4041 return ret_val; 4042 } 4043 if ((hw->mac_type == em_ich8lan) && 4044 (hw->phy_type == em_phy_igp_3) && 4045 (*speed == SPEED_1000)) { 4046 ret_val = em_kumeran_lock_loss_workaround(hw); 4047 if (ret_val) 4048 return ret_val; 4049 } 4050 return E1000_SUCCESS; 4051 } 4052 4053 /****************************************************************************** 4054 * Blocks until autoneg completes or times out (~4.5 seconds) 4055 * 4056 * hw - Struct containing variables accessed by shared code 4057 *****************************************************************************/ 4058 STATIC int32_t 4059 em_wait_autoneg(struct em_hw *hw) 4060 { 4061 int32_t ret_val; 4062 uint16_t i; 4063 uint16_t phy_data; 4064 DEBUGFUNC("em_wait_autoneg"); 4065 DEBUGOUT("Waiting for Auto-Neg to complete.\n"); 4066 4067 /* We will wait for autoneg to complete or 4.5 seconds to expire. */ 4068 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) { 4069 /* 4070 * Read the MII Status Register and wait for Auto-Neg 4071 * Complete bit to be set. 4072 */ 4073 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 4074 if (ret_val) 4075 return ret_val; 4076 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 4077 if (ret_val) 4078 return ret_val; 4079 if (phy_data & MII_SR_AUTONEG_COMPLETE) { 4080 return E1000_SUCCESS; 4081 } 4082 msec_delay(100); 4083 } 4084 return E1000_SUCCESS; 4085 } 4086 4087 /****************************************************************************** 4088 * Raises the Management Data Clock 4089 * 4090 * hw - Struct containing variables accessed by shared code 4091 * ctrl - Device control register's current value 4092 *****************************************************************************/ 4093 static void 4094 em_raise_mdi_clk(struct em_hw *hw, uint32_t *ctrl) 4095 { 4096 /* 4097 * Raise the clock input to the Management Data Clock (by setting the 4098 * MDC bit), and then delay 10 microseconds. 4099 */ 4100 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC)); 4101 E1000_WRITE_FLUSH(hw); 4102 usec_delay(10); 4103 } 4104 4105 /****************************************************************************** 4106 * Lowers the Management Data Clock 4107 * 4108 * hw - Struct containing variables accessed by shared code 4109 * ctrl - Device control register's current value 4110 *****************************************************************************/ 4111 static void 4112 em_lower_mdi_clk(struct em_hw *hw, uint32_t *ctrl) 4113 { 4114 /* 4115 * Lower the clock input to the Management Data Clock (by clearing 4116 * the MDC bit), and then delay 10 microseconds. 4117 */ 4118 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC)); 4119 E1000_WRITE_FLUSH(hw); 4120 usec_delay(10); 4121 } 4122 4123 /****************************************************************************** 4124 * Shifts data bits out to the PHY 4125 * 4126 * hw - Struct containing variables accessed by shared code 4127 * data - Data to send out to the PHY 4128 * count - Number of bits to shift out 4129 * 4130 * Bits are shifted out in MSB to LSB order. 4131 *****************************************************************************/ 4132 static void 4133 em_shift_out_mdi_bits(struct em_hw *hw, uint32_t data, uint16_t count) 4134 { 4135 uint32_t ctrl; 4136 uint32_t mask; 4137 /* 4138 * We need to shift "count" number of bits out to the PHY. So, the 4139 * value in the "data" parameter will be shifted out to the PHY one 4140 * bit at a time. In order to do this, "data" must be broken down 4141 * into bits. 4142 */ 4143 mask = 0x01; 4144 mask <<= (count - 1); 4145 4146 ctrl = E1000_READ_REG(hw, CTRL); 4147 4148 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output 4149 * pins. 4150 */ 4151 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); 4152 4153 while (mask) { 4154 /* 4155 * A "1" is shifted out to the PHY by setting the MDIO bit to 4156 * "1" and then raising and lowering the Management Data 4157 * Clock. A "0" is shifted out to the PHY by setting the MDIO 4158 * bit to "0" and then raising and lowering the clock. 4159 */ 4160 if (data & mask) 4161 ctrl |= E1000_CTRL_MDIO; 4162 else 4163 ctrl &= ~E1000_CTRL_MDIO; 4164 4165 E1000_WRITE_REG(hw, CTRL, ctrl); 4166 E1000_WRITE_FLUSH(hw); 4167 4168 usec_delay(10); 4169 4170 em_raise_mdi_clk(hw, &ctrl); 4171 em_lower_mdi_clk(hw, &ctrl); 4172 4173 mask = mask >> 1; 4174 } 4175 } 4176 4177 /****************************************************************************** 4178 * Shifts data bits in from the PHY 4179 * 4180 * hw - Struct containing variables accessed by shared code 4181 * 4182 * Bits are shifted in in MSB to LSB order. 4183 *****************************************************************************/ 4184 static uint16_t 4185 em_shift_in_mdi_bits(struct em_hw *hw) 4186 { 4187 uint32_t ctrl; 4188 uint16_t data = 0; 4189 uint8_t i; 4190 /* 4191 * In order to read a register from the PHY, we need to shift in a 4192 * total of 18 bits from the PHY. The first two bit (turnaround) 4193 * times are used to avoid contention on the MDIO pin when a read 4194 * operation is performed. These two bits are ignored by us and 4195 * thrown away. Bits are "shifted in" by raising the input to the 4196 * Management Data Clock (setting the MDC bit), and then reading the 4197 * value of the MDIO bit. 4198 */ 4199 ctrl = E1000_READ_REG(hw, CTRL); 4200 /* 4201 * Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as 4202 * input. 4203 */ 4204 ctrl &= ~E1000_CTRL_MDIO_DIR; 4205 ctrl &= ~E1000_CTRL_MDIO; 4206 4207 E1000_WRITE_REG(hw, CTRL, ctrl); 4208 E1000_WRITE_FLUSH(hw); 4209 /* 4210 * Raise and Lower the clock before reading in the data. This 4211 * accounts for the turnaround bits. The first clock occurred when we 4212 * clocked out the last bit of the Register Address. 4213 */ 4214 em_raise_mdi_clk(hw, &ctrl); 4215 em_lower_mdi_clk(hw, &ctrl); 4216 4217 for (data = 0, i = 0; i < 16; i++) { 4218 data = data << 1; 4219 em_raise_mdi_clk(hw, &ctrl); 4220 ctrl = E1000_READ_REG(hw, CTRL); 4221 /* Check to see if we shifted in a "1". */ 4222 if (ctrl & E1000_CTRL_MDIO) 4223 data |= 1; 4224 em_lower_mdi_clk(hw, &ctrl); 4225 } 4226 4227 em_raise_mdi_clk(hw, &ctrl); 4228 em_lower_mdi_clk(hw, &ctrl); 4229 4230 return data; 4231 } 4232 4233 STATIC int32_t 4234 em_swfw_sync_acquire(struct em_hw *hw, uint16_t mask) 4235 { 4236 uint32_t swfw_sync = 0; 4237 uint32_t swmask = mask; 4238 uint32_t fwmask = mask << 16; 4239 int32_t timeout = 200; 4240 DEBUGFUNC("em_swfw_sync_acquire"); 4241 4242 if (hw->swfwhw_semaphore_present) 4243 return em_get_software_flag(hw); 4244 4245 if (!hw->swfw_sync_present) 4246 return em_get_hw_eeprom_semaphore(hw); 4247 4248 while (timeout) { 4249 if (em_get_hw_eeprom_semaphore(hw)) 4250 return -E1000_ERR_SWFW_SYNC; 4251 4252 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); 4253 if (!(swfw_sync & (fwmask | swmask))) { 4254 break; 4255 } 4256 /* 4257 * firmware currently using resource (fwmask) 4258 * or other software thread currently using resource (swmask) 4259 */ 4260 em_put_hw_eeprom_semaphore(hw); 4261 msec_delay_irq(5); 4262 timeout--; 4263 } 4264 4265 if (!timeout) { 4266 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout." 4267 "\n"); 4268 return -E1000_ERR_SWFW_SYNC; 4269 } 4270 swfw_sync |= swmask; 4271 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync); 4272 4273 em_put_hw_eeprom_semaphore(hw); 4274 return E1000_SUCCESS; 4275 } 4276 4277 STATIC void 4278 em_swfw_sync_release(struct em_hw *hw, uint16_t mask) 4279 { 4280 uint32_t swfw_sync; 4281 uint32_t swmask = mask; 4282 DEBUGFUNC("em_swfw_sync_release"); 4283 4284 if (hw->swfwhw_semaphore_present) { 4285 em_release_software_flag(hw); 4286 return; 4287 } 4288 if (!hw->swfw_sync_present) { 4289 em_put_hw_eeprom_semaphore(hw); 4290 return; 4291 } 4292 /* 4293 * if (em_get_hw_eeprom_semaphore(hw)) return -E1000_ERR_SWFW_SYNC; 4294 */ 4295 while (em_get_hw_eeprom_semaphore(hw) != E1000_SUCCESS); 4296 /* empty */ 4297 4298 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); 4299 swfw_sync &= ~swmask; 4300 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync); 4301 4302 em_put_hw_eeprom_semaphore(hw); 4303 } 4304 4305 /**************************************************************************** 4306 * Read BM PHY wakeup register. It works as such: 4307 * 1) Set page 769, register 17, bit 2 = 1 4308 * 2) Set page to 800 for host (801 if we were manageability) 4309 * 3) Write the address using the address opcode (0x11) 4310 * 4) Read or write the data using the data opcode (0x12) 4311 * 5) Restore 769_17.2 to its original value 4312 ****************************************************************************/ 4313 int32_t 4314 em_access_phy_wakeup_reg_bm(struct em_hw *hw, uint32_t reg_addr, 4315 uint16_t *phy_data, boolean_t read) 4316 { 4317 int32_t ret_val; 4318 uint16_t reg = BM_PHY_REG_NUM(reg_addr); 4319 uint16_t phy_reg = 0; 4320 4321 /* All operations in this function are phy address 1 */ 4322 hw->phy_addr = 1; 4323 4324 /* Set page 769 */ 4325 em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 4326 (BM_WUC_ENABLE_PAGE << PHY_PAGE_SHIFT)); 4327 4328 ret_val = em_read_phy_reg_ex(hw, BM_WUC_ENABLE_REG, &phy_reg); 4329 if (ret_val) 4330 goto out; 4331 4332 /* First clear bit 4 to avoid a power state change */ 4333 phy_reg &= ~(BM_WUC_HOST_WU_BIT); 4334 ret_val = em_write_phy_reg_ex(hw, BM_WUC_ENABLE_REG, phy_reg); 4335 if (ret_val) 4336 goto out; 4337 4338 /* Write bit 2 = 1, and clear bit 4 to 769_17 */ 4339 ret_val = em_write_phy_reg_ex(hw, BM_WUC_ENABLE_REG, 4340 phy_reg | BM_WUC_ENABLE_BIT); 4341 if (ret_val) 4342 goto out; 4343 4344 /* Select page 800 */ 4345 ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 4346 (BM_WUC_PAGE << PHY_PAGE_SHIFT)); 4347 4348 /* Write the page 800 offset value using opcode 0x11 */ 4349 ret_val = em_write_phy_reg_ex(hw, BM_WUC_ADDRESS_OPCODE, reg); 4350 if (ret_val) 4351 goto out; 4352 4353 if (read) 4354 /* Read the page 800 value using opcode 0x12 */ 4355 ret_val = em_read_phy_reg_ex(hw, BM_WUC_DATA_OPCODE, 4356 phy_data); 4357 else 4358 /* Write the page 800 value using opcode 0x12 */ 4359 ret_val = em_write_phy_reg_ex(hw, BM_WUC_DATA_OPCODE, 4360 *phy_data); 4361 4362 if (ret_val) 4363 goto out; 4364 4365 /* 4366 * Restore 769_17.2 to its original value 4367 * Set page 769 4368 */ 4369 em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 4370 (BM_WUC_ENABLE_PAGE << PHY_PAGE_SHIFT)); 4371 4372 /* Clear 769_17.2 */ 4373 ret_val = em_write_phy_reg_ex(hw, BM_WUC_ENABLE_REG, phy_reg); 4374 if (ret_val) 4375 goto out; 4376 4377 out: 4378 return ret_val; 4379 } 4380 4381 /*************************************************************************** 4382 * Read HV PHY vendor specific high registers 4383 ***************************************************************************/ 4384 int32_t 4385 em_access_phy_debug_regs_hv(struct em_hw *hw, uint32_t reg_addr, 4386 uint16_t *phy_data, boolean_t read) 4387 { 4388 int32_t ret_val; 4389 uint32_t addr_reg = 0; 4390 uint32_t data_reg = 0; 4391 4392 /* This takes care of the difference with desktop vs mobile phy */ 4393 addr_reg = (hw->phy_type == em_phy_82578) ? 4394 I82578_PHY_ADDR_REG : I82577_PHY_ADDR_REG; 4395 data_reg = addr_reg + 1; 4396 4397 /* All operations in this function are phy address 2 */ 4398 hw->phy_addr = 2; 4399 4400 /* masking with 0x3F to remove the page from offset */ 4401 ret_val = em_write_phy_reg_ex(hw, addr_reg, (uint16_t)reg_addr & 0x3F); 4402 if (ret_val) { 4403 printf("Could not write PHY the HV address register\n"); 4404 goto out; 4405 } 4406 4407 /* Read or write the data value next */ 4408 if (read) 4409 ret_val = em_read_phy_reg_ex(hw, data_reg, phy_data); 4410 else 4411 ret_val = em_write_phy_reg_ex(hw, data_reg, *phy_data); 4412 4413 if (ret_val) { 4414 printf("Could not read data value from HV data register\n"); 4415 goto out; 4416 } 4417 4418 out: 4419 return ret_val; 4420 } 4421 4422 /****************************************************************************** 4423 * Reads or writes the value from a PHY register, if the value is on a specific 4424 * non zero page, sets the page first. 4425 * hw - Struct containing variables accessed by shared code 4426 * reg_addr - address of the PHY register to read 4427 *****************************************************************************/ 4428 int32_t 4429 em_access_phy_reg_hv(struct em_hw *hw, uint32_t reg_addr, uint16_t *phy_data, 4430 boolean_t read) 4431 { 4432 uint32_t ret_val; 4433 uint16_t swfw; 4434 uint16_t page = BM_PHY_REG_PAGE(reg_addr); 4435 uint16_t reg = BM_PHY_REG_NUM(reg_addr); 4436 4437 DEBUGFUNC("em_access_phy_reg_hv"); 4438 4439 swfw = E1000_SWFW_PHY0_SM; 4440 4441 if (em_swfw_sync_acquire(hw, swfw)) 4442 return -E1000_ERR_SWFW_SYNC; 4443 4444 if (page == BM_WUC_PAGE) { 4445 ret_val = em_access_phy_wakeup_reg_bm(hw, reg_addr, 4446 phy_data, read); 4447 goto release; 4448 } 4449 4450 if (page >= HV_INTC_FC_PAGE_START) 4451 hw->phy_addr = 1; 4452 else 4453 hw->phy_addr = 2; 4454 4455 if (page == HV_INTC_FC_PAGE_START) 4456 page = 0; 4457 4458 /* 4459 * Workaround MDIO accesses being disabled after entering IEEE Power 4460 * Down (whenever bit 11 of the PHY Control register is set) 4461 */ 4462 if (!read && 4463 (hw->phy_type == em_phy_82578) && 4464 (hw->phy_revision >= 1) && 4465 (hw->phy_addr == 2) && 4466 ((MAX_PHY_REG_ADDRESS & reg) == 0) && 4467 (*phy_data & (1 << 11))) { 4468 uint16_t data2 = 0x7EFF; 4469 4470 ret_val = em_access_phy_debug_regs_hv(hw, (1 << 6) | 0x3, 4471 &data2, FALSE); 4472 if (ret_val) 4473 return ret_val; 4474 } 4475 4476 if (reg_addr > MAX_PHY_MULTI_PAGE_REG) { 4477 ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 4478 (page << PHY_PAGE_SHIFT)); 4479 if (ret_val) 4480 return ret_val; 4481 } 4482 if (read) 4483 ret_val = em_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg, 4484 phy_data); 4485 else 4486 ret_val = em_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg, 4487 *phy_data); 4488 release: 4489 em_swfw_sync_release(hw, swfw); 4490 return ret_val; 4491 } 4492 4493 /****************************************************************************** 4494 * Reads the value from a PHY register, if the value is on a specific non zero 4495 * page, sets the page first. 4496 * hw - Struct containing variables accessed by shared code 4497 * reg_addr - address of the PHY register to read 4498 *****************************************************************************/ 4499 int32_t 4500 em_read_phy_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t *phy_data) 4501 { 4502 uint32_t ret_val; 4503 uint16_t swfw; 4504 DEBUGFUNC("em_read_phy_reg"); 4505 4506 if (hw->mac_type == em_pchlan || 4507 hw->mac_type == em_pch2lan || 4508 hw->mac_type == em_pch_lpt) 4509 return (em_access_phy_reg_hv(hw, reg_addr, phy_data, TRUE)); 4510 4511 if (((hw->mac_type == em_80003es2lan) || (hw->mac_type == em_82575)) && 4512 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { 4513 swfw = E1000_SWFW_PHY1_SM; 4514 } else { 4515 swfw = E1000_SWFW_PHY0_SM; 4516 } 4517 if (em_swfw_sync_acquire(hw, swfw)) 4518 return -E1000_ERR_SWFW_SYNC; 4519 4520 if ((hw->phy_type == em_phy_igp || 4521 hw->phy_type == em_phy_igp_3 || 4522 hw->phy_type == em_phy_igp_2) && 4523 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { 4524 ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 4525 (uint16_t) reg_addr); 4526 if (ret_val) { 4527 em_swfw_sync_release(hw, swfw); 4528 return ret_val; 4529 } 4530 } else if (hw->phy_type == em_phy_gg82563) { 4531 if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) || 4532 (hw->mac_type == em_80003es2lan)) { 4533 /* Select Configuration Page */ 4534 if ((reg_addr & MAX_PHY_REG_ADDRESS) < 4535 GG82563_MIN_ALT_REG) { 4536 ret_val = em_write_phy_reg_ex(hw, 4537 GG82563_PHY_PAGE_SELECT, 4538 (uint16_t) ((uint16_t) reg_addr >> 4539 GG82563_PAGE_SHIFT)); 4540 } else { 4541 /* 4542 * Use Alternative Page Select register to 4543 * access registers 30 and 31 4544 */ 4545 ret_val = em_write_phy_reg_ex(hw, 4546 GG82563_PHY_PAGE_SELECT_ALT, 4547 (uint16_t) ((uint16_t) reg_addr >> 4548 GG82563_PAGE_SHIFT)); 4549 } 4550 4551 if (ret_val) { 4552 em_swfw_sync_release(hw, swfw); 4553 return ret_val; 4554 } 4555 } 4556 } else if ((hw->phy_type == em_phy_bm) && (hw->phy_revision == 1)) { 4557 if (reg_addr > MAX_PHY_MULTI_PAGE_REG) { 4558 ret_val = em_write_phy_reg_ex(hw, BM_PHY_PAGE_SELECT, 4559 (uint16_t) ((uint16_t) reg_addr >> 4560 PHY_PAGE_SHIFT)); 4561 if (ret_val) 4562 return ret_val; 4563 } 4564 } 4565 ret_val = em_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, 4566 phy_data); 4567 4568 em_swfw_sync_release(hw, swfw); 4569 return ret_val; 4570 } 4571 4572 STATIC int32_t 4573 em_read_phy_reg_ex(struct em_hw *hw, uint32_t reg_addr, uint16_t *phy_data) 4574 { 4575 uint32_t i; 4576 uint32_t mdic = 0; 4577 DEBUGFUNC("em_read_phy_reg_ex"); 4578 4579 if (reg_addr > MAX_PHY_REG_ADDRESS) { 4580 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); 4581 return -E1000_ERR_PARAM; 4582 } 4583 if (hw->mac_type == em_icp_xxxx) { 4584 *phy_data = gcu_miibus_readreg(hw, hw->icp_xxxx_port_num, 4585 reg_addr); 4586 return E1000_SUCCESS; 4587 } 4588 if (hw->mac_type > em_82543) { 4589 /* 4590 * Set up Op-code, Phy Address, and register address in the 4591 * MDI Control register. The MAC will take care of 4592 * interfacing with the PHY to retrieve the desired data. 4593 */ 4594 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) | 4595 (hw->phy_addr << E1000_MDIC_PHY_SHIFT) | 4596 (E1000_MDIC_OP_READ)); 4597 4598 E1000_WRITE_REG(hw, MDIC, mdic); 4599 4600 /* 4601 * Poll the ready bit to see if the MDI read completed 4602 * Increasing the time out as testing showed failures with 4603 * the lower time out (from FreeBSD driver) 4604 */ 4605 for (i = 0; i < 1960; i++) { 4606 usec_delay(50); 4607 mdic = E1000_READ_REG(hw, MDIC); 4608 if (mdic & E1000_MDIC_READY) 4609 break; 4610 } 4611 if (!(mdic & E1000_MDIC_READY)) { 4612 DEBUGOUT("MDI Read did not complete\n"); 4613 return -E1000_ERR_PHY; 4614 } 4615 if (mdic & E1000_MDIC_ERROR) { 4616 DEBUGOUT("MDI Error\n"); 4617 return -E1000_ERR_PHY; 4618 } 4619 *phy_data = (uint16_t) mdic; 4620 4621 if (hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt) 4622 usec_delay(100); 4623 } else { 4624 /* 4625 * We must first send a preamble through the MDIO pin to 4626 * signal the beginning of an MII instruction. This is done 4627 * by sending 32 consecutive "1" bits. 4628 */ 4629 em_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 4630 /* 4631 * Now combine the next few fields that are required for a 4632 * read operation. We use this method instead of calling the 4633 * em_shift_out_mdi_bits routine five different times. The 4634 * format of a MII read instruction consists of a shift out 4635 * of 14 bits and is defined as follows: <Preamble><SOF><Op 4636 * Code><Phy Addr><Reg Addr> followed by a shift in of 18 4637 * bits. This first two bits shifted in are TurnAround bits 4638 * used to avoid contention on the MDIO pin when a READ 4639 * operation is performed. These two bits are thrown away 4640 * followed by a shift in of 16 bits which contains the 4641 * desired data. 4642 */ 4643 mdic = ((reg_addr) | (hw->phy_addr << 5) | 4644 (PHY_OP_READ << 10) | (PHY_SOF << 12)); 4645 4646 em_shift_out_mdi_bits(hw, mdic, 14); 4647 /* 4648 * Now that we've shifted out the read command to the MII, we 4649 * need to "shift in" the 16-bit value (18 total bits) of the 4650 * requested PHY register address. 4651 */ 4652 *phy_data = em_shift_in_mdi_bits(hw); 4653 } 4654 return E1000_SUCCESS; 4655 } 4656 4657 /****************************************************************************** 4658 * Writes a value to a PHY register 4659 * 4660 * hw - Struct containing variables accessed by shared code 4661 * reg_addr - address of the PHY register to write 4662 * data - data to write to the PHY 4663 *****************************************************************************/ 4664 int32_t 4665 em_write_phy_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t phy_data) 4666 { 4667 uint32_t ret_val; 4668 DEBUGFUNC("em_write_phy_reg"); 4669 4670 if (hw->mac_type == em_pchlan || 4671 hw->mac_type == em_pch2lan || 4672 hw->mac_type == em_pch_lpt) 4673 return (em_access_phy_reg_hv(hw, reg_addr, &phy_data, FALSE)); 4674 4675 if (em_swfw_sync_acquire(hw, hw->swfw)) 4676 return -E1000_ERR_SWFW_SYNC; 4677 4678 if ((hw->phy_type == em_phy_igp || 4679 hw->phy_type == em_phy_igp_3 || 4680 hw->phy_type == em_phy_igp_2) && 4681 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { 4682 ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 4683 (uint16_t) reg_addr); 4684 if (ret_val) { 4685 em_swfw_sync_release(hw, hw->swfw); 4686 return ret_val; 4687 } 4688 } else if (hw->phy_type == em_phy_gg82563) { 4689 if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) || 4690 (hw->mac_type == em_80003es2lan)) { 4691 /* Select Configuration Page */ 4692 if ((reg_addr & MAX_PHY_REG_ADDRESS) < 4693 GG82563_MIN_ALT_REG) { 4694 ret_val = em_write_phy_reg_ex(hw, 4695 GG82563_PHY_PAGE_SELECT, 4696 (uint16_t) ((uint16_t) reg_addr >> 4697 GG82563_PAGE_SHIFT)); 4698 } else { 4699 /* 4700 * Use Alternative Page Select register to 4701 * access registers 30 and 31 4702 */ 4703 ret_val = em_write_phy_reg_ex(hw, 4704 GG82563_PHY_PAGE_SELECT_ALT, 4705 (uint16_t) ((uint16_t) reg_addr >> 4706 GG82563_PAGE_SHIFT)); 4707 } 4708 4709 if (ret_val) { 4710 em_swfw_sync_release(hw, hw->swfw); 4711 return ret_val; 4712 } 4713 } 4714 } else if ((hw->phy_type == em_phy_bm) && (hw->phy_revision == 1)) { 4715 if (reg_addr > MAX_PHY_MULTI_PAGE_REG) { 4716 ret_val = em_write_phy_reg_ex(hw, BM_PHY_PAGE_SELECT, 4717 (uint16_t) ((uint16_t) reg_addr >> 4718 PHY_PAGE_SHIFT)); 4719 if (ret_val) 4720 return ret_val; 4721 } 4722 } 4723 ret_val = em_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, 4724 phy_data); 4725 4726 em_swfw_sync_release(hw, hw->swfw); 4727 return ret_val; 4728 } 4729 4730 STATIC int32_t 4731 em_write_phy_reg_ex(struct em_hw *hw, uint32_t reg_addr, uint16_t phy_data) 4732 { 4733 uint32_t i; 4734 uint32_t mdic = 0; 4735 DEBUGFUNC("em_write_phy_reg_ex"); 4736 4737 if (reg_addr > MAX_PHY_REG_ADDRESS) { 4738 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); 4739 return -E1000_ERR_PARAM; 4740 } 4741 if (hw->mac_type == em_icp_xxxx) { 4742 gcu_miibus_writereg(hw, hw->icp_xxxx_port_num, 4743 reg_addr, phy_data); 4744 return E1000_SUCCESS; 4745 } 4746 if (hw->mac_type > em_82543) { 4747 /* 4748 * Set up Op-code, Phy Address, register address, and data 4749 * intended for the PHY register in the MDI Control register. 4750 * The MAC will take care of interfacing with the PHY to send 4751 * the desired data. 4752 */ 4753 mdic = (((uint32_t) phy_data) | 4754 (reg_addr << E1000_MDIC_REG_SHIFT) | 4755 (hw->phy_addr << E1000_MDIC_PHY_SHIFT) | 4756 (E1000_MDIC_OP_WRITE)); 4757 4758 E1000_WRITE_REG(hw, MDIC, mdic); 4759 4760 /* Poll the ready bit to see if the MDI read completed */ 4761 for (i = 0; i < 641; i++) { 4762 usec_delay(5); 4763 mdic = E1000_READ_REG(hw, MDIC); 4764 if (mdic & E1000_MDIC_READY) 4765 break; 4766 } 4767 if (!(mdic & E1000_MDIC_READY)) { 4768 DEBUGOUT("MDI Write did not complete\n"); 4769 return -E1000_ERR_PHY; 4770 } 4771 4772 if (hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt) 4773 usec_delay(100); 4774 } else { 4775 /* 4776 * We'll need to use the SW defined pins to shift the write 4777 * command out to the PHY. We first send a preamble to the 4778 * PHY to signal the beginning of the MII instruction. This 4779 * is done by sending 32 consecutive "1" bits. 4780 */ 4781 em_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 4782 /* 4783 * Now combine the remaining required fields that will 4784 * indicate a write operation. We use this method instead of 4785 * calling the em_shift_out_mdi_bits routine for each field 4786 * in the command. The format of a MII write instruction is 4787 * as follows: <Preamble><SOF><Op Code><Phy Addr><Reg 4788 * Addr><Turnaround><Data>. 4789 */ 4790 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | 4791 (hw->phy_addr << 7) | (PHY_OP_WRITE << 12) | 4792 (PHY_SOF << 14)); 4793 mdic <<= 16; 4794 mdic |= (uint32_t) phy_data; 4795 4796 em_shift_out_mdi_bits(hw, mdic, 32); 4797 } 4798 4799 return E1000_SUCCESS; 4800 } 4801 4802 STATIC int32_t 4803 em_read_kmrn_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t *data) 4804 { 4805 uint32_t reg_val; 4806 DEBUGFUNC("em_read_kmrn_reg"); 4807 4808 if (em_swfw_sync_acquire(hw, hw->swfw)) 4809 return -E1000_ERR_SWFW_SYNC; 4810 4811 /* Write register address */ 4812 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) & 4813 E1000_KUMCTRLSTA_OFFSET) | 4814 E1000_KUMCTRLSTA_REN; 4815 4816 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); 4817 usec_delay(2); 4818 4819 /* Read the data returned */ 4820 reg_val = E1000_READ_REG(hw, KUMCTRLSTA); 4821 *data = (uint16_t) reg_val; 4822 4823 em_swfw_sync_release(hw, hw->swfw); 4824 return E1000_SUCCESS; 4825 } 4826 4827 STATIC int32_t 4828 em_write_kmrn_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t data) 4829 { 4830 uint32_t reg_val; 4831 DEBUGFUNC("em_write_kmrn_reg"); 4832 4833 if (em_swfw_sync_acquire(hw, hw->swfw)) 4834 return -E1000_ERR_SWFW_SYNC; 4835 4836 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) & 4837 E1000_KUMCTRLSTA_OFFSET) | data; 4838 4839 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); 4840 usec_delay(2); 4841 4842 em_swfw_sync_release(hw, hw->swfw); 4843 return E1000_SUCCESS; 4844 } 4845 4846 /****************************************************************************** 4847 * Returns the PHY to the power-on reset state 4848 * 4849 * hw - Struct containing variables accessed by shared code 4850 *****************************************************************************/ 4851 int32_t 4852 em_phy_hw_reset(struct em_hw *hw) 4853 { 4854 uint32_t ctrl, ctrl_ext; 4855 uint32_t led_ctrl; 4856 int32_t ret_val; 4857 DEBUGFUNC("em_phy_hw_reset"); 4858 /* 4859 * In the case of the phy reset being blocked, it's not an error, we 4860 * simply return success without performing the reset. 4861 */ 4862 ret_val = em_check_phy_reset_block(hw); 4863 if (ret_val) 4864 return E1000_SUCCESS; 4865 4866 DEBUGOUT("Resetting Phy...\n"); 4867 4868 if (hw->mac_type > em_82543 && hw->mac_type != em_icp_xxxx) { 4869 if (em_swfw_sync_acquire(hw, hw->swfw)) { 4870 DEBUGOUT("Unable to acquire swfw sync\n"); 4871 return -E1000_ERR_SWFW_SYNC; 4872 } 4873 /* 4874 * Read the device control register and assert the 4875 * E1000_CTRL_PHY_RST bit. Then, take it out of reset. For 4876 * pre-em_82571 hardware, we delay for 10ms between the 4877 * assert and deassert. For em_82571 hardware and later, we 4878 * instead delay for 50us between and 10ms after the 4879 * deassertion. 4880 */ 4881 ctrl = E1000_READ_REG(hw, CTRL); 4882 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST); 4883 E1000_WRITE_FLUSH(hw); 4884 4885 if (hw->mac_type < em_82571) 4886 msec_delay(10); 4887 else 4888 usec_delay(100); 4889 4890 E1000_WRITE_REG(hw, CTRL, ctrl); 4891 E1000_WRITE_FLUSH(hw); 4892 4893 if (hw->mac_type >= em_82571) 4894 msec_delay_irq(10); 4895 em_swfw_sync_release(hw, hw->swfw); 4896 /* 4897 * the M88E1141_E_PHY_ID might need reset here, but nothing 4898 * proves it 4899 */ 4900 } else { 4901 /* 4902 * Read the Extended Device Control Register, assert the 4903 * PHY_RESET_DIR bit to put the PHY into reset. Then, take it 4904 * out of reset. 4905 */ 4906 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 4907 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; 4908 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; 4909 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 4910 E1000_WRITE_FLUSH(hw); 4911 msec_delay(10); 4912 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; 4913 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 4914 E1000_WRITE_FLUSH(hw); 4915 } 4916 usec_delay(150); 4917 4918 if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) { 4919 /* Configure activity LED after PHY reset */ 4920 led_ctrl = E1000_READ_REG(hw, LEDCTL); 4921 led_ctrl &= IGP_ACTIVITY_LED_MASK; 4922 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 4923 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 4924 } 4925 /* Wait for FW to finish PHY configuration. */ 4926 ret_val = em_get_phy_cfg_done(hw); 4927 if (ret_val != E1000_SUCCESS) 4928 return ret_val; 4929 em_release_software_semaphore(hw); 4930 4931 if ((hw->mac_type == em_ich8lan) && (hw->phy_type == em_phy_igp_3)) 4932 ret_val = em_init_lcd_from_nvm(hw); 4933 4934 return ret_val; 4935 } 4936 4937 /***************************************************************************** 4938 * SW-based LCD Configuration. 4939 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are 4940 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit 4941 * in NVM determines whether HW should configure LPLU and Gbe Disable. 4942 *****************************************************************************/ 4943 int32_t 4944 em_oem_bits_config_pchlan(struct em_hw *hw, boolean_t d0_state) 4945 { 4946 int32_t ret_val = E1000_SUCCESS; 4947 uint32_t mac_reg; 4948 uint16_t oem_reg; 4949 uint16_t swfw = E1000_SWFW_PHY0_SM; 4950 4951 if (hw->mac_type < em_pchlan) 4952 return ret_val; 4953 4954 ret_val = em_swfw_sync_acquire(hw, swfw); 4955 if (ret_val) 4956 return ret_val; 4957 4958 if (hw->mac_type == em_pchlan) { 4959 mac_reg = E1000_READ_REG(hw, EXTCNF_CTRL); 4960 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) 4961 goto out; 4962 } 4963 4964 mac_reg = E1000_READ_REG(hw, FEXTNVM); 4965 if (!(mac_reg & FEXTNVM_SW_CONFIG_ICH8M)) 4966 goto out; 4967 4968 mac_reg = E1000_READ_REG(hw, PHY_CTRL); 4969 4970 ret_val = em_read_phy_reg(hw, HV_OEM_BITS, &oem_reg); 4971 if (ret_val) 4972 goto out; 4973 4974 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU); 4975 4976 if (d0_state) { 4977 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE) 4978 oem_reg |= HV_OEM_BITS_GBE_DIS; 4979 4980 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU) 4981 oem_reg |= HV_OEM_BITS_LPLU; 4982 /* Restart auto-neg to activate the bits */ 4983 if (!em_check_phy_reset_block(hw)) 4984 oem_reg |= HV_OEM_BITS_RESTART_AN; 4985 4986 } else { 4987 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE | 4988 E1000_PHY_CTRL_NOND0A_GBE_DISABLE)) 4989 oem_reg |= HV_OEM_BITS_GBE_DIS; 4990 4991 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU | 4992 E1000_PHY_CTRL_NOND0A_LPLU)) 4993 oem_reg |= HV_OEM_BITS_LPLU; 4994 } 4995 4996 ret_val = em_write_phy_reg(hw, HV_OEM_BITS, oem_reg); 4997 4998 out: 4999 em_swfw_sync_release(hw, swfw); 5000 5001 return ret_val; 5002 } 5003 5004 5005 /****************************************************************************** 5006 * Resets the PHY 5007 * 5008 * hw - Struct containing variables accessed by shared code 5009 * 5010 * Sets bit 15 of the MII Control regiser 5011 *****************************************************************************/ 5012 int32_t 5013 em_phy_reset(struct em_hw *hw) 5014 { 5015 int32_t ret_val; 5016 uint16_t phy_data; 5017 DEBUGFUNC("em_phy_reset"); 5018 /* 5019 * In the case of the phy reset being blocked, it's not an error, we 5020 * simply return success without performing the reset. 5021 */ 5022 ret_val = em_check_phy_reset_block(hw); 5023 if (ret_val) 5024 return E1000_SUCCESS; 5025 5026 switch (hw->phy_type) { 5027 case em_phy_igp: 5028 case em_phy_igp_2: 5029 case em_phy_igp_3: 5030 case em_phy_ife: 5031 ret_val = em_phy_hw_reset(hw); 5032 if (ret_val) 5033 return ret_val; 5034 break; 5035 default: 5036 ret_val = em_read_phy_reg(hw, PHY_CTRL, &phy_data); 5037 if (ret_val) 5038 return ret_val; 5039 5040 phy_data |= MII_CR_RESET; 5041 ret_val = em_write_phy_reg(hw, PHY_CTRL, phy_data); 5042 if (ret_val) 5043 return ret_val; 5044 5045 usec_delay(1); 5046 break; 5047 } 5048 5049 /* Allow time for h/w to get to a quiescent state after reset */ 5050 msec_delay(10); 5051 5052 if (hw->phy_type == em_phy_igp || hw->phy_type == em_phy_igp_2) 5053 em_phy_init_script(hw); 5054 5055 if (hw->mac_type == em_pchlan) { 5056 ret_val = em_hv_phy_workarounds_ich8lan(hw); 5057 if (ret_val) 5058 return ret_val; 5059 } else if (hw->mac_type == em_pch2lan) { 5060 ret_val = em_lv_phy_workarounds_ich8lan(hw); 5061 if (ret_val) 5062 return ret_val; 5063 } 5064 5065 if (hw->mac_type >= em_pchlan) { 5066 ret_val = em_oem_bits_config_pchlan(hw, TRUE); 5067 if (ret_val) 5068 return ret_val; 5069 } 5070 5071 /* Ungate automatic PHY configuration on non-managed 82579 */ 5072 if ((hw->mac_type == em_pch2lan) && 5073 !(E1000_READ_REG(hw, FWSM) & E1000_FWSM_FW_VALID)) { 5074 msec_delay(10); 5075 em_gate_hw_phy_config_ich8lan(hw, FALSE); 5076 } 5077 5078 return E1000_SUCCESS; 5079 } 5080 5081 /****************************************************************************** 5082 * Work-around for 82566 Kumeran PCS lock loss: 5083 * On link status change (i.e. PCI reset, speed change) and link is up and 5084 * speed is gigabit- 5085 * 0) if workaround is optionally disabled do nothing 5086 * 1) wait 1ms for Kumeran link to come up 5087 * 2) check Kumeran Diagnostic register PCS lock loss bit 5088 * 3) if not set the link is locked (all is good), otherwise... 5089 * 4) reset the PHY 5090 * 5) repeat up to 10 times 5091 * Note: this is only called for IGP3 copper when speed is 1gb. 5092 * 5093 * hw - struct containing variables accessed by shared code 5094 *****************************************************************************/ 5095 STATIC int32_t 5096 em_kumeran_lock_loss_workaround(struct em_hw *hw) 5097 { 5098 int32_t ret_val; 5099 int32_t reg; 5100 int32_t cnt; 5101 uint16_t phy_data; 5102 if (hw->kmrn_lock_loss_workaround_disabled) 5103 return E1000_SUCCESS; 5104 /* 5105 * Make sure link is up before proceeding. If not just return. 5106 * Attempting this while link is negotiating fouled up link stability 5107 */ 5108 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 5109 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 5110 5111 if (phy_data & MII_SR_LINK_STATUS) { 5112 for (cnt = 0; cnt < 10; cnt++) { 5113 /* read once to clear */ 5114 ret_val = em_read_phy_reg(hw, IGP3_KMRN_DIAG, 5115 &phy_data); 5116 if (ret_val) 5117 return ret_val; 5118 /* and again to get new status */ 5119 ret_val = em_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data); 5120 if (ret_val) 5121 return ret_val; 5122 5123 /* check for PCS lock */ 5124 if (!(phy_data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) 5125 return E1000_SUCCESS; 5126 5127 /* Issue PHY reset */ 5128 em_phy_hw_reset(hw); 5129 msec_delay_irq(5); 5130 } 5131 /* Disable GigE link negotiation */ 5132 reg = E1000_READ_REG(hw, PHY_CTRL); 5133 E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE 5134 | E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 5135 5136 /* unable to acquire PCS lock */ 5137 return E1000_ERR_PHY; 5138 } 5139 return E1000_SUCCESS; 5140 } 5141 5142 /****************************************************************************** 5143 * Reads and matches the expected PHY address for known PHY IDs 5144 * 5145 * hw - Struct containing variables accessed by shared code 5146 *****************************************************************************/ 5147 STATIC int32_t 5148 em_match_gig_phy(struct em_hw *hw) 5149 { 5150 int32_t phy_init_status, ret_val; 5151 uint16_t phy_id_high, phy_id_low; 5152 boolean_t match = FALSE; 5153 DEBUGFUNC("em_match_gig_phy"); 5154 5155 ret_val = em_read_phy_reg(hw, PHY_ID1, &phy_id_high); 5156 if (ret_val) 5157 return ret_val; 5158 5159 hw->phy_id = (uint32_t) (phy_id_high << 16); 5160 usec_delay(20); 5161 ret_val = em_read_phy_reg(hw, PHY_ID2, &phy_id_low); 5162 if (ret_val) 5163 return ret_val; 5164 5165 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK); 5166 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK; 5167 5168 switch (hw->mac_type) { 5169 case em_82543: 5170 if (hw->phy_id == M88E1000_E_PHY_ID) 5171 match = TRUE; 5172 break; 5173 case em_82544: 5174 if (hw->phy_id == M88E1000_I_PHY_ID) 5175 match = TRUE; 5176 break; 5177 case em_82540: 5178 case em_82545: 5179 case em_82545_rev_3: 5180 case em_82546: 5181 case em_82546_rev_3: 5182 if (hw->phy_id == M88E1011_I_PHY_ID) 5183 match = TRUE; 5184 break; 5185 case em_82541: 5186 case em_82541_rev_2: 5187 case em_82547: 5188 case em_82547_rev_2: 5189 if (hw->phy_id == IGP01E1000_I_PHY_ID) 5190 match = TRUE; 5191 break; 5192 case em_82573: 5193 if (hw->phy_id == M88E1111_I_PHY_ID) 5194 match = TRUE; 5195 break; 5196 case em_82574: 5197 if (hw->phy_id == BME1000_E_PHY_ID) 5198 match = TRUE; 5199 break; 5200 case em_82575: 5201 if (hw->phy_id == M88E1000_E_PHY_ID) 5202 match = TRUE; 5203 if (hw->phy_id == IGP01E1000_I_PHY_ID) 5204 match = TRUE; 5205 if (hw->phy_id == IGP03E1000_E_PHY_ID) 5206 match = TRUE; 5207 break; 5208 case em_82580: 5209 case em_i210: 5210 case em_i350: 5211 if (hw->phy_id == I82580_I_PHY_ID || 5212 hw->phy_id == I210_I_PHY_ID || 5213 hw->phy_id == I347AT4_E_PHY_ID || 5214 hw->phy_id == I350_I_PHY_ID || 5215 hw->phy_id == M88E1112_E_PHY_ID || 5216 hw->phy_id == M88E1543_E_PHY_ID) { 5217 uint32_t mdic; 5218 5219 mdic = EM_READ_REG(hw, E1000_MDICNFG); 5220 mdic &= E1000_MDICNFG_PHY_MASK; 5221 hw->phy_addr = mdic >> E1000_MDICNFG_PHY_SHIFT; 5222 DEBUGOUT1("MDICNFG PHY ADDR %d", 5223 mdic >> E1000_MDICNFG_PHY_SHIFT); 5224 match = TRUE; 5225 } 5226 break; 5227 case em_80003es2lan: 5228 if (hw->phy_id == GG82563_E_PHY_ID) 5229 match = TRUE; 5230 break; 5231 case em_ich8lan: 5232 case em_ich9lan: 5233 case em_ich10lan: 5234 case em_pchlan: 5235 case em_pch2lan: 5236 if (hw->phy_id == IGP03E1000_E_PHY_ID) 5237 match = TRUE; 5238 if (hw->phy_id == IFE_E_PHY_ID) 5239 match = TRUE; 5240 if (hw->phy_id == IFE_PLUS_E_PHY_ID) 5241 match = TRUE; 5242 if (hw->phy_id == IFE_C_E_PHY_ID) 5243 match = TRUE; 5244 if (hw->phy_id == BME1000_E_PHY_ID) 5245 match = TRUE; 5246 if (hw->phy_id == I82577_E_PHY_ID) 5247 match = TRUE; 5248 if (hw->phy_id == I82578_E_PHY_ID) 5249 match = TRUE; 5250 if (hw->phy_id == I82579_E_PHY_ID) 5251 match = TRUE; 5252 break; 5253 case em_pch_lpt: 5254 if (hw->phy_id == I217_E_PHY_ID) 5255 match = TRUE; 5256 break; 5257 case em_icp_xxxx: 5258 if (hw->phy_id == M88E1141_E_PHY_ID) 5259 match = TRUE; 5260 break; 5261 default: 5262 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type); 5263 return -E1000_ERR_CONFIG; 5264 } 5265 phy_init_status = em_set_phy_type(hw); 5266 5267 if ((match) && (phy_init_status == E1000_SUCCESS)) { 5268 DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id); 5269 return E1000_SUCCESS; 5270 } 5271 DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id); 5272 return -E1000_ERR_PHY; 5273 } 5274 5275 /****************************************************************************** 5276 * Probes the expected PHY address for known PHY IDs 5277 * 5278 * hw - Struct containing variables accessed by shared code 5279 *****************************************************************************/ 5280 STATIC int32_t 5281 em_detect_gig_phy(struct em_hw *hw) 5282 { 5283 int32_t ret_val; 5284 DEBUGFUNC("em_detect_gig_phy"); 5285 5286 if (hw->phy_id != 0) 5287 return E1000_SUCCESS; 5288 5289 /* default phy address, most phys reside here, but not all (ICH10) */ 5290 if (hw->mac_type != em_icp_xxxx) 5291 hw->phy_addr = 1; 5292 else 5293 hw->phy_addr = 0; /* There is a phy at phy_addr 0 on EP80579 */ 5294 5295 /* 5296 * The 82571 firmware may still be configuring the PHY. In this 5297 * case, we cannot access the PHY until the configuration is done. 5298 * So we explicitly set the PHY values. 5299 */ 5300 if (hw->mac_type == em_82571 || 5301 hw->mac_type == em_82572) { 5302 hw->phy_id = IGP01E1000_I_PHY_ID; 5303 hw->phy_type = em_phy_igp_2; 5304 return E1000_SUCCESS; 5305 } 5306 5307 /* 5308 * Some of the fiber cards dont have a phy, so we must exit cleanly 5309 * here 5310 */ 5311 if ((hw->media_type == em_media_type_fiber) && 5312 (hw->mac_type == em_82542_rev2_0 || 5313 hw->mac_type == em_82542_rev2_1 || 5314 hw->mac_type == em_82543 || 5315 hw->mac_type == em_82574 || 5316 hw->mac_type == em_82573 || 5317 hw->mac_type == em_82574 || 5318 hw->mac_type == em_80003es2lan)) { 5319 hw->phy_type = em_phy_undefined; 5320 return E1000_SUCCESS; 5321 } 5322 5323 if ((hw->media_type == em_media_type_internal_serdes || 5324 hw->media_type == em_media_type_fiber) && 5325 hw->mac_type >= em_82575) { 5326 hw->phy_type = em_phy_undefined; 5327 return E1000_SUCCESS; 5328 } 5329 5330 /* 5331 * Up to 82543 (incl), we need reset the phy, or it might not get 5332 * detected 5333 */ 5334 if (hw->mac_type <= em_82543) { 5335 ret_val = em_phy_hw_reset(hw); 5336 if (ret_val) 5337 return ret_val; 5338 } 5339 /* 5340 * ESB-2 PHY reads require em_phy_gg82563 to be set because of a 5341 * work- around that forces PHY page 0 to be set or the reads fail. 5342 * The rest of the code in this routine uses em_read_phy_reg to read 5343 * the PHY ID. So for ESB-2 we need to have this set so our reads 5344 * won't fail. If the attached PHY is not a em_phy_gg82563, the 5345 * routines below will figure this out as well. 5346 */ 5347 if (hw->mac_type == em_80003es2lan) 5348 hw->phy_type = em_phy_gg82563; 5349 5350 /* Power on SGMII phy if it is disabled */ 5351 if (hw->mac_type == em_82580 || hw->mac_type == em_i210 || 5352 hw->mac_type == em_i350) { 5353 uint32_t ctrl_ext = EM_READ_REG(hw, E1000_CTRL_EXT); 5354 EM_WRITE_REG(hw, E1000_CTRL_EXT, 5355 ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA); 5356 delay(300); 5357 } 5358 5359 /* Read the PHY ID Registers to identify which PHY is onboard. */ 5360 for (hw->phy_addr = 1; (hw->phy_addr < 4); hw->phy_addr++) { 5361 ret_val = em_match_gig_phy(hw); 5362 if (ret_val == E1000_SUCCESS) 5363 return E1000_SUCCESS; 5364 } 5365 return -E1000_ERR_PHY; 5366 } 5367 5368 /****************************************************************************** 5369 * Resets the PHY's DSP 5370 * 5371 * hw - Struct containing variables accessed by shared code 5372 *****************************************************************************/ 5373 static int32_t 5374 em_phy_reset_dsp(struct em_hw *hw) 5375 { 5376 int32_t ret_val; 5377 DEBUGFUNC("em_phy_reset_dsp"); 5378 5379 do { 5380 if (hw->phy_type != em_phy_gg82563) { 5381 ret_val = em_write_phy_reg(hw, 29, 0x001d); 5382 if (ret_val) 5383 break; 5384 } 5385 ret_val = em_write_phy_reg(hw, 30, 0x00c1); 5386 if (ret_val) 5387 break; 5388 ret_val = em_write_phy_reg(hw, 30, 0x0000); 5389 if (ret_val) 5390 break; 5391 ret_val = E1000_SUCCESS; 5392 } while (0); 5393 5394 return ret_val; 5395 } 5396 5397 /****************************************************************************** 5398 * Sets up eeprom variables in the hw struct. Must be called after mac_type 5399 * is configured. Additionally, if this is ICH8, the flash controller GbE 5400 * registers must be mapped, or this will crash. 5401 * 5402 * hw - Struct containing variables accessed by shared code 5403 *****************************************************************************/ 5404 int32_t 5405 em_init_eeprom_params(struct em_hw *hw) 5406 { 5407 struct em_eeprom_info *eeprom = &hw->eeprom; 5408 uint32_t eecd = E1000_READ_REG(hw, EECD); 5409 int32_t ret_val = E1000_SUCCESS; 5410 uint16_t eeprom_size; 5411 DEBUGFUNC("em_init_eeprom_params"); 5412 5413 switch (hw->mac_type) { 5414 case em_82542_rev2_0: 5415 case em_82542_rev2_1: 5416 case em_82543: 5417 case em_82544: 5418 eeprom->type = em_eeprom_microwire; 5419 eeprom->word_size = 64; 5420 eeprom->opcode_bits = 3; 5421 eeprom->address_bits = 6; 5422 eeprom->delay_usec = 50; 5423 eeprom->use_eerd = FALSE; 5424 eeprom->use_eewr = FALSE; 5425 break; 5426 case em_82540: 5427 case em_82545: 5428 case em_82545_rev_3: 5429 case em_icp_xxxx: 5430 case em_82546: 5431 case em_82546_rev_3: 5432 eeprom->type = em_eeprom_microwire; 5433 eeprom->opcode_bits = 3; 5434 eeprom->delay_usec = 50; 5435 if (eecd & E1000_EECD_SIZE) { 5436 eeprom->word_size = 256; 5437 eeprom->address_bits = 8; 5438 } else { 5439 eeprom->word_size = 64; 5440 eeprom->address_bits = 6; 5441 } 5442 eeprom->use_eerd = FALSE; 5443 eeprom->use_eewr = FALSE; 5444 break; 5445 case em_82541: 5446 case em_82541_rev_2: 5447 case em_82547: 5448 case em_82547_rev_2: 5449 if (eecd & E1000_EECD_TYPE) { 5450 eeprom->type = em_eeprom_spi; 5451 eeprom->opcode_bits = 8; 5452 eeprom->delay_usec = 1; 5453 if (eecd & E1000_EECD_ADDR_BITS) { 5454 eeprom->page_size = 32; 5455 eeprom->address_bits = 16; 5456 } else { 5457 eeprom->page_size = 8; 5458 eeprom->address_bits = 8; 5459 } 5460 } else { 5461 eeprom->type = em_eeprom_microwire; 5462 eeprom->opcode_bits = 3; 5463 eeprom->delay_usec = 50; 5464 if (eecd & E1000_EECD_ADDR_BITS) { 5465 eeprom->word_size = 256; 5466 eeprom->address_bits = 8; 5467 } else { 5468 eeprom->word_size = 64; 5469 eeprom->address_bits = 6; 5470 } 5471 } 5472 eeprom->use_eerd = FALSE; 5473 eeprom->use_eewr = FALSE; 5474 break; 5475 case em_82571: 5476 case em_82572: 5477 eeprom->type = em_eeprom_spi; 5478 eeprom->opcode_bits = 8; 5479 eeprom->delay_usec = 1; 5480 if (eecd & E1000_EECD_ADDR_BITS) { 5481 eeprom->page_size = 32; 5482 eeprom->address_bits = 16; 5483 } else { 5484 eeprom->page_size = 8; 5485 eeprom->address_bits = 8; 5486 } 5487 eeprom->use_eerd = FALSE; 5488 eeprom->use_eewr = FALSE; 5489 break; 5490 case em_82573: 5491 case em_82574: 5492 case em_82575: 5493 case em_82580: 5494 case em_i210: 5495 case em_i350: 5496 eeprom->type = em_eeprom_spi; 5497 eeprom->opcode_bits = 8; 5498 eeprom->delay_usec = 1; 5499 if (eecd & E1000_EECD_ADDR_BITS) { 5500 eeprom->page_size = 32; 5501 eeprom->address_bits = 16; 5502 } else { 5503 eeprom->page_size = 8; 5504 eeprom->address_bits = 8; 5505 } 5506 eeprom->use_eerd = TRUE; 5507 eeprom->use_eewr = TRUE; 5508 if (em_is_onboard_nvm_eeprom(hw) == FALSE) { 5509 eeprom->type = em_eeprom_flash; 5510 eeprom->word_size = 2048; 5511 /* 5512 * Ensure that the Autonomous FLASH update bit is 5513 * cleared due to Flash update issue on parts which 5514 * use a FLASH for NVM. 5515 */ 5516 eecd &= ~E1000_EECD_AUPDEN; 5517 E1000_WRITE_REG(hw, EECD, eecd); 5518 } 5519 break; 5520 case em_80003es2lan: 5521 eeprom->type = em_eeprom_spi; 5522 eeprom->opcode_bits = 8; 5523 eeprom->delay_usec = 1; 5524 if (eecd & E1000_EECD_ADDR_BITS) { 5525 eeprom->page_size = 32; 5526 eeprom->address_bits = 16; 5527 } else { 5528 eeprom->page_size = 8; 5529 eeprom->address_bits = 8; 5530 } 5531 eeprom->use_eerd = TRUE; 5532 eeprom->use_eewr = FALSE; 5533 break; 5534 case em_ich8lan: 5535 case em_ich9lan: 5536 case em_ich10lan: 5537 case em_pchlan: 5538 case em_pch2lan: 5539 case em_pch_lpt: 5540 { 5541 int32_t i = 0; 5542 uint32_t flash_size = 5543 E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_GFPREG); 5544 eeprom->type = em_eeprom_ich8; 5545 eeprom->use_eerd = FALSE; 5546 eeprom->use_eewr = FALSE; 5547 eeprom->word_size = E1000_SHADOW_RAM_WORDS; 5548 /* 5549 * Zero the shadow RAM structure. But don't load it 5550 * from NVM so as to save time for driver init 5551 */ 5552 if (hw->eeprom_shadow_ram != NULL) { 5553 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 5554 hw->eeprom_shadow_ram[i].modified = 5555 FALSE; 5556 hw->eeprom_shadow_ram[i].eeprom_word = 5557 0xFFFF; 5558 } 5559 } 5560 hw->flash_base_addr = (flash_size & 5561 ICH_GFPREG_BASE_MASK) * ICH_FLASH_SECTOR_SIZE; 5562 5563 hw->flash_bank_size = ((flash_size >> 16) & 5564 ICH_GFPREG_BASE_MASK) + 1; 5565 hw->flash_bank_size -= (flash_size & 5566 ICH_GFPREG_BASE_MASK); 5567 5568 hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE; 5569 5570 hw->flash_bank_size /= 2 * sizeof(uint16_t); 5571 5572 break; 5573 } 5574 default: 5575 break; 5576 } 5577 5578 if (eeprom->type == em_eeprom_spi) { 5579 /* 5580 * eeprom_size will be an enum [0..8] that maps to eeprom 5581 * sizes 128B to 32KB (incremented by powers of 2). 5582 */ 5583 if (hw->mac_type <= em_82547_rev_2) { 5584 /* Set to default value for initial eeprom read. */ 5585 eeprom->word_size = 64; 5586 ret_val = em_read_eeprom(hw, EEPROM_CFG, 1, 5587 &eeprom_size); 5588 if (ret_val) 5589 return ret_val; 5590 eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> 5591 EEPROM_SIZE_SHIFT; 5592 /* 5593 * 256B eeprom size was not supported in earlier 5594 * hardware, so we bump eeprom_size up one to ensure 5595 * that "1" (which maps to 256B) is never the result 5596 * used in the shifting logic below. 5597 */ 5598 if (eeprom_size) 5599 eeprom_size++; 5600 } else { 5601 eeprom_size = (uint16_t) ( 5602 (eecd & E1000_EECD_SIZE_EX_MASK) >> 5603 E1000_EECD_SIZE_EX_SHIFT); 5604 } 5605 5606 /* EEPROM access above 16k is unsupported */ 5607 if (eeprom_size + EEPROM_WORD_SIZE_SHIFT > 5608 EEPROM_WORD_SIZE_SHIFT_MAX) { 5609 eeprom->word_size = 1 << EEPROM_WORD_SIZE_SHIFT_MAX; 5610 } else { 5611 eeprom->word_size = 1 << 5612 (eeprom_size + EEPROM_WORD_SIZE_SHIFT); 5613 } 5614 } 5615 return ret_val; 5616 } 5617 5618 /****************************************************************************** 5619 * Raises the EEPROM's clock input. 5620 * 5621 * hw - Struct containing variables accessed by shared code 5622 * eecd - EECD's current value 5623 *****************************************************************************/ 5624 static void 5625 em_raise_ee_clk(struct em_hw *hw, uint32_t *eecd) 5626 { 5627 /* 5628 * Raise the clock input to the EEPROM (by setting the SK bit), and 5629 * then wait <delay> microseconds. 5630 */ 5631 *eecd = *eecd | E1000_EECD_SK; 5632 E1000_WRITE_REG(hw, EECD, *eecd); 5633 E1000_WRITE_FLUSH(hw); 5634 usec_delay(hw->eeprom.delay_usec); 5635 } 5636 5637 /****************************************************************************** 5638 * Lowers the EEPROM's clock input. 5639 * 5640 * hw - Struct containing variables accessed by shared code 5641 * eecd - EECD's current value 5642 *****************************************************************************/ 5643 static void 5644 em_lower_ee_clk(struct em_hw *hw, uint32_t *eecd) 5645 { 5646 /* 5647 * Lower the clock input to the EEPROM (by clearing the SK bit), and 5648 * then wait 50 microseconds. 5649 */ 5650 *eecd = *eecd & ~E1000_EECD_SK; 5651 E1000_WRITE_REG(hw, EECD, *eecd); 5652 E1000_WRITE_FLUSH(hw); 5653 usec_delay(hw->eeprom.delay_usec); 5654 } 5655 5656 /****************************************************************************** 5657 * Shift data bits out to the EEPROM. 5658 * 5659 * hw - Struct containing variables accessed by shared code 5660 * data - data to send to the EEPROM 5661 * count - number of bits to shift out 5662 *****************************************************************************/ 5663 static void 5664 em_shift_out_ee_bits(struct em_hw *hw, uint16_t data, uint16_t count) 5665 { 5666 struct em_eeprom_info *eeprom = &hw->eeprom; 5667 uint32_t eecd; 5668 uint32_t mask; 5669 /* 5670 * We need to shift "count" bits out to the EEPROM. So, value in the 5671 * "data" parameter will be shifted out to the EEPROM one bit at a 5672 * time. In order to do this, "data" must be broken down into bits. 5673 */ 5674 mask = 0x01 << (count - 1); 5675 eecd = E1000_READ_REG(hw, EECD); 5676 if (eeprom->type == em_eeprom_microwire) { 5677 eecd &= ~E1000_EECD_DO; 5678 } else if (eeprom->type == em_eeprom_spi) { 5679 eecd |= E1000_EECD_DO; 5680 } 5681 do { 5682 /* 5683 * A "1" is shifted out to the EEPROM by setting bit "DI" to 5684 * a "1", and then raising and then lowering the clock (the 5685 * SK bit controls the clock input to the EEPROM). A "0" is 5686 * shifted out to the EEPROM by setting "DI" to "0" and then 5687 * raising and then lowering the clock. 5688 */ 5689 eecd &= ~E1000_EECD_DI; 5690 5691 if (data & mask) 5692 eecd |= E1000_EECD_DI; 5693 5694 E1000_WRITE_REG(hw, EECD, eecd); 5695 E1000_WRITE_FLUSH(hw); 5696 5697 usec_delay(eeprom->delay_usec); 5698 5699 em_raise_ee_clk(hw, &eecd); 5700 em_lower_ee_clk(hw, &eecd); 5701 5702 mask = mask >> 1; 5703 5704 } while (mask); 5705 5706 /* We leave the "DI" bit set to "0" when we leave this routine. */ 5707 eecd &= ~E1000_EECD_DI; 5708 E1000_WRITE_REG(hw, EECD, eecd); 5709 } 5710 5711 /****************************************************************************** 5712 * Shift data bits in from the EEPROM 5713 * 5714 * hw - Struct containing variables accessed by shared code 5715 *****************************************************************************/ 5716 static uint16_t 5717 em_shift_in_ee_bits(struct em_hw *hw, uint16_t count) 5718 { 5719 uint32_t eecd; 5720 uint32_t i; 5721 uint16_t data; 5722 /* 5723 * In order to read a register from the EEPROM, we need to shift 5724 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising 5725 * the clock input to the EEPROM (setting the SK bit), and then 5726 * reading the value of the "DO" bit. During this "shifting in" 5727 * process the "DI" bit should always be clear. 5728 */ 5729 5730 eecd = E1000_READ_REG(hw, EECD); 5731 5732 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 5733 data = 0; 5734 5735 for (i = 0; i < count; i++) { 5736 data = data << 1; 5737 em_raise_ee_clk(hw, &eecd); 5738 5739 eecd = E1000_READ_REG(hw, EECD); 5740 5741 eecd &= ~(E1000_EECD_DI); 5742 if (eecd & E1000_EECD_DO) 5743 data |= 1; 5744 5745 em_lower_ee_clk(hw, &eecd); 5746 } 5747 5748 return data; 5749 } 5750 /****************************************************************************** 5751 * Prepares EEPROM for access 5752 * 5753 * hw - Struct containing variables accessed by shared code 5754 * 5755 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This 5756 * function should be called before issuing a command to the EEPROM. 5757 *****************************************************************************/ 5758 static int32_t 5759 em_acquire_eeprom(struct em_hw *hw) 5760 { 5761 struct em_eeprom_info *eeprom = &hw->eeprom; 5762 uint32_t eecd, i = 0; 5763 DEBUGFUNC("em_acquire_eeprom"); 5764 5765 if (em_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM)) 5766 return -E1000_ERR_SWFW_SYNC; 5767 eecd = E1000_READ_REG(hw, EECD); 5768 5769 if ((hw->mac_type != em_82573) && (hw->mac_type != em_82574)) { 5770 /* Request EEPROM Access */ 5771 if (hw->mac_type > em_82544) { 5772 eecd |= E1000_EECD_REQ; 5773 E1000_WRITE_REG(hw, EECD, eecd); 5774 eecd = E1000_READ_REG(hw, EECD); 5775 while ((!(eecd & E1000_EECD_GNT)) && 5776 (i < E1000_EEPROM_GRANT_ATTEMPTS)) { 5777 i++; 5778 usec_delay(5); 5779 eecd = E1000_READ_REG(hw, EECD); 5780 } 5781 if (!(eecd & E1000_EECD_GNT)) { 5782 eecd &= ~E1000_EECD_REQ; 5783 E1000_WRITE_REG(hw, EECD, eecd); 5784 DEBUGOUT("Could not acquire EEPROM grant\n"); 5785 em_swfw_sync_release(hw, E1000_SWFW_EEP_SM); 5786 return -E1000_ERR_EEPROM; 5787 } 5788 } 5789 } 5790 5791 /* Setup EEPROM for Read/Write */ 5792 if (eeprom->type == em_eeprom_microwire) { 5793 /* Clear SK and DI */ 5794 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK); 5795 E1000_WRITE_REG(hw, EECD, eecd); 5796 5797 /* Set CS */ 5798 eecd |= E1000_EECD_CS; 5799 E1000_WRITE_REG(hw, EECD, eecd); 5800 } else if (eeprom->type == em_eeprom_spi) { 5801 /* Clear SK and CS */ 5802 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 5803 E1000_WRITE_REG(hw, EECD, eecd); 5804 usec_delay(1); 5805 } 5806 return E1000_SUCCESS; 5807 } 5808 5809 /****************************************************************************** 5810 * Returns EEPROM to a "standby" state 5811 * 5812 * hw - Struct containing variables accessed by shared code 5813 *****************************************************************************/ 5814 static void 5815 em_standby_eeprom(struct em_hw *hw) 5816 { 5817 struct em_eeprom_info *eeprom = &hw->eeprom; 5818 uint32_t eecd; 5819 eecd = E1000_READ_REG(hw, EECD); 5820 5821 if (eeprom->type == em_eeprom_microwire) { 5822 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 5823 E1000_WRITE_REG(hw, EECD, eecd); 5824 E1000_WRITE_FLUSH(hw); 5825 usec_delay(eeprom->delay_usec); 5826 5827 /* Clock high */ 5828 eecd |= E1000_EECD_SK; 5829 E1000_WRITE_REG(hw, EECD, eecd); 5830 E1000_WRITE_FLUSH(hw); 5831 usec_delay(eeprom->delay_usec); 5832 5833 /* Select EEPROM */ 5834 eecd |= E1000_EECD_CS; 5835 E1000_WRITE_REG(hw, EECD, eecd); 5836 E1000_WRITE_FLUSH(hw); 5837 usec_delay(eeprom->delay_usec); 5838 5839 /* Clock low */ 5840 eecd &= ~E1000_EECD_SK; 5841 E1000_WRITE_REG(hw, EECD, eecd); 5842 E1000_WRITE_FLUSH(hw); 5843 usec_delay(eeprom->delay_usec); 5844 } else if (eeprom->type == em_eeprom_spi) { 5845 /* Toggle CS to flush commands */ 5846 eecd |= E1000_EECD_CS; 5847 E1000_WRITE_REG(hw, EECD, eecd); 5848 E1000_WRITE_FLUSH(hw); 5849 usec_delay(eeprom->delay_usec); 5850 eecd &= ~E1000_EECD_CS; 5851 E1000_WRITE_REG(hw, EECD, eecd); 5852 E1000_WRITE_FLUSH(hw); 5853 usec_delay(eeprom->delay_usec); 5854 } 5855 } 5856 5857 /****************************************************************************** 5858 * Terminates a command by inverting the EEPROM's chip select pin 5859 * 5860 * hw - Struct containing variables accessed by shared code 5861 *****************************************************************************/ 5862 static void 5863 em_release_eeprom(struct em_hw *hw) 5864 { 5865 uint32_t eecd; 5866 DEBUGFUNC("em_release_eeprom"); 5867 5868 eecd = E1000_READ_REG(hw, EECD); 5869 5870 if (hw->eeprom.type == em_eeprom_spi) { 5871 eecd |= E1000_EECD_CS; /* Pull CS high */ 5872 eecd &= ~E1000_EECD_SK; /* Lower SCK */ 5873 5874 E1000_WRITE_REG(hw, EECD, eecd); 5875 5876 usec_delay(hw->eeprom.delay_usec); 5877 } else if (hw->eeprom.type == em_eeprom_microwire) { 5878 /* cleanup eeprom */ 5879 5880 /* CS on Microwire is active-high */ 5881 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); 5882 5883 E1000_WRITE_REG(hw, EECD, eecd); 5884 5885 /* Rising edge of clock */ 5886 eecd |= E1000_EECD_SK; 5887 E1000_WRITE_REG(hw, EECD, eecd); 5888 E1000_WRITE_FLUSH(hw); 5889 usec_delay(hw->eeprom.delay_usec); 5890 5891 /* Falling edge of clock */ 5892 eecd &= ~E1000_EECD_SK; 5893 E1000_WRITE_REG(hw, EECD, eecd); 5894 E1000_WRITE_FLUSH(hw); 5895 usec_delay(hw->eeprom.delay_usec); 5896 } 5897 /* Stop requesting EEPROM access */ 5898 if (hw->mac_type > em_82544) { 5899 eecd &= ~E1000_EECD_REQ; 5900 E1000_WRITE_REG(hw, EECD, eecd); 5901 } 5902 em_swfw_sync_release(hw, E1000_SWFW_EEP_SM); 5903 } 5904 5905 /****************************************************************************** 5906 * Reads a 16 bit word from the EEPROM. 5907 * 5908 * hw - Struct containing variables accessed by shared code 5909 *****************************************************************************/ 5910 STATIC int32_t 5911 em_spi_eeprom_ready(struct em_hw *hw) 5912 { 5913 uint16_t retry_count = 0; 5914 uint8_t spi_stat_reg; 5915 DEBUGFUNC("em_spi_eeprom_ready"); 5916 /* 5917 * Read "Status Register" repeatedly until the LSB is cleared. The 5918 * EEPROM will signal that the command has been completed by clearing 5919 * bit 0 of the internal status register. If it's not cleared within 5920 * 5 milliseconds, then error out. 5921 */ 5922 retry_count = 0; 5923 do { 5924 em_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI, 5925 hw->eeprom.opcode_bits); 5926 spi_stat_reg = (uint8_t) em_shift_in_ee_bits(hw, 8); 5927 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI)) 5928 break; 5929 5930 usec_delay(5); 5931 retry_count += 5; 5932 5933 em_standby_eeprom(hw); 5934 } while (retry_count < EEPROM_MAX_RETRY_SPI); 5935 /* 5936 * ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and 5937 * only 0-5mSec on 5V devices) 5938 */ 5939 if (retry_count >= EEPROM_MAX_RETRY_SPI) { 5940 DEBUGOUT("SPI EEPROM Status error\n"); 5941 return -E1000_ERR_EEPROM; 5942 } 5943 return E1000_SUCCESS; 5944 } 5945 5946 /****************************************************************************** 5947 * Reads a 16 bit word from the EEPROM. 5948 * 5949 * hw - Struct containing variables accessed by shared code 5950 * offset - offset of word in the EEPROM to read 5951 * data - word read from the EEPROM 5952 * words - number of words to read 5953 *****************************************************************************/ 5954 int32_t 5955 em_read_eeprom(struct em_hw *hw, uint16_t offset, uint16_t words, 5956 uint16_t *data) 5957 { 5958 struct em_eeprom_info *eeprom = &hw->eeprom; 5959 uint32_t i = 0; 5960 DEBUGFUNC("em_read_eeprom"); 5961 5962 /* If eeprom is not yet detected, do so now */ 5963 if (eeprom->word_size == 0) 5964 em_init_eeprom_params(hw); 5965 /* 5966 * A check for invalid values: offset too large, too many words, and 5967 * not enough words. 5968 */ 5969 if ((offset >= eeprom->word_size) || 5970 (words > eeprom->word_size - offset) || 5971 (words == 0)) { 5972 DEBUGOUT2("\"words\" parameter out of bounds. Words = %d," 5973 " size = %d\n", offset, eeprom->word_size); 5974 return -E1000_ERR_EEPROM; 5975 } 5976 /* 5977 * EEPROM's that don't use EERD to read require us to bit-bang the 5978 * SPI directly. In this case, we need to acquire the EEPROM so that 5979 * FW or other port software does not interrupt. 5980 */ 5981 if (em_is_onboard_nvm_eeprom(hw) == TRUE && 5982 hw->eeprom.use_eerd == FALSE) { 5983 /* Prepare the EEPROM for bit-bang reading */ 5984 if (em_acquire_eeprom(hw) != E1000_SUCCESS) 5985 return -E1000_ERR_EEPROM; 5986 } 5987 /* Eerd register EEPROM access requires no eeprom aquire/release */ 5988 if (eeprom->use_eerd == TRUE) 5989 return em_read_eeprom_eerd(hw, offset, words, data); 5990 5991 /* ICH EEPROM access is done via the ICH flash controller */ 5992 if (eeprom->type == em_eeprom_ich8) 5993 return em_read_eeprom_ich8(hw, offset, words, data); 5994 /* 5995 * Set up the SPI or Microwire EEPROM for bit-bang reading. We have 5996 * acquired the EEPROM at this point, so any returns should relase it 5997 */ 5998 if (eeprom->type == em_eeprom_spi) { 5999 uint16_t word_in; 6000 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI; 6001 if (em_spi_eeprom_ready(hw)) { 6002 em_release_eeprom(hw); 6003 return -E1000_ERR_EEPROM; 6004 } 6005 em_standby_eeprom(hw); 6006 /* 6007 * Some SPI eeproms use the 8th address bit embedded in the 6008 * opcode 6009 */ 6010 if ((eeprom->address_bits == 8) && (offset >= 128)) 6011 read_opcode |= EEPROM_A8_OPCODE_SPI; 6012 6013 /* Send the READ command (opcode + addr) */ 6014 em_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits); 6015 em_shift_out_ee_bits(hw, (uint16_t) (offset * 2), 6016 eeprom->address_bits); 6017 /* 6018 * Read the data. The address of the eeprom internally 6019 * increments with each byte (spi) being read, saving on the 6020 * overhead of eeprom setup and tear-down. The address 6021 * counter will roll over if reading beyond the size of the 6022 * eeprom, thus allowing the entire memory to be read 6023 * starting from any offset. 6024 */ 6025 for (i = 0; i < words; i++) { 6026 word_in = em_shift_in_ee_bits(hw, 16); 6027 data[i] = (word_in >> 8) | (word_in << 8); 6028 } 6029 } else if (eeprom->type == em_eeprom_microwire) { 6030 for (i = 0; i < words; i++) { 6031 /* Send the READ command (opcode + addr) */ 6032 em_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE, 6033 eeprom->opcode_bits); 6034 em_shift_out_ee_bits(hw, (uint16_t) (offset + i), 6035 eeprom->address_bits); 6036 /* 6037 * Read the data. For microwire, each word requires 6038 * the overhead of eeprom setup and tear-down. 6039 */ 6040 data[i] = em_shift_in_ee_bits(hw, 16); 6041 em_standby_eeprom(hw); 6042 } 6043 } 6044 /* End this read operation */ 6045 em_release_eeprom(hw); 6046 6047 return E1000_SUCCESS; 6048 } 6049 6050 /****************************************************************************** 6051 * Reads a 16 bit word from the EEPROM using the EERD register. 6052 * 6053 * hw - Struct containing variables accessed by shared code 6054 * offset - offset of word in the EEPROM to read 6055 * data - word read from the EEPROM 6056 * words - number of words to read 6057 *****************************************************************************/ 6058 STATIC int32_t 6059 em_read_eeprom_eerd(struct em_hw *hw, uint16_t offset, uint16_t words, 6060 uint16_t *data) 6061 { 6062 uint32_t i, eerd = 0; 6063 int32_t error = 0; 6064 for (i = 0; i < words; i++) { 6065 eerd = ((offset + i) << E1000_EEPROM_RW_ADDR_SHIFT) + 6066 E1000_EEPROM_RW_REG_START; 6067 6068 E1000_WRITE_REG(hw, EERD, eerd); 6069 error = em_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ); 6070 6071 if (error) { 6072 break; 6073 } 6074 data[i] = (E1000_READ_REG(hw, EERD) >> 6075 E1000_EEPROM_RW_REG_DATA); 6076 6077 } 6078 6079 return error; 6080 } 6081 6082 /****************************************************************************** 6083 * Writes a 16 bit word from the EEPROM using the EEWR register. 6084 * 6085 * hw - Struct containing variables accessed by shared code 6086 * offset - offset of word in the EEPROM to read 6087 * data - word read from the EEPROM 6088 * words - number of words to read 6089 *****************************************************************************/ 6090 STATIC int32_t 6091 em_write_eeprom_eewr(struct em_hw *hw, uint16_t offset, uint16_t words, 6092 uint16_t *data) 6093 { 6094 uint32_t register_value = 0; 6095 uint32_t i = 0; 6096 int32_t error = 0; 6097 if (em_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM)) 6098 return -E1000_ERR_SWFW_SYNC; 6099 6100 for (i = 0; i < words; i++) { 6101 register_value = (data[i] << E1000_EEPROM_RW_REG_DATA) | 6102 ((offset + i) << E1000_EEPROM_RW_ADDR_SHIFT) | 6103 E1000_EEPROM_RW_REG_START; 6104 6105 error = em_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE); 6106 if (error) { 6107 break; 6108 } 6109 E1000_WRITE_REG(hw, EEWR, register_value); 6110 6111 error = em_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE); 6112 6113 if (error) { 6114 break; 6115 } 6116 } 6117 6118 em_swfw_sync_release(hw, E1000_SWFW_EEP_SM); 6119 return error; 6120 } 6121 6122 /****************************************************************************** 6123 * Polls the status bit (bit 1) of the EERD to determine when the read is done. 6124 * 6125 * hw - Struct containing variables accessed by shared code 6126 *****************************************************************************/ 6127 STATIC int32_t 6128 em_poll_eerd_eewr_done(struct em_hw *hw, int eerd) 6129 { 6130 uint32_t attempts = 100000; 6131 uint32_t i, reg = 0; 6132 int32_t done = E1000_ERR_EEPROM; 6133 for (i = 0; i < attempts; i++) { 6134 if (eerd == E1000_EEPROM_POLL_READ) 6135 reg = E1000_READ_REG(hw, EERD); 6136 else 6137 reg = E1000_READ_REG(hw, EEWR); 6138 6139 if (reg & E1000_EEPROM_RW_REG_DONE) { 6140 done = E1000_SUCCESS; 6141 break; 6142 } 6143 usec_delay(5); 6144 } 6145 6146 return done; 6147 } 6148 6149 /****************************************************************************** 6150 * Description: Determines if the onboard NVM is FLASH or EEPROM. 6151 * 6152 * hw - Struct containing variables accessed by shared code 6153 *****************************************************************************/ 6154 STATIC boolean_t 6155 em_is_onboard_nvm_eeprom(struct em_hw *hw) 6156 { 6157 uint32_t eecd = 0; 6158 DEBUGFUNC("em_is_onboard_nvm_eeprom"); 6159 6160 if (IS_ICH8(hw->mac_type)) 6161 return FALSE; 6162 6163 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) { 6164 eecd = E1000_READ_REG(hw, EECD); 6165 6166 /* Isolate bits 15 & 16 */ 6167 eecd = ((eecd >> 15) & 0x03); 6168 6169 /* If both bits are set, device is Flash type */ 6170 if (eecd == 0x03) { 6171 return FALSE; 6172 } 6173 } 6174 return TRUE; 6175 } 6176 6177 /****************************************************************************** 6178 * Verifies that the EEPROM has a valid checksum 6179 * 6180 * hw - Struct containing variables accessed by shared code 6181 * 6182 * Reads the first 64 16 bit words of the EEPROM and sums the values read. 6183 * If the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is 6184 * valid. 6185 *****************************************************************************/ 6186 int32_t 6187 em_validate_eeprom_checksum(struct em_hw *hw) 6188 { 6189 uint16_t checksum = 0; 6190 uint16_t i, eeprom_data; 6191 uint16_t checksum_reg; 6192 DEBUGFUNC("em_validate_eeprom_checksum"); 6193 6194 checksum_reg = hw->mac_type != em_icp_xxxx ? 6195 EEPROM_CHECKSUM_REG : 6196 EEPROM_CHECKSUM_REG_ICP_xxxx; 6197 6198 if (((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) && 6199 (em_is_onboard_nvm_eeprom(hw) == FALSE)) { 6200 /* 6201 * Check bit 4 of word 10h. If it is 0, firmware is done 6202 * updating 10h-12h. Checksum may need to be fixed. 6203 */ 6204 em_read_eeprom(hw, 0x10, 1, &eeprom_data); 6205 if ((eeprom_data & 0x10) == 0) { 6206 /* 6207 * Read 0x23 and check bit 15. This bit is a 1 when 6208 * the checksum has already been fixed. If the 6209 * checksum is still wrong and this bit is a 1, we 6210 * need to return bad checksum. Otherwise, we need 6211 * to set this bit to a 1 and update the checksum. 6212 */ 6213 em_read_eeprom(hw, 0x23, 1, &eeprom_data); 6214 if ((eeprom_data & 0x8000) == 0) { 6215 eeprom_data |= 0x8000; 6216 em_write_eeprom(hw, 0x23, 1, &eeprom_data); 6217 em_update_eeprom_checksum(hw); 6218 } 6219 } 6220 } 6221 if (IS_ICH8(hw->mac_type)) { 6222 uint16_t word; 6223 uint16_t valid_csum_mask; 6224 6225 /* 6226 * Drivers must allocate the shadow ram structure for the 6227 * EEPROM checksum to be updated. Otherwise, this bit as 6228 * well as the checksum must both be set correctly for this 6229 * validation to pass. 6230 */ 6231 switch (hw->mac_type) { 6232 case em_pch_lpt: 6233 word = EEPROM_COMPAT; 6234 valid_csum_mask = EEPROM_COMPAT_VALID_CSUM; 6235 break; 6236 default: 6237 word = EEPROM_FUTURE_INIT_WORD1; 6238 valid_csum_mask = EEPROM_FUTURE_INIT_WORD1_VALID_CSUM; 6239 break; 6240 } 6241 em_read_eeprom(hw, word, 1, &eeprom_data); 6242 if ((eeprom_data & valid_csum_mask) == 0) { 6243 eeprom_data |= valid_csum_mask; 6244 em_write_eeprom(hw, word, 1, &eeprom_data); 6245 em_update_eeprom_checksum(hw); 6246 } 6247 } 6248 for (i = 0; i < (checksum_reg + 1); i++) { 6249 if (em_read_eeprom(hw, i, 1, &eeprom_data) < 0) { 6250 DEBUGOUT("EEPROM Read Error\n"); 6251 return -E1000_ERR_EEPROM; 6252 } 6253 checksum += eeprom_data; 6254 } 6255 6256 if (checksum == (uint16_t) EEPROM_SUM) 6257 return E1000_SUCCESS; 6258 else { 6259 DEBUGOUT("EEPROM Checksum Invalid\n"); 6260 return -E1000_ERR_EEPROM; 6261 } 6262 } 6263 6264 /****************************************************************************** 6265 * Calculates the EEPROM checksum and writes it to the EEPROM 6266 * 6267 * hw - Struct containing variables accessed by shared code 6268 * 6269 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA. 6270 * Writes the difference to word offset 63 of the EEPROM. 6271 *****************************************************************************/ 6272 int32_t 6273 em_update_eeprom_checksum(struct em_hw *hw) 6274 { 6275 uint32_t ctrl_ext; 6276 uint16_t checksum = 0; 6277 uint16_t i, eeprom_data; 6278 DEBUGFUNC("em_update_eeprom_checksum"); 6279 6280 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) { 6281 if (em_read_eeprom(hw, i, 1, &eeprom_data) < 0) { 6282 DEBUGOUT("EEPROM Read Error\n"); 6283 return -E1000_ERR_EEPROM; 6284 } 6285 checksum += eeprom_data; 6286 } 6287 checksum = (uint16_t) EEPROM_SUM - checksum; 6288 if (em_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) { 6289 DEBUGOUT("EEPROM Write Error\n"); 6290 return -E1000_ERR_EEPROM; 6291 } else if (hw->eeprom.type == em_eeprom_flash) { 6292 em_commit_shadow_ram(hw); 6293 } else if (hw->eeprom.type == em_eeprom_ich8) { 6294 em_commit_shadow_ram(hw); 6295 /* 6296 * Reload the EEPROM, or else modifications will not appear 6297 * until after next adapter reset. 6298 */ 6299 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 6300 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 6301 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 6302 msec_delay(10); 6303 } 6304 return E1000_SUCCESS; 6305 } 6306 6307 /****************************************************************************** 6308 * Parent function for writing words to the different EEPROM types. 6309 * 6310 * hw - Struct containing variables accessed by shared code 6311 * offset - offset within the EEPROM to be written to 6312 * words - number of words to write 6313 * data - 16 bit word to be written to the EEPROM 6314 * 6315 * If em_update_eeprom_checksum is not called after this function, the 6316 * EEPROM will most likely contain an invalid checksum. 6317 *****************************************************************************/ 6318 int32_t 6319 em_write_eeprom(struct em_hw *hw, uint16_t offset, uint16_t words, 6320 uint16_t *data) 6321 { 6322 struct em_eeprom_info *eeprom = &hw->eeprom; 6323 int32_t status = 0; 6324 DEBUGFUNC("em_write_eeprom"); 6325 6326 /* If eeprom is not yet detected, do so now */ 6327 if (eeprom->word_size == 0) 6328 em_init_eeprom_params(hw); 6329 /* 6330 * A check for invalid values: offset too large, too many words, and 6331 * not enough words. 6332 */ 6333 if ((offset >= eeprom->word_size) || 6334 (words > eeprom->word_size - offset) || 6335 (words == 0)) { 6336 DEBUGOUT("\"words\" parameter out of bounds\n"); 6337 return -E1000_ERR_EEPROM; 6338 } 6339 /* 82573/4 writes only through eewr */ 6340 if (eeprom->use_eewr == TRUE) 6341 return em_write_eeprom_eewr(hw, offset, words, data); 6342 6343 if (eeprom->type == em_eeprom_ich8) 6344 return em_write_eeprom_ich8(hw, offset, words, data); 6345 6346 /* Prepare the EEPROM for writing */ 6347 if (em_acquire_eeprom(hw) != E1000_SUCCESS) 6348 return -E1000_ERR_EEPROM; 6349 6350 if (eeprom->type == em_eeprom_microwire) { 6351 status = em_write_eeprom_microwire(hw, offset, words, data); 6352 } else { 6353 status = em_write_eeprom_spi(hw, offset, words, data); 6354 msec_delay(10); 6355 } 6356 6357 /* Done with writing */ 6358 em_release_eeprom(hw); 6359 6360 return status; 6361 } 6362 6363 /****************************************************************************** 6364 * Writes a 16 bit word to a given offset in an SPI EEPROM. 6365 * 6366 * hw - Struct containing variables accessed by shared code 6367 * offset - offset within the EEPROM to be written to 6368 * words - number of words to write 6369 * data - pointer to array of 8 bit words to be written to the EEPROM 6370 * 6371 *****************************************************************************/ 6372 STATIC int32_t 6373 em_write_eeprom_spi(struct em_hw *hw, uint16_t offset, uint16_t words, 6374 uint16_t *data) 6375 { 6376 struct em_eeprom_info *eeprom = &hw->eeprom; 6377 uint16_t widx = 0; 6378 DEBUGFUNC("em_write_eeprom_spi"); 6379 6380 while (widx < words) { 6381 uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI; 6382 if (em_spi_eeprom_ready(hw)) 6383 return -E1000_ERR_EEPROM; 6384 6385 em_standby_eeprom(hw); 6386 6387 /* Send the WRITE ENABLE command (8 bit opcode ) */ 6388 em_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI, 6389 eeprom->opcode_bits); 6390 6391 em_standby_eeprom(hw); 6392 /* 6393 * Some SPI eeproms use the 8th address bit embedded in the 6394 * opcode 6395 */ 6396 if ((eeprom->address_bits == 8) && (offset >= 128)) 6397 write_opcode |= EEPROM_A8_OPCODE_SPI; 6398 6399 /* Send the Write command (8-bit opcode + addr) */ 6400 em_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits); 6401 6402 em_shift_out_ee_bits(hw, (uint16_t) ((offset + widx) * 2), 6403 eeprom->address_bits); 6404 6405 /* Send the data */ 6406 /* 6407 * Loop to allow for up to whole page write (32 bytes) of 6408 * eeprom 6409 */ 6410 while (widx < words) { 6411 uint16_t word_out = data[widx]; 6412 word_out = (word_out >> 8) | (word_out << 8); 6413 em_shift_out_ee_bits(hw, word_out, 16); 6414 widx++; 6415 /* 6416 * Some larger eeprom sizes are capable of a 32-byte 6417 * PAGE WRITE operation, while the smaller eeproms 6418 * are capable of an 8-byte PAGE WRITE operation. 6419 * Break the inner loop to pass new address 6420 */ 6421 if ((((offset + widx) * 2) % eeprom->page_size) == 0) { 6422 em_standby_eeprom(hw); 6423 break; 6424 } 6425 } 6426 } 6427 6428 return E1000_SUCCESS; 6429 } 6430 6431 /****************************************************************************** 6432 * Writes a 16 bit word to a given offset in a Microwire EEPROM. 6433 * 6434 * hw - Struct containing variables accessed by shared code 6435 * offset - offset within the EEPROM to be written to 6436 * words - number of words to write 6437 * data - pointer to array of 16 bit words to be written to the EEPROM 6438 * 6439 *****************************************************************************/ 6440 STATIC int32_t 6441 em_write_eeprom_microwire(struct em_hw *hw, uint16_t offset, uint16_t words, 6442 uint16_t *data) 6443 { 6444 struct em_eeprom_info *eeprom = &hw->eeprom; 6445 uint32_t eecd; 6446 uint16_t words_written = 0; 6447 uint16_t i = 0; 6448 DEBUGFUNC("em_write_eeprom_microwire"); 6449 /* 6450 * Send the write enable command to the EEPROM (3-bit opcode plus 6451 * 6/8-bit dummy address beginning with 11). It's less work to 6452 * include the 11 of the dummy address as part of the opcode than it 6453 * is to shift it over the correct number of bits for the address. 6454 * This puts the EEPROM into write/erase mode. 6455 */ 6456 em_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE, 6457 (uint16_t) (eeprom->opcode_bits + 2)); 6458 6459 em_shift_out_ee_bits(hw, 0, (uint16_t) (eeprom->address_bits - 2)); 6460 6461 /* Prepare the EEPROM */ 6462 em_standby_eeprom(hw); 6463 6464 while (words_written < words) { 6465 /* Send the Write command (3-bit opcode + addr) */ 6466 em_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE, 6467 eeprom->opcode_bits); 6468 6469 em_shift_out_ee_bits(hw, (uint16_t) (offset + words_written), 6470 eeprom->address_bits); 6471 6472 /* Send the data */ 6473 em_shift_out_ee_bits(hw, data[words_written], 16); 6474 /* 6475 * Toggle the CS line. This in effect tells the EEPROM to 6476 * execute the previous command. 6477 */ 6478 em_standby_eeprom(hw); 6479 /* 6480 * Read DO repeatedly until it is high (equal to '1'). The 6481 * EEPROM will signal that the command has been completed by 6482 * raising the DO signal. If DO does not go high in 10 6483 * milliseconds, then error out. 6484 */ 6485 for (i = 0; i < 200; i++) { 6486 eecd = E1000_READ_REG(hw, EECD); 6487 if (eecd & E1000_EECD_DO) 6488 break; 6489 usec_delay(50); 6490 } 6491 if (i == 200) { 6492 DEBUGOUT("EEPROM Write did not complete\n"); 6493 return -E1000_ERR_EEPROM; 6494 } 6495 /* Recover from write */ 6496 em_standby_eeprom(hw); 6497 6498 words_written++; 6499 } 6500 /* 6501 * Send the write disable command to the EEPROM (3-bit opcode plus 6502 * 6/8-bit dummy address beginning with 10). It's less work to 6503 * include the 10 of the dummy address as part of the opcode than it 6504 * is to shift it over the correct number of bits for the address. 6505 * This takes the EEPROM out of write/erase mode. 6506 */ 6507 em_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE, 6508 (uint16_t) (eeprom->opcode_bits + 2)); 6509 6510 em_shift_out_ee_bits(hw, 0, (uint16_t) (eeprom->address_bits - 2)); 6511 6512 return E1000_SUCCESS; 6513 } 6514 6515 /****************************************************************************** 6516 * Flushes the cached eeprom to NVM. This is done by saving the modified values 6517 * in the eeprom cache and the non modified values in the currently active bank 6518 * to the new bank. 6519 * 6520 * hw - Struct containing variables accessed by shared code 6521 * offset - offset of word in the EEPROM to read 6522 * data - word read from the EEPROM 6523 * words - number of words to read 6524 *****************************************************************************/ 6525 STATIC int32_t 6526 em_commit_shadow_ram(struct em_hw *hw) 6527 { 6528 uint32_t attempts = 100000; 6529 uint32_t eecd = 0; 6530 uint32_t flop = 0; 6531 uint32_t i = 0; 6532 int32_t error = E1000_SUCCESS; 6533 uint32_t old_bank_offset = 0; 6534 uint32_t new_bank_offset = 0; 6535 uint8_t low_byte = 0; 6536 uint8_t high_byte = 0; 6537 boolean_t sector_write_failed = FALSE; 6538 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) { 6539 /* 6540 * The flop register will be used to determine if flash type 6541 * is STM 6542 */ 6543 flop = E1000_READ_REG(hw, FLOP); 6544 for (i = 0; i < attempts; i++) { 6545 eecd = E1000_READ_REG(hw, EECD); 6546 if ((eecd & E1000_EECD_FLUPD) == 0) { 6547 break; 6548 } 6549 usec_delay(5); 6550 } 6551 6552 if (i == attempts) { 6553 return -E1000_ERR_EEPROM; 6554 } 6555 /* 6556 * If STM opcode located in bits 15:8 of flop, reset firmware 6557 */ 6558 if ((flop & 0xFF00) == E1000_STM_OPCODE) { 6559 E1000_WRITE_REG(hw, HICR, E1000_HICR_FW_RESET); 6560 } 6561 /* Perform the flash update */ 6562 E1000_WRITE_REG(hw, EECD, eecd | E1000_EECD_FLUPD); 6563 6564 for (i = 0; i < attempts; i++) { 6565 eecd = E1000_READ_REG(hw, EECD); 6566 if ((eecd & E1000_EECD_FLUPD) == 0) { 6567 break; 6568 } 6569 usec_delay(5); 6570 } 6571 6572 if (i == attempts) { 6573 return -E1000_ERR_EEPROM; 6574 } 6575 } 6576 if ((hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) && 6577 hw->eeprom_shadow_ram != NULL) { 6578 /* 6579 * We're writing to the opposite bank so if we're on bank 1, 6580 * write to bank 0 etc. We also need to erase the segment 6581 * that is going to be written 6582 */ 6583 if (!(E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL)) { 6584 new_bank_offset = hw->flash_bank_size * 2; 6585 old_bank_offset = 0; 6586 em_erase_ich8_4k_segment(hw, 1); 6587 } else { 6588 old_bank_offset = hw->flash_bank_size * 2; 6589 new_bank_offset = 0; 6590 em_erase_ich8_4k_segment(hw, 0); 6591 } 6592 6593 sector_write_failed = FALSE; 6594 /* 6595 * Loop for every byte in the shadow RAM, which is in units 6596 * of words. 6597 */ 6598 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 6599 /* 6600 * Determine whether to write the value stored in the 6601 * other NVM bank or a modified value stored in the 6602 * shadow RAM 6603 */ 6604 if (hw->eeprom_shadow_ram[i].modified == TRUE) { 6605 low_byte = (uint8_t) 6606 hw->eeprom_shadow_ram[i].eeprom_word; 6607 usec_delay(100); 6608 error = em_verify_write_ich8_byte(hw, 6609 (i << 1) + new_bank_offset, low_byte); 6610 6611 if (error != E1000_SUCCESS) 6612 sector_write_failed = TRUE; 6613 else { 6614 high_byte = (uint8_t) 6615 (hw->eeprom_shadow_ram 6616 [i].eeprom_word >> 8); 6617 usec_delay(100); 6618 } 6619 } else { 6620 em_read_ich8_byte(hw, (i << 1) + 6621 old_bank_offset, &low_byte); 6622 usec_delay(100); 6623 error = em_verify_write_ich8_byte(hw, 6624 (i << 1) + new_bank_offset, low_byte); 6625 6626 if (error != E1000_SUCCESS) 6627 sector_write_failed = TRUE; 6628 else { 6629 em_read_ich8_byte(hw, (i << 1) + 6630 old_bank_offset + 1, &high_byte); 6631 usec_delay(100); 6632 } 6633 } 6634 /* 6635 * If the write of the low byte was successful, go 6636 * ahread and write the high byte while checking to 6637 * make sure that if it is the signature byte, then 6638 * it is handled properly 6639 */ 6640 if (sector_write_failed == FALSE) { 6641 /* 6642 * If the word is 0x13, then make sure the 6643 * signature bits (15:14) are 11b until the 6644 * commit has completed. This will allow us 6645 * to write 10b which indicates the signature 6646 * is valid. We want to do this after the 6647 * write has completed so that we don't mark 6648 * the segment valid while the write is still 6649 * in progress 6650 */ 6651 if (i == E1000_ICH_NVM_SIG_WORD) 6652 high_byte = E1000_ICH_NVM_VALID_SIG_MASK | 6653 high_byte; 6654 6655 error = em_verify_write_ich8_byte(hw, (i << 1) 6656 + new_bank_offset + 1, high_byte); 6657 if (error != E1000_SUCCESS) 6658 sector_write_failed = TRUE; 6659 6660 } else { 6661 /* 6662 * If the write failed then break from the 6663 * loop and return an error 6664 */ 6665 break; 6666 } 6667 } 6668 /* 6669 * Don't bother writing the segment valid bits if sector 6670 * programming failed. 6671 */ 6672 if (sector_write_failed == FALSE) { 6673 /* 6674 * Finally validate the new segment by setting bit 6675 * 15:14 to 10b in word 0x13 , this can be done 6676 * without an erase as well since these bits are 11 6677 * to start with and we need to change bit 14 to 0b 6678 */ 6679 em_read_ich8_byte(hw, E1000_ICH_NVM_SIG_WORD * 2 + 1 + 6680 new_bank_offset, &high_byte); 6681 high_byte &= 0xBF; 6682 error = em_verify_write_ich8_byte(hw, 6683 E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset, 6684 high_byte); 6685 /* 6686 * And invalidate the previously valid segment by 6687 * setting its signature word (0x13) high_byte to 0b. 6688 * This can be done without an erase because flash 6689 * erase sets all bits to 1's. We can write 1's to 6690 * 0's without an erase 6691 */ 6692 if (error == E1000_SUCCESS) { 6693 error = em_verify_write_ich8_byte(hw, 6694 E1000_ICH_NVM_SIG_WORD * 2 + 1 + 6695 old_bank_offset, 0); 6696 } 6697 /* Clear the now not used entry in the cache */ 6698 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 6699 hw->eeprom_shadow_ram[i].modified = FALSE; 6700 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF; 6701 } 6702 } 6703 } 6704 return error; 6705 } 6706 6707 /****************************************************************************** 6708 * Reads the adapter's part number from the EEPROM 6709 * 6710 * hw - Struct containing variables accessed by shared code 6711 * part_num - Adapter's part number 6712 *****************************************************************************/ 6713 int32_t 6714 em_read_part_num(struct em_hw *hw, uint32_t *part_num) 6715 { 6716 uint16_t offset = EEPROM_PBA_BYTE_1; 6717 uint16_t eeprom_data; 6718 DEBUGFUNC("em_read_part_num"); 6719 6720 /* Get word 0 from EEPROM */ 6721 if (em_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { 6722 DEBUGOUT("EEPROM Read Error\n"); 6723 return -E1000_ERR_EEPROM; 6724 } 6725 /* Save word 0 in upper half of part_num */ 6726 *part_num = (uint32_t) (eeprom_data << 16); 6727 6728 /* Get word 1 from EEPROM */ 6729 if (em_read_eeprom(hw, ++offset, 1, &eeprom_data) < 0) { 6730 DEBUGOUT("EEPROM Read Error\n"); 6731 return -E1000_ERR_EEPROM; 6732 } 6733 /* Save word 1 in lower half of part_num */ 6734 *part_num |= eeprom_data; 6735 6736 return E1000_SUCCESS; 6737 } 6738 6739 /****************************************************************************** 6740 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the 6741 * second function of dual function devices 6742 * 6743 * hw - Struct containing variables accessed by shared code 6744 *****************************************************************************/ 6745 int32_t 6746 em_read_mac_addr(struct em_hw *hw) 6747 { 6748 uint16_t offset; 6749 uint16_t eeprom_data, i; 6750 uint16_t ia_base_addr = 0; 6751 DEBUGFUNC("em_read_mac_addr"); 6752 6753 if (hw->mac_type == em_icp_xxxx) { 6754 ia_base_addr = (uint16_t) 6755 EEPROM_IA_START_ICP_xxxx(hw->icp_xxxx_port_num); 6756 } else if (hw->mac_type == em_82580 || hw->mac_type == em_i350) { 6757 ia_base_addr = NVM_82580_LAN_FUNC_OFFSET(hw->bus_func); 6758 } 6759 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) { 6760 offset = i >> 1; 6761 if (em_read_eeprom(hw, offset + ia_base_addr, 1, &eeprom_data) 6762 < 0) { 6763 DEBUGOUT("EEPROM Read Error\n"); 6764 return -E1000_ERR_EEPROM; 6765 } 6766 hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF); 6767 hw->perm_mac_addr[i + 1] = (uint8_t) (eeprom_data >> 8); 6768 } 6769 6770 switch (hw->mac_type) { 6771 default: 6772 break; 6773 case em_82546: 6774 case em_82546_rev_3: 6775 case em_82571: 6776 case em_82575: 6777 case em_80003es2lan: 6778 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) 6779 hw->perm_mac_addr[5] ^= 0x01; 6780 break; 6781 } 6782 6783 for (i = 0; i < NODE_ADDRESS_SIZE; i++) 6784 hw->mac_addr[i] = hw->perm_mac_addr[i]; 6785 return E1000_SUCCESS; 6786 } 6787 6788 /****************************************************************************** 6789 * Initializes receive address filters. 6790 * 6791 * hw - Struct containing variables accessed by shared code 6792 * 6793 * Places the MAC address in receive address register 0 and clears the rest 6794 * of the receive addresss registers. Clears the multicast table. Assumes 6795 * the receiver is in reset when the routine is called. 6796 *****************************************************************************/ 6797 STATIC void 6798 em_init_rx_addrs(struct em_hw *hw) 6799 { 6800 uint32_t i; 6801 uint32_t rar_num; 6802 DEBUGFUNC("em_init_rx_addrs"); 6803 6804 /* Setup the receive address. */ 6805 DEBUGOUT("Programming MAC Address into RAR[0]\n"); 6806 6807 em_rar_set(hw, hw->mac_addr, 0); 6808 6809 rar_num = E1000_RAR_ENTRIES; 6810 /* 6811 * Reserve a spot for the Locally Administered Address to work around 6812 * an 82571 issue in which a reset on one port will reload the MAC on 6813 * the other port. 6814 */ 6815 if ((hw->mac_type == em_82571) && (hw->laa_is_present == TRUE)) 6816 rar_num -= 1; 6817 if (IS_ICH8(hw->mac_type)) 6818 rar_num = E1000_RAR_ENTRIES_ICH8LAN; 6819 if (hw->mac_type == em_ich8lan) 6820 rar_num -= 1; 6821 if (hw->mac_type == em_82580) 6822 rar_num = E1000_RAR_ENTRIES_82580; 6823 if (hw->mac_type == em_i210) 6824 rar_num = E1000_RAR_ENTRIES_82575; 6825 if (hw->mac_type == em_i350) 6826 rar_num = E1000_RAR_ENTRIES_I350; 6827 6828 /* Zero out the other 15 receive addresses. */ 6829 DEBUGOUT("Clearing RAR[1-15]\n"); 6830 for (i = 1; i < rar_num; i++) { 6831 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 6832 E1000_WRITE_FLUSH(hw); 6833 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 6834 E1000_WRITE_FLUSH(hw); 6835 } 6836 } 6837 6838 /****************************************************************************** 6839 * Updates the MAC's list of multicast addresses. 6840 * 6841 * hw - Struct containing variables accessed by shared code 6842 * mc_addr_list - the list of new multicast addresses 6843 * mc_addr_count - number of addresses 6844 * pad - number of bytes between addresses in the list 6845 * rar_used_count - offset where to start adding mc addresses into the RAR's 6846 * 6847 * The given list replaces any existing list. Clears the last 15 receive 6848 * address registers and the multicast table. Uses receive address registers 6849 * for the first 15 multicast addresses, and hashes the rest into the 6850 * multicast table. 6851 *****************************************************************************/ 6852 void 6853 em_mc_addr_list_update(struct em_hw *hw, uint8_t *mc_addr_list, 6854 uint32_t mc_addr_count, uint32_t pad, uint32_t rar_used_count) 6855 { 6856 uint32_t hash_value; 6857 uint32_t i; 6858 uint32_t num_rar_entry; 6859 uint32_t num_mta_entry; 6860 DEBUGFUNC("em_mc_addr_list_update"); 6861 /* 6862 * Set the new number of MC addresses that we are being requested to 6863 * use. 6864 */ 6865 hw->num_mc_addrs = mc_addr_count; 6866 6867 /* Clear RAR[1-15] */ 6868 DEBUGOUT(" Clearing RAR[1-15]\n"); 6869 num_rar_entry = E1000_RAR_ENTRIES; 6870 if (IS_ICH8(hw->mac_type)) 6871 num_rar_entry = E1000_RAR_ENTRIES_ICH8LAN; 6872 if (hw->mac_type == em_ich8lan) 6873 num_rar_entry -= 1; 6874 /* 6875 * Reserve a spot for the Locally Administered Address to work around 6876 * an 82571 issue in which a reset on one port will reload the MAC on 6877 * the other port. 6878 */ 6879 if ((hw->mac_type == em_82571) && (hw->laa_is_present == TRUE)) 6880 num_rar_entry -= 1; 6881 6882 for (i = rar_used_count; i < num_rar_entry; i++) { 6883 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 6884 E1000_WRITE_FLUSH(hw); 6885 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 6886 E1000_WRITE_FLUSH(hw); 6887 } 6888 6889 /* Clear the MTA */ 6890 DEBUGOUT(" Clearing MTA\n"); 6891 num_mta_entry = E1000_NUM_MTA_REGISTERS; 6892 if (IS_ICH8(hw->mac_type)) 6893 num_mta_entry = E1000_NUM_MTA_REGISTERS_ICH8LAN; 6894 6895 for (i = 0; i < num_mta_entry; i++) { 6896 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 6897 E1000_WRITE_FLUSH(hw); 6898 } 6899 6900 /* Add the new addresses */ 6901 for (i = 0; i < mc_addr_count; i++) { 6902 DEBUGOUT(" Adding the multicast addresses:\n"); 6903 DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i, 6904 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad)], 6905 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 1], 6906 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 2], 6907 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 3], 6908 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 4], 6909 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 5]); 6910 6911 hash_value = em_hash_mc_addr(hw, mc_addr_list + 6912 (i * (ETH_LENGTH_OF_ADDRESS + pad))); 6913 6914 DEBUGOUT1(" Hash value = 0x%03X\n", hash_value); 6915 /* 6916 * Place this multicast address in the RAR if there is room, * 6917 * else put it in the MTA 6918 */ 6919 if (rar_used_count < num_rar_entry) { 6920 em_rar_set(hw, mc_addr_list + 6921 (i * (ETH_LENGTH_OF_ADDRESS + pad)), 6922 rar_used_count); 6923 rar_used_count++; 6924 } else { 6925 em_mta_set(hw, hash_value); 6926 } 6927 } 6928 DEBUGOUT("MC Update Complete\n"); 6929 } 6930 6931 /****************************************************************************** 6932 * Hashes an address to determine its location in the multicast table 6933 * 6934 * hw - Struct containing variables accessed by shared code 6935 * mc_addr - the multicast address to hash 6936 *****************************************************************************/ 6937 uint32_t 6938 em_hash_mc_addr(struct em_hw *hw, uint8_t *mc_addr) 6939 { 6940 uint32_t hash_value = 0; 6941 /* 6942 * The portion of the address that is used for the hash table is 6943 * determined by the mc_filter_type setting. 6944 */ 6945 switch (hw->mc_filter_type) { 6946 /* 6947 * [0] [1] [2] [3] [4] [5] 01 AA 00 12 34 56 LSB 6948 * MSB 6949 */ 6950 case 0: 6951 if (IS_ICH8(hw->mac_type)) { 6952 /* [47:38] i.e. 0x158 for above example address */ 6953 hash_value = ((mc_addr[4] >> 6) | 6954 (((uint16_t) mc_addr[5]) << 2)); 6955 } else { 6956 /* [47:36] i.e. 0x563 for above example address */ 6957 hash_value = ((mc_addr[4] >> 4) | 6958 (((uint16_t) mc_addr[5]) << 4)); 6959 } 6960 break; 6961 case 1: 6962 if (IS_ICH8(hw->mac_type)) { 6963 /* [46:37] i.e. 0x2B1 for above example address */ 6964 hash_value = ((mc_addr[4] >> 5) | 6965 (((uint16_t) mc_addr[5]) << 3)); 6966 } else { 6967 /* [46:35] i.e. 0xAC6 for above example address */ 6968 hash_value = ((mc_addr[4] >> 3) | 6969 (((uint16_t) mc_addr[5]) << 5)); 6970 } 6971 break; 6972 case 2: 6973 if (IS_ICH8(hw->mac_type)) { 6974 /* [45:36] i.e. 0x163 for above example address */ 6975 hash_value = ((mc_addr[4] >> 4) | 6976 (((uint16_t) mc_addr[5]) << 4)); 6977 } else { 6978 /* [45:34] i.e. 0x5D8 for above example address */ 6979 hash_value = ((mc_addr[4] >> 2) | 6980 (((uint16_t) mc_addr[5]) << 6)); 6981 } 6982 break; 6983 case 3: 6984 if (IS_ICH8(hw->mac_type)) { 6985 /* [43:34] i.e. 0x18D for above example address */ 6986 hash_value = ((mc_addr[4] >> 2) | 6987 (((uint16_t) mc_addr[5]) << 6)); 6988 } else { 6989 /* [43:32] i.e. 0x634 for above example address */ 6990 hash_value = ((mc_addr[4]) | 6991 (((uint16_t) mc_addr[5]) << 8)); 6992 } 6993 break; 6994 } 6995 6996 hash_value &= 0xFFF; 6997 if (IS_ICH8(hw->mac_type)) 6998 hash_value &= 0x3FF; 6999 7000 return hash_value; 7001 } 7002 7003 /****************************************************************************** 7004 * Sets the bit in the multicast table corresponding to the hash value. 7005 * 7006 * hw - Struct containing variables accessed by shared code 7007 * hash_value - Multicast address hash value 7008 *****************************************************************************/ 7009 void 7010 em_mta_set(struct em_hw *hw, uint32_t hash_value) 7011 { 7012 uint32_t hash_bit, hash_reg; 7013 uint32_t mta; 7014 uint32_t temp; 7015 /* 7016 * The MTA is a register array of 128 32-bit registers. It is treated 7017 * like an array of 4096 bits. We want to set bit 7018 * BitArray[hash_value]. So we figure out what register the bit is 7019 * in, read it, OR in the new bit, then write back the new value. 7020 * The register is determined by the upper 7 bits of the hash value 7021 * and the bit within that register are determined by the lower 5 7022 * bits of the value. 7023 */ 7024 hash_reg = (hash_value >> 5) & 0x7F; 7025 if (IS_ICH8(hw->mac_type)) 7026 hash_reg &= 0x1F; 7027 7028 hash_bit = hash_value & 0x1F; 7029 7030 mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg); 7031 7032 mta |= (1 << hash_bit); 7033 /* 7034 * If we are on an 82544 and we are trying to write an odd offset in 7035 * the MTA, save off the previous entry before writing and restore 7036 * the old value after writing. 7037 */ 7038 if ((hw->mac_type == em_82544) && ((hash_reg & 0x1) == 1)) { 7039 temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1)); 7040 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta); 7041 E1000_WRITE_FLUSH(hw); 7042 E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp); 7043 E1000_WRITE_FLUSH(hw); 7044 } else { 7045 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta); 7046 E1000_WRITE_FLUSH(hw); 7047 } 7048 } 7049 7050 /****************************************************************************** 7051 * Puts an ethernet address into a receive address register. 7052 * 7053 * hw - Struct containing variables accessed by shared code 7054 * addr - Address to put into receive address register 7055 * index - Receive address register to write 7056 *****************************************************************************/ 7057 void 7058 em_rar_set(struct em_hw *hw, uint8_t *addr, uint32_t index) 7059 { 7060 uint32_t rar_low, rar_high; 7061 /* 7062 * HW expects these in little endian so we reverse the byte order 7063 * from network order (big endian) to little endian 7064 */ 7065 rar_low = ((uint32_t) addr[0] | ((uint32_t) addr[1] << 8) | 7066 ((uint32_t) addr[2] << 16) | ((uint32_t) addr[3] << 24)); 7067 rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8)); 7068 /* 7069 * Disable Rx and flush all Rx frames before enabling RSS to avoid Rx 7070 * unit hang. 7071 * 7072 * Description: If there are any Rx frames queued up or otherwise 7073 * present in the HW before RSS is enabled, and then we enable RSS, 7074 * the HW Rx unit will hang. To work around this issue, we have to 7075 * disable receives and flush out all Rx frames before we enable RSS. 7076 * To do so, we modify we redirect all Rx traffic to manageability 7077 * and then reset the HW. This flushes away Rx frames, and (since the 7078 * redirections to manageability persists across resets) keeps new 7079 * ones from coming in while we work. Then, we clear the Address 7080 * Valid AV bit for all MAC addresses and undo the re-direction to 7081 * manageability. Now, frames are coming in again, but the MAC won't 7082 * accept them, so far so good. We now proceed to initialize RSS (if 7083 * necessary) and configure the Rx unit. Last, we re-enable the AV 7084 * bits and continue on our merry way. 7085 */ 7086 switch (hw->mac_type) { 7087 case em_82571: 7088 case em_82572: 7089 case em_80003es2lan: 7090 if (hw->leave_av_bit_off == TRUE) 7091 break; 7092 default: 7093 /* Indicate to hardware the Address is Valid. */ 7094 rar_high |= E1000_RAH_AV; 7095 break; 7096 } 7097 7098 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low); 7099 E1000_WRITE_FLUSH(hw); 7100 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high); 7101 E1000_WRITE_FLUSH(hw); 7102 } 7103 7104 /****************************************************************************** 7105 * Clears the VLAN filer table 7106 * 7107 * hw - Struct containing variables accessed by shared code 7108 *****************************************************************************/ 7109 STATIC void 7110 em_clear_vfta(struct em_hw *hw) 7111 { 7112 uint32_t offset; 7113 uint32_t vfta_value = 0; 7114 uint32_t vfta_offset = 0; 7115 uint32_t vfta_bit_in_reg = 0; 7116 if (IS_ICH8(hw->mac_type)) 7117 return; 7118 7119 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) { 7120 if (hw->mng_cookie.vlan_id != 0) { 7121 /* 7122 * The VFTA is a 4096b bit-field, each identifying a 7123 * single VLAN ID. The following operations 7124 * determine which 32b entry (i.e. offset) into the 7125 * array we want to set the VLAN ID (i.e. bit) of the 7126 * manageability unit. 7127 */ 7128 vfta_offset = (hw->mng_cookie.vlan_id >> 7129 E1000_VFTA_ENTRY_SHIFT) & E1000_VFTA_ENTRY_MASK; 7130 7131 vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id & 7132 E1000_VFTA_ENTRY_BIT_SHIFT_MASK); 7133 } 7134 } 7135 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 7136 /* 7137 * If the offset we want to clear is the same offset of the 7138 * manageability VLAN ID, then clear all bits except that of 7139 * the manageability unit 7140 */ 7141 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; 7142 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value); 7143 E1000_WRITE_FLUSH(hw); 7144 } 7145 } 7146 7147 /* 7148 * Due to hw errata, if the host tries to configure the VFTA register 7149 * while performing queries from the BMC or DMA, then the VFTA in some 7150 * cases won't be written. 7151 */ 7152 void 7153 em_clear_vfta_i350(struct em_hw *hw) 7154 { 7155 uint32_t offset; 7156 int i; 7157 7158 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 7159 for (i = 0; i < 10; i++) 7160 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0); 7161 E1000_WRITE_FLUSH(hw); 7162 } 7163 } 7164 7165 STATIC int32_t 7166 em_id_led_init(struct em_hw *hw) 7167 { 7168 uint32_t ledctl; 7169 const uint32_t ledctl_mask = 0x000000FF; 7170 const uint32_t ledctl_on = E1000_LEDCTL_MODE_LED_ON; 7171 const uint32_t ledctl_off = E1000_LEDCTL_MODE_LED_OFF; 7172 uint16_t eeprom_data, i, temp; 7173 const uint16_t led_mask = 0x0F; 7174 DEBUGFUNC("em_id_led_init"); 7175 7176 if (hw->mac_type < em_82540 || hw->mac_type == em_icp_xxxx) { 7177 /* Nothing to do */ 7178 return E1000_SUCCESS; 7179 } 7180 ledctl = E1000_READ_REG(hw, LEDCTL); 7181 hw->ledctl_default = ledctl; 7182 hw->ledctl_mode1 = hw->ledctl_default; 7183 hw->ledctl_mode2 = hw->ledctl_default; 7184 7185 if (em_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) { 7186 DEBUGOUT("EEPROM Read Error\n"); 7187 return -E1000_ERR_EEPROM; 7188 } 7189 if ((hw->mac_type == em_82573) && 7190 (eeprom_data == ID_LED_RESERVED_82573)) 7191 eeprom_data = ID_LED_DEFAULT_82573; 7192 else if ((eeprom_data == ID_LED_RESERVED_0000) || 7193 (eeprom_data == ID_LED_RESERVED_FFFF)) { 7194 if (hw->mac_type == em_ich8lan || 7195 hw->mac_type == em_ich9lan || 7196 hw->mac_type == em_ich10lan) // XXX 7197 eeprom_data = ID_LED_DEFAULT_ICH8LAN; 7198 else 7199 eeprom_data = ID_LED_DEFAULT; 7200 } 7201 for (i = 0; i < 4; i++) { 7202 temp = (eeprom_data >> (i << 2)) & led_mask; 7203 switch (temp) { 7204 case ID_LED_ON1_DEF2: 7205 case ID_LED_ON1_ON2: 7206 case ID_LED_ON1_OFF2: 7207 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 7208 hw->ledctl_mode1 |= ledctl_on << (i << 3); 7209 break; 7210 case ID_LED_OFF1_DEF2: 7211 case ID_LED_OFF1_ON2: 7212 case ID_LED_OFF1_OFF2: 7213 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 7214 hw->ledctl_mode1 |= ledctl_off << (i << 3); 7215 break; 7216 default: 7217 /* Do nothing */ 7218 break; 7219 } 7220 switch (temp) { 7221 case ID_LED_DEF1_ON2: 7222 case ID_LED_ON1_ON2: 7223 case ID_LED_OFF1_ON2: 7224 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 7225 hw->ledctl_mode2 |= ledctl_on << (i << 3); 7226 break; 7227 case ID_LED_DEF1_OFF2: 7228 case ID_LED_ON1_OFF2: 7229 case ID_LED_OFF1_OFF2: 7230 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 7231 hw->ledctl_mode2 |= ledctl_off << (i << 3); 7232 break; 7233 default: 7234 /* Do nothing */ 7235 break; 7236 } 7237 } 7238 return E1000_SUCCESS; 7239 } 7240 7241 /****************************************************************************** 7242 * Clears all hardware statistics counters. 7243 * 7244 * hw - Struct containing variables accessed by shared code 7245 *****************************************************************************/ 7246 void 7247 em_clear_hw_cntrs(struct em_hw *hw) 7248 { 7249 volatile uint32_t temp; 7250 temp = E1000_READ_REG(hw, CRCERRS); 7251 temp = E1000_READ_REG(hw, SYMERRS); 7252 temp = E1000_READ_REG(hw, MPC); 7253 temp = E1000_READ_REG(hw, SCC); 7254 temp = E1000_READ_REG(hw, ECOL); 7255 temp = E1000_READ_REG(hw, MCC); 7256 temp = E1000_READ_REG(hw, LATECOL); 7257 temp = E1000_READ_REG(hw, COLC); 7258 temp = E1000_READ_REG(hw, DC); 7259 temp = E1000_READ_REG(hw, SEC); 7260 temp = E1000_READ_REG(hw, RLEC); 7261 temp = E1000_READ_REG(hw, XONRXC); 7262 temp = E1000_READ_REG(hw, XONTXC); 7263 temp = E1000_READ_REG(hw, XOFFRXC); 7264 temp = E1000_READ_REG(hw, XOFFTXC); 7265 temp = E1000_READ_REG(hw, FCRUC); 7266 7267 if (!IS_ICH8(hw->mac_type)) { 7268 temp = E1000_READ_REG(hw, PRC64); 7269 temp = E1000_READ_REG(hw, PRC127); 7270 temp = E1000_READ_REG(hw, PRC255); 7271 temp = E1000_READ_REG(hw, PRC511); 7272 temp = E1000_READ_REG(hw, PRC1023); 7273 temp = E1000_READ_REG(hw, PRC1522); 7274 } 7275 temp = E1000_READ_REG(hw, GPRC); 7276 temp = E1000_READ_REG(hw, BPRC); 7277 temp = E1000_READ_REG(hw, MPRC); 7278 temp = E1000_READ_REG(hw, GPTC); 7279 temp = E1000_READ_REG(hw, GORCL); 7280 temp = E1000_READ_REG(hw, GORCH); 7281 temp = E1000_READ_REG(hw, GOTCL); 7282 temp = E1000_READ_REG(hw, GOTCH); 7283 temp = E1000_READ_REG(hw, RNBC); 7284 temp = E1000_READ_REG(hw, RUC); 7285 temp = E1000_READ_REG(hw, RFC); 7286 temp = E1000_READ_REG(hw, ROC); 7287 temp = E1000_READ_REG(hw, RJC); 7288 temp = E1000_READ_REG(hw, TORL); 7289 temp = E1000_READ_REG(hw, TORH); 7290 temp = E1000_READ_REG(hw, TOTL); 7291 temp = E1000_READ_REG(hw, TOTH); 7292 temp = E1000_READ_REG(hw, TPR); 7293 temp = E1000_READ_REG(hw, TPT); 7294 7295 if (!IS_ICH8(hw->mac_type)) { 7296 temp = E1000_READ_REG(hw, PTC64); 7297 temp = E1000_READ_REG(hw, PTC127); 7298 temp = E1000_READ_REG(hw, PTC255); 7299 temp = E1000_READ_REG(hw, PTC511); 7300 temp = E1000_READ_REG(hw, PTC1023); 7301 temp = E1000_READ_REG(hw, PTC1522); 7302 } 7303 temp = E1000_READ_REG(hw, MPTC); 7304 temp = E1000_READ_REG(hw, BPTC); 7305 7306 if (hw->mac_type < em_82543) 7307 return; 7308 7309 temp = E1000_READ_REG(hw, ALGNERRC); 7310 temp = E1000_READ_REG(hw, RXERRC); 7311 temp = E1000_READ_REG(hw, TNCRS); 7312 temp = E1000_READ_REG(hw, CEXTERR); 7313 temp = E1000_READ_REG(hw, TSCTC); 7314 temp = E1000_READ_REG(hw, TSCTFC); 7315 7316 if (hw->mac_type <= em_82544 7317 || hw->mac_type == em_icp_xxxx) 7318 return; 7319 7320 temp = E1000_READ_REG(hw, MGTPRC); 7321 temp = E1000_READ_REG(hw, MGTPDC); 7322 temp = E1000_READ_REG(hw, MGTPTC); 7323 7324 if (hw->mac_type <= em_82547_rev_2) 7325 return; 7326 7327 temp = E1000_READ_REG(hw, IAC); 7328 temp = E1000_READ_REG(hw, ICRXOC); 7329 7330 if (hw->phy_type == em_phy_82577 || 7331 hw->phy_type == em_phy_82578 || 7332 hw->phy_type == em_phy_82579 || 7333 hw->phy_type == em_phy_i217) { 7334 uint16_t phy_data; 7335 7336 em_read_phy_reg(hw, HV_SCC_UPPER, &phy_data); 7337 em_read_phy_reg(hw, HV_SCC_LOWER, &phy_data); 7338 em_read_phy_reg(hw, HV_ECOL_UPPER, &phy_data); 7339 em_read_phy_reg(hw, HV_ECOL_LOWER, &phy_data); 7340 em_read_phy_reg(hw, HV_MCC_UPPER, &phy_data); 7341 em_read_phy_reg(hw, HV_MCC_LOWER, &phy_data); 7342 em_read_phy_reg(hw, HV_LATECOL_UPPER, &phy_data); 7343 em_read_phy_reg(hw, HV_LATECOL_LOWER, &phy_data); 7344 em_read_phy_reg(hw, HV_COLC_UPPER, &phy_data); 7345 em_read_phy_reg(hw, HV_COLC_LOWER, &phy_data); 7346 em_read_phy_reg(hw, HV_DC_UPPER, &phy_data); 7347 em_read_phy_reg(hw, HV_DC_LOWER, &phy_data); 7348 em_read_phy_reg(hw, HV_TNCRS_UPPER, &phy_data); 7349 em_read_phy_reg(hw, HV_TNCRS_LOWER, &phy_data); 7350 } 7351 7352 if (hw->mac_type == em_ich8lan || 7353 hw->mac_type == em_ich9lan || 7354 hw->mac_type == em_ich10lan || 7355 hw->mac_type == em_pchlan || 7356 (hw->mac_type != em_pch2lan && hw->mac_type != em_pch_lpt)) 7357 return; 7358 7359 temp = E1000_READ_REG(hw, ICRXPTC); 7360 temp = E1000_READ_REG(hw, ICRXATC); 7361 temp = E1000_READ_REG(hw, ICTXPTC); 7362 temp = E1000_READ_REG(hw, ICTXATC); 7363 temp = E1000_READ_REG(hw, ICTXQEC); 7364 temp = E1000_READ_REG(hw, ICTXQMTC); 7365 temp = E1000_READ_REG(hw, ICRXDMTC); 7366 } 7367 7368 #ifndef SMALL_KERNEL 7369 /****************************************************************************** 7370 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT 7371 * 7372 * hw - Struct containing variables accessed by shared code 7373 * frame_len - The length of the frame in question 7374 * mac_addr - The Ethernet destination address of the frame in question 7375 *****************************************************************************/ 7376 void 7377 em_tbi_adjust_stats(struct em_hw *hw, struct em_hw_stats *stats, 7378 uint32_t frame_len, uint8_t *mac_addr) 7379 { 7380 uint64_t carry_bit; 7381 /* First adjust the frame length. */ 7382 frame_len--; 7383 /* 7384 * We need to adjust the statistics counters, since the hardware 7385 * counters overcount this packet as a CRC error and undercount the 7386 * packet as a good packet 7387 */ 7388 /* This packet should not be counted as a CRC error. */ 7389 stats->crcerrs--; 7390 /* This packet does count as a Good Packet Received. */ 7391 stats->gprc++; 7392 7393 /* Adjust the Good Octets received counters */ 7394 carry_bit = 0x80000000 & stats->gorcl; 7395 stats->gorcl += frame_len; 7396 /* 7397 * If the high bit of Gorcl (the low 32 bits of the Good Octets 7398 * Received Count) was one before the addition, AND it is zero after, 7399 * then we lost the carry out, need to add one to Gorch (Good Octets 7400 * Received Count High). This could be simplified if all environments 7401 * supported 64-bit integers. 7402 */ 7403 if (carry_bit && ((stats->gorcl & 0x80000000) == 0)) 7404 stats->gorch++; 7405 /* 7406 * Is this a broadcast or multicast? Check broadcast first, since 7407 * the test for a multicast frame will test positive on a broadcast 7408 * frame. 7409 */ 7410 if ((mac_addr[0] == (uint8_t) 0xff) && (mac_addr[1] == (uint8_t) 0xff)) 7411 /* Broadcast packet */ 7412 stats->bprc++; 7413 else if (*mac_addr & 0x01) 7414 /* Multicast packet */ 7415 stats->mprc++; 7416 7417 if (frame_len == hw->max_frame_size) { 7418 /* 7419 * In this case, the hardware has overcounted the number of 7420 * oversize frames. 7421 */ 7422 if (stats->roc > 0) 7423 stats->roc--; 7424 } 7425 /* 7426 * Adjust the bin counters when the extra byte put the frame in the 7427 * wrong bin. Remember that the frame_len was adjusted above. 7428 */ 7429 if (frame_len == 64) { 7430 stats->prc64++; 7431 stats->prc127--; 7432 } else if (frame_len == 127) { 7433 stats->prc127++; 7434 stats->prc255--; 7435 } else if (frame_len == 255) { 7436 stats->prc255++; 7437 stats->prc511--; 7438 } else if (frame_len == 511) { 7439 stats->prc511++; 7440 stats->prc1023--; 7441 } else if (frame_len == 1023) { 7442 stats->prc1023++; 7443 stats->prc1522--; 7444 } else if (frame_len == 1522) { 7445 stats->prc1522++; 7446 } 7447 } 7448 #endif /* !SMALL_KERNEL */ 7449 7450 /****************************************************************************** 7451 * Gets the current PCI bus type, speed, and width of the hardware 7452 * 7453 * hw - Struct containing variables accessed by shared code 7454 *****************************************************************************/ 7455 void 7456 em_get_bus_info(struct em_hw *hw) 7457 { 7458 int32_t ret_val; 7459 uint16_t pci_ex_link_status; 7460 uint32_t status; 7461 switch (hw->mac_type) { 7462 case em_82542_rev2_0: 7463 case em_82542_rev2_1: 7464 hw->bus_type = em_bus_type_unknown; 7465 hw->bus_speed = em_bus_speed_unknown; 7466 hw->bus_width = em_bus_width_unknown; 7467 break; 7468 case em_icp_xxxx: 7469 hw->bus_type = em_bus_type_cpp; 7470 hw->bus_speed = em_bus_speed_unknown; 7471 hw->bus_width = em_bus_width_unknown; 7472 break; 7473 case em_82571: 7474 case em_82572: 7475 case em_82573: 7476 case em_82574: 7477 case em_82575: 7478 case em_82580: 7479 case em_80003es2lan: 7480 case em_i210: 7481 case em_i350: 7482 hw->bus_type = em_bus_type_pci_express; 7483 hw->bus_speed = em_bus_speed_2500; 7484 ret_val = em_read_pcie_cap_reg(hw, PCI_EX_LINK_STATUS, 7485 &pci_ex_link_status); 7486 if (ret_val) 7487 hw->bus_width = em_bus_width_unknown; 7488 else 7489 hw->bus_width = (pci_ex_link_status & 7490 PCI_EX_LINK_WIDTH_MASK) >> PCI_EX_LINK_WIDTH_SHIFT; 7491 break; 7492 case em_ich8lan: 7493 case em_ich9lan: 7494 case em_ich10lan: 7495 case em_pchlan: 7496 case em_pch2lan: 7497 case em_pch_lpt: 7498 hw->bus_type = em_bus_type_pci_express; 7499 hw->bus_speed = em_bus_speed_2500; 7500 hw->bus_width = em_bus_width_pciex_1; 7501 break; 7502 default: 7503 status = E1000_READ_REG(hw, STATUS); 7504 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ? 7505 em_bus_type_pcix : em_bus_type_pci; 7506 7507 if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) { 7508 hw->bus_speed = (hw->bus_type == em_bus_type_pci) ? 7509 em_bus_speed_66 : em_bus_speed_120; 7510 } else if (hw->bus_type == em_bus_type_pci) { 7511 hw->bus_speed = (status & E1000_STATUS_PCI66) ? 7512 em_bus_speed_66 : em_bus_speed_33; 7513 } else { 7514 switch (status & E1000_STATUS_PCIX_SPEED) { 7515 case E1000_STATUS_PCIX_SPEED_66: 7516 hw->bus_speed = em_bus_speed_66; 7517 break; 7518 case E1000_STATUS_PCIX_SPEED_100: 7519 hw->bus_speed = em_bus_speed_100; 7520 break; 7521 case E1000_STATUS_PCIX_SPEED_133: 7522 hw->bus_speed = em_bus_speed_133; 7523 break; 7524 default: 7525 hw->bus_speed = em_bus_speed_reserved; 7526 break; 7527 } 7528 } 7529 hw->bus_width = (status & E1000_STATUS_BUS64) ? 7530 em_bus_width_64 : em_bus_width_32; 7531 break; 7532 } 7533 } 7534 7535 /****************************************************************************** 7536 * Writes a value to one of the devices registers using port I/O (as opposed to 7537 * memory mapped I/O). Only 82544 and newer devices support port I/O. 7538 * 7539 * hw - Struct containing variables accessed by shared code 7540 * offset - offset to write to 7541 * value - value to write 7542 *****************************************************************************/ 7543 STATIC void 7544 em_write_reg_io(struct em_hw *hw, uint32_t offset, uint32_t value) 7545 { 7546 unsigned long io_addr = hw->io_base; 7547 unsigned long io_data = hw->io_base + 4; 7548 em_io_write(hw, io_addr, offset); 7549 em_io_write(hw, io_data, value); 7550 } 7551 7552 /****************************************************************************** 7553 * Estimates the cable length. 7554 * 7555 * hw - Struct containing variables accessed by shared code 7556 * min_length - The estimated minimum length 7557 * max_length - The estimated maximum length 7558 * 7559 * returns: - E1000_ERR_XXX 7560 * E1000_SUCCESS 7561 * 7562 * This function always returns a ranged length (minimum & maximum). 7563 * So for M88 phy's, this function interprets the one value returned from the 7564 * register to the minimum and maximum range. 7565 * For IGP phy's, the function calculates the range by the AGC registers. 7566 *****************************************************************************/ 7567 STATIC int32_t 7568 em_get_cable_length(struct em_hw *hw, uint16_t *min_length, 7569 uint16_t *max_length) 7570 { 7571 int32_t ret_val; 7572 uint16_t agc_value = 0; 7573 uint16_t i, phy_data; 7574 uint16_t cable_length; 7575 DEBUGFUNC("em_get_cable_length"); 7576 7577 *min_length = *max_length = 0; 7578 7579 /* Use old method for Phy older than IGP */ 7580 if (hw->phy_type == em_phy_m88 || 7581 hw->phy_type == em_phy_oem || 7582 hw->phy_type == em_phy_82578) { 7583 7584 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, 7585 &phy_data); 7586 if (ret_val) 7587 return ret_val; 7588 cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 7589 M88E1000_PSSR_CABLE_LENGTH_SHIFT; 7590 7591 /* Convert the enum value to ranged values */ 7592 switch (cable_length) { 7593 case em_cable_length_50: 7594 *min_length = 0; 7595 *max_length = em_igp_cable_length_50; 7596 break; 7597 case em_cable_length_50_80: 7598 *min_length = em_igp_cable_length_50; 7599 *max_length = em_igp_cable_length_80; 7600 break; 7601 case em_cable_length_80_110: 7602 *min_length = em_igp_cable_length_80; 7603 *max_length = em_igp_cable_length_110; 7604 break; 7605 case em_cable_length_110_140: 7606 *min_length = em_igp_cable_length_110; 7607 *max_length = em_igp_cable_length_140; 7608 break; 7609 case em_cable_length_140: 7610 *min_length = em_igp_cable_length_140; 7611 *max_length = em_igp_cable_length_170; 7612 break; 7613 default: 7614 return -E1000_ERR_PHY; 7615 break; 7616 } 7617 } else if (hw->phy_type == em_phy_gg82563) { 7618 ret_val = em_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE, 7619 &phy_data); 7620 if (ret_val) 7621 return ret_val; 7622 cable_length = phy_data & GG82563_DSPD_CABLE_LENGTH; 7623 7624 switch (cable_length) { 7625 case em_gg_cable_length_60: 7626 *min_length = 0; 7627 *max_length = em_igp_cable_length_60; 7628 break; 7629 case em_gg_cable_length_60_115: 7630 *min_length = em_igp_cable_length_60; 7631 *max_length = em_igp_cable_length_115; 7632 break; 7633 case em_gg_cable_length_115_150: 7634 *min_length = em_igp_cable_length_115; 7635 *max_length = em_igp_cable_length_150; 7636 break; 7637 case em_gg_cable_length_150: 7638 *min_length = em_igp_cable_length_150; 7639 *max_length = em_igp_cable_length_180; 7640 break; 7641 default: 7642 return -E1000_ERR_PHY; 7643 break; 7644 } 7645 } else if (hw->phy_type == em_phy_igp) { /* For IGP PHY */ 7646 uint16_t cur_agc_value; 7647 uint16_t min_agc_value = 7648 IGP01E1000_AGC_LENGTH_TABLE_SIZE; 7649 uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = 7650 {IGP01E1000_PHY_AGC_A, IGP01E1000_PHY_AGC_B, 7651 IGP01E1000_PHY_AGC_C, IGP01E1000_PHY_AGC_D}; 7652 7653 /* Read the AGC registers for all channels */ 7654 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 7655 ret_val = em_read_phy_reg(hw, agc_reg_array[i], 7656 &phy_data); 7657 if (ret_val) 7658 return ret_val; 7659 7660 cur_agc_value = phy_data >> 7661 IGP01E1000_AGC_LENGTH_SHIFT; 7662 7663 /* Value bound check. */ 7664 if ((cur_agc_value >= 7665 IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) || 7666 (cur_agc_value == 0)) 7667 return -E1000_ERR_PHY; 7668 7669 agc_value += cur_agc_value; 7670 7671 /* Update minimal AGC value. */ 7672 if (min_agc_value > cur_agc_value) 7673 min_agc_value = cur_agc_value; 7674 } 7675 7676 /* Remove the minimal AGC result for length < 50m */ 7677 if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * 7678 em_igp_cable_length_50) { 7679 agc_value -= min_agc_value; 7680 7681 /* 7682 * Get the average length of the remaining 3 channels 7683 */ 7684 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1); 7685 } else { 7686 /* Get the average length of all the 4 channels. */ 7687 agc_value /= IGP01E1000_PHY_CHANNEL_NUM; 7688 } 7689 7690 /* Set the range of the calculated length. */ 7691 *min_length = ((em_igp_cable_length_table[agc_value] - 7692 IGP01E1000_AGC_RANGE) > 0) ? 7693 (em_igp_cable_length_table[agc_value] - 7694 IGP01E1000_AGC_RANGE) : 0; 7695 *max_length = em_igp_cable_length_table[agc_value] + 7696 IGP01E1000_AGC_RANGE; 7697 } else if (hw->phy_type == em_phy_igp_2 || 7698 hw->phy_type == em_phy_igp_3) { 7699 uint16_t cur_agc_index, max_agc_index = 0; 7700 uint16_t min_agc_index = IGP02E1000_AGC_LENGTH_TABLE_SIZE - 1; 7701 uint16_t agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = 7702 {IGP02E1000_PHY_AGC_A, IGP02E1000_PHY_AGC_B, 7703 IGP02E1000_PHY_AGC_C, IGP02E1000_PHY_AGC_D}; 7704 /* Read the AGC registers for all channels */ 7705 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { 7706 ret_val = em_read_phy_reg(hw, agc_reg_array[i], 7707 &phy_data); 7708 if (ret_val) 7709 return ret_val; 7710 /* 7711 * Getting bits 15:9, which represent the combination 7712 * of course and fine gain values. The result is a 7713 * number that can be put into the lookup table to 7714 * obtain the approximate cable length. 7715 */ 7716 cur_agc_index = (phy_data >> 7717 IGP02E1000_AGC_LENGTH_SHIFT) & 7718 IGP02E1000_AGC_LENGTH_MASK; 7719 7720 /* Array index bound check. */ 7721 if ((cur_agc_index >= IGP02E1000_AGC_LENGTH_TABLE_SIZE) 7722 || (cur_agc_index == 0)) 7723 return -E1000_ERR_PHY; 7724 7725 /* Remove min & max AGC values from calculation. */ 7726 if (em_igp_2_cable_length_table[min_agc_index] > 7727 em_igp_2_cable_length_table[cur_agc_index]) 7728 min_agc_index = cur_agc_index; 7729 if (em_igp_2_cable_length_table[max_agc_index] < 7730 em_igp_2_cable_length_table[cur_agc_index]) 7731 max_agc_index = cur_agc_index; 7732 7733 agc_value += em_igp_2_cable_length_table 7734 [cur_agc_index]; 7735 } 7736 7737 agc_value -= (em_igp_2_cable_length_table[min_agc_index] + 7738 em_igp_2_cable_length_table[max_agc_index]); 7739 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); 7740 /* 7741 * Calculate cable length with the error range of +/- 10 7742 * meters. 7743 */ 7744 *min_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ? 7745 (agc_value - IGP02E1000_AGC_RANGE) : 0; 7746 *max_length = agc_value + IGP02E1000_AGC_RANGE; 7747 } 7748 return E1000_SUCCESS; 7749 } 7750 7751 /****************************************************************************** 7752 * Check if Downshift occured 7753 * 7754 * hw - Struct containing variables accessed by shared code 7755 * downshift - output parameter : 0 - No Downshift ocured. 7756 * 1 - Downshift ocured. 7757 * 7758 * returns: - E1000_ERR_XXX 7759 * E1000_SUCCESS 7760 * 7761 * For phy's older then IGP, this function reads the Downshift bit in the Phy 7762 * Specific Status register. For IGP phy's, it reads the Downgrade bit in the 7763 * Link Health register. In IGP this bit is latched high, so the driver must 7764 * read it immediately after link is established. 7765 *****************************************************************************/ 7766 STATIC int32_t 7767 em_check_downshift(struct em_hw *hw) 7768 { 7769 int32_t ret_val; 7770 uint16_t phy_data; 7771 DEBUGFUNC("em_check_downshift"); 7772 7773 if (hw->phy_type == em_phy_igp || 7774 hw->phy_type == em_phy_igp_3 || 7775 hw->phy_type == em_phy_igp_2) { 7776 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH, 7777 &phy_data); 7778 if (ret_val) 7779 return ret_val; 7780 7781 hw->speed_downgraded = (phy_data & 7782 IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0; 7783 } else if ((hw->phy_type == em_phy_m88) || 7784 (hw->phy_type == em_phy_gg82563) || 7785 (hw->phy_type == em_phy_oem) || 7786 (hw->phy_type == em_phy_82578)) { 7787 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, 7788 &phy_data); 7789 if (ret_val) 7790 return ret_val; 7791 7792 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >> 7793 M88E1000_PSSR_DOWNSHIFT_SHIFT; 7794 } else if (hw->phy_type == em_phy_ife) { 7795 /* em_phy_ife supports 10/100 speed only */ 7796 hw->speed_downgraded = FALSE; 7797 } 7798 return E1000_SUCCESS; 7799 } 7800 7801 /***************************************************************************** 7802 * 7803 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a 7804 * gigabit link is achieved to improve link quality. 7805 * 7806 * hw: Struct containing variables accessed by shared code 7807 * 7808 * returns: - E1000_ERR_PHY if fail to read/write the PHY 7809 * E1000_SUCCESS at any other case. 7810 * 7811 ****************************************************************************/ 7812 STATIC int32_t 7813 em_config_dsp_after_link_change(struct em_hw *hw, boolean_t link_up) 7814 { 7815 int32_t ret_val; 7816 uint16_t phy_data, phy_saved_data, speed, duplex, i; 7817 uint16_t dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = 7818 {IGP01E1000_PHY_AGC_PARAM_A, IGP01E1000_PHY_AGC_PARAM_B, 7819 IGP01E1000_PHY_AGC_PARAM_C, IGP01E1000_PHY_AGC_PARAM_D}; 7820 uint16_t min_length, max_length; 7821 DEBUGFUNC("em_config_dsp_after_link_change"); 7822 7823 if (hw->phy_type != em_phy_igp) 7824 return E1000_SUCCESS; 7825 7826 if (link_up) { 7827 ret_val = em_get_speed_and_duplex(hw, &speed, &duplex); 7828 if (ret_val) { 7829 DEBUGOUT("Error getting link speed and duplex\n"); 7830 return ret_val; 7831 } 7832 if (speed == SPEED_1000) { 7833 7834 ret_val = em_get_cable_length(hw, &min_length, &max_length); 7835 if (ret_val) 7836 return ret_val; 7837 7838 if ((hw->dsp_config_state == em_dsp_config_enabled) && 7839 min_length >= em_igp_cable_length_50) { 7840 7841 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; 7842 i++) { 7843 ret_val = em_read_phy_reg(hw, 7844 dsp_reg_array[i], &phy_data); 7845 if (ret_val) 7846 return ret_val; 7847 7848 phy_data &= 7849 ~IGP01E1000_PHY_EDAC_MU_INDEX; 7850 7851 ret_val = em_write_phy_reg(hw, 7852 dsp_reg_array[i], phy_data); 7853 if (ret_val) 7854 return ret_val; 7855 } 7856 hw->dsp_config_state = em_dsp_config_activated; 7857 } 7858 if ((hw->ffe_config_state == em_ffe_config_enabled) && 7859 (min_length < em_igp_cable_length_50)) { 7860 7861 uint16_t ffe_idle_err_timeout = 7862 FFE_IDLE_ERR_COUNT_TIMEOUT_20; 7863 uint32_t idle_errs = 0; 7864 /* clear previous idle error counts */ 7865 ret_val = em_read_phy_reg(hw, PHY_1000T_STATUS, 7866 &phy_data); 7867 if (ret_val) 7868 return ret_val; 7869 7870 for (i = 0; i < ffe_idle_err_timeout; i++) { 7871 usec_delay(1000); 7872 ret_val = em_read_phy_reg(hw, 7873 PHY_1000T_STATUS, &phy_data); 7874 if (ret_val) 7875 return ret_val; 7876 7877 idle_errs += (phy_data & 7878 SR_1000T_IDLE_ERROR_CNT); 7879 if (idle_errs > 7880 SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) { 7881 hw->ffe_config_state = 7882 em_ffe_config_active; 7883 7884 ret_val = em_write_phy_reg(hw, 7885 IGP01E1000_PHY_DSP_FFE, 7886 IGP01E1000_PHY_DSP_FFE_CM_CP); 7887 if (ret_val) 7888 return ret_val; 7889 break; 7890 } 7891 if (idle_errs) 7892 ffe_idle_err_timeout = 7893 FFE_IDLE_ERR_COUNT_TIMEOUT_100; 7894 } 7895 } 7896 } 7897 } else { 7898 if (hw->dsp_config_state == em_dsp_config_activated) { 7899 /* 7900 * Save off the current value of register 0x2F5B to 7901 * be restored at the end of the routines. 7902 */ 7903 ret_val = em_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 7904 7905 if (ret_val) 7906 return ret_val; 7907 7908 /* Disable the PHY transmitter */ 7909 ret_val = em_write_phy_reg(hw, 0x2F5B, 0x0003); 7910 7911 if (ret_val) 7912 return ret_val; 7913 7914 msec_delay_irq(20); 7915 7916 ret_val = em_write_phy_reg(hw, 0x0000, 7917 IGP01E1000_IEEE_FORCE_GIGA); 7918 if (ret_val) 7919 return ret_val; 7920 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 7921 ret_val = em_read_phy_reg(hw, dsp_reg_array[i], 7922 &phy_data); 7923 if (ret_val) 7924 return ret_val; 7925 7926 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; 7927 phy_data |= 7928 IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS; 7929 7930 ret_val = em_write_phy_reg(hw, 7931 dsp_reg_array[i], phy_data); 7932 if (ret_val) 7933 return ret_val; 7934 } 7935 7936 ret_val = em_write_phy_reg(hw, 0x0000, 7937 IGP01E1000_IEEE_RESTART_AUTONEG); 7938 if (ret_val) 7939 return ret_val; 7940 7941 msec_delay_irq(20); 7942 7943 /* Now enable the transmitter */ 7944 ret_val = em_write_phy_reg(hw, 0x2F5B, phy_saved_data); 7945 7946 if (ret_val) 7947 return ret_val; 7948 7949 hw->dsp_config_state = em_dsp_config_enabled; 7950 } 7951 if (hw->ffe_config_state == em_ffe_config_active) { 7952 /* 7953 * Save off the current value of register 0x2F5B to 7954 * be restored at the end of the routines. 7955 */ 7956 ret_val = em_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 7957 7958 if (ret_val) 7959 return ret_val; 7960 7961 /* Disable the PHY transmitter */ 7962 ret_val = em_write_phy_reg(hw, 0x2F5B, 0x0003); 7963 7964 if (ret_val) 7965 return ret_val; 7966 7967 msec_delay_irq(20); 7968 7969 ret_val = em_write_phy_reg(hw, 0x0000, 7970 IGP01E1000_IEEE_FORCE_GIGA); 7971 if (ret_val) 7972 return ret_val; 7973 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE, 7974 IGP01E1000_PHY_DSP_FFE_DEFAULT); 7975 if (ret_val) 7976 return ret_val; 7977 7978 ret_val = em_write_phy_reg(hw, 0x0000, 7979 IGP01E1000_IEEE_RESTART_AUTONEG); 7980 if (ret_val) 7981 return ret_val; 7982 7983 msec_delay_irq(20); 7984 7985 /* Now enable the transmitter */ 7986 ret_val = em_write_phy_reg(hw, 0x2F5B, phy_saved_data); 7987 7988 if (ret_val) 7989 return ret_val; 7990 7991 hw->ffe_config_state = em_ffe_config_enabled; 7992 } 7993 } 7994 return E1000_SUCCESS; 7995 } 7996 7997 /***************************************************************************** 7998 * Set PHY to class A mode 7999 * Assumes the following operations will follow to enable the new class mode. 8000 * 1. Do a PHY soft reset 8001 * 2. Restart auto-negotiation or force link. 8002 * 8003 * hw - Struct containing variables accessed by shared code 8004 ****************************************************************************/ 8005 static int32_t 8006 em_set_phy_mode(struct em_hw *hw) 8007 { 8008 int32_t ret_val; 8009 uint16_t eeprom_data; 8010 DEBUGFUNC("em_set_phy_mode"); 8011 8012 if ((hw->mac_type == em_82545_rev_3) && 8013 (hw->media_type == em_media_type_copper)) { 8014 ret_val = em_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, 8015 &eeprom_data); 8016 if (ret_val) { 8017 return ret_val; 8018 } 8019 if ((eeprom_data != EEPROM_RESERVED_WORD) && 8020 (eeprom_data & EEPROM_PHY_CLASS_A)) { 8021 ret_val = em_write_phy_reg(hw, 8022 M88E1000_PHY_PAGE_SELECT, 0x000B); 8023 if (ret_val) 8024 return ret_val; 8025 ret_val = em_write_phy_reg(hw, 8026 M88E1000_PHY_GEN_CONTROL, 0x8104); 8027 if (ret_val) 8028 return ret_val; 8029 8030 hw->phy_reset_disable = FALSE; 8031 } 8032 } 8033 return E1000_SUCCESS; 8034 } 8035 8036 /***************************************************************************** 8037 * 8038 * This function sets the lplu state according to the active flag. When 8039 * activating lplu this function also disables smart speed and vise versa. 8040 * lplu will not be activated unless the device autonegotiation advertisement 8041 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. 8042 * hw: Struct containing variables accessed by shared code 8043 * active - true to enable lplu false to disable lplu. 8044 * 8045 * returns: - E1000_ERR_PHY if fail to read/write the PHY 8046 * E1000_SUCCESS at any other case. 8047 * 8048 ****************************************************************************/ 8049 STATIC int32_t 8050 em_set_d3_lplu_state(struct em_hw *hw, boolean_t active) 8051 { 8052 uint32_t phy_ctrl = 0; 8053 int32_t ret_val; 8054 uint16_t phy_data; 8055 DEBUGFUNC("em_set_d3_lplu_state"); 8056 8057 if (hw->phy_type != em_phy_igp && hw->phy_type != em_phy_igp_2 8058 && hw->phy_type != em_phy_igp_3) 8059 return E1000_SUCCESS; 8060 /* 8061 * During driver activity LPLU should not be used or it will attain 8062 * link from the lowest speeds starting from 10Mbps. The capability 8063 * is used for Dx transitions and states 8064 */ 8065 if (hw->mac_type == em_82541_rev_2 || hw->mac_type == em_82547_rev_2) { 8066 ret_val = em_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data); 8067 if (ret_val) 8068 return ret_val; 8069 } else if (IS_ICH8(hw->mac_type)) { 8070 /* 8071 * MAC writes into PHY register based on the state transition 8072 * and start auto-negotiation. SW driver can overwrite the 8073 * settings in CSR PHY power control E1000_PHY_CTRL register. 8074 */ 8075 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); 8076 } else { 8077 ret_val = em_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, 8078 &phy_data); 8079 if (ret_val) 8080 return ret_val; 8081 } 8082 8083 if (!active) { 8084 if (hw->mac_type == em_82541_rev_2 || 8085 hw->mac_type == em_82547_rev_2) { 8086 phy_data &= ~IGP01E1000_GMII_FLEX_SPD; 8087 ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO, 8088 phy_data); 8089 if (ret_val) 8090 return ret_val; 8091 } else { 8092 if (IS_ICH8(hw->mac_type)) { 8093 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; 8094 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 8095 } else { 8096 phy_data &= ~IGP02E1000_PM_D3_LPLU; 8097 ret_val = em_write_phy_reg(hw, 8098 IGP02E1000_PHY_POWER_MGMT, phy_data); 8099 if (ret_val) 8100 return ret_val; 8101 } 8102 } 8103 /* 8104 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 8105 * during Dx states where the power conservation is most 8106 * important. During driver activity we should enable 8107 * SmartSpeed, so performance is maintained. 8108 */ 8109 if (hw->smart_speed == em_smart_speed_on) { 8110 ret_val = em_read_phy_reg(hw, 8111 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 8112 if (ret_val) 8113 return ret_val; 8114 8115 phy_data |= IGP01E1000_PSCFR_SMART_SPEED; 8116 ret_val = em_write_phy_reg(hw, 8117 IGP01E1000_PHY_PORT_CONFIG, phy_data); 8118 if (ret_val) 8119 return ret_val; 8120 } else if (hw->smart_speed == em_smart_speed_off) { 8121 ret_val = em_read_phy_reg(hw, 8122 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 8123 if (ret_val) 8124 return ret_val; 8125 8126 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 8127 ret_val = em_write_phy_reg(hw, 8128 IGP01E1000_PHY_PORT_CONFIG, phy_data); 8129 if (ret_val) 8130 return ret_val; 8131 } 8132 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) 8133 || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) || 8134 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) { 8135 8136 if (hw->mac_type == em_82541_rev_2 || 8137 hw->mac_type == em_82547_rev_2) { 8138 phy_data |= IGP01E1000_GMII_FLEX_SPD; 8139 ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO, 8140 phy_data); 8141 if (ret_val) 8142 return ret_val; 8143 } else { 8144 if (IS_ICH8(hw->mac_type)) { 8145 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; 8146 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 8147 } else { 8148 phy_data |= IGP02E1000_PM_D3_LPLU; 8149 ret_val = em_write_phy_reg(hw, 8150 IGP02E1000_PHY_POWER_MGMT, phy_data); 8151 if (ret_val) 8152 return ret_val; 8153 } 8154 } 8155 8156 /* When LPLU is enabled we should disable SmartSpeed */ 8157 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 8158 &phy_data); 8159 if (ret_val) 8160 return ret_val; 8161 8162 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 8163 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 8164 phy_data); 8165 if (ret_val) 8166 return ret_val; 8167 8168 } 8169 return E1000_SUCCESS; 8170 } 8171 8172 /***************************************************************************** 8173 * 8174 * This function sets the lplu d0 state according to the active flag. When 8175 * activating lplu this function also disables smart speed and vise versa. 8176 * lplu will not be activated unless the device autonegotiation advertisement 8177 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. 8178 * hw: Struct containing variables accessed by shared code 8179 * active - true to enable lplu false to disable lplu. 8180 * 8181 * returns: - E1000_ERR_PHY if fail to read/write the PHY 8182 * E1000_SUCCESS at any other case. 8183 * 8184 ****************************************************************************/ 8185 STATIC int32_t 8186 em_set_d0_lplu_state(struct em_hw *hw, boolean_t active) 8187 { 8188 uint32_t phy_ctrl = 0; 8189 int32_t ret_val; 8190 uint16_t phy_data; 8191 DEBUGFUNC("em_set_d0_lplu_state"); 8192 8193 if (hw->mac_type <= em_82547_rev_2) 8194 return E1000_SUCCESS; 8195 8196 if (IS_ICH8(hw->mac_type)) { 8197 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); 8198 } else { 8199 ret_val = em_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, 8200 &phy_data); 8201 if (ret_val) 8202 return ret_val; 8203 } 8204 8205 if (!active) { 8206 if (IS_ICH8(hw->mac_type)) { 8207 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; 8208 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 8209 } else { 8210 phy_data &= ~IGP02E1000_PM_D0_LPLU; 8211 ret_val = em_write_phy_reg(hw, 8212 IGP02E1000_PHY_POWER_MGMT, phy_data); 8213 if (ret_val) 8214 return ret_val; 8215 } 8216 /* 8217 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 8218 * during Dx states where the power conservation is most 8219 * important. During driver activity we should enable 8220 * SmartSpeed, so performance is maintained. 8221 */ 8222 if (hw->smart_speed == em_smart_speed_on) { 8223 ret_val = em_read_phy_reg(hw, 8224 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 8225 if (ret_val) 8226 return ret_val; 8227 8228 phy_data |= IGP01E1000_PSCFR_SMART_SPEED; 8229 ret_val = em_write_phy_reg(hw, 8230 IGP01E1000_PHY_PORT_CONFIG, phy_data); 8231 if (ret_val) 8232 return ret_val; 8233 } else if (hw->smart_speed == em_smart_speed_off) { 8234 ret_val = em_read_phy_reg(hw, 8235 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 8236 if (ret_val) 8237 return ret_val; 8238 8239 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 8240 ret_val = em_write_phy_reg(hw, 8241 IGP01E1000_PHY_PORT_CONFIG, phy_data); 8242 if (ret_val) 8243 return ret_val; 8244 } 8245 } else { 8246 if (IS_ICH8(hw->mac_type)) { 8247 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; 8248 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 8249 } else { 8250 phy_data |= IGP02E1000_PM_D0_LPLU; 8251 ret_val = em_write_phy_reg(hw, 8252 IGP02E1000_PHY_POWER_MGMT, phy_data); 8253 if (ret_val) 8254 return ret_val; 8255 } 8256 8257 /* When LPLU is enabled we should disable SmartSpeed */ 8258 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 8259 &phy_data); 8260 if (ret_val) 8261 return ret_val; 8262 8263 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 8264 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 8265 phy_data); 8266 if (ret_val) 8267 return ret_val; 8268 8269 } 8270 return E1000_SUCCESS; 8271 } 8272 8273 /*************************************************************************** 8274 * Set Low Power Link Up state 8275 * 8276 * Sets the LPLU state according to the active flag. For PCH, if OEM write 8277 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set 8278 * the phy speed. This function will manually set the LPLU bit and restart 8279 * auto-neg as hw would do. D3 and D0 LPLU will call the same function 8280 * since it configures the same bit. 8281 ***************************************************************************/ 8282 int32_t 8283 em_set_lplu_state_pchlan(struct em_hw *hw, boolean_t active) 8284 { 8285 int32_t ret_val = E1000_SUCCESS; 8286 uint16_t oem_reg; 8287 8288 DEBUGFUNC("e1000_set_lplu_state_pchlan"); 8289 8290 ret_val = em_read_phy_reg(hw, HV_OEM_BITS, &oem_reg); 8291 if (ret_val) 8292 goto out; 8293 8294 if (active) 8295 oem_reg |= HV_OEM_BITS_LPLU; 8296 else 8297 oem_reg &= ~HV_OEM_BITS_LPLU; 8298 8299 oem_reg |= HV_OEM_BITS_RESTART_AN; 8300 ret_val = em_write_phy_reg(hw, HV_OEM_BITS, oem_reg); 8301 8302 out: 8303 return ret_val; 8304 } 8305 8306 /****************************************************************************** 8307 * Change VCO speed register to improve Bit Error Rate performance of SERDES. 8308 * 8309 * hw - Struct containing variables accessed by shared code 8310 *****************************************************************************/ 8311 static int32_t 8312 em_set_vco_speed(struct em_hw *hw) 8313 { 8314 int32_t ret_val; 8315 uint16_t default_page = 0; 8316 uint16_t phy_data; 8317 DEBUGFUNC("em_set_vco_speed"); 8318 8319 switch (hw->mac_type) { 8320 case em_82545_rev_3: 8321 case em_82546_rev_3: 8322 break; 8323 default: 8324 return E1000_SUCCESS; 8325 } 8326 8327 /* Set PHY register 30, page 5, bit 8 to 0 */ 8328 8329 ret_val = em_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page); 8330 if (ret_val) 8331 return ret_val; 8332 8333 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005); 8334 if (ret_val) 8335 return ret_val; 8336 8337 ret_val = em_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); 8338 if (ret_val) 8339 return ret_val; 8340 8341 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8; 8342 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); 8343 if (ret_val) 8344 return ret_val; 8345 8346 /* Set PHY register 30, page 4, bit 11 to 1 */ 8347 8348 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004); 8349 if (ret_val) 8350 return ret_val; 8351 8352 ret_val = em_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); 8353 if (ret_val) 8354 return ret_val; 8355 8356 phy_data |= M88E1000_PHY_VCO_REG_BIT11; 8357 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); 8358 if (ret_val) 8359 return ret_val; 8360 8361 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page); 8362 if (ret_val) 8363 return ret_val; 8364 8365 return E1000_SUCCESS; 8366 } 8367 8368 /***************************************************************************** 8369 * This function reads the cookie from ARC ram. 8370 * 8371 * returns: - E1000_SUCCESS . 8372 ****************************************************************************/ 8373 STATIC int32_t 8374 em_host_if_read_cookie(struct em_hw *hw, uint8_t *buffer) 8375 { 8376 uint8_t i; 8377 uint32_t offset = E1000_MNG_DHCP_COOKIE_OFFSET; 8378 uint8_t length = E1000_MNG_DHCP_COOKIE_LENGTH; 8379 length = (length >> 2); 8380 offset = (offset >> 2); 8381 8382 for (i = 0; i < length; i++) { 8383 *((uint32_t *) buffer + i) = 8384 E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i); 8385 } 8386 return E1000_SUCCESS; 8387 } 8388 8389 /***************************************************************************** 8390 * This function checks whether the HOST IF is enabled for command operaton 8391 * and also checks whether the previous command is completed. 8392 * It busy waits in case of previous command is not completed. 8393 * 8394 * returns: - E1000_ERR_HOST_INTERFACE_COMMAND in case if is not ready or 8395 * timeout 8396 * - E1000_SUCCESS for success. 8397 ****************************************************************************/ 8398 STATIC int32_t 8399 em_mng_enable_host_if(struct em_hw *hw) 8400 { 8401 uint32_t hicr; 8402 uint8_t i; 8403 /* Check that the host interface is enabled. */ 8404 hicr = E1000_READ_REG(hw, HICR); 8405 if ((hicr & E1000_HICR_EN) == 0) { 8406 DEBUGOUT("E1000_HOST_EN bit disabled.\n"); 8407 return -E1000_ERR_HOST_INTERFACE_COMMAND; 8408 } 8409 /* check the previous command is completed */ 8410 for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) { 8411 hicr = E1000_READ_REG(hw, HICR); 8412 if (!(hicr & E1000_HICR_C)) 8413 break; 8414 msec_delay_irq(1); 8415 } 8416 8417 if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) { 8418 DEBUGOUT("Previous command timeout failed .\n"); 8419 return -E1000_ERR_HOST_INTERFACE_COMMAND; 8420 } 8421 return E1000_SUCCESS; 8422 } 8423 8424 /***************************************************************************** 8425 * This function checks the mode of the firmware. 8426 * 8427 * returns - TRUE when the mode is IAMT or FALSE. 8428 ****************************************************************************/ 8429 boolean_t 8430 em_check_mng_mode(struct em_hw *hw) 8431 { 8432 uint32_t fwsm; 8433 fwsm = E1000_READ_REG(hw, FWSM); 8434 8435 if (IS_ICH8(hw->mac_type)) { 8436 if ((fwsm & E1000_FWSM_MODE_MASK) == 8437 (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) 8438 return TRUE; 8439 } else if ((fwsm & E1000_FWSM_MODE_MASK) == 8440 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) 8441 return TRUE; 8442 8443 return FALSE; 8444 } 8445 8446 /***************************************************************************** 8447 * This function calculates the checksum. 8448 * 8449 * returns - checksum of buffer contents. 8450 ****************************************************************************/ 8451 STATIC uint8_t 8452 em_calculate_mng_checksum(char *buffer, uint32_t length) 8453 { 8454 uint8_t sum = 0; 8455 uint32_t i; 8456 if (!buffer) 8457 return 0; 8458 8459 for (i = 0; i < length; i++) 8460 sum += buffer[i]; 8461 8462 return (uint8_t) (0 - sum); 8463 } 8464 8465 /***************************************************************************** 8466 * This function checks whether tx pkt filtering needs to be enabled or not. 8467 * 8468 * returns - TRUE for packet filtering or FALSE. 8469 ****************************************************************************/ 8470 boolean_t 8471 em_enable_tx_pkt_filtering(struct em_hw *hw) 8472 { 8473 /* called in init as well as watchdog timer functions */ 8474 int32_t ret_val, checksum; 8475 boolean_t tx_filter = FALSE; 8476 struct em_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie); 8477 uint8_t *buffer = (uint8_t *) & (hw->mng_cookie); 8478 if (em_check_mng_mode(hw)) { 8479 ret_val = em_mng_enable_host_if(hw); 8480 if (ret_val == E1000_SUCCESS) { 8481 ret_val = em_host_if_read_cookie(hw, buffer); 8482 if (ret_val == E1000_SUCCESS) { 8483 checksum = hdr->checksum; 8484 hdr->checksum = 0; 8485 if ((hdr->signature == E1000_IAMT_SIGNATURE) && 8486 checksum == em_calculate_mng_checksum( 8487 (char *) buffer, 8488 E1000_MNG_DHCP_COOKIE_LENGTH)) { 8489 if (hdr->status & 8490 E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT) 8491 tx_filter = TRUE; 8492 } else 8493 tx_filter = TRUE; 8494 } else 8495 tx_filter = TRUE; 8496 } 8497 } 8498 hw->tx_pkt_filtering = tx_filter; 8499 return tx_filter; 8500 } 8501 8502 static int32_t 8503 em_polarity_reversal_workaround(struct em_hw *hw) 8504 { 8505 int32_t ret_val; 8506 uint16_t mii_status_reg; 8507 uint16_t i; 8508 /* Polarity reversal workaround for forced 10F/10H links. */ 8509 8510 /* Disable the transmitter on the PHY */ 8511 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 8512 if (ret_val) 8513 return ret_val; 8514 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF); 8515 if (ret_val) 8516 return ret_val; 8517 8518 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 8519 if (ret_val) 8520 return ret_val; 8521 8522 /* This loop will early-out if the NO link condition has been met. */ 8523 for (i = PHY_FORCE_TIME; i > 0; i--) { 8524 /* 8525 * Read the MII Status Register and wait for Link Status bit 8526 * to be clear. 8527 */ 8528 8529 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 8530 if (ret_val) 8531 return ret_val; 8532 8533 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 8534 if (ret_val) 8535 return ret_val; 8536 8537 if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) 8538 break; 8539 msec_delay_irq(100); 8540 } 8541 8542 /* Recommended delay time after link has been lost */ 8543 msec_delay_irq(1000); 8544 8545 /* Now we will re-enable the transmitter on the PHY */ 8546 8547 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 8548 if (ret_val) 8549 return ret_val; 8550 msec_delay_irq(50); 8551 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0); 8552 if (ret_val) 8553 return ret_val; 8554 msec_delay_irq(50); 8555 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00); 8556 if (ret_val) 8557 return ret_val; 8558 msec_delay_irq(50); 8559 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000); 8560 if (ret_val) 8561 return ret_val; 8562 8563 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 8564 if (ret_val) 8565 return ret_val; 8566 8567 /* This loop will early-out if the link condition has been met. */ 8568 for (i = PHY_FORCE_TIME; i > 0; i--) { 8569 /* 8570 * Read the MII Status Register and wait for Link Status bit 8571 * to be set. 8572 */ 8573 8574 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 8575 if (ret_val) 8576 return ret_val; 8577 8578 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 8579 if (ret_val) 8580 return ret_val; 8581 8582 if (mii_status_reg & MII_SR_LINK_STATUS) 8583 break; 8584 msec_delay_irq(100); 8585 } 8586 return E1000_SUCCESS; 8587 } 8588 8589 /****************************************************************************** 8590 * 8591 * Disables PCI-Express master access. 8592 * 8593 * hw: Struct containing variables accessed by shared code 8594 * 8595 * returns: - none. 8596 * 8597 *****************************************************************************/ 8598 STATIC void 8599 em_set_pci_express_master_disable(struct em_hw *hw) 8600 { 8601 uint32_t ctrl; 8602 DEBUGFUNC("em_set_pci_express_master_disable"); 8603 8604 if (hw->bus_type != em_bus_type_pci_express) 8605 return; 8606 8607 ctrl = E1000_READ_REG(hw, CTRL); 8608 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; 8609 E1000_WRITE_REG(hw, CTRL, ctrl); 8610 } 8611 8612 /****************************************************************************** 8613 * 8614 * Disables PCI-Express master access and verifies there are no pending 8615 * requests 8616 * 8617 * hw: Struct containing variables accessed by shared code 8618 * 8619 * returns: - E1000_ERR_MASTER_REQUESTS_PENDING if master disable bit hasn't 8620 * caused the master requests to be disabled. 8621 * E1000_SUCCESS master requests disabled. 8622 * 8623 ******************************************************************************/ 8624 int32_t 8625 em_disable_pciex_master(struct em_hw *hw) 8626 { 8627 int32_t timeout = MASTER_DISABLE_TIMEOUT; /* 80ms */ 8628 DEBUGFUNC("em_disable_pciex_master"); 8629 8630 if (hw->bus_type != em_bus_type_pci_express) 8631 return E1000_SUCCESS; 8632 8633 em_set_pci_express_master_disable(hw); 8634 8635 while (timeout) { 8636 if (!(E1000_READ_REG(hw, STATUS) & 8637 E1000_STATUS_GIO_MASTER_ENABLE)) 8638 break; 8639 else 8640 usec_delay(100); 8641 timeout--; 8642 } 8643 8644 if (!timeout) { 8645 DEBUGOUT("Master requests are pending.\n"); 8646 return -E1000_ERR_MASTER_REQUESTS_PENDING; 8647 } 8648 return E1000_SUCCESS; 8649 } 8650 8651 /****************************************************************************** 8652 * 8653 * Check for EEPROM Auto Read bit done. 8654 * 8655 * hw: Struct containing variables accessed by shared code 8656 * 8657 * returns: - E1000_ERR_RESET if fail to reset MAC 8658 * E1000_SUCCESS at any other case. 8659 * 8660 ******************************************************************************/ 8661 STATIC int32_t 8662 em_get_auto_rd_done(struct em_hw *hw) 8663 { 8664 int32_t timeout = AUTO_READ_DONE_TIMEOUT; 8665 DEBUGFUNC("em_get_auto_rd_done"); 8666 8667 switch (hw->mac_type) { 8668 default: 8669 msec_delay(5); 8670 break; 8671 case em_82571: 8672 case em_82572: 8673 case em_82573: 8674 case em_82574: 8675 case em_82575: 8676 case em_82580: 8677 case em_80003es2lan: 8678 case em_i210: 8679 case em_i350: 8680 case em_ich8lan: 8681 case em_ich9lan: 8682 case em_ich10lan: 8683 case em_pchlan: 8684 case em_pch2lan: 8685 case em_pch_lpt: 8686 while (timeout) { 8687 if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD) 8688 break; 8689 else 8690 msec_delay(1); 8691 timeout--; 8692 } 8693 8694 if (!timeout) { 8695 DEBUGOUT("Auto read by HW from EEPROM has not" 8696 " completed.\n"); 8697 return -E1000_ERR_RESET; 8698 } 8699 break; 8700 } 8701 /* 8702 * PHY configuration from NVM just starts after EECD_AUTO_RD sets to 8703 * high. Need to wait for PHY configuration completion before 8704 * accessing NVM and PHY. 8705 */ 8706 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) 8707 msec_delay(25); 8708 8709 return E1000_SUCCESS; 8710 } 8711 8712 /*************************************************************************** 8713 * Checks if the PHY configuration is done 8714 * 8715 * hw: Struct containing variables accessed by shared code 8716 * 8717 * returns: - E1000_ERR_RESET if fail to reset MAC 8718 * E1000_SUCCESS at any other case. 8719 * 8720 ***************************************************************************/ 8721 STATIC int32_t 8722 em_get_phy_cfg_done(struct em_hw *hw) 8723 { 8724 int32_t timeout = PHY_CFG_TIMEOUT; 8725 uint32_t cfg_mask = E1000_NVM_CFG_DONE_PORT_0; 8726 DEBUGFUNC("em_get_phy_cfg_done"); 8727 8728 switch (hw->mac_type) { 8729 default: 8730 msec_delay_irq(10); 8731 break; 8732 case em_80003es2lan: 8733 case em_82575: 8734 case em_82580: 8735 case em_i350: 8736 switch (hw->bus_func) { 8737 case 1: 8738 cfg_mask = E1000_NVM_CFG_DONE_PORT_1; 8739 break; 8740 case 2: 8741 cfg_mask = E1000_NVM_CFG_DONE_PORT_2; 8742 break; 8743 case 3: 8744 cfg_mask = E1000_NVM_CFG_DONE_PORT_3; 8745 break; 8746 } 8747 /* FALLTHROUGH */ 8748 case em_82571: 8749 case em_82572: 8750 while (timeout) { 8751 if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask) 8752 break; 8753 else 8754 msec_delay(1); 8755 timeout--; 8756 } 8757 if (!timeout) { 8758 DEBUGOUT("MNG configuration cycle has not completed." 8759 "\n"); 8760 } 8761 break; 8762 } 8763 8764 return E1000_SUCCESS; 8765 } 8766 8767 /*************************************************************************** 8768 * 8769 * Using the combination of SMBI and SWESMBI semaphore bits when resetting 8770 * adapter or Eeprom access. 8771 * 8772 * hw: Struct containing variables accessed by shared code 8773 * 8774 * returns: - E1000_ERR_EEPROM if fail to access EEPROM. 8775 * E1000_SUCCESS at any other case. 8776 * 8777 ***************************************************************************/ 8778 STATIC int32_t 8779 em_get_hw_eeprom_semaphore(struct em_hw *hw) 8780 { 8781 int32_t timeout; 8782 uint32_t swsm; 8783 DEBUGFUNC("em_get_hw_eeprom_semaphore"); 8784 8785 if (!hw->eeprom_semaphore_present) 8786 return E1000_SUCCESS; 8787 8788 if (hw->mac_type == em_80003es2lan) { 8789 /* Get the SW semaphore. */ 8790 if (em_get_software_semaphore(hw) != E1000_SUCCESS) 8791 return -E1000_ERR_EEPROM; 8792 } 8793 /* Get the FW semaphore. */ 8794 timeout = hw->eeprom.word_size + 1; 8795 while (timeout) { 8796 swsm = E1000_READ_REG(hw, SWSM); 8797 swsm |= E1000_SWSM_SWESMBI; 8798 E1000_WRITE_REG(hw, SWSM, swsm); 8799 /* if we managed to set the bit we got the semaphore. */ 8800 swsm = E1000_READ_REG(hw, SWSM); 8801 if (swsm & E1000_SWSM_SWESMBI) 8802 break; 8803 8804 usec_delay(50); 8805 timeout--; 8806 } 8807 8808 if (!timeout) { 8809 /* Release semaphores */ 8810 em_put_hw_eeprom_semaphore(hw); 8811 DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set." 8812 "\n"); 8813 return -E1000_ERR_EEPROM; 8814 } 8815 return E1000_SUCCESS; 8816 } 8817 8818 /*************************************************************************** 8819 * This function clears HW semaphore bits. 8820 * 8821 * hw: Struct containing variables accessed by shared code 8822 * 8823 * returns: - None. 8824 * 8825 ***************************************************************************/ 8826 STATIC void 8827 em_put_hw_eeprom_semaphore(struct em_hw *hw) 8828 { 8829 uint32_t swsm; 8830 DEBUGFUNC("em_put_hw_eeprom_semaphore"); 8831 8832 if (!hw->eeprom_semaphore_present) 8833 return; 8834 8835 swsm = E1000_READ_REG(hw, SWSM); 8836 if (hw->mac_type == em_80003es2lan) { 8837 /* Release both semaphores. */ 8838 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 8839 } else 8840 swsm &= ~(E1000_SWSM_SWESMBI); 8841 E1000_WRITE_REG(hw, SWSM, swsm); 8842 } 8843 8844 /*************************************************************************** 8845 * 8846 * Obtaining software semaphore bit (SMBI) before resetting PHY. 8847 * 8848 * hw: Struct containing variables accessed by shared code 8849 * 8850 * returns: - E1000_ERR_RESET if fail to obtain semaphore. 8851 * E1000_SUCCESS at any other case. 8852 * 8853 ***************************************************************************/ 8854 STATIC int32_t 8855 em_get_software_semaphore(struct em_hw *hw) 8856 { 8857 int32_t timeout = hw->eeprom.word_size + 1; 8858 uint32_t swsm; 8859 DEBUGFUNC("em_get_software_semaphore"); 8860 8861 if (hw->mac_type != em_80003es2lan) 8862 return E1000_SUCCESS; 8863 8864 while (timeout) { 8865 swsm = E1000_READ_REG(hw, SWSM); 8866 /* 8867 * If SMBI bit cleared, it is now set and we hold the 8868 * semaphore 8869 */ 8870 if (!(swsm & E1000_SWSM_SMBI)) 8871 break; 8872 msec_delay_irq(1); 8873 timeout--; 8874 } 8875 8876 if (!timeout) { 8877 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 8878 return -E1000_ERR_RESET; 8879 } 8880 return E1000_SUCCESS; 8881 } 8882 8883 /*************************************************************************** 8884 * 8885 * Release semaphore bit (SMBI). 8886 * 8887 * hw: Struct containing variables accessed by shared code 8888 * 8889 ***************************************************************************/ 8890 STATIC void 8891 em_release_software_semaphore(struct em_hw *hw) 8892 { 8893 uint32_t swsm; 8894 DEBUGFUNC("em_release_software_semaphore"); 8895 8896 if (hw->mac_type != em_80003es2lan) 8897 return; 8898 8899 swsm = E1000_READ_REG(hw, SWSM); 8900 /* Release the SW semaphores. */ 8901 swsm &= ~E1000_SWSM_SMBI; 8902 E1000_WRITE_REG(hw, SWSM, swsm); 8903 } 8904 8905 /****************************************************************************** 8906 * Checks if PHY reset is blocked due to SOL/IDER session, for example. 8907 * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to 8908 * the caller to figure out how to deal with it. 8909 * 8910 * hw - Struct containing variables accessed by shared code 8911 * 8912 * returns: - E1000_BLK_PHY_RESET 8913 * E1000_SUCCESS 8914 * 8915 *****************************************************************************/ 8916 int32_t 8917 em_check_phy_reset_block(struct em_hw *hw) 8918 { 8919 uint32_t manc = 0; 8920 uint32_t fwsm = 0; 8921 if (IS_ICH8(hw->mac_type)) { 8922 fwsm = E1000_READ_REG(hw, FWSM); 8923 return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS : 8924 E1000_BLK_PHY_RESET; 8925 } 8926 if (hw->mac_type > em_82547_rev_2) 8927 manc = E1000_READ_REG(hw, MANC); 8928 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? 8929 E1000_BLK_PHY_RESET : E1000_SUCCESS; 8930 } 8931 8932 /****************************************************************************** 8933 * Configure PCI-Ex no-snoop 8934 * 8935 * hw - Struct containing variables accessed by shared code. 8936 * no_snoop - Bitmap of no-snoop events. 8937 * 8938 * returns: E1000_SUCCESS 8939 * 8940 *****************************************************************************/ 8941 STATIC int32_t 8942 em_set_pci_ex_no_snoop(struct em_hw *hw, uint32_t no_snoop) 8943 { 8944 uint32_t gcr_reg = 0; 8945 DEBUGFUNC("em_set_pci_ex_no_snoop"); 8946 8947 if (hw->bus_type == em_bus_type_unknown) 8948 em_get_bus_info(hw); 8949 8950 if (hw->bus_type != em_bus_type_pci_express) 8951 return E1000_SUCCESS; 8952 8953 if (no_snoop) { 8954 gcr_reg = E1000_READ_REG(hw, GCR); 8955 gcr_reg &= ~(PCI_EX_NO_SNOOP_ALL); 8956 gcr_reg |= no_snoop; 8957 E1000_WRITE_REG(hw, GCR, gcr_reg); 8958 } 8959 if (IS_ICH8(hw->mac_type)) { 8960 uint32_t ctrl_ext; 8961 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 8962 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 8963 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 8964 } 8965 return E1000_SUCCESS; 8966 } 8967 8968 /*************************************************************************** 8969 * 8970 * Get software semaphore FLAG bit (SWFLAG). 8971 * SWFLAG is used to synchronize the access to all shared resource between 8972 * SW, FW and HW. 8973 * 8974 * hw: Struct containing variables accessed by shared code 8975 * 8976 ***************************************************************************/ 8977 STATIC int32_t 8978 em_get_software_flag(struct em_hw *hw) 8979 { 8980 int32_t timeout = PHY_CFG_TIMEOUT; 8981 uint32_t extcnf_ctrl; 8982 DEBUGFUNC("em_get_software_flag"); 8983 8984 if (IS_ICH8(hw->mac_type)) { 8985 while (timeout) { 8986 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 8987 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; 8988 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); 8989 8990 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 8991 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) 8992 break; 8993 msec_delay_irq(1); 8994 timeout--; 8995 } 8996 8997 if (!timeout) { 8998 DEBUGOUT("FW or HW locks the resource too long.\n"); 8999 return -E1000_ERR_CONFIG; 9000 } 9001 } 9002 return E1000_SUCCESS; 9003 } 9004 9005 /*************************************************************************** 9006 * 9007 * Release software semaphore FLAG bit (SWFLAG). 9008 * SWFLAG is used to synchronize the access to all shared resource between 9009 * SW, FW and HW. 9010 * 9011 * hw: Struct containing variables accessed by shared code 9012 * 9013 ***************************************************************************/ 9014 STATIC void 9015 em_release_software_flag(struct em_hw *hw) 9016 { 9017 uint32_t extcnf_ctrl; 9018 DEBUGFUNC("em_release_software_flag"); 9019 9020 if (IS_ICH8(hw->mac_type)) { 9021 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 9022 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 9023 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); 9024 } 9025 return; 9026 } 9027 9028 /** 9029 * em_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1 9030 * @hw: pointer to the HW structure 9031 * @bank: pointer to the variable that returns the active bank 9032 * 9033 * Reads signature byte from the NVM using the flash access registers. 9034 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank. 9035 **/ 9036 int32_t 9037 em_valid_nvm_bank_detect_ich8lan(struct em_hw *hw, uint32_t *bank) 9038 { 9039 uint32_t eecd; 9040 uint32_t bank1_offset = hw->flash_bank_size * sizeof(uint16_t); 9041 uint32_t act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1; 9042 uint8_t sig_byte = 0; 9043 int32_t ret_val; 9044 9045 DEBUGFUNC("em_valid_nvm_bank_detect_ich8lan"); 9046 9047 switch (hw->mac_type) { 9048 case em_ich8lan: 9049 case em_ich9lan: 9050 eecd = E1000_READ_REG(hw, EECD); 9051 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) == 9052 E1000_EECD_SEC1VAL_VALID_MASK) { 9053 if (eecd & E1000_EECD_SEC1VAL) 9054 *bank = 1; 9055 else 9056 *bank = 0; 9057 9058 return E1000_SUCCESS; 9059 } 9060 DEBUGOUT("Unable to determine valid NVM bank via EEC - reading flash signature\n"); 9061 /* fall-thru */ 9062 default: 9063 /* set bank to 0 in case flash read fails */ 9064 *bank = 0; 9065 9066 /* Check bank 0 */ 9067 ret_val = em_read_ich8_byte(hw, act_offset, 9068 &sig_byte); 9069 if (ret_val) 9070 return ret_val; 9071 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 9072 E1000_ICH_NVM_SIG_VALUE) { 9073 *bank = 0; 9074 return E1000_SUCCESS; 9075 } 9076 9077 /* Check bank 1 */ 9078 ret_val = em_read_ich8_byte(hw, act_offset + 9079 bank1_offset, 9080 &sig_byte); 9081 if (ret_val) 9082 return ret_val; 9083 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 9084 E1000_ICH_NVM_SIG_VALUE) { 9085 *bank = 1; 9086 return E1000_SUCCESS; 9087 } 9088 9089 DEBUGOUT("ERROR: No valid NVM bank present\n"); 9090 return -1; 9091 } 9092 } 9093 9094 /****************************************************************************** 9095 * Reads a 16 bit word or words from the EEPROM using the ICH8's flash access 9096 * register. 9097 * 9098 * hw - Struct containing variables accessed by shared code 9099 * offset - offset of word in the EEPROM to read 9100 * data - word read from the EEPROM 9101 * words - number of words to read 9102 *****************************************************************************/ 9103 STATIC int32_t 9104 em_read_eeprom_ich8(struct em_hw *hw, uint16_t offset, uint16_t words, 9105 uint16_t *data) 9106 { 9107 int32_t error = E1000_SUCCESS; 9108 uint32_t flash_bank = 0; 9109 uint32_t act_offset = 0; 9110 uint32_t bank_offset = 0; 9111 uint16_t word = 0; 9112 uint16_t i = 0; 9113 /* 9114 * We need to know which is the valid flash bank. In the event that 9115 * we didn't allocate eeprom_shadow_ram, we may not be managing 9116 * flash_bank. So it cannot be trusted and needs to be updated with 9117 * each read. 9118 */ 9119 9120 error = em_get_software_flag(hw); 9121 if (error != E1000_SUCCESS) 9122 return error; 9123 9124 error = em_valid_nvm_bank_detect_ich8lan(hw, &flash_bank); 9125 if (error != E1000_SUCCESS) { 9126 DEBUGOUT("Could not detect valid bank, assuming bank 0\n"); 9127 flash_bank = 0; 9128 } 9129 9130 /* 9131 * Adjust offset appropriately if we're on bank 1 - adjust for word 9132 * size 9133 */ 9134 bank_offset = flash_bank * (hw->flash_bank_size * 2); 9135 9136 for (i = 0; i < words; i++) { 9137 if (hw->eeprom_shadow_ram != NULL && 9138 hw->eeprom_shadow_ram[offset + i].modified == TRUE) { 9139 data[i] = 9140 hw->eeprom_shadow_ram[offset + i].eeprom_word; 9141 } else { 9142 /* The NVM part needs a byte offset, hence * 2 */ 9143 act_offset = bank_offset + ((offset + i) * 2); 9144 error = em_read_ich8_word(hw, act_offset, &word); 9145 if (error != E1000_SUCCESS) 9146 break; 9147 data[i] = word; 9148 } 9149 } 9150 9151 em_release_software_flag(hw); 9152 9153 return error; 9154 } 9155 9156 /****************************************************************************** 9157 * Writes a 16 bit word or words to the EEPROM using the ICH8's flash access 9158 * register. Actually, writes are written to the shadow ram cache in the hw 9159 * structure hw->em_shadow_ram. em_commit_shadow_ram flushes this to 9160 * the NVM, which occurs when the NVM checksum is updated. 9161 * 9162 * hw - Struct containing variables accessed by shared code 9163 * offset - offset of word in the EEPROM to write 9164 * words - number of words to write 9165 * data - words to write to the EEPROM 9166 *****************************************************************************/ 9167 STATIC int32_t 9168 em_write_eeprom_ich8(struct em_hw *hw, uint16_t offset, uint16_t words, 9169 uint16_t *data) 9170 { 9171 uint32_t i = 0; 9172 int32_t error = E1000_SUCCESS; 9173 error = em_get_software_flag(hw); 9174 if (error != E1000_SUCCESS) 9175 return error; 9176 /* 9177 * A driver can write to the NVM only if it has eeprom_shadow_ram 9178 * allocated. Subsequent reads to the modified words are read from 9179 * this cached structure as well. Writes will only go into this 9180 * cached structure unless it's followed by a call to 9181 * em_update_eeprom_checksum() where it will commit the changes and 9182 * clear the "modified" field. 9183 */ 9184 if (hw->eeprom_shadow_ram != NULL) { 9185 for (i = 0; i < words; i++) { 9186 if ((offset + i) < E1000_SHADOW_RAM_WORDS) { 9187 hw->eeprom_shadow_ram[offset + i].modified = 9188 TRUE; 9189 hw->eeprom_shadow_ram[offset + i].eeprom_word = 9190 data[i]; 9191 } else { 9192 error = -E1000_ERR_EEPROM; 9193 break; 9194 } 9195 } 9196 } else { 9197 /* 9198 * Drivers have the option to not allocate eeprom_shadow_ram 9199 * as long as they don't perform any NVM writes. An attempt 9200 * in doing so will result in this error. 9201 */ 9202 error = -E1000_ERR_EEPROM; 9203 } 9204 9205 em_release_software_flag(hw); 9206 9207 return error; 9208 } 9209 9210 /****************************************************************************** 9211 * This function does initial flash setup so that a new read/write/erase cycle 9212 * can be started. 9213 * 9214 * hw - The pointer to the hw structure 9215 ****************************************************************************/ 9216 STATIC int32_t 9217 em_ich8_cycle_init(struct em_hw *hw) 9218 { 9219 union ich8_hws_flash_status hsfsts; 9220 int32_t error = E1000_ERR_EEPROM; 9221 int32_t i = 0; 9222 DEBUGFUNC("em_ich8_cycle_init"); 9223 9224 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 9225 9226 /* May be check the Flash Des Valid bit in Hw status */ 9227 if (hsfsts.hsf_status.fldesvalid == 0) { 9228 DEBUGOUT("Flash descriptor invalid. SW Sequencing must be" 9229 " used."); 9230 return error; 9231 } 9232 /* Clear FCERR in Hw status by writing 1 */ 9233 /* Clear DAEL in Hw status by writing a 1 */ 9234 hsfsts.hsf_status.flcerr = 1; 9235 hsfsts.hsf_status.dael = 1; 9236 9237 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval); 9238 /* 9239 * Either we should have a hardware SPI cycle in progress bit to 9240 * check against, in order to start a new cycle or FDONE bit should 9241 * be changed in the hardware so that it is 1 after harware reset, 9242 * which can then be used as an indication whether a cycle is in 9243 * progress or has been completed .. we should also have some 9244 * software semaphore mechanism to guard FDONE or the cycle in 9245 * progress bit so that two threads access to those bits can be 9246 * sequentiallized or a way so that 2 threads dont start the cycle at 9247 * the same time 9248 */ 9249 9250 if (hsfsts.hsf_status.flcinprog == 0) { 9251 /* 9252 * There is no cycle running at present, so we can start a 9253 * cycle 9254 */ 9255 /* Begin by setting Flash Cycle Done. */ 9256 hsfsts.hsf_status.flcdone = 1; 9257 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, 9258 hsfsts.regval); 9259 error = E1000_SUCCESS; 9260 } else { 9261 /* 9262 * otherwise poll for sometime so the current cycle has a 9263 * chance to end before giving up. 9264 */ 9265 for (i = 0; i < ICH_FLASH_COMMAND_TIMEOUT; i++) { 9266 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, 9267 ICH_FLASH_HSFSTS); 9268 if (hsfsts.hsf_status.flcinprog == 0) { 9269 error = E1000_SUCCESS; 9270 break; 9271 } 9272 usec_delay(1); 9273 } 9274 if (error == E1000_SUCCESS) { 9275 /* 9276 * Successful in waiting for previous cycle to 9277 * timeout, now set the Flash Cycle Done. 9278 */ 9279 hsfsts.hsf_status.flcdone = 1; 9280 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, 9281 hsfsts.regval); 9282 } else { 9283 DEBUGOUT("Flash controller busy, cannot get access"); 9284 } 9285 } 9286 return error; 9287 } 9288 9289 /****************************************************************************** 9290 * This function starts a flash cycle and waits for its completion 9291 * 9292 * hw - The pointer to the hw structure 9293 *****************************************************************************/ 9294 STATIC int32_t 9295 em_ich8_flash_cycle(struct em_hw *hw, uint32_t timeout) 9296 { 9297 union ich8_hws_flash_ctrl hsflctl; 9298 union ich8_hws_flash_status hsfsts; 9299 int32_t error = E1000_ERR_EEPROM; 9300 uint32_t i = 0; 9301 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ 9302 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL); 9303 hsflctl.hsf_ctrl.flcgo = 1; 9304 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); 9305 9306 /* wait till FDONE bit is set to 1 */ 9307 do { 9308 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, 9309 ICH_FLASH_HSFSTS); 9310 if (hsfsts.hsf_status.flcdone == 1) 9311 break; 9312 usec_delay(1); 9313 i++; 9314 } while (i < timeout); 9315 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) { 9316 error = E1000_SUCCESS; 9317 } 9318 return error; 9319 } 9320 9321 /****************************************************************************** 9322 * Reads a byte or word from the NVM using the ICH8 flash access registers. 9323 * 9324 * hw - The pointer to the hw structure 9325 * index - The index of the byte or word to read. 9326 * size - Size of data to read, 1=byte 2=word 9327 * data - Pointer to the word to store the value read. 9328 *****************************************************************************/ 9329 STATIC int32_t 9330 em_read_ich8_data(struct em_hw *hw, uint32_t index, uint32_t size, 9331 uint16_t *data) 9332 { 9333 union ich8_hws_flash_status hsfsts; 9334 union ich8_hws_flash_ctrl hsflctl; 9335 uint32_t flash_linear_address; 9336 uint32_t flash_data = 0; 9337 int32_t error = -E1000_ERR_EEPROM; 9338 int32_t count = 0; 9339 DEBUGFUNC("em_read_ich8_data"); 9340 9341 if (size < 1 || size > 2 || data == 0x0 || 9342 index > ICH_FLASH_LINEAR_ADDR_MASK) 9343 return error; 9344 9345 flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) + 9346 hw->flash_base_addr; 9347 9348 do { 9349 usec_delay(1); 9350 /* Steps */ 9351 error = em_ich8_cycle_init(hw); 9352 if (error != E1000_SUCCESS) 9353 break; 9354 9355 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, 9356 ICH_FLASH_HSFCTL); 9357 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 9358 hsflctl.hsf_ctrl.fldbcount = size - 1; 9359 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; 9360 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, 9361 hsflctl.regval); 9362 /* 9363 * Write the last 24 bits of index into Flash Linear address 9364 * field in Flash Address 9365 */ 9366 /* TODO: TBD maybe check the index against the size of flash */ 9367 9368 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, 9369 flash_linear_address); 9370 9371 error = em_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT); 9372 /* 9373 * Check if FCERR is set to 1, if set to 1, clear it and try 9374 * the whole sequence a few more times, else read in (shift 9375 * in) the Flash Data0, the order is least significant byte 9376 * first msb to lsb 9377 */ 9378 if (error == E1000_SUCCESS) { 9379 flash_data = E1000_READ_ICH_FLASH_REG(hw, 9380 ICH_FLASH_FDATA0); 9381 if (size == 1) { 9382 *data = (uint8_t) (flash_data & 0x000000FF); 9383 } else if (size == 2) { 9384 *data = (uint16_t) (flash_data & 0x0000FFFF); 9385 } 9386 break; 9387 } else { 9388 /* 9389 * If we've gotten here, then things are probably 9390 * completely hosed, but if the error condition is 9391 * detected, it won't hurt to give it another 9392 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 9393 */ 9394 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, 9395 ICH_FLASH_HSFSTS); 9396 if (hsfsts.hsf_status.flcerr == 1) { 9397 /* Repeat for some time before giving up. */ 9398 continue; 9399 } else if (hsfsts.hsf_status.flcdone == 0) { 9400 DEBUGOUT("Timeout error - flash cycle did not" 9401 " complete."); 9402 break; 9403 } 9404 } 9405 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 9406 9407 return error; 9408 } 9409 9410 /****************************************************************************** 9411 * Writes One /two bytes to the NVM using the ICH8 flash access registers. 9412 * 9413 * hw - The pointer to the hw structure 9414 * index - The index of the byte/word to read. 9415 * size - Size of data to read, 1=byte 2=word 9416 * data - The byte(s) to write to the NVM. 9417 *****************************************************************************/ 9418 STATIC int32_t 9419 em_write_ich8_data(struct em_hw *hw, uint32_t index, uint32_t size, 9420 uint16_t data) 9421 { 9422 union ich8_hws_flash_status hsfsts; 9423 union ich8_hws_flash_ctrl hsflctl; 9424 uint32_t flash_linear_address; 9425 uint32_t flash_data = 0; 9426 int32_t error = -E1000_ERR_EEPROM; 9427 int32_t count = 0; 9428 DEBUGFUNC("em_write_ich8_data"); 9429 9430 if (size < 1 || size > 2 || data > size * 0xff || 9431 index > ICH_FLASH_LINEAR_ADDR_MASK) 9432 return error; 9433 9434 flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) + 9435 hw->flash_base_addr; 9436 9437 do { 9438 usec_delay(1); 9439 /* Steps */ 9440 error = em_ich8_cycle_init(hw); 9441 if (error != E1000_SUCCESS) 9442 break; 9443 9444 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, 9445 ICH_FLASH_HSFCTL); 9446 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 9447 hsflctl.hsf_ctrl.fldbcount = size - 1; 9448 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; 9449 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, 9450 hsflctl.regval); 9451 /* 9452 * Write the last 24 bits of index into Flash Linear address 9453 * field in Flash Address 9454 */ 9455 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, 9456 flash_linear_address); 9457 9458 if (size == 1) 9459 flash_data = (uint32_t) data & 0x00FF; 9460 else 9461 flash_data = (uint32_t) data; 9462 9463 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data); 9464 /* 9465 * check if FCERR is set to 1 , if set to 1, clear it and try 9466 * the whole sequence a few more times else done 9467 */ 9468 error = em_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT); 9469 if (error == E1000_SUCCESS) { 9470 break; 9471 } else { 9472 /* 9473 * If we're here, then things are most likely 9474 * completely hosed, but if the error condition is 9475 * detected, it won't hurt to give it another 9476 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 9477 */ 9478 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, 9479 ICH_FLASH_HSFSTS); 9480 if (hsfsts.hsf_status.flcerr == 1) { 9481 /* Repeat for some time before giving up. */ 9482 continue; 9483 } else if (hsfsts.hsf_status.flcdone == 0) { 9484 DEBUGOUT("Timeout error - flash cycle did not" 9485 " complete."); 9486 break; 9487 } 9488 } 9489 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 9490 9491 return error; 9492 } 9493 9494 /****************************************************************************** 9495 * Reads a single byte from the NVM using the ICH8 flash access registers. 9496 * 9497 * hw - pointer to em_hw structure 9498 * index - The index of the byte to read. 9499 * data - Pointer to a byte to store the value read. 9500 *****************************************************************************/ 9501 STATIC int32_t 9502 em_read_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t *data) 9503 { 9504 int32_t status = E1000_SUCCESS; 9505 uint16_t word = 0; 9506 status = em_read_ich8_data(hw, index, 1, &word); 9507 if (status == E1000_SUCCESS) { 9508 *data = (uint8_t) word; 9509 } 9510 return status; 9511 } 9512 9513 /****************************************************************************** 9514 * Writes a single byte to the NVM using the ICH8 flash access registers. 9515 * Performs verification by reading back the value and then going through 9516 * a retry algorithm before giving up. 9517 * 9518 * hw - pointer to em_hw structure 9519 * index - The index of the byte to write. 9520 * byte - The byte to write to the NVM. 9521 *****************************************************************************/ 9522 STATIC int32_t 9523 em_verify_write_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t byte) 9524 { 9525 int32_t error = E1000_SUCCESS; 9526 int32_t program_retries = 0; 9527 DEBUGOUT2("Byte := %2.2X Offset := %d\n", byte, index); 9528 9529 error = em_write_ich8_byte(hw, index, byte); 9530 9531 if (error != E1000_SUCCESS) { 9532 for (program_retries = 0; program_retries < 100; 9533 program_retries++) { 9534 DEBUGOUT2("Retrying \t Byte := %2.2X Offset := %d\n", 9535 byte, index); 9536 error = em_write_ich8_byte(hw, index, byte); 9537 usec_delay(100); 9538 if (error == E1000_SUCCESS) 9539 break; 9540 } 9541 } 9542 if (program_retries == 100) 9543 error = E1000_ERR_EEPROM; 9544 9545 return error; 9546 } 9547 9548 /****************************************************************************** 9549 * Writes a single byte to the NVM using the ICH8 flash access registers. 9550 * 9551 * hw - pointer to em_hw structure 9552 * index - The index of the byte to read. 9553 * data - The byte to write to the NVM. 9554 *****************************************************************************/ 9555 STATIC int32_t 9556 em_write_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t data) 9557 { 9558 int32_t status = E1000_SUCCESS; 9559 uint16_t word = (uint16_t) data; 9560 status = em_write_ich8_data(hw, index, 1, word); 9561 9562 return status; 9563 } 9564 9565 /****************************************************************************** 9566 * Reads a word from the NVM using the ICH8 flash access registers. 9567 * 9568 * hw - pointer to em_hw structure 9569 * index - The starting byte index of the word to read. 9570 * data - Pointer to a word to store the value read. 9571 *****************************************************************************/ 9572 STATIC int32_t 9573 em_read_ich8_word(struct em_hw *hw, uint32_t index, uint16_t *data) 9574 { 9575 int32_t status = E1000_SUCCESS; 9576 status = em_read_ich8_data(hw, index, 2, data); 9577 return status; 9578 } 9579 9580 /****************************************************************************** 9581 * Erases the bank specified. Each bank may be a 4, 8 or 64k block. Banks are 0 9582 * based. 9583 * 9584 * hw - pointer to em_hw structure 9585 * bank - 0 for first bank, 1 for second bank 9586 * 9587 * Note that this function may actually erase as much as 8 or 64 KBytes. The 9588 * amount of NVM used in each bank is a *minimum* of 4 KBytes, but in fact the 9589 * bank size may be 4, 8 or 64 KBytes 9590 *****************************************************************************/ 9591 int32_t 9592 em_erase_ich8_4k_segment(struct em_hw *hw, uint32_t bank) 9593 { 9594 union ich8_hws_flash_status hsfsts; 9595 union ich8_hws_flash_ctrl hsflctl; 9596 uint32_t flash_linear_address; 9597 int32_t count = 0; 9598 int32_t error = E1000_ERR_EEPROM; 9599 int32_t iteration; 9600 int32_t sub_sector_size = 0; 9601 int32_t bank_size; 9602 int32_t j = 0; 9603 int32_t error_flag = 0; 9604 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 9605 /* 9606 * Determine HW Sector size: Read BERASE bits of Hw flash Status 9607 * register 9608 */ 9609 /* 9610 * 00: The Hw sector is 256 bytes, hence we need to erase 16 9611 * consecutive sectors. The start index for the nth Hw sector can be 9612 * calculated as bank * 4096 + n * 256 01: The Hw sector is 4K bytes, 9613 * hence we need to erase 1 sector. The start index for the nth Hw 9614 * sector can be calculated as bank * 4096 10: The HW sector is 8K 9615 * bytes 11: The Hw sector size is 64K bytes 9616 */ 9617 if (hsfsts.hsf_status.berasesz == 0x0) { 9618 /* Hw sector size 256 */ 9619 sub_sector_size = ICH_FLASH_SEG_SIZE_256; 9620 bank_size = ICH_FLASH_SECTOR_SIZE; 9621 iteration = ICH_FLASH_SECTOR_SIZE / ICH_FLASH_SEG_SIZE_256; 9622 } else if (hsfsts.hsf_status.berasesz == 0x1) { 9623 bank_size = ICH_FLASH_SEG_SIZE_4K; 9624 iteration = 1; 9625 } else if (hsfsts.hsf_status.berasesz == 0x2) { 9626 if (hw->mac_type == em_ich9lan) { 9627 uint32_t gfpreg, sector_base_addr, sector_end_addr; 9628 gfpreg = E1000_READ_ICH_FLASH_REG(hw, 9629 ICH_FLASH_GFPREG); 9630 /* 9631 * sector_X_addr is a "sector"-aligned address (4096 bytes) 9632 * Add 1 to sector_end_addr since this sector is included in 9633 * the overall size. 9634 */ 9635 sector_base_addr = gfpreg & ICH_GFPREG_BASE_MASK; 9636 sector_end_addr = 9637 ((gfpreg >> 16) & ICH_GFPREG_BASE_MASK) + 1; 9638 9639 /* 9640 * find total size of the NVM, then cut in half since the total 9641 * size represents two separate NVM banks. 9642 */ 9643 bank_size = (sector_end_addr - sector_base_addr) 9644 << ICH_FLASH_SECT_ADDR_SHIFT; 9645 bank_size /= 2; 9646 /* Word align */ 9647 bank_size = 9648 (bank_size / sizeof(uint16_t)) * sizeof(uint16_t); 9649 9650 sub_sector_size = ICH_FLASH_SEG_SIZE_8K; 9651 iteration = bank_size / ICH_FLASH_SEG_SIZE_8K; 9652 } else { 9653 return error; 9654 } 9655 } else if (hsfsts.hsf_status.berasesz == 0x3) { 9656 bank_size = ICH_FLASH_SEG_SIZE_64K; 9657 iteration = 1; 9658 } else { 9659 return error; 9660 } 9661 9662 for (j = 0; j < iteration; j++) { 9663 do { 9664 count++; 9665 /* Steps */ 9666 error = em_ich8_cycle_init(hw); 9667 if (error != E1000_SUCCESS) { 9668 error_flag = 1; 9669 break; 9670 } 9671 /* 9672 * Write a value 11 (block Erase) in Flash Cycle 9673 * field in Hw flash Control 9674 */ 9675 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, 9676 ICH_FLASH_HSFCTL); 9677 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE; 9678 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, 9679 hsflctl.regval); 9680 /* 9681 * Write the last 24 bits of an index within the 9682 * block into Flash Linear address field in Flash 9683 * Address. This probably needs to be calculated 9684 * here based off the on-chip erase sector size and 9685 * the software bank size (4, 8 or 64 KBytes) 9686 */ 9687 flash_linear_address = 9688 bank * bank_size + j * sub_sector_size; 9689 flash_linear_address += hw->flash_base_addr; 9690 flash_linear_address &= ICH_FLASH_LINEAR_ADDR_MASK; 9691 9692 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, 9693 flash_linear_address); 9694 9695 error = 9696 em_ich8_flash_cycle(hw, ICH_FLASH_ERASE_TIMEOUT); 9697 /* 9698 * Check if FCERR is set to 1. If 1, clear it and 9699 * try the whole sequence a few more times else Done 9700 */ 9701 if (error == E1000_SUCCESS) { 9702 break; 9703 } else { 9704 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, 9705 ICH_FLASH_HSFSTS); 9706 if (hsfsts.hsf_status.flcerr == 1) { 9707 /* 9708 * repeat for some time before giving 9709 * up 9710 */ 9711 continue; 9712 } else if (hsfsts.hsf_status.flcdone == 0) { 9713 error_flag = 1; 9714 break; 9715 } 9716 } 9717 } while ((count < ICH_FLASH_CYCLE_REPEAT_COUNT) && !error_flag); 9718 if (error_flag == 1) 9719 break; 9720 } 9721 if (error_flag != 1) 9722 error = E1000_SUCCESS; 9723 return error; 9724 } 9725 9726 STATIC int32_t 9727 em_init_lcd_from_nvm_config_region(struct em_hw *hw, uint32_t cnf_base_addr, 9728 uint32_t cnf_size) 9729 { 9730 uint32_t ret_val = E1000_SUCCESS; 9731 uint16_t word_addr, reg_data, reg_addr; 9732 uint16_t i; 9733 /* cnf_base_addr is in DWORD */ 9734 word_addr = (uint16_t) (cnf_base_addr << 1); 9735 9736 /* cnf_size is returned in size of dwords */ 9737 for (i = 0; i < cnf_size; i++) { 9738 ret_val = 9739 em_read_eeprom(hw, (word_addr + i * 2), 1, ®_data); 9740 if (ret_val) 9741 return ret_val; 9742 9743 ret_val = 9744 em_read_eeprom(hw, (word_addr + i * 2 + 1), 1, ®_addr); 9745 if (ret_val) 9746 return ret_val; 9747 9748 ret_val = em_get_software_flag(hw); 9749 if (ret_val != E1000_SUCCESS) 9750 return ret_val; 9751 9752 ret_val = 9753 em_write_phy_reg_ex(hw, (uint32_t) reg_addr, reg_data); 9754 9755 em_release_software_flag(hw); 9756 } 9757 9758 return ret_val; 9759 } 9760 9761 /****************************************************************************** 9762 * This function initializes the PHY from the NVM on ICH8 platforms. This 9763 * is needed due to an issue where the NVM configuration is not properly 9764 * autoloaded after power transitions. Therefore, after each PHY reset, we 9765 * will load the configuration data out of the NVM manually. 9766 * 9767 * hw: Struct containing variables accessed by shared code 9768 *****************************************************************************/ 9769 STATIC int32_t 9770 em_init_lcd_from_nvm(struct em_hw *hw) 9771 { 9772 uint32_t reg_data, cnf_base_addr, cnf_size, ret_val, loop, sw_cfg_mask; 9773 if (hw->phy_type != em_phy_igp_3) 9774 return E1000_SUCCESS; 9775 9776 /* Check if SW needs configure the PHY */ 9777 if (hw->device_id == E1000_DEV_ID_ICH8_IGP_M_AMT || 9778 hw->device_id == E1000_DEV_ID_ICH8_IGP_M || 9779 hw->mac_type == em_pchlan || 9780 hw->mac_type == em_pch2lan || 9781 hw->mac_type == em_pch_lpt) 9782 sw_cfg_mask = FEXTNVM_SW_CONFIG_ICH8M; 9783 else 9784 sw_cfg_mask = FEXTNVM_SW_CONFIG; 9785 9786 reg_data = E1000_READ_REG(hw, FEXTNVM); 9787 if (!(reg_data & sw_cfg_mask)) 9788 return E1000_SUCCESS; 9789 9790 /* Wait for basic configuration completes before proceeding */ 9791 loop = 0; 9792 do { 9793 reg_data = 9794 E1000_READ_REG(hw, STATUS) & E1000_STATUS_LAN_INIT_DONE; 9795 usec_delay(100); 9796 loop++; 9797 } while ((!reg_data) && (loop < 50)); 9798 9799 /* Clear the Init Done bit for the next init event */ 9800 reg_data = E1000_READ_REG(hw, STATUS); 9801 reg_data &= ~E1000_STATUS_LAN_INIT_DONE; 9802 E1000_WRITE_REG(hw, STATUS, reg_data); 9803 /* 9804 * Make sure HW does not configure LCD from PHY extended 9805 * configuration before SW configuration 9806 */ 9807 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL); 9808 if ((reg_data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) == 0x0000) { 9809 reg_data = E1000_READ_REG(hw, EXTCNF_SIZE); 9810 cnf_size = reg_data & E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH; 9811 cnf_size >>= 16; 9812 if (cnf_size) { 9813 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL); 9814 cnf_base_addr = reg_data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER; 9815 /* cnf_base_addr is in DWORD */ 9816 cnf_base_addr >>= 16; 9817 9818 /* Configure LCD from extended configuration region. */ 9819 ret_val = em_init_lcd_from_nvm_config_region(hw, 9820 cnf_base_addr, cnf_size); 9821 if (ret_val) 9822 return ret_val; 9823 } 9824 } 9825 return E1000_SUCCESS; 9826 } 9827 9828 /****************************************************************************** 9829 * em_set_pciex_completion_timeout - set pci-e completion timeout 9830 * 9831 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms, 9832 * however the hardware default for these parts is 500us to 1ms which is less 9833 * than the 10ms recommended by the pci-e spec. To address this we need to 9834 * increase the value to either 10ms to 200ms for capability version 1 config, 9835 * or 16ms to 55ms for version 2. 9836 * 9837 * * hw - pointer to em_hw structure 9838 *****************************************************************************/ 9839 int32_t 9840 em_set_pciex_completion_timeout(struct em_hw *hw) 9841 { 9842 uint32_t gcr = E1000_READ_REG(hw, GCR); 9843 int32_t ret_val = E1000_SUCCESS; 9844 9845 /* Only take action if timeout value is not set by system BIOS */ 9846 if (gcr & E1000_GCR_CMPL_TMOUT_MASK) 9847 goto out; 9848 9849 DEBUGOUT("PCIe completion timeout not set by system BIOS."); 9850 9851 /* 9852 * If capababilities version is type 1 we can write the 9853 * timeout of 10ms to 200ms through the GCR register 9854 */ 9855 9856 if (!(gcr & E1000_GCR_CAP_VER2)) { 9857 gcr |= E1000_GCR_CMPL_TMOUT_10ms; 9858 DEBUGOUT("PCIe capability version 1 detected, setting \ 9859 completion timeout to 10ms."); 9860 goto out; 9861 } 9862 9863 /* 9864 * For version 2 capabilities we need to write the config space 9865 * directly in order to set the completion timeout value for 9866 * 16ms to 55ms 9867 * 9868 * XXX: Implement em_*_pcie_cap_reg() first. 9869 */ 9870 #if 0 9871 ret_val = em_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 9872 &pciex_devctl2); 9873 9874 if (ret_val) 9875 goto out; 9876 9877 pciex_devctl2 |= PCIE_DEVICE_CONTROL2_16ms; 9878 9879 ret_val = em_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 9880 &pciex_devctl2); 9881 #endif 9882 9883 out: 9884 9885 /* Disable completion timeout resend */ 9886 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND; 9887 9888 DEBUGOUT("PCIe completion timeout resend disabled."); 9889 9890 E1000_WRITE_REG(hw, GCR, gcr); 9891 return ret_val; 9892 } 9893 9894 /*************************************************************************** 9895 * Set slow MDIO access mode 9896 ***************************************************************************/ 9897 static int32_t 9898 em_set_mdio_slow_mode_hv(struct em_hw *hw) 9899 { 9900 int32_t ret_val; 9901 uint16_t data; 9902 DEBUGFUNC("em_set_mdio_slow_mode_hv"); 9903 9904 ret_val = em_read_phy_reg(hw, HV_KMRN_MODE_CTRL, &data); 9905 if (ret_val) 9906 return ret_val; 9907 9908 data |= HV_KMRN_MDIO_SLOW; 9909 9910 ret_val = em_write_phy_reg(hw, HV_KMRN_MODE_CTRL, data); 9911 9912 return ret_val; 9913 } 9914 9915 /*************************************************************************** 9916 * A series of Phy workarounds to be done after every PHY reset. 9917 ***************************************************************************/ 9918 int32_t 9919 em_hv_phy_workarounds_ich8lan(struct em_hw *hw) 9920 { 9921 int32_t ret_val = E1000_SUCCESS; 9922 uint16_t phy_data; 9923 uint16_t swfw; 9924 DEBUGFUNC("em_hv_phy_workarounds_ich8lan"); 9925 9926 if (hw->mac_type != em_pchlan) 9927 goto out; 9928 9929 swfw = E1000_SWFW_PHY0_SM; 9930 9931 /* Set MDIO slow mode before any other MDIO access */ 9932 if (hw->phy_type == em_phy_82577 || 9933 hw->phy_type == em_phy_82578) { 9934 ret_val = em_set_mdio_slow_mode_hv(hw); 9935 if (ret_val) 9936 goto out; 9937 } 9938 9939 /* Hanksville M Phy init for IEEE. */ 9940 if ((hw->revision_id == 2) && 9941 (hw->phy_type == em_phy_82577) && 9942 ((hw->phy_revision == 2) || (hw->phy_revision == 3))) { 9943 em_write_phy_reg(hw, 0x10, 0x8823); 9944 em_write_phy_reg(hw, 0x11, 0x0018); 9945 em_write_phy_reg(hw, 0x10, 0x8824); 9946 em_write_phy_reg(hw, 0x11, 0x0016); 9947 em_write_phy_reg(hw, 0x10, 0x8825); 9948 em_write_phy_reg(hw, 0x11, 0x001A); 9949 em_write_phy_reg(hw, 0x10, 0x888C); 9950 em_write_phy_reg(hw, 0x11, 0x0007); 9951 em_write_phy_reg(hw, 0x10, 0x888D); 9952 em_write_phy_reg(hw, 0x11, 0x0007); 9953 em_write_phy_reg(hw, 0x10, 0x888E); 9954 em_write_phy_reg(hw, 0x11, 0x0007); 9955 em_write_phy_reg(hw, 0x10, 0x8827); 9956 em_write_phy_reg(hw, 0x11, 0x0001); 9957 em_write_phy_reg(hw, 0x10, 0x8835); 9958 em_write_phy_reg(hw, 0x11, 0x0001); 9959 em_write_phy_reg(hw, 0x10, 0x8834); 9960 em_write_phy_reg(hw, 0x11, 0x0001); 9961 em_write_phy_reg(hw, 0x10, 0x8833); 9962 em_write_phy_reg(hw, 0x11, 0x0002); 9963 } 9964 9965 if (((hw->phy_type == em_phy_82577) && 9966 ((hw->phy_revision == 1) || (hw->phy_revision == 2))) || 9967 ((hw->phy_type == em_phy_82578) && (hw->phy_revision == 1))) { 9968 /* Disable generation of early preamble */ 9969 ret_val = em_write_phy_reg(hw, PHY_REG(769, 25), 0x4431); 9970 if (ret_val) 9971 goto out; 9972 9973 /* Preamble tuning for SSC */ 9974 ret_val = em_write_phy_reg(hw, PHY_REG(770, 16), 0xA204); 9975 if (ret_val) 9976 goto out; 9977 } 9978 9979 if (hw->phy_type == em_phy_82578) { 9980 /* 9981 * Return registers to default by doing a soft reset then 9982 * writing 0x3140 to the control register. 9983 */ 9984 if (hw->phy_revision < 2) { 9985 em_phy_reset(hw); 9986 ret_val = em_write_phy_reg(hw, PHY_CTRL, 0x3140); 9987 } 9988 } 9989 9990 if ((hw->revision_id == 2) && 9991 (hw->phy_type == em_phy_82577) && 9992 ((hw->phy_revision == 2) || (hw->phy_revision == 3))) { 9993 /* 9994 * Workaround for OEM (GbE) not operating after reset - 9995 * restart AN (twice) 9996 */ 9997 ret_val = em_write_phy_reg(hw, PHY_REG(0, 25), 0x0400); 9998 if (ret_val) 9999 goto out; 10000 ret_val = em_write_phy_reg(hw, PHY_REG(0, 25), 0x0400); 10001 if (ret_val) 10002 goto out; 10003 } 10004 10005 /* Select page 0 */ 10006 ret_val = em_swfw_sync_acquire(hw, swfw); 10007 if (ret_val) 10008 goto out; 10009 10010 hw->phy_addr = 1; 10011 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT, 0); 10012 em_swfw_sync_release(hw, swfw); 10013 if (ret_val) 10014 goto out; 10015 10016 /* Workaround for link disconnects on a busy hub in half duplex */ 10017 ret_val = em_read_phy_reg(hw, 10018 PHY_REG(BM_PORT_CTRL_PAGE, 17), 10019 &phy_data); 10020 if (ret_val) 10021 goto release; 10022 ret_val = em_write_phy_reg(hw, 10023 PHY_REG(BM_PORT_CTRL_PAGE, 17), 10024 phy_data & 0x00FF); 10025 release: 10026 out: 10027 return ret_val; 10028 } 10029 10030 10031 /*************************************************************************** 10032 * Si workaround 10033 * 10034 * This function works around a Si bug where the link partner can get 10035 * a link up indication before the PHY does. If small packets are sent 10036 * by the link partner they can be placed in the packet buffer without 10037 * being properly accounted for by the PHY and will stall preventing 10038 * further packets from being received. The workaround is to clear the 10039 * packet buffer after the PHY detects link up. 10040 ***************************************************************************/ 10041 int32_t 10042 em_link_stall_workaround_hv(struct em_hw *hw) 10043 { 10044 int32_t ret_val = E1000_SUCCESS; 10045 uint16_t phy_data; 10046 10047 if (hw->phy_type != em_phy_82578) 10048 goto out; 10049 10050 /* Do not apply workaround if in PHY loopback bit 14 set */ 10051 em_read_phy_reg(hw, PHY_CTRL, &phy_data); 10052 if (phy_data & E1000_PHY_CTRL_LOOPBACK) 10053 goto out; 10054 10055 /* check if link is up and at 1Gbps */ 10056 ret_val = em_read_phy_reg(hw, BM_CS_STATUS, &phy_data); 10057 if (ret_val) 10058 goto out; 10059 10060 phy_data &= BM_CS_STATUS_LINK_UP | 10061 BM_CS_STATUS_RESOLVED | 10062 BM_CS_STATUS_SPEED_MASK; 10063 10064 if (phy_data != (BM_CS_STATUS_LINK_UP | 10065 BM_CS_STATUS_RESOLVED | 10066 BM_CS_STATUS_SPEED_1000)) 10067 goto out; 10068 10069 msec_delay(200); 10070 10071 /* flush the packets in the fifo buffer */ 10072 ret_val = em_write_phy_reg(hw, HV_MUX_DATA_CTRL, 10073 HV_MUX_DATA_CTRL_GEN_TO_MAC | HV_MUX_DATA_CTRL_FORCE_SPEED); 10074 if (ret_val) 10075 goto out; 10076 10077 ret_val = em_write_phy_reg(hw, HV_MUX_DATA_CTRL, 10078 HV_MUX_DATA_CTRL_GEN_TO_MAC); 10079 10080 out: 10081 return ret_val; 10082 } 10083 10084 /**************************************************************************** 10085 * K1 Si workaround 10086 * 10087 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning 10088 * from a lower speed. This workaround disables K1 whenever link is at 1Gig. 10089 * If link is down, the function will restore the default K1 setting located 10090 * in the NVM. 10091 ****************************************************************************/ 10092 int32_t 10093 em_k1_gig_workaround_hv(struct em_hw *hw, boolean_t link) 10094 { 10095 int32_t ret_val; 10096 uint16_t phy_data; 10097 boolean_t k1_enable; 10098 10099 DEBUGFUNC("em_k1_gig_workaround_hv"); 10100 10101 if (hw->mac_type != em_pchlan) 10102 return E1000_SUCCESS; 10103 10104 ret_val = em_read_eeprom_ich8(hw, E1000_NVM_K1_CONFIG, 1, &phy_data); 10105 if (ret_val) 10106 return ret_val; 10107 10108 k1_enable = phy_data & E1000_NVM_K1_ENABLE ? TRUE : FALSE; 10109 10110 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */ 10111 if (link) { 10112 if (hw->phy_type == em_phy_82578) { 10113 ret_val = em_read_phy_reg(hw, BM_CS_STATUS, 10114 &phy_data); 10115 if (ret_val) 10116 return ret_val; 10117 10118 phy_data &= BM_CS_STATUS_LINK_UP | 10119 BM_CS_STATUS_RESOLVED | 10120 BM_CS_STATUS_SPEED_MASK; 10121 10122 if (phy_data == (BM_CS_STATUS_LINK_UP | 10123 BM_CS_STATUS_RESOLVED | 10124 BM_CS_STATUS_SPEED_1000)) 10125 k1_enable = FALSE; 10126 } 10127 10128 if (hw->phy_type == em_phy_82577) { 10129 ret_val = em_read_phy_reg(hw, HV_M_STATUS, 10130 &phy_data); 10131 if (ret_val) 10132 return ret_val; 10133 10134 phy_data &= HV_M_STATUS_LINK_UP | 10135 HV_M_STATUS_AUTONEG_COMPLETE | 10136 HV_M_STATUS_SPEED_MASK; 10137 10138 if (phy_data == (HV_M_STATUS_LINK_UP | 10139 HV_M_STATUS_AUTONEG_COMPLETE | 10140 HV_M_STATUS_SPEED_1000)) 10141 k1_enable = FALSE; 10142 } 10143 10144 /* Link stall fix for link up */ 10145 ret_val = em_write_phy_reg(hw, PHY_REG(770, 19), 10146 0x0100); 10147 if (ret_val) 10148 return ret_val; 10149 10150 } else { 10151 /* Link stall fix for link down */ 10152 ret_val = em_write_phy_reg(hw, PHY_REG(770, 19), 10153 0x4100); 10154 if (ret_val) 10155 return ret_val; 10156 } 10157 10158 ret_val = em_configure_k1_ich8lan(hw, k1_enable); 10159 10160 return ret_val; 10161 } 10162 10163 /* Workaround to set the K1 beacon duration for 82579 parts */ 10164 int32_t 10165 em_k1_workaround_lv(struct em_hw *hw) 10166 { 10167 int32_t ret_val; 10168 uint16_t phy_data; 10169 uint32_t mac_reg; 10170 10171 ret_val = em_read_phy_reg(hw, BM_CS_STATUS, &phy_data); 10172 if (ret_val) 10173 return ret_val; 10174 10175 if ((phy_data & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) 10176 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) { 10177 mac_reg = E1000_READ_REG(hw, FEXTNVM4); 10178 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK; 10179 10180 if (phy_data & HV_M_STATUS_SPEED_1000) 10181 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC; 10182 else 10183 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC; 10184 10185 E1000_WRITE_REG(hw, FEXTNVM4, mac_reg); 10186 } 10187 10188 return E1000_SUCCESS; 10189 } 10190 10191 /*************************************************************************** 10192 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware 10193 * @hw: pointer to the HW structure 10194 * @gate: boolean set to TRUE to gate, FALSE to ungate 10195 * 10196 * Gate/ungate the automatic PHY configuration via hardware; perform 10197 * the configuration via software instead. 10198 ***************************************************************************/ 10199 void 10200 em_gate_hw_phy_config_ich8lan(struct em_hw *hw, boolean_t gate) 10201 { 10202 uint32_t extcnf_ctrl; 10203 10204 DEBUGFUNC("em_gate_hw_phy_config_ich8lan"); 10205 10206 if (hw->mac_type != em_pch2lan) 10207 return; 10208 10209 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 10210 10211 if (gate) 10212 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG; 10213 else 10214 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG; 10215 10216 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); 10217 } 10218 10219 /*************************************************************************** 10220 * Configure K1 power state 10221 * 10222 * Configure the K1 power state based on the provided parameter. 10223 * Assumes semaphore already acquired. 10224 * 10225 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 10226 ***************************************************************************/ 10227 int32_t 10228 em_configure_k1_ich8lan(struct em_hw *hw, boolean_t k1_enable) 10229 { 10230 int32_t ret_val = E1000_SUCCESS; 10231 uint32_t ctrl_reg = 0; 10232 uint32_t ctrl_ext = 0; 10233 uint32_t reg = 0; 10234 uint16_t kmrn_reg = 0; 10235 10236 ret_val = em_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 10237 &kmrn_reg); 10238 if (ret_val) 10239 goto out; 10240 10241 if (k1_enable) 10242 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE; 10243 else 10244 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE; 10245 10246 ret_val = em_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 10247 kmrn_reg); 10248 if (ret_val) 10249 goto out; 10250 10251 usec_delay(20); 10252 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 10253 ctrl_reg = E1000_READ_REG(hw, CTRL); 10254 10255 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 10256 reg |= E1000_CTRL_FRCSPD; 10257 E1000_WRITE_REG(hw, CTRL, reg); 10258 10259 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS); 10260 usec_delay(20); 10261 E1000_WRITE_REG(hw, CTRL, ctrl_reg); 10262 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 10263 usec_delay(20); 10264 10265 out: 10266 return ret_val; 10267 } 10268 10269 /*************************************************************************** 10270 * em_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be 10271 * done after every PHY reset. 10272 ***************************************************************************/ 10273 int32_t 10274 em_lv_phy_workarounds_ich8lan(struct em_hw *hw) 10275 { 10276 int32_t ret_val = E1000_SUCCESS; 10277 uint16_t swfw; 10278 10279 DEBUGFUNC("e1000_lv_phy_workarounds_ich8lan"); 10280 10281 if (hw->mac_type != em_pch2lan) 10282 goto out; 10283 10284 /* Set MDIO slow mode before any other MDIO access */ 10285 ret_val = em_set_mdio_slow_mode_hv(hw); 10286 10287 swfw = E1000_SWFW_PHY0_SM; 10288 ret_val = em_swfw_sync_acquire(hw, swfw); 10289 if (ret_val) 10290 goto out; 10291 ret_val = em_write_phy_reg(hw, I82579_EMI_ADDR, 10292 I82579_MSE_THRESHOLD); 10293 if (ret_val) 10294 goto release; 10295 /* set MSE higher to enable link to stay up when noise is high */ 10296 ret_val = em_write_phy_reg(hw, I82579_EMI_DATA, 10297 0x0034); 10298 if (ret_val) 10299 goto release; 10300 ret_val = em_write_phy_reg(hw, I82579_EMI_ADDR, 10301 I82579_MSE_LINK_DOWN); 10302 if (ret_val) 10303 goto release; 10304 /* drop link after 5 times MSE threshold was reached */ 10305 ret_val = em_write_phy_reg(hw, I82579_EMI_DATA, 10306 0x0005); 10307 release: 10308 em_swfw_sync_release(hw, swfw); 10309 10310 out: 10311 return ret_val; 10312 } 10313 10314 int32_t 10315 em_set_eee_i350(struct em_hw *hw) 10316 { 10317 int32_t ret_val = E1000_SUCCESS; 10318 uint32_t ipcnfg, eeer; 10319 10320 if ((hw->mac_type < em_i350) || 10321 (hw->media_type != em_media_type_copper)) 10322 goto out; 10323 ipcnfg = EM_READ_REG(hw, E1000_IPCNFG); 10324 eeer = EM_READ_REG(hw, E1000_EEER); 10325 10326 if (hw->eee_enable) { 10327 ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN); 10328 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN | 10329 E1000_EEER_LPI_FC); 10330 } else { 10331 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN); 10332 eeer &= ~(E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN | 10333 E1000_EEER_LPI_FC); 10334 } 10335 EM_WRITE_REG(hw, E1000_IPCNFG, ipcnfg); 10336 EM_WRITE_REG(hw, E1000_EEER, eeer); 10337 EM_READ_REG(hw, E1000_IPCNFG); 10338 EM_READ_REG(hw, E1000_EEER); 10339 out: 10340 return ret_val; 10341 } 10342 10343 /*************************************************************************** 10344 * em_set_eee_pchlan - Enable/disable EEE support 10345 * @hw: pointer to the HW structure 10346 * 10347 * Enable/disable EEE based on setting in dev_spec structure. The bits in 10348 * the LPI Control register will remain set only if/when link is up. 10349 ***************************************************************************/ 10350 int32_t 10351 em_set_eee_pchlan(struct em_hw *hw) 10352 { 10353 int32_t ret_val = E1000_SUCCESS; 10354 uint16_t phy_reg; 10355 10356 DEBUGFUNC("em_set_eee_pchlan"); 10357 10358 if (hw->phy_type != em_phy_82579 && 10359 hw->phy_type != em_phy_i217) 10360 goto out; 10361 10362 ret_val = em_read_phy_reg(hw, I82579_LPI_CTRL, &phy_reg); 10363 if (ret_val) 10364 goto out; 10365 10366 if (hw->eee_enable) 10367 phy_reg &= ~I82579_LPI_CTRL_ENABLE_MASK; 10368 else 10369 phy_reg |= I82579_LPI_CTRL_ENABLE_MASK; 10370 10371 ret_val = em_write_phy_reg(hw, I82579_LPI_CTRL, phy_reg); 10372 out: 10373 return ret_val; 10374 } 10375 10376