1 /******************************************************************************* 2 3 Copyright (c) 2001-2005, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 *******************************************************************************/ 33 34 /* $OpenBSD: if_em_hw.c,v 1.69 2012/05/17 10:45:17 jsg Exp $ */ 35 /* 36 * if_em_hw.c Shared functions for accessing and configuring the MAC 37 */ 38 39 #if 0 40 #include <sys/cdefs.h> 41 __FBSDID("$FreeBSD: if_em_hw.c,v 1.16 2005/05/26 23:32:02 tackerman Exp $"); 42 #endif 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/sockio.h> 47 #include <sys/mbuf.h> 48 #include <sys/malloc.h> 49 #include <sys/kernel.h> 50 #include <sys/device.h> 51 #include <sys/socket.h> 52 53 #include <net/if.h> 54 #include <net/if_dl.h> 55 #include <net/if_media.h> 56 57 #ifdef INET 58 #include <netinet/in.h> 59 #include <netinet/in_systm.h> 60 #include <netinet/in_var.h> 61 #include <netinet/ip.h> 62 #include <netinet/if_ether.h> 63 #endif 64 65 #include <uvm/uvm_extern.h> 66 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pcivar.h> 69 #include <dev/pci/pcidevs.h> 70 71 #include <dev/pci/if_em_hw.h> 72 #include <dev/pci/if_em_soc.h> 73 74 #define STATIC 75 76 static int32_t em_swfw_sync_acquire(struct em_hw *, uint16_t); 77 static void em_swfw_sync_release(struct em_hw *, uint16_t); 78 static int32_t em_read_kmrn_reg(struct em_hw *, uint32_t, uint16_t *); 79 static int32_t em_write_kmrn_reg(struct em_hw *hw, uint32_t, uint16_t); 80 static int32_t em_get_software_semaphore(struct em_hw *); 81 static void em_release_software_semaphore(struct em_hw *); 82 83 static int32_t em_check_downshift(struct em_hw *); 84 static void em_clear_vfta(struct em_hw *); 85 void em_clear_vfta_i350(struct em_hw *); 86 static int32_t em_commit_shadow_ram(struct em_hw *); 87 static int32_t em_config_dsp_after_link_change(struct em_hw *, boolean_t); 88 static int32_t em_config_fc_after_link_up(struct em_hw *); 89 static int32_t em_match_gig_phy(struct em_hw *); 90 static int32_t em_detect_gig_phy(struct em_hw *); 91 static int32_t em_erase_ich8_4k_segment(struct em_hw *, uint32_t); 92 static int32_t em_get_auto_rd_done(struct em_hw *); 93 static int32_t em_get_cable_length(struct em_hw *, uint16_t *, uint16_t *); 94 static int32_t em_get_hw_eeprom_semaphore(struct em_hw *); 95 static int32_t em_get_phy_cfg_done(struct em_hw *); 96 static int32_t em_get_software_flag(struct em_hw *); 97 static int32_t em_ich8_cycle_init(struct em_hw *); 98 static int32_t em_ich8_flash_cycle(struct em_hw *, uint32_t); 99 static int32_t em_id_led_init(struct em_hw *); 100 static int32_t em_init_lcd_from_nvm_config_region(struct em_hw *, uint32_t, 101 uint32_t); 102 static int32_t em_init_lcd_from_nvm(struct em_hw *); 103 static void em_init_rx_addrs(struct em_hw *); 104 static void em_initialize_hardware_bits(struct em_hw *); 105 static boolean_t em_is_onboard_nvm_eeprom(struct em_hw *); 106 static int32_t em_kumeran_lock_loss_workaround(struct em_hw *); 107 static int32_t em_mng_enable_host_if(struct em_hw *); 108 static int32_t em_read_eeprom_eerd(struct em_hw *, uint16_t, uint16_t, 109 uint16_t *); 110 static int32_t em_write_eeprom_eewr(struct em_hw *, uint16_t, uint16_t, 111 uint16_t *data); 112 static int32_t em_poll_eerd_eewr_done(struct em_hw *, int); 113 static void em_put_hw_eeprom_semaphore(struct em_hw *); 114 static int32_t em_read_ich8_byte(struct em_hw *, uint32_t, uint8_t *); 115 static int32_t em_verify_write_ich8_byte(struct em_hw *, uint32_t, uint8_t); 116 static int32_t em_write_ich8_byte(struct em_hw *, uint32_t, uint8_t); 117 static int32_t em_read_ich8_word(struct em_hw *, uint32_t, uint16_t *); 118 static int32_t em_read_ich8_data(struct em_hw *, uint32_t, uint32_t, 119 uint16_t *); 120 static int32_t em_write_ich8_data(struct em_hw *, uint32_t, uint32_t, 121 uint16_t); 122 static int32_t em_read_eeprom_ich8(struct em_hw *, uint16_t, uint16_t, 123 uint16_t *); 124 static int32_t em_write_eeprom_ich8(struct em_hw *, uint16_t, uint16_t, 125 uint16_t *); 126 static void em_release_software_flag(struct em_hw *); 127 static int32_t em_set_d3_lplu_state(struct em_hw *, boolean_t); 128 static int32_t em_set_d0_lplu_state(struct em_hw *, boolean_t); 129 static int32_t em_set_lplu_state_pchlan(struct em_hw *, boolean_t); 130 static int32_t em_set_pci_ex_no_snoop(struct em_hw *, uint32_t); 131 static void em_set_pci_express_master_disable(struct em_hw *); 132 static int32_t em_wait_autoneg(struct em_hw *); 133 static void em_write_reg_io(struct em_hw *, uint32_t, uint32_t); 134 static int32_t em_set_phy_type(struct em_hw *); 135 static void em_phy_init_script(struct em_hw *); 136 static int32_t em_setup_copper_link(struct em_hw *); 137 static int32_t em_setup_fiber_serdes_link(struct em_hw *); 138 static int32_t em_adjust_serdes_amplitude(struct em_hw *); 139 static int32_t em_phy_force_speed_duplex(struct em_hw *); 140 static int32_t em_config_mac_to_phy(struct em_hw *); 141 static void em_raise_mdi_clk(struct em_hw *, uint32_t *); 142 static void em_lower_mdi_clk(struct em_hw *, uint32_t *); 143 static void em_shift_out_mdi_bits(struct em_hw *, uint32_t, uint16_t); 144 static uint16_t em_shift_in_mdi_bits(struct em_hw *); 145 static int32_t em_phy_reset_dsp(struct em_hw *); 146 static int32_t em_write_eeprom_spi(struct em_hw *, uint16_t, uint16_t, 147 uint16_t *); 148 static int32_t em_write_eeprom_microwire(struct em_hw *, uint16_t, uint16_t, 149 uint16_t *); 150 static int32_t em_spi_eeprom_ready(struct em_hw *); 151 static void em_raise_ee_clk(struct em_hw *, uint32_t *); 152 static void em_lower_ee_clk(struct em_hw *, uint32_t *); 153 static void em_shift_out_ee_bits(struct em_hw *, uint16_t, uint16_t); 154 static int32_t em_write_phy_reg_ex(struct em_hw *, uint32_t, uint16_t); 155 static int32_t em_read_phy_reg_ex(struct em_hw *, uint32_t, uint16_t *); 156 static uint16_t em_shift_in_ee_bits(struct em_hw *, uint16_t); 157 static int32_t em_acquire_eeprom(struct em_hw *); 158 static void em_release_eeprom(struct em_hw *); 159 static void em_standby_eeprom(struct em_hw *); 160 static int32_t em_set_vco_speed(struct em_hw *); 161 static int32_t em_polarity_reversal_workaround(struct em_hw *); 162 static void em_pch2lan_disable_hw_config(struct em_hw *, boolean_t); 163 static int32_t em_set_phy_mode(struct em_hw *); 164 static int32_t em_host_if_read_cookie(struct em_hw *, uint8_t *); 165 static uint8_t em_calculate_mng_checksum(char *, uint32_t); 166 static int32_t em_configure_kmrn_for_10_100(struct em_hw *, uint16_t); 167 static int32_t em_configure_kmrn_for_1000(struct em_hw *); 168 static int32_t em_set_pciex_completion_timeout(struct em_hw *hw); 169 static int32_t em_set_mdio_slow_mode_hv(struct em_hw *); 170 int32_t em_hv_phy_workarounds_ich8lan(struct em_hw *); 171 int32_t em_link_stall_workaround_hv(struct em_hw *); 172 int32_t em_k1_gig_workaround_hv(struct em_hw *, boolean_t); 173 int32_t em_k1_workaround_lv(struct em_hw *); 174 int32_t em_configure_k1_ich8lan(struct em_hw *, boolean_t); 175 int32_t em_access_phy_wakeup_reg_bm(struct em_hw *, uint32_t, 176 uint16_t *, boolean_t); 177 int32_t em_access_phy_debug_regs_hv(struct em_hw *, uint32_t, 178 uint16_t *, boolean_t); 179 int32_t em_access_phy_reg_hv(struct em_hw *, uint32_t, uint16_t *, 180 boolean_t); 181 int32_t em_oem_bits_config_pchlan(struct em_hw *, boolean_t); 182 void em_power_up_serdes_link_82575(struct em_hw *); 183 int32_t em_get_pcs_speed_and_duplex_82575(struct em_hw *, uint16_t *, 184 uint16_t *); 185 int32_t em_set_eee_i350(struct em_hw *); 186 187 /* IGP cable length table */ 188 static const uint16_t 189 em_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = 190 {5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 191 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25, 192 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40, 193 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60, 194 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90, 195 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 196 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 197 110, 198 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 199 120}; 200 201 static const uint16_t 202 em_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] = 203 {0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 204 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 205 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 206 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 207 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 208 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 209 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 210 121, 124}; 211 212 /****************************************************************************** 213 * Set the phy type member in the hw struct. 214 * 215 * hw - Struct containing variables accessed by shared code 216 *****************************************************************************/ 217 STATIC int32_t 218 em_set_phy_type(struct em_hw *hw) 219 { 220 DEBUGFUNC("em_set_phy_type"); 221 222 if (hw->mac_type == em_undefined) 223 return -E1000_ERR_PHY_TYPE; 224 225 switch (hw->phy_id) { 226 case M88E1000_E_PHY_ID: 227 case M88E1000_I_PHY_ID: 228 case M88E1011_I_PHY_ID: 229 case M88E1111_I_PHY_ID: 230 hw->phy_type = em_phy_m88; 231 break; 232 case IGP01E1000_I_PHY_ID: 233 if (hw->mac_type == em_82541 || 234 hw->mac_type == em_82541_rev_2 || 235 hw->mac_type == em_82547 || 236 hw->mac_type == em_82547_rev_2) { 237 hw->phy_type = em_phy_igp; 238 break; 239 } 240 case IGP03E1000_E_PHY_ID: 241 case IGP04E1000_E_PHY_ID: 242 hw->phy_type = em_phy_igp_3; 243 break; 244 case IFE_E_PHY_ID: 245 case IFE_PLUS_E_PHY_ID: 246 case IFE_C_E_PHY_ID: 247 hw->phy_type = em_phy_ife; 248 break; 249 case M88E1141_E_PHY_ID: 250 hw->phy_type = em_phy_oem; 251 break; 252 case I82577_E_PHY_ID: 253 hw->phy_type = em_phy_82577; 254 break; 255 case I82578_E_PHY_ID: 256 hw->phy_type = em_phy_82578; 257 break; 258 case I82579_E_PHY_ID: 259 hw->phy_type = em_phy_82579; 260 break; 261 case I82580_I_PHY_ID: 262 case I350_I_PHY_ID: 263 hw->phy_type = em_phy_82580; 264 break; 265 case BME1000_E_PHY_ID: 266 if (hw->phy_revision == 1) { 267 hw->phy_type = em_phy_bm; 268 break; 269 } 270 /* FALLTHROUGH */ 271 case GG82563_E_PHY_ID: 272 if (hw->mac_type == em_80003es2lan) { 273 hw->phy_type = em_phy_gg82563; 274 break; 275 } 276 /* FALLTHROUGH */ 277 default: 278 /* Should never have loaded on this device */ 279 hw->phy_type = em_phy_undefined; 280 return -E1000_ERR_PHY_TYPE; 281 } 282 283 return E1000_SUCCESS; 284 } 285 286 /****************************************************************************** 287 * IGP phy init script - initializes the GbE PHY 288 * 289 * hw - Struct containing variables accessed by shared code 290 *****************************************************************************/ 291 static void 292 em_phy_init_script(struct em_hw *hw) 293 { 294 uint16_t phy_saved_data; 295 DEBUGFUNC("em_phy_init_script"); 296 297 if (hw->phy_init_script) { 298 msec_delay(20); 299 /* 300 * Save off the current value of register 0x2F5B to be 301 * restored at the end of this routine. 302 */ 303 em_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 304 305 /* Disabled the PHY transmitter */ 306 em_write_phy_reg(hw, 0x2F5B, 0x0003); 307 msec_delay(20); 308 em_write_phy_reg(hw, 0x0000, 0x0140); 309 msec_delay(5); 310 311 switch (hw->mac_type) { 312 case em_82541: 313 case em_82547: 314 em_write_phy_reg(hw, 0x1F95, 0x0001); 315 em_write_phy_reg(hw, 0x1F71, 0xBD21); 316 em_write_phy_reg(hw, 0x1F79, 0x0018); 317 em_write_phy_reg(hw, 0x1F30, 0x1600); 318 em_write_phy_reg(hw, 0x1F31, 0x0014); 319 em_write_phy_reg(hw, 0x1F32, 0x161C); 320 em_write_phy_reg(hw, 0x1F94, 0x0003); 321 em_write_phy_reg(hw, 0x1F96, 0x003F); 322 em_write_phy_reg(hw, 0x2010, 0x0008); 323 break; 324 case em_82541_rev_2: 325 case em_82547_rev_2: 326 em_write_phy_reg(hw, 0x1F73, 0x0099); 327 break; 328 default: 329 break; 330 } 331 332 em_write_phy_reg(hw, 0x0000, 0x3300); 333 msec_delay(20); 334 335 /* Now enable the transmitter */ 336 em_write_phy_reg(hw, 0x2F5B, phy_saved_data); 337 338 if (hw->mac_type == em_82547) { 339 uint16_t fused, fine, coarse; 340 /* Move to analog registers page */ 341 em_read_phy_reg(hw, 342 IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused); 343 344 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { 345 em_read_phy_reg(hw, 346 IGP01E1000_ANALOG_FUSE_STATUS, &fused); 347 348 fine = fused & 349 IGP01E1000_ANALOG_FUSE_FINE_MASK; 350 coarse = fused & 351 IGP01E1000_ANALOG_FUSE_COARSE_MASK; 352 353 if (coarse > 354 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { 355 coarse -= 356 IGP01E1000_ANALOG_FUSE_COARSE_10; 357 fine -= 358 IGP01E1000_ANALOG_FUSE_FINE_1; 359 } else if (coarse == 360 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) 361 fine -= IGP01E1000_ANALOG_FUSE_FINE_10; 362 363 fused = (fused & 364 IGP01E1000_ANALOG_FUSE_POLY_MASK) | 365 (fine & 366 IGP01E1000_ANALOG_FUSE_FINE_MASK) | 367 (coarse & 368 IGP01E1000_ANALOG_FUSE_COARSE_MASK); 369 370 em_write_phy_reg(hw, 371 IGP01E1000_ANALOG_FUSE_CONTROL, 372 fused); 373 374 em_write_phy_reg(hw, 375 IGP01E1000_ANALOG_FUSE_BYPASS, 376 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL); 377 } 378 } 379 } 380 } 381 382 /****************************************************************************** 383 * Set the mac type member in the hw struct. 384 * 385 * hw - Struct containing variables accessed by shared code 386 *****************************************************************************/ 387 int32_t 388 em_set_mac_type(struct em_hw *hw) 389 { 390 DEBUGFUNC("em_set_mac_type"); 391 392 switch (hw->device_id) { 393 case E1000_DEV_ID_82542: 394 switch (hw->revision_id) { 395 case E1000_82542_2_0_REV_ID: 396 hw->mac_type = em_82542_rev2_0; 397 break; 398 case E1000_82542_2_1_REV_ID: 399 hw->mac_type = em_82542_rev2_1; 400 break; 401 default: 402 /* Invalid 82542 revision ID */ 403 return -E1000_ERR_MAC_TYPE; 404 } 405 break; 406 case E1000_DEV_ID_82543GC_FIBER: 407 case E1000_DEV_ID_82543GC_COPPER: 408 hw->mac_type = em_82543; 409 break; 410 case E1000_DEV_ID_82544EI_COPPER: 411 case E1000_DEV_ID_82544EI_FIBER: 412 case E1000_DEV_ID_82544GC_COPPER: 413 case E1000_DEV_ID_82544GC_LOM: 414 hw->mac_type = em_82544; 415 break; 416 case E1000_DEV_ID_82540EM: 417 case E1000_DEV_ID_82540EM_LOM: 418 case E1000_DEV_ID_82540EP: 419 case E1000_DEV_ID_82540EP_LOM: 420 case E1000_DEV_ID_82540EP_LP: 421 hw->mac_type = em_82540; 422 break; 423 case E1000_DEV_ID_82545EM_COPPER: 424 case E1000_DEV_ID_82545EM_FIBER: 425 hw->mac_type = em_82545; 426 break; 427 case E1000_DEV_ID_82545GM_COPPER: 428 case E1000_DEV_ID_82545GM_FIBER: 429 case E1000_DEV_ID_82545GM_SERDES: 430 hw->mac_type = em_82545_rev_3; 431 break; 432 case E1000_DEV_ID_82546EB_COPPER: 433 case E1000_DEV_ID_82546EB_FIBER: 434 case E1000_DEV_ID_82546EB_QUAD_COPPER: 435 hw->mac_type = em_82546; 436 break; 437 case E1000_DEV_ID_82546GB_COPPER: 438 case E1000_DEV_ID_82546GB_FIBER: 439 case E1000_DEV_ID_82546GB_SERDES: 440 case E1000_DEV_ID_82546GB_PCIE: 441 case E1000_DEV_ID_82546GB_QUAD_COPPER: 442 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 443 case E1000_DEV_ID_82546GB_2: 444 hw->mac_type = em_82546_rev_3; 445 break; 446 case E1000_DEV_ID_82541EI: 447 case E1000_DEV_ID_82541EI_MOBILE: 448 case E1000_DEV_ID_82541ER_LOM: 449 hw->mac_type = em_82541; 450 break; 451 case E1000_DEV_ID_82541ER: 452 case E1000_DEV_ID_82541GI: 453 case E1000_DEV_ID_82541GI_LF: 454 case E1000_DEV_ID_82541GI_MOBILE: 455 hw->mac_type = em_82541_rev_2; 456 break; 457 case E1000_DEV_ID_82547EI: 458 case E1000_DEV_ID_82547EI_MOBILE: 459 hw->mac_type = em_82547; 460 break; 461 case E1000_DEV_ID_82547GI: 462 hw->mac_type = em_82547_rev_2; 463 break; 464 case E1000_DEV_ID_82571EB_AF: 465 case E1000_DEV_ID_82571EB_AT: 466 case E1000_DEV_ID_82571EB_COPPER: 467 case E1000_DEV_ID_82571EB_FIBER: 468 case E1000_DEV_ID_82571EB_SERDES: 469 case E1000_DEV_ID_82571EB_QUAD_COPPER: 470 case E1000_DEV_ID_82571EB_QUAD_FIBER: 471 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 472 case E1000_DEV_ID_82571EB_SERDES_DUAL: 473 case E1000_DEV_ID_82571EB_SERDES_QUAD: 474 case E1000_DEV_ID_82571PT_QUAD_COPPER: 475 hw->mac_type = em_82571; 476 break; 477 case E1000_DEV_ID_82572EI_COPPER: 478 case E1000_DEV_ID_82572EI_FIBER: 479 case E1000_DEV_ID_82572EI_SERDES: 480 case E1000_DEV_ID_82572EI: 481 hw->mac_type = em_82572; 482 break; 483 case E1000_DEV_ID_82573E: 484 case E1000_DEV_ID_82573E_IAMT: 485 case E1000_DEV_ID_82573E_PM: 486 case E1000_DEV_ID_82573L: 487 case E1000_DEV_ID_82573L_PL_1: 488 case E1000_DEV_ID_82573L_PL_2: 489 case E1000_DEV_ID_82573V_PM: 490 hw->mac_type = em_82573; 491 break; 492 case E1000_DEV_ID_82574L: 493 case E1000_DEV_ID_82574LA: 494 case E1000_DEV_ID_82583V: 495 hw->mac_type = em_82574; 496 break; 497 case E1000_DEV_ID_82575EB_PT: 498 case E1000_DEV_ID_82575EB_PF: 499 case E1000_DEV_ID_82575GB_QP: 500 case E1000_DEV_ID_82575GB_QP_PM: 501 case E1000_DEV_ID_82576: 502 case E1000_DEV_ID_82576_FIBER: 503 case E1000_DEV_ID_82576_SERDES: 504 case E1000_DEV_ID_82576_QUAD_COPPER: 505 case E1000_DEV_ID_82576_QUAD_CU_ET2: 506 case E1000_DEV_ID_82576_NS: 507 case E1000_DEV_ID_82576_NS_SERDES: 508 case E1000_DEV_ID_82576_SERDES_QUAD: 509 hw->mac_type = em_82575; 510 hw->initialize_hw_bits_disable = 1; 511 break; 512 case E1000_DEV_ID_82580_COPPER: 513 case E1000_DEV_ID_82580_FIBER: 514 case E1000_DEV_ID_82580_SERDES: 515 case E1000_DEV_ID_82580_SGMII: 516 case E1000_DEV_ID_82580_COPPER_DUAL: 517 hw->mac_type = em_82580; 518 hw->initialize_hw_bits_disable = 1; 519 break; 520 case E1000_DEV_ID_I350_COPPER: 521 case E1000_DEV_ID_I350_FIBER: 522 case E1000_DEV_ID_I350_SERDES: 523 case E1000_DEV_ID_I350_SGMII: 524 case E1000_DEV_ID_I350_DA4: 525 hw->mac_type = em_i350; 526 hw->initialize_hw_bits_disable = 1; 527 hw->eee_enable = 1; 528 break; 529 case E1000_DEV_ID_80003ES2LAN_COPPER_SPT: 530 case E1000_DEV_ID_80003ES2LAN_SERDES_SPT: 531 case E1000_DEV_ID_80003ES2LAN_COPPER_DPT: 532 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: 533 hw->mac_type = em_80003es2lan; 534 break; 535 case E1000_DEV_ID_ICH8_IFE: 536 case E1000_DEV_ID_ICH8_IFE_G: 537 case E1000_DEV_ID_ICH8_IFE_GT: 538 case E1000_DEV_ID_ICH8_IGP_AMT: 539 case E1000_DEV_ID_ICH8_IGP_C: 540 case E1000_DEV_ID_ICH8_IGP_M: 541 case E1000_DEV_ID_ICH8_IGP_M_AMT: 542 case E1000_DEV_ID_ICH8_82567V_3: 543 hw->mac_type = em_ich8lan; 544 break; 545 case E1000_DEV_ID_ICH9_BM: 546 case E1000_DEV_ID_ICH9_IFE: 547 case E1000_DEV_ID_ICH9_IFE_G: 548 case E1000_DEV_ID_ICH9_IFE_GT: 549 case E1000_DEV_ID_ICH9_IGP_AMT: 550 case E1000_DEV_ID_ICH9_IGP_C: 551 case E1000_DEV_ID_ICH9_IGP_M: 552 case E1000_DEV_ID_ICH9_IGP_M_AMT: 553 case E1000_DEV_ID_ICH9_IGP_M_V: 554 case E1000_DEV_ID_ICH10_R_BM_LF: 555 case E1000_DEV_ID_ICH10_R_BM_LM: 556 case E1000_DEV_ID_ICH10_R_BM_V: 557 hw->mac_type = em_ich9lan; 558 break; 559 case E1000_DEV_ID_ICH10_D_BM_LF: 560 case E1000_DEV_ID_ICH10_D_BM_LM: 561 hw->mac_type = em_ich10lan; 562 break; 563 case E1000_DEV_ID_PCH_M_HV_LC: 564 case E1000_DEV_ID_PCH_M_HV_LM: 565 case E1000_DEV_ID_PCH_D_HV_DC: 566 case E1000_DEV_ID_PCH_D_HV_DM: 567 hw->mac_type = em_pchlan; 568 break; 569 case E1000_DEV_ID_PCH2_LV_LM: 570 case E1000_DEV_ID_PCH2_LV_V: 571 hw->mac_type = em_pch2lan; 572 break; 573 case E1000_DEV_ID_EP80579_LAN_1: 574 hw->mac_type = em_icp_xxxx; 575 hw->icp_xxxx_port_num = 0; 576 break; 577 case E1000_DEV_ID_EP80579_LAN_2: 578 hw->mac_type = em_icp_xxxx; 579 hw->icp_xxxx_port_num = 1; 580 break; 581 case E1000_DEV_ID_EP80579_LAN_3: 582 hw->mac_type = em_icp_xxxx; 583 hw->icp_xxxx_port_num = 2; 584 break; 585 default: 586 /* Should never have loaded on this device */ 587 return -E1000_ERR_MAC_TYPE; 588 } 589 590 switch (hw->mac_type) { 591 case em_ich8lan: 592 case em_ich9lan: 593 case em_ich10lan: 594 case em_pchlan: 595 case em_pch2lan: 596 hw->swfwhw_semaphore_present = TRUE; 597 hw->asf_firmware_present = TRUE; 598 break; 599 case em_80003es2lan: 600 case em_82575: 601 case em_82580: 602 case em_i350: 603 hw->swfw_sync_present = TRUE; 604 /* FALLTHROUGH */ 605 case em_82571: 606 case em_82572: 607 case em_82573: 608 case em_82574: 609 hw->eeprom_semaphore_present = TRUE; 610 /* FALLTHROUGH */ 611 case em_82541: 612 case em_82547: 613 case em_82541_rev_2: 614 case em_82547_rev_2: 615 hw->asf_firmware_present = TRUE; 616 break; 617 default: 618 break; 619 } 620 621 return E1000_SUCCESS; 622 } 623 /***************************************************************************** 624 * Set media type and TBI compatibility. 625 * 626 * hw - Struct containing variables accessed by shared code 627 * **************************************************************************/ 628 void 629 em_set_media_type(struct em_hw *hw) 630 { 631 uint32_t status, ctrl_ext; 632 DEBUGFUNC("em_set_media_type"); 633 634 if (hw->mac_type != em_82543) { 635 /* tbi_compatibility is only valid on 82543 */ 636 hw->tbi_compatibility_en = FALSE; 637 } 638 639 if (hw->mac_type == em_82575 || hw->mac_type == em_82580 || 640 hw->mac_type == em_i350) { 641 hw->media_type = em_media_type_copper; 642 643 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 644 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) { 645 case E1000_CTRL_EXT_LINK_MODE_SGMII: 646 ctrl_ext |= E1000_CTRL_I2C_ENA; 647 break; 648 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: 649 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES: 650 hw->media_type = em_media_type_internal_serdes; 651 ctrl_ext |= E1000_CTRL_I2C_ENA; 652 break; 653 default: 654 ctrl_ext &= ~E1000_CTRL_I2C_ENA; 655 break; 656 } 657 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 658 return; 659 } 660 661 switch (hw->device_id) { 662 case E1000_DEV_ID_82545GM_SERDES: 663 case E1000_DEV_ID_82546GB_SERDES: 664 case E1000_DEV_ID_82571EB_SERDES: 665 case E1000_DEV_ID_82571EB_SERDES_DUAL: 666 case E1000_DEV_ID_82571EB_SERDES_QUAD: 667 case E1000_DEV_ID_82572EI_SERDES: 668 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: 669 hw->media_type = em_media_type_internal_serdes; 670 break; 671 case E1000_DEV_ID_EP80579_LAN_1: 672 case E1000_DEV_ID_EP80579_LAN_2: 673 case E1000_DEV_ID_EP80579_LAN_3: 674 hw->media_type = em_media_type_oem; 675 break; 676 default: 677 switch (hw->mac_type) { 678 case em_82542_rev2_0: 679 case em_82542_rev2_1: 680 hw->media_type = em_media_type_fiber; 681 break; 682 case em_ich8lan: 683 case em_ich9lan: 684 case em_ich10lan: 685 case em_pchlan: 686 case em_pch2lan: 687 case em_82573: 688 case em_82574: 689 /* 690 * The STATUS_TBIMODE bit is reserved or reused for 691 * the this device. 692 */ 693 hw->media_type = em_media_type_copper; 694 break; 695 default: 696 status = E1000_READ_REG(hw, STATUS); 697 if (status & E1000_STATUS_TBIMODE) { 698 hw->media_type = em_media_type_fiber; 699 /* tbi_compatibility not valid on fiber */ 700 hw->tbi_compatibility_en = FALSE; 701 } else { 702 hw->media_type = em_media_type_copper; 703 } 704 break; 705 } 706 } 707 } 708 /****************************************************************************** 709 * Reset the transmit and receive units; mask and clear all interrupts. 710 * 711 * hw - Struct containing variables accessed by shared code 712 *****************************************************************************/ 713 int32_t 714 em_reset_hw(struct em_hw *hw) 715 { 716 uint32_t ctrl; 717 uint32_t ctrl_ext; 718 uint32_t icr; 719 uint32_t manc; 720 uint32_t led_ctrl; 721 uint32_t timeout; 722 uint32_t extcnf_ctrl; 723 int32_t ret_val; 724 DEBUGFUNC("em_reset_hw"); 725 726 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ 727 if (hw->mac_type == em_82542_rev2_0) { 728 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 729 em_pci_clear_mwi(hw); 730 } 731 if (hw->bus_type == em_bus_type_pci_express) { 732 /* 733 * Prevent the PCI-E bus from sticking if there is no TLP 734 * connection on the last TLP read/write transaction when MAC 735 * is reset. 736 */ 737 if (em_disable_pciex_master(hw) != E1000_SUCCESS) { 738 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 739 } 740 } 741 742 /* Set the completion timeout for 82575 chips */ 743 if (hw->mac_type == em_82575 || hw->mac_type == em_82580 || 744 hw->mac_type == em_i350) { 745 ret_val = em_set_pciex_completion_timeout(hw); 746 if (ret_val) { 747 DEBUGOUT("PCI-E Set completion timeout has failed.\n"); 748 } 749 } 750 751 /* Clear interrupt mask to stop board from generating interrupts */ 752 DEBUGOUT("Masking off all interrupts\n"); 753 E1000_WRITE_REG(hw, IMC, 0xffffffff); 754 /* 755 * Disable the Transmit and Receive units. Then delay to allow any 756 * pending transactions to complete before we hit the MAC with the 757 * global reset. 758 */ 759 E1000_WRITE_REG(hw, RCTL, 0); 760 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP); 761 E1000_WRITE_FLUSH(hw); 762 /* 763 * The tbi_compatibility_on Flag must be cleared when Rctl is 764 * cleared. 765 */ 766 hw->tbi_compatibility_on = FALSE; 767 /* 768 * Delay to allow any outstanding PCI transactions to complete before 769 * resetting the device 770 */ 771 msec_delay(10); 772 773 ctrl = E1000_READ_REG(hw, CTRL); 774 775 /* Must reset the PHY before resetting the MAC */ 776 if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) { 777 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST)); 778 msec_delay(5); 779 } 780 /* 781 * Must acquire the MDIO ownership before MAC reset. Ownership 782 * defaults to firmware after a reset. 783 */ 784 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) { 785 timeout = 10; 786 787 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 788 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 789 790 do { 791 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); 792 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 793 794 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) 795 break; 796 else 797 extcnf_ctrl |= 798 E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 799 800 msec_delay(2); 801 timeout--; 802 } while (timeout); 803 } 804 /* Workaround for ICH8 bit corruption issue in FIFO memory */ 805 if (hw->mac_type == em_ich8lan) { 806 /* Set Tx and Rx buffer allocation to 8k apiece. */ 807 E1000_WRITE_REG(hw, PBA, E1000_PBA_8K); 808 /* Set Packet Buffer Size to 16k. */ 809 E1000_WRITE_REG(hw, PBS, E1000_PBS_16K); 810 } 811 /* 812 * Issue a global reset to the MAC. This will reset the chip's 813 * transmit, receive, DMA, and link units. It will not effect the 814 * current PCI configuration. The global reset bit is self- 815 * clearing, and should clear within a microsecond. 816 */ 817 DEBUGOUT("Issuing a global reset to MAC\n"); 818 819 switch (hw->mac_type) { 820 case em_82544: 821 case em_82540: 822 case em_82545: 823 case em_82546: 824 case em_82541: 825 case em_82541_rev_2: 826 /* 827 * These controllers can't ack the 64-bit write when issuing 828 * the reset, so use IO-mapping as a workaround to issue the 829 * reset 830 */ 831 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST)); 832 break; 833 case em_82545_rev_3: 834 case em_82546_rev_3: 835 /* Reset is performed on a shadow of the control register */ 836 E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST)); 837 break; 838 case em_ich8lan: 839 case em_ich9lan: 840 case em_ich10lan: 841 case em_pchlan: 842 case em_pch2lan: 843 if (!hw->phy_reset_disable && 844 em_check_phy_reset_block(hw) == E1000_SUCCESS) { 845 /* 846 * PHY HW reset requires MAC CORE reset at the same 847 * time to make sure the interface between MAC and 848 * the external PHY is reset. 849 */ 850 ctrl |= E1000_CTRL_PHY_RST; 851 852 if ((hw->mac_type == em_pch2lan) && 853 !(E1000_READ_REG(hw, FWSM) & E1000_FWSM_FW_VALID)) { 854 em_pch2lan_disable_hw_config(hw, TRUE); 855 } 856 } 857 em_get_software_flag(hw); 858 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); 859 msec_delay(5); 860 break; 861 default: 862 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); 863 break; 864 } 865 866 if (em_check_phy_reset_block(hw) == E1000_SUCCESS) { 867 if (hw->mac_type == em_pchlan) { 868 ret_val = em_hv_phy_workarounds_ich8lan(hw); 869 if (ret_val) 870 return ret_val; 871 } 872 else if (hw->mac_type == em_pch2lan) { 873 ret_val = em_set_mdio_slow_mode_hv(hw); 874 if (ret_val) 875 return ret_val; 876 } 877 } 878 879 /* 880 * After MAC reset, force reload of EEPROM to restore power-on 881 * settings to device. Later controllers reload the EEPROM 882 * automatically, so just wait for reload to complete. 883 */ 884 switch (hw->mac_type) { 885 case em_82542_rev2_0: 886 case em_82542_rev2_1: 887 case em_82543: 888 case em_82544: 889 /* Wait for reset to complete */ 890 usec_delay(10); 891 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 892 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 893 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 894 E1000_WRITE_FLUSH(hw); 895 /* Wait for EEPROM reload */ 896 msec_delay(2); 897 break; 898 case em_82541: 899 case em_82541_rev_2: 900 case em_82547: 901 case em_82547_rev_2: 902 /* Wait for EEPROM reload */ 903 msec_delay(20); 904 break; 905 case em_82573: 906 case em_82574: 907 if (em_is_onboard_nvm_eeprom(hw) == FALSE) { 908 usec_delay(10); 909 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 910 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 911 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 912 E1000_WRITE_FLUSH(hw); 913 } 914 /* FALLTHROUGH */ 915 916 /* Auto read done will delay 5ms or poll based on mac type */ 917 ret_val = em_get_auto_rd_done(hw); 918 if (ret_val) 919 return ret_val; 920 break; 921 default: 922 /* Wait for EEPROM reload (it happens automatically) */ 923 msec_delay(5); 924 break; 925 } 926 927 /* Disable HW ARPs on ASF enabled adapters */ 928 if (hw->mac_type >= em_82540 && hw->mac_type <= em_82547_rev_2 && 929 hw->mac_type != em_icp_xxxx) { 930 manc = E1000_READ_REG(hw, MANC); 931 manc &= ~(E1000_MANC_ARP_EN); 932 E1000_WRITE_REG(hw, MANC, manc); 933 } 934 if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) { 935 em_phy_init_script(hw); 936 937 /* Configure activity LED after PHY reset */ 938 led_ctrl = E1000_READ_REG(hw, LEDCTL); 939 led_ctrl &= IGP_ACTIVITY_LED_MASK; 940 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 941 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 942 } 943 944 /* 945 * For PCH, this write will make sure that any noise 946 * will be detected as a CRC error and be dropped rather than show up 947 * as a bad packet to the DMA engine. 948 */ 949 if (hw->mac_type == em_pchlan) 950 E1000_WRITE_REG(hw, CRC_OFFSET, 0x65656565); 951 952 /* Clear interrupt mask to stop board from generating interrupts */ 953 DEBUGOUT("Masking off all interrupts\n"); 954 E1000_WRITE_REG(hw, IMC, 0xffffffff); 955 956 /* Clear any pending interrupt events. */ 957 icr = E1000_READ_REG(hw, ICR); 958 959 /* If MWI was previously enabled, reenable it. */ 960 if (hw->mac_type == em_82542_rev2_0) { 961 if (hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 962 em_pci_set_mwi(hw); 963 } 964 if (hw->mac_type == em_ich8lan || 965 hw->mac_type == em_ich9lan || 966 hw->mac_type == em_ich10lan || 967 hw->mac_type == em_pchlan || 968 hw->mac_type == em_pch2lan) { 969 uint32_t kab = E1000_READ_REG(hw, KABGTXD); 970 kab |= E1000_KABGTXD_BGSQLBIAS; 971 E1000_WRITE_REG(hw, KABGTXD, kab); 972 } 973 974 if (hw->mac_type == em_82580 || hw->mac_type == em_i350) { 975 uint32_t mdicnfg; 976 uint16_t nvm_data; 977 978 /* clear global device reset status bit */ 979 EM_WRITE_REG(hw, E1000_STATUS, E1000_STATUS_DEV_RST_SET); 980 981 em_read_eeprom(hw, EEPROM_INIT_CONTROL3_PORT_A + 982 NVM_82580_LAN_FUNC_OFFSET(hw->bus_func), 1, 983 &nvm_data); 984 985 mdicnfg = EM_READ_REG(hw, E1000_MDICNFG); 986 if (nvm_data & NVM_WORD24_EXT_MDIO) 987 mdicnfg |= E1000_MDICNFG_EXT_MDIO; 988 if (nvm_data & NVM_WORD24_COM_MDIO) 989 mdicnfg |= E1000_MDICNFG_COM_MDIO; 990 EM_WRITE_REG(hw, E1000_MDICNFG, mdicnfg); 991 } 992 993 if (hw->mac_type == em_i350) 994 em_set_eee_i350(hw); 995 996 return E1000_SUCCESS; 997 } 998 999 /****************************************************************************** 1000 * 1001 * Initialize a number of hardware-dependent bits 1002 * 1003 * hw: Struct containing variables accessed by shared code 1004 * 1005 *****************************************************************************/ 1006 STATIC void 1007 em_initialize_hardware_bits(struct em_hw *hw) 1008 { 1009 DEBUGFUNC("em_initialize_hardware_bits"); 1010 1011 if ((hw->mac_type >= em_82571) && (!hw->initialize_hw_bits_disable)) { 1012 /* Settings common to all silicon */ 1013 uint32_t reg_ctrl, reg_ctrl_ext; 1014 uint32_t reg_tarc0, reg_tarc1; 1015 uint32_t reg_tctl; 1016 uint32_t reg_txdctl, reg_txdctl1; 1017 reg_tarc0 = E1000_READ_REG(hw, TARC0); 1018 reg_tarc0 &= ~0x78000000; /* Clear bits 30, 29, 28, and 1019 * 27 */ 1020 1021 reg_txdctl = E1000_READ_REG(hw, TXDCTL); 1022 reg_txdctl |= E1000_TXDCTL_COUNT_DESC; /* Set bit 22 */ 1023 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl); 1024 1025 reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1); 1026 reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC; /* Set bit 22 */ 1027 E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1); 1028 1029 switch (hw->mac_type) { 1030 case em_82571: 1031 case em_82572: 1032 reg_tarc1 = E1000_READ_REG(hw, TARC1); 1033 reg_tctl = E1000_READ_REG(hw, TCTL); 1034 1035 /* Set the phy Tx compatible mode bits */ 1036 reg_tarc1 &= ~0x60000000; /* Clear bits 30 and 29 */ 1037 1038 reg_tarc0 |= 0x07800000; /* Set TARC0 bits 23-26 */ 1039 reg_tarc1 |= 0x07000000; /* Set TARC1 bits 24-26 */ 1040 1041 if (reg_tctl & E1000_TCTL_MULR) 1042 /* Clear bit 28 if MULR is 1b */ 1043 reg_tarc1 &= ~0x10000000; 1044 else 1045 /* Set bit 28 if MULR is 0b */ 1046 reg_tarc1 |= 0x10000000; 1047 1048 E1000_WRITE_REG(hw, TARC1, reg_tarc1); 1049 break; 1050 case em_82573: 1051 case em_82574: 1052 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1053 reg_ctrl = E1000_READ_REG(hw, CTRL); 1054 1055 reg_ctrl_ext &= ~0x00800000; /* Clear bit 23 */ 1056 reg_ctrl_ext |= 0x00400000; /* Set bit 22 */ 1057 reg_ctrl &= ~0x20000000; /* Clear bit 29 */ 1058 1059 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); 1060 E1000_WRITE_REG(hw, CTRL, reg_ctrl); 1061 break; 1062 case em_80003es2lan: 1063 if ((hw->media_type == em_media_type_fiber) || 1064 (hw->media_type == em_media_type_internal_serdes)) { 1065 /* Clear bit 20 */ 1066 reg_tarc0 &= ~0x00100000; 1067 } 1068 reg_tctl = E1000_READ_REG(hw, TCTL); 1069 reg_tarc1 = E1000_READ_REG(hw, TARC1); 1070 if (reg_tctl & E1000_TCTL_MULR) 1071 /* Clear bit 28 if MULR is 1b */ 1072 reg_tarc1 &= ~0x10000000; 1073 else 1074 /* Set bit 28 if MULR is 0b */ 1075 reg_tarc1 |= 0x10000000; 1076 1077 E1000_WRITE_REG(hw, TARC1, reg_tarc1); 1078 break; 1079 case em_ich8lan: 1080 case em_ich9lan: 1081 case em_ich10lan: 1082 case em_pchlan: 1083 case em_pch2lan: 1084 if (hw->mac_type == em_ich8lan) 1085 /* Set TARC0 bits 29 and 28 */ 1086 reg_tarc0 |= 0x30000000; 1087 1088 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1089 reg_ctrl_ext |= 0x00400000; /* Set bit 22 */ 1090 /* Enable PHY low-power state when MAC is at D3 w/o WoL */ 1091 if (hw->mac_type >= em_pchlan) 1092 reg_ctrl_ext |= E1000_CTRL_EXT_PHYPDEN; 1093 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); 1094 1095 reg_tarc0 |= 0x0d800000; /* Set TARC0 bits 23, 1096 * 24, 26, 27 */ 1097 1098 reg_tarc1 = E1000_READ_REG(hw, TARC1); 1099 reg_tctl = E1000_READ_REG(hw, TCTL); 1100 1101 if (reg_tctl & E1000_TCTL_MULR) 1102 /* Clear bit 28 if MULR is 1b */ 1103 reg_tarc1 &= ~0x10000000; 1104 else 1105 /* Set bit 28 if MULR is 0b */ 1106 reg_tarc1 |= 0x10000000; 1107 1108 reg_tarc1 |= 0x45000000; /* Set bit 24, 26 and 1109 * 30 */ 1110 1111 E1000_WRITE_REG(hw, TARC1, reg_tarc1); 1112 break; 1113 default: 1114 break; 1115 } 1116 1117 E1000_WRITE_REG(hw, TARC0, reg_tarc0); 1118 } 1119 } 1120 1121 /****************************************************************************** 1122 * Performs basic configuration of the adapter. 1123 * 1124 * hw - Struct containing variables accessed by shared code 1125 * 1126 * Assumes that the controller has previously been reset and is in a 1127 * post-reset uninitialized state. Initializes the receive address registers, 1128 * multicast table, and VLAN filter table. Calls routines to setup link 1129 * configuration and flow control settings. Clears all on-chip counters. Leaves 1130 * the transmit and receive units disabled and uninitialized. 1131 *****************************************************************************/ 1132 int32_t 1133 em_init_hw(struct em_hw *hw) 1134 { 1135 uint32_t ctrl; 1136 uint32_t i; 1137 int32_t ret_val; 1138 uint16_t pcix_cmd_word; 1139 uint16_t pcix_stat_hi_word; 1140 uint16_t cmd_mmrbc; 1141 uint16_t stat_mmrbc; 1142 uint32_t mta_size; 1143 uint32_t reg_data; 1144 uint32_t ctrl_ext; 1145 uint32_t snoop; 1146 uint32_t fwsm; 1147 DEBUGFUNC("em_init_hw"); 1148 1149 /* force full DMA clock frequency for ICH8 */ 1150 if (hw->mac_type == em_ich8lan) { 1151 reg_data = E1000_READ_REG(hw, STATUS); 1152 reg_data &= ~0x80000000; 1153 E1000_WRITE_REG(hw, STATUS, reg_data); 1154 } 1155 1156 if (hw->mac_type == em_pchlan || 1157 hw->mac_type == em_pch2lan) { 1158 /* 1159 * The MAC-PHY interconnect may still be in SMBus mode 1160 * after Sx->S0. Toggle the LANPHYPC Value bit to force 1161 * the interconnect to PCIe mode, but only if there is no 1162 * firmware present otherwise firmware will have done it. 1163 */ 1164 fwsm = E1000_READ_REG(hw, FWSM); 1165 if ((fwsm & E1000_FWSM_FW_VALID) == 0) { 1166 ctrl = E1000_READ_REG(hw, CTRL); 1167 ctrl |= E1000_CTRL_LANPHYPC_OVERRIDE; 1168 ctrl &= ~E1000_CTRL_LANPHYPC_VALUE; 1169 E1000_WRITE_REG(hw, CTRL, ctrl); 1170 usec_delay(10); 1171 ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE; 1172 E1000_WRITE_REG(hw, CTRL, ctrl); 1173 msec_delay(50); 1174 } 1175 1176 if (hw->mac_type == em_pch2lan) 1177 em_pch2lan_disable_hw_config(hw, TRUE); 1178 1179 /* 1180 * Reset the PHY before any acccess to it. Doing so, 1181 * ensures that the PHY is in a known good state before 1182 * we read/write PHY registers. The generic reset is 1183 * sufficient here, because we haven't determined 1184 * the PHY type yet. 1185 */ 1186 em_phy_reset(hw); 1187 1188 if (hw->mac_type == em_pch2lan && 1189 (fwsm & E1000_FWSM_FW_VALID) == 0) 1190 em_pch2lan_disable_hw_config(hw, FALSE); 1191 1192 /* Set MDIO slow mode before any other MDIO access */ 1193 ret_val = em_set_mdio_slow_mode_hv(hw); 1194 if (ret_val) 1195 return ret_val; 1196 } 1197 1198 /* Initialize Identification LED */ 1199 ret_val = em_id_led_init(hw); 1200 if (ret_val) { 1201 DEBUGOUT("Error Initializing Identification LED\n"); 1202 return ret_val; 1203 } 1204 /* Set the media type and TBI compatibility */ 1205 em_set_media_type(hw); 1206 1207 /* Must be called after em_set_media_type because media_type is used */ 1208 em_initialize_hardware_bits(hw); 1209 1210 /* Disabling VLAN filtering. */ 1211 DEBUGOUT("Initializing the IEEE VLAN\n"); 1212 /* VET hardcoded to standard value and VFTA removed in ICH8/ICH9 LAN */ 1213 if (hw->mac_type != em_ich8lan && 1214 hw->mac_type != em_ich9lan && 1215 hw->mac_type != em_ich10lan && 1216 hw->mac_type != em_pchlan && 1217 hw->mac_type != em_pch2lan) { 1218 if (hw->mac_type < em_82545_rev_3) 1219 E1000_WRITE_REG(hw, VET, 0); 1220 if (hw->mac_type == em_i350) 1221 em_clear_vfta_i350(hw); 1222 else 1223 em_clear_vfta(hw); 1224 } 1225 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ 1226 if (hw->mac_type == em_82542_rev2_0) { 1227 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 1228 em_pci_clear_mwi(hw); 1229 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST); 1230 E1000_WRITE_FLUSH(hw); 1231 msec_delay(5); 1232 } 1233 /* 1234 * Setup the receive address. This involves initializing all of the 1235 * Receive Address Registers (RARs 0 - 15). 1236 */ 1237 em_init_rx_addrs(hw); 1238 1239 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI*/ 1240 if (hw->mac_type == em_82542_rev2_0) { 1241 E1000_WRITE_REG(hw, RCTL, 0); 1242 E1000_WRITE_FLUSH(hw); 1243 msec_delay(1); 1244 if (hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1245 em_pci_set_mwi(hw); 1246 } 1247 /* Zero out the Multicast HASH table */ 1248 DEBUGOUT("Zeroing the MTA\n"); 1249 mta_size = E1000_MC_TBL_SIZE; 1250 if (hw->mac_type == em_ich8lan || 1251 hw->mac_type == em_ich9lan || 1252 hw->mac_type == em_ich10lan || 1253 hw->mac_type == em_pchlan || 1254 hw->mac_type == em_pch2lan) 1255 mta_size = E1000_MC_TBL_SIZE_ICH8LAN; 1256 for (i = 0; i < mta_size; i++) { 1257 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 1258 /* 1259 * use write flush to prevent Memory Write Block (MWB) from 1260 * occuring when accessing our register space 1261 */ 1262 E1000_WRITE_FLUSH(hw); 1263 } 1264 /* 1265 * Set the PCI priority bit correctly in the CTRL register. This 1266 * determines if the adapter gives priority to receives, or if it 1267 * gives equal priority to transmits and receives. Valid only on 1268 * 82542 and 82543 silicon. 1269 */ 1270 if (hw->dma_fairness && hw->mac_type <= em_82543) { 1271 ctrl = E1000_READ_REG(hw, CTRL); 1272 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR); 1273 } 1274 switch (hw->mac_type) { 1275 case em_82545_rev_3: 1276 case em_82546_rev_3: 1277 break; 1278 default: 1279 /* 1280 * Workaround for PCI-X problem when BIOS sets MMRBC 1281 * incorrectly. 1282 */ 1283 if (hw->bus_type == em_bus_type_pcix) { 1284 em_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, 1285 &pcix_cmd_word); 1286 em_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, 1287 &pcix_stat_hi_word); 1288 cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) 1289 >> PCIX_COMMAND_MMRBC_SHIFT; 1290 stat_mmrbc = (pcix_stat_hi_word & 1291 PCIX_STATUS_HI_MMRBC_MASK) >> 1292 PCIX_STATUS_HI_MMRBC_SHIFT; 1293 1294 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) 1295 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; 1296 if (cmd_mmrbc > stat_mmrbc) { 1297 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK; 1298 pcix_cmd_word |= stat_mmrbc << 1299 PCIX_COMMAND_MMRBC_SHIFT; 1300 em_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, 1301 &pcix_cmd_word); 1302 } 1303 } 1304 break; 1305 } 1306 1307 /* More time needed for PHY to initialize */ 1308 if (hw->mac_type == em_ich8lan || 1309 hw->mac_type == em_ich9lan || 1310 hw->mac_type == em_ich10lan || 1311 hw->mac_type == em_pchlan || 1312 hw->mac_type == em_pch2lan) 1313 msec_delay(15); 1314 1315 /* 1316 * The 82578 Rx buffer will stall if wakeup is enabled in host and 1317 * the ME. Reading the BM_WUC register will clear the host wakeup bit. 1318 * Reset the phy after disabling host wakeup to reset the Rx buffer. 1319 */ 1320 if (hw->phy_type == em_phy_82578) { 1321 em_read_phy_reg(hw, PHY_REG(BM_WUC_PAGE, 1), 1322 (uint16_t *)®_data); 1323 ret_val = em_phy_reset(hw); 1324 if (ret_val) 1325 return ret_val; 1326 } 1327 1328 /* Call a subroutine to configure the link and setup flow control. */ 1329 ret_val = em_setup_link(hw); 1330 1331 /* Set the transmit descriptor write-back policy */ 1332 if (hw->mac_type > em_82544) { 1333 ctrl = E1000_READ_REG(hw, TXDCTL); 1334 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | 1335 E1000_TXDCTL_FULL_TX_DESC_WB; 1336 E1000_WRITE_REG(hw, TXDCTL, ctrl); 1337 } 1338 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) { 1339 em_enable_tx_pkt_filtering(hw); 1340 } 1341 switch (hw->mac_type) { 1342 default: 1343 break; 1344 case em_80003es2lan: 1345 /* Enable retransmit on late collisions */ 1346 reg_data = E1000_READ_REG(hw, TCTL); 1347 reg_data |= E1000_TCTL_RTLC; 1348 E1000_WRITE_REG(hw, TCTL, reg_data); 1349 1350 /* Configure Gigabit Carry Extend Padding */ 1351 reg_data = E1000_READ_REG(hw, TCTL_EXT); 1352 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK; 1353 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX; 1354 E1000_WRITE_REG(hw, TCTL_EXT, reg_data); 1355 1356 /* Configure Transmit Inter-Packet Gap */ 1357 reg_data = E1000_READ_REG(hw, TIPG); 1358 reg_data &= ~E1000_TIPG_IPGT_MASK; 1359 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; 1360 E1000_WRITE_REG(hw, TIPG, reg_data); 1361 1362 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001); 1363 reg_data &= ~0x00100000; 1364 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data); 1365 /* FALLTHROUGH */ 1366 case em_82571: 1367 case em_82572: 1368 case em_82575: 1369 case em_82580: 1370 case em_i350: 1371 case em_ich8lan: 1372 case em_ich9lan: 1373 case em_ich10lan: 1374 case em_pchlan: 1375 case em_pch2lan: 1376 ctrl = E1000_READ_REG(hw, TXDCTL1); 1377 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | 1378 E1000_TXDCTL_FULL_TX_DESC_WB; 1379 E1000_WRITE_REG(hw, TXDCTL1, ctrl); 1380 break; 1381 } 1382 1383 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) { 1384 uint32_t gcr = E1000_READ_REG(hw, GCR); 1385 gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; 1386 E1000_WRITE_REG(hw, GCR, gcr); 1387 } 1388 /* 1389 * Clear all of the statistics registers (clear on read). It is 1390 * important that we do this after we have tried to establish link 1391 * because the symbol error count will increment wildly if there is 1392 * no link. 1393 */ 1394 em_clear_hw_cntrs(hw); 1395 /* 1396 * ICH8 No-snoop bits are opposite polarity. Set to snoop by default 1397 * after reset. 1398 */ 1399 if (hw->mac_type == em_ich8lan || 1400 hw->mac_type == em_ich9lan || 1401 hw->mac_type == em_ich10lan || 1402 hw->mac_type == em_pchlan || 1403 hw->mac_type == em_pch2lan) { 1404 if (hw->mac_type == em_ich8lan) 1405 snoop = PCI_EX_82566_SNOOP_ALL; 1406 else 1407 snoop = (u_int32_t) ~ (PCI_EX_NO_SNOOP_ALL); 1408 1409 em_set_pci_ex_no_snoop(hw, snoop); 1410 } 1411 1412 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER || 1413 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) { 1414 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1415 /* 1416 * Relaxed ordering must be disabled to avoid a parity error 1417 * crash in a PCI slot. 1418 */ 1419 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 1420 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1421 } 1422 return ret_val; 1423 } 1424 1425 /****************************************************************************** 1426 * Adjust SERDES output amplitude based on EEPROM setting. 1427 * 1428 * hw - Struct containing variables accessed by shared code. 1429 *****************************************************************************/ 1430 static int32_t 1431 em_adjust_serdes_amplitude(struct em_hw *hw) 1432 { 1433 uint16_t eeprom_data; 1434 int32_t ret_val; 1435 DEBUGFUNC("em_adjust_serdes_amplitude"); 1436 1437 if (hw->media_type != em_media_type_internal_serdes || 1438 hw->mac_type == em_82575) 1439 return E1000_SUCCESS; 1440 1441 switch (hw->mac_type) { 1442 case em_82545_rev_3: 1443 case em_82546_rev_3: 1444 break; 1445 default: 1446 return E1000_SUCCESS; 1447 } 1448 1449 ret_val = em_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data); 1450 if (ret_val) { 1451 return ret_val; 1452 } 1453 if (eeprom_data != EEPROM_RESERVED_WORD) { 1454 /* Adjust SERDES output amplitude only. */ 1455 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK; 1456 ret_val = em_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, 1457 eeprom_data); 1458 if (ret_val) 1459 return ret_val; 1460 } 1461 return E1000_SUCCESS; 1462 } 1463 1464 /****************************************************************************** 1465 * Configures flow control and link settings. 1466 * 1467 * hw - Struct containing variables accessed by shared code 1468 * 1469 * Determines which flow control settings to use. Calls the appropriate media- 1470 * specific link configuration function. Configures the flow control settings. 1471 * Assuming the adapter has a valid link partner, a valid link should be 1472 * established. Assumes the hardware has previously been reset and the 1473 * transmitter and receiver are not enabled. 1474 *****************************************************************************/ 1475 int32_t 1476 em_setup_link(struct em_hw *hw) 1477 { 1478 uint32_t ctrl_ext; 1479 int32_t ret_val; 1480 uint16_t eeprom_data; 1481 uint16_t eeprom_control2_reg_offset; 1482 DEBUGFUNC("em_setup_link"); 1483 1484 eeprom_control2_reg_offset = 1485 (hw->mac_type != em_icp_xxxx) 1486 ? EEPROM_INIT_CONTROL2_REG 1487 : EEPROM_INIT_CONTROL3_ICP_xxxx(hw->icp_xxxx_port_num); 1488 /* 1489 * In the case of the phy reset being blocked, we already have a 1490 * link. We do not have to set it up again. 1491 */ 1492 if (em_check_phy_reset_block(hw)) 1493 return E1000_SUCCESS; 1494 /* 1495 * Read and store word 0x0F of the EEPROM. This word contains bits 1496 * that determine the hardware's default PAUSE (flow control) mode, a 1497 * bit that determines whether the HW defaults to enabling or 1498 * disabling auto-negotiation, and the direction of the SW defined 1499 * pins. If there is no SW over-ride of the flow control setting, 1500 * then the variable hw->fc will be initialized based on a value in 1501 * the EEPROM. 1502 */ 1503 if (hw->fc == E1000_FC_DEFAULT) { 1504 switch (hw->mac_type) { 1505 case em_ich8lan: 1506 case em_ich9lan: 1507 case em_ich10lan: 1508 case em_pchlan: 1509 case em_pch2lan: 1510 case em_82573: 1511 case em_82574: 1512 hw->fc = E1000_FC_FULL; 1513 break; 1514 default: 1515 ret_val = em_read_eeprom(hw, 1516 eeprom_control2_reg_offset, 1, &eeprom_data); 1517 if (ret_val) { 1518 DEBUGOUT("EEPROM Read Error\n"); 1519 return -E1000_ERR_EEPROM; 1520 } 1521 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0) 1522 hw->fc = E1000_FC_NONE; 1523 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 1524 EEPROM_WORD0F_ASM_DIR) 1525 hw->fc = E1000_FC_TX_PAUSE; 1526 else 1527 hw->fc = E1000_FC_FULL; 1528 break; 1529 } 1530 } 1531 /* 1532 * We want to save off the original Flow Control configuration just 1533 * in case we get disconnected and then reconnected into a different 1534 * hub or switch with different Flow Control capabilities. 1535 */ 1536 if (hw->mac_type == em_82542_rev2_0) 1537 hw->fc &= (~E1000_FC_TX_PAUSE); 1538 1539 if ((hw->mac_type < em_82543) && (hw->report_tx_early == 1)) 1540 hw->fc &= (~E1000_FC_RX_PAUSE); 1541 1542 hw->original_fc = hw->fc; 1543 1544 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc); 1545 /* 1546 * Take the 4 bits from EEPROM word 0x0F that determine the initial 1547 * polarity value for the SW controlled pins, and setup the Extended 1548 * Device Control reg with that info. This is needed because one of 1549 * the SW controlled pins is used for signal detection. So this 1550 * should be done before em_setup_pcs_link() or em_phy_setup() is 1551 * called. 1552 */ 1553 if (hw->mac_type == em_82543) { 1554 ret_val = em_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1555 1, &eeprom_data); 1556 if (ret_val) { 1557 DEBUGOUT("EEPROM Read Error\n"); 1558 return -E1000_ERR_EEPROM; 1559 } 1560 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << 1561 SWDPIO__EXT_SHIFT); 1562 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1563 } 1564 /* Make sure we have a valid PHY */ 1565 ret_val = em_detect_gig_phy(hw); 1566 if (ret_val) { 1567 DEBUGOUT("Error, did not detect valid phy.\n"); 1568 if (hw->mac_type == em_icp_xxxx) 1569 return E1000_DEFER_INIT; 1570 else 1571 return ret_val; 1572 } 1573 DEBUGOUT1("Phy ID = %x \n", hw->phy_id); 1574 1575 /* Call the necessary subroutine to configure the link. */ 1576 switch (hw->media_type) { 1577 case em_media_type_copper: 1578 case em_media_type_oem: 1579 ret_val = em_setup_copper_link(hw); 1580 break; 1581 default: 1582 ret_val = em_setup_fiber_serdes_link(hw); 1583 break; 1584 } 1585 /* 1586 * Initialize the flow control address, type, and PAUSE timer 1587 * registers to their default values. This is done even if flow 1588 * control is disabled, because it does not hurt anything to 1589 * initialize these registers. 1590 */ 1591 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n" 1592 ); 1593 1594 /* 1595 * FCAL/H and FCT are hardcoded to standard values in 1596 * em_ich8lan / em_ich9lan / em_ich10lan. 1597 */ 1598 if (hw->mac_type != em_ich8lan && 1599 hw->mac_type != em_ich9lan && 1600 hw->mac_type != em_ich10lan && 1601 hw->mac_type != em_pchlan && 1602 hw->mac_type != em_pch2lan) { 1603 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE); 1604 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH); 1605 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW); 1606 } 1607 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time); 1608 1609 if (hw->phy_type == em_phy_82577 || 1610 hw->phy_type == em_phy_82578 || 1611 hw->phy_type == em_phy_82579) { 1612 E1000_WRITE_REG(hw, FCRTV_PCH, 0x1000); 1613 em_write_phy_reg(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27), 1614 hw->fc_pause_time); 1615 } 1616 1617 /* 1618 * Set the flow control receive threshold registers. Normally, these 1619 * registers will be set to a default threshold that may be adjusted 1620 * later by the driver's runtime code. However, if the ability to 1621 * transmit pause frames in not enabled, then these registers will be 1622 * set to 0. 1623 */ 1624 if (!(hw->fc & E1000_FC_TX_PAUSE)) { 1625 E1000_WRITE_REG(hw, FCRTL, 0); 1626 E1000_WRITE_REG(hw, FCRTH, 0); 1627 } else { 1628 /* 1629 * We need to set up the Receive Threshold high and low water 1630 * marks as well as (optionally) enabling the transmission of 1631 * XON frames. 1632 */ 1633 if (hw->fc_send_xon) { 1634 E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water 1635 | E1000_FCRTL_XONE)); 1636 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); 1637 } else { 1638 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water); 1639 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); 1640 } 1641 } 1642 return ret_val; 1643 } 1644 1645 void 1646 em_power_up_serdes_link_82575(struct em_hw *hw) 1647 { 1648 uint32_t reg; 1649 1650 /* Enable PCS to turn on link */ 1651 reg = E1000_READ_REG(hw, PCS_CFG0); 1652 reg |= E1000_PCS_CFG_PCS_EN; 1653 E1000_WRITE_REG(hw, PCS_CFG0, reg); 1654 1655 /* Power up the laser */ 1656 reg = E1000_READ_REG(hw, CTRL_EXT); 1657 reg &= ~E1000_CTRL_EXT_SDP3_DATA; 1658 E1000_WRITE_REG(hw, CTRL_EXT, reg); 1659 1660 /* flush the write to verify completion */ 1661 E1000_WRITE_FLUSH(hw); 1662 delay(5); 1663 } 1664 1665 /****************************************************************************** 1666 * Sets up link for a fiber based or serdes based adapter 1667 * 1668 * hw - Struct containing variables accessed by shared code 1669 * 1670 * Manipulates Physical Coding Sublayer functions in order to configure 1671 * link. Assumes the hardware has been previously reset and the transmitter 1672 * and receiver are not enabled. 1673 *****************************************************************************/ 1674 static int32_t 1675 em_setup_fiber_serdes_link(struct em_hw *hw) 1676 { 1677 uint32_t ctrl, ctrl_ext, reg; 1678 uint32_t status; 1679 uint32_t txcw = 0; 1680 uint32_t i; 1681 uint32_t signal = 0; 1682 int32_t ret_val; 1683 DEBUGFUNC("em_setup_fiber_serdes_link"); 1684 /* 1685 * On 82571 and 82572 Fiber connections, SerDes loopback mode 1686 * persists until explicitly turned off or a power cycle is 1687 * performed. A read to the register does not indicate its status. 1688 * Therefore, we ensure loopback mode is disabled during 1689 * initialization. 1690 */ 1691 if (hw->mac_type == em_82571 || hw->mac_type == em_82572 || 1692 hw->mac_type == em_82575) 1693 E1000_WRITE_REG(hw, SCTL, E1000_DISABLE_SERDES_LOOPBACK); 1694 1695 if (hw->mac_type == em_82575) 1696 em_power_up_serdes_link_82575(hw); 1697 1698 /* 1699 * On adapters with a MAC newer than 82544, SWDP 1 will be set when 1700 * the optics detect a signal. On older adapters, it will be cleared 1701 * when there is a signal. This applies to fiber media only. If 1702 * we're on serdes media, adjust the output amplitude to value set in 1703 * the EEPROM. 1704 */ 1705 ctrl = E1000_READ_REG(hw, CTRL); 1706 if (hw->media_type == em_media_type_fiber) 1707 signal = (hw->mac_type > em_82544) ? E1000_CTRL_SWDPIN1 : 0; 1708 1709 ret_val = em_adjust_serdes_amplitude(hw); 1710 if (ret_val) 1711 return ret_val; 1712 1713 /* Take the link out of reset */ 1714 ctrl &= ~(E1000_CTRL_LRST); 1715 1716 if (hw->mac_type == em_82575) { 1717 /* set both sw defined pins on 82575/82576*/ 1718 ctrl |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1; 1719 1720 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1721 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) { 1722 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: 1723 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES: 1724 /* the backplane is always connected */ 1725 reg = E1000_READ_REG(hw, PCS_LCTL); 1726 reg |= E1000_PCS_LCTL_FORCE_FCTRL; 1727 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL; 1728 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */ 1729 DEBUGOUT("Configuring Forced Link\n"); 1730 E1000_WRITE_REG(hw, PCS_LCTL, reg); 1731 em_force_mac_fc(hw); 1732 hw->autoneg_failed = 0; 1733 return E1000_SUCCESS; 1734 break; 1735 default: 1736 /* Set switch control to serdes energy detect */ 1737 reg = E1000_READ_REG(hw, CONNSW); 1738 reg |= E1000_CONNSW_ENRGSRC; 1739 E1000_WRITE_REG(hw, CONNSW, reg); 1740 break; 1741 } 1742 } 1743 1744 /* Adjust VCO speed to improve BER performance */ 1745 ret_val = em_set_vco_speed(hw); 1746 if (ret_val) 1747 return ret_val; 1748 1749 em_config_collision_dist(hw); 1750 /* 1751 * Check for a software override of the flow control settings, and 1752 * setup the device accordingly. If auto-negotiation is enabled, 1753 * then software will have to set the "PAUSE" bits to the correct 1754 * value in the Tranmsit Config Word Register (TXCW) and re-start 1755 * auto-negotiation. However, if auto-negotiation is disabled, then 1756 * software will have to manually configure the two flow control 1757 * enable bits in the CTRL register. 1758 * 1759 * The possible values of the "fc" parameter are: 0: Flow control is 1760 * completely disabled 1: Rx flow control is enabled (we can receive 1761 * pause frames, but not send pause frames). 2: Tx flow control is 1762 * enabled (we can send pause frames but we do not support receiving 1763 * pause frames). 3: Both Rx and TX flow control (symmetric) are 1764 * enabled. 1765 */ 1766 switch (hw->fc) { 1767 case E1000_FC_NONE: 1768 /* 1769 * Flow control is completely disabled by a software 1770 * over-ride. 1771 */ 1772 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 1773 break; 1774 case E1000_FC_RX_PAUSE: 1775 /* 1776 * RX Flow control is enabled and TX Flow control is disabled 1777 * by a software over-ride. Since there really isn't a way to 1778 * advertise that we are capable of RX Pause ONLY, we will 1779 * advertise that we support both symmetric and asymmetric RX 1780 * PAUSE. Later, we will disable the adapter's ability to 1781 * send PAUSE frames. 1782 */ 1783 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | 1784 E1000_TXCW_PAUSE_MASK); 1785 break; 1786 case E1000_FC_TX_PAUSE: 1787 /* 1788 * TX Flow control is enabled, and RX Flow control is 1789 * disabled, by a software over-ride. 1790 */ 1791 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 1792 break; 1793 case E1000_FC_FULL: 1794 /* 1795 * Flow control (both RX and TX) is enabled by a software 1796 * over-ride. 1797 */ 1798 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | 1799 E1000_TXCW_PAUSE_MASK); 1800 break; 1801 default: 1802 DEBUGOUT("Flow control param set incorrectly\n"); 1803 return -E1000_ERR_CONFIG; 1804 break; 1805 } 1806 /* 1807 * Since auto-negotiation is enabled, take the link out of reset (the 1808 * link will be in reset, because we previously reset the chip). This 1809 * will restart auto-negotiation. If auto-neogtiation is successful 1810 * then the link-up status bit will be set and the flow control 1811 * enable bits (RFCE and TFCE) will be set according to their 1812 * negotiated value. 1813 */ 1814 DEBUGOUT("Auto-negotiation enabled\n"); 1815 1816 E1000_WRITE_REG(hw, TXCW, txcw); 1817 E1000_WRITE_REG(hw, CTRL, ctrl); 1818 E1000_WRITE_FLUSH(hw); 1819 1820 hw->txcw = txcw; 1821 msec_delay(1); 1822 /* 1823 * If we have a signal (the cable is plugged in) then poll for a 1824 * "Link-Up" indication in the Device Status Register. Time-out if a 1825 * link isn't seen in 500 milliseconds seconds (Auto-negotiation 1826 * should complete in less than 500 milliseconds even if the other 1827 * end is doing it in SW). For internal serdes, we just assume a 1828 * signal is present, then poll. 1829 */ 1830 if (hw->media_type == em_media_type_internal_serdes || 1831 (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) { 1832 DEBUGOUT("Looking for Link\n"); 1833 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) { 1834 msec_delay(10); 1835 status = E1000_READ_REG(hw, STATUS); 1836 if (status & E1000_STATUS_LU) 1837 break; 1838 } 1839 if (i == (LINK_UP_TIMEOUT / 10)) { 1840 DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 1841 hw->autoneg_failed = 1; 1842 /* 1843 * AutoNeg failed to achieve a link, so we'll call 1844 * em_check_for_link. This routine will force the 1845 * link up if we detect a signal. This will allow us 1846 * to communicate with non-autonegotiating link 1847 * partners. 1848 */ 1849 ret_val = em_check_for_link(hw); 1850 if (ret_val) { 1851 DEBUGOUT("Error while checking for link\n"); 1852 return ret_val; 1853 } 1854 hw->autoneg_failed = 0; 1855 } else { 1856 hw->autoneg_failed = 0; 1857 DEBUGOUT("Valid Link Found\n"); 1858 } 1859 } else { 1860 DEBUGOUT("No Signal Detected\n"); 1861 } 1862 return E1000_SUCCESS; 1863 } 1864 1865 /****************************************************************************** 1866 * Make sure we have a valid PHY and change PHY mode before link setup. 1867 * 1868 * hw - Struct containing variables accessed by shared code 1869 *****************************************************************************/ 1870 static int32_t 1871 em_copper_link_preconfig(struct em_hw *hw) 1872 { 1873 uint32_t ctrl; 1874 int32_t ret_val; 1875 uint16_t phy_data; 1876 DEBUGFUNC("em_copper_link_preconfig"); 1877 1878 ctrl = E1000_READ_REG(hw, CTRL); 1879 /* 1880 * With 82543, we need to force speed and duplex on the MAC equal to 1881 * what the PHY speed and duplex configuration is. In addition, we 1882 * need to perform a hardware reset on the PHY to take it out of 1883 * reset. 1884 */ 1885 if (hw->mac_type > em_82543) { 1886 ctrl |= E1000_CTRL_SLU; 1887 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1888 E1000_WRITE_REG(hw, CTRL, ctrl); 1889 } else { 1890 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | 1891 E1000_CTRL_SLU); 1892 E1000_WRITE_REG(hw, CTRL, ctrl); 1893 ret_val = em_phy_hw_reset(hw); 1894 if (ret_val) 1895 return ret_val; 1896 } 1897 1898 /* Set PHY to class A mode (if necessary) */ 1899 ret_val = em_set_phy_mode(hw); 1900 if (ret_val) 1901 return ret_val; 1902 1903 if ((hw->mac_type == em_82545_rev_3) || 1904 (hw->mac_type == em_82546_rev_3)) { 1905 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 1906 &phy_data); 1907 phy_data |= 0x00000008; 1908 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 1909 phy_data); 1910 } 1911 if (hw->mac_type <= em_82543 || 1912 hw->mac_type == em_82541 || hw->mac_type == em_82547 || 1913 hw->mac_type == em_82541_rev_2 || hw->mac_type == em_82547_rev_2) 1914 hw->phy_reset_disable = FALSE; 1915 1916 return E1000_SUCCESS; 1917 } 1918 1919 /****************************************************************************** 1920 * Copper link setup for em_phy_igp series. 1921 * 1922 * hw - Struct containing variables accessed by shared code 1923 *****************************************************************************/ 1924 static int32_t 1925 em_copper_link_igp_setup(struct em_hw *hw) 1926 { 1927 uint32_t led_ctrl; 1928 int32_t ret_val; 1929 uint16_t phy_data; 1930 DEBUGFUNC("em_copper_link_igp_setup"); 1931 1932 if (hw->phy_reset_disable) 1933 return E1000_SUCCESS; 1934 1935 ret_val = em_phy_reset(hw); 1936 if (ret_val) { 1937 DEBUGOUT("Error Resetting the PHY\n"); 1938 return ret_val; 1939 } 1940 /* Wait 15ms for MAC to configure PHY from eeprom settings */ 1941 msec_delay(15); 1942 if (hw->mac_type != em_ich8lan && 1943 hw->mac_type != em_ich9lan && 1944 hw->mac_type != em_ich10lan) { 1945 /* Configure activity LED after PHY reset */ 1946 led_ctrl = E1000_READ_REG(hw, LEDCTL); 1947 led_ctrl &= IGP_ACTIVITY_LED_MASK; 1948 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 1949 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 1950 } 1951 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */ 1952 if (hw->phy_type == em_phy_igp) { 1953 /* disable lplu d3 during driver init */ 1954 ret_val = em_set_d3_lplu_state(hw, FALSE); 1955 if (ret_val) { 1956 DEBUGOUT("Error Disabling LPLU D3\n"); 1957 return ret_val; 1958 } 1959 } 1960 /* disable lplu d0 during driver init */ 1961 if (hw->mac_type == em_pchlan || 1962 hw->mac_type == em_pch2lan) 1963 ret_val = em_set_lplu_state_pchlan(hw, FALSE); 1964 else 1965 ret_val = em_set_d0_lplu_state(hw, FALSE); 1966 if (ret_val) { 1967 DEBUGOUT("Error Disabling LPLU D0\n"); 1968 return ret_val; 1969 } 1970 /* Configure mdi-mdix settings */ 1971 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 1972 if (ret_val) 1973 return ret_val; 1974 1975 if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) { 1976 hw->dsp_config_state = em_dsp_config_disabled; 1977 /* Force MDI for earlier revs of the IGP PHY */ 1978 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | 1979 IGP01E1000_PSCR_FORCE_MDI_MDIX); 1980 hw->mdix = 1; 1981 1982 } else { 1983 hw->dsp_config_state = em_dsp_config_enabled; 1984 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 1985 1986 switch (hw->mdix) { 1987 case 1: 1988 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 1989 break; 1990 case 2: 1991 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; 1992 break; 1993 case 0: 1994 default: 1995 phy_data |= IGP01E1000_PSCR_AUTO_MDIX; 1996 break; 1997 } 1998 } 1999 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 2000 if (ret_val) 2001 return ret_val; 2002 2003 /* set auto-master slave resolution settings */ 2004 if (hw->autoneg) { 2005 em_ms_type phy_ms_setting = hw->master_slave; 2006 if (hw->ffe_config_state == em_ffe_config_active) 2007 hw->ffe_config_state = em_ffe_config_enabled; 2008 2009 if (hw->dsp_config_state == em_dsp_config_activated) 2010 hw->dsp_config_state = em_dsp_config_enabled; 2011 /* 2012 * when autonegotiation advertisement is only 1000Mbps then 2013 * we should disable SmartSpeed and enable Auto MasterSlave 2014 * resolution as hardware default. 2015 */ 2016 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) { 2017 /* Disable SmartSpeed */ 2018 ret_val = em_read_phy_reg(hw, 2019 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2020 if (ret_val) 2021 return ret_val; 2022 2023 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2024 ret_val = em_write_phy_reg(hw, 2025 IGP01E1000_PHY_PORT_CONFIG, phy_data); 2026 if (ret_val) 2027 return ret_val; 2028 /* Set auto Master/Slave resolution process */ 2029 ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, 2030 &phy_data); 2031 if (ret_val) 2032 return ret_val; 2033 2034 phy_data &= ~CR_1000T_MS_ENABLE; 2035 ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL, 2036 phy_data); 2037 if (ret_val) 2038 return ret_val; 2039 } 2040 ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); 2041 if (ret_val) 2042 return ret_val; 2043 2044 /* load defaults for future use */ 2045 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ? 2046 ((phy_data & CR_1000T_MS_VALUE) ? em_ms_force_master : 2047 em_ms_force_slave) : em_ms_auto; 2048 2049 switch (phy_ms_setting) { 2050 case em_ms_force_master: 2051 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 2052 break; 2053 case em_ms_force_slave: 2054 phy_data |= CR_1000T_MS_ENABLE; 2055 phy_data &= ~(CR_1000T_MS_VALUE); 2056 break; 2057 case em_ms_auto: 2058 phy_data &= ~CR_1000T_MS_ENABLE; 2059 break; 2060 default: 2061 break; 2062 } 2063 ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); 2064 if (ret_val) 2065 return ret_val; 2066 } 2067 return E1000_SUCCESS; 2068 } 2069 2070 /****************************************************************************** 2071 * Copper link setup for em_phy_gg82563 series. 2072 * 2073 * hw - Struct containing variables accessed by shared code 2074 *****************************************************************************/ 2075 static int32_t 2076 em_copper_link_ggp_setup(struct em_hw *hw) 2077 { 2078 int32_t ret_val; 2079 uint16_t phy_data; 2080 uint32_t reg_data; 2081 DEBUGFUNC("em_copper_link_ggp_setup"); 2082 2083 if (!hw->phy_reset_disable) { 2084 2085 /* Enable CRS on TX for half-duplex operation. */ 2086 ret_val = em_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 2087 &phy_data); 2088 if (ret_val) 2089 return ret_val; 2090 2091 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 2092 /* Use 25MHz for both link down and 1000BASE-T for Tx clock */ 2093 phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ; 2094 2095 ret_val = em_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 2096 phy_data); 2097 if (ret_val) 2098 return ret_val; 2099 /* 2100 * Options: MDI/MDI-X = 0 (default) 0 - Auto for all speeds 1 2101 * - MDI mode 2 - MDI-X mode 3 - Auto for 1000Base-T only 2102 * (MDI-X for 10/100Base-T modes) 2103 */ 2104 ret_val = em_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, 2105 &phy_data); 2106 2107 if (ret_val) 2108 return ret_val; 2109 2110 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK; 2111 2112 switch (hw->mdix) { 2113 case 1: 2114 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI; 2115 break; 2116 case 2: 2117 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX; 2118 break; 2119 case 0: 2120 default: 2121 phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO; 2122 break; 2123 } 2124 /* 2125 * Options: disable_polarity_correction = 0 (default) 2126 * Automatic Correction for Reversed Cable Polarity 0 - 2127 * Disabled 1 - Enabled 2128 */ 2129 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 2130 if (hw->disable_polarity_correction == 1) 2131 phy_data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 2132 ret_val = em_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, 2133 phy_data); 2134 2135 if (ret_val) 2136 return ret_val; 2137 2138 /* SW Reset the PHY so all changes take effect */ 2139 ret_val = em_phy_reset(hw); 2140 if (ret_val) { 2141 DEBUGOUT("Error Resetting the PHY\n"); 2142 return ret_val; 2143 } 2144 } /* phy_reset_disable */ 2145 if (hw->mac_type == em_80003es2lan) { 2146 /* Bypass RX and TX FIFO's */ 2147 ret_val = em_write_kmrn_reg(hw, 2148 E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL, 2149 E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS | 2150 E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS); 2151 if (ret_val) 2152 return ret_val; 2153 2154 ret_val = em_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, 2155 &phy_data); 2156 if (ret_val) 2157 return ret_val; 2158 2159 phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG; 2160 ret_val = em_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, 2161 phy_data); 2162 2163 if (ret_val) 2164 return ret_val; 2165 2166 reg_data = E1000_READ_REG(hw, CTRL_EXT); 2167 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK); 2168 E1000_WRITE_REG(hw, CTRL_EXT, reg_data); 2169 2170 ret_val = em_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, 2171 &phy_data); 2172 if (ret_val) 2173 return ret_val; 2174 /* 2175 * Do not init these registers when the HW is in IAMT mode, 2176 * since the firmware will have already initialized them. We 2177 * only initialize them if the HW is not in IAMT mode. 2178 */ 2179 if (em_check_mng_mode(hw) == FALSE) { 2180 /* Enable Electrical Idle on the PHY */ 2181 phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; 2182 ret_val = em_write_phy_reg(hw, 2183 GG82563_PHY_PWR_MGMT_CTRL, phy_data); 2184 if (ret_val) 2185 return ret_val; 2186 2187 ret_val = em_read_phy_reg(hw, 2188 GG82563_PHY_KMRN_MODE_CTRL, &phy_data); 2189 if (ret_val) 2190 return ret_val; 2191 2192 phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 2193 ret_val = em_write_phy_reg(hw, 2194 GG82563_PHY_KMRN_MODE_CTRL, phy_data); 2195 2196 if (ret_val) 2197 return ret_val; 2198 } 2199 /* 2200 * Workaround: Disable padding in Kumeran interface in the 2201 * MAC and in the PHY to avoid CRC errors. 2202 */ 2203 ret_val = em_read_phy_reg(hw, GG82563_PHY_INBAND_CTRL, 2204 &phy_data); 2205 if (ret_val) 2206 return ret_val; 2207 phy_data |= GG82563_ICR_DIS_PADDING; 2208 ret_val = em_write_phy_reg(hw, GG82563_PHY_INBAND_CTRL, 2209 phy_data); 2210 if (ret_val) 2211 return ret_val; 2212 } 2213 return E1000_SUCCESS; 2214 } 2215 2216 /****************************************************************************** 2217 * Copper link setup for em_phy_m88 series. 2218 * 2219 * hw - Struct containing variables accessed by shared code 2220 *****************************************************************************/ 2221 static int32_t 2222 em_copper_link_mgp_setup(struct em_hw *hw) 2223 { 2224 int32_t ret_val; 2225 uint16_t phy_data; 2226 DEBUGFUNC("em_copper_link_mgp_setup"); 2227 2228 if (hw->phy_reset_disable) 2229 return E1000_SUCCESS; 2230 2231 /* disable lplu d0 during driver init */ 2232 if (hw->mac_type == em_pchlan || 2233 hw->mac_type == em_pch2lan) 2234 ret_val = em_set_lplu_state_pchlan(hw, FALSE); 2235 2236 /* Enable CRS on TX. This must be set for half-duplex operation. */ 2237 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 2238 if (ret_val) 2239 return ret_val; 2240 2241 if (hw->phy_id == M88E1141_E_PHY_ID) { 2242 phy_data |= 0x00000008; 2243 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 2244 phy_data); 2245 if (ret_val) 2246 return ret_val; 2247 2248 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 2249 &phy_data); 2250 if (ret_val) 2251 return ret_val; 2252 2253 phy_data &= ~M88E1000_PSCR_ASSERT_CRS_ON_TX; 2254 2255 } 2256 /* For BM PHY this bit is downshift enable */ 2257 else if (hw->phy_type != em_phy_bm) 2258 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 2259 /* 2260 * Options: MDI/MDI-X = 0 (default) 0 - Auto for all speeds 1 - MDI 2261 * mode 2 - MDI-X mode 3 - Auto for 1000Base-T only (MDI-X for 2262 * 10/100Base-T modes) 2263 */ 2264 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 2265 2266 switch (hw->mdix) { 2267 case 1: 2268 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 2269 break; 2270 case 2: 2271 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 2272 break; 2273 case 3: 2274 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 2275 break; 2276 case 0: 2277 default: 2278 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 2279 break; 2280 } 2281 /* 2282 * Options: disable_polarity_correction = 0 (default) Automatic 2283 * Correction for Reversed Cable Polarity 0 - Disabled 1 - Enabled 2284 */ 2285 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 2286 if (hw->disable_polarity_correction == 1) 2287 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 2288 2289 /* Enable downshift on BM (disabled by default) */ 2290 if (hw->phy_type == em_phy_bm) 2291 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT; 2292 2293 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 2294 if (ret_val) 2295 return ret_val; 2296 2297 if (((hw->phy_type == em_phy_m88) && 2298 (hw->phy_revision < M88E1011_I_REV_4) && 2299 (hw->phy_id != BME1000_E_PHY_ID)) || 2300 (hw->phy_type == em_phy_oem)) { 2301 /* 2302 * Force TX_CLK in the Extended PHY Specific Control Register 2303 * to 25MHz clock. 2304 */ 2305 ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 2306 &phy_data); 2307 if (ret_val) 2308 return ret_val; 2309 2310 if (hw->phy_type == em_phy_oem) { 2311 phy_data |= M88E1000_EPSCR_TX_TIME_CTRL; 2312 phy_data |= M88E1000_EPSCR_RX_TIME_CTRL; 2313 } 2314 phy_data |= M88E1000_EPSCR_TX_CLK_25; 2315 2316 if ((hw->phy_revision == E1000_REVISION_2) && 2317 (hw->phy_id == M88E1111_I_PHY_ID)) { 2318 /* Vidalia Phy, set the downshift counter to 5x */ 2319 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK); 2320 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; 2321 ret_val = em_write_phy_reg(hw, 2322 M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 2323 if (ret_val) 2324 return ret_val; 2325 } else { 2326 /* Configure Master and Slave downshift values */ 2327 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 2328 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 2329 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 2330 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 2331 ret_val = em_write_phy_reg(hw, 2332 M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 2333 if (ret_val) 2334 return ret_val; 2335 } 2336 } 2337 if ((hw->phy_type == em_phy_bm) && (hw->phy_revision == 1)) { 2338 /* 2339 * Set PHY page 0, register 29 to 0x0003 2340 * The next two writes are supposed to lower BER for gig 2341 * conection 2342 */ 2343 ret_val = em_write_phy_reg(hw, BM_REG_BIAS1, 0x0003); 2344 if (ret_val) 2345 return ret_val; 2346 2347 /* Set PHY page 0, register 30 to 0x0000 */ 2348 ret_val = em_write_phy_reg(hw, BM_REG_BIAS2, 0x0000); 2349 if (ret_val) 2350 return ret_val; 2351 } 2352 if (hw->phy_type == em_phy_82578) { 2353 ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 2354 &phy_data); 2355 if (ret_val) 2356 return ret_val; 2357 2358 /* 82578 PHY - set the downshift count to 1x. */ 2359 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE; 2360 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK; 2361 ret_val = em_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 2362 phy_data); 2363 if (ret_val) 2364 return ret_val; 2365 } 2366 /* SW Reset the PHY so all changes take effect */ 2367 ret_val = em_phy_reset(hw); 2368 if (ret_val) { 2369 DEBUGOUT("Error Resetting the PHY\n"); 2370 return ret_val; 2371 } 2372 return E1000_SUCCESS; 2373 } 2374 2375 /****************************************************************************** 2376 * Copper link setup for em_phy_82577 series. 2377 * 2378 * hw - Struct containing variables accessed by shared code 2379 *****************************************************************************/ 2380 static int32_t 2381 em_copper_link_82577_setup(struct em_hw *hw) 2382 { 2383 int32_t ret_val; 2384 uint16_t phy_data; 2385 uint32_t led_ctl; 2386 DEBUGFUNC("em_copper_link_82577_setup"); 2387 2388 if (hw->phy_reset_disable) 2389 return E1000_SUCCESS; 2390 2391 /* Enable CRS on TX for half-duplex operation. */ 2392 ret_val = em_read_phy_reg(hw, I82577_PHY_CFG_REG, &phy_data); 2393 if (ret_val) 2394 return ret_val; 2395 2396 phy_data |= I82577_PHY_CFG_ENABLE_CRS_ON_TX | 2397 I82577_PHY_CFG_ENABLE_DOWNSHIFT; 2398 2399 ret_val = em_write_phy_reg(hw, I82577_PHY_CFG_REG, phy_data); 2400 if (ret_val) 2401 return ret_val; 2402 2403 /* Wait 15ms for MAC to configure PHY from eeprom settings */ 2404 msec_delay(15); 2405 led_ctl = hw->ledctl_mode1; 2406 2407 /* disable lplu d0 during driver init */ 2408 ret_val = em_set_lplu_state_pchlan(hw, FALSE); 2409 if (ret_val) { 2410 DEBUGOUT("Error Disabling LPLU D0\n"); 2411 return ret_val; 2412 } 2413 2414 E1000_WRITE_REG(hw, LEDCTL, led_ctl); 2415 2416 return E1000_SUCCESS; 2417 } 2418 2419 static int32_t 2420 em_copper_link_82580_setup(struct em_hw *hw) 2421 { 2422 int32_t ret_val; 2423 uint16_t phy_data; 2424 2425 if (hw->phy_reset_disable) 2426 return E1000_SUCCESS; 2427 2428 ret_val = em_phy_reset(hw); 2429 if (ret_val) 2430 goto out; 2431 2432 /* Enable CRS on TX. This must be set for half-duplex operation. */ 2433 ret_val = em_read_phy_reg(hw, I82580_CFG_REG, &phy_data); 2434 if (ret_val) 2435 goto out; 2436 2437 phy_data |= I82580_CFG_ASSERT_CRS_ON_TX | 2438 I82580_CFG_ENABLE_DOWNSHIFT; 2439 2440 ret_val = em_write_phy_reg(hw, I82580_CFG_REG, phy_data); 2441 2442 out: 2443 return ret_val; 2444 } 2445 2446 /****************************************************************************** 2447 * Setup auto-negotiation and flow control advertisements, 2448 * and then perform auto-negotiation. 2449 * 2450 * hw - Struct containing variables accessed by shared code 2451 *****************************************************************************/ 2452 int32_t 2453 em_copper_link_autoneg(struct em_hw *hw) 2454 { 2455 int32_t ret_val; 2456 uint16_t phy_data; 2457 DEBUGFUNC("em_copper_link_autoneg"); 2458 /* 2459 * Perform some bounds checking on the hw->autoneg_advertised 2460 * parameter. If this variable is zero, then set it to the default. 2461 */ 2462 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT; 2463 /* 2464 * If autoneg_advertised is zero, we assume it was not defaulted by 2465 * the calling code so we set to advertise full capability. 2466 */ 2467 if (hw->autoneg_advertised == 0) 2468 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 2469 2470 /* IFE phy only supports 10/100 */ 2471 if (hw->phy_type == em_phy_ife) 2472 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL; 2473 2474 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); 2475 ret_val = em_phy_setup_autoneg(hw); 2476 if (ret_val) { 2477 DEBUGOUT("Error Setting up Auto-Negotiation\n"); 2478 return ret_val; 2479 } 2480 DEBUGOUT("Restarting Auto-Neg\n"); 2481 /* 2482 * Restart auto-negotiation by setting the Auto Neg Enable bit and 2483 * the Auto Neg Restart bit in the PHY control register. 2484 */ 2485 ret_val = em_read_phy_reg(hw, PHY_CTRL, &phy_data); 2486 if (ret_val) 2487 return ret_val; 2488 2489 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 2490 ret_val = em_write_phy_reg(hw, PHY_CTRL, phy_data); 2491 if (ret_val) 2492 return ret_val; 2493 /* 2494 * Does the user want to wait for Auto-Neg to complete here, or check 2495 * at a later time (for example, callback routine). 2496 */ 2497 if (hw->wait_autoneg_complete) { 2498 ret_val = em_wait_autoneg(hw); 2499 if (ret_val) { 2500 DEBUGOUT("Error while waiting for autoneg to complete\n" 2501 ); 2502 return ret_val; 2503 } 2504 } 2505 hw->get_link_status = TRUE; 2506 2507 return E1000_SUCCESS; 2508 } 2509 2510 /****************************************************************************** 2511 * Config the MAC and the PHY after link is up. 2512 * 1) Set up the MAC to the current PHY speed/duplex 2513 * if we are on 82543. If we 2514 * are on newer silicon, we only need to configure 2515 * collision distance in the Transmit Control Register. 2516 * 2) Set up flow control on the MAC to that established with 2517 * the link partner. 2518 * 3) Config DSP to improve Gigabit link quality for some PHY revisions. 2519 * 2520 * hw - Struct containing variables accessed by shared code 2521 *****************************************************************************/ 2522 int32_t 2523 em_copper_link_postconfig(struct em_hw *hw) 2524 { 2525 int32_t ret_val; 2526 DEBUGFUNC("em_copper_link_postconfig"); 2527 2528 if (hw->mac_type >= em_82544 && 2529 hw->mac_type != em_icp_xxxx) { 2530 em_config_collision_dist(hw); 2531 } else { 2532 ret_val = em_config_mac_to_phy(hw); 2533 if (ret_val) { 2534 DEBUGOUT("Error configuring MAC to PHY settings\n"); 2535 return ret_val; 2536 } 2537 } 2538 ret_val = em_config_fc_after_link_up(hw); 2539 if (ret_val) { 2540 DEBUGOUT("Error Configuring Flow Control\n"); 2541 return ret_val; 2542 } 2543 /* Config DSP to improve Giga link quality */ 2544 if (hw->phy_type == em_phy_igp) { 2545 ret_val = em_config_dsp_after_link_change(hw, TRUE); 2546 if (ret_val) { 2547 DEBUGOUT("Error Configuring DSP after link up\n"); 2548 return ret_val; 2549 } 2550 } 2551 return E1000_SUCCESS; 2552 } 2553 2554 /****************************************************************************** 2555 * Detects which PHY is present and setup the speed and duplex 2556 * 2557 * hw - Struct containing variables accessed by shared code 2558 *****************************************************************************/ 2559 static int32_t 2560 em_setup_copper_link(struct em_hw *hw) 2561 { 2562 int32_t ret_val; 2563 uint16_t i; 2564 uint16_t phy_data; 2565 uint16_t reg_data; 2566 DEBUGFUNC("em_setup_copper_link"); 2567 2568 switch (hw->mac_type) { 2569 case em_80003es2lan: 2570 case em_ich8lan: 2571 case em_ich9lan: 2572 case em_ich10lan: 2573 case em_pchlan: 2574 case em_pch2lan: 2575 /* 2576 * Set the mac to wait the maximum time between each 2577 * iteration and increase the max iterations when polling the 2578 * phy; this fixes erroneous timeouts at 10Mbps. 2579 */ 2580 ret_val = em_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF); 2581 if (ret_val) 2582 return ret_val; 2583 ret_val = em_read_kmrn_reg(hw, GG82563_REG(0x34, 9), 2584 ®_data); 2585 if (ret_val) 2586 return ret_val; 2587 reg_data |= 0x3F; 2588 ret_val = em_write_kmrn_reg(hw, GG82563_REG(0x34, 9), 2589 reg_data); 2590 if (ret_val) 2591 return ret_val; 2592 default: 2593 break; 2594 } 2595 2596 /* Check if it is a valid PHY and set PHY mode if necessary. */ 2597 ret_val = em_copper_link_preconfig(hw); 2598 if (ret_val) 2599 return ret_val; 2600 2601 switch (hw->mac_type) { 2602 case em_80003es2lan: 2603 /* Kumeran registers are written-only */ 2604 reg_data = 2605 E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT; 2606 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING; 2607 ret_val = em_write_kmrn_reg(hw, 2608 E1000_KUMCTRLSTA_OFFSET_INB_CTRL, reg_data); 2609 if (ret_val) 2610 return ret_val; 2611 break; 2612 default: 2613 break; 2614 } 2615 2616 if (hw->phy_type == em_phy_igp || 2617 hw->phy_type == em_phy_igp_3 || 2618 hw->phy_type == em_phy_igp_2) { 2619 ret_val = em_copper_link_igp_setup(hw); 2620 if (ret_val) 2621 return ret_val; 2622 } else if (hw->phy_type == em_phy_m88 || 2623 hw->phy_type == em_phy_bm || 2624 hw->phy_type == em_phy_oem || 2625 hw->phy_type == em_phy_82578) { 2626 ret_val = em_copper_link_mgp_setup(hw); 2627 if (ret_val) 2628 return ret_val; 2629 } else if (hw->phy_type == em_phy_gg82563) { 2630 ret_val = em_copper_link_ggp_setup(hw); 2631 if (ret_val) 2632 return ret_val; 2633 } else if (hw->phy_type == em_phy_82577 || 2634 hw->phy_type == em_phy_82579) { 2635 ret_val = em_copper_link_82577_setup(hw); 2636 if (ret_val) 2637 return ret_val; 2638 } else if (hw->phy_type == em_phy_82580) { 2639 ret_val = em_copper_link_82580_setup(hw); 2640 if (ret_val) 2641 return ret_val; 2642 } 2643 if (hw->autoneg) { 2644 /* 2645 * Setup autoneg and flow control advertisement and perform 2646 * autonegotiation 2647 */ 2648 ret_val = em_copper_link_autoneg(hw); 2649 if (ret_val) 2650 return ret_val; 2651 } else { 2652 /* 2653 * PHY will be set to 10H, 10F, 100H,or 100F depending on 2654 * value from forced_speed_duplex. 2655 */ 2656 DEBUGOUT("Forcing speed and duplex\n"); 2657 ret_val = em_phy_force_speed_duplex(hw); 2658 if (ret_val) { 2659 DEBUGOUT("Error Forcing Speed and Duplex\n"); 2660 return ret_val; 2661 } 2662 } 2663 /* 2664 * Check link status. Wait up to 100 microseconds for link to become 2665 * valid. 2666 */ 2667 for (i = 0; i < 10; i++) { 2668 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 2669 if (ret_val) 2670 return ret_val; 2671 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 2672 if (ret_val) 2673 return ret_val; 2674 2675 hw->icp_xxxx_is_link_up = (phy_data & MII_SR_LINK_STATUS) != 0; 2676 2677 if (phy_data & MII_SR_LINK_STATUS) { 2678 /* Config the MAC and PHY after link is up */ 2679 ret_val = em_copper_link_postconfig(hw); 2680 if (ret_val) 2681 return ret_val; 2682 2683 DEBUGOUT("Valid link established!!!\n"); 2684 return E1000_SUCCESS; 2685 } 2686 usec_delay(10); 2687 } 2688 2689 DEBUGOUT("Unable to establish link!!!\n"); 2690 return E1000_SUCCESS; 2691 } 2692 2693 /****************************************************************************** 2694 * Configure the MAC-to-PHY interface for 10/100Mbps 2695 * 2696 * hw - Struct containing variables accessed by shared code 2697 *****************************************************************************/ 2698 static int32_t 2699 em_configure_kmrn_for_10_100(struct em_hw *hw, uint16_t duplex) 2700 { 2701 int32_t ret_val = E1000_SUCCESS; 2702 uint32_t tipg; 2703 uint16_t reg_data; 2704 DEBUGFUNC("em_configure_kmrn_for_10_100"); 2705 2706 reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT; 2707 ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL, 2708 reg_data); 2709 if (ret_val) 2710 return ret_val; 2711 2712 /* Configure Transmit Inter-Packet Gap */ 2713 tipg = E1000_READ_REG(hw, TIPG); 2714 tipg &= ~E1000_TIPG_IPGT_MASK; 2715 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100; 2716 E1000_WRITE_REG(hw, TIPG, tipg); 2717 2718 ret_val = em_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); 2719 2720 if (ret_val) 2721 return ret_val; 2722 2723 if (duplex == HALF_DUPLEX) 2724 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER; 2725 else 2726 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 2727 2728 ret_val = em_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 2729 2730 return ret_val; 2731 } 2732 2733 static int32_t 2734 em_configure_kmrn_for_1000(struct em_hw *hw) 2735 { 2736 int32_t ret_val = E1000_SUCCESS; 2737 uint16_t reg_data; 2738 uint32_t tipg; 2739 DEBUGFUNC("em_configure_kmrn_for_1000"); 2740 2741 reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT; 2742 ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL, 2743 reg_data); 2744 if (ret_val) 2745 return ret_val; 2746 2747 /* Configure Transmit Inter-Packet Gap */ 2748 tipg = E1000_READ_REG(hw, TIPG); 2749 tipg &= ~E1000_TIPG_IPGT_MASK; 2750 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; 2751 E1000_WRITE_REG(hw, TIPG, tipg); 2752 2753 ret_val = em_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); 2754 2755 if (ret_val) 2756 return ret_val; 2757 2758 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 2759 ret_val = em_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 2760 2761 return ret_val; 2762 } 2763 2764 /****************************************************************************** 2765 * Configures PHY autoneg and flow control advertisement settings 2766 * 2767 * hw - Struct containing variables accessed by shared code 2768 *****************************************************************************/ 2769 int32_t 2770 em_phy_setup_autoneg(struct em_hw *hw) 2771 { 2772 int32_t ret_val; 2773 uint16_t mii_autoneg_adv_reg; 2774 uint16_t mii_1000t_ctrl_reg; 2775 DEBUGFUNC("em_phy_setup_autoneg"); 2776 2777 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 2778 ret_val = em_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 2779 if (ret_val) 2780 return ret_val; 2781 2782 if (hw->phy_type != em_phy_ife) { 2783 /* Read the MII 1000Base-T Control Register (Address 9). */ 2784 ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, 2785 &mii_1000t_ctrl_reg); 2786 if (ret_val) 2787 return ret_val; 2788 } else 2789 mii_1000t_ctrl_reg = 0; 2790 /* 2791 * Need to parse both autoneg_advertised and fc and set up the 2792 * appropriate PHY registers. First we will parse for 2793 * autoneg_advertised software override. Since we can advertise a 2794 * plethora of combinations, we need to check each bit individually. 2795 */ 2796 /* 2797 * First we clear all the 10/100 mb speed bits in the Auto-Neg 2798 * Advertisement Register (Address 4) and the 1000 mb speed bits in 2799 * the 1000Base-T Control Register (Address 9). 2800 */ 2801 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK; 2802 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK; 2803 2804 DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised); 2805 2806 /* Do we want to advertise 10 Mb Half Duplex? */ 2807 if (hw->autoneg_advertised & ADVERTISE_10_HALF) { 2808 DEBUGOUT("Advertise 10mb Half duplex\n"); 2809 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 2810 } 2811 /* Do we want to advertise 10 Mb Full Duplex? */ 2812 if (hw->autoneg_advertised & ADVERTISE_10_FULL) { 2813 DEBUGOUT("Advertise 10mb Full duplex\n"); 2814 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 2815 } 2816 /* Do we want to advertise 100 Mb Half Duplex? */ 2817 if (hw->autoneg_advertised & ADVERTISE_100_HALF) { 2818 DEBUGOUT("Advertise 100mb Half duplex\n"); 2819 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 2820 } 2821 /* Do we want to advertise 100 Mb Full Duplex? */ 2822 if (hw->autoneg_advertised & ADVERTISE_100_FULL) { 2823 DEBUGOUT("Advertise 100mb Full duplex\n"); 2824 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 2825 } 2826 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 2827 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) { 2828 DEBUGOUT("Advertise 1000mb Half duplex requested, request" 2829 " denied!\n"); 2830 } 2831 /* Do we want to advertise 1000 Mb Full Duplex? */ 2832 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) { 2833 DEBUGOUT("Advertise 1000mb Full duplex\n"); 2834 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 2835 if (hw->phy_type == em_phy_ife) { 2836 DEBUGOUT("em_phy_ife is a 10/100 PHY. Gigabit speed is" 2837 " not supported.\n"); 2838 } 2839 } 2840 /* 2841 * Check for a software override of the flow control settings, and 2842 * setup the PHY advertisement registers accordingly. If 2843 * auto-negotiation is enabled, then software will have to set the 2844 * "PAUSE" bits to the correct value in the Auto-Negotiation 2845 * Advertisement Register (PHY_AUTONEG_ADV) and re-start 2846 * auto-negotiation. 2847 * 2848 * The possible values of the "fc" parameter are: 0: Flow control is 2849 * completely disabled 1: Rx flow control is enabled (we can receive 2850 * pause frames but not send pause frames). 2: Tx flow control is 2851 * enabled (we can send pause frames but we do not support receiving 2852 * pause frames). 3: Both Rx and TX flow control (symmetric) are 2853 * enabled. other: No software override. The flow control 2854 * configuration in the EEPROM is used. 2855 */ 2856 switch (hw->fc) { 2857 case E1000_FC_NONE: /* 0 */ 2858 /* 2859 * Flow control (RX & TX) is completely disabled by a 2860 * software over-ride. 2861 */ 2862 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 2863 break; 2864 case E1000_FC_RX_PAUSE:/* 1 */ 2865 /* 2866 * RX Flow control is enabled, and TX Flow control is 2867 * disabled, by a software over-ride. 2868 */ 2869 /* 2870 * Since there really isn't a way to advertise that we are 2871 * capable of RX Pause ONLY, we will advertise that we 2872 * support both symmetric and asymmetric RX PAUSE. Later (in 2873 * em_config_fc_after_link_up) we will disable the hw's 2874 * ability to send PAUSE frames. 2875 */ 2876 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 2877 break; 2878 case E1000_FC_TX_PAUSE:/* 2 */ 2879 /* 2880 * TX Flow control is enabled, and RX Flow control is 2881 * disabled, by a software over-ride. 2882 */ 2883 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 2884 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 2885 break; 2886 case E1000_FC_FULL: /* 3 */ 2887 /* 2888 * Flow control (both RX and TX) is enabled by a software 2889 * over-ride. 2890 */ 2891 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 2892 break; 2893 default: 2894 DEBUGOUT("Flow control param set incorrectly\n"); 2895 return -E1000_ERR_CONFIG; 2896 } 2897 2898 ret_val = em_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 2899 if (ret_val) 2900 return ret_val; 2901 2902 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 2903 2904 if (hw->phy_type != em_phy_ife) { 2905 ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL, 2906 mii_1000t_ctrl_reg); 2907 if (ret_val) 2908 return ret_val; 2909 } 2910 return E1000_SUCCESS; 2911 } 2912 /****************************************************************************** 2913 * Force PHY speed and duplex settings to hw->forced_speed_duplex 2914 * 2915 * hw - Struct containing variables accessed by shared code 2916 *****************************************************************************/ 2917 static int32_t 2918 em_phy_force_speed_duplex(struct em_hw *hw) 2919 { 2920 uint32_t ctrl; 2921 int32_t ret_val; 2922 uint16_t mii_ctrl_reg; 2923 uint16_t mii_status_reg; 2924 uint16_t phy_data; 2925 uint16_t i; 2926 DEBUGFUNC("em_phy_force_speed_duplex"); 2927 2928 /* Turn off Flow control if we are forcing speed and duplex. */ 2929 hw->fc = E1000_FC_NONE; 2930 2931 DEBUGOUT1("hw->fc = %d\n", hw->fc); 2932 2933 /* Read the Device Control Register. */ 2934 ctrl = E1000_READ_REG(hw, CTRL); 2935 2936 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */ 2937 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 2938 ctrl &= ~(DEVICE_SPEED_MASK); 2939 2940 /* Clear the Auto Speed Detect Enable bit. */ 2941 ctrl &= ~E1000_CTRL_ASDE; 2942 2943 /* Read the MII Control Register. */ 2944 ret_val = em_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg); 2945 if (ret_val) 2946 return ret_val; 2947 2948 /* We need to disable autoneg in order to force link and duplex. */ 2949 2950 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN; 2951 2952 /* Are we forcing Full or Half Duplex? */ 2953 if (hw->forced_speed_duplex == em_100_full || 2954 hw->forced_speed_duplex == em_10_full) { 2955 /* 2956 * We want to force full duplex so we SET the full duplex 2957 * bits in the Device and MII Control Registers. 2958 */ 2959 ctrl |= E1000_CTRL_FD; 2960 mii_ctrl_reg |= MII_CR_FULL_DUPLEX; 2961 DEBUGOUT("Full Duplex\n"); 2962 } else { 2963 /* 2964 * We want to force half duplex so we CLEAR the full duplex 2965 * bits in the Device and MII Control Registers. 2966 */ 2967 ctrl &= ~E1000_CTRL_FD; 2968 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX; 2969 DEBUGOUT("Half Duplex\n"); 2970 } 2971 2972 /* Are we forcing 100Mbps??? */ 2973 if (hw->forced_speed_duplex == em_100_full || 2974 hw->forced_speed_duplex == em_100_half) { 2975 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */ 2976 ctrl |= E1000_CTRL_SPD_100; 2977 mii_ctrl_reg |= MII_CR_SPEED_100; 2978 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); 2979 DEBUGOUT("Forcing 100mb "); 2980 } else { 2981 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */ 2982 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 2983 mii_ctrl_reg |= MII_CR_SPEED_10; 2984 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); 2985 DEBUGOUT("Forcing 10mb "); 2986 } 2987 2988 em_config_collision_dist(hw); 2989 2990 /* Write the configured values back to the Device Control Reg. */ 2991 E1000_WRITE_REG(hw, CTRL, ctrl); 2992 2993 if ((hw->phy_type == em_phy_m88) || 2994 (hw->phy_type == em_phy_gg82563) || 2995 (hw->phy_type == em_phy_bm) || 2996 (hw->phy_type == em_phy_oem || 2997 (hw->phy_type == em_phy_82578))) { 2998 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 2999 &phy_data); 3000 if (ret_val) 3001 return ret_val; 3002 /* 3003 * Clear Auto-Crossover to force MDI manually. M88E1000 3004 * requires MDI forced whenever speed are duplex are forced. 3005 */ 3006 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 3007 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 3008 phy_data); 3009 if (ret_val) 3010 return ret_val; 3011 3012 DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data); 3013 3014 /* Need to reset the PHY or these changes will be ignored */ 3015 mii_ctrl_reg |= MII_CR_RESET; 3016 3017 } 3018 /* Disable MDI-X support for 10/100 */ 3019 else if (hw->phy_type == em_phy_ife) { 3020 ret_val = em_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data); 3021 if (ret_val) 3022 return ret_val; 3023 3024 phy_data &= ~IFE_PMC_AUTO_MDIX; 3025 phy_data &= ~IFE_PMC_FORCE_MDIX; 3026 3027 ret_val = em_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, phy_data); 3028 if (ret_val) 3029 return ret_val; 3030 } else { 3031 /* 3032 * Clear Auto-Crossover to force MDI manually. IGP requires 3033 * MDI forced whenever speed or duplex are forced. 3034 */ 3035 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, 3036 &phy_data); 3037 if (ret_val) 3038 return ret_val; 3039 3040 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 3041 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 3042 3043 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, 3044 phy_data); 3045 if (ret_val) 3046 return ret_val; 3047 } 3048 3049 /* Write back the modified PHY MII control register. */ 3050 ret_val = em_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg); 3051 if (ret_val) 3052 return ret_val; 3053 3054 usec_delay(1); 3055 /* 3056 * The wait_autoneg_complete flag may be a little misleading here. 3057 * Since we are forcing speed and duplex, Auto-Neg is not enabled. 3058 * But we do want to delay for a period while forcing only so we 3059 * don't generate false No Link messages. So we will wait here only 3060 * if the user has set wait_autoneg_complete to 1, which is the 3061 * default. 3062 */ 3063 if (hw->wait_autoneg_complete) { 3064 /* We will wait for autoneg to complete. */ 3065 DEBUGOUT("Waiting for forced speed/duplex link.\n"); 3066 mii_status_reg = 0; 3067 /* 3068 * We will wait for autoneg to complete or 4.5 seconds to 3069 * expire. 3070 */ 3071 for (i = PHY_FORCE_TIME; i > 0; i--) { 3072 /* 3073 * Read the MII Status Register and wait for Auto-Neg 3074 * Complete bit to be set. 3075 */ 3076 ret_val = em_read_phy_reg(hw, PHY_STATUS, 3077 &mii_status_reg); 3078 if (ret_val) 3079 return ret_val; 3080 3081 ret_val = em_read_phy_reg(hw, PHY_STATUS, 3082 &mii_status_reg); 3083 if (ret_val) 3084 return ret_val; 3085 3086 if (mii_status_reg & MII_SR_LINK_STATUS) 3087 break; 3088 msec_delay(100); 3089 } 3090 if ((i == 0) && 3091 ((hw->phy_type == em_phy_m88) || 3092 (hw->phy_type == em_phy_gg82563) || 3093 (hw->phy_type == em_phy_bm))) { 3094 /* 3095 * We didn't get link. Reset the DSP and wait again 3096 * for link. 3097 */ 3098 ret_val = em_phy_reset_dsp(hw); 3099 if (ret_val) { 3100 DEBUGOUT("Error Resetting PHY DSP\n"); 3101 return ret_val; 3102 } 3103 } 3104 /* 3105 * This loop will early-out if the link condition has been 3106 * met. 3107 */ 3108 for (i = PHY_FORCE_TIME; i > 0; i--) { 3109 if (mii_status_reg & MII_SR_LINK_STATUS) 3110 break; 3111 msec_delay(100); 3112 /* 3113 * Read the MII Status Register and wait for Auto-Neg 3114 * Complete bit to be set. 3115 */ 3116 ret_val = em_read_phy_reg(hw, PHY_STATUS, 3117 &mii_status_reg); 3118 if (ret_val) 3119 return ret_val; 3120 3121 ret_val = em_read_phy_reg(hw, PHY_STATUS, 3122 &mii_status_reg); 3123 if (ret_val) 3124 return ret_val; 3125 } 3126 } 3127 if (hw->phy_type == em_phy_m88 || 3128 hw->phy_type == em_phy_bm || 3129 hw->phy_type == em_phy_oem) { 3130 /* 3131 * Because we reset the PHY above, we need to re-force TX_CLK 3132 * in the Extended PHY Specific Control Register to 25MHz 3133 * clock. This value defaults back to a 2.5MHz clock when 3134 * the PHY is reset. 3135 */ 3136 ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 3137 &phy_data); 3138 if (ret_val) 3139 return ret_val; 3140 3141 phy_data |= M88E1000_EPSCR_TX_CLK_25; 3142 ret_val = em_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 3143 phy_data); 3144 if (ret_val) 3145 return ret_val; 3146 /* 3147 * In addition, because of the s/w reset above, we need to 3148 * enable CRS on TX. This must be set for both full and half 3149 * duplex operation. 3150 */ 3151 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 3152 &phy_data); 3153 if (ret_val) 3154 return ret_val; 3155 3156 if (hw->phy_id == M88E1141_E_PHY_ID) 3157 phy_data &= ~M88E1000_PSCR_ASSERT_CRS_ON_TX; 3158 else 3159 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 3160 3161 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 3162 phy_data); 3163 if (ret_val) 3164 return ret_val; 3165 3166 if ((hw->mac_type == em_82544 || hw->mac_type == em_82543) && 3167 (!hw->autoneg) && (hw->forced_speed_duplex == em_10_full || 3168 hw->forced_speed_duplex == em_10_half)) { 3169 ret_val = em_polarity_reversal_workaround(hw); 3170 if (ret_val) 3171 return ret_val; 3172 } 3173 } else if (hw->phy_type == em_phy_gg82563) { 3174 /* 3175 * The TX_CLK of the Extended PHY Specific Control Register 3176 * defaults to 2.5MHz on a reset. We need to re-force it 3177 * back to 25MHz, if we're not in a forced 10/duplex 3178 * configuration. 3179 */ 3180 ret_val = em_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 3181 &phy_data); 3182 if (ret_val) 3183 return ret_val; 3184 3185 phy_data &= ~GG82563_MSCR_TX_CLK_MASK; 3186 if ((hw->forced_speed_duplex == em_10_full) || 3187 (hw->forced_speed_duplex == em_10_half)) 3188 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ; 3189 else 3190 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25MHZ; 3191 3192 /* Also due to the reset, we need to enable CRS on Tx. */ 3193 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 3194 3195 ret_val = em_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 3196 phy_data); 3197 if (ret_val) 3198 return ret_val; 3199 } 3200 return E1000_SUCCESS; 3201 } 3202 3203 /****************************************************************************** 3204 * Sets the collision distance in the Transmit Control register 3205 * 3206 * hw - Struct containing variables accessed by shared code 3207 * 3208 * Link should have been established previously. Reads the speed and duplex 3209 * information from the Device Status register. 3210 *****************************************************************************/ 3211 void 3212 em_config_collision_dist(struct em_hw *hw) 3213 { 3214 uint32_t tctl, coll_dist; 3215 DEBUGFUNC("em_config_collision_dist"); 3216 3217 if (hw->mac_type < em_82543) 3218 coll_dist = E1000_COLLISION_DISTANCE_82542; 3219 else 3220 coll_dist = E1000_COLLISION_DISTANCE; 3221 3222 tctl = E1000_READ_REG(hw, TCTL); 3223 3224 tctl &= ~E1000_TCTL_COLD; 3225 tctl |= coll_dist << E1000_COLD_SHIFT; 3226 3227 E1000_WRITE_REG(hw, TCTL, tctl); 3228 E1000_WRITE_FLUSH(hw); 3229 } 3230 3231 /****************************************************************************** 3232 * Sets MAC speed and duplex settings to reflect the those in the PHY 3233 * 3234 * hw - Struct containing variables accessed by shared code 3235 * mii_reg - data to write to the MII control register 3236 * 3237 * The contents of the PHY register containing the needed information need to 3238 * be passed in. 3239 *****************************************************************************/ 3240 static int32_t 3241 em_config_mac_to_phy(struct em_hw *hw) 3242 { 3243 uint32_t ctrl; 3244 int32_t ret_val; 3245 uint16_t phy_data; 3246 DEBUGFUNC("em_config_mac_to_phy"); 3247 /* 3248 * 82544 or newer MAC, Auto Speed Detection takes care of MAC 3249 * speed/duplex configuration. 3250 */ 3251 if (hw->mac_type >= em_82544 3252 && hw->mac_type != em_icp_xxxx) 3253 return E1000_SUCCESS; 3254 /* 3255 * Read the Device Control Register and set the bits to Force Speed 3256 * and Duplex. 3257 */ 3258 ctrl = E1000_READ_REG(hw, CTRL); 3259 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 3260 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); 3261 /* 3262 * Set up duplex in the Device Control and Transmit Control registers 3263 * depending on negotiated values. 3264 */ 3265 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 3266 if (ret_val) 3267 return ret_val; 3268 3269 if (phy_data & M88E1000_PSSR_DPLX) 3270 ctrl |= E1000_CTRL_FD; 3271 else 3272 ctrl &= ~E1000_CTRL_FD; 3273 3274 em_config_collision_dist(hw); 3275 /* 3276 * Set up speed in the Device Control register depending on 3277 * negotiated values. 3278 */ 3279 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) 3280 ctrl |= E1000_CTRL_SPD_1000; 3281 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) 3282 ctrl |= E1000_CTRL_SPD_100; 3283 3284 /* Write the configured values back to the Device Control Reg. */ 3285 E1000_WRITE_REG(hw, CTRL, ctrl); 3286 return E1000_SUCCESS; 3287 } 3288 3289 /****************************************************************************** 3290 * Forces the MAC's flow control settings. 3291 * 3292 * hw - Struct containing variables accessed by shared code 3293 * 3294 * Sets the TFCE and RFCE bits in the device control register to reflect 3295 * the adapter settings. TFCE and RFCE need to be explicitly set by 3296 * software when a Copper PHY is used because autonegotiation is managed 3297 * by the PHY rather than the MAC. Software must also configure these 3298 * bits when link is forced on a fiber connection. 3299 *****************************************************************************/ 3300 int32_t 3301 em_force_mac_fc(struct em_hw *hw) 3302 { 3303 uint32_t ctrl; 3304 DEBUGFUNC("em_force_mac_fc"); 3305 3306 /* Get the current configuration of the Device Control Register */ 3307 ctrl = E1000_READ_REG(hw, CTRL); 3308 /* 3309 * Because we didn't get link via the internal auto-negotiation 3310 * mechanism (we either forced link or we got link via PHY auto-neg), 3311 * we have to manually enable/disable transmit an receive flow 3312 * control. 3313 * 3314 * The "Case" statement below enables/disable flow control according to 3315 * the "hw->fc" parameter. 3316 * 3317 * The possible values of the "fc" parameter are: 0: Flow control is 3318 * completely disabled 1: Rx flow control is enabled (we can receive 3319 * pause frames but not send pause frames). 2: Tx flow control is 3320 * enabled (we can send pause frames frames but we do not receive 3321 * pause frames). 3: Both Rx and TX flow control (symmetric) is 3322 * enabled. other: No other values should be possible at this point. 3323 */ 3324 3325 switch (hw->fc) { 3326 case E1000_FC_NONE: 3327 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 3328 break; 3329 case E1000_FC_RX_PAUSE: 3330 ctrl &= (~E1000_CTRL_TFCE); 3331 ctrl |= E1000_CTRL_RFCE; 3332 break; 3333 case E1000_FC_TX_PAUSE: 3334 ctrl &= (~E1000_CTRL_RFCE); 3335 ctrl |= E1000_CTRL_TFCE; 3336 break; 3337 case E1000_FC_FULL: 3338 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 3339 break; 3340 default: 3341 DEBUGOUT("Flow control param set incorrectly\n"); 3342 return -E1000_ERR_CONFIG; 3343 } 3344 3345 /* Disable TX Flow Control for 82542 (rev 2.0) */ 3346 if (hw->mac_type == em_82542_rev2_0) 3347 ctrl &= (~E1000_CTRL_TFCE); 3348 3349 E1000_WRITE_REG(hw, CTRL, ctrl); 3350 return E1000_SUCCESS; 3351 } 3352 /****************************************************************************** 3353 * Configures flow control settings after link is established 3354 * 3355 * hw - Struct containing variables accessed by shared code 3356 * 3357 * Should be called immediately after a valid link has been established. 3358 * Forces MAC flow control settings if link was forced. When in MII/GMII mode 3359 * and autonegotiation is enabled, the MAC flow control settings will be set 3360 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE 3361 * and RFCE bits will be automaticaly set to the negotiated flow control mode. 3362 *****************************************************************************/ 3363 STATIC int32_t 3364 em_config_fc_after_link_up(struct em_hw *hw) 3365 { 3366 int32_t ret_val; 3367 uint16_t mii_status_reg; 3368 uint16_t mii_nway_adv_reg; 3369 uint16_t mii_nway_lp_ability_reg; 3370 uint16_t speed; 3371 uint16_t duplex; 3372 DEBUGFUNC("em_config_fc_after_link_up"); 3373 /* 3374 * Check for the case where we have fiber media and auto-neg failed 3375 * so we had to force link. In this case, we need to force the 3376 * configuration of the MAC to match the "fc" parameter. 3377 */ 3378 if (((hw->media_type == em_media_type_fiber) && (hw->autoneg_failed)) 3379 || ((hw->media_type == em_media_type_internal_serdes) && 3380 (hw->autoneg_failed)) || 3381 ((hw->media_type == em_media_type_copper) && (!hw->autoneg)) || 3382 ((hw->media_type == em_media_type_oem) && (!hw->autoneg))) { 3383 ret_val = em_force_mac_fc(hw); 3384 if (ret_val) { 3385 DEBUGOUT("Error forcing flow control settings\n"); 3386 return ret_val; 3387 } 3388 } 3389 /* 3390 * Check for the case where we have copper media and auto-neg is 3391 * enabled. In this case, we need to check and see if Auto-Neg has 3392 * completed, and if so, how the PHY and link partner has flow 3393 * control configured. 3394 */ 3395 if ((hw->media_type == em_media_type_copper || 3396 (hw->media_type == em_media_type_oem)) && 3397 hw->autoneg) { 3398 /* 3399 * Read the MII Status Register and check to see if AutoNeg 3400 * has completed. We read this twice because this reg has 3401 * some "sticky" (latched) bits. 3402 */ 3403 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 3404 if (ret_val) 3405 return ret_val; 3406 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 3407 if (ret_val) 3408 return ret_val; 3409 3410 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) { 3411 /* 3412 * The AutoNeg process has completed, so we now need 3413 * to read both the Auto Negotiation Advertisement 3414 * Register (Address 4) and the Auto_Negotiation Base 3415 * Page Ability Register (Address 5) to determine how 3416 * flow control was negotiated. 3417 */ 3418 ret_val = em_read_phy_reg(hw, PHY_AUTONEG_ADV, 3419 &mii_nway_adv_reg); 3420 if (ret_val) 3421 return ret_val; 3422 ret_val = em_read_phy_reg(hw, PHY_LP_ABILITY, 3423 &mii_nway_lp_ability_reg); 3424 if (ret_val) 3425 return ret_val; 3426 /* 3427 * Two bits in the Auto Negotiation Advertisement 3428 * Register (Address 4) and two bits in the Auto 3429 * Negotiation Base Page Ability Register (Address 5) 3430 * determine flow control for both the PHY and the 3431 * link partner. The following table, taken out of 3432 * the IEEE 802.3ab/D6.0 dated March 25, 1999, 3433 * describes these PAUSE resolution bits and how flow 3434 * control is determined based upon these settings. 3435 * NOTE: DC = Don't Care 3436 * 3437 * LOCAL DEVICE | LINK PARTNER | 3438 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 3439 * -------|---------|-------|---------|--------------- 3440 * 0 | 0 | DC | DC | em_fc_none 3441 * 0 | 1 | 0 | DC | em_fc_none 3442 * 0 | 1 | 1 | 0 | em_fc_none 3443 * 0 | 1 | 1 | 1 | em_fc_tx_pause 3444 * 1 | 0 | 0 | DC | em_fc_none 3445 * 1 | DC | 1 | DC | em_fc_full 3446 * 1 | 1 | 0 | 0 | em_fc_none 3447 * 1 | 1 | 0 | 1 | em_fc_rx_pause 3448 * 3449 */ 3450 /* 3451 * Are both PAUSE bits set to 1? If so, this implies 3452 * Symmetric Flow Control is enabled at both ends. 3453 * The ASM_DIR bits are irrelevant per the spec. 3454 * 3455 * For Symmetric Flow Control: 3456 * 3457 * LOCAL DEVICE | LINK PARTNER 3458 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 3459 * -------|---------|-------|---------|--------------- 3460 * 1 | DC | 1 | DC | em_fc_full 3461 * 3462 */ 3463 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 3464 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 3465 /* 3466 * Now we need to check if the user selected 3467 * RX ONLY of pause frames. In this case, we 3468 * had to advertise FULL flow control because 3469 * we could not advertise RX ONLY. Hence, we 3470 * must now check to see if we need to turn 3471 * OFF the TRANSMISSION of PAUSE frames. 3472 */ 3473 if (hw->original_fc == E1000_FC_FULL) { 3474 hw->fc = E1000_FC_FULL; 3475 DEBUGOUT("Flow Control = FULL.\n"); 3476 } else { 3477 hw->fc = E1000_FC_RX_PAUSE; 3478 DEBUGOUT("Flow Control = RX PAUSE" 3479 " frames only.\n"); 3480 } 3481 } 3482 /* 3483 * For receiving PAUSE frames ONLY. 3484 * 3485 * LOCAL DEVICE | LINK PARTNER PAUSE | ASM_DIR | 3486 * PAUSE | ASM_DIR | Result 3487 * -------|---------|-------|---------|--------------- 3488 * ----- 0 | 1 | 1 | 1 | 3489 * em_fc_tx_pause 3490 * 3491 */ 3492 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 3493 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 3494 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 3495 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 3496 hw->fc = E1000_FC_TX_PAUSE; 3497 DEBUGOUT("Flow Control = TX PAUSE frames only." 3498 "\n"); 3499 } 3500 /* 3501 * For transmitting PAUSE frames ONLY. 3502 * 3503 * LOCAL DEVICE | LINK PARTNER 3504 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 3505 * -------|---------|-------|---------|--------------- 3506 * 1 | 1 | 0 | 1 | em_fc_rx_pause 3507 * 3508 */ 3509 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 3510 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 3511 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 3512 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 3513 hw->fc = E1000_FC_RX_PAUSE; 3514 DEBUGOUT("Flow Control = RX PAUSE frames only." 3515 "\n"); 3516 } 3517 /* 3518 * Per the IEEE spec, at this point flow control 3519 * should be disabled. However, we want to consider 3520 * that we could be connected to a legacy switch that 3521 * doesn't advertise desired flow control, but can be 3522 * forced on the link partner. So if we advertised 3523 * no flow control, that is what we will resolve to. 3524 * If we advertised some kind of receive capability 3525 * (Rx Pause Only or Full Flow Control) and the link 3526 * partner advertised none, we will configure 3527 * ourselves to enable Rx Flow Control only. We can 3528 * do this safely for two reasons: If the link 3529 * partner really didn't want flow control enabled, 3530 * and we enable Rx, no harm done since we won't be 3531 * receiving any PAUSE frames anyway. If the intent 3532 * on the link partner was to have flow control 3533 * enabled, then by us enabling RX only, we can at 3534 * least receive pause frames and process them. This 3535 * is a good idea because in most cases, since we are 3536 * predominantly a server NIC, more times than not we 3537 * will be asked to delay transmission of packets 3538 * than asking our link partner to pause transmission 3539 * of frames. 3540 */ 3541 else if ((hw->original_fc == E1000_FC_NONE || 3542 hw->original_fc == E1000_FC_TX_PAUSE) || 3543 hw->fc_strict_ieee) { 3544 hw->fc = E1000_FC_NONE; 3545 DEBUGOUT("Flow Control = NONE.\n"); 3546 } else { 3547 hw->fc = E1000_FC_RX_PAUSE; 3548 DEBUGOUT("Flow Control = RX PAUSE frames only." 3549 "\n"); 3550 } 3551 /* 3552 * Now we need to do one last check... If we auto- 3553 * negotiated to HALF DUPLEX, flow control should not 3554 * be enabled per IEEE 802.3 spec. 3555 */ 3556 ret_val = em_get_speed_and_duplex(hw, &speed, &duplex); 3557 if (ret_val) { 3558 DEBUGOUT("Error getting link speed and duplex" 3559 "\n"); 3560 return ret_val; 3561 } 3562 if (duplex == HALF_DUPLEX) 3563 hw->fc = E1000_FC_NONE; 3564 /* 3565 * Now we call a subroutine to actually force the MAC 3566 * controller to use the correct flow control 3567 * settings. 3568 */ 3569 ret_val = em_force_mac_fc(hw); 3570 if (ret_val) { 3571 DEBUGOUT("Error forcing flow control settings" 3572 "\n"); 3573 return ret_val; 3574 } 3575 } else { 3576 DEBUGOUT("Copper PHY and Auto Neg has not completed." 3577 "\n"); 3578 } 3579 } 3580 return E1000_SUCCESS; 3581 } 3582 /****************************************************************************** 3583 * Checks to see if the link status of the hardware has changed. 3584 * 3585 * hw - Struct containing variables accessed by shared code 3586 * 3587 * Called by any function that needs to check the link status of the adapter. 3588 *****************************************************************************/ 3589 int32_t 3590 em_check_for_link(struct em_hw *hw) 3591 { 3592 uint32_t rxcw = 0; 3593 uint32_t ctrl; 3594 uint32_t status; 3595 uint32_t rctl; 3596 uint32_t icr; 3597 uint32_t signal = 0; 3598 int32_t ret_val; 3599 uint16_t phy_data; 3600 DEBUGFUNC("em_check_for_link"); 3601 uint16_t speed, duplex; 3602 3603 if (hw->mac_type == em_82575 && 3604 hw->media_type != em_media_type_copper) { 3605 ret_val = em_get_pcs_speed_and_duplex_82575(hw, &speed, 3606 &duplex); 3607 hw->get_link_status = hw->serdes_link_down; 3608 3609 return (ret_val); 3610 } 3611 3612 ctrl = E1000_READ_REG(hw, CTRL); 3613 status = E1000_READ_REG(hw, STATUS); 3614 /* 3615 * On adapters with a MAC newer than 82544, SW Defineable pin 1 will 3616 * be set when the optics detect a signal. On older adapters, it will 3617 * be cleared when there is a signal. This applies to fiber media 3618 * only. 3619 */ 3620 if ((hw->media_type == em_media_type_fiber) || 3621 (hw->media_type == em_media_type_internal_serdes)) { 3622 rxcw = E1000_READ_REG(hw, RXCW); 3623 3624 if (hw->media_type == em_media_type_fiber) { 3625 signal = (hw->mac_type > em_82544) ? 3626 E1000_CTRL_SWDPIN1 : 0; 3627 if (status & E1000_STATUS_LU) 3628 hw->get_link_status = FALSE; 3629 } 3630 } 3631 /* 3632 * If we have a copper PHY then we only want to go out to the PHY 3633 * registers to see if Auto-Neg has completed and/or if our link 3634 * status has changed. The get_link_status flag will be set if we 3635 * receive a Link Status Change interrupt or we have Rx Sequence 3636 * Errors. 3637 */ 3638 if ((hw->media_type == em_media_type_copper || 3639 (hw->media_type == em_media_type_oem)) && 3640 hw->get_link_status) { 3641 /* 3642 * First we want to see if the MII Status Register reports 3643 * link. If so, then we want to get the current speed/duplex 3644 * of the PHY. Read the register twice since the link bit is 3645 * sticky. 3646 */ 3647 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 3648 if (ret_val) 3649 return ret_val; 3650 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 3651 if (ret_val) 3652 return ret_val; 3653 3654 hw->icp_xxxx_is_link_up = (phy_data & MII_SR_LINK_STATUS) != 0; 3655 3656 if (hw->mac_type == em_pchlan) { 3657 ret_val = em_k1_gig_workaround_hv(hw, 3658 hw->icp_xxxx_is_link_up); 3659 if (ret_val) 3660 return ret_val; 3661 } 3662 3663 if (phy_data & MII_SR_LINK_STATUS) { 3664 hw->get_link_status = FALSE; 3665 3666 if (hw->phy_type == em_phy_82578) { 3667 ret_val = em_link_stall_workaround_hv(hw); 3668 if (ret_val) 3669 return ret_val; 3670 } 3671 3672 if (hw->mac_type == em_pch2lan) { 3673 ret_val = em_k1_workaround_lv(hw); 3674 if (ret_val) 3675 return ret_val; 3676 } 3677 3678 /* 3679 * Check if there was DownShift, must be checked 3680 * immediately after link-up 3681 */ 3682 em_check_downshift(hw); 3683 3684 /* 3685 * If we are on 82544 or 82543 silicon and 3686 * speed/duplex are forced to 10H or 10F, then we 3687 * will implement the polarity reversal workaround. 3688 * We disable interrupts first, and upon returning, 3689 * place the devices interrupt state to its previous 3690 * value except for the link status change interrupt 3691 * which will happen due to the execution of this 3692 * workaround. 3693 */ 3694 if ((hw->mac_type == em_82544 || 3695 hw->mac_type == em_82543) && (!hw->autoneg) && 3696 (hw->forced_speed_duplex == em_10_full || 3697 hw->forced_speed_duplex == em_10_half)) { 3698 E1000_WRITE_REG(hw, IMC, 0xffffffff); 3699 ret_val = em_polarity_reversal_workaround(hw); 3700 icr = E1000_READ_REG(hw, ICR); 3701 E1000_WRITE_REG(hw, ICS, 3702 (icr & ~E1000_ICS_LSC)); 3703 E1000_WRITE_REG(hw, IMS, IMS_ENABLE_MASK); 3704 } 3705 } else { 3706 /* No link detected */ 3707 em_config_dsp_after_link_change(hw, FALSE); 3708 return 0; 3709 } 3710 /* 3711 * If we are forcing speed/duplex, then we simply return 3712 * since we have already determined whether we have link or 3713 * not. 3714 */ 3715 if (!hw->autoneg) 3716 return -E1000_ERR_CONFIG; 3717 3718 /* optimize the dsp settings for the igp phy */ 3719 em_config_dsp_after_link_change(hw, TRUE); 3720 /* 3721 * We have a M88E1000 PHY and Auto-Neg is enabled. If we 3722 * have Si on board that is 82544 or newer, Auto Speed 3723 * Detection takes care of MAC speed/duplex configuration. 3724 * So we only need to configure Collision Distance in the 3725 * MAC. Otherwise, we need to force speed/duplex on the MAC 3726 * to the current PHY speed/duplex settings. 3727 */ 3728 if (hw->mac_type >= em_82544 && hw->mac_type != em_icp_xxxx) 3729 em_config_collision_dist(hw); 3730 else { 3731 ret_val = em_config_mac_to_phy(hw); 3732 if (ret_val) { 3733 DEBUGOUT("Error configuring MAC to PHY" 3734 " settings\n"); 3735 return ret_val; 3736 } 3737 } 3738 /* 3739 * Configure Flow Control now that Auto-Neg has completed. 3740 * First, we need to restore the desired flow control 3741 * settings because we may have had to re-autoneg with a 3742 * different link partner. 3743 */ 3744 ret_val = em_config_fc_after_link_up(hw); 3745 if (ret_val) { 3746 DEBUGOUT("Error configuring flow control\n"); 3747 return ret_val; 3748 } 3749 /* 3750 * At this point we know that we are on copper and we have 3751 * auto-negotiated link. These are conditions for checking 3752 * the link partner capability register. We use the link 3753 * speed to determine if TBI compatibility needs to be turned 3754 * on or off. If the link is not at gigabit speed, then TBI 3755 * compatibility is not needed. If we are at gigabit speed, 3756 * we turn on TBI compatibility. 3757 */ 3758 if (hw->tbi_compatibility_en) { 3759 uint16_t speed, duplex; 3760 ret_val = em_get_speed_and_duplex(hw, &speed, &duplex); 3761 if (ret_val) { 3762 DEBUGOUT("Error getting link speed and duplex" 3763 "\n"); 3764 return ret_val; 3765 } 3766 if (speed != SPEED_1000) { 3767 /* 3768 * If link speed is not set to gigabit speed, 3769 * we do not need to enable TBI 3770 * compatibility. 3771 */ 3772 if (hw->tbi_compatibility_on) { 3773 /* 3774 * If we previously were in the mode, 3775 * turn it off. 3776 */ 3777 rctl = E1000_READ_REG(hw, RCTL); 3778 rctl &= ~E1000_RCTL_SBP; 3779 E1000_WRITE_REG(hw, RCTL, rctl); 3780 hw->tbi_compatibility_on = FALSE; 3781 } 3782 } else { 3783 /* 3784 * If TBI compatibility is was previously 3785 * off, turn it on. For compatibility with a 3786 * TBI link partner, we will store bad 3787 * packets. Some frames have an additional 3788 * byte on the end and will look like CRC 3789 * errors to to the hardware. 3790 */ 3791 if (!hw->tbi_compatibility_on) { 3792 hw->tbi_compatibility_on = TRUE; 3793 rctl = E1000_READ_REG(hw, RCTL); 3794 rctl |= E1000_RCTL_SBP; 3795 E1000_WRITE_REG(hw, RCTL, rctl); 3796 } 3797 } 3798 } 3799 } 3800 /* 3801 * If we don't have link (auto-negotiation failed or link partner 3802 * cannot auto-negotiate), the cable is plugged in (we have signal), 3803 * and our link partner is not trying to auto-negotiate with us (we 3804 * are receiving idles or data), we need to force link up. We also 3805 * need to give auto-negotiation time to complete, in case the cable 3806 * was just plugged in. The autoneg_failed flag does this. 3807 */ 3808 else if ((((hw->media_type == em_media_type_fiber) && 3809 ((ctrl & E1000_CTRL_SWDPIN1) == signal)) || 3810 (hw->media_type == em_media_type_internal_serdes)) && 3811 (!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) { 3812 if (hw->autoneg_failed == 0) { 3813 hw->autoneg_failed = 1; 3814 return 0; 3815 } 3816 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 3817 3818 /* Disable auto-negotiation in the TXCW register */ 3819 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE)); 3820 3821 /* Force link-up and also force full-duplex. */ 3822 ctrl = E1000_READ_REG(hw, CTRL); 3823 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 3824 E1000_WRITE_REG(hw, CTRL, ctrl); 3825 3826 /* Configure Flow Control after forcing link up. */ 3827 ret_val = em_config_fc_after_link_up(hw); 3828 if (ret_val) { 3829 DEBUGOUT("Error configuring flow control\n"); 3830 return ret_val; 3831 } 3832 } 3833 /* 3834 * If we are forcing link and we are receiving /C/ ordered sets, 3835 * re-enable auto-negotiation in the TXCW register and disable forced 3836 * link in the Device Control register in an attempt to 3837 * auto-negotiate with our link partner. 3838 */ 3839 else if (((hw->media_type == em_media_type_fiber) || 3840 (hw->media_type == em_media_type_internal_serdes)) && 3841 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 3842 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 3843 E1000_WRITE_REG(hw, TXCW, hw->txcw); 3844 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU)); 3845 3846 hw->serdes_link_down = FALSE; 3847 } 3848 /* 3849 * If we force link for non-auto-negotiation switch, check link 3850 * status based on MAC synchronization for internal serdes media 3851 * type. 3852 */ 3853 else if ((hw->media_type == em_media_type_internal_serdes) && 3854 !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) { 3855 /* SYNCH bit and IV bit are sticky. */ 3856 usec_delay(10); 3857 if (E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) { 3858 if (!(rxcw & E1000_RXCW_IV)) { 3859 hw->serdes_link_down = FALSE; 3860 DEBUGOUT("SERDES: Link is up.\n"); 3861 } 3862 } else { 3863 hw->serdes_link_down = TRUE; 3864 DEBUGOUT("SERDES: Link is down.\n"); 3865 } 3866 } 3867 if ((hw->media_type == em_media_type_internal_serdes) && 3868 (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) { 3869 hw->serdes_link_down = !(E1000_STATUS_LU & 3870 E1000_READ_REG(hw, STATUS)); 3871 } 3872 return E1000_SUCCESS; 3873 } 3874 3875 int32_t 3876 em_get_pcs_speed_and_duplex_82575(struct em_hw *hw, uint16_t *speed, 3877 uint16_t *duplex) 3878 { 3879 uint32_t pcs; 3880 3881 hw->serdes_link_down = TRUE; 3882 *speed = 0; 3883 *duplex = 0; 3884 3885 /* 3886 * Read the PCS Status register for link state. For non-copper mode, 3887 * the status register is not accurate. The PCS status register is 3888 * used instead. 3889 */ 3890 pcs = E1000_READ_REG(hw, PCS_LSTAT); 3891 3892 /* 3893 * The link up bit determines when link is up on autoneg. The sync ok 3894 * gets set once both sides sync up and agree upon link. Stable link 3895 * can be determined by checking for both link up and link sync ok 3896 */ 3897 if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) { 3898 hw->serdes_link_down = FALSE; 3899 3900 /* Detect and store PCS speed */ 3901 if (pcs & E1000_PCS_LSTS_SPEED_1000) { 3902 *speed = SPEED_1000; 3903 } else if (pcs & E1000_PCS_LSTS_SPEED_100) { 3904 *speed = SPEED_100; 3905 } else { 3906 *speed = SPEED_10; 3907 } 3908 3909 /* Detect and store PCS duplex */ 3910 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) { 3911 *duplex = FULL_DUPLEX; 3912 } else { 3913 *duplex = HALF_DUPLEX; 3914 } 3915 } 3916 3917 return (0); 3918 } 3919 3920 3921 /****************************************************************************** 3922 * Detects the current speed and duplex settings of the hardware. 3923 * 3924 * hw - Struct containing variables accessed by shared code 3925 * speed - Speed of the connection 3926 * duplex - Duplex setting of the connection 3927 *****************************************************************************/ 3928 int32_t 3929 em_get_speed_and_duplex(struct em_hw *hw, uint16_t *speed, uint16_t *duplex) 3930 { 3931 uint32_t status; 3932 int32_t ret_val; 3933 uint16_t phy_data; 3934 DEBUGFUNC("em_get_speed_and_duplex"); 3935 3936 if (hw->mac_type == em_82575 && hw->media_type != em_media_type_copper) 3937 return em_get_pcs_speed_and_duplex_82575(hw, speed, duplex); 3938 3939 if (hw->mac_type >= em_82543) { 3940 status = E1000_READ_REG(hw, STATUS); 3941 if (status & E1000_STATUS_SPEED_1000) { 3942 *speed = SPEED_1000; 3943 DEBUGOUT("1000 Mbs, "); 3944 } else if (status & E1000_STATUS_SPEED_100) { 3945 *speed = SPEED_100; 3946 DEBUGOUT("100 Mbs, "); 3947 } else { 3948 *speed = SPEED_10; 3949 DEBUGOUT("10 Mbs, "); 3950 } 3951 3952 if (status & E1000_STATUS_FD) { 3953 *duplex = FULL_DUPLEX; 3954 DEBUGOUT("Full Duplex\n"); 3955 } else { 3956 *duplex = HALF_DUPLEX; 3957 DEBUGOUT(" Half Duplex\n"); 3958 } 3959 } else { 3960 DEBUGOUT("1000 Mbs, Full Duplex\n"); 3961 *speed = SPEED_1000; 3962 *duplex = FULL_DUPLEX; 3963 } 3964 /* 3965 * IGP01 PHY may advertise full duplex operation after speed 3966 * downgrade even if it is operating at half duplex. Here we set the 3967 * duplex settings to match the duplex in the link partner's 3968 * capabilities. 3969 */ 3970 if (hw->phy_type == em_phy_igp && hw->speed_downgraded) { 3971 ret_val = em_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data); 3972 if (ret_val) 3973 return ret_val; 3974 3975 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS)) 3976 *duplex = HALF_DUPLEX; 3977 else { 3978 ret_val = em_read_phy_reg(hw, PHY_LP_ABILITY, 3979 &phy_data); 3980 if (ret_val) 3981 return ret_val; 3982 if ((*speed == SPEED_100 && 3983 !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) || 3984 (*speed == SPEED_10 && 3985 !(phy_data & NWAY_LPAR_10T_FD_CAPS))) 3986 *duplex = HALF_DUPLEX; 3987 } 3988 } 3989 if ((hw->mac_type == em_80003es2lan) && 3990 (hw->media_type == em_media_type_copper)) { 3991 if (*speed == SPEED_1000) 3992 ret_val = em_configure_kmrn_for_1000(hw); 3993 else 3994 ret_val = em_configure_kmrn_for_10_100(hw, *duplex); 3995 if (ret_val) 3996 return ret_val; 3997 } 3998 if ((hw->mac_type == em_ich8lan) && 3999 (hw->phy_type == em_phy_igp_3) && 4000 (*speed == SPEED_1000)) { 4001 ret_val = em_kumeran_lock_loss_workaround(hw); 4002 if (ret_val) 4003 return ret_val; 4004 } 4005 return E1000_SUCCESS; 4006 } 4007 4008 /****************************************************************************** 4009 * Blocks until autoneg completes or times out (~4.5 seconds) 4010 * 4011 * hw - Struct containing variables accessed by shared code 4012 *****************************************************************************/ 4013 STATIC int32_t 4014 em_wait_autoneg(struct em_hw *hw) 4015 { 4016 int32_t ret_val; 4017 uint16_t i; 4018 uint16_t phy_data; 4019 DEBUGFUNC("em_wait_autoneg"); 4020 DEBUGOUT("Waiting for Auto-Neg to complete.\n"); 4021 4022 /* We will wait for autoneg to complete or 4.5 seconds to expire. */ 4023 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) { 4024 /* 4025 * Read the MII Status Register and wait for Auto-Neg 4026 * Complete bit to be set. 4027 */ 4028 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 4029 if (ret_val) 4030 return ret_val; 4031 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 4032 if (ret_val) 4033 return ret_val; 4034 if (phy_data & MII_SR_AUTONEG_COMPLETE) { 4035 return E1000_SUCCESS; 4036 } 4037 msec_delay(100); 4038 } 4039 return E1000_SUCCESS; 4040 } 4041 4042 /****************************************************************************** 4043 * Raises the Management Data Clock 4044 * 4045 * hw - Struct containing variables accessed by shared code 4046 * ctrl - Device control register's current value 4047 *****************************************************************************/ 4048 static void 4049 em_raise_mdi_clk(struct em_hw *hw, uint32_t *ctrl) 4050 { 4051 /* 4052 * Raise the clock input to the Management Data Clock (by setting the 4053 * MDC bit), and then delay 10 microseconds. 4054 */ 4055 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC)); 4056 E1000_WRITE_FLUSH(hw); 4057 usec_delay(10); 4058 } 4059 4060 /****************************************************************************** 4061 * Lowers the Management Data Clock 4062 * 4063 * hw - Struct containing variables accessed by shared code 4064 * ctrl - Device control register's current value 4065 *****************************************************************************/ 4066 static void 4067 em_lower_mdi_clk(struct em_hw *hw, uint32_t *ctrl) 4068 { 4069 /* 4070 * Lower the clock input to the Management Data Clock (by clearing 4071 * the MDC bit), and then delay 10 microseconds. 4072 */ 4073 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC)); 4074 E1000_WRITE_FLUSH(hw); 4075 usec_delay(10); 4076 } 4077 4078 /****************************************************************************** 4079 * Shifts data bits out to the PHY 4080 * 4081 * hw - Struct containing variables accessed by shared code 4082 * data - Data to send out to the PHY 4083 * count - Number of bits to shift out 4084 * 4085 * Bits are shifted out in MSB to LSB order. 4086 *****************************************************************************/ 4087 static void 4088 em_shift_out_mdi_bits(struct em_hw *hw, uint32_t data, uint16_t count) 4089 { 4090 uint32_t ctrl; 4091 uint32_t mask; 4092 /* 4093 * We need to shift "count" number of bits out to the PHY. So, the 4094 * value in the "data" parameter will be shifted out to the PHY one 4095 * bit at a time. In order to do this, "data" must be broken down 4096 * into bits. 4097 */ 4098 mask = 0x01; 4099 mask <<= (count - 1); 4100 4101 ctrl = E1000_READ_REG(hw, CTRL); 4102 4103 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output 4104 * pins. 4105 */ 4106 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); 4107 4108 while (mask) { 4109 /* 4110 * A "1" is shifted out to the PHY by setting the MDIO bit to 4111 * "1" and then raising and lowering the Management Data 4112 * Clock. A "0" is shifted out to the PHY by setting the MDIO 4113 * bit to "0" and then raising and lowering the clock. 4114 */ 4115 if (data & mask) 4116 ctrl |= E1000_CTRL_MDIO; 4117 else 4118 ctrl &= ~E1000_CTRL_MDIO; 4119 4120 E1000_WRITE_REG(hw, CTRL, ctrl); 4121 E1000_WRITE_FLUSH(hw); 4122 4123 usec_delay(10); 4124 4125 em_raise_mdi_clk(hw, &ctrl); 4126 em_lower_mdi_clk(hw, &ctrl); 4127 4128 mask = mask >> 1; 4129 } 4130 } 4131 4132 /****************************************************************************** 4133 * Shifts data bits in from the PHY 4134 * 4135 * hw - Struct containing variables accessed by shared code 4136 * 4137 * Bits are shifted in in MSB to LSB order. 4138 *****************************************************************************/ 4139 static uint16_t 4140 em_shift_in_mdi_bits(struct em_hw *hw) 4141 { 4142 uint32_t ctrl; 4143 uint16_t data = 0; 4144 uint8_t i; 4145 /* 4146 * In order to read a register from the PHY, we need to shift in a 4147 * total of 18 bits from the PHY. The first two bit (turnaround) 4148 * times are used to avoid contention on the MDIO pin when a read 4149 * operation is performed. These two bits are ignored by us and 4150 * thrown away. Bits are "shifted in" by raising the input to the 4151 * Management Data Clock (setting the MDC bit), and then reading the 4152 * value of the MDIO bit. 4153 */ 4154 ctrl = E1000_READ_REG(hw, CTRL); 4155 /* 4156 * Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as 4157 * input. 4158 */ 4159 ctrl &= ~E1000_CTRL_MDIO_DIR; 4160 ctrl &= ~E1000_CTRL_MDIO; 4161 4162 E1000_WRITE_REG(hw, CTRL, ctrl); 4163 E1000_WRITE_FLUSH(hw); 4164 /* 4165 * Raise and Lower the clock before reading in the data. This 4166 * accounts for the turnaround bits. The first clock occurred when we 4167 * clocked out the last bit of the Register Address. 4168 */ 4169 em_raise_mdi_clk(hw, &ctrl); 4170 em_lower_mdi_clk(hw, &ctrl); 4171 4172 for (data = 0, i = 0; i < 16; i++) { 4173 data = data << 1; 4174 em_raise_mdi_clk(hw, &ctrl); 4175 ctrl = E1000_READ_REG(hw, CTRL); 4176 /* Check to see if we shifted in a "1". */ 4177 if (ctrl & E1000_CTRL_MDIO) 4178 data |= 1; 4179 em_lower_mdi_clk(hw, &ctrl); 4180 } 4181 4182 em_raise_mdi_clk(hw, &ctrl); 4183 em_lower_mdi_clk(hw, &ctrl); 4184 4185 return data; 4186 } 4187 4188 STATIC int32_t 4189 em_swfw_sync_acquire(struct em_hw *hw, uint16_t mask) 4190 { 4191 uint32_t swfw_sync = 0; 4192 uint32_t swmask = mask; 4193 uint32_t fwmask = mask << 16; 4194 int32_t timeout = 200; 4195 DEBUGFUNC("em_swfw_sync_acquire"); 4196 4197 if (hw->swfwhw_semaphore_present) 4198 return em_get_software_flag(hw); 4199 4200 if (!hw->swfw_sync_present) 4201 return em_get_hw_eeprom_semaphore(hw); 4202 4203 while (timeout) { 4204 if (em_get_hw_eeprom_semaphore(hw)) 4205 return -E1000_ERR_SWFW_SYNC; 4206 4207 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); 4208 if (!(swfw_sync & (fwmask | swmask))) { 4209 break; 4210 } 4211 /* 4212 * firmware currently using resource (fwmask) 4213 * or other software thread currently using resource (swmask) 4214 */ 4215 em_put_hw_eeprom_semaphore(hw); 4216 msec_delay_irq(5); 4217 timeout--; 4218 } 4219 4220 if (!timeout) { 4221 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout." 4222 "\n"); 4223 return -E1000_ERR_SWFW_SYNC; 4224 } 4225 swfw_sync |= swmask; 4226 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync); 4227 4228 em_put_hw_eeprom_semaphore(hw); 4229 return E1000_SUCCESS; 4230 } 4231 4232 STATIC void 4233 em_swfw_sync_release(struct em_hw *hw, uint16_t mask) 4234 { 4235 uint32_t swfw_sync; 4236 uint32_t swmask = mask; 4237 DEBUGFUNC("em_swfw_sync_release"); 4238 4239 if (hw->swfwhw_semaphore_present) { 4240 em_release_software_flag(hw); 4241 return; 4242 } 4243 if (!hw->swfw_sync_present) { 4244 em_put_hw_eeprom_semaphore(hw); 4245 return; 4246 } 4247 /* 4248 * if (em_get_hw_eeprom_semaphore(hw)) return -E1000_ERR_SWFW_SYNC; 4249 */ 4250 while (em_get_hw_eeprom_semaphore(hw) != E1000_SUCCESS); 4251 /* empty */ 4252 4253 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); 4254 swfw_sync &= ~swmask; 4255 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync); 4256 4257 em_put_hw_eeprom_semaphore(hw); 4258 } 4259 4260 /**************************************************************************** 4261 * Read BM PHY wakeup register. It works as such: 4262 * 1) Set page 769, register 17, bit 2 = 1 4263 * 2) Set page to 800 for host (801 if we were manageability) 4264 * 3) Write the address using the address opcode (0x11) 4265 * 4) Read or write the data using the data opcode (0x12) 4266 * 5) Restore 769_17.2 to its original value 4267 ****************************************************************************/ 4268 int32_t 4269 em_access_phy_wakeup_reg_bm(struct em_hw *hw, uint32_t reg_addr, 4270 uint16_t *phy_data, boolean_t read) 4271 { 4272 int32_t ret_val; 4273 uint16_t reg = BM_PHY_REG_NUM(reg_addr); 4274 uint16_t phy_reg = 0; 4275 4276 /* All operations in this function are phy address 1 */ 4277 hw->phy_addr = 1; 4278 4279 /* Set page 769 */ 4280 em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 4281 (BM_WUC_ENABLE_PAGE << PHY_PAGE_SHIFT)); 4282 4283 ret_val = em_read_phy_reg_ex(hw, BM_WUC_ENABLE_REG, &phy_reg); 4284 if (ret_val) 4285 goto out; 4286 4287 /* First clear bit 4 to avoid a power state change */ 4288 phy_reg &= ~(BM_WUC_HOST_WU_BIT); 4289 ret_val = em_write_phy_reg_ex(hw, BM_WUC_ENABLE_REG, phy_reg); 4290 if (ret_val) 4291 goto out; 4292 4293 /* Write bit 2 = 1, and clear bit 4 to 769_17 */ 4294 ret_val = em_write_phy_reg_ex(hw, BM_WUC_ENABLE_REG, 4295 phy_reg | BM_WUC_ENABLE_BIT); 4296 if (ret_val) 4297 goto out; 4298 4299 /* Select page 800 */ 4300 ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 4301 (BM_WUC_PAGE << PHY_PAGE_SHIFT)); 4302 4303 /* Write the page 800 offset value using opcode 0x11 */ 4304 ret_val = em_write_phy_reg_ex(hw, BM_WUC_ADDRESS_OPCODE, reg); 4305 if (ret_val) 4306 goto out; 4307 4308 if (read) 4309 /* Read the page 800 value using opcode 0x12 */ 4310 ret_val = em_read_phy_reg_ex(hw, BM_WUC_DATA_OPCODE, 4311 phy_data); 4312 else 4313 /* Write the page 800 value using opcode 0x12 */ 4314 ret_val = em_write_phy_reg_ex(hw, BM_WUC_DATA_OPCODE, 4315 *phy_data); 4316 4317 if (ret_val) 4318 goto out; 4319 4320 /* 4321 * Restore 769_17.2 to its original value 4322 * Set page 769 4323 */ 4324 em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 4325 (BM_WUC_ENABLE_PAGE << PHY_PAGE_SHIFT)); 4326 4327 /* Clear 769_17.2 */ 4328 ret_val = em_write_phy_reg_ex(hw, BM_WUC_ENABLE_REG, phy_reg); 4329 if (ret_val) 4330 goto out; 4331 4332 out: 4333 return ret_val; 4334 } 4335 4336 /*************************************************************************** 4337 * Read HV PHY vendor specific high registers 4338 ***************************************************************************/ 4339 int32_t 4340 em_access_phy_debug_regs_hv(struct em_hw *hw, uint32_t reg_addr, 4341 uint16_t *phy_data, boolean_t read) 4342 { 4343 int32_t ret_val; 4344 uint32_t addr_reg = 0; 4345 uint32_t data_reg = 0; 4346 4347 /* This takes care of the difference with desktop vs mobile phy */ 4348 addr_reg = (hw->phy_type == em_phy_82578) ? 4349 I82578_PHY_ADDR_REG : I82577_PHY_ADDR_REG; 4350 data_reg = addr_reg + 1; 4351 4352 /* All operations in this function are phy address 2 */ 4353 hw->phy_addr = 2; 4354 4355 /* masking with 0x3F to remove the page from offset */ 4356 ret_val = em_write_phy_reg_ex(hw, addr_reg, (uint16_t)reg_addr & 0x3F); 4357 if (ret_val) { 4358 printf("Could not write PHY the HV address register\n"); 4359 goto out; 4360 } 4361 4362 /* Read or write the data value next */ 4363 if (read) 4364 ret_val = em_read_phy_reg_ex(hw, data_reg, phy_data); 4365 else 4366 ret_val = em_write_phy_reg_ex(hw, data_reg, *phy_data); 4367 4368 if (ret_val) { 4369 printf("Could not read data value from HV data register\n"); 4370 goto out; 4371 } 4372 4373 out: 4374 return ret_val; 4375 } 4376 4377 /****************************************************************************** 4378 * Reads or writes the value from a PHY register, if the value is on a specific 4379 * non zero page, sets the page first. 4380 * hw - Struct containing variables accessed by shared code 4381 * reg_addr - address of the PHY register to read 4382 *****************************************************************************/ 4383 int32_t 4384 em_access_phy_reg_hv(struct em_hw *hw, uint32_t reg_addr, uint16_t *phy_data, 4385 boolean_t read) 4386 { 4387 uint32_t ret_val; 4388 uint16_t swfw; 4389 uint16_t page = BM_PHY_REG_PAGE(reg_addr); 4390 uint16_t reg = BM_PHY_REG_NUM(reg_addr); 4391 4392 DEBUGFUNC("em_access_phy_reg_hv"); 4393 4394 swfw = E1000_SWFW_PHY0_SM; 4395 4396 if (em_swfw_sync_acquire(hw, swfw)) 4397 return -E1000_ERR_SWFW_SYNC; 4398 4399 if (page == BM_WUC_PAGE) { 4400 ret_val = em_access_phy_wakeup_reg_bm(hw, reg_addr, 4401 phy_data, read); 4402 goto release; 4403 } 4404 4405 if (page >= HV_INTC_FC_PAGE_START) 4406 hw->phy_addr = 1; 4407 else 4408 hw->phy_addr = 2; 4409 4410 if (page == HV_INTC_FC_PAGE_START) 4411 page = 0; 4412 4413 /* 4414 * Workaround MDIO accesses being disabled after entering IEEE Power 4415 * Down (whenever bit 11 of the PHY Control register is set) 4416 */ 4417 if (!read && 4418 (hw->phy_type == em_phy_82578) && 4419 (hw->phy_revision >= 1) && 4420 (hw->phy_addr == 2) && 4421 ((MAX_PHY_REG_ADDRESS & reg) == 0) && 4422 (*phy_data & (1 << 11))) { 4423 uint16_t data2 = 0x7EFF; 4424 4425 ret_val = em_access_phy_debug_regs_hv(hw, (1 << 6) | 0x3, 4426 &data2, FALSE); 4427 if (ret_val) 4428 return ret_val; 4429 } 4430 4431 if (reg_addr > MAX_PHY_MULTI_PAGE_REG) { 4432 ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 4433 (page << PHY_PAGE_SHIFT)); 4434 if (ret_val) 4435 return ret_val; 4436 } 4437 if (read) 4438 ret_val = em_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg, 4439 phy_data); 4440 else 4441 ret_val = em_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg, 4442 *phy_data); 4443 release: 4444 em_swfw_sync_release(hw, swfw); 4445 return ret_val; 4446 } 4447 4448 /****************************************************************************** 4449 * Reads the value from a PHY register, if the value is on a specific non zero 4450 * page, sets the page first. 4451 * hw - Struct containing variables accessed by shared code 4452 * reg_addr - address of the PHY register to read 4453 *****************************************************************************/ 4454 int32_t 4455 em_read_phy_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t *phy_data) 4456 { 4457 uint32_t ret_val; 4458 uint16_t swfw; 4459 DEBUGFUNC("em_read_phy_reg"); 4460 4461 if (hw->mac_type == em_pchlan || 4462 hw->mac_type == em_pch2lan) 4463 return (em_access_phy_reg_hv(hw, reg_addr, phy_data, TRUE)); 4464 4465 if (((hw->mac_type == em_80003es2lan) || (hw->mac_type == em_82575)) && 4466 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { 4467 swfw = E1000_SWFW_PHY1_SM; 4468 } else { 4469 swfw = E1000_SWFW_PHY0_SM; 4470 } 4471 if (em_swfw_sync_acquire(hw, swfw)) 4472 return -E1000_ERR_SWFW_SYNC; 4473 4474 if ((hw->phy_type == em_phy_igp || 4475 hw->phy_type == em_phy_igp_3 || 4476 hw->phy_type == em_phy_igp_2) && 4477 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { 4478 ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 4479 (uint16_t) reg_addr); 4480 if (ret_val) { 4481 em_swfw_sync_release(hw, swfw); 4482 return ret_val; 4483 } 4484 } else if (hw->phy_type == em_phy_gg82563) { 4485 if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) || 4486 (hw->mac_type == em_80003es2lan)) { 4487 /* Select Configuration Page */ 4488 if ((reg_addr & MAX_PHY_REG_ADDRESS) < 4489 GG82563_MIN_ALT_REG) { 4490 ret_val = em_write_phy_reg_ex(hw, 4491 GG82563_PHY_PAGE_SELECT, 4492 (uint16_t) ((uint16_t) reg_addr >> 4493 GG82563_PAGE_SHIFT)); 4494 } else { 4495 /* 4496 * Use Alternative Page Select register to 4497 * access registers 30 and 31 4498 */ 4499 ret_val = em_write_phy_reg_ex(hw, 4500 GG82563_PHY_PAGE_SELECT_ALT, 4501 (uint16_t) ((uint16_t) reg_addr >> 4502 GG82563_PAGE_SHIFT)); 4503 } 4504 4505 if (ret_val) { 4506 em_swfw_sync_release(hw, swfw); 4507 return ret_val; 4508 } 4509 } 4510 } else if ((hw->phy_type == em_phy_bm) && (hw->phy_revision == 1)) { 4511 if (reg_addr > MAX_PHY_MULTI_PAGE_REG) { 4512 ret_val = em_write_phy_reg_ex(hw, BM_PHY_PAGE_SELECT, 4513 (uint16_t) ((uint16_t) reg_addr >> 4514 PHY_PAGE_SHIFT)); 4515 if (ret_val) 4516 return ret_val; 4517 } 4518 } 4519 ret_val = em_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, 4520 phy_data); 4521 4522 em_swfw_sync_release(hw, swfw); 4523 return ret_val; 4524 } 4525 4526 STATIC int32_t 4527 em_read_phy_reg_ex(struct em_hw *hw, uint32_t reg_addr, uint16_t *phy_data) 4528 { 4529 uint32_t i; 4530 uint32_t mdic = 0; 4531 DEBUGFUNC("em_read_phy_reg_ex"); 4532 4533 if (reg_addr > MAX_PHY_REG_ADDRESS) { 4534 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); 4535 return -E1000_ERR_PARAM; 4536 } 4537 if (hw->mac_type == em_icp_xxxx) { 4538 *phy_data = gcu_miibus_readreg(hw, hw->icp_xxxx_port_num, 4539 reg_addr); 4540 return E1000_SUCCESS; 4541 } 4542 if (hw->mac_type > em_82543) { 4543 /* 4544 * Set up Op-code, Phy Address, and register address in the 4545 * MDI Control register. The MAC will take care of 4546 * interfacing with the PHY to retrieve the desired data. 4547 */ 4548 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) | 4549 (hw->phy_addr << E1000_MDIC_PHY_SHIFT) | 4550 (E1000_MDIC_OP_READ)); 4551 4552 E1000_WRITE_REG(hw, MDIC, mdic); 4553 4554 /* 4555 * Poll the ready bit to see if the MDI read completed 4556 * Increasing the time out as testing showed failures with 4557 * the lower time out (from FreeBSD driver) 4558 */ 4559 for (i = 0; i < 1960; i++) { 4560 usec_delay(50); 4561 mdic = E1000_READ_REG(hw, MDIC); 4562 if (mdic & E1000_MDIC_READY) 4563 break; 4564 } 4565 if (!(mdic & E1000_MDIC_READY)) { 4566 DEBUGOUT("MDI Read did not complete\n"); 4567 return -E1000_ERR_PHY; 4568 } 4569 if (mdic & E1000_MDIC_ERROR) { 4570 DEBUGOUT("MDI Error\n"); 4571 return -E1000_ERR_PHY; 4572 } 4573 *phy_data = (uint16_t) mdic; 4574 4575 if (hw->mac_type == em_pch2lan) 4576 usec_delay(100); 4577 } else { 4578 /* 4579 * We must first send a preamble through the MDIO pin to 4580 * signal the beginning of an MII instruction. This is done 4581 * by sending 32 consecutive "1" bits. 4582 */ 4583 em_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 4584 /* 4585 * Now combine the next few fields that are required for a 4586 * read operation. We use this method instead of calling the 4587 * em_shift_out_mdi_bits routine five different times. The 4588 * format of a MII read instruction consists of a shift out 4589 * of 14 bits and is defined as follows: <Preamble><SOF><Op 4590 * Code><Phy Addr><Reg Addr> followed by a shift in of 18 4591 * bits. This first two bits shifted in are TurnAround bits 4592 * used to avoid contention on the MDIO pin when a READ 4593 * operation is performed. These two bits are thrown away 4594 * followed by a shift in of 16 bits which contains the 4595 * desired data. 4596 */ 4597 mdic = ((reg_addr) | (hw->phy_addr << 5) | 4598 (PHY_OP_READ << 10) | (PHY_SOF << 12)); 4599 4600 em_shift_out_mdi_bits(hw, mdic, 14); 4601 /* 4602 * Now that we've shifted out the read command to the MII, we 4603 * need to "shift in" the 16-bit value (18 total bits) of the 4604 * requested PHY register address. 4605 */ 4606 *phy_data = em_shift_in_mdi_bits(hw); 4607 } 4608 return E1000_SUCCESS; 4609 } 4610 4611 /****************************************************************************** 4612 * Writes a value to a PHY register 4613 * 4614 * hw - Struct containing variables accessed by shared code 4615 * reg_addr - address of the PHY register to write 4616 * data - data to write to the PHY 4617 *****************************************************************************/ 4618 int32_t 4619 em_write_phy_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t phy_data) 4620 { 4621 uint32_t ret_val; 4622 DEBUGFUNC("em_write_phy_reg"); 4623 4624 if (hw->mac_type == em_pchlan || 4625 hw->mac_type == em_pch2lan) 4626 return (em_access_phy_reg_hv(hw, reg_addr, &phy_data, FALSE)); 4627 4628 if (em_swfw_sync_acquire(hw, hw->swfw)) 4629 return -E1000_ERR_SWFW_SYNC; 4630 4631 if ((hw->phy_type == em_phy_igp || 4632 hw->phy_type == em_phy_igp_3 || 4633 hw->phy_type == em_phy_igp_2) && 4634 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { 4635 ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 4636 (uint16_t) reg_addr); 4637 if (ret_val) { 4638 em_swfw_sync_release(hw, hw->swfw); 4639 return ret_val; 4640 } 4641 } else if (hw->phy_type == em_phy_gg82563) { 4642 if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) || 4643 (hw->mac_type == em_80003es2lan)) { 4644 /* Select Configuration Page */ 4645 if ((reg_addr & MAX_PHY_REG_ADDRESS) < 4646 GG82563_MIN_ALT_REG) { 4647 ret_val = em_write_phy_reg_ex(hw, 4648 GG82563_PHY_PAGE_SELECT, 4649 (uint16_t) ((uint16_t) reg_addr >> 4650 GG82563_PAGE_SHIFT)); 4651 } else { 4652 /* 4653 * Use Alternative Page Select register to 4654 * access registers 30 and 31 4655 */ 4656 ret_val = em_write_phy_reg_ex(hw, 4657 GG82563_PHY_PAGE_SELECT_ALT, 4658 (uint16_t) ((uint16_t) reg_addr >> 4659 GG82563_PAGE_SHIFT)); 4660 } 4661 4662 if (ret_val) { 4663 em_swfw_sync_release(hw, hw->swfw); 4664 return ret_val; 4665 } 4666 } 4667 } else if ((hw->phy_type == em_phy_bm) && (hw->phy_revision == 1)) { 4668 if (reg_addr > MAX_PHY_MULTI_PAGE_REG) { 4669 ret_val = em_write_phy_reg_ex(hw, BM_PHY_PAGE_SELECT, 4670 (uint16_t) ((uint16_t) reg_addr >> 4671 PHY_PAGE_SHIFT)); 4672 if (ret_val) 4673 return ret_val; 4674 } 4675 } 4676 ret_val = em_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, 4677 phy_data); 4678 4679 em_swfw_sync_release(hw, hw->swfw); 4680 return ret_val; 4681 } 4682 4683 STATIC int32_t 4684 em_write_phy_reg_ex(struct em_hw *hw, uint32_t reg_addr, uint16_t phy_data) 4685 { 4686 uint32_t i; 4687 uint32_t mdic = 0; 4688 DEBUGFUNC("em_write_phy_reg_ex"); 4689 4690 if (reg_addr > MAX_PHY_REG_ADDRESS) { 4691 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); 4692 return -E1000_ERR_PARAM; 4693 } 4694 if (hw->mac_type == em_icp_xxxx) { 4695 gcu_miibus_writereg(hw, hw->icp_xxxx_port_num, 4696 reg_addr, phy_data); 4697 return E1000_SUCCESS; 4698 } 4699 if (hw->mac_type > em_82543) { 4700 /* 4701 * Set up Op-code, Phy Address, register address, and data 4702 * intended for the PHY register in the MDI Control register. 4703 * The MAC will take care of interfacing with the PHY to send 4704 * the desired data. 4705 */ 4706 mdic = (((uint32_t) phy_data) | 4707 (reg_addr << E1000_MDIC_REG_SHIFT) | 4708 (hw->phy_addr << E1000_MDIC_PHY_SHIFT) | 4709 (E1000_MDIC_OP_WRITE)); 4710 4711 E1000_WRITE_REG(hw, MDIC, mdic); 4712 4713 /* Poll the ready bit to see if the MDI read completed */ 4714 for (i = 0; i < 641; i++) { 4715 usec_delay(5); 4716 mdic = E1000_READ_REG(hw, MDIC); 4717 if (mdic & E1000_MDIC_READY) 4718 break; 4719 } 4720 if (!(mdic & E1000_MDIC_READY)) { 4721 DEBUGOUT("MDI Write did not complete\n"); 4722 return -E1000_ERR_PHY; 4723 } 4724 4725 if (hw->mac_type == em_pch2lan) 4726 usec_delay(100); 4727 } else { 4728 /* 4729 * We'll need to use the SW defined pins to shift the write 4730 * command out to the PHY. We first send a preamble to the 4731 * PHY to signal the beginning of the MII instruction. This 4732 * is done by sending 32 consecutive "1" bits. 4733 */ 4734 em_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 4735 /* 4736 * Now combine the remaining required fields that will 4737 * indicate a write operation. We use this method instead of 4738 * calling the em_shift_out_mdi_bits routine for each field 4739 * in the command. The format of a MII write instruction is 4740 * as follows: <Preamble><SOF><Op Code><Phy Addr><Reg 4741 * Addr><Turnaround><Data>. 4742 */ 4743 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | 4744 (hw->phy_addr << 7) | (PHY_OP_WRITE << 12) | 4745 (PHY_SOF << 14)); 4746 mdic <<= 16; 4747 mdic |= (uint32_t) phy_data; 4748 4749 em_shift_out_mdi_bits(hw, mdic, 32); 4750 } 4751 4752 return E1000_SUCCESS; 4753 } 4754 4755 STATIC int32_t 4756 em_read_kmrn_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t *data) 4757 { 4758 uint32_t reg_val; 4759 DEBUGFUNC("em_read_kmrn_reg"); 4760 4761 if (em_swfw_sync_acquire(hw, hw->swfw)) 4762 return -E1000_ERR_SWFW_SYNC; 4763 4764 /* Write register address */ 4765 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) & 4766 E1000_KUMCTRLSTA_OFFSET) | 4767 E1000_KUMCTRLSTA_REN; 4768 4769 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); 4770 usec_delay(2); 4771 4772 /* Read the data returned */ 4773 reg_val = E1000_READ_REG(hw, KUMCTRLSTA); 4774 *data = (uint16_t) reg_val; 4775 4776 em_swfw_sync_release(hw, hw->swfw); 4777 return E1000_SUCCESS; 4778 } 4779 4780 STATIC int32_t 4781 em_write_kmrn_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t data) 4782 { 4783 uint32_t reg_val; 4784 DEBUGFUNC("em_write_kmrn_reg"); 4785 4786 if (em_swfw_sync_acquire(hw, hw->swfw)) 4787 return -E1000_ERR_SWFW_SYNC; 4788 4789 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) & 4790 E1000_KUMCTRLSTA_OFFSET) | data; 4791 4792 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); 4793 usec_delay(2); 4794 4795 em_swfw_sync_release(hw, hw->swfw); 4796 return E1000_SUCCESS; 4797 } 4798 4799 /****************************************************************************** 4800 * Returns the PHY to the power-on reset state 4801 * 4802 * hw - Struct containing variables accessed by shared code 4803 *****************************************************************************/ 4804 int32_t 4805 em_phy_hw_reset(struct em_hw *hw) 4806 { 4807 uint32_t ctrl, ctrl_ext; 4808 uint32_t led_ctrl; 4809 int32_t ret_val; 4810 DEBUGFUNC("em_phy_hw_reset"); 4811 /* 4812 * In the case of the phy reset being blocked, it's not an error, we 4813 * simply return success without performing the reset. 4814 */ 4815 ret_val = em_check_phy_reset_block(hw); 4816 if (ret_val) 4817 return E1000_SUCCESS; 4818 4819 DEBUGOUT("Resetting Phy...\n"); 4820 4821 if (hw->mac_type > em_82543 && hw->mac_type != em_icp_xxxx) { 4822 if (em_swfw_sync_acquire(hw, hw->swfw)) { 4823 DEBUGOUT("Unable to acquire swfw sync\n"); 4824 return -E1000_ERR_SWFW_SYNC; 4825 } 4826 /* 4827 * Read the device control register and assert the 4828 * E1000_CTRL_PHY_RST bit. Then, take it out of reset. For 4829 * pre-em_82571 hardware, we delay for 10ms between the 4830 * assert and deassert. For em_82571 hardware and later, we 4831 * instead delay for 50us between and 10ms after the 4832 * deassertion. 4833 */ 4834 ctrl = E1000_READ_REG(hw, CTRL); 4835 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST); 4836 E1000_WRITE_FLUSH(hw); 4837 4838 if (hw->mac_type < em_82571) 4839 msec_delay(10); 4840 else 4841 usec_delay(100); 4842 4843 E1000_WRITE_REG(hw, CTRL, ctrl); 4844 E1000_WRITE_FLUSH(hw); 4845 4846 if (hw->mac_type >= em_82571) 4847 msec_delay_irq(10); 4848 em_swfw_sync_release(hw, hw->swfw); 4849 /* 4850 * the M88E1141_E_PHY_ID might need reset here, but nothing 4851 * proves it 4852 */ 4853 } else { 4854 /* 4855 * Read the Extended Device Control Register, assert the 4856 * PHY_RESET_DIR bit to put the PHY into reset. Then, take it 4857 * out of reset. 4858 */ 4859 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 4860 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; 4861 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; 4862 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 4863 E1000_WRITE_FLUSH(hw); 4864 msec_delay(10); 4865 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; 4866 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 4867 E1000_WRITE_FLUSH(hw); 4868 } 4869 usec_delay(150); 4870 4871 if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) { 4872 /* Configure activity LED after PHY reset */ 4873 led_ctrl = E1000_READ_REG(hw, LEDCTL); 4874 led_ctrl &= IGP_ACTIVITY_LED_MASK; 4875 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 4876 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 4877 } 4878 /* Wait for FW to finish PHY configuration. */ 4879 ret_val = em_get_phy_cfg_done(hw); 4880 if (ret_val != E1000_SUCCESS) 4881 return ret_val; 4882 em_release_software_semaphore(hw); 4883 4884 if ((hw->mac_type == em_ich8lan) && (hw->phy_type == em_phy_igp_3)) 4885 ret_val = em_init_lcd_from_nvm(hw); 4886 4887 return ret_val; 4888 } 4889 4890 /***************************************************************************** 4891 * SW-based LCD Configuration. 4892 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are 4893 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit 4894 * in NVM determines whether HW should configure LPLU and Gbe Disable. 4895 *****************************************************************************/ 4896 int32_t 4897 em_oem_bits_config_pchlan(struct em_hw *hw, boolean_t d0_state) 4898 { 4899 int32_t ret_val = E1000_SUCCESS; 4900 uint32_t mac_reg; 4901 uint16_t oem_reg; 4902 uint16_t swfw = E1000_SWFW_PHY0_SM; 4903 4904 if (hw->mac_type != em_pchlan) 4905 return ret_val; 4906 4907 ret_val = em_swfw_sync_acquire(hw, swfw); 4908 if (ret_val) 4909 return ret_val; 4910 4911 mac_reg = E1000_READ_REG(hw, EXTCNF_CTRL); 4912 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) 4913 goto out; 4914 4915 mac_reg = E1000_READ_REG(hw, FEXTNVM); 4916 if (!(mac_reg & FEXTNVM_SW_CONFIG_ICH8M)) 4917 goto out; 4918 4919 mac_reg = E1000_READ_REG(hw, PHY_CTRL); 4920 4921 ret_val = em_read_phy_reg(hw, HV_OEM_BITS, &oem_reg); 4922 if (ret_val) 4923 goto out; 4924 4925 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU); 4926 4927 if (d0_state) { 4928 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE) 4929 oem_reg |= HV_OEM_BITS_GBE_DIS; 4930 4931 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU) 4932 oem_reg |= HV_OEM_BITS_LPLU; 4933 } else { 4934 if (mac_reg & E1000_PHY_CTRL_NOND0A_GBE_DISABLE) 4935 oem_reg |= HV_OEM_BITS_GBE_DIS; 4936 4937 if (mac_reg & E1000_PHY_CTRL_NOND0A_LPLU) 4938 oem_reg |= HV_OEM_BITS_LPLU; 4939 } 4940 /* Restart auto-neg to activate the bits */ 4941 if (!em_check_phy_reset_block(hw)) 4942 oem_reg |= HV_OEM_BITS_RESTART_AN; 4943 ret_val = em_write_phy_reg(hw, HV_OEM_BITS, oem_reg); 4944 4945 out: 4946 em_swfw_sync_release(hw, swfw); 4947 4948 return ret_val; 4949 } 4950 4951 4952 /****************************************************************************** 4953 * Resets the PHY 4954 * 4955 * hw - Struct containing variables accessed by shared code 4956 * 4957 * Sets bit 15 of the MII Control regiser 4958 *****************************************************************************/ 4959 int32_t 4960 em_phy_reset(struct em_hw *hw) 4961 { 4962 int32_t ret_val; 4963 uint16_t phy_data; 4964 DEBUGFUNC("em_phy_reset"); 4965 /* 4966 * In the case of the phy reset being blocked, it's not an error, we 4967 * simply return success without performing the reset. 4968 */ 4969 ret_val = em_check_phy_reset_block(hw); 4970 if (ret_val) 4971 return E1000_SUCCESS; 4972 4973 switch (hw->phy_type) { 4974 case em_phy_igp: 4975 case em_phy_igp_2: 4976 case em_phy_igp_3: 4977 case em_phy_ife: 4978 ret_val = em_phy_hw_reset(hw); 4979 if (ret_val) 4980 return ret_val; 4981 break; 4982 default: 4983 ret_val = em_read_phy_reg(hw, PHY_CTRL, &phy_data); 4984 if (ret_val) 4985 return ret_val; 4986 4987 phy_data |= MII_CR_RESET; 4988 ret_val = em_write_phy_reg(hw, PHY_CTRL, phy_data); 4989 if (ret_val) 4990 return ret_val; 4991 4992 usec_delay(1); 4993 break; 4994 } 4995 4996 /* Allow time for h/w to get to a quiescent state after reset */ 4997 msec_delay(10); 4998 4999 if (hw->phy_type == em_phy_igp || hw->phy_type == em_phy_igp_2) 5000 em_phy_init_script(hw); 5001 else if (hw->mac_type == em_pchlan) { 5002 ret_val = em_hv_phy_workarounds_ich8lan(hw); 5003 if (ret_val) 5004 return ret_val; 5005 5006 ret_val = em_oem_bits_config_pchlan(hw, TRUE); 5007 if (ret_val) 5008 return ret_val; 5009 } 5010 else if (hw->mac_type == em_pch2lan) { 5011 ret_val = em_set_mdio_slow_mode_hv(hw); 5012 if (ret_val) 5013 return ret_val; 5014 } 5015 5016 return E1000_SUCCESS; 5017 } 5018 5019 /****************************************************************************** 5020 * Work-around for 82566 Kumeran PCS lock loss: 5021 * On link status change (i.e. PCI reset, speed change) and link is up and 5022 * speed is gigabit- 5023 * 0) if workaround is optionally disabled do nothing 5024 * 1) wait 1ms for Kumeran link to come up 5025 * 2) check Kumeran Diagnostic register PCS lock loss bit 5026 * 3) if not set the link is locked (all is good), otherwise... 5027 * 4) reset the PHY 5028 * 5) repeat up to 10 times 5029 * Note: this is only called for IGP3 copper when speed is 1gb. 5030 * 5031 * hw - struct containing variables accessed by shared code 5032 *****************************************************************************/ 5033 STATIC int32_t 5034 em_kumeran_lock_loss_workaround(struct em_hw *hw) 5035 { 5036 int32_t ret_val; 5037 int32_t reg; 5038 int32_t cnt; 5039 uint16_t phy_data; 5040 if (hw->kmrn_lock_loss_workaround_disabled) 5041 return E1000_SUCCESS; 5042 /* 5043 * Make sure link is up before proceeding. If not just return. 5044 * Attempting this while link is negotiating fouled up link stability 5045 */ 5046 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 5047 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 5048 5049 if (phy_data & MII_SR_LINK_STATUS) { 5050 for (cnt = 0; cnt < 10; cnt++) { 5051 /* read once to clear */ 5052 ret_val = em_read_phy_reg(hw, IGP3_KMRN_DIAG, 5053 &phy_data); 5054 if (ret_val) 5055 return ret_val; 5056 /* and again to get new status */ 5057 ret_val = em_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data); 5058 if (ret_val) 5059 return ret_val; 5060 5061 /* check for PCS lock */ 5062 if (!(phy_data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) 5063 return E1000_SUCCESS; 5064 5065 /* Issue PHY reset */ 5066 em_phy_hw_reset(hw); 5067 msec_delay_irq(5); 5068 } 5069 /* Disable GigE link negotiation */ 5070 reg = E1000_READ_REG(hw, PHY_CTRL); 5071 E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE 5072 | E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 5073 5074 /* unable to acquire PCS lock */ 5075 return E1000_ERR_PHY; 5076 } 5077 return E1000_SUCCESS; 5078 } 5079 5080 /****************************************************************************** 5081 * Reads and matches the expected PHY address for known PHY IDs 5082 * 5083 * hw - Struct containing variables accessed by shared code 5084 *****************************************************************************/ 5085 STATIC int32_t 5086 em_match_gig_phy(struct em_hw *hw) 5087 { 5088 int32_t phy_init_status, ret_val; 5089 uint16_t phy_id_high, phy_id_low; 5090 boolean_t match = FALSE; 5091 DEBUGFUNC("em_match_gig_phy"); 5092 5093 ret_val = em_read_phy_reg(hw, PHY_ID1, &phy_id_high); 5094 if (ret_val) 5095 return ret_val; 5096 5097 hw->phy_id = (uint32_t) (phy_id_high << 16); 5098 usec_delay(20); 5099 ret_val = em_read_phy_reg(hw, PHY_ID2, &phy_id_low); 5100 if (ret_val) 5101 return ret_val; 5102 5103 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK); 5104 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK; 5105 5106 switch (hw->mac_type) { 5107 case em_82543: 5108 if (hw->phy_id == M88E1000_E_PHY_ID) 5109 match = TRUE; 5110 break; 5111 case em_82544: 5112 if (hw->phy_id == M88E1000_I_PHY_ID) 5113 match = TRUE; 5114 break; 5115 case em_82540: 5116 case em_82545: 5117 case em_82545_rev_3: 5118 case em_82546: 5119 case em_82546_rev_3: 5120 if (hw->phy_id == M88E1011_I_PHY_ID) 5121 match = TRUE; 5122 break; 5123 case em_82541: 5124 case em_82541_rev_2: 5125 case em_82547: 5126 case em_82547_rev_2: 5127 if (hw->phy_id == IGP01E1000_I_PHY_ID) 5128 match = TRUE; 5129 break; 5130 case em_82573: 5131 if (hw->phy_id == M88E1111_I_PHY_ID) 5132 match = TRUE; 5133 break; 5134 case em_82574: 5135 if (hw->phy_id == BME1000_E_PHY_ID) 5136 match = TRUE; 5137 break; 5138 case em_82575: 5139 if (hw->phy_id == M88E1000_E_PHY_ID) 5140 match = TRUE; 5141 if (hw->phy_id == IGP01E1000_I_PHY_ID) 5142 match = TRUE; 5143 if (hw->phy_id == IGP03E1000_E_PHY_ID) 5144 match = TRUE; 5145 break; 5146 case em_82580: 5147 case em_i350: 5148 if (hw->phy_id == I82580_I_PHY_ID || hw->phy_id == I350_I_PHY_ID) { 5149 uint32_t mdic; 5150 5151 mdic = EM_READ_REG(hw, E1000_MDICNFG); 5152 mdic &= E1000_MDICNFG_PHY_MASK; 5153 hw->phy_addr = mdic >> E1000_MDICNFG_PHY_SHIFT; 5154 DEBUGOUT1("MDICNFG PHY ADDR %d", 5155 mdic >> E1000_MDICNFG_PHY_SHIFT); 5156 match = TRUE; 5157 } 5158 break; 5159 case em_80003es2lan: 5160 if (hw->phy_id == GG82563_E_PHY_ID) 5161 match = TRUE; 5162 break; 5163 case em_ich8lan: 5164 case em_ich9lan: 5165 case em_ich10lan: 5166 case em_pchlan: 5167 case em_pch2lan: 5168 if (hw->phy_id == IGP03E1000_E_PHY_ID) 5169 match = TRUE; 5170 if (hw->phy_id == IFE_E_PHY_ID) 5171 match = TRUE; 5172 if (hw->phy_id == IFE_PLUS_E_PHY_ID) 5173 match = TRUE; 5174 if (hw->phy_id == IFE_C_E_PHY_ID) 5175 match = TRUE; 5176 if (hw->phy_id == BME1000_E_PHY_ID) 5177 match = TRUE; 5178 if (hw->phy_id == I82577_E_PHY_ID) 5179 match = TRUE; 5180 if (hw->phy_id == I82578_E_PHY_ID) 5181 match = TRUE; 5182 if (hw->phy_id == I82579_E_PHY_ID) 5183 match = TRUE; 5184 break; 5185 case em_icp_xxxx: 5186 if (hw->phy_id == M88E1141_E_PHY_ID) 5187 match = TRUE; 5188 break; 5189 default: 5190 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type); 5191 return -E1000_ERR_CONFIG; 5192 } 5193 phy_init_status = em_set_phy_type(hw); 5194 5195 if ((match) && (phy_init_status == E1000_SUCCESS)) { 5196 DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id); 5197 return E1000_SUCCESS; 5198 } 5199 DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id); 5200 return -E1000_ERR_PHY; 5201 } 5202 5203 /****************************************************************************** 5204 * Probes the expected PHY address for known PHY IDs 5205 * 5206 * hw - Struct containing variables accessed by shared code 5207 *****************************************************************************/ 5208 STATIC int32_t 5209 em_detect_gig_phy(struct em_hw *hw) 5210 { 5211 int32_t ret_val; 5212 DEBUGFUNC("em_detect_gig_phy"); 5213 5214 if (hw->phy_id != 0) 5215 return E1000_SUCCESS; 5216 5217 /* default phy address, most phys reside here, but not all (ICH10) */ 5218 if (hw->mac_type != em_icp_xxxx) 5219 hw->phy_addr = 1; 5220 else 5221 hw->phy_addr = 0; /* There is a phy at phy_addr 0 on EP80579 */ 5222 5223 /* 5224 * The 82571 firmware may still be configuring the PHY. In this 5225 * case, we cannot access the PHY until the configuration is done. 5226 * So we explicitly set the PHY values. 5227 */ 5228 if (hw->mac_type == em_82571 || 5229 hw->mac_type == em_82572) { 5230 hw->phy_id = IGP01E1000_I_PHY_ID; 5231 hw->phy_type = em_phy_igp_2; 5232 return E1000_SUCCESS; 5233 } 5234 5235 /* 5236 * Some of the fiber cards dont have a phy, so we must exit cleanly 5237 * here 5238 */ 5239 if ((hw->media_type == em_media_type_fiber) && 5240 (hw->mac_type == em_82542_rev2_0 || 5241 hw->mac_type == em_82542_rev2_1 || 5242 hw->mac_type == em_82543 || 5243 hw->mac_type == em_82574 || 5244 hw->mac_type == em_82573 || 5245 hw->mac_type == em_82574 || 5246 hw->mac_type == em_80003es2lan)) { 5247 hw->phy_type = em_phy_undefined; 5248 return E1000_SUCCESS; 5249 } 5250 5251 if ((hw->media_type == em_media_type_internal_serdes || 5252 hw->media_type == em_media_type_fiber) && 5253 hw->mac_type == em_82575) { 5254 hw->phy_type = em_phy_undefined; 5255 return E1000_SUCCESS; 5256 } 5257 5258 /* 5259 * Up to 82543 (incl), we need reset the phy, or it might not get 5260 * detected 5261 */ 5262 if (hw->mac_type <= em_82543) { 5263 ret_val = em_phy_hw_reset(hw); 5264 if (ret_val) 5265 return ret_val; 5266 } 5267 /* 5268 * ESB-2 PHY reads require em_phy_gg82563 to be set because of a 5269 * work- around that forces PHY page 0 to be set or the reads fail. 5270 * The rest of the code in this routine uses em_read_phy_reg to read 5271 * the PHY ID. So for ESB-2 we need to have this set so our reads 5272 * won't fail. If the attached PHY is not a em_phy_gg82563, the 5273 * routines below will figure this out as well. 5274 */ 5275 if (hw->mac_type == em_80003es2lan) 5276 hw->phy_type = em_phy_gg82563; 5277 5278 /* Power on SGMII phy if it is disabled */ 5279 if (hw->mac_type == em_82580 || hw->mac_type == em_i350) { 5280 uint32_t ctrl_ext = EM_READ_REG(hw, E1000_CTRL_EXT); 5281 EM_WRITE_REG(hw, E1000_CTRL_EXT, 5282 ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA); 5283 delay(300); 5284 } 5285 5286 /* Read the PHY ID Registers to identify which PHY is onboard. */ 5287 for (hw->phy_addr = 1; (hw->phy_addr < 4); hw->phy_addr++) { 5288 ret_val = em_match_gig_phy(hw); 5289 if (ret_val == E1000_SUCCESS) 5290 return E1000_SUCCESS; 5291 } 5292 return -E1000_ERR_PHY; 5293 } 5294 5295 /****************************************************************************** 5296 * Resets the PHY's DSP 5297 * 5298 * hw - Struct containing variables accessed by shared code 5299 *****************************************************************************/ 5300 static int32_t 5301 em_phy_reset_dsp(struct em_hw *hw) 5302 { 5303 int32_t ret_val; 5304 DEBUGFUNC("em_phy_reset_dsp"); 5305 5306 do { 5307 if (hw->phy_type != em_phy_gg82563) { 5308 ret_val = em_write_phy_reg(hw, 29, 0x001d); 5309 if (ret_val) 5310 break; 5311 } 5312 ret_val = em_write_phy_reg(hw, 30, 0x00c1); 5313 if (ret_val) 5314 break; 5315 ret_val = em_write_phy_reg(hw, 30, 0x0000); 5316 if (ret_val) 5317 break; 5318 ret_val = E1000_SUCCESS; 5319 } while (0); 5320 5321 return ret_val; 5322 } 5323 5324 /****************************************************************************** 5325 * Sets up eeprom variables in the hw struct. Must be called after mac_type 5326 * is configured. Additionally, if this is ICH8, the flash controller GbE 5327 * registers must be mapped, or this will crash. 5328 * 5329 * hw - Struct containing variables accessed by shared code 5330 *****************************************************************************/ 5331 int32_t 5332 em_init_eeprom_params(struct em_hw *hw) 5333 { 5334 struct em_eeprom_info *eeprom = &hw->eeprom; 5335 uint32_t eecd = E1000_READ_REG(hw, EECD); 5336 int32_t ret_val = E1000_SUCCESS; 5337 uint16_t eeprom_size; 5338 DEBUGFUNC("em_init_eeprom_params"); 5339 5340 switch (hw->mac_type) { 5341 case em_82542_rev2_0: 5342 case em_82542_rev2_1: 5343 case em_82543: 5344 case em_82544: 5345 eeprom->type = em_eeprom_microwire; 5346 eeprom->word_size = 64; 5347 eeprom->opcode_bits = 3; 5348 eeprom->address_bits = 6; 5349 eeprom->delay_usec = 50; 5350 eeprom->use_eerd = FALSE; 5351 eeprom->use_eewr = FALSE; 5352 break; 5353 case em_82540: 5354 case em_82545: 5355 case em_82545_rev_3: 5356 case em_icp_xxxx: 5357 case em_82546: 5358 case em_82546_rev_3: 5359 eeprom->type = em_eeprom_microwire; 5360 eeprom->opcode_bits = 3; 5361 eeprom->delay_usec = 50; 5362 if (eecd & E1000_EECD_SIZE) { 5363 eeprom->word_size = 256; 5364 eeprom->address_bits = 8; 5365 } else { 5366 eeprom->word_size = 64; 5367 eeprom->address_bits = 6; 5368 } 5369 eeprom->use_eerd = FALSE; 5370 eeprom->use_eewr = FALSE; 5371 break; 5372 case em_82541: 5373 case em_82541_rev_2: 5374 case em_82547: 5375 case em_82547_rev_2: 5376 if (eecd & E1000_EECD_TYPE) { 5377 eeprom->type = em_eeprom_spi; 5378 eeprom->opcode_bits = 8; 5379 eeprom->delay_usec = 1; 5380 if (eecd & E1000_EECD_ADDR_BITS) { 5381 eeprom->page_size = 32; 5382 eeprom->address_bits = 16; 5383 } else { 5384 eeprom->page_size = 8; 5385 eeprom->address_bits = 8; 5386 } 5387 } else { 5388 eeprom->type = em_eeprom_microwire; 5389 eeprom->opcode_bits = 3; 5390 eeprom->delay_usec = 50; 5391 if (eecd & E1000_EECD_ADDR_BITS) { 5392 eeprom->word_size = 256; 5393 eeprom->address_bits = 8; 5394 } else { 5395 eeprom->word_size = 64; 5396 eeprom->address_bits = 6; 5397 } 5398 } 5399 eeprom->use_eerd = FALSE; 5400 eeprom->use_eewr = FALSE; 5401 break; 5402 case em_82571: 5403 case em_82572: 5404 eeprom->type = em_eeprom_spi; 5405 eeprom->opcode_bits = 8; 5406 eeprom->delay_usec = 1; 5407 if (eecd & E1000_EECD_ADDR_BITS) { 5408 eeprom->page_size = 32; 5409 eeprom->address_bits = 16; 5410 } else { 5411 eeprom->page_size = 8; 5412 eeprom->address_bits = 8; 5413 } 5414 eeprom->use_eerd = FALSE; 5415 eeprom->use_eewr = FALSE; 5416 break; 5417 case em_82573: 5418 case em_82574: 5419 case em_82575: 5420 case em_82580: 5421 case em_i350: 5422 eeprom->type = em_eeprom_spi; 5423 eeprom->opcode_bits = 8; 5424 eeprom->delay_usec = 1; 5425 if (eecd & E1000_EECD_ADDR_BITS) { 5426 eeprom->page_size = 32; 5427 eeprom->address_bits = 16; 5428 } else { 5429 eeprom->page_size = 8; 5430 eeprom->address_bits = 8; 5431 } 5432 eeprom->use_eerd = TRUE; 5433 eeprom->use_eewr = TRUE; 5434 if (em_is_onboard_nvm_eeprom(hw) == FALSE) { 5435 eeprom->type = em_eeprom_flash; 5436 eeprom->word_size = 2048; 5437 /* 5438 * Ensure that the Autonomous FLASH update bit is 5439 * cleared due to Flash update issue on parts which 5440 * use a FLASH for NVM. 5441 */ 5442 eecd &= ~E1000_EECD_AUPDEN; 5443 E1000_WRITE_REG(hw, EECD, eecd); 5444 } 5445 break; 5446 case em_80003es2lan: 5447 eeprom->type = em_eeprom_spi; 5448 eeprom->opcode_bits = 8; 5449 eeprom->delay_usec = 1; 5450 if (eecd & E1000_EECD_ADDR_BITS) { 5451 eeprom->page_size = 32; 5452 eeprom->address_bits = 16; 5453 } else { 5454 eeprom->page_size = 8; 5455 eeprom->address_bits = 8; 5456 } 5457 eeprom->use_eerd = TRUE; 5458 eeprom->use_eewr = FALSE; 5459 break; 5460 case em_ich8lan: 5461 case em_ich9lan: 5462 case em_ich10lan: 5463 case em_pchlan: 5464 case em_pch2lan: 5465 { 5466 int32_t i = 0; 5467 uint32_t flash_size = 5468 E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_GFPREG); 5469 eeprom->type = em_eeprom_ich8; 5470 eeprom->use_eerd = FALSE; 5471 eeprom->use_eewr = FALSE; 5472 eeprom->word_size = E1000_SHADOW_RAM_WORDS; 5473 /* 5474 * Zero the shadow RAM structure. But don't load it 5475 * from NVM so as to save time for driver init 5476 */ 5477 if (hw->eeprom_shadow_ram != NULL) { 5478 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 5479 hw->eeprom_shadow_ram[i].modified = 5480 FALSE; 5481 hw->eeprom_shadow_ram[i].eeprom_word = 5482 0xFFFF; 5483 } 5484 } 5485 hw->flash_base_addr = (flash_size & 5486 ICH_GFPREG_BASE_MASK) * ICH_FLASH_SECTOR_SIZE; 5487 5488 hw->flash_bank_size = ((flash_size >> 16) & 5489 ICH_GFPREG_BASE_MASK) + 1; 5490 hw->flash_bank_size -= (flash_size & 5491 ICH_GFPREG_BASE_MASK); 5492 5493 hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE; 5494 5495 hw->flash_bank_size /= 2 * sizeof(uint16_t); 5496 5497 break; 5498 } 5499 default: 5500 break; 5501 } 5502 5503 if (eeprom->type == em_eeprom_spi) { 5504 /* 5505 * eeprom_size will be an enum [0..8] that maps to eeprom 5506 * sizes 128B to 32KB (incremented by powers of 2). 5507 */ 5508 if (hw->mac_type <= em_82547_rev_2) { 5509 /* Set to default value for initial eeprom read. */ 5510 eeprom->word_size = 64; 5511 ret_val = em_read_eeprom(hw, EEPROM_CFG, 1, 5512 &eeprom_size); 5513 if (ret_val) 5514 return ret_val; 5515 eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> 5516 EEPROM_SIZE_SHIFT; 5517 /* 5518 * 256B eeprom size was not supported in earlier 5519 * hardware, so we bump eeprom_size up one to ensure 5520 * that "1" (which maps to 256B) is never the result 5521 * used in the shifting logic below. 5522 */ 5523 if (eeprom_size) 5524 eeprom_size++; 5525 } else { 5526 eeprom_size = (uint16_t) ( 5527 (eecd & E1000_EECD_SIZE_EX_MASK) >> 5528 E1000_EECD_SIZE_EX_SHIFT); 5529 } 5530 5531 /* EEPROM access above 16k is unsupported */ 5532 if (eeprom_size + EEPROM_WORD_SIZE_SHIFT > 5533 EEPROM_WORD_SIZE_SHIFT_MAX) { 5534 eeprom->word_size = 1 << EEPROM_WORD_SIZE_SHIFT_MAX; 5535 } else { 5536 eeprom->word_size = 1 << 5537 (eeprom_size + EEPROM_WORD_SIZE_SHIFT); 5538 } 5539 } 5540 return ret_val; 5541 } 5542 5543 /****************************************************************************** 5544 * Raises the EEPROM's clock input. 5545 * 5546 * hw - Struct containing variables accessed by shared code 5547 * eecd - EECD's current value 5548 *****************************************************************************/ 5549 static void 5550 em_raise_ee_clk(struct em_hw *hw, uint32_t *eecd) 5551 { 5552 /* 5553 * Raise the clock input to the EEPROM (by setting the SK bit), and 5554 * then wait <delay> microseconds. 5555 */ 5556 *eecd = *eecd | E1000_EECD_SK; 5557 E1000_WRITE_REG(hw, EECD, *eecd); 5558 E1000_WRITE_FLUSH(hw); 5559 usec_delay(hw->eeprom.delay_usec); 5560 } 5561 5562 /****************************************************************************** 5563 * Lowers the EEPROM's clock input. 5564 * 5565 * hw - Struct containing variables accessed by shared code 5566 * eecd - EECD's current value 5567 *****************************************************************************/ 5568 static void 5569 em_lower_ee_clk(struct em_hw *hw, uint32_t *eecd) 5570 { 5571 /* 5572 * Lower the clock input to the EEPROM (by clearing the SK bit), and 5573 * then wait 50 microseconds. 5574 */ 5575 *eecd = *eecd & ~E1000_EECD_SK; 5576 E1000_WRITE_REG(hw, EECD, *eecd); 5577 E1000_WRITE_FLUSH(hw); 5578 usec_delay(hw->eeprom.delay_usec); 5579 } 5580 5581 /****************************************************************************** 5582 * Shift data bits out to the EEPROM. 5583 * 5584 * hw - Struct containing variables accessed by shared code 5585 * data - data to send to the EEPROM 5586 * count - number of bits to shift out 5587 *****************************************************************************/ 5588 static void 5589 em_shift_out_ee_bits(struct em_hw *hw, uint16_t data, uint16_t count) 5590 { 5591 struct em_eeprom_info *eeprom = &hw->eeprom; 5592 uint32_t eecd; 5593 uint32_t mask; 5594 /* 5595 * We need to shift "count" bits out to the EEPROM. So, value in the 5596 * "data" parameter will be shifted out to the EEPROM one bit at a 5597 * time. In order to do this, "data" must be broken down into bits. 5598 */ 5599 mask = 0x01 << (count - 1); 5600 eecd = E1000_READ_REG(hw, EECD); 5601 if (eeprom->type == em_eeprom_microwire) { 5602 eecd &= ~E1000_EECD_DO; 5603 } else if (eeprom->type == em_eeprom_spi) { 5604 eecd |= E1000_EECD_DO; 5605 } 5606 do { 5607 /* 5608 * A "1" is shifted out to the EEPROM by setting bit "DI" to 5609 * a "1", and then raising and then lowering the clock (the 5610 * SK bit controls the clock input to the EEPROM). A "0" is 5611 * shifted out to the EEPROM by setting "DI" to "0" and then 5612 * raising and then lowering the clock. 5613 */ 5614 eecd &= ~E1000_EECD_DI; 5615 5616 if (data & mask) 5617 eecd |= E1000_EECD_DI; 5618 5619 E1000_WRITE_REG(hw, EECD, eecd); 5620 E1000_WRITE_FLUSH(hw); 5621 5622 usec_delay(eeprom->delay_usec); 5623 5624 em_raise_ee_clk(hw, &eecd); 5625 em_lower_ee_clk(hw, &eecd); 5626 5627 mask = mask >> 1; 5628 5629 } while (mask); 5630 5631 /* We leave the "DI" bit set to "0" when we leave this routine. */ 5632 eecd &= ~E1000_EECD_DI; 5633 E1000_WRITE_REG(hw, EECD, eecd); 5634 } 5635 5636 /****************************************************************************** 5637 * Shift data bits in from the EEPROM 5638 * 5639 * hw - Struct containing variables accessed by shared code 5640 *****************************************************************************/ 5641 static uint16_t 5642 em_shift_in_ee_bits(struct em_hw *hw, uint16_t count) 5643 { 5644 uint32_t eecd; 5645 uint32_t i; 5646 uint16_t data; 5647 /* 5648 * In order to read a register from the EEPROM, we need to shift 5649 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising 5650 * the clock input to the EEPROM (setting the SK bit), and then 5651 * reading the value of the "DO" bit. During this "shifting in" 5652 * process the "DI" bit should always be clear. 5653 */ 5654 5655 eecd = E1000_READ_REG(hw, EECD); 5656 5657 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 5658 data = 0; 5659 5660 for (i = 0; i < count; i++) { 5661 data = data << 1; 5662 em_raise_ee_clk(hw, &eecd); 5663 5664 eecd = E1000_READ_REG(hw, EECD); 5665 5666 eecd &= ~(E1000_EECD_DI); 5667 if (eecd & E1000_EECD_DO) 5668 data |= 1; 5669 5670 em_lower_ee_clk(hw, &eecd); 5671 } 5672 5673 return data; 5674 } 5675 /****************************************************************************** 5676 * Prepares EEPROM for access 5677 * 5678 * hw - Struct containing variables accessed by shared code 5679 * 5680 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This 5681 * function should be called before issuing a command to the EEPROM. 5682 *****************************************************************************/ 5683 static int32_t 5684 em_acquire_eeprom(struct em_hw *hw) 5685 { 5686 struct em_eeprom_info *eeprom = &hw->eeprom; 5687 uint32_t eecd, i = 0; 5688 DEBUGFUNC("em_acquire_eeprom"); 5689 5690 if (em_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM)) 5691 return -E1000_ERR_SWFW_SYNC; 5692 eecd = E1000_READ_REG(hw, EECD); 5693 5694 if ((hw->mac_type != em_82573) && (hw->mac_type != em_82574)) { 5695 /* Request EEPROM Access */ 5696 if (hw->mac_type > em_82544) { 5697 eecd |= E1000_EECD_REQ; 5698 E1000_WRITE_REG(hw, EECD, eecd); 5699 eecd = E1000_READ_REG(hw, EECD); 5700 while ((!(eecd & E1000_EECD_GNT)) && 5701 (i < E1000_EEPROM_GRANT_ATTEMPTS)) { 5702 i++; 5703 usec_delay(5); 5704 eecd = E1000_READ_REG(hw, EECD); 5705 } 5706 if (!(eecd & E1000_EECD_GNT)) { 5707 eecd &= ~E1000_EECD_REQ; 5708 E1000_WRITE_REG(hw, EECD, eecd); 5709 DEBUGOUT("Could not acquire EEPROM grant\n"); 5710 em_swfw_sync_release(hw, E1000_SWFW_EEP_SM); 5711 return -E1000_ERR_EEPROM; 5712 } 5713 } 5714 } 5715 5716 /* Setup EEPROM for Read/Write */ 5717 if (eeprom->type == em_eeprom_microwire) { 5718 /* Clear SK and DI */ 5719 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK); 5720 E1000_WRITE_REG(hw, EECD, eecd); 5721 5722 /* Set CS */ 5723 eecd |= E1000_EECD_CS; 5724 E1000_WRITE_REG(hw, EECD, eecd); 5725 } else if (eeprom->type == em_eeprom_spi) { 5726 /* Clear SK and CS */ 5727 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 5728 E1000_WRITE_REG(hw, EECD, eecd); 5729 usec_delay(1); 5730 } 5731 return E1000_SUCCESS; 5732 } 5733 5734 /****************************************************************************** 5735 * Returns EEPROM to a "standby" state 5736 * 5737 * hw - Struct containing variables accessed by shared code 5738 *****************************************************************************/ 5739 static void 5740 em_standby_eeprom(struct em_hw *hw) 5741 { 5742 struct em_eeprom_info *eeprom = &hw->eeprom; 5743 uint32_t eecd; 5744 eecd = E1000_READ_REG(hw, EECD); 5745 5746 if (eeprom->type == em_eeprom_microwire) { 5747 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 5748 E1000_WRITE_REG(hw, EECD, eecd); 5749 E1000_WRITE_FLUSH(hw); 5750 usec_delay(eeprom->delay_usec); 5751 5752 /* Clock high */ 5753 eecd |= E1000_EECD_SK; 5754 E1000_WRITE_REG(hw, EECD, eecd); 5755 E1000_WRITE_FLUSH(hw); 5756 usec_delay(eeprom->delay_usec); 5757 5758 /* Select EEPROM */ 5759 eecd |= E1000_EECD_CS; 5760 E1000_WRITE_REG(hw, EECD, eecd); 5761 E1000_WRITE_FLUSH(hw); 5762 usec_delay(eeprom->delay_usec); 5763 5764 /* Clock low */ 5765 eecd &= ~E1000_EECD_SK; 5766 E1000_WRITE_REG(hw, EECD, eecd); 5767 E1000_WRITE_FLUSH(hw); 5768 usec_delay(eeprom->delay_usec); 5769 } else if (eeprom->type == em_eeprom_spi) { 5770 /* Toggle CS to flush commands */ 5771 eecd |= E1000_EECD_CS; 5772 E1000_WRITE_REG(hw, EECD, eecd); 5773 E1000_WRITE_FLUSH(hw); 5774 usec_delay(eeprom->delay_usec); 5775 eecd &= ~E1000_EECD_CS; 5776 E1000_WRITE_REG(hw, EECD, eecd); 5777 E1000_WRITE_FLUSH(hw); 5778 usec_delay(eeprom->delay_usec); 5779 } 5780 } 5781 5782 /****************************************************************************** 5783 * Terminates a command by inverting the EEPROM's chip select pin 5784 * 5785 * hw - Struct containing variables accessed by shared code 5786 *****************************************************************************/ 5787 static void 5788 em_release_eeprom(struct em_hw *hw) 5789 { 5790 uint32_t eecd; 5791 DEBUGFUNC("em_release_eeprom"); 5792 5793 eecd = E1000_READ_REG(hw, EECD); 5794 5795 if (hw->eeprom.type == em_eeprom_spi) { 5796 eecd |= E1000_EECD_CS; /* Pull CS high */ 5797 eecd &= ~E1000_EECD_SK; /* Lower SCK */ 5798 5799 E1000_WRITE_REG(hw, EECD, eecd); 5800 5801 usec_delay(hw->eeprom.delay_usec); 5802 } else if (hw->eeprom.type == em_eeprom_microwire) { 5803 /* cleanup eeprom */ 5804 5805 /* CS on Microwire is active-high */ 5806 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); 5807 5808 E1000_WRITE_REG(hw, EECD, eecd); 5809 5810 /* Rising edge of clock */ 5811 eecd |= E1000_EECD_SK; 5812 E1000_WRITE_REG(hw, EECD, eecd); 5813 E1000_WRITE_FLUSH(hw); 5814 usec_delay(hw->eeprom.delay_usec); 5815 5816 /* Falling edge of clock */ 5817 eecd &= ~E1000_EECD_SK; 5818 E1000_WRITE_REG(hw, EECD, eecd); 5819 E1000_WRITE_FLUSH(hw); 5820 usec_delay(hw->eeprom.delay_usec); 5821 } 5822 /* Stop requesting EEPROM access */ 5823 if (hw->mac_type > em_82544) { 5824 eecd &= ~E1000_EECD_REQ; 5825 E1000_WRITE_REG(hw, EECD, eecd); 5826 } 5827 em_swfw_sync_release(hw, E1000_SWFW_EEP_SM); 5828 } 5829 5830 /****************************************************************************** 5831 * Reads a 16 bit word from the EEPROM. 5832 * 5833 * hw - Struct containing variables accessed by shared code 5834 *****************************************************************************/ 5835 STATIC int32_t 5836 em_spi_eeprom_ready(struct em_hw *hw) 5837 { 5838 uint16_t retry_count = 0; 5839 uint8_t spi_stat_reg; 5840 DEBUGFUNC("em_spi_eeprom_ready"); 5841 /* 5842 * Read "Status Register" repeatedly until the LSB is cleared. The 5843 * EEPROM will signal that the command has been completed by clearing 5844 * bit 0 of the internal status register. If it's not cleared within 5845 * 5 milliseconds, then error out. 5846 */ 5847 retry_count = 0; 5848 do { 5849 em_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI, 5850 hw->eeprom.opcode_bits); 5851 spi_stat_reg = (uint8_t) em_shift_in_ee_bits(hw, 8); 5852 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI)) 5853 break; 5854 5855 usec_delay(5); 5856 retry_count += 5; 5857 5858 em_standby_eeprom(hw); 5859 } while (retry_count < EEPROM_MAX_RETRY_SPI); 5860 /* 5861 * ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and 5862 * only 0-5mSec on 5V devices) 5863 */ 5864 if (retry_count >= EEPROM_MAX_RETRY_SPI) { 5865 DEBUGOUT("SPI EEPROM Status error\n"); 5866 return -E1000_ERR_EEPROM; 5867 } 5868 return E1000_SUCCESS; 5869 } 5870 5871 /****************************************************************************** 5872 * Reads a 16 bit word from the EEPROM. 5873 * 5874 * hw - Struct containing variables accessed by shared code 5875 * offset - offset of word in the EEPROM to read 5876 * data - word read from the EEPROM 5877 * words - number of words to read 5878 *****************************************************************************/ 5879 int32_t 5880 em_read_eeprom(struct em_hw *hw, uint16_t offset, uint16_t words, 5881 uint16_t *data) 5882 { 5883 struct em_eeprom_info *eeprom = &hw->eeprom; 5884 uint32_t i = 0; 5885 DEBUGFUNC("em_read_eeprom"); 5886 5887 /* If eeprom is not yet detected, do so now */ 5888 if (eeprom->word_size == 0) 5889 em_init_eeprom_params(hw); 5890 /* 5891 * A check for invalid values: offset too large, too many words, and 5892 * not enough words. 5893 */ 5894 if ((offset >= eeprom->word_size) || 5895 (words > eeprom->word_size - offset) || 5896 (words == 0)) { 5897 DEBUGOUT2("\"words\" parameter out of bounds. Words = %d," 5898 " size = %d\n", offset, eeprom->word_size); 5899 return -E1000_ERR_EEPROM; 5900 } 5901 /* 5902 * EEPROM's that don't use EERD to read require us to bit-bang the 5903 * SPI directly. In this case, we need to acquire the EEPROM so that 5904 * FW or other port software does not interrupt. 5905 */ 5906 if (em_is_onboard_nvm_eeprom(hw) == TRUE && 5907 hw->eeprom.use_eerd == FALSE) { 5908 /* Prepare the EEPROM for bit-bang reading */ 5909 if (em_acquire_eeprom(hw) != E1000_SUCCESS) 5910 return -E1000_ERR_EEPROM; 5911 } 5912 /* Eerd register EEPROM access requires no eeprom aquire/release */ 5913 if (eeprom->use_eerd == TRUE) 5914 return em_read_eeprom_eerd(hw, offset, words, data); 5915 5916 /* ICH EEPROM access is done via the ICH flash controller */ 5917 if (eeprom->type == em_eeprom_ich8) 5918 return em_read_eeprom_ich8(hw, offset, words, data); 5919 /* 5920 * Set up the SPI or Microwire EEPROM for bit-bang reading. We have 5921 * acquired the EEPROM at this point, so any returns should relase it 5922 */ 5923 if (eeprom->type == em_eeprom_spi) { 5924 uint16_t word_in; 5925 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI; 5926 if (em_spi_eeprom_ready(hw)) { 5927 em_release_eeprom(hw); 5928 return -E1000_ERR_EEPROM; 5929 } 5930 em_standby_eeprom(hw); 5931 /* 5932 * Some SPI eeproms use the 8th address bit embedded in the 5933 * opcode 5934 */ 5935 if ((eeprom->address_bits == 8) && (offset >= 128)) 5936 read_opcode |= EEPROM_A8_OPCODE_SPI; 5937 5938 /* Send the READ command (opcode + addr) */ 5939 em_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits); 5940 em_shift_out_ee_bits(hw, (uint16_t) (offset * 2), 5941 eeprom->address_bits); 5942 /* 5943 * Read the data. The address of the eeprom internally 5944 * increments with each byte (spi) being read, saving on the 5945 * overhead of eeprom setup and tear-down. The address 5946 * counter will roll over if reading beyond the size of the 5947 * eeprom, thus allowing the entire memory to be read 5948 * starting from any offset. 5949 */ 5950 for (i = 0; i < words; i++) { 5951 word_in = em_shift_in_ee_bits(hw, 16); 5952 data[i] = (word_in >> 8) | (word_in << 8); 5953 } 5954 } else if (eeprom->type == em_eeprom_microwire) { 5955 for (i = 0; i < words; i++) { 5956 /* Send the READ command (opcode + addr) */ 5957 em_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE, 5958 eeprom->opcode_bits); 5959 em_shift_out_ee_bits(hw, (uint16_t) (offset + i), 5960 eeprom->address_bits); 5961 /* 5962 * Read the data. For microwire, each word requires 5963 * the overhead of eeprom setup and tear-down. 5964 */ 5965 data[i] = em_shift_in_ee_bits(hw, 16); 5966 em_standby_eeprom(hw); 5967 } 5968 } 5969 /* End this read operation */ 5970 em_release_eeprom(hw); 5971 5972 return E1000_SUCCESS; 5973 } 5974 5975 /****************************************************************************** 5976 * Reads a 16 bit word from the EEPROM using the EERD register. 5977 * 5978 * hw - Struct containing variables accessed by shared code 5979 * offset - offset of word in the EEPROM to read 5980 * data - word read from the EEPROM 5981 * words - number of words to read 5982 *****************************************************************************/ 5983 STATIC int32_t 5984 em_read_eeprom_eerd(struct em_hw *hw, uint16_t offset, uint16_t words, 5985 uint16_t *data) 5986 { 5987 uint32_t i, eerd = 0; 5988 int32_t error = 0; 5989 for (i = 0; i < words; i++) { 5990 eerd = ((offset + i) << E1000_EEPROM_RW_ADDR_SHIFT) + 5991 E1000_EEPROM_RW_REG_START; 5992 5993 E1000_WRITE_REG(hw, EERD, eerd); 5994 error = em_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ); 5995 5996 if (error) { 5997 break; 5998 } 5999 data[i] = (E1000_READ_REG(hw, EERD) >> 6000 E1000_EEPROM_RW_REG_DATA); 6001 6002 } 6003 6004 return error; 6005 } 6006 6007 /****************************************************************************** 6008 * Writes a 16 bit word from the EEPROM using the EEWR register. 6009 * 6010 * hw - Struct containing variables accessed by shared code 6011 * offset - offset of word in the EEPROM to read 6012 * data - word read from the EEPROM 6013 * words - number of words to read 6014 *****************************************************************************/ 6015 STATIC int32_t 6016 em_write_eeprom_eewr(struct em_hw *hw, uint16_t offset, uint16_t words, 6017 uint16_t *data) 6018 { 6019 uint32_t register_value = 0; 6020 uint32_t i = 0; 6021 int32_t error = 0; 6022 if (em_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM)) 6023 return -E1000_ERR_SWFW_SYNC; 6024 6025 for (i = 0; i < words; i++) { 6026 register_value = (data[i] << E1000_EEPROM_RW_REG_DATA) | 6027 ((offset + i) << E1000_EEPROM_RW_ADDR_SHIFT) | 6028 E1000_EEPROM_RW_REG_START; 6029 6030 error = em_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE); 6031 if (error) { 6032 break; 6033 } 6034 E1000_WRITE_REG(hw, EEWR, register_value); 6035 6036 error = em_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE); 6037 6038 if (error) { 6039 break; 6040 } 6041 } 6042 6043 em_swfw_sync_release(hw, E1000_SWFW_EEP_SM); 6044 return error; 6045 } 6046 6047 /****************************************************************************** 6048 * Polls the status bit (bit 1) of the EERD to determine when the read is done. 6049 * 6050 * hw - Struct containing variables accessed by shared code 6051 *****************************************************************************/ 6052 STATIC int32_t 6053 em_poll_eerd_eewr_done(struct em_hw *hw, int eerd) 6054 { 6055 uint32_t attempts = 100000; 6056 uint32_t i, reg = 0; 6057 int32_t done = E1000_ERR_EEPROM; 6058 for (i = 0; i < attempts; i++) { 6059 if (eerd == E1000_EEPROM_POLL_READ) 6060 reg = E1000_READ_REG(hw, EERD); 6061 else 6062 reg = E1000_READ_REG(hw, EEWR); 6063 6064 if (reg & E1000_EEPROM_RW_REG_DONE) { 6065 done = E1000_SUCCESS; 6066 break; 6067 } 6068 usec_delay(5); 6069 } 6070 6071 return done; 6072 } 6073 6074 /****************************************************************************** 6075 * Description: Determines if the onboard NVM is FLASH or EEPROM. 6076 * 6077 * hw - Struct containing variables accessed by shared code 6078 *****************************************************************************/ 6079 STATIC boolean_t 6080 em_is_onboard_nvm_eeprom(struct em_hw *hw) 6081 { 6082 uint32_t eecd = 0; 6083 DEBUGFUNC("em_is_onboard_nvm_eeprom"); 6084 6085 if (hw->mac_type == em_ich8lan || 6086 hw->mac_type == em_ich9lan || 6087 hw->mac_type == em_ich10lan || 6088 hw->mac_type == em_pchlan || 6089 hw->mac_type == em_pch2lan) 6090 return FALSE; 6091 6092 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) { 6093 eecd = E1000_READ_REG(hw, EECD); 6094 6095 /* Isolate bits 15 & 16 */ 6096 eecd = ((eecd >> 15) & 0x03); 6097 6098 /* If both bits are set, device is Flash type */ 6099 if (eecd == 0x03) { 6100 return FALSE; 6101 } 6102 } 6103 return TRUE; 6104 } 6105 6106 /****************************************************************************** 6107 * Verifies that the EEPROM has a valid checksum 6108 * 6109 * hw - Struct containing variables accessed by shared code 6110 * 6111 * Reads the first 64 16 bit words of the EEPROM and sums the values read. 6112 * If the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is 6113 * valid. 6114 *****************************************************************************/ 6115 int32_t 6116 em_validate_eeprom_checksum(struct em_hw *hw) 6117 { 6118 uint16_t checksum = 0; 6119 uint16_t i, eeprom_data; 6120 uint16_t checksum_reg; 6121 DEBUGFUNC("em_validate_eeprom_checksum"); 6122 6123 checksum_reg = hw->mac_type != em_icp_xxxx ? 6124 EEPROM_CHECKSUM_REG : 6125 EEPROM_CHECKSUM_REG_ICP_xxxx; 6126 6127 if (((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) && 6128 (em_is_onboard_nvm_eeprom(hw) == FALSE)) { 6129 /* 6130 * Check bit 4 of word 10h. If it is 0, firmware is done 6131 * updating 10h-12h. Checksum may need to be fixed. 6132 */ 6133 em_read_eeprom(hw, 0x10, 1, &eeprom_data); 6134 if ((eeprom_data & 0x10) == 0) { 6135 /* 6136 * Read 0x23 and check bit 15. This bit is a 1 when 6137 * the checksum has already been fixed. If the 6138 * checksum is still wrong and this bit is a 1, we 6139 * need to return bad checksum. Otherwise, we need 6140 * to set this bit to a 1 and update the checksum. 6141 */ 6142 em_read_eeprom(hw, 0x23, 1, &eeprom_data); 6143 if ((eeprom_data & 0x8000) == 0) { 6144 eeprom_data |= 0x8000; 6145 em_write_eeprom(hw, 0x23, 1, &eeprom_data); 6146 em_update_eeprom_checksum(hw); 6147 } 6148 } 6149 } 6150 if (hw->mac_type == em_ich8lan || 6151 hw->mac_type == em_ich9lan || 6152 hw->mac_type == em_ich10lan || 6153 hw->mac_type == em_pchlan || 6154 hw->mac_type == em_pch2lan) { 6155 /* 6156 * Drivers must allocate the shadow ram structure for the 6157 * EEPROM checksum to be updated. Otherwise, this bit as 6158 * well as the checksum must both be set correctly for this 6159 * validation to pass. 6160 */ 6161 em_read_eeprom(hw, 0x19, 1, &eeprom_data); 6162 if ((eeprom_data & 0x40) == 0) { 6163 eeprom_data |= 0x40; 6164 em_write_eeprom(hw, 0x19, 1, &eeprom_data); 6165 em_update_eeprom_checksum(hw); 6166 } 6167 } 6168 for (i = 0; i < (checksum_reg + 1); i++) { 6169 if (em_read_eeprom(hw, i, 1, &eeprom_data) < 0) { 6170 DEBUGOUT("EEPROM Read Error\n"); 6171 return -E1000_ERR_EEPROM; 6172 } 6173 checksum += eeprom_data; 6174 } 6175 6176 if (checksum == (uint16_t) EEPROM_SUM) 6177 return E1000_SUCCESS; 6178 else { 6179 DEBUGOUT("EEPROM Checksum Invalid\n"); 6180 return -E1000_ERR_EEPROM; 6181 } 6182 } 6183 6184 /****************************************************************************** 6185 * Calculates the EEPROM checksum and writes it to the EEPROM 6186 * 6187 * hw - Struct containing variables accessed by shared code 6188 * 6189 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA. 6190 * Writes the difference to word offset 63 of the EEPROM. 6191 *****************************************************************************/ 6192 int32_t 6193 em_update_eeprom_checksum(struct em_hw *hw) 6194 { 6195 uint32_t ctrl_ext; 6196 uint16_t checksum = 0; 6197 uint16_t i, eeprom_data; 6198 DEBUGFUNC("em_update_eeprom_checksum"); 6199 6200 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) { 6201 if (em_read_eeprom(hw, i, 1, &eeprom_data) < 0) { 6202 DEBUGOUT("EEPROM Read Error\n"); 6203 return -E1000_ERR_EEPROM; 6204 } 6205 checksum += eeprom_data; 6206 } 6207 checksum = (uint16_t) EEPROM_SUM - checksum; 6208 if (em_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) { 6209 DEBUGOUT("EEPROM Write Error\n"); 6210 return -E1000_ERR_EEPROM; 6211 } else if (hw->eeprom.type == em_eeprom_flash) { 6212 em_commit_shadow_ram(hw); 6213 } else if (hw->eeprom.type == em_eeprom_ich8) { 6214 em_commit_shadow_ram(hw); 6215 /* 6216 * Reload the EEPROM, or else modifications will not appear 6217 * until after next adapter reset. 6218 */ 6219 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 6220 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 6221 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 6222 msec_delay(10); 6223 } 6224 return E1000_SUCCESS; 6225 } 6226 6227 /****************************************************************************** 6228 * Parent function for writing words to the different EEPROM types. 6229 * 6230 * hw - Struct containing variables accessed by shared code 6231 * offset - offset within the EEPROM to be written to 6232 * words - number of words to write 6233 * data - 16 bit word to be written to the EEPROM 6234 * 6235 * If em_update_eeprom_checksum is not called after this function, the 6236 * EEPROM will most likely contain an invalid checksum. 6237 *****************************************************************************/ 6238 int32_t 6239 em_write_eeprom(struct em_hw *hw, uint16_t offset, uint16_t words, 6240 uint16_t *data) 6241 { 6242 struct em_eeprom_info *eeprom = &hw->eeprom; 6243 int32_t status = 0; 6244 DEBUGFUNC("em_write_eeprom"); 6245 6246 /* If eeprom is not yet detected, do so now */ 6247 if (eeprom->word_size == 0) 6248 em_init_eeprom_params(hw); 6249 /* 6250 * A check for invalid values: offset too large, too many words, and 6251 * not enough words. 6252 */ 6253 if ((offset >= eeprom->word_size) || 6254 (words > eeprom->word_size - offset) || 6255 (words == 0)) { 6256 DEBUGOUT("\"words\" parameter out of bounds\n"); 6257 return -E1000_ERR_EEPROM; 6258 } 6259 /* 82573/4 writes only through eewr */ 6260 if (eeprom->use_eewr == TRUE) 6261 return em_write_eeprom_eewr(hw, offset, words, data); 6262 6263 if (eeprom->type == em_eeprom_ich8) 6264 return em_write_eeprom_ich8(hw, offset, words, data); 6265 6266 /* Prepare the EEPROM for writing */ 6267 if (em_acquire_eeprom(hw) != E1000_SUCCESS) 6268 return -E1000_ERR_EEPROM; 6269 6270 if (eeprom->type == em_eeprom_microwire) { 6271 status = em_write_eeprom_microwire(hw, offset, words, data); 6272 } else { 6273 status = em_write_eeprom_spi(hw, offset, words, data); 6274 msec_delay(10); 6275 } 6276 6277 /* Done with writing */ 6278 em_release_eeprom(hw); 6279 6280 return status; 6281 } 6282 6283 /****************************************************************************** 6284 * Writes a 16 bit word to a given offset in an SPI EEPROM. 6285 * 6286 * hw - Struct containing variables accessed by shared code 6287 * offset - offset within the EEPROM to be written to 6288 * words - number of words to write 6289 * data - pointer to array of 8 bit words to be written to the EEPROM 6290 * 6291 *****************************************************************************/ 6292 STATIC int32_t 6293 em_write_eeprom_spi(struct em_hw *hw, uint16_t offset, uint16_t words, 6294 uint16_t *data) 6295 { 6296 struct em_eeprom_info *eeprom = &hw->eeprom; 6297 uint16_t widx = 0; 6298 DEBUGFUNC("em_write_eeprom_spi"); 6299 6300 while (widx < words) { 6301 uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI; 6302 if (em_spi_eeprom_ready(hw)) 6303 return -E1000_ERR_EEPROM; 6304 6305 em_standby_eeprom(hw); 6306 6307 /* Send the WRITE ENABLE command (8 bit opcode ) */ 6308 em_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI, 6309 eeprom->opcode_bits); 6310 6311 em_standby_eeprom(hw); 6312 /* 6313 * Some SPI eeproms use the 8th address bit embedded in the 6314 * opcode 6315 */ 6316 if ((eeprom->address_bits == 8) && (offset >= 128)) 6317 write_opcode |= EEPROM_A8_OPCODE_SPI; 6318 6319 /* Send the Write command (8-bit opcode + addr) */ 6320 em_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits); 6321 6322 em_shift_out_ee_bits(hw, (uint16_t) ((offset + widx) * 2), 6323 eeprom->address_bits); 6324 6325 /* Send the data */ 6326 /* 6327 * Loop to allow for up to whole page write (32 bytes) of 6328 * eeprom 6329 */ 6330 while (widx < words) { 6331 uint16_t word_out = data[widx]; 6332 word_out = (word_out >> 8) | (word_out << 8); 6333 em_shift_out_ee_bits(hw, word_out, 16); 6334 widx++; 6335 /* 6336 * Some larger eeprom sizes are capable of a 32-byte 6337 * PAGE WRITE operation, while the smaller eeproms 6338 * are capable of an 8-byte PAGE WRITE operation. 6339 * Break the inner loop to pass new address 6340 */ 6341 if ((((offset + widx) * 2) % eeprom->page_size) == 0) { 6342 em_standby_eeprom(hw); 6343 break; 6344 } 6345 } 6346 } 6347 6348 return E1000_SUCCESS; 6349 } 6350 6351 /****************************************************************************** 6352 * Writes a 16 bit word to a given offset in a Microwire EEPROM. 6353 * 6354 * hw - Struct containing variables accessed by shared code 6355 * offset - offset within the EEPROM to be written to 6356 * words - number of words to write 6357 * data - pointer to array of 16 bit words to be written to the EEPROM 6358 * 6359 *****************************************************************************/ 6360 STATIC int32_t 6361 em_write_eeprom_microwire(struct em_hw *hw, uint16_t offset, uint16_t words, 6362 uint16_t *data) 6363 { 6364 struct em_eeprom_info *eeprom = &hw->eeprom; 6365 uint32_t eecd; 6366 uint16_t words_written = 0; 6367 uint16_t i = 0; 6368 DEBUGFUNC("em_write_eeprom_microwire"); 6369 /* 6370 * Send the write enable command to the EEPROM (3-bit opcode plus 6371 * 6/8-bit dummy address beginning with 11). It's less work to 6372 * include the 11 of the dummy address as part of the opcode than it 6373 * is to shift it over the correct number of bits for the address. 6374 * This puts the EEPROM into write/erase mode. 6375 */ 6376 em_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE, 6377 (uint16_t) (eeprom->opcode_bits + 2)); 6378 6379 em_shift_out_ee_bits(hw, 0, (uint16_t) (eeprom->address_bits - 2)); 6380 6381 /* Prepare the EEPROM */ 6382 em_standby_eeprom(hw); 6383 6384 while (words_written < words) { 6385 /* Send the Write command (3-bit opcode + addr) */ 6386 em_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE, 6387 eeprom->opcode_bits); 6388 6389 em_shift_out_ee_bits(hw, (uint16_t) (offset + words_written), 6390 eeprom->address_bits); 6391 6392 /* Send the data */ 6393 em_shift_out_ee_bits(hw, data[words_written], 16); 6394 /* 6395 * Toggle the CS line. This in effect tells the EEPROM to 6396 * execute the previous command. 6397 */ 6398 em_standby_eeprom(hw); 6399 /* 6400 * Read DO repeatedly until it is high (equal to '1'). The 6401 * EEPROM will signal that the command has been completed by 6402 * raising the DO signal. If DO does not go high in 10 6403 * milliseconds, then error out. 6404 */ 6405 for (i = 0; i < 200; i++) { 6406 eecd = E1000_READ_REG(hw, EECD); 6407 if (eecd & E1000_EECD_DO) 6408 break; 6409 usec_delay(50); 6410 } 6411 if (i == 200) { 6412 DEBUGOUT("EEPROM Write did not complete\n"); 6413 return -E1000_ERR_EEPROM; 6414 } 6415 /* Recover from write */ 6416 em_standby_eeprom(hw); 6417 6418 words_written++; 6419 } 6420 /* 6421 * Send the write disable command to the EEPROM (3-bit opcode plus 6422 * 6/8-bit dummy address beginning with 10). It's less work to 6423 * include the 10 of the dummy address as part of the opcode than it 6424 * is to shift it over the correct number of bits for the address. 6425 * This takes the EEPROM out of write/erase mode. 6426 */ 6427 em_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE, 6428 (uint16_t) (eeprom->opcode_bits + 2)); 6429 6430 em_shift_out_ee_bits(hw, 0, (uint16_t) (eeprom->address_bits - 2)); 6431 6432 return E1000_SUCCESS; 6433 } 6434 6435 /****************************************************************************** 6436 * Flushes the cached eeprom to NVM. This is done by saving the modified values 6437 * in the eeprom cache and the non modified values in the currently active bank 6438 * to the new bank. 6439 * 6440 * hw - Struct containing variables accessed by shared code 6441 * offset - offset of word in the EEPROM to read 6442 * data - word read from the EEPROM 6443 * words - number of words to read 6444 *****************************************************************************/ 6445 STATIC int32_t 6446 em_commit_shadow_ram(struct em_hw *hw) 6447 { 6448 uint32_t attempts = 100000; 6449 uint32_t eecd = 0; 6450 uint32_t flop = 0; 6451 uint32_t i = 0; 6452 int32_t error = E1000_SUCCESS; 6453 uint32_t old_bank_offset = 0; 6454 uint32_t new_bank_offset = 0; 6455 uint8_t low_byte = 0; 6456 uint8_t high_byte = 0; 6457 boolean_t sector_write_failed = FALSE; 6458 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) { 6459 /* 6460 * The flop register will be used to determine if flash type 6461 * is STM 6462 */ 6463 flop = E1000_READ_REG(hw, FLOP); 6464 for (i = 0; i < attempts; i++) { 6465 eecd = E1000_READ_REG(hw, EECD); 6466 if ((eecd & E1000_EECD_FLUPD) == 0) { 6467 break; 6468 } 6469 usec_delay(5); 6470 } 6471 6472 if (i == attempts) { 6473 return -E1000_ERR_EEPROM; 6474 } 6475 /* 6476 * If STM opcode located in bits 15:8 of flop, reset firmware 6477 */ 6478 if ((flop & 0xFF00) == E1000_STM_OPCODE) { 6479 E1000_WRITE_REG(hw, HICR, E1000_HICR_FW_RESET); 6480 } 6481 /* Perform the flash update */ 6482 E1000_WRITE_REG(hw, EECD, eecd | E1000_EECD_FLUPD); 6483 6484 for (i = 0; i < attempts; i++) { 6485 eecd = E1000_READ_REG(hw, EECD); 6486 if ((eecd & E1000_EECD_FLUPD) == 0) { 6487 break; 6488 } 6489 usec_delay(5); 6490 } 6491 6492 if (i == attempts) { 6493 return -E1000_ERR_EEPROM; 6494 } 6495 } 6496 if ((hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) && 6497 hw->eeprom_shadow_ram != NULL) { 6498 /* 6499 * We're writing to the opposite bank so if we're on bank 1, 6500 * write to bank 0 etc. We also need to erase the segment 6501 * that is going to be written 6502 */ 6503 if (!(E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL)) { 6504 new_bank_offset = hw->flash_bank_size * 2; 6505 old_bank_offset = 0; 6506 em_erase_ich8_4k_segment(hw, 1); 6507 } else { 6508 old_bank_offset = hw->flash_bank_size * 2; 6509 new_bank_offset = 0; 6510 em_erase_ich8_4k_segment(hw, 0); 6511 } 6512 6513 sector_write_failed = FALSE; 6514 /* 6515 * Loop for every byte in the shadow RAM, which is in units 6516 * of words. 6517 */ 6518 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 6519 /* 6520 * Determine whether to write the value stored in the 6521 * other NVM bank or a modified value stored in the 6522 * shadow RAM 6523 */ 6524 if (hw->eeprom_shadow_ram[i].modified == TRUE) { 6525 low_byte = (uint8_t) 6526 hw->eeprom_shadow_ram[i].eeprom_word; 6527 usec_delay(100); 6528 error = em_verify_write_ich8_byte(hw, 6529 (i << 1) + new_bank_offset, low_byte); 6530 6531 if (error != E1000_SUCCESS) 6532 sector_write_failed = TRUE; 6533 else { 6534 high_byte = (uint8_t) 6535 (hw->eeprom_shadow_ram 6536 [i].eeprom_word >> 8); 6537 usec_delay(100); 6538 } 6539 } else { 6540 em_read_ich8_byte(hw, (i << 1) + 6541 old_bank_offset, &low_byte); 6542 usec_delay(100); 6543 error = em_verify_write_ich8_byte(hw, 6544 (i << 1) + new_bank_offset, low_byte); 6545 6546 if (error != E1000_SUCCESS) 6547 sector_write_failed = TRUE; 6548 else { 6549 em_read_ich8_byte(hw, (i << 1) + 6550 old_bank_offset + 1, &high_byte); 6551 usec_delay(100); 6552 } 6553 } 6554 /* 6555 * If the write of the low byte was successful, go 6556 * ahread and write the high byte while checking to 6557 * make sure that if it is the signature byte, then 6558 * it is handled properly 6559 */ 6560 if (sector_write_failed == FALSE) { 6561 /* 6562 * If the word is 0x13, then make sure the 6563 * signature bits (15:14) are 11b until the 6564 * commit has completed. This will allow us 6565 * to write 10b which indicates the signature 6566 * is valid. We want to do this after the 6567 * write has completed so that we don't mark 6568 * the segment valid while the write is still 6569 * in progress 6570 */ 6571 if (i == E1000_ICH_NVM_SIG_WORD) 6572 high_byte = E1000_ICH_NVM_SIG_MASK | 6573 high_byte; 6574 6575 error = em_verify_write_ich8_byte(hw, (i << 1) 6576 + new_bank_offset + 1, high_byte); 6577 if (error != E1000_SUCCESS) 6578 sector_write_failed = TRUE; 6579 6580 } else { 6581 /* 6582 * If the write failed then break from the 6583 * loop and return an error 6584 */ 6585 break; 6586 } 6587 } 6588 /* 6589 * Don't bother writing the segment valid bits if sector 6590 * programming failed. 6591 */ 6592 if (sector_write_failed == FALSE) { 6593 /* 6594 * Finally validate the new segment by setting bit 6595 * 15:14 to 10b in word 0x13 , this can be done 6596 * without an erase as well since these bits are 11 6597 * to start with and we need to change bit 14 to 0b 6598 */ 6599 em_read_ich8_byte(hw, E1000_ICH_NVM_SIG_WORD * 2 + 1 + 6600 new_bank_offset, &high_byte); 6601 high_byte &= 0xBF; 6602 error = em_verify_write_ich8_byte(hw, 6603 E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset, 6604 high_byte); 6605 /* 6606 * And invalidate the previously valid segment by 6607 * setting its signature word (0x13) high_byte to 0b. 6608 * This can be done without an erase because flash 6609 * erase sets all bits to 1's. We can write 1's to 6610 * 0's without an erase 6611 */ 6612 if (error == E1000_SUCCESS) { 6613 error = em_verify_write_ich8_byte(hw, 6614 E1000_ICH_NVM_SIG_WORD * 2 + 1 + 6615 old_bank_offset, 0); 6616 } 6617 /* Clear the now not used entry in the cache */ 6618 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 6619 hw->eeprom_shadow_ram[i].modified = FALSE; 6620 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF; 6621 } 6622 } 6623 } 6624 return error; 6625 } 6626 6627 /****************************************************************************** 6628 * Reads the adapter's part number from the EEPROM 6629 * 6630 * hw - Struct containing variables accessed by shared code 6631 * part_num - Adapter's part number 6632 *****************************************************************************/ 6633 int32_t 6634 em_read_part_num(struct em_hw *hw, uint32_t *part_num) 6635 { 6636 uint16_t offset = EEPROM_PBA_BYTE_1; 6637 uint16_t eeprom_data; 6638 DEBUGFUNC("em_read_part_num"); 6639 6640 /* Get word 0 from EEPROM */ 6641 if (em_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { 6642 DEBUGOUT("EEPROM Read Error\n"); 6643 return -E1000_ERR_EEPROM; 6644 } 6645 /* Save word 0 in upper half of part_num */ 6646 *part_num = (uint32_t) (eeprom_data << 16); 6647 6648 /* Get word 1 from EEPROM */ 6649 if (em_read_eeprom(hw, ++offset, 1, &eeprom_data) < 0) { 6650 DEBUGOUT("EEPROM Read Error\n"); 6651 return -E1000_ERR_EEPROM; 6652 } 6653 /* Save word 1 in lower half of part_num */ 6654 *part_num |= eeprom_data; 6655 6656 return E1000_SUCCESS; 6657 } 6658 6659 /****************************************************************************** 6660 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the 6661 * second function of dual function devices 6662 * 6663 * hw - Struct containing variables accessed by shared code 6664 *****************************************************************************/ 6665 int32_t 6666 em_read_mac_addr(struct em_hw *hw) 6667 { 6668 uint16_t offset; 6669 uint16_t eeprom_data, i; 6670 uint16_t ia_base_addr = 0; 6671 DEBUGFUNC("em_read_mac_addr"); 6672 6673 if (hw->mac_type == em_icp_xxxx) { 6674 ia_base_addr = (uint16_t) 6675 EEPROM_IA_START_ICP_xxxx(hw->icp_xxxx_port_num); 6676 } else if (hw->mac_type == em_82580 || hw->mac_type == em_i350) { 6677 ia_base_addr = NVM_82580_LAN_FUNC_OFFSET(hw->bus_func); 6678 } 6679 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) { 6680 offset = i >> 1; 6681 if (em_read_eeprom(hw, offset + ia_base_addr, 1, &eeprom_data) 6682 < 0) { 6683 DEBUGOUT("EEPROM Read Error\n"); 6684 return -E1000_ERR_EEPROM; 6685 } 6686 hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF); 6687 hw->perm_mac_addr[i + 1] = (uint8_t) (eeprom_data >> 8); 6688 } 6689 6690 switch (hw->mac_type) { 6691 default: 6692 break; 6693 case em_82546: 6694 case em_82546_rev_3: 6695 case em_82571: 6696 case em_82575: 6697 case em_80003es2lan: 6698 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) 6699 hw->perm_mac_addr[5] ^= 0x01; 6700 break; 6701 } 6702 6703 for (i = 0; i < NODE_ADDRESS_SIZE; i++) 6704 hw->mac_addr[i] = hw->perm_mac_addr[i]; 6705 return E1000_SUCCESS; 6706 } 6707 6708 /****************************************************************************** 6709 * Initializes receive address filters. 6710 * 6711 * hw - Struct containing variables accessed by shared code 6712 * 6713 * Places the MAC address in receive address register 0 and clears the rest 6714 * of the receive addresss registers. Clears the multicast table. Assumes 6715 * the receiver is in reset when the routine is called. 6716 *****************************************************************************/ 6717 STATIC void 6718 em_init_rx_addrs(struct em_hw *hw) 6719 { 6720 uint32_t i; 6721 uint32_t rar_num; 6722 DEBUGFUNC("em_init_rx_addrs"); 6723 6724 /* Setup the receive address. */ 6725 DEBUGOUT("Programming MAC Address into RAR[0]\n"); 6726 6727 em_rar_set(hw, hw->mac_addr, 0); 6728 6729 rar_num = E1000_RAR_ENTRIES; 6730 /* 6731 * Reserve a spot for the Locally Administered Address to work around 6732 * an 82571 issue in which a reset on one port will reload the MAC on 6733 * the other port. 6734 */ 6735 if ((hw->mac_type == em_82571) && (hw->laa_is_present == TRUE)) 6736 rar_num -= 1; 6737 if (hw->mac_type == em_ich8lan || 6738 hw->mac_type == em_ich9lan || 6739 hw->mac_type == em_ich10lan || 6740 hw->mac_type == em_pchlan || 6741 hw->mac_type == em_pch2lan) 6742 rar_num = E1000_RAR_ENTRIES_ICH8LAN; 6743 if (hw->mac_type == em_ich8lan) 6744 rar_num -= 1; 6745 if (hw->mac_type == em_82580) 6746 rar_num = E1000_RAR_ENTRIES_82580; 6747 if (hw->mac_type == em_i350) 6748 rar_num = E1000_RAR_ENTRIES_I350; 6749 6750 /* Zero out the other 15 receive addresses. */ 6751 DEBUGOUT("Clearing RAR[1-15]\n"); 6752 for (i = 1; i < rar_num; i++) { 6753 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 6754 E1000_WRITE_FLUSH(hw); 6755 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 6756 E1000_WRITE_FLUSH(hw); 6757 } 6758 } 6759 6760 /****************************************************************************** 6761 * Updates the MAC's list of multicast addresses. 6762 * 6763 * hw - Struct containing variables accessed by shared code 6764 * mc_addr_list - the list of new multicast addresses 6765 * mc_addr_count - number of addresses 6766 * pad - number of bytes between addresses in the list 6767 * rar_used_count - offset where to start adding mc addresses into the RAR's 6768 * 6769 * The given list replaces any existing list. Clears the last 15 receive 6770 * address registers and the multicast table. Uses receive address registers 6771 * for the first 15 multicast addresses, and hashes the rest into the 6772 * multicast table. 6773 *****************************************************************************/ 6774 void 6775 em_mc_addr_list_update(struct em_hw *hw, uint8_t *mc_addr_list, 6776 uint32_t mc_addr_count, uint32_t pad, uint32_t rar_used_count) 6777 { 6778 uint32_t hash_value; 6779 uint32_t i; 6780 uint32_t num_rar_entry; 6781 uint32_t num_mta_entry; 6782 DEBUGFUNC("em_mc_addr_list_update"); 6783 /* 6784 * Set the new number of MC addresses that we are being requested to 6785 * use. 6786 */ 6787 hw->num_mc_addrs = mc_addr_count; 6788 6789 /* Clear RAR[1-15] */ 6790 DEBUGOUT(" Clearing RAR[1-15]\n"); 6791 num_rar_entry = E1000_RAR_ENTRIES; 6792 if (hw->mac_type == em_ich8lan || 6793 hw->mac_type == em_ich9lan || 6794 hw->mac_type == em_ich10lan || 6795 hw->mac_type == em_pchlan || 6796 hw->mac_type == em_pch2lan) 6797 num_rar_entry = E1000_RAR_ENTRIES_ICH8LAN; 6798 if (hw->mac_type == em_ich8lan) 6799 num_rar_entry -= 1; 6800 /* 6801 * Reserve a spot for the Locally Administered Address to work around 6802 * an 82571 issue in which a reset on one port will reload the MAC on 6803 * the other port. 6804 */ 6805 if ((hw->mac_type == em_82571) && (hw->laa_is_present == TRUE)) 6806 num_rar_entry -= 1; 6807 6808 for (i = rar_used_count; i < num_rar_entry; i++) { 6809 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 6810 E1000_WRITE_FLUSH(hw); 6811 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 6812 E1000_WRITE_FLUSH(hw); 6813 } 6814 6815 /* Clear the MTA */ 6816 DEBUGOUT(" Clearing MTA\n"); 6817 num_mta_entry = E1000_NUM_MTA_REGISTERS; 6818 if (hw->mac_type == em_ich8lan || 6819 hw->mac_type == em_ich9lan || 6820 hw->mac_type == em_ich10lan || 6821 hw->mac_type == em_pchlan || 6822 hw->mac_type == em_pch2lan) 6823 num_mta_entry = E1000_NUM_MTA_REGISTERS_ICH8LAN; 6824 6825 for (i = 0; i < num_mta_entry; i++) { 6826 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 6827 E1000_WRITE_FLUSH(hw); 6828 } 6829 6830 /* Add the new addresses */ 6831 for (i = 0; i < mc_addr_count; i++) { 6832 DEBUGOUT(" Adding the multicast addresses:\n"); 6833 DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i, 6834 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad)], 6835 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 1], 6836 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 2], 6837 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 3], 6838 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 4], 6839 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 5]); 6840 6841 hash_value = em_hash_mc_addr(hw, mc_addr_list + 6842 (i * (ETH_LENGTH_OF_ADDRESS + pad))); 6843 6844 DEBUGOUT1(" Hash value = 0x%03X\n", hash_value); 6845 /* 6846 * Place this multicast address in the RAR if there is room, * 6847 * else put it in the MTA 6848 */ 6849 if (rar_used_count < num_rar_entry) { 6850 em_rar_set(hw, mc_addr_list + 6851 (i * (ETH_LENGTH_OF_ADDRESS + pad)), 6852 rar_used_count); 6853 rar_used_count++; 6854 } else { 6855 em_mta_set(hw, hash_value); 6856 } 6857 } 6858 DEBUGOUT("MC Update Complete\n"); 6859 } 6860 6861 /****************************************************************************** 6862 * Hashes an address to determine its location in the multicast table 6863 * 6864 * hw - Struct containing variables accessed by shared code 6865 * mc_addr - the multicast address to hash 6866 *****************************************************************************/ 6867 uint32_t 6868 em_hash_mc_addr(struct em_hw *hw, uint8_t *mc_addr) 6869 { 6870 uint32_t hash_value = 0; 6871 /* 6872 * The portion of the address that is used for the hash table is 6873 * determined by the mc_filter_type setting. 6874 */ 6875 switch (hw->mc_filter_type) { 6876 /* 6877 * [0] [1] [2] [3] [4] [5] 01 AA 00 12 34 56 LSB 6878 * MSB 6879 */ 6880 case 0: 6881 if (hw->mac_type == em_ich8lan || 6882 hw->mac_type == em_ich9lan || 6883 hw->mac_type == em_ich10lan || 6884 hw->mac_type == em_pchlan || 6885 hw->mac_type == em_pch2lan) { 6886 /* [47:38] i.e. 0x158 for above example address */ 6887 hash_value = ((mc_addr[4] >> 6) | 6888 (((uint16_t) mc_addr[5]) << 2)); 6889 } else { 6890 /* [47:36] i.e. 0x563 for above example address */ 6891 hash_value = ((mc_addr[4] >> 4) | 6892 (((uint16_t) mc_addr[5]) << 4)); 6893 } 6894 break; 6895 case 1: 6896 if (hw->mac_type == em_ich8lan || 6897 hw->mac_type == em_ich9lan || 6898 hw->mac_type == em_ich10lan || 6899 hw->mac_type == em_pchlan || 6900 hw->mac_type == em_pch2lan) { 6901 /* [46:37] i.e. 0x2B1 for above example address */ 6902 hash_value = ((mc_addr[4] >> 5) | 6903 (((uint16_t) mc_addr[5]) << 3)); 6904 } else { 6905 /* [46:35] i.e. 0xAC6 for above example address */ 6906 hash_value = ((mc_addr[4] >> 3) | 6907 (((uint16_t) mc_addr[5]) << 5)); 6908 } 6909 break; 6910 case 2: 6911 if (hw->mac_type == em_ich8lan || 6912 hw->mac_type == em_ich9lan || 6913 hw->mac_type == em_ich10lan || 6914 hw->mac_type == em_pchlan || 6915 hw->mac_type == em_pch2lan) { 6916 /* [45:36] i.e. 0x163 for above example address */ 6917 hash_value = ((mc_addr[4] >> 4) | 6918 (((uint16_t) mc_addr[5]) << 4)); 6919 } else { 6920 /* [45:34] i.e. 0x5D8 for above example address */ 6921 hash_value = ((mc_addr[4] >> 2) | 6922 (((uint16_t) mc_addr[5]) << 6)); 6923 } 6924 break; 6925 case 3: 6926 if (hw->mac_type == em_ich8lan || 6927 hw->mac_type == em_ich9lan || 6928 hw->mac_type == em_ich10lan || 6929 hw->mac_type == em_pchlan || 6930 hw->mac_type == em_pch2lan) { 6931 /* [43:34] i.e. 0x18D for above example address */ 6932 hash_value = ((mc_addr[4] >> 2) | 6933 (((uint16_t) mc_addr[5]) << 6)); 6934 } else { 6935 /* [43:32] i.e. 0x634 for above example address */ 6936 hash_value = ((mc_addr[4]) | 6937 (((uint16_t) mc_addr[5]) << 8)); 6938 } 6939 break; 6940 } 6941 6942 hash_value &= 0xFFF; 6943 if (hw->mac_type == em_ich8lan || 6944 hw->mac_type == em_ich9lan || 6945 hw->mac_type == em_ich10lan || 6946 hw->mac_type == em_pchlan || 6947 hw->mac_type == em_pch2lan) 6948 hash_value &= 0x3FF; 6949 6950 return hash_value; 6951 } 6952 6953 /****************************************************************************** 6954 * Sets the bit in the multicast table corresponding to the hash value. 6955 * 6956 * hw - Struct containing variables accessed by shared code 6957 * hash_value - Multicast address hash value 6958 *****************************************************************************/ 6959 void 6960 em_mta_set(struct em_hw *hw, uint32_t hash_value) 6961 { 6962 uint32_t hash_bit, hash_reg; 6963 uint32_t mta; 6964 uint32_t temp; 6965 /* 6966 * The MTA is a register array of 128 32-bit registers. It is treated 6967 * like an array of 4096 bits. We want to set bit 6968 * BitArray[hash_value]. So we figure out what register the bit is 6969 * in, read it, OR in the new bit, then write back the new value. 6970 * The register is determined by the upper 7 bits of the hash value 6971 * and the bit within that register are determined by the lower 5 6972 * bits of the value. 6973 */ 6974 hash_reg = (hash_value >> 5) & 0x7F; 6975 if (hw->mac_type == em_ich8lan || 6976 hw->mac_type == em_ich9lan || 6977 hw->mac_type == em_ich10lan || 6978 hw->mac_type == em_pchlan || 6979 hw->mac_type == em_pch2lan) 6980 hash_reg &= 0x1F; 6981 6982 hash_bit = hash_value & 0x1F; 6983 6984 mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg); 6985 6986 mta |= (1 << hash_bit); 6987 /* 6988 * If we are on an 82544 and we are trying to write an odd offset in 6989 * the MTA, save off the previous entry before writing and restore 6990 * the old value after writing. 6991 */ 6992 if ((hw->mac_type == em_82544) && ((hash_reg & 0x1) == 1)) { 6993 temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1)); 6994 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta); 6995 E1000_WRITE_FLUSH(hw); 6996 E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp); 6997 E1000_WRITE_FLUSH(hw); 6998 } else { 6999 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta); 7000 E1000_WRITE_FLUSH(hw); 7001 } 7002 } 7003 7004 /****************************************************************************** 7005 * Puts an ethernet address into a receive address register. 7006 * 7007 * hw - Struct containing variables accessed by shared code 7008 * addr - Address to put into receive address register 7009 * index - Receive address register to write 7010 *****************************************************************************/ 7011 void 7012 em_rar_set(struct em_hw *hw, uint8_t *addr, uint32_t index) 7013 { 7014 uint32_t rar_low, rar_high; 7015 /* 7016 * HW expects these in little endian so we reverse the byte order 7017 * from network order (big endian) to little endian 7018 */ 7019 rar_low = ((uint32_t) addr[0] | ((uint32_t) addr[1] << 8) | 7020 ((uint32_t) addr[2] << 16) | ((uint32_t) addr[3] << 24)); 7021 rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8)); 7022 /* 7023 * Disable Rx and flush all Rx frames before enabling RSS to avoid Rx 7024 * unit hang. 7025 * 7026 * Description: If there are any Rx frames queued up or otherwise 7027 * present in the HW before RSS is enabled, and then we enable RSS, 7028 * the HW Rx unit will hang. To work around this issue, we have to 7029 * disable receives and flush out all Rx frames before we enable RSS. 7030 * To do so, we modify we redirect all Rx traffic to manageability 7031 * and then reset the HW. This flushes away Rx frames, and (since the 7032 * redirections to manageability persists across resets) keeps new 7033 * ones from coming in while we work. Then, we clear the Address 7034 * Valid AV bit for all MAC addresses and undo the re-direction to 7035 * manageability. Now, frames are coming in again, but the MAC won't 7036 * accept them, so far so good. We now proceed to initialize RSS (if 7037 * necessary) and configure the Rx unit. Last, we re-enable the AV 7038 * bits and continue on our merry way. 7039 */ 7040 switch (hw->mac_type) { 7041 case em_82571: 7042 case em_82572: 7043 case em_80003es2lan: 7044 if (hw->leave_av_bit_off == TRUE) 7045 break; 7046 default: 7047 /* Indicate to hardware the Address is Valid. */ 7048 rar_high |= E1000_RAH_AV; 7049 break; 7050 } 7051 7052 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low); 7053 E1000_WRITE_FLUSH(hw); 7054 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high); 7055 E1000_WRITE_FLUSH(hw); 7056 } 7057 7058 /****************************************************************************** 7059 * Clears the VLAN filer table 7060 * 7061 * hw - Struct containing variables accessed by shared code 7062 *****************************************************************************/ 7063 STATIC void 7064 em_clear_vfta(struct em_hw *hw) 7065 { 7066 uint32_t offset; 7067 uint32_t vfta_value = 0; 7068 uint32_t vfta_offset = 0; 7069 uint32_t vfta_bit_in_reg = 0; 7070 if (hw->mac_type == em_ich8lan || 7071 hw->mac_type == em_ich9lan || 7072 hw->mac_type == em_ich10lan || 7073 hw->mac_type == em_pchlan || 7074 hw->mac_type == em_pch2lan) 7075 return; 7076 7077 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) { 7078 if (hw->mng_cookie.vlan_id != 0) { 7079 /* 7080 * The VFTA is a 4096b bit-field, each identifying a 7081 * single VLAN ID. The following operations 7082 * determine which 32b entry (i.e. offset) into the 7083 * array we want to set the VLAN ID (i.e. bit) of the 7084 * manageability unit. 7085 */ 7086 vfta_offset = (hw->mng_cookie.vlan_id >> 7087 E1000_VFTA_ENTRY_SHIFT) & E1000_VFTA_ENTRY_MASK; 7088 7089 vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id & 7090 E1000_VFTA_ENTRY_BIT_SHIFT_MASK); 7091 } 7092 } 7093 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 7094 /* 7095 * If the offset we want to clear is the same offset of the 7096 * manageability VLAN ID, then clear all bits except that of 7097 * the manageability unit 7098 */ 7099 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; 7100 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value); 7101 E1000_WRITE_FLUSH(hw); 7102 } 7103 } 7104 7105 /* 7106 * Due to hw errata, if the host tries to configure the VFTA register 7107 * while performing queries from the BMC or DMA, then the VFTA in some 7108 * cases won't be written. 7109 */ 7110 void 7111 em_clear_vfta_i350(struct em_hw *hw) 7112 { 7113 uint32_t offset; 7114 int i; 7115 7116 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 7117 for (i = 0; i < 10; i++) 7118 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0); 7119 E1000_WRITE_FLUSH(hw); 7120 } 7121 } 7122 7123 STATIC int32_t 7124 em_id_led_init(struct em_hw *hw) 7125 { 7126 uint32_t ledctl; 7127 const uint32_t ledctl_mask = 0x000000FF; 7128 const uint32_t ledctl_on = E1000_LEDCTL_MODE_LED_ON; 7129 const uint32_t ledctl_off = E1000_LEDCTL_MODE_LED_OFF; 7130 uint16_t eeprom_data, i, temp; 7131 const uint16_t led_mask = 0x0F; 7132 DEBUGFUNC("em_id_led_init"); 7133 7134 if (hw->mac_type < em_82540 || hw->mac_type == em_icp_xxxx) { 7135 /* Nothing to do */ 7136 return E1000_SUCCESS; 7137 } 7138 ledctl = E1000_READ_REG(hw, LEDCTL); 7139 hw->ledctl_default = ledctl; 7140 hw->ledctl_mode1 = hw->ledctl_default; 7141 hw->ledctl_mode2 = hw->ledctl_default; 7142 7143 if (em_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) { 7144 DEBUGOUT("EEPROM Read Error\n"); 7145 return -E1000_ERR_EEPROM; 7146 } 7147 if ((hw->mac_type == em_82573) && 7148 (eeprom_data == ID_LED_RESERVED_82573)) 7149 eeprom_data = ID_LED_DEFAULT_82573; 7150 else if ((eeprom_data == ID_LED_RESERVED_0000) || 7151 (eeprom_data == ID_LED_RESERVED_FFFF)) { 7152 if (hw->mac_type == em_ich8lan || 7153 hw->mac_type == em_ich9lan || 7154 hw->mac_type == em_ich10lan) // XXX 7155 eeprom_data = ID_LED_DEFAULT_ICH8LAN; 7156 else 7157 eeprom_data = ID_LED_DEFAULT; 7158 } 7159 for (i = 0; i < 4; i++) { 7160 temp = (eeprom_data >> (i << 2)) & led_mask; 7161 switch (temp) { 7162 case ID_LED_ON1_DEF2: 7163 case ID_LED_ON1_ON2: 7164 case ID_LED_ON1_OFF2: 7165 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 7166 hw->ledctl_mode1 |= ledctl_on << (i << 3); 7167 break; 7168 case ID_LED_OFF1_DEF2: 7169 case ID_LED_OFF1_ON2: 7170 case ID_LED_OFF1_OFF2: 7171 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 7172 hw->ledctl_mode1 |= ledctl_off << (i << 3); 7173 break; 7174 default: 7175 /* Do nothing */ 7176 break; 7177 } 7178 switch (temp) { 7179 case ID_LED_DEF1_ON2: 7180 case ID_LED_ON1_ON2: 7181 case ID_LED_OFF1_ON2: 7182 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 7183 hw->ledctl_mode2 |= ledctl_on << (i << 3); 7184 break; 7185 case ID_LED_DEF1_OFF2: 7186 case ID_LED_ON1_OFF2: 7187 case ID_LED_OFF1_OFF2: 7188 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 7189 hw->ledctl_mode2 |= ledctl_off << (i << 3); 7190 break; 7191 default: 7192 /* Do nothing */ 7193 break; 7194 } 7195 } 7196 return E1000_SUCCESS; 7197 } 7198 7199 /****************************************************************************** 7200 * Clears all hardware statistics counters. 7201 * 7202 * hw - Struct containing variables accessed by shared code 7203 *****************************************************************************/ 7204 void 7205 em_clear_hw_cntrs(struct em_hw *hw) 7206 { 7207 volatile uint32_t temp; 7208 temp = E1000_READ_REG(hw, CRCERRS); 7209 temp = E1000_READ_REG(hw, SYMERRS); 7210 temp = E1000_READ_REG(hw, MPC); 7211 temp = E1000_READ_REG(hw, SCC); 7212 temp = E1000_READ_REG(hw, ECOL); 7213 temp = E1000_READ_REG(hw, MCC); 7214 temp = E1000_READ_REG(hw, LATECOL); 7215 temp = E1000_READ_REG(hw, COLC); 7216 temp = E1000_READ_REG(hw, DC); 7217 temp = E1000_READ_REG(hw, SEC); 7218 temp = E1000_READ_REG(hw, RLEC); 7219 temp = E1000_READ_REG(hw, XONRXC); 7220 temp = E1000_READ_REG(hw, XONTXC); 7221 temp = E1000_READ_REG(hw, XOFFRXC); 7222 temp = E1000_READ_REG(hw, XOFFTXC); 7223 temp = E1000_READ_REG(hw, FCRUC); 7224 7225 if (hw->mac_type != em_ich8lan && 7226 hw->mac_type != em_ich9lan && 7227 hw->mac_type != em_ich10lan && 7228 hw->mac_type != em_pchlan && 7229 hw->mac_type != em_pch2lan) { 7230 temp = E1000_READ_REG(hw, PRC64); 7231 temp = E1000_READ_REG(hw, PRC127); 7232 temp = E1000_READ_REG(hw, PRC255); 7233 temp = E1000_READ_REG(hw, PRC511); 7234 temp = E1000_READ_REG(hw, PRC1023); 7235 temp = E1000_READ_REG(hw, PRC1522); 7236 } 7237 temp = E1000_READ_REG(hw, GPRC); 7238 temp = E1000_READ_REG(hw, BPRC); 7239 temp = E1000_READ_REG(hw, MPRC); 7240 temp = E1000_READ_REG(hw, GPTC); 7241 temp = E1000_READ_REG(hw, GORCL); 7242 temp = E1000_READ_REG(hw, GORCH); 7243 temp = E1000_READ_REG(hw, GOTCL); 7244 temp = E1000_READ_REG(hw, GOTCH); 7245 temp = E1000_READ_REG(hw, RNBC); 7246 temp = E1000_READ_REG(hw, RUC); 7247 temp = E1000_READ_REG(hw, RFC); 7248 temp = E1000_READ_REG(hw, ROC); 7249 temp = E1000_READ_REG(hw, RJC); 7250 temp = E1000_READ_REG(hw, TORL); 7251 temp = E1000_READ_REG(hw, TORH); 7252 temp = E1000_READ_REG(hw, TOTL); 7253 temp = E1000_READ_REG(hw, TOTH); 7254 temp = E1000_READ_REG(hw, TPR); 7255 temp = E1000_READ_REG(hw, TPT); 7256 7257 if (hw->mac_type != em_ich8lan && 7258 hw->mac_type != em_ich9lan && 7259 hw->mac_type != em_ich10lan && 7260 hw->mac_type != em_pchlan && 7261 hw->mac_type != em_pch2lan) { 7262 temp = E1000_READ_REG(hw, PTC64); 7263 temp = E1000_READ_REG(hw, PTC127); 7264 temp = E1000_READ_REG(hw, PTC255); 7265 temp = E1000_READ_REG(hw, PTC511); 7266 temp = E1000_READ_REG(hw, PTC1023); 7267 temp = E1000_READ_REG(hw, PTC1522); 7268 } 7269 temp = E1000_READ_REG(hw, MPTC); 7270 temp = E1000_READ_REG(hw, BPTC); 7271 7272 if (hw->mac_type < em_82543) 7273 return; 7274 7275 temp = E1000_READ_REG(hw, ALGNERRC); 7276 temp = E1000_READ_REG(hw, RXERRC); 7277 temp = E1000_READ_REG(hw, TNCRS); 7278 temp = E1000_READ_REG(hw, CEXTERR); 7279 temp = E1000_READ_REG(hw, TSCTC); 7280 temp = E1000_READ_REG(hw, TSCTFC); 7281 7282 if (hw->mac_type <= em_82544 7283 || hw->mac_type == em_icp_xxxx) 7284 return; 7285 7286 temp = E1000_READ_REG(hw, MGTPRC); 7287 temp = E1000_READ_REG(hw, MGTPDC); 7288 temp = E1000_READ_REG(hw, MGTPTC); 7289 7290 if (hw->mac_type <= em_82547_rev_2) 7291 return; 7292 7293 temp = E1000_READ_REG(hw, IAC); 7294 temp = E1000_READ_REG(hw, ICRXOC); 7295 7296 if (hw->phy_type == em_phy_82577 || 7297 hw->phy_type == em_phy_82578 || 7298 hw->phy_type == em_phy_82579) { 7299 uint16_t phy_data; 7300 7301 em_read_phy_reg(hw, HV_SCC_UPPER, &phy_data); 7302 em_read_phy_reg(hw, HV_SCC_LOWER, &phy_data); 7303 em_read_phy_reg(hw, HV_ECOL_UPPER, &phy_data); 7304 em_read_phy_reg(hw, HV_ECOL_LOWER, &phy_data); 7305 em_read_phy_reg(hw, HV_MCC_UPPER, &phy_data); 7306 em_read_phy_reg(hw, HV_MCC_LOWER, &phy_data); 7307 em_read_phy_reg(hw, HV_LATECOL_UPPER, &phy_data); 7308 em_read_phy_reg(hw, HV_LATECOL_LOWER, &phy_data); 7309 em_read_phy_reg(hw, HV_COLC_UPPER, &phy_data); 7310 em_read_phy_reg(hw, HV_COLC_LOWER, &phy_data); 7311 em_read_phy_reg(hw, HV_DC_UPPER, &phy_data); 7312 em_read_phy_reg(hw, HV_DC_LOWER, &phy_data); 7313 em_read_phy_reg(hw, HV_TNCRS_UPPER, &phy_data); 7314 em_read_phy_reg(hw, HV_TNCRS_LOWER, &phy_data); 7315 } 7316 7317 if (hw->mac_type == em_ich8lan || 7318 hw->mac_type == em_ich9lan || 7319 hw->mac_type == em_ich10lan || 7320 hw->mac_type == em_pchlan || 7321 hw->mac_type != em_pch2lan) 7322 return; 7323 7324 temp = E1000_READ_REG(hw, ICRXPTC); 7325 temp = E1000_READ_REG(hw, ICRXATC); 7326 temp = E1000_READ_REG(hw, ICTXPTC); 7327 temp = E1000_READ_REG(hw, ICTXATC); 7328 temp = E1000_READ_REG(hw, ICTXQEC); 7329 temp = E1000_READ_REG(hw, ICTXQMTC); 7330 temp = E1000_READ_REG(hw, ICRXDMTC); 7331 } 7332 7333 #ifndef SMALL_KERNEL 7334 /****************************************************************************** 7335 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT 7336 * 7337 * hw - Struct containing variables accessed by shared code 7338 * frame_len - The length of the frame in question 7339 * mac_addr - The Ethernet destination address of the frame in question 7340 *****************************************************************************/ 7341 void 7342 em_tbi_adjust_stats(struct em_hw *hw, struct em_hw_stats *stats, 7343 uint32_t frame_len, uint8_t *mac_addr) 7344 { 7345 uint64_t carry_bit; 7346 /* First adjust the frame length. */ 7347 frame_len--; 7348 /* 7349 * We need to adjust the statistics counters, since the hardware 7350 * counters overcount this packet as a CRC error and undercount the 7351 * packet as a good packet 7352 */ 7353 /* This packet should not be counted as a CRC error. */ 7354 stats->crcerrs--; 7355 /* This packet does count as a Good Packet Received. */ 7356 stats->gprc++; 7357 7358 /* Adjust the Good Octets received counters */ 7359 carry_bit = 0x80000000 & stats->gorcl; 7360 stats->gorcl += frame_len; 7361 /* 7362 * If the high bit of Gorcl (the low 32 bits of the Good Octets 7363 * Received Count) was one before the addition, AND it is zero after, 7364 * then we lost the carry out, need to add one to Gorch (Good Octets 7365 * Received Count High). This could be simplified if all environments 7366 * supported 64-bit integers. 7367 */ 7368 if (carry_bit && ((stats->gorcl & 0x80000000) == 0)) 7369 stats->gorch++; 7370 /* 7371 * Is this a broadcast or multicast? Check broadcast first, since 7372 * the test for a multicast frame will test positive on a broadcast 7373 * frame. 7374 */ 7375 if ((mac_addr[0] == (uint8_t) 0xff) && (mac_addr[1] == (uint8_t) 0xff)) 7376 /* Broadcast packet */ 7377 stats->bprc++; 7378 else if (*mac_addr & 0x01) 7379 /* Multicast packet */ 7380 stats->mprc++; 7381 7382 if (frame_len == hw->max_frame_size) { 7383 /* 7384 * In this case, the hardware has overcounted the number of 7385 * oversize frames. 7386 */ 7387 if (stats->roc > 0) 7388 stats->roc--; 7389 } 7390 /* 7391 * Adjust the bin counters when the extra byte put the frame in the 7392 * wrong bin. Remember that the frame_len was adjusted above. 7393 */ 7394 if (frame_len == 64) { 7395 stats->prc64++; 7396 stats->prc127--; 7397 } else if (frame_len == 127) { 7398 stats->prc127++; 7399 stats->prc255--; 7400 } else if (frame_len == 255) { 7401 stats->prc255++; 7402 stats->prc511--; 7403 } else if (frame_len == 511) { 7404 stats->prc511++; 7405 stats->prc1023--; 7406 } else if (frame_len == 1023) { 7407 stats->prc1023++; 7408 stats->prc1522--; 7409 } else if (frame_len == 1522) { 7410 stats->prc1522++; 7411 } 7412 } 7413 #endif /* !SMALL_KERNEL */ 7414 7415 /****************************************************************************** 7416 * Gets the current PCI bus type, speed, and width of the hardware 7417 * 7418 * hw - Struct containing variables accessed by shared code 7419 *****************************************************************************/ 7420 void 7421 em_get_bus_info(struct em_hw *hw) 7422 { 7423 int32_t ret_val; 7424 uint16_t pci_ex_link_status; 7425 uint32_t status; 7426 switch (hw->mac_type) { 7427 case em_82542_rev2_0: 7428 case em_82542_rev2_1: 7429 hw->bus_type = em_bus_type_unknown; 7430 hw->bus_speed = em_bus_speed_unknown; 7431 hw->bus_width = em_bus_width_unknown; 7432 break; 7433 case em_icp_xxxx: 7434 hw->bus_type = em_bus_type_cpp; 7435 hw->bus_speed = em_bus_speed_unknown; 7436 hw->bus_width = em_bus_width_unknown; 7437 break; 7438 case em_82571: 7439 case em_82572: 7440 case em_82573: 7441 case em_82574: 7442 case em_82575: 7443 case em_82580: 7444 case em_80003es2lan: 7445 case em_i350: 7446 hw->bus_type = em_bus_type_pci_express; 7447 hw->bus_speed = em_bus_speed_2500; 7448 ret_val = em_read_pcie_cap_reg(hw, PCI_EX_LINK_STATUS, 7449 &pci_ex_link_status); 7450 if (ret_val) 7451 hw->bus_width = em_bus_width_unknown; 7452 else 7453 hw->bus_width = (pci_ex_link_status & 7454 PCI_EX_LINK_WIDTH_MASK) >> PCI_EX_LINK_WIDTH_SHIFT; 7455 break; 7456 case em_ich8lan: 7457 case em_ich9lan: 7458 case em_ich10lan: 7459 case em_pchlan: 7460 case em_pch2lan: 7461 hw->bus_type = em_bus_type_pci_express; 7462 hw->bus_speed = em_bus_speed_2500; 7463 hw->bus_width = em_bus_width_pciex_1; 7464 break; 7465 default: 7466 status = E1000_READ_REG(hw, STATUS); 7467 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ? 7468 em_bus_type_pcix : em_bus_type_pci; 7469 7470 if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) { 7471 hw->bus_speed = (hw->bus_type == em_bus_type_pci) ? 7472 em_bus_speed_66 : em_bus_speed_120; 7473 } else if (hw->bus_type == em_bus_type_pci) { 7474 hw->bus_speed = (status & E1000_STATUS_PCI66) ? 7475 em_bus_speed_66 : em_bus_speed_33; 7476 } else { 7477 switch (status & E1000_STATUS_PCIX_SPEED) { 7478 case E1000_STATUS_PCIX_SPEED_66: 7479 hw->bus_speed = em_bus_speed_66; 7480 break; 7481 case E1000_STATUS_PCIX_SPEED_100: 7482 hw->bus_speed = em_bus_speed_100; 7483 break; 7484 case E1000_STATUS_PCIX_SPEED_133: 7485 hw->bus_speed = em_bus_speed_133; 7486 break; 7487 default: 7488 hw->bus_speed = em_bus_speed_reserved; 7489 break; 7490 } 7491 } 7492 hw->bus_width = (status & E1000_STATUS_BUS64) ? 7493 em_bus_width_64 : em_bus_width_32; 7494 break; 7495 } 7496 } 7497 7498 /****************************************************************************** 7499 * Writes a value to one of the devices registers using port I/O (as opposed to 7500 * memory mapped I/O). Only 82544 and newer devices support port I/O. 7501 * 7502 * hw - Struct containing variables accessed by shared code 7503 * offset - offset to write to 7504 * value - value to write 7505 *****************************************************************************/ 7506 STATIC void 7507 em_write_reg_io(struct em_hw *hw, uint32_t offset, uint32_t value) 7508 { 7509 unsigned long io_addr = hw->io_base; 7510 unsigned long io_data = hw->io_base + 4; 7511 em_io_write(hw, io_addr, offset); 7512 em_io_write(hw, io_data, value); 7513 } 7514 7515 /****************************************************************************** 7516 * Estimates the cable length. 7517 * 7518 * hw - Struct containing variables accessed by shared code 7519 * min_length - The estimated minimum length 7520 * max_length - The estimated maximum length 7521 * 7522 * returns: - E1000_ERR_XXX 7523 * E1000_SUCCESS 7524 * 7525 * This function always returns a ranged length (minimum & maximum). 7526 * So for M88 phy's, this function interprets the one value returned from the 7527 * register to the minimum and maximum range. 7528 * For IGP phy's, the function calculates the range by the AGC registers. 7529 *****************************************************************************/ 7530 STATIC int32_t 7531 em_get_cable_length(struct em_hw *hw, uint16_t *min_length, 7532 uint16_t *max_length) 7533 { 7534 int32_t ret_val; 7535 uint16_t agc_value = 0; 7536 uint16_t i, phy_data; 7537 uint16_t cable_length; 7538 DEBUGFUNC("em_get_cable_length"); 7539 7540 *min_length = *max_length = 0; 7541 7542 /* Use old method for Phy older than IGP */ 7543 if (hw->phy_type == em_phy_m88 || 7544 hw->phy_type == em_phy_oem || 7545 hw->phy_type == em_phy_82578) { 7546 7547 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, 7548 &phy_data); 7549 if (ret_val) 7550 return ret_val; 7551 cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 7552 M88E1000_PSSR_CABLE_LENGTH_SHIFT; 7553 7554 /* Convert the enum value to ranged values */ 7555 switch (cable_length) { 7556 case em_cable_length_50: 7557 *min_length = 0; 7558 *max_length = em_igp_cable_length_50; 7559 break; 7560 case em_cable_length_50_80: 7561 *min_length = em_igp_cable_length_50; 7562 *max_length = em_igp_cable_length_80; 7563 break; 7564 case em_cable_length_80_110: 7565 *min_length = em_igp_cable_length_80; 7566 *max_length = em_igp_cable_length_110; 7567 break; 7568 case em_cable_length_110_140: 7569 *min_length = em_igp_cable_length_110; 7570 *max_length = em_igp_cable_length_140; 7571 break; 7572 case em_cable_length_140: 7573 *min_length = em_igp_cable_length_140; 7574 *max_length = em_igp_cable_length_170; 7575 break; 7576 default: 7577 return -E1000_ERR_PHY; 7578 break; 7579 } 7580 } else if (hw->phy_type == em_phy_gg82563) { 7581 ret_val = em_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE, 7582 &phy_data); 7583 if (ret_val) 7584 return ret_val; 7585 cable_length = phy_data & GG82563_DSPD_CABLE_LENGTH; 7586 7587 switch (cable_length) { 7588 case em_gg_cable_length_60: 7589 *min_length = 0; 7590 *max_length = em_igp_cable_length_60; 7591 break; 7592 case em_gg_cable_length_60_115: 7593 *min_length = em_igp_cable_length_60; 7594 *max_length = em_igp_cable_length_115; 7595 break; 7596 case em_gg_cable_length_115_150: 7597 *min_length = em_igp_cable_length_115; 7598 *max_length = em_igp_cable_length_150; 7599 break; 7600 case em_gg_cable_length_150: 7601 *min_length = em_igp_cable_length_150; 7602 *max_length = em_igp_cable_length_180; 7603 break; 7604 default: 7605 return -E1000_ERR_PHY; 7606 break; 7607 } 7608 } else if (hw->phy_type == em_phy_igp) { /* For IGP PHY */ 7609 uint16_t cur_agc_value; 7610 uint16_t min_agc_value = 7611 IGP01E1000_AGC_LENGTH_TABLE_SIZE; 7612 uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = 7613 {IGP01E1000_PHY_AGC_A, IGP01E1000_PHY_AGC_B, 7614 IGP01E1000_PHY_AGC_C, IGP01E1000_PHY_AGC_D}; 7615 7616 /* Read the AGC registers for all channels */ 7617 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 7618 ret_val = em_read_phy_reg(hw, agc_reg_array[i], 7619 &phy_data); 7620 if (ret_val) 7621 return ret_val; 7622 7623 cur_agc_value = phy_data >> 7624 IGP01E1000_AGC_LENGTH_SHIFT; 7625 7626 /* Value bound check. */ 7627 if ((cur_agc_value >= 7628 IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) || 7629 (cur_agc_value == 0)) 7630 return -E1000_ERR_PHY; 7631 7632 agc_value += cur_agc_value; 7633 7634 /* Update minimal AGC value. */ 7635 if (min_agc_value > cur_agc_value) 7636 min_agc_value = cur_agc_value; 7637 } 7638 7639 /* Remove the minimal AGC result for length < 50m */ 7640 if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * 7641 em_igp_cable_length_50) { 7642 agc_value -= min_agc_value; 7643 7644 /* 7645 * Get the average length of the remaining 3 channels 7646 */ 7647 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1); 7648 } else { 7649 /* Get the average length of all the 4 channels. */ 7650 agc_value /= IGP01E1000_PHY_CHANNEL_NUM; 7651 } 7652 7653 /* Set the range of the calculated length. */ 7654 *min_length = ((em_igp_cable_length_table[agc_value] - 7655 IGP01E1000_AGC_RANGE) > 0) ? 7656 (em_igp_cable_length_table[agc_value] - 7657 IGP01E1000_AGC_RANGE) : 0; 7658 *max_length = em_igp_cable_length_table[agc_value] + 7659 IGP01E1000_AGC_RANGE; 7660 } else if (hw->phy_type == em_phy_igp_2 || 7661 hw->phy_type == em_phy_igp_3) { 7662 uint16_t cur_agc_index, max_agc_index = 0; 7663 uint16_t min_agc_index = IGP02E1000_AGC_LENGTH_TABLE_SIZE - 1; 7664 uint16_t agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = 7665 {IGP02E1000_PHY_AGC_A, IGP02E1000_PHY_AGC_B, 7666 IGP02E1000_PHY_AGC_C, IGP02E1000_PHY_AGC_D}; 7667 /* Read the AGC registers for all channels */ 7668 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { 7669 ret_val = em_read_phy_reg(hw, agc_reg_array[i], 7670 &phy_data); 7671 if (ret_val) 7672 return ret_val; 7673 /* 7674 * Getting bits 15:9, which represent the combination 7675 * of course and fine gain values. The result is a 7676 * number that can be put into the lookup table to 7677 * obtain the approximate cable length. 7678 */ 7679 cur_agc_index = (phy_data >> 7680 IGP02E1000_AGC_LENGTH_SHIFT) & 7681 IGP02E1000_AGC_LENGTH_MASK; 7682 7683 /* Array index bound check. */ 7684 if ((cur_agc_index >= IGP02E1000_AGC_LENGTH_TABLE_SIZE) 7685 || (cur_agc_index == 0)) 7686 return -E1000_ERR_PHY; 7687 7688 /* Remove min & max AGC values from calculation. */ 7689 if (em_igp_2_cable_length_table[min_agc_index] > 7690 em_igp_2_cable_length_table[cur_agc_index]) 7691 min_agc_index = cur_agc_index; 7692 if (em_igp_2_cable_length_table[max_agc_index] < 7693 em_igp_2_cable_length_table[cur_agc_index]) 7694 max_agc_index = cur_agc_index; 7695 7696 agc_value += em_igp_2_cable_length_table 7697 [cur_agc_index]; 7698 } 7699 7700 agc_value -= (em_igp_2_cable_length_table[min_agc_index] + 7701 em_igp_2_cable_length_table[max_agc_index]); 7702 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); 7703 /* 7704 * Calculate cable length with the error range of +/- 10 7705 * meters. 7706 */ 7707 *min_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ? 7708 (agc_value - IGP02E1000_AGC_RANGE) : 0; 7709 *max_length = agc_value + IGP02E1000_AGC_RANGE; 7710 } 7711 return E1000_SUCCESS; 7712 } 7713 7714 /****************************************************************************** 7715 * Check if Downshift occured 7716 * 7717 * hw - Struct containing variables accessed by shared code 7718 * downshift - output parameter : 0 - No Downshift ocured. 7719 * 1 - Downshift ocured. 7720 * 7721 * returns: - E1000_ERR_XXX 7722 * E1000_SUCCESS 7723 * 7724 * For phy's older then IGP, this function reads the Downshift bit in the Phy 7725 * Specific Status register. For IGP phy's, it reads the Downgrade bit in the 7726 * Link Health register. In IGP this bit is latched high, so the driver must 7727 * read it immediately after link is established. 7728 *****************************************************************************/ 7729 STATIC int32_t 7730 em_check_downshift(struct em_hw *hw) 7731 { 7732 int32_t ret_val; 7733 uint16_t phy_data; 7734 DEBUGFUNC("em_check_downshift"); 7735 7736 if (hw->phy_type == em_phy_igp || 7737 hw->phy_type == em_phy_igp_3 || 7738 hw->phy_type == em_phy_igp_2) { 7739 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH, 7740 &phy_data); 7741 if (ret_val) 7742 return ret_val; 7743 7744 hw->speed_downgraded = (phy_data & 7745 IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0; 7746 } else if ((hw->phy_type == em_phy_m88) || 7747 (hw->phy_type == em_phy_gg82563) || 7748 (hw->phy_type == em_phy_oem) || 7749 (hw->phy_type == em_phy_82578)) { 7750 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, 7751 &phy_data); 7752 if (ret_val) 7753 return ret_val; 7754 7755 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >> 7756 M88E1000_PSSR_DOWNSHIFT_SHIFT; 7757 } else if (hw->phy_type == em_phy_ife) { 7758 /* em_phy_ife supports 10/100 speed only */ 7759 hw->speed_downgraded = FALSE; 7760 } 7761 return E1000_SUCCESS; 7762 } 7763 7764 /***************************************************************************** 7765 * 7766 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a 7767 * gigabit link is achieved to improve link quality. 7768 * 7769 * hw: Struct containing variables accessed by shared code 7770 * 7771 * returns: - E1000_ERR_PHY if fail to read/write the PHY 7772 * E1000_SUCCESS at any other case. 7773 * 7774 ****************************************************************************/ 7775 STATIC int32_t 7776 em_config_dsp_after_link_change(struct em_hw *hw, boolean_t link_up) 7777 { 7778 int32_t ret_val; 7779 uint16_t phy_data, phy_saved_data, speed, duplex, i; 7780 uint16_t dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = 7781 {IGP01E1000_PHY_AGC_PARAM_A, IGP01E1000_PHY_AGC_PARAM_B, 7782 IGP01E1000_PHY_AGC_PARAM_C, IGP01E1000_PHY_AGC_PARAM_D}; 7783 uint16_t min_length, max_length; 7784 DEBUGFUNC("em_config_dsp_after_link_change"); 7785 7786 if (hw->phy_type != em_phy_igp) 7787 return E1000_SUCCESS; 7788 7789 if (link_up) { 7790 ret_val = em_get_speed_and_duplex(hw, &speed, &duplex); 7791 if (ret_val) { 7792 DEBUGOUT("Error getting link speed and duplex\n"); 7793 return ret_val; 7794 } 7795 if (speed == SPEED_1000) { 7796 7797 ret_val = em_get_cable_length(hw, &min_length, &max_length); 7798 if (ret_val) 7799 return ret_val; 7800 7801 if ((hw->dsp_config_state == em_dsp_config_enabled) && 7802 min_length >= em_igp_cable_length_50) { 7803 7804 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; 7805 i++) { 7806 ret_val = em_read_phy_reg(hw, 7807 dsp_reg_array[i], &phy_data); 7808 if (ret_val) 7809 return ret_val; 7810 7811 phy_data &= 7812 ~IGP01E1000_PHY_EDAC_MU_INDEX; 7813 7814 ret_val = em_write_phy_reg(hw, 7815 dsp_reg_array[i], phy_data); 7816 if (ret_val) 7817 return ret_val; 7818 } 7819 hw->dsp_config_state = em_dsp_config_activated; 7820 } 7821 if ((hw->ffe_config_state == em_ffe_config_enabled) && 7822 (min_length < em_igp_cable_length_50)) { 7823 7824 uint16_t ffe_idle_err_timeout = 7825 FFE_IDLE_ERR_COUNT_TIMEOUT_20; 7826 uint32_t idle_errs = 0; 7827 /* clear previous idle error counts */ 7828 ret_val = em_read_phy_reg(hw, PHY_1000T_STATUS, 7829 &phy_data); 7830 if (ret_val) 7831 return ret_val; 7832 7833 for (i = 0; i < ffe_idle_err_timeout; i++) { 7834 usec_delay(1000); 7835 ret_val = em_read_phy_reg(hw, 7836 PHY_1000T_STATUS, &phy_data); 7837 if (ret_val) 7838 return ret_val; 7839 7840 idle_errs += (phy_data & 7841 SR_1000T_IDLE_ERROR_CNT); 7842 if (idle_errs > 7843 SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) { 7844 hw->ffe_config_state = 7845 em_ffe_config_active; 7846 7847 ret_val = em_write_phy_reg(hw, 7848 IGP01E1000_PHY_DSP_FFE, 7849 IGP01E1000_PHY_DSP_FFE_CM_CP); 7850 if (ret_val) 7851 return ret_val; 7852 break; 7853 } 7854 if (idle_errs) 7855 ffe_idle_err_timeout = 7856 FFE_IDLE_ERR_COUNT_TIMEOUT_100; 7857 } 7858 } 7859 } 7860 } else { 7861 if (hw->dsp_config_state == em_dsp_config_activated) { 7862 /* 7863 * Save off the current value of register 0x2F5B to 7864 * be restored at the end of the routines. 7865 */ 7866 ret_val = em_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 7867 7868 if (ret_val) 7869 return ret_val; 7870 7871 /* Disable the PHY transmitter */ 7872 ret_val = em_write_phy_reg(hw, 0x2F5B, 0x0003); 7873 7874 if (ret_val) 7875 return ret_val; 7876 7877 msec_delay_irq(20); 7878 7879 ret_val = em_write_phy_reg(hw, 0x0000, 7880 IGP01E1000_IEEE_FORCE_GIGA); 7881 if (ret_val) 7882 return ret_val; 7883 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 7884 ret_val = em_read_phy_reg(hw, dsp_reg_array[i], 7885 &phy_data); 7886 if (ret_val) 7887 return ret_val; 7888 7889 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; 7890 phy_data |= 7891 IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS; 7892 7893 ret_val = em_write_phy_reg(hw, 7894 dsp_reg_array[i], phy_data); 7895 if (ret_val) 7896 return ret_val; 7897 } 7898 7899 ret_val = em_write_phy_reg(hw, 0x0000, 7900 IGP01E1000_IEEE_RESTART_AUTONEG); 7901 if (ret_val) 7902 return ret_val; 7903 7904 msec_delay_irq(20); 7905 7906 /* Now enable the transmitter */ 7907 ret_val = em_write_phy_reg(hw, 0x2F5B, phy_saved_data); 7908 7909 if (ret_val) 7910 return ret_val; 7911 7912 hw->dsp_config_state = em_dsp_config_enabled; 7913 } 7914 if (hw->ffe_config_state == em_ffe_config_active) { 7915 /* 7916 * Save off the current value of register 0x2F5B to 7917 * be restored at the end of the routines. 7918 */ 7919 ret_val = em_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 7920 7921 if (ret_val) 7922 return ret_val; 7923 7924 /* Disable the PHY transmitter */ 7925 ret_val = em_write_phy_reg(hw, 0x2F5B, 0x0003); 7926 7927 if (ret_val) 7928 return ret_val; 7929 7930 msec_delay_irq(20); 7931 7932 ret_val = em_write_phy_reg(hw, 0x0000, 7933 IGP01E1000_IEEE_FORCE_GIGA); 7934 if (ret_val) 7935 return ret_val; 7936 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE, 7937 IGP01E1000_PHY_DSP_FFE_DEFAULT); 7938 if (ret_val) 7939 return ret_val; 7940 7941 ret_val = em_write_phy_reg(hw, 0x0000, 7942 IGP01E1000_IEEE_RESTART_AUTONEG); 7943 if (ret_val) 7944 return ret_val; 7945 7946 msec_delay_irq(20); 7947 7948 /* Now enable the transmitter */ 7949 ret_val = em_write_phy_reg(hw, 0x2F5B, phy_saved_data); 7950 7951 if (ret_val) 7952 return ret_val; 7953 7954 hw->ffe_config_state = em_ffe_config_enabled; 7955 } 7956 } 7957 return E1000_SUCCESS; 7958 } 7959 7960 /***************************************************************************** 7961 * Set PHY to class A mode 7962 * Assumes the following operations will follow to enable the new class mode. 7963 * 1. Do a PHY soft reset 7964 * 2. Restart auto-negotiation or force link. 7965 * 7966 * hw - Struct containing variables accessed by shared code 7967 ****************************************************************************/ 7968 static int32_t 7969 em_set_phy_mode(struct em_hw *hw) 7970 { 7971 int32_t ret_val; 7972 uint16_t eeprom_data; 7973 DEBUGFUNC("em_set_phy_mode"); 7974 7975 if ((hw->mac_type == em_82545_rev_3) && 7976 (hw->media_type == em_media_type_copper)) { 7977 ret_val = em_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, 7978 &eeprom_data); 7979 if (ret_val) { 7980 return ret_val; 7981 } 7982 if ((eeprom_data != EEPROM_RESERVED_WORD) && 7983 (eeprom_data & EEPROM_PHY_CLASS_A)) { 7984 ret_val = em_write_phy_reg(hw, 7985 M88E1000_PHY_PAGE_SELECT, 0x000B); 7986 if (ret_val) 7987 return ret_val; 7988 ret_val = em_write_phy_reg(hw, 7989 M88E1000_PHY_GEN_CONTROL, 0x8104); 7990 if (ret_val) 7991 return ret_val; 7992 7993 hw->phy_reset_disable = FALSE; 7994 } 7995 } 7996 return E1000_SUCCESS; 7997 } 7998 7999 /***************************************************************************** 8000 * 8001 * This function sets the lplu state according to the active flag. When 8002 * activating lplu this function also disables smart speed and vise versa. 8003 * lplu will not be activated unless the device autonegotiation advertisement 8004 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. 8005 * hw: Struct containing variables accessed by shared code 8006 * active - true to enable lplu false to disable lplu. 8007 * 8008 * returns: - E1000_ERR_PHY if fail to read/write the PHY 8009 * E1000_SUCCESS at any other case. 8010 * 8011 ****************************************************************************/ 8012 STATIC int32_t 8013 em_set_d3_lplu_state(struct em_hw *hw, boolean_t active) 8014 { 8015 uint32_t phy_ctrl = 0; 8016 int32_t ret_val; 8017 uint16_t phy_data; 8018 DEBUGFUNC("em_set_d3_lplu_state"); 8019 8020 if (hw->phy_type != em_phy_igp && hw->phy_type != em_phy_igp_2 8021 && hw->phy_type != em_phy_igp_3) 8022 return E1000_SUCCESS; 8023 /* 8024 * During driver activity LPLU should not be used or it will attain 8025 * link from the lowest speeds starting from 10Mbps. The capability 8026 * is used for Dx transitions and states 8027 */ 8028 if (hw->mac_type == em_82541_rev_2 || hw->mac_type == em_82547_rev_2) { 8029 ret_val = em_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data); 8030 if (ret_val) 8031 return ret_val; 8032 } else if (hw->mac_type == em_ich8lan || 8033 hw->mac_type == em_ich9lan || 8034 hw->mac_type == em_ich10lan || 8035 hw->mac_type == em_pchlan || 8036 hw->mac_type == em_pch2lan) { 8037 /* 8038 * MAC writes into PHY register based on the state transition 8039 * and start auto-negotiation. SW driver can overwrite the 8040 * settings in CSR PHY power control E1000_PHY_CTRL register. 8041 */ 8042 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); 8043 } else { 8044 ret_val = em_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, 8045 &phy_data); 8046 if (ret_val) 8047 return ret_val; 8048 } 8049 8050 if (!active) { 8051 if (hw->mac_type == em_82541_rev_2 || 8052 hw->mac_type == em_82547_rev_2) { 8053 phy_data &= ~IGP01E1000_GMII_FLEX_SPD; 8054 ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO, 8055 phy_data); 8056 if (ret_val) 8057 return ret_val; 8058 } else { 8059 if (hw->mac_type == em_ich8lan || 8060 hw->mac_type == em_ich9lan || 8061 hw->mac_type == em_ich10lan || 8062 hw->mac_type == em_pchlan || 8063 hw->mac_type == em_pch2lan) { 8064 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; 8065 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 8066 } else { 8067 phy_data &= ~IGP02E1000_PM_D3_LPLU; 8068 ret_val = em_write_phy_reg(hw, 8069 IGP02E1000_PHY_POWER_MGMT, phy_data); 8070 if (ret_val) 8071 return ret_val; 8072 } 8073 } 8074 /* 8075 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 8076 * during Dx states where the power conservation is most 8077 * important. During driver activity we should enable 8078 * SmartSpeed, so performance is maintained. 8079 */ 8080 if (hw->smart_speed == em_smart_speed_on) { 8081 ret_val = em_read_phy_reg(hw, 8082 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 8083 if (ret_val) 8084 return ret_val; 8085 8086 phy_data |= IGP01E1000_PSCFR_SMART_SPEED; 8087 ret_val = em_write_phy_reg(hw, 8088 IGP01E1000_PHY_PORT_CONFIG, phy_data); 8089 if (ret_val) 8090 return ret_val; 8091 } else if (hw->smart_speed == em_smart_speed_off) { 8092 ret_val = em_read_phy_reg(hw, 8093 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 8094 if (ret_val) 8095 return ret_val; 8096 8097 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 8098 ret_val = em_write_phy_reg(hw, 8099 IGP01E1000_PHY_PORT_CONFIG, phy_data); 8100 if (ret_val) 8101 return ret_val; 8102 } 8103 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) 8104 || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) || 8105 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) { 8106 8107 if (hw->mac_type == em_82541_rev_2 || 8108 hw->mac_type == em_82547_rev_2) { 8109 phy_data |= IGP01E1000_GMII_FLEX_SPD; 8110 ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO, 8111 phy_data); 8112 if (ret_val) 8113 return ret_val; 8114 } else { 8115 if (hw->mac_type == em_ich8lan || 8116 hw->mac_type == em_ich9lan || 8117 hw->mac_type == em_ich10lan || 8118 hw->mac_type == em_pchlan || 8119 hw->mac_type == em_pch2lan) { 8120 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; 8121 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 8122 } else { 8123 phy_data |= IGP02E1000_PM_D3_LPLU; 8124 ret_val = em_write_phy_reg(hw, 8125 IGP02E1000_PHY_POWER_MGMT, phy_data); 8126 if (ret_val) 8127 return ret_val; 8128 } 8129 } 8130 8131 /* When LPLU is enabled we should disable SmartSpeed */ 8132 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 8133 &phy_data); 8134 if (ret_val) 8135 return ret_val; 8136 8137 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 8138 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 8139 phy_data); 8140 if (ret_val) 8141 return ret_val; 8142 8143 } 8144 return E1000_SUCCESS; 8145 } 8146 8147 /***************************************************************************** 8148 * 8149 * This function sets the lplu d0 state according to the active flag. When 8150 * activating lplu this function also disables smart speed and vise versa. 8151 * lplu will not be activated unless the device autonegotiation advertisement 8152 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. 8153 * hw: Struct containing variables accessed by shared code 8154 * active - true to enable lplu false to disable lplu. 8155 * 8156 * returns: - E1000_ERR_PHY if fail to read/write the PHY 8157 * E1000_SUCCESS at any other case. 8158 * 8159 ****************************************************************************/ 8160 STATIC int32_t 8161 em_set_d0_lplu_state(struct em_hw *hw, boolean_t active) 8162 { 8163 uint32_t phy_ctrl = 0; 8164 int32_t ret_val; 8165 uint16_t phy_data; 8166 DEBUGFUNC("em_set_d0_lplu_state"); 8167 8168 if (hw->mac_type <= em_82547_rev_2) 8169 return E1000_SUCCESS; 8170 8171 if (hw->mac_type == em_ich8lan || 8172 hw->mac_type == em_ich9lan || 8173 hw->mac_type == em_ich10lan || 8174 hw->mac_type == em_pchlan || 8175 hw->mac_type == em_pch2lan) { 8176 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); 8177 } else { 8178 ret_val = em_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, 8179 &phy_data); 8180 if (ret_val) 8181 return ret_val; 8182 } 8183 8184 if (!active) { 8185 if (hw->mac_type == em_ich8lan || 8186 hw->mac_type == em_ich9lan || 8187 hw->mac_type == em_ich10lan || 8188 hw->mac_type == em_pchlan || 8189 hw->mac_type == em_pch2lan) { 8190 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; 8191 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 8192 } else { 8193 phy_data &= ~IGP02E1000_PM_D0_LPLU; 8194 ret_val = em_write_phy_reg(hw, 8195 IGP02E1000_PHY_POWER_MGMT, phy_data); 8196 if (ret_val) 8197 return ret_val; 8198 } 8199 /* 8200 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 8201 * during Dx states where the power conservation is most 8202 * important. During driver activity we should enable 8203 * SmartSpeed, so performance is maintained. 8204 */ 8205 if (hw->smart_speed == em_smart_speed_on) { 8206 ret_val = em_read_phy_reg(hw, 8207 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 8208 if (ret_val) 8209 return ret_val; 8210 8211 phy_data |= IGP01E1000_PSCFR_SMART_SPEED; 8212 ret_val = em_write_phy_reg(hw, 8213 IGP01E1000_PHY_PORT_CONFIG, phy_data); 8214 if (ret_val) 8215 return ret_val; 8216 } else if (hw->smart_speed == em_smart_speed_off) { 8217 ret_val = em_read_phy_reg(hw, 8218 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 8219 if (ret_val) 8220 return ret_val; 8221 8222 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 8223 ret_val = em_write_phy_reg(hw, 8224 IGP01E1000_PHY_PORT_CONFIG, phy_data); 8225 if (ret_val) 8226 return ret_val; 8227 } 8228 } else { 8229 if (hw->mac_type == em_ich8lan || 8230 hw->mac_type == em_ich9lan || 8231 hw->mac_type == em_ich10lan || 8232 hw->mac_type == em_pchlan || 8233 hw->mac_type == em_pch2lan) { 8234 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; 8235 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 8236 } else { 8237 phy_data |= IGP02E1000_PM_D0_LPLU; 8238 ret_val = em_write_phy_reg(hw, 8239 IGP02E1000_PHY_POWER_MGMT, phy_data); 8240 if (ret_val) 8241 return ret_val; 8242 } 8243 8244 /* When LPLU is enabled we should disable SmartSpeed */ 8245 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 8246 &phy_data); 8247 if (ret_val) 8248 return ret_val; 8249 8250 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 8251 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 8252 phy_data); 8253 if (ret_val) 8254 return ret_val; 8255 8256 } 8257 return E1000_SUCCESS; 8258 } 8259 8260 /*************************************************************************** 8261 * Set Low Power Link Up state 8262 * 8263 * Sets the LPLU state according to the active flag. For PCH, if OEM write 8264 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set 8265 * the phy speed. This function will manually set the LPLU bit and restart 8266 * auto-neg as hw would do. D3 and D0 LPLU will call the same function 8267 * since it configures the same bit. 8268 ***************************************************************************/ 8269 int32_t 8270 em_set_lplu_state_pchlan(struct em_hw *hw, boolean_t active) 8271 { 8272 int32_t ret_val = E1000_SUCCESS; 8273 uint16_t oem_reg; 8274 8275 DEBUGFUNC("e1000_set_lplu_state_pchlan"); 8276 8277 ret_val = em_read_phy_reg(hw, HV_OEM_BITS, &oem_reg); 8278 if (ret_val) 8279 goto out; 8280 8281 if (active) 8282 oem_reg |= HV_OEM_BITS_LPLU; 8283 else 8284 oem_reg &= ~HV_OEM_BITS_LPLU; 8285 8286 oem_reg |= HV_OEM_BITS_RESTART_AN; 8287 ret_val = em_write_phy_reg(hw, HV_OEM_BITS, oem_reg); 8288 8289 out: 8290 return ret_val; 8291 } 8292 8293 /****************************************************************************** 8294 * Change VCO speed register to improve Bit Error Rate performance of SERDES. 8295 * 8296 * hw - Struct containing variables accessed by shared code 8297 *****************************************************************************/ 8298 static int32_t 8299 em_set_vco_speed(struct em_hw *hw) 8300 { 8301 int32_t ret_val; 8302 uint16_t default_page = 0; 8303 uint16_t phy_data; 8304 DEBUGFUNC("em_set_vco_speed"); 8305 8306 switch (hw->mac_type) { 8307 case em_82545_rev_3: 8308 case em_82546_rev_3: 8309 break; 8310 default: 8311 return E1000_SUCCESS; 8312 } 8313 8314 /* Set PHY register 30, page 5, bit 8 to 0 */ 8315 8316 ret_val = em_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page); 8317 if (ret_val) 8318 return ret_val; 8319 8320 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005); 8321 if (ret_val) 8322 return ret_val; 8323 8324 ret_val = em_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); 8325 if (ret_val) 8326 return ret_val; 8327 8328 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8; 8329 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); 8330 if (ret_val) 8331 return ret_val; 8332 8333 /* Set PHY register 30, page 4, bit 11 to 1 */ 8334 8335 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004); 8336 if (ret_val) 8337 return ret_val; 8338 8339 ret_val = em_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); 8340 if (ret_val) 8341 return ret_val; 8342 8343 phy_data |= M88E1000_PHY_VCO_REG_BIT11; 8344 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); 8345 if (ret_val) 8346 return ret_val; 8347 8348 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page); 8349 if (ret_val) 8350 return ret_val; 8351 8352 return E1000_SUCCESS; 8353 } 8354 8355 /***************************************************************************** 8356 * This function reads the cookie from ARC ram. 8357 * 8358 * returns: - E1000_SUCCESS . 8359 ****************************************************************************/ 8360 STATIC int32_t 8361 em_host_if_read_cookie(struct em_hw *hw, uint8_t *buffer) 8362 { 8363 uint8_t i; 8364 uint32_t offset = E1000_MNG_DHCP_COOKIE_OFFSET; 8365 uint8_t length = E1000_MNG_DHCP_COOKIE_LENGTH; 8366 length = (length >> 2); 8367 offset = (offset >> 2); 8368 8369 for (i = 0; i < length; i++) { 8370 *((uint32_t *) buffer + i) = 8371 E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i); 8372 } 8373 return E1000_SUCCESS; 8374 } 8375 8376 /***************************************************************************** 8377 * This function checks whether the HOST IF is enabled for command operaton 8378 * and also checks whether the previous command is completed. 8379 * It busy waits in case of previous command is not completed. 8380 * 8381 * returns: - E1000_ERR_HOST_INTERFACE_COMMAND in case if is not ready or 8382 * timeout 8383 * - E1000_SUCCESS for success. 8384 ****************************************************************************/ 8385 STATIC int32_t 8386 em_mng_enable_host_if(struct em_hw *hw) 8387 { 8388 uint32_t hicr; 8389 uint8_t i; 8390 /* Check that the host interface is enabled. */ 8391 hicr = E1000_READ_REG(hw, HICR); 8392 if ((hicr & E1000_HICR_EN) == 0) { 8393 DEBUGOUT("E1000_HOST_EN bit disabled.\n"); 8394 return -E1000_ERR_HOST_INTERFACE_COMMAND; 8395 } 8396 /* check the previous command is completed */ 8397 for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) { 8398 hicr = E1000_READ_REG(hw, HICR); 8399 if (!(hicr & E1000_HICR_C)) 8400 break; 8401 msec_delay_irq(1); 8402 } 8403 8404 if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) { 8405 DEBUGOUT("Previous command timeout failed .\n"); 8406 return -E1000_ERR_HOST_INTERFACE_COMMAND; 8407 } 8408 return E1000_SUCCESS; 8409 } 8410 8411 /***************************************************************************** 8412 * This function checks the mode of the firmware. 8413 * 8414 * returns - TRUE when the mode is IAMT or FALSE. 8415 ****************************************************************************/ 8416 boolean_t 8417 em_check_mng_mode(struct em_hw *hw) 8418 { 8419 uint32_t fwsm; 8420 fwsm = E1000_READ_REG(hw, FWSM); 8421 8422 if (hw->mac_type == em_ich8lan || 8423 hw->mac_type == em_ich9lan || 8424 hw->mac_type == em_ich10lan || 8425 hw->mac_type == em_pchlan || 8426 hw->mac_type == em_pch2lan) { 8427 if ((fwsm & E1000_FWSM_MODE_MASK) == 8428 (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) 8429 return TRUE; 8430 } else if ((fwsm & E1000_FWSM_MODE_MASK) == 8431 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) 8432 return TRUE; 8433 8434 return FALSE; 8435 } 8436 8437 /***************************************************************************** 8438 * This function calculates the checksum. 8439 * 8440 * returns - checksum of buffer contents. 8441 ****************************************************************************/ 8442 STATIC uint8_t 8443 em_calculate_mng_checksum(char *buffer, uint32_t length) 8444 { 8445 uint8_t sum = 0; 8446 uint32_t i; 8447 if (!buffer) 8448 return 0; 8449 8450 for (i = 0; i < length; i++) 8451 sum += buffer[i]; 8452 8453 return (uint8_t) (0 - sum); 8454 } 8455 8456 /***************************************************************************** 8457 * This function checks whether tx pkt filtering needs to be enabled or not. 8458 * 8459 * returns - TRUE for packet filtering or FALSE. 8460 ****************************************************************************/ 8461 boolean_t 8462 em_enable_tx_pkt_filtering(struct em_hw *hw) 8463 { 8464 /* called in init as well as watchdog timer functions */ 8465 int32_t ret_val, checksum; 8466 boolean_t tx_filter = FALSE; 8467 struct em_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie); 8468 uint8_t *buffer = (uint8_t *) & (hw->mng_cookie); 8469 if (em_check_mng_mode(hw)) { 8470 ret_val = em_mng_enable_host_if(hw); 8471 if (ret_val == E1000_SUCCESS) { 8472 ret_val = em_host_if_read_cookie(hw, buffer); 8473 if (ret_val == E1000_SUCCESS) { 8474 checksum = hdr->checksum; 8475 hdr->checksum = 0; 8476 if ((hdr->signature == E1000_IAMT_SIGNATURE) && 8477 checksum == em_calculate_mng_checksum( 8478 (char *) buffer, 8479 E1000_MNG_DHCP_COOKIE_LENGTH)) { 8480 if (hdr->status & 8481 E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT) 8482 tx_filter = TRUE; 8483 } else 8484 tx_filter = TRUE; 8485 } else 8486 tx_filter = TRUE; 8487 } 8488 } 8489 hw->tx_pkt_filtering = tx_filter; 8490 return tx_filter; 8491 } 8492 8493 static int32_t 8494 em_polarity_reversal_workaround(struct em_hw *hw) 8495 { 8496 int32_t ret_val; 8497 uint16_t mii_status_reg; 8498 uint16_t i; 8499 /* Polarity reversal workaround for forced 10F/10H links. */ 8500 8501 /* Disable the transmitter on the PHY */ 8502 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 8503 if (ret_val) 8504 return ret_val; 8505 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF); 8506 if (ret_val) 8507 return ret_val; 8508 8509 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 8510 if (ret_val) 8511 return ret_val; 8512 8513 /* This loop will early-out if the NO link condition has been met. */ 8514 for (i = PHY_FORCE_TIME; i > 0; i--) { 8515 /* 8516 * Read the MII Status Register and wait for Link Status bit 8517 * to be clear. 8518 */ 8519 8520 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 8521 if (ret_val) 8522 return ret_val; 8523 8524 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 8525 if (ret_val) 8526 return ret_val; 8527 8528 if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) 8529 break; 8530 msec_delay_irq(100); 8531 } 8532 8533 /* Recommended delay time after link has been lost */ 8534 msec_delay_irq(1000); 8535 8536 /* Now we will re-enable the transmitter on the PHY */ 8537 8538 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 8539 if (ret_val) 8540 return ret_val; 8541 msec_delay_irq(50); 8542 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0); 8543 if (ret_val) 8544 return ret_val; 8545 msec_delay_irq(50); 8546 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00); 8547 if (ret_val) 8548 return ret_val; 8549 msec_delay_irq(50); 8550 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000); 8551 if (ret_val) 8552 return ret_val; 8553 8554 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 8555 if (ret_val) 8556 return ret_val; 8557 8558 /* This loop will early-out if the link condition has been met. */ 8559 for (i = PHY_FORCE_TIME; i > 0; i--) { 8560 /* 8561 * Read the MII Status Register and wait for Link Status bit 8562 * to be set. 8563 */ 8564 8565 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 8566 if (ret_val) 8567 return ret_val; 8568 8569 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 8570 if (ret_val) 8571 return ret_val; 8572 8573 if (mii_status_reg & MII_SR_LINK_STATUS) 8574 break; 8575 msec_delay_irq(100); 8576 } 8577 return E1000_SUCCESS; 8578 } 8579 8580 /* 8581 * Set whether the PHY self-configures itself in hardware 8582 */ 8583 static void em_pch2lan_disable_hw_config(struct em_hw *hw, boolean_t sc) 8584 { 8585 uint32_t ctrl_ext; 8586 DEBUGFUNC("em_pch2lan_disable_hw_config"); 8587 8588 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 8589 8590 if (sc) 8591 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA; 8592 else 8593 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA; 8594 8595 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 8596 } 8597 8598 /****************************************************************************** 8599 * 8600 * Disables PCI-Express master access. 8601 * 8602 * hw: Struct containing variables accessed by shared code 8603 * 8604 * returns: - none. 8605 * 8606 *****************************************************************************/ 8607 STATIC void 8608 em_set_pci_express_master_disable(struct em_hw *hw) 8609 { 8610 uint32_t ctrl; 8611 DEBUGFUNC("em_set_pci_express_master_disable"); 8612 8613 if (hw->bus_type != em_bus_type_pci_express) 8614 return; 8615 8616 ctrl = E1000_READ_REG(hw, CTRL); 8617 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; 8618 E1000_WRITE_REG(hw, CTRL, ctrl); 8619 } 8620 8621 /****************************************************************************** 8622 * 8623 * Disables PCI-Express master access and verifies there are no pending 8624 * requests 8625 * 8626 * hw: Struct containing variables accessed by shared code 8627 * 8628 * returns: - E1000_ERR_MASTER_REQUESTS_PENDING if master disable bit hasn't 8629 * caused the master requests to be disabled. 8630 * E1000_SUCCESS master requests disabled. 8631 * 8632 ******************************************************************************/ 8633 int32_t 8634 em_disable_pciex_master(struct em_hw *hw) 8635 { 8636 int32_t timeout = MASTER_DISABLE_TIMEOUT; /* 80ms */ 8637 DEBUGFUNC("em_disable_pciex_master"); 8638 8639 if (hw->bus_type != em_bus_type_pci_express) 8640 return E1000_SUCCESS; 8641 8642 em_set_pci_express_master_disable(hw); 8643 8644 while (timeout) { 8645 if (!(E1000_READ_REG(hw, STATUS) & 8646 E1000_STATUS_GIO_MASTER_ENABLE)) 8647 break; 8648 else 8649 usec_delay(100); 8650 timeout--; 8651 } 8652 8653 if (!timeout) { 8654 DEBUGOUT("Master requests are pending.\n"); 8655 return -E1000_ERR_MASTER_REQUESTS_PENDING; 8656 } 8657 return E1000_SUCCESS; 8658 } 8659 8660 /****************************************************************************** 8661 * 8662 * Check for EEPROM Auto Read bit done. 8663 * 8664 * hw: Struct containing variables accessed by shared code 8665 * 8666 * returns: - E1000_ERR_RESET if fail to reset MAC 8667 * E1000_SUCCESS at any other case. 8668 * 8669 ******************************************************************************/ 8670 STATIC int32_t 8671 em_get_auto_rd_done(struct em_hw *hw) 8672 { 8673 int32_t timeout = AUTO_READ_DONE_TIMEOUT; 8674 DEBUGFUNC("em_get_auto_rd_done"); 8675 8676 switch (hw->mac_type) { 8677 default: 8678 msec_delay(5); 8679 break; 8680 case em_82571: 8681 case em_82572: 8682 case em_82573: 8683 case em_82574: 8684 case em_82575: 8685 case em_82580: 8686 case em_80003es2lan: 8687 case em_i350: 8688 case em_ich8lan: 8689 case em_ich9lan: 8690 case em_ich10lan: 8691 case em_pchlan: 8692 case em_pch2lan: 8693 while (timeout) { 8694 if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD) 8695 break; 8696 else 8697 msec_delay(1); 8698 timeout--; 8699 } 8700 8701 if (!timeout) { 8702 DEBUGOUT("Auto read by HW from EEPROM has not" 8703 " completed.\n"); 8704 return -E1000_ERR_RESET; 8705 } 8706 break; 8707 } 8708 /* 8709 * PHY configuration from NVM just starts after EECD_AUTO_RD sets to 8710 * high. Need to wait for PHY configuration completion before 8711 * accessing NVM and PHY. 8712 */ 8713 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) 8714 msec_delay(25); 8715 8716 return E1000_SUCCESS; 8717 } 8718 8719 /*************************************************************************** 8720 * Checks if the PHY configuration is done 8721 * 8722 * hw: Struct containing variables accessed by shared code 8723 * 8724 * returns: - E1000_ERR_RESET if fail to reset MAC 8725 * E1000_SUCCESS at any other case. 8726 * 8727 ***************************************************************************/ 8728 STATIC int32_t 8729 em_get_phy_cfg_done(struct em_hw *hw) 8730 { 8731 int32_t timeout = PHY_CFG_TIMEOUT; 8732 uint32_t cfg_mask = E1000_NVM_CFG_DONE_PORT_0; 8733 DEBUGFUNC("em_get_phy_cfg_done"); 8734 8735 switch (hw->mac_type) { 8736 default: 8737 msec_delay_irq(10); 8738 break; 8739 case em_80003es2lan: 8740 case em_82575: 8741 case em_82580: 8742 case em_i350: 8743 switch (hw->bus_func) { 8744 case 1: 8745 cfg_mask = E1000_NVM_CFG_DONE_PORT_1; 8746 break; 8747 case 2: 8748 cfg_mask = E1000_NVM_CFG_DONE_PORT_2; 8749 break; 8750 case 3: 8751 cfg_mask = E1000_NVM_CFG_DONE_PORT_3; 8752 break; 8753 } 8754 /* FALLTHROUGH */ 8755 case em_82571: 8756 case em_82572: 8757 while (timeout) { 8758 if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask) 8759 break; 8760 else 8761 msec_delay(1); 8762 timeout--; 8763 } 8764 if (!timeout) { 8765 DEBUGOUT("MNG configuration cycle has not completed." 8766 "\n"); 8767 } 8768 break; 8769 } 8770 8771 return E1000_SUCCESS; 8772 } 8773 8774 /*************************************************************************** 8775 * 8776 * Using the combination of SMBI and SWESMBI semaphore bits when resetting 8777 * adapter or Eeprom access. 8778 * 8779 * hw: Struct containing variables accessed by shared code 8780 * 8781 * returns: - E1000_ERR_EEPROM if fail to access EEPROM. 8782 * E1000_SUCCESS at any other case. 8783 * 8784 ***************************************************************************/ 8785 STATIC int32_t 8786 em_get_hw_eeprom_semaphore(struct em_hw *hw) 8787 { 8788 int32_t timeout; 8789 uint32_t swsm; 8790 DEBUGFUNC("em_get_hw_eeprom_semaphore"); 8791 8792 if (!hw->eeprom_semaphore_present) 8793 return E1000_SUCCESS; 8794 8795 if (hw->mac_type == em_80003es2lan) { 8796 /* Get the SW semaphore. */ 8797 if (em_get_software_semaphore(hw) != E1000_SUCCESS) 8798 return -E1000_ERR_EEPROM; 8799 } 8800 /* Get the FW semaphore. */ 8801 timeout = hw->eeprom.word_size + 1; 8802 while (timeout) { 8803 swsm = E1000_READ_REG(hw, SWSM); 8804 swsm |= E1000_SWSM_SWESMBI; 8805 E1000_WRITE_REG(hw, SWSM, swsm); 8806 /* if we managed to set the bit we got the semaphore. */ 8807 swsm = E1000_READ_REG(hw, SWSM); 8808 if (swsm & E1000_SWSM_SWESMBI) 8809 break; 8810 8811 usec_delay(50); 8812 timeout--; 8813 } 8814 8815 if (!timeout) { 8816 /* Release semaphores */ 8817 em_put_hw_eeprom_semaphore(hw); 8818 DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set." 8819 "\n"); 8820 return -E1000_ERR_EEPROM; 8821 } 8822 return E1000_SUCCESS; 8823 } 8824 8825 /*************************************************************************** 8826 * This function clears HW semaphore bits. 8827 * 8828 * hw: Struct containing variables accessed by shared code 8829 * 8830 * returns: - None. 8831 * 8832 ***************************************************************************/ 8833 STATIC void 8834 em_put_hw_eeprom_semaphore(struct em_hw *hw) 8835 { 8836 uint32_t swsm; 8837 DEBUGFUNC("em_put_hw_eeprom_semaphore"); 8838 8839 if (!hw->eeprom_semaphore_present) 8840 return; 8841 8842 swsm = E1000_READ_REG(hw, SWSM); 8843 if (hw->mac_type == em_80003es2lan) { 8844 /* Release both semaphores. */ 8845 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 8846 } else 8847 swsm &= ~(E1000_SWSM_SWESMBI); 8848 E1000_WRITE_REG(hw, SWSM, swsm); 8849 } 8850 8851 /*************************************************************************** 8852 * 8853 * Obtaining software semaphore bit (SMBI) before resetting PHY. 8854 * 8855 * hw: Struct containing variables accessed by shared code 8856 * 8857 * returns: - E1000_ERR_RESET if fail to obtain semaphore. 8858 * E1000_SUCCESS at any other case. 8859 * 8860 ***************************************************************************/ 8861 STATIC int32_t 8862 em_get_software_semaphore(struct em_hw *hw) 8863 { 8864 int32_t timeout = hw->eeprom.word_size + 1; 8865 uint32_t swsm; 8866 DEBUGFUNC("em_get_software_semaphore"); 8867 8868 if (hw->mac_type != em_80003es2lan) 8869 return E1000_SUCCESS; 8870 8871 while (timeout) { 8872 swsm = E1000_READ_REG(hw, SWSM); 8873 /* 8874 * If SMBI bit cleared, it is now set and we hold the 8875 * semaphore 8876 */ 8877 if (!(swsm & E1000_SWSM_SMBI)) 8878 break; 8879 msec_delay_irq(1); 8880 timeout--; 8881 } 8882 8883 if (!timeout) { 8884 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 8885 return -E1000_ERR_RESET; 8886 } 8887 return E1000_SUCCESS; 8888 } 8889 8890 /*************************************************************************** 8891 * 8892 * Release semaphore bit (SMBI). 8893 * 8894 * hw: Struct containing variables accessed by shared code 8895 * 8896 ***************************************************************************/ 8897 STATIC void 8898 em_release_software_semaphore(struct em_hw *hw) 8899 { 8900 uint32_t swsm; 8901 DEBUGFUNC("em_release_software_semaphore"); 8902 8903 if (hw->mac_type != em_80003es2lan) 8904 return; 8905 8906 swsm = E1000_READ_REG(hw, SWSM); 8907 /* Release the SW semaphores. */ 8908 swsm &= ~E1000_SWSM_SMBI; 8909 E1000_WRITE_REG(hw, SWSM, swsm); 8910 } 8911 8912 /****************************************************************************** 8913 * Checks if PHY reset is blocked due to SOL/IDER session, for example. 8914 * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to 8915 * the caller to figure out how to deal with it. 8916 * 8917 * hw - Struct containing variables accessed by shared code 8918 * 8919 * returns: - E1000_BLK_PHY_RESET 8920 * E1000_SUCCESS 8921 * 8922 *****************************************************************************/ 8923 int32_t 8924 em_check_phy_reset_block(struct em_hw *hw) 8925 { 8926 uint32_t manc = 0; 8927 uint32_t fwsm = 0; 8928 if (hw->mac_type == em_ich8lan || 8929 hw->mac_type == em_ich9lan || 8930 hw->mac_type == em_ich10lan || 8931 hw->mac_type == em_pchlan || 8932 hw->mac_type == em_pch2lan) { 8933 fwsm = E1000_READ_REG(hw, FWSM); 8934 return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS : 8935 E1000_BLK_PHY_RESET; 8936 } 8937 if (hw->mac_type > em_82547_rev_2) 8938 manc = E1000_READ_REG(hw, MANC); 8939 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? 8940 E1000_BLK_PHY_RESET : E1000_SUCCESS; 8941 } 8942 8943 /****************************************************************************** 8944 * Configure PCI-Ex no-snoop 8945 * 8946 * hw - Struct containing variables accessed by shared code. 8947 * no_snoop - Bitmap of no-snoop events. 8948 * 8949 * returns: E1000_SUCCESS 8950 * 8951 *****************************************************************************/ 8952 STATIC int32_t 8953 em_set_pci_ex_no_snoop(struct em_hw *hw, uint32_t no_snoop) 8954 { 8955 uint32_t gcr_reg = 0; 8956 DEBUGFUNC("em_set_pci_ex_no_snoop"); 8957 8958 if (hw->bus_type == em_bus_type_unknown) 8959 em_get_bus_info(hw); 8960 8961 if (hw->bus_type != em_bus_type_pci_express) 8962 return E1000_SUCCESS; 8963 8964 if (no_snoop) { 8965 gcr_reg = E1000_READ_REG(hw, GCR); 8966 gcr_reg &= ~(PCI_EX_NO_SNOOP_ALL); 8967 gcr_reg |= no_snoop; 8968 E1000_WRITE_REG(hw, GCR, gcr_reg); 8969 } 8970 if (hw->mac_type == em_ich8lan || 8971 hw->mac_type == em_ich9lan || 8972 hw->mac_type == em_ich10lan || 8973 hw->mac_type == em_pchlan || 8974 hw->mac_type == em_pch2lan) { 8975 uint32_t ctrl_ext; 8976 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 8977 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 8978 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 8979 } 8980 return E1000_SUCCESS; 8981 } 8982 8983 /*************************************************************************** 8984 * 8985 * Get software semaphore FLAG bit (SWFLAG). 8986 * SWFLAG is used to synchronize the access to all shared resource between 8987 * SW, FW and HW. 8988 * 8989 * hw: Struct containing variables accessed by shared code 8990 * 8991 ***************************************************************************/ 8992 STATIC int32_t 8993 em_get_software_flag(struct em_hw *hw) 8994 { 8995 int32_t timeout = PHY_CFG_TIMEOUT; 8996 uint32_t extcnf_ctrl; 8997 DEBUGFUNC("em_get_software_flag"); 8998 8999 if (hw->mac_type == em_ich8lan || 9000 hw->mac_type == em_ich9lan || 9001 hw->mac_type == em_ich10lan || 9002 hw->mac_type == em_pchlan || 9003 hw->mac_type == em_pch2lan) { 9004 while (timeout) { 9005 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 9006 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; 9007 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); 9008 9009 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 9010 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) 9011 break; 9012 msec_delay_irq(1); 9013 timeout--; 9014 } 9015 9016 if (!timeout) { 9017 DEBUGOUT("FW or HW locks the resource too long.\n"); 9018 return -E1000_ERR_CONFIG; 9019 } 9020 } 9021 return E1000_SUCCESS; 9022 } 9023 9024 /*************************************************************************** 9025 * 9026 * Release software semaphore FLAG bit (SWFLAG). 9027 * SWFLAG is used to synchronize the access to all shared resource between 9028 * SW, FW and HW. 9029 * 9030 * hw: Struct containing variables accessed by shared code 9031 * 9032 ***************************************************************************/ 9033 STATIC void 9034 em_release_software_flag(struct em_hw *hw) 9035 { 9036 uint32_t extcnf_ctrl; 9037 DEBUGFUNC("em_release_software_flag"); 9038 9039 if (hw->mac_type == em_ich8lan || 9040 hw->mac_type == em_ich9lan || 9041 hw->mac_type == em_ich10lan || 9042 hw->mac_type == em_pchlan || 9043 hw->mac_type == em_pch2lan) { 9044 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 9045 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 9046 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); 9047 } 9048 return; 9049 } 9050 9051 /****************************************************************************** 9052 * Reads a 16 bit word or words from the EEPROM using the ICH8's flash access 9053 * register. 9054 * 9055 * hw - Struct containing variables accessed by shared code 9056 * offset - offset of word in the EEPROM to read 9057 * data - word read from the EEPROM 9058 * words - number of words to read 9059 *****************************************************************************/ 9060 STATIC int32_t 9061 em_read_eeprom_ich8(struct em_hw *hw, uint16_t offset, uint16_t words, 9062 uint16_t *data) 9063 { 9064 int32_t error = E1000_SUCCESS; 9065 uint32_t flash_bank = 0; 9066 uint32_t act_offset = 0; 9067 uint32_t bank_offset = 0; 9068 uint16_t word = 0; 9069 uint16_t i = 0; 9070 /* 9071 * We need to know which is the valid flash bank. In the event that 9072 * we didn't allocate eeprom_shadow_ram, we may not be managing 9073 * flash_bank. So it cannot be trusted and needs to be updated with 9074 * each read. 9075 */ 9076 /* Value of bit 22 corresponds to the flash bank we're on. */ 9077 flash_bank = (E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL) ? 1 : 0; 9078 /* 9079 * Adjust offset appropriately if we're on bank 1 - adjust for word 9080 * size 9081 */ 9082 bank_offset = flash_bank * (hw->flash_bank_size * 2); 9083 9084 error = em_get_software_flag(hw); 9085 if (error != E1000_SUCCESS) 9086 return error; 9087 9088 for (i = 0; i < words; i++) { 9089 if (hw->eeprom_shadow_ram != NULL && 9090 hw->eeprom_shadow_ram[offset + i].modified == TRUE) { 9091 data[i] = 9092 hw->eeprom_shadow_ram[offset + i].eeprom_word; 9093 } else { 9094 /* The NVM part needs a byte offset, hence * 2 */ 9095 act_offset = bank_offset + ((offset + i) * 2); 9096 error = em_read_ich8_word(hw, act_offset, &word); 9097 if (error != E1000_SUCCESS) 9098 break; 9099 data[i] = word; 9100 } 9101 } 9102 9103 em_release_software_flag(hw); 9104 9105 return error; 9106 } 9107 9108 /****************************************************************************** 9109 * Writes a 16 bit word or words to the EEPROM using the ICH8's flash access 9110 * register. Actually, writes are written to the shadow ram cache in the hw 9111 * structure hw->em_shadow_ram. em_commit_shadow_ram flushes this to 9112 * the NVM, which occurs when the NVM checksum is updated. 9113 * 9114 * hw - Struct containing variables accessed by shared code 9115 * offset - offset of word in the EEPROM to write 9116 * words - number of words to write 9117 * data - words to write to the EEPROM 9118 *****************************************************************************/ 9119 STATIC int32_t 9120 em_write_eeprom_ich8(struct em_hw *hw, uint16_t offset, uint16_t words, 9121 uint16_t *data) 9122 { 9123 uint32_t i = 0; 9124 int32_t error = E1000_SUCCESS; 9125 error = em_get_software_flag(hw); 9126 if (error != E1000_SUCCESS) 9127 return error; 9128 /* 9129 * A driver can write to the NVM only if it has eeprom_shadow_ram 9130 * allocated. Subsequent reads to the modified words are read from 9131 * this cached structure as well. Writes will only go into this 9132 * cached structure unless it's followed by a call to 9133 * em_update_eeprom_checksum() where it will commit the changes and 9134 * clear the "modified" field. 9135 */ 9136 if (hw->eeprom_shadow_ram != NULL) { 9137 for (i = 0; i < words; i++) { 9138 if ((offset + i) < E1000_SHADOW_RAM_WORDS) { 9139 hw->eeprom_shadow_ram[offset + i].modified = 9140 TRUE; 9141 hw->eeprom_shadow_ram[offset + i].eeprom_word = 9142 data[i]; 9143 } else { 9144 error = -E1000_ERR_EEPROM; 9145 break; 9146 } 9147 } 9148 } else { 9149 /* 9150 * Drivers have the option to not allocate eeprom_shadow_ram 9151 * as long as they don't perform any NVM writes. An attempt 9152 * in doing so will result in this error. 9153 */ 9154 error = -E1000_ERR_EEPROM; 9155 } 9156 9157 em_release_software_flag(hw); 9158 9159 return error; 9160 } 9161 9162 /****************************************************************************** 9163 * This function does initial flash setup so that a new read/write/erase cycle 9164 * can be started. 9165 * 9166 * hw - The pointer to the hw structure 9167 ****************************************************************************/ 9168 STATIC int32_t 9169 em_ich8_cycle_init(struct em_hw *hw) 9170 { 9171 union ich8_hws_flash_status hsfsts; 9172 int32_t error = E1000_ERR_EEPROM; 9173 int32_t i = 0; 9174 DEBUGFUNC("em_ich8_cycle_init"); 9175 9176 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 9177 9178 /* May be check the Flash Des Valid bit in Hw status */ 9179 if (hsfsts.hsf_status.fldesvalid == 0) { 9180 DEBUGOUT("Flash descriptor invalid. SW Sequencing must be" 9181 " used."); 9182 return error; 9183 } 9184 /* Clear FCERR in Hw status by writing 1 */ 9185 /* Clear DAEL in Hw status by writing a 1 */ 9186 hsfsts.hsf_status.flcerr = 1; 9187 hsfsts.hsf_status.dael = 1; 9188 9189 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval); 9190 /* 9191 * Either we should have a hardware SPI cycle in progress bit to 9192 * check against, in order to start a new cycle or FDONE bit should 9193 * be changed in the hardware so that it is 1 after harware reset, 9194 * which can then be used as an indication whether a cycle is in 9195 * progress or has been completed .. we should also have some 9196 * software semaphore mechanism to guard FDONE or the cycle in 9197 * progress bit so that two threads access to those bits can be 9198 * sequentiallized or a way so that 2 threads dont start the cycle at 9199 * the same time 9200 */ 9201 9202 if (hsfsts.hsf_status.flcinprog == 0) { 9203 /* 9204 * There is no cycle running at present, so we can start a 9205 * cycle 9206 */ 9207 /* Begin by setting Flash Cycle Done. */ 9208 hsfsts.hsf_status.flcdone = 1; 9209 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, 9210 hsfsts.regval); 9211 error = E1000_SUCCESS; 9212 } else { 9213 /* 9214 * otherwise poll for sometime so the current cycle has a 9215 * chance to end before giving up. 9216 */ 9217 for (i = 0; i < ICH_FLASH_COMMAND_TIMEOUT; i++) { 9218 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, 9219 ICH_FLASH_HSFSTS); 9220 if (hsfsts.hsf_status.flcinprog == 0) { 9221 error = E1000_SUCCESS; 9222 break; 9223 } 9224 usec_delay(1); 9225 } 9226 if (error == E1000_SUCCESS) { 9227 /* 9228 * Successful in waiting for previous cycle to 9229 * timeout, now set the Flash Cycle Done. 9230 */ 9231 hsfsts.hsf_status.flcdone = 1; 9232 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, 9233 hsfsts.regval); 9234 } else { 9235 DEBUGOUT("Flash controller busy, cannot get access"); 9236 } 9237 } 9238 return error; 9239 } 9240 9241 /****************************************************************************** 9242 * This function starts a flash cycle and waits for its completion 9243 * 9244 * hw - The pointer to the hw structure 9245 *****************************************************************************/ 9246 STATIC int32_t 9247 em_ich8_flash_cycle(struct em_hw *hw, uint32_t timeout) 9248 { 9249 union ich8_hws_flash_ctrl hsflctl; 9250 union ich8_hws_flash_status hsfsts; 9251 int32_t error = E1000_ERR_EEPROM; 9252 uint32_t i = 0; 9253 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ 9254 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL); 9255 hsflctl.hsf_ctrl.flcgo = 1; 9256 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); 9257 9258 /* wait till FDONE bit is set to 1 */ 9259 do { 9260 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, 9261 ICH_FLASH_HSFSTS); 9262 if (hsfsts.hsf_status.flcdone == 1) 9263 break; 9264 usec_delay(1); 9265 i++; 9266 } while (i < timeout); 9267 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) { 9268 error = E1000_SUCCESS; 9269 } 9270 return error; 9271 } 9272 9273 /****************************************************************************** 9274 * Reads a byte or word from the NVM using the ICH8 flash access registers. 9275 * 9276 * hw - The pointer to the hw structure 9277 * index - The index of the byte or word to read. 9278 * size - Size of data to read, 1=byte 2=word 9279 * data - Pointer to the word to store the value read. 9280 *****************************************************************************/ 9281 STATIC int32_t 9282 em_read_ich8_data(struct em_hw *hw, uint32_t index, uint32_t size, 9283 uint16_t *data) 9284 { 9285 union ich8_hws_flash_status hsfsts; 9286 union ich8_hws_flash_ctrl hsflctl; 9287 uint32_t flash_linear_address; 9288 uint32_t flash_data = 0; 9289 int32_t error = -E1000_ERR_EEPROM; 9290 int32_t count = 0; 9291 DEBUGFUNC("em_read_ich8_data"); 9292 9293 if (size < 1 || size > 2 || data == 0x0 || 9294 index > ICH_FLASH_LINEAR_ADDR_MASK) 9295 return error; 9296 9297 flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) + 9298 hw->flash_base_addr; 9299 9300 do { 9301 usec_delay(1); 9302 /* Steps */ 9303 error = em_ich8_cycle_init(hw); 9304 if (error != E1000_SUCCESS) 9305 break; 9306 9307 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, 9308 ICH_FLASH_HSFCTL); 9309 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 9310 hsflctl.hsf_ctrl.fldbcount = size - 1; 9311 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; 9312 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, 9313 hsflctl.regval); 9314 /* 9315 * Write the last 24 bits of index into Flash Linear address 9316 * field in Flash Address 9317 */ 9318 /* TODO: TBD maybe check the index against the size of flash */ 9319 9320 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, 9321 flash_linear_address); 9322 9323 error = em_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT); 9324 /* 9325 * Check if FCERR is set to 1, if set to 1, clear it and try 9326 * the whole sequence a few more times, else read in (shift 9327 * in) the Flash Data0, the order is least significant byte 9328 * first msb to lsb 9329 */ 9330 if (error == E1000_SUCCESS) { 9331 flash_data = E1000_READ_ICH_FLASH_REG(hw, 9332 ICH_FLASH_FDATA0); 9333 if (size == 1) { 9334 *data = (uint8_t) (flash_data & 0x000000FF); 9335 } else if (size == 2) { 9336 *data = (uint16_t) (flash_data & 0x0000FFFF); 9337 } 9338 break; 9339 } else { 9340 /* 9341 * If we've gotten here, then things are probably 9342 * completely hosed, but if the error condition is 9343 * detected, it won't hurt to give it another 9344 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 9345 */ 9346 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, 9347 ICH_FLASH_HSFSTS); 9348 if (hsfsts.hsf_status.flcerr == 1) { 9349 /* Repeat for some time before giving up. */ 9350 continue; 9351 } else if (hsfsts.hsf_status.flcdone == 0) { 9352 DEBUGOUT("Timeout error - flash cycle did not" 9353 " complete."); 9354 break; 9355 } 9356 } 9357 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 9358 9359 return error; 9360 } 9361 9362 /****************************************************************************** 9363 * Writes One /two bytes to the NVM using the ICH8 flash access registers. 9364 * 9365 * hw - The pointer to the hw structure 9366 * index - The index of the byte/word to read. 9367 * size - Size of data to read, 1=byte 2=word 9368 * data - The byte(s) to write to the NVM. 9369 *****************************************************************************/ 9370 STATIC int32_t 9371 em_write_ich8_data(struct em_hw *hw, uint32_t index, uint32_t size, 9372 uint16_t data) 9373 { 9374 union ich8_hws_flash_status hsfsts; 9375 union ich8_hws_flash_ctrl hsflctl; 9376 uint32_t flash_linear_address; 9377 uint32_t flash_data = 0; 9378 int32_t error = -E1000_ERR_EEPROM; 9379 int32_t count = 0; 9380 DEBUGFUNC("em_write_ich8_data"); 9381 9382 if (size < 1 || size > 2 || data > size * 0xff || 9383 index > ICH_FLASH_LINEAR_ADDR_MASK) 9384 return error; 9385 9386 flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) + 9387 hw->flash_base_addr; 9388 9389 do { 9390 usec_delay(1); 9391 /* Steps */ 9392 error = em_ich8_cycle_init(hw); 9393 if (error != E1000_SUCCESS) 9394 break; 9395 9396 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, 9397 ICH_FLASH_HSFCTL); 9398 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 9399 hsflctl.hsf_ctrl.fldbcount = size - 1; 9400 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; 9401 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, 9402 hsflctl.regval); 9403 /* 9404 * Write the last 24 bits of index into Flash Linear address 9405 * field in Flash Address 9406 */ 9407 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, 9408 flash_linear_address); 9409 9410 if (size == 1) 9411 flash_data = (uint32_t) data & 0x00FF; 9412 else 9413 flash_data = (uint32_t) data; 9414 9415 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data); 9416 /* 9417 * check if FCERR is set to 1 , if set to 1, clear it and try 9418 * the whole sequence a few more times else done 9419 */ 9420 error = em_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT); 9421 if (error == E1000_SUCCESS) { 9422 break; 9423 } else { 9424 /* 9425 * If we're here, then things are most likely 9426 * completely hosed, but if the error condition is 9427 * detected, it won't hurt to give it another 9428 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 9429 */ 9430 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, 9431 ICH_FLASH_HSFSTS); 9432 if (hsfsts.hsf_status.flcerr == 1) { 9433 /* Repeat for some time before giving up. */ 9434 continue; 9435 } else if (hsfsts.hsf_status.flcdone == 0) { 9436 DEBUGOUT("Timeout error - flash cycle did not" 9437 " complete."); 9438 break; 9439 } 9440 } 9441 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 9442 9443 return error; 9444 } 9445 9446 /****************************************************************************** 9447 * Reads a single byte from the NVM using the ICH8 flash access registers. 9448 * 9449 * hw - pointer to em_hw structure 9450 * index - The index of the byte to read. 9451 * data - Pointer to a byte to store the value read. 9452 *****************************************************************************/ 9453 STATIC int32_t 9454 em_read_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t *data) 9455 { 9456 int32_t status = E1000_SUCCESS; 9457 uint16_t word = 0; 9458 status = em_read_ich8_data(hw, index, 1, &word); 9459 if (status == E1000_SUCCESS) { 9460 *data = (uint8_t) word; 9461 } 9462 return status; 9463 } 9464 9465 /****************************************************************************** 9466 * Writes a single byte to the NVM using the ICH8 flash access registers. 9467 * Performs verification by reading back the value and then going through 9468 * a retry algorithm before giving up. 9469 * 9470 * hw - pointer to em_hw structure 9471 * index - The index of the byte to write. 9472 * byte - The byte to write to the NVM. 9473 *****************************************************************************/ 9474 STATIC int32_t 9475 em_verify_write_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t byte) 9476 { 9477 int32_t error = E1000_SUCCESS; 9478 int32_t program_retries = 0; 9479 DEBUGOUT2("Byte := %2.2X Offset := %d\n", byte, index); 9480 9481 error = em_write_ich8_byte(hw, index, byte); 9482 9483 if (error != E1000_SUCCESS) { 9484 for (program_retries = 0; program_retries < 100; 9485 program_retries++) { 9486 DEBUGOUT2("Retrying \t Byte := %2.2X Offset := %d\n", 9487 byte, index); 9488 error = em_write_ich8_byte(hw, index, byte); 9489 usec_delay(100); 9490 if (error == E1000_SUCCESS) 9491 break; 9492 } 9493 } 9494 if (program_retries == 100) 9495 error = E1000_ERR_EEPROM; 9496 9497 return error; 9498 } 9499 9500 /****************************************************************************** 9501 * Writes a single byte to the NVM using the ICH8 flash access registers. 9502 * 9503 * hw - pointer to em_hw structure 9504 * index - The index of the byte to read. 9505 * data - The byte to write to the NVM. 9506 *****************************************************************************/ 9507 STATIC int32_t 9508 em_write_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t data) 9509 { 9510 int32_t status = E1000_SUCCESS; 9511 uint16_t word = (uint16_t) data; 9512 status = em_write_ich8_data(hw, index, 1, word); 9513 9514 return status; 9515 } 9516 9517 /****************************************************************************** 9518 * Reads a word from the NVM using the ICH8 flash access registers. 9519 * 9520 * hw - pointer to em_hw structure 9521 * index - The starting byte index of the word to read. 9522 * data - Pointer to a word to store the value read. 9523 *****************************************************************************/ 9524 STATIC int32_t 9525 em_read_ich8_word(struct em_hw *hw, uint32_t index, uint16_t *data) 9526 { 9527 int32_t status = E1000_SUCCESS; 9528 status = em_read_ich8_data(hw, index, 2, data); 9529 return status; 9530 } 9531 9532 /****************************************************************************** 9533 * Erases the bank specified. Each bank may be a 4, 8 or 64k block. Banks are 0 9534 * based. 9535 * 9536 * hw - pointer to em_hw structure 9537 * bank - 0 for first bank, 1 for second bank 9538 * 9539 * Note that this function may actually erase as much as 8 or 64 KBytes. The 9540 * amount of NVM used in each bank is a *minimum* of 4 KBytes, but in fact the 9541 * bank size may be 4, 8 or 64 KBytes 9542 *****************************************************************************/ 9543 int32_t 9544 em_erase_ich8_4k_segment(struct em_hw *hw, uint32_t bank) 9545 { 9546 union ich8_hws_flash_status hsfsts; 9547 union ich8_hws_flash_ctrl hsflctl; 9548 uint32_t flash_linear_address; 9549 int32_t count = 0; 9550 int32_t error = E1000_ERR_EEPROM; 9551 int32_t iteration; 9552 int32_t sub_sector_size = 0; 9553 int32_t bank_size; 9554 int32_t j = 0; 9555 int32_t error_flag = 0; 9556 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 9557 /* 9558 * Determine HW Sector size: Read BERASE bits of Hw flash Status 9559 * register 9560 */ 9561 /* 9562 * 00: The Hw sector is 256 bytes, hence we need to erase 16 9563 * consecutive sectors. The start index for the nth Hw sector can be 9564 * calculated as bank * 4096 + n * 256 01: The Hw sector is 4K bytes, 9565 * hence we need to erase 1 sector. The start index for the nth Hw 9566 * sector can be calculated as bank * 4096 10: The HW sector is 8K 9567 * bytes 11: The Hw sector size is 64K bytes 9568 */ 9569 if (hsfsts.hsf_status.berasesz == 0x0) { 9570 /* Hw sector size 256 */ 9571 sub_sector_size = ICH_FLASH_SEG_SIZE_256; 9572 bank_size = ICH_FLASH_SECTOR_SIZE; 9573 iteration = ICH_FLASH_SECTOR_SIZE / ICH_FLASH_SEG_SIZE_256; 9574 } else if (hsfsts.hsf_status.berasesz == 0x1) { 9575 bank_size = ICH_FLASH_SEG_SIZE_4K; 9576 iteration = 1; 9577 } else if (hsfsts.hsf_status.berasesz == 0x2) { 9578 if (hw->mac_type == em_ich9lan) { 9579 uint32_t gfpreg, sector_base_addr, sector_end_addr; 9580 gfpreg = E1000_READ_ICH_FLASH_REG(hw, 9581 ICH_FLASH_GFPREG); 9582 /* 9583 * sector_X_addr is a "sector"-aligned address (4096 bytes) 9584 * Add 1 to sector_end_addr since this sector is included in 9585 * the overall size. 9586 */ 9587 sector_base_addr = gfpreg & ICH_GFPREG_BASE_MASK; 9588 sector_end_addr = 9589 ((gfpreg >> 16) & ICH_GFPREG_BASE_MASK) + 1; 9590 9591 /* 9592 * find total size of the NVM, then cut in half since the total 9593 * size represents two separate NVM banks. 9594 */ 9595 bank_size = (sector_end_addr - sector_base_addr) 9596 << ICH_FLASH_SECT_ADDR_SHIFT; 9597 bank_size /= 2; 9598 /* Word align */ 9599 bank_size = 9600 (bank_size / sizeof(uint16_t)) * sizeof(uint16_t); 9601 9602 sub_sector_size = ICH_FLASH_SEG_SIZE_8K; 9603 iteration = bank_size / ICH_FLASH_SEG_SIZE_8K; 9604 } else { 9605 return error; 9606 } 9607 } else if (hsfsts.hsf_status.berasesz == 0x3) { 9608 bank_size = ICH_FLASH_SEG_SIZE_64K; 9609 iteration = 1; 9610 } else { 9611 return error; 9612 } 9613 9614 for (j = 0; j < iteration; j++) { 9615 do { 9616 count++; 9617 /* Steps */ 9618 error = em_ich8_cycle_init(hw); 9619 if (error != E1000_SUCCESS) { 9620 error_flag = 1; 9621 break; 9622 } 9623 /* 9624 * Write a value 11 (block Erase) in Flash Cycle 9625 * field in Hw flash Control 9626 */ 9627 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, 9628 ICH_FLASH_HSFCTL); 9629 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE; 9630 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, 9631 hsflctl.regval); 9632 /* 9633 * Write the last 24 bits of an index within the 9634 * block into Flash Linear address field in Flash 9635 * Address. This probably needs to be calculated 9636 * here based off the on-chip erase sector size and 9637 * the software bank size (4, 8 or 64 KBytes) 9638 */ 9639 flash_linear_address = 9640 bank * bank_size + j * sub_sector_size; 9641 flash_linear_address += hw->flash_base_addr; 9642 flash_linear_address &= ICH_FLASH_LINEAR_ADDR_MASK; 9643 9644 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, 9645 flash_linear_address); 9646 9647 error = 9648 em_ich8_flash_cycle(hw, ICH_FLASH_ERASE_TIMEOUT); 9649 /* 9650 * Check if FCERR is set to 1. If 1, clear it and 9651 * try the whole sequence a few more times else Done 9652 */ 9653 if (error == E1000_SUCCESS) { 9654 break; 9655 } else { 9656 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, 9657 ICH_FLASH_HSFSTS); 9658 if (hsfsts.hsf_status.flcerr == 1) { 9659 /* 9660 * repeat for some time before giving 9661 * up 9662 */ 9663 continue; 9664 } else if (hsfsts.hsf_status.flcdone == 0) { 9665 error_flag = 1; 9666 break; 9667 } 9668 } 9669 } while ((count < ICH_FLASH_CYCLE_REPEAT_COUNT) && !error_flag); 9670 if (error_flag == 1) 9671 break; 9672 } 9673 if (error_flag != 1) 9674 error = E1000_SUCCESS; 9675 return error; 9676 } 9677 9678 STATIC int32_t 9679 em_init_lcd_from_nvm_config_region(struct em_hw *hw, uint32_t cnf_base_addr, 9680 uint32_t cnf_size) 9681 { 9682 uint32_t ret_val = E1000_SUCCESS; 9683 uint16_t word_addr, reg_data, reg_addr; 9684 uint16_t i; 9685 /* cnf_base_addr is in DWORD */ 9686 word_addr = (uint16_t) (cnf_base_addr << 1); 9687 9688 /* cnf_size is returned in size of dwords */ 9689 for (i = 0; i < cnf_size; i++) { 9690 ret_val = 9691 em_read_eeprom(hw, (word_addr + i * 2), 1, ®_data); 9692 if (ret_val) 9693 return ret_val; 9694 9695 ret_val = 9696 em_read_eeprom(hw, (word_addr + i * 2 + 1), 1, ®_addr); 9697 if (ret_val) 9698 return ret_val; 9699 9700 ret_val = em_get_software_flag(hw); 9701 if (ret_val != E1000_SUCCESS) 9702 return ret_val; 9703 9704 ret_val = 9705 em_write_phy_reg_ex(hw, (uint32_t) reg_addr, reg_data); 9706 9707 em_release_software_flag(hw); 9708 } 9709 9710 return ret_val; 9711 } 9712 9713 /****************************************************************************** 9714 * This function initializes the PHY from the NVM on ICH8 platforms. This 9715 * is needed due to an issue where the NVM configuration is not properly 9716 * autoloaded after power transitions. Therefore, after each PHY reset, we 9717 * will load the configuration data out of the NVM manually. 9718 * 9719 * hw: Struct containing variables accessed by shared code 9720 *****************************************************************************/ 9721 STATIC int32_t 9722 em_init_lcd_from_nvm(struct em_hw *hw) 9723 { 9724 uint32_t reg_data, cnf_base_addr, cnf_size, ret_val, loop, sw_cfg_mask; 9725 if (hw->phy_type != em_phy_igp_3) 9726 return E1000_SUCCESS; 9727 9728 /* Check if SW needs configure the PHY */ 9729 if (hw->device_id == E1000_DEV_ID_ICH8_IGP_M_AMT || 9730 hw->device_id == E1000_DEV_ID_ICH8_IGP_M || 9731 hw->mac_type == em_pchlan || 9732 hw->mac_type == em_pch2lan) 9733 sw_cfg_mask = FEXTNVM_SW_CONFIG_ICH8M; 9734 else 9735 sw_cfg_mask = FEXTNVM_SW_CONFIG; 9736 9737 reg_data = E1000_READ_REG(hw, FEXTNVM); 9738 if (!(reg_data & sw_cfg_mask)) 9739 return E1000_SUCCESS; 9740 9741 /* Wait for basic configuration completes before proceeding */ 9742 loop = 0; 9743 do { 9744 reg_data = 9745 E1000_READ_REG(hw, STATUS) & E1000_STATUS_LAN_INIT_DONE; 9746 usec_delay(100); 9747 loop++; 9748 } while ((!reg_data) && (loop < 50)); 9749 9750 /* Clear the Init Done bit for the next init event */ 9751 reg_data = E1000_READ_REG(hw, STATUS); 9752 reg_data &= ~E1000_STATUS_LAN_INIT_DONE; 9753 E1000_WRITE_REG(hw, STATUS, reg_data); 9754 /* 9755 * Make sure HW does not configure LCD from PHY extended 9756 * configuration before SW configuration 9757 */ 9758 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL); 9759 if ((reg_data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) == 0x0000) { 9760 reg_data = E1000_READ_REG(hw, EXTCNF_SIZE); 9761 cnf_size = reg_data & E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH; 9762 cnf_size >>= 16; 9763 if (cnf_size) { 9764 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL); 9765 cnf_base_addr = reg_data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER; 9766 /* cnf_base_addr is in DWORD */ 9767 cnf_base_addr >>= 16; 9768 9769 /* Configure LCD from extended configuration region. */ 9770 ret_val = em_init_lcd_from_nvm_config_region(hw, 9771 cnf_base_addr, cnf_size); 9772 if (ret_val) 9773 return ret_val; 9774 } 9775 } 9776 return E1000_SUCCESS; 9777 } 9778 9779 /****************************************************************************** 9780 * em_set_pciex_completion_timeout - set pci-e completion timeout 9781 * 9782 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms, 9783 * however the hardware default for these parts is 500us to 1ms which is less 9784 * than the 10ms recommended by the pci-e spec. To address this we need to 9785 * increase the value to either 10ms to 200ms for capability version 1 config, 9786 * or 16ms to 55ms for version 2. 9787 * 9788 * * hw - pointer to em_hw structure 9789 *****************************************************************************/ 9790 int32_t 9791 em_set_pciex_completion_timeout(struct em_hw *hw) 9792 { 9793 uint32_t gcr = E1000_READ_REG(hw, GCR); 9794 int32_t ret_val = E1000_SUCCESS; 9795 9796 /* Only take action if timeout value is not set by system BIOS */ 9797 if (gcr & E1000_GCR_CMPL_TMOUT_MASK) 9798 goto out; 9799 9800 DEBUGOUT("PCIe completion timeout not set by system BIOS."); 9801 9802 /* 9803 * If capababilities version is type 1 we can write the 9804 * timeout of 10ms to 200ms through the GCR register 9805 */ 9806 9807 if (!(gcr & E1000_GCR_CAP_VER2)) { 9808 gcr |= E1000_GCR_CMPL_TMOUT_10ms; 9809 DEBUGOUT("PCIe capability version 1 detected, setting \ 9810 completion timeout to 10ms."); 9811 goto out; 9812 } 9813 9814 /* 9815 * For version 2 capabilities we need to write the config space 9816 * directly in order to set the completion timeout value for 9817 * 16ms to 55ms 9818 * 9819 * XXX: Implement em_*_pcie_cap_reg() first. 9820 */ 9821 #if 0 9822 ret_val = em_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 9823 &pciex_devctl2); 9824 9825 if (ret_val) 9826 goto out; 9827 9828 pciex_devctl2 |= PCIE_DEVICE_CONTROL2_16ms; 9829 9830 ret_val = em_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 9831 &pciex_devctl2); 9832 #endif 9833 9834 out: 9835 9836 /* Disable completion timeout resend */ 9837 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND; 9838 9839 DEBUGOUT("PCIe completion timeout resend disabled."); 9840 9841 E1000_WRITE_REG(hw, GCR, gcr); 9842 return ret_val; 9843 } 9844 9845 /*************************************************************************** 9846 * Set slow MDIO access mode 9847 ***************************************************************************/ 9848 static int32_t 9849 em_set_mdio_slow_mode_hv(struct em_hw *hw) 9850 { 9851 int32_t ret_val; 9852 uint16_t data; 9853 DEBUGFUNC("em_set_mdio_slow_mode_hv"); 9854 9855 ret_val = em_read_phy_reg(hw, HV_KMRN_MODE_CTRL, &data); 9856 if (ret_val) 9857 return ret_val; 9858 9859 data |= HV_KMRN_MDIO_SLOW; 9860 9861 ret_val = em_write_phy_reg(hw, HV_KMRN_MODE_CTRL, data); 9862 9863 return ret_val; 9864 } 9865 9866 /*************************************************************************** 9867 * A series of Phy workarounds to be done after every PHY reset. 9868 ***************************************************************************/ 9869 int32_t 9870 em_hv_phy_workarounds_ich8lan(struct em_hw *hw) 9871 { 9872 int32_t ret_val = E1000_SUCCESS; 9873 uint16_t phy_data; 9874 uint16_t swfw; 9875 DEBUGFUNC("em_hv_phy_workarounds_ich8lan"); 9876 9877 if (hw->mac_type != em_pchlan) 9878 goto out; 9879 9880 swfw = E1000_SWFW_PHY0_SM; 9881 9882 /* Set MDIO slow mode before any other MDIO access */ 9883 if (hw->phy_type == em_phy_82577 || 9884 hw->phy_type == em_phy_82578) { 9885 ret_val = em_set_mdio_slow_mode_hv(hw); 9886 if (ret_val) 9887 goto out; 9888 } 9889 9890 /* Hanksville M Phy init for IEEE. */ 9891 if ((hw->revision_id == 2) && 9892 (hw->phy_type == em_phy_82577) && 9893 ((hw->phy_revision == 2) || (hw->phy_revision == 3))) { 9894 em_write_phy_reg(hw, 0x10, 0x8823); 9895 em_write_phy_reg(hw, 0x11, 0x0018); 9896 em_write_phy_reg(hw, 0x10, 0x8824); 9897 em_write_phy_reg(hw, 0x11, 0x0016); 9898 em_write_phy_reg(hw, 0x10, 0x8825); 9899 em_write_phy_reg(hw, 0x11, 0x001A); 9900 em_write_phy_reg(hw, 0x10, 0x888C); 9901 em_write_phy_reg(hw, 0x11, 0x0007); 9902 em_write_phy_reg(hw, 0x10, 0x888D); 9903 em_write_phy_reg(hw, 0x11, 0x0007); 9904 em_write_phy_reg(hw, 0x10, 0x888E); 9905 em_write_phy_reg(hw, 0x11, 0x0007); 9906 em_write_phy_reg(hw, 0x10, 0x8827); 9907 em_write_phy_reg(hw, 0x11, 0x0001); 9908 em_write_phy_reg(hw, 0x10, 0x8835); 9909 em_write_phy_reg(hw, 0x11, 0x0001); 9910 em_write_phy_reg(hw, 0x10, 0x8834); 9911 em_write_phy_reg(hw, 0x11, 0x0001); 9912 em_write_phy_reg(hw, 0x10, 0x8833); 9913 em_write_phy_reg(hw, 0x11, 0x0002); 9914 } 9915 9916 if (((hw->phy_type == em_phy_82577) && 9917 ((hw->phy_revision == 1) || (hw->phy_revision == 2))) || 9918 ((hw->phy_type == em_phy_82578) && (hw->phy_revision == 1))) { 9919 /* Disable generation of early preamble */ 9920 ret_val = em_write_phy_reg(hw, PHY_REG(769, 25), 0x4431); 9921 if (ret_val) 9922 goto out; 9923 9924 /* Preamble tuning for SSC */ 9925 ret_val = em_write_phy_reg(hw, PHY_REG(770, 16), 0xA204); 9926 if (ret_val) 9927 goto out; 9928 } 9929 9930 if (hw->phy_type == em_phy_82578) { 9931 /* 9932 * Return registers to default by doing a soft reset then 9933 * writing 0x3140 to the control register. 9934 */ 9935 if (hw->phy_revision < 2) { 9936 em_phy_reset(hw); 9937 ret_val = em_write_phy_reg(hw, PHY_CTRL, 0x3140); 9938 } 9939 } 9940 9941 if ((hw->revision_id == 2) && 9942 (hw->phy_type == em_phy_82577) && 9943 ((hw->phy_revision == 2) || (hw->phy_revision == 3))) { 9944 /* 9945 * Workaround for OEM (GbE) not operating after reset - 9946 * restart AN (twice) 9947 */ 9948 ret_val = em_write_phy_reg(hw, PHY_REG(0, 25), 0x0400); 9949 if (ret_val) 9950 goto out; 9951 ret_val = em_write_phy_reg(hw, PHY_REG(0, 25), 0x0400); 9952 if (ret_val) 9953 goto out; 9954 } 9955 9956 /* Select page 0 */ 9957 ret_val = em_swfw_sync_acquire(hw, swfw); 9958 if (ret_val) 9959 goto out; 9960 9961 hw->phy_addr = 1; 9962 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT, 0); 9963 em_swfw_sync_release(hw, swfw); 9964 if (ret_val) 9965 goto out; 9966 9967 /* Workaround for link disconnects on a busy hub in half duplex */ 9968 ret_val = em_read_phy_reg(hw, 9969 PHY_REG(BM_PORT_CTRL_PAGE, 17), 9970 &phy_data); 9971 if (ret_val) 9972 goto release; 9973 ret_val = em_write_phy_reg(hw, 9974 PHY_REG(BM_PORT_CTRL_PAGE, 17), 9975 phy_data & 0x00FF); 9976 release: 9977 out: 9978 return ret_val; 9979 } 9980 9981 9982 /*************************************************************************** 9983 * Si workaround 9984 * 9985 * This function works around a Si bug where the link partner can get 9986 * a link up indication before the PHY does. If small packets are sent 9987 * by the link partner they can be placed in the packet buffer without 9988 * being properly accounted for by the PHY and will stall preventing 9989 * further packets from being received. The workaround is to clear the 9990 * packet buffer after the PHY detects link up. 9991 ***************************************************************************/ 9992 int32_t 9993 em_link_stall_workaround_hv(struct em_hw *hw) 9994 { 9995 int32_t ret_val = E1000_SUCCESS; 9996 uint16_t phy_data; 9997 9998 if (hw->phy_type != em_phy_82578) 9999 goto out; 10000 10001 /* Do not apply workaround if in PHY loopback bit 14 set */ 10002 em_read_phy_reg(hw, PHY_CTRL, &phy_data); 10003 if (phy_data & E1000_PHY_CTRL_LOOPBACK) 10004 goto out; 10005 10006 /* check if link is up and at 1Gbps */ 10007 ret_val = em_read_phy_reg(hw, BM_CS_STATUS, &phy_data); 10008 if (ret_val) 10009 goto out; 10010 10011 phy_data &= BM_CS_STATUS_LINK_UP | 10012 BM_CS_STATUS_RESOLVED | 10013 BM_CS_STATUS_SPEED_MASK; 10014 10015 if (phy_data != (BM_CS_STATUS_LINK_UP | 10016 BM_CS_STATUS_RESOLVED | 10017 BM_CS_STATUS_SPEED_1000)) 10018 goto out; 10019 10020 msec_delay(200); 10021 10022 /* flush the packets in the fifo buffer */ 10023 ret_val = em_write_phy_reg(hw, HV_MUX_DATA_CTRL, 10024 HV_MUX_DATA_CTRL_GEN_TO_MAC | HV_MUX_DATA_CTRL_FORCE_SPEED); 10025 if (ret_val) 10026 goto out; 10027 10028 ret_val = em_write_phy_reg(hw, HV_MUX_DATA_CTRL, 10029 HV_MUX_DATA_CTRL_GEN_TO_MAC); 10030 10031 out: 10032 return ret_val; 10033 } 10034 10035 /**************************************************************************** 10036 * K1 Si workaround 10037 * 10038 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning 10039 * from a lower speed. This workaround disables K1 whenever link is at 1Gig. 10040 * If link is down, the function will restore the default K1 setting located 10041 * in the NVM. 10042 ****************************************************************************/ 10043 int32_t 10044 em_k1_gig_workaround_hv(struct em_hw *hw, boolean_t link) 10045 { 10046 int32_t ret_val; 10047 uint16_t phy_data; 10048 boolean_t k1_enable; 10049 10050 DEBUGFUNC("em_k1_gig_workaround_hv"); 10051 10052 if (hw->mac_type != em_pchlan) 10053 return E1000_SUCCESS; 10054 10055 ret_val = em_read_eeprom_ich8(hw, E1000_NVM_K1_CONFIG, 1, &phy_data); 10056 if (ret_val) 10057 return ret_val; 10058 10059 k1_enable = phy_data & E1000_NVM_K1_ENABLE ? TRUE : FALSE; 10060 10061 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */ 10062 if (link) { 10063 if (hw->phy_type == em_phy_82578) { 10064 ret_val = em_read_phy_reg(hw, BM_CS_STATUS, 10065 &phy_data); 10066 if (ret_val) 10067 return ret_val; 10068 10069 phy_data &= BM_CS_STATUS_LINK_UP | 10070 BM_CS_STATUS_RESOLVED | 10071 BM_CS_STATUS_SPEED_MASK; 10072 10073 if (phy_data == (BM_CS_STATUS_LINK_UP | 10074 BM_CS_STATUS_RESOLVED | 10075 BM_CS_STATUS_SPEED_1000)) 10076 k1_enable = FALSE; 10077 } 10078 10079 if (hw->phy_type == em_phy_82577) { 10080 ret_val = em_read_phy_reg(hw, HV_M_STATUS, 10081 &phy_data); 10082 if (ret_val) 10083 return ret_val; 10084 10085 phy_data &= HV_M_STATUS_LINK_UP | 10086 HV_M_STATUS_AUTONEG_COMPLETE | 10087 HV_M_STATUS_SPEED_MASK; 10088 10089 if (phy_data == (HV_M_STATUS_LINK_UP | 10090 HV_M_STATUS_AUTONEG_COMPLETE | 10091 HV_M_STATUS_SPEED_1000)) 10092 k1_enable = FALSE; 10093 } 10094 10095 /* Link stall fix for link up */ 10096 ret_val = em_write_phy_reg(hw, PHY_REG(770, 19), 10097 0x0100); 10098 if (ret_val) 10099 return ret_val; 10100 10101 } else { 10102 /* Link stall fix for link down */ 10103 ret_val = em_write_phy_reg(hw, PHY_REG(770, 19), 10104 0x4100); 10105 if (ret_val) 10106 return ret_val; 10107 } 10108 10109 ret_val = em_configure_k1_ich8lan(hw, k1_enable); 10110 10111 return ret_val; 10112 } 10113 10114 /* Workaround to set the K1 beacon duration for 82579 parts */ 10115 int32_t 10116 em_k1_workaround_lv(struct em_hw *hw) 10117 { 10118 int32_t ret_val; 10119 uint16_t phy_data; 10120 uint32_t mac_reg; 10121 10122 ret_val = em_read_phy_reg(hw, BM_CS_STATUS, &phy_data); 10123 if (ret_val) 10124 return ret_val; 10125 10126 if ((phy_data & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) 10127 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) { 10128 mac_reg = E1000_READ_REG(hw, FEXTNVM4); 10129 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK; 10130 10131 if (phy_data & HV_M_STATUS_SPEED_1000) 10132 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC; 10133 else 10134 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC; 10135 10136 E1000_WRITE_REG(hw, FEXTNVM4, mac_reg); 10137 } 10138 10139 return E1000_SUCCESS; 10140 } 10141 10142 /*************************************************************************** 10143 * Configure K1 power state 10144 * 10145 * Configure the K1 power state based on the provided parameter. 10146 * Assumes semaphore already acquired. 10147 * 10148 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 10149 ***************************************************************************/ 10150 int32_t 10151 em_configure_k1_ich8lan(struct em_hw *hw, boolean_t k1_enable) 10152 { 10153 int32_t ret_val = E1000_SUCCESS; 10154 uint32_t ctrl_reg = 0; 10155 uint32_t ctrl_ext = 0; 10156 uint32_t reg = 0; 10157 uint16_t kmrn_reg = 0; 10158 10159 ret_val = em_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 10160 &kmrn_reg); 10161 if (ret_val) 10162 goto out; 10163 10164 if (k1_enable) 10165 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE; 10166 else 10167 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE; 10168 10169 ret_val = em_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 10170 kmrn_reg); 10171 if (ret_val) 10172 goto out; 10173 10174 usec_delay(20); 10175 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 10176 ctrl_reg = E1000_READ_REG(hw, CTRL); 10177 10178 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 10179 reg |= E1000_CTRL_FRCSPD; 10180 E1000_WRITE_REG(hw, CTRL, reg); 10181 10182 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS); 10183 usec_delay(20); 10184 E1000_WRITE_REG(hw, CTRL, ctrl_reg); 10185 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 10186 usec_delay(20); 10187 10188 out: 10189 return ret_val; 10190 } 10191 10192 int32_t 10193 em_set_eee_i350(struct em_hw *hw) 10194 { 10195 int32_t ret_val = E1000_SUCCESS; 10196 uint32_t ipcnfg, eeer; 10197 10198 if ((hw->mac_type < em_i350) || 10199 (hw->media_type != em_media_type_copper)) 10200 goto out; 10201 ipcnfg = EM_READ_REG(hw, E1000_IPCNFG); 10202 eeer = EM_READ_REG(hw, E1000_EEER); 10203 10204 if (hw->eee_enable) { 10205 ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN); 10206 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN | 10207 E1000_EEER_LPI_FC); 10208 } else { 10209 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN); 10210 eeer &= ~(E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN | 10211 E1000_EEER_LPI_FC); 10212 } 10213 EM_WRITE_REG(hw, E1000_IPCNFG, ipcnfg); 10214 EM_WRITE_REG(hw, E1000_EEER, eeer); 10215 EM_READ_REG(hw, E1000_IPCNFG); 10216 EM_READ_REG(hw, E1000_EEER); 10217 out: 10218 return ret_val; 10219 } 10220