1 /******************************************************************************* 2 3 Copyright (c) 2001-2005, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 *******************************************************************************/ 33 34 /* $OpenBSD: if_em_hw.c,v 1.109 2020/07/13 10:35:55 dlg Exp $ */ 35 /* 36 * if_em_hw.c Shared functions for accessing and configuring the MAC 37 */ 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/sockio.h> 42 #include <sys/mbuf.h> 43 #include <sys/malloc.h> 44 #include <sys/kernel.h> 45 #include <sys/device.h> 46 #include <sys/socket.h> 47 #include <sys/kstat.h> 48 49 #include <net/if.h> 50 #include <net/if_media.h> 51 52 #include <netinet/in.h> 53 #include <netinet/if_ether.h> 54 55 #include <uvm/uvm_extern.h> 56 57 #include <dev/pci/pcireg.h> 58 #include <dev/pci/pcivar.h> 59 60 #include <dev/pci/if_em.h> 61 #include <dev/pci/if_em_hw.h> 62 #include <dev/pci/if_em_soc.h> 63 64 #include <dev/mii/rgephyreg.h> 65 66 #define STATIC 67 68 static int32_t em_swfw_sync_acquire(struct em_hw *, uint16_t); 69 static void em_swfw_sync_release(struct em_hw *, uint16_t); 70 static int32_t em_read_kmrn_reg(struct em_hw *, uint32_t, uint16_t *); 71 static int32_t em_write_kmrn_reg(struct em_hw *hw, uint32_t, uint16_t); 72 static int32_t em_get_software_semaphore(struct em_hw *); 73 static void em_release_software_semaphore(struct em_hw *); 74 75 static int32_t em_check_downshift(struct em_hw *); 76 static void em_clear_vfta(struct em_hw *); 77 void em_clear_vfta_i350(struct em_hw *); 78 static int32_t em_commit_shadow_ram(struct em_hw *); 79 static int32_t em_config_dsp_after_link_change(struct em_hw *, boolean_t); 80 static int32_t em_config_fc_after_link_up(struct em_hw *); 81 static int32_t em_match_gig_phy(struct em_hw *); 82 static int32_t em_detect_gig_phy(struct em_hw *); 83 static int32_t em_erase_ich8_4k_segment(struct em_hw *, uint32_t); 84 static int32_t em_get_auto_rd_done(struct em_hw *); 85 static int32_t em_get_cable_length(struct em_hw *, uint16_t *, uint16_t *); 86 static int32_t em_get_hw_eeprom_semaphore(struct em_hw *); 87 static int32_t em_get_phy_cfg_done(struct em_hw *); 88 static int32_t em_get_software_flag(struct em_hw *); 89 static int32_t em_ich8_cycle_init(struct em_hw *); 90 static int32_t em_ich8_flash_cycle(struct em_hw *, uint32_t); 91 static int32_t em_id_led_init(struct em_hw *); 92 static int32_t em_init_lcd_from_nvm_config_region(struct em_hw *, uint32_t, 93 uint32_t); 94 static int32_t em_init_lcd_from_nvm(struct em_hw *); 95 static int32_t em_phy_no_cable_workaround(struct em_hw *); 96 static void em_init_rx_addrs(struct em_hw *); 97 static void em_initialize_hardware_bits(struct em_softc *); 98 static void em_toggle_lanphypc_pch_lpt(struct em_hw *); 99 static int em_disable_ulp_lpt_lp(struct em_hw *hw, bool force); 100 static boolean_t em_is_onboard_nvm_eeprom(struct em_hw *); 101 static int32_t em_kumeran_lock_loss_workaround(struct em_hw *); 102 static int32_t em_mng_enable_host_if(struct em_hw *); 103 static int32_t em_read_eeprom_eerd(struct em_hw *, uint16_t, uint16_t, 104 uint16_t *); 105 static int32_t em_write_eeprom_eewr(struct em_hw *, uint16_t, uint16_t, 106 uint16_t *data); 107 static int32_t em_poll_eerd_eewr_done(struct em_hw *, int); 108 static void em_put_hw_eeprom_semaphore(struct em_hw *); 109 static int32_t em_read_ich8_byte(struct em_hw *, uint32_t, uint8_t *); 110 static int32_t em_verify_write_ich8_byte(struct em_hw *, uint32_t, uint8_t); 111 static int32_t em_write_ich8_byte(struct em_hw *, uint32_t, uint8_t); 112 static int32_t em_read_ich8_word(struct em_hw *, uint32_t, uint16_t *); 113 static int32_t em_read_ich8_dword(struct em_hw *, uint32_t, uint32_t *); 114 static int32_t em_read_ich8_data(struct em_hw *, uint32_t, uint32_t, 115 uint16_t *); 116 static int32_t em_write_ich8_data(struct em_hw *, uint32_t, uint32_t, 117 uint16_t); 118 static int32_t em_read_eeprom_ich8(struct em_hw *, uint16_t, uint16_t, 119 uint16_t *); 120 static int32_t em_write_eeprom_ich8(struct em_hw *, uint16_t, uint16_t, 121 uint16_t *); 122 static int32_t em_read_invm_i210(struct em_hw *, uint16_t, uint16_t, 123 uint16_t *); 124 static int32_t em_read_invm_word_i210(struct em_hw *, uint16_t, uint16_t *); 125 static void em_release_software_flag(struct em_hw *); 126 static int32_t em_set_d3_lplu_state(struct em_hw *, boolean_t); 127 static int32_t em_set_d0_lplu_state(struct em_hw *, boolean_t); 128 static int32_t em_set_lplu_state_pchlan(struct em_hw *, boolean_t); 129 static int32_t em_set_pci_ex_no_snoop(struct em_hw *, uint32_t); 130 static void em_set_pci_express_master_disable(struct em_hw *); 131 static int32_t em_wait_autoneg(struct em_hw *); 132 static void em_write_reg_io(struct em_hw *, uint32_t, uint32_t); 133 static int32_t em_set_phy_type(struct em_hw *); 134 static void em_phy_init_script(struct em_hw *); 135 static int32_t em_setup_copper_link(struct em_hw *); 136 static int32_t em_setup_fiber_serdes_link(struct em_hw *); 137 static int32_t em_adjust_serdes_amplitude(struct em_hw *); 138 static int32_t em_phy_force_speed_duplex(struct em_hw *); 139 static int32_t em_config_mac_to_phy(struct em_hw *); 140 static void em_raise_mdi_clk(struct em_hw *, uint32_t *); 141 static void em_lower_mdi_clk(struct em_hw *, uint32_t *); 142 static void em_shift_out_mdi_bits(struct em_hw *, uint32_t, uint16_t); 143 static uint16_t em_shift_in_mdi_bits(struct em_hw *); 144 static int32_t em_phy_reset_dsp(struct em_hw *); 145 static int32_t em_write_eeprom_spi(struct em_hw *, uint16_t, uint16_t, 146 uint16_t *); 147 static int32_t em_write_eeprom_microwire(struct em_hw *, uint16_t, uint16_t, 148 uint16_t *); 149 static int32_t em_spi_eeprom_ready(struct em_hw *); 150 static void em_raise_ee_clk(struct em_hw *, uint32_t *); 151 static void em_lower_ee_clk(struct em_hw *, uint32_t *); 152 static void em_shift_out_ee_bits(struct em_hw *, uint16_t, uint16_t); 153 static int32_t em_write_phy_reg_ex(struct em_hw *, uint32_t, uint16_t); 154 static int32_t em_read_phy_reg_ex(struct em_hw *, uint32_t, uint16_t *); 155 static uint16_t em_shift_in_ee_bits(struct em_hw *, uint16_t); 156 static int32_t em_acquire_eeprom(struct em_hw *); 157 static void em_release_eeprom(struct em_hw *); 158 static void em_standby_eeprom(struct em_hw *); 159 static int32_t em_set_vco_speed(struct em_hw *); 160 static int32_t em_polarity_reversal_workaround(struct em_hw *); 161 static int32_t em_set_phy_mode(struct em_hw *); 162 static int32_t em_host_if_read_cookie(struct em_hw *, uint8_t *); 163 static uint8_t em_calculate_mng_checksum(char *, uint32_t); 164 static int32_t em_configure_kmrn_for_10_100(struct em_hw *, uint16_t); 165 static int32_t em_configure_kmrn_for_1000(struct em_hw *); 166 static int32_t em_set_pciex_completion_timeout(struct em_hw *hw); 167 static int32_t em_set_mdio_slow_mode_hv(struct em_hw *); 168 int32_t em_hv_phy_workarounds_ich8lan(struct em_hw *); 169 int32_t em_lv_phy_workarounds_ich8lan(struct em_hw *); 170 int32_t em_link_stall_workaround_hv(struct em_hw *); 171 int32_t em_k1_gig_workaround_hv(struct em_hw *, boolean_t); 172 int32_t em_k1_workaround_lv(struct em_hw *); 173 int32_t em_k1_workaround_lpt_lp(struct em_hw *, boolean_t); 174 int32_t em_configure_k1_ich8lan(struct em_hw *, boolean_t); 175 void em_gate_hw_phy_config_ich8lan(struct em_hw *, boolean_t); 176 int32_t em_access_phy_wakeup_reg_bm(struct em_hw *, uint32_t, 177 uint16_t *, boolean_t); 178 int32_t em_access_phy_debug_regs_hv(struct em_hw *, uint32_t, 179 uint16_t *, boolean_t); 180 int32_t em_access_phy_reg_hv(struct em_hw *, uint32_t, uint16_t *, 181 boolean_t); 182 int32_t em_oem_bits_config_pchlan(struct em_hw *, boolean_t); 183 void em_power_up_serdes_link_82575(struct em_hw *); 184 int32_t em_get_pcs_speed_and_duplex_82575(struct em_hw *, uint16_t *, 185 uint16_t *); 186 int32_t em_set_eee_i350(struct em_hw *); 187 int32_t em_set_eee_pchlan(struct em_hw *); 188 int32_t em_valid_nvm_bank_detect_ich8lan(struct em_hw *, uint32_t *); 189 int32_t em_initialize_M88E1512_phy(struct em_hw *); 190 191 /* IGP cable length table */ 192 static const uint16_t 193 em_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = 194 {5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 195 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25, 196 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40, 197 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60, 198 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90, 199 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 200 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 201 110, 202 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 203 120}; 204 205 static const uint16_t 206 em_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] = 207 {0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 208 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 209 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 210 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 211 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 212 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 213 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 214 121, 124}; 215 216 /****************************************************************************** 217 * Set the phy type member in the hw struct. 218 * 219 * hw - Struct containing variables accessed by shared code 220 *****************************************************************************/ 221 STATIC int32_t 222 em_set_phy_type(struct em_hw *hw) 223 { 224 DEBUGFUNC("em_set_phy_type"); 225 226 if (hw->mac_type == em_undefined) 227 return -E1000_ERR_PHY_TYPE; 228 229 switch (hw->phy_id) { 230 case M88E1000_E_PHY_ID: 231 case M88E1000_I_PHY_ID: 232 case M88E1011_I_PHY_ID: 233 case M88E1111_I_PHY_ID: 234 case M88E1112_E_PHY_ID: 235 case M88E1543_E_PHY_ID: 236 case M88E1512_E_PHY_ID: 237 case I210_I_PHY_ID: 238 case I347AT4_E_PHY_ID: 239 hw->phy_type = em_phy_m88; 240 break; 241 case IGP01E1000_I_PHY_ID: 242 if (hw->mac_type == em_82541 || 243 hw->mac_type == em_82541_rev_2 || 244 hw->mac_type == em_82547 || 245 hw->mac_type == em_82547_rev_2) { 246 hw->phy_type = em_phy_igp; 247 break; 248 } 249 case IGP03E1000_E_PHY_ID: 250 case IGP04E1000_E_PHY_ID: 251 hw->phy_type = em_phy_igp_3; 252 break; 253 case IFE_E_PHY_ID: 254 case IFE_PLUS_E_PHY_ID: 255 case IFE_C_E_PHY_ID: 256 hw->phy_type = em_phy_ife; 257 break; 258 case M88E1141_E_PHY_ID: 259 hw->phy_type = em_phy_oem; 260 break; 261 case I82577_E_PHY_ID: 262 hw->phy_type = em_phy_82577; 263 break; 264 case I82578_E_PHY_ID: 265 hw->phy_type = em_phy_82578; 266 break; 267 case I82579_E_PHY_ID: 268 hw->phy_type = em_phy_82579; 269 break; 270 case I217_E_PHY_ID: 271 hw->phy_type = em_phy_i217; 272 break; 273 case I82580_I_PHY_ID: 274 case I350_I_PHY_ID: 275 hw->phy_type = em_phy_82580; 276 break; 277 case RTL8211_E_PHY_ID: 278 hw->phy_type = em_phy_rtl8211; 279 break; 280 case BME1000_E_PHY_ID: 281 if (hw->phy_revision == 1) { 282 hw->phy_type = em_phy_bm; 283 break; 284 } 285 /* FALLTHROUGH */ 286 case GG82563_E_PHY_ID: 287 if (hw->mac_type == em_80003es2lan) { 288 hw->phy_type = em_phy_gg82563; 289 break; 290 } 291 /* FALLTHROUGH */ 292 default: 293 /* Should never have loaded on this device */ 294 hw->phy_type = em_phy_undefined; 295 return -E1000_ERR_PHY_TYPE; 296 } 297 298 return E1000_SUCCESS; 299 } 300 301 /****************************************************************************** 302 * IGP phy init script - initializes the GbE PHY 303 * 304 * hw - Struct containing variables accessed by shared code 305 *****************************************************************************/ 306 static void 307 em_phy_init_script(struct em_hw *hw) 308 { 309 uint16_t phy_saved_data; 310 DEBUGFUNC("em_phy_init_script"); 311 312 if (hw->phy_init_script) { 313 msec_delay(20); 314 /* 315 * Save off the current value of register 0x2F5B to be 316 * restored at the end of this routine. 317 */ 318 em_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 319 320 /* Disabled the PHY transmitter */ 321 em_write_phy_reg(hw, 0x2F5B, 0x0003); 322 msec_delay(20); 323 em_write_phy_reg(hw, 0x0000, 0x0140); 324 msec_delay(5); 325 326 switch (hw->mac_type) { 327 case em_82541: 328 case em_82547: 329 em_write_phy_reg(hw, 0x1F95, 0x0001); 330 em_write_phy_reg(hw, 0x1F71, 0xBD21); 331 em_write_phy_reg(hw, 0x1F79, 0x0018); 332 em_write_phy_reg(hw, 0x1F30, 0x1600); 333 em_write_phy_reg(hw, 0x1F31, 0x0014); 334 em_write_phy_reg(hw, 0x1F32, 0x161C); 335 em_write_phy_reg(hw, 0x1F94, 0x0003); 336 em_write_phy_reg(hw, 0x1F96, 0x003F); 337 em_write_phy_reg(hw, 0x2010, 0x0008); 338 break; 339 case em_82541_rev_2: 340 case em_82547_rev_2: 341 em_write_phy_reg(hw, 0x1F73, 0x0099); 342 break; 343 default: 344 break; 345 } 346 347 em_write_phy_reg(hw, 0x0000, 0x3300); 348 msec_delay(20); 349 350 /* Now enable the transmitter */ 351 em_write_phy_reg(hw, 0x2F5B, phy_saved_data); 352 353 if (hw->mac_type == em_82547) { 354 uint16_t fused, fine, coarse; 355 /* Move to analog registers page */ 356 em_read_phy_reg(hw, 357 IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused); 358 359 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { 360 em_read_phy_reg(hw, 361 IGP01E1000_ANALOG_FUSE_STATUS, &fused); 362 363 fine = fused & 364 IGP01E1000_ANALOG_FUSE_FINE_MASK; 365 coarse = fused & 366 IGP01E1000_ANALOG_FUSE_COARSE_MASK; 367 368 if (coarse > 369 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { 370 coarse -= 371 IGP01E1000_ANALOG_FUSE_COARSE_10; 372 fine -= 373 IGP01E1000_ANALOG_FUSE_FINE_1; 374 } else if (coarse == 375 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) 376 fine -= IGP01E1000_ANALOG_FUSE_FINE_10; 377 378 fused = (fused & 379 IGP01E1000_ANALOG_FUSE_POLY_MASK) | 380 (fine & 381 IGP01E1000_ANALOG_FUSE_FINE_MASK) | 382 (coarse & 383 IGP01E1000_ANALOG_FUSE_COARSE_MASK); 384 385 em_write_phy_reg(hw, 386 IGP01E1000_ANALOG_FUSE_CONTROL, 387 fused); 388 389 em_write_phy_reg(hw, 390 IGP01E1000_ANALOG_FUSE_BYPASS, 391 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL); 392 } 393 } 394 } 395 } 396 397 /****************************************************************************** 398 * Set the mac type member in the hw struct. 399 * 400 * hw - Struct containing variables accessed by shared code 401 *****************************************************************************/ 402 int32_t 403 em_set_mac_type(struct em_hw *hw) 404 { 405 DEBUGFUNC("em_set_mac_type"); 406 407 switch (hw->device_id) { 408 case E1000_DEV_ID_82542: 409 switch (hw->revision_id) { 410 case E1000_82542_2_0_REV_ID: 411 hw->mac_type = em_82542_rev2_0; 412 break; 413 case E1000_82542_2_1_REV_ID: 414 hw->mac_type = em_82542_rev2_1; 415 break; 416 default: 417 /* Invalid 82542 revision ID */ 418 return -E1000_ERR_MAC_TYPE; 419 } 420 break; 421 case E1000_DEV_ID_82543GC_FIBER: 422 case E1000_DEV_ID_82543GC_COPPER: 423 hw->mac_type = em_82543; 424 break; 425 case E1000_DEV_ID_82544EI_COPPER: 426 case E1000_DEV_ID_82544EI_FIBER: 427 case E1000_DEV_ID_82544GC_COPPER: 428 case E1000_DEV_ID_82544GC_LOM: 429 hw->mac_type = em_82544; 430 break; 431 case E1000_DEV_ID_82540EM: 432 case E1000_DEV_ID_82540EM_LOM: 433 case E1000_DEV_ID_82540EP: 434 case E1000_DEV_ID_82540EP_LOM: 435 case E1000_DEV_ID_82540EP_LP: 436 hw->mac_type = em_82540; 437 break; 438 case E1000_DEV_ID_82545EM_COPPER: 439 case E1000_DEV_ID_82545EM_FIBER: 440 hw->mac_type = em_82545; 441 break; 442 case E1000_DEV_ID_82545GM_COPPER: 443 case E1000_DEV_ID_82545GM_FIBER: 444 case E1000_DEV_ID_82545GM_SERDES: 445 hw->mac_type = em_82545_rev_3; 446 break; 447 case E1000_DEV_ID_82546EB_COPPER: 448 case E1000_DEV_ID_82546EB_FIBER: 449 case E1000_DEV_ID_82546EB_QUAD_COPPER: 450 hw->mac_type = em_82546; 451 break; 452 case E1000_DEV_ID_82546GB_COPPER: 453 case E1000_DEV_ID_82546GB_FIBER: 454 case E1000_DEV_ID_82546GB_SERDES: 455 case E1000_DEV_ID_82546GB_PCIE: 456 case E1000_DEV_ID_82546GB_QUAD_COPPER: 457 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 458 case E1000_DEV_ID_82546GB_2: 459 hw->mac_type = em_82546_rev_3; 460 break; 461 case E1000_DEV_ID_82541EI: 462 case E1000_DEV_ID_82541EI_MOBILE: 463 case E1000_DEV_ID_82541ER_LOM: 464 hw->mac_type = em_82541; 465 break; 466 case E1000_DEV_ID_82541ER: 467 case E1000_DEV_ID_82541GI: 468 case E1000_DEV_ID_82541GI_LF: 469 case E1000_DEV_ID_82541GI_MOBILE: 470 hw->mac_type = em_82541_rev_2; 471 break; 472 case E1000_DEV_ID_82547EI: 473 case E1000_DEV_ID_82547EI_MOBILE: 474 hw->mac_type = em_82547; 475 break; 476 case E1000_DEV_ID_82547GI: 477 hw->mac_type = em_82547_rev_2; 478 break; 479 case E1000_DEV_ID_82571EB_AF: 480 case E1000_DEV_ID_82571EB_AT: 481 case E1000_DEV_ID_82571EB_COPPER: 482 case E1000_DEV_ID_82571EB_FIBER: 483 case E1000_DEV_ID_82571EB_SERDES: 484 case E1000_DEV_ID_82571EB_QUAD_COPPER: 485 case E1000_DEV_ID_82571EB_QUAD_FIBER: 486 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 487 case E1000_DEV_ID_82571EB_SERDES_DUAL: 488 case E1000_DEV_ID_82571EB_SERDES_QUAD: 489 case E1000_DEV_ID_82571PT_QUAD_COPPER: 490 hw->mac_type = em_82571; 491 break; 492 case E1000_DEV_ID_82572EI_COPPER: 493 case E1000_DEV_ID_82572EI_FIBER: 494 case E1000_DEV_ID_82572EI_SERDES: 495 case E1000_DEV_ID_82572EI: 496 hw->mac_type = em_82572; 497 break; 498 case E1000_DEV_ID_82573E: 499 case E1000_DEV_ID_82573E_IAMT: 500 case E1000_DEV_ID_82573E_PM: 501 case E1000_DEV_ID_82573L: 502 case E1000_DEV_ID_82573L_PL_1: 503 case E1000_DEV_ID_82573L_PL_2: 504 case E1000_DEV_ID_82573V_PM: 505 hw->mac_type = em_82573; 506 break; 507 case E1000_DEV_ID_82574L: 508 case E1000_DEV_ID_82574LA: 509 case E1000_DEV_ID_82583V: 510 hw->mac_type = em_82574; 511 break; 512 case E1000_DEV_ID_82575EB_PT: 513 case E1000_DEV_ID_82575EB_PF: 514 case E1000_DEV_ID_82575GB_QP: 515 case E1000_DEV_ID_82575GB_QP_PM: 516 hw->mac_type = em_82575; 517 hw->initialize_hw_bits_disable = 1; 518 break; 519 case E1000_DEV_ID_82576: 520 case E1000_DEV_ID_82576_FIBER: 521 case E1000_DEV_ID_82576_SERDES: 522 case E1000_DEV_ID_82576_QUAD_COPPER: 523 case E1000_DEV_ID_82576_QUAD_CU_ET2: 524 case E1000_DEV_ID_82576_NS: 525 case E1000_DEV_ID_82576_NS_SERDES: 526 case E1000_DEV_ID_82576_SERDES_QUAD: 527 hw->mac_type = em_82576; 528 hw->initialize_hw_bits_disable = 1; 529 break; 530 case E1000_DEV_ID_82580_COPPER: 531 case E1000_DEV_ID_82580_FIBER: 532 case E1000_DEV_ID_82580_QUAD_FIBER: 533 case E1000_DEV_ID_82580_SERDES: 534 case E1000_DEV_ID_82580_SGMII: 535 case E1000_DEV_ID_82580_COPPER_DUAL: 536 case E1000_DEV_ID_DH89XXCC_SGMII: 537 case E1000_DEV_ID_DH89XXCC_SERDES: 538 case E1000_DEV_ID_DH89XXCC_BACKPLANE: 539 case E1000_DEV_ID_DH89XXCC_SFP: 540 hw->mac_type = em_82580; 541 hw->initialize_hw_bits_disable = 1; 542 break; 543 case E1000_DEV_ID_I210_COPPER: 544 case E1000_DEV_ID_I210_COPPER_OEM1: 545 case E1000_DEV_ID_I210_COPPER_IT: 546 case E1000_DEV_ID_I210_FIBER: 547 case E1000_DEV_ID_I210_SERDES: 548 case E1000_DEV_ID_I210_SGMII: 549 case E1000_DEV_ID_I210_COPPER_FLASHLESS: 550 case E1000_DEV_ID_I210_SERDES_FLASHLESS: 551 case E1000_DEV_ID_I211_COPPER: 552 hw->mac_type = em_i210; 553 hw->initialize_hw_bits_disable = 1; 554 hw->eee_enable = 1; 555 break; 556 case E1000_DEV_ID_I350_COPPER: 557 case E1000_DEV_ID_I350_FIBER: 558 case E1000_DEV_ID_I350_SERDES: 559 case E1000_DEV_ID_I350_SGMII: 560 case E1000_DEV_ID_I350_DA4: 561 case E1000_DEV_ID_I354_BACKPLANE_1GBPS: 562 case E1000_DEV_ID_I354_SGMII: 563 case E1000_DEV_ID_I354_BACKPLANE_2_5GBPS: 564 hw->mac_type = em_i350; 565 hw->initialize_hw_bits_disable = 1; 566 hw->eee_enable = 1; 567 break; 568 case E1000_DEV_ID_80003ES2LAN_COPPER_SPT: 569 case E1000_DEV_ID_80003ES2LAN_SERDES_SPT: 570 case E1000_DEV_ID_80003ES2LAN_COPPER_DPT: 571 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: 572 hw->mac_type = em_80003es2lan; 573 break; 574 case E1000_DEV_ID_ICH8_IFE: 575 case E1000_DEV_ID_ICH8_IFE_G: 576 case E1000_DEV_ID_ICH8_IFE_GT: 577 case E1000_DEV_ID_ICH8_IGP_AMT: 578 case E1000_DEV_ID_ICH8_IGP_C: 579 case E1000_DEV_ID_ICH8_IGP_M: 580 case E1000_DEV_ID_ICH8_IGP_M_AMT: 581 case E1000_DEV_ID_ICH8_82567V_3: 582 hw->mac_type = em_ich8lan; 583 break; 584 case E1000_DEV_ID_ICH9_BM: 585 case E1000_DEV_ID_ICH9_IFE: 586 case E1000_DEV_ID_ICH9_IFE_G: 587 case E1000_DEV_ID_ICH9_IFE_GT: 588 case E1000_DEV_ID_ICH9_IGP_AMT: 589 case E1000_DEV_ID_ICH9_IGP_C: 590 case E1000_DEV_ID_ICH9_IGP_M: 591 case E1000_DEV_ID_ICH9_IGP_M_AMT: 592 case E1000_DEV_ID_ICH9_IGP_M_V: 593 case E1000_DEV_ID_ICH10_R_BM_LF: 594 case E1000_DEV_ID_ICH10_R_BM_LM: 595 case E1000_DEV_ID_ICH10_R_BM_V: 596 hw->mac_type = em_ich9lan; 597 break; 598 case E1000_DEV_ID_ICH10_D_BM_LF: 599 case E1000_DEV_ID_ICH10_D_BM_LM: 600 case E1000_DEV_ID_ICH10_D_BM_V: 601 hw->mac_type = em_ich10lan; 602 break; 603 case E1000_DEV_ID_PCH_M_HV_LC: 604 case E1000_DEV_ID_PCH_M_HV_LM: 605 case E1000_DEV_ID_PCH_D_HV_DC: 606 case E1000_DEV_ID_PCH_D_HV_DM: 607 hw->mac_type = em_pchlan; 608 hw->eee_enable = 1; 609 break; 610 case E1000_DEV_ID_PCH2_LV_LM: 611 case E1000_DEV_ID_PCH2_LV_V: 612 hw->mac_type = em_pch2lan; 613 break; 614 case E1000_DEV_ID_PCH_LPT_I217_LM: 615 case E1000_DEV_ID_PCH_LPT_I217_V: 616 case E1000_DEV_ID_PCH_LPTLP_I218_LM: 617 case E1000_DEV_ID_PCH_LPTLP_I218_V: 618 case E1000_DEV_ID_PCH_I218_LM2: 619 case E1000_DEV_ID_PCH_I218_V2: 620 case E1000_DEV_ID_PCH_I218_LM3: 621 case E1000_DEV_ID_PCH_I218_V3: 622 hw->mac_type = em_pch_lpt; 623 break; 624 case E1000_DEV_ID_PCH_SPT_I219_LM: 625 case E1000_DEV_ID_PCH_SPT_I219_V: 626 case E1000_DEV_ID_PCH_SPT_I219_LM2: 627 case E1000_DEV_ID_PCH_SPT_I219_V2: 628 case E1000_DEV_ID_PCH_LBG_I219_LM3: 629 case E1000_DEV_ID_PCH_SPT_I219_LM4: 630 case E1000_DEV_ID_PCH_SPT_I219_V4: 631 case E1000_DEV_ID_PCH_SPT_I219_LM5: 632 case E1000_DEV_ID_PCH_SPT_I219_V5: 633 case E1000_DEV_ID_PCH_CMP_I219_LM12: 634 case E1000_DEV_ID_PCH_CMP_I219_V12: 635 hw->mac_type = em_pch_spt; 636 break; 637 case E1000_DEV_ID_PCH_CNP_I219_LM6: 638 case E1000_DEV_ID_PCH_CNP_I219_V6: 639 case E1000_DEV_ID_PCH_CNP_I219_LM7: 640 case E1000_DEV_ID_PCH_CNP_I219_V7: 641 case E1000_DEV_ID_PCH_ICP_I219_LM8: 642 case E1000_DEV_ID_PCH_ICP_I219_V8: 643 case E1000_DEV_ID_PCH_ICP_I219_LM9: 644 case E1000_DEV_ID_PCH_ICP_I219_V9: 645 case E1000_DEV_ID_PCH_CMP_I219_LM10: 646 case E1000_DEV_ID_PCH_CMP_I219_V10: 647 case E1000_DEV_ID_PCH_CMP_I219_LM11: 648 case E1000_DEV_ID_PCH_CMP_I219_V11: 649 case E1000_DEV_ID_PCH_TGP_I219_LM13: 650 case E1000_DEV_ID_PCH_TGP_I219_V13: 651 case E1000_DEV_ID_PCH_TGP_I219_LM14: 652 case E1000_DEV_ID_PCH_TGP_I219_V14: 653 case E1000_DEV_ID_PCH_TGP_I219_LM15: 654 hw->mac_type = em_pch_cnp; 655 break; 656 case E1000_DEV_ID_EP80579_LAN_1: 657 hw->mac_type = em_icp_xxxx; 658 hw->icp_xxxx_port_num = 0; 659 break; 660 case E1000_DEV_ID_EP80579_LAN_2: 661 case E1000_DEV_ID_EP80579_LAN_4: 662 hw->mac_type = em_icp_xxxx; 663 hw->icp_xxxx_port_num = 1; 664 break; 665 case E1000_DEV_ID_EP80579_LAN_3: 666 case E1000_DEV_ID_EP80579_LAN_5: 667 hw->mac_type = em_icp_xxxx; 668 hw->icp_xxxx_port_num = 2; 669 break; 670 case E1000_DEV_ID_EP80579_LAN_6: 671 hw->mac_type = em_icp_xxxx; 672 hw->icp_xxxx_port_num = 3; 673 break; 674 default: 675 /* Should never have loaded on this device */ 676 return -E1000_ERR_MAC_TYPE; 677 } 678 679 switch (hw->mac_type) { 680 case em_ich8lan: 681 case em_ich9lan: 682 case em_ich10lan: 683 case em_pchlan: 684 case em_pch2lan: 685 case em_pch_lpt: 686 case em_pch_spt: 687 case em_pch_cnp: 688 hw->swfwhw_semaphore_present = TRUE; 689 hw->asf_firmware_present = TRUE; 690 break; 691 case em_80003es2lan: 692 case em_82575: 693 case em_82576: 694 case em_82580: 695 case em_i210: 696 case em_i350: 697 hw->swfw_sync_present = TRUE; 698 /* FALLTHROUGH */ 699 case em_82571: 700 case em_82572: 701 case em_82573: 702 case em_82574: 703 hw->eeprom_semaphore_present = TRUE; 704 /* FALLTHROUGH */ 705 case em_82541: 706 case em_82547: 707 case em_82541_rev_2: 708 case em_82547_rev_2: 709 hw->asf_firmware_present = TRUE; 710 break; 711 default: 712 break; 713 } 714 715 return E1000_SUCCESS; 716 } 717 718 /***************************************************************************** 719 * Set media type and TBI compatibility. 720 * 721 * hw - Struct containing variables accessed by shared code 722 * **************************************************************************/ 723 void 724 em_set_media_type(struct em_hw *hw) 725 { 726 uint32_t status, ctrl_ext; 727 DEBUGFUNC("em_set_media_type"); 728 729 if (hw->mac_type != em_82543) { 730 /* tbi_compatibility is only valid on 82543 */ 731 hw->tbi_compatibility_en = FALSE; 732 } 733 734 if (hw->mac_type == em_82575 || hw->mac_type == em_82580 || 735 hw->mac_type == em_82576 || 736 hw->mac_type == em_i210 || hw->mac_type == em_i350) { 737 hw->media_type = em_media_type_copper; 738 739 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 740 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) { 741 case E1000_CTRL_EXT_LINK_MODE_SGMII: 742 ctrl_ext |= E1000_CTRL_I2C_ENA; 743 break; 744 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: 745 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES: 746 hw->media_type = em_media_type_internal_serdes; 747 ctrl_ext |= E1000_CTRL_I2C_ENA; 748 break; 749 default: 750 ctrl_ext &= ~E1000_CTRL_I2C_ENA; 751 break; 752 } 753 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 754 return; 755 } 756 757 switch (hw->device_id) { 758 case E1000_DEV_ID_82545GM_SERDES: 759 case E1000_DEV_ID_82546GB_SERDES: 760 case E1000_DEV_ID_82571EB_SERDES: 761 case E1000_DEV_ID_82571EB_SERDES_DUAL: 762 case E1000_DEV_ID_82571EB_SERDES_QUAD: 763 case E1000_DEV_ID_82572EI_SERDES: 764 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: 765 hw->media_type = em_media_type_internal_serdes; 766 break; 767 case E1000_DEV_ID_EP80579_LAN_1: 768 case E1000_DEV_ID_EP80579_LAN_2: 769 case E1000_DEV_ID_EP80579_LAN_3: 770 case E1000_DEV_ID_EP80579_LAN_4: 771 case E1000_DEV_ID_EP80579_LAN_5: 772 case E1000_DEV_ID_EP80579_LAN_6: 773 hw->media_type = em_media_type_copper; 774 break; 775 default: 776 switch (hw->mac_type) { 777 case em_82542_rev2_0: 778 case em_82542_rev2_1: 779 hw->media_type = em_media_type_fiber; 780 break; 781 case em_ich8lan: 782 case em_ich9lan: 783 case em_ich10lan: 784 case em_pchlan: 785 case em_pch2lan: 786 case em_pch_lpt: 787 case em_pch_spt: 788 case em_pch_cnp: 789 case em_82573: 790 case em_82574: 791 /* 792 * The STATUS_TBIMODE bit is reserved or reused for 793 * the this device. 794 */ 795 hw->media_type = em_media_type_copper; 796 break; 797 default: 798 status = E1000_READ_REG(hw, STATUS); 799 if (status & E1000_STATUS_TBIMODE) { 800 hw->media_type = em_media_type_fiber; 801 /* tbi_compatibility not valid on fiber */ 802 hw->tbi_compatibility_en = FALSE; 803 } else { 804 hw->media_type = em_media_type_copper; 805 } 806 break; 807 } 808 } 809 } 810 /****************************************************************************** 811 * Reset the transmit and receive units; mask and clear all interrupts. 812 * 813 * hw - Struct containing variables accessed by shared code 814 *****************************************************************************/ 815 int32_t 816 em_reset_hw(struct em_hw *hw) 817 { 818 uint32_t ctrl; 819 uint32_t ctrl_ext; 820 uint32_t icr; 821 uint32_t manc; 822 uint32_t led_ctrl; 823 uint32_t timeout; 824 uint32_t extcnf_ctrl; 825 int32_t ret_val; 826 DEBUGFUNC("em_reset_hw"); 827 828 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ 829 if (hw->mac_type == em_82542_rev2_0) { 830 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 831 em_pci_clear_mwi(hw); 832 } 833 if (hw->bus_type == em_bus_type_pci_express) { 834 /* 835 * Prevent the PCI-E bus from sticking if there is no TLP 836 * connection on the last TLP read/write transaction when MAC 837 * is reset. 838 */ 839 if (em_disable_pciex_master(hw) != E1000_SUCCESS) { 840 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 841 } 842 } 843 844 /* Set the completion timeout for 82575 chips */ 845 if (hw->mac_type == em_82575 || hw->mac_type == em_82580 || 846 hw->mac_type == em_82576 || 847 hw->mac_type == em_i210 || hw->mac_type == em_i350) { 848 ret_val = em_set_pciex_completion_timeout(hw); 849 if (ret_val) { 850 DEBUGOUT("PCI-E Set completion timeout has failed.\n"); 851 } 852 } 853 854 /* Clear interrupt mask to stop board from generating interrupts */ 855 DEBUGOUT("Masking off all interrupts\n"); 856 E1000_WRITE_REG(hw, IMC, 0xffffffff); 857 /* 858 * Disable the Transmit and Receive units. Then delay to allow any 859 * pending transactions to complete before we hit the MAC with the 860 * global reset. 861 */ 862 E1000_WRITE_REG(hw, RCTL, 0); 863 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP); 864 E1000_WRITE_FLUSH(hw); 865 /* 866 * The tbi_compatibility_on Flag must be cleared when Rctl is 867 * cleared. 868 */ 869 hw->tbi_compatibility_on = FALSE; 870 /* 871 * Delay to allow any outstanding PCI transactions to complete before 872 * resetting the device 873 */ 874 msec_delay(10); 875 876 ctrl = E1000_READ_REG(hw, CTRL); 877 878 /* Must reset the PHY before resetting the MAC */ 879 if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) { 880 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST)); 881 msec_delay(5); 882 } 883 /* 884 * Must acquire the MDIO ownership before MAC reset. Ownership 885 * defaults to firmware after a reset. 886 */ 887 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) { 888 timeout = 10; 889 890 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 891 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 892 893 do { 894 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); 895 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 896 897 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) 898 break; 899 else 900 extcnf_ctrl |= 901 E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 902 903 msec_delay(2); 904 timeout--; 905 } while (timeout); 906 } 907 /* Workaround for ICH8 bit corruption issue in FIFO memory */ 908 if (hw->mac_type == em_ich8lan) { 909 /* Set Tx and Rx buffer allocation to 8k apiece. */ 910 E1000_WRITE_REG(hw, PBA, E1000_PBA_8K); 911 /* Set Packet Buffer Size to 16k. */ 912 E1000_WRITE_REG(hw, PBS, E1000_PBS_16K); 913 } 914 /* 915 * Issue a global reset to the MAC. This will reset the chip's 916 * transmit, receive, DMA, and link units. It will not effect the 917 * current PCI configuration. The global reset bit is self- 918 * clearing, and should clear within a microsecond. 919 */ 920 DEBUGOUT("Issuing a global reset to MAC\n"); 921 922 switch (hw->mac_type) { 923 case em_82544: 924 case em_82540: 925 case em_82545: 926 case em_82546: 927 case em_82541: 928 case em_82541_rev_2: 929 /* 930 * These controllers can't ack the 64-bit write when issuing 931 * the reset, so use IO-mapping as a workaround to issue the 932 * reset 933 */ 934 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST)); 935 break; 936 case em_82545_rev_3: 937 case em_82546_rev_3: 938 /* Reset is performed on a shadow of the control register */ 939 E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST)); 940 break; 941 case em_ich8lan: 942 case em_ich9lan: 943 case em_ich10lan: 944 case em_pchlan: 945 case em_pch2lan: 946 case em_pch_lpt: 947 case em_pch_spt: 948 case em_pch_cnp: 949 if (!hw->phy_reset_disable && 950 em_check_phy_reset_block(hw) == E1000_SUCCESS) { 951 /* 952 * PHY HW reset requires MAC CORE reset at the same 953 * time to make sure the interface between MAC and 954 * the external PHY is reset. 955 */ 956 ctrl |= E1000_CTRL_PHY_RST; 957 /* 958 * Gate automatic PHY configuration by hardware on 959 * non-managed 82579 960 */ 961 if ((hw->mac_type == em_pch2lan) && 962 !(E1000_READ_REG(hw, FWSM) & E1000_FWSM_FW_VALID)) { 963 em_gate_hw_phy_config_ich8lan(hw, TRUE); 964 } 965 } 966 em_get_software_flag(hw); 967 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); 968 /* HW reset releases software_flag */ 969 hw->sw_flag = 0; 970 msec_delay(20); 971 972 /* Ungate automatic PHY configuration on non-managed 82579 */ 973 if (hw->mac_type == em_pch2lan && !hw->phy_reset_disable && 974 !(E1000_READ_REG(hw, FWSM) & E1000_FWSM_FW_VALID)) { 975 msec_delay(10); 976 em_gate_hw_phy_config_ich8lan(hw, FALSE); 977 } 978 break; 979 default: 980 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); 981 break; 982 } 983 984 if (em_check_phy_reset_block(hw) == E1000_SUCCESS) { 985 if (hw->mac_type == em_pchlan) { 986 ret_val = em_hv_phy_workarounds_ich8lan(hw); 987 if (ret_val) 988 return ret_val; 989 } 990 else if (hw->mac_type == em_pch2lan) { 991 ret_val = em_lv_phy_workarounds_ich8lan(hw); 992 if (ret_val) 993 return ret_val; 994 } 995 } 996 997 /* 998 * After MAC reset, force reload of EEPROM to restore power-on 999 * settings to device. Later controllers reload the EEPROM 1000 * automatically, so just wait for reload to complete. 1001 */ 1002 switch (hw->mac_type) { 1003 case em_82542_rev2_0: 1004 case em_82542_rev2_1: 1005 case em_82543: 1006 case em_82544: 1007 /* Wait for reset to complete */ 1008 usec_delay(10); 1009 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1010 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 1011 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1012 E1000_WRITE_FLUSH(hw); 1013 /* Wait for EEPROM reload */ 1014 msec_delay(2); 1015 break; 1016 case em_82541: 1017 case em_82541_rev_2: 1018 case em_82547: 1019 case em_82547_rev_2: 1020 /* Wait for EEPROM reload */ 1021 msec_delay(20); 1022 break; 1023 case em_82573: 1024 case em_82574: 1025 if (em_is_onboard_nvm_eeprom(hw) == FALSE) { 1026 usec_delay(10); 1027 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1028 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 1029 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1030 E1000_WRITE_FLUSH(hw); 1031 } 1032 /* FALLTHROUGH */ 1033 1034 /* Auto read done will delay 5ms or poll based on mac type */ 1035 ret_val = em_get_auto_rd_done(hw); 1036 if (ret_val) 1037 return ret_val; 1038 break; 1039 default: 1040 /* Wait for EEPROM reload (it happens automatically) */ 1041 msec_delay(5); 1042 break; 1043 } 1044 1045 /* Disable HW ARPs on ASF enabled adapters */ 1046 if (hw->mac_type >= em_82540 && hw->mac_type <= em_82547_rev_2 && 1047 hw->mac_type != em_icp_xxxx) { 1048 manc = E1000_READ_REG(hw, MANC); 1049 manc &= ~(E1000_MANC_ARP_EN); 1050 E1000_WRITE_REG(hw, MANC, manc); 1051 } 1052 if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) { 1053 em_phy_init_script(hw); 1054 1055 /* Configure activity LED after PHY reset */ 1056 led_ctrl = E1000_READ_REG(hw, LEDCTL); 1057 led_ctrl &= IGP_ACTIVITY_LED_MASK; 1058 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 1059 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 1060 } 1061 1062 /* 1063 * For PCH, this write will make sure that any noise 1064 * will be detected as a CRC error and be dropped rather than show up 1065 * as a bad packet to the DMA engine. 1066 */ 1067 if (hw->mac_type == em_pchlan) 1068 E1000_WRITE_REG(hw, CRC_OFFSET, 0x65656565); 1069 1070 /* Clear interrupt mask to stop board from generating interrupts */ 1071 DEBUGOUT("Masking off all interrupts\n"); 1072 E1000_WRITE_REG(hw, IMC, 0xffffffff); 1073 1074 /* Clear any pending interrupt events. */ 1075 icr = E1000_READ_REG(hw, ICR); 1076 1077 /* If MWI was previously enabled, reenable it. */ 1078 if (hw->mac_type == em_82542_rev2_0) { 1079 if (hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1080 em_pci_set_mwi(hw); 1081 } 1082 if (IS_ICH8(hw->mac_type)) { 1083 uint32_t kab = E1000_READ_REG(hw, KABGTXD); 1084 kab |= E1000_KABGTXD_BGSQLBIAS; 1085 E1000_WRITE_REG(hw, KABGTXD, kab); 1086 } 1087 1088 if (hw->mac_type == em_82580 || hw->mac_type == em_i350) { 1089 uint32_t mdicnfg; 1090 uint16_t nvm_data; 1091 1092 /* clear global device reset status bit */ 1093 EM_WRITE_REG(hw, E1000_STATUS, E1000_STATUS_DEV_RST_SET); 1094 1095 em_read_eeprom(hw, EEPROM_INIT_CONTROL3_PORT_A + 1096 NVM_82580_LAN_FUNC_OFFSET(hw->bus_func), 1, 1097 &nvm_data); 1098 1099 mdicnfg = EM_READ_REG(hw, E1000_MDICNFG); 1100 if (nvm_data & NVM_WORD24_EXT_MDIO) 1101 mdicnfg |= E1000_MDICNFG_EXT_MDIO; 1102 if (nvm_data & NVM_WORD24_COM_MDIO) 1103 mdicnfg |= E1000_MDICNFG_COM_MDIO; 1104 EM_WRITE_REG(hw, E1000_MDICNFG, mdicnfg); 1105 } 1106 1107 if (hw->mac_type == em_i210 || hw->mac_type == em_i350) 1108 em_set_eee_i350(hw); 1109 1110 return E1000_SUCCESS; 1111 } 1112 1113 /****************************************************************************** 1114 * 1115 * Initialize a number of hardware-dependent bits 1116 * 1117 * hw: Struct containing variables accessed by shared code 1118 * 1119 *****************************************************************************/ 1120 STATIC void 1121 em_initialize_hardware_bits(struct em_softc *sc) 1122 { 1123 struct em_hw *hw = &sc->hw; 1124 struct em_queue *que; 1125 1126 DEBUGFUNC("em_initialize_hardware_bits"); 1127 1128 if ((hw->mac_type >= em_82571) && (!hw->initialize_hw_bits_disable)) { 1129 /* Settings common to all silicon */ 1130 uint32_t reg_ctrl, reg_ctrl_ext; 1131 uint32_t reg_tarc0, reg_tarc1; 1132 uint32_t reg_tctl; 1133 uint32_t reg_txdctl; 1134 reg_tarc0 = E1000_READ_REG(hw, TARC0); 1135 reg_tarc0 &= ~0x78000000; /* Clear bits 30, 29, 28, and 1136 * 27 */ 1137 FOREACH_QUEUE(sc, que) { 1138 reg_txdctl = E1000_READ_REG(hw, TXDCTL(que->me)); 1139 reg_txdctl |= E1000_TXDCTL_COUNT_DESC; /* Set bit 22 */ 1140 E1000_WRITE_REG(hw, TXDCTL(que->me), reg_txdctl); 1141 } 1142 1143 /* 1144 * Old code always initialized queue 1, 1145 * even when unused, keep behaviour 1146 */ 1147 if (sc->num_queues == 1) { 1148 reg_txdctl = E1000_READ_REG(hw, TXDCTL(1)); 1149 reg_txdctl |= E1000_TXDCTL_COUNT_DESC; 1150 E1000_WRITE_REG(hw, TXDCTL(1), reg_txdctl); 1151 } 1152 1153 switch (hw->mac_type) { 1154 case em_82571: 1155 case em_82572: 1156 reg_tarc1 = E1000_READ_REG(hw, TARC1); 1157 reg_tctl = E1000_READ_REG(hw, TCTL); 1158 1159 /* Set the phy Tx compatible mode bits */ 1160 reg_tarc1 &= ~0x60000000; /* Clear bits 30 and 29 */ 1161 1162 reg_tarc0 |= 0x07800000; /* Set TARC0 bits 23-26 */ 1163 reg_tarc1 |= 0x07000000; /* Set TARC1 bits 24-26 */ 1164 1165 if (reg_tctl & E1000_TCTL_MULR) 1166 /* Clear bit 28 if MULR is 1b */ 1167 reg_tarc1 &= ~0x10000000; 1168 else 1169 /* Set bit 28 if MULR is 0b */ 1170 reg_tarc1 |= 0x10000000; 1171 1172 E1000_WRITE_REG(hw, TARC1, reg_tarc1); 1173 break; 1174 case em_82573: 1175 case em_82574: 1176 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1177 reg_ctrl = E1000_READ_REG(hw, CTRL); 1178 1179 reg_ctrl_ext &= ~0x00800000; /* Clear bit 23 */ 1180 reg_ctrl_ext |= 0x00400000; /* Set bit 22 */ 1181 reg_ctrl &= ~0x20000000; /* Clear bit 29 */ 1182 1183 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); 1184 E1000_WRITE_REG(hw, CTRL, reg_ctrl); 1185 break; 1186 case em_80003es2lan: 1187 if ((hw->media_type == em_media_type_fiber) || 1188 (hw->media_type == em_media_type_internal_serdes)) { 1189 /* Clear bit 20 */ 1190 reg_tarc0 &= ~0x00100000; 1191 } 1192 reg_tctl = E1000_READ_REG(hw, TCTL); 1193 reg_tarc1 = E1000_READ_REG(hw, TARC1); 1194 if (reg_tctl & E1000_TCTL_MULR) 1195 /* Clear bit 28 if MULR is 1b */ 1196 reg_tarc1 &= ~0x10000000; 1197 else 1198 /* Set bit 28 if MULR is 0b */ 1199 reg_tarc1 |= 0x10000000; 1200 1201 E1000_WRITE_REG(hw, TARC1, reg_tarc1); 1202 break; 1203 case em_ich8lan: 1204 case em_ich9lan: 1205 case em_ich10lan: 1206 case em_pchlan: 1207 case em_pch2lan: 1208 case em_pch_lpt: 1209 case em_pch_spt: 1210 case em_pch_cnp: 1211 if (hw->mac_type == em_ich8lan) 1212 /* Set TARC0 bits 29 and 28 */ 1213 reg_tarc0 |= 0x30000000; 1214 1215 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1216 reg_ctrl_ext |= 0x00400000; /* Set bit 22 */ 1217 /* Enable PHY low-power state when MAC is at D3 w/o WoL */ 1218 if (hw->mac_type >= em_pchlan) 1219 reg_ctrl_ext |= E1000_CTRL_EXT_PHYPDEN; 1220 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); 1221 1222 reg_tarc0 |= 0x0d800000; /* Set TARC0 bits 23, 1223 * 24, 26, 27 */ 1224 1225 reg_tarc1 = E1000_READ_REG(hw, TARC1); 1226 reg_tctl = E1000_READ_REG(hw, TCTL); 1227 1228 if (reg_tctl & E1000_TCTL_MULR) 1229 /* Clear bit 28 if MULR is 1b */ 1230 reg_tarc1 &= ~0x10000000; 1231 else 1232 /* Set bit 28 if MULR is 0b */ 1233 reg_tarc1 |= 0x10000000; 1234 1235 reg_tarc1 |= 0x45000000; /* Set bit 24, 26 and 1236 * 30 */ 1237 1238 E1000_WRITE_REG(hw, TARC1, reg_tarc1); 1239 break; 1240 default: 1241 break; 1242 } 1243 1244 E1000_WRITE_REG(hw, TARC0, reg_tarc0); 1245 } 1246 } 1247 1248 /** 1249 * e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value 1250 * @hw: pointer to the HW structure 1251 * 1252 * Toggling the LANPHYPC pin value fully power-cycles the PHY and is 1253 * used to reset the PHY to a quiescent state when necessary. 1254 **/ 1255 static void 1256 em_toggle_lanphypc_pch_lpt(struct em_hw *hw) 1257 { 1258 uint32_t mac_reg; 1259 1260 DEBUGFUNC("e1000_toggle_lanphypc_pch_lpt"); 1261 1262 /* Set Phy Config Counter to 50msec */ 1263 mac_reg = E1000_READ_REG(hw, FEXTNVM3); 1264 mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK; 1265 mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC; 1266 E1000_WRITE_REG(hw, FEXTNVM3, mac_reg); 1267 1268 /* Toggle LANPHYPC Value bit */ 1269 mac_reg = E1000_READ_REG(hw, CTRL); 1270 mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE; 1271 mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE; 1272 E1000_WRITE_REG(hw, CTRL, mac_reg); 1273 E1000_WRITE_FLUSH(hw); 1274 msec_delay(1); 1275 mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE; 1276 E1000_WRITE_REG(hw, CTRL, mac_reg); 1277 E1000_WRITE_FLUSH(hw); 1278 1279 if (hw->mac_type < em_pch_lpt) { 1280 msec_delay(50); 1281 } else { 1282 uint16_t count = 20; 1283 1284 do { 1285 msec_delay(5); 1286 } while (!(E1000_READ_REG(hw, CTRL_EXT) & 1287 E1000_CTRL_EXT_LPCD) && count--); 1288 1289 msec_delay(30); 1290 } 1291 } 1292 1293 /** 1294 * em_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP 1295 * @hw: pointer to the HW structure 1296 * @force: boolean indicating whether or not to force disabling ULP 1297 * 1298 * Un-configure ULP mode when link is up, the system is transitioned from 1299 * Sx or the driver is unloaded. If on a Manageability Engine (ME) enabled 1300 * system, poll for an indication from ME that ULP has been un-configured. 1301 * If not on an ME enabled system, un-configure the ULP mode by software. 1302 * 1303 * During nominal operation, this function is called when link is acquired 1304 * to disable ULP mode (force=FALSE); otherwise, for example when unloading 1305 * the driver or during Sx->S0 transitions, this is called with force=TRUE 1306 * to forcibly disable ULP. 1307 */ 1308 static int 1309 em_disable_ulp_lpt_lp(struct em_hw *hw, bool force) 1310 { 1311 int ret_val = E1000_SUCCESS; 1312 uint32_t mac_reg; 1313 uint16_t phy_reg; 1314 int i = 0; 1315 1316 if ((hw->mac_type < em_pch_lpt) || 1317 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) || 1318 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) || 1319 (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) || 1320 (hw->device_id == E1000_DEV_ID_PCH_I218_V2)) 1321 return 0; 1322 1323 if (E1000_READ_REG(hw, FWSM) & E1000_FWSM_FW_VALID) { 1324 if (force) { 1325 /* Request ME un-configure ULP mode in the PHY */ 1326 mac_reg = E1000_READ_REG(hw, H2ME); 1327 mac_reg &= ~E1000_H2ME_ULP; 1328 mac_reg |= E1000_H2ME_ENFORCE_SETTINGS; 1329 E1000_WRITE_REG(hw, H2ME, mac_reg); 1330 } 1331 1332 /* Poll up to 300msec for ME to clear ULP_CFG_DONE. */ 1333 while (E1000_READ_REG(hw, FWSM) & E1000_FWSM_ULP_CFG_DONE) { 1334 if (i++ == 30) { 1335 ret_val = -E1000_ERR_PHY; 1336 goto out; 1337 } 1338 1339 msec_delay(10); 1340 } 1341 DEBUGOUT1("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10); 1342 1343 if (force) { 1344 mac_reg = E1000_READ_REG(hw, H2ME); 1345 mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS; 1346 E1000_WRITE_REG(hw, H2ME, mac_reg); 1347 } else { 1348 /* Clear H2ME.ULP after ME ULP configuration */ 1349 mac_reg = E1000_READ_REG(hw, H2ME); 1350 mac_reg &= ~E1000_H2ME_ULP; 1351 E1000_WRITE_REG(hw, H2ME, mac_reg); 1352 } 1353 1354 goto out; 1355 } 1356 1357 ret_val = em_get_software_flag(hw); 1358 if (ret_val) 1359 goto out; 1360 1361 if (force) 1362 /* Toggle LANPHYPC Value bit */ 1363 em_toggle_lanphypc_pch_lpt(hw); 1364 1365 /* Unforce SMBus mode in PHY */ 1366 ret_val = em_read_phy_reg(hw, CV_SMB_CTRL, &phy_reg); 1367 if (ret_val) { 1368 /* The MAC might be in PCIe mode, so temporarily force to 1369 * SMBus mode in order to access the PHY. 1370 */ 1371 mac_reg = E1000_READ_REG(hw, CTRL_EXT); 1372 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS; 1373 E1000_WRITE_REG(hw, CTRL_EXT, mac_reg); 1374 1375 msec_delay(50); 1376 1377 ret_val = em_read_phy_reg(hw, CV_SMB_CTRL, &phy_reg); 1378 if (ret_val) 1379 goto release; 1380 } 1381 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS; 1382 em_write_phy_reg(hw, CV_SMB_CTRL, phy_reg); 1383 1384 /* Unforce SMBus mode in MAC */ 1385 mac_reg = E1000_READ_REG(hw, CTRL_EXT); 1386 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; 1387 E1000_WRITE_REG(hw, CTRL_EXT, mac_reg); 1388 1389 /* When ULP mode was previously entered, K1 was disabled by the 1390 * hardware. Re-Enable K1 in the PHY when exiting ULP. 1391 */ 1392 ret_val = em_read_phy_reg(hw, HV_PM_CTRL, &phy_reg); 1393 if (ret_val) 1394 goto release; 1395 phy_reg |= HV_PM_CTRL_K1_ENABLE; 1396 em_write_phy_reg(hw, HV_PM_CTRL, phy_reg); 1397 1398 /* Clear ULP enabled configuration */ 1399 ret_val = em_read_phy_reg(hw, I218_ULP_CONFIG1, &phy_reg); 1400 if (ret_val) 1401 goto release; 1402 phy_reg &= ~(I218_ULP_CONFIG1_IND | 1403 I218_ULP_CONFIG1_STICKY_ULP | 1404 I218_ULP_CONFIG1_RESET_TO_SMBUS | 1405 I218_ULP_CONFIG1_WOL_HOST | 1406 I218_ULP_CONFIG1_INBAND_EXIT | 1407 I218_ULP_CONFIG1_EN_ULP_LANPHYPC | 1408 I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST | 1409 I218_ULP_CONFIG1_DISABLE_SMB_PERST); 1410 em_write_phy_reg(hw, I218_ULP_CONFIG1, phy_reg); 1411 1412 /* Commit ULP changes by starting auto ULP configuration */ 1413 phy_reg |= I218_ULP_CONFIG1_START; 1414 em_write_phy_reg(hw, I218_ULP_CONFIG1, phy_reg); 1415 1416 /* Clear Disable SMBus Release on PERST# in MAC */ 1417 mac_reg = E1000_READ_REG(hw, FEXTNVM7); 1418 mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST; 1419 E1000_WRITE_REG(hw, FEXTNVM7, mac_reg); 1420 1421 release: 1422 em_release_software_flag(hw); 1423 if (force) { 1424 em_phy_reset(hw); 1425 msec_delay(50); 1426 } 1427 out: 1428 if (ret_val) 1429 DEBUGOUT1("Error in ULP disable flow: %d\n", ret_val); 1430 1431 return ret_val; 1432 } 1433 1434 /****************************************************************************** 1435 * Performs basic configuration of the adapter. 1436 * 1437 * hw - Struct containing variables accessed by shared code 1438 * 1439 * Assumes that the controller has previously been reset and is in a 1440 * post-reset uninitialized state. Initializes the receive address registers, 1441 * multicast table, and VLAN filter table. Calls routines to setup link 1442 * configuration and flow control settings. Clears all on-chip counters. Leaves 1443 * the transmit and receive units disabled and uninitialized. 1444 *****************************************************************************/ 1445 int32_t 1446 em_init_hw(struct em_softc *sc) 1447 { 1448 struct em_hw *hw = &sc->hw; 1449 struct em_queue *que; 1450 uint32_t ctrl; 1451 uint32_t i; 1452 int32_t ret_val; 1453 uint16_t pcix_cmd_word; 1454 uint16_t pcix_stat_hi_word; 1455 uint16_t cmd_mmrbc; 1456 uint16_t stat_mmrbc; 1457 uint32_t mta_size; 1458 uint32_t reg_data; 1459 uint32_t ctrl_ext; 1460 uint32_t snoop; 1461 uint32_t fwsm; 1462 DEBUGFUNC("em_init_hw"); 1463 1464 /* force full DMA clock frequency for ICH8 */ 1465 if (hw->mac_type == em_ich8lan) { 1466 reg_data = E1000_READ_REG(hw, STATUS); 1467 reg_data &= ~0x80000000; 1468 E1000_WRITE_REG(hw, STATUS, reg_data); 1469 } 1470 1471 if (hw->mac_type == em_pchlan || 1472 hw->mac_type == em_pch2lan || 1473 hw->mac_type == em_pch_lpt || 1474 hw->mac_type == em_pch_spt || 1475 hw->mac_type == em_pch_cnp) { 1476 /* 1477 * The MAC-PHY interconnect may still be in SMBus mode 1478 * after Sx->S0. Toggle the LANPHYPC Value bit to force 1479 * the interconnect to PCIe mode, but only if there is no 1480 * firmware present otherwise firmware will have done it. 1481 */ 1482 fwsm = E1000_READ_REG(hw, FWSM); 1483 if ((fwsm & E1000_FWSM_FW_VALID) == 0) { 1484 ctrl = E1000_READ_REG(hw, CTRL); 1485 ctrl |= E1000_CTRL_LANPHYPC_OVERRIDE; 1486 ctrl &= ~E1000_CTRL_LANPHYPC_VALUE; 1487 E1000_WRITE_REG(hw, CTRL, ctrl); 1488 usec_delay(10); 1489 ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE; 1490 E1000_WRITE_REG(hw, CTRL, ctrl); 1491 msec_delay(50); 1492 } 1493 1494 /* Gate automatic PHY configuration on non-managed 82579 */ 1495 if (hw->mac_type == em_pch2lan) 1496 em_gate_hw_phy_config_ich8lan(hw, TRUE); 1497 1498 em_disable_ulp_lpt_lp(hw, TRUE); 1499 /* 1500 * Reset the PHY before any acccess to it. Doing so, 1501 * ensures that the PHY is in a known good state before 1502 * we read/write PHY registers. The generic reset is 1503 * sufficient here, because we haven't determined 1504 * the PHY type yet. 1505 */ 1506 em_phy_reset(hw); 1507 1508 /* Ungate automatic PHY configuration on non-managed 82579 */ 1509 if (hw->mac_type == em_pch2lan && 1510 (fwsm & E1000_FWSM_FW_VALID) == 0) 1511 em_gate_hw_phy_config_ich8lan(hw, FALSE); 1512 1513 /* Set MDIO slow mode before any other MDIO access */ 1514 ret_val = em_set_mdio_slow_mode_hv(hw); 1515 if (ret_val) 1516 return ret_val; 1517 } 1518 1519 /* Initialize Identification LED */ 1520 ret_val = em_id_led_init(hw); 1521 if (ret_val) { 1522 DEBUGOUT("Error Initializing Identification LED\n"); 1523 return ret_val; 1524 } 1525 /* Set the media type and TBI compatibility */ 1526 em_set_media_type(hw); 1527 1528 /* Magic delay that improves problems with i219LM on HP Elitebook */ 1529 msec_delay(1); 1530 /* Must be called after em_set_media_type because media_type is used */ 1531 em_initialize_hardware_bits(sc); 1532 1533 /* Disabling VLAN filtering. */ 1534 DEBUGOUT("Initializing the IEEE VLAN\n"); 1535 /* VET hardcoded to standard value and VFTA removed in ICH8/ICH9 LAN */ 1536 if (!IS_ICH8(hw->mac_type)) { 1537 if (hw->mac_type < em_82545_rev_3) 1538 E1000_WRITE_REG(hw, VET, 0); 1539 if (hw->mac_type == em_i350) 1540 em_clear_vfta_i350(hw); 1541 else 1542 em_clear_vfta(hw); 1543 } 1544 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ 1545 if (hw->mac_type == em_82542_rev2_0) { 1546 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 1547 em_pci_clear_mwi(hw); 1548 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST); 1549 E1000_WRITE_FLUSH(hw); 1550 msec_delay(5); 1551 } 1552 /* 1553 * Setup the receive address. This involves initializing all of the 1554 * Receive Address Registers (RARs 0 - 15). 1555 */ 1556 em_init_rx_addrs(hw); 1557 1558 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI*/ 1559 if (hw->mac_type == em_82542_rev2_0) { 1560 E1000_WRITE_REG(hw, RCTL, 0); 1561 E1000_WRITE_FLUSH(hw); 1562 msec_delay(1); 1563 if (hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1564 em_pci_set_mwi(hw); 1565 } 1566 /* Zero out the Multicast HASH table */ 1567 DEBUGOUT("Zeroing the MTA\n"); 1568 mta_size = E1000_MC_TBL_SIZE; 1569 if (IS_ICH8(hw->mac_type)) 1570 mta_size = E1000_MC_TBL_SIZE_ICH8LAN; 1571 for (i = 0; i < mta_size; i++) { 1572 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 1573 /* 1574 * use write flush to prevent Memory Write Block (MWB) from 1575 * occuring when accessing our register space 1576 */ 1577 E1000_WRITE_FLUSH(hw); 1578 } 1579 /* 1580 * Set the PCI priority bit correctly in the CTRL register. This 1581 * determines if the adapter gives priority to receives, or if it 1582 * gives equal priority to transmits and receives. Valid only on 1583 * 82542 and 82543 silicon. 1584 */ 1585 if (hw->dma_fairness && hw->mac_type <= em_82543) { 1586 ctrl = E1000_READ_REG(hw, CTRL); 1587 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR); 1588 } 1589 switch (hw->mac_type) { 1590 case em_82545_rev_3: 1591 case em_82546_rev_3: 1592 break; 1593 default: 1594 /* 1595 * Workaround for PCI-X problem when BIOS sets MMRBC 1596 * incorrectly. 1597 */ 1598 if (hw->bus_type == em_bus_type_pcix) { 1599 em_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, 1600 &pcix_cmd_word); 1601 em_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, 1602 &pcix_stat_hi_word); 1603 cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) 1604 >> PCIX_COMMAND_MMRBC_SHIFT; 1605 stat_mmrbc = (pcix_stat_hi_word & 1606 PCIX_STATUS_HI_MMRBC_MASK) >> 1607 PCIX_STATUS_HI_MMRBC_SHIFT; 1608 1609 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) 1610 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; 1611 if (cmd_mmrbc > stat_mmrbc) { 1612 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK; 1613 pcix_cmd_word |= stat_mmrbc << 1614 PCIX_COMMAND_MMRBC_SHIFT; 1615 em_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, 1616 &pcix_cmd_word); 1617 } 1618 } 1619 break; 1620 } 1621 1622 /* More time needed for PHY to initialize */ 1623 if (IS_ICH8(hw->mac_type)) 1624 msec_delay(15); 1625 1626 /* 1627 * The 82578 Rx buffer will stall if wakeup is enabled in host and 1628 * the ME. Reading the BM_WUC register will clear the host wakeup bit. 1629 * Reset the phy after disabling host wakeup to reset the Rx buffer. 1630 */ 1631 if (hw->phy_type == em_phy_82578) { 1632 em_read_phy_reg(hw, PHY_REG(BM_WUC_PAGE, 1), 1633 (uint16_t *)®_data); 1634 ret_val = em_phy_reset(hw); 1635 if (ret_val) 1636 return ret_val; 1637 } 1638 1639 /* Call a subroutine to configure the link and setup flow control. */ 1640 ret_val = em_setup_link(hw); 1641 1642 /* Set the transmit descriptor write-back policy */ 1643 if (hw->mac_type > em_82544) { 1644 FOREACH_QUEUE(sc, que) { 1645 ctrl = E1000_READ_REG(hw, TXDCTL(que->me)); 1646 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | 1647 E1000_TXDCTL_FULL_TX_DESC_WB; 1648 E1000_WRITE_REG(hw, TXDCTL(que->me), ctrl); 1649 } 1650 } 1651 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) { 1652 em_enable_tx_pkt_filtering(hw); 1653 } 1654 switch (hw->mac_type) { 1655 default: 1656 break; 1657 case em_80003es2lan: 1658 /* Enable retransmit on late collisions */ 1659 reg_data = E1000_READ_REG(hw, TCTL); 1660 reg_data |= E1000_TCTL_RTLC; 1661 E1000_WRITE_REG(hw, TCTL, reg_data); 1662 1663 /* Configure Gigabit Carry Extend Padding */ 1664 reg_data = E1000_READ_REG(hw, TCTL_EXT); 1665 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK; 1666 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX; 1667 E1000_WRITE_REG(hw, TCTL_EXT, reg_data); 1668 1669 /* Configure Transmit Inter-Packet Gap */ 1670 reg_data = E1000_READ_REG(hw, TIPG); 1671 reg_data &= ~E1000_TIPG_IPGT_MASK; 1672 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; 1673 E1000_WRITE_REG(hw, TIPG, reg_data); 1674 1675 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001); 1676 reg_data &= ~0x00100000; 1677 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data); 1678 /* FALLTHROUGH */ 1679 case em_82571: 1680 case em_82572: 1681 case em_82575: 1682 case em_82576: 1683 case em_82580: 1684 case em_i210: 1685 case em_i350: 1686 case em_ich8lan: 1687 case em_ich9lan: 1688 case em_ich10lan: 1689 case em_pchlan: 1690 case em_pch2lan: 1691 case em_pch_lpt: 1692 case em_pch_spt: 1693 case em_pch_cnp: 1694 /* 1695 * Old code always initialized queue 1, 1696 * even when unused, keep behaviour 1697 */ 1698 if (sc->num_queues == 1) { 1699 ctrl = E1000_READ_REG(hw, TXDCTL(1)); 1700 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | 1701 E1000_TXDCTL_FULL_TX_DESC_WB; 1702 E1000_WRITE_REG(hw, TXDCTL(1), ctrl); 1703 } 1704 break; 1705 } 1706 1707 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) { 1708 uint32_t gcr = E1000_READ_REG(hw, GCR); 1709 gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; 1710 E1000_WRITE_REG(hw, GCR, gcr); 1711 } 1712 /* 1713 * Clear all of the statistics registers (clear on read). It is 1714 * important that we do this after we have tried to establish link 1715 * because the symbol error count will increment wildly if there is 1716 * no link. 1717 */ 1718 em_clear_hw_cntrs(hw); 1719 /* 1720 * ICH8 No-snoop bits are opposite polarity. Set to snoop by default 1721 * after reset. 1722 */ 1723 if (IS_ICH8(hw->mac_type)) { 1724 if (hw->mac_type == em_ich8lan) 1725 snoop = PCI_EX_82566_SNOOP_ALL; 1726 else 1727 snoop = (u_int32_t) ~ (PCI_EX_NO_SNOOP_ALL); 1728 1729 em_set_pci_ex_no_snoop(hw, snoop); 1730 } 1731 1732 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER || 1733 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) { 1734 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1735 /* 1736 * Relaxed ordering must be disabled to avoid a parity error 1737 * crash in a PCI slot. 1738 */ 1739 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 1740 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1741 } 1742 return ret_val; 1743 } 1744 1745 /****************************************************************************** 1746 * Adjust SERDES output amplitude based on EEPROM setting. 1747 * 1748 * hw - Struct containing variables accessed by shared code. 1749 *****************************************************************************/ 1750 static int32_t 1751 em_adjust_serdes_amplitude(struct em_hw *hw) 1752 { 1753 uint16_t eeprom_data; 1754 int32_t ret_val; 1755 DEBUGFUNC("em_adjust_serdes_amplitude"); 1756 1757 if (hw->media_type != em_media_type_internal_serdes || 1758 hw->mac_type >= em_82575) 1759 return E1000_SUCCESS; 1760 1761 switch (hw->mac_type) { 1762 case em_82545_rev_3: 1763 case em_82546_rev_3: 1764 break; 1765 default: 1766 return E1000_SUCCESS; 1767 } 1768 1769 ret_val = em_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data); 1770 if (ret_val) { 1771 return ret_val; 1772 } 1773 if (eeprom_data != EEPROM_RESERVED_WORD) { 1774 /* Adjust SERDES output amplitude only. */ 1775 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK; 1776 ret_val = em_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, 1777 eeprom_data); 1778 if (ret_val) 1779 return ret_val; 1780 } 1781 return E1000_SUCCESS; 1782 } 1783 1784 /****************************************************************************** 1785 * Configures flow control and link settings. 1786 * 1787 * hw - Struct containing variables accessed by shared code 1788 * 1789 * Determines which flow control settings to use. Calls the appropriate media- 1790 * specific link configuration function. Configures the flow control settings. 1791 * Assuming the adapter has a valid link partner, a valid link should be 1792 * established. Assumes the hardware has previously been reset and the 1793 * transmitter and receiver are not enabled. 1794 *****************************************************************************/ 1795 int32_t 1796 em_setup_link(struct em_hw *hw) 1797 { 1798 uint32_t ctrl_ext; 1799 int32_t ret_val; 1800 uint16_t eeprom_data; 1801 uint16_t eeprom_control2_reg_offset; 1802 DEBUGFUNC("em_setup_link"); 1803 1804 eeprom_control2_reg_offset = 1805 (hw->mac_type != em_icp_xxxx) 1806 ? EEPROM_INIT_CONTROL2_REG 1807 : EEPROM_INIT_CONTROL3_ICP_xxxx(hw->icp_xxxx_port_num); 1808 /* 1809 * In the case of the phy reset being blocked, we already have a 1810 * link. We do not have to set it up again. 1811 */ 1812 if (em_check_phy_reset_block(hw)) 1813 return E1000_SUCCESS; 1814 /* 1815 * Read and store word 0x0F of the EEPROM. This word contains bits 1816 * that determine the hardware's default PAUSE (flow control) mode, a 1817 * bit that determines whether the HW defaults to enabling or 1818 * disabling auto-negotiation, and the direction of the SW defined 1819 * pins. If there is no SW over-ride of the flow control setting, 1820 * then the variable hw->fc will be initialized based on a value in 1821 * the EEPROM. 1822 */ 1823 if (hw->fc == E1000_FC_DEFAULT) { 1824 switch (hw->mac_type) { 1825 case em_ich8lan: 1826 case em_ich9lan: 1827 case em_ich10lan: 1828 case em_pchlan: 1829 case em_pch2lan: 1830 case em_pch_lpt: 1831 case em_pch_spt: 1832 case em_pch_cnp: 1833 case em_82573: 1834 case em_82574: 1835 hw->fc = E1000_FC_FULL; 1836 break; 1837 default: 1838 ret_val = em_read_eeprom(hw, 1839 eeprom_control2_reg_offset, 1, &eeprom_data); 1840 if (ret_val) { 1841 DEBUGOUT("EEPROM Read Error\n"); 1842 return -E1000_ERR_EEPROM; 1843 } 1844 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0) 1845 hw->fc = E1000_FC_NONE; 1846 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 1847 EEPROM_WORD0F_ASM_DIR) 1848 hw->fc = E1000_FC_TX_PAUSE; 1849 else 1850 hw->fc = E1000_FC_FULL; 1851 break; 1852 } 1853 } 1854 /* 1855 * We want to save off the original Flow Control configuration just 1856 * in case we get disconnected and then reconnected into a different 1857 * hub or switch with different Flow Control capabilities. 1858 */ 1859 if (hw->mac_type == em_82542_rev2_0) 1860 hw->fc &= (~E1000_FC_TX_PAUSE); 1861 1862 if ((hw->mac_type < em_82543) && (hw->report_tx_early == 1)) 1863 hw->fc &= (~E1000_FC_RX_PAUSE); 1864 1865 hw->original_fc = hw->fc; 1866 1867 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc); 1868 /* 1869 * Take the 4 bits from EEPROM word 0x0F that determine the initial 1870 * polarity value for the SW controlled pins, and setup the Extended 1871 * Device Control reg with that info. This is needed because one of 1872 * the SW controlled pins is used for signal detection. So this 1873 * should be done before em_setup_pcs_link() or em_phy_setup() is 1874 * called. 1875 */ 1876 if (hw->mac_type == em_82543) { 1877 ret_val = em_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1878 1, &eeprom_data); 1879 if (ret_val) { 1880 DEBUGOUT("EEPROM Read Error\n"); 1881 return -E1000_ERR_EEPROM; 1882 } 1883 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << 1884 SWDPIO__EXT_SHIFT); 1885 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1886 } 1887 /* Make sure we have a valid PHY */ 1888 ret_val = em_detect_gig_phy(hw); 1889 if (ret_val) { 1890 DEBUGOUT("Error, did not detect valid phy.\n"); 1891 if (hw->mac_type == em_icp_xxxx) 1892 return E1000_DEFER_INIT; 1893 else 1894 return ret_val; 1895 } 1896 DEBUGOUT1("Phy ID = %x \n", hw->phy_id); 1897 1898 /* Call the necessary subroutine to configure the link. */ 1899 switch (hw->media_type) { 1900 case em_media_type_copper: 1901 case em_media_type_oem: 1902 ret_val = em_setup_copper_link(hw); 1903 break; 1904 default: 1905 ret_val = em_setup_fiber_serdes_link(hw); 1906 break; 1907 } 1908 /* 1909 * Initialize the flow control address, type, and PAUSE timer 1910 * registers to their default values. This is done even if flow 1911 * control is disabled, because it does not hurt anything to 1912 * initialize these registers. 1913 */ 1914 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n" 1915 ); 1916 1917 /* 1918 * FCAL/H and FCT are hardcoded to standard values in 1919 * em_ich8lan / em_ich9lan / em_ich10lan. 1920 */ 1921 if (!IS_ICH8(hw->mac_type)) { 1922 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE); 1923 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH); 1924 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW); 1925 } 1926 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time); 1927 1928 if (hw->phy_type == em_phy_82577 || 1929 hw->phy_type == em_phy_82578 || 1930 hw->phy_type == em_phy_82579 || 1931 hw->phy_type == em_phy_i217) { 1932 E1000_WRITE_REG(hw, FCRTV_PCH, 0x1000); 1933 em_write_phy_reg(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27), 1934 hw->fc_pause_time); 1935 } 1936 1937 /* 1938 * Set the flow control receive threshold registers. Normally, these 1939 * registers will be set to a default threshold that may be adjusted 1940 * later by the driver's runtime code. However, if the ability to 1941 * transmit pause frames in not enabled, then these registers will be 1942 * set to 0. 1943 */ 1944 if (!(hw->fc & E1000_FC_TX_PAUSE)) { 1945 E1000_WRITE_REG(hw, FCRTL, 0); 1946 E1000_WRITE_REG(hw, FCRTH, 0); 1947 } else { 1948 /* 1949 * We need to set up the Receive Threshold high and low water 1950 * marks as well as (optionally) enabling the transmission of 1951 * XON frames. 1952 */ 1953 if (hw->fc_send_xon) { 1954 E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water 1955 | E1000_FCRTL_XONE)); 1956 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); 1957 } else { 1958 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water); 1959 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); 1960 } 1961 } 1962 return ret_val; 1963 } 1964 1965 void 1966 em_power_up_serdes_link_82575(struct em_hw *hw) 1967 { 1968 uint32_t reg; 1969 1970 /* Enable PCS to turn on link */ 1971 reg = E1000_READ_REG(hw, PCS_CFG0); 1972 reg |= E1000_PCS_CFG_PCS_EN; 1973 E1000_WRITE_REG(hw, PCS_CFG0, reg); 1974 1975 /* Power up the laser */ 1976 reg = E1000_READ_REG(hw, CTRL_EXT); 1977 reg &= ~E1000_CTRL_EXT_SDP3_DATA; 1978 E1000_WRITE_REG(hw, CTRL_EXT, reg); 1979 1980 /* flush the write to verify completion */ 1981 E1000_WRITE_FLUSH(hw); 1982 delay(5); 1983 } 1984 1985 /****************************************************************************** 1986 * Sets up link for a fiber based or serdes based adapter 1987 * 1988 * hw - Struct containing variables accessed by shared code 1989 * 1990 * Manipulates Physical Coding Sublayer functions in order to configure 1991 * link. Assumes the hardware has been previously reset and the transmitter 1992 * and receiver are not enabled. 1993 *****************************************************************************/ 1994 static int32_t 1995 em_setup_fiber_serdes_link(struct em_hw *hw) 1996 { 1997 uint32_t ctrl, ctrl_ext, reg; 1998 uint32_t status; 1999 uint32_t txcw = 0; 2000 uint32_t i; 2001 uint32_t signal = 0; 2002 int32_t ret_val; 2003 DEBUGFUNC("em_setup_fiber_serdes_link"); 2004 /* 2005 * On 82571 and 82572 Fiber connections, SerDes loopback mode 2006 * persists until explicitly turned off or a power cycle is 2007 * performed. A read to the register does not indicate its status. 2008 * Therefore, we ensure loopback mode is disabled during 2009 * initialization. 2010 */ 2011 if (hw->mac_type == em_82571 || hw->mac_type == em_82572 || 2012 hw->mac_type >= em_82575) 2013 E1000_WRITE_REG(hw, SCTL, E1000_DISABLE_SERDES_LOOPBACK); 2014 2015 if (hw->mac_type >= em_82575) 2016 em_power_up_serdes_link_82575(hw); 2017 2018 /* 2019 * On adapters with a MAC newer than 82544, SWDP 1 will be set when 2020 * the optics detect a signal. On older adapters, it will be cleared 2021 * when there is a signal. This applies to fiber media only. If 2022 * we're on serdes media, adjust the output amplitude to value set in 2023 * the EEPROM. 2024 */ 2025 ctrl = E1000_READ_REG(hw, CTRL); 2026 if (hw->media_type == em_media_type_fiber) 2027 signal = (hw->mac_type > em_82544) ? E1000_CTRL_SWDPIN1 : 0; 2028 2029 ret_val = em_adjust_serdes_amplitude(hw); 2030 if (ret_val) 2031 return ret_val; 2032 2033 /* Take the link out of reset */ 2034 ctrl &= ~(E1000_CTRL_LRST); 2035 2036 if (hw->mac_type >= em_82575) { 2037 /* set both sw defined pins on 82575/82576*/ 2038 ctrl |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1; 2039 2040 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 2041 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) { 2042 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: 2043 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES: 2044 /* the backplane is always connected */ 2045 reg = E1000_READ_REG(hw, PCS_LCTL); 2046 reg |= E1000_PCS_LCTL_FORCE_FCTRL; 2047 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL; 2048 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */ 2049 DEBUGOUT("Configuring Forced Link\n"); 2050 E1000_WRITE_REG(hw, PCS_LCTL, reg); 2051 em_force_mac_fc(hw); 2052 hw->autoneg_failed = 0; 2053 return E1000_SUCCESS; 2054 break; 2055 default: 2056 /* Set switch control to serdes energy detect */ 2057 reg = E1000_READ_REG(hw, CONNSW); 2058 reg |= E1000_CONNSW_ENRGSRC; 2059 E1000_WRITE_REG(hw, CONNSW, reg); 2060 break; 2061 } 2062 } 2063 2064 /* Adjust VCO speed to improve BER performance */ 2065 ret_val = em_set_vco_speed(hw); 2066 if (ret_val) 2067 return ret_val; 2068 2069 em_config_collision_dist(hw); 2070 /* 2071 * Check for a software override of the flow control settings, and 2072 * setup the device accordingly. If auto-negotiation is enabled, 2073 * then software will have to set the "PAUSE" bits to the correct 2074 * value in the Tranmsit Config Word Register (TXCW) and re-start 2075 * auto-negotiation. However, if auto-negotiation is disabled, then 2076 * software will have to manually configure the two flow control 2077 * enable bits in the CTRL register. 2078 * 2079 * The possible values of the "fc" parameter are: 0: Flow control is 2080 * completely disabled 1: Rx flow control is enabled (we can receive 2081 * pause frames, but not send pause frames). 2: Tx flow control is 2082 * enabled (we can send pause frames but we do not support receiving 2083 * pause frames). 3: Both Rx and TX flow control (symmetric) are 2084 * enabled. 2085 */ 2086 switch (hw->fc) { 2087 case E1000_FC_NONE: 2088 /* 2089 * Flow control is completely disabled by a software 2090 * over-ride. 2091 */ 2092 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 2093 break; 2094 case E1000_FC_RX_PAUSE: 2095 /* 2096 * RX Flow control is enabled and TX Flow control is disabled 2097 * by a software over-ride. Since there really isn't a way to 2098 * advertise that we are capable of RX Pause ONLY, we will 2099 * advertise that we support both symmetric and asymmetric RX 2100 * PAUSE. Later, we will disable the adapter's ability to 2101 * send PAUSE frames. 2102 */ 2103 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | 2104 E1000_TXCW_PAUSE_MASK); 2105 break; 2106 case E1000_FC_TX_PAUSE: 2107 /* 2108 * TX Flow control is enabled, and RX Flow control is 2109 * disabled, by a software over-ride. 2110 */ 2111 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 2112 break; 2113 case E1000_FC_FULL: 2114 /* 2115 * Flow control (both RX and TX) is enabled by a software 2116 * over-ride. 2117 */ 2118 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | 2119 E1000_TXCW_PAUSE_MASK); 2120 break; 2121 default: 2122 DEBUGOUT("Flow control param set incorrectly\n"); 2123 return -E1000_ERR_CONFIG; 2124 break; 2125 } 2126 /* 2127 * Since auto-negotiation is enabled, take the link out of reset (the 2128 * link will be in reset, because we previously reset the chip). This 2129 * will restart auto-negotiation. If auto-neogtiation is successful 2130 * then the link-up status bit will be set and the flow control 2131 * enable bits (RFCE and TFCE) will be set according to their 2132 * negotiated value. 2133 */ 2134 DEBUGOUT("Auto-negotiation enabled\n"); 2135 2136 E1000_WRITE_REG(hw, TXCW, txcw); 2137 E1000_WRITE_REG(hw, CTRL, ctrl); 2138 E1000_WRITE_FLUSH(hw); 2139 2140 hw->txcw = txcw; 2141 msec_delay(1); 2142 /* 2143 * If we have a signal (the cable is plugged in) then poll for a 2144 * "Link-Up" indication in the Device Status Register. Time-out if a 2145 * link isn't seen in 500 milliseconds seconds (Auto-negotiation 2146 * should complete in less than 500 milliseconds even if the other 2147 * end is doing it in SW). For internal serdes, we just assume a 2148 * signal is present, then poll. 2149 */ 2150 if (hw->media_type == em_media_type_internal_serdes || 2151 (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) { 2152 DEBUGOUT("Looking for Link\n"); 2153 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) { 2154 msec_delay(10); 2155 status = E1000_READ_REG(hw, STATUS); 2156 if (status & E1000_STATUS_LU) 2157 break; 2158 } 2159 if (i == (LINK_UP_TIMEOUT / 10)) { 2160 DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 2161 hw->autoneg_failed = 1; 2162 /* 2163 * AutoNeg failed to achieve a link, so we'll call 2164 * em_check_for_link. This routine will force the 2165 * link up if we detect a signal. This will allow us 2166 * to communicate with non-autonegotiating link 2167 * partners. 2168 */ 2169 ret_val = em_check_for_link(hw); 2170 if (ret_val) { 2171 DEBUGOUT("Error while checking for link\n"); 2172 return ret_val; 2173 } 2174 hw->autoneg_failed = 0; 2175 } else { 2176 hw->autoneg_failed = 0; 2177 DEBUGOUT("Valid Link Found\n"); 2178 } 2179 } else { 2180 DEBUGOUT("No Signal Detected\n"); 2181 } 2182 return E1000_SUCCESS; 2183 } 2184 2185 /****************************************************************************** 2186 * Make sure we have a valid PHY and change PHY mode before link setup. 2187 * 2188 * hw - Struct containing variables accessed by shared code 2189 *****************************************************************************/ 2190 static int32_t 2191 em_copper_link_preconfig(struct em_hw *hw) 2192 { 2193 uint32_t ctrl; 2194 int32_t ret_val; 2195 uint16_t phy_data; 2196 DEBUGFUNC("em_copper_link_preconfig"); 2197 2198 ctrl = E1000_READ_REG(hw, CTRL); 2199 /* 2200 * With 82543, we need to force speed and duplex on the MAC equal to 2201 * what the PHY speed and duplex configuration is. In addition, we 2202 * need to perform a hardware reset on the PHY to take it out of 2203 * reset. 2204 */ 2205 if (hw->mac_type > em_82543) { 2206 ctrl |= E1000_CTRL_SLU; 2207 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 2208 E1000_WRITE_REG(hw, CTRL, ctrl); 2209 } else { 2210 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | 2211 E1000_CTRL_SLU); 2212 E1000_WRITE_REG(hw, CTRL, ctrl); 2213 ret_val = em_phy_hw_reset(hw); 2214 if (ret_val) 2215 return ret_val; 2216 } 2217 2218 /* Set PHY to class A mode (if necessary) */ 2219 ret_val = em_set_phy_mode(hw); 2220 if (ret_val) 2221 return ret_val; 2222 2223 if ((hw->mac_type == em_82545_rev_3) || 2224 (hw->mac_type == em_82546_rev_3)) { 2225 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 2226 &phy_data); 2227 phy_data |= 0x00000008; 2228 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 2229 phy_data); 2230 } 2231 if (hw->mac_type <= em_82543 || 2232 hw->mac_type == em_82541 || hw->mac_type == em_82547 || 2233 hw->mac_type == em_82541_rev_2 || hw->mac_type == em_82547_rev_2) 2234 hw->phy_reset_disable = FALSE; 2235 2236 return E1000_SUCCESS; 2237 } 2238 2239 /****************************************************************************** 2240 * Copper link setup for em_phy_igp series. 2241 * 2242 * hw - Struct containing variables accessed by shared code 2243 *****************************************************************************/ 2244 static int32_t 2245 em_copper_link_igp_setup(struct em_hw *hw) 2246 { 2247 uint32_t led_ctrl; 2248 int32_t ret_val; 2249 uint16_t phy_data; 2250 DEBUGFUNC("em_copper_link_igp_setup"); 2251 2252 if (hw->phy_reset_disable) 2253 return E1000_SUCCESS; 2254 2255 ret_val = em_phy_reset(hw); 2256 if (ret_val) { 2257 DEBUGOUT("Error Resetting the PHY\n"); 2258 return ret_val; 2259 } 2260 /* Wait 15ms for MAC to configure PHY from eeprom settings */ 2261 msec_delay(15); 2262 if (hw->mac_type != em_ich8lan && 2263 hw->mac_type != em_ich9lan && 2264 hw->mac_type != em_ich10lan) { 2265 /* Configure activity LED after PHY reset */ 2266 led_ctrl = E1000_READ_REG(hw, LEDCTL); 2267 led_ctrl &= IGP_ACTIVITY_LED_MASK; 2268 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 2269 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 2270 } 2271 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */ 2272 if (hw->phy_type == em_phy_igp) { 2273 /* disable lplu d3 during driver init */ 2274 ret_val = em_set_d3_lplu_state(hw, FALSE); 2275 if (ret_val) { 2276 DEBUGOUT("Error Disabling LPLU D3\n"); 2277 return ret_val; 2278 } 2279 } 2280 /* disable lplu d0 during driver init */ 2281 if (hw->mac_type == em_pchlan || 2282 hw->mac_type == em_pch2lan || 2283 hw->mac_type == em_pch_lpt || 2284 hw->mac_type == em_pch_spt || 2285 hw->mac_type == em_pch_cnp) 2286 ret_val = em_set_lplu_state_pchlan(hw, FALSE); 2287 else 2288 ret_val = em_set_d0_lplu_state(hw, FALSE); 2289 if (ret_val) { 2290 DEBUGOUT("Error Disabling LPLU D0\n"); 2291 return ret_val; 2292 } 2293 /* Configure mdi-mdix settings */ 2294 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 2295 if (ret_val) 2296 return ret_val; 2297 2298 if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) { 2299 hw->dsp_config_state = em_dsp_config_disabled; 2300 /* Force MDI for earlier revs of the IGP PHY */ 2301 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | 2302 IGP01E1000_PSCR_FORCE_MDI_MDIX); 2303 hw->mdix = 1; 2304 2305 } else { 2306 hw->dsp_config_state = em_dsp_config_enabled; 2307 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 2308 2309 switch (hw->mdix) { 2310 case 1: 2311 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 2312 break; 2313 case 2: 2314 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; 2315 break; 2316 case 0: 2317 default: 2318 phy_data |= IGP01E1000_PSCR_AUTO_MDIX; 2319 break; 2320 } 2321 } 2322 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 2323 if (ret_val) 2324 return ret_val; 2325 2326 /* set auto-master slave resolution settings */ 2327 if (hw->autoneg) { 2328 em_ms_type phy_ms_setting = hw->master_slave; 2329 if (hw->ffe_config_state == em_ffe_config_active) 2330 hw->ffe_config_state = em_ffe_config_enabled; 2331 2332 if (hw->dsp_config_state == em_dsp_config_activated) 2333 hw->dsp_config_state = em_dsp_config_enabled; 2334 /* 2335 * when autonegotiation advertisement is only 1000Mbps then 2336 * we should disable SmartSpeed and enable Auto MasterSlave 2337 * resolution as hardware default. 2338 */ 2339 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) { 2340 /* Disable SmartSpeed */ 2341 ret_val = em_read_phy_reg(hw, 2342 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2343 if (ret_val) 2344 return ret_val; 2345 2346 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2347 ret_val = em_write_phy_reg(hw, 2348 IGP01E1000_PHY_PORT_CONFIG, phy_data); 2349 if (ret_val) 2350 return ret_val; 2351 /* Set auto Master/Slave resolution process */ 2352 ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, 2353 &phy_data); 2354 if (ret_val) 2355 return ret_val; 2356 2357 phy_data &= ~CR_1000T_MS_ENABLE; 2358 ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL, 2359 phy_data); 2360 if (ret_val) 2361 return ret_val; 2362 } 2363 ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); 2364 if (ret_val) 2365 return ret_val; 2366 2367 /* load defaults for future use */ 2368 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ? 2369 ((phy_data & CR_1000T_MS_VALUE) ? em_ms_force_master : 2370 em_ms_force_slave) : em_ms_auto; 2371 2372 switch (phy_ms_setting) { 2373 case em_ms_force_master: 2374 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 2375 break; 2376 case em_ms_force_slave: 2377 phy_data |= CR_1000T_MS_ENABLE; 2378 phy_data &= ~(CR_1000T_MS_VALUE); 2379 break; 2380 case em_ms_auto: 2381 phy_data &= ~CR_1000T_MS_ENABLE; 2382 break; 2383 default: 2384 break; 2385 } 2386 ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); 2387 if (ret_val) 2388 return ret_val; 2389 } 2390 return E1000_SUCCESS; 2391 } 2392 2393 /****************************************************************************** 2394 * Copper link setup for em_phy_gg82563 series. 2395 * 2396 * hw - Struct containing variables accessed by shared code 2397 *****************************************************************************/ 2398 static int32_t 2399 em_copper_link_ggp_setup(struct em_hw *hw) 2400 { 2401 int32_t ret_val; 2402 uint16_t phy_data; 2403 uint32_t reg_data; 2404 DEBUGFUNC("em_copper_link_ggp_setup"); 2405 2406 if (!hw->phy_reset_disable) { 2407 2408 /* Enable CRS on TX for half-duplex operation. */ 2409 ret_val = em_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 2410 &phy_data); 2411 if (ret_val) 2412 return ret_val; 2413 2414 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 2415 /* Use 25MHz for both link down and 1000BASE-T for Tx clock */ 2416 phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ; 2417 2418 ret_val = em_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 2419 phy_data); 2420 if (ret_val) 2421 return ret_val; 2422 /* 2423 * Options: MDI/MDI-X = 0 (default) 0 - Auto for all speeds 1 2424 * - MDI mode 2 - MDI-X mode 3 - Auto for 1000Base-T only 2425 * (MDI-X for 10/100Base-T modes) 2426 */ 2427 ret_val = em_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, 2428 &phy_data); 2429 2430 if (ret_val) 2431 return ret_val; 2432 2433 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK; 2434 2435 switch (hw->mdix) { 2436 case 1: 2437 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI; 2438 break; 2439 case 2: 2440 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX; 2441 break; 2442 case 0: 2443 default: 2444 phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO; 2445 break; 2446 } 2447 /* 2448 * Options: disable_polarity_correction = 0 (default) 2449 * Automatic Correction for Reversed Cable Polarity 0 - 2450 * Disabled 1 - Enabled 2451 */ 2452 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 2453 if (hw->disable_polarity_correction == 1) 2454 phy_data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 2455 ret_val = em_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, 2456 phy_data); 2457 2458 if (ret_val) 2459 return ret_val; 2460 2461 /* SW Reset the PHY so all changes take effect */ 2462 ret_val = em_phy_reset(hw); 2463 if (ret_val) { 2464 DEBUGOUT("Error Resetting the PHY\n"); 2465 return ret_val; 2466 } 2467 } /* phy_reset_disable */ 2468 if (hw->mac_type == em_80003es2lan) { 2469 /* Bypass RX and TX FIFO's */ 2470 ret_val = em_write_kmrn_reg(hw, 2471 E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL, 2472 E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS | 2473 E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS); 2474 if (ret_val) 2475 return ret_val; 2476 2477 ret_val = em_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, 2478 &phy_data); 2479 if (ret_val) 2480 return ret_val; 2481 2482 phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG; 2483 ret_val = em_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, 2484 phy_data); 2485 2486 if (ret_val) 2487 return ret_val; 2488 2489 reg_data = E1000_READ_REG(hw, CTRL_EXT); 2490 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK); 2491 E1000_WRITE_REG(hw, CTRL_EXT, reg_data); 2492 2493 ret_val = em_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, 2494 &phy_data); 2495 if (ret_val) 2496 return ret_val; 2497 /* 2498 * Do not init these registers when the HW is in IAMT mode, 2499 * since the firmware will have already initialized them. We 2500 * only initialize them if the HW is not in IAMT mode. 2501 */ 2502 if (em_check_mng_mode(hw) == FALSE) { 2503 /* Enable Electrical Idle on the PHY */ 2504 phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; 2505 ret_val = em_write_phy_reg(hw, 2506 GG82563_PHY_PWR_MGMT_CTRL, phy_data); 2507 if (ret_val) 2508 return ret_val; 2509 2510 ret_val = em_read_phy_reg(hw, 2511 GG82563_PHY_KMRN_MODE_CTRL, &phy_data); 2512 if (ret_val) 2513 return ret_val; 2514 2515 phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 2516 ret_val = em_write_phy_reg(hw, 2517 GG82563_PHY_KMRN_MODE_CTRL, phy_data); 2518 2519 if (ret_val) 2520 return ret_val; 2521 } 2522 /* 2523 * Workaround: Disable padding in Kumeran interface in the 2524 * MAC and in the PHY to avoid CRC errors. 2525 */ 2526 ret_val = em_read_phy_reg(hw, GG82563_PHY_INBAND_CTRL, 2527 &phy_data); 2528 if (ret_val) 2529 return ret_val; 2530 phy_data |= GG82563_ICR_DIS_PADDING; 2531 ret_val = em_write_phy_reg(hw, GG82563_PHY_INBAND_CTRL, 2532 phy_data); 2533 if (ret_val) 2534 return ret_val; 2535 } 2536 return E1000_SUCCESS; 2537 } 2538 2539 /****************************************************************************** 2540 * Copper link setup for em_phy_m88 series. 2541 * 2542 * hw - Struct containing variables accessed by shared code 2543 *****************************************************************************/ 2544 static int32_t 2545 em_copper_link_mgp_setup(struct em_hw *hw) 2546 { 2547 int32_t ret_val; 2548 uint16_t phy_data; 2549 DEBUGFUNC("em_copper_link_mgp_setup"); 2550 2551 if (hw->phy_reset_disable) 2552 return E1000_SUCCESS; 2553 2554 /* disable lplu d0 during driver init */ 2555 if (hw->mac_type == em_pchlan || 2556 hw->mac_type == em_pch2lan || 2557 hw->mac_type == em_pch_lpt || 2558 hw->mac_type == em_pch_spt || 2559 hw->mac_type == em_pch_cnp) 2560 ret_val = em_set_lplu_state_pchlan(hw, FALSE); 2561 2562 /* Enable CRS on TX. This must be set for half-duplex operation. */ 2563 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 2564 if (ret_val) 2565 return ret_val; 2566 2567 if (hw->phy_id == M88E1141_E_PHY_ID) { 2568 phy_data |= 0x00000008; 2569 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 2570 phy_data); 2571 if (ret_val) 2572 return ret_val; 2573 2574 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 2575 &phy_data); 2576 if (ret_val) 2577 return ret_val; 2578 2579 phy_data &= ~M88E1000_PSCR_ASSERT_CRS_ON_TX; 2580 2581 } 2582 /* For BM PHY this bit is downshift enable */ 2583 else if (hw->phy_type != em_phy_bm) 2584 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 2585 /* 2586 * Options: MDI/MDI-X = 0 (default) 0 - Auto for all speeds 1 - MDI 2587 * mode 2 - MDI-X mode 3 - Auto for 1000Base-T only (MDI-X for 2588 * 10/100Base-T modes) 2589 */ 2590 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 2591 2592 switch (hw->mdix) { 2593 case 1: 2594 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 2595 break; 2596 case 2: 2597 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 2598 break; 2599 case 3: 2600 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 2601 break; 2602 case 0: 2603 default: 2604 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 2605 break; 2606 } 2607 /* 2608 * Options: disable_polarity_correction = 0 (default) Automatic 2609 * Correction for Reversed Cable Polarity 0 - Disabled 1 - Enabled 2610 */ 2611 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 2612 if (hw->disable_polarity_correction == 1) 2613 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 2614 2615 /* Enable downshift on BM (disabled by default) */ 2616 if (hw->phy_type == em_phy_bm) 2617 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT; 2618 2619 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 2620 if (ret_val) 2621 return ret_val; 2622 2623 if (((hw->phy_type == em_phy_m88) && 2624 (hw->phy_revision < M88E1011_I_REV_4) && 2625 (hw->phy_id != BME1000_E_PHY_ID)) || 2626 (hw->phy_type == em_phy_oem)) { 2627 /* 2628 * Force TX_CLK in the Extended PHY Specific Control Register 2629 * to 25MHz clock. 2630 */ 2631 ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 2632 &phy_data); 2633 if (ret_val) 2634 return ret_val; 2635 2636 if (hw->phy_type == em_phy_oem) { 2637 phy_data |= M88E1000_EPSCR_TX_TIME_CTRL; 2638 phy_data |= M88E1000_EPSCR_RX_TIME_CTRL; 2639 } 2640 phy_data |= M88E1000_EPSCR_TX_CLK_25; 2641 2642 if ((hw->phy_revision == E1000_REVISION_2) && 2643 (hw->phy_id == M88E1111_I_PHY_ID)) { 2644 /* Vidalia Phy, set the downshift counter to 5x */ 2645 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK); 2646 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; 2647 ret_val = em_write_phy_reg(hw, 2648 M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 2649 if (ret_val) 2650 return ret_val; 2651 } else { 2652 /* Configure Master and Slave downshift values */ 2653 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 2654 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 2655 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 2656 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 2657 ret_val = em_write_phy_reg(hw, 2658 M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 2659 if (ret_val) 2660 return ret_val; 2661 } 2662 } 2663 if ((hw->phy_type == em_phy_bm) && (hw->phy_revision == 1)) { 2664 /* 2665 * Set PHY page 0, register 29 to 0x0003 2666 * The next two writes are supposed to lower BER for gig 2667 * conection 2668 */ 2669 ret_val = em_write_phy_reg(hw, BM_REG_BIAS1, 0x0003); 2670 if (ret_val) 2671 return ret_val; 2672 2673 /* Set PHY page 0, register 30 to 0x0000 */ 2674 ret_val = em_write_phy_reg(hw, BM_REG_BIAS2, 0x0000); 2675 if (ret_val) 2676 return ret_val; 2677 } 2678 if (hw->phy_type == em_phy_82578) { 2679 ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 2680 &phy_data); 2681 if (ret_val) 2682 return ret_val; 2683 2684 /* 82578 PHY - set the downshift count to 1x. */ 2685 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE; 2686 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK; 2687 ret_val = em_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 2688 phy_data); 2689 if (ret_val) 2690 return ret_val; 2691 } 2692 /* SW Reset the PHY so all changes take effect */ 2693 ret_val = em_phy_reset(hw); 2694 if (ret_val) { 2695 DEBUGOUT("Error Resetting the PHY\n"); 2696 return ret_val; 2697 } 2698 return E1000_SUCCESS; 2699 } 2700 2701 /****************************************************************************** 2702 * Copper link setup for em_phy_82577 series. 2703 * 2704 * hw - Struct containing variables accessed by shared code 2705 *****************************************************************************/ 2706 static int32_t 2707 em_copper_link_82577_setup(struct em_hw *hw) 2708 { 2709 int32_t ret_val; 2710 uint16_t phy_data; 2711 uint32_t led_ctl; 2712 DEBUGFUNC("em_copper_link_82577_setup"); 2713 2714 if (hw->phy_reset_disable) 2715 return E1000_SUCCESS; 2716 2717 /* Enable CRS on TX for half-duplex operation. */ 2718 ret_val = em_read_phy_reg(hw, I82577_PHY_CFG_REG, &phy_data); 2719 if (ret_val) 2720 return ret_val; 2721 2722 phy_data |= I82577_PHY_CFG_ENABLE_CRS_ON_TX | 2723 I82577_PHY_CFG_ENABLE_DOWNSHIFT; 2724 2725 ret_val = em_write_phy_reg(hw, I82577_PHY_CFG_REG, phy_data); 2726 if (ret_val) 2727 return ret_val; 2728 2729 /* Wait 15ms for MAC to configure PHY from eeprom settings */ 2730 msec_delay(15); 2731 led_ctl = hw->ledctl_mode1; 2732 2733 /* disable lplu d0 during driver init */ 2734 ret_val = em_set_lplu_state_pchlan(hw, FALSE); 2735 if (ret_val) { 2736 DEBUGOUT("Error Disabling LPLU D0\n"); 2737 return ret_val; 2738 } 2739 2740 E1000_WRITE_REG(hw, LEDCTL, led_ctl); 2741 2742 return E1000_SUCCESS; 2743 } 2744 2745 static int32_t 2746 em_copper_link_82580_setup(struct em_hw *hw) 2747 { 2748 int32_t ret_val; 2749 uint16_t phy_data; 2750 2751 if (hw->phy_reset_disable) 2752 return E1000_SUCCESS; 2753 2754 ret_val = em_phy_reset(hw); 2755 if (ret_val) 2756 goto out; 2757 2758 /* Enable CRS on TX. This must be set for half-duplex operation. */ 2759 ret_val = em_read_phy_reg(hw, I82580_CFG_REG, &phy_data); 2760 if (ret_val) 2761 goto out; 2762 2763 phy_data |= I82580_CFG_ASSERT_CRS_ON_TX | 2764 I82580_CFG_ENABLE_DOWNSHIFT; 2765 2766 ret_val = em_write_phy_reg(hw, I82580_CFG_REG, phy_data); 2767 2768 out: 2769 return ret_val; 2770 } 2771 2772 static int32_t 2773 em_copper_link_rtl8211_setup(struct em_hw *hw) 2774 { 2775 int32_t ret_val; 2776 uint16_t phy_data; 2777 2778 DEBUGFUNC("em_copper_link_rtl8211_setup: begin"); 2779 2780 if (!hw) { 2781 return -1; 2782 } 2783 /* SW Reset the PHY so all changes take effect */ 2784 em_phy_hw_reset(hw); 2785 2786 /* Enable CRS on TX. This must be set for half-duplex operation. */ 2787 phy_data = 0; 2788 2789 ret_val = em_read_phy_reg_ex(hw, RGEPHY_CR, &phy_data); 2790 if (ret_val) { 2791 printf("Unable to read RGEPHY_CR register\n"); 2792 return ret_val; 2793 } 2794 DEBUGOUT3("RTL8211: Rx phy_id=%X addr=%X SPEC_CTRL=%X\n", hw->phy_id, 2795 hw->phy_addr, phy_data); 2796 phy_data |= RGEPHY_CR_ASSERT_CRS; 2797 2798 ret_val = em_write_phy_reg_ex(hw, RGEPHY_CR, phy_data); 2799 if (ret_val) { 2800 printf("Unable to write RGEPHY_CR register\n"); 2801 return ret_val; 2802 } 2803 2804 phy_data = 0; /* LED Control Register 0x18 */ 2805 ret_val = em_read_phy_reg_ex(hw, RGEPHY_LC, &phy_data); 2806 if (ret_val) { 2807 printf("Unable to read RGEPHY_LC register\n"); 2808 return ret_val; 2809 } 2810 2811 phy_data &= 0x80FF; /* bit-15=0 disable, clear bit 8-10 */ 2812 ret_val = em_write_phy_reg_ex(hw, RGEPHY_LC, phy_data); 2813 if (ret_val) { 2814 printf("Unable to write RGEPHY_LC register\n"); 2815 return ret_val; 2816 } 2817 /* LED Control and Definition Register 0x11, PHY spec status reg */ 2818 phy_data = 0; 2819 ret_val = em_read_phy_reg_ex(hw, RGEPHY_SR, &phy_data); 2820 if (ret_val) { 2821 printf("Unable to read RGEPHY_SR register\n"); 2822 return ret_val; 2823 } 2824 2825 phy_data |= 0x0010; /* LED active Low */ 2826 ret_val = em_write_phy_reg_ex(hw, RGEPHY_SR, phy_data); 2827 if (ret_val) { 2828 printf("Unable to write RGEPHY_SR register\n"); 2829 return ret_val; 2830 } 2831 2832 phy_data = 0; 2833 ret_val = em_read_phy_reg_ex(hw, RGEPHY_SR, &phy_data); 2834 if (ret_val) { 2835 printf("Unable to read RGEPHY_SR register\n"); 2836 return ret_val; 2837 } 2838 2839 /* Switch to Page2 */ 2840 phy_data = RGEPHY_PS_PAGE_2; 2841 ret_val = em_write_phy_reg_ex(hw, RGEPHY_PS, phy_data); 2842 if (ret_val) { 2843 printf("Unable to write PHY RGEPHY_PS register\n"); 2844 return ret_val; 2845 } 2846 2847 phy_data = 0x0000; 2848 ret_val = em_write_phy_reg_ex(hw, RGEPHY_LC_P2, phy_data); 2849 if (ret_val) { 2850 printf("Unable to write RGEPHY_LC_P2 register\n"); 2851 return ret_val; 2852 } 2853 usec_delay(5); 2854 2855 2856 /* LED Configuration Control Reg for setting for 0x1A Register */ 2857 phy_data = 0; 2858 ret_val = em_read_phy_reg_ex(hw, RGEPHY_LC_P2, &phy_data); 2859 if (ret_val) { 2860 printf("Unable to read RGEPHY_LC_P2 register\n"); 2861 return ret_val; 2862 } 2863 2864 phy_data &= 0xF000; 2865 phy_data |= 0x0F24; 2866 ret_val = em_write_phy_reg_ex(hw, RGEPHY_LC_P2, phy_data); 2867 if (ret_val) { 2868 printf("Unable to write RGEPHY_LC_P2 register\n"); 2869 return ret_val; 2870 } 2871 phy_data = 0; 2872 ret_val= em_read_phy_reg_ex(hw, RGEPHY_LC_P2, &phy_data); 2873 if (ret_val) { 2874 printf("Unable to read RGEPHY_LC_P2 register\n"); 2875 return ret_val; 2876 } 2877 DEBUGOUT1("RTL8211:ReadBack for check, LED_CFG->data=%X\n", phy_data); 2878 2879 2880 /* After setting Page2, go back to Page 0 */ 2881 phy_data = 0; 2882 ret_val = em_write_phy_reg_ex(hw, RGEPHY_PS, phy_data); 2883 if (ret_val) { 2884 printf("Unable to write PHY RGEPHY_PS register\n"); 2885 return ret_val; 2886 } 2887 2888 /* pulse streching= 42-84ms, blink rate=84mm */ 2889 phy_data = 0x140 | RGEPHY_LC_PULSE_42MS | RGEPHY_LC_LINK | 2890 RGEPHY_LC_DUPLEX | RGEPHY_LC_RX; 2891 2892 ret_val = em_write_phy_reg_ex(hw, RGEPHY_LC, phy_data); 2893 if (ret_val) { 2894 printf("Unable to write RGEPHY_LC register\n"); 2895 return ret_val; 2896 } 2897 return E1000_SUCCESS; 2898 } 2899 2900 /****************************************************************************** 2901 * Setup auto-negotiation and flow control advertisements, 2902 * and then perform auto-negotiation. 2903 * 2904 * hw - Struct containing variables accessed by shared code 2905 *****************************************************************************/ 2906 int32_t 2907 em_copper_link_autoneg(struct em_hw *hw) 2908 { 2909 int32_t ret_val; 2910 uint16_t phy_data; 2911 DEBUGFUNC("em_copper_link_autoneg"); 2912 /* 2913 * Perform some bounds checking on the hw->autoneg_advertised 2914 * parameter. If this variable is zero, then set it to the default. 2915 */ 2916 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT; 2917 /* 2918 * If autoneg_advertised is zero, we assume it was not defaulted by 2919 * the calling code so we set to advertise full capability. 2920 */ 2921 if (hw->autoneg_advertised == 0) 2922 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 2923 2924 /* IFE phy only supports 10/100 */ 2925 if (hw->phy_type == em_phy_ife) 2926 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL; 2927 2928 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); 2929 ret_val = em_phy_setup_autoneg(hw); 2930 if (ret_val) { 2931 DEBUGOUT("Error Setting up Auto-Negotiation\n"); 2932 return ret_val; 2933 } 2934 DEBUGOUT("Restarting Auto-Neg\n"); 2935 /* 2936 * Restart auto-negotiation by setting the Auto Neg Enable bit and 2937 * the Auto Neg Restart bit in the PHY control register. 2938 */ 2939 ret_val = em_read_phy_reg(hw, PHY_CTRL, &phy_data); 2940 if (ret_val) 2941 return ret_val; 2942 2943 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 2944 ret_val = em_write_phy_reg(hw, PHY_CTRL, phy_data); 2945 if (ret_val) 2946 return ret_val; 2947 /* 2948 * Does the user want to wait for Auto-Neg to complete here, or check 2949 * at a later time (for example, callback routine). 2950 */ 2951 if (hw->wait_autoneg_complete) { 2952 ret_val = em_wait_autoneg(hw); 2953 if (ret_val) { 2954 DEBUGOUT("Error while waiting for autoneg to complete\n" 2955 ); 2956 return ret_val; 2957 } 2958 } 2959 hw->get_link_status = TRUE; 2960 2961 return E1000_SUCCESS; 2962 } 2963 2964 /****************************************************************************** 2965 * Config the MAC and the PHY after link is up. 2966 * 1) Set up the MAC to the current PHY speed/duplex 2967 * if we are on 82543. If we 2968 * are on newer silicon, we only need to configure 2969 * collision distance in the Transmit Control Register. 2970 * 2) Set up flow control on the MAC to that established with 2971 * the link partner. 2972 * 3) Config DSP to improve Gigabit link quality for some PHY revisions. 2973 * 2974 * hw - Struct containing variables accessed by shared code 2975 *****************************************************************************/ 2976 int32_t 2977 em_copper_link_postconfig(struct em_hw *hw) 2978 { 2979 int32_t ret_val; 2980 DEBUGFUNC("em_copper_link_postconfig"); 2981 2982 if (hw->mac_type >= em_82544 && 2983 hw->mac_type != em_icp_xxxx) { 2984 em_config_collision_dist(hw); 2985 } else { 2986 ret_val = em_config_mac_to_phy(hw); 2987 if (ret_val) { 2988 DEBUGOUT("Error configuring MAC to PHY settings\n"); 2989 return ret_val; 2990 } 2991 } 2992 ret_val = em_config_fc_after_link_up(hw); 2993 if (ret_val) { 2994 DEBUGOUT("Error Configuring Flow Control\n"); 2995 return ret_val; 2996 } 2997 /* Config DSP to improve Giga link quality */ 2998 if (hw->phy_type == em_phy_igp) { 2999 ret_val = em_config_dsp_after_link_change(hw, TRUE); 3000 if (ret_val) { 3001 DEBUGOUT("Error Configuring DSP after link up\n"); 3002 return ret_val; 3003 } 3004 } 3005 return E1000_SUCCESS; 3006 } 3007 3008 /****************************************************************************** 3009 * Detects which PHY is present and setup the speed and duplex 3010 * 3011 * hw - Struct containing variables accessed by shared code 3012 *****************************************************************************/ 3013 static int32_t 3014 em_setup_copper_link(struct em_hw *hw) 3015 { 3016 int32_t ret_val; 3017 uint16_t i; 3018 uint16_t phy_data; 3019 uint16_t reg_data; 3020 DEBUGFUNC("em_setup_copper_link"); 3021 3022 switch (hw->mac_type) { 3023 case em_80003es2lan: 3024 case em_ich8lan: 3025 case em_ich9lan: 3026 case em_ich10lan: 3027 case em_pchlan: 3028 case em_pch2lan: 3029 case em_pch_lpt: 3030 case em_pch_spt: 3031 case em_pch_cnp: 3032 /* 3033 * Set the mac to wait the maximum time between each 3034 * iteration and increase the max iterations when polling the 3035 * phy; this fixes erroneous timeouts at 10Mbps. 3036 */ 3037 ret_val = em_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF); 3038 if (ret_val) 3039 return ret_val; 3040 ret_val = em_read_kmrn_reg(hw, GG82563_REG(0x34, 9), 3041 ®_data); 3042 if (ret_val) 3043 return ret_val; 3044 reg_data |= 0x3F; 3045 ret_val = em_write_kmrn_reg(hw, GG82563_REG(0x34, 9), 3046 reg_data); 3047 if (ret_val) 3048 return ret_val; 3049 default: 3050 break; 3051 } 3052 3053 /* Check if it is a valid PHY and set PHY mode if necessary. */ 3054 ret_val = em_copper_link_preconfig(hw); 3055 if (ret_val) 3056 return ret_val; 3057 3058 switch (hw->mac_type) { 3059 case em_80003es2lan: 3060 /* Kumeran registers are written-only */ 3061 reg_data = 3062 E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT; 3063 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING; 3064 ret_val = em_write_kmrn_reg(hw, 3065 E1000_KUMCTRLSTA_OFFSET_INB_CTRL, reg_data); 3066 if (ret_val) 3067 return ret_val; 3068 break; 3069 default: 3070 break; 3071 } 3072 3073 if (hw->phy_type == em_phy_igp || 3074 hw->phy_type == em_phy_igp_3 || 3075 hw->phy_type == em_phy_igp_2) { 3076 ret_val = em_copper_link_igp_setup(hw); 3077 if (ret_val) 3078 return ret_val; 3079 } else if (hw->phy_type == em_phy_m88 || 3080 hw->phy_type == em_phy_bm || 3081 hw->phy_type == em_phy_oem || 3082 hw->phy_type == em_phy_82578) { 3083 ret_val = em_copper_link_mgp_setup(hw); 3084 if (ret_val) 3085 return ret_val; 3086 } else if (hw->phy_type == em_phy_gg82563) { 3087 ret_val = em_copper_link_ggp_setup(hw); 3088 if (ret_val) 3089 return ret_val; 3090 } else if (hw->phy_type == em_phy_82577 || 3091 hw->phy_type == em_phy_82579 || 3092 hw->phy_type == em_phy_i217) { 3093 ret_val = em_copper_link_82577_setup(hw); 3094 if (ret_val) 3095 return ret_val; 3096 } else if (hw->phy_type == em_phy_82580) { 3097 ret_val = em_copper_link_82580_setup(hw); 3098 if (ret_val) 3099 return ret_val; 3100 } else if (hw->phy_type == em_phy_rtl8211) { 3101 ret_val = em_copper_link_rtl8211_setup(hw); 3102 if (ret_val) 3103 return ret_val; 3104 } 3105 if (hw->autoneg) { 3106 /* 3107 * Setup autoneg and flow control advertisement and perform 3108 * autonegotiation 3109 */ 3110 ret_val = em_copper_link_autoneg(hw); 3111 if (ret_val) 3112 return ret_val; 3113 } else { 3114 /* 3115 * PHY will be set to 10H, 10F, 100H,or 100F depending on 3116 * value from forced_speed_duplex. 3117 */ 3118 DEBUGOUT("Forcing speed and duplex\n"); 3119 ret_val = em_phy_force_speed_duplex(hw); 3120 if (ret_val) { 3121 DEBUGOUT("Error Forcing Speed and Duplex\n"); 3122 return ret_val; 3123 } 3124 } 3125 /* 3126 * Check link status. Wait up to 100 microseconds for link to become 3127 * valid. 3128 */ 3129 for (i = 0; i < 10; i++) { 3130 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 3131 if (ret_val) 3132 return ret_val; 3133 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 3134 if (ret_val) 3135 return ret_val; 3136 3137 hw->icp_xxxx_is_link_up = (phy_data & MII_SR_LINK_STATUS) != 0; 3138 3139 if (phy_data & MII_SR_LINK_STATUS) { 3140 /* Config the MAC and PHY after link is up */ 3141 ret_val = em_copper_link_postconfig(hw); 3142 if (ret_val) 3143 return ret_val; 3144 3145 DEBUGOUT("Valid link established!!!\n"); 3146 return E1000_SUCCESS; 3147 } 3148 usec_delay(10); 3149 } 3150 3151 DEBUGOUT("Unable to establish link!!!\n"); 3152 return E1000_SUCCESS; 3153 } 3154 3155 /****************************************************************************** 3156 * Configure the MAC-to-PHY interface for 10/100Mbps 3157 * 3158 * hw - Struct containing variables accessed by shared code 3159 *****************************************************************************/ 3160 static int32_t 3161 em_configure_kmrn_for_10_100(struct em_hw *hw, uint16_t duplex) 3162 { 3163 int32_t ret_val = E1000_SUCCESS; 3164 uint32_t tipg; 3165 uint16_t reg_data; 3166 DEBUGFUNC("em_configure_kmrn_for_10_100"); 3167 3168 reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT; 3169 ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL, 3170 reg_data); 3171 if (ret_val) 3172 return ret_val; 3173 3174 /* Configure Transmit Inter-Packet Gap */ 3175 tipg = E1000_READ_REG(hw, TIPG); 3176 tipg &= ~E1000_TIPG_IPGT_MASK; 3177 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100; 3178 E1000_WRITE_REG(hw, TIPG, tipg); 3179 3180 ret_val = em_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); 3181 3182 if (ret_val) 3183 return ret_val; 3184 3185 if (duplex == HALF_DUPLEX) 3186 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER; 3187 else 3188 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 3189 3190 ret_val = em_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 3191 3192 return ret_val; 3193 } 3194 3195 static int32_t 3196 em_configure_kmrn_for_1000(struct em_hw *hw) 3197 { 3198 int32_t ret_val = E1000_SUCCESS; 3199 uint16_t reg_data; 3200 uint32_t tipg; 3201 DEBUGFUNC("em_configure_kmrn_for_1000"); 3202 3203 reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT; 3204 ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL, 3205 reg_data); 3206 if (ret_val) 3207 return ret_val; 3208 3209 /* Configure Transmit Inter-Packet Gap */ 3210 tipg = E1000_READ_REG(hw, TIPG); 3211 tipg &= ~E1000_TIPG_IPGT_MASK; 3212 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; 3213 E1000_WRITE_REG(hw, TIPG, tipg); 3214 3215 ret_val = em_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); 3216 3217 if (ret_val) 3218 return ret_val; 3219 3220 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 3221 ret_val = em_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 3222 3223 return ret_val; 3224 } 3225 3226 /****************************************************************************** 3227 * Configures PHY autoneg and flow control advertisement settings 3228 * 3229 * hw - Struct containing variables accessed by shared code 3230 *****************************************************************************/ 3231 int32_t 3232 em_phy_setup_autoneg(struct em_hw *hw) 3233 { 3234 int32_t ret_val; 3235 uint16_t mii_autoneg_adv_reg; 3236 uint16_t mii_1000t_ctrl_reg; 3237 DEBUGFUNC("em_phy_setup_autoneg"); 3238 3239 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 3240 ret_val = em_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 3241 if (ret_val) 3242 return ret_val; 3243 3244 if (hw->phy_type != em_phy_ife) { 3245 /* Read the MII 1000Base-T Control Register (Address 9). */ 3246 ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, 3247 &mii_1000t_ctrl_reg); 3248 if (ret_val) 3249 return ret_val; 3250 } else 3251 mii_1000t_ctrl_reg = 0; 3252 /* 3253 * Need to parse both autoneg_advertised and fc and set up the 3254 * appropriate PHY registers. First we will parse for 3255 * autoneg_advertised software override. Since we can advertise a 3256 * plethora of combinations, we need to check each bit individually. 3257 */ 3258 /* 3259 * First we clear all the 10/100 mb speed bits in the Auto-Neg 3260 * Advertisement Register (Address 4) and the 1000 mb speed bits in 3261 * the 1000Base-T Control Register (Address 9). 3262 */ 3263 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK; 3264 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK; 3265 3266 DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised); 3267 3268 /* Do we want to advertise 10 Mb Half Duplex? */ 3269 if (hw->autoneg_advertised & ADVERTISE_10_HALF) { 3270 DEBUGOUT("Advertise 10mb Half duplex\n"); 3271 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 3272 } 3273 /* Do we want to advertise 10 Mb Full Duplex? */ 3274 if (hw->autoneg_advertised & ADVERTISE_10_FULL) { 3275 DEBUGOUT("Advertise 10mb Full duplex\n"); 3276 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 3277 } 3278 /* Do we want to advertise 100 Mb Half Duplex? */ 3279 if (hw->autoneg_advertised & ADVERTISE_100_HALF) { 3280 DEBUGOUT("Advertise 100mb Half duplex\n"); 3281 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 3282 } 3283 /* Do we want to advertise 100 Mb Full Duplex? */ 3284 if (hw->autoneg_advertised & ADVERTISE_100_FULL) { 3285 DEBUGOUT("Advertise 100mb Full duplex\n"); 3286 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 3287 } 3288 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 3289 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) { 3290 DEBUGOUT("Advertise 1000mb Half duplex requested, request" 3291 " denied!\n"); 3292 } 3293 /* Do we want to advertise 1000 Mb Full Duplex? */ 3294 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) { 3295 DEBUGOUT("Advertise 1000mb Full duplex\n"); 3296 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 3297 if (hw->phy_type == em_phy_ife) { 3298 DEBUGOUT("em_phy_ife is a 10/100 PHY. Gigabit speed is" 3299 " not supported.\n"); 3300 } 3301 } 3302 /* 3303 * Check for a software override of the flow control settings, and 3304 * setup the PHY advertisement registers accordingly. If 3305 * auto-negotiation is enabled, then software will have to set the 3306 * "PAUSE" bits to the correct value in the Auto-Negotiation 3307 * Advertisement Register (PHY_AUTONEG_ADV) and re-start 3308 * auto-negotiation. 3309 * 3310 * The possible values of the "fc" parameter are: 0: Flow control is 3311 * completely disabled 1: Rx flow control is enabled (we can receive 3312 * pause frames but not send pause frames). 2: Tx flow control is 3313 * enabled (we can send pause frames but we do not support receiving 3314 * pause frames). 3: Both Rx and TX flow control (symmetric) are 3315 * enabled. other: No software override. The flow control 3316 * configuration in the EEPROM is used. 3317 */ 3318 switch (hw->fc) { 3319 case E1000_FC_NONE: /* 0 */ 3320 /* 3321 * Flow control (RX & TX) is completely disabled by a 3322 * software over-ride. 3323 */ 3324 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 3325 break; 3326 case E1000_FC_RX_PAUSE:/* 1 */ 3327 /* 3328 * RX Flow control is enabled, and TX Flow control is 3329 * disabled, by a software over-ride. 3330 */ 3331 /* 3332 * Since there really isn't a way to advertise that we are 3333 * capable of RX Pause ONLY, we will advertise that we 3334 * support both symmetric and asymmetric RX PAUSE. Later (in 3335 * em_config_fc_after_link_up) we will disable the hw's 3336 * ability to send PAUSE frames. 3337 */ 3338 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 3339 break; 3340 case E1000_FC_TX_PAUSE:/* 2 */ 3341 /* 3342 * TX Flow control is enabled, and RX Flow control is 3343 * disabled, by a software over-ride. 3344 */ 3345 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 3346 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 3347 break; 3348 case E1000_FC_FULL: /* 3 */ 3349 /* 3350 * Flow control (both RX and TX) is enabled by a software 3351 * over-ride. 3352 */ 3353 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 3354 break; 3355 default: 3356 DEBUGOUT("Flow control param set incorrectly\n"); 3357 return -E1000_ERR_CONFIG; 3358 } 3359 3360 ret_val = em_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 3361 if (ret_val) 3362 return ret_val; 3363 3364 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 3365 3366 if (hw->phy_type != em_phy_ife) { 3367 ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL, 3368 mii_1000t_ctrl_reg); 3369 if (ret_val) 3370 return ret_val; 3371 } 3372 return E1000_SUCCESS; 3373 } 3374 /****************************************************************************** 3375 * Force PHY speed and duplex settings to hw->forced_speed_duplex 3376 * 3377 * hw - Struct containing variables accessed by shared code 3378 *****************************************************************************/ 3379 static int32_t 3380 em_phy_force_speed_duplex(struct em_hw *hw) 3381 { 3382 uint32_t ctrl; 3383 int32_t ret_val; 3384 uint16_t mii_ctrl_reg; 3385 uint16_t mii_status_reg; 3386 uint16_t phy_data; 3387 uint16_t i; 3388 DEBUGFUNC("em_phy_force_speed_duplex"); 3389 3390 /* Turn off Flow control if we are forcing speed and duplex. */ 3391 hw->fc = E1000_FC_NONE; 3392 3393 DEBUGOUT1("hw->fc = %d\n", hw->fc); 3394 3395 /* Read the Device Control Register. */ 3396 ctrl = E1000_READ_REG(hw, CTRL); 3397 3398 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */ 3399 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 3400 ctrl &= ~(DEVICE_SPEED_MASK); 3401 3402 /* Clear the Auto Speed Detect Enable bit. */ 3403 ctrl &= ~E1000_CTRL_ASDE; 3404 3405 /* Read the MII Control Register. */ 3406 ret_val = em_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg); 3407 if (ret_val) 3408 return ret_val; 3409 3410 /* We need to disable autoneg in order to force link and duplex. */ 3411 3412 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN; 3413 3414 /* Are we forcing Full or Half Duplex? */ 3415 if (hw->forced_speed_duplex == em_100_full || 3416 hw->forced_speed_duplex == em_10_full) { 3417 /* 3418 * We want to force full duplex so we SET the full duplex 3419 * bits in the Device and MII Control Registers. 3420 */ 3421 ctrl |= E1000_CTRL_FD; 3422 mii_ctrl_reg |= MII_CR_FULL_DUPLEX; 3423 DEBUGOUT("Full Duplex\n"); 3424 } else { 3425 /* 3426 * We want to force half duplex so we CLEAR the full duplex 3427 * bits in the Device and MII Control Registers. 3428 */ 3429 ctrl &= ~E1000_CTRL_FD; 3430 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX; 3431 DEBUGOUT("Half Duplex\n"); 3432 } 3433 3434 /* Are we forcing 100Mbps??? */ 3435 if (hw->forced_speed_duplex == em_100_full || 3436 hw->forced_speed_duplex == em_100_half) { 3437 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */ 3438 ctrl |= E1000_CTRL_SPD_100; 3439 mii_ctrl_reg |= MII_CR_SPEED_100; 3440 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); 3441 DEBUGOUT("Forcing 100mb "); 3442 } else { 3443 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */ 3444 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 3445 mii_ctrl_reg |= MII_CR_SPEED_10; 3446 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); 3447 DEBUGOUT("Forcing 10mb "); 3448 } 3449 3450 em_config_collision_dist(hw); 3451 3452 /* Write the configured values back to the Device Control Reg. */ 3453 E1000_WRITE_REG(hw, CTRL, ctrl); 3454 3455 if ((hw->phy_type == em_phy_m88) || 3456 (hw->phy_type == em_phy_gg82563) || 3457 (hw->phy_type == em_phy_bm) || 3458 (hw->phy_type == em_phy_oem || 3459 (hw->phy_type == em_phy_82578))) { 3460 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 3461 &phy_data); 3462 if (ret_val) 3463 return ret_val; 3464 /* 3465 * Clear Auto-Crossover to force MDI manually. M88E1000 3466 * requires MDI forced whenever speed are duplex are forced. 3467 */ 3468 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 3469 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 3470 phy_data); 3471 if (ret_val) 3472 return ret_val; 3473 3474 DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data); 3475 3476 /* Need to reset the PHY or these changes will be ignored */ 3477 mii_ctrl_reg |= MII_CR_RESET; 3478 3479 } 3480 else if (hw->phy_type == em_phy_rtl8211) { 3481 ret_val = em_read_phy_reg_ex(hw, RGEPHY_CR, &phy_data); 3482 if(ret_val) { 3483 printf("Unable to read RGEPHY_CR register\n" 3484 ); 3485 return ret_val; 3486 } 3487 3488 /* 3489 * Clear Auto-Crossover to force MDI manually. RTL8211 requires 3490 * MDI forced whenever speed are duplex are forced. 3491 */ 3492 3493 phy_data |= RGEPHY_CR_MDI_MASK; // enable MDIX 3494 ret_val = em_write_phy_reg_ex(hw, RGEPHY_CR, phy_data); 3495 if(ret_val) { 3496 printf("Unable to write RGEPHY_CR register\n"); 3497 return ret_val; 3498 } 3499 mii_ctrl_reg |= MII_CR_RESET; 3500 3501 } 3502 /* Disable MDI-X support for 10/100 */ 3503 else if (hw->phy_type == em_phy_ife) { 3504 ret_val = em_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data); 3505 if (ret_val) 3506 return ret_val; 3507 3508 phy_data &= ~IFE_PMC_AUTO_MDIX; 3509 phy_data &= ~IFE_PMC_FORCE_MDIX; 3510 3511 ret_val = em_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, phy_data); 3512 if (ret_val) 3513 return ret_val; 3514 } else { 3515 /* 3516 * Clear Auto-Crossover to force MDI manually. IGP requires 3517 * MDI forced whenever speed or duplex are forced. 3518 */ 3519 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, 3520 &phy_data); 3521 if (ret_val) 3522 return ret_val; 3523 3524 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 3525 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 3526 3527 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, 3528 phy_data); 3529 if (ret_val) 3530 return ret_val; 3531 } 3532 3533 /* Write back the modified PHY MII control register. */ 3534 ret_val = em_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg); 3535 if (ret_val) 3536 return ret_val; 3537 3538 usec_delay(1); 3539 /* 3540 * The wait_autoneg_complete flag may be a little misleading here. 3541 * Since we are forcing speed and duplex, Auto-Neg is not enabled. 3542 * But we do want to delay for a period while forcing only so we 3543 * don't generate false No Link messages. So we will wait here only 3544 * if the user has set wait_autoneg_complete to 1, which is the 3545 * default. 3546 */ 3547 if (hw->wait_autoneg_complete) { 3548 /* We will wait for autoneg to complete. */ 3549 DEBUGOUT("Waiting for forced speed/duplex link.\n"); 3550 mii_status_reg = 0; 3551 /* 3552 * We will wait for autoneg to complete or 4.5 seconds to 3553 * expire. 3554 */ 3555 for (i = PHY_FORCE_TIME; i > 0; i--) { 3556 /* 3557 * Read the MII Status Register and wait for Auto-Neg 3558 * Complete bit to be set. 3559 */ 3560 ret_val = em_read_phy_reg(hw, PHY_STATUS, 3561 &mii_status_reg); 3562 if (ret_val) 3563 return ret_val; 3564 3565 ret_val = em_read_phy_reg(hw, PHY_STATUS, 3566 &mii_status_reg); 3567 if (ret_val) 3568 return ret_val; 3569 3570 if (mii_status_reg & MII_SR_LINK_STATUS) 3571 break; 3572 msec_delay(100); 3573 } 3574 if ((i == 0) && 3575 ((hw->phy_type == em_phy_m88) || 3576 (hw->phy_type == em_phy_gg82563) || 3577 (hw->phy_type == em_phy_bm))) { 3578 /* 3579 * We didn't get link. Reset the DSP and wait again 3580 * for link. 3581 */ 3582 ret_val = em_phy_reset_dsp(hw); 3583 if (ret_val) { 3584 DEBUGOUT("Error Resetting PHY DSP\n"); 3585 return ret_val; 3586 } 3587 } 3588 /* 3589 * This loop will early-out if the link condition has been 3590 * met. 3591 */ 3592 for (i = PHY_FORCE_TIME; i > 0; i--) { 3593 if (mii_status_reg & MII_SR_LINK_STATUS) 3594 break; 3595 msec_delay(100); 3596 /* 3597 * Read the MII Status Register and wait for Auto-Neg 3598 * Complete bit to be set. 3599 */ 3600 ret_val = em_read_phy_reg(hw, PHY_STATUS, 3601 &mii_status_reg); 3602 if (ret_val) 3603 return ret_val; 3604 3605 ret_val = em_read_phy_reg(hw, PHY_STATUS, 3606 &mii_status_reg); 3607 if (ret_val) 3608 return ret_val; 3609 } 3610 } 3611 if (hw->phy_type == em_phy_m88 || 3612 hw->phy_type == em_phy_bm || 3613 hw->phy_type == em_phy_oem) { 3614 /* 3615 * Because we reset the PHY above, we need to re-force TX_CLK 3616 * in the Extended PHY Specific Control Register to 25MHz 3617 * clock. This value defaults back to a 2.5MHz clock when 3618 * the PHY is reset. 3619 */ 3620 ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 3621 &phy_data); 3622 if (ret_val) 3623 return ret_val; 3624 3625 phy_data |= M88E1000_EPSCR_TX_CLK_25; 3626 ret_val = em_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 3627 phy_data); 3628 if (ret_val) 3629 return ret_val; 3630 /* 3631 * In addition, because of the s/w reset above, we need to 3632 * enable CRS on TX. This must be set for both full and half 3633 * duplex operation. 3634 */ 3635 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 3636 &phy_data); 3637 if (ret_val) 3638 return ret_val; 3639 3640 if (hw->phy_id == M88E1141_E_PHY_ID) 3641 phy_data &= ~M88E1000_PSCR_ASSERT_CRS_ON_TX; 3642 else 3643 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 3644 3645 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 3646 phy_data); 3647 if (ret_val) 3648 return ret_val; 3649 3650 if ((hw->mac_type == em_82544 || hw->mac_type == em_82543) && 3651 (!hw->autoneg) && (hw->forced_speed_duplex == em_10_full || 3652 hw->forced_speed_duplex == em_10_half)) { 3653 ret_val = em_polarity_reversal_workaround(hw); 3654 if (ret_val) 3655 return ret_val; 3656 } 3657 } else if (hw->phy_type == em_phy_rtl8211) { 3658 /* 3659 * In addition, because of the s/w reset above, we need to enable 3660 * CRX on TX. This must be set for both full and half duplex 3661 * operation. 3662 */ 3663 3664 ret_val = em_read_phy_reg_ex(hw, RGEPHY_CR, &phy_data); 3665 if(ret_val) { 3666 printf("Unable to read RGEPHY_CR register\n"); 3667 return ret_val; 3668 } 3669 3670 phy_data &= ~RGEPHY_CR_ASSERT_CRS; 3671 ret_val = em_write_phy_reg_ex(hw, RGEPHY_CR, phy_data); 3672 if(ret_val) { 3673 printf("Unable to write RGEPHY_CR register\n"); 3674 return ret_val; 3675 } 3676 } else if (hw->phy_type == em_phy_gg82563) { 3677 /* 3678 * The TX_CLK of the Extended PHY Specific Control Register 3679 * defaults to 2.5MHz on a reset. We need to re-force it 3680 * back to 25MHz, if we're not in a forced 10/duplex 3681 * configuration. 3682 */ 3683 ret_val = em_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 3684 &phy_data); 3685 if (ret_val) 3686 return ret_val; 3687 3688 phy_data &= ~GG82563_MSCR_TX_CLK_MASK; 3689 if ((hw->forced_speed_duplex == em_10_full) || 3690 (hw->forced_speed_duplex == em_10_half)) 3691 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ; 3692 else 3693 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25MHZ; 3694 3695 /* Also due to the reset, we need to enable CRS on Tx. */ 3696 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 3697 3698 ret_val = em_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 3699 phy_data); 3700 if (ret_val) 3701 return ret_val; 3702 } 3703 return E1000_SUCCESS; 3704 } 3705 3706 /****************************************************************************** 3707 * Sets the collision distance in the Transmit Control register 3708 * 3709 * hw - Struct containing variables accessed by shared code 3710 * 3711 * Link should have been established previously. Reads the speed and duplex 3712 * information from the Device Status register. 3713 *****************************************************************************/ 3714 void 3715 em_config_collision_dist(struct em_hw *hw) 3716 { 3717 uint32_t tctl, coll_dist; 3718 DEBUGFUNC("em_config_collision_dist"); 3719 3720 if (hw->mac_type < em_82543) 3721 coll_dist = E1000_COLLISION_DISTANCE_82542; 3722 else 3723 coll_dist = E1000_COLLISION_DISTANCE; 3724 3725 tctl = E1000_READ_REG(hw, TCTL); 3726 3727 tctl &= ~E1000_TCTL_COLD; 3728 tctl |= coll_dist << E1000_COLD_SHIFT; 3729 3730 E1000_WRITE_REG(hw, TCTL, tctl); 3731 E1000_WRITE_FLUSH(hw); 3732 } 3733 3734 /****************************************************************************** 3735 * Sets MAC speed and duplex settings to reflect the those in the PHY 3736 * 3737 * hw - Struct containing variables accessed by shared code 3738 * mii_reg - data to write to the MII control register 3739 * 3740 * The contents of the PHY register containing the needed information need to 3741 * be passed in. 3742 *****************************************************************************/ 3743 static int32_t 3744 em_config_mac_to_phy(struct em_hw *hw) 3745 { 3746 uint32_t ctrl; 3747 int32_t ret_val; 3748 uint16_t phy_data; 3749 DEBUGFUNC("em_config_mac_to_phy"); 3750 /* 3751 * 82544 or newer MAC, Auto Speed Detection takes care of MAC 3752 * speed/duplex configuration. 3753 */ 3754 if (hw->mac_type >= em_82544 3755 && hw->mac_type != em_icp_xxxx) 3756 return E1000_SUCCESS; 3757 /* 3758 * Read the Device Control Register and set the bits to Force Speed 3759 * and Duplex. 3760 */ 3761 ctrl = E1000_READ_REG(hw, CTRL); 3762 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 3763 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); 3764 /* 3765 * Set up duplex in the Device Control and Transmit Control registers 3766 * depending on negotiated values. 3767 */ 3768 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 3769 if (ret_val) 3770 return ret_val; 3771 3772 if (phy_data & M88E1000_PSSR_DPLX) 3773 ctrl |= E1000_CTRL_FD; 3774 else 3775 ctrl &= ~E1000_CTRL_FD; 3776 3777 em_config_collision_dist(hw); 3778 /* 3779 * Set up speed in the Device Control register depending on 3780 * negotiated values. 3781 */ 3782 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) 3783 ctrl |= E1000_CTRL_SPD_1000; 3784 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) 3785 ctrl |= E1000_CTRL_SPD_100; 3786 3787 /* Write the configured values back to the Device Control Reg. */ 3788 E1000_WRITE_REG(hw, CTRL, ctrl); 3789 return E1000_SUCCESS; 3790 } 3791 3792 /****************************************************************************** 3793 * Forces the MAC's flow control settings. 3794 * 3795 * hw - Struct containing variables accessed by shared code 3796 * 3797 * Sets the TFCE and RFCE bits in the device control register to reflect 3798 * the adapter settings. TFCE and RFCE need to be explicitly set by 3799 * software when a Copper PHY is used because autonegotiation is managed 3800 * by the PHY rather than the MAC. Software must also configure these 3801 * bits when link is forced on a fiber connection. 3802 *****************************************************************************/ 3803 int32_t 3804 em_force_mac_fc(struct em_hw *hw) 3805 { 3806 uint32_t ctrl; 3807 DEBUGFUNC("em_force_mac_fc"); 3808 3809 /* Get the current configuration of the Device Control Register */ 3810 ctrl = E1000_READ_REG(hw, CTRL); 3811 /* 3812 * Because we didn't get link via the internal auto-negotiation 3813 * mechanism (we either forced link or we got link via PHY auto-neg), 3814 * we have to manually enable/disable transmit an receive flow 3815 * control. 3816 * 3817 * The "Case" statement below enables/disable flow control according to 3818 * the "hw->fc" parameter. 3819 * 3820 * The possible values of the "fc" parameter are: 0: Flow control is 3821 * completely disabled 1: Rx flow control is enabled (we can receive 3822 * pause frames but not send pause frames). 2: Tx flow control is 3823 * enabled (we can send pause frames frames but we do not receive 3824 * pause frames). 3: Both Rx and TX flow control (symmetric) is 3825 * enabled. other: No other values should be possible at this point. 3826 */ 3827 3828 switch (hw->fc) { 3829 case E1000_FC_NONE: 3830 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 3831 break; 3832 case E1000_FC_RX_PAUSE: 3833 ctrl &= (~E1000_CTRL_TFCE); 3834 ctrl |= E1000_CTRL_RFCE; 3835 break; 3836 case E1000_FC_TX_PAUSE: 3837 ctrl &= (~E1000_CTRL_RFCE); 3838 ctrl |= E1000_CTRL_TFCE; 3839 break; 3840 case E1000_FC_FULL: 3841 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 3842 break; 3843 default: 3844 DEBUGOUT("Flow control param set incorrectly\n"); 3845 return -E1000_ERR_CONFIG; 3846 } 3847 3848 /* Disable TX Flow Control for 82542 (rev 2.0) */ 3849 if (hw->mac_type == em_82542_rev2_0) 3850 ctrl &= (~E1000_CTRL_TFCE); 3851 3852 E1000_WRITE_REG(hw, CTRL, ctrl); 3853 return E1000_SUCCESS; 3854 } 3855 /****************************************************************************** 3856 * Configures flow control settings after link is established 3857 * 3858 * hw - Struct containing variables accessed by shared code 3859 * 3860 * Should be called immediately after a valid link has been established. 3861 * Forces MAC flow control settings if link was forced. When in MII/GMII mode 3862 * and autonegotiation is enabled, the MAC flow control settings will be set 3863 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE 3864 * and RFCE bits will be automaticaly set to the negotiated flow control mode. 3865 *****************************************************************************/ 3866 STATIC int32_t 3867 em_config_fc_after_link_up(struct em_hw *hw) 3868 { 3869 int32_t ret_val; 3870 uint16_t mii_status_reg; 3871 uint16_t mii_nway_adv_reg; 3872 uint16_t mii_nway_lp_ability_reg; 3873 uint16_t speed; 3874 uint16_t duplex; 3875 DEBUGFUNC("em_config_fc_after_link_up"); 3876 /* 3877 * Check for the case where we have fiber media and auto-neg failed 3878 * so we had to force link. In this case, we need to force the 3879 * configuration of the MAC to match the "fc" parameter. 3880 */ 3881 if (((hw->media_type == em_media_type_fiber) && (hw->autoneg_failed)) 3882 || ((hw->media_type == em_media_type_internal_serdes) && 3883 (hw->autoneg_failed)) || 3884 ((hw->media_type == em_media_type_copper) && (!hw->autoneg)) || 3885 ((hw->media_type == em_media_type_oem) && (!hw->autoneg))) { 3886 ret_val = em_force_mac_fc(hw); 3887 if (ret_val) { 3888 DEBUGOUT("Error forcing flow control settings\n"); 3889 return ret_val; 3890 } 3891 } 3892 /* 3893 * Check for the case where we have copper media and auto-neg is 3894 * enabled. In this case, we need to check and see if Auto-Neg has 3895 * completed, and if so, how the PHY and link partner has flow 3896 * control configured. 3897 */ 3898 if ((hw->media_type == em_media_type_copper || 3899 (hw->media_type == em_media_type_oem)) && 3900 hw->autoneg) { 3901 /* 3902 * Read the MII Status Register and check to see if AutoNeg 3903 * has completed. We read this twice because this reg has 3904 * some "sticky" (latched) bits. 3905 */ 3906 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 3907 if (ret_val) 3908 return ret_val; 3909 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 3910 if (ret_val) 3911 return ret_val; 3912 3913 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) { 3914 /* 3915 * The AutoNeg process has completed, so we now need 3916 * to read both the Auto Negotiation Advertisement 3917 * Register (Address 4) and the Auto_Negotiation Base 3918 * Page Ability Register (Address 5) to determine how 3919 * flow control was negotiated. 3920 */ 3921 ret_val = em_read_phy_reg(hw, PHY_AUTONEG_ADV, 3922 &mii_nway_adv_reg); 3923 if (ret_val) 3924 return ret_val; 3925 ret_val = em_read_phy_reg(hw, PHY_LP_ABILITY, 3926 &mii_nway_lp_ability_reg); 3927 if (ret_val) 3928 return ret_val; 3929 /* 3930 * Two bits in the Auto Negotiation Advertisement 3931 * Register (Address 4) and two bits in the Auto 3932 * Negotiation Base Page Ability Register (Address 5) 3933 * determine flow control for both the PHY and the 3934 * link partner. The following table, taken out of 3935 * the IEEE 802.3ab/D6.0 dated March 25, 1999, 3936 * describes these PAUSE resolution bits and how flow 3937 * control is determined based upon these settings. 3938 * NOTE: DC = Don't Care 3939 * 3940 * LOCAL DEVICE | LINK PARTNER | 3941 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 3942 * -------|---------|-------|---------|--------------- 3943 * 0 | 0 | DC | DC | em_fc_none 3944 * 0 | 1 | 0 | DC | em_fc_none 3945 * 0 | 1 | 1 | 0 | em_fc_none 3946 * 0 | 1 | 1 | 1 | em_fc_tx_pause 3947 * 1 | 0 | 0 | DC | em_fc_none 3948 * 1 | DC | 1 | DC | em_fc_full 3949 * 1 | 1 | 0 | 0 | em_fc_none 3950 * 1 | 1 | 0 | 1 | em_fc_rx_pause 3951 * 3952 */ 3953 /* 3954 * Are both PAUSE bits set to 1? If so, this implies 3955 * Symmetric Flow Control is enabled at both ends. 3956 * The ASM_DIR bits are irrelevant per the spec. 3957 * 3958 * For Symmetric Flow Control: 3959 * 3960 * LOCAL DEVICE | LINK PARTNER 3961 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 3962 * -------|---------|-------|---------|--------------- 3963 * 1 | DC | 1 | DC | em_fc_full 3964 * 3965 */ 3966 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 3967 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 3968 /* 3969 * Now we need to check if the user selected 3970 * RX ONLY of pause frames. In this case, we 3971 * had to advertise FULL flow control because 3972 * we could not advertise RX ONLY. Hence, we 3973 * must now check to see if we need to turn 3974 * OFF the TRANSMISSION of PAUSE frames. 3975 */ 3976 if (hw->original_fc == E1000_FC_FULL) { 3977 hw->fc = E1000_FC_FULL; 3978 DEBUGOUT("Flow Control = FULL.\n"); 3979 } else { 3980 hw->fc = E1000_FC_RX_PAUSE; 3981 DEBUGOUT("Flow Control = RX PAUSE" 3982 " frames only.\n"); 3983 } 3984 } 3985 /* 3986 * For receiving PAUSE frames ONLY. 3987 * 3988 * LOCAL DEVICE | LINK PARTNER PAUSE | ASM_DIR | 3989 * PAUSE | ASM_DIR | Result 3990 * -------|---------|-------|---------|--------------- 3991 * ----- 0 | 1 | 1 | 1 | 3992 * em_fc_tx_pause 3993 * 3994 */ 3995 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 3996 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 3997 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 3998 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 3999 hw->fc = E1000_FC_TX_PAUSE; 4000 DEBUGOUT("Flow Control = TX PAUSE frames only." 4001 "\n"); 4002 } 4003 /* 4004 * For transmitting PAUSE frames ONLY. 4005 * 4006 * LOCAL DEVICE | LINK PARTNER 4007 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 4008 * -------|---------|-------|---------|--------------- 4009 * 1 | 1 | 0 | 1 | em_fc_rx_pause 4010 * 4011 */ 4012 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 4013 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 4014 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 4015 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 4016 hw->fc = E1000_FC_RX_PAUSE; 4017 DEBUGOUT("Flow Control = RX PAUSE frames only." 4018 "\n"); 4019 } 4020 /* 4021 * Per the IEEE spec, at this point flow control 4022 * should be disabled. However, we want to consider 4023 * that we could be connected to a legacy switch that 4024 * doesn't advertise desired flow control, but can be 4025 * forced on the link partner. So if we advertised 4026 * no flow control, that is what we will resolve to. 4027 * If we advertised some kind of receive capability 4028 * (Rx Pause Only or Full Flow Control) and the link 4029 * partner advertised none, we will configure 4030 * ourselves to enable Rx Flow Control only. We can 4031 * do this safely for two reasons: If the link 4032 * partner really didn't want flow control enabled, 4033 * and we enable Rx, no harm done since we won't be 4034 * receiving any PAUSE frames anyway. If the intent 4035 * on the link partner was to have flow control 4036 * enabled, then by us enabling RX only, we can at 4037 * least receive pause frames and process them. This 4038 * is a good idea because in most cases, since we are 4039 * predominantly a server NIC, more times than not we 4040 * will be asked to delay transmission of packets 4041 * than asking our link partner to pause transmission 4042 * of frames. 4043 */ 4044 else if ((hw->original_fc == E1000_FC_NONE || 4045 hw->original_fc == E1000_FC_TX_PAUSE) || 4046 hw->fc_strict_ieee) { 4047 hw->fc = E1000_FC_NONE; 4048 DEBUGOUT("Flow Control = NONE.\n"); 4049 } else { 4050 hw->fc = E1000_FC_RX_PAUSE; 4051 DEBUGOUT("Flow Control = RX PAUSE frames only." 4052 "\n"); 4053 } 4054 /* 4055 * Now we need to do one last check... If we auto- 4056 * negotiated to HALF DUPLEX, flow control should not 4057 * be enabled per IEEE 802.3 spec. 4058 */ 4059 ret_val = em_get_speed_and_duplex(hw, &speed, &duplex); 4060 if (ret_val) { 4061 DEBUGOUT("Error getting link speed and duplex" 4062 "\n"); 4063 return ret_val; 4064 } 4065 if (duplex == HALF_DUPLEX) 4066 hw->fc = E1000_FC_NONE; 4067 /* 4068 * Now we call a subroutine to actually force the MAC 4069 * controller to use the correct flow control 4070 * settings. 4071 */ 4072 ret_val = em_force_mac_fc(hw); 4073 if (ret_val) { 4074 DEBUGOUT("Error forcing flow control settings" 4075 "\n"); 4076 return ret_val; 4077 } 4078 } else { 4079 DEBUGOUT("Copper PHY and Auto Neg has not completed." 4080 "\n"); 4081 } 4082 } 4083 return E1000_SUCCESS; 4084 } 4085 /****************************************************************************** 4086 * Checks to see if the link status of the hardware has changed. 4087 * 4088 * hw - Struct containing variables accessed by shared code 4089 * 4090 * Called by any function that needs to check the link status of the adapter. 4091 *****************************************************************************/ 4092 int32_t 4093 em_check_for_link(struct em_hw *hw) 4094 { 4095 uint32_t rxcw = 0; 4096 uint32_t ctrl; 4097 uint32_t status; 4098 uint32_t rctl; 4099 uint32_t icr; 4100 uint32_t signal = 0; 4101 int32_t ret_val; 4102 uint16_t phy_data; 4103 DEBUGFUNC("em_check_for_link"); 4104 uint16_t speed, duplex; 4105 4106 if (hw->mac_type >= em_82575 && 4107 hw->media_type != em_media_type_copper) { 4108 ret_val = em_get_pcs_speed_and_duplex_82575(hw, &speed, 4109 &duplex); 4110 hw->get_link_status = hw->serdes_link_down; 4111 4112 return (ret_val); 4113 } 4114 4115 ctrl = E1000_READ_REG(hw, CTRL); 4116 status = E1000_READ_REG(hw, STATUS); 4117 /* 4118 * On adapters with a MAC newer than 82544, SW Defineable pin 1 will 4119 * be set when the optics detect a signal. On older adapters, it will 4120 * be cleared when there is a signal. This applies to fiber media 4121 * only. 4122 */ 4123 if ((hw->media_type == em_media_type_fiber) || 4124 (hw->media_type == em_media_type_internal_serdes)) { 4125 rxcw = E1000_READ_REG(hw, RXCW); 4126 4127 if (hw->media_type == em_media_type_fiber) { 4128 signal = (hw->mac_type > em_82544) ? 4129 E1000_CTRL_SWDPIN1 : 0; 4130 if (status & E1000_STATUS_LU) 4131 hw->get_link_status = FALSE; 4132 } 4133 } 4134 /* 4135 * If we have a copper PHY then we only want to go out to the PHY 4136 * registers to see if Auto-Neg has completed and/or if our link 4137 * status has changed. The get_link_status flag will be set if we 4138 * receive a Link Status Change interrupt or we have Rx Sequence 4139 * Errors. 4140 */ 4141 if ((hw->media_type == em_media_type_copper || 4142 (hw->media_type == em_media_type_oem)) && 4143 hw->get_link_status) { 4144 /* 4145 * First we want to see if the MII Status Register reports 4146 * link. If so, then we want to get the current speed/duplex 4147 * of the PHY. Read the register twice since the link bit is 4148 * sticky. 4149 */ 4150 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 4151 if (ret_val) 4152 return ret_val; 4153 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 4154 if (ret_val) 4155 return ret_val; 4156 4157 hw->icp_xxxx_is_link_up = (phy_data & MII_SR_LINK_STATUS) != 0; 4158 4159 if (hw->mac_type == em_pchlan) { 4160 ret_val = em_k1_gig_workaround_hv(hw, 4161 hw->icp_xxxx_is_link_up); 4162 if (ret_val) 4163 return ret_val; 4164 } 4165 4166 if (phy_data & MII_SR_LINK_STATUS) { 4167 hw->get_link_status = FALSE; 4168 4169 if (hw->phy_type == em_phy_82578) { 4170 ret_val = em_link_stall_workaround_hv(hw); 4171 if (ret_val) 4172 return ret_val; 4173 } 4174 4175 if (hw->mac_type == em_pch2lan) { 4176 ret_val = em_k1_workaround_lv(hw); 4177 if (ret_val) 4178 return ret_val; 4179 } 4180 /* Work-around I218 hang issue */ 4181 if ((hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) || 4182 (hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) || 4183 (hw->device_id == E1000_DEV_ID_PCH_I218_LM3) || 4184 (hw->device_id == E1000_DEV_ID_PCH_I218_V3)) { 4185 ret_val = em_k1_workaround_lpt_lp(hw, 4186 hw->icp_xxxx_is_link_up); 4187 if (ret_val) 4188 return ret_val; 4189 } 4190 4191 /* 4192 * Check if there was DownShift, must be checked 4193 * immediately after link-up 4194 */ 4195 em_check_downshift(hw); 4196 4197 /* Enable/Disable EEE after link up */ 4198 if (hw->mac_type == em_pch2lan || 4199 hw->mac_type == em_pch_lpt || 4200 hw->mac_type == em_pch_spt || 4201 hw->mac_type == em_pch_cnp) { 4202 ret_val = em_set_eee_pchlan(hw); 4203 if (ret_val) 4204 return ret_val; 4205 } 4206 4207 /* 4208 * If we are on 82544 or 82543 silicon and 4209 * speed/duplex are forced to 10H or 10F, then we 4210 * will implement the polarity reversal workaround. 4211 * We disable interrupts first, and upon returning, 4212 * place the devices interrupt state to its previous 4213 * value except for the link status change interrupt 4214 * which will happen due to the execution of this 4215 * workaround. 4216 */ 4217 if ((hw->mac_type == em_82544 || 4218 hw->mac_type == em_82543) && (!hw->autoneg) && 4219 (hw->forced_speed_duplex == em_10_full || 4220 hw->forced_speed_duplex == em_10_half)) { 4221 E1000_WRITE_REG(hw, IMC, 0xffffffff); 4222 ret_val = em_polarity_reversal_workaround(hw); 4223 icr = E1000_READ_REG(hw, ICR); 4224 E1000_WRITE_REG(hw, ICS, 4225 (icr & ~E1000_ICS_LSC)); 4226 E1000_WRITE_REG(hw, IMS, IMS_ENABLE_MASK); 4227 } 4228 } else { 4229 /* No link detected */ 4230 em_config_dsp_after_link_change(hw, FALSE); 4231 return 0; 4232 } 4233 /* 4234 * If we are forcing speed/duplex, then we simply return 4235 * since we have already determined whether we have link or 4236 * not. 4237 */ 4238 if (!hw->autoneg) 4239 return -E1000_ERR_CONFIG; 4240 4241 /* optimize the dsp settings for the igp phy */ 4242 em_config_dsp_after_link_change(hw, TRUE); 4243 /* 4244 * We have a M88E1000 PHY and Auto-Neg is enabled. If we 4245 * have Si on board that is 82544 or newer, Auto Speed 4246 * Detection takes care of MAC speed/duplex configuration. 4247 * So we only need to configure Collision Distance in the 4248 * MAC. Otherwise, we need to force speed/duplex on the MAC 4249 * to the current PHY speed/duplex settings. 4250 */ 4251 if (hw->mac_type >= em_82544 && hw->mac_type != em_icp_xxxx) { 4252 em_config_collision_dist(hw); 4253 } else { 4254 ret_val = em_config_mac_to_phy(hw); 4255 if (ret_val) { 4256 DEBUGOUT("Error configuring MAC to PHY" 4257 " settings\n"); 4258 return ret_val; 4259 } 4260 } 4261 /* 4262 * Configure Flow Control now that Auto-Neg has completed. 4263 * First, we need to restore the desired flow control 4264 * settings because we may have had to re-autoneg with a 4265 * different link partner. 4266 */ 4267 ret_val = em_config_fc_after_link_up(hw); 4268 if (ret_val) { 4269 DEBUGOUT("Error configuring flow control\n"); 4270 return ret_val; 4271 } 4272 /* 4273 * At this point we know that we are on copper and we have 4274 * auto-negotiated link. These are conditions for checking 4275 * the link partner capability register. We use the link 4276 * speed to determine if TBI compatibility needs to be turned 4277 * on or off. If the link is not at gigabit speed, then TBI 4278 * compatibility is not needed. If we are at gigabit speed, 4279 * we turn on TBI compatibility. 4280 */ 4281 if (hw->tbi_compatibility_en) { 4282 uint16_t speed, duplex; 4283 ret_val = em_get_speed_and_duplex(hw, &speed, &duplex); 4284 if (ret_val) { 4285 DEBUGOUT("Error getting link speed and duplex" 4286 "\n"); 4287 return ret_val; 4288 } 4289 if (speed != SPEED_1000) { 4290 /* 4291 * If link speed is not set to gigabit speed, 4292 * we do not need to enable TBI 4293 * compatibility. 4294 */ 4295 if (hw->tbi_compatibility_on) { 4296 /* 4297 * If we previously were in the mode, 4298 * turn it off. 4299 */ 4300 rctl = E1000_READ_REG(hw, RCTL); 4301 rctl &= ~E1000_RCTL_SBP; 4302 E1000_WRITE_REG(hw, RCTL, rctl); 4303 hw->tbi_compatibility_on = FALSE; 4304 } 4305 } else { 4306 /* 4307 * If TBI compatibility is was previously 4308 * off, turn it on. For compatibility with a 4309 * TBI link partner, we will store bad 4310 * packets. Some frames have an additional 4311 * byte on the end and will look like CRC 4312 * errors to to the hardware. 4313 */ 4314 if (!hw->tbi_compatibility_on) { 4315 hw->tbi_compatibility_on = TRUE; 4316 rctl = E1000_READ_REG(hw, RCTL); 4317 rctl |= E1000_RCTL_SBP; 4318 E1000_WRITE_REG(hw, RCTL, rctl); 4319 } 4320 } 4321 } 4322 } 4323 /* 4324 * If we don't have link (auto-negotiation failed or link partner 4325 * cannot auto-negotiate), the cable is plugged in (we have signal), 4326 * and our link partner is not trying to auto-negotiate with us (we 4327 * are receiving idles or data), we need to force link up. We also 4328 * need to give auto-negotiation time to complete, in case the cable 4329 * was just plugged in. The autoneg_failed flag does this. 4330 */ 4331 else if ((((hw->media_type == em_media_type_fiber) && 4332 ((ctrl & E1000_CTRL_SWDPIN1) == signal)) || 4333 (hw->media_type == em_media_type_internal_serdes)) && 4334 (!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) { 4335 if (hw->autoneg_failed == 0) { 4336 hw->autoneg_failed = 1; 4337 return 0; 4338 } 4339 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 4340 4341 /* Disable auto-negotiation in the TXCW register */ 4342 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE)); 4343 4344 /* Force link-up and also force full-duplex. */ 4345 ctrl = E1000_READ_REG(hw, CTRL); 4346 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 4347 E1000_WRITE_REG(hw, CTRL, ctrl); 4348 4349 /* Configure Flow Control after forcing link up. */ 4350 ret_val = em_config_fc_after_link_up(hw); 4351 if (ret_val) { 4352 DEBUGOUT("Error configuring flow control\n"); 4353 return ret_val; 4354 } 4355 } 4356 /* 4357 * If we are forcing link and we are receiving /C/ ordered sets, 4358 * re-enable auto-negotiation in the TXCW register and disable forced 4359 * link in the Device Control register in an attempt to 4360 * auto-negotiate with our link partner. 4361 */ 4362 else if (((hw->media_type == em_media_type_fiber) || 4363 (hw->media_type == em_media_type_internal_serdes)) && 4364 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 4365 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 4366 E1000_WRITE_REG(hw, TXCW, hw->txcw); 4367 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU)); 4368 4369 hw->serdes_link_down = FALSE; 4370 } 4371 /* 4372 * If we force link for non-auto-negotiation switch, check link 4373 * status based on MAC synchronization for internal serdes media 4374 * type. 4375 */ 4376 else if ((hw->media_type == em_media_type_internal_serdes) && 4377 !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) { 4378 /* SYNCH bit and IV bit are sticky. */ 4379 usec_delay(10); 4380 if (E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) { 4381 if (!(rxcw & E1000_RXCW_IV)) { 4382 hw->serdes_link_down = FALSE; 4383 DEBUGOUT("SERDES: Link is up.\n"); 4384 } 4385 } else { 4386 hw->serdes_link_down = TRUE; 4387 DEBUGOUT("SERDES: Link is down.\n"); 4388 } 4389 } 4390 if ((hw->media_type == em_media_type_internal_serdes) && 4391 (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) { 4392 hw->serdes_link_down = !(E1000_STATUS_LU & 4393 E1000_READ_REG(hw, STATUS)); 4394 } 4395 return E1000_SUCCESS; 4396 } 4397 4398 int32_t 4399 em_get_pcs_speed_and_duplex_82575(struct em_hw *hw, uint16_t *speed, 4400 uint16_t *duplex) 4401 { 4402 uint32_t pcs; 4403 4404 hw->serdes_link_down = TRUE; 4405 *speed = 0; 4406 *duplex = 0; 4407 4408 /* 4409 * Read the PCS Status register for link state. For non-copper mode, 4410 * the status register is not accurate. The PCS status register is 4411 * used instead. 4412 */ 4413 pcs = E1000_READ_REG(hw, PCS_LSTAT); 4414 4415 /* 4416 * The link up bit determines when link is up on autoneg. The sync ok 4417 * gets set once both sides sync up and agree upon link. Stable link 4418 * can be determined by checking for both link up and link sync ok 4419 */ 4420 if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) { 4421 hw->serdes_link_down = FALSE; 4422 4423 /* Detect and store PCS speed */ 4424 if (pcs & E1000_PCS_LSTS_SPEED_1000) { 4425 *speed = SPEED_1000; 4426 } else if (pcs & E1000_PCS_LSTS_SPEED_100) { 4427 *speed = SPEED_100; 4428 } else { 4429 *speed = SPEED_10; 4430 } 4431 4432 /* Detect and store PCS duplex */ 4433 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) { 4434 *duplex = FULL_DUPLEX; 4435 } else { 4436 *duplex = HALF_DUPLEX; 4437 } 4438 } 4439 4440 return (0); 4441 } 4442 4443 4444 /****************************************************************************** 4445 * Detects the current speed and duplex settings of the hardware. 4446 * 4447 * hw - Struct containing variables accessed by shared code 4448 * speed - Speed of the connection 4449 * duplex - Duplex setting of the connection 4450 *****************************************************************************/ 4451 int32_t 4452 em_get_speed_and_duplex(struct em_hw *hw, uint16_t *speed, uint16_t *duplex) 4453 { 4454 uint32_t status; 4455 int32_t ret_val; 4456 uint16_t phy_data; 4457 DEBUGFUNC("em_get_speed_and_duplex"); 4458 4459 if (hw->mac_type >= em_82575 && hw->media_type != em_media_type_copper) 4460 return em_get_pcs_speed_and_duplex_82575(hw, speed, duplex); 4461 4462 if (hw->mac_type >= em_82543) { 4463 status = E1000_READ_REG(hw, STATUS); 4464 if (status & E1000_STATUS_SPEED_1000) { 4465 *speed = SPEED_1000; 4466 DEBUGOUT("1000 Mbs, "); 4467 } else if (status & E1000_STATUS_SPEED_100) { 4468 *speed = SPEED_100; 4469 DEBUGOUT("100 Mbs, "); 4470 } else { 4471 *speed = SPEED_10; 4472 DEBUGOUT("10 Mbs, "); 4473 } 4474 4475 if (status & E1000_STATUS_FD) { 4476 *duplex = FULL_DUPLEX; 4477 DEBUGOUT("Full Duplex\n"); 4478 } else { 4479 *duplex = HALF_DUPLEX; 4480 DEBUGOUT(" Half Duplex\n"); 4481 } 4482 } else { 4483 DEBUGOUT("1000 Mbs, Full Duplex\n"); 4484 *speed = SPEED_1000; 4485 *duplex = FULL_DUPLEX; 4486 } 4487 /* 4488 * IGP01 PHY may advertise full duplex operation after speed 4489 * downgrade even if it is operating at half duplex. Here we set the 4490 * duplex settings to match the duplex in the link partner's 4491 * capabilities. 4492 */ 4493 if (hw->phy_type == em_phy_igp && hw->speed_downgraded) { 4494 ret_val = em_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data); 4495 if (ret_val) 4496 return ret_val; 4497 4498 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS)) 4499 *duplex = HALF_DUPLEX; 4500 else { 4501 ret_val = em_read_phy_reg(hw, PHY_LP_ABILITY, 4502 &phy_data); 4503 if (ret_val) 4504 return ret_val; 4505 if ((*speed == SPEED_100 && 4506 !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) || 4507 (*speed == SPEED_10 && 4508 !(phy_data & NWAY_LPAR_10T_FD_CAPS))) 4509 *duplex = HALF_DUPLEX; 4510 } 4511 } 4512 if ((hw->mac_type == em_80003es2lan) && 4513 (hw->media_type == em_media_type_copper)) { 4514 if (*speed == SPEED_1000) 4515 ret_val = em_configure_kmrn_for_1000(hw); 4516 else 4517 ret_val = em_configure_kmrn_for_10_100(hw, *duplex); 4518 if (ret_val) 4519 return ret_val; 4520 } 4521 if ((hw->mac_type == em_ich8lan) && 4522 (hw->phy_type == em_phy_igp_3) && 4523 (*speed == SPEED_1000)) { 4524 ret_val = em_kumeran_lock_loss_workaround(hw); 4525 if (ret_val) 4526 return ret_val; 4527 } 4528 return E1000_SUCCESS; 4529 } 4530 4531 /****************************************************************************** 4532 * Blocks until autoneg completes or times out (~4.5 seconds) 4533 * 4534 * hw - Struct containing variables accessed by shared code 4535 *****************************************************************************/ 4536 STATIC int32_t 4537 em_wait_autoneg(struct em_hw *hw) 4538 { 4539 int32_t ret_val; 4540 uint16_t i; 4541 uint16_t phy_data; 4542 DEBUGFUNC("em_wait_autoneg"); 4543 DEBUGOUT("Waiting for Auto-Neg to complete.\n"); 4544 4545 /* We will wait for autoneg to complete or 4.5 seconds to expire. */ 4546 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) { 4547 /* 4548 * Read the MII Status Register and wait for Auto-Neg 4549 * Complete bit to be set. 4550 */ 4551 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 4552 if (ret_val) 4553 return ret_val; 4554 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 4555 if (ret_val) 4556 return ret_val; 4557 if (phy_data & MII_SR_AUTONEG_COMPLETE) { 4558 return E1000_SUCCESS; 4559 } 4560 msec_delay(100); 4561 } 4562 return E1000_SUCCESS; 4563 } 4564 4565 /****************************************************************************** 4566 * Raises the Management Data Clock 4567 * 4568 * hw - Struct containing variables accessed by shared code 4569 * ctrl - Device control register's current value 4570 *****************************************************************************/ 4571 static void 4572 em_raise_mdi_clk(struct em_hw *hw, uint32_t *ctrl) 4573 { 4574 /* 4575 * Raise the clock input to the Management Data Clock (by setting the 4576 * MDC bit), and then delay 10 microseconds. 4577 */ 4578 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC)); 4579 E1000_WRITE_FLUSH(hw); 4580 usec_delay(10); 4581 } 4582 4583 /****************************************************************************** 4584 * Lowers the Management Data Clock 4585 * 4586 * hw - Struct containing variables accessed by shared code 4587 * ctrl - Device control register's current value 4588 *****************************************************************************/ 4589 static void 4590 em_lower_mdi_clk(struct em_hw *hw, uint32_t *ctrl) 4591 { 4592 /* 4593 * Lower the clock input to the Management Data Clock (by clearing 4594 * the MDC bit), and then delay 10 microseconds. 4595 */ 4596 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC)); 4597 E1000_WRITE_FLUSH(hw); 4598 usec_delay(10); 4599 } 4600 4601 /****************************************************************************** 4602 * Shifts data bits out to the PHY 4603 * 4604 * hw - Struct containing variables accessed by shared code 4605 * data - Data to send out to the PHY 4606 * count - Number of bits to shift out 4607 * 4608 * Bits are shifted out in MSB to LSB order. 4609 *****************************************************************************/ 4610 static void 4611 em_shift_out_mdi_bits(struct em_hw *hw, uint32_t data, uint16_t count) 4612 { 4613 uint32_t ctrl; 4614 uint32_t mask; 4615 /* 4616 * We need to shift "count" number of bits out to the PHY. So, the 4617 * value in the "data" parameter will be shifted out to the PHY one 4618 * bit at a time. In order to do this, "data" must be broken down 4619 * into bits. 4620 */ 4621 mask = 0x01; 4622 mask <<= (count - 1); 4623 4624 ctrl = E1000_READ_REG(hw, CTRL); 4625 4626 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output 4627 * pins. 4628 */ 4629 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); 4630 4631 while (mask) { 4632 /* 4633 * A "1" is shifted out to the PHY by setting the MDIO bit to 4634 * "1" and then raising and lowering the Management Data 4635 * Clock. A "0" is shifted out to the PHY by setting the MDIO 4636 * bit to "0" and then raising and lowering the clock. 4637 */ 4638 if (data & mask) 4639 ctrl |= E1000_CTRL_MDIO; 4640 else 4641 ctrl &= ~E1000_CTRL_MDIO; 4642 4643 E1000_WRITE_REG(hw, CTRL, ctrl); 4644 E1000_WRITE_FLUSH(hw); 4645 4646 usec_delay(10); 4647 4648 em_raise_mdi_clk(hw, &ctrl); 4649 em_lower_mdi_clk(hw, &ctrl); 4650 4651 mask = mask >> 1; 4652 } 4653 } 4654 4655 /****************************************************************************** 4656 * Shifts data bits in from the PHY 4657 * 4658 * hw - Struct containing variables accessed by shared code 4659 * 4660 * Bits are shifted in in MSB to LSB order. 4661 *****************************************************************************/ 4662 static uint16_t 4663 em_shift_in_mdi_bits(struct em_hw *hw) 4664 { 4665 uint32_t ctrl; 4666 uint16_t data = 0; 4667 uint8_t i; 4668 /* 4669 * In order to read a register from the PHY, we need to shift in a 4670 * total of 18 bits from the PHY. The first two bit (turnaround) 4671 * times are used to avoid contention on the MDIO pin when a read 4672 * operation is performed. These two bits are ignored by us and 4673 * thrown away. Bits are "shifted in" by raising the input to the 4674 * Management Data Clock (setting the MDC bit), and then reading the 4675 * value of the MDIO bit. 4676 */ 4677 ctrl = E1000_READ_REG(hw, CTRL); 4678 /* 4679 * Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as 4680 * input. 4681 */ 4682 ctrl &= ~E1000_CTRL_MDIO_DIR; 4683 ctrl &= ~E1000_CTRL_MDIO; 4684 4685 E1000_WRITE_REG(hw, CTRL, ctrl); 4686 E1000_WRITE_FLUSH(hw); 4687 /* 4688 * Raise and Lower the clock before reading in the data. This 4689 * accounts for the turnaround bits. The first clock occurred when we 4690 * clocked out the last bit of the Register Address. 4691 */ 4692 em_raise_mdi_clk(hw, &ctrl); 4693 em_lower_mdi_clk(hw, &ctrl); 4694 4695 for (data = 0, i = 0; i < 16; i++) { 4696 data = data << 1; 4697 em_raise_mdi_clk(hw, &ctrl); 4698 ctrl = E1000_READ_REG(hw, CTRL); 4699 /* Check to see if we shifted in a "1". */ 4700 if (ctrl & E1000_CTRL_MDIO) 4701 data |= 1; 4702 em_lower_mdi_clk(hw, &ctrl); 4703 } 4704 4705 em_raise_mdi_clk(hw, &ctrl); 4706 em_lower_mdi_clk(hw, &ctrl); 4707 4708 return data; 4709 } 4710 4711 STATIC int32_t 4712 em_swfw_sync_acquire(struct em_hw *hw, uint16_t mask) 4713 { 4714 uint32_t swfw_sync = 0; 4715 uint32_t swmask = mask; 4716 uint32_t fwmask = mask << 16; 4717 int32_t timeout = 200; 4718 DEBUGFUNC("em_swfw_sync_acquire"); 4719 4720 if (hw->swfwhw_semaphore_present) 4721 return em_get_software_flag(hw); 4722 4723 if (!hw->swfw_sync_present) 4724 return em_get_hw_eeprom_semaphore(hw); 4725 4726 while (timeout) { 4727 if (em_get_hw_eeprom_semaphore(hw)) 4728 return -E1000_ERR_SWFW_SYNC; 4729 4730 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); 4731 if (!(swfw_sync & (fwmask | swmask))) { 4732 break; 4733 } 4734 /* 4735 * firmware currently using resource (fwmask) 4736 * or other software thread currently using resource (swmask) 4737 */ 4738 em_put_hw_eeprom_semaphore(hw); 4739 msec_delay_irq(5); 4740 timeout--; 4741 } 4742 4743 if (!timeout) { 4744 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout." 4745 "\n"); 4746 return -E1000_ERR_SWFW_SYNC; 4747 } 4748 swfw_sync |= swmask; 4749 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync); 4750 4751 em_put_hw_eeprom_semaphore(hw); 4752 return E1000_SUCCESS; 4753 } 4754 4755 STATIC void 4756 em_swfw_sync_release(struct em_hw *hw, uint16_t mask) 4757 { 4758 uint32_t swfw_sync; 4759 uint32_t swmask = mask; 4760 DEBUGFUNC("em_swfw_sync_release"); 4761 4762 if (hw->swfwhw_semaphore_present) { 4763 em_release_software_flag(hw); 4764 return; 4765 } 4766 if (!hw->swfw_sync_present) { 4767 em_put_hw_eeprom_semaphore(hw); 4768 return; 4769 } 4770 /* 4771 * if (em_get_hw_eeprom_semaphore(hw)) return -E1000_ERR_SWFW_SYNC; 4772 */ 4773 while (em_get_hw_eeprom_semaphore(hw) != E1000_SUCCESS); 4774 /* empty */ 4775 4776 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); 4777 swfw_sync &= ~swmask; 4778 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync); 4779 4780 em_put_hw_eeprom_semaphore(hw); 4781 } 4782 4783 /**************************************************************************** 4784 * Read BM PHY wakeup register. It works as such: 4785 * 1) Set page 769, register 17, bit 2 = 1 4786 * 2) Set page to 800 for host (801 if we were manageability) 4787 * 3) Write the address using the address opcode (0x11) 4788 * 4) Read or write the data using the data opcode (0x12) 4789 * 5) Restore 769_17.2 to its original value 4790 ****************************************************************************/ 4791 int32_t 4792 em_access_phy_wakeup_reg_bm(struct em_hw *hw, uint32_t reg_addr, 4793 uint16_t *phy_data, boolean_t read) 4794 { 4795 int32_t ret_val; 4796 uint16_t reg = BM_PHY_REG_NUM(reg_addr); 4797 uint16_t phy_reg = 0; 4798 4799 /* All operations in this function are phy address 1 */ 4800 hw->phy_addr = 1; 4801 4802 /* Set page 769 */ 4803 em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 4804 (BM_WUC_ENABLE_PAGE << PHY_PAGE_SHIFT)); 4805 4806 ret_val = em_read_phy_reg_ex(hw, BM_WUC_ENABLE_REG, &phy_reg); 4807 if (ret_val) 4808 goto out; 4809 4810 /* First clear bit 4 to avoid a power state change */ 4811 phy_reg &= ~(BM_WUC_HOST_WU_BIT); 4812 ret_val = em_write_phy_reg_ex(hw, BM_WUC_ENABLE_REG, phy_reg); 4813 if (ret_val) 4814 goto out; 4815 4816 /* Write bit 2 = 1, and clear bit 4 to 769_17 */ 4817 ret_val = em_write_phy_reg_ex(hw, BM_WUC_ENABLE_REG, 4818 phy_reg | BM_WUC_ENABLE_BIT); 4819 if (ret_val) 4820 goto out; 4821 4822 /* Select page 800 */ 4823 ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 4824 (BM_WUC_PAGE << PHY_PAGE_SHIFT)); 4825 4826 /* Write the page 800 offset value using opcode 0x11 */ 4827 ret_val = em_write_phy_reg_ex(hw, BM_WUC_ADDRESS_OPCODE, reg); 4828 if (ret_val) 4829 goto out; 4830 4831 if (read) 4832 /* Read the page 800 value using opcode 0x12 */ 4833 ret_val = em_read_phy_reg_ex(hw, BM_WUC_DATA_OPCODE, 4834 phy_data); 4835 else 4836 /* Write the page 800 value using opcode 0x12 */ 4837 ret_val = em_write_phy_reg_ex(hw, BM_WUC_DATA_OPCODE, 4838 *phy_data); 4839 4840 if (ret_val) 4841 goto out; 4842 4843 /* 4844 * Restore 769_17.2 to its original value 4845 * Set page 769 4846 */ 4847 em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 4848 (BM_WUC_ENABLE_PAGE << PHY_PAGE_SHIFT)); 4849 4850 /* Clear 769_17.2 */ 4851 ret_val = em_write_phy_reg_ex(hw, BM_WUC_ENABLE_REG, phy_reg); 4852 if (ret_val) 4853 goto out; 4854 4855 out: 4856 return ret_val; 4857 } 4858 4859 /*************************************************************************** 4860 * Read HV PHY vendor specific high registers 4861 ***************************************************************************/ 4862 int32_t 4863 em_access_phy_debug_regs_hv(struct em_hw *hw, uint32_t reg_addr, 4864 uint16_t *phy_data, boolean_t read) 4865 { 4866 int32_t ret_val; 4867 uint32_t addr_reg = 0; 4868 uint32_t data_reg = 0; 4869 4870 /* This takes care of the difference with desktop vs mobile phy */ 4871 addr_reg = (hw->phy_type == em_phy_82578) ? 4872 I82578_PHY_ADDR_REG : I82577_PHY_ADDR_REG; 4873 data_reg = addr_reg + 1; 4874 4875 /* All operations in this function are phy address 2 */ 4876 hw->phy_addr = 2; 4877 4878 /* masking with 0x3F to remove the page from offset */ 4879 ret_val = em_write_phy_reg_ex(hw, addr_reg, (uint16_t)reg_addr & 0x3F); 4880 if (ret_val) { 4881 printf("Could not write PHY the HV address register\n"); 4882 goto out; 4883 } 4884 4885 /* Read or write the data value next */ 4886 if (read) 4887 ret_val = em_read_phy_reg_ex(hw, data_reg, phy_data); 4888 else 4889 ret_val = em_write_phy_reg_ex(hw, data_reg, *phy_data); 4890 4891 if (ret_val) { 4892 printf("Could not read data value from HV data register\n"); 4893 goto out; 4894 } 4895 4896 out: 4897 return ret_val; 4898 } 4899 4900 /****************************************************************************** 4901 * Reads or writes the value from a PHY register, if the value is on a specific 4902 * non zero page, sets the page first. 4903 * hw - Struct containing variables accessed by shared code 4904 * reg_addr - address of the PHY register to read 4905 *****************************************************************************/ 4906 int32_t 4907 em_access_phy_reg_hv(struct em_hw *hw, uint32_t reg_addr, uint16_t *phy_data, 4908 boolean_t read) 4909 { 4910 uint32_t ret_val; 4911 uint16_t swfw; 4912 uint16_t page = BM_PHY_REG_PAGE(reg_addr); 4913 uint16_t reg = BM_PHY_REG_NUM(reg_addr); 4914 4915 DEBUGFUNC("em_access_phy_reg_hv"); 4916 4917 swfw = E1000_SWFW_PHY0_SM; 4918 4919 if (em_swfw_sync_acquire(hw, swfw)) 4920 return -E1000_ERR_SWFW_SYNC; 4921 4922 if (page == BM_WUC_PAGE) { 4923 ret_val = em_access_phy_wakeup_reg_bm(hw, reg_addr, 4924 phy_data, read); 4925 goto release; 4926 } 4927 4928 if (page >= HV_INTC_FC_PAGE_START) 4929 hw->phy_addr = 1; 4930 else 4931 hw->phy_addr = 2; 4932 4933 if (page == HV_INTC_FC_PAGE_START) 4934 page = 0; 4935 4936 /* 4937 * Workaround MDIO accesses being disabled after entering IEEE Power 4938 * Down (whenever bit 11 of the PHY Control register is set) 4939 */ 4940 if (!read && 4941 (hw->phy_type == em_phy_82578) && 4942 (hw->phy_revision >= 1) && 4943 (hw->phy_addr == 2) && 4944 ((MAX_PHY_REG_ADDRESS & reg) == 0) && 4945 (*phy_data & (1 << 11))) { 4946 uint16_t data2 = 0x7EFF; 4947 4948 ret_val = em_access_phy_debug_regs_hv(hw, (1 << 6) | 0x3, 4949 &data2, FALSE); 4950 if (ret_val) 4951 return ret_val; 4952 } 4953 4954 if (reg_addr > MAX_PHY_MULTI_PAGE_REG) { 4955 ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 4956 (page << PHY_PAGE_SHIFT)); 4957 if (ret_val) 4958 return ret_val; 4959 } 4960 if (read) 4961 ret_val = em_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg, 4962 phy_data); 4963 else 4964 ret_val = em_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg, 4965 *phy_data); 4966 release: 4967 em_swfw_sync_release(hw, swfw); 4968 return ret_val; 4969 } 4970 4971 /****************************************************************************** 4972 * Reads the value from a PHY register, if the value is on a specific non zero 4973 * page, sets the page first. 4974 * hw - Struct containing variables accessed by shared code 4975 * reg_addr - address of the PHY register to read 4976 *****************************************************************************/ 4977 int32_t 4978 em_read_phy_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t *phy_data) 4979 { 4980 uint32_t ret_val; 4981 uint16_t swfw; 4982 DEBUGFUNC("em_read_phy_reg"); 4983 4984 if (hw->mac_type == em_pchlan || 4985 hw->mac_type == em_pch2lan || 4986 hw->mac_type == em_pch_lpt || 4987 hw->mac_type == em_pch_spt || 4988 hw->mac_type == em_pch_cnp) 4989 return (em_access_phy_reg_hv(hw, reg_addr, phy_data, TRUE)); 4990 4991 if (((hw->mac_type == em_80003es2lan) || (hw->mac_type == em_82575) || 4992 (hw->mac_type == em_82576)) && 4993 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { 4994 swfw = E1000_SWFW_PHY1_SM; 4995 } else { 4996 swfw = E1000_SWFW_PHY0_SM; 4997 } 4998 if (em_swfw_sync_acquire(hw, swfw)) 4999 return -E1000_ERR_SWFW_SYNC; 5000 5001 if ((hw->phy_type == em_phy_igp || 5002 hw->phy_type == em_phy_igp_3 || 5003 hw->phy_type == em_phy_igp_2) && 5004 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { 5005 ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 5006 (uint16_t) reg_addr); 5007 if (ret_val) { 5008 em_swfw_sync_release(hw, swfw); 5009 return ret_val; 5010 } 5011 } else if (hw->phy_type == em_phy_gg82563) { 5012 if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) || 5013 (hw->mac_type == em_80003es2lan)) { 5014 /* Select Configuration Page */ 5015 if ((reg_addr & MAX_PHY_REG_ADDRESS) < 5016 GG82563_MIN_ALT_REG) { 5017 ret_val = em_write_phy_reg_ex(hw, 5018 GG82563_PHY_PAGE_SELECT, 5019 (uint16_t) ((uint16_t) reg_addr >> 5020 GG82563_PAGE_SHIFT)); 5021 } else { 5022 /* 5023 * Use Alternative Page Select register to 5024 * access registers 30 and 31 5025 */ 5026 ret_val = em_write_phy_reg_ex(hw, 5027 GG82563_PHY_PAGE_SELECT_ALT, 5028 (uint16_t) ((uint16_t) reg_addr >> 5029 GG82563_PAGE_SHIFT)); 5030 } 5031 5032 if (ret_val) { 5033 em_swfw_sync_release(hw, swfw); 5034 return ret_val; 5035 } 5036 } 5037 } else if ((hw->phy_type == em_phy_bm) && (hw->phy_revision == 1)) { 5038 if (reg_addr > MAX_PHY_MULTI_PAGE_REG) { 5039 ret_val = em_write_phy_reg_ex(hw, BM_PHY_PAGE_SELECT, 5040 (uint16_t) ((uint16_t) reg_addr >> 5041 PHY_PAGE_SHIFT)); 5042 if (ret_val) 5043 return ret_val; 5044 } 5045 } 5046 ret_val = em_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, 5047 phy_data); 5048 5049 em_swfw_sync_release(hw, swfw); 5050 return ret_val; 5051 } 5052 5053 STATIC int32_t 5054 em_read_phy_reg_ex(struct em_hw *hw, uint32_t reg_addr, uint16_t *phy_data) 5055 { 5056 uint32_t i; 5057 uint32_t mdic = 0; 5058 DEBUGFUNC("em_read_phy_reg_ex"); 5059 5060 if (reg_addr > MAX_PHY_REG_ADDRESS) { 5061 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); 5062 return -E1000_ERR_PARAM; 5063 } 5064 if (hw->mac_type == em_icp_xxxx) { 5065 *phy_data = gcu_miibus_readreg(hw, hw->icp_xxxx_port_num, 5066 reg_addr); 5067 return E1000_SUCCESS; 5068 } 5069 if (hw->mac_type > em_82543) { 5070 /* 5071 * Set up Op-code, Phy Address, and register address in the 5072 * MDI Control register. The MAC will take care of 5073 * interfacing with the PHY to retrieve the desired data. 5074 */ 5075 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) | 5076 (hw->phy_addr << E1000_MDIC_PHY_SHIFT) | 5077 (E1000_MDIC_OP_READ)); 5078 5079 E1000_WRITE_REG(hw, MDIC, mdic); 5080 5081 /* 5082 * Poll the ready bit to see if the MDI read completed 5083 * Increasing the time out as testing showed failures with 5084 * the lower time out (from FreeBSD driver) 5085 */ 5086 for (i = 0; i < 1960; i++) { 5087 usec_delay(50); 5088 mdic = E1000_READ_REG(hw, MDIC); 5089 if (mdic & E1000_MDIC_READY) 5090 break; 5091 } 5092 if (!(mdic & E1000_MDIC_READY)) { 5093 DEBUGOUT("MDI Read did not complete\n"); 5094 return -E1000_ERR_PHY; 5095 } 5096 if (mdic & E1000_MDIC_ERROR) { 5097 DEBUGOUT("MDI Error\n"); 5098 return -E1000_ERR_PHY; 5099 } 5100 *phy_data = (uint16_t) mdic; 5101 5102 if (hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt || 5103 hw->mac_type == em_pch_spt || hw->mac_type == em_pch_cnp) 5104 usec_delay(100); 5105 } else { 5106 /* 5107 * We must first send a preamble through the MDIO pin to 5108 * signal the beginning of an MII instruction. This is done 5109 * by sending 32 consecutive "1" bits. 5110 */ 5111 em_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 5112 /* 5113 * Now combine the next few fields that are required for a 5114 * read operation. We use this method instead of calling the 5115 * em_shift_out_mdi_bits routine five different times. The 5116 * format of a MII read instruction consists of a shift out 5117 * of 14 bits and is defined as follows: <Preamble><SOF><Op 5118 * Code><Phy Addr><Reg Addr> followed by a shift in of 18 5119 * bits. This first two bits shifted in are TurnAround bits 5120 * used to avoid contention on the MDIO pin when a READ 5121 * operation is performed. These two bits are thrown away 5122 * followed by a shift in of 16 bits which contains the 5123 * desired data. 5124 */ 5125 mdic = ((reg_addr) | (hw->phy_addr << 5) | 5126 (PHY_OP_READ << 10) | (PHY_SOF << 12)); 5127 5128 em_shift_out_mdi_bits(hw, mdic, 14); 5129 /* 5130 * Now that we've shifted out the read command to the MII, we 5131 * need to "shift in" the 16-bit value (18 total bits) of the 5132 * requested PHY register address. 5133 */ 5134 *phy_data = em_shift_in_mdi_bits(hw); 5135 } 5136 return E1000_SUCCESS; 5137 } 5138 5139 /****************************************************************************** 5140 * Writes a value to a PHY register 5141 * 5142 * hw - Struct containing variables accessed by shared code 5143 * reg_addr - address of the PHY register to write 5144 * data - data to write to the PHY 5145 *****************************************************************************/ 5146 int32_t 5147 em_write_phy_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t phy_data) 5148 { 5149 uint32_t ret_val; 5150 DEBUGFUNC("em_write_phy_reg"); 5151 5152 if (hw->mac_type == em_pchlan || 5153 hw->mac_type == em_pch2lan || 5154 hw->mac_type == em_pch_lpt || 5155 hw->mac_type == em_pch_spt || 5156 hw->mac_type == em_pch_cnp) 5157 return (em_access_phy_reg_hv(hw, reg_addr, &phy_data, FALSE)); 5158 5159 if (em_swfw_sync_acquire(hw, hw->swfw)) 5160 return -E1000_ERR_SWFW_SYNC; 5161 5162 if ((hw->phy_type == em_phy_igp || 5163 hw->phy_type == em_phy_igp_3 || 5164 hw->phy_type == em_phy_igp_2) && 5165 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { 5166 ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 5167 (uint16_t) reg_addr); 5168 if (ret_val) { 5169 em_swfw_sync_release(hw, hw->swfw); 5170 return ret_val; 5171 } 5172 } else if (hw->phy_type == em_phy_gg82563) { 5173 if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) || 5174 (hw->mac_type == em_80003es2lan)) { 5175 /* Select Configuration Page */ 5176 if ((reg_addr & MAX_PHY_REG_ADDRESS) < 5177 GG82563_MIN_ALT_REG) { 5178 ret_val = em_write_phy_reg_ex(hw, 5179 GG82563_PHY_PAGE_SELECT, 5180 (uint16_t) ((uint16_t) reg_addr >> 5181 GG82563_PAGE_SHIFT)); 5182 } else { 5183 /* 5184 * Use Alternative Page Select register to 5185 * access registers 30 and 31 5186 */ 5187 ret_val = em_write_phy_reg_ex(hw, 5188 GG82563_PHY_PAGE_SELECT_ALT, 5189 (uint16_t) ((uint16_t) reg_addr >> 5190 GG82563_PAGE_SHIFT)); 5191 } 5192 5193 if (ret_val) { 5194 em_swfw_sync_release(hw, hw->swfw); 5195 return ret_val; 5196 } 5197 } 5198 } else if ((hw->phy_type == em_phy_bm) && (hw->phy_revision == 1)) { 5199 if (reg_addr > MAX_PHY_MULTI_PAGE_REG) { 5200 ret_val = em_write_phy_reg_ex(hw, BM_PHY_PAGE_SELECT, 5201 (uint16_t) ((uint16_t) reg_addr >> 5202 PHY_PAGE_SHIFT)); 5203 if (ret_val) 5204 return ret_val; 5205 } 5206 } 5207 ret_val = em_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, 5208 phy_data); 5209 5210 em_swfw_sync_release(hw, hw->swfw); 5211 return ret_val; 5212 } 5213 5214 STATIC int32_t 5215 em_write_phy_reg_ex(struct em_hw *hw, uint32_t reg_addr, uint16_t phy_data) 5216 { 5217 uint32_t i; 5218 uint32_t mdic = 0; 5219 DEBUGFUNC("em_write_phy_reg_ex"); 5220 5221 if (reg_addr > MAX_PHY_REG_ADDRESS) { 5222 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); 5223 return -E1000_ERR_PARAM; 5224 } 5225 if (hw->mac_type == em_icp_xxxx) { 5226 gcu_miibus_writereg(hw, hw->icp_xxxx_port_num, 5227 reg_addr, phy_data); 5228 return E1000_SUCCESS; 5229 } 5230 if (hw->mac_type > em_82543) { 5231 /* 5232 * Set up Op-code, Phy Address, register address, and data 5233 * intended for the PHY register in the MDI Control register. 5234 * The MAC will take care of interfacing with the PHY to send 5235 * the desired data. 5236 */ 5237 mdic = (((uint32_t) phy_data) | 5238 (reg_addr << E1000_MDIC_REG_SHIFT) | 5239 (hw->phy_addr << E1000_MDIC_PHY_SHIFT) | 5240 (E1000_MDIC_OP_WRITE)); 5241 5242 E1000_WRITE_REG(hw, MDIC, mdic); 5243 5244 /* Poll the ready bit to see if the MDI read completed */ 5245 for (i = 0; i < 641; i++) { 5246 usec_delay(5); 5247 mdic = E1000_READ_REG(hw, MDIC); 5248 if (mdic & E1000_MDIC_READY) 5249 break; 5250 } 5251 if (!(mdic & E1000_MDIC_READY)) { 5252 DEBUGOUT("MDI Write did not complete\n"); 5253 return -E1000_ERR_PHY; 5254 } 5255 5256 if (hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt || 5257 hw->mac_type == em_pch_spt || hw->mac_type == em_pch_cnp) 5258 usec_delay(100); 5259 } else { 5260 /* 5261 * We'll need to use the SW defined pins to shift the write 5262 * command out to the PHY. We first send a preamble to the 5263 * PHY to signal the beginning of the MII instruction. This 5264 * is done by sending 32 consecutive "1" bits. 5265 */ 5266 em_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 5267 /* 5268 * Now combine the remaining required fields that will 5269 * indicate a write operation. We use this method instead of 5270 * calling the em_shift_out_mdi_bits routine for each field 5271 * in the command. The format of a MII write instruction is 5272 * as follows: <Preamble><SOF><Op Code><Phy Addr><Reg 5273 * Addr><Turnaround><Data>. 5274 */ 5275 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | 5276 (hw->phy_addr << 7) | (PHY_OP_WRITE << 12) | 5277 (PHY_SOF << 14)); 5278 mdic <<= 16; 5279 mdic |= (uint32_t) phy_data; 5280 5281 em_shift_out_mdi_bits(hw, mdic, 32); 5282 } 5283 5284 return E1000_SUCCESS; 5285 } 5286 5287 STATIC int32_t 5288 em_read_kmrn_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t *data) 5289 { 5290 uint32_t reg_val; 5291 DEBUGFUNC("em_read_kmrn_reg"); 5292 5293 if (em_swfw_sync_acquire(hw, hw->swfw)) 5294 return -E1000_ERR_SWFW_SYNC; 5295 5296 /* Write register address */ 5297 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) & 5298 E1000_KUMCTRLSTA_OFFSET) | 5299 E1000_KUMCTRLSTA_REN; 5300 5301 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); 5302 usec_delay(2); 5303 5304 /* Read the data returned */ 5305 reg_val = E1000_READ_REG(hw, KUMCTRLSTA); 5306 *data = (uint16_t) reg_val; 5307 5308 em_swfw_sync_release(hw, hw->swfw); 5309 return E1000_SUCCESS; 5310 } 5311 5312 STATIC int32_t 5313 em_write_kmrn_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t data) 5314 { 5315 uint32_t reg_val; 5316 DEBUGFUNC("em_write_kmrn_reg"); 5317 5318 if (em_swfw_sync_acquire(hw, hw->swfw)) 5319 return -E1000_ERR_SWFW_SYNC; 5320 5321 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) & 5322 E1000_KUMCTRLSTA_OFFSET) | data; 5323 5324 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); 5325 usec_delay(2); 5326 5327 em_swfw_sync_release(hw, hw->swfw); 5328 return E1000_SUCCESS; 5329 } 5330 5331 /****************************************************************************** 5332 * Returns the PHY to the power-on reset state 5333 * 5334 * hw - Struct containing variables accessed by shared code 5335 *****************************************************************************/ 5336 int32_t 5337 em_phy_hw_reset(struct em_hw *hw) 5338 { 5339 uint32_t ctrl, ctrl_ext; 5340 uint32_t led_ctrl; 5341 int32_t ret_val; 5342 DEBUGFUNC("em_phy_hw_reset"); 5343 /* 5344 * In the case of the phy reset being blocked, it's not an error, we 5345 * simply return success without performing the reset. 5346 */ 5347 ret_val = em_check_phy_reset_block(hw); 5348 if (ret_val) 5349 return E1000_SUCCESS; 5350 5351 DEBUGOUT("Resetting Phy...\n"); 5352 5353 if (hw->mac_type > em_82543 && hw->mac_type != em_icp_xxxx) { 5354 if (em_swfw_sync_acquire(hw, hw->swfw)) { 5355 DEBUGOUT("Unable to acquire swfw sync\n"); 5356 return -E1000_ERR_SWFW_SYNC; 5357 } 5358 /* 5359 * Read the device control register and assert the 5360 * E1000_CTRL_PHY_RST bit. Then, take it out of reset. For 5361 * pre-em_82571 hardware, we delay for 10ms between the 5362 * assert and deassert. For em_82571 hardware and later, we 5363 * instead delay for 50us between and 10ms after the 5364 * deassertion. 5365 */ 5366 ctrl = E1000_READ_REG(hw, CTRL); 5367 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST); 5368 E1000_WRITE_FLUSH(hw); 5369 5370 if (hw->mac_type < em_82571) 5371 msec_delay(10); 5372 else 5373 usec_delay(100); 5374 5375 E1000_WRITE_REG(hw, CTRL, ctrl); 5376 E1000_WRITE_FLUSH(hw); 5377 5378 if (hw->mac_type >= em_82571) 5379 msec_delay_irq(10); 5380 em_swfw_sync_release(hw, hw->swfw); 5381 /* 5382 * the M88E1141_E_PHY_ID might need reset here, but nothing 5383 * proves it 5384 */ 5385 } else { 5386 /* 5387 * Read the Extended Device Control Register, assert the 5388 * PHY_RESET_DIR bit to put the PHY into reset. Then, take it 5389 * out of reset. 5390 */ 5391 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 5392 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; 5393 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; 5394 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 5395 E1000_WRITE_FLUSH(hw); 5396 msec_delay(10); 5397 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; 5398 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 5399 E1000_WRITE_FLUSH(hw); 5400 } 5401 usec_delay(150); 5402 5403 if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) { 5404 /* Configure activity LED after PHY reset */ 5405 led_ctrl = E1000_READ_REG(hw, LEDCTL); 5406 led_ctrl &= IGP_ACTIVITY_LED_MASK; 5407 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 5408 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 5409 } 5410 /* Wait for FW to finish PHY configuration. */ 5411 ret_val = em_get_phy_cfg_done(hw); 5412 if (ret_val != E1000_SUCCESS) 5413 return ret_val; 5414 em_release_software_semaphore(hw); 5415 5416 if ((hw->mac_type == em_ich8lan) && (hw->phy_type == em_phy_igp_3)) 5417 ret_val = em_init_lcd_from_nvm(hw); 5418 5419 return ret_val; 5420 } 5421 5422 /***************************************************************************** 5423 * SW-based LCD Configuration. 5424 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are 5425 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit 5426 * in NVM determines whether HW should configure LPLU and Gbe Disable. 5427 *****************************************************************************/ 5428 int32_t 5429 em_oem_bits_config_pchlan(struct em_hw *hw, boolean_t d0_state) 5430 { 5431 int32_t ret_val = E1000_SUCCESS; 5432 uint32_t mac_reg; 5433 uint16_t oem_reg; 5434 uint16_t swfw = E1000_SWFW_PHY0_SM; 5435 5436 if (hw->mac_type < em_pchlan) 5437 return ret_val; 5438 5439 ret_val = em_swfw_sync_acquire(hw, swfw); 5440 if (ret_val) 5441 return ret_val; 5442 5443 if (hw->mac_type == em_pchlan) { 5444 mac_reg = E1000_READ_REG(hw, EXTCNF_CTRL); 5445 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) 5446 goto out; 5447 } 5448 5449 mac_reg = E1000_READ_REG(hw, FEXTNVM); 5450 if (!(mac_reg & FEXTNVM_SW_CONFIG_ICH8M)) 5451 goto out; 5452 5453 mac_reg = E1000_READ_REG(hw, PHY_CTRL); 5454 5455 ret_val = em_read_phy_reg(hw, HV_OEM_BITS, &oem_reg); 5456 if (ret_val) 5457 goto out; 5458 5459 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU); 5460 5461 if (d0_state) { 5462 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE) 5463 oem_reg |= HV_OEM_BITS_GBE_DIS; 5464 5465 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU) 5466 oem_reg |= HV_OEM_BITS_LPLU; 5467 /* Restart auto-neg to activate the bits */ 5468 if (!em_check_phy_reset_block(hw)) 5469 oem_reg |= HV_OEM_BITS_RESTART_AN; 5470 5471 } else { 5472 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE | 5473 E1000_PHY_CTRL_NOND0A_GBE_DISABLE)) 5474 oem_reg |= HV_OEM_BITS_GBE_DIS; 5475 5476 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU | 5477 E1000_PHY_CTRL_NOND0A_LPLU)) 5478 oem_reg |= HV_OEM_BITS_LPLU; 5479 } 5480 5481 ret_val = em_write_phy_reg(hw, HV_OEM_BITS, oem_reg); 5482 5483 out: 5484 em_swfw_sync_release(hw, swfw); 5485 5486 return ret_val; 5487 } 5488 5489 5490 /****************************************************************************** 5491 * Resets the PHY 5492 * 5493 * hw - Struct containing variables accessed by shared code 5494 * 5495 * Sets bit 15 of the MII Control regiser 5496 *****************************************************************************/ 5497 int32_t 5498 em_phy_reset(struct em_hw *hw) 5499 { 5500 int32_t ret_val; 5501 uint16_t phy_data; 5502 DEBUGFUNC("em_phy_reset"); 5503 /* 5504 * In the case of the phy reset being blocked, it's not an error, we 5505 * simply return success without performing the reset. 5506 */ 5507 ret_val = em_check_phy_reset_block(hw); 5508 if (ret_val) 5509 return E1000_SUCCESS; 5510 5511 switch (hw->phy_type) { 5512 case em_phy_igp: 5513 case em_phy_igp_2: 5514 case em_phy_igp_3: 5515 case em_phy_ife: 5516 ret_val = em_phy_hw_reset(hw); 5517 if (ret_val) 5518 return ret_val; 5519 break; 5520 default: 5521 ret_val = em_read_phy_reg(hw, PHY_CTRL, &phy_data); 5522 if (ret_val) 5523 return ret_val; 5524 5525 phy_data |= MII_CR_RESET; 5526 ret_val = em_write_phy_reg(hw, PHY_CTRL, phy_data); 5527 if (ret_val) 5528 return ret_val; 5529 5530 usec_delay(1); 5531 break; 5532 } 5533 5534 /* Allow time for h/w to get to a quiescent state after reset */ 5535 msec_delay(10); 5536 5537 if (hw->phy_type == em_phy_igp || hw->phy_type == em_phy_igp_2) 5538 em_phy_init_script(hw); 5539 5540 if (hw->mac_type == em_pchlan) { 5541 ret_val = em_hv_phy_workarounds_ich8lan(hw); 5542 if (ret_val) 5543 return ret_val; 5544 } else if (hw->mac_type == em_pch2lan) { 5545 ret_val = em_lv_phy_workarounds_ich8lan(hw); 5546 if (ret_val) 5547 return ret_val; 5548 } 5549 5550 if (hw->mac_type >= em_pchlan) { 5551 ret_val = em_oem_bits_config_pchlan(hw, TRUE); 5552 if (ret_val) 5553 return ret_val; 5554 } 5555 5556 /* Ungate automatic PHY configuration on non-managed 82579 */ 5557 if ((hw->mac_type == em_pch2lan) && 5558 !(E1000_READ_REG(hw, FWSM) & E1000_FWSM_FW_VALID)) { 5559 msec_delay(10); 5560 em_gate_hw_phy_config_ich8lan(hw, FALSE); 5561 } 5562 5563 if (hw->phy_id == M88E1512_E_PHY_ID) { 5564 ret_val = em_initialize_M88E1512_phy(hw); 5565 if (ret_val) 5566 return ret_val; 5567 } 5568 5569 return E1000_SUCCESS; 5570 } 5571 5572 /****************************************************************************** 5573 * Work-around for 82566 Kumeran PCS lock loss: 5574 * On link status change (i.e. PCI reset, speed change) and link is up and 5575 * speed is gigabit- 5576 * 0) if workaround is optionally disabled do nothing 5577 * 1) wait 1ms for Kumeran link to come up 5578 * 2) check Kumeran Diagnostic register PCS lock loss bit 5579 * 3) if not set the link is locked (all is good), otherwise... 5580 * 4) reset the PHY 5581 * 5) repeat up to 10 times 5582 * Note: this is only called for IGP3 copper when speed is 1gb. 5583 * 5584 * hw - struct containing variables accessed by shared code 5585 *****************************************************************************/ 5586 STATIC int32_t 5587 em_kumeran_lock_loss_workaround(struct em_hw *hw) 5588 { 5589 int32_t ret_val; 5590 int32_t reg; 5591 int32_t cnt; 5592 uint16_t phy_data; 5593 if (hw->kmrn_lock_loss_workaround_disabled) 5594 return E1000_SUCCESS; 5595 /* 5596 * Make sure link is up before proceeding. If not just return. 5597 * Attempting this while link is negotiating fouled up link stability 5598 */ 5599 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 5600 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 5601 5602 if (phy_data & MII_SR_LINK_STATUS) { 5603 for (cnt = 0; cnt < 10; cnt++) { 5604 /* read once to clear */ 5605 ret_val = em_read_phy_reg(hw, IGP3_KMRN_DIAG, 5606 &phy_data); 5607 if (ret_val) 5608 return ret_val; 5609 /* and again to get new status */ 5610 ret_val = em_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data); 5611 if (ret_val) 5612 return ret_val; 5613 5614 /* check for PCS lock */ 5615 if (!(phy_data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) 5616 return E1000_SUCCESS; 5617 5618 /* Issue PHY reset */ 5619 em_phy_hw_reset(hw); 5620 msec_delay_irq(5); 5621 } 5622 /* Disable GigE link negotiation */ 5623 reg = E1000_READ_REG(hw, PHY_CTRL); 5624 E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE 5625 | E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 5626 5627 /* unable to acquire PCS lock */ 5628 return E1000_ERR_PHY; 5629 } 5630 return E1000_SUCCESS; 5631 } 5632 5633 /****************************************************************************** 5634 * Reads and matches the expected PHY address for known PHY IDs 5635 * 5636 * hw - Struct containing variables accessed by shared code 5637 *****************************************************************************/ 5638 STATIC int32_t 5639 em_match_gig_phy(struct em_hw *hw) 5640 { 5641 int32_t phy_init_status, ret_val; 5642 uint16_t phy_id_high, phy_id_low; 5643 boolean_t match = FALSE; 5644 DEBUGFUNC("em_match_gig_phy"); 5645 5646 ret_val = em_read_phy_reg(hw, PHY_ID1, &phy_id_high); 5647 if (ret_val) 5648 return ret_val; 5649 5650 hw->phy_id = (uint32_t) (phy_id_high << 16); 5651 usec_delay(20); 5652 ret_val = em_read_phy_reg(hw, PHY_ID2, &phy_id_low); 5653 if (ret_val) 5654 return ret_val; 5655 5656 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK); 5657 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK; 5658 5659 switch (hw->mac_type) { 5660 case em_82543: 5661 if (hw->phy_id == M88E1000_E_PHY_ID) 5662 match = TRUE; 5663 break; 5664 case em_82544: 5665 if (hw->phy_id == M88E1000_I_PHY_ID) 5666 match = TRUE; 5667 break; 5668 case em_82540: 5669 case em_82545: 5670 case em_82545_rev_3: 5671 case em_82546: 5672 case em_82546_rev_3: 5673 if (hw->phy_id == M88E1011_I_PHY_ID) 5674 match = TRUE; 5675 break; 5676 case em_82541: 5677 case em_82541_rev_2: 5678 case em_82547: 5679 case em_82547_rev_2: 5680 if (hw->phy_id == IGP01E1000_I_PHY_ID) 5681 match = TRUE; 5682 break; 5683 case em_82573: 5684 if (hw->phy_id == M88E1111_I_PHY_ID) 5685 match = TRUE; 5686 break; 5687 case em_82574: 5688 if (hw->phy_id == BME1000_E_PHY_ID) 5689 match = TRUE; 5690 break; 5691 case em_82575: 5692 case em_82576: 5693 if (hw->phy_id == M88E1000_E_PHY_ID) 5694 match = TRUE; 5695 if (hw->phy_id == IGP01E1000_I_PHY_ID) 5696 match = TRUE; 5697 if (hw->phy_id == IGP03E1000_E_PHY_ID) 5698 match = TRUE; 5699 break; 5700 case em_82580: 5701 case em_i210: 5702 case em_i350: 5703 if (hw->phy_id == I82580_I_PHY_ID || 5704 hw->phy_id == I210_I_PHY_ID || 5705 hw->phy_id == I347AT4_E_PHY_ID || 5706 hw->phy_id == I350_I_PHY_ID || 5707 hw->phy_id == M88E1112_E_PHY_ID || 5708 hw->phy_id == M88E1543_E_PHY_ID || 5709 hw->phy_id == M88E1512_E_PHY_ID) { 5710 uint32_t mdic; 5711 5712 mdic = EM_READ_REG(hw, E1000_MDICNFG); 5713 mdic &= E1000_MDICNFG_PHY_MASK; 5714 hw->phy_addr = mdic >> E1000_MDICNFG_PHY_SHIFT; 5715 DEBUGOUT1("MDICNFG PHY ADDR %d", 5716 mdic >> E1000_MDICNFG_PHY_SHIFT); 5717 match = TRUE; 5718 } 5719 break; 5720 case em_80003es2lan: 5721 if (hw->phy_id == GG82563_E_PHY_ID) 5722 match = TRUE; 5723 break; 5724 case em_ich8lan: 5725 case em_ich9lan: 5726 case em_ich10lan: 5727 case em_pchlan: 5728 case em_pch2lan: 5729 if (hw->phy_id == IGP03E1000_E_PHY_ID) 5730 match = TRUE; 5731 if (hw->phy_id == IFE_E_PHY_ID) 5732 match = TRUE; 5733 if (hw->phy_id == IFE_PLUS_E_PHY_ID) 5734 match = TRUE; 5735 if (hw->phy_id == IFE_C_E_PHY_ID) 5736 match = TRUE; 5737 if (hw->phy_id == BME1000_E_PHY_ID) 5738 match = TRUE; 5739 if (hw->phy_id == I82577_E_PHY_ID) 5740 match = TRUE; 5741 if (hw->phy_id == I82578_E_PHY_ID) 5742 match = TRUE; 5743 if (hw->phy_id == I82579_E_PHY_ID) 5744 match = TRUE; 5745 break; 5746 case em_pch_lpt: 5747 case em_pch_spt: 5748 case em_pch_cnp: 5749 if (hw->phy_id == I217_E_PHY_ID) 5750 match = TRUE; 5751 break; 5752 case em_icp_xxxx: 5753 if (hw->phy_id == M88E1141_E_PHY_ID) 5754 match = TRUE; 5755 if (hw->phy_id == RTL8211_E_PHY_ID) 5756 match = TRUE; 5757 break; 5758 default: 5759 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type); 5760 return -E1000_ERR_CONFIG; 5761 } 5762 phy_init_status = em_set_phy_type(hw); 5763 5764 if ((match) && (phy_init_status == E1000_SUCCESS)) { 5765 DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id); 5766 return E1000_SUCCESS; 5767 } 5768 DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id); 5769 return -E1000_ERR_PHY; 5770 } 5771 5772 /****************************************************************************** 5773 * Probes the expected PHY address for known PHY IDs 5774 * 5775 * hw - Struct containing variables accessed by shared code 5776 *****************************************************************************/ 5777 STATIC int32_t 5778 em_detect_gig_phy(struct em_hw *hw) 5779 { 5780 int32_t ret_val, i; 5781 DEBUGFUNC("em_detect_gig_phy"); 5782 5783 if (hw->phy_id != 0) 5784 return E1000_SUCCESS; 5785 5786 /* default phy address, most phys reside here, but not all (ICH10) */ 5787 if (hw->mac_type != em_icp_xxxx) 5788 hw->phy_addr = 1; 5789 else 5790 hw->phy_addr = 0; /* There is a phy at phy_addr 0 on EP80579 */ 5791 5792 /* 5793 * The 82571 firmware may still be configuring the PHY. In this 5794 * case, we cannot access the PHY until the configuration is done. 5795 * So we explicitly set the PHY values. 5796 */ 5797 if (hw->mac_type == em_82571 || 5798 hw->mac_type == em_82572) { 5799 hw->phy_id = IGP01E1000_I_PHY_ID; 5800 hw->phy_type = em_phy_igp_2; 5801 return E1000_SUCCESS; 5802 } 5803 5804 /* 5805 * Some of the fiber cards dont have a phy, so we must exit cleanly 5806 * here 5807 */ 5808 if ((hw->media_type == em_media_type_fiber) && 5809 (hw->mac_type == em_82542_rev2_0 || 5810 hw->mac_type == em_82542_rev2_1 || 5811 hw->mac_type == em_82543 || 5812 hw->mac_type == em_82573 || 5813 hw->mac_type == em_82574 || 5814 hw->mac_type == em_80003es2lan)) { 5815 hw->phy_type = em_phy_undefined; 5816 return E1000_SUCCESS; 5817 } 5818 5819 if ((hw->media_type == em_media_type_internal_serdes || 5820 hw->media_type == em_media_type_fiber) && 5821 hw->mac_type >= em_82575) { 5822 hw->phy_type = em_phy_undefined; 5823 return E1000_SUCCESS; 5824 } 5825 5826 /* 5827 * Up to 82543 (incl), we need reset the phy, or it might not get 5828 * detected 5829 */ 5830 if (hw->mac_type <= em_82543) { 5831 ret_val = em_phy_hw_reset(hw); 5832 if (ret_val) 5833 return ret_val; 5834 } 5835 /* 5836 * ESB-2 PHY reads require em_phy_gg82563 to be set because of a 5837 * work- around that forces PHY page 0 to be set or the reads fail. 5838 * The rest of the code in this routine uses em_read_phy_reg to read 5839 * the PHY ID. So for ESB-2 we need to have this set so our reads 5840 * won't fail. If the attached PHY is not a em_phy_gg82563, the 5841 * routines below will figure this out as well. 5842 */ 5843 if (hw->mac_type == em_80003es2lan) 5844 hw->phy_type = em_phy_gg82563; 5845 5846 /* Power on SGMII phy if it is disabled */ 5847 if (hw->mac_type == em_82580 || hw->mac_type == em_i210 || 5848 hw->mac_type == em_i350) { 5849 uint32_t ctrl_ext = EM_READ_REG(hw, E1000_CTRL_EXT); 5850 EM_WRITE_REG(hw, E1000_CTRL_EXT, 5851 ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA); 5852 delay(300); 5853 } 5854 5855 /* Read the PHY ID Registers to identify which PHY is onboard. */ 5856 for (i = 1; i < 4; i++) { 5857 /* 5858 * hw->phy_addr may be modified down in the call stack, 5859 * we can't use it as loop variable. 5860 */ 5861 hw->phy_addr = i; 5862 ret_val = em_match_gig_phy(hw); 5863 if (ret_val == E1000_SUCCESS) 5864 return E1000_SUCCESS; 5865 } 5866 return -E1000_ERR_PHY; 5867 } 5868 5869 /****************************************************************************** 5870 * Resets the PHY's DSP 5871 * 5872 * hw - Struct containing variables accessed by shared code 5873 *****************************************************************************/ 5874 static int32_t 5875 em_phy_reset_dsp(struct em_hw *hw) 5876 { 5877 int32_t ret_val; 5878 DEBUGFUNC("em_phy_reset_dsp"); 5879 5880 do { 5881 if (hw->phy_type != em_phy_gg82563) { 5882 ret_val = em_write_phy_reg(hw, 29, 0x001d); 5883 if (ret_val) 5884 break; 5885 } 5886 ret_val = em_write_phy_reg(hw, 30, 0x00c1); 5887 if (ret_val) 5888 break; 5889 ret_val = em_write_phy_reg(hw, 30, 0x0000); 5890 if (ret_val) 5891 break; 5892 ret_val = E1000_SUCCESS; 5893 } while (0); 5894 5895 return ret_val; 5896 } 5897 5898 /****************************************************************************** 5899 * Sets up eeprom variables in the hw struct. Must be called after mac_type 5900 * is configured. Additionally, if this is ICH8, the flash controller GbE 5901 * registers must be mapped, or this will crash. 5902 * 5903 * hw - Struct containing variables accessed by shared code 5904 *****************************************************************************/ 5905 int32_t 5906 em_init_eeprom_params(struct em_hw *hw) 5907 { 5908 struct em_eeprom_info *eeprom = &hw->eeprom; 5909 uint32_t eecd = E1000_READ_REG(hw, EECD); 5910 int32_t ret_val = E1000_SUCCESS; 5911 uint16_t eeprom_size; 5912 DEBUGFUNC("em_init_eeprom_params"); 5913 5914 switch (hw->mac_type) { 5915 case em_82542_rev2_0: 5916 case em_82542_rev2_1: 5917 case em_82543: 5918 case em_82544: 5919 eeprom->type = em_eeprom_microwire; 5920 eeprom->word_size = 64; 5921 eeprom->opcode_bits = 3; 5922 eeprom->address_bits = 6; 5923 eeprom->delay_usec = 50; 5924 eeprom->use_eerd = FALSE; 5925 eeprom->use_eewr = FALSE; 5926 break; 5927 case em_82540: 5928 case em_82545: 5929 case em_82545_rev_3: 5930 case em_icp_xxxx: 5931 case em_82546: 5932 case em_82546_rev_3: 5933 eeprom->type = em_eeprom_microwire; 5934 eeprom->opcode_bits = 3; 5935 eeprom->delay_usec = 50; 5936 if (eecd & E1000_EECD_SIZE) { 5937 eeprom->word_size = 256; 5938 eeprom->address_bits = 8; 5939 } else { 5940 eeprom->word_size = 64; 5941 eeprom->address_bits = 6; 5942 } 5943 eeprom->use_eerd = FALSE; 5944 eeprom->use_eewr = FALSE; 5945 break; 5946 case em_82541: 5947 case em_82541_rev_2: 5948 case em_82547: 5949 case em_82547_rev_2: 5950 if (eecd & E1000_EECD_TYPE) { 5951 eeprom->type = em_eeprom_spi; 5952 eeprom->opcode_bits = 8; 5953 eeprom->delay_usec = 1; 5954 if (eecd & E1000_EECD_ADDR_BITS) { 5955 eeprom->page_size = 32; 5956 eeprom->address_bits = 16; 5957 } else { 5958 eeprom->page_size = 8; 5959 eeprom->address_bits = 8; 5960 } 5961 } else { 5962 eeprom->type = em_eeprom_microwire; 5963 eeprom->opcode_bits = 3; 5964 eeprom->delay_usec = 50; 5965 if (eecd & E1000_EECD_ADDR_BITS) { 5966 eeprom->word_size = 256; 5967 eeprom->address_bits = 8; 5968 } else { 5969 eeprom->word_size = 64; 5970 eeprom->address_bits = 6; 5971 } 5972 } 5973 eeprom->use_eerd = FALSE; 5974 eeprom->use_eewr = FALSE; 5975 break; 5976 case em_82571: 5977 case em_82572: 5978 eeprom->type = em_eeprom_spi; 5979 eeprom->opcode_bits = 8; 5980 eeprom->delay_usec = 1; 5981 if (eecd & E1000_EECD_ADDR_BITS) { 5982 eeprom->page_size = 32; 5983 eeprom->address_bits = 16; 5984 } else { 5985 eeprom->page_size = 8; 5986 eeprom->address_bits = 8; 5987 } 5988 eeprom->use_eerd = FALSE; 5989 eeprom->use_eewr = FALSE; 5990 break; 5991 case em_82573: 5992 case em_82574: 5993 case em_82575: 5994 case em_82576: 5995 case em_82580: 5996 case em_i210: 5997 case em_i350: 5998 eeprom->type = em_eeprom_spi; 5999 eeprom->opcode_bits = 8; 6000 eeprom->delay_usec = 1; 6001 if (eecd & E1000_EECD_ADDR_BITS) { 6002 eeprom->page_size = 32; 6003 eeprom->address_bits = 16; 6004 } else { 6005 eeprom->page_size = 8; 6006 eeprom->address_bits = 8; 6007 } 6008 eeprom->use_eerd = TRUE; 6009 eeprom->use_eewr = TRUE; 6010 if (em_is_onboard_nvm_eeprom(hw) == FALSE) { 6011 eeprom->type = em_eeprom_flash; 6012 eeprom->word_size = 2048; 6013 /* 6014 * Ensure that the Autonomous FLASH update bit is 6015 * cleared due to Flash update issue on parts which 6016 * use a FLASH for NVM. 6017 */ 6018 eecd &= ~E1000_EECD_AUPDEN; 6019 E1000_WRITE_REG(hw, EECD, eecd); 6020 } 6021 if (em_get_flash_presence_i210(hw) == FALSE) { 6022 eeprom->type = em_eeprom_invm; 6023 eeprom->word_size = INVM_SIZE; 6024 eeprom->use_eerd = FALSE; 6025 eeprom->use_eewr = FALSE; 6026 } 6027 break; 6028 case em_80003es2lan: 6029 eeprom->type = em_eeprom_spi; 6030 eeprom->opcode_bits = 8; 6031 eeprom->delay_usec = 1; 6032 if (eecd & E1000_EECD_ADDR_BITS) { 6033 eeprom->page_size = 32; 6034 eeprom->address_bits = 16; 6035 } else { 6036 eeprom->page_size = 8; 6037 eeprom->address_bits = 8; 6038 } 6039 eeprom->use_eerd = TRUE; 6040 eeprom->use_eewr = FALSE; 6041 break; 6042 case em_ich8lan: 6043 case em_ich9lan: 6044 case em_ich10lan: 6045 case em_pchlan: 6046 case em_pch2lan: 6047 case em_pch_lpt: 6048 { 6049 int32_t i = 0; 6050 uint32_t flash_size = 6051 E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_GFPREG); 6052 eeprom->type = em_eeprom_ich8; 6053 eeprom->use_eerd = FALSE; 6054 eeprom->use_eewr = FALSE; 6055 eeprom->word_size = E1000_SHADOW_RAM_WORDS; 6056 /* 6057 * Zero the shadow RAM structure. But don't load it 6058 * from NVM so as to save time for driver init 6059 */ 6060 if (hw->eeprom_shadow_ram != NULL) { 6061 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 6062 hw->eeprom_shadow_ram[i].modified = 6063 FALSE; 6064 hw->eeprom_shadow_ram[i].eeprom_word = 6065 0xFFFF; 6066 } 6067 } 6068 hw->flash_base_addr = (flash_size & 6069 ICH_GFPREG_BASE_MASK) * ICH_FLASH_SECTOR_SIZE; 6070 6071 hw->flash_bank_size = ((flash_size >> 16) & 6072 ICH_GFPREG_BASE_MASK) + 1; 6073 hw->flash_bank_size -= (flash_size & 6074 ICH_GFPREG_BASE_MASK); 6075 6076 hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE; 6077 6078 hw->flash_bank_size /= 2 * sizeof(uint16_t); 6079 6080 break; 6081 } 6082 case em_pch_spt: 6083 case em_pch_cnp: 6084 { 6085 int32_t i = 0; 6086 uint32_t flash_size = EM_READ_REG(hw, 0xc /* STRAP */); 6087 6088 eeprom->type = em_eeprom_ich8; 6089 eeprom->use_eerd = FALSE; 6090 eeprom->use_eewr = FALSE; 6091 eeprom->word_size = E1000_SHADOW_RAM_WORDS; 6092 /* 6093 * Zero the shadow RAM structure. But don't load it 6094 * from NVM so as to save time for driver init 6095 */ 6096 if (hw->eeprom_shadow_ram != NULL) { 6097 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 6098 hw->eeprom_shadow_ram[i].modified = 6099 FALSE; 6100 hw->eeprom_shadow_ram[i].eeprom_word = 6101 0xFFFF; 6102 } 6103 } 6104 hw->flash_base_addr = 0; 6105 flash_size = ((flash_size >> 1) & 0x1f) + 1; 6106 flash_size *= 4096; 6107 hw->flash_bank_size = flash_size / 4; 6108 } 6109 break; 6110 default: 6111 break; 6112 } 6113 6114 if (eeprom->type == em_eeprom_spi) { 6115 /* 6116 * eeprom_size will be an enum [0..8] that maps to eeprom 6117 * sizes 128B to 32KB (incremented by powers of 2). 6118 */ 6119 if (hw->mac_type <= em_82547_rev_2) { 6120 /* Set to default value for initial eeprom read. */ 6121 eeprom->word_size = 64; 6122 ret_val = em_read_eeprom(hw, EEPROM_CFG, 1, 6123 &eeprom_size); 6124 if (ret_val) 6125 return ret_val; 6126 eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> 6127 EEPROM_SIZE_SHIFT; 6128 /* 6129 * 256B eeprom size was not supported in earlier 6130 * hardware, so we bump eeprom_size up one to ensure 6131 * that "1" (which maps to 256B) is never the result 6132 * used in the shifting logic below. 6133 */ 6134 if (eeprom_size) 6135 eeprom_size++; 6136 } else { 6137 eeprom_size = (uint16_t) ( 6138 (eecd & E1000_EECD_SIZE_EX_MASK) >> 6139 E1000_EECD_SIZE_EX_SHIFT); 6140 } 6141 6142 /* EEPROM access above 16k is unsupported */ 6143 if (eeprom_size + EEPROM_WORD_SIZE_SHIFT > 6144 EEPROM_WORD_SIZE_SHIFT_MAX) { 6145 eeprom->word_size = 1 << EEPROM_WORD_SIZE_SHIFT_MAX; 6146 } else { 6147 eeprom->word_size = 1 << 6148 (eeprom_size + EEPROM_WORD_SIZE_SHIFT); 6149 } 6150 } 6151 return ret_val; 6152 } 6153 6154 /****************************************************************************** 6155 * Raises the EEPROM's clock input. 6156 * 6157 * hw - Struct containing variables accessed by shared code 6158 * eecd - EECD's current value 6159 *****************************************************************************/ 6160 static void 6161 em_raise_ee_clk(struct em_hw *hw, uint32_t *eecd) 6162 { 6163 /* 6164 * Raise the clock input to the EEPROM (by setting the SK bit), and 6165 * then wait <delay> microseconds. 6166 */ 6167 *eecd = *eecd | E1000_EECD_SK; 6168 E1000_WRITE_REG(hw, EECD, *eecd); 6169 E1000_WRITE_FLUSH(hw); 6170 usec_delay(hw->eeprom.delay_usec); 6171 } 6172 6173 /****************************************************************************** 6174 * Lowers the EEPROM's clock input. 6175 * 6176 * hw - Struct containing variables accessed by shared code 6177 * eecd - EECD's current value 6178 *****************************************************************************/ 6179 static void 6180 em_lower_ee_clk(struct em_hw *hw, uint32_t *eecd) 6181 { 6182 /* 6183 * Lower the clock input to the EEPROM (by clearing the SK bit), and 6184 * then wait 50 microseconds. 6185 */ 6186 *eecd = *eecd & ~E1000_EECD_SK; 6187 E1000_WRITE_REG(hw, EECD, *eecd); 6188 E1000_WRITE_FLUSH(hw); 6189 usec_delay(hw->eeprom.delay_usec); 6190 } 6191 6192 /****************************************************************************** 6193 * Shift data bits out to the EEPROM. 6194 * 6195 * hw - Struct containing variables accessed by shared code 6196 * data - data to send to the EEPROM 6197 * count - number of bits to shift out 6198 *****************************************************************************/ 6199 static void 6200 em_shift_out_ee_bits(struct em_hw *hw, uint16_t data, uint16_t count) 6201 { 6202 struct em_eeprom_info *eeprom = &hw->eeprom; 6203 uint32_t eecd; 6204 uint32_t mask; 6205 /* 6206 * We need to shift "count" bits out to the EEPROM. So, value in the 6207 * "data" parameter will be shifted out to the EEPROM one bit at a 6208 * time. In order to do this, "data" must be broken down into bits. 6209 */ 6210 mask = 0x01 << (count - 1); 6211 eecd = E1000_READ_REG(hw, EECD); 6212 if (eeprom->type == em_eeprom_microwire) { 6213 eecd &= ~E1000_EECD_DO; 6214 } else if (eeprom->type == em_eeprom_spi) { 6215 eecd |= E1000_EECD_DO; 6216 } 6217 do { 6218 /* 6219 * A "1" is shifted out to the EEPROM by setting bit "DI" to 6220 * a "1", and then raising and then lowering the clock (the 6221 * SK bit controls the clock input to the EEPROM). A "0" is 6222 * shifted out to the EEPROM by setting "DI" to "0" and then 6223 * raising and then lowering the clock. 6224 */ 6225 eecd &= ~E1000_EECD_DI; 6226 6227 if (data & mask) 6228 eecd |= E1000_EECD_DI; 6229 6230 E1000_WRITE_REG(hw, EECD, eecd); 6231 E1000_WRITE_FLUSH(hw); 6232 6233 usec_delay(eeprom->delay_usec); 6234 6235 em_raise_ee_clk(hw, &eecd); 6236 em_lower_ee_clk(hw, &eecd); 6237 6238 mask = mask >> 1; 6239 6240 } while (mask); 6241 6242 /* We leave the "DI" bit set to "0" when we leave this routine. */ 6243 eecd &= ~E1000_EECD_DI; 6244 E1000_WRITE_REG(hw, EECD, eecd); 6245 } 6246 6247 /****************************************************************************** 6248 * Shift data bits in from the EEPROM 6249 * 6250 * hw - Struct containing variables accessed by shared code 6251 *****************************************************************************/ 6252 static uint16_t 6253 em_shift_in_ee_bits(struct em_hw *hw, uint16_t count) 6254 { 6255 uint32_t eecd; 6256 uint32_t i; 6257 uint16_t data; 6258 /* 6259 * In order to read a register from the EEPROM, we need to shift 6260 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising 6261 * the clock input to the EEPROM (setting the SK bit), and then 6262 * reading the value of the "DO" bit. During this "shifting in" 6263 * process the "DI" bit should always be clear. 6264 */ 6265 6266 eecd = E1000_READ_REG(hw, EECD); 6267 6268 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 6269 data = 0; 6270 6271 for (i = 0; i < count; i++) { 6272 data = data << 1; 6273 em_raise_ee_clk(hw, &eecd); 6274 6275 eecd = E1000_READ_REG(hw, EECD); 6276 6277 eecd &= ~(E1000_EECD_DI); 6278 if (eecd & E1000_EECD_DO) 6279 data |= 1; 6280 6281 em_lower_ee_clk(hw, &eecd); 6282 } 6283 6284 return data; 6285 } 6286 /****************************************************************************** 6287 * Prepares EEPROM for access 6288 * 6289 * hw - Struct containing variables accessed by shared code 6290 * 6291 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This 6292 * function should be called before issuing a command to the EEPROM. 6293 *****************************************************************************/ 6294 static int32_t 6295 em_acquire_eeprom(struct em_hw *hw) 6296 { 6297 struct em_eeprom_info *eeprom = &hw->eeprom; 6298 uint32_t eecd, i = 0; 6299 DEBUGFUNC("em_acquire_eeprom"); 6300 6301 if (em_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM)) 6302 return -E1000_ERR_SWFW_SYNC; 6303 eecd = E1000_READ_REG(hw, EECD); 6304 6305 if ((hw->mac_type != em_82573) && (hw->mac_type != em_82574)) { 6306 /* Request EEPROM Access */ 6307 if (hw->mac_type > em_82544) { 6308 eecd |= E1000_EECD_REQ; 6309 E1000_WRITE_REG(hw, EECD, eecd); 6310 eecd = E1000_READ_REG(hw, EECD); 6311 while ((!(eecd & E1000_EECD_GNT)) && 6312 (i < E1000_EEPROM_GRANT_ATTEMPTS)) { 6313 i++; 6314 usec_delay(5); 6315 eecd = E1000_READ_REG(hw, EECD); 6316 } 6317 if (!(eecd & E1000_EECD_GNT)) { 6318 eecd &= ~E1000_EECD_REQ; 6319 E1000_WRITE_REG(hw, EECD, eecd); 6320 DEBUGOUT("Could not acquire EEPROM grant\n"); 6321 em_swfw_sync_release(hw, E1000_SWFW_EEP_SM); 6322 return -E1000_ERR_EEPROM; 6323 } 6324 } 6325 } 6326 6327 /* Setup EEPROM for Read/Write */ 6328 if (eeprom->type == em_eeprom_microwire) { 6329 /* Clear SK and DI */ 6330 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK); 6331 E1000_WRITE_REG(hw, EECD, eecd); 6332 6333 /* Set CS */ 6334 eecd |= E1000_EECD_CS; 6335 E1000_WRITE_REG(hw, EECD, eecd); 6336 } else if (eeprom->type == em_eeprom_spi) { 6337 /* Clear SK and CS */ 6338 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 6339 E1000_WRITE_REG(hw, EECD, eecd); 6340 usec_delay(1); 6341 } 6342 return E1000_SUCCESS; 6343 } 6344 6345 /****************************************************************************** 6346 * Returns EEPROM to a "standby" state 6347 * 6348 * hw - Struct containing variables accessed by shared code 6349 *****************************************************************************/ 6350 static void 6351 em_standby_eeprom(struct em_hw *hw) 6352 { 6353 struct em_eeprom_info *eeprom = &hw->eeprom; 6354 uint32_t eecd; 6355 eecd = E1000_READ_REG(hw, EECD); 6356 6357 if (eeprom->type == em_eeprom_microwire) { 6358 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 6359 E1000_WRITE_REG(hw, EECD, eecd); 6360 E1000_WRITE_FLUSH(hw); 6361 usec_delay(eeprom->delay_usec); 6362 6363 /* Clock high */ 6364 eecd |= E1000_EECD_SK; 6365 E1000_WRITE_REG(hw, EECD, eecd); 6366 E1000_WRITE_FLUSH(hw); 6367 usec_delay(eeprom->delay_usec); 6368 6369 /* Select EEPROM */ 6370 eecd |= E1000_EECD_CS; 6371 E1000_WRITE_REG(hw, EECD, eecd); 6372 E1000_WRITE_FLUSH(hw); 6373 usec_delay(eeprom->delay_usec); 6374 6375 /* Clock low */ 6376 eecd &= ~E1000_EECD_SK; 6377 E1000_WRITE_REG(hw, EECD, eecd); 6378 E1000_WRITE_FLUSH(hw); 6379 usec_delay(eeprom->delay_usec); 6380 } else if (eeprom->type == em_eeprom_spi) { 6381 /* Toggle CS to flush commands */ 6382 eecd |= E1000_EECD_CS; 6383 E1000_WRITE_REG(hw, EECD, eecd); 6384 E1000_WRITE_FLUSH(hw); 6385 usec_delay(eeprom->delay_usec); 6386 eecd &= ~E1000_EECD_CS; 6387 E1000_WRITE_REG(hw, EECD, eecd); 6388 E1000_WRITE_FLUSH(hw); 6389 usec_delay(eeprom->delay_usec); 6390 } 6391 } 6392 6393 /****************************************************************************** 6394 * Terminates a command by inverting the EEPROM's chip select pin 6395 * 6396 * hw - Struct containing variables accessed by shared code 6397 *****************************************************************************/ 6398 static void 6399 em_release_eeprom(struct em_hw *hw) 6400 { 6401 uint32_t eecd; 6402 DEBUGFUNC("em_release_eeprom"); 6403 6404 eecd = E1000_READ_REG(hw, EECD); 6405 6406 if (hw->eeprom.type == em_eeprom_spi) { 6407 eecd |= E1000_EECD_CS; /* Pull CS high */ 6408 eecd &= ~E1000_EECD_SK; /* Lower SCK */ 6409 6410 E1000_WRITE_REG(hw, EECD, eecd); 6411 6412 usec_delay(hw->eeprom.delay_usec); 6413 } else if (hw->eeprom.type == em_eeprom_microwire) { 6414 /* cleanup eeprom */ 6415 6416 /* CS on Microwire is active-high */ 6417 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); 6418 6419 E1000_WRITE_REG(hw, EECD, eecd); 6420 6421 /* Rising edge of clock */ 6422 eecd |= E1000_EECD_SK; 6423 E1000_WRITE_REG(hw, EECD, eecd); 6424 E1000_WRITE_FLUSH(hw); 6425 usec_delay(hw->eeprom.delay_usec); 6426 6427 /* Falling edge of clock */ 6428 eecd &= ~E1000_EECD_SK; 6429 E1000_WRITE_REG(hw, EECD, eecd); 6430 E1000_WRITE_FLUSH(hw); 6431 usec_delay(hw->eeprom.delay_usec); 6432 } 6433 /* Stop requesting EEPROM access */ 6434 if (hw->mac_type > em_82544) { 6435 eecd &= ~E1000_EECD_REQ; 6436 E1000_WRITE_REG(hw, EECD, eecd); 6437 } 6438 em_swfw_sync_release(hw, E1000_SWFW_EEP_SM); 6439 } 6440 6441 /****************************************************************************** 6442 * Reads a 16 bit word from the EEPROM. 6443 * 6444 * hw - Struct containing variables accessed by shared code 6445 *****************************************************************************/ 6446 STATIC int32_t 6447 em_spi_eeprom_ready(struct em_hw *hw) 6448 { 6449 uint16_t retry_count = 0; 6450 uint8_t spi_stat_reg; 6451 DEBUGFUNC("em_spi_eeprom_ready"); 6452 /* 6453 * Read "Status Register" repeatedly until the LSB is cleared. The 6454 * EEPROM will signal that the command has been completed by clearing 6455 * bit 0 of the internal status register. If it's not cleared within 6456 * 5 milliseconds, then error out. 6457 */ 6458 retry_count = 0; 6459 do { 6460 em_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI, 6461 hw->eeprom.opcode_bits); 6462 spi_stat_reg = (uint8_t) em_shift_in_ee_bits(hw, 8); 6463 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI)) 6464 break; 6465 6466 usec_delay(5); 6467 retry_count += 5; 6468 6469 em_standby_eeprom(hw); 6470 } while (retry_count < EEPROM_MAX_RETRY_SPI); 6471 /* 6472 * ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and 6473 * only 0-5mSec on 5V devices) 6474 */ 6475 if (retry_count >= EEPROM_MAX_RETRY_SPI) { 6476 DEBUGOUT("SPI EEPROM Status error\n"); 6477 return -E1000_ERR_EEPROM; 6478 } 6479 return E1000_SUCCESS; 6480 } 6481 6482 /****************************************************************************** 6483 * Reads a 16 bit word from the EEPROM. 6484 * 6485 * hw - Struct containing variables accessed by shared code 6486 * offset - offset of word in the EEPROM to read 6487 * data - word read from the EEPROM 6488 * words - number of words to read 6489 *****************************************************************************/ 6490 int32_t 6491 em_read_eeprom(struct em_hw *hw, uint16_t offset, uint16_t words, 6492 uint16_t *data) 6493 { 6494 struct em_eeprom_info *eeprom = &hw->eeprom; 6495 uint32_t i = 0; 6496 DEBUGFUNC("em_read_eeprom"); 6497 6498 /* If eeprom is not yet detected, do so now */ 6499 if (eeprom->word_size == 0) 6500 em_init_eeprom_params(hw); 6501 /* 6502 * A check for invalid values: offset too large, too many words, and 6503 * not enough words. 6504 */ 6505 if ((offset >= eeprom->word_size) || 6506 (words > eeprom->word_size - offset) || 6507 (words == 0)) { 6508 DEBUGOUT2("\"words\" parameter out of bounds. Words = %d," 6509 " size = %d\n", offset, eeprom->word_size); 6510 return -E1000_ERR_EEPROM; 6511 } 6512 /* 6513 * EEPROM's that don't use EERD to read require us to bit-bang the 6514 * SPI directly. In this case, we need to acquire the EEPROM so that 6515 * FW or other port software does not interrupt. 6516 */ 6517 if (em_is_onboard_nvm_eeprom(hw) == TRUE && 6518 em_get_flash_presence_i210(hw) == TRUE && 6519 hw->eeprom.use_eerd == FALSE) { 6520 /* Prepare the EEPROM for bit-bang reading */ 6521 if (em_acquire_eeprom(hw) != E1000_SUCCESS) 6522 return -E1000_ERR_EEPROM; 6523 } 6524 /* Eerd register EEPROM access requires no eeprom aquire/release */ 6525 if (eeprom->use_eerd == TRUE) 6526 return em_read_eeprom_eerd(hw, offset, words, data); 6527 6528 /* ICH EEPROM access is done via the ICH flash controller */ 6529 if (eeprom->type == em_eeprom_ich8) 6530 return em_read_eeprom_ich8(hw, offset, words, data); 6531 6532 /* Some i210/i211 have a special OTP chip */ 6533 if (eeprom->type == em_eeprom_invm) 6534 return em_read_invm_i210(hw, offset, words, data); 6535 6536 /* 6537 * Set up the SPI or Microwire EEPROM for bit-bang reading. We have 6538 * acquired the EEPROM at this point, so any returns should relase it 6539 */ 6540 if (eeprom->type == em_eeprom_spi) { 6541 uint16_t word_in; 6542 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI; 6543 if (em_spi_eeprom_ready(hw)) { 6544 em_release_eeprom(hw); 6545 return -E1000_ERR_EEPROM; 6546 } 6547 em_standby_eeprom(hw); 6548 /* 6549 * Some SPI eeproms use the 8th address bit embedded in the 6550 * opcode 6551 */ 6552 if ((eeprom->address_bits == 8) && (offset >= 128)) 6553 read_opcode |= EEPROM_A8_OPCODE_SPI; 6554 6555 /* Send the READ command (opcode + addr) */ 6556 em_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits); 6557 em_shift_out_ee_bits(hw, (uint16_t) (offset * 2), 6558 eeprom->address_bits); 6559 /* 6560 * Read the data. The address of the eeprom internally 6561 * increments with each byte (spi) being read, saving on the 6562 * overhead of eeprom setup and tear-down. The address 6563 * counter will roll over if reading beyond the size of the 6564 * eeprom, thus allowing the entire memory to be read 6565 * starting from any offset. 6566 */ 6567 for (i = 0; i < words; i++) { 6568 word_in = em_shift_in_ee_bits(hw, 16); 6569 data[i] = (word_in >> 8) | (word_in << 8); 6570 } 6571 } else if (eeprom->type == em_eeprom_microwire) { 6572 for (i = 0; i < words; i++) { 6573 /* Send the READ command (opcode + addr) */ 6574 em_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE, 6575 eeprom->opcode_bits); 6576 em_shift_out_ee_bits(hw, (uint16_t) (offset + i), 6577 eeprom->address_bits); 6578 /* 6579 * Read the data. For microwire, each word requires 6580 * the overhead of eeprom setup and tear-down. 6581 */ 6582 data[i] = em_shift_in_ee_bits(hw, 16); 6583 em_standby_eeprom(hw); 6584 } 6585 } 6586 /* End this read operation */ 6587 em_release_eeprom(hw); 6588 6589 return E1000_SUCCESS; 6590 } 6591 6592 /****************************************************************************** 6593 * Reads a 16 bit word from the EEPROM using the EERD register. 6594 * 6595 * hw - Struct containing variables accessed by shared code 6596 * offset - offset of word in the EEPROM to read 6597 * data - word read from the EEPROM 6598 * words - number of words to read 6599 *****************************************************************************/ 6600 STATIC int32_t 6601 em_read_eeprom_eerd(struct em_hw *hw, uint16_t offset, uint16_t words, 6602 uint16_t *data) 6603 { 6604 uint32_t i, eerd = 0; 6605 int32_t error = 0; 6606 for (i = 0; i < words; i++) { 6607 eerd = ((offset + i) << E1000_EEPROM_RW_ADDR_SHIFT) + 6608 E1000_EEPROM_RW_REG_START; 6609 6610 E1000_WRITE_REG(hw, EERD, eerd); 6611 error = em_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ); 6612 6613 if (error) { 6614 break; 6615 } 6616 data[i] = (E1000_READ_REG(hw, EERD) >> 6617 E1000_EEPROM_RW_REG_DATA); 6618 6619 } 6620 6621 return error; 6622 } 6623 6624 /****************************************************************************** 6625 * Writes a 16 bit word from the EEPROM using the EEWR register. 6626 * 6627 * hw - Struct containing variables accessed by shared code 6628 * offset - offset of word in the EEPROM to read 6629 * data - word read from the EEPROM 6630 * words - number of words to read 6631 *****************************************************************************/ 6632 STATIC int32_t 6633 em_write_eeprom_eewr(struct em_hw *hw, uint16_t offset, uint16_t words, 6634 uint16_t *data) 6635 { 6636 uint32_t register_value = 0; 6637 uint32_t i = 0; 6638 int32_t error = 0; 6639 if (em_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM)) 6640 return -E1000_ERR_SWFW_SYNC; 6641 6642 for (i = 0; i < words; i++) { 6643 register_value = (data[i] << E1000_EEPROM_RW_REG_DATA) | 6644 ((offset + i) << E1000_EEPROM_RW_ADDR_SHIFT) | 6645 E1000_EEPROM_RW_REG_START; 6646 6647 error = em_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE); 6648 if (error) { 6649 break; 6650 } 6651 E1000_WRITE_REG(hw, EEWR, register_value); 6652 6653 error = em_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE); 6654 6655 if (error) { 6656 break; 6657 } 6658 } 6659 6660 em_swfw_sync_release(hw, E1000_SWFW_EEP_SM); 6661 return error; 6662 } 6663 6664 /****************************************************************************** 6665 * Polls the status bit (bit 1) of the EERD to determine when the read is done. 6666 * 6667 * hw - Struct containing variables accessed by shared code 6668 *****************************************************************************/ 6669 STATIC int32_t 6670 em_poll_eerd_eewr_done(struct em_hw *hw, int eerd) 6671 { 6672 uint32_t attempts = 100000; 6673 uint32_t i, reg = 0; 6674 int32_t done = E1000_ERR_EEPROM; 6675 for (i = 0; i < attempts; i++) { 6676 if (eerd == E1000_EEPROM_POLL_READ) 6677 reg = E1000_READ_REG(hw, EERD); 6678 else 6679 reg = E1000_READ_REG(hw, EEWR); 6680 6681 if (reg & E1000_EEPROM_RW_REG_DONE) { 6682 done = E1000_SUCCESS; 6683 break; 6684 } 6685 usec_delay(5); 6686 } 6687 6688 return done; 6689 } 6690 6691 /****************************************************************************** 6692 * Description: Determines if the onboard NVM is FLASH or EEPROM. 6693 * 6694 * hw - Struct containing variables accessed by shared code 6695 *****************************************************************************/ 6696 STATIC boolean_t 6697 em_is_onboard_nvm_eeprom(struct em_hw *hw) 6698 { 6699 uint32_t eecd = 0; 6700 DEBUGFUNC("em_is_onboard_nvm_eeprom"); 6701 6702 if (IS_ICH8(hw->mac_type)) 6703 return FALSE; 6704 6705 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) { 6706 eecd = E1000_READ_REG(hw, EECD); 6707 6708 /* Isolate bits 15 & 16 */ 6709 eecd = ((eecd >> 15) & 0x03); 6710 6711 /* If both bits are set, device is Flash type */ 6712 if (eecd == 0x03) { 6713 return FALSE; 6714 } 6715 } 6716 return TRUE; 6717 } 6718 6719 /****************************************************************************** 6720 * Check if flash device is detected. 6721 * 6722 * hw - Struct containing variables accessed by shared code 6723 *****************************************************************************/ 6724 boolean_t 6725 em_get_flash_presence_i210(struct em_hw *hw) 6726 { 6727 uint32_t eecd; 6728 DEBUGFUNC("em_get_flash_presence_i210"); 6729 6730 if (hw->mac_type != em_i210) 6731 return TRUE; 6732 6733 eecd = E1000_READ_REG(hw, EECD); 6734 6735 if (eecd & E1000_EECD_FLUPD) 6736 return TRUE; 6737 6738 return FALSE; 6739 } 6740 6741 /****************************************************************************** 6742 * Verifies that the EEPROM has a valid checksum 6743 * 6744 * hw - Struct containing variables accessed by shared code 6745 * 6746 * Reads the first 64 16 bit words of the EEPROM and sums the values read. 6747 * If the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is 6748 * valid. 6749 *****************************************************************************/ 6750 int32_t 6751 em_validate_eeprom_checksum(struct em_hw *hw) 6752 { 6753 uint16_t checksum = 0; 6754 uint16_t i, eeprom_data; 6755 uint16_t checksum_reg; 6756 DEBUGFUNC("em_validate_eeprom_checksum"); 6757 6758 checksum_reg = hw->mac_type != em_icp_xxxx ? 6759 EEPROM_CHECKSUM_REG : 6760 EEPROM_CHECKSUM_REG_ICP_xxxx; 6761 6762 if (((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) && 6763 (em_is_onboard_nvm_eeprom(hw) == FALSE)) { 6764 /* 6765 * Check bit 4 of word 10h. If it is 0, firmware is done 6766 * updating 10h-12h. Checksum may need to be fixed. 6767 */ 6768 em_read_eeprom(hw, 0x10, 1, &eeprom_data); 6769 if ((eeprom_data & 0x10) == 0) { 6770 /* 6771 * Read 0x23 and check bit 15. This bit is a 1 when 6772 * the checksum has already been fixed. If the 6773 * checksum is still wrong and this bit is a 1, we 6774 * need to return bad checksum. Otherwise, we need 6775 * to set this bit to a 1 and update the checksum. 6776 */ 6777 em_read_eeprom(hw, 0x23, 1, &eeprom_data); 6778 if ((eeprom_data & 0x8000) == 0) { 6779 eeprom_data |= 0x8000; 6780 em_write_eeprom(hw, 0x23, 1, &eeprom_data); 6781 em_update_eeprom_checksum(hw); 6782 } 6783 } 6784 } 6785 if (IS_ICH8(hw->mac_type)) { 6786 uint16_t word; 6787 uint16_t valid_csum_mask; 6788 6789 /* 6790 * Drivers must allocate the shadow ram structure for the 6791 * EEPROM checksum to be updated. Otherwise, this bit as 6792 * well as the checksum must both be set correctly for this 6793 * validation to pass. 6794 */ 6795 switch (hw->mac_type) { 6796 case em_pch_lpt: 6797 case em_pch_spt: 6798 case em_pch_cnp: 6799 word = EEPROM_COMPAT; 6800 valid_csum_mask = EEPROM_COMPAT_VALID_CSUM; 6801 break; 6802 default: 6803 word = EEPROM_FUTURE_INIT_WORD1; 6804 valid_csum_mask = EEPROM_FUTURE_INIT_WORD1_VALID_CSUM; 6805 break; 6806 } 6807 em_read_eeprom(hw, word, 1, &eeprom_data); 6808 if ((eeprom_data & valid_csum_mask) == 0) { 6809 eeprom_data |= valid_csum_mask; 6810 em_write_eeprom(hw, word, 1, &eeprom_data); 6811 em_update_eeprom_checksum(hw); 6812 } 6813 } 6814 for (i = 0; i < (checksum_reg + 1); i++) { 6815 if (em_read_eeprom(hw, i, 1, &eeprom_data) < 0) { 6816 DEBUGOUT("EEPROM Read Error\n"); 6817 return -E1000_ERR_EEPROM; 6818 } 6819 checksum += eeprom_data; 6820 } 6821 6822 if (checksum == (uint16_t) EEPROM_SUM) 6823 return E1000_SUCCESS; 6824 else { 6825 DEBUGOUT("EEPROM Checksum Invalid\n"); 6826 return -E1000_ERR_EEPROM; 6827 } 6828 } 6829 6830 /****************************************************************************** 6831 * Calculates the EEPROM checksum and writes it to the EEPROM 6832 * 6833 * hw - Struct containing variables accessed by shared code 6834 * 6835 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA. 6836 * Writes the difference to word offset 63 of the EEPROM. 6837 *****************************************************************************/ 6838 int32_t 6839 em_update_eeprom_checksum(struct em_hw *hw) 6840 { 6841 uint32_t ctrl_ext; 6842 uint16_t checksum = 0; 6843 uint16_t i, eeprom_data; 6844 DEBUGFUNC("em_update_eeprom_checksum"); 6845 6846 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) { 6847 if (em_read_eeprom(hw, i, 1, &eeprom_data) < 0) { 6848 DEBUGOUT("EEPROM Read Error\n"); 6849 return -E1000_ERR_EEPROM; 6850 } 6851 checksum += eeprom_data; 6852 } 6853 checksum = (uint16_t) EEPROM_SUM - checksum; 6854 if (em_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) { 6855 DEBUGOUT("EEPROM Write Error\n"); 6856 return -E1000_ERR_EEPROM; 6857 } else if (hw->eeprom.type == em_eeprom_flash) { 6858 em_commit_shadow_ram(hw); 6859 } else if (hw->eeprom.type == em_eeprom_ich8) { 6860 em_commit_shadow_ram(hw); 6861 /* 6862 * Reload the EEPROM, or else modifications will not appear 6863 * until after next adapter reset. 6864 */ 6865 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 6866 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 6867 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 6868 msec_delay(10); 6869 } 6870 return E1000_SUCCESS; 6871 } 6872 6873 /****************************************************************************** 6874 * Parent function for writing words to the different EEPROM types. 6875 * 6876 * hw - Struct containing variables accessed by shared code 6877 * offset - offset within the EEPROM to be written to 6878 * words - number of words to write 6879 * data - 16 bit word to be written to the EEPROM 6880 * 6881 * If em_update_eeprom_checksum is not called after this function, the 6882 * EEPROM will most likely contain an invalid checksum. 6883 *****************************************************************************/ 6884 int32_t 6885 em_write_eeprom(struct em_hw *hw, uint16_t offset, uint16_t words, 6886 uint16_t *data) 6887 { 6888 struct em_eeprom_info *eeprom = &hw->eeprom; 6889 int32_t status = 0; 6890 DEBUGFUNC("em_write_eeprom"); 6891 6892 /* If eeprom is not yet detected, do so now */ 6893 if (eeprom->word_size == 0) 6894 em_init_eeprom_params(hw); 6895 /* 6896 * A check for invalid values: offset too large, too many words, and 6897 * not enough words. 6898 */ 6899 if ((offset >= eeprom->word_size) || 6900 (words > eeprom->word_size - offset) || 6901 (words == 0)) { 6902 DEBUGOUT("\"words\" parameter out of bounds\n"); 6903 return -E1000_ERR_EEPROM; 6904 } 6905 /* 82573/4 writes only through eewr */ 6906 if (eeprom->use_eewr == TRUE) 6907 return em_write_eeprom_eewr(hw, offset, words, data); 6908 6909 if (eeprom->type == em_eeprom_ich8) 6910 return em_write_eeprom_ich8(hw, offset, words, data); 6911 6912 /* Prepare the EEPROM for writing */ 6913 if (em_acquire_eeprom(hw) != E1000_SUCCESS) 6914 return -E1000_ERR_EEPROM; 6915 6916 if (eeprom->type == em_eeprom_microwire) { 6917 status = em_write_eeprom_microwire(hw, offset, words, data); 6918 } else { 6919 status = em_write_eeprom_spi(hw, offset, words, data); 6920 msec_delay(10); 6921 } 6922 6923 /* Done with writing */ 6924 em_release_eeprom(hw); 6925 6926 return status; 6927 } 6928 6929 /****************************************************************************** 6930 * Writes a 16 bit word to a given offset in an SPI EEPROM. 6931 * 6932 * hw - Struct containing variables accessed by shared code 6933 * offset - offset within the EEPROM to be written to 6934 * words - number of words to write 6935 * data - pointer to array of 8 bit words to be written to the EEPROM 6936 * 6937 *****************************************************************************/ 6938 STATIC int32_t 6939 em_write_eeprom_spi(struct em_hw *hw, uint16_t offset, uint16_t words, 6940 uint16_t *data) 6941 { 6942 struct em_eeprom_info *eeprom = &hw->eeprom; 6943 uint16_t widx = 0; 6944 DEBUGFUNC("em_write_eeprom_spi"); 6945 6946 while (widx < words) { 6947 uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI; 6948 if (em_spi_eeprom_ready(hw)) 6949 return -E1000_ERR_EEPROM; 6950 6951 em_standby_eeprom(hw); 6952 6953 /* Send the WRITE ENABLE command (8 bit opcode ) */ 6954 em_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI, 6955 eeprom->opcode_bits); 6956 6957 em_standby_eeprom(hw); 6958 /* 6959 * Some SPI eeproms use the 8th address bit embedded in the 6960 * opcode 6961 */ 6962 if ((eeprom->address_bits == 8) && (offset >= 128)) 6963 write_opcode |= EEPROM_A8_OPCODE_SPI; 6964 6965 /* Send the Write command (8-bit opcode + addr) */ 6966 em_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits); 6967 6968 em_shift_out_ee_bits(hw, (uint16_t) ((offset + widx) * 2), 6969 eeprom->address_bits); 6970 6971 /* Send the data */ 6972 /* 6973 * Loop to allow for up to whole page write (32 bytes) of 6974 * eeprom 6975 */ 6976 while (widx < words) { 6977 uint16_t word_out = data[widx]; 6978 word_out = (word_out >> 8) | (word_out << 8); 6979 em_shift_out_ee_bits(hw, word_out, 16); 6980 widx++; 6981 /* 6982 * Some larger eeprom sizes are capable of a 32-byte 6983 * PAGE WRITE operation, while the smaller eeproms 6984 * are capable of an 8-byte PAGE WRITE operation. 6985 * Break the inner loop to pass new address 6986 */ 6987 if ((((offset + widx) * 2) % eeprom->page_size) == 0) { 6988 em_standby_eeprom(hw); 6989 break; 6990 } 6991 } 6992 } 6993 6994 return E1000_SUCCESS; 6995 } 6996 6997 /****************************************************************************** 6998 * Writes a 16 bit word to a given offset in a Microwire EEPROM. 6999 * 7000 * hw - Struct containing variables accessed by shared code 7001 * offset - offset within the EEPROM to be written to 7002 * words - number of words to write 7003 * data - pointer to array of 16 bit words to be written to the EEPROM 7004 * 7005 *****************************************************************************/ 7006 STATIC int32_t 7007 em_write_eeprom_microwire(struct em_hw *hw, uint16_t offset, uint16_t words, 7008 uint16_t *data) 7009 { 7010 struct em_eeprom_info *eeprom = &hw->eeprom; 7011 uint32_t eecd; 7012 uint16_t words_written = 0; 7013 uint16_t i = 0; 7014 DEBUGFUNC("em_write_eeprom_microwire"); 7015 /* 7016 * Send the write enable command to the EEPROM (3-bit opcode plus 7017 * 6/8-bit dummy address beginning with 11). It's less work to 7018 * include the 11 of the dummy address as part of the opcode than it 7019 * is to shift it over the correct number of bits for the address. 7020 * This puts the EEPROM into write/erase mode. 7021 */ 7022 em_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE, 7023 (uint16_t) (eeprom->opcode_bits + 2)); 7024 7025 em_shift_out_ee_bits(hw, 0, (uint16_t) (eeprom->address_bits - 2)); 7026 7027 /* Prepare the EEPROM */ 7028 em_standby_eeprom(hw); 7029 7030 while (words_written < words) { 7031 /* Send the Write command (3-bit opcode + addr) */ 7032 em_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE, 7033 eeprom->opcode_bits); 7034 7035 em_shift_out_ee_bits(hw, (uint16_t) (offset + words_written), 7036 eeprom->address_bits); 7037 7038 /* Send the data */ 7039 em_shift_out_ee_bits(hw, data[words_written], 16); 7040 /* 7041 * Toggle the CS line. This in effect tells the EEPROM to 7042 * execute the previous command. 7043 */ 7044 em_standby_eeprom(hw); 7045 /* 7046 * Read DO repeatedly until it is high (equal to '1'). The 7047 * EEPROM will signal that the command has been completed by 7048 * raising the DO signal. If DO does not go high in 10 7049 * milliseconds, then error out. 7050 */ 7051 for (i = 0; i < 200; i++) { 7052 eecd = E1000_READ_REG(hw, EECD); 7053 if (eecd & E1000_EECD_DO) 7054 break; 7055 usec_delay(50); 7056 } 7057 if (i == 200) { 7058 DEBUGOUT("EEPROM Write did not complete\n"); 7059 return -E1000_ERR_EEPROM; 7060 } 7061 /* Recover from write */ 7062 em_standby_eeprom(hw); 7063 7064 words_written++; 7065 } 7066 /* 7067 * Send the write disable command to the EEPROM (3-bit opcode plus 7068 * 6/8-bit dummy address beginning with 10). It's less work to 7069 * include the 10 of the dummy address as part of the opcode than it 7070 * is to shift it over the correct number of bits for the address. 7071 * This takes the EEPROM out of write/erase mode. 7072 */ 7073 em_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE, 7074 (uint16_t) (eeprom->opcode_bits + 2)); 7075 7076 em_shift_out_ee_bits(hw, 0, (uint16_t) (eeprom->address_bits - 2)); 7077 7078 return E1000_SUCCESS; 7079 } 7080 7081 /****************************************************************************** 7082 * Flushes the cached eeprom to NVM. This is done by saving the modified values 7083 * in the eeprom cache and the non modified values in the currently active bank 7084 * to the new bank. 7085 * 7086 * hw - Struct containing variables accessed by shared code 7087 * offset - offset of word in the EEPROM to read 7088 * data - word read from the EEPROM 7089 * words - number of words to read 7090 *****************************************************************************/ 7091 STATIC int32_t 7092 em_commit_shadow_ram(struct em_hw *hw) 7093 { 7094 uint32_t attempts = 100000; 7095 uint32_t eecd = 0; 7096 uint32_t flop = 0; 7097 uint32_t i = 0; 7098 int32_t error = E1000_SUCCESS; 7099 uint32_t old_bank_offset = 0; 7100 uint32_t new_bank_offset = 0; 7101 uint8_t low_byte = 0; 7102 uint8_t high_byte = 0; 7103 boolean_t sector_write_failed = FALSE; 7104 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) { 7105 /* 7106 * The flop register will be used to determine if flash type 7107 * is STM 7108 */ 7109 flop = E1000_READ_REG(hw, FLOP); 7110 for (i = 0; i < attempts; i++) { 7111 eecd = E1000_READ_REG(hw, EECD); 7112 if ((eecd & E1000_EECD_FLUPD) == 0) { 7113 break; 7114 } 7115 usec_delay(5); 7116 } 7117 7118 if (i == attempts) { 7119 return -E1000_ERR_EEPROM; 7120 } 7121 /* 7122 * If STM opcode located in bits 15:8 of flop, reset firmware 7123 */ 7124 if ((flop & 0xFF00) == E1000_STM_OPCODE) { 7125 E1000_WRITE_REG(hw, HICR, E1000_HICR_FW_RESET); 7126 } 7127 /* Perform the flash update */ 7128 E1000_WRITE_REG(hw, EECD, eecd | E1000_EECD_FLUPD); 7129 7130 for (i = 0; i < attempts; i++) { 7131 eecd = E1000_READ_REG(hw, EECD); 7132 if ((eecd & E1000_EECD_FLUPD) == 0) { 7133 break; 7134 } 7135 usec_delay(5); 7136 } 7137 7138 if (i == attempts) { 7139 return -E1000_ERR_EEPROM; 7140 } 7141 } 7142 if ((hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) && 7143 hw->eeprom_shadow_ram != NULL) { 7144 /* 7145 * We're writing to the opposite bank so if we're on bank 1, 7146 * write to bank 0 etc. We also need to erase the segment 7147 * that is going to be written 7148 */ 7149 if (!(E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL)) { 7150 new_bank_offset = hw->flash_bank_size * 2; 7151 old_bank_offset = 0; 7152 em_erase_ich8_4k_segment(hw, 1); 7153 } else { 7154 old_bank_offset = hw->flash_bank_size * 2; 7155 new_bank_offset = 0; 7156 em_erase_ich8_4k_segment(hw, 0); 7157 } 7158 7159 sector_write_failed = FALSE; 7160 /* 7161 * Loop for every byte in the shadow RAM, which is in units 7162 * of words. 7163 */ 7164 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 7165 /* 7166 * Determine whether to write the value stored in the 7167 * other NVM bank or a modified value stored in the 7168 * shadow RAM 7169 */ 7170 if (hw->eeprom_shadow_ram[i].modified == TRUE) { 7171 low_byte = (uint8_t) 7172 hw->eeprom_shadow_ram[i].eeprom_word; 7173 usec_delay(100); 7174 error = em_verify_write_ich8_byte(hw, 7175 (i << 1) + new_bank_offset, low_byte); 7176 7177 if (error != E1000_SUCCESS) 7178 sector_write_failed = TRUE; 7179 else { 7180 high_byte = (uint8_t) 7181 (hw->eeprom_shadow_ram 7182 [i].eeprom_word >> 8); 7183 usec_delay(100); 7184 } 7185 } else { 7186 em_read_ich8_byte(hw, (i << 1) + 7187 old_bank_offset, &low_byte); 7188 usec_delay(100); 7189 error = em_verify_write_ich8_byte(hw, 7190 (i << 1) + new_bank_offset, low_byte); 7191 7192 if (error != E1000_SUCCESS) 7193 sector_write_failed = TRUE; 7194 else { 7195 em_read_ich8_byte(hw, (i << 1) + 7196 old_bank_offset + 1, &high_byte); 7197 usec_delay(100); 7198 } 7199 } 7200 /* 7201 * If the write of the low byte was successful, go 7202 * ahread and write the high byte while checking to 7203 * make sure that if it is the signature byte, then 7204 * it is handled properly 7205 */ 7206 if (sector_write_failed == FALSE) { 7207 /* 7208 * If the word is 0x13, then make sure the 7209 * signature bits (15:14) are 11b until the 7210 * commit has completed. This will allow us 7211 * to write 10b which indicates the signature 7212 * is valid. We want to do this after the 7213 * write has completed so that we don't mark 7214 * the segment valid while the write is still 7215 * in progress 7216 */ 7217 if (i == E1000_ICH_NVM_SIG_WORD) 7218 high_byte = E1000_ICH_NVM_VALID_SIG_MASK | 7219 high_byte; 7220 7221 error = em_verify_write_ich8_byte(hw, (i << 1) 7222 + new_bank_offset + 1, high_byte); 7223 if (error != E1000_SUCCESS) 7224 sector_write_failed = TRUE; 7225 7226 } else { 7227 /* 7228 * If the write failed then break from the 7229 * loop and return an error 7230 */ 7231 break; 7232 } 7233 } 7234 /* 7235 * Don't bother writing the segment valid bits if sector 7236 * programming failed. 7237 */ 7238 if (sector_write_failed == FALSE) { 7239 /* 7240 * Finally validate the new segment by setting bit 7241 * 15:14 to 10b in word 0x13 , this can be done 7242 * without an erase as well since these bits are 11 7243 * to start with and we need to change bit 14 to 0b 7244 */ 7245 em_read_ich8_byte(hw, E1000_ICH_NVM_SIG_WORD * 2 + 1 + 7246 new_bank_offset, &high_byte); 7247 high_byte &= 0xBF; 7248 error = em_verify_write_ich8_byte(hw, 7249 E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset, 7250 high_byte); 7251 /* 7252 * And invalidate the previously valid segment by 7253 * setting its signature word (0x13) high_byte to 0b. 7254 * This can be done without an erase because flash 7255 * erase sets all bits to 1's. We can write 1's to 7256 * 0's without an erase 7257 */ 7258 if (error == E1000_SUCCESS) { 7259 error = em_verify_write_ich8_byte(hw, 7260 E1000_ICH_NVM_SIG_WORD * 2 + 1 + 7261 old_bank_offset, 0); 7262 } 7263 /* Clear the now not used entry in the cache */ 7264 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 7265 hw->eeprom_shadow_ram[i].modified = FALSE; 7266 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF; 7267 } 7268 } 7269 } 7270 return error; 7271 } 7272 7273 /****************************************************************************** 7274 * Reads the adapter's part number from the EEPROM 7275 * 7276 * hw - Struct containing variables accessed by shared code 7277 * part_num - Adapter's part number 7278 *****************************************************************************/ 7279 int32_t 7280 em_read_part_num(struct em_hw *hw, uint32_t *part_num) 7281 { 7282 uint16_t offset = EEPROM_PBA_BYTE_1; 7283 uint16_t eeprom_data; 7284 DEBUGFUNC("em_read_part_num"); 7285 7286 /* Get word 0 from EEPROM */ 7287 if (em_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { 7288 DEBUGOUT("EEPROM Read Error\n"); 7289 return -E1000_ERR_EEPROM; 7290 } 7291 /* Save word 0 in upper half of part_num */ 7292 *part_num = (uint32_t) (eeprom_data << 16); 7293 7294 /* Get word 1 from EEPROM */ 7295 if (em_read_eeprom(hw, ++offset, 1, &eeprom_data) < 0) { 7296 DEBUGOUT("EEPROM Read Error\n"); 7297 return -E1000_ERR_EEPROM; 7298 } 7299 /* Save word 1 in lower half of part_num */ 7300 *part_num |= eeprom_data; 7301 7302 return E1000_SUCCESS; 7303 } 7304 7305 /****************************************************************************** 7306 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the 7307 * second function of dual function devices 7308 * 7309 * hw - Struct containing variables accessed by shared code 7310 *****************************************************************************/ 7311 int32_t 7312 em_read_mac_addr(struct em_hw *hw) 7313 { 7314 uint16_t offset; 7315 uint16_t eeprom_data, i; 7316 uint16_t ia_base_addr = 0; 7317 DEBUGFUNC("em_read_mac_addr"); 7318 7319 if (hw->mac_type == em_icp_xxxx) { 7320 ia_base_addr = (uint16_t) 7321 EEPROM_IA_START_ICP_xxxx(hw->icp_xxxx_port_num); 7322 } else if (hw->mac_type == em_82580 || hw->mac_type == em_i350) { 7323 ia_base_addr = NVM_82580_LAN_FUNC_OFFSET(hw->bus_func); 7324 } 7325 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) { 7326 offset = i >> 1; 7327 if (em_read_eeprom(hw, offset + ia_base_addr, 1, &eeprom_data) 7328 < 0) { 7329 DEBUGOUT("EEPROM Read Error\n"); 7330 return -E1000_ERR_EEPROM; 7331 } 7332 hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF); 7333 hw->perm_mac_addr[i + 1] = (uint8_t) (eeprom_data >> 8); 7334 } 7335 7336 switch (hw->mac_type) { 7337 default: 7338 break; 7339 case em_82546: 7340 case em_82546_rev_3: 7341 case em_82571: 7342 case em_82575: 7343 case em_82576: 7344 case em_80003es2lan: 7345 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) 7346 hw->perm_mac_addr[5] ^= 0x01; 7347 break; 7348 } 7349 7350 for (i = 0; i < NODE_ADDRESS_SIZE; i++) 7351 hw->mac_addr[i] = hw->perm_mac_addr[i]; 7352 return E1000_SUCCESS; 7353 } 7354 7355 /****************************************************************************** 7356 * Explicitly disables jumbo frames and resets some PHY registers back to hw- 7357 * defaults. This is necessary in case the ethernet cable was inserted AFTER 7358 * the firmware initialized the PHY. Otherwise it is left in a state where 7359 * it is possible to transmit but not receive packets. Observed on I217-LM and 7360 * fixed in FreeBSD's sys/dev/e1000/e1000_ich8lan.c. 7361 * 7362 * hw - Struct containing variables accessed by shared code 7363 *****************************************************************************/ 7364 STATIC int32_t 7365 em_phy_no_cable_workaround(struct em_hw *hw) { 7366 int32_t ret_val, dft_ret_val; 7367 uint32_t mac_reg; 7368 uint16_t data, phy_reg; 7369 7370 /* disable Rx path while enabling workaround */ 7371 em_read_phy_reg(hw, I2_DFT_CTRL, &phy_reg); 7372 ret_val = em_write_phy_reg(hw, I2_DFT_CTRL, phy_reg | (1 << 14)); 7373 if (ret_val) 7374 return ret_val; 7375 7376 /* Write MAC register values back to h/w defaults */ 7377 mac_reg = E1000_READ_REG(hw, FFLT_DBG); 7378 mac_reg &= ~(0xF << 14); 7379 E1000_WRITE_REG(hw, FFLT_DBG, mac_reg); 7380 7381 mac_reg = E1000_READ_REG(hw, RCTL); 7382 mac_reg &= ~E1000_RCTL_SECRC; 7383 E1000_WRITE_REG(hw, RCTL, mac_reg); 7384 7385 ret_val = em_read_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_CTRL, &data); 7386 if (ret_val) 7387 goto out; 7388 ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_CTRL, 7389 data & ~(1 << 0)); 7390 if (ret_val) 7391 goto out; 7392 7393 ret_val = em_read_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL, &data); 7394 if (ret_val) 7395 goto out; 7396 7397 data &= ~(0xF << 8); 7398 data |= (0xB << 8); 7399 ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL, data); 7400 if (ret_val) 7401 goto out; 7402 7403 /* Write PHY register values back to h/w defaults */ 7404 em_read_phy_reg(hw, I2_SMBUS_CTRL, &data); 7405 data &= ~(0x7F << 5); 7406 ret_val = em_write_phy_reg(hw, I2_SMBUS_CTRL, data); 7407 if (ret_val) 7408 goto out; 7409 7410 em_read_phy_reg(hw, I2_MODE_CTRL, &data); 7411 data |= (1 << 13); 7412 ret_val = em_write_phy_reg(hw, I2_MODE_CTRL, data); 7413 if (ret_val) 7414 goto out; 7415 7416 /* 7417 * 776.20 and 776.23 are not documented in 7418 * i217-ethernet-controller-datasheet.pdf... 7419 */ 7420 em_read_phy_reg(hw, PHY_REG(776, 20), &data); 7421 data &= ~(0x3FF << 2); 7422 data |= (0x8 << 2); 7423 ret_val = em_write_phy_reg(hw, PHY_REG(776, 20), data); 7424 if (ret_val) 7425 goto out; 7426 7427 ret_val = em_write_phy_reg(hw, PHY_REG(776, 23), 0x7E00); 7428 if (ret_val) 7429 goto out; 7430 7431 em_read_phy_reg(hw, I2_PCIE_POWER_CTRL, &data); 7432 ret_val = em_write_phy_reg(hw, I2_PCIE_POWER_CTRL, data & ~(1 << 10)); 7433 if (ret_val) 7434 goto out; 7435 7436 out: 7437 /* re-enable Rx path after enabling workaround */ 7438 dft_ret_val = em_write_phy_reg(hw, I2_DFT_CTRL, phy_reg & ~(1 << 14)); 7439 if (ret_val) 7440 return ret_val; 7441 else 7442 return dft_ret_val; 7443 } 7444 7445 /****************************************************************************** 7446 * Initializes receive address filters. 7447 * 7448 * hw - Struct containing variables accessed by shared code 7449 * 7450 * Places the MAC address in receive address register 0 and clears the rest 7451 * of the receive addresss registers. Clears the multicast table. Assumes 7452 * the receiver is in reset when the routine is called. 7453 *****************************************************************************/ 7454 STATIC void 7455 em_init_rx_addrs(struct em_hw *hw) 7456 { 7457 uint32_t i; 7458 uint32_t rar_num; 7459 DEBUGFUNC("em_init_rx_addrs"); 7460 7461 if (hw->mac_type == em_pch_lpt || hw->mac_type == em_pch_spt || 7462 hw->mac_type == em_pch_cnp || hw->mac_type == em_pch2lan) 7463 if (em_phy_no_cable_workaround(hw)) 7464 printf(" ...failed to apply em_phy_no_cable_" 7465 "workaround.\n"); 7466 7467 /* Setup the receive address. */ 7468 DEBUGOUT("Programming MAC Address into RAR[0]\n"); 7469 7470 em_rar_set(hw, hw->mac_addr, 0); 7471 7472 rar_num = E1000_RAR_ENTRIES; 7473 /* 7474 * Reserve a spot for the Locally Administered Address to work around 7475 * an 82571 issue in which a reset on one port will reload the MAC on 7476 * the other port. 7477 */ 7478 if ((hw->mac_type == em_82571) && (hw->laa_is_present == TRUE)) 7479 rar_num -= 1; 7480 if (IS_ICH8(hw->mac_type)) 7481 rar_num = E1000_RAR_ENTRIES_ICH8LAN; 7482 if (hw->mac_type == em_ich8lan) 7483 rar_num -= 1; 7484 if (hw->mac_type == em_82580) 7485 rar_num = E1000_RAR_ENTRIES_82580; 7486 if (hw->mac_type == em_i210) 7487 rar_num = E1000_RAR_ENTRIES_82575; 7488 if (hw->mac_type == em_i350) 7489 rar_num = E1000_RAR_ENTRIES_I350; 7490 7491 /* Zero out the other 15 receive addresses. */ 7492 DEBUGOUT("Clearing RAR[1-15]\n"); 7493 for (i = 1; i < rar_num; i++) { 7494 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 7495 E1000_WRITE_FLUSH(hw); 7496 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 7497 E1000_WRITE_FLUSH(hw); 7498 } 7499 } 7500 7501 /****************************************************************************** 7502 * Updates the MAC's list of multicast addresses. 7503 * 7504 * hw - Struct containing variables accessed by shared code 7505 * mc_addr_list - the list of new multicast addresses 7506 * mc_addr_count - number of addresses 7507 * pad - number of bytes between addresses in the list 7508 * rar_used_count - offset where to start adding mc addresses into the RAR's 7509 * 7510 * The given list replaces any existing list. Clears the last 15 receive 7511 * address registers and the multicast table. Uses receive address registers 7512 * for the first 15 multicast addresses, and hashes the rest into the 7513 * multicast table. 7514 *****************************************************************************/ 7515 void 7516 em_mc_addr_list_update(struct em_hw *hw, uint8_t *mc_addr_list, 7517 uint32_t mc_addr_count, uint32_t pad, uint32_t rar_used_count) 7518 { 7519 uint32_t hash_value; 7520 uint32_t i; 7521 uint32_t num_rar_entry; 7522 uint32_t num_mta_entry; 7523 DEBUGFUNC("em_mc_addr_list_update"); 7524 /* 7525 * Set the new number of MC addresses that we are being requested to 7526 * use. 7527 */ 7528 hw->num_mc_addrs = mc_addr_count; 7529 7530 /* Clear RAR[1-15] */ 7531 DEBUGOUT(" Clearing RAR[1-15]\n"); 7532 num_rar_entry = E1000_RAR_ENTRIES; 7533 if (IS_ICH8(hw->mac_type)) 7534 num_rar_entry = E1000_RAR_ENTRIES_ICH8LAN; 7535 if (hw->mac_type == em_ich8lan) 7536 num_rar_entry -= 1; 7537 /* 7538 * Reserve a spot for the Locally Administered Address to work around 7539 * an 82571 issue in which a reset on one port will reload the MAC on 7540 * the other port. 7541 */ 7542 if ((hw->mac_type == em_82571) && (hw->laa_is_present == TRUE)) 7543 num_rar_entry -= 1; 7544 7545 for (i = rar_used_count; i < num_rar_entry; i++) { 7546 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 7547 E1000_WRITE_FLUSH(hw); 7548 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 7549 E1000_WRITE_FLUSH(hw); 7550 } 7551 7552 /* Clear the MTA */ 7553 DEBUGOUT(" Clearing MTA\n"); 7554 num_mta_entry = E1000_NUM_MTA_REGISTERS; 7555 if (IS_ICH8(hw->mac_type)) 7556 num_mta_entry = E1000_NUM_MTA_REGISTERS_ICH8LAN; 7557 7558 for (i = 0; i < num_mta_entry; i++) { 7559 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 7560 E1000_WRITE_FLUSH(hw); 7561 } 7562 7563 /* Add the new addresses */ 7564 for (i = 0; i < mc_addr_count; i++) { 7565 DEBUGOUT(" Adding the multicast addresses:\n"); 7566 DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i, 7567 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad)], 7568 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 1], 7569 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 2], 7570 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 3], 7571 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 4], 7572 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 5]); 7573 7574 hash_value = em_hash_mc_addr(hw, mc_addr_list + 7575 (i * (ETH_LENGTH_OF_ADDRESS + pad))); 7576 7577 DEBUGOUT1(" Hash value = 0x%03X\n", hash_value); 7578 /* 7579 * Place this multicast address in the RAR if there is room, * 7580 * else put it in the MTA 7581 */ 7582 if (rar_used_count < num_rar_entry) { 7583 em_rar_set(hw, mc_addr_list + 7584 (i * (ETH_LENGTH_OF_ADDRESS + pad)), 7585 rar_used_count); 7586 rar_used_count++; 7587 } else { 7588 em_mta_set(hw, hash_value); 7589 } 7590 } 7591 DEBUGOUT("MC Update Complete\n"); 7592 } 7593 7594 /****************************************************************************** 7595 * Hashes an address to determine its location in the multicast table 7596 * 7597 * hw - Struct containing variables accessed by shared code 7598 * mc_addr - the multicast address to hash 7599 *****************************************************************************/ 7600 uint32_t 7601 em_hash_mc_addr(struct em_hw *hw, uint8_t *mc_addr) 7602 { 7603 uint32_t hash_value = 0; 7604 /* 7605 * The portion of the address that is used for the hash table is 7606 * determined by the mc_filter_type setting. 7607 */ 7608 switch (hw->mc_filter_type) { 7609 /* 7610 * [0] [1] [2] [3] [4] [5] 01 AA 00 12 34 56 LSB 7611 * MSB 7612 */ 7613 case 0: 7614 if (IS_ICH8(hw->mac_type)) { 7615 /* [47:38] i.e. 0x158 for above example address */ 7616 hash_value = ((mc_addr[4] >> 6) | 7617 (((uint16_t) mc_addr[5]) << 2)); 7618 } else { 7619 /* [47:36] i.e. 0x563 for above example address */ 7620 hash_value = ((mc_addr[4] >> 4) | 7621 (((uint16_t) mc_addr[5]) << 4)); 7622 } 7623 break; 7624 case 1: 7625 if (IS_ICH8(hw->mac_type)) { 7626 /* [46:37] i.e. 0x2B1 for above example address */ 7627 hash_value = ((mc_addr[4] >> 5) | 7628 (((uint16_t) mc_addr[5]) << 3)); 7629 } else { 7630 /* [46:35] i.e. 0xAC6 for above example address */ 7631 hash_value = ((mc_addr[4] >> 3) | 7632 (((uint16_t) mc_addr[5]) << 5)); 7633 } 7634 break; 7635 case 2: 7636 if (IS_ICH8(hw->mac_type)) { 7637 /* [45:36] i.e. 0x163 for above example address */ 7638 hash_value = ((mc_addr[4] >> 4) | 7639 (((uint16_t) mc_addr[5]) << 4)); 7640 } else { 7641 /* [45:34] i.e. 0x5D8 for above example address */ 7642 hash_value = ((mc_addr[4] >> 2) | 7643 (((uint16_t) mc_addr[5]) << 6)); 7644 } 7645 break; 7646 case 3: 7647 if (IS_ICH8(hw->mac_type)) { 7648 /* [43:34] i.e. 0x18D for above example address */ 7649 hash_value = ((mc_addr[4] >> 2) | 7650 (((uint16_t) mc_addr[5]) << 6)); 7651 } else { 7652 /* [43:32] i.e. 0x634 for above example address */ 7653 hash_value = ((mc_addr[4]) | 7654 (((uint16_t) mc_addr[5]) << 8)); 7655 } 7656 break; 7657 } 7658 7659 hash_value &= 0xFFF; 7660 if (IS_ICH8(hw->mac_type)) 7661 hash_value &= 0x3FF; 7662 7663 return hash_value; 7664 } 7665 7666 /****************************************************************************** 7667 * Sets the bit in the multicast table corresponding to the hash value. 7668 * 7669 * hw - Struct containing variables accessed by shared code 7670 * hash_value - Multicast address hash value 7671 *****************************************************************************/ 7672 void 7673 em_mta_set(struct em_hw *hw, uint32_t hash_value) 7674 { 7675 uint32_t hash_bit, hash_reg; 7676 uint32_t mta; 7677 uint32_t temp; 7678 /* 7679 * The MTA is a register array of 128 32-bit registers. It is treated 7680 * like an array of 4096 bits. We want to set bit 7681 * BitArray[hash_value]. So we figure out what register the bit is 7682 * in, read it, OR in the new bit, then write back the new value. 7683 * The register is determined by the upper 7 bits of the hash value 7684 * and the bit within that register are determined by the lower 5 7685 * bits of the value. 7686 */ 7687 hash_reg = (hash_value >> 5) & 0x7F; 7688 if (IS_ICH8(hw->mac_type)) 7689 hash_reg &= 0x1F; 7690 7691 hash_bit = hash_value & 0x1F; 7692 7693 mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg); 7694 7695 mta |= (1 << hash_bit); 7696 /* 7697 * If we are on an 82544 and we are trying to write an odd offset in 7698 * the MTA, save off the previous entry before writing and restore 7699 * the old value after writing. 7700 */ 7701 if ((hw->mac_type == em_82544) && ((hash_reg & 0x1) == 1)) { 7702 temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1)); 7703 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta); 7704 E1000_WRITE_FLUSH(hw); 7705 E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp); 7706 E1000_WRITE_FLUSH(hw); 7707 } else { 7708 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta); 7709 E1000_WRITE_FLUSH(hw); 7710 } 7711 } 7712 7713 /****************************************************************************** 7714 * Puts an ethernet address into a receive address register. 7715 * 7716 * hw - Struct containing variables accessed by shared code 7717 * addr - Address to put into receive address register 7718 * index - Receive address register to write 7719 *****************************************************************************/ 7720 void 7721 em_rar_set(struct em_hw *hw, uint8_t *addr, uint32_t index) 7722 { 7723 uint32_t rar_low, rar_high; 7724 /* 7725 * HW expects these in little endian so we reverse the byte order 7726 * from network order (big endian) to little endian 7727 */ 7728 rar_low = ((uint32_t) addr[0] | ((uint32_t) addr[1] << 8) | 7729 ((uint32_t) addr[2] << 16) | ((uint32_t) addr[3] << 24)); 7730 rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8)); 7731 /* 7732 * Disable Rx and flush all Rx frames before enabling RSS to avoid Rx 7733 * unit hang. 7734 * 7735 * Description: If there are any Rx frames queued up or otherwise 7736 * present in the HW before RSS is enabled, and then we enable RSS, 7737 * the HW Rx unit will hang. To work around this issue, we have to 7738 * disable receives and flush out all Rx frames before we enable RSS. 7739 * To do so, we modify we redirect all Rx traffic to manageability 7740 * and then reset the HW. This flushes away Rx frames, and (since the 7741 * redirections to manageability persists across resets) keeps new 7742 * ones from coming in while we work. Then, we clear the Address 7743 * Valid AV bit for all MAC addresses and undo the re-direction to 7744 * manageability. Now, frames are coming in again, but the MAC won't 7745 * accept them, so far so good. We now proceed to initialize RSS (if 7746 * necessary) and configure the Rx unit. Last, we re-enable the AV 7747 * bits and continue on our merry way. 7748 */ 7749 switch (hw->mac_type) { 7750 case em_82571: 7751 case em_82572: 7752 case em_80003es2lan: 7753 if (hw->leave_av_bit_off == TRUE) 7754 break; 7755 default: 7756 /* Indicate to hardware the Address is Valid. */ 7757 rar_high |= E1000_RAH_AV; 7758 break; 7759 } 7760 7761 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low); 7762 E1000_WRITE_FLUSH(hw); 7763 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high); 7764 E1000_WRITE_FLUSH(hw); 7765 } 7766 7767 /****************************************************************************** 7768 * Clears the VLAN filer table 7769 * 7770 * hw - Struct containing variables accessed by shared code 7771 *****************************************************************************/ 7772 STATIC void 7773 em_clear_vfta(struct em_hw *hw) 7774 { 7775 uint32_t offset; 7776 uint32_t vfta_value = 0; 7777 uint32_t vfta_offset = 0; 7778 uint32_t vfta_bit_in_reg = 0; 7779 if (IS_ICH8(hw->mac_type)) 7780 return; 7781 7782 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) { 7783 if (hw->mng_cookie.vlan_id != 0) { 7784 /* 7785 * The VFTA is a 4096b bit-field, each identifying a 7786 * single VLAN ID. The following operations 7787 * determine which 32b entry (i.e. offset) into the 7788 * array we want to set the VLAN ID (i.e. bit) of the 7789 * manageability unit. 7790 */ 7791 vfta_offset = (hw->mng_cookie.vlan_id >> 7792 E1000_VFTA_ENTRY_SHIFT) & E1000_VFTA_ENTRY_MASK; 7793 7794 vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id & 7795 E1000_VFTA_ENTRY_BIT_SHIFT_MASK); 7796 } 7797 } 7798 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 7799 /* 7800 * If the offset we want to clear is the same offset of the 7801 * manageability VLAN ID, then clear all bits except that of 7802 * the manageability unit 7803 */ 7804 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; 7805 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value); 7806 E1000_WRITE_FLUSH(hw); 7807 } 7808 } 7809 7810 /* 7811 * Due to hw errata, if the host tries to configure the VFTA register 7812 * while performing queries from the BMC or DMA, then the VFTA in some 7813 * cases won't be written. 7814 */ 7815 void 7816 em_clear_vfta_i350(struct em_hw *hw) 7817 { 7818 uint32_t offset; 7819 int i; 7820 7821 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 7822 for (i = 0; i < 10; i++) 7823 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0); 7824 E1000_WRITE_FLUSH(hw); 7825 } 7826 } 7827 7828 STATIC int32_t 7829 em_id_led_init(struct em_hw *hw) 7830 { 7831 uint32_t ledctl; 7832 const uint32_t ledctl_mask = 0x000000FF; 7833 const uint32_t ledctl_on = E1000_LEDCTL_MODE_LED_ON; 7834 const uint32_t ledctl_off = E1000_LEDCTL_MODE_LED_OFF; 7835 uint16_t eeprom_data, i, temp; 7836 const uint16_t led_mask = 0x0F; 7837 DEBUGFUNC("em_id_led_init"); 7838 7839 if (hw->mac_type < em_82540 || hw->mac_type == em_icp_xxxx) { 7840 /* Nothing to do */ 7841 return E1000_SUCCESS; 7842 } 7843 ledctl = E1000_READ_REG(hw, LEDCTL); 7844 hw->ledctl_default = ledctl; 7845 hw->ledctl_mode1 = hw->ledctl_default; 7846 hw->ledctl_mode2 = hw->ledctl_default; 7847 7848 if (em_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) { 7849 DEBUGOUT("EEPROM Read Error\n"); 7850 return -E1000_ERR_EEPROM; 7851 } 7852 if ((hw->mac_type == em_82573) && 7853 (eeprom_data == ID_LED_RESERVED_82573)) 7854 eeprom_data = ID_LED_DEFAULT_82573; 7855 else if ((eeprom_data == ID_LED_RESERVED_0000) || 7856 (eeprom_data == ID_LED_RESERVED_FFFF)) { 7857 if (hw->mac_type == em_ich8lan || 7858 hw->mac_type == em_ich9lan || 7859 hw->mac_type == em_ich10lan) // XXX 7860 eeprom_data = ID_LED_DEFAULT_ICH8LAN; 7861 else 7862 eeprom_data = ID_LED_DEFAULT; 7863 } 7864 for (i = 0; i < 4; i++) { 7865 temp = (eeprom_data >> (i << 2)) & led_mask; 7866 switch (temp) { 7867 case ID_LED_ON1_DEF2: 7868 case ID_LED_ON1_ON2: 7869 case ID_LED_ON1_OFF2: 7870 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 7871 hw->ledctl_mode1 |= ledctl_on << (i << 3); 7872 break; 7873 case ID_LED_OFF1_DEF2: 7874 case ID_LED_OFF1_ON2: 7875 case ID_LED_OFF1_OFF2: 7876 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 7877 hw->ledctl_mode1 |= ledctl_off << (i << 3); 7878 break; 7879 default: 7880 /* Do nothing */ 7881 break; 7882 } 7883 switch (temp) { 7884 case ID_LED_DEF1_ON2: 7885 case ID_LED_ON1_ON2: 7886 case ID_LED_OFF1_ON2: 7887 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 7888 hw->ledctl_mode2 |= ledctl_on << (i << 3); 7889 break; 7890 case ID_LED_DEF1_OFF2: 7891 case ID_LED_ON1_OFF2: 7892 case ID_LED_OFF1_OFF2: 7893 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 7894 hw->ledctl_mode2 |= ledctl_off << (i << 3); 7895 break; 7896 default: 7897 /* Do nothing */ 7898 break; 7899 } 7900 } 7901 return E1000_SUCCESS; 7902 } 7903 7904 /****************************************************************************** 7905 * Clears all hardware statistics counters. 7906 * 7907 * hw - Struct containing variables accessed by shared code 7908 *****************************************************************************/ 7909 void 7910 em_clear_hw_cntrs(struct em_hw *hw) 7911 { 7912 volatile uint32_t temp; 7913 temp = E1000_READ_REG(hw, CRCERRS); 7914 temp = E1000_READ_REG(hw, SYMERRS); 7915 temp = E1000_READ_REG(hw, MPC); 7916 temp = E1000_READ_REG(hw, SCC); 7917 temp = E1000_READ_REG(hw, ECOL); 7918 temp = E1000_READ_REG(hw, MCC); 7919 temp = E1000_READ_REG(hw, LATECOL); 7920 temp = E1000_READ_REG(hw, COLC); 7921 temp = E1000_READ_REG(hw, DC); 7922 temp = E1000_READ_REG(hw, SEC); 7923 temp = E1000_READ_REG(hw, RLEC); 7924 temp = E1000_READ_REG(hw, XONRXC); 7925 temp = E1000_READ_REG(hw, XONTXC); 7926 temp = E1000_READ_REG(hw, XOFFRXC); 7927 temp = E1000_READ_REG(hw, XOFFTXC); 7928 temp = E1000_READ_REG(hw, FCRUC); 7929 7930 if (!IS_ICH8(hw->mac_type)) { 7931 temp = E1000_READ_REG(hw, PRC64); 7932 temp = E1000_READ_REG(hw, PRC127); 7933 temp = E1000_READ_REG(hw, PRC255); 7934 temp = E1000_READ_REG(hw, PRC511); 7935 temp = E1000_READ_REG(hw, PRC1023); 7936 temp = E1000_READ_REG(hw, PRC1522); 7937 } 7938 temp = E1000_READ_REG(hw, GPRC); 7939 temp = E1000_READ_REG(hw, BPRC); 7940 temp = E1000_READ_REG(hw, MPRC); 7941 temp = E1000_READ_REG(hw, GPTC); 7942 temp = E1000_READ_REG(hw, GORCL); 7943 temp = E1000_READ_REG(hw, GORCH); 7944 temp = E1000_READ_REG(hw, GOTCL); 7945 temp = E1000_READ_REG(hw, GOTCH); 7946 temp = E1000_READ_REG(hw, RNBC); 7947 temp = E1000_READ_REG(hw, RUC); 7948 temp = E1000_READ_REG(hw, RFC); 7949 temp = E1000_READ_REG(hw, ROC); 7950 temp = E1000_READ_REG(hw, RJC); 7951 temp = E1000_READ_REG(hw, TORL); 7952 temp = E1000_READ_REG(hw, TORH); 7953 temp = E1000_READ_REG(hw, TOTL); 7954 temp = E1000_READ_REG(hw, TOTH); 7955 temp = E1000_READ_REG(hw, TPR); 7956 temp = E1000_READ_REG(hw, TPT); 7957 7958 if (!IS_ICH8(hw->mac_type)) { 7959 temp = E1000_READ_REG(hw, PTC64); 7960 temp = E1000_READ_REG(hw, PTC127); 7961 temp = E1000_READ_REG(hw, PTC255); 7962 temp = E1000_READ_REG(hw, PTC511); 7963 temp = E1000_READ_REG(hw, PTC1023); 7964 temp = E1000_READ_REG(hw, PTC1522); 7965 } 7966 temp = E1000_READ_REG(hw, MPTC); 7967 temp = E1000_READ_REG(hw, BPTC); 7968 7969 if (hw->mac_type < em_82543) 7970 return; 7971 7972 temp = E1000_READ_REG(hw, ALGNERRC); 7973 temp = E1000_READ_REG(hw, RXERRC); 7974 temp = E1000_READ_REG(hw, TNCRS); 7975 temp = E1000_READ_REG(hw, CEXTERR); 7976 temp = E1000_READ_REG(hw, TSCTC); 7977 temp = E1000_READ_REG(hw, TSCTFC); 7978 7979 if (hw->mac_type <= em_82544 7980 || hw->mac_type == em_icp_xxxx) 7981 return; 7982 7983 temp = E1000_READ_REG(hw, MGTPRC); 7984 temp = E1000_READ_REG(hw, MGTPDC); 7985 temp = E1000_READ_REG(hw, MGTPTC); 7986 7987 if (hw->mac_type <= em_82547_rev_2) 7988 return; 7989 7990 temp = E1000_READ_REG(hw, IAC); 7991 temp = E1000_READ_REG(hw, ICRXOC); 7992 7993 if (hw->phy_type == em_phy_82577 || 7994 hw->phy_type == em_phy_82578 || 7995 hw->phy_type == em_phy_82579 || 7996 hw->phy_type == em_phy_i217) { 7997 uint16_t phy_data; 7998 7999 em_read_phy_reg(hw, HV_SCC_UPPER, &phy_data); 8000 em_read_phy_reg(hw, HV_SCC_LOWER, &phy_data); 8001 em_read_phy_reg(hw, HV_ECOL_UPPER, &phy_data); 8002 em_read_phy_reg(hw, HV_ECOL_LOWER, &phy_data); 8003 em_read_phy_reg(hw, HV_MCC_UPPER, &phy_data); 8004 em_read_phy_reg(hw, HV_MCC_LOWER, &phy_data); 8005 em_read_phy_reg(hw, HV_LATECOL_UPPER, &phy_data); 8006 em_read_phy_reg(hw, HV_LATECOL_LOWER, &phy_data); 8007 em_read_phy_reg(hw, HV_COLC_UPPER, &phy_data); 8008 em_read_phy_reg(hw, HV_COLC_LOWER, &phy_data); 8009 em_read_phy_reg(hw, HV_DC_UPPER, &phy_data); 8010 em_read_phy_reg(hw, HV_DC_LOWER, &phy_data); 8011 em_read_phy_reg(hw, HV_TNCRS_UPPER, &phy_data); 8012 em_read_phy_reg(hw, HV_TNCRS_LOWER, &phy_data); 8013 } 8014 8015 if (hw->mac_type == em_ich8lan || 8016 hw->mac_type == em_ich9lan || 8017 hw->mac_type == em_ich10lan || 8018 hw->mac_type == em_pchlan || 8019 (hw->mac_type != em_pch2lan && hw->mac_type != em_pch_lpt && 8020 hw->mac_type != em_pch_spt && hw->mac_type != em_pch_cnp)) 8021 return; 8022 8023 temp = E1000_READ_REG(hw, ICRXPTC); 8024 temp = E1000_READ_REG(hw, ICRXATC); 8025 temp = E1000_READ_REG(hw, ICTXPTC); 8026 temp = E1000_READ_REG(hw, ICTXATC); 8027 temp = E1000_READ_REG(hw, ICTXQEC); 8028 temp = E1000_READ_REG(hw, ICTXQMTC); 8029 temp = E1000_READ_REG(hw, ICRXDMTC); 8030 } 8031 8032 /****************************************************************************** 8033 * Gets the current PCI bus type, speed, and width of the hardware 8034 * 8035 * hw - Struct containing variables accessed by shared code 8036 *****************************************************************************/ 8037 void 8038 em_get_bus_info(struct em_hw *hw) 8039 { 8040 int32_t ret_val; 8041 uint16_t pci_ex_link_status; 8042 uint32_t status; 8043 switch (hw->mac_type) { 8044 case em_82542_rev2_0: 8045 case em_82542_rev2_1: 8046 hw->bus_type = em_bus_type_unknown; 8047 hw->bus_speed = em_bus_speed_unknown; 8048 hw->bus_width = em_bus_width_unknown; 8049 break; 8050 case em_icp_xxxx: 8051 hw->bus_type = em_bus_type_cpp; 8052 hw->bus_speed = em_bus_speed_unknown; 8053 hw->bus_width = em_bus_width_unknown; 8054 break; 8055 case em_82571: 8056 case em_82572: 8057 case em_82573: 8058 case em_82574: 8059 case em_82575: 8060 case em_82576: 8061 case em_82580: 8062 case em_80003es2lan: 8063 case em_i210: 8064 case em_i350: 8065 hw->bus_type = em_bus_type_pci_express; 8066 hw->bus_speed = em_bus_speed_2500; 8067 ret_val = em_read_pcie_cap_reg(hw, PCI_EX_LINK_STATUS, 8068 &pci_ex_link_status); 8069 if (ret_val) 8070 hw->bus_width = em_bus_width_unknown; 8071 else 8072 hw->bus_width = (pci_ex_link_status & 8073 PCI_EX_LINK_WIDTH_MASK) >> PCI_EX_LINK_WIDTH_SHIFT; 8074 break; 8075 case em_ich8lan: 8076 case em_ich9lan: 8077 case em_ich10lan: 8078 case em_pchlan: 8079 case em_pch2lan: 8080 case em_pch_lpt: 8081 case em_pch_spt: 8082 case em_pch_cnp: 8083 hw->bus_type = em_bus_type_pci_express; 8084 hw->bus_speed = em_bus_speed_2500; 8085 hw->bus_width = em_bus_width_pciex_1; 8086 break; 8087 default: 8088 status = E1000_READ_REG(hw, STATUS); 8089 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ? 8090 em_bus_type_pcix : em_bus_type_pci; 8091 8092 if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) { 8093 hw->bus_speed = (hw->bus_type == em_bus_type_pci) ? 8094 em_bus_speed_66 : em_bus_speed_120; 8095 } else if (hw->bus_type == em_bus_type_pci) { 8096 hw->bus_speed = (status & E1000_STATUS_PCI66) ? 8097 em_bus_speed_66 : em_bus_speed_33; 8098 } else { 8099 switch (status & E1000_STATUS_PCIX_SPEED) { 8100 case E1000_STATUS_PCIX_SPEED_66: 8101 hw->bus_speed = em_bus_speed_66; 8102 break; 8103 case E1000_STATUS_PCIX_SPEED_100: 8104 hw->bus_speed = em_bus_speed_100; 8105 break; 8106 case E1000_STATUS_PCIX_SPEED_133: 8107 hw->bus_speed = em_bus_speed_133; 8108 break; 8109 default: 8110 hw->bus_speed = em_bus_speed_reserved; 8111 break; 8112 } 8113 } 8114 hw->bus_width = (status & E1000_STATUS_BUS64) ? 8115 em_bus_width_64 : em_bus_width_32; 8116 break; 8117 } 8118 } 8119 8120 /****************************************************************************** 8121 * Writes a value to one of the devices registers using port I/O (as opposed to 8122 * memory mapped I/O). Only 82544 and newer devices support port I/O. 8123 * 8124 * hw - Struct containing variables accessed by shared code 8125 * offset - offset to write to 8126 * value - value to write 8127 *****************************************************************************/ 8128 STATIC void 8129 em_write_reg_io(struct em_hw *hw, uint32_t offset, uint32_t value) 8130 { 8131 unsigned long io_addr = hw->io_base; 8132 unsigned long io_data = hw->io_base + 4; 8133 em_io_write(hw, io_addr, offset); 8134 em_io_write(hw, io_data, value); 8135 } 8136 8137 /****************************************************************************** 8138 * Estimates the cable length. 8139 * 8140 * hw - Struct containing variables accessed by shared code 8141 * min_length - The estimated minimum length 8142 * max_length - The estimated maximum length 8143 * 8144 * returns: - E1000_ERR_XXX 8145 * E1000_SUCCESS 8146 * 8147 * This function always returns a ranged length (minimum & maximum). 8148 * So for M88 phy's, this function interprets the one value returned from the 8149 * register to the minimum and maximum range. 8150 * For IGP phy's, the function calculates the range by the AGC registers. 8151 *****************************************************************************/ 8152 STATIC int32_t 8153 em_get_cable_length(struct em_hw *hw, uint16_t *min_length, 8154 uint16_t *max_length) 8155 { 8156 int32_t ret_val; 8157 uint16_t agc_value = 0; 8158 uint16_t i, phy_data; 8159 uint16_t cable_length; 8160 DEBUGFUNC("em_get_cable_length"); 8161 8162 *min_length = *max_length = 0; 8163 8164 /* Use old method for Phy older than IGP */ 8165 if (hw->phy_type == em_phy_m88 || 8166 hw->phy_type == em_phy_oem || 8167 hw->phy_type == em_phy_82578) { 8168 8169 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, 8170 &phy_data); 8171 if (ret_val) 8172 return ret_val; 8173 cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 8174 M88E1000_PSSR_CABLE_LENGTH_SHIFT; 8175 8176 /* Convert the enum value to ranged values */ 8177 switch (cable_length) { 8178 case em_cable_length_50: 8179 *min_length = 0; 8180 *max_length = em_igp_cable_length_50; 8181 break; 8182 case em_cable_length_50_80: 8183 *min_length = em_igp_cable_length_50; 8184 *max_length = em_igp_cable_length_80; 8185 break; 8186 case em_cable_length_80_110: 8187 *min_length = em_igp_cable_length_80; 8188 *max_length = em_igp_cable_length_110; 8189 break; 8190 case em_cable_length_110_140: 8191 *min_length = em_igp_cable_length_110; 8192 *max_length = em_igp_cable_length_140; 8193 break; 8194 case em_cable_length_140: 8195 *min_length = em_igp_cable_length_140; 8196 *max_length = em_igp_cable_length_170; 8197 break; 8198 default: 8199 return -E1000_ERR_PHY; 8200 break; 8201 } 8202 } else if (hw->phy_type == em_phy_rtl8211) { 8203 /* no cable length info on RTL8211, fake */ 8204 *min_length = 0; 8205 *max_length = em_igp_cable_length_50; 8206 } else if (hw->phy_type == em_phy_gg82563) { 8207 ret_val = em_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE, 8208 &phy_data); 8209 if (ret_val) 8210 return ret_val; 8211 cable_length = phy_data & GG82563_DSPD_CABLE_LENGTH; 8212 8213 switch (cable_length) { 8214 case em_gg_cable_length_60: 8215 *min_length = 0; 8216 *max_length = em_igp_cable_length_60; 8217 break; 8218 case em_gg_cable_length_60_115: 8219 *min_length = em_igp_cable_length_60; 8220 *max_length = em_igp_cable_length_115; 8221 break; 8222 case em_gg_cable_length_115_150: 8223 *min_length = em_igp_cable_length_115; 8224 *max_length = em_igp_cable_length_150; 8225 break; 8226 case em_gg_cable_length_150: 8227 *min_length = em_igp_cable_length_150; 8228 *max_length = em_igp_cable_length_180; 8229 break; 8230 default: 8231 return -E1000_ERR_PHY; 8232 break; 8233 } 8234 } else if (hw->phy_type == em_phy_igp) { /* For IGP PHY */ 8235 uint16_t cur_agc_value; 8236 uint16_t min_agc_value = 8237 IGP01E1000_AGC_LENGTH_TABLE_SIZE; 8238 uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = 8239 {IGP01E1000_PHY_AGC_A, IGP01E1000_PHY_AGC_B, 8240 IGP01E1000_PHY_AGC_C, IGP01E1000_PHY_AGC_D}; 8241 8242 /* Read the AGC registers for all channels */ 8243 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 8244 ret_val = em_read_phy_reg(hw, agc_reg_array[i], 8245 &phy_data); 8246 if (ret_val) 8247 return ret_val; 8248 8249 cur_agc_value = phy_data >> 8250 IGP01E1000_AGC_LENGTH_SHIFT; 8251 8252 /* Value bound check. */ 8253 if ((cur_agc_value >= 8254 IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) || 8255 (cur_agc_value == 0)) 8256 return -E1000_ERR_PHY; 8257 8258 agc_value += cur_agc_value; 8259 8260 /* Update minimal AGC value. */ 8261 if (min_agc_value > cur_agc_value) 8262 min_agc_value = cur_agc_value; 8263 } 8264 8265 /* Remove the minimal AGC result for length < 50m */ 8266 if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * 8267 em_igp_cable_length_50) { 8268 agc_value -= min_agc_value; 8269 8270 /* 8271 * Get the average length of the remaining 3 channels 8272 */ 8273 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1); 8274 } else { 8275 /* Get the average length of all the 4 channels. */ 8276 agc_value /= IGP01E1000_PHY_CHANNEL_NUM; 8277 } 8278 8279 /* Set the range of the calculated length. */ 8280 *min_length = ((em_igp_cable_length_table[agc_value] - 8281 IGP01E1000_AGC_RANGE) > 0) ? 8282 (em_igp_cable_length_table[agc_value] - 8283 IGP01E1000_AGC_RANGE) : 0; 8284 *max_length = em_igp_cable_length_table[agc_value] + 8285 IGP01E1000_AGC_RANGE; 8286 } else if (hw->phy_type == em_phy_igp_2 || 8287 hw->phy_type == em_phy_igp_3) { 8288 uint16_t cur_agc_index, max_agc_index = 0; 8289 uint16_t min_agc_index = IGP02E1000_AGC_LENGTH_TABLE_SIZE - 1; 8290 uint16_t agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = 8291 {IGP02E1000_PHY_AGC_A, IGP02E1000_PHY_AGC_B, 8292 IGP02E1000_PHY_AGC_C, IGP02E1000_PHY_AGC_D}; 8293 /* Read the AGC registers for all channels */ 8294 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { 8295 ret_val = em_read_phy_reg(hw, agc_reg_array[i], 8296 &phy_data); 8297 if (ret_val) 8298 return ret_val; 8299 /* 8300 * Getting bits 15:9, which represent the combination 8301 * of course and fine gain values. The result is a 8302 * number that can be put into the lookup table to 8303 * obtain the approximate cable length. 8304 */ 8305 cur_agc_index = (phy_data >> 8306 IGP02E1000_AGC_LENGTH_SHIFT) & 8307 IGP02E1000_AGC_LENGTH_MASK; 8308 8309 /* Array index bound check. */ 8310 if ((cur_agc_index >= IGP02E1000_AGC_LENGTH_TABLE_SIZE) 8311 || (cur_agc_index == 0)) 8312 return -E1000_ERR_PHY; 8313 8314 /* Remove min & max AGC values from calculation. */ 8315 if (em_igp_2_cable_length_table[min_agc_index] > 8316 em_igp_2_cable_length_table[cur_agc_index]) 8317 min_agc_index = cur_agc_index; 8318 if (em_igp_2_cable_length_table[max_agc_index] < 8319 em_igp_2_cable_length_table[cur_agc_index]) 8320 max_agc_index = cur_agc_index; 8321 8322 agc_value += em_igp_2_cable_length_table 8323 [cur_agc_index]; 8324 } 8325 8326 agc_value -= (em_igp_2_cable_length_table[min_agc_index] + 8327 em_igp_2_cable_length_table[max_agc_index]); 8328 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); 8329 /* 8330 * Calculate cable length with the error range of +/- 10 8331 * meters. 8332 */ 8333 *min_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ? 8334 (agc_value - IGP02E1000_AGC_RANGE) : 0; 8335 *max_length = agc_value + IGP02E1000_AGC_RANGE; 8336 } 8337 return E1000_SUCCESS; 8338 } 8339 8340 /****************************************************************************** 8341 * Check if Downshift occured 8342 * 8343 * hw - Struct containing variables accessed by shared code 8344 * downshift - output parameter : 0 - No Downshift ocured. 8345 * 1 - Downshift ocured. 8346 * 8347 * returns: - E1000_ERR_XXX 8348 * E1000_SUCCESS 8349 * 8350 * For phy's older then IGP, this function reads the Downshift bit in the Phy 8351 * Specific Status register. For IGP phy's, it reads the Downgrade bit in the 8352 * Link Health register. In IGP this bit is latched high, so the driver must 8353 * read it immediately after link is established. 8354 *****************************************************************************/ 8355 STATIC int32_t 8356 em_check_downshift(struct em_hw *hw) 8357 { 8358 int32_t ret_val; 8359 uint16_t phy_data; 8360 DEBUGFUNC("em_check_downshift"); 8361 8362 if (hw->phy_type == em_phy_igp || 8363 hw->phy_type == em_phy_igp_3 || 8364 hw->phy_type == em_phy_igp_2) { 8365 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH, 8366 &phy_data); 8367 if (ret_val) 8368 return ret_val; 8369 8370 hw->speed_downgraded = (phy_data & 8371 IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0; 8372 } else if ((hw->phy_type == em_phy_m88) || 8373 (hw->phy_type == em_phy_gg82563) || 8374 (hw->phy_type == em_phy_oem) || 8375 (hw->phy_type == em_phy_82578)) { 8376 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, 8377 &phy_data); 8378 if (ret_val) 8379 return ret_val; 8380 8381 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >> 8382 M88E1000_PSSR_DOWNSHIFT_SHIFT; 8383 } else if (hw->phy_type == em_phy_ife) { 8384 /* em_phy_ife supports 10/100 speed only */ 8385 hw->speed_downgraded = FALSE; 8386 } 8387 return E1000_SUCCESS; 8388 } 8389 8390 /***************************************************************************** 8391 * 8392 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a 8393 * gigabit link is achieved to improve link quality. 8394 * 8395 * hw: Struct containing variables accessed by shared code 8396 * 8397 * returns: - E1000_ERR_PHY if fail to read/write the PHY 8398 * E1000_SUCCESS at any other case. 8399 * 8400 ****************************************************************************/ 8401 STATIC int32_t 8402 em_config_dsp_after_link_change(struct em_hw *hw, boolean_t link_up) 8403 { 8404 int32_t ret_val; 8405 uint16_t phy_data, phy_saved_data, speed, duplex, i; 8406 uint16_t dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = 8407 {IGP01E1000_PHY_AGC_PARAM_A, IGP01E1000_PHY_AGC_PARAM_B, 8408 IGP01E1000_PHY_AGC_PARAM_C, IGP01E1000_PHY_AGC_PARAM_D}; 8409 uint16_t min_length, max_length; 8410 DEBUGFUNC("em_config_dsp_after_link_change"); 8411 8412 if (hw->phy_type != em_phy_igp) 8413 return E1000_SUCCESS; 8414 8415 if (link_up) { 8416 ret_val = em_get_speed_and_duplex(hw, &speed, &duplex); 8417 if (ret_val) { 8418 DEBUGOUT("Error getting link speed and duplex\n"); 8419 return ret_val; 8420 } 8421 if (speed == SPEED_1000) { 8422 8423 ret_val = em_get_cable_length(hw, &min_length, &max_length); 8424 if (ret_val) 8425 return ret_val; 8426 8427 if ((hw->dsp_config_state == em_dsp_config_enabled) && 8428 min_length >= em_igp_cable_length_50) { 8429 8430 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; 8431 i++) { 8432 ret_val = em_read_phy_reg(hw, 8433 dsp_reg_array[i], &phy_data); 8434 if (ret_val) 8435 return ret_val; 8436 8437 phy_data &= 8438 ~IGP01E1000_PHY_EDAC_MU_INDEX; 8439 8440 ret_val = em_write_phy_reg(hw, 8441 dsp_reg_array[i], phy_data); 8442 if (ret_val) 8443 return ret_val; 8444 } 8445 hw->dsp_config_state = em_dsp_config_activated; 8446 } 8447 if ((hw->ffe_config_state == em_ffe_config_enabled) && 8448 (min_length < em_igp_cable_length_50)) { 8449 8450 uint16_t ffe_idle_err_timeout = 8451 FFE_IDLE_ERR_COUNT_TIMEOUT_20; 8452 uint32_t idle_errs = 0; 8453 /* clear previous idle error counts */ 8454 ret_val = em_read_phy_reg(hw, PHY_1000T_STATUS, 8455 &phy_data); 8456 if (ret_val) 8457 return ret_val; 8458 8459 for (i = 0; i < ffe_idle_err_timeout; i++) { 8460 usec_delay(1000); 8461 ret_val = em_read_phy_reg(hw, 8462 PHY_1000T_STATUS, &phy_data); 8463 if (ret_val) 8464 return ret_val; 8465 8466 idle_errs += (phy_data & 8467 SR_1000T_IDLE_ERROR_CNT); 8468 if (idle_errs > 8469 SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) { 8470 hw->ffe_config_state = 8471 em_ffe_config_active; 8472 8473 ret_val = em_write_phy_reg(hw, 8474 IGP01E1000_PHY_DSP_FFE, 8475 IGP01E1000_PHY_DSP_FFE_CM_CP); 8476 if (ret_val) 8477 return ret_val; 8478 break; 8479 } 8480 if (idle_errs) 8481 ffe_idle_err_timeout = 8482 FFE_IDLE_ERR_COUNT_TIMEOUT_100; 8483 } 8484 } 8485 } 8486 } else { 8487 if (hw->dsp_config_state == em_dsp_config_activated) { 8488 /* 8489 * Save off the current value of register 0x2F5B to 8490 * be restored at the end of the routines. 8491 */ 8492 ret_val = em_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 8493 8494 if (ret_val) 8495 return ret_val; 8496 8497 /* Disable the PHY transmitter */ 8498 ret_val = em_write_phy_reg(hw, 0x2F5B, 0x0003); 8499 8500 if (ret_val) 8501 return ret_val; 8502 8503 msec_delay_irq(20); 8504 8505 ret_val = em_write_phy_reg(hw, 0x0000, 8506 IGP01E1000_IEEE_FORCE_GIGA); 8507 if (ret_val) 8508 return ret_val; 8509 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 8510 ret_val = em_read_phy_reg(hw, dsp_reg_array[i], 8511 &phy_data); 8512 if (ret_val) 8513 return ret_val; 8514 8515 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; 8516 phy_data |= 8517 IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS; 8518 8519 ret_val = em_write_phy_reg(hw, 8520 dsp_reg_array[i], phy_data); 8521 if (ret_val) 8522 return ret_val; 8523 } 8524 8525 ret_val = em_write_phy_reg(hw, 0x0000, 8526 IGP01E1000_IEEE_RESTART_AUTONEG); 8527 if (ret_val) 8528 return ret_val; 8529 8530 msec_delay_irq(20); 8531 8532 /* Now enable the transmitter */ 8533 ret_val = em_write_phy_reg(hw, 0x2F5B, phy_saved_data); 8534 8535 if (ret_val) 8536 return ret_val; 8537 8538 hw->dsp_config_state = em_dsp_config_enabled; 8539 } 8540 if (hw->ffe_config_state == em_ffe_config_active) { 8541 /* 8542 * Save off the current value of register 0x2F5B to 8543 * be restored at the end of the routines. 8544 */ 8545 ret_val = em_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 8546 8547 if (ret_val) 8548 return ret_val; 8549 8550 /* Disable the PHY transmitter */ 8551 ret_val = em_write_phy_reg(hw, 0x2F5B, 0x0003); 8552 8553 if (ret_val) 8554 return ret_val; 8555 8556 msec_delay_irq(20); 8557 8558 ret_val = em_write_phy_reg(hw, 0x0000, 8559 IGP01E1000_IEEE_FORCE_GIGA); 8560 if (ret_val) 8561 return ret_val; 8562 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE, 8563 IGP01E1000_PHY_DSP_FFE_DEFAULT); 8564 if (ret_val) 8565 return ret_val; 8566 8567 ret_val = em_write_phy_reg(hw, 0x0000, 8568 IGP01E1000_IEEE_RESTART_AUTONEG); 8569 if (ret_val) 8570 return ret_val; 8571 8572 msec_delay_irq(20); 8573 8574 /* Now enable the transmitter */ 8575 ret_val = em_write_phy_reg(hw, 0x2F5B, phy_saved_data); 8576 8577 if (ret_val) 8578 return ret_val; 8579 8580 hw->ffe_config_state = em_ffe_config_enabled; 8581 } 8582 } 8583 return E1000_SUCCESS; 8584 } 8585 8586 /***************************************************************************** 8587 * Set PHY to class A mode 8588 * Assumes the following operations will follow to enable the new class mode. 8589 * 1. Do a PHY soft reset 8590 * 2. Restart auto-negotiation or force link. 8591 * 8592 * hw - Struct containing variables accessed by shared code 8593 ****************************************************************************/ 8594 static int32_t 8595 em_set_phy_mode(struct em_hw *hw) 8596 { 8597 int32_t ret_val; 8598 uint16_t eeprom_data; 8599 DEBUGFUNC("em_set_phy_mode"); 8600 8601 if ((hw->mac_type == em_82545_rev_3) && 8602 (hw->media_type == em_media_type_copper)) { 8603 ret_val = em_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, 8604 &eeprom_data); 8605 if (ret_val) { 8606 return ret_val; 8607 } 8608 if ((eeprom_data != EEPROM_RESERVED_WORD) && 8609 (eeprom_data & EEPROM_PHY_CLASS_A)) { 8610 ret_val = em_write_phy_reg(hw, 8611 M88E1000_PHY_PAGE_SELECT, 0x000B); 8612 if (ret_val) 8613 return ret_val; 8614 ret_val = em_write_phy_reg(hw, 8615 M88E1000_PHY_GEN_CONTROL, 0x8104); 8616 if (ret_val) 8617 return ret_val; 8618 8619 hw->phy_reset_disable = FALSE; 8620 } 8621 } 8622 return E1000_SUCCESS; 8623 } 8624 8625 /***************************************************************************** 8626 * 8627 * This function sets the lplu state according to the active flag. When 8628 * activating lplu this function also disables smart speed and vise versa. 8629 * lplu will not be activated unless the device autonegotiation advertisement 8630 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. 8631 * hw: Struct containing variables accessed by shared code 8632 * active - true to enable lplu false to disable lplu. 8633 * 8634 * returns: - E1000_ERR_PHY if fail to read/write the PHY 8635 * E1000_SUCCESS at any other case. 8636 * 8637 ****************************************************************************/ 8638 STATIC int32_t 8639 em_set_d3_lplu_state(struct em_hw *hw, boolean_t active) 8640 { 8641 uint32_t phy_ctrl = 0; 8642 int32_t ret_val; 8643 uint16_t phy_data; 8644 DEBUGFUNC("em_set_d3_lplu_state"); 8645 8646 if (hw->phy_type != em_phy_igp && hw->phy_type != em_phy_igp_2 8647 && hw->phy_type != em_phy_igp_3) 8648 return E1000_SUCCESS; 8649 /* 8650 * During driver activity LPLU should not be used or it will attain 8651 * link from the lowest speeds starting from 10Mbps. The capability 8652 * is used for Dx transitions and states 8653 */ 8654 if (hw->mac_type == em_82541_rev_2 || hw->mac_type == em_82547_rev_2) { 8655 ret_val = em_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data); 8656 if (ret_val) 8657 return ret_val; 8658 } else if (IS_ICH8(hw->mac_type)) { 8659 /* 8660 * MAC writes into PHY register based on the state transition 8661 * and start auto-negotiation. SW driver can overwrite the 8662 * settings in CSR PHY power control E1000_PHY_CTRL register. 8663 */ 8664 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); 8665 } else { 8666 ret_val = em_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, 8667 &phy_data); 8668 if (ret_val) 8669 return ret_val; 8670 } 8671 8672 if (!active) { 8673 if (hw->mac_type == em_82541_rev_2 || 8674 hw->mac_type == em_82547_rev_2) { 8675 phy_data &= ~IGP01E1000_GMII_FLEX_SPD; 8676 ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO, 8677 phy_data); 8678 if (ret_val) 8679 return ret_val; 8680 } else { 8681 if (IS_ICH8(hw->mac_type)) { 8682 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; 8683 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 8684 } else { 8685 phy_data &= ~IGP02E1000_PM_D3_LPLU; 8686 ret_val = em_write_phy_reg(hw, 8687 IGP02E1000_PHY_POWER_MGMT, phy_data); 8688 if (ret_val) 8689 return ret_val; 8690 } 8691 } 8692 /* 8693 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 8694 * during Dx states where the power conservation is most 8695 * important. During driver activity we should enable 8696 * SmartSpeed, so performance is maintained. 8697 */ 8698 if (hw->smart_speed == em_smart_speed_on) { 8699 ret_val = em_read_phy_reg(hw, 8700 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 8701 if (ret_val) 8702 return ret_val; 8703 8704 phy_data |= IGP01E1000_PSCFR_SMART_SPEED; 8705 ret_val = em_write_phy_reg(hw, 8706 IGP01E1000_PHY_PORT_CONFIG, phy_data); 8707 if (ret_val) 8708 return ret_val; 8709 } else if (hw->smart_speed == em_smart_speed_off) { 8710 ret_val = em_read_phy_reg(hw, 8711 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 8712 if (ret_val) 8713 return ret_val; 8714 8715 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 8716 ret_val = em_write_phy_reg(hw, 8717 IGP01E1000_PHY_PORT_CONFIG, phy_data); 8718 if (ret_val) 8719 return ret_val; 8720 } 8721 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) 8722 || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) || 8723 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) { 8724 8725 if (hw->mac_type == em_82541_rev_2 || 8726 hw->mac_type == em_82547_rev_2) { 8727 phy_data |= IGP01E1000_GMII_FLEX_SPD; 8728 ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO, 8729 phy_data); 8730 if (ret_val) 8731 return ret_val; 8732 } else { 8733 if (IS_ICH8(hw->mac_type)) { 8734 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; 8735 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 8736 } else { 8737 phy_data |= IGP02E1000_PM_D3_LPLU; 8738 ret_val = em_write_phy_reg(hw, 8739 IGP02E1000_PHY_POWER_MGMT, phy_data); 8740 if (ret_val) 8741 return ret_val; 8742 } 8743 } 8744 8745 /* When LPLU is enabled we should disable SmartSpeed */ 8746 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 8747 &phy_data); 8748 if (ret_val) 8749 return ret_val; 8750 8751 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 8752 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 8753 phy_data); 8754 if (ret_val) 8755 return ret_val; 8756 8757 } 8758 return E1000_SUCCESS; 8759 } 8760 8761 /***************************************************************************** 8762 * 8763 * This function sets the lplu d0 state according to the active flag. When 8764 * activating lplu this function also disables smart speed and vise versa. 8765 * lplu will not be activated unless the device autonegotiation advertisement 8766 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. 8767 * hw: Struct containing variables accessed by shared code 8768 * active - true to enable lplu false to disable lplu. 8769 * 8770 * returns: - E1000_ERR_PHY if fail to read/write the PHY 8771 * E1000_SUCCESS at any other case. 8772 * 8773 ****************************************************************************/ 8774 STATIC int32_t 8775 em_set_d0_lplu_state(struct em_hw *hw, boolean_t active) 8776 { 8777 uint32_t phy_ctrl = 0; 8778 int32_t ret_val; 8779 uint16_t phy_data; 8780 DEBUGFUNC("em_set_d0_lplu_state"); 8781 8782 if (hw->mac_type <= em_82547_rev_2) 8783 return E1000_SUCCESS; 8784 8785 if (IS_ICH8(hw->mac_type)) { 8786 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); 8787 } else { 8788 ret_val = em_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, 8789 &phy_data); 8790 if (ret_val) 8791 return ret_val; 8792 } 8793 8794 if (!active) { 8795 if (IS_ICH8(hw->mac_type)) { 8796 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; 8797 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 8798 } else { 8799 phy_data &= ~IGP02E1000_PM_D0_LPLU; 8800 ret_val = em_write_phy_reg(hw, 8801 IGP02E1000_PHY_POWER_MGMT, phy_data); 8802 if (ret_val) 8803 return ret_val; 8804 } 8805 /* 8806 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 8807 * during Dx states where the power conservation is most 8808 * important. During driver activity we should enable 8809 * SmartSpeed, so performance is maintained. 8810 */ 8811 if (hw->smart_speed == em_smart_speed_on) { 8812 ret_val = em_read_phy_reg(hw, 8813 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 8814 if (ret_val) 8815 return ret_val; 8816 8817 phy_data |= IGP01E1000_PSCFR_SMART_SPEED; 8818 ret_val = em_write_phy_reg(hw, 8819 IGP01E1000_PHY_PORT_CONFIG, phy_data); 8820 if (ret_val) 8821 return ret_val; 8822 } else if (hw->smart_speed == em_smart_speed_off) { 8823 ret_val = em_read_phy_reg(hw, 8824 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 8825 if (ret_val) 8826 return ret_val; 8827 8828 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 8829 ret_val = em_write_phy_reg(hw, 8830 IGP01E1000_PHY_PORT_CONFIG, phy_data); 8831 if (ret_val) 8832 return ret_val; 8833 } 8834 } else { 8835 if (IS_ICH8(hw->mac_type)) { 8836 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; 8837 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 8838 } else { 8839 phy_data |= IGP02E1000_PM_D0_LPLU; 8840 ret_val = em_write_phy_reg(hw, 8841 IGP02E1000_PHY_POWER_MGMT, phy_data); 8842 if (ret_val) 8843 return ret_val; 8844 } 8845 8846 /* When LPLU is enabled we should disable SmartSpeed */ 8847 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 8848 &phy_data); 8849 if (ret_val) 8850 return ret_val; 8851 8852 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 8853 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 8854 phy_data); 8855 if (ret_val) 8856 return ret_val; 8857 8858 } 8859 return E1000_SUCCESS; 8860 } 8861 8862 /*************************************************************************** 8863 * Set Low Power Link Up state 8864 * 8865 * Sets the LPLU state according to the active flag. For PCH, if OEM write 8866 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set 8867 * the phy speed. This function will manually set the LPLU bit and restart 8868 * auto-neg as hw would do. D3 and D0 LPLU will call the same function 8869 * since it configures the same bit. 8870 ***************************************************************************/ 8871 int32_t 8872 em_set_lplu_state_pchlan(struct em_hw *hw, boolean_t active) 8873 { 8874 int32_t ret_val = E1000_SUCCESS; 8875 uint16_t oem_reg; 8876 8877 DEBUGFUNC("e1000_set_lplu_state_pchlan"); 8878 8879 ret_val = em_read_phy_reg(hw, HV_OEM_BITS, &oem_reg); 8880 if (ret_val) 8881 goto out; 8882 8883 if (active) 8884 oem_reg |= HV_OEM_BITS_LPLU; 8885 else 8886 oem_reg &= ~HV_OEM_BITS_LPLU; 8887 8888 oem_reg |= HV_OEM_BITS_RESTART_AN; 8889 ret_val = em_write_phy_reg(hw, HV_OEM_BITS, oem_reg); 8890 8891 out: 8892 return ret_val; 8893 } 8894 8895 /****************************************************************************** 8896 * Change VCO speed register to improve Bit Error Rate performance of SERDES. 8897 * 8898 * hw - Struct containing variables accessed by shared code 8899 *****************************************************************************/ 8900 static int32_t 8901 em_set_vco_speed(struct em_hw *hw) 8902 { 8903 int32_t ret_val; 8904 uint16_t default_page = 0; 8905 uint16_t phy_data; 8906 DEBUGFUNC("em_set_vco_speed"); 8907 8908 switch (hw->mac_type) { 8909 case em_82545_rev_3: 8910 case em_82546_rev_3: 8911 break; 8912 default: 8913 return E1000_SUCCESS; 8914 } 8915 8916 /* Set PHY register 30, page 5, bit 8 to 0 */ 8917 8918 ret_val = em_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page); 8919 if (ret_val) 8920 return ret_val; 8921 8922 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005); 8923 if (ret_val) 8924 return ret_val; 8925 8926 ret_val = em_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); 8927 if (ret_val) 8928 return ret_val; 8929 8930 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8; 8931 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); 8932 if (ret_val) 8933 return ret_val; 8934 8935 /* Set PHY register 30, page 4, bit 11 to 1 */ 8936 8937 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004); 8938 if (ret_val) 8939 return ret_val; 8940 8941 ret_val = em_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); 8942 if (ret_val) 8943 return ret_val; 8944 8945 phy_data |= M88E1000_PHY_VCO_REG_BIT11; 8946 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); 8947 if (ret_val) 8948 return ret_val; 8949 8950 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page); 8951 if (ret_val) 8952 return ret_val; 8953 8954 return E1000_SUCCESS; 8955 } 8956 8957 /***************************************************************************** 8958 * This function reads the cookie from ARC ram. 8959 * 8960 * returns: - E1000_SUCCESS . 8961 ****************************************************************************/ 8962 STATIC int32_t 8963 em_host_if_read_cookie(struct em_hw *hw, uint8_t *buffer) 8964 { 8965 uint8_t i; 8966 uint32_t offset = E1000_MNG_DHCP_COOKIE_OFFSET; 8967 uint8_t length = E1000_MNG_DHCP_COOKIE_LENGTH; 8968 length = (length >> 2); 8969 offset = (offset >> 2); 8970 8971 for (i = 0; i < length; i++) { 8972 *((uint32_t *) buffer + i) = 8973 E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i); 8974 } 8975 return E1000_SUCCESS; 8976 } 8977 8978 /***************************************************************************** 8979 * This function checks whether the HOST IF is enabled for command operaton 8980 * and also checks whether the previous command is completed. 8981 * It busy waits in case of previous command is not completed. 8982 * 8983 * returns: - E1000_ERR_HOST_INTERFACE_COMMAND in case if is not ready or 8984 * timeout 8985 * - E1000_SUCCESS for success. 8986 ****************************************************************************/ 8987 STATIC int32_t 8988 em_mng_enable_host_if(struct em_hw *hw) 8989 { 8990 uint32_t hicr; 8991 uint8_t i; 8992 /* Check that the host interface is enabled. */ 8993 hicr = E1000_READ_REG(hw, HICR); 8994 if ((hicr & E1000_HICR_EN) == 0) { 8995 DEBUGOUT("E1000_HOST_EN bit disabled.\n"); 8996 return -E1000_ERR_HOST_INTERFACE_COMMAND; 8997 } 8998 /* check the previous command is completed */ 8999 for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) { 9000 hicr = E1000_READ_REG(hw, HICR); 9001 if (!(hicr & E1000_HICR_C)) 9002 break; 9003 msec_delay_irq(1); 9004 } 9005 9006 if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) { 9007 DEBUGOUT("Previous command timeout failed .\n"); 9008 return -E1000_ERR_HOST_INTERFACE_COMMAND; 9009 } 9010 return E1000_SUCCESS; 9011 } 9012 9013 /***************************************************************************** 9014 * This function checks the mode of the firmware. 9015 * 9016 * returns - TRUE when the mode is IAMT or FALSE. 9017 ****************************************************************************/ 9018 boolean_t 9019 em_check_mng_mode(struct em_hw *hw) 9020 { 9021 uint32_t fwsm; 9022 fwsm = E1000_READ_REG(hw, FWSM); 9023 9024 if (IS_ICH8(hw->mac_type)) { 9025 if ((fwsm & E1000_FWSM_MODE_MASK) == 9026 (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) 9027 return TRUE; 9028 } else if ((fwsm & E1000_FWSM_MODE_MASK) == 9029 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) 9030 return TRUE; 9031 9032 return FALSE; 9033 } 9034 9035 /***************************************************************************** 9036 * This function calculates the checksum. 9037 * 9038 * returns - checksum of buffer contents. 9039 ****************************************************************************/ 9040 STATIC uint8_t 9041 em_calculate_mng_checksum(char *buffer, uint32_t length) 9042 { 9043 uint8_t sum = 0; 9044 uint32_t i; 9045 if (!buffer) 9046 return 0; 9047 9048 for (i = 0; i < length; i++) 9049 sum += buffer[i]; 9050 9051 return (uint8_t) (0 - sum); 9052 } 9053 9054 /***************************************************************************** 9055 * This function checks whether tx pkt filtering needs to be enabled or not. 9056 * 9057 * returns - TRUE for packet filtering or FALSE. 9058 ****************************************************************************/ 9059 boolean_t 9060 em_enable_tx_pkt_filtering(struct em_hw *hw) 9061 { 9062 /* called in init as well as watchdog timer functions */ 9063 int32_t ret_val, checksum; 9064 boolean_t tx_filter = FALSE; 9065 struct em_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie); 9066 uint8_t *buffer = (uint8_t *) & (hw->mng_cookie); 9067 if (em_check_mng_mode(hw)) { 9068 ret_val = em_mng_enable_host_if(hw); 9069 if (ret_val == E1000_SUCCESS) { 9070 ret_val = em_host_if_read_cookie(hw, buffer); 9071 if (ret_val == E1000_SUCCESS) { 9072 checksum = hdr->checksum; 9073 hdr->checksum = 0; 9074 if ((hdr->signature == E1000_IAMT_SIGNATURE) && 9075 checksum == em_calculate_mng_checksum( 9076 (char *) buffer, 9077 E1000_MNG_DHCP_COOKIE_LENGTH)) { 9078 if (hdr->status & 9079 E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT) 9080 tx_filter = TRUE; 9081 } else 9082 tx_filter = TRUE; 9083 } else 9084 tx_filter = TRUE; 9085 } 9086 } 9087 hw->tx_pkt_filtering = tx_filter; 9088 return tx_filter; 9089 } 9090 9091 static int32_t 9092 em_polarity_reversal_workaround(struct em_hw *hw) 9093 { 9094 int32_t ret_val; 9095 uint16_t mii_status_reg; 9096 uint16_t i; 9097 /* Polarity reversal workaround for forced 10F/10H links. */ 9098 9099 /* Disable the transmitter on the PHY */ 9100 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 9101 if (ret_val) 9102 return ret_val; 9103 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF); 9104 if (ret_val) 9105 return ret_val; 9106 9107 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 9108 if (ret_val) 9109 return ret_val; 9110 9111 /* This loop will early-out if the NO link condition has been met. */ 9112 for (i = PHY_FORCE_TIME; i > 0; i--) { 9113 /* 9114 * Read the MII Status Register and wait for Link Status bit 9115 * to be clear. 9116 */ 9117 9118 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 9119 if (ret_val) 9120 return ret_val; 9121 9122 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 9123 if (ret_val) 9124 return ret_val; 9125 9126 if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) 9127 break; 9128 msec_delay_irq(100); 9129 } 9130 9131 /* Recommended delay time after link has been lost */ 9132 msec_delay_irq(1000); 9133 9134 /* Now we will re-enable the transmitter on the PHY */ 9135 9136 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 9137 if (ret_val) 9138 return ret_val; 9139 msec_delay_irq(50); 9140 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0); 9141 if (ret_val) 9142 return ret_val; 9143 msec_delay_irq(50); 9144 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00); 9145 if (ret_val) 9146 return ret_val; 9147 msec_delay_irq(50); 9148 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000); 9149 if (ret_val) 9150 return ret_val; 9151 9152 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 9153 if (ret_val) 9154 return ret_val; 9155 9156 /* This loop will early-out if the link condition has been met. */ 9157 for (i = PHY_FORCE_TIME; i > 0; i--) { 9158 /* 9159 * Read the MII Status Register and wait for Link Status bit 9160 * to be set. 9161 */ 9162 9163 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 9164 if (ret_val) 9165 return ret_val; 9166 9167 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 9168 if (ret_val) 9169 return ret_val; 9170 9171 if (mii_status_reg & MII_SR_LINK_STATUS) 9172 break; 9173 msec_delay_irq(100); 9174 } 9175 return E1000_SUCCESS; 9176 } 9177 9178 /****************************************************************************** 9179 * 9180 * Disables PCI-Express master access. 9181 * 9182 * hw: Struct containing variables accessed by shared code 9183 * 9184 * returns: - none. 9185 * 9186 *****************************************************************************/ 9187 STATIC void 9188 em_set_pci_express_master_disable(struct em_hw *hw) 9189 { 9190 uint32_t ctrl; 9191 DEBUGFUNC("em_set_pci_express_master_disable"); 9192 9193 if (hw->bus_type != em_bus_type_pci_express) 9194 return; 9195 9196 ctrl = E1000_READ_REG(hw, CTRL); 9197 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; 9198 E1000_WRITE_REG(hw, CTRL, ctrl); 9199 } 9200 9201 /****************************************************************************** 9202 * 9203 * Disables PCI-Express master access and verifies there are no pending 9204 * requests 9205 * 9206 * hw: Struct containing variables accessed by shared code 9207 * 9208 * returns: - E1000_ERR_MASTER_REQUESTS_PENDING if master disable bit hasn't 9209 * caused the master requests to be disabled. 9210 * E1000_SUCCESS master requests disabled. 9211 * 9212 ******************************************************************************/ 9213 int32_t 9214 em_disable_pciex_master(struct em_hw *hw) 9215 { 9216 int32_t timeout = MASTER_DISABLE_TIMEOUT; /* 80ms */ 9217 DEBUGFUNC("em_disable_pciex_master"); 9218 9219 if (hw->bus_type != em_bus_type_pci_express) 9220 return E1000_SUCCESS; 9221 9222 em_set_pci_express_master_disable(hw); 9223 9224 while (timeout) { 9225 if (!(E1000_READ_REG(hw, STATUS) & 9226 E1000_STATUS_GIO_MASTER_ENABLE)) 9227 break; 9228 else 9229 usec_delay(100); 9230 timeout--; 9231 } 9232 9233 if (!timeout) { 9234 DEBUGOUT("Master requests are pending.\n"); 9235 return -E1000_ERR_MASTER_REQUESTS_PENDING; 9236 } 9237 return E1000_SUCCESS; 9238 } 9239 9240 /****************************************************************************** 9241 * 9242 * Check for EEPROM Auto Read bit done. 9243 * 9244 * hw: Struct containing variables accessed by shared code 9245 * 9246 * returns: - E1000_ERR_RESET if fail to reset MAC 9247 * E1000_SUCCESS at any other case. 9248 * 9249 ******************************************************************************/ 9250 STATIC int32_t 9251 em_get_auto_rd_done(struct em_hw *hw) 9252 { 9253 int32_t timeout = AUTO_READ_DONE_TIMEOUT; 9254 DEBUGFUNC("em_get_auto_rd_done"); 9255 9256 switch (hw->mac_type) { 9257 default: 9258 msec_delay(5); 9259 break; 9260 case em_82571: 9261 case em_82572: 9262 case em_82573: 9263 case em_82574: 9264 case em_82575: 9265 case em_82576: 9266 case em_82580: 9267 case em_80003es2lan: 9268 case em_i210: 9269 case em_i350: 9270 case em_ich8lan: 9271 case em_ich9lan: 9272 case em_ich10lan: 9273 case em_pchlan: 9274 case em_pch2lan: 9275 case em_pch_lpt: 9276 case em_pch_spt: 9277 case em_pch_cnp: 9278 while (timeout) { 9279 if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD) 9280 break; 9281 else 9282 msec_delay(1); 9283 timeout--; 9284 } 9285 9286 if (!timeout) { 9287 DEBUGOUT("Auto read by HW from EEPROM has not" 9288 " completed.\n"); 9289 return -E1000_ERR_RESET; 9290 } 9291 break; 9292 } 9293 /* 9294 * PHY configuration from NVM just starts after EECD_AUTO_RD sets to 9295 * high. Need to wait for PHY configuration completion before 9296 * accessing NVM and PHY. 9297 */ 9298 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) 9299 msec_delay(25); 9300 9301 return E1000_SUCCESS; 9302 } 9303 9304 /*************************************************************************** 9305 * Checks if the PHY configuration is done 9306 * 9307 * hw: Struct containing variables accessed by shared code 9308 * 9309 * returns: - E1000_ERR_RESET if fail to reset MAC 9310 * E1000_SUCCESS at any other case. 9311 * 9312 ***************************************************************************/ 9313 STATIC int32_t 9314 em_get_phy_cfg_done(struct em_hw *hw) 9315 { 9316 int32_t timeout = PHY_CFG_TIMEOUT; 9317 uint32_t cfg_mask = E1000_NVM_CFG_DONE_PORT_0; 9318 DEBUGFUNC("em_get_phy_cfg_done"); 9319 9320 switch (hw->mac_type) { 9321 default: 9322 msec_delay_irq(10); 9323 break; 9324 case em_80003es2lan: 9325 case em_82575: 9326 case em_82576: 9327 case em_82580: 9328 case em_i350: 9329 switch (hw->bus_func) { 9330 case 1: 9331 cfg_mask = E1000_NVM_CFG_DONE_PORT_1; 9332 break; 9333 case 2: 9334 cfg_mask = E1000_NVM_CFG_DONE_PORT_2; 9335 break; 9336 case 3: 9337 cfg_mask = E1000_NVM_CFG_DONE_PORT_3; 9338 break; 9339 } 9340 /* FALLTHROUGH */ 9341 case em_82571: 9342 case em_82572: 9343 while (timeout) { 9344 if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask) 9345 break; 9346 else 9347 msec_delay(1); 9348 timeout--; 9349 } 9350 if (!timeout) { 9351 DEBUGOUT("MNG configuration cycle has not completed." 9352 "\n"); 9353 } 9354 break; 9355 } 9356 9357 return E1000_SUCCESS; 9358 } 9359 9360 /*************************************************************************** 9361 * 9362 * Using the combination of SMBI and SWESMBI semaphore bits when resetting 9363 * adapter or Eeprom access. 9364 * 9365 * hw: Struct containing variables accessed by shared code 9366 * 9367 * returns: - E1000_ERR_EEPROM if fail to access EEPROM. 9368 * E1000_SUCCESS at any other case. 9369 * 9370 ***************************************************************************/ 9371 STATIC int32_t 9372 em_get_hw_eeprom_semaphore(struct em_hw *hw) 9373 { 9374 int32_t timeout; 9375 uint32_t swsm; 9376 DEBUGFUNC("em_get_hw_eeprom_semaphore"); 9377 9378 if (!hw->eeprom_semaphore_present) 9379 return E1000_SUCCESS; 9380 9381 if (hw->mac_type == em_80003es2lan) { 9382 /* Get the SW semaphore. */ 9383 if (em_get_software_semaphore(hw) != E1000_SUCCESS) 9384 return -E1000_ERR_EEPROM; 9385 } 9386 /* Get the FW semaphore. */ 9387 timeout = hw->eeprom.word_size + 1; 9388 while (timeout) { 9389 swsm = E1000_READ_REG(hw, SWSM); 9390 swsm |= E1000_SWSM_SWESMBI; 9391 E1000_WRITE_REG(hw, SWSM, swsm); 9392 /* if we managed to set the bit we got the semaphore. */ 9393 swsm = E1000_READ_REG(hw, SWSM); 9394 if (swsm & E1000_SWSM_SWESMBI) 9395 break; 9396 9397 usec_delay(50); 9398 timeout--; 9399 } 9400 9401 if (!timeout) { 9402 /* Release semaphores */ 9403 em_put_hw_eeprom_semaphore(hw); 9404 DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set." 9405 "\n"); 9406 return -E1000_ERR_EEPROM; 9407 } 9408 return E1000_SUCCESS; 9409 } 9410 9411 /*************************************************************************** 9412 * This function clears HW semaphore bits. 9413 * 9414 * hw: Struct containing variables accessed by shared code 9415 * 9416 * returns: - None. 9417 * 9418 ***************************************************************************/ 9419 STATIC void 9420 em_put_hw_eeprom_semaphore(struct em_hw *hw) 9421 { 9422 uint32_t swsm; 9423 DEBUGFUNC("em_put_hw_eeprom_semaphore"); 9424 9425 if (!hw->eeprom_semaphore_present) 9426 return; 9427 9428 swsm = E1000_READ_REG(hw, SWSM); 9429 if (hw->mac_type == em_80003es2lan) { 9430 /* Release both semaphores. */ 9431 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 9432 } else 9433 swsm &= ~(E1000_SWSM_SWESMBI); 9434 E1000_WRITE_REG(hw, SWSM, swsm); 9435 } 9436 9437 /*************************************************************************** 9438 * 9439 * Obtaining software semaphore bit (SMBI) before resetting PHY. 9440 * 9441 * hw: Struct containing variables accessed by shared code 9442 * 9443 * returns: - E1000_ERR_RESET if fail to obtain semaphore. 9444 * E1000_SUCCESS at any other case. 9445 * 9446 ***************************************************************************/ 9447 STATIC int32_t 9448 em_get_software_semaphore(struct em_hw *hw) 9449 { 9450 int32_t timeout = hw->eeprom.word_size + 1; 9451 uint32_t swsm; 9452 DEBUGFUNC("em_get_software_semaphore"); 9453 9454 if (hw->mac_type != em_80003es2lan) 9455 return E1000_SUCCESS; 9456 9457 while (timeout) { 9458 swsm = E1000_READ_REG(hw, SWSM); 9459 /* 9460 * If SMBI bit cleared, it is now set and we hold the 9461 * semaphore 9462 */ 9463 if (!(swsm & E1000_SWSM_SMBI)) 9464 break; 9465 msec_delay_irq(1); 9466 timeout--; 9467 } 9468 9469 if (!timeout) { 9470 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 9471 return -E1000_ERR_RESET; 9472 } 9473 return E1000_SUCCESS; 9474 } 9475 9476 /*************************************************************************** 9477 * 9478 * Release semaphore bit (SMBI). 9479 * 9480 * hw: Struct containing variables accessed by shared code 9481 * 9482 ***************************************************************************/ 9483 STATIC void 9484 em_release_software_semaphore(struct em_hw *hw) 9485 { 9486 uint32_t swsm; 9487 DEBUGFUNC("em_release_software_semaphore"); 9488 9489 if (hw->mac_type != em_80003es2lan) 9490 return; 9491 9492 swsm = E1000_READ_REG(hw, SWSM); 9493 /* Release the SW semaphores. */ 9494 swsm &= ~E1000_SWSM_SMBI; 9495 E1000_WRITE_REG(hw, SWSM, swsm); 9496 } 9497 9498 /****************************************************************************** 9499 * Checks if PHY reset is blocked due to SOL/IDER session, for example. 9500 * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to 9501 * the caller to figure out how to deal with it. 9502 * 9503 * hw - Struct containing variables accessed by shared code 9504 * 9505 * returns: - E1000_BLK_PHY_RESET 9506 * E1000_SUCCESS 9507 * 9508 *****************************************************************************/ 9509 int32_t 9510 em_check_phy_reset_block(struct em_hw *hw) 9511 { 9512 uint32_t manc = 0; 9513 uint32_t fwsm = 0; 9514 DEBUGFUNC("em_check_phy_reset_block\n"); 9515 9516 if (IS_ICH8(hw->mac_type)) { 9517 int i = 0; 9518 int blocked = 0; 9519 do { 9520 fwsm = E1000_READ_REG(hw, FWSM); 9521 if (!(fwsm & E1000_FWSM_RSPCIPHY)) { 9522 blocked = 1; 9523 msec_delay(10); 9524 continue; 9525 } 9526 blocked = 0; 9527 } while (blocked && (i++ < 30)); 9528 return blocked ? E1000_BLK_PHY_RESET : E1000_SUCCESS; 9529 } 9530 if (hw->mac_type > em_82547_rev_2) 9531 manc = E1000_READ_REG(hw, MANC); 9532 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? 9533 E1000_BLK_PHY_RESET : E1000_SUCCESS; 9534 } 9535 9536 /****************************************************************************** 9537 * Configure PCI-Ex no-snoop 9538 * 9539 * hw - Struct containing variables accessed by shared code. 9540 * no_snoop - Bitmap of no-snoop events. 9541 * 9542 * returns: E1000_SUCCESS 9543 * 9544 *****************************************************************************/ 9545 STATIC int32_t 9546 em_set_pci_ex_no_snoop(struct em_hw *hw, uint32_t no_snoop) 9547 { 9548 uint32_t gcr_reg = 0; 9549 DEBUGFUNC("em_set_pci_ex_no_snoop"); 9550 9551 if (hw->bus_type == em_bus_type_unknown) 9552 em_get_bus_info(hw); 9553 9554 if (hw->bus_type != em_bus_type_pci_express) 9555 return E1000_SUCCESS; 9556 9557 if (no_snoop) { 9558 gcr_reg = E1000_READ_REG(hw, GCR); 9559 gcr_reg &= ~(PCI_EX_NO_SNOOP_ALL); 9560 gcr_reg |= no_snoop; 9561 E1000_WRITE_REG(hw, GCR, gcr_reg); 9562 } 9563 if (IS_ICH8(hw->mac_type)) { 9564 uint32_t ctrl_ext; 9565 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 9566 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 9567 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 9568 } 9569 return E1000_SUCCESS; 9570 } 9571 9572 /*************************************************************************** 9573 * 9574 * Get software semaphore FLAG bit (SWFLAG). 9575 * SWFLAG is used to synchronize the access to all shared resource between 9576 * SW, FW and HW. 9577 * 9578 * hw: Struct containing variables accessed by shared code 9579 * 9580 ***************************************************************************/ 9581 STATIC int32_t 9582 em_get_software_flag(struct em_hw *hw) 9583 { 9584 int32_t timeout = PHY_CFG_TIMEOUT; 9585 uint32_t extcnf_ctrl; 9586 DEBUGFUNC("em_get_software_flag"); 9587 9588 if (IS_ICH8(hw->mac_type)) { 9589 if (hw->sw_flag) { 9590 hw->sw_flag++; 9591 return E1000_SUCCESS; 9592 } 9593 while (timeout) { 9594 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 9595 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)) 9596 break; 9597 msec_delay_irq(1); 9598 timeout--; 9599 } 9600 if (!timeout) { 9601 printf("%s: SW has already locked the resource?\n", 9602 __func__); 9603 return -E1000_ERR_CONFIG; 9604 } 9605 timeout = SW_FLAG_TIMEOUT; 9606 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; 9607 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); 9608 9609 while (timeout) { 9610 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 9611 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) 9612 break; 9613 msec_delay_irq(1); 9614 timeout--; 9615 } 9616 9617 if (!timeout) { 9618 printf("Failed to acquire the semaphore, FW or HW " 9619 "has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n", 9620 E1000_READ_REG(hw, FWSM), extcnf_ctrl); 9621 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 9622 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); 9623 return -E1000_ERR_CONFIG; 9624 } 9625 } 9626 hw->sw_flag++; 9627 return E1000_SUCCESS; 9628 } 9629 9630 /*************************************************************************** 9631 * 9632 * Release software semaphore FLAG bit (SWFLAG). 9633 * SWFLAG is used to synchronize the access to all shared resource between 9634 * SW, FW and HW. 9635 * 9636 * hw: Struct containing variables accessed by shared code 9637 * 9638 ***************************************************************************/ 9639 STATIC void 9640 em_release_software_flag(struct em_hw *hw) 9641 { 9642 uint32_t extcnf_ctrl; 9643 DEBUGFUNC("em_release_software_flag"); 9644 9645 if (IS_ICH8(hw->mac_type)) { 9646 KASSERT(hw->sw_flag > 0); 9647 if (--hw->sw_flag > 0) 9648 return; 9649 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 9650 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 9651 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); 9652 } 9653 return; 9654 } 9655 9656 /** 9657 * em_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1 9658 * @hw: pointer to the HW structure 9659 * @bank: pointer to the variable that returns the active bank 9660 * 9661 * Reads signature byte from the NVM using the flash access registers. 9662 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank. 9663 **/ 9664 int32_t 9665 em_valid_nvm_bank_detect_ich8lan(struct em_hw *hw, uint32_t *bank) 9666 { 9667 uint32_t eecd; 9668 uint32_t bank1_offset = hw->flash_bank_size * sizeof(uint16_t); 9669 uint32_t act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1; 9670 uint32_t nvm_dword = 0; 9671 uint8_t sig_byte = 0; 9672 int32_t ret_val; 9673 9674 DEBUGFUNC("em_valid_nvm_bank_detect_ich8lan"); 9675 9676 switch (hw->mac_type) { 9677 case em_pch_spt: 9678 case em_pch_cnp: 9679 bank1_offset = hw->flash_bank_size * 2; 9680 act_offset = E1000_ICH_NVM_SIG_WORD * 2; 9681 9682 /* set bank to 0 in case flash read fails. */ 9683 *bank = 0; 9684 9685 /* Check bank 0 */ 9686 ret_val = em_read_ich8_dword(hw, act_offset, &nvm_dword); 9687 if (ret_val) 9688 return ret_val; 9689 sig_byte = (uint8_t)((nvm_dword & 0xFF00) >> 8); 9690 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 9691 E1000_ICH_NVM_SIG_VALUE) { 9692 *bank = 0; 9693 return 0; 9694 } 9695 9696 /* Check bank 1 */ 9697 ret_val = em_read_ich8_dword(hw, act_offset + bank1_offset, 9698 &nvm_dword); 9699 if (ret_val) 9700 return ret_val; 9701 sig_byte = (uint8_t)((nvm_dword & 0xFF00) >> 8); 9702 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 9703 E1000_ICH_NVM_SIG_VALUE) { 9704 *bank = 1; 9705 return 0; 9706 } 9707 9708 DEBUGOUT("ERROR: No valid NVM bank present\n"); 9709 return -1; 9710 case em_ich8lan: 9711 case em_ich9lan: 9712 eecd = E1000_READ_REG(hw, EECD); 9713 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) == 9714 E1000_EECD_SEC1VAL_VALID_MASK) { 9715 if (eecd & E1000_EECD_SEC1VAL) 9716 *bank = 1; 9717 else 9718 *bank = 0; 9719 9720 return E1000_SUCCESS; 9721 } 9722 DEBUGOUT("Unable to determine valid NVM bank via EEC - reading flash signature\n"); 9723 /* fall-thru */ 9724 default: 9725 /* set bank to 0 in case flash read fails */ 9726 *bank = 0; 9727 9728 /* Check bank 0 */ 9729 ret_val = em_read_ich8_byte(hw, act_offset, 9730 &sig_byte); 9731 if (ret_val) 9732 return ret_val; 9733 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 9734 E1000_ICH_NVM_SIG_VALUE) { 9735 *bank = 0; 9736 return E1000_SUCCESS; 9737 } 9738 9739 /* Check bank 1 */ 9740 ret_val = em_read_ich8_byte(hw, act_offset + 9741 bank1_offset, 9742 &sig_byte); 9743 if (ret_val) 9744 return ret_val; 9745 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 9746 E1000_ICH_NVM_SIG_VALUE) { 9747 *bank = 1; 9748 return E1000_SUCCESS; 9749 } 9750 9751 DEBUGOUT("ERROR: No valid NVM bank present\n"); 9752 return -1; 9753 } 9754 } 9755 9756 STATIC int32_t 9757 em_read_eeprom_spt(struct em_hw *hw, uint16_t offset, uint16_t words, 9758 uint16_t *data) 9759 { 9760 int32_t error = E1000_SUCCESS; 9761 uint32_t flash_bank = 0; 9762 uint32_t act_offset = 0; 9763 uint32_t bank_offset = 0; 9764 uint32_t dword = 0; 9765 uint16_t i = 0, add; 9766 9767 /* 9768 * We need to know which is the valid flash bank. In the event that 9769 * we didn't allocate eeprom_shadow_ram, we may not be managing 9770 * flash_bank. So it cannot be trusted and needs to be updated with 9771 * each read. 9772 */ 9773 9774 if (hw->mac_type < em_pch_spt) 9775 return -E1000_ERR_EEPROM; 9776 9777 error = em_get_software_flag(hw); 9778 if (error != E1000_SUCCESS) 9779 return error; 9780 9781 error = em_valid_nvm_bank_detect_ich8lan(hw, &flash_bank); 9782 if (error != E1000_SUCCESS) { 9783 DEBUGOUT("Could not detect valid bank, assuming bank 0\n"); 9784 flash_bank = 0; 9785 } 9786 9787 /* 9788 * Adjust offset appropriately if we're on bank 1 - adjust for word 9789 * size 9790 */ 9791 bank_offset = flash_bank * (hw->flash_bank_size * 2); 9792 9793 for (i = add = 0; i < words; i += add) { 9794 if ((offset + i) % 2) { 9795 add = 1; 9796 if (hw->eeprom_shadow_ram != NULL 9797 && hw->eeprom_shadow_ram[offset + i].modified) { 9798 data[i] = 9799 hw->eeprom_shadow_ram[offset+i].eeprom_word; 9800 continue; 9801 } 9802 act_offset = bank_offset + (offset + i - 1) * 2; 9803 } else { 9804 add = 2; 9805 if (hw->eeprom_shadow_ram != NULL 9806 && hw->eeprom_shadow_ram[offset+i].modified 9807 && hw->eeprom_shadow_ram[offset+i+1].modified) { 9808 data[i] = hw->eeprom_shadow_ram[offset+i].eeprom_word; 9809 data[i+1] = hw->eeprom_shadow_ram[offset+i+1].eeprom_word; 9810 continue; 9811 } 9812 act_offset = bank_offset + (offset + i) * 2; 9813 } 9814 error = em_read_ich8_dword(hw, act_offset, &dword); 9815 if (error != E1000_SUCCESS) 9816 break; 9817 if (hw->eeprom_shadow_ram != NULL 9818 && hw->eeprom_shadow_ram[offset+i].modified) { 9819 data[i] = hw->eeprom_shadow_ram[offset+i].eeprom_word; 9820 } else { 9821 if (add == 1) 9822 data[i] = dword >> 16; 9823 else 9824 data[i] = dword & 0xFFFFUL; 9825 } 9826 if (add == 1 || words-i == 1) 9827 continue; 9828 if (hw->eeprom_shadow_ram != NULL 9829 && hw->eeprom_shadow_ram[offset+i+1].modified) { 9830 data[i+1] = 9831 hw->eeprom_shadow_ram[offset+i+1].eeprom_word; 9832 } else { 9833 data[i+1] = dword >> 16; 9834 } 9835 } 9836 9837 em_release_software_flag(hw); 9838 9839 return error; 9840 } 9841 9842 /****************************************************************************** 9843 * Reads a 16 bit word or words from the EEPROM using the ICH8's flash access 9844 * register. 9845 * 9846 * hw - Struct containing variables accessed by shared code 9847 * offset - offset of word in the EEPROM to read 9848 * data - word read from the EEPROM 9849 * words - number of words to read 9850 *****************************************************************************/ 9851 STATIC int32_t 9852 em_read_eeprom_ich8(struct em_hw *hw, uint16_t offset, uint16_t words, 9853 uint16_t *data) 9854 { 9855 int32_t error = E1000_SUCCESS; 9856 uint32_t flash_bank = 0; 9857 uint32_t act_offset = 0; 9858 uint32_t bank_offset = 0; 9859 uint16_t word = 0; 9860 uint16_t i = 0; 9861 /* 9862 * We need to know which is the valid flash bank. In the event that 9863 * we didn't allocate eeprom_shadow_ram, we may not be managing 9864 * flash_bank. So it cannot be trusted and needs to be updated with 9865 * each read. 9866 */ 9867 9868 if (hw->mac_type >= em_pch_spt) 9869 return em_read_eeprom_spt(hw, offset, words, data); 9870 9871 error = em_get_software_flag(hw); 9872 if (error != E1000_SUCCESS) 9873 return error; 9874 9875 error = em_valid_nvm_bank_detect_ich8lan(hw, &flash_bank); 9876 if (error != E1000_SUCCESS) { 9877 DEBUGOUT("Could not detect valid bank, assuming bank 0\n"); 9878 flash_bank = 0; 9879 } 9880 9881 /* 9882 * Adjust offset appropriately if we're on bank 1 - adjust for word 9883 * size 9884 */ 9885 bank_offset = flash_bank * (hw->flash_bank_size * 2); 9886 9887 for (i = 0; i < words; i++) { 9888 if (hw->eeprom_shadow_ram != NULL && 9889 hw->eeprom_shadow_ram[offset + i].modified == TRUE) { 9890 data[i] = 9891 hw->eeprom_shadow_ram[offset + i].eeprom_word; 9892 } else { 9893 /* The NVM part needs a byte offset, hence * 2 */ 9894 act_offset = bank_offset + ((offset + i) * 2); 9895 error = em_read_ich8_word(hw, act_offset, &word); 9896 if (error != E1000_SUCCESS) 9897 break; 9898 data[i] = word; 9899 } 9900 } 9901 9902 em_release_software_flag(hw); 9903 9904 return error; 9905 } 9906 9907 /****************************************************************************** 9908 * Writes a 16 bit word or words to the EEPROM using the ICH8's flash access 9909 * register. Actually, writes are written to the shadow ram cache in the hw 9910 * structure hw->em_shadow_ram. em_commit_shadow_ram flushes this to 9911 * the NVM, which occurs when the NVM checksum is updated. 9912 * 9913 * hw - Struct containing variables accessed by shared code 9914 * offset - offset of word in the EEPROM to write 9915 * words - number of words to write 9916 * data - words to write to the EEPROM 9917 *****************************************************************************/ 9918 STATIC int32_t 9919 em_write_eeprom_ich8(struct em_hw *hw, uint16_t offset, uint16_t words, 9920 uint16_t *data) 9921 { 9922 uint32_t i = 0; 9923 int32_t error = E1000_SUCCESS; 9924 error = em_get_software_flag(hw); 9925 if (error != E1000_SUCCESS) 9926 return error; 9927 /* 9928 * A driver can write to the NVM only if it has eeprom_shadow_ram 9929 * allocated. Subsequent reads to the modified words are read from 9930 * this cached structure as well. Writes will only go into this 9931 * cached structure unless it's followed by a call to 9932 * em_update_eeprom_checksum() where it will commit the changes and 9933 * clear the "modified" field. 9934 */ 9935 if (hw->eeprom_shadow_ram != NULL) { 9936 for (i = 0; i < words; i++) { 9937 if ((offset + i) < E1000_SHADOW_RAM_WORDS) { 9938 hw->eeprom_shadow_ram[offset + i].modified = 9939 TRUE; 9940 hw->eeprom_shadow_ram[offset + i].eeprom_word = 9941 data[i]; 9942 } else { 9943 error = -E1000_ERR_EEPROM; 9944 break; 9945 } 9946 } 9947 } else { 9948 /* 9949 * Drivers have the option to not allocate eeprom_shadow_ram 9950 * as long as they don't perform any NVM writes. An attempt 9951 * in doing so will result in this error. 9952 */ 9953 error = -E1000_ERR_EEPROM; 9954 } 9955 9956 em_release_software_flag(hw); 9957 9958 return error; 9959 } 9960 9961 /****************************************************************************** 9962 * This function does initial flash setup so that a new read/write/erase cycle 9963 * can be started. 9964 * 9965 * hw - The pointer to the hw structure 9966 ****************************************************************************/ 9967 STATIC int32_t 9968 em_ich8_cycle_init(struct em_hw *hw) 9969 { 9970 union ich8_hws_flash_status hsfsts; 9971 int32_t error = E1000_ERR_EEPROM; 9972 int32_t i = 0; 9973 DEBUGFUNC("em_ich8_cycle_init"); 9974 9975 if (hw->mac_type >= em_pch_spt) 9976 hsfsts.regval = E1000_READ_ICH_FLASH_REG32(hw, 9977 ICH_FLASH_HSFSTS) & 0xFFFFUL; 9978 else 9979 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, 9980 ICH_FLASH_HSFSTS); 9981 9982 /* May be check the Flash Des Valid bit in Hw status */ 9983 if (hsfsts.hsf_status.fldesvalid == 0) { 9984 DEBUGOUT("Flash descriptor invalid. SW Sequencing must be" 9985 " used."); 9986 return error; 9987 } 9988 /* Clear FCERR in Hw status by writing 1 */ 9989 /* Clear DAEL in Hw status by writing a 1 */ 9990 hsfsts.hsf_status.flcerr = 1; 9991 hsfsts.hsf_status.dael = 1; 9992 if (hw->mac_type >= em_pch_spt) 9993 E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_HSFSTS, 9994 hsfsts.regval & 0xFFFFUL); 9995 else 9996 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, 9997 hsfsts.regval); 9998 /* 9999 * Either we should have a hardware SPI cycle in progress bit to 10000 * check against, in order to start a new cycle or FDONE bit should 10001 * be changed in the hardware so that it is 1 after hardware reset, 10002 * which can then be used as an indication whether a cycle is in 10003 * progress or has been completed .. we should also have some 10004 * software semaphore mechanism to guard FDONE or the cycle in 10005 * progress bit so that two threads access to those bits can be 10006 * sequentiallized or a way so that 2 threads dont start the cycle at 10007 * the same time 10008 */ 10009 10010 if (hsfsts.hsf_status.flcinprog == 0) { 10011 /* 10012 * There is no cycle running at present, so we can start a 10013 * cycle 10014 */ 10015 /* Begin by setting Flash Cycle Done. */ 10016 hsfsts.hsf_status.flcdone = 1; 10017 if (hw->mac_type >= em_pch_spt) 10018 E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_HSFSTS, 10019 hsfsts.regval & 0xFFFFUL); 10020 else 10021 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, 10022 hsfsts.regval); 10023 error = E1000_SUCCESS; 10024 } else { 10025 /* 10026 * otherwise poll for sometime so the current cycle has a 10027 * chance to end before giving up. 10028 */ 10029 for (i = 0; i < ICH_FLASH_COMMAND_TIMEOUT; i++) { 10030 if (hw->mac_type >= em_pch_spt) 10031 hsfsts.regval = E1000_READ_ICH_FLASH_REG32( 10032 hw, ICH_FLASH_HSFSTS) & 0xFFFFUL; 10033 else 10034 hsfsts.regval = E1000_READ_ICH_FLASH_REG16( 10035 hw, ICH_FLASH_HSFSTS); 10036 if (hsfsts.hsf_status.flcinprog == 0) { 10037 error = E1000_SUCCESS; 10038 break; 10039 } 10040 usec_delay(1); 10041 } 10042 if (error == E1000_SUCCESS) { 10043 /* 10044 * Successful in waiting for previous cycle to 10045 * timeout, now set the Flash Cycle Done. 10046 */ 10047 hsfsts.hsf_status.flcdone = 1; 10048 if (hw->mac_type >= em_pch_spt) 10049 E1000_WRITE_ICH_FLASH_REG32(hw, 10050 ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFFUL); 10051 else 10052 E1000_WRITE_ICH_FLASH_REG16(hw, 10053 ICH_FLASH_HSFSTS, hsfsts.regval); 10054 } else { 10055 DEBUGOUT("Flash controller busy, cannot get access"); 10056 } 10057 } 10058 return error; 10059 } 10060 10061 /****************************************************************************** 10062 * This function starts a flash cycle and waits for its completion 10063 * 10064 * hw - The pointer to the hw structure 10065 *****************************************************************************/ 10066 STATIC int32_t 10067 em_ich8_flash_cycle(struct em_hw *hw, uint32_t timeout) 10068 { 10069 union ich8_hws_flash_ctrl hsflctl; 10070 union ich8_hws_flash_status hsfsts; 10071 int32_t error = E1000_ERR_EEPROM; 10072 uint32_t i = 0; 10073 10074 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ 10075 if (hw->mac_type >= em_pch_spt) 10076 hsflctl.regval = E1000_READ_ICH_FLASH_REG32(hw, 10077 ICH_FLASH_HSFSTS) >> 16; 10078 else 10079 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, 10080 ICH_FLASH_HSFCTL); 10081 hsflctl.hsf_ctrl.flcgo = 1; 10082 10083 if (hw->mac_type >= em_pch_spt) 10084 E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_HSFSTS, 10085 (uint32_t)hsflctl.regval << 16); 10086 else 10087 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, 10088 hsflctl.regval); 10089 10090 /* wait till FDONE bit is set to 1 */ 10091 do { 10092 if (hw->mac_type >= em_pch_spt) 10093 hsfsts.regval = E1000_READ_ICH_FLASH_REG32(hw, 10094 ICH_FLASH_HSFSTS) & 0xFFFFUL; 10095 else 10096 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, 10097 ICH_FLASH_HSFSTS); 10098 if (hsfsts.hsf_status.flcdone == 1) 10099 break; 10100 usec_delay(1); 10101 i++; 10102 } while (i < timeout); 10103 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) { 10104 error = E1000_SUCCESS; 10105 } 10106 return error; 10107 } 10108 10109 /****************************************************************************** 10110 * Reads a byte or word from the NVM using the ICH8 flash access registers. 10111 * 10112 * hw - The pointer to the hw structure 10113 * index - The index of the byte or word to read. 10114 * size - Size of data to read, 1=byte 2=word 10115 * data - Pointer to the word to store the value read. 10116 *****************************************************************************/ 10117 STATIC int32_t 10118 em_read_ich8_data(struct em_hw *hw, uint32_t index, uint32_t size, 10119 uint16_t *data) 10120 { 10121 union ich8_hws_flash_status hsfsts; 10122 union ich8_hws_flash_ctrl hsflctl; 10123 uint32_t flash_linear_address; 10124 uint32_t flash_data = 0; 10125 int32_t error = -E1000_ERR_EEPROM; 10126 int32_t count = 0; 10127 DEBUGFUNC("em_read_ich8_data"); 10128 10129 if (size < 1 || size > 2 || data == 0x0 || 10130 index > ICH_FLASH_LINEAR_ADDR_MASK) 10131 return error; 10132 10133 flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) + 10134 hw->flash_base_addr; 10135 10136 do { 10137 usec_delay(1); 10138 /* Steps */ 10139 error = em_ich8_cycle_init(hw); 10140 if (error != E1000_SUCCESS) 10141 break; 10142 10143 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, 10144 ICH_FLASH_HSFCTL); 10145 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 10146 hsflctl.hsf_ctrl.fldbcount = size - 1; 10147 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; 10148 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, 10149 hsflctl.regval); 10150 /* 10151 * Write the last 24 bits of index into Flash Linear address 10152 * field in Flash Address 10153 */ 10154 /* TODO: TBD maybe check the index against the size of flash */ 10155 10156 E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_FADDR, 10157 flash_linear_address); 10158 10159 error = em_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT); 10160 /* 10161 * Check if FCERR is set to 1, if set to 1, clear it and try 10162 * the whole sequence a few more times, else read in (shift 10163 * in) the Flash Data0, the order is least significant byte 10164 * first msb to lsb 10165 */ 10166 if (error == E1000_SUCCESS) { 10167 flash_data = E1000_READ_ICH_FLASH_REG(hw, 10168 ICH_FLASH_FDATA0); 10169 if (size == 1) { 10170 *data = (uint8_t) (flash_data & 0x000000FF); 10171 } else if (size == 2) { 10172 *data = (uint16_t) (flash_data & 0x0000FFFF); 10173 } 10174 break; 10175 } else { 10176 /* 10177 * If we've gotten here, then things are probably 10178 * completely hosed, but if the error condition is 10179 * detected, it won't hurt to give it another 10180 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 10181 */ 10182 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, 10183 ICH_FLASH_HSFSTS); 10184 if (hsfsts.hsf_status.flcerr == 1) { 10185 /* Repeat for some time before giving up. */ 10186 continue; 10187 } else if (hsfsts.hsf_status.flcdone == 0) { 10188 DEBUGOUT("Timeout error - flash cycle did not" 10189 " complete."); 10190 break; 10191 } 10192 } 10193 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 10194 10195 return error; 10196 } 10197 10198 STATIC int32_t 10199 em_read_ich8_data32(struct em_hw *hw, uint32_t offset, uint32_t *data) 10200 { 10201 union ich8_hws_flash_status hsfsts; 10202 union ich8_hws_flash_ctrl hsflctl; 10203 uint32_t flash_linear_address; 10204 int32_t error = -E1000_ERR_EEPROM; 10205 uint32_t count = 0; 10206 DEBUGFUNC("em_read_ich8_data32"); 10207 10208 if (hw->mac_type < em_pch_spt) 10209 return error; 10210 if (offset > ICH_FLASH_LINEAR_ADDR_MASK) 10211 return error; 10212 flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & offset) + 10213 hw->flash_base_addr; 10214 10215 do { 10216 usec_delay(1); 10217 /* Steps */ 10218 error = em_ich8_cycle_init(hw); 10219 if (error != E1000_SUCCESS) 10220 break; 10221 10222 /* 32 bit accesses in SPT. */ 10223 hsflctl.regval = E1000_READ_ICH_FLASH_REG32(hw, 10224 ICH_FLASH_HSFSTS) >> 16; 10225 10226 hsflctl.hsf_ctrl.fldbcount = sizeof(uint32_t) - 1; 10227 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; 10228 10229 E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_HSFSTS, 10230 (uint32_t)hsflctl.regval << 16); 10231 /* 10232 * Write the last 24 bits of offset into Flash Linear address 10233 * field in Flash Address 10234 */ 10235 /* TODO: TBD maybe check the offset against the size of flash */ 10236 10237 E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_FADDR, 10238 flash_linear_address); 10239 10240 error = em_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT); 10241 /* 10242 * Check if FCERR is set to 1, if set to 1, clear it and try 10243 * the whole sequence a few more times, else read in (shift 10244 * in) the Flash Data0, the order is least significant byte 10245 * first msb to lsb 10246 */ 10247 if (error == E1000_SUCCESS) { 10248 (*data) = (uint32_t)E1000_READ_ICH_FLASH_REG32(hw, 10249 ICH_FLASH_FDATA0); 10250 break; 10251 } else { 10252 /* 10253 * If we've gotten here, then things are probably 10254 * completely hosed, but if the error condition is 10255 * detected, it won't hurt to give it another 10256 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 10257 */ 10258 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, 10259 ICH_FLASH_HSFSTS); 10260 if (hsfsts.hsf_status.flcerr == 1) { 10261 /* Repeat for some time before giving up. */ 10262 continue; 10263 } else if (hsfsts.hsf_status.flcdone == 0) { 10264 DEBUGOUT("Timeout error - flash cycle did not" 10265 " complete."); 10266 break; 10267 } 10268 } 10269 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 10270 10271 return error; 10272 } 10273 10274 10275 /****************************************************************************** 10276 * Writes One /two bytes to the NVM using the ICH8 flash access registers. 10277 * 10278 * hw - The pointer to the hw structure 10279 * index - The index of the byte/word to write. 10280 * size - Size of data to read, 1=byte 2=word 10281 * data - The byte(s) to write to the NVM. 10282 *****************************************************************************/ 10283 STATIC int32_t 10284 em_write_ich8_data(struct em_hw *hw, uint32_t index, uint32_t size, 10285 uint16_t data) 10286 { 10287 union ich8_hws_flash_status hsfsts; 10288 union ich8_hws_flash_ctrl hsflctl; 10289 uint32_t flash_linear_address; 10290 uint32_t flash_data = 0; 10291 int32_t error = -E1000_ERR_EEPROM; 10292 int32_t count = 0; 10293 DEBUGFUNC("em_write_ich8_data"); 10294 10295 if (hw->mac_type >= em_pch_spt) 10296 return -E1000_ERR_EEPROM; 10297 if (size < 1 || size > 2 || data > size * 0xff || 10298 index > ICH_FLASH_LINEAR_ADDR_MASK) 10299 return error; 10300 10301 flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) + 10302 hw->flash_base_addr; 10303 10304 do { 10305 usec_delay(1); 10306 /* Steps */ 10307 error = em_ich8_cycle_init(hw); 10308 if (error != E1000_SUCCESS) 10309 break; 10310 10311 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, 10312 ICH_FLASH_HSFCTL); 10313 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 10314 hsflctl.hsf_ctrl.fldbcount = size - 1; 10315 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; 10316 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, 10317 hsflctl.regval); 10318 /* 10319 * Write the last 24 bits of index into Flash Linear address 10320 * field in Flash Address 10321 */ 10322 E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_FADDR, 10323 flash_linear_address); 10324 10325 if (size == 1) 10326 flash_data = (uint32_t) data & 0x00FF; 10327 else 10328 flash_data = (uint32_t) data; 10329 10330 E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_FDATA0, flash_data); 10331 /* 10332 * check if FCERR is set to 1 , if set to 1, clear it and try 10333 * the whole sequence a few more times else done 10334 */ 10335 error = em_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT); 10336 if (error == E1000_SUCCESS) { 10337 break; 10338 } else { 10339 /* 10340 * If we're here, then things are most likely 10341 * completely hosed, but if the error condition is 10342 * detected, it won't hurt to give it another 10343 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 10344 */ 10345 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, 10346 ICH_FLASH_HSFSTS); 10347 if (hsfsts.hsf_status.flcerr == 1) { 10348 /* Repeat for some time before giving up. */ 10349 continue; 10350 } else if (hsfsts.hsf_status.flcdone == 0) { 10351 DEBUGOUT("Timeout error - flash cycle did not" 10352 " complete."); 10353 break; 10354 } 10355 } 10356 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 10357 10358 return error; 10359 } 10360 10361 /****************************************************************************** 10362 * Reads a single byte from the NVM using the ICH8 flash access registers. 10363 * 10364 * hw - pointer to em_hw structure 10365 * index - The index of the byte to read. 10366 * data - Pointer to a byte to store the value read. 10367 *****************************************************************************/ 10368 STATIC int32_t 10369 em_read_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t *data) 10370 { 10371 int32_t status = E1000_SUCCESS; 10372 uint16_t word = 0; 10373 10374 if (hw->mac_type >= em_pch_spt) 10375 return -E1000_ERR_EEPROM; 10376 else 10377 status = em_read_ich8_data(hw, index, 1, &word); 10378 if (status == E1000_SUCCESS) { 10379 *data = (uint8_t) word; 10380 } 10381 return status; 10382 } 10383 10384 /****************************************************************************** 10385 * Writes a single byte to the NVM using the ICH8 flash access registers. 10386 * Performs verification by reading back the value and then going through 10387 * a retry algorithm before giving up. 10388 * 10389 * hw - pointer to em_hw structure 10390 * index - The index of the byte to write. 10391 * byte - The byte to write to the NVM. 10392 *****************************************************************************/ 10393 STATIC int32_t 10394 em_verify_write_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t byte) 10395 { 10396 int32_t error = E1000_SUCCESS; 10397 int32_t program_retries = 0; 10398 DEBUGOUT2("Byte := %2.2X Offset := %d\n", byte, index); 10399 10400 error = em_write_ich8_byte(hw, index, byte); 10401 10402 if (error != E1000_SUCCESS) { 10403 for (program_retries = 0; program_retries < 100; 10404 program_retries++) { 10405 DEBUGOUT2("Retrying \t Byte := %2.2X Offset := %d\n", 10406 byte, index); 10407 error = em_write_ich8_byte(hw, index, byte); 10408 usec_delay(100); 10409 if (error == E1000_SUCCESS) 10410 break; 10411 } 10412 } 10413 if (program_retries == 100) 10414 error = E1000_ERR_EEPROM; 10415 10416 return error; 10417 } 10418 10419 /****************************************************************************** 10420 * Writes a single byte to the NVM using the ICH8 flash access registers. 10421 * 10422 * hw - pointer to em_hw structure 10423 * index - The index of the byte to read. 10424 * data - The byte to write to the NVM. 10425 *****************************************************************************/ 10426 STATIC int32_t 10427 em_write_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t data) 10428 { 10429 int32_t status = E1000_SUCCESS; 10430 uint16_t word = (uint16_t) data; 10431 status = em_write_ich8_data(hw, index, 1, word); 10432 10433 return status; 10434 } 10435 10436 /****************************************************************************** 10437 * Reads a dword from the NVM using the ICH8 flash access registers. 10438 * 10439 * hw - pointer to em_hw structure 10440 * index - The starting BYTE index of the word to read. 10441 * data - Pointer to a word to store the value read. 10442 *****************************************************************************/ 10443 STATIC int32_t 10444 em_read_ich8_dword(struct em_hw *hw, uint32_t index, uint32_t *data) 10445 { 10446 int32_t status = E1000_SUCCESS; 10447 status = em_read_ich8_data32(hw, index, data); 10448 return status; 10449 } 10450 10451 /****************************************************************************** 10452 * Reads a word from the NVM using the ICH8 flash access registers. 10453 * 10454 * hw - pointer to em_hw structure 10455 * index - The starting byte index of the word to read. 10456 * data - Pointer to a word to store the value read. 10457 *****************************************************************************/ 10458 STATIC int32_t 10459 em_read_ich8_word(struct em_hw *hw, uint32_t index, uint16_t *data) 10460 { 10461 int32_t status = E1000_SUCCESS; 10462 status = em_read_ich8_data(hw, index, 2, data); 10463 return status; 10464 } 10465 10466 /****************************************************************************** 10467 * Erases the bank specified. Each bank may be a 4, 8 or 64k block. Banks are 0 10468 * based. 10469 * 10470 * hw - pointer to em_hw structure 10471 * bank - 0 for first bank, 1 for second bank 10472 * 10473 * Note that this function may actually erase as much as 8 or 64 KBytes. The 10474 * amount of NVM used in each bank is a *minimum* of 4 KBytes, but in fact the 10475 * bank size may be 4, 8 or 64 KBytes 10476 *****************************************************************************/ 10477 int32_t 10478 em_erase_ich8_4k_segment(struct em_hw *hw, uint32_t bank) 10479 { 10480 union ich8_hws_flash_status hsfsts; 10481 union ich8_hws_flash_ctrl hsflctl; 10482 uint32_t flash_linear_address; 10483 int32_t count = 0; 10484 int32_t error = E1000_ERR_EEPROM; 10485 int32_t iteration; 10486 int32_t sub_sector_size = 0; 10487 int32_t bank_size; 10488 int32_t j = 0; 10489 int32_t error_flag = 0; 10490 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 10491 /* 10492 * Determine HW Sector size: Read BERASE bits of Hw flash Status 10493 * register 10494 */ 10495 /* 10496 * 00: The Hw sector is 256 bytes, hence we need to erase 16 10497 * consecutive sectors. The start index for the nth Hw sector can be 10498 * calculated as bank * 4096 + n * 256 01: The Hw sector is 4K bytes, 10499 * hence we need to erase 1 sector. The start index for the nth Hw 10500 * sector can be calculated as bank * 4096 10: The HW sector is 8K 10501 * bytes 11: The Hw sector size is 64K bytes 10502 */ 10503 if (hsfsts.hsf_status.berasesz == 0x0) { 10504 /* Hw sector size 256 */ 10505 sub_sector_size = ICH_FLASH_SEG_SIZE_256; 10506 bank_size = ICH_FLASH_SECTOR_SIZE; 10507 iteration = ICH_FLASH_SECTOR_SIZE / ICH_FLASH_SEG_SIZE_256; 10508 } else if (hsfsts.hsf_status.berasesz == 0x1) { 10509 bank_size = ICH_FLASH_SEG_SIZE_4K; 10510 iteration = 1; 10511 } else if (hsfsts.hsf_status.berasesz == 0x2) { 10512 if (hw->mac_type == em_ich9lan) { 10513 uint32_t gfpreg, sector_base_addr, sector_end_addr; 10514 gfpreg = E1000_READ_ICH_FLASH_REG(hw, 10515 ICH_FLASH_GFPREG); 10516 /* 10517 * sector_X_addr is a "sector"-aligned address (4096 bytes) 10518 * Add 1 to sector_end_addr since this sector is included in 10519 * the overall size. 10520 */ 10521 sector_base_addr = gfpreg & ICH_GFPREG_BASE_MASK; 10522 sector_end_addr = 10523 ((gfpreg >> 16) & ICH_GFPREG_BASE_MASK) + 1; 10524 10525 /* 10526 * find total size of the NVM, then cut in half since the total 10527 * size represents two separate NVM banks. 10528 */ 10529 bank_size = (sector_end_addr - sector_base_addr) 10530 << ICH_FLASH_SECT_ADDR_SHIFT; 10531 bank_size /= 2; 10532 /* Word align */ 10533 bank_size = 10534 (bank_size / sizeof(uint16_t)) * sizeof(uint16_t); 10535 10536 sub_sector_size = ICH_FLASH_SEG_SIZE_8K; 10537 iteration = bank_size / ICH_FLASH_SEG_SIZE_8K; 10538 } else { 10539 return error; 10540 } 10541 } else if (hsfsts.hsf_status.berasesz == 0x3) { 10542 bank_size = ICH_FLASH_SEG_SIZE_64K; 10543 iteration = 1; 10544 } else { 10545 return error; 10546 } 10547 10548 for (j = 0; j < iteration; j++) { 10549 do { 10550 count++; 10551 /* Steps */ 10552 error = em_ich8_cycle_init(hw); 10553 if (error != E1000_SUCCESS) { 10554 error_flag = 1; 10555 break; 10556 } 10557 /* 10558 * Write a value 11 (block Erase) in Flash Cycle 10559 * field in Hw flash Control 10560 */ 10561 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, 10562 ICH_FLASH_HSFCTL); 10563 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE; 10564 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, 10565 hsflctl.regval); 10566 /* 10567 * Write the last 24 bits of an index within the 10568 * block into Flash Linear address field in Flash 10569 * Address. This probably needs to be calculated 10570 * here based off the on-chip erase sector size and 10571 * the software bank size (4, 8 or 64 KBytes) 10572 */ 10573 flash_linear_address = 10574 bank * bank_size + j * sub_sector_size; 10575 flash_linear_address += hw->flash_base_addr; 10576 flash_linear_address &= ICH_FLASH_LINEAR_ADDR_MASK; 10577 10578 E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_FADDR, 10579 flash_linear_address); 10580 10581 error = 10582 em_ich8_flash_cycle(hw, ICH_FLASH_ERASE_TIMEOUT); 10583 /* 10584 * Check if FCERR is set to 1. If 1, clear it and 10585 * try the whole sequence a few more times else Done 10586 */ 10587 if (error == E1000_SUCCESS) { 10588 break; 10589 } else { 10590 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, 10591 ICH_FLASH_HSFSTS); 10592 if (hsfsts.hsf_status.flcerr == 1) { 10593 /* 10594 * repeat for some time before giving 10595 * up 10596 */ 10597 continue; 10598 } else if (hsfsts.hsf_status.flcdone == 0) { 10599 error_flag = 1; 10600 break; 10601 } 10602 } 10603 } while ((count < ICH_FLASH_CYCLE_REPEAT_COUNT) && !error_flag); 10604 if (error_flag == 1) 10605 break; 10606 } 10607 if (error_flag != 1) 10608 error = E1000_SUCCESS; 10609 return error; 10610 } 10611 10612 /****************************************************************************** 10613 * Reads 16-bit words from the OTP. Return error when the word is not 10614 * stored in OTP. 10615 * 10616 * hw - Struct containing variables accessed by shared code 10617 * offset - offset of word in the OTP to read 10618 * data - word read from the OTP 10619 * words - number of words to read 10620 *****************************************************************************/ 10621 STATIC int32_t 10622 em_read_invm_i210(struct em_hw *hw, uint16_t offset, uint16_t words, 10623 uint16_t *data) 10624 { 10625 int32_t ret_val = E1000_SUCCESS; 10626 10627 switch (offset) 10628 { 10629 case EEPROM_MAC_ADDR_WORD0: 10630 case EEPROM_MAC_ADDR_WORD1: 10631 case EEPROM_MAC_ADDR_WORD2: 10632 /* Generate random MAC address if there's none. */ 10633 ret_val = em_read_invm_word_i210(hw, offset, data); 10634 if (ret_val != E1000_SUCCESS) { 10635 DEBUGOUT("MAC Addr not found in iNVM\n"); 10636 *data = 0xFFFF; 10637 ret_val = E1000_SUCCESS; 10638 } 10639 break; 10640 case EEPROM_INIT_CONTROL2_REG: 10641 ret_val = em_read_invm_word_i210(hw, offset, data); 10642 if (ret_val != E1000_SUCCESS) { 10643 *data = NVM_INIT_CTRL_2_DEFAULT_I211; 10644 ret_val = E1000_SUCCESS; 10645 } 10646 break; 10647 case EEPROM_INIT_CONTROL4_REG: 10648 ret_val = em_read_invm_word_i210(hw, offset, data); 10649 if (ret_val != E1000_SUCCESS) { 10650 *data = NVM_INIT_CTRL_4_DEFAULT_I211; 10651 ret_val = E1000_SUCCESS; 10652 } 10653 break; 10654 case EEPROM_LED_1_CFG: 10655 ret_val = em_read_invm_word_i210(hw, offset, data); 10656 if (ret_val != E1000_SUCCESS) { 10657 *data = NVM_LED_1_CFG_DEFAULT_I211; 10658 ret_val = E1000_SUCCESS; 10659 } 10660 break; 10661 case EEPROM_LED_0_2_CFG: 10662 ret_val = em_read_invm_word_i210(hw, offset, data); 10663 if (ret_val != E1000_SUCCESS) { 10664 *data = NVM_LED_0_2_CFG_DEFAULT_I211; 10665 ret_val = E1000_SUCCESS; 10666 } 10667 break; 10668 case EEPROM_ID_LED_SETTINGS: 10669 ret_val = em_read_invm_word_i210(hw, offset, data); 10670 if (ret_val != E1000_SUCCESS) { 10671 *data = ID_LED_RESERVED_FFFF; 10672 ret_val = E1000_SUCCESS; 10673 } 10674 break; 10675 default: 10676 DEBUGOUT1("NVM word 0x%02x is not mapped.\n", offset); 10677 *data = NVM_RESERVED_WORD; 10678 break; 10679 } 10680 10681 return ret_val; 10682 } 10683 10684 /****************************************************************************** 10685 * Reads 16-bit words from the OTP. Return error when the word is not 10686 * stored in OTP. 10687 * 10688 * hw - Struct containing variables accessed by shared code 10689 * offset - offset of word in the OTP to read 10690 * data - word read from the OTP 10691 *****************************************************************************/ 10692 STATIC int32_t 10693 em_read_invm_word_i210(struct em_hw *hw, uint16_t address, uint16_t *data) 10694 { 10695 int32_t error = -E1000_NOT_IMPLEMENTED; 10696 uint32_t invm_dword; 10697 uint16_t i; 10698 uint8_t record_type, word_address; 10699 10700 for (i = 0; i < INVM_SIZE; i++) { 10701 invm_dword = EM_READ_REG(hw, E1000_INVM_DATA_REG(i)); 10702 /* Get record type */ 10703 record_type = INVM_DWORD_TO_RECORD_TYPE(invm_dword); 10704 if (record_type == INVM_UNINITIALIZED_STRUCTURE) 10705 break; 10706 if (record_type == INVM_CSR_AUTOLOAD_STRUCTURE) 10707 i += INVM_CSR_AUTOLOAD_DATA_SIZE_IN_DWORDS; 10708 if (record_type == INVM_RSA_KEY_SHA256_STRUCTURE) 10709 i += INVM_RSA_KEY_SHA256_DATA_SIZE_IN_DWORDS; 10710 if (record_type == INVM_WORD_AUTOLOAD_STRUCTURE) { 10711 word_address = INVM_DWORD_TO_WORD_ADDRESS(invm_dword); 10712 if (word_address == address) { 10713 *data = INVM_DWORD_TO_WORD_DATA(invm_dword); 10714 error = E1000_SUCCESS; 10715 break; 10716 } 10717 } 10718 } 10719 10720 return error; 10721 } 10722 10723 STATIC int32_t 10724 em_init_lcd_from_nvm_config_region(struct em_hw *hw, uint32_t cnf_base_addr, 10725 uint32_t cnf_size) 10726 { 10727 uint32_t ret_val = E1000_SUCCESS; 10728 uint16_t word_addr, reg_data, reg_addr; 10729 uint16_t i; 10730 /* cnf_base_addr is in DWORD */ 10731 word_addr = (uint16_t) (cnf_base_addr << 1); 10732 10733 /* cnf_size is returned in size of dwords */ 10734 for (i = 0; i < cnf_size; i++) { 10735 ret_val = 10736 em_read_eeprom(hw, (word_addr + i * 2), 1, ®_data); 10737 if (ret_val) 10738 return ret_val; 10739 10740 ret_val = 10741 em_read_eeprom(hw, (word_addr + i * 2 + 1), 1, ®_addr); 10742 if (ret_val) 10743 return ret_val; 10744 10745 ret_val = em_get_software_flag(hw); 10746 if (ret_val != E1000_SUCCESS) 10747 return ret_val; 10748 10749 ret_val = 10750 em_write_phy_reg_ex(hw, (uint32_t) reg_addr, reg_data); 10751 10752 em_release_software_flag(hw); 10753 } 10754 10755 return ret_val; 10756 } 10757 10758 /****************************************************************************** 10759 * This function initializes the PHY from the NVM on ICH8 platforms. This 10760 * is needed due to an issue where the NVM configuration is not properly 10761 * autoloaded after power transitions. Therefore, after each PHY reset, we 10762 * will load the configuration data out of the NVM manually. 10763 * 10764 * hw: Struct containing variables accessed by shared code 10765 *****************************************************************************/ 10766 STATIC int32_t 10767 em_init_lcd_from_nvm(struct em_hw *hw) 10768 { 10769 uint32_t reg_data, cnf_base_addr, cnf_size, ret_val, loop, sw_cfg_mask; 10770 if (hw->phy_type != em_phy_igp_3) 10771 return E1000_SUCCESS; 10772 10773 /* Check if SW needs configure the PHY */ 10774 if (hw->device_id == E1000_DEV_ID_ICH8_IGP_M_AMT || 10775 hw->device_id == E1000_DEV_ID_ICH8_IGP_M || 10776 hw->mac_type == em_pchlan || 10777 hw->mac_type == em_pch2lan || 10778 hw->mac_type == em_pch_lpt || 10779 hw->mac_type == em_pch_spt || 10780 hw->mac_type == em_pch_cnp) 10781 sw_cfg_mask = FEXTNVM_SW_CONFIG_ICH8M; 10782 else 10783 sw_cfg_mask = FEXTNVM_SW_CONFIG; 10784 10785 reg_data = E1000_READ_REG(hw, FEXTNVM); 10786 if (!(reg_data & sw_cfg_mask)) 10787 return E1000_SUCCESS; 10788 10789 /* Wait for basic configuration completes before proceeding */ 10790 loop = 0; 10791 do { 10792 reg_data = 10793 E1000_READ_REG(hw, STATUS) & E1000_STATUS_LAN_INIT_DONE; 10794 usec_delay(100); 10795 loop++; 10796 } while ((!reg_data) && (loop < 50)); 10797 10798 /* Clear the Init Done bit for the next init event */ 10799 reg_data = E1000_READ_REG(hw, STATUS); 10800 reg_data &= ~E1000_STATUS_LAN_INIT_DONE; 10801 E1000_WRITE_REG(hw, STATUS, reg_data); 10802 /* 10803 * Make sure HW does not configure LCD from PHY extended 10804 * configuration before SW configuration 10805 */ 10806 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL); 10807 if ((reg_data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) == 0x0000) { 10808 reg_data = E1000_READ_REG(hw, EXTCNF_SIZE); 10809 cnf_size = reg_data & E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH; 10810 cnf_size >>= 16; 10811 if (cnf_size) { 10812 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL); 10813 cnf_base_addr = reg_data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER; 10814 /* cnf_base_addr is in DWORD */ 10815 cnf_base_addr >>= 16; 10816 10817 /* Configure LCD from extended configuration region. */ 10818 ret_val = em_init_lcd_from_nvm_config_region(hw, 10819 cnf_base_addr, cnf_size); 10820 if (ret_val) 10821 return ret_val; 10822 } 10823 } 10824 return E1000_SUCCESS; 10825 } 10826 10827 /****************************************************************************** 10828 * em_set_pciex_completion_timeout - set pci-e completion timeout 10829 * 10830 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms, 10831 * however the hardware default for these parts is 500us to 1ms which is less 10832 * than the 10ms recommended by the pci-e spec. To address this we need to 10833 * increase the value to either 10ms to 200ms for capability version 1 config, 10834 * or 16ms to 55ms for version 2. 10835 * 10836 * * hw - pointer to em_hw structure 10837 *****************************************************************************/ 10838 int32_t 10839 em_set_pciex_completion_timeout(struct em_hw *hw) 10840 { 10841 uint32_t gcr = E1000_READ_REG(hw, GCR); 10842 int32_t ret_val = E1000_SUCCESS; 10843 10844 /* Only take action if timeout value is not set by system BIOS */ 10845 if (gcr & E1000_GCR_CMPL_TMOUT_MASK) 10846 goto out; 10847 10848 DEBUGOUT("PCIe completion timeout not set by system BIOS."); 10849 10850 /* 10851 * If capababilities version is type 1 we can write the 10852 * timeout of 10ms to 200ms through the GCR register 10853 */ 10854 10855 if (!(gcr & E1000_GCR_CAP_VER2)) { 10856 gcr |= E1000_GCR_CMPL_TMOUT_10ms; 10857 DEBUGOUT("PCIe capability version 1 detected, setting \ 10858 completion timeout to 10ms."); 10859 goto out; 10860 } 10861 10862 /* 10863 * For version 2 capabilities we need to write the config space 10864 * directly in order to set the completion timeout value for 10865 * 16ms to 55ms 10866 * 10867 * XXX: Implement em_*_pcie_cap_reg() first. 10868 */ 10869 #if 0 10870 ret_val = em_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 10871 &pciex_devctl2); 10872 10873 if (ret_val) 10874 goto out; 10875 10876 pciex_devctl2 |= PCIE_DEVICE_CONTROL2_16ms; 10877 10878 ret_val = em_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 10879 &pciex_devctl2); 10880 #endif 10881 10882 out: 10883 10884 /* Disable completion timeout resend */ 10885 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND; 10886 10887 DEBUGOUT("PCIe completion timeout resend disabled."); 10888 10889 E1000_WRITE_REG(hw, GCR, gcr); 10890 return ret_val; 10891 } 10892 10893 /*************************************************************************** 10894 * Set slow MDIO access mode 10895 ***************************************************************************/ 10896 static int32_t 10897 em_set_mdio_slow_mode_hv(struct em_hw *hw) 10898 { 10899 int32_t ret_val; 10900 uint16_t data; 10901 DEBUGFUNC("em_set_mdio_slow_mode_hv"); 10902 10903 ret_val = em_read_phy_reg(hw, HV_KMRN_MODE_CTRL, &data); 10904 if (ret_val) 10905 return ret_val; 10906 10907 data |= HV_KMRN_MDIO_SLOW; 10908 10909 ret_val = em_write_phy_reg(hw, HV_KMRN_MODE_CTRL, data); 10910 10911 return ret_val; 10912 } 10913 10914 /*************************************************************************** 10915 * A series of Phy workarounds to be done after every PHY reset. 10916 ***************************************************************************/ 10917 int32_t 10918 em_hv_phy_workarounds_ich8lan(struct em_hw *hw) 10919 { 10920 int32_t ret_val = E1000_SUCCESS; 10921 uint16_t phy_data; 10922 uint16_t swfw; 10923 DEBUGFUNC("em_hv_phy_workarounds_ich8lan"); 10924 10925 if (hw->mac_type != em_pchlan) 10926 goto out; 10927 10928 swfw = E1000_SWFW_PHY0_SM; 10929 10930 /* Set MDIO slow mode before any other MDIO access */ 10931 if (hw->phy_type == em_phy_82577 || 10932 hw->phy_type == em_phy_82578) { 10933 ret_val = em_set_mdio_slow_mode_hv(hw); 10934 if (ret_val) 10935 goto out; 10936 } 10937 10938 /* Hanksville M Phy init for IEEE. */ 10939 if ((hw->revision_id == 2) && 10940 (hw->phy_type == em_phy_82577) && 10941 ((hw->phy_revision == 2) || (hw->phy_revision == 3))) { 10942 em_write_phy_reg(hw, 0x10, 0x8823); 10943 em_write_phy_reg(hw, 0x11, 0x0018); 10944 em_write_phy_reg(hw, 0x10, 0x8824); 10945 em_write_phy_reg(hw, 0x11, 0x0016); 10946 em_write_phy_reg(hw, 0x10, 0x8825); 10947 em_write_phy_reg(hw, 0x11, 0x001A); 10948 em_write_phy_reg(hw, 0x10, 0x888C); 10949 em_write_phy_reg(hw, 0x11, 0x0007); 10950 em_write_phy_reg(hw, 0x10, 0x888D); 10951 em_write_phy_reg(hw, 0x11, 0x0007); 10952 em_write_phy_reg(hw, 0x10, 0x888E); 10953 em_write_phy_reg(hw, 0x11, 0x0007); 10954 em_write_phy_reg(hw, 0x10, 0x8827); 10955 em_write_phy_reg(hw, 0x11, 0x0001); 10956 em_write_phy_reg(hw, 0x10, 0x8835); 10957 em_write_phy_reg(hw, 0x11, 0x0001); 10958 em_write_phy_reg(hw, 0x10, 0x8834); 10959 em_write_phy_reg(hw, 0x11, 0x0001); 10960 em_write_phy_reg(hw, 0x10, 0x8833); 10961 em_write_phy_reg(hw, 0x11, 0x0002); 10962 } 10963 10964 if (((hw->phy_type == em_phy_82577) && 10965 ((hw->phy_revision == 1) || (hw->phy_revision == 2))) || 10966 ((hw->phy_type == em_phy_82578) && (hw->phy_revision == 1))) { 10967 /* Disable generation of early preamble */ 10968 ret_val = em_write_phy_reg(hw, PHY_REG(769, 25), 0x4431); 10969 if (ret_val) 10970 goto out; 10971 10972 /* Preamble tuning for SSC */ 10973 ret_val = em_write_phy_reg(hw, PHY_REG(770, 16), 0xA204); 10974 if (ret_val) 10975 goto out; 10976 } 10977 10978 if (hw->phy_type == em_phy_82578) { 10979 /* 10980 * Return registers to default by doing a soft reset then 10981 * writing 0x3140 to the control register. 10982 */ 10983 if (hw->phy_revision < 2) { 10984 em_phy_reset(hw); 10985 ret_val = em_write_phy_reg(hw, PHY_CTRL, 0x3140); 10986 } 10987 } 10988 10989 if ((hw->revision_id == 2) && 10990 (hw->phy_type == em_phy_82577) && 10991 ((hw->phy_revision == 2) || (hw->phy_revision == 3))) { 10992 /* 10993 * Workaround for OEM (GbE) not operating after reset - 10994 * restart AN (twice) 10995 */ 10996 ret_val = em_write_phy_reg(hw, PHY_REG(0, 25), 0x0400); 10997 if (ret_val) 10998 goto out; 10999 ret_val = em_write_phy_reg(hw, PHY_REG(0, 25), 0x0400); 11000 if (ret_val) 11001 goto out; 11002 } 11003 11004 /* Select page 0 */ 11005 ret_val = em_swfw_sync_acquire(hw, swfw); 11006 if (ret_val) 11007 goto out; 11008 11009 hw->phy_addr = 1; 11010 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT, 0); 11011 em_swfw_sync_release(hw, swfw); 11012 if (ret_val) 11013 goto out; 11014 11015 /* Workaround for link disconnects on a busy hub in half duplex */ 11016 ret_val = em_read_phy_reg(hw, 11017 PHY_REG(BM_PORT_CTRL_PAGE, 17), 11018 &phy_data); 11019 if (ret_val) 11020 goto release; 11021 ret_val = em_write_phy_reg(hw, 11022 PHY_REG(BM_PORT_CTRL_PAGE, 17), 11023 phy_data & 0x00FF); 11024 release: 11025 out: 11026 return ret_val; 11027 } 11028 11029 11030 /*************************************************************************** 11031 * Si workaround 11032 * 11033 * This function works around a Si bug where the link partner can get 11034 * a link up indication before the PHY does. If small packets are sent 11035 * by the link partner they can be placed in the packet buffer without 11036 * being properly accounted for by the PHY and will stall preventing 11037 * further packets from being received. The workaround is to clear the 11038 * packet buffer after the PHY detects link up. 11039 ***************************************************************************/ 11040 int32_t 11041 em_link_stall_workaround_hv(struct em_hw *hw) 11042 { 11043 int32_t ret_val = E1000_SUCCESS; 11044 uint16_t phy_data; 11045 11046 if (hw->phy_type != em_phy_82578) 11047 goto out; 11048 11049 /* Do not apply workaround if in PHY loopback bit 14 set */ 11050 em_read_phy_reg(hw, PHY_CTRL, &phy_data); 11051 if (phy_data & E1000_PHY_CTRL_LOOPBACK) 11052 goto out; 11053 11054 /* check if link is up and at 1Gbps */ 11055 ret_val = em_read_phy_reg(hw, BM_CS_STATUS, &phy_data); 11056 if (ret_val) 11057 goto out; 11058 11059 phy_data &= BM_CS_STATUS_LINK_UP | 11060 BM_CS_STATUS_RESOLVED | 11061 BM_CS_STATUS_SPEED_MASK; 11062 11063 if (phy_data != (BM_CS_STATUS_LINK_UP | 11064 BM_CS_STATUS_RESOLVED | 11065 BM_CS_STATUS_SPEED_1000)) 11066 goto out; 11067 11068 msec_delay(200); 11069 11070 /* flush the packets in the fifo buffer */ 11071 ret_val = em_write_phy_reg(hw, HV_MUX_DATA_CTRL, 11072 HV_MUX_DATA_CTRL_GEN_TO_MAC | HV_MUX_DATA_CTRL_FORCE_SPEED); 11073 if (ret_val) 11074 goto out; 11075 11076 ret_val = em_write_phy_reg(hw, HV_MUX_DATA_CTRL, 11077 HV_MUX_DATA_CTRL_GEN_TO_MAC); 11078 11079 out: 11080 return ret_val; 11081 } 11082 11083 /**************************************************************************** 11084 * K1 Si workaround 11085 * 11086 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning 11087 * from a lower speed. This workaround disables K1 whenever link is at 1Gig. 11088 * If link is down, the function will restore the default K1 setting located 11089 * in the NVM. 11090 ****************************************************************************/ 11091 int32_t 11092 em_k1_gig_workaround_hv(struct em_hw *hw, boolean_t link) 11093 { 11094 int32_t ret_val; 11095 uint16_t phy_data; 11096 boolean_t k1_enable; 11097 11098 DEBUGFUNC("em_k1_gig_workaround_hv"); 11099 11100 if (hw->mac_type != em_pchlan) 11101 return E1000_SUCCESS; 11102 11103 ret_val = em_read_eeprom_ich8(hw, E1000_NVM_K1_CONFIG, 1, &phy_data); 11104 if (ret_val) 11105 return ret_val; 11106 11107 k1_enable = phy_data & E1000_NVM_K1_ENABLE ? TRUE : FALSE; 11108 11109 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */ 11110 if (link) { 11111 if (hw->phy_type == em_phy_82578) { 11112 ret_val = em_read_phy_reg(hw, BM_CS_STATUS, 11113 &phy_data); 11114 if (ret_val) 11115 return ret_val; 11116 11117 phy_data &= BM_CS_STATUS_LINK_UP | 11118 BM_CS_STATUS_RESOLVED | 11119 BM_CS_STATUS_SPEED_MASK; 11120 11121 if (phy_data == (BM_CS_STATUS_LINK_UP | 11122 BM_CS_STATUS_RESOLVED | 11123 BM_CS_STATUS_SPEED_1000)) 11124 k1_enable = FALSE; 11125 } 11126 11127 if (hw->phy_type == em_phy_82577) { 11128 ret_val = em_read_phy_reg(hw, HV_M_STATUS, 11129 &phy_data); 11130 if (ret_val) 11131 return ret_val; 11132 11133 phy_data &= HV_M_STATUS_LINK_UP | 11134 HV_M_STATUS_AUTONEG_COMPLETE | 11135 HV_M_STATUS_SPEED_MASK; 11136 11137 if (phy_data == (HV_M_STATUS_LINK_UP | 11138 HV_M_STATUS_AUTONEG_COMPLETE | 11139 HV_M_STATUS_SPEED_1000)) 11140 k1_enable = FALSE; 11141 } 11142 11143 /* Link stall fix for link up */ 11144 ret_val = em_write_phy_reg(hw, PHY_REG(770, 19), 11145 0x0100); 11146 if (ret_val) 11147 return ret_val; 11148 11149 } else { 11150 /* Link stall fix for link down */ 11151 ret_val = em_write_phy_reg(hw, PHY_REG(770, 19), 11152 0x4100); 11153 if (ret_val) 11154 return ret_val; 11155 } 11156 11157 ret_val = em_configure_k1_ich8lan(hw, k1_enable); 11158 11159 return ret_val; 11160 } 11161 11162 /* Workaround to set the K1 beacon duration for 82579 parts */ 11163 int32_t 11164 em_k1_workaround_lv(struct em_hw *hw) 11165 { 11166 int32_t ret_val; 11167 uint16_t phy_data; 11168 uint32_t mac_reg; 11169 11170 ret_val = em_read_phy_reg(hw, BM_CS_STATUS, &phy_data); 11171 if (ret_val) 11172 return ret_val; 11173 11174 if ((phy_data & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) 11175 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) { 11176 mac_reg = E1000_READ_REG(hw, FEXTNVM4); 11177 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK; 11178 11179 if (phy_data & HV_M_STATUS_SPEED_1000) 11180 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC; 11181 else 11182 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC; 11183 11184 E1000_WRITE_REG(hw, FEXTNVM4, mac_reg); 11185 } 11186 11187 return E1000_SUCCESS; 11188 } 11189 11190 /** 11191 * em_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP 11192 * 11193 * When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications 11194 * preventing further DMA write requests. Workaround the issue by disabling 11195 * the de-assertion of the clock request when in 1Gbps mode. 11196 * Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link 11197 * speeds in order to avoid Tx hangs. 11198 **/ 11199 int32_t 11200 em_k1_workaround_lpt_lp(struct em_hw *hw, boolean_t link) 11201 { 11202 uint32_t fextnvm6 = E1000_READ_REG(hw, FEXTNVM6); 11203 uint32_t status = E1000_READ_REG(hw, STATUS); 11204 int32_t ret_val = E1000_SUCCESS; 11205 uint16_t reg; 11206 11207 if (link && (status & E1000_STATUS_SPEED_1000)) { 11208 ret_val = em_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 11209 ®); 11210 if (ret_val) 11211 return ret_val; 11212 11213 ret_val = em_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 11214 reg & ~E1000_KMRNCTRLSTA_K1_ENABLE); 11215 if (ret_val) 11216 return ret_val; 11217 11218 usec_delay(10); 11219 11220 E1000_WRITE_REG(hw, FEXTNVM6, 11221 fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK); 11222 11223 ret_val = em_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 11224 reg); 11225 } else { 11226 /* clear FEXTNVM6 bit 8 on link down or 10/100 */ 11227 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK; 11228 11229 if (!link || ((status & E1000_STATUS_SPEED_100) && 11230 (status & E1000_STATUS_FD))) 11231 goto update_fextnvm6; 11232 11233 ret_val = em_read_phy_reg(hw, I217_INBAND_CTRL, ®); 11234 if (ret_val) 11235 return ret_val; 11236 11237 /* Clear link status transmit timeout */ 11238 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK; 11239 11240 if (status & E1000_STATUS_SPEED_100) { 11241 /* Set inband Tx timeout to 5x10us for 100Half */ 11242 reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT; 11243 11244 /* Do not extend the K1 entry latency for 100Half */ 11245 fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION; 11246 } else { 11247 /* Set inband Tx timeout to 50x10us for 10Full/Half */ 11248 reg |= 50 << 11249 I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT; 11250 11251 /* Extend the K1 entry latency for 10 Mbps */ 11252 fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION; 11253 } 11254 11255 ret_val = em_write_phy_reg(hw, I217_INBAND_CTRL, reg); 11256 if (ret_val) 11257 return ret_val; 11258 11259 update_fextnvm6: 11260 E1000_WRITE_REG(hw, FEXTNVM6, fextnvm6); 11261 } 11262 11263 return ret_val; 11264 11265 } 11266 11267 11268 /*************************************************************************** 11269 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware 11270 * @hw: pointer to the HW structure 11271 * @gate: boolean set to TRUE to gate, FALSE to ungate 11272 * 11273 * Gate/ungate the automatic PHY configuration via hardware; perform 11274 * the configuration via software instead. 11275 ***************************************************************************/ 11276 void 11277 em_gate_hw_phy_config_ich8lan(struct em_hw *hw, boolean_t gate) 11278 { 11279 uint32_t extcnf_ctrl; 11280 11281 DEBUGFUNC("em_gate_hw_phy_config_ich8lan"); 11282 11283 if (hw->mac_type != em_pch2lan) 11284 return; 11285 11286 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 11287 11288 if (gate) 11289 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG; 11290 else 11291 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG; 11292 11293 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); 11294 } 11295 11296 /*************************************************************************** 11297 * Configure K1 power state 11298 * 11299 * Configure the K1 power state based on the provided parameter. 11300 * Assumes semaphore already acquired. 11301 * 11302 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 11303 ***************************************************************************/ 11304 int32_t 11305 em_configure_k1_ich8lan(struct em_hw *hw, boolean_t k1_enable) 11306 { 11307 int32_t ret_val = E1000_SUCCESS; 11308 uint32_t ctrl_reg = 0; 11309 uint32_t ctrl_ext = 0; 11310 uint32_t reg = 0; 11311 uint16_t kmrn_reg = 0; 11312 11313 ret_val = em_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 11314 &kmrn_reg); 11315 if (ret_val) 11316 goto out; 11317 11318 if (k1_enable) 11319 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE; 11320 else 11321 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE; 11322 11323 ret_val = em_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 11324 kmrn_reg); 11325 if (ret_val) 11326 goto out; 11327 11328 usec_delay(20); 11329 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 11330 ctrl_reg = E1000_READ_REG(hw, CTRL); 11331 11332 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 11333 reg |= E1000_CTRL_FRCSPD; 11334 E1000_WRITE_REG(hw, CTRL, reg); 11335 11336 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS); 11337 usec_delay(20); 11338 E1000_WRITE_REG(hw, CTRL, ctrl_reg); 11339 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 11340 usec_delay(20); 11341 11342 out: 11343 return ret_val; 11344 } 11345 11346 /*************************************************************************** 11347 * em_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be 11348 * done after every PHY reset. 11349 ***************************************************************************/ 11350 int32_t 11351 em_lv_phy_workarounds_ich8lan(struct em_hw *hw) 11352 { 11353 int32_t ret_val = E1000_SUCCESS; 11354 uint16_t swfw; 11355 11356 DEBUGFUNC("e1000_lv_phy_workarounds_ich8lan"); 11357 11358 if (hw->mac_type != em_pch2lan) 11359 goto out; 11360 11361 /* Set MDIO slow mode before any other MDIO access */ 11362 ret_val = em_set_mdio_slow_mode_hv(hw); 11363 11364 swfw = E1000_SWFW_PHY0_SM; 11365 ret_val = em_swfw_sync_acquire(hw, swfw); 11366 if (ret_val) 11367 goto out; 11368 ret_val = em_write_phy_reg(hw, I82579_EMI_ADDR, 11369 I82579_MSE_THRESHOLD); 11370 if (ret_val) 11371 goto release; 11372 /* set MSE higher to enable link to stay up when noise is high */ 11373 ret_val = em_write_phy_reg(hw, I82579_EMI_DATA, 11374 0x0034); 11375 if (ret_val) 11376 goto release; 11377 ret_val = em_write_phy_reg(hw, I82579_EMI_ADDR, 11378 I82579_MSE_LINK_DOWN); 11379 if (ret_val) 11380 goto release; 11381 /* drop link after 5 times MSE threshold was reached */ 11382 ret_val = em_write_phy_reg(hw, I82579_EMI_DATA, 11383 0x0005); 11384 release: 11385 em_swfw_sync_release(hw, swfw); 11386 11387 out: 11388 return ret_val; 11389 } 11390 11391 int32_t 11392 em_set_eee_i350(struct em_hw *hw) 11393 { 11394 int32_t ret_val = E1000_SUCCESS; 11395 uint32_t ipcnfg, eeer; 11396 11397 if ((hw->mac_type < em_i350) || 11398 (hw->media_type != em_media_type_copper)) 11399 goto out; 11400 ipcnfg = EM_READ_REG(hw, E1000_IPCNFG); 11401 eeer = EM_READ_REG(hw, E1000_EEER); 11402 11403 if (hw->eee_enable) { 11404 ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN); 11405 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN | 11406 E1000_EEER_LPI_FC); 11407 } else { 11408 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN); 11409 eeer &= ~(E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN | 11410 E1000_EEER_LPI_FC); 11411 } 11412 EM_WRITE_REG(hw, E1000_IPCNFG, ipcnfg); 11413 EM_WRITE_REG(hw, E1000_EEER, eeer); 11414 EM_READ_REG(hw, E1000_IPCNFG); 11415 EM_READ_REG(hw, E1000_EEER); 11416 out: 11417 return ret_val; 11418 } 11419 11420 /*************************************************************************** 11421 * em_set_eee_pchlan - Enable/disable EEE support 11422 * @hw: pointer to the HW structure 11423 * 11424 * Enable/disable EEE based on setting in dev_spec structure. The bits in 11425 * the LPI Control register will remain set only if/when link is up. 11426 ***************************************************************************/ 11427 int32_t 11428 em_set_eee_pchlan(struct em_hw *hw) 11429 { 11430 int32_t ret_val = E1000_SUCCESS; 11431 uint16_t phy_reg; 11432 11433 DEBUGFUNC("em_set_eee_pchlan"); 11434 11435 if (hw->phy_type != em_phy_82579 && 11436 hw->phy_type != em_phy_i217) 11437 goto out; 11438 11439 ret_val = em_read_phy_reg(hw, I82579_LPI_CTRL, &phy_reg); 11440 if (ret_val) 11441 goto out; 11442 11443 if (hw->eee_enable) 11444 phy_reg &= ~I82579_LPI_CTRL_ENABLE_MASK; 11445 else 11446 phy_reg |= I82579_LPI_CTRL_ENABLE_MASK; 11447 11448 ret_val = em_write_phy_reg(hw, I82579_LPI_CTRL, phy_reg); 11449 out: 11450 return ret_val; 11451 } 11452 11453 /** 11454 * em_initialize_M88E1512_phy - Initialize M88E1512 PHY 11455 * @hw: pointer to the HW structure 11456 * 11457 * Initialize Marvell 1512 to work correctly with Avoton. 11458 **/ 11459 int32_t 11460 em_initialize_M88E1512_phy(struct em_hw *hw) 11461 { 11462 int32_t ret_val = E1000_SUCCESS; 11463 11464 DEBUGFUNC("e1000_initialize_M88E1512_phy"); 11465 11466 /* Check if this is correct PHY. */ 11467 if (hw->phy_id != M88E1512_E_PHY_ID) 11468 goto out; 11469 11470 /* Switch to PHY page 0xFF. */ 11471 ret_val = em_write_phy_reg(hw, M88E1543_PAGE_ADDR, 0x00FF); 11472 if (ret_val) 11473 goto out; 11474 11475 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_2, 0x214B); 11476 if (ret_val) 11477 goto out; 11478 11479 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_1, 0x2144); 11480 if (ret_val) 11481 goto out; 11482 11483 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_2, 0x0C28); 11484 if (ret_val) 11485 goto out; 11486 11487 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_1, 0x2146); 11488 if (ret_val) 11489 goto out; 11490 11491 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_2, 0xB233); 11492 if (ret_val) 11493 goto out; 11494 11495 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_1, 0x214D); 11496 if (ret_val) 11497 goto out; 11498 11499 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_2, 0xCC0C); 11500 if (ret_val) 11501 goto out; 11502 11503 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_1, 0x2159); 11504 if (ret_val) 11505 goto out; 11506 11507 /* Switch to PHY page 0xFB. */ 11508 ret_val = em_write_phy_reg(hw, M88E1543_PAGE_ADDR, 0x00FB); 11509 if (ret_val) 11510 goto out; 11511 11512 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_3, 0x000D); 11513 if (ret_val) 11514 goto out; 11515 11516 /* Switch to PHY page 0x12. */ 11517 ret_val = em_write_phy_reg(hw, M88E1543_PAGE_ADDR, 0x12); 11518 if (ret_val) 11519 goto out; 11520 11521 /* Change mode to SGMII-to-Copper */ 11522 ret_val = em_write_phy_reg(hw, M88E1512_MODE, 0x8001); 11523 if (ret_val) 11524 goto out; 11525 11526 /* Return the PHY to page 0. */ 11527 ret_val = em_write_phy_reg(hw, M88E1543_PAGE_ADDR, 0); 11528 if (ret_val) 11529 goto out; 11530 11531 ret_val = em_phy_hw_reset(hw); 11532 if (ret_val) { 11533 DEBUGOUT("Error committing the PHY changes\n"); 11534 return ret_val; 11535 } 11536 11537 msec_delay(1000); 11538 out: 11539 return ret_val; 11540 } 11541 11542 uint32_t 11543 em_translate_82542_register(uint32_t reg) 11544 { 11545 /* 11546 * Some of the 82542 registers are located at different 11547 * offsets than they are in newer adapters. 11548 * Despite the difference in location, the registers 11549 * function in the same manner. 11550 */ 11551 switch (reg) { 11552 case E1000_RA: 11553 reg = 0x00040; 11554 break; 11555 case E1000_RDTR: 11556 reg = 0x00108; 11557 break; 11558 case E1000_RDBAL(0): 11559 reg = 0x00110; 11560 break; 11561 case E1000_RDBAH(0): 11562 reg = 0x00114; 11563 break; 11564 case E1000_RDLEN(0): 11565 reg = 0x00118; 11566 break; 11567 case E1000_RDH(0): 11568 reg = 0x00120; 11569 break; 11570 case E1000_RDT(0): 11571 reg = 0x00128; 11572 break; 11573 case E1000_RDBAL(1): 11574 reg = 0x00138; 11575 break; 11576 case E1000_RDBAH(1): 11577 reg = 0x0013C; 11578 break; 11579 case E1000_RDLEN(1): 11580 reg = 0x00140; 11581 break; 11582 case E1000_RDH(1): 11583 reg = 0x00148; 11584 break; 11585 case E1000_RDT(1): 11586 reg = 0x00150; 11587 break; 11588 case E1000_FCRTH: 11589 reg = 0x00160; 11590 break; 11591 case E1000_FCRTL: 11592 reg = 0x00168; 11593 break; 11594 case E1000_MTA: 11595 reg = 0x00200; 11596 break; 11597 case E1000_TDBAL(0): 11598 reg = 0x00420; 11599 break; 11600 case E1000_TDBAH(0): 11601 reg = 0x00424; 11602 break; 11603 case E1000_TDLEN(0): 11604 reg = 0x00428; 11605 break; 11606 case E1000_TDH(0): 11607 reg = 0x00430; 11608 break; 11609 case E1000_TDT(0): 11610 reg = 0x00438; 11611 break; 11612 case E1000_TIDV: 11613 reg = 0x00440; 11614 break; 11615 case E1000_VFTA: 11616 reg = 0x00600; 11617 break; 11618 case E1000_TDFH: 11619 reg = 0x08010; 11620 break; 11621 case E1000_TDFT: 11622 reg = 0x08018; 11623 break; 11624 default: 11625 break; 11626 } 11627 11628 return (reg); 11629 } 11630