1 /******************************************************************************* 2 3 Copyright (c) 2001-2005, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 *******************************************************************************/ 33 34 /* $OpenBSD: if_em_hw.c,v 1.116 2022/06/23 09:47:04 jsg Exp $ */ 35 /* 36 * if_em_hw.c Shared functions for accessing and configuring the MAC 37 */ 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/sockio.h> 42 #include <sys/mbuf.h> 43 #include <sys/malloc.h> 44 #include <sys/kernel.h> 45 #include <sys/device.h> 46 #include <sys/socket.h> 47 #include <sys/kstat.h> 48 49 #include <net/if.h> 50 #include <net/if_media.h> 51 52 #include <netinet/in.h> 53 #include <netinet/if_ether.h> 54 55 #include <uvm/uvm_extern.h> 56 57 #include <dev/pci/pcireg.h> 58 #include <dev/pci/pcivar.h> 59 60 #include <dev/pci/if_em.h> 61 #include <dev/pci/if_em_hw.h> 62 #include <dev/pci/if_em_soc.h> 63 64 #include <dev/mii/rgephyreg.h> 65 66 #define STATIC 67 68 static int32_t em_swfw_sync_acquire(struct em_hw *, uint16_t); 69 static void em_swfw_sync_release(struct em_hw *, uint16_t); 70 static int32_t em_read_kmrn_reg(struct em_hw *, uint32_t, uint16_t *); 71 static int32_t em_write_kmrn_reg(struct em_hw *hw, uint32_t, uint16_t); 72 static int32_t em_get_software_semaphore(struct em_hw *); 73 static void em_release_software_semaphore(struct em_hw *); 74 75 static int32_t em_check_downshift(struct em_hw *); 76 static void em_clear_vfta(struct em_hw *); 77 void em_clear_vfta_i350(struct em_hw *); 78 static int32_t em_commit_shadow_ram(struct em_hw *); 79 static int32_t em_config_dsp_after_link_change(struct em_hw *, boolean_t); 80 static int32_t em_config_fc_after_link_up(struct em_hw *); 81 static int32_t em_match_gig_phy(struct em_hw *); 82 static int32_t em_detect_gig_phy(struct em_hw *); 83 static int32_t em_erase_ich8_4k_segment(struct em_hw *, uint32_t); 84 static int32_t em_get_auto_rd_done(struct em_hw *); 85 static int32_t em_get_cable_length(struct em_hw *, uint16_t *, uint16_t *); 86 static int32_t em_get_hw_eeprom_semaphore(struct em_hw *); 87 static int32_t em_get_phy_cfg_done(struct em_hw *); 88 static int32_t em_get_software_flag(struct em_hw *); 89 static int32_t em_ich8_cycle_init(struct em_hw *); 90 static int32_t em_ich8_flash_cycle(struct em_hw *, uint32_t); 91 static int32_t em_id_led_init(struct em_hw *); 92 static int32_t em_init_lcd_from_nvm_config_region(struct em_hw *, uint32_t, 93 uint32_t); 94 static int32_t em_init_lcd_from_nvm(struct em_hw *); 95 static int32_t em_phy_no_cable_workaround(struct em_hw *); 96 static void em_init_rx_addrs(struct em_hw *); 97 static void em_initialize_hardware_bits(struct em_softc *); 98 static void em_toggle_lanphypc_pch_lpt(struct em_hw *); 99 static int em_disable_ulp_lpt_lp(struct em_hw *hw, bool force); 100 static boolean_t em_is_onboard_nvm_eeprom(struct em_hw *); 101 static int32_t em_kumeran_lock_loss_workaround(struct em_hw *); 102 static int32_t em_mng_enable_host_if(struct em_hw *); 103 static int32_t em_read_eeprom_eerd(struct em_hw *, uint16_t, uint16_t, 104 uint16_t *); 105 static int32_t em_write_eeprom_eewr(struct em_hw *, uint16_t, uint16_t, 106 uint16_t *data); 107 static int32_t em_poll_eerd_eewr_done(struct em_hw *, int); 108 static void em_put_hw_eeprom_semaphore(struct em_hw *); 109 static int32_t em_read_ich8_byte(struct em_hw *, uint32_t, uint8_t *); 110 static int32_t em_verify_write_ich8_byte(struct em_hw *, uint32_t, uint8_t); 111 static int32_t em_write_ich8_byte(struct em_hw *, uint32_t, uint8_t); 112 static int32_t em_read_ich8_word(struct em_hw *, uint32_t, uint16_t *); 113 static int32_t em_read_ich8_dword(struct em_hw *, uint32_t, uint32_t *); 114 static int32_t em_read_ich8_data(struct em_hw *, uint32_t, uint32_t, 115 uint16_t *); 116 static int32_t em_write_ich8_data(struct em_hw *, uint32_t, uint32_t, 117 uint16_t); 118 static int32_t em_read_eeprom_ich8(struct em_hw *, uint16_t, uint16_t, 119 uint16_t *); 120 static int32_t em_write_eeprom_ich8(struct em_hw *, uint16_t, uint16_t, 121 uint16_t *); 122 static int32_t em_read_invm_i210(struct em_hw *, uint16_t, uint16_t, 123 uint16_t *); 124 static int32_t em_read_invm_word_i210(struct em_hw *, uint16_t, uint16_t *); 125 static void em_release_software_flag(struct em_hw *); 126 static int32_t em_set_d3_lplu_state(struct em_hw *, boolean_t); 127 static int32_t em_set_d0_lplu_state(struct em_hw *, boolean_t); 128 static int32_t em_set_lplu_state_pchlan(struct em_hw *, boolean_t); 129 static int32_t em_set_pci_ex_no_snoop(struct em_hw *, uint32_t); 130 static void em_set_pci_express_master_disable(struct em_hw *); 131 static int32_t em_wait_autoneg(struct em_hw *); 132 static void em_write_reg_io(struct em_hw *, uint32_t, uint32_t); 133 static int32_t em_set_phy_type(struct em_hw *); 134 static void em_phy_init_script(struct em_hw *); 135 static int32_t em_setup_copper_link(struct em_hw *); 136 static int32_t em_setup_fiber_serdes_link(struct em_hw *); 137 static int32_t em_adjust_serdes_amplitude(struct em_hw *); 138 static int32_t em_phy_force_speed_duplex(struct em_hw *); 139 static int32_t em_config_mac_to_phy(struct em_hw *); 140 static void em_raise_mdi_clk(struct em_hw *, uint32_t *); 141 static void em_lower_mdi_clk(struct em_hw *, uint32_t *); 142 static void em_shift_out_mdi_bits(struct em_hw *, uint32_t, uint16_t); 143 static uint16_t em_shift_in_mdi_bits(struct em_hw *); 144 static int32_t em_phy_reset_dsp(struct em_hw *); 145 static int32_t em_write_eeprom_spi(struct em_hw *, uint16_t, uint16_t, 146 uint16_t *); 147 static int32_t em_write_eeprom_microwire(struct em_hw *, uint16_t, uint16_t, 148 uint16_t *); 149 static int32_t em_spi_eeprom_ready(struct em_hw *); 150 static void em_raise_ee_clk(struct em_hw *, uint32_t *); 151 static void em_lower_ee_clk(struct em_hw *, uint32_t *); 152 static void em_shift_out_ee_bits(struct em_hw *, uint16_t, uint16_t); 153 static int32_t em_write_phy_reg_ex(struct em_hw *, uint32_t, uint16_t); 154 static int32_t em_read_phy_reg_ex(struct em_hw *, uint32_t, uint16_t *); 155 static uint16_t em_shift_in_ee_bits(struct em_hw *, uint16_t); 156 static int32_t em_acquire_eeprom(struct em_hw *); 157 static void em_release_eeprom(struct em_hw *); 158 static void em_standby_eeprom(struct em_hw *); 159 static int32_t em_set_vco_speed(struct em_hw *); 160 static int32_t em_polarity_reversal_workaround(struct em_hw *); 161 static int32_t em_set_phy_mode(struct em_hw *); 162 static int32_t em_host_if_read_cookie(struct em_hw *, uint8_t *); 163 static uint8_t em_calculate_mng_checksum(char *, uint32_t); 164 static int32_t em_configure_kmrn_for_10_100(struct em_hw *, uint16_t); 165 static int32_t em_configure_kmrn_for_1000(struct em_hw *); 166 static int32_t em_set_pciex_completion_timeout(struct em_hw *hw); 167 static int32_t em_set_mdio_slow_mode_hv(struct em_hw *); 168 int32_t em_hv_phy_workarounds_ich8lan(struct em_hw *); 169 int32_t em_lv_phy_workarounds_ich8lan(struct em_hw *); 170 int32_t em_link_stall_workaround_hv(struct em_hw *); 171 int32_t em_k1_gig_workaround_hv(struct em_hw *, boolean_t); 172 int32_t em_k1_workaround_lv(struct em_hw *); 173 int32_t em_k1_workaround_lpt_lp(struct em_hw *, boolean_t); 174 int32_t em_configure_k1_ich8lan(struct em_hw *, boolean_t); 175 void em_gate_hw_phy_config_ich8lan(struct em_hw *, boolean_t); 176 int32_t em_access_phy_wakeup_reg_bm(struct em_hw *, uint32_t, 177 uint16_t *, boolean_t); 178 int32_t em_access_phy_debug_regs_hv(struct em_hw *, uint32_t, 179 uint16_t *, boolean_t); 180 int32_t em_access_phy_reg_hv(struct em_hw *, uint32_t, uint16_t *, 181 boolean_t); 182 int32_t em_oem_bits_config_pchlan(struct em_hw *, boolean_t); 183 void em_power_up_serdes_link_82575(struct em_hw *); 184 int32_t em_get_pcs_speed_and_duplex_82575(struct em_hw *, uint16_t *, 185 uint16_t *); 186 int32_t em_set_eee_i350(struct em_hw *); 187 int32_t em_set_eee_pchlan(struct em_hw *); 188 int32_t em_valid_nvm_bank_detect_ich8lan(struct em_hw *, uint32_t *); 189 int32_t em_initialize_M88E1512_phy(struct em_hw *); 190 191 /* IGP cable length table */ 192 static const uint16_t 193 em_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = 194 {5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 195 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25, 196 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40, 197 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60, 198 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90, 199 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 200 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 201 110, 202 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 203 120}; 204 205 static const uint16_t 206 em_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] = 207 {0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 208 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 209 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 210 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 211 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 212 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 213 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 214 121, 124}; 215 216 /****************************************************************************** 217 * Set the phy type member in the hw struct. 218 * 219 * hw - Struct containing variables accessed by shared code 220 *****************************************************************************/ 221 STATIC int32_t 222 em_set_phy_type(struct em_hw *hw) 223 { 224 DEBUGFUNC("em_set_phy_type"); 225 226 if (hw->mac_type == em_undefined) 227 return -E1000_ERR_PHY_TYPE; 228 229 switch (hw->phy_id) { 230 case M88E1000_E_PHY_ID: 231 case M88E1000_I_PHY_ID: 232 case M88E1011_I_PHY_ID: 233 case M88E1111_I_PHY_ID: 234 case M88E1112_E_PHY_ID: 235 case M88E1543_E_PHY_ID: 236 case M88E1512_E_PHY_ID: 237 case I210_I_PHY_ID: 238 case I347AT4_E_PHY_ID: 239 hw->phy_type = em_phy_m88; 240 break; 241 case IGP01E1000_I_PHY_ID: 242 if (hw->mac_type == em_82541 || 243 hw->mac_type == em_82541_rev_2 || 244 hw->mac_type == em_82547 || 245 hw->mac_type == em_82547_rev_2) { 246 hw->phy_type = em_phy_igp; 247 break; 248 } 249 case IGP03E1000_E_PHY_ID: 250 case IGP04E1000_E_PHY_ID: 251 hw->phy_type = em_phy_igp_3; 252 break; 253 case IFE_E_PHY_ID: 254 case IFE_PLUS_E_PHY_ID: 255 case IFE_C_E_PHY_ID: 256 hw->phy_type = em_phy_ife; 257 break; 258 case M88E1141_E_PHY_ID: 259 hw->phy_type = em_phy_oem; 260 break; 261 case I82577_E_PHY_ID: 262 hw->phy_type = em_phy_82577; 263 break; 264 case I82578_E_PHY_ID: 265 hw->phy_type = em_phy_82578; 266 break; 267 case I82579_E_PHY_ID: 268 hw->phy_type = em_phy_82579; 269 break; 270 case I217_E_PHY_ID: 271 hw->phy_type = em_phy_i217; 272 break; 273 case I82580_I_PHY_ID: 274 case I350_I_PHY_ID: 275 hw->phy_type = em_phy_82580; 276 break; 277 case RTL8211_E_PHY_ID: 278 hw->phy_type = em_phy_rtl8211; 279 break; 280 case BME1000_E_PHY_ID: 281 if (hw->phy_revision == 1) { 282 hw->phy_type = em_phy_bm; 283 break; 284 } 285 /* FALLTHROUGH */ 286 case GG82563_E_PHY_ID: 287 if (hw->mac_type == em_80003es2lan) { 288 hw->phy_type = em_phy_gg82563; 289 break; 290 } 291 /* FALLTHROUGH */ 292 default: 293 /* Should never have loaded on this device */ 294 hw->phy_type = em_phy_undefined; 295 return -E1000_ERR_PHY_TYPE; 296 } 297 298 return E1000_SUCCESS; 299 } 300 301 /****************************************************************************** 302 * IGP phy init script - initializes the GbE PHY 303 * 304 * hw - Struct containing variables accessed by shared code 305 *****************************************************************************/ 306 static void 307 em_phy_init_script(struct em_hw *hw) 308 { 309 uint16_t phy_saved_data; 310 DEBUGFUNC("em_phy_init_script"); 311 312 if (hw->phy_init_script) { 313 msec_delay(20); 314 /* 315 * Save off the current value of register 0x2F5B to be 316 * restored at the end of this routine. 317 */ 318 em_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 319 320 /* Disabled the PHY transmitter */ 321 em_write_phy_reg(hw, 0x2F5B, 0x0003); 322 msec_delay(20); 323 em_write_phy_reg(hw, 0x0000, 0x0140); 324 msec_delay(5); 325 326 switch (hw->mac_type) { 327 case em_82541: 328 case em_82547: 329 em_write_phy_reg(hw, 0x1F95, 0x0001); 330 em_write_phy_reg(hw, 0x1F71, 0xBD21); 331 em_write_phy_reg(hw, 0x1F79, 0x0018); 332 em_write_phy_reg(hw, 0x1F30, 0x1600); 333 em_write_phy_reg(hw, 0x1F31, 0x0014); 334 em_write_phy_reg(hw, 0x1F32, 0x161C); 335 em_write_phy_reg(hw, 0x1F94, 0x0003); 336 em_write_phy_reg(hw, 0x1F96, 0x003F); 337 em_write_phy_reg(hw, 0x2010, 0x0008); 338 break; 339 case em_82541_rev_2: 340 case em_82547_rev_2: 341 em_write_phy_reg(hw, 0x1F73, 0x0099); 342 break; 343 default: 344 break; 345 } 346 347 em_write_phy_reg(hw, 0x0000, 0x3300); 348 msec_delay(20); 349 350 /* Now enable the transmitter */ 351 em_write_phy_reg(hw, 0x2F5B, phy_saved_data); 352 353 if (hw->mac_type == em_82547) { 354 uint16_t fused, fine, coarse; 355 /* Move to analog registers page */ 356 em_read_phy_reg(hw, 357 IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused); 358 359 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { 360 em_read_phy_reg(hw, 361 IGP01E1000_ANALOG_FUSE_STATUS, &fused); 362 363 fine = fused & 364 IGP01E1000_ANALOG_FUSE_FINE_MASK; 365 coarse = fused & 366 IGP01E1000_ANALOG_FUSE_COARSE_MASK; 367 368 if (coarse > 369 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { 370 coarse -= 371 IGP01E1000_ANALOG_FUSE_COARSE_10; 372 fine -= 373 IGP01E1000_ANALOG_FUSE_FINE_1; 374 } else if (coarse == 375 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) 376 fine -= IGP01E1000_ANALOG_FUSE_FINE_10; 377 378 fused = (fused & 379 IGP01E1000_ANALOG_FUSE_POLY_MASK) | 380 (fine & 381 IGP01E1000_ANALOG_FUSE_FINE_MASK) | 382 (coarse & 383 IGP01E1000_ANALOG_FUSE_COARSE_MASK); 384 385 em_write_phy_reg(hw, 386 IGP01E1000_ANALOG_FUSE_CONTROL, 387 fused); 388 389 em_write_phy_reg(hw, 390 IGP01E1000_ANALOG_FUSE_BYPASS, 391 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL); 392 } 393 } 394 } 395 } 396 397 /****************************************************************************** 398 * Set the mac type member in the hw struct. 399 * 400 * hw - Struct containing variables accessed by shared code 401 *****************************************************************************/ 402 int32_t 403 em_set_mac_type(struct em_hw *hw) 404 { 405 DEBUGFUNC("em_set_mac_type"); 406 407 switch (hw->device_id) { 408 case E1000_DEV_ID_82542: 409 switch (hw->revision_id) { 410 case E1000_82542_2_0_REV_ID: 411 hw->mac_type = em_82542_rev2_0; 412 break; 413 case E1000_82542_2_1_REV_ID: 414 hw->mac_type = em_82542_rev2_1; 415 break; 416 default: 417 /* Invalid 82542 revision ID */ 418 return -E1000_ERR_MAC_TYPE; 419 } 420 break; 421 case E1000_DEV_ID_82543GC_FIBER: 422 case E1000_DEV_ID_82543GC_COPPER: 423 hw->mac_type = em_82543; 424 break; 425 case E1000_DEV_ID_82544EI_COPPER: 426 case E1000_DEV_ID_82544EI_FIBER: 427 case E1000_DEV_ID_82544GC_COPPER: 428 case E1000_DEV_ID_82544GC_LOM: 429 hw->mac_type = em_82544; 430 break; 431 case E1000_DEV_ID_82540EM: 432 case E1000_DEV_ID_82540EM_LOM: 433 case E1000_DEV_ID_82540EP: 434 case E1000_DEV_ID_82540EP_LOM: 435 case E1000_DEV_ID_82540EP_LP: 436 hw->mac_type = em_82540; 437 break; 438 case E1000_DEV_ID_82545EM_COPPER: 439 case E1000_DEV_ID_82545EM_FIBER: 440 hw->mac_type = em_82545; 441 break; 442 case E1000_DEV_ID_82545GM_COPPER: 443 case E1000_DEV_ID_82545GM_FIBER: 444 case E1000_DEV_ID_82545GM_SERDES: 445 hw->mac_type = em_82545_rev_3; 446 break; 447 case E1000_DEV_ID_82546EB_COPPER: 448 case E1000_DEV_ID_82546EB_FIBER: 449 case E1000_DEV_ID_82546EB_QUAD_COPPER: 450 hw->mac_type = em_82546; 451 break; 452 case E1000_DEV_ID_82546GB_COPPER: 453 case E1000_DEV_ID_82546GB_FIBER: 454 case E1000_DEV_ID_82546GB_SERDES: 455 case E1000_DEV_ID_82546GB_PCIE: 456 case E1000_DEV_ID_82546GB_QUAD_COPPER: 457 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 458 case E1000_DEV_ID_82546GB_2: 459 hw->mac_type = em_82546_rev_3; 460 break; 461 case E1000_DEV_ID_82541EI: 462 case E1000_DEV_ID_82541EI_MOBILE: 463 case E1000_DEV_ID_82541ER_LOM: 464 hw->mac_type = em_82541; 465 break; 466 case E1000_DEV_ID_82541ER: 467 case E1000_DEV_ID_82541GI: 468 case E1000_DEV_ID_82541GI_LF: 469 case E1000_DEV_ID_82541GI_MOBILE: 470 hw->mac_type = em_82541_rev_2; 471 break; 472 case E1000_DEV_ID_82547EI: 473 case E1000_DEV_ID_82547EI_MOBILE: 474 hw->mac_type = em_82547; 475 break; 476 case E1000_DEV_ID_82547GI: 477 hw->mac_type = em_82547_rev_2; 478 break; 479 case E1000_DEV_ID_82571EB_AF: 480 case E1000_DEV_ID_82571EB_AT: 481 case E1000_DEV_ID_82571EB_COPPER: 482 case E1000_DEV_ID_82571EB_FIBER: 483 case E1000_DEV_ID_82571EB_SERDES: 484 case E1000_DEV_ID_82571EB_QUAD_COPPER: 485 case E1000_DEV_ID_82571EB_QUAD_FIBER: 486 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 487 case E1000_DEV_ID_82571EB_SERDES_DUAL: 488 case E1000_DEV_ID_82571EB_SERDES_QUAD: 489 case E1000_DEV_ID_82571PT_QUAD_COPPER: 490 hw->mac_type = em_82571; 491 break; 492 case E1000_DEV_ID_82572EI_COPPER: 493 case E1000_DEV_ID_82572EI_FIBER: 494 case E1000_DEV_ID_82572EI_SERDES: 495 case E1000_DEV_ID_82572EI: 496 hw->mac_type = em_82572; 497 break; 498 case E1000_DEV_ID_82573E: 499 case E1000_DEV_ID_82573E_IAMT: 500 case E1000_DEV_ID_82573E_PM: 501 case E1000_DEV_ID_82573L: 502 case E1000_DEV_ID_82573L_PL_1: 503 case E1000_DEV_ID_82573L_PL_2: 504 case E1000_DEV_ID_82573V_PM: 505 hw->mac_type = em_82573; 506 break; 507 case E1000_DEV_ID_82574L: 508 case E1000_DEV_ID_82574LA: 509 case E1000_DEV_ID_82583V: 510 hw->mac_type = em_82574; 511 break; 512 case E1000_DEV_ID_82575EB_PT: 513 case E1000_DEV_ID_82575EB_PF: 514 case E1000_DEV_ID_82575GB_QP: 515 case E1000_DEV_ID_82575GB_QP_PM: 516 hw->mac_type = em_82575; 517 hw->initialize_hw_bits_disable = 1; 518 break; 519 case E1000_DEV_ID_82576: 520 case E1000_DEV_ID_82576_FIBER: 521 case E1000_DEV_ID_82576_SERDES: 522 case E1000_DEV_ID_82576_QUAD_COPPER: 523 case E1000_DEV_ID_82576_QUAD_CU_ET2: 524 case E1000_DEV_ID_82576_NS: 525 case E1000_DEV_ID_82576_NS_SERDES: 526 case E1000_DEV_ID_82576_SERDES_QUAD: 527 hw->mac_type = em_82576; 528 hw->initialize_hw_bits_disable = 1; 529 break; 530 case E1000_DEV_ID_82580_COPPER: 531 case E1000_DEV_ID_82580_FIBER: 532 case E1000_DEV_ID_82580_QUAD_FIBER: 533 case E1000_DEV_ID_82580_SERDES: 534 case E1000_DEV_ID_82580_SGMII: 535 case E1000_DEV_ID_82580_COPPER_DUAL: 536 case E1000_DEV_ID_DH89XXCC_SGMII: 537 case E1000_DEV_ID_DH89XXCC_SERDES: 538 case E1000_DEV_ID_DH89XXCC_BACKPLANE: 539 case E1000_DEV_ID_DH89XXCC_SFP: 540 hw->mac_type = em_82580; 541 hw->initialize_hw_bits_disable = 1; 542 break; 543 case E1000_DEV_ID_I210_COPPER: 544 case E1000_DEV_ID_I210_COPPER_OEM1: 545 case E1000_DEV_ID_I210_COPPER_IT: 546 case E1000_DEV_ID_I210_FIBER: 547 case E1000_DEV_ID_I210_SERDES: 548 case E1000_DEV_ID_I210_SGMII: 549 case E1000_DEV_ID_I210_COPPER_FLASHLESS: 550 case E1000_DEV_ID_I210_SERDES_FLASHLESS: 551 case E1000_DEV_ID_I211_COPPER: 552 hw->mac_type = em_i210; 553 hw->initialize_hw_bits_disable = 1; 554 hw->eee_enable = 1; 555 break; 556 case E1000_DEV_ID_I350_COPPER: 557 case E1000_DEV_ID_I350_FIBER: 558 case E1000_DEV_ID_I350_SERDES: 559 case E1000_DEV_ID_I350_SGMII: 560 case E1000_DEV_ID_I350_DA4: 561 case E1000_DEV_ID_I354_BACKPLANE_1GBPS: 562 case E1000_DEV_ID_I354_SGMII: 563 case E1000_DEV_ID_I354_BACKPLANE_2_5GBPS: 564 hw->mac_type = em_i350; 565 hw->initialize_hw_bits_disable = 1; 566 hw->eee_enable = 1; 567 break; 568 case E1000_DEV_ID_80003ES2LAN_COPPER_SPT: 569 case E1000_DEV_ID_80003ES2LAN_SERDES_SPT: 570 case E1000_DEV_ID_80003ES2LAN_COPPER_DPT: 571 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: 572 hw->mac_type = em_80003es2lan; 573 break; 574 case E1000_DEV_ID_ICH8_IFE: 575 case E1000_DEV_ID_ICH8_IFE_G: 576 case E1000_DEV_ID_ICH8_IFE_GT: 577 case E1000_DEV_ID_ICH8_IGP_AMT: 578 case E1000_DEV_ID_ICH8_IGP_C: 579 case E1000_DEV_ID_ICH8_IGP_M: 580 case E1000_DEV_ID_ICH8_IGP_M_AMT: 581 case E1000_DEV_ID_ICH8_82567V_3: 582 hw->mac_type = em_ich8lan; 583 break; 584 case E1000_DEV_ID_ICH9_BM: 585 case E1000_DEV_ID_ICH9_IFE: 586 case E1000_DEV_ID_ICH9_IFE_G: 587 case E1000_DEV_ID_ICH9_IFE_GT: 588 case E1000_DEV_ID_ICH9_IGP_AMT: 589 case E1000_DEV_ID_ICH9_IGP_C: 590 case E1000_DEV_ID_ICH9_IGP_M: 591 case E1000_DEV_ID_ICH9_IGP_M_AMT: 592 case E1000_DEV_ID_ICH9_IGP_M_V: 593 case E1000_DEV_ID_ICH10_R_BM_LF: 594 case E1000_DEV_ID_ICH10_R_BM_LM: 595 case E1000_DEV_ID_ICH10_R_BM_V: 596 hw->mac_type = em_ich9lan; 597 break; 598 case E1000_DEV_ID_ICH10_D_BM_LF: 599 case E1000_DEV_ID_ICH10_D_BM_LM: 600 case E1000_DEV_ID_ICH10_D_BM_V: 601 hw->mac_type = em_ich10lan; 602 break; 603 case E1000_DEV_ID_PCH_M_HV_LC: 604 case E1000_DEV_ID_PCH_M_HV_LM: 605 case E1000_DEV_ID_PCH_D_HV_DC: 606 case E1000_DEV_ID_PCH_D_HV_DM: 607 hw->mac_type = em_pchlan; 608 hw->eee_enable = 1; 609 break; 610 case E1000_DEV_ID_PCH2_LV_LM: 611 case E1000_DEV_ID_PCH2_LV_V: 612 hw->mac_type = em_pch2lan; 613 break; 614 case E1000_DEV_ID_PCH_LPT_I217_LM: 615 case E1000_DEV_ID_PCH_LPT_I217_V: 616 case E1000_DEV_ID_PCH_LPTLP_I218_LM: 617 case E1000_DEV_ID_PCH_LPTLP_I218_V: 618 case E1000_DEV_ID_PCH_I218_LM2: 619 case E1000_DEV_ID_PCH_I218_V2: 620 case E1000_DEV_ID_PCH_I218_LM3: 621 case E1000_DEV_ID_PCH_I218_V3: 622 hw->mac_type = em_pch_lpt; 623 break; 624 case E1000_DEV_ID_PCH_SPT_I219_LM: 625 case E1000_DEV_ID_PCH_SPT_I219_V: 626 case E1000_DEV_ID_PCH_SPT_I219_LM2: 627 case E1000_DEV_ID_PCH_SPT_I219_V2: 628 case E1000_DEV_ID_PCH_LBG_I219_LM3: 629 case E1000_DEV_ID_PCH_SPT_I219_LM4: 630 case E1000_DEV_ID_PCH_SPT_I219_V4: 631 case E1000_DEV_ID_PCH_SPT_I219_LM5: 632 case E1000_DEV_ID_PCH_SPT_I219_V5: 633 case E1000_DEV_ID_PCH_CMP_I219_LM12: 634 case E1000_DEV_ID_PCH_CMP_I219_V12: 635 hw->mac_type = em_pch_spt; 636 break; 637 case E1000_DEV_ID_PCH_CNP_I219_LM6: 638 case E1000_DEV_ID_PCH_CNP_I219_V6: 639 case E1000_DEV_ID_PCH_CNP_I219_LM7: 640 case E1000_DEV_ID_PCH_CNP_I219_V7: 641 case E1000_DEV_ID_PCH_ICP_I219_LM8: 642 case E1000_DEV_ID_PCH_ICP_I219_V8: 643 case E1000_DEV_ID_PCH_ICP_I219_LM9: 644 case E1000_DEV_ID_PCH_ICP_I219_V9: 645 case E1000_DEV_ID_PCH_CMP_I219_LM10: 646 case E1000_DEV_ID_PCH_CMP_I219_V10: 647 case E1000_DEV_ID_PCH_CMP_I219_LM11: 648 case E1000_DEV_ID_PCH_CMP_I219_V11: 649 hw->mac_type = em_pch_cnp; 650 break; 651 case E1000_DEV_ID_PCH_TGP_I219_LM13: 652 case E1000_DEV_ID_PCH_TGP_I219_V13: 653 case E1000_DEV_ID_PCH_TGP_I219_LM14: 654 case E1000_DEV_ID_PCH_TGP_I219_V14: 655 case E1000_DEV_ID_PCH_TGP_I219_LM15: 656 case E1000_DEV_ID_PCH_TGP_I219_V15: 657 hw->mac_type = em_pch_tgp; 658 break; 659 case E1000_DEV_ID_PCH_ADP_I219_LM16: 660 case E1000_DEV_ID_PCH_ADP_I219_V16: 661 case E1000_DEV_ID_PCH_ADP_I219_LM17: 662 case E1000_DEV_ID_PCH_ADP_I219_V17: 663 case E1000_DEV_ID_PCH_MTP_I219_LM18: 664 case E1000_DEV_ID_PCH_MTP_I219_V18: 665 case E1000_DEV_ID_PCH_MTP_I219_LM19: 666 case E1000_DEV_ID_PCH_MTP_I219_V19: 667 hw->mac_type = em_pch_adp; 668 break; 669 case E1000_DEV_ID_EP80579_LAN_1: 670 hw->mac_type = em_icp_xxxx; 671 hw->icp_xxxx_port_num = 0; 672 break; 673 case E1000_DEV_ID_EP80579_LAN_2: 674 case E1000_DEV_ID_EP80579_LAN_4: 675 hw->mac_type = em_icp_xxxx; 676 hw->icp_xxxx_port_num = 1; 677 break; 678 case E1000_DEV_ID_EP80579_LAN_3: 679 case E1000_DEV_ID_EP80579_LAN_5: 680 hw->mac_type = em_icp_xxxx; 681 hw->icp_xxxx_port_num = 2; 682 break; 683 case E1000_DEV_ID_EP80579_LAN_6: 684 hw->mac_type = em_icp_xxxx; 685 hw->icp_xxxx_port_num = 3; 686 break; 687 default: 688 /* Should never have loaded on this device */ 689 return -E1000_ERR_MAC_TYPE; 690 } 691 692 switch (hw->mac_type) { 693 case em_ich8lan: 694 case em_ich9lan: 695 case em_ich10lan: 696 case em_pchlan: 697 case em_pch2lan: 698 case em_pch_lpt: 699 case em_pch_spt: 700 case em_pch_cnp: 701 case em_pch_tgp: 702 case em_pch_adp: 703 hw->swfwhw_semaphore_present = TRUE; 704 hw->asf_firmware_present = TRUE; 705 break; 706 case em_80003es2lan: 707 case em_82575: 708 case em_82576: 709 case em_82580: 710 case em_i210: 711 case em_i350: 712 hw->swfw_sync_present = TRUE; 713 /* FALLTHROUGH */ 714 case em_82571: 715 case em_82572: 716 case em_82573: 717 case em_82574: 718 hw->eeprom_semaphore_present = TRUE; 719 /* FALLTHROUGH */ 720 case em_82541: 721 case em_82547: 722 case em_82541_rev_2: 723 case em_82547_rev_2: 724 hw->asf_firmware_present = TRUE; 725 break; 726 default: 727 break; 728 } 729 730 return E1000_SUCCESS; 731 } 732 733 /** 734 * em_set_sfp_media_type_82575 - derives SFP module media type. 735 * @hw: pointer to the HW structure 736 * 737 * The media type is chosen based on SFP module. 738 * compatibility flags retrieved from SFP ID EEPROM. 739 **/ 740 STATIC int32_t em_set_sfp_media_type_82575(struct em_hw *hw) 741 { 742 struct sfp_e1000_flags eth_flags; 743 int32_t ret_val = E1000_ERR_CONFIG; 744 uint32_t ctrl_ext = 0; 745 uint8_t transceiver_type = 0; 746 int32_t timeout = 3; 747 748 /* Turn I2C interface ON and power on sfp cage */ 749 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 750 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA; 751 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA); 752 753 E1000_WRITE_FLUSH(hw); 754 755 /* Read SFP module data */ 756 while (timeout) { 757 ret_val = em_read_sfp_data_byte(hw, 758 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET), 759 &transceiver_type); 760 if (ret_val == E1000_SUCCESS) 761 break; 762 msec_delay(100); 763 timeout--; 764 } 765 if (ret_val != E1000_SUCCESS) 766 goto out; 767 768 ret_val = em_read_sfp_data_byte(hw, 769 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET), 770 (uint8_t *)ð_flags); 771 if (ret_val != E1000_SUCCESS) 772 goto out; 773 774 /* Check if there is some SFP module plugged and powered */ 775 if ((transceiver_type == E1000_SFF_IDENTIFIER_SFP) || 776 (transceiver_type == E1000_SFF_IDENTIFIER_SFF)) { 777 if (eth_flags.e1000_base_lx || eth_flags.e1000_base_sx) { 778 hw->media_type = em_media_type_internal_serdes; 779 } else if (eth_flags.e100_base_fx || eth_flags.e100_base_lx) { 780 hw->media_type = em_media_type_internal_serdes; 781 hw->sgmii_active = TRUE; 782 } else if (eth_flags.e1000_base_t) { 783 hw->media_type = em_media_type_copper; 784 hw->sgmii_active = TRUE; 785 } else { 786 DEBUGOUT("PHY module has not been recognized\n"); 787 ret_val = E1000_ERR_CONFIG; 788 goto out; 789 } 790 } else { 791 ret_val = E1000_ERR_CONFIG; 792 goto out; 793 } 794 ret_val = E1000_SUCCESS; 795 out: 796 /* Restore I2C interface setting */ 797 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 798 return ret_val; 799 } 800 801 802 /***************************************************************************** 803 * Set media type and TBI compatibility. 804 * 805 * hw - Struct containing variables accessed by shared code 806 * **************************************************************************/ 807 void 808 em_set_media_type(struct em_hw *hw) 809 { 810 uint32_t status, ctrl_ext, mdic; 811 DEBUGFUNC("em_set_media_type"); 812 813 if (hw->mac_type != em_82543) { 814 /* tbi_compatibility is only valid on 82543 */ 815 hw->tbi_compatibility_en = FALSE; 816 } 817 818 if (hw->mac_type == em_82575 || hw->mac_type == em_82580 || 819 hw->mac_type == em_82576 || 820 hw->mac_type == em_i210 || hw->mac_type == em_i350) { 821 hw->media_type = em_media_type_copper; 822 hw->sgmii_active = FALSE; 823 824 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 825 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) { 826 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: 827 hw->media_type = em_media_type_internal_serdes; 828 ctrl_ext |= E1000_CTRL_I2C_ENA; 829 break; 830 case E1000_CTRL_EXT_LINK_MODE_SGMII: 831 mdic = EM_READ_REG(hw, E1000_MDICNFG); 832 ctrl_ext |= E1000_CTRL_I2C_ENA; 833 if (mdic & E1000_MDICNFG_EXT_MDIO) { 834 hw->media_type = em_media_type_copper; 835 hw->sgmii_active = TRUE; 836 break; 837 } 838 /* FALLTHROUGH */ 839 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES: 840 ctrl_ext |= E1000_CTRL_I2C_ENA; 841 if (em_set_sfp_media_type_82575(hw) != 0) { 842 hw->media_type = em_media_type_internal_serdes; 843 if ((ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) == 844 E1000_CTRL_EXT_LINK_MODE_SGMII) { 845 hw->media_type = em_media_type_copper; 846 hw->sgmii_active = TRUE; 847 } 848 } 849 850 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK; 851 if (hw->sgmii_active) 852 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII; 853 else 854 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 855 break; 856 default: 857 ctrl_ext &= ~E1000_CTRL_I2C_ENA; 858 break; 859 } 860 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 861 return; 862 } 863 864 switch (hw->device_id) { 865 case E1000_DEV_ID_82545GM_SERDES: 866 case E1000_DEV_ID_82546GB_SERDES: 867 case E1000_DEV_ID_82571EB_SERDES: 868 case E1000_DEV_ID_82571EB_SERDES_DUAL: 869 case E1000_DEV_ID_82571EB_SERDES_QUAD: 870 case E1000_DEV_ID_82572EI_SERDES: 871 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: 872 hw->media_type = em_media_type_internal_serdes; 873 break; 874 case E1000_DEV_ID_EP80579_LAN_1: 875 case E1000_DEV_ID_EP80579_LAN_2: 876 case E1000_DEV_ID_EP80579_LAN_3: 877 case E1000_DEV_ID_EP80579_LAN_4: 878 case E1000_DEV_ID_EP80579_LAN_5: 879 case E1000_DEV_ID_EP80579_LAN_6: 880 hw->media_type = em_media_type_copper; 881 break; 882 default: 883 switch (hw->mac_type) { 884 case em_82542_rev2_0: 885 case em_82542_rev2_1: 886 hw->media_type = em_media_type_fiber; 887 break; 888 case em_ich8lan: 889 case em_ich9lan: 890 case em_ich10lan: 891 case em_pchlan: 892 case em_pch2lan: 893 case em_pch_lpt: 894 case em_pch_spt: 895 case em_pch_cnp: 896 case em_pch_tgp: 897 case em_pch_adp: 898 case em_82573: 899 case em_82574: 900 /* 901 * The STATUS_TBIMODE bit is reserved or reused for 902 * the this device. 903 */ 904 hw->media_type = em_media_type_copper; 905 break; 906 default: 907 status = E1000_READ_REG(hw, STATUS); 908 if (status & E1000_STATUS_TBIMODE) { 909 hw->media_type = em_media_type_fiber; 910 /* tbi_compatibility not valid on fiber */ 911 hw->tbi_compatibility_en = FALSE; 912 } else { 913 hw->media_type = em_media_type_copper; 914 } 915 break; 916 } 917 } 918 } 919 /****************************************************************************** 920 * Reset the transmit and receive units; mask and clear all interrupts. 921 * 922 * hw - Struct containing variables accessed by shared code 923 *****************************************************************************/ 924 int32_t 925 em_reset_hw(struct em_hw *hw) 926 { 927 uint32_t ctrl; 928 uint32_t ctrl_ext; 929 uint32_t icr; 930 uint32_t manc; 931 uint32_t led_ctrl; 932 uint32_t timeout; 933 uint32_t extcnf_ctrl; 934 int32_t ret_val; 935 DEBUGFUNC("em_reset_hw"); 936 937 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ 938 if (hw->mac_type == em_82542_rev2_0) { 939 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 940 em_pci_clear_mwi(hw); 941 } 942 if (hw->bus_type == em_bus_type_pci_express) { 943 /* 944 * Prevent the PCI-E bus from sticking if there is no TLP 945 * connection on the last TLP read/write transaction when MAC 946 * is reset. 947 */ 948 if (em_disable_pciex_master(hw) != E1000_SUCCESS) { 949 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 950 } 951 } 952 953 /* Set the completion timeout for 82575 chips */ 954 if (hw->mac_type == em_82575 || hw->mac_type == em_82580 || 955 hw->mac_type == em_82576 || 956 hw->mac_type == em_i210 || hw->mac_type == em_i350) { 957 ret_val = em_set_pciex_completion_timeout(hw); 958 if (ret_val) { 959 DEBUGOUT("PCI-E Set completion timeout has failed.\n"); 960 } 961 } 962 963 /* Clear interrupt mask to stop board from generating interrupts */ 964 DEBUGOUT("Masking off all interrupts\n"); 965 E1000_WRITE_REG(hw, IMC, 0xffffffff); 966 /* 967 * Disable the Transmit and Receive units. Then delay to allow any 968 * pending transactions to complete before we hit the MAC with the 969 * global reset. 970 */ 971 E1000_WRITE_REG(hw, RCTL, 0); 972 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP); 973 E1000_WRITE_FLUSH(hw); 974 /* 975 * The tbi_compatibility_on Flag must be cleared when Rctl is 976 * cleared. 977 */ 978 hw->tbi_compatibility_on = FALSE; 979 /* 980 * Delay to allow any outstanding PCI transactions to complete before 981 * resetting the device 982 */ 983 msec_delay(10); 984 985 ctrl = E1000_READ_REG(hw, CTRL); 986 987 /* Must reset the PHY before resetting the MAC */ 988 if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) { 989 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST)); 990 msec_delay(5); 991 } 992 /* 993 * Must acquire the MDIO ownership before MAC reset. Ownership 994 * defaults to firmware after a reset. 995 */ 996 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) { 997 timeout = 10; 998 999 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 1000 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 1001 1002 do { 1003 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); 1004 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 1005 1006 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) 1007 break; 1008 else 1009 extcnf_ctrl |= 1010 E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 1011 1012 msec_delay(2); 1013 timeout--; 1014 } while (timeout); 1015 } 1016 /* Workaround for ICH8 bit corruption issue in FIFO memory */ 1017 if (hw->mac_type == em_ich8lan) { 1018 /* Set Tx and Rx buffer allocation to 8k apiece. */ 1019 E1000_WRITE_REG(hw, PBA, E1000_PBA_8K); 1020 /* Set Packet Buffer Size to 16k. */ 1021 E1000_WRITE_REG(hw, PBS, E1000_PBS_16K); 1022 } 1023 /* 1024 * Issue a global reset to the MAC. This will reset the chip's 1025 * transmit, receive, DMA, and link units. It will not effect the 1026 * current PCI configuration. The global reset bit is self- 1027 * clearing, and should clear within a microsecond. 1028 */ 1029 DEBUGOUT("Issuing a global reset to MAC\n"); 1030 1031 switch (hw->mac_type) { 1032 case em_82544: 1033 case em_82540: 1034 case em_82545: 1035 case em_82546: 1036 case em_82541: 1037 case em_82541_rev_2: 1038 /* 1039 * These controllers can't ack the 64-bit write when issuing 1040 * the reset, so use IO-mapping as a workaround to issue the 1041 * reset 1042 */ 1043 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST)); 1044 break; 1045 case em_82545_rev_3: 1046 case em_82546_rev_3: 1047 /* Reset is performed on a shadow of the control register */ 1048 E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST)); 1049 break; 1050 case em_ich8lan: 1051 case em_ich9lan: 1052 case em_ich10lan: 1053 case em_pchlan: 1054 case em_pch2lan: 1055 case em_pch_lpt: 1056 case em_pch_spt: 1057 case em_pch_cnp: 1058 case em_pch_tgp: 1059 case em_pch_adp: 1060 if (!hw->phy_reset_disable && 1061 em_check_phy_reset_block(hw) == E1000_SUCCESS) { 1062 /* 1063 * PHY HW reset requires MAC CORE reset at the same 1064 * time to make sure the interface between MAC and 1065 * the external PHY is reset. 1066 */ 1067 ctrl |= E1000_CTRL_PHY_RST; 1068 /* 1069 * Gate automatic PHY configuration by hardware on 1070 * non-managed 82579 1071 */ 1072 if ((hw->mac_type == em_pch2lan) && 1073 !(E1000_READ_REG(hw, FWSM) & E1000_FWSM_FW_VALID)) { 1074 em_gate_hw_phy_config_ich8lan(hw, TRUE); 1075 } 1076 } 1077 em_get_software_flag(hw); 1078 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); 1079 /* HW reset releases software_flag */ 1080 hw->sw_flag = 0; 1081 msec_delay(20); 1082 1083 /* Ungate automatic PHY configuration on non-managed 82579 */ 1084 if (hw->mac_type == em_pch2lan && !hw->phy_reset_disable && 1085 !(E1000_READ_REG(hw, FWSM) & E1000_FWSM_FW_VALID)) { 1086 msec_delay(10); 1087 em_gate_hw_phy_config_ich8lan(hw, FALSE); 1088 } 1089 break; 1090 default: 1091 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); 1092 break; 1093 } 1094 1095 if (em_check_phy_reset_block(hw) == E1000_SUCCESS) { 1096 if (hw->mac_type == em_pchlan) { 1097 ret_val = em_hv_phy_workarounds_ich8lan(hw); 1098 if (ret_val) 1099 return ret_val; 1100 } 1101 else if (hw->mac_type == em_pch2lan) { 1102 ret_val = em_lv_phy_workarounds_ich8lan(hw); 1103 if (ret_val) 1104 return ret_val; 1105 } 1106 } 1107 1108 /* 1109 * After MAC reset, force reload of EEPROM to restore power-on 1110 * settings to device. Later controllers reload the EEPROM 1111 * automatically, so just wait for reload to complete. 1112 */ 1113 switch (hw->mac_type) { 1114 case em_82542_rev2_0: 1115 case em_82542_rev2_1: 1116 case em_82543: 1117 case em_82544: 1118 /* Wait for reset to complete */ 1119 usec_delay(10); 1120 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1121 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 1122 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1123 E1000_WRITE_FLUSH(hw); 1124 /* Wait for EEPROM reload */ 1125 msec_delay(2); 1126 break; 1127 case em_82541: 1128 case em_82541_rev_2: 1129 case em_82547: 1130 case em_82547_rev_2: 1131 /* Wait for EEPROM reload */ 1132 msec_delay(20); 1133 break; 1134 case em_82573: 1135 case em_82574: 1136 if (em_is_onboard_nvm_eeprom(hw) == FALSE) { 1137 usec_delay(10); 1138 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1139 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 1140 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1141 E1000_WRITE_FLUSH(hw); 1142 } 1143 /* FALLTHROUGH */ 1144 1145 /* Auto read done will delay 5ms or poll based on mac type */ 1146 ret_val = em_get_auto_rd_done(hw); 1147 if (ret_val) 1148 return ret_val; 1149 break; 1150 default: 1151 /* Wait for EEPROM reload (it happens automatically) */ 1152 msec_delay(5); 1153 break; 1154 } 1155 1156 /* Disable HW ARPs on ASF enabled adapters */ 1157 if (hw->mac_type >= em_82540 && hw->mac_type <= em_82547_rev_2 && 1158 hw->mac_type != em_icp_xxxx) { 1159 manc = E1000_READ_REG(hw, MANC); 1160 manc &= ~(E1000_MANC_ARP_EN); 1161 E1000_WRITE_REG(hw, MANC, manc); 1162 } 1163 if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) { 1164 em_phy_init_script(hw); 1165 1166 /* Configure activity LED after PHY reset */ 1167 led_ctrl = E1000_READ_REG(hw, LEDCTL); 1168 led_ctrl &= IGP_ACTIVITY_LED_MASK; 1169 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 1170 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 1171 } 1172 1173 /* 1174 * For PCH, this write will make sure that any noise 1175 * will be detected as a CRC error and be dropped rather than show up 1176 * as a bad packet to the DMA engine. 1177 */ 1178 if (hw->mac_type == em_pchlan) 1179 E1000_WRITE_REG(hw, CRC_OFFSET, 0x65656565); 1180 1181 /* Clear interrupt mask to stop board from generating interrupts */ 1182 DEBUGOUT("Masking off all interrupts\n"); 1183 E1000_WRITE_REG(hw, IMC, 0xffffffff); 1184 1185 /* Clear any pending interrupt events. */ 1186 icr = E1000_READ_REG(hw, ICR); 1187 1188 /* If MWI was previously enabled, reenable it. */ 1189 if (hw->mac_type == em_82542_rev2_0) { 1190 if (hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1191 em_pci_set_mwi(hw); 1192 } 1193 if (IS_ICH8(hw->mac_type)) { 1194 uint32_t kab = E1000_READ_REG(hw, KABGTXD); 1195 kab |= E1000_KABGTXD_BGSQLBIAS; 1196 E1000_WRITE_REG(hw, KABGTXD, kab); 1197 } 1198 1199 if (hw->mac_type == em_82580 || hw->mac_type == em_i350) { 1200 uint32_t mdicnfg; 1201 uint16_t nvm_data; 1202 1203 /* clear global device reset status bit */ 1204 EM_WRITE_REG(hw, E1000_STATUS, E1000_STATUS_DEV_RST_SET); 1205 1206 em_read_eeprom(hw, EEPROM_INIT_CONTROL3_PORT_A + 1207 NVM_82580_LAN_FUNC_OFFSET(hw->bus_func), 1, 1208 &nvm_data); 1209 1210 mdicnfg = EM_READ_REG(hw, E1000_MDICNFG); 1211 if (nvm_data & NVM_WORD24_EXT_MDIO) 1212 mdicnfg |= E1000_MDICNFG_EXT_MDIO; 1213 if (nvm_data & NVM_WORD24_COM_MDIO) 1214 mdicnfg |= E1000_MDICNFG_COM_MDIO; 1215 EM_WRITE_REG(hw, E1000_MDICNFG, mdicnfg); 1216 } 1217 1218 if (hw->mac_type == em_i210 || hw->mac_type == em_i350) 1219 em_set_eee_i350(hw); 1220 1221 return E1000_SUCCESS; 1222 } 1223 1224 /****************************************************************************** 1225 * 1226 * Initialize a number of hardware-dependent bits 1227 * 1228 * hw: Struct containing variables accessed by shared code 1229 * 1230 *****************************************************************************/ 1231 STATIC void 1232 em_initialize_hardware_bits(struct em_softc *sc) 1233 { 1234 struct em_hw *hw = &sc->hw; 1235 struct em_queue *que; 1236 1237 DEBUGFUNC("em_initialize_hardware_bits"); 1238 1239 if ((hw->mac_type >= em_82571) && (!hw->initialize_hw_bits_disable)) { 1240 /* Settings common to all silicon */ 1241 uint32_t reg_ctrl, reg_ctrl_ext; 1242 uint32_t reg_tarc0, reg_tarc1; 1243 uint32_t reg_tctl; 1244 uint32_t reg_txdctl; 1245 reg_tarc0 = E1000_READ_REG(hw, TARC0); 1246 reg_tarc0 &= ~0x78000000; /* Clear bits 30, 29, 28, and 1247 * 27 */ 1248 FOREACH_QUEUE(sc, que) { 1249 reg_txdctl = E1000_READ_REG(hw, TXDCTL(que->me)); 1250 reg_txdctl |= E1000_TXDCTL_COUNT_DESC; /* Set bit 22 */ 1251 E1000_WRITE_REG(hw, TXDCTL(que->me), reg_txdctl); 1252 } 1253 1254 /* 1255 * Old code always initialized queue 1, 1256 * even when unused, keep behaviour 1257 */ 1258 if (sc->num_queues == 1) { 1259 reg_txdctl = E1000_READ_REG(hw, TXDCTL(1)); 1260 reg_txdctl |= E1000_TXDCTL_COUNT_DESC; 1261 E1000_WRITE_REG(hw, TXDCTL(1), reg_txdctl); 1262 } 1263 1264 switch (hw->mac_type) { 1265 case em_82571: 1266 case em_82572: 1267 reg_tarc1 = E1000_READ_REG(hw, TARC1); 1268 reg_tctl = E1000_READ_REG(hw, TCTL); 1269 1270 /* Set the phy Tx compatible mode bits */ 1271 reg_tarc1 &= ~0x60000000; /* Clear bits 30 and 29 */ 1272 1273 reg_tarc0 |= 0x07800000; /* Set TARC0 bits 23-26 */ 1274 reg_tarc1 |= 0x07000000; /* Set TARC1 bits 24-26 */ 1275 1276 if (reg_tctl & E1000_TCTL_MULR) 1277 /* Clear bit 28 if MULR is 1b */ 1278 reg_tarc1 &= ~0x10000000; 1279 else 1280 /* Set bit 28 if MULR is 0b */ 1281 reg_tarc1 |= 0x10000000; 1282 1283 E1000_WRITE_REG(hw, TARC1, reg_tarc1); 1284 break; 1285 case em_82573: 1286 case em_82574: 1287 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1288 reg_ctrl = E1000_READ_REG(hw, CTRL); 1289 1290 reg_ctrl_ext &= ~0x00800000; /* Clear bit 23 */ 1291 reg_ctrl_ext |= 0x00400000; /* Set bit 22 */ 1292 reg_ctrl &= ~0x20000000; /* Clear bit 29 */ 1293 1294 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); 1295 E1000_WRITE_REG(hw, CTRL, reg_ctrl); 1296 break; 1297 case em_80003es2lan: 1298 if ((hw->media_type == em_media_type_fiber) || 1299 (hw->media_type == em_media_type_internal_serdes)) { 1300 /* Clear bit 20 */ 1301 reg_tarc0 &= ~0x00100000; 1302 } 1303 reg_tctl = E1000_READ_REG(hw, TCTL); 1304 reg_tarc1 = E1000_READ_REG(hw, TARC1); 1305 if (reg_tctl & E1000_TCTL_MULR) 1306 /* Clear bit 28 if MULR is 1b */ 1307 reg_tarc1 &= ~0x10000000; 1308 else 1309 /* Set bit 28 if MULR is 0b */ 1310 reg_tarc1 |= 0x10000000; 1311 1312 E1000_WRITE_REG(hw, TARC1, reg_tarc1); 1313 break; 1314 case em_ich8lan: 1315 case em_ich9lan: 1316 case em_ich10lan: 1317 case em_pchlan: 1318 case em_pch2lan: 1319 case em_pch_lpt: 1320 case em_pch_spt: 1321 case em_pch_cnp: 1322 case em_pch_tgp: 1323 case em_pch_adp: 1324 if (hw->mac_type == em_ich8lan) 1325 /* Set TARC0 bits 29 and 28 */ 1326 reg_tarc0 |= 0x30000000; 1327 1328 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1329 reg_ctrl_ext |= 0x00400000; /* Set bit 22 */ 1330 /* Enable PHY low-power state when MAC is at D3 w/o WoL */ 1331 if (hw->mac_type >= em_pchlan) 1332 reg_ctrl_ext |= E1000_CTRL_EXT_PHYPDEN; 1333 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); 1334 1335 reg_tarc0 |= 0x0d800000; /* Set TARC0 bits 23, 1336 * 24, 26, 27 */ 1337 1338 reg_tarc1 = E1000_READ_REG(hw, TARC1); 1339 reg_tctl = E1000_READ_REG(hw, TCTL); 1340 1341 if (reg_tctl & E1000_TCTL_MULR) 1342 /* Clear bit 28 if MULR is 1b */ 1343 reg_tarc1 &= ~0x10000000; 1344 else 1345 /* Set bit 28 if MULR is 0b */ 1346 reg_tarc1 |= 0x10000000; 1347 1348 reg_tarc1 |= 0x45000000; /* Set bit 24, 26 and 1349 * 30 */ 1350 1351 E1000_WRITE_REG(hw, TARC1, reg_tarc1); 1352 break; 1353 default: 1354 break; 1355 } 1356 1357 E1000_WRITE_REG(hw, TARC0, reg_tarc0); 1358 } 1359 } 1360 1361 /** 1362 * e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value 1363 * @hw: pointer to the HW structure 1364 * 1365 * Toggling the LANPHYPC pin value fully power-cycles the PHY and is 1366 * used to reset the PHY to a quiescent state when necessary. 1367 **/ 1368 static void 1369 em_toggle_lanphypc_pch_lpt(struct em_hw *hw) 1370 { 1371 uint32_t mac_reg; 1372 1373 DEBUGFUNC("e1000_toggle_lanphypc_pch_lpt"); 1374 1375 /* Set Phy Config Counter to 50msec */ 1376 mac_reg = E1000_READ_REG(hw, FEXTNVM3); 1377 mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK; 1378 mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC; 1379 E1000_WRITE_REG(hw, FEXTNVM3, mac_reg); 1380 1381 /* Toggle LANPHYPC Value bit */ 1382 mac_reg = E1000_READ_REG(hw, CTRL); 1383 mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE; 1384 mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE; 1385 E1000_WRITE_REG(hw, CTRL, mac_reg); 1386 E1000_WRITE_FLUSH(hw); 1387 msec_delay(1); 1388 mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE; 1389 E1000_WRITE_REG(hw, CTRL, mac_reg); 1390 E1000_WRITE_FLUSH(hw); 1391 1392 if (hw->mac_type < em_pch_lpt) { 1393 msec_delay(50); 1394 } else { 1395 uint16_t count = 20; 1396 1397 do { 1398 msec_delay(5); 1399 } while (!(E1000_READ_REG(hw, CTRL_EXT) & 1400 E1000_CTRL_EXT_LPCD) && count--); 1401 1402 msec_delay(30); 1403 } 1404 } 1405 1406 /** 1407 * em_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP 1408 * @hw: pointer to the HW structure 1409 * @force: boolean indicating whether or not to force disabling ULP 1410 * 1411 * Un-configure ULP mode when link is up, the system is transitioned from 1412 * Sx or the driver is unloaded. If on a Manageability Engine (ME) enabled 1413 * system, poll for an indication from ME that ULP has been un-configured. 1414 * If not on an ME enabled system, un-configure the ULP mode by software. 1415 * 1416 * During nominal operation, this function is called when link is acquired 1417 * to disable ULP mode (force=FALSE); otherwise, for example when unloading 1418 * the driver or during Sx->S0 transitions, this is called with force=TRUE 1419 * to forcibly disable ULP. 1420 */ 1421 static int 1422 em_disable_ulp_lpt_lp(struct em_hw *hw, bool force) 1423 { 1424 int ret_val = E1000_SUCCESS; 1425 uint32_t mac_reg; 1426 uint16_t phy_reg; 1427 int i = 0; 1428 1429 if ((hw->mac_type < em_pch_lpt) || 1430 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) || 1431 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) || 1432 (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) || 1433 (hw->device_id == E1000_DEV_ID_PCH_I218_V2)) 1434 return 0; 1435 1436 if (E1000_READ_REG(hw, FWSM) & E1000_FWSM_FW_VALID) { 1437 if (force) { 1438 /* Request ME un-configure ULP mode in the PHY */ 1439 mac_reg = E1000_READ_REG(hw, H2ME); 1440 mac_reg &= ~E1000_H2ME_ULP; 1441 mac_reg |= E1000_H2ME_ENFORCE_SETTINGS; 1442 E1000_WRITE_REG(hw, H2ME, mac_reg); 1443 } 1444 1445 /* Poll up to 300msec for ME to clear ULP_CFG_DONE. */ 1446 while (E1000_READ_REG(hw, FWSM) & E1000_FWSM_ULP_CFG_DONE) { 1447 if (i++ == 30) { 1448 ret_val = -E1000_ERR_PHY; 1449 goto out; 1450 } 1451 1452 msec_delay(10); 1453 } 1454 DEBUGOUT1("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10); 1455 1456 if (force) { 1457 mac_reg = E1000_READ_REG(hw, H2ME); 1458 mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS; 1459 E1000_WRITE_REG(hw, H2ME, mac_reg); 1460 } else { 1461 /* Clear H2ME.ULP after ME ULP configuration */ 1462 mac_reg = E1000_READ_REG(hw, H2ME); 1463 mac_reg &= ~E1000_H2ME_ULP; 1464 E1000_WRITE_REG(hw, H2ME, mac_reg); 1465 } 1466 1467 goto out; 1468 } 1469 1470 ret_val = em_get_software_flag(hw); 1471 if (ret_val) 1472 goto out; 1473 1474 if (force) 1475 /* Toggle LANPHYPC Value bit */ 1476 em_toggle_lanphypc_pch_lpt(hw); 1477 1478 /* Unforce SMBus mode in PHY */ 1479 ret_val = em_read_phy_reg(hw, CV_SMB_CTRL, &phy_reg); 1480 if (ret_val) { 1481 /* The MAC might be in PCIe mode, so temporarily force to 1482 * SMBus mode in order to access the PHY. 1483 */ 1484 mac_reg = E1000_READ_REG(hw, CTRL_EXT); 1485 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS; 1486 E1000_WRITE_REG(hw, CTRL_EXT, mac_reg); 1487 1488 msec_delay(50); 1489 1490 ret_val = em_read_phy_reg(hw, CV_SMB_CTRL, &phy_reg); 1491 if (ret_val) 1492 goto release; 1493 } 1494 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS; 1495 em_write_phy_reg(hw, CV_SMB_CTRL, phy_reg); 1496 1497 /* Unforce SMBus mode in MAC */ 1498 mac_reg = E1000_READ_REG(hw, CTRL_EXT); 1499 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; 1500 E1000_WRITE_REG(hw, CTRL_EXT, mac_reg); 1501 1502 /* When ULP mode was previously entered, K1 was disabled by the 1503 * hardware. Re-Enable K1 in the PHY when exiting ULP. 1504 */ 1505 ret_val = em_read_phy_reg(hw, HV_PM_CTRL, &phy_reg); 1506 if (ret_val) 1507 goto release; 1508 phy_reg |= HV_PM_CTRL_K1_ENABLE; 1509 em_write_phy_reg(hw, HV_PM_CTRL, phy_reg); 1510 1511 /* Clear ULP enabled configuration */ 1512 ret_val = em_read_phy_reg(hw, I218_ULP_CONFIG1, &phy_reg); 1513 if (ret_val) 1514 goto release; 1515 phy_reg &= ~(I218_ULP_CONFIG1_IND | 1516 I218_ULP_CONFIG1_STICKY_ULP | 1517 I218_ULP_CONFIG1_RESET_TO_SMBUS | 1518 I218_ULP_CONFIG1_WOL_HOST | 1519 I218_ULP_CONFIG1_INBAND_EXIT | 1520 I218_ULP_CONFIG1_EN_ULP_LANPHYPC | 1521 I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST | 1522 I218_ULP_CONFIG1_DISABLE_SMB_PERST); 1523 em_write_phy_reg(hw, I218_ULP_CONFIG1, phy_reg); 1524 1525 /* Commit ULP changes by starting auto ULP configuration */ 1526 phy_reg |= I218_ULP_CONFIG1_START; 1527 em_write_phy_reg(hw, I218_ULP_CONFIG1, phy_reg); 1528 1529 /* Clear Disable SMBus Release on PERST# in MAC */ 1530 mac_reg = E1000_READ_REG(hw, FEXTNVM7); 1531 mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST; 1532 E1000_WRITE_REG(hw, FEXTNVM7, mac_reg); 1533 1534 release: 1535 em_release_software_flag(hw); 1536 if (force) { 1537 em_phy_reset(hw); 1538 msec_delay(50); 1539 } 1540 out: 1541 if (ret_val) 1542 DEBUGOUT1("Error in ULP disable flow: %d\n", ret_val); 1543 1544 return ret_val; 1545 } 1546 1547 /****************************************************************************** 1548 * Performs basic configuration of the adapter. 1549 * 1550 * hw - Struct containing variables accessed by shared code 1551 * 1552 * Assumes that the controller has previously been reset and is in a 1553 * post-reset uninitialized state. Initializes the receive address registers, 1554 * multicast table, and VLAN filter table. Calls routines to setup link 1555 * configuration and flow control settings. Clears all on-chip counters. Leaves 1556 * the transmit and receive units disabled and uninitialized. 1557 *****************************************************************************/ 1558 int32_t 1559 em_init_hw(struct em_softc *sc) 1560 { 1561 struct em_hw *hw = &sc->hw; 1562 struct em_queue *que; 1563 uint32_t ctrl; 1564 uint32_t i; 1565 int32_t ret_val; 1566 uint16_t pcix_cmd_word; 1567 uint16_t pcix_stat_hi_word; 1568 uint16_t cmd_mmrbc; 1569 uint16_t stat_mmrbc; 1570 uint32_t mta_size; 1571 uint32_t reg_data; 1572 uint32_t ctrl_ext; 1573 uint32_t snoop; 1574 uint32_t fwsm; 1575 DEBUGFUNC("em_init_hw"); 1576 1577 /* force full DMA clock frequency for ICH8 */ 1578 if (hw->mac_type == em_ich8lan) { 1579 reg_data = E1000_READ_REG(hw, STATUS); 1580 reg_data &= ~0x80000000; 1581 E1000_WRITE_REG(hw, STATUS, reg_data); 1582 } 1583 1584 if (hw->mac_type == em_pchlan || 1585 hw->mac_type == em_pch2lan || 1586 hw->mac_type == em_pch_lpt || 1587 hw->mac_type == em_pch_spt || 1588 hw->mac_type == em_pch_cnp || 1589 hw->mac_type == em_pch_tgp || 1590 hw->mac_type == em_pch_adp) { 1591 /* 1592 * The MAC-PHY interconnect may still be in SMBus mode 1593 * after Sx->S0. Toggle the LANPHYPC Value bit to force 1594 * the interconnect to PCIe mode, but only if there is no 1595 * firmware present otherwise firmware will have done it. 1596 */ 1597 fwsm = E1000_READ_REG(hw, FWSM); 1598 if ((fwsm & E1000_FWSM_FW_VALID) == 0) { 1599 ctrl = E1000_READ_REG(hw, CTRL); 1600 ctrl |= E1000_CTRL_LANPHYPC_OVERRIDE; 1601 ctrl &= ~E1000_CTRL_LANPHYPC_VALUE; 1602 E1000_WRITE_REG(hw, CTRL, ctrl); 1603 usec_delay(10); 1604 ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE; 1605 E1000_WRITE_REG(hw, CTRL, ctrl); 1606 msec_delay(50); 1607 } 1608 1609 /* Gate automatic PHY configuration on non-managed 82579 */ 1610 if (hw->mac_type == em_pch2lan) 1611 em_gate_hw_phy_config_ich8lan(hw, TRUE); 1612 1613 em_disable_ulp_lpt_lp(hw, TRUE); 1614 /* 1615 * Reset the PHY before any access to it. Doing so, 1616 * ensures that the PHY is in a known good state before 1617 * we read/write PHY registers. The generic reset is 1618 * sufficient here, because we haven't determined 1619 * the PHY type yet. 1620 */ 1621 em_phy_reset(hw); 1622 1623 /* Ungate automatic PHY configuration on non-managed 82579 */ 1624 if (hw->mac_type == em_pch2lan && 1625 (fwsm & E1000_FWSM_FW_VALID) == 0) 1626 em_gate_hw_phy_config_ich8lan(hw, FALSE); 1627 1628 /* Set MDIO slow mode before any other MDIO access */ 1629 ret_val = em_set_mdio_slow_mode_hv(hw); 1630 if (ret_val) 1631 return ret_val; 1632 } 1633 1634 /* Initialize Identification LED */ 1635 ret_val = em_id_led_init(hw); 1636 if (ret_val) { 1637 DEBUGOUT("Error Initializing Identification LED\n"); 1638 return ret_val; 1639 } 1640 /* Set the media type and TBI compatibility */ 1641 em_set_media_type(hw); 1642 1643 /* Magic delay that improves problems with i219LM on HP Elitebook */ 1644 msec_delay(1); 1645 /* Must be called after em_set_media_type because media_type is used */ 1646 em_initialize_hardware_bits(sc); 1647 1648 /* Disabling VLAN filtering. */ 1649 DEBUGOUT("Initializing the IEEE VLAN\n"); 1650 /* VET hardcoded to standard value and VFTA removed in ICH8/ICH9 LAN */ 1651 if (!IS_ICH8(hw->mac_type)) { 1652 if (hw->mac_type < em_82545_rev_3) 1653 E1000_WRITE_REG(hw, VET, 0); 1654 if (hw->mac_type == em_i350) 1655 em_clear_vfta_i350(hw); 1656 else 1657 em_clear_vfta(hw); 1658 } 1659 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ 1660 if (hw->mac_type == em_82542_rev2_0) { 1661 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 1662 em_pci_clear_mwi(hw); 1663 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST); 1664 E1000_WRITE_FLUSH(hw); 1665 msec_delay(5); 1666 } 1667 /* 1668 * Setup the receive address. This involves initializing all of the 1669 * Receive Address Registers (RARs 0 - 15). 1670 */ 1671 em_init_rx_addrs(hw); 1672 1673 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI*/ 1674 if (hw->mac_type == em_82542_rev2_0) { 1675 E1000_WRITE_REG(hw, RCTL, 0); 1676 E1000_WRITE_FLUSH(hw); 1677 msec_delay(1); 1678 if (hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1679 em_pci_set_mwi(hw); 1680 } 1681 /* Zero out the Multicast HASH table */ 1682 DEBUGOUT("Zeroing the MTA\n"); 1683 mta_size = E1000_MC_TBL_SIZE; 1684 if (IS_ICH8(hw->mac_type)) 1685 mta_size = E1000_MC_TBL_SIZE_ICH8LAN; 1686 for (i = 0; i < mta_size; i++) { 1687 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 1688 /* 1689 * use write flush to prevent Memory Write Block (MWB) from 1690 * occurring when accessing our register space 1691 */ 1692 E1000_WRITE_FLUSH(hw); 1693 } 1694 /* 1695 * Set the PCI priority bit correctly in the CTRL register. This 1696 * determines if the adapter gives priority to receives, or if it 1697 * gives equal priority to transmits and receives. Valid only on 1698 * 82542 and 82543 silicon. 1699 */ 1700 if (hw->dma_fairness && hw->mac_type <= em_82543) { 1701 ctrl = E1000_READ_REG(hw, CTRL); 1702 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR); 1703 } 1704 switch (hw->mac_type) { 1705 case em_82545_rev_3: 1706 case em_82546_rev_3: 1707 break; 1708 default: 1709 /* 1710 * Workaround for PCI-X problem when BIOS sets MMRBC 1711 * incorrectly. 1712 */ 1713 if (hw->bus_type == em_bus_type_pcix) { 1714 em_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, 1715 &pcix_cmd_word); 1716 em_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, 1717 &pcix_stat_hi_word); 1718 cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) 1719 >> PCIX_COMMAND_MMRBC_SHIFT; 1720 stat_mmrbc = (pcix_stat_hi_word & 1721 PCIX_STATUS_HI_MMRBC_MASK) >> 1722 PCIX_STATUS_HI_MMRBC_SHIFT; 1723 1724 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) 1725 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; 1726 if (cmd_mmrbc > stat_mmrbc) { 1727 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK; 1728 pcix_cmd_word |= stat_mmrbc << 1729 PCIX_COMMAND_MMRBC_SHIFT; 1730 em_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, 1731 &pcix_cmd_word); 1732 } 1733 } 1734 break; 1735 } 1736 1737 /* More time needed for PHY to initialize */ 1738 if (IS_ICH8(hw->mac_type)) 1739 msec_delay(15); 1740 1741 /* 1742 * The 82578 Rx buffer will stall if wakeup is enabled in host and 1743 * the ME. Reading the BM_WUC register will clear the host wakeup bit. 1744 * Reset the phy after disabling host wakeup to reset the Rx buffer. 1745 */ 1746 if (hw->phy_type == em_phy_82578) { 1747 em_read_phy_reg(hw, PHY_REG(BM_WUC_PAGE, 1), 1748 (uint16_t *)®_data); 1749 ret_val = em_phy_reset(hw); 1750 if (ret_val) 1751 return ret_val; 1752 } 1753 1754 /* Call a subroutine to configure the link and setup flow control. */ 1755 ret_val = em_setup_link(hw); 1756 1757 /* Set the transmit descriptor write-back policy */ 1758 if (hw->mac_type > em_82544) { 1759 FOREACH_QUEUE(sc, que) { 1760 ctrl = E1000_READ_REG(hw, TXDCTL(que->me)); 1761 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | 1762 E1000_TXDCTL_FULL_TX_DESC_WB; 1763 E1000_WRITE_REG(hw, TXDCTL(que->me), ctrl); 1764 } 1765 } 1766 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) { 1767 em_enable_tx_pkt_filtering(hw); 1768 } 1769 switch (hw->mac_type) { 1770 default: 1771 break; 1772 case em_80003es2lan: 1773 /* Enable retransmit on late collisions */ 1774 reg_data = E1000_READ_REG(hw, TCTL); 1775 reg_data |= E1000_TCTL_RTLC; 1776 E1000_WRITE_REG(hw, TCTL, reg_data); 1777 1778 /* Configure Gigabit Carry Extend Padding */ 1779 reg_data = E1000_READ_REG(hw, TCTL_EXT); 1780 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK; 1781 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX; 1782 E1000_WRITE_REG(hw, TCTL_EXT, reg_data); 1783 1784 /* Configure Transmit Inter-Packet Gap */ 1785 reg_data = E1000_READ_REG(hw, TIPG); 1786 reg_data &= ~E1000_TIPG_IPGT_MASK; 1787 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; 1788 E1000_WRITE_REG(hw, TIPG, reg_data); 1789 1790 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001); 1791 reg_data &= ~0x00100000; 1792 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data); 1793 /* FALLTHROUGH */ 1794 case em_82571: 1795 case em_82572: 1796 case em_82575: 1797 case em_82576: 1798 case em_82580: 1799 case em_i210: 1800 case em_i350: 1801 case em_ich8lan: 1802 case em_ich9lan: 1803 case em_ich10lan: 1804 case em_pchlan: 1805 case em_pch2lan: 1806 case em_pch_lpt: 1807 case em_pch_spt: 1808 case em_pch_cnp: 1809 case em_pch_tgp: 1810 case em_pch_adp: 1811 /* 1812 * Old code always initialized queue 1, 1813 * even when unused, keep behaviour 1814 */ 1815 if (sc->num_queues == 1) { 1816 ctrl = E1000_READ_REG(hw, TXDCTL(1)); 1817 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | 1818 E1000_TXDCTL_FULL_TX_DESC_WB; 1819 E1000_WRITE_REG(hw, TXDCTL(1), ctrl); 1820 } 1821 break; 1822 } 1823 1824 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) { 1825 uint32_t gcr = E1000_READ_REG(hw, GCR); 1826 gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; 1827 E1000_WRITE_REG(hw, GCR, gcr); 1828 } 1829 /* 1830 * Clear all of the statistics registers (clear on read). It is 1831 * important that we do this after we have tried to establish link 1832 * because the symbol error count will increment wildly if there is 1833 * no link. 1834 */ 1835 em_clear_hw_cntrs(hw); 1836 /* 1837 * ICH8 No-snoop bits are opposite polarity. Set to snoop by default 1838 * after reset. 1839 */ 1840 if (IS_ICH8(hw->mac_type)) { 1841 if (hw->mac_type == em_ich8lan) 1842 snoop = PCI_EX_82566_SNOOP_ALL; 1843 else 1844 snoop = (u_int32_t) ~ (PCI_EX_NO_SNOOP_ALL); 1845 1846 em_set_pci_ex_no_snoop(hw, snoop); 1847 } 1848 1849 /* ungate DMA clock to avoid packet loss */ 1850 if (hw->mac_type >= em_pch_tgp) { 1851 uint32_t fflt_dbg = E1000_READ_REG(hw, FFLT_DBG); 1852 fflt_dbg |= (1 << 12); 1853 E1000_WRITE_REG(hw, FFLT_DBG, fflt_dbg); 1854 } 1855 1856 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER || 1857 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) { 1858 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1859 /* 1860 * Relaxed ordering must be disabled to avoid a parity error 1861 * crash in a PCI slot. 1862 */ 1863 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 1864 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1865 } 1866 return ret_val; 1867 } 1868 1869 /****************************************************************************** 1870 * Adjust SERDES output amplitude based on EEPROM setting. 1871 * 1872 * hw - Struct containing variables accessed by shared code. 1873 *****************************************************************************/ 1874 static int32_t 1875 em_adjust_serdes_amplitude(struct em_hw *hw) 1876 { 1877 uint16_t eeprom_data; 1878 int32_t ret_val; 1879 DEBUGFUNC("em_adjust_serdes_amplitude"); 1880 1881 if (hw->media_type != em_media_type_internal_serdes || 1882 hw->mac_type >= em_82575) 1883 return E1000_SUCCESS; 1884 1885 switch (hw->mac_type) { 1886 case em_82545_rev_3: 1887 case em_82546_rev_3: 1888 break; 1889 default: 1890 return E1000_SUCCESS; 1891 } 1892 1893 ret_val = em_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data); 1894 if (ret_val) { 1895 return ret_val; 1896 } 1897 if (eeprom_data != EEPROM_RESERVED_WORD) { 1898 /* Adjust SERDES output amplitude only. */ 1899 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK; 1900 ret_val = em_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, 1901 eeprom_data); 1902 if (ret_val) 1903 return ret_val; 1904 } 1905 return E1000_SUCCESS; 1906 } 1907 1908 /****************************************************************************** 1909 * Configures flow control and link settings. 1910 * 1911 * hw - Struct containing variables accessed by shared code 1912 * 1913 * Determines which flow control settings to use. Calls the appropriate media- 1914 * specific link configuration function. Configures the flow control settings. 1915 * Assuming the adapter has a valid link partner, a valid link should be 1916 * established. Assumes the hardware has previously been reset and the 1917 * transmitter and receiver are not enabled. 1918 *****************************************************************************/ 1919 int32_t 1920 em_setup_link(struct em_hw *hw) 1921 { 1922 uint32_t ctrl_ext; 1923 int32_t ret_val; 1924 uint16_t eeprom_data; 1925 uint16_t eeprom_control2_reg_offset; 1926 DEBUGFUNC("em_setup_link"); 1927 1928 eeprom_control2_reg_offset = 1929 (hw->mac_type != em_icp_xxxx) 1930 ? EEPROM_INIT_CONTROL2_REG 1931 : EEPROM_INIT_CONTROL3_ICP_xxxx(hw->icp_xxxx_port_num); 1932 /* 1933 * In the case of the phy reset being blocked, we already have a 1934 * link. We do not have to set it up again. 1935 */ 1936 if (em_check_phy_reset_block(hw)) 1937 return E1000_SUCCESS; 1938 /* 1939 * Read and store word 0x0F of the EEPROM. This word contains bits 1940 * that determine the hardware's default PAUSE (flow control) mode, a 1941 * bit that determines whether the HW defaults to enabling or 1942 * disabling auto-negotiation, and the direction of the SW defined 1943 * pins. If there is no SW over-ride of the flow control setting, 1944 * then the variable hw->fc will be initialized based on a value in 1945 * the EEPROM. 1946 */ 1947 if (hw->fc == E1000_FC_DEFAULT) { 1948 switch (hw->mac_type) { 1949 case em_ich8lan: 1950 case em_ich9lan: 1951 case em_ich10lan: 1952 case em_pchlan: 1953 case em_pch2lan: 1954 case em_pch_lpt: 1955 case em_pch_spt: 1956 case em_pch_cnp: 1957 case em_pch_tgp: 1958 case em_pch_adp: 1959 case em_82573: 1960 case em_82574: 1961 hw->fc = E1000_FC_FULL; 1962 break; 1963 default: 1964 ret_val = em_read_eeprom(hw, 1965 eeprom_control2_reg_offset, 1, &eeprom_data); 1966 if (ret_val) { 1967 DEBUGOUT("EEPROM Read Error\n"); 1968 return -E1000_ERR_EEPROM; 1969 } 1970 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0) 1971 hw->fc = E1000_FC_NONE; 1972 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 1973 EEPROM_WORD0F_ASM_DIR) 1974 hw->fc = E1000_FC_TX_PAUSE; 1975 else 1976 hw->fc = E1000_FC_FULL; 1977 break; 1978 } 1979 } 1980 /* 1981 * We want to save off the original Flow Control configuration just 1982 * in case we get disconnected and then reconnected into a different 1983 * hub or switch with different Flow Control capabilities. 1984 */ 1985 if (hw->mac_type == em_82542_rev2_0) 1986 hw->fc &= (~E1000_FC_TX_PAUSE); 1987 1988 if ((hw->mac_type < em_82543) && (hw->report_tx_early == 1)) 1989 hw->fc &= (~E1000_FC_RX_PAUSE); 1990 1991 hw->original_fc = hw->fc; 1992 1993 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc); 1994 /* 1995 * Take the 4 bits from EEPROM word 0x0F that determine the initial 1996 * polarity value for the SW controlled pins, and setup the Extended 1997 * Device Control reg with that info. This is needed because one of 1998 * the SW controlled pins is used for signal detection. So this 1999 * should be done before em_setup_pcs_link() or em_phy_setup() is 2000 * called. 2001 */ 2002 if (hw->mac_type == em_82543) { 2003 ret_val = em_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 2004 1, &eeprom_data); 2005 if (ret_val) { 2006 DEBUGOUT("EEPROM Read Error\n"); 2007 return -E1000_ERR_EEPROM; 2008 } 2009 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << 2010 SWDPIO__EXT_SHIFT); 2011 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 2012 } 2013 /* Make sure we have a valid PHY */ 2014 ret_val = em_detect_gig_phy(hw); 2015 if (ret_val) { 2016 DEBUGOUT("Error, did not detect valid phy.\n"); 2017 if (hw->mac_type == em_icp_xxxx) 2018 return E1000_DEFER_INIT; 2019 else 2020 return ret_val; 2021 } 2022 DEBUGOUT1("Phy ID = %x \n", hw->phy_id); 2023 2024 /* Call the necessary subroutine to configure the link. */ 2025 switch (hw->media_type) { 2026 case em_media_type_copper: 2027 case em_media_type_oem: 2028 ret_val = em_setup_copper_link(hw); 2029 break; 2030 default: 2031 ret_val = em_setup_fiber_serdes_link(hw); 2032 break; 2033 } 2034 /* 2035 * Initialize the flow control address, type, and PAUSE timer 2036 * registers to their default values. This is done even if flow 2037 * control is disabled, because it does not hurt anything to 2038 * initialize these registers. 2039 */ 2040 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n" 2041 ); 2042 2043 /* 2044 * FCAL/H and FCT are hardcoded to standard values in 2045 * em_ich8lan / em_ich9lan / em_ich10lan. 2046 */ 2047 if (!IS_ICH8(hw->mac_type)) { 2048 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE); 2049 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH); 2050 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW); 2051 } 2052 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time); 2053 2054 if (hw->phy_type == em_phy_82577 || 2055 hw->phy_type == em_phy_82578 || 2056 hw->phy_type == em_phy_82579 || 2057 hw->phy_type == em_phy_i217) { 2058 E1000_WRITE_REG(hw, FCRTV_PCH, 0x1000); 2059 em_write_phy_reg(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27), 2060 hw->fc_pause_time); 2061 } 2062 2063 /* 2064 * Set the flow control receive threshold registers. Normally, these 2065 * registers will be set to a default threshold that may be adjusted 2066 * later by the driver's runtime code. However, if the ability to 2067 * transmit pause frames in not enabled, then these registers will be 2068 * set to 0. 2069 */ 2070 if (!(hw->fc & E1000_FC_TX_PAUSE)) { 2071 E1000_WRITE_REG(hw, FCRTL, 0); 2072 E1000_WRITE_REG(hw, FCRTH, 0); 2073 } else { 2074 /* 2075 * We need to set up the Receive Threshold high and low water 2076 * marks as well as (optionally) enabling the transmission of 2077 * XON frames. 2078 */ 2079 if (hw->fc_send_xon) { 2080 E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water 2081 | E1000_FCRTL_XONE)); 2082 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); 2083 } else { 2084 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water); 2085 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); 2086 } 2087 } 2088 return ret_val; 2089 } 2090 2091 void 2092 em_power_up_serdes_link_82575(struct em_hw *hw) 2093 { 2094 uint32_t reg; 2095 2096 if (hw->media_type != em_media_type_internal_serdes && 2097 hw->sgmii_active == FALSE) 2098 return; 2099 2100 /* Enable PCS to turn on link */ 2101 reg = E1000_READ_REG(hw, PCS_CFG0); 2102 reg |= E1000_PCS_CFG_PCS_EN; 2103 E1000_WRITE_REG(hw, PCS_CFG0, reg); 2104 2105 /* Power up the laser */ 2106 reg = E1000_READ_REG(hw, CTRL_EXT); 2107 reg &= ~E1000_CTRL_EXT_SDP3_DATA; 2108 E1000_WRITE_REG(hw, CTRL_EXT, reg); 2109 2110 /* flush the write to verify completion */ 2111 E1000_WRITE_FLUSH(hw); 2112 delay(5); 2113 } 2114 2115 /****************************************************************************** 2116 * Sets up link for a fiber based or serdes based adapter 2117 * 2118 * hw - Struct containing variables accessed by shared code 2119 * 2120 * Manipulates Physical Coding Sublayer functions in order to configure 2121 * link. Assumes the hardware has been previously reset and the transmitter 2122 * and receiver are not enabled. 2123 *****************************************************************************/ 2124 static int32_t 2125 em_setup_fiber_serdes_link(struct em_hw *hw) 2126 { 2127 uint32_t ctrl, ctrl_ext, reg; 2128 uint32_t status; 2129 uint32_t txcw = 0; 2130 uint32_t i; 2131 uint32_t signal = 0; 2132 int32_t ret_val; 2133 DEBUGFUNC("em_setup_fiber_serdes_link"); 2134 2135 if (hw->media_type != em_media_type_internal_serdes && 2136 hw->sgmii_active == FALSE) 2137 return -E1000_ERR_CONFIG; 2138 2139 /* 2140 * On 82571 and 82572 Fiber connections, SerDes loopback mode 2141 * persists until explicitly turned off or a power cycle is 2142 * performed. A read to the register does not indicate its status. 2143 * Therefore, we ensure loopback mode is disabled during 2144 * initialization. 2145 */ 2146 if (hw->mac_type == em_82571 || hw->mac_type == em_82572 || 2147 hw->mac_type >= em_82575) 2148 E1000_WRITE_REG(hw, SCTL, E1000_DISABLE_SERDES_LOOPBACK); 2149 2150 if (hw->mac_type >= em_82575) 2151 em_power_up_serdes_link_82575(hw); 2152 2153 /* 2154 * On adapters with a MAC newer than 82544, SWDP 1 will be set when 2155 * the optics detect a signal. On older adapters, it will be cleared 2156 * when there is a signal. This applies to fiber media only. If 2157 * we're on serdes media, adjust the output amplitude to value set in 2158 * the EEPROM. 2159 */ 2160 ctrl = E1000_READ_REG(hw, CTRL); 2161 if (hw->media_type == em_media_type_fiber) 2162 signal = (hw->mac_type > em_82544) ? E1000_CTRL_SWDPIN1 : 0; 2163 2164 ret_val = em_adjust_serdes_amplitude(hw); 2165 if (ret_val) 2166 return ret_val; 2167 2168 /* Take the link out of reset */ 2169 ctrl &= ~(E1000_CTRL_LRST); 2170 2171 if (hw->mac_type >= em_82575) { 2172 /* set both sw defined pins on 82575/82576*/ 2173 ctrl |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1; 2174 2175 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 2176 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) { 2177 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: 2178 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES: 2179 /* the backplane is always connected */ 2180 reg = E1000_READ_REG(hw, PCS_LCTL); 2181 reg |= E1000_PCS_LCTL_FORCE_FCTRL; 2182 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL; 2183 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */ 2184 DEBUGOUT("Configuring Forced Link\n"); 2185 E1000_WRITE_REG(hw, PCS_LCTL, reg); 2186 em_force_mac_fc(hw); 2187 hw->autoneg_failed = 0; 2188 return E1000_SUCCESS; 2189 break; 2190 default: 2191 /* Set switch control to serdes energy detect */ 2192 reg = E1000_READ_REG(hw, CONNSW); 2193 reg |= E1000_CONNSW_ENRGSRC; 2194 E1000_WRITE_REG(hw, CONNSW, reg); 2195 break; 2196 } 2197 } 2198 2199 /* Adjust VCO speed to improve BER performance */ 2200 ret_val = em_set_vco_speed(hw); 2201 if (ret_val) 2202 return ret_val; 2203 2204 em_config_collision_dist(hw); 2205 /* 2206 * Check for a software override of the flow control settings, and 2207 * setup the device accordingly. If auto-negotiation is enabled, 2208 * then software will have to set the "PAUSE" bits to the correct 2209 * value in the Tranmsit Config Word Register (TXCW) and re-start 2210 * auto-negotiation. However, if auto-negotiation is disabled, then 2211 * software will have to manually configure the two flow control 2212 * enable bits in the CTRL register. 2213 * 2214 * The possible values of the "fc" parameter are: 0: Flow control is 2215 * completely disabled 1: Rx flow control is enabled (we can receive 2216 * pause frames, but not send pause frames). 2: Tx flow control is 2217 * enabled (we can send pause frames but we do not support receiving 2218 * pause frames). 3: Both Rx and TX flow control (symmetric) are 2219 * enabled. 2220 */ 2221 switch (hw->fc) { 2222 case E1000_FC_NONE: 2223 /* 2224 * Flow control is completely disabled by a software 2225 * over-ride. 2226 */ 2227 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 2228 break; 2229 case E1000_FC_RX_PAUSE: 2230 /* 2231 * RX Flow control is enabled and TX Flow control is disabled 2232 * by a software over-ride. Since there really isn't a way to 2233 * advertise that we are capable of RX Pause ONLY, we will 2234 * advertise that we support both symmetric and asymmetric RX 2235 * PAUSE. Later, we will disable the adapter's ability to 2236 * send PAUSE frames. 2237 */ 2238 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | 2239 E1000_TXCW_PAUSE_MASK); 2240 break; 2241 case E1000_FC_TX_PAUSE: 2242 /* 2243 * TX Flow control is enabled, and RX Flow control is 2244 * disabled, by a software over-ride. 2245 */ 2246 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 2247 break; 2248 case E1000_FC_FULL: 2249 /* 2250 * Flow control (both RX and TX) is enabled by a software 2251 * over-ride. 2252 */ 2253 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | 2254 E1000_TXCW_PAUSE_MASK); 2255 break; 2256 default: 2257 DEBUGOUT("Flow control param set incorrectly\n"); 2258 return -E1000_ERR_CONFIG; 2259 break; 2260 } 2261 /* 2262 * Since auto-negotiation is enabled, take the link out of reset (the 2263 * link will be in reset, because we previously reset the chip). This 2264 * will restart auto-negotiation. If auto-negotiation is successful 2265 * then the link-up status bit will be set and the flow control 2266 * enable bits (RFCE and TFCE) will be set according to their 2267 * negotiated value. 2268 */ 2269 DEBUGOUT("Auto-negotiation enabled\n"); 2270 2271 E1000_WRITE_REG(hw, TXCW, txcw); 2272 E1000_WRITE_REG(hw, CTRL, ctrl); 2273 E1000_WRITE_FLUSH(hw); 2274 2275 hw->txcw = txcw; 2276 msec_delay(1); 2277 /* 2278 * If we have a signal (the cable is plugged in) then poll for a 2279 * "Link-Up" indication in the Device Status Register. Time-out if a 2280 * link isn't seen in 500 milliseconds seconds (Auto-negotiation 2281 * should complete in less than 500 milliseconds even if the other 2282 * end is doing it in SW). For internal serdes, we just assume a 2283 * signal is present, then poll. 2284 */ 2285 if (hw->media_type == em_media_type_internal_serdes || 2286 (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) { 2287 DEBUGOUT("Looking for Link\n"); 2288 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) { 2289 msec_delay(10); 2290 status = E1000_READ_REG(hw, STATUS); 2291 if (status & E1000_STATUS_LU) 2292 break; 2293 } 2294 if (i == (LINK_UP_TIMEOUT / 10)) { 2295 DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 2296 hw->autoneg_failed = 1; 2297 /* 2298 * AutoNeg failed to achieve a link, so we'll call 2299 * em_check_for_link. This routine will force the 2300 * link up if we detect a signal. This will allow us 2301 * to communicate with non-autonegotiating link 2302 * partners. 2303 */ 2304 ret_val = em_check_for_link(hw); 2305 if (ret_val) { 2306 DEBUGOUT("Error while checking for link\n"); 2307 return ret_val; 2308 } 2309 hw->autoneg_failed = 0; 2310 } else { 2311 hw->autoneg_failed = 0; 2312 DEBUGOUT("Valid Link Found\n"); 2313 } 2314 } else { 2315 DEBUGOUT("No Signal Detected\n"); 2316 } 2317 return E1000_SUCCESS; 2318 } 2319 2320 /****************************************************************************** 2321 * Make sure we have a valid PHY and change PHY mode before link setup. 2322 * 2323 * hw - Struct containing variables accessed by shared code 2324 *****************************************************************************/ 2325 static int32_t 2326 em_copper_link_preconfig(struct em_hw *hw) 2327 { 2328 uint32_t ctrl; 2329 int32_t ret_val; 2330 uint16_t phy_data; 2331 DEBUGFUNC("em_copper_link_preconfig"); 2332 2333 ctrl = E1000_READ_REG(hw, CTRL); 2334 /* 2335 * With 82543, we need to force speed and duplex on the MAC equal to 2336 * what the PHY speed and duplex configuration is. In addition, we 2337 * need to perform a hardware reset on the PHY to take it out of 2338 * reset. 2339 */ 2340 if (hw->mac_type > em_82543) { 2341 ctrl |= E1000_CTRL_SLU; 2342 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 2343 E1000_WRITE_REG(hw, CTRL, ctrl); 2344 } else { 2345 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | 2346 E1000_CTRL_SLU); 2347 E1000_WRITE_REG(hw, CTRL, ctrl); 2348 ret_val = em_phy_hw_reset(hw); 2349 if (ret_val) 2350 return ret_val; 2351 } 2352 2353 /* Set PHY to class A mode (if necessary) */ 2354 ret_val = em_set_phy_mode(hw); 2355 if (ret_val) 2356 return ret_val; 2357 2358 if ((hw->mac_type == em_82545_rev_3) || 2359 (hw->mac_type == em_82546_rev_3)) { 2360 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 2361 &phy_data); 2362 phy_data |= 0x00000008; 2363 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 2364 phy_data); 2365 } 2366 if (hw->mac_type <= em_82543 || 2367 hw->mac_type == em_82541 || hw->mac_type == em_82547 || 2368 hw->mac_type == em_82541_rev_2 || hw->mac_type == em_82547_rev_2) 2369 hw->phy_reset_disable = FALSE; 2370 if ((hw->mac_type == em_82575 || hw->mac_type == em_82580 || 2371 hw->mac_type == em_82576 || 2372 hw->mac_type == em_i210 || hw->mac_type == em_i350) && 2373 hw->sgmii_active) { 2374 /* allow time for SFP cage time to power up phy */ 2375 msec_delay(300); 2376 2377 /* 2378 * SFP documentation requires the following to configure the SFP module 2379 * to work on SGMII. No further documentation is given. 2380 */ 2381 em_write_phy_reg(hw, 0x1B, 0x8084); 2382 em_phy_hw_reset(hw); 2383 } 2384 2385 return E1000_SUCCESS; 2386 } 2387 2388 /****************************************************************************** 2389 * Copper link setup for em_phy_igp series. 2390 * 2391 * hw - Struct containing variables accessed by shared code 2392 *****************************************************************************/ 2393 static int32_t 2394 em_copper_link_igp_setup(struct em_hw *hw) 2395 { 2396 uint32_t led_ctrl; 2397 int32_t ret_val; 2398 uint16_t phy_data; 2399 DEBUGFUNC("em_copper_link_igp_setup"); 2400 2401 if (hw->phy_reset_disable) 2402 return E1000_SUCCESS; 2403 2404 ret_val = em_phy_reset(hw); 2405 if (ret_val) { 2406 DEBUGOUT("Error Resetting the PHY\n"); 2407 return ret_val; 2408 } 2409 /* Wait 15ms for MAC to configure PHY from eeprom settings */ 2410 msec_delay(15); 2411 if (hw->mac_type != em_ich8lan && 2412 hw->mac_type != em_ich9lan && 2413 hw->mac_type != em_ich10lan) { 2414 /* Configure activity LED after PHY reset */ 2415 led_ctrl = E1000_READ_REG(hw, LEDCTL); 2416 led_ctrl &= IGP_ACTIVITY_LED_MASK; 2417 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 2418 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 2419 } 2420 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */ 2421 if (hw->phy_type == em_phy_igp) { 2422 /* disable lplu d3 during driver init */ 2423 ret_val = em_set_d3_lplu_state(hw, FALSE); 2424 if (ret_val) { 2425 DEBUGOUT("Error Disabling LPLU D3\n"); 2426 return ret_val; 2427 } 2428 } 2429 /* disable lplu d0 during driver init */ 2430 if (hw->mac_type == em_pchlan || 2431 hw->mac_type == em_pch2lan || 2432 hw->mac_type == em_pch_lpt || 2433 hw->mac_type == em_pch_spt || 2434 hw->mac_type == em_pch_cnp || 2435 hw->mac_type == em_pch_tgp || 2436 hw->mac_type == em_pch_adp) 2437 ret_val = em_set_lplu_state_pchlan(hw, FALSE); 2438 else 2439 ret_val = em_set_d0_lplu_state(hw, FALSE); 2440 if (ret_val) { 2441 DEBUGOUT("Error Disabling LPLU D0\n"); 2442 return ret_val; 2443 } 2444 /* Configure mdi-mdix settings */ 2445 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 2446 if (ret_val) 2447 return ret_val; 2448 2449 if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) { 2450 hw->dsp_config_state = em_dsp_config_disabled; 2451 /* Force MDI for earlier revs of the IGP PHY */ 2452 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | 2453 IGP01E1000_PSCR_FORCE_MDI_MDIX); 2454 hw->mdix = 1; 2455 2456 } else { 2457 hw->dsp_config_state = em_dsp_config_enabled; 2458 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 2459 2460 switch (hw->mdix) { 2461 case 1: 2462 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 2463 break; 2464 case 2: 2465 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; 2466 break; 2467 case 0: 2468 default: 2469 phy_data |= IGP01E1000_PSCR_AUTO_MDIX; 2470 break; 2471 } 2472 } 2473 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 2474 if (ret_val) 2475 return ret_val; 2476 2477 /* set auto-master slave resolution settings */ 2478 if (hw->autoneg) { 2479 em_ms_type phy_ms_setting = hw->master_slave; 2480 if (hw->ffe_config_state == em_ffe_config_active) 2481 hw->ffe_config_state = em_ffe_config_enabled; 2482 2483 if (hw->dsp_config_state == em_dsp_config_activated) 2484 hw->dsp_config_state = em_dsp_config_enabled; 2485 /* 2486 * when autonegotiation advertisement is only 1000Mbps then 2487 * we should disable SmartSpeed and enable Auto MasterSlave 2488 * resolution as hardware default. 2489 */ 2490 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) { 2491 /* Disable SmartSpeed */ 2492 ret_val = em_read_phy_reg(hw, 2493 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2494 if (ret_val) 2495 return ret_val; 2496 2497 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2498 ret_val = em_write_phy_reg(hw, 2499 IGP01E1000_PHY_PORT_CONFIG, phy_data); 2500 if (ret_val) 2501 return ret_val; 2502 /* Set auto Master/Slave resolution process */ 2503 ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, 2504 &phy_data); 2505 if (ret_val) 2506 return ret_val; 2507 2508 phy_data &= ~CR_1000T_MS_ENABLE; 2509 ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL, 2510 phy_data); 2511 if (ret_val) 2512 return ret_val; 2513 } 2514 ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); 2515 if (ret_val) 2516 return ret_val; 2517 2518 /* load defaults for future use */ 2519 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ? 2520 ((phy_data & CR_1000T_MS_VALUE) ? em_ms_force_master : 2521 em_ms_force_slave) : em_ms_auto; 2522 2523 switch (phy_ms_setting) { 2524 case em_ms_force_master: 2525 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 2526 break; 2527 case em_ms_force_slave: 2528 phy_data |= CR_1000T_MS_ENABLE; 2529 phy_data &= ~(CR_1000T_MS_VALUE); 2530 break; 2531 case em_ms_auto: 2532 phy_data &= ~CR_1000T_MS_ENABLE; 2533 break; 2534 default: 2535 break; 2536 } 2537 ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); 2538 if (ret_val) 2539 return ret_val; 2540 } 2541 return E1000_SUCCESS; 2542 } 2543 2544 /****************************************************************************** 2545 * Copper link setup for em_phy_gg82563 series. 2546 * 2547 * hw - Struct containing variables accessed by shared code 2548 *****************************************************************************/ 2549 static int32_t 2550 em_copper_link_ggp_setup(struct em_hw *hw) 2551 { 2552 int32_t ret_val; 2553 uint16_t phy_data; 2554 uint32_t reg_data; 2555 DEBUGFUNC("em_copper_link_ggp_setup"); 2556 2557 if (!hw->phy_reset_disable) { 2558 2559 /* Enable CRS on TX for half-duplex operation. */ 2560 ret_val = em_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 2561 &phy_data); 2562 if (ret_val) 2563 return ret_val; 2564 2565 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 2566 /* Use 25MHz for both link down and 1000BASE-T for Tx clock */ 2567 phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ; 2568 2569 ret_val = em_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 2570 phy_data); 2571 if (ret_val) 2572 return ret_val; 2573 /* 2574 * Options: MDI/MDI-X = 0 (default) 0 - Auto for all speeds 1 2575 * - MDI mode 2 - MDI-X mode 3 - Auto for 1000Base-T only 2576 * (MDI-X for 10/100Base-T modes) 2577 */ 2578 ret_val = em_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, 2579 &phy_data); 2580 2581 if (ret_val) 2582 return ret_val; 2583 2584 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK; 2585 2586 switch (hw->mdix) { 2587 case 1: 2588 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI; 2589 break; 2590 case 2: 2591 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX; 2592 break; 2593 case 0: 2594 default: 2595 phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO; 2596 break; 2597 } 2598 /* 2599 * Options: disable_polarity_correction = 0 (default) 2600 * Automatic Correction for Reversed Cable Polarity 0 - 2601 * Disabled 1 - Enabled 2602 */ 2603 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 2604 if (hw->disable_polarity_correction == 1) 2605 phy_data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 2606 ret_val = em_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, 2607 phy_data); 2608 2609 if (ret_val) 2610 return ret_val; 2611 2612 /* SW Reset the PHY so all changes take effect */ 2613 ret_val = em_phy_reset(hw); 2614 if (ret_val) { 2615 DEBUGOUT("Error Resetting the PHY\n"); 2616 return ret_val; 2617 } 2618 } /* phy_reset_disable */ 2619 if (hw->mac_type == em_80003es2lan) { 2620 /* Bypass RX and TX FIFO's */ 2621 ret_val = em_write_kmrn_reg(hw, 2622 E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL, 2623 E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS | 2624 E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS); 2625 if (ret_val) 2626 return ret_val; 2627 2628 ret_val = em_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, 2629 &phy_data); 2630 if (ret_val) 2631 return ret_val; 2632 2633 phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG; 2634 ret_val = em_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, 2635 phy_data); 2636 2637 if (ret_val) 2638 return ret_val; 2639 2640 reg_data = E1000_READ_REG(hw, CTRL_EXT); 2641 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK); 2642 E1000_WRITE_REG(hw, CTRL_EXT, reg_data); 2643 2644 ret_val = em_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, 2645 &phy_data); 2646 if (ret_val) 2647 return ret_val; 2648 /* 2649 * Do not init these registers when the HW is in IAMT mode, 2650 * since the firmware will have already initialized them. We 2651 * only initialize them if the HW is not in IAMT mode. 2652 */ 2653 if (em_check_mng_mode(hw) == FALSE) { 2654 /* Enable Electrical Idle on the PHY */ 2655 phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; 2656 ret_val = em_write_phy_reg(hw, 2657 GG82563_PHY_PWR_MGMT_CTRL, phy_data); 2658 if (ret_val) 2659 return ret_val; 2660 2661 ret_val = em_read_phy_reg(hw, 2662 GG82563_PHY_KMRN_MODE_CTRL, &phy_data); 2663 if (ret_val) 2664 return ret_val; 2665 2666 phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 2667 ret_val = em_write_phy_reg(hw, 2668 GG82563_PHY_KMRN_MODE_CTRL, phy_data); 2669 2670 if (ret_val) 2671 return ret_val; 2672 } 2673 /* 2674 * Workaround: Disable padding in Kumeran interface in the 2675 * MAC and in the PHY to avoid CRC errors. 2676 */ 2677 ret_val = em_read_phy_reg(hw, GG82563_PHY_INBAND_CTRL, 2678 &phy_data); 2679 if (ret_val) 2680 return ret_val; 2681 phy_data |= GG82563_ICR_DIS_PADDING; 2682 ret_val = em_write_phy_reg(hw, GG82563_PHY_INBAND_CTRL, 2683 phy_data); 2684 if (ret_val) 2685 return ret_val; 2686 } 2687 return E1000_SUCCESS; 2688 } 2689 2690 /****************************************************************************** 2691 * Copper link setup for em_phy_m88 series. 2692 * 2693 * hw - Struct containing variables accessed by shared code 2694 *****************************************************************************/ 2695 static int32_t 2696 em_copper_link_mgp_setup(struct em_hw *hw) 2697 { 2698 int32_t ret_val; 2699 uint16_t phy_data; 2700 DEBUGFUNC("em_copper_link_mgp_setup"); 2701 2702 if (hw->phy_reset_disable) 2703 return E1000_SUCCESS; 2704 2705 /* disable lplu d0 during driver init */ 2706 if (hw->mac_type == em_pchlan || 2707 hw->mac_type == em_pch2lan || 2708 hw->mac_type == em_pch_lpt || 2709 hw->mac_type == em_pch_spt || 2710 hw->mac_type == em_pch_cnp || 2711 hw->mac_type == em_pch_tgp || 2712 hw->mac_type == em_pch_adp) 2713 ret_val = em_set_lplu_state_pchlan(hw, FALSE); 2714 2715 /* Enable CRS on TX. This must be set for half-duplex operation. */ 2716 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 2717 if (ret_val) 2718 return ret_val; 2719 2720 if (hw->phy_id == M88E1141_E_PHY_ID) { 2721 phy_data |= 0x00000008; 2722 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 2723 phy_data); 2724 if (ret_val) 2725 return ret_val; 2726 2727 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 2728 &phy_data); 2729 if (ret_val) 2730 return ret_val; 2731 2732 phy_data &= ~M88E1000_PSCR_ASSERT_CRS_ON_TX; 2733 2734 } 2735 /* For BM PHY this bit is downshift enable */ 2736 else if (hw->phy_type != em_phy_bm) 2737 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 2738 /* 2739 * Options: MDI/MDI-X = 0 (default) 0 - Auto for all speeds 1 - MDI 2740 * mode 2 - MDI-X mode 3 - Auto for 1000Base-T only (MDI-X for 2741 * 10/100Base-T modes) 2742 */ 2743 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 2744 2745 switch (hw->mdix) { 2746 case 1: 2747 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 2748 break; 2749 case 2: 2750 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 2751 break; 2752 case 3: 2753 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 2754 break; 2755 case 0: 2756 default: 2757 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 2758 break; 2759 } 2760 /* 2761 * Options: disable_polarity_correction = 0 (default) Automatic 2762 * Correction for Reversed Cable Polarity 0 - Disabled 1 - Enabled 2763 */ 2764 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 2765 if (hw->disable_polarity_correction == 1) 2766 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 2767 2768 /* Enable downshift on BM (disabled by default) */ 2769 if (hw->phy_type == em_phy_bm) 2770 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT; 2771 2772 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 2773 if (ret_val) 2774 return ret_val; 2775 2776 if (((hw->phy_type == em_phy_m88) && 2777 (hw->phy_revision < M88E1011_I_REV_4) && 2778 (hw->phy_id != BME1000_E_PHY_ID)) || 2779 (hw->phy_type == em_phy_oem)) { 2780 /* 2781 * Force TX_CLK in the Extended PHY Specific Control Register 2782 * to 25MHz clock. 2783 */ 2784 ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 2785 &phy_data); 2786 if (ret_val) 2787 return ret_val; 2788 2789 if (hw->phy_type == em_phy_oem) { 2790 phy_data |= M88E1000_EPSCR_TX_TIME_CTRL; 2791 phy_data |= M88E1000_EPSCR_RX_TIME_CTRL; 2792 } 2793 phy_data |= M88E1000_EPSCR_TX_CLK_25; 2794 2795 if ((hw->phy_revision == E1000_REVISION_2) && 2796 (hw->phy_id == M88E1111_I_PHY_ID)) { 2797 /* Vidalia Phy, set the downshift counter to 5x */ 2798 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK); 2799 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; 2800 ret_val = em_write_phy_reg(hw, 2801 M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 2802 if (ret_val) 2803 return ret_val; 2804 } else { 2805 /* Configure Master and Slave downshift values */ 2806 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 2807 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 2808 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 2809 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 2810 ret_val = em_write_phy_reg(hw, 2811 M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 2812 if (ret_val) 2813 return ret_val; 2814 } 2815 } 2816 if ((hw->phy_type == em_phy_bm) && (hw->phy_revision == 1)) { 2817 /* 2818 * Set PHY page 0, register 29 to 0x0003 2819 * The next two writes are supposed to lower BER for gig 2820 * connection 2821 */ 2822 ret_val = em_write_phy_reg(hw, BM_REG_BIAS1, 0x0003); 2823 if (ret_val) 2824 return ret_val; 2825 2826 /* Set PHY page 0, register 30 to 0x0000 */ 2827 ret_val = em_write_phy_reg(hw, BM_REG_BIAS2, 0x0000); 2828 if (ret_val) 2829 return ret_val; 2830 } 2831 if (hw->phy_type == em_phy_82578) { 2832 ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 2833 &phy_data); 2834 if (ret_val) 2835 return ret_val; 2836 2837 /* 82578 PHY - set the downshift count to 1x. */ 2838 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE; 2839 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK; 2840 ret_val = em_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 2841 phy_data); 2842 if (ret_val) 2843 return ret_val; 2844 } 2845 /* SW Reset the PHY so all changes take effect */ 2846 ret_val = em_phy_reset(hw); 2847 if (ret_val) { 2848 DEBUGOUT("Error Resetting the PHY\n"); 2849 return ret_val; 2850 } 2851 return E1000_SUCCESS; 2852 } 2853 2854 /****************************************************************************** 2855 * Copper link setup for em_phy_82577 series. 2856 * 2857 * hw - Struct containing variables accessed by shared code 2858 *****************************************************************************/ 2859 static int32_t 2860 em_copper_link_82577_setup(struct em_hw *hw) 2861 { 2862 int32_t ret_val; 2863 uint16_t phy_data; 2864 uint32_t led_ctl; 2865 DEBUGFUNC("em_copper_link_82577_setup"); 2866 2867 if (hw->phy_reset_disable) 2868 return E1000_SUCCESS; 2869 2870 /* Enable CRS on TX for half-duplex operation. */ 2871 ret_val = em_read_phy_reg(hw, I82577_PHY_CFG_REG, &phy_data); 2872 if (ret_val) 2873 return ret_val; 2874 2875 phy_data |= I82577_PHY_CFG_ENABLE_CRS_ON_TX | 2876 I82577_PHY_CFG_ENABLE_DOWNSHIFT; 2877 2878 ret_val = em_write_phy_reg(hw, I82577_PHY_CFG_REG, phy_data); 2879 if (ret_val) 2880 return ret_val; 2881 2882 /* Wait 15ms for MAC to configure PHY from eeprom settings */ 2883 msec_delay(15); 2884 led_ctl = hw->ledctl_mode1; 2885 2886 /* disable lplu d0 during driver init */ 2887 ret_val = em_set_lplu_state_pchlan(hw, FALSE); 2888 if (ret_val) { 2889 DEBUGOUT("Error Disabling LPLU D0\n"); 2890 return ret_val; 2891 } 2892 2893 E1000_WRITE_REG(hw, LEDCTL, led_ctl); 2894 2895 return E1000_SUCCESS; 2896 } 2897 2898 static int32_t 2899 em_copper_link_82580_setup(struct em_hw *hw) 2900 { 2901 int32_t ret_val; 2902 uint16_t phy_data; 2903 2904 if (hw->phy_reset_disable) 2905 return E1000_SUCCESS; 2906 2907 ret_val = em_phy_reset(hw); 2908 if (ret_val) 2909 goto out; 2910 2911 /* Enable CRS on TX. This must be set for half-duplex operation. */ 2912 ret_val = em_read_phy_reg(hw, I82580_CFG_REG, &phy_data); 2913 if (ret_val) 2914 goto out; 2915 2916 phy_data |= I82580_CFG_ASSERT_CRS_ON_TX | 2917 I82580_CFG_ENABLE_DOWNSHIFT; 2918 2919 ret_val = em_write_phy_reg(hw, I82580_CFG_REG, phy_data); 2920 2921 out: 2922 return ret_val; 2923 } 2924 2925 static int32_t 2926 em_copper_link_rtl8211_setup(struct em_hw *hw) 2927 { 2928 int32_t ret_val; 2929 uint16_t phy_data; 2930 2931 DEBUGFUNC("em_copper_link_rtl8211_setup: begin"); 2932 2933 if (!hw) { 2934 return -1; 2935 } 2936 /* SW Reset the PHY so all changes take effect */ 2937 em_phy_hw_reset(hw); 2938 2939 /* Enable CRS on TX. This must be set for half-duplex operation. */ 2940 phy_data = 0; 2941 2942 ret_val = em_read_phy_reg_ex(hw, RGEPHY_CR, &phy_data); 2943 if (ret_val) { 2944 printf("Unable to read RGEPHY_CR register\n"); 2945 return ret_val; 2946 } 2947 DEBUGOUT3("RTL8211: Rx phy_id=%X addr=%X SPEC_CTRL=%X\n", hw->phy_id, 2948 hw->phy_addr, phy_data); 2949 phy_data |= RGEPHY_CR_ASSERT_CRS; 2950 2951 ret_val = em_write_phy_reg_ex(hw, RGEPHY_CR, phy_data); 2952 if (ret_val) { 2953 printf("Unable to write RGEPHY_CR register\n"); 2954 return ret_val; 2955 } 2956 2957 phy_data = 0; /* LED Control Register 0x18 */ 2958 ret_val = em_read_phy_reg_ex(hw, RGEPHY_LC, &phy_data); 2959 if (ret_val) { 2960 printf("Unable to read RGEPHY_LC register\n"); 2961 return ret_val; 2962 } 2963 2964 phy_data &= 0x80FF; /* bit-15=0 disable, clear bit 8-10 */ 2965 ret_val = em_write_phy_reg_ex(hw, RGEPHY_LC, phy_data); 2966 if (ret_val) { 2967 printf("Unable to write RGEPHY_LC register\n"); 2968 return ret_val; 2969 } 2970 /* LED Control and Definition Register 0x11, PHY spec status reg */ 2971 phy_data = 0; 2972 ret_val = em_read_phy_reg_ex(hw, RGEPHY_SR, &phy_data); 2973 if (ret_val) { 2974 printf("Unable to read RGEPHY_SR register\n"); 2975 return ret_val; 2976 } 2977 2978 phy_data |= 0x0010; /* LED active Low */ 2979 ret_val = em_write_phy_reg_ex(hw, RGEPHY_SR, phy_data); 2980 if (ret_val) { 2981 printf("Unable to write RGEPHY_SR register\n"); 2982 return ret_val; 2983 } 2984 2985 phy_data = 0; 2986 ret_val = em_read_phy_reg_ex(hw, RGEPHY_SR, &phy_data); 2987 if (ret_val) { 2988 printf("Unable to read RGEPHY_SR register\n"); 2989 return ret_val; 2990 } 2991 2992 /* Switch to Page2 */ 2993 phy_data = RGEPHY_PS_PAGE_2; 2994 ret_val = em_write_phy_reg_ex(hw, RGEPHY_PS, phy_data); 2995 if (ret_val) { 2996 printf("Unable to write PHY RGEPHY_PS register\n"); 2997 return ret_val; 2998 } 2999 3000 phy_data = 0x0000; 3001 ret_val = em_write_phy_reg_ex(hw, RGEPHY_LC_P2, phy_data); 3002 if (ret_val) { 3003 printf("Unable to write RGEPHY_LC_P2 register\n"); 3004 return ret_val; 3005 } 3006 usec_delay(5); 3007 3008 3009 /* LED Configuration Control Reg for setting for 0x1A Register */ 3010 phy_data = 0; 3011 ret_val = em_read_phy_reg_ex(hw, RGEPHY_LC_P2, &phy_data); 3012 if (ret_val) { 3013 printf("Unable to read RGEPHY_LC_P2 register\n"); 3014 return ret_val; 3015 } 3016 3017 phy_data &= 0xF000; 3018 phy_data |= 0x0F24; 3019 ret_val = em_write_phy_reg_ex(hw, RGEPHY_LC_P2, phy_data); 3020 if (ret_val) { 3021 printf("Unable to write RGEPHY_LC_P2 register\n"); 3022 return ret_val; 3023 } 3024 phy_data = 0; 3025 ret_val= em_read_phy_reg_ex(hw, RGEPHY_LC_P2, &phy_data); 3026 if (ret_val) { 3027 printf("Unable to read RGEPHY_LC_P2 register\n"); 3028 return ret_val; 3029 } 3030 DEBUGOUT1("RTL8211:ReadBack for check, LED_CFG->data=%X\n", phy_data); 3031 3032 3033 /* After setting Page2, go back to Page 0 */ 3034 phy_data = 0; 3035 ret_val = em_write_phy_reg_ex(hw, RGEPHY_PS, phy_data); 3036 if (ret_val) { 3037 printf("Unable to write PHY RGEPHY_PS register\n"); 3038 return ret_val; 3039 } 3040 3041 /* pulse streching= 42-84ms, blink rate=84mm */ 3042 phy_data = 0x140 | RGEPHY_LC_PULSE_42MS | RGEPHY_LC_LINK | 3043 RGEPHY_LC_DUPLEX | RGEPHY_LC_RX; 3044 3045 ret_val = em_write_phy_reg_ex(hw, RGEPHY_LC, phy_data); 3046 if (ret_val) { 3047 printf("Unable to write RGEPHY_LC register\n"); 3048 return ret_val; 3049 } 3050 return E1000_SUCCESS; 3051 } 3052 3053 /****************************************************************************** 3054 * Setup auto-negotiation and flow control advertisements, 3055 * and then perform auto-negotiation. 3056 * 3057 * hw - Struct containing variables accessed by shared code 3058 *****************************************************************************/ 3059 int32_t 3060 em_copper_link_autoneg(struct em_hw *hw) 3061 { 3062 int32_t ret_val; 3063 uint16_t phy_data; 3064 DEBUGFUNC("em_copper_link_autoneg"); 3065 /* 3066 * Perform some bounds checking on the hw->autoneg_advertised 3067 * parameter. If this variable is zero, then set it to the default. 3068 */ 3069 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT; 3070 /* 3071 * If autoneg_advertised is zero, we assume it was not defaulted by 3072 * the calling code so we set to advertise full capability. 3073 */ 3074 if (hw->autoneg_advertised == 0) 3075 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 3076 3077 /* IFE phy only supports 10/100 */ 3078 if (hw->phy_type == em_phy_ife) 3079 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL; 3080 3081 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); 3082 ret_val = em_phy_setup_autoneg(hw); 3083 if (ret_val) { 3084 DEBUGOUT("Error Setting up Auto-Negotiation\n"); 3085 return ret_val; 3086 } 3087 DEBUGOUT("Restarting Auto-Neg\n"); 3088 /* 3089 * Restart auto-negotiation by setting the Auto Neg Enable bit and 3090 * the Auto Neg Restart bit in the PHY control register. 3091 */ 3092 ret_val = em_read_phy_reg(hw, PHY_CTRL, &phy_data); 3093 if (ret_val) 3094 return ret_val; 3095 3096 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 3097 ret_val = em_write_phy_reg(hw, PHY_CTRL, phy_data); 3098 if (ret_val) 3099 return ret_val; 3100 /* 3101 * Does the user want to wait for Auto-Neg to complete here, or check 3102 * at a later time (for example, callback routine). 3103 */ 3104 if (hw->wait_autoneg_complete) { 3105 ret_val = em_wait_autoneg(hw); 3106 if (ret_val) { 3107 DEBUGOUT("Error while waiting for autoneg to complete\n" 3108 ); 3109 return ret_val; 3110 } 3111 } 3112 hw->get_link_status = TRUE; 3113 3114 return E1000_SUCCESS; 3115 } 3116 3117 /****************************************************************************** 3118 * Config the MAC and the PHY after link is up. 3119 * 1) Set up the MAC to the current PHY speed/duplex 3120 * if we are on 82543. If we 3121 * are on newer silicon, we only need to configure 3122 * collision distance in the Transmit Control Register. 3123 * 2) Set up flow control on the MAC to that established with 3124 * the link partner. 3125 * 3) Config DSP to improve Gigabit link quality for some PHY revisions. 3126 * 3127 * hw - Struct containing variables accessed by shared code 3128 *****************************************************************************/ 3129 int32_t 3130 em_copper_link_postconfig(struct em_hw *hw) 3131 { 3132 int32_t ret_val; 3133 DEBUGFUNC("em_copper_link_postconfig"); 3134 3135 if (hw->mac_type >= em_82544 && 3136 hw->mac_type != em_icp_xxxx) { 3137 em_config_collision_dist(hw); 3138 } else { 3139 ret_val = em_config_mac_to_phy(hw); 3140 if (ret_val) { 3141 DEBUGOUT("Error configuring MAC to PHY settings\n"); 3142 return ret_val; 3143 } 3144 } 3145 ret_val = em_config_fc_after_link_up(hw); 3146 if (ret_val) { 3147 DEBUGOUT("Error Configuring Flow Control\n"); 3148 return ret_val; 3149 } 3150 /* Config DSP to improve Giga link quality */ 3151 if (hw->phy_type == em_phy_igp) { 3152 ret_val = em_config_dsp_after_link_change(hw, TRUE); 3153 if (ret_val) { 3154 DEBUGOUT("Error Configuring DSP after link up\n"); 3155 return ret_val; 3156 } 3157 } 3158 return E1000_SUCCESS; 3159 } 3160 3161 /****************************************************************************** 3162 * Detects which PHY is present and setup the speed and duplex 3163 * 3164 * hw - Struct containing variables accessed by shared code 3165 *****************************************************************************/ 3166 static int32_t 3167 em_setup_copper_link(struct em_hw *hw) 3168 { 3169 int32_t ret_val; 3170 uint16_t i; 3171 uint16_t phy_data; 3172 uint16_t reg_data; 3173 DEBUGFUNC("em_setup_copper_link"); 3174 3175 switch (hw->mac_type) { 3176 case em_80003es2lan: 3177 case em_ich8lan: 3178 case em_ich9lan: 3179 case em_ich10lan: 3180 case em_pchlan: 3181 case em_pch2lan: 3182 case em_pch_lpt: 3183 case em_pch_spt: 3184 case em_pch_cnp: 3185 case em_pch_tgp: 3186 case em_pch_adp: 3187 /* 3188 * Set the mac to wait the maximum time between each 3189 * iteration and increase the max iterations when polling the 3190 * phy; this fixes erroneous timeouts at 10Mbps. 3191 */ 3192 ret_val = em_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF); 3193 if (ret_val) 3194 return ret_val; 3195 ret_val = em_read_kmrn_reg(hw, GG82563_REG(0x34, 9), 3196 ®_data); 3197 if (ret_val) 3198 return ret_val; 3199 reg_data |= 0x3F; 3200 ret_val = em_write_kmrn_reg(hw, GG82563_REG(0x34, 9), 3201 reg_data); 3202 if (ret_val) 3203 return ret_val; 3204 default: 3205 break; 3206 } 3207 3208 /* Check if it is a valid PHY and set PHY mode if necessary. */ 3209 ret_val = em_copper_link_preconfig(hw); 3210 if (ret_val) 3211 return ret_val; 3212 3213 switch (hw->mac_type) { 3214 case em_80003es2lan: 3215 /* Kumeran registers are written-only */ 3216 reg_data = 3217 E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT; 3218 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING; 3219 ret_val = em_write_kmrn_reg(hw, 3220 E1000_KUMCTRLSTA_OFFSET_INB_CTRL, reg_data); 3221 if (ret_val) 3222 return ret_val; 3223 break; 3224 default: 3225 break; 3226 } 3227 3228 if (hw->phy_type == em_phy_igp || 3229 hw->phy_type == em_phy_igp_3 || 3230 hw->phy_type == em_phy_igp_2) { 3231 ret_val = em_copper_link_igp_setup(hw); 3232 if (ret_val) 3233 return ret_val; 3234 } else if (hw->phy_type == em_phy_m88 || 3235 hw->phy_type == em_phy_bm || 3236 hw->phy_type == em_phy_oem || 3237 hw->phy_type == em_phy_82578) { 3238 ret_val = em_copper_link_mgp_setup(hw); 3239 if (ret_val) 3240 return ret_val; 3241 } else if (hw->phy_type == em_phy_gg82563) { 3242 ret_val = em_copper_link_ggp_setup(hw); 3243 if (ret_val) 3244 return ret_val; 3245 } else if (hw->phy_type == em_phy_82577 || 3246 hw->phy_type == em_phy_82579 || 3247 hw->phy_type == em_phy_i217) { 3248 ret_val = em_copper_link_82577_setup(hw); 3249 if (ret_val) 3250 return ret_val; 3251 } else if (hw->phy_type == em_phy_82580) { 3252 ret_val = em_copper_link_82580_setup(hw); 3253 if (ret_val) 3254 return ret_val; 3255 } else if (hw->phy_type == em_phy_rtl8211) { 3256 ret_val = em_copper_link_rtl8211_setup(hw); 3257 if (ret_val) 3258 return ret_val; 3259 } 3260 if (hw->autoneg) { 3261 /* 3262 * Setup autoneg and flow control advertisement and perform 3263 * autonegotiation 3264 */ 3265 ret_val = em_copper_link_autoneg(hw); 3266 if (ret_val) 3267 return ret_val; 3268 } else { 3269 /* 3270 * PHY will be set to 10H, 10F, 100H,or 100F depending on 3271 * value from forced_speed_duplex. 3272 */ 3273 DEBUGOUT("Forcing speed and duplex\n"); 3274 ret_val = em_phy_force_speed_duplex(hw); 3275 if (ret_val) { 3276 DEBUGOUT("Error Forcing Speed and Duplex\n"); 3277 return ret_val; 3278 } 3279 } 3280 /* 3281 * Check link status. Wait up to 100 microseconds for link to become 3282 * valid. 3283 */ 3284 for (i = 0; i < 10; i++) { 3285 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 3286 if (ret_val) 3287 return ret_val; 3288 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 3289 if (ret_val) 3290 return ret_val; 3291 3292 hw->icp_xxxx_is_link_up = (phy_data & MII_SR_LINK_STATUS) != 0; 3293 3294 if (phy_data & MII_SR_LINK_STATUS) { 3295 /* Config the MAC and PHY after link is up */ 3296 ret_val = em_copper_link_postconfig(hw); 3297 if (ret_val) 3298 return ret_val; 3299 3300 DEBUGOUT("Valid link established!!!\n"); 3301 return E1000_SUCCESS; 3302 } 3303 usec_delay(10); 3304 } 3305 3306 DEBUGOUT("Unable to establish link!!!\n"); 3307 return E1000_SUCCESS; 3308 } 3309 3310 /****************************************************************************** 3311 * Configure the MAC-to-PHY interface for 10/100Mbps 3312 * 3313 * hw - Struct containing variables accessed by shared code 3314 *****************************************************************************/ 3315 static int32_t 3316 em_configure_kmrn_for_10_100(struct em_hw *hw, uint16_t duplex) 3317 { 3318 int32_t ret_val = E1000_SUCCESS; 3319 uint32_t tipg; 3320 uint16_t reg_data; 3321 DEBUGFUNC("em_configure_kmrn_for_10_100"); 3322 3323 reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT; 3324 ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL, 3325 reg_data); 3326 if (ret_val) 3327 return ret_val; 3328 3329 /* Configure Transmit Inter-Packet Gap */ 3330 tipg = E1000_READ_REG(hw, TIPG); 3331 tipg &= ~E1000_TIPG_IPGT_MASK; 3332 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100; 3333 E1000_WRITE_REG(hw, TIPG, tipg); 3334 3335 ret_val = em_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); 3336 3337 if (ret_val) 3338 return ret_val; 3339 3340 if (duplex == HALF_DUPLEX) 3341 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER; 3342 else 3343 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 3344 3345 ret_val = em_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 3346 3347 return ret_val; 3348 } 3349 3350 static int32_t 3351 em_configure_kmrn_for_1000(struct em_hw *hw) 3352 { 3353 int32_t ret_val = E1000_SUCCESS; 3354 uint16_t reg_data; 3355 uint32_t tipg; 3356 DEBUGFUNC("em_configure_kmrn_for_1000"); 3357 3358 reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT; 3359 ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL, 3360 reg_data); 3361 if (ret_val) 3362 return ret_val; 3363 3364 /* Configure Transmit Inter-Packet Gap */ 3365 tipg = E1000_READ_REG(hw, TIPG); 3366 tipg &= ~E1000_TIPG_IPGT_MASK; 3367 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; 3368 E1000_WRITE_REG(hw, TIPG, tipg); 3369 3370 ret_val = em_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); 3371 3372 if (ret_val) 3373 return ret_val; 3374 3375 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 3376 ret_val = em_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 3377 3378 return ret_val; 3379 } 3380 3381 /****************************************************************************** 3382 * Configures PHY autoneg and flow control advertisement settings 3383 * 3384 * hw - Struct containing variables accessed by shared code 3385 *****************************************************************************/ 3386 int32_t 3387 em_phy_setup_autoneg(struct em_hw *hw) 3388 { 3389 int32_t ret_val; 3390 uint16_t mii_autoneg_adv_reg; 3391 uint16_t mii_1000t_ctrl_reg; 3392 DEBUGFUNC("em_phy_setup_autoneg"); 3393 3394 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 3395 ret_val = em_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 3396 if (ret_val) 3397 return ret_val; 3398 3399 if (hw->phy_type != em_phy_ife) { 3400 /* Read the MII 1000Base-T Control Register (Address 9). */ 3401 ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, 3402 &mii_1000t_ctrl_reg); 3403 if (ret_val) 3404 return ret_val; 3405 } else 3406 mii_1000t_ctrl_reg = 0; 3407 /* 3408 * Need to parse both autoneg_advertised and fc and set up the 3409 * appropriate PHY registers. First we will parse for 3410 * autoneg_advertised software override. Since we can advertise a 3411 * plethora of combinations, we need to check each bit individually. 3412 */ 3413 /* 3414 * First we clear all the 10/100 mb speed bits in the Auto-Neg 3415 * Advertisement Register (Address 4) and the 1000 mb speed bits in 3416 * the 1000Base-T Control Register (Address 9). 3417 */ 3418 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK; 3419 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK; 3420 3421 DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised); 3422 3423 /* Do we want to advertise 10 Mb Half Duplex? */ 3424 if (hw->autoneg_advertised & ADVERTISE_10_HALF) { 3425 DEBUGOUT("Advertise 10mb Half duplex\n"); 3426 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 3427 } 3428 /* Do we want to advertise 10 Mb Full Duplex? */ 3429 if (hw->autoneg_advertised & ADVERTISE_10_FULL) { 3430 DEBUGOUT("Advertise 10mb Full duplex\n"); 3431 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 3432 } 3433 /* Do we want to advertise 100 Mb Half Duplex? */ 3434 if (hw->autoneg_advertised & ADVERTISE_100_HALF) { 3435 DEBUGOUT("Advertise 100mb Half duplex\n"); 3436 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 3437 } 3438 /* Do we want to advertise 100 Mb Full Duplex? */ 3439 if (hw->autoneg_advertised & ADVERTISE_100_FULL) { 3440 DEBUGOUT("Advertise 100mb Full duplex\n"); 3441 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 3442 } 3443 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 3444 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) { 3445 DEBUGOUT("Advertise 1000mb Half duplex requested, request" 3446 " denied!\n"); 3447 } 3448 /* Do we want to advertise 1000 Mb Full Duplex? */ 3449 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) { 3450 DEBUGOUT("Advertise 1000mb Full duplex\n"); 3451 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 3452 if (hw->phy_type == em_phy_ife) { 3453 DEBUGOUT("em_phy_ife is a 10/100 PHY. Gigabit speed is" 3454 " not supported.\n"); 3455 } 3456 } 3457 /* 3458 * Check for a software override of the flow control settings, and 3459 * setup the PHY advertisement registers accordingly. If 3460 * auto-negotiation is enabled, then software will have to set the 3461 * "PAUSE" bits to the correct value in the Auto-Negotiation 3462 * Advertisement Register (PHY_AUTONEG_ADV) and re-start 3463 * auto-negotiation. 3464 * 3465 * The possible values of the "fc" parameter are: 0: Flow control is 3466 * completely disabled 1: Rx flow control is enabled (we can receive 3467 * pause frames but not send pause frames). 2: Tx flow control is 3468 * enabled (we can send pause frames but we do not support receiving 3469 * pause frames). 3: Both Rx and TX flow control (symmetric) are 3470 * enabled. other: No software override. The flow control 3471 * configuration in the EEPROM is used. 3472 */ 3473 switch (hw->fc) { 3474 case E1000_FC_NONE: /* 0 */ 3475 /* 3476 * Flow control (RX & TX) is completely disabled by a 3477 * software over-ride. 3478 */ 3479 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 3480 break; 3481 case E1000_FC_RX_PAUSE:/* 1 */ 3482 /* 3483 * RX Flow control is enabled, and TX Flow control is 3484 * disabled, by a software over-ride. 3485 */ 3486 /* 3487 * Since there really isn't a way to advertise that we are 3488 * capable of RX Pause ONLY, we will advertise that we 3489 * support both symmetric and asymmetric RX PAUSE. Later (in 3490 * em_config_fc_after_link_up) we will disable the hw's 3491 * ability to send PAUSE frames. 3492 */ 3493 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 3494 break; 3495 case E1000_FC_TX_PAUSE:/* 2 */ 3496 /* 3497 * TX Flow control is enabled, and RX Flow control is 3498 * disabled, by a software over-ride. 3499 */ 3500 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 3501 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 3502 break; 3503 case E1000_FC_FULL: /* 3 */ 3504 /* 3505 * Flow control (both RX and TX) is enabled by a software 3506 * over-ride. 3507 */ 3508 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 3509 break; 3510 default: 3511 DEBUGOUT("Flow control param set incorrectly\n"); 3512 return -E1000_ERR_CONFIG; 3513 } 3514 3515 ret_val = em_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 3516 if (ret_val) 3517 return ret_val; 3518 3519 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 3520 3521 if (hw->phy_type != em_phy_ife) { 3522 ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL, 3523 mii_1000t_ctrl_reg); 3524 if (ret_val) 3525 return ret_val; 3526 } 3527 return E1000_SUCCESS; 3528 } 3529 /****************************************************************************** 3530 * Force PHY speed and duplex settings to hw->forced_speed_duplex 3531 * 3532 * hw - Struct containing variables accessed by shared code 3533 *****************************************************************************/ 3534 static int32_t 3535 em_phy_force_speed_duplex(struct em_hw *hw) 3536 { 3537 uint32_t ctrl; 3538 int32_t ret_val; 3539 uint16_t mii_ctrl_reg; 3540 uint16_t mii_status_reg; 3541 uint16_t phy_data; 3542 uint16_t i; 3543 DEBUGFUNC("em_phy_force_speed_duplex"); 3544 3545 /* Turn off Flow control if we are forcing speed and duplex. */ 3546 hw->fc = E1000_FC_NONE; 3547 3548 DEBUGOUT1("hw->fc = %d\n", hw->fc); 3549 3550 /* Read the Device Control Register. */ 3551 ctrl = E1000_READ_REG(hw, CTRL); 3552 3553 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */ 3554 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 3555 ctrl &= ~(DEVICE_SPEED_MASK); 3556 3557 /* Clear the Auto Speed Detect Enable bit. */ 3558 ctrl &= ~E1000_CTRL_ASDE; 3559 3560 /* Read the MII Control Register. */ 3561 ret_val = em_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg); 3562 if (ret_val) 3563 return ret_val; 3564 3565 /* We need to disable autoneg in order to force link and duplex. */ 3566 3567 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN; 3568 3569 /* Are we forcing Full or Half Duplex? */ 3570 if (hw->forced_speed_duplex == em_100_full || 3571 hw->forced_speed_duplex == em_10_full) { 3572 /* 3573 * We want to force full duplex so we SET the full duplex 3574 * bits in the Device and MII Control Registers. 3575 */ 3576 ctrl |= E1000_CTRL_FD; 3577 mii_ctrl_reg |= MII_CR_FULL_DUPLEX; 3578 DEBUGOUT("Full Duplex\n"); 3579 } else { 3580 /* 3581 * We want to force half duplex so we CLEAR the full duplex 3582 * bits in the Device and MII Control Registers. 3583 */ 3584 ctrl &= ~E1000_CTRL_FD; 3585 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX; 3586 DEBUGOUT("Half Duplex\n"); 3587 } 3588 3589 /* Are we forcing 100Mbps??? */ 3590 if (hw->forced_speed_duplex == em_100_full || 3591 hw->forced_speed_duplex == em_100_half) { 3592 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */ 3593 ctrl |= E1000_CTRL_SPD_100; 3594 mii_ctrl_reg |= MII_CR_SPEED_100; 3595 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); 3596 DEBUGOUT("Forcing 100mb "); 3597 } else { 3598 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */ 3599 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 3600 mii_ctrl_reg |= MII_CR_SPEED_10; 3601 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); 3602 DEBUGOUT("Forcing 10mb "); 3603 } 3604 3605 em_config_collision_dist(hw); 3606 3607 /* Write the configured values back to the Device Control Reg. */ 3608 E1000_WRITE_REG(hw, CTRL, ctrl); 3609 3610 if ((hw->phy_type == em_phy_m88) || 3611 (hw->phy_type == em_phy_gg82563) || 3612 (hw->phy_type == em_phy_bm) || 3613 (hw->phy_type == em_phy_oem || 3614 (hw->phy_type == em_phy_82578))) { 3615 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 3616 &phy_data); 3617 if (ret_val) 3618 return ret_val; 3619 /* 3620 * Clear Auto-Crossover to force MDI manually. M88E1000 3621 * requires MDI forced whenever speed are duplex are forced. 3622 */ 3623 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 3624 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 3625 phy_data); 3626 if (ret_val) 3627 return ret_val; 3628 3629 DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data); 3630 3631 /* Need to reset the PHY or these changes will be ignored */ 3632 mii_ctrl_reg |= MII_CR_RESET; 3633 3634 } 3635 else if (hw->phy_type == em_phy_rtl8211) { 3636 ret_val = em_read_phy_reg_ex(hw, RGEPHY_CR, &phy_data); 3637 if(ret_val) { 3638 printf("Unable to read RGEPHY_CR register\n" 3639 ); 3640 return ret_val; 3641 } 3642 3643 /* 3644 * Clear Auto-Crossover to force MDI manually. RTL8211 requires 3645 * MDI forced whenever speed are duplex are forced. 3646 */ 3647 3648 phy_data |= RGEPHY_CR_MDI_MASK; // enable MDIX 3649 ret_val = em_write_phy_reg_ex(hw, RGEPHY_CR, phy_data); 3650 if(ret_val) { 3651 printf("Unable to write RGEPHY_CR register\n"); 3652 return ret_val; 3653 } 3654 mii_ctrl_reg |= MII_CR_RESET; 3655 3656 } 3657 /* Disable MDI-X support for 10/100 */ 3658 else if (hw->phy_type == em_phy_ife) { 3659 ret_val = em_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data); 3660 if (ret_val) 3661 return ret_val; 3662 3663 phy_data &= ~IFE_PMC_AUTO_MDIX; 3664 phy_data &= ~IFE_PMC_FORCE_MDIX; 3665 3666 ret_val = em_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, phy_data); 3667 if (ret_val) 3668 return ret_val; 3669 } else { 3670 /* 3671 * Clear Auto-Crossover to force MDI manually. IGP requires 3672 * MDI forced whenever speed or duplex are forced. 3673 */ 3674 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, 3675 &phy_data); 3676 if (ret_val) 3677 return ret_val; 3678 3679 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 3680 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 3681 3682 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, 3683 phy_data); 3684 if (ret_val) 3685 return ret_val; 3686 } 3687 3688 /* Write back the modified PHY MII control register. */ 3689 ret_val = em_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg); 3690 if (ret_val) 3691 return ret_val; 3692 3693 usec_delay(1); 3694 /* 3695 * The wait_autoneg_complete flag may be a little misleading here. 3696 * Since we are forcing speed and duplex, Auto-Neg is not enabled. 3697 * But we do want to delay for a period while forcing only so we 3698 * don't generate false No Link messages. So we will wait here only 3699 * if the user has set wait_autoneg_complete to 1, which is the 3700 * default. 3701 */ 3702 if (hw->wait_autoneg_complete) { 3703 /* We will wait for autoneg to complete. */ 3704 DEBUGOUT("Waiting for forced speed/duplex link.\n"); 3705 mii_status_reg = 0; 3706 /* 3707 * We will wait for autoneg to complete or 4.5 seconds to 3708 * expire. 3709 */ 3710 for (i = PHY_FORCE_TIME; i > 0; i--) { 3711 /* 3712 * Read the MII Status Register and wait for Auto-Neg 3713 * Complete bit to be set. 3714 */ 3715 ret_val = em_read_phy_reg(hw, PHY_STATUS, 3716 &mii_status_reg); 3717 if (ret_val) 3718 return ret_val; 3719 3720 ret_val = em_read_phy_reg(hw, PHY_STATUS, 3721 &mii_status_reg); 3722 if (ret_val) 3723 return ret_val; 3724 3725 if (mii_status_reg & MII_SR_LINK_STATUS) 3726 break; 3727 msec_delay(100); 3728 } 3729 if ((i == 0) && 3730 ((hw->phy_type == em_phy_m88) || 3731 (hw->phy_type == em_phy_gg82563) || 3732 (hw->phy_type == em_phy_bm))) { 3733 /* 3734 * We didn't get link. Reset the DSP and wait again 3735 * for link. 3736 */ 3737 ret_val = em_phy_reset_dsp(hw); 3738 if (ret_val) { 3739 DEBUGOUT("Error Resetting PHY DSP\n"); 3740 return ret_val; 3741 } 3742 } 3743 /* 3744 * This loop will early-out if the link condition has been 3745 * met. 3746 */ 3747 for (i = PHY_FORCE_TIME; i > 0; i--) { 3748 if (mii_status_reg & MII_SR_LINK_STATUS) 3749 break; 3750 msec_delay(100); 3751 /* 3752 * Read the MII Status Register and wait for Auto-Neg 3753 * Complete bit to be set. 3754 */ 3755 ret_val = em_read_phy_reg(hw, PHY_STATUS, 3756 &mii_status_reg); 3757 if (ret_val) 3758 return ret_val; 3759 3760 ret_val = em_read_phy_reg(hw, PHY_STATUS, 3761 &mii_status_reg); 3762 if (ret_val) 3763 return ret_val; 3764 } 3765 } 3766 if (hw->phy_type == em_phy_m88 || 3767 hw->phy_type == em_phy_bm || 3768 hw->phy_type == em_phy_oem) { 3769 /* 3770 * Because we reset the PHY above, we need to re-force TX_CLK 3771 * in the Extended PHY Specific Control Register to 25MHz 3772 * clock. This value defaults back to a 2.5MHz clock when 3773 * the PHY is reset. 3774 */ 3775 ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 3776 &phy_data); 3777 if (ret_val) 3778 return ret_val; 3779 3780 phy_data |= M88E1000_EPSCR_TX_CLK_25; 3781 ret_val = em_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 3782 phy_data); 3783 if (ret_val) 3784 return ret_val; 3785 /* 3786 * In addition, because of the s/w reset above, we need to 3787 * enable CRS on TX. This must be set for both full and half 3788 * duplex operation. 3789 */ 3790 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 3791 &phy_data); 3792 if (ret_val) 3793 return ret_val; 3794 3795 if (hw->phy_id == M88E1141_E_PHY_ID) 3796 phy_data &= ~M88E1000_PSCR_ASSERT_CRS_ON_TX; 3797 else 3798 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 3799 3800 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 3801 phy_data); 3802 if (ret_val) 3803 return ret_val; 3804 3805 if ((hw->mac_type == em_82544 || hw->mac_type == em_82543) && 3806 (!hw->autoneg) && (hw->forced_speed_duplex == em_10_full || 3807 hw->forced_speed_duplex == em_10_half)) { 3808 ret_val = em_polarity_reversal_workaround(hw); 3809 if (ret_val) 3810 return ret_val; 3811 } 3812 } else if (hw->phy_type == em_phy_rtl8211) { 3813 /* 3814 * In addition, because of the s/w reset above, we need to enable 3815 * CRX on TX. This must be set for both full and half duplex 3816 * operation. 3817 */ 3818 3819 ret_val = em_read_phy_reg_ex(hw, RGEPHY_CR, &phy_data); 3820 if(ret_val) { 3821 printf("Unable to read RGEPHY_CR register\n"); 3822 return ret_val; 3823 } 3824 3825 phy_data &= ~RGEPHY_CR_ASSERT_CRS; 3826 ret_val = em_write_phy_reg_ex(hw, RGEPHY_CR, phy_data); 3827 if(ret_val) { 3828 printf("Unable to write RGEPHY_CR register\n"); 3829 return ret_val; 3830 } 3831 } else if (hw->phy_type == em_phy_gg82563) { 3832 /* 3833 * The TX_CLK of the Extended PHY Specific Control Register 3834 * defaults to 2.5MHz on a reset. We need to re-force it 3835 * back to 25MHz, if we're not in a forced 10/duplex 3836 * configuration. 3837 */ 3838 ret_val = em_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 3839 &phy_data); 3840 if (ret_val) 3841 return ret_val; 3842 3843 phy_data &= ~GG82563_MSCR_TX_CLK_MASK; 3844 if ((hw->forced_speed_duplex == em_10_full) || 3845 (hw->forced_speed_duplex == em_10_half)) 3846 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ; 3847 else 3848 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25MHZ; 3849 3850 /* Also due to the reset, we need to enable CRS on Tx. */ 3851 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 3852 3853 ret_val = em_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 3854 phy_data); 3855 if (ret_val) 3856 return ret_val; 3857 } 3858 return E1000_SUCCESS; 3859 } 3860 3861 /****************************************************************************** 3862 * Sets the collision distance in the Transmit Control register 3863 * 3864 * hw - Struct containing variables accessed by shared code 3865 * 3866 * Link should have been established previously. Reads the speed and duplex 3867 * information from the Device Status register. 3868 *****************************************************************************/ 3869 void 3870 em_config_collision_dist(struct em_hw *hw) 3871 { 3872 uint32_t tctl, coll_dist; 3873 DEBUGFUNC("em_config_collision_dist"); 3874 3875 if (hw->mac_type < em_82543) 3876 coll_dist = E1000_COLLISION_DISTANCE_82542; 3877 else 3878 coll_dist = E1000_COLLISION_DISTANCE; 3879 3880 tctl = E1000_READ_REG(hw, TCTL); 3881 3882 tctl &= ~E1000_TCTL_COLD; 3883 tctl |= coll_dist << E1000_COLD_SHIFT; 3884 3885 E1000_WRITE_REG(hw, TCTL, tctl); 3886 E1000_WRITE_FLUSH(hw); 3887 } 3888 3889 /****************************************************************************** 3890 * Sets MAC speed and duplex settings to reflect the those in the PHY 3891 * 3892 * hw - Struct containing variables accessed by shared code 3893 * mii_reg - data to write to the MII control register 3894 * 3895 * The contents of the PHY register containing the needed information need to 3896 * be passed in. 3897 *****************************************************************************/ 3898 static int32_t 3899 em_config_mac_to_phy(struct em_hw *hw) 3900 { 3901 uint32_t ctrl; 3902 int32_t ret_val; 3903 uint16_t phy_data; 3904 DEBUGFUNC("em_config_mac_to_phy"); 3905 /* 3906 * 82544 or newer MAC, Auto Speed Detection takes care of MAC 3907 * speed/duplex configuration. 3908 */ 3909 if (hw->mac_type >= em_82544 3910 && hw->mac_type != em_icp_xxxx) 3911 return E1000_SUCCESS; 3912 /* 3913 * Read the Device Control Register and set the bits to Force Speed 3914 * and Duplex. 3915 */ 3916 ctrl = E1000_READ_REG(hw, CTRL); 3917 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 3918 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); 3919 /* 3920 * Set up duplex in the Device Control and Transmit Control registers 3921 * depending on negotiated values. 3922 */ 3923 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 3924 if (ret_val) 3925 return ret_val; 3926 3927 if (phy_data & M88E1000_PSSR_DPLX) 3928 ctrl |= E1000_CTRL_FD; 3929 else 3930 ctrl &= ~E1000_CTRL_FD; 3931 3932 em_config_collision_dist(hw); 3933 /* 3934 * Set up speed in the Device Control register depending on 3935 * negotiated values. 3936 */ 3937 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) 3938 ctrl |= E1000_CTRL_SPD_1000; 3939 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) 3940 ctrl |= E1000_CTRL_SPD_100; 3941 3942 /* Write the configured values back to the Device Control Reg. */ 3943 E1000_WRITE_REG(hw, CTRL, ctrl); 3944 return E1000_SUCCESS; 3945 } 3946 3947 /****************************************************************************** 3948 * Forces the MAC's flow control settings. 3949 * 3950 * hw - Struct containing variables accessed by shared code 3951 * 3952 * Sets the TFCE and RFCE bits in the device control register to reflect 3953 * the adapter settings. TFCE and RFCE need to be explicitly set by 3954 * software when a Copper PHY is used because autonegotiation is managed 3955 * by the PHY rather than the MAC. Software must also configure these 3956 * bits when link is forced on a fiber connection. 3957 *****************************************************************************/ 3958 int32_t 3959 em_force_mac_fc(struct em_hw *hw) 3960 { 3961 uint32_t ctrl; 3962 DEBUGFUNC("em_force_mac_fc"); 3963 3964 /* Get the current configuration of the Device Control Register */ 3965 ctrl = E1000_READ_REG(hw, CTRL); 3966 /* 3967 * Because we didn't get link via the internal auto-negotiation 3968 * mechanism (we either forced link or we got link via PHY auto-neg), 3969 * we have to manually enable/disable transmit an receive flow 3970 * control. 3971 * 3972 * The "Case" statement below enables/disable flow control according to 3973 * the "hw->fc" parameter. 3974 * 3975 * The possible values of the "fc" parameter are: 0: Flow control is 3976 * completely disabled 1: Rx flow control is enabled (we can receive 3977 * pause frames but not send pause frames). 2: Tx flow control is 3978 * enabled (we can send pause frames frames but we do not receive 3979 * pause frames). 3: Both Rx and TX flow control (symmetric) is 3980 * enabled. other: No other values should be possible at this point. 3981 */ 3982 3983 switch (hw->fc) { 3984 case E1000_FC_NONE: 3985 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 3986 break; 3987 case E1000_FC_RX_PAUSE: 3988 ctrl &= (~E1000_CTRL_TFCE); 3989 ctrl |= E1000_CTRL_RFCE; 3990 break; 3991 case E1000_FC_TX_PAUSE: 3992 ctrl &= (~E1000_CTRL_RFCE); 3993 ctrl |= E1000_CTRL_TFCE; 3994 break; 3995 case E1000_FC_FULL: 3996 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 3997 break; 3998 default: 3999 DEBUGOUT("Flow control param set incorrectly\n"); 4000 return -E1000_ERR_CONFIG; 4001 } 4002 4003 /* Disable TX Flow Control for 82542 (rev 2.0) */ 4004 if (hw->mac_type == em_82542_rev2_0) 4005 ctrl &= (~E1000_CTRL_TFCE); 4006 4007 E1000_WRITE_REG(hw, CTRL, ctrl); 4008 return E1000_SUCCESS; 4009 } 4010 /****************************************************************************** 4011 * Configures flow control settings after link is established 4012 * 4013 * hw - Struct containing variables accessed by shared code 4014 * 4015 * Should be called immediately after a valid link has been established. 4016 * Forces MAC flow control settings if link was forced. When in MII/GMII mode 4017 * and autonegotiation is enabled, the MAC flow control settings will be set 4018 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE 4019 * and RFCE bits will be automatically set to the negotiated flow control mode. 4020 *****************************************************************************/ 4021 STATIC int32_t 4022 em_config_fc_after_link_up(struct em_hw *hw) 4023 { 4024 int32_t ret_val; 4025 uint16_t mii_status_reg; 4026 uint16_t mii_nway_adv_reg; 4027 uint16_t mii_nway_lp_ability_reg; 4028 uint16_t speed; 4029 uint16_t duplex; 4030 DEBUGFUNC("em_config_fc_after_link_up"); 4031 /* 4032 * Check for the case where we have fiber media and auto-neg failed 4033 * so we had to force link. In this case, we need to force the 4034 * configuration of the MAC to match the "fc" parameter. 4035 */ 4036 if (((hw->media_type == em_media_type_fiber) && (hw->autoneg_failed)) 4037 || ((hw->media_type == em_media_type_internal_serdes) && 4038 (hw->autoneg_failed)) || 4039 ((hw->media_type == em_media_type_copper) && (!hw->autoneg)) || 4040 ((hw->media_type == em_media_type_oem) && (!hw->autoneg))) { 4041 ret_val = em_force_mac_fc(hw); 4042 if (ret_val) { 4043 DEBUGOUT("Error forcing flow control settings\n"); 4044 return ret_val; 4045 } 4046 } 4047 /* 4048 * Check for the case where we have copper media and auto-neg is 4049 * enabled. In this case, we need to check and see if Auto-Neg has 4050 * completed, and if so, how the PHY and link partner has flow 4051 * control configured. 4052 */ 4053 if ((hw->media_type == em_media_type_copper || 4054 (hw->media_type == em_media_type_oem)) && 4055 hw->autoneg) { 4056 /* 4057 * Read the MII Status Register and check to see if AutoNeg 4058 * has completed. We read this twice because this reg has 4059 * some "sticky" (latched) bits. 4060 */ 4061 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 4062 if (ret_val) 4063 return ret_val; 4064 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 4065 if (ret_val) 4066 return ret_val; 4067 4068 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) { 4069 /* 4070 * The AutoNeg process has completed, so we now need 4071 * to read both the Auto Negotiation Advertisement 4072 * Register (Address 4) and the Auto_Negotiation Base 4073 * Page Ability Register (Address 5) to determine how 4074 * flow control was negotiated. 4075 */ 4076 ret_val = em_read_phy_reg(hw, PHY_AUTONEG_ADV, 4077 &mii_nway_adv_reg); 4078 if (ret_val) 4079 return ret_val; 4080 ret_val = em_read_phy_reg(hw, PHY_LP_ABILITY, 4081 &mii_nway_lp_ability_reg); 4082 if (ret_val) 4083 return ret_val; 4084 /* 4085 * Two bits in the Auto Negotiation Advertisement 4086 * Register (Address 4) and two bits in the Auto 4087 * Negotiation Base Page Ability Register (Address 5) 4088 * determine flow control for both the PHY and the 4089 * link partner. The following table, taken out of 4090 * the IEEE 802.3ab/D6.0 dated March 25, 1999, 4091 * describes these PAUSE resolution bits and how flow 4092 * control is determined based upon these settings. 4093 * NOTE: DC = Don't Care 4094 * 4095 * LOCAL DEVICE | LINK PARTNER | 4096 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 4097 * -------|---------|-------|---------|--------------- 4098 * 0 | 0 | DC | DC | em_fc_none 4099 * 0 | 1 | 0 | DC | em_fc_none 4100 * 0 | 1 | 1 | 0 | em_fc_none 4101 * 0 | 1 | 1 | 1 | em_fc_tx_pause 4102 * 1 | 0 | 0 | DC | em_fc_none 4103 * 1 | DC | 1 | DC | em_fc_full 4104 * 1 | 1 | 0 | 0 | em_fc_none 4105 * 1 | 1 | 0 | 1 | em_fc_rx_pause 4106 * 4107 */ 4108 /* 4109 * Are both PAUSE bits set to 1? If so, this implies 4110 * Symmetric Flow Control is enabled at both ends. 4111 * The ASM_DIR bits are irrelevant per the spec. 4112 * 4113 * For Symmetric Flow Control: 4114 * 4115 * LOCAL DEVICE | LINK PARTNER 4116 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 4117 * -------|---------|-------|---------|--------------- 4118 * 1 | DC | 1 | DC | em_fc_full 4119 * 4120 */ 4121 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 4122 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 4123 /* 4124 * Now we need to check if the user selected 4125 * RX ONLY of pause frames. In this case, we 4126 * had to advertise FULL flow control because 4127 * we could not advertise RX ONLY. Hence, we 4128 * must now check to see if we need to turn 4129 * OFF the TRANSMISSION of PAUSE frames. 4130 */ 4131 if (hw->original_fc == E1000_FC_FULL) { 4132 hw->fc = E1000_FC_FULL; 4133 DEBUGOUT("Flow Control = FULL.\n"); 4134 } else { 4135 hw->fc = E1000_FC_RX_PAUSE; 4136 DEBUGOUT("Flow Control = RX PAUSE" 4137 " frames only.\n"); 4138 } 4139 } 4140 /* 4141 * For receiving PAUSE frames ONLY. 4142 * 4143 * LOCAL DEVICE | LINK PARTNER PAUSE | ASM_DIR | 4144 * PAUSE | ASM_DIR | Result 4145 * -------|---------|-------|---------|--------------- 4146 * ----- 0 | 1 | 1 | 1 | 4147 * em_fc_tx_pause 4148 * 4149 */ 4150 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 4151 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 4152 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 4153 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 4154 hw->fc = E1000_FC_TX_PAUSE; 4155 DEBUGOUT("Flow Control = TX PAUSE frames only." 4156 "\n"); 4157 } 4158 /* 4159 * For transmitting PAUSE frames ONLY. 4160 * 4161 * LOCAL DEVICE | LINK PARTNER 4162 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 4163 * -------|---------|-------|---------|--------------- 4164 * 1 | 1 | 0 | 1 | em_fc_rx_pause 4165 * 4166 */ 4167 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 4168 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 4169 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 4170 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 4171 hw->fc = E1000_FC_RX_PAUSE; 4172 DEBUGOUT("Flow Control = RX PAUSE frames only." 4173 "\n"); 4174 } 4175 /* 4176 * Per the IEEE spec, at this point flow control 4177 * should be disabled. However, we want to consider 4178 * that we could be connected to a legacy switch that 4179 * doesn't advertise desired flow control, but can be 4180 * forced on the link partner. So if we advertised 4181 * no flow control, that is what we will resolve to. 4182 * If we advertised some kind of receive capability 4183 * (Rx Pause Only or Full Flow Control) and the link 4184 * partner advertised none, we will configure 4185 * ourselves to enable Rx Flow Control only. We can 4186 * do this safely for two reasons: If the link 4187 * partner really didn't want flow control enabled, 4188 * and we enable Rx, no harm done since we won't be 4189 * receiving any PAUSE frames anyway. If the intent 4190 * on the link partner was to have flow control 4191 * enabled, then by us enabling RX only, we can at 4192 * least receive pause frames and process them. This 4193 * is a good idea because in most cases, since we are 4194 * predominantly a server NIC, more times than not we 4195 * will be asked to delay transmission of packets 4196 * than asking our link partner to pause transmission 4197 * of frames. 4198 */ 4199 else if ((hw->original_fc == E1000_FC_NONE || 4200 hw->original_fc == E1000_FC_TX_PAUSE) || 4201 hw->fc_strict_ieee) { 4202 hw->fc = E1000_FC_NONE; 4203 DEBUGOUT("Flow Control = NONE.\n"); 4204 } else { 4205 hw->fc = E1000_FC_RX_PAUSE; 4206 DEBUGOUT("Flow Control = RX PAUSE frames only." 4207 "\n"); 4208 } 4209 /* 4210 * Now we need to do one last check... If we auto- 4211 * negotiated to HALF DUPLEX, flow control should not 4212 * be enabled per IEEE 802.3 spec. 4213 */ 4214 ret_val = em_get_speed_and_duplex(hw, &speed, &duplex); 4215 if (ret_val) { 4216 DEBUGOUT("Error getting link speed and duplex" 4217 "\n"); 4218 return ret_val; 4219 } 4220 if (duplex == HALF_DUPLEX) 4221 hw->fc = E1000_FC_NONE; 4222 /* 4223 * Now we call a subroutine to actually force the MAC 4224 * controller to use the correct flow control 4225 * settings. 4226 */ 4227 ret_val = em_force_mac_fc(hw); 4228 if (ret_val) { 4229 DEBUGOUT("Error forcing flow control settings" 4230 "\n"); 4231 return ret_val; 4232 } 4233 } else { 4234 DEBUGOUT("Copper PHY and Auto Neg has not completed." 4235 "\n"); 4236 } 4237 } 4238 return E1000_SUCCESS; 4239 } 4240 /****************************************************************************** 4241 * Checks to see if the link status of the hardware has changed. 4242 * 4243 * hw - Struct containing variables accessed by shared code 4244 * 4245 * Called by any function that needs to check the link status of the adapter. 4246 *****************************************************************************/ 4247 int32_t 4248 em_check_for_link(struct em_hw *hw) 4249 { 4250 uint32_t rxcw = 0; 4251 uint32_t ctrl; 4252 uint32_t status; 4253 uint32_t rctl; 4254 uint32_t icr; 4255 uint32_t signal = 0; 4256 int32_t ret_val; 4257 uint16_t phy_data; 4258 DEBUGFUNC("em_check_for_link"); 4259 uint16_t speed, duplex; 4260 4261 if (hw->mac_type >= em_82575 && 4262 hw->media_type != em_media_type_copper) { 4263 ret_val = em_get_pcs_speed_and_duplex_82575(hw, &speed, 4264 &duplex); 4265 hw->get_link_status = hw->serdes_link_down; 4266 4267 return (ret_val); 4268 } 4269 4270 ctrl = E1000_READ_REG(hw, CTRL); 4271 status = E1000_READ_REG(hw, STATUS); 4272 /* 4273 * On adapters with a MAC newer than 82544, SW Defineable pin 1 will 4274 * be set when the optics detect a signal. On older adapters, it will 4275 * be cleared when there is a signal. This applies to fiber media 4276 * only. 4277 */ 4278 if ((hw->media_type == em_media_type_fiber) || 4279 (hw->media_type == em_media_type_internal_serdes)) { 4280 rxcw = E1000_READ_REG(hw, RXCW); 4281 4282 if (hw->media_type == em_media_type_fiber) { 4283 signal = (hw->mac_type > em_82544) ? 4284 E1000_CTRL_SWDPIN1 : 0; 4285 if (status & E1000_STATUS_LU) 4286 hw->get_link_status = FALSE; 4287 } 4288 } 4289 /* 4290 * If we have a copper PHY then we only want to go out to the PHY 4291 * registers to see if Auto-Neg has completed and/or if our link 4292 * status has changed. The get_link_status flag will be set if we 4293 * receive a Link Status Change interrupt or we have Rx Sequence 4294 * Errors. 4295 */ 4296 if ((hw->media_type == em_media_type_copper || 4297 (hw->media_type == em_media_type_oem)) && 4298 hw->get_link_status) { 4299 /* 4300 * First we want to see if the MII Status Register reports 4301 * link. If so, then we want to get the current speed/duplex 4302 * of the PHY. Read the register twice since the link bit is 4303 * sticky. 4304 */ 4305 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 4306 if (ret_val) 4307 return ret_val; 4308 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 4309 if (ret_val) 4310 return ret_val; 4311 4312 hw->icp_xxxx_is_link_up = (phy_data & MII_SR_LINK_STATUS) != 0; 4313 4314 if (hw->mac_type == em_pchlan) { 4315 ret_val = em_k1_gig_workaround_hv(hw, 4316 hw->icp_xxxx_is_link_up); 4317 if (ret_val) 4318 return ret_val; 4319 } 4320 4321 if (phy_data & MII_SR_LINK_STATUS) { 4322 hw->get_link_status = FALSE; 4323 4324 if (hw->phy_type == em_phy_82578) { 4325 ret_val = em_link_stall_workaround_hv(hw); 4326 if (ret_val) 4327 return ret_val; 4328 } 4329 4330 if (hw->mac_type == em_pch2lan) { 4331 ret_val = em_k1_workaround_lv(hw); 4332 if (ret_val) 4333 return ret_val; 4334 } 4335 /* Work-around I218 hang issue */ 4336 if ((hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) || 4337 (hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) || 4338 (hw->device_id == E1000_DEV_ID_PCH_I218_LM3) || 4339 (hw->device_id == E1000_DEV_ID_PCH_I218_V3)) { 4340 ret_val = em_k1_workaround_lpt_lp(hw, 4341 hw->icp_xxxx_is_link_up); 4342 if (ret_val) 4343 return ret_val; 4344 } 4345 4346 /* 4347 * Check if there was DownShift, must be checked 4348 * immediately after link-up 4349 */ 4350 em_check_downshift(hw); 4351 4352 /* Enable/Disable EEE after link up */ 4353 if (hw->mac_type == em_pch2lan || 4354 hw->mac_type == em_pch_lpt || 4355 hw->mac_type == em_pch_spt || 4356 hw->mac_type == em_pch_cnp || 4357 hw->mac_type == em_pch_tgp || 4358 hw->mac_type == em_pch_adp) { 4359 ret_val = em_set_eee_pchlan(hw); 4360 if (ret_val) 4361 return ret_val; 4362 } 4363 4364 /* 4365 * If we are on 82544 or 82543 silicon and 4366 * speed/duplex are forced to 10H or 10F, then we 4367 * will implement the polarity reversal workaround. 4368 * We disable interrupts first, and upon returning, 4369 * place the devices interrupt state to its previous 4370 * value except for the link status change interrupt 4371 * which will happen due to the execution of this 4372 * workaround. 4373 */ 4374 if ((hw->mac_type == em_82544 || 4375 hw->mac_type == em_82543) && (!hw->autoneg) && 4376 (hw->forced_speed_duplex == em_10_full || 4377 hw->forced_speed_duplex == em_10_half)) { 4378 E1000_WRITE_REG(hw, IMC, 0xffffffff); 4379 ret_val = em_polarity_reversal_workaround(hw); 4380 icr = E1000_READ_REG(hw, ICR); 4381 E1000_WRITE_REG(hw, ICS, 4382 (icr & ~E1000_ICS_LSC)); 4383 E1000_WRITE_REG(hw, IMS, IMS_ENABLE_MASK); 4384 } 4385 } else { 4386 /* No link detected */ 4387 em_config_dsp_after_link_change(hw, FALSE); 4388 return 0; 4389 } 4390 /* 4391 * If we are forcing speed/duplex, then we simply return 4392 * since we have already determined whether we have link or 4393 * not. 4394 */ 4395 if (!hw->autoneg) 4396 return -E1000_ERR_CONFIG; 4397 4398 /* optimize the dsp settings for the igp phy */ 4399 em_config_dsp_after_link_change(hw, TRUE); 4400 /* 4401 * We have a M88E1000 PHY and Auto-Neg is enabled. If we 4402 * have Si on board that is 82544 or newer, Auto Speed 4403 * Detection takes care of MAC speed/duplex configuration. 4404 * So we only need to configure Collision Distance in the 4405 * MAC. Otherwise, we need to force speed/duplex on the MAC 4406 * to the current PHY speed/duplex settings. 4407 */ 4408 if (hw->mac_type >= em_82544 && hw->mac_type != em_icp_xxxx) { 4409 em_config_collision_dist(hw); 4410 } else { 4411 ret_val = em_config_mac_to_phy(hw); 4412 if (ret_val) { 4413 DEBUGOUT("Error configuring MAC to PHY" 4414 " settings\n"); 4415 return ret_val; 4416 } 4417 } 4418 /* 4419 * Configure Flow Control now that Auto-Neg has completed. 4420 * First, we need to restore the desired flow control 4421 * settings because we may have had to re-autoneg with a 4422 * different link partner. 4423 */ 4424 ret_val = em_config_fc_after_link_up(hw); 4425 if (ret_val) { 4426 DEBUGOUT("Error configuring flow control\n"); 4427 return ret_val; 4428 } 4429 /* 4430 * At this point we know that we are on copper and we have 4431 * auto-negotiated link. These are conditions for checking 4432 * the link partner capability register. We use the link 4433 * speed to determine if TBI compatibility needs to be turned 4434 * on or off. If the link is not at gigabit speed, then TBI 4435 * compatibility is not needed. If we are at gigabit speed, 4436 * we turn on TBI compatibility. 4437 */ 4438 if (hw->tbi_compatibility_en) { 4439 uint16_t speed, duplex; 4440 ret_val = em_get_speed_and_duplex(hw, &speed, &duplex); 4441 if (ret_val) { 4442 DEBUGOUT("Error getting link speed and duplex" 4443 "\n"); 4444 return ret_val; 4445 } 4446 if (speed != SPEED_1000) { 4447 /* 4448 * If link speed is not set to gigabit speed, 4449 * we do not need to enable TBI 4450 * compatibility. 4451 */ 4452 if (hw->tbi_compatibility_on) { 4453 /* 4454 * If we previously were in the mode, 4455 * turn it off. 4456 */ 4457 rctl = E1000_READ_REG(hw, RCTL); 4458 rctl &= ~E1000_RCTL_SBP; 4459 E1000_WRITE_REG(hw, RCTL, rctl); 4460 hw->tbi_compatibility_on = FALSE; 4461 } 4462 } else { 4463 /* 4464 * If TBI compatibility is was previously 4465 * off, turn it on. For compatibility with a 4466 * TBI link partner, we will store bad 4467 * packets. Some frames have an additional 4468 * byte on the end and will look like CRC 4469 * errors to to the hardware. 4470 */ 4471 if (!hw->tbi_compatibility_on) { 4472 hw->tbi_compatibility_on = TRUE; 4473 rctl = E1000_READ_REG(hw, RCTL); 4474 rctl |= E1000_RCTL_SBP; 4475 E1000_WRITE_REG(hw, RCTL, rctl); 4476 } 4477 } 4478 } 4479 } 4480 /* 4481 * If we don't have link (auto-negotiation failed or link partner 4482 * cannot auto-negotiate), the cable is plugged in (we have signal), 4483 * and our link partner is not trying to auto-negotiate with us (we 4484 * are receiving idles or data), we need to force link up. We also 4485 * need to give auto-negotiation time to complete, in case the cable 4486 * was just plugged in. The autoneg_failed flag does this. 4487 */ 4488 else if ((((hw->media_type == em_media_type_fiber) && 4489 ((ctrl & E1000_CTRL_SWDPIN1) == signal)) || 4490 (hw->media_type == em_media_type_internal_serdes)) && 4491 (!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) { 4492 if (hw->autoneg_failed == 0) { 4493 hw->autoneg_failed = 1; 4494 return 0; 4495 } 4496 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 4497 4498 /* Disable auto-negotiation in the TXCW register */ 4499 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE)); 4500 4501 /* Force link-up and also force full-duplex. */ 4502 ctrl = E1000_READ_REG(hw, CTRL); 4503 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 4504 E1000_WRITE_REG(hw, CTRL, ctrl); 4505 4506 /* Configure Flow Control after forcing link up. */ 4507 ret_val = em_config_fc_after_link_up(hw); 4508 if (ret_val) { 4509 DEBUGOUT("Error configuring flow control\n"); 4510 return ret_val; 4511 } 4512 } 4513 /* 4514 * If we are forcing link and we are receiving /C/ ordered sets, 4515 * re-enable auto-negotiation in the TXCW register and disable forced 4516 * link in the Device Control register in an attempt to 4517 * auto-negotiate with our link partner. 4518 */ 4519 else if (((hw->media_type == em_media_type_fiber) || 4520 (hw->media_type == em_media_type_internal_serdes)) && 4521 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 4522 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 4523 E1000_WRITE_REG(hw, TXCW, hw->txcw); 4524 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU)); 4525 4526 hw->serdes_link_down = FALSE; 4527 } 4528 /* 4529 * If we force link for non-auto-negotiation switch, check link 4530 * status based on MAC synchronization for internal serdes media 4531 * type. 4532 */ 4533 else if ((hw->media_type == em_media_type_internal_serdes) && 4534 !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) { 4535 /* SYNCH bit and IV bit are sticky. */ 4536 usec_delay(10); 4537 if (E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) { 4538 if (!(rxcw & E1000_RXCW_IV)) { 4539 hw->serdes_link_down = FALSE; 4540 DEBUGOUT("SERDES: Link is up.\n"); 4541 } 4542 } else { 4543 hw->serdes_link_down = TRUE; 4544 DEBUGOUT("SERDES: Link is down.\n"); 4545 } 4546 } 4547 if ((hw->media_type == em_media_type_internal_serdes) && 4548 (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) { 4549 hw->serdes_link_down = !(E1000_STATUS_LU & 4550 E1000_READ_REG(hw, STATUS)); 4551 } 4552 return E1000_SUCCESS; 4553 } 4554 4555 int32_t 4556 em_get_pcs_speed_and_duplex_82575(struct em_hw *hw, uint16_t *speed, 4557 uint16_t *duplex) 4558 { 4559 uint32_t pcs; 4560 4561 hw->serdes_link_down = TRUE; 4562 *speed = 0; 4563 *duplex = 0; 4564 4565 /* 4566 * Read the PCS Status register for link state. For non-copper mode, 4567 * the status register is not accurate. The PCS status register is 4568 * used instead. 4569 */ 4570 pcs = E1000_READ_REG(hw, PCS_LSTAT); 4571 4572 /* 4573 * The link up bit determines when link is up on autoneg. The sync ok 4574 * gets set once both sides sync up and agree upon link. Stable link 4575 * can be determined by checking for both link up and link sync ok 4576 */ 4577 if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) { 4578 hw->serdes_link_down = FALSE; 4579 4580 /* Detect and store PCS speed */ 4581 if (pcs & E1000_PCS_LSTS_SPEED_1000) { 4582 *speed = SPEED_1000; 4583 } else if (pcs & E1000_PCS_LSTS_SPEED_100) { 4584 *speed = SPEED_100; 4585 } else { 4586 *speed = SPEED_10; 4587 } 4588 4589 /* Detect and store PCS duplex */ 4590 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) { 4591 *duplex = FULL_DUPLEX; 4592 } else { 4593 *duplex = HALF_DUPLEX; 4594 } 4595 } 4596 4597 return (0); 4598 } 4599 4600 4601 /****************************************************************************** 4602 * Detects the current speed and duplex settings of the hardware. 4603 * 4604 * hw - Struct containing variables accessed by shared code 4605 * speed - Speed of the connection 4606 * duplex - Duplex setting of the connection 4607 *****************************************************************************/ 4608 int32_t 4609 em_get_speed_and_duplex(struct em_hw *hw, uint16_t *speed, uint16_t *duplex) 4610 { 4611 uint32_t status; 4612 int32_t ret_val; 4613 uint16_t phy_data; 4614 DEBUGFUNC("em_get_speed_and_duplex"); 4615 4616 if (hw->mac_type >= em_82575 && hw->media_type != em_media_type_copper) 4617 return em_get_pcs_speed_and_duplex_82575(hw, speed, duplex); 4618 4619 if (hw->mac_type >= em_82543) { 4620 status = E1000_READ_REG(hw, STATUS); 4621 if (status & E1000_STATUS_SPEED_1000) { 4622 *speed = SPEED_1000; 4623 DEBUGOUT("1000 Mbs, "); 4624 } else if (status & E1000_STATUS_SPEED_100) { 4625 *speed = SPEED_100; 4626 DEBUGOUT("100 Mbs, "); 4627 } else { 4628 *speed = SPEED_10; 4629 DEBUGOUT("10 Mbs, "); 4630 } 4631 4632 if (status & E1000_STATUS_FD) { 4633 *duplex = FULL_DUPLEX; 4634 DEBUGOUT("Full Duplex\n"); 4635 } else { 4636 *duplex = HALF_DUPLEX; 4637 DEBUGOUT(" Half Duplex\n"); 4638 } 4639 } else { 4640 DEBUGOUT("1000 Mbs, Full Duplex\n"); 4641 *speed = SPEED_1000; 4642 *duplex = FULL_DUPLEX; 4643 } 4644 /* 4645 * IGP01 PHY may advertise full duplex operation after speed 4646 * downgrade even if it is operating at half duplex. Here we set the 4647 * duplex settings to match the duplex in the link partner's 4648 * capabilities. 4649 */ 4650 if (hw->phy_type == em_phy_igp && hw->speed_downgraded) { 4651 ret_val = em_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data); 4652 if (ret_val) 4653 return ret_val; 4654 4655 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS)) 4656 *duplex = HALF_DUPLEX; 4657 else { 4658 ret_val = em_read_phy_reg(hw, PHY_LP_ABILITY, 4659 &phy_data); 4660 if (ret_val) 4661 return ret_val; 4662 if ((*speed == SPEED_100 && 4663 !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) || 4664 (*speed == SPEED_10 && 4665 !(phy_data & NWAY_LPAR_10T_FD_CAPS))) 4666 *duplex = HALF_DUPLEX; 4667 } 4668 } 4669 if ((hw->mac_type == em_80003es2lan) && 4670 (hw->media_type == em_media_type_copper)) { 4671 if (*speed == SPEED_1000) 4672 ret_val = em_configure_kmrn_for_1000(hw); 4673 else 4674 ret_val = em_configure_kmrn_for_10_100(hw, *duplex); 4675 if (ret_val) 4676 return ret_val; 4677 } 4678 if ((hw->mac_type == em_ich8lan) && 4679 (hw->phy_type == em_phy_igp_3) && 4680 (*speed == SPEED_1000)) { 4681 ret_val = em_kumeran_lock_loss_workaround(hw); 4682 if (ret_val) 4683 return ret_val; 4684 } 4685 return E1000_SUCCESS; 4686 } 4687 4688 /****************************************************************************** 4689 * Blocks until autoneg completes or times out (~4.5 seconds) 4690 * 4691 * hw - Struct containing variables accessed by shared code 4692 *****************************************************************************/ 4693 STATIC int32_t 4694 em_wait_autoneg(struct em_hw *hw) 4695 { 4696 int32_t ret_val; 4697 uint16_t i; 4698 uint16_t phy_data; 4699 DEBUGFUNC("em_wait_autoneg"); 4700 DEBUGOUT("Waiting for Auto-Neg to complete.\n"); 4701 4702 /* We will wait for autoneg to complete or 4.5 seconds to expire. */ 4703 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) { 4704 /* 4705 * Read the MII Status Register and wait for Auto-Neg 4706 * Complete bit to be set. 4707 */ 4708 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 4709 if (ret_val) 4710 return ret_val; 4711 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 4712 if (ret_val) 4713 return ret_val; 4714 if (phy_data & MII_SR_AUTONEG_COMPLETE) { 4715 return E1000_SUCCESS; 4716 } 4717 msec_delay(100); 4718 } 4719 return E1000_SUCCESS; 4720 } 4721 4722 /****************************************************************************** 4723 * Raises the Management Data Clock 4724 * 4725 * hw - Struct containing variables accessed by shared code 4726 * ctrl - Device control register's current value 4727 *****************************************************************************/ 4728 static void 4729 em_raise_mdi_clk(struct em_hw *hw, uint32_t *ctrl) 4730 { 4731 /* 4732 * Raise the clock input to the Management Data Clock (by setting the 4733 * MDC bit), and then delay 10 microseconds. 4734 */ 4735 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC)); 4736 E1000_WRITE_FLUSH(hw); 4737 usec_delay(10); 4738 } 4739 4740 /****************************************************************************** 4741 * Lowers the Management Data Clock 4742 * 4743 * hw - Struct containing variables accessed by shared code 4744 * ctrl - Device control register's current value 4745 *****************************************************************************/ 4746 static void 4747 em_lower_mdi_clk(struct em_hw *hw, uint32_t *ctrl) 4748 { 4749 /* 4750 * Lower the clock input to the Management Data Clock (by clearing 4751 * the MDC bit), and then delay 10 microseconds. 4752 */ 4753 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC)); 4754 E1000_WRITE_FLUSH(hw); 4755 usec_delay(10); 4756 } 4757 4758 /****************************************************************************** 4759 * Shifts data bits out to the PHY 4760 * 4761 * hw - Struct containing variables accessed by shared code 4762 * data - Data to send out to the PHY 4763 * count - Number of bits to shift out 4764 * 4765 * Bits are shifted out in MSB to LSB order. 4766 *****************************************************************************/ 4767 static void 4768 em_shift_out_mdi_bits(struct em_hw *hw, uint32_t data, uint16_t count) 4769 { 4770 uint32_t ctrl; 4771 uint32_t mask; 4772 /* 4773 * We need to shift "count" number of bits out to the PHY. So, the 4774 * value in the "data" parameter will be shifted out to the PHY one 4775 * bit at a time. In order to do this, "data" must be broken down 4776 * into bits. 4777 */ 4778 mask = 0x01; 4779 mask <<= (count - 1); 4780 4781 ctrl = E1000_READ_REG(hw, CTRL); 4782 4783 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output 4784 * pins. 4785 */ 4786 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); 4787 4788 while (mask) { 4789 /* 4790 * A "1" is shifted out to the PHY by setting the MDIO bit to 4791 * "1" and then raising and lowering the Management Data 4792 * Clock. A "0" is shifted out to the PHY by setting the MDIO 4793 * bit to "0" and then raising and lowering the clock. 4794 */ 4795 if (data & mask) 4796 ctrl |= E1000_CTRL_MDIO; 4797 else 4798 ctrl &= ~E1000_CTRL_MDIO; 4799 4800 E1000_WRITE_REG(hw, CTRL, ctrl); 4801 E1000_WRITE_FLUSH(hw); 4802 4803 usec_delay(10); 4804 4805 em_raise_mdi_clk(hw, &ctrl); 4806 em_lower_mdi_clk(hw, &ctrl); 4807 4808 mask = mask >> 1; 4809 } 4810 } 4811 4812 /****************************************************************************** 4813 * Shifts data bits in from the PHY 4814 * 4815 * hw - Struct containing variables accessed by shared code 4816 * 4817 * Bits are shifted in in MSB to LSB order. 4818 *****************************************************************************/ 4819 static uint16_t 4820 em_shift_in_mdi_bits(struct em_hw *hw) 4821 { 4822 uint32_t ctrl; 4823 uint16_t data = 0; 4824 uint8_t i; 4825 /* 4826 * In order to read a register from the PHY, we need to shift in a 4827 * total of 18 bits from the PHY. The first two bit (turnaround) 4828 * times are used to avoid contention on the MDIO pin when a read 4829 * operation is performed. These two bits are ignored by us and 4830 * thrown away. Bits are "shifted in" by raising the input to the 4831 * Management Data Clock (setting the MDC bit), and then reading the 4832 * value of the MDIO bit. 4833 */ 4834 ctrl = E1000_READ_REG(hw, CTRL); 4835 /* 4836 * Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as 4837 * input. 4838 */ 4839 ctrl &= ~E1000_CTRL_MDIO_DIR; 4840 ctrl &= ~E1000_CTRL_MDIO; 4841 4842 E1000_WRITE_REG(hw, CTRL, ctrl); 4843 E1000_WRITE_FLUSH(hw); 4844 /* 4845 * Raise and Lower the clock before reading in the data. This 4846 * accounts for the turnaround bits. The first clock occurred when we 4847 * clocked out the last bit of the Register Address. 4848 */ 4849 em_raise_mdi_clk(hw, &ctrl); 4850 em_lower_mdi_clk(hw, &ctrl); 4851 4852 for (data = 0, i = 0; i < 16; i++) { 4853 data = data << 1; 4854 em_raise_mdi_clk(hw, &ctrl); 4855 ctrl = E1000_READ_REG(hw, CTRL); 4856 /* Check to see if we shifted in a "1". */ 4857 if (ctrl & E1000_CTRL_MDIO) 4858 data |= 1; 4859 em_lower_mdi_clk(hw, &ctrl); 4860 } 4861 4862 em_raise_mdi_clk(hw, &ctrl); 4863 em_lower_mdi_clk(hw, &ctrl); 4864 4865 return data; 4866 } 4867 4868 STATIC int32_t 4869 em_swfw_sync_acquire(struct em_hw *hw, uint16_t mask) 4870 { 4871 uint32_t swfw_sync = 0; 4872 uint32_t swmask = mask; 4873 uint32_t fwmask = mask << 16; 4874 int32_t timeout = 200; 4875 DEBUGFUNC("em_swfw_sync_acquire"); 4876 4877 if (hw->swfwhw_semaphore_present) 4878 return em_get_software_flag(hw); 4879 4880 if (!hw->swfw_sync_present) 4881 return em_get_hw_eeprom_semaphore(hw); 4882 4883 while (timeout) { 4884 if (em_get_hw_eeprom_semaphore(hw)) 4885 return -E1000_ERR_SWFW_SYNC; 4886 4887 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); 4888 if (!(swfw_sync & (fwmask | swmask))) { 4889 break; 4890 } 4891 /* 4892 * firmware currently using resource (fwmask) 4893 * or other software thread currently using resource (swmask) 4894 */ 4895 em_put_hw_eeprom_semaphore(hw); 4896 msec_delay_irq(5); 4897 timeout--; 4898 } 4899 4900 if (!timeout) { 4901 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout." 4902 "\n"); 4903 return -E1000_ERR_SWFW_SYNC; 4904 } 4905 swfw_sync |= swmask; 4906 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync); 4907 4908 em_put_hw_eeprom_semaphore(hw); 4909 return E1000_SUCCESS; 4910 } 4911 4912 STATIC void 4913 em_swfw_sync_release(struct em_hw *hw, uint16_t mask) 4914 { 4915 uint32_t swfw_sync; 4916 uint32_t swmask = mask; 4917 DEBUGFUNC("em_swfw_sync_release"); 4918 4919 if (hw->swfwhw_semaphore_present) { 4920 em_release_software_flag(hw); 4921 return; 4922 } 4923 if (!hw->swfw_sync_present) { 4924 em_put_hw_eeprom_semaphore(hw); 4925 return; 4926 } 4927 /* 4928 * if (em_get_hw_eeprom_semaphore(hw)) return -E1000_ERR_SWFW_SYNC; 4929 */ 4930 while (em_get_hw_eeprom_semaphore(hw) != E1000_SUCCESS); 4931 /* empty */ 4932 4933 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); 4934 swfw_sync &= ~swmask; 4935 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync); 4936 4937 em_put_hw_eeprom_semaphore(hw); 4938 } 4939 4940 /**************************************************************************** 4941 * Read BM PHY wakeup register. It works as such: 4942 * 1) Set page 769, register 17, bit 2 = 1 4943 * 2) Set page to 800 for host (801 if we were manageability) 4944 * 3) Write the address using the address opcode (0x11) 4945 * 4) Read or write the data using the data opcode (0x12) 4946 * 5) Restore 769_17.2 to its original value 4947 ****************************************************************************/ 4948 int32_t 4949 em_access_phy_wakeup_reg_bm(struct em_hw *hw, uint32_t reg_addr, 4950 uint16_t *phy_data, boolean_t read) 4951 { 4952 int32_t ret_val; 4953 uint16_t reg = BM_PHY_REG_NUM(reg_addr); 4954 uint16_t phy_reg = 0; 4955 4956 /* All operations in this function are phy address 1 */ 4957 hw->phy_addr = 1; 4958 4959 /* Set page 769 */ 4960 em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 4961 (BM_WUC_ENABLE_PAGE << PHY_PAGE_SHIFT)); 4962 4963 ret_val = em_read_phy_reg_ex(hw, BM_WUC_ENABLE_REG, &phy_reg); 4964 if (ret_val) 4965 goto out; 4966 4967 /* First clear bit 4 to avoid a power state change */ 4968 phy_reg &= ~(BM_WUC_HOST_WU_BIT); 4969 ret_val = em_write_phy_reg_ex(hw, BM_WUC_ENABLE_REG, phy_reg); 4970 if (ret_val) 4971 goto out; 4972 4973 /* Write bit 2 = 1, and clear bit 4 to 769_17 */ 4974 ret_val = em_write_phy_reg_ex(hw, BM_WUC_ENABLE_REG, 4975 phy_reg | BM_WUC_ENABLE_BIT); 4976 if (ret_val) 4977 goto out; 4978 4979 /* Select page 800 */ 4980 ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 4981 (BM_WUC_PAGE << PHY_PAGE_SHIFT)); 4982 4983 /* Write the page 800 offset value using opcode 0x11 */ 4984 ret_val = em_write_phy_reg_ex(hw, BM_WUC_ADDRESS_OPCODE, reg); 4985 if (ret_val) 4986 goto out; 4987 4988 if (read) 4989 /* Read the page 800 value using opcode 0x12 */ 4990 ret_val = em_read_phy_reg_ex(hw, BM_WUC_DATA_OPCODE, 4991 phy_data); 4992 else 4993 /* Write the page 800 value using opcode 0x12 */ 4994 ret_val = em_write_phy_reg_ex(hw, BM_WUC_DATA_OPCODE, 4995 *phy_data); 4996 4997 if (ret_val) 4998 goto out; 4999 5000 /* 5001 * Restore 769_17.2 to its original value 5002 * Set page 769 5003 */ 5004 em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 5005 (BM_WUC_ENABLE_PAGE << PHY_PAGE_SHIFT)); 5006 5007 /* Clear 769_17.2 */ 5008 ret_val = em_write_phy_reg_ex(hw, BM_WUC_ENABLE_REG, phy_reg); 5009 if (ret_val) 5010 goto out; 5011 5012 out: 5013 return ret_val; 5014 } 5015 5016 /*************************************************************************** 5017 * Read HV PHY vendor specific high registers 5018 ***************************************************************************/ 5019 int32_t 5020 em_access_phy_debug_regs_hv(struct em_hw *hw, uint32_t reg_addr, 5021 uint16_t *phy_data, boolean_t read) 5022 { 5023 int32_t ret_val; 5024 uint32_t addr_reg = 0; 5025 uint32_t data_reg = 0; 5026 5027 /* This takes care of the difference with desktop vs mobile phy */ 5028 addr_reg = (hw->phy_type == em_phy_82578) ? 5029 I82578_PHY_ADDR_REG : I82577_PHY_ADDR_REG; 5030 data_reg = addr_reg + 1; 5031 5032 /* All operations in this function are phy address 2 */ 5033 hw->phy_addr = 2; 5034 5035 /* masking with 0x3F to remove the page from offset */ 5036 ret_val = em_write_phy_reg_ex(hw, addr_reg, (uint16_t)reg_addr & 0x3F); 5037 if (ret_val) { 5038 printf("Could not write PHY the HV address register\n"); 5039 goto out; 5040 } 5041 5042 /* Read or write the data value next */ 5043 if (read) 5044 ret_val = em_read_phy_reg_ex(hw, data_reg, phy_data); 5045 else 5046 ret_val = em_write_phy_reg_ex(hw, data_reg, *phy_data); 5047 5048 if (ret_val) { 5049 printf("Could not read data value from HV data register\n"); 5050 goto out; 5051 } 5052 5053 out: 5054 return ret_val; 5055 } 5056 5057 /****************************************************************************** 5058 * Reads or writes the value from a PHY register, if the value is on a specific 5059 * non zero page, sets the page first. 5060 * hw - Struct containing variables accessed by shared code 5061 * reg_addr - address of the PHY register to read 5062 *****************************************************************************/ 5063 int32_t 5064 em_access_phy_reg_hv(struct em_hw *hw, uint32_t reg_addr, uint16_t *phy_data, 5065 boolean_t read) 5066 { 5067 uint32_t ret_val; 5068 uint16_t swfw; 5069 uint16_t page = BM_PHY_REG_PAGE(reg_addr); 5070 uint16_t reg = BM_PHY_REG_NUM(reg_addr); 5071 5072 DEBUGFUNC("em_access_phy_reg_hv"); 5073 5074 swfw = E1000_SWFW_PHY0_SM; 5075 5076 if (em_swfw_sync_acquire(hw, swfw)) 5077 return -E1000_ERR_SWFW_SYNC; 5078 5079 if (page == BM_WUC_PAGE) { 5080 ret_val = em_access_phy_wakeup_reg_bm(hw, reg_addr, 5081 phy_data, read); 5082 goto release; 5083 } 5084 5085 if (page >= HV_INTC_FC_PAGE_START) 5086 hw->phy_addr = 1; 5087 else 5088 hw->phy_addr = 2; 5089 5090 if (page == HV_INTC_FC_PAGE_START) 5091 page = 0; 5092 5093 /* 5094 * Workaround MDIO accesses being disabled after entering IEEE Power 5095 * Down (whenever bit 11 of the PHY Control register is set) 5096 */ 5097 if (!read && 5098 (hw->phy_type == em_phy_82578) && 5099 (hw->phy_revision >= 1) && 5100 (hw->phy_addr == 2) && 5101 ((MAX_PHY_REG_ADDRESS & reg) == 0) && 5102 (*phy_data & (1 << 11))) { 5103 uint16_t data2 = 0x7EFF; 5104 5105 ret_val = em_access_phy_debug_regs_hv(hw, (1 << 6) | 0x3, 5106 &data2, FALSE); 5107 if (ret_val) 5108 return ret_val; 5109 } 5110 5111 if (reg_addr > MAX_PHY_MULTI_PAGE_REG) { 5112 ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 5113 (page << PHY_PAGE_SHIFT)); 5114 if (ret_val) 5115 return ret_val; 5116 } 5117 if (read) 5118 ret_val = em_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg, 5119 phy_data); 5120 else 5121 ret_val = em_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg, 5122 *phy_data); 5123 release: 5124 em_swfw_sync_release(hw, swfw); 5125 return ret_val; 5126 } 5127 5128 /****************************************************************************** 5129 * Reads the value from a PHY register, if the value is on a specific non zero 5130 * page, sets the page first. 5131 * hw - Struct containing variables accessed by shared code 5132 * reg_addr - address of the PHY register to read 5133 *****************************************************************************/ 5134 int32_t 5135 em_read_phy_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t *phy_data) 5136 { 5137 uint32_t ret_val; 5138 uint16_t swfw; 5139 DEBUGFUNC("em_read_phy_reg"); 5140 5141 if (hw->mac_type == em_pchlan || 5142 hw->mac_type == em_pch2lan || 5143 hw->mac_type == em_pch_lpt || 5144 hw->mac_type == em_pch_spt || 5145 hw->mac_type == em_pch_cnp || 5146 hw->mac_type == em_pch_tgp || 5147 hw->mac_type == em_pch_adp) 5148 return (em_access_phy_reg_hv(hw, reg_addr, phy_data, TRUE)); 5149 5150 if (((hw->mac_type == em_80003es2lan) || (hw->mac_type == em_82575) || 5151 (hw->mac_type == em_82576)) && 5152 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { 5153 swfw = E1000_SWFW_PHY1_SM; 5154 } else { 5155 swfw = E1000_SWFW_PHY0_SM; 5156 } 5157 if (em_swfw_sync_acquire(hw, swfw)) 5158 return -E1000_ERR_SWFW_SYNC; 5159 5160 if ((hw->phy_type == em_phy_igp || 5161 hw->phy_type == em_phy_igp_3 || 5162 hw->phy_type == em_phy_igp_2) && 5163 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { 5164 ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 5165 (uint16_t) reg_addr); 5166 if (ret_val) { 5167 em_swfw_sync_release(hw, swfw); 5168 return ret_val; 5169 } 5170 } else if (hw->phy_type == em_phy_gg82563) { 5171 if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) || 5172 (hw->mac_type == em_80003es2lan)) { 5173 /* Select Configuration Page */ 5174 if ((reg_addr & MAX_PHY_REG_ADDRESS) < 5175 GG82563_MIN_ALT_REG) { 5176 ret_val = em_write_phy_reg_ex(hw, 5177 GG82563_PHY_PAGE_SELECT, 5178 (uint16_t) ((uint16_t) reg_addr >> 5179 GG82563_PAGE_SHIFT)); 5180 } else { 5181 /* 5182 * Use Alternative Page Select register to 5183 * access registers 30 and 31 5184 */ 5185 ret_val = em_write_phy_reg_ex(hw, 5186 GG82563_PHY_PAGE_SELECT_ALT, 5187 (uint16_t) ((uint16_t) reg_addr >> 5188 GG82563_PAGE_SHIFT)); 5189 } 5190 5191 if (ret_val) { 5192 em_swfw_sync_release(hw, swfw); 5193 return ret_val; 5194 } 5195 } 5196 } else if ((hw->phy_type == em_phy_bm) && (hw->phy_revision == 1)) { 5197 if (reg_addr > MAX_PHY_MULTI_PAGE_REG) { 5198 ret_val = em_write_phy_reg_ex(hw, BM_PHY_PAGE_SELECT, 5199 (uint16_t) ((uint16_t) reg_addr >> 5200 PHY_PAGE_SHIFT)); 5201 if (ret_val) 5202 return ret_val; 5203 } 5204 } 5205 ret_val = em_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, 5206 phy_data); 5207 5208 em_swfw_sync_release(hw, swfw); 5209 return ret_val; 5210 } 5211 5212 STATIC int32_t 5213 em_read_phy_reg_ex(struct em_hw *hw, uint32_t reg_addr, uint16_t *phy_data) 5214 { 5215 uint32_t i; 5216 uint32_t mdic = 0; 5217 DEBUGFUNC("em_read_phy_reg_ex"); 5218 5219 /* SGMII active is only set on some specific chips */ 5220 if (hw->sgmii_active && !em_sgmii_uses_mdio_82575(hw)) { 5221 if (reg_addr > E1000_MAX_SGMII_PHY_REG_ADDR) { 5222 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); 5223 return -E1000_ERR_PARAM; 5224 } 5225 return em_read_phy_reg_i2c(hw, reg_addr, phy_data); 5226 } 5227 if (reg_addr > MAX_PHY_REG_ADDRESS) { 5228 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); 5229 return -E1000_ERR_PARAM; 5230 } 5231 if (hw->mac_type == em_icp_xxxx) { 5232 *phy_data = gcu_miibus_readreg(hw, hw->icp_xxxx_port_num, 5233 reg_addr); 5234 return E1000_SUCCESS; 5235 } 5236 if (hw->mac_type > em_82543) { 5237 /* 5238 * Set up Op-code, Phy Address, and register address in the 5239 * MDI Control register. The MAC will take care of 5240 * interfacing with the PHY to retrieve the desired data. 5241 */ 5242 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) | 5243 (hw->phy_addr << E1000_MDIC_PHY_SHIFT) | 5244 (E1000_MDIC_OP_READ)); 5245 5246 E1000_WRITE_REG(hw, MDIC, mdic); 5247 5248 /* 5249 * Poll the ready bit to see if the MDI read completed 5250 * Increasing the time out as testing showed failures with 5251 * the lower time out (from FreeBSD driver) 5252 */ 5253 for (i = 0; i < 1960; i++) { 5254 usec_delay(50); 5255 mdic = E1000_READ_REG(hw, MDIC); 5256 if (mdic & E1000_MDIC_READY) 5257 break; 5258 } 5259 if (!(mdic & E1000_MDIC_READY)) { 5260 DEBUGOUT("MDI Read did not complete\n"); 5261 return -E1000_ERR_PHY; 5262 } 5263 if (mdic & E1000_MDIC_ERROR) { 5264 DEBUGOUT("MDI Error\n"); 5265 return -E1000_ERR_PHY; 5266 } 5267 *phy_data = (uint16_t) mdic; 5268 5269 if (hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt || 5270 hw->mac_type == em_pch_spt || hw->mac_type == em_pch_cnp || 5271 hw->mac_type == em_pch_tgp || hw->mac_type == em_pch_adp) 5272 usec_delay(100); 5273 } else { 5274 /* 5275 * We must first send a preamble through the MDIO pin to 5276 * signal the beginning of an MII instruction. This is done 5277 * by sending 32 consecutive "1" bits. 5278 */ 5279 em_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 5280 /* 5281 * Now combine the next few fields that are required for a 5282 * read operation. We use this method instead of calling the 5283 * em_shift_out_mdi_bits routine five different times. The 5284 * format of a MII read instruction consists of a shift out 5285 * of 14 bits and is defined as follows: <Preamble><SOF><Op 5286 * Code><Phy Addr><Reg Addr> followed by a shift in of 18 5287 * bits. This first two bits shifted in are TurnAround bits 5288 * used to avoid contention on the MDIO pin when a READ 5289 * operation is performed. These two bits are thrown away 5290 * followed by a shift in of 16 bits which contains the 5291 * desired data. 5292 */ 5293 mdic = ((reg_addr) | (hw->phy_addr << 5) | 5294 (PHY_OP_READ << 10) | (PHY_SOF << 12)); 5295 5296 em_shift_out_mdi_bits(hw, mdic, 14); 5297 /* 5298 * Now that we've shifted out the read command to the MII, we 5299 * need to "shift in" the 16-bit value (18 total bits) of the 5300 * requested PHY register address. 5301 */ 5302 *phy_data = em_shift_in_mdi_bits(hw); 5303 } 5304 return E1000_SUCCESS; 5305 } 5306 5307 /****************************************************************************** 5308 * Writes a value to a PHY register 5309 * 5310 * hw - Struct containing variables accessed by shared code 5311 * reg_addr - address of the PHY register to write 5312 * data - data to write to the PHY 5313 *****************************************************************************/ 5314 int32_t 5315 em_write_phy_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t phy_data) 5316 { 5317 uint32_t ret_val; 5318 DEBUGFUNC("em_write_phy_reg"); 5319 5320 if (hw->mac_type == em_pchlan || 5321 hw->mac_type == em_pch2lan || 5322 hw->mac_type == em_pch_lpt || 5323 hw->mac_type == em_pch_spt || 5324 hw->mac_type == em_pch_cnp || 5325 hw->mac_type == em_pch_tgp || 5326 hw->mac_type == em_pch_adp) 5327 return (em_access_phy_reg_hv(hw, reg_addr, &phy_data, FALSE)); 5328 5329 if (em_swfw_sync_acquire(hw, hw->swfw)) 5330 return -E1000_ERR_SWFW_SYNC; 5331 5332 if ((hw->phy_type == em_phy_igp || 5333 hw->phy_type == em_phy_igp_3 || 5334 hw->phy_type == em_phy_igp_2) && 5335 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { 5336 ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 5337 (uint16_t) reg_addr); 5338 if (ret_val) { 5339 em_swfw_sync_release(hw, hw->swfw); 5340 return ret_val; 5341 } 5342 } else if (hw->phy_type == em_phy_gg82563) { 5343 if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) || 5344 (hw->mac_type == em_80003es2lan)) { 5345 /* Select Configuration Page */ 5346 if ((reg_addr & MAX_PHY_REG_ADDRESS) < 5347 GG82563_MIN_ALT_REG) { 5348 ret_val = em_write_phy_reg_ex(hw, 5349 GG82563_PHY_PAGE_SELECT, 5350 (uint16_t) ((uint16_t) reg_addr >> 5351 GG82563_PAGE_SHIFT)); 5352 } else { 5353 /* 5354 * Use Alternative Page Select register to 5355 * access registers 30 and 31 5356 */ 5357 ret_val = em_write_phy_reg_ex(hw, 5358 GG82563_PHY_PAGE_SELECT_ALT, 5359 (uint16_t) ((uint16_t) reg_addr >> 5360 GG82563_PAGE_SHIFT)); 5361 } 5362 5363 if (ret_val) { 5364 em_swfw_sync_release(hw, hw->swfw); 5365 return ret_val; 5366 } 5367 } 5368 } else if ((hw->phy_type == em_phy_bm) && (hw->phy_revision == 1)) { 5369 if (reg_addr > MAX_PHY_MULTI_PAGE_REG) { 5370 ret_val = em_write_phy_reg_ex(hw, BM_PHY_PAGE_SELECT, 5371 (uint16_t) ((uint16_t) reg_addr >> 5372 PHY_PAGE_SHIFT)); 5373 if (ret_val) 5374 return ret_val; 5375 } 5376 } 5377 ret_val = em_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, 5378 phy_data); 5379 5380 em_swfw_sync_release(hw, hw->swfw); 5381 return ret_val; 5382 } 5383 5384 STATIC int32_t 5385 em_write_phy_reg_ex(struct em_hw *hw, uint32_t reg_addr, uint16_t phy_data) 5386 { 5387 uint32_t i; 5388 uint32_t mdic = 0; 5389 DEBUGFUNC("em_write_phy_reg_ex"); 5390 5391 /* SGMII active is only set on some specific chips */ 5392 if (hw->sgmii_active && !em_sgmii_uses_mdio_82575(hw)) { 5393 if (reg_addr > E1000_MAX_SGMII_PHY_REG_ADDR) { 5394 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); 5395 return -E1000_ERR_PARAM; 5396 } 5397 return em_write_phy_reg_i2c(hw, reg_addr, phy_data); 5398 } 5399 if (reg_addr > MAX_PHY_REG_ADDRESS) { 5400 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); 5401 return -E1000_ERR_PARAM; 5402 } 5403 if (hw->mac_type == em_icp_xxxx) { 5404 gcu_miibus_writereg(hw, hw->icp_xxxx_port_num, 5405 reg_addr, phy_data); 5406 return E1000_SUCCESS; 5407 } 5408 if (hw->mac_type > em_82543) { 5409 /* 5410 * Set up Op-code, Phy Address, register address, and data 5411 * intended for the PHY register in the MDI Control register. 5412 * The MAC will take care of interfacing with the PHY to send 5413 * the desired data. 5414 */ 5415 mdic = (((uint32_t) phy_data) | 5416 (reg_addr << E1000_MDIC_REG_SHIFT) | 5417 (hw->phy_addr << E1000_MDIC_PHY_SHIFT) | 5418 (E1000_MDIC_OP_WRITE)); 5419 5420 E1000_WRITE_REG(hw, MDIC, mdic); 5421 5422 /* Poll the ready bit to see if the MDI read completed */ 5423 for (i = 0; i < 641; i++) { 5424 usec_delay(5); 5425 mdic = E1000_READ_REG(hw, MDIC); 5426 if (mdic & E1000_MDIC_READY) 5427 break; 5428 } 5429 if (!(mdic & E1000_MDIC_READY)) { 5430 DEBUGOUT("MDI Write did not complete\n"); 5431 return -E1000_ERR_PHY; 5432 } 5433 5434 if (hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt || 5435 hw->mac_type == em_pch_spt || hw->mac_type == em_pch_cnp || 5436 hw->mac_type == em_pch_tgp || hw->mac_type == em_pch_adp) 5437 usec_delay(100); 5438 } else { 5439 /* 5440 * We'll need to use the SW defined pins to shift the write 5441 * command out to the PHY. We first send a preamble to the 5442 * PHY to signal the beginning of the MII instruction. This 5443 * is done by sending 32 consecutive "1" bits. 5444 */ 5445 em_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 5446 /* 5447 * Now combine the remaining required fields that will 5448 * indicate a write operation. We use this method instead of 5449 * calling the em_shift_out_mdi_bits routine for each field 5450 * in the command. The format of a MII write instruction is 5451 * as follows: <Preamble><SOF><Op Code><Phy Addr><Reg 5452 * Addr><Turnaround><Data>. 5453 */ 5454 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | 5455 (hw->phy_addr << 7) | (PHY_OP_WRITE << 12) | 5456 (PHY_SOF << 14)); 5457 mdic <<= 16; 5458 mdic |= (uint32_t) phy_data; 5459 5460 em_shift_out_mdi_bits(hw, mdic, 32); 5461 } 5462 5463 return E1000_SUCCESS; 5464 } 5465 5466 STATIC int32_t 5467 em_read_kmrn_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t *data) 5468 { 5469 uint32_t reg_val; 5470 DEBUGFUNC("em_read_kmrn_reg"); 5471 5472 if (em_swfw_sync_acquire(hw, hw->swfw)) 5473 return -E1000_ERR_SWFW_SYNC; 5474 5475 /* Write register address */ 5476 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) & 5477 E1000_KUMCTRLSTA_OFFSET) | 5478 E1000_KUMCTRLSTA_REN; 5479 5480 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); 5481 usec_delay(2); 5482 5483 /* Read the data returned */ 5484 reg_val = E1000_READ_REG(hw, KUMCTRLSTA); 5485 *data = (uint16_t) reg_val; 5486 5487 em_swfw_sync_release(hw, hw->swfw); 5488 return E1000_SUCCESS; 5489 } 5490 5491 STATIC int32_t 5492 em_write_kmrn_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t data) 5493 { 5494 uint32_t reg_val; 5495 DEBUGFUNC("em_write_kmrn_reg"); 5496 5497 if (em_swfw_sync_acquire(hw, hw->swfw)) 5498 return -E1000_ERR_SWFW_SYNC; 5499 5500 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) & 5501 E1000_KUMCTRLSTA_OFFSET) | data; 5502 5503 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); 5504 usec_delay(2); 5505 5506 em_swfw_sync_release(hw, hw->swfw); 5507 return E1000_SUCCESS; 5508 } 5509 5510 /** 5511 * em_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO 5512 * @hw: pointer to the HW structure 5513 * 5514 * Called to determine if the I2C pins are being used for I2C or as an 5515 * external MDIO interface since the two options are mutually exclusive. 5516 **/ 5517 int em_sgmii_uses_mdio_82575(struct em_hw *hw) 5518 { 5519 uint32_t reg = 0; 5520 int ext_mdio = 0; 5521 5522 DEBUGFUNC("em_sgmii_uses_mdio_82575"); 5523 5524 switch (hw->mac_type) { 5525 case em_82575: 5526 case em_82576: 5527 reg = E1000_READ_REG(hw, MDIC); 5528 ext_mdio = !!(reg & E1000_MDIC_DEST); 5529 break; 5530 case em_82580: 5531 case em_i350: 5532 case em_i210: 5533 reg = E1000_READ_REG(hw, MDICNFG); 5534 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO); 5535 break; 5536 default: 5537 break; 5538 } 5539 return ext_mdio; 5540 } 5541 5542 /** 5543 * em_read_phy_reg_i2c - Read PHY register using i2c 5544 * @hw: pointer to the HW structure 5545 * @offset: register offset to be read 5546 * @data: pointer to the read data 5547 * 5548 * Reads the PHY register at offset using the i2c interface and stores the 5549 * retrieved information in data. 5550 **/ 5551 int32_t em_read_phy_reg_i2c(struct em_hw *hw, uint32_t offset, uint16_t *data) 5552 { 5553 uint32_t i, i2ccmd = 0; 5554 5555 DEBUGFUNC("em_read_phy_reg_i2c"); 5556 5557 /* Set up Op-code, Phy Address, and register address in the I2CCMD 5558 * register. The MAC will take care of interfacing with the 5559 * PHY to retrieve the desired data. 5560 */ 5561 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 5562 (hw->phy_addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | 5563 (E1000_I2CCMD_OPCODE_READ)); 5564 5565 E1000_WRITE_REG(hw, I2CCMD, i2ccmd); 5566 5567 /* Poll the ready bit to see if the I2C read completed */ 5568 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 5569 usec_delay(50); 5570 i2ccmd = E1000_READ_REG(hw, I2CCMD); 5571 if (i2ccmd & E1000_I2CCMD_READY) 5572 break; 5573 } 5574 if (!(i2ccmd & E1000_I2CCMD_READY)) { 5575 DEBUGOUT("I2CCMD Read did not complete\n"); 5576 return -E1000_ERR_PHY; 5577 } 5578 if (i2ccmd & E1000_I2CCMD_ERROR) { 5579 DEBUGOUT("I2CCMD Error bit set\n"); 5580 return -E1000_ERR_PHY; 5581 } 5582 5583 /* Need to byte-swap the 16-bit value. */ 5584 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00); 5585 5586 return E1000_SUCCESS; 5587 } 5588 5589 /** 5590 * em_write_phy_reg_i2c - Write PHY register using i2c 5591 * @hw: pointer to the HW structure 5592 * @offset: register offset to write to 5593 * @data: data to write at register offset 5594 * 5595 * Writes the data to PHY register at the offset using the i2c interface. 5596 **/ 5597 int32_t em_write_phy_reg_i2c(struct em_hw *hw, uint32_t offset, uint16_t data) 5598 { 5599 uint32_t i, i2ccmd = 0; 5600 uint16_t phy_data_swapped; 5601 5602 DEBUGFUNC("em_write_phy_reg_i2c"); 5603 5604 /* Prevent overwriting SFP I2C EEPROM which is at A0 address.*/ 5605 if ((hw->phy_addr == 0) || (hw->phy_addr > 7)) { 5606 DEBUGOUT1("PHY I2C Address %d is out of range.\n", 5607 hw->phy_addr); 5608 return -E1000_ERR_CONFIG; 5609 } 5610 5611 /* Swap the data bytes for the I2C interface */ 5612 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00); 5613 5614 /* Set up Op-code, Phy Address, and register address in the I2CCMD 5615 * register. The MAC will take care of interfacing with the 5616 * PHY to retrieve the desired data. 5617 */ 5618 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 5619 (hw->phy_addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | 5620 E1000_I2CCMD_OPCODE_WRITE | 5621 phy_data_swapped); 5622 5623 E1000_WRITE_REG(hw, I2CCMD, i2ccmd); 5624 5625 /* Poll the ready bit to see if the I2C read completed */ 5626 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 5627 usec_delay(50); 5628 i2ccmd = E1000_READ_REG(hw, I2CCMD); 5629 if (i2ccmd & E1000_I2CCMD_READY) 5630 break; 5631 } 5632 if (!(i2ccmd & E1000_I2CCMD_READY)) { 5633 DEBUGOUT("I2CCMD Write did not complete\n"); 5634 return -E1000_ERR_PHY; 5635 } 5636 if (i2ccmd & E1000_I2CCMD_ERROR) { 5637 DEBUGOUT("I2CCMD Error bit set\n"); 5638 return -E1000_ERR_PHY; 5639 } 5640 5641 return E1000_SUCCESS; 5642 } 5643 5644 /** 5645 * em_read_sfp_data_byte - Reads SFP module data. 5646 * @hw: pointer to the HW structure 5647 * @offset: byte location offset to be read 5648 * @data: read data buffer pointer 5649 * 5650 * Reads one byte from SFP module data stored 5651 * in SFP resided EEPROM memory or SFP diagnostic area. 5652 * Function should be called with 5653 * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access 5654 * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters 5655 * access 5656 **/ 5657 int32_t em_read_sfp_data_byte(struct em_hw *hw, uint16_t offset, uint8_t *data) 5658 { 5659 uint32_t i = 0; 5660 uint32_t i2ccmd = 0; 5661 uint32_t data_local = 0; 5662 5663 DEBUGFUNC("em_read_sfp_data_byte"); 5664 5665 if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) { 5666 DEBUGOUT("I2CCMD command address exceeds upper limit\n"); 5667 return -E1000_ERR_PHY; 5668 } 5669 5670 /* Set up Op-code, EEPROM Address,in the I2CCMD 5671 * register. The MAC will take care of interfacing with the 5672 * EEPROM to retrieve the desired data. 5673 */ 5674 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 5675 E1000_I2CCMD_OPCODE_READ); 5676 5677 E1000_WRITE_REG(hw, I2CCMD, i2ccmd); 5678 5679 /* Poll the ready bit to see if the I2C read completed */ 5680 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 5681 usec_delay(50); 5682 data_local = E1000_READ_REG(hw, I2CCMD); 5683 if (data_local & E1000_I2CCMD_READY) 5684 break; 5685 } 5686 if (!(data_local & E1000_I2CCMD_READY)) { 5687 DEBUGOUT("I2CCMD Read did not complete\n"); 5688 return -E1000_ERR_PHY; 5689 } 5690 if (data_local & E1000_I2CCMD_ERROR) { 5691 DEBUGOUT("I2CCMD Error bit set\n"); 5692 return -E1000_ERR_PHY; 5693 } 5694 *data = (uint8_t) data_local & 0xFF; 5695 5696 return E1000_SUCCESS; 5697 } 5698 5699 /****************************************************************************** 5700 * Returns the PHY to the power-on reset state 5701 * 5702 * hw - Struct containing variables accessed by shared code 5703 *****************************************************************************/ 5704 int32_t 5705 em_phy_hw_reset(struct em_hw *hw) 5706 { 5707 uint32_t ctrl, ctrl_ext; 5708 uint32_t led_ctrl; 5709 int32_t ret_val; 5710 DEBUGFUNC("em_phy_hw_reset"); 5711 /* 5712 * In the case of the phy reset being blocked, it's not an error, we 5713 * simply return success without performing the reset. 5714 */ 5715 ret_val = em_check_phy_reset_block(hw); 5716 if (ret_val) 5717 return E1000_SUCCESS; 5718 5719 DEBUGOUT("Resetting Phy...\n"); 5720 5721 if (hw->mac_type > em_82543 && hw->mac_type != em_icp_xxxx) { 5722 if (em_swfw_sync_acquire(hw, hw->swfw)) { 5723 DEBUGOUT("Unable to acquire swfw sync\n"); 5724 return -E1000_ERR_SWFW_SYNC; 5725 } 5726 /* 5727 * Read the device control register and assert the 5728 * E1000_CTRL_PHY_RST bit. Then, take it out of reset. For 5729 * pre-em_82571 hardware, we delay for 10ms between the 5730 * assert and deassert. For em_82571 hardware and later, we 5731 * instead delay for 50us between and 10ms after the 5732 * deassertion. 5733 */ 5734 ctrl = E1000_READ_REG(hw, CTRL); 5735 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST); 5736 E1000_WRITE_FLUSH(hw); 5737 5738 if (hw->mac_type < em_82571) 5739 msec_delay(10); 5740 else 5741 usec_delay(100); 5742 5743 E1000_WRITE_REG(hw, CTRL, ctrl); 5744 E1000_WRITE_FLUSH(hw); 5745 5746 if (hw->mac_type >= em_82571) 5747 msec_delay_irq(10); 5748 em_swfw_sync_release(hw, hw->swfw); 5749 /* 5750 * the M88E1141_E_PHY_ID might need reset here, but nothing 5751 * proves it 5752 */ 5753 } else { 5754 /* 5755 * Read the Extended Device Control Register, assert the 5756 * PHY_RESET_DIR bit to put the PHY into reset. Then, take it 5757 * out of reset. 5758 */ 5759 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 5760 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; 5761 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; 5762 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 5763 E1000_WRITE_FLUSH(hw); 5764 msec_delay(10); 5765 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; 5766 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 5767 E1000_WRITE_FLUSH(hw); 5768 } 5769 usec_delay(150); 5770 5771 if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) { 5772 /* Configure activity LED after PHY reset */ 5773 led_ctrl = E1000_READ_REG(hw, LEDCTL); 5774 led_ctrl &= IGP_ACTIVITY_LED_MASK; 5775 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 5776 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 5777 } 5778 /* Wait for FW to finish PHY configuration. */ 5779 ret_val = em_get_phy_cfg_done(hw); 5780 if (ret_val != E1000_SUCCESS) 5781 return ret_val; 5782 em_release_software_semaphore(hw); 5783 5784 if ((hw->mac_type == em_ich8lan) && (hw->phy_type == em_phy_igp_3)) 5785 ret_val = em_init_lcd_from_nvm(hw); 5786 5787 return ret_val; 5788 } 5789 5790 /***************************************************************************** 5791 * SW-based LCD Configuration. 5792 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are 5793 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit 5794 * in NVM determines whether HW should configure LPLU and Gbe Disable. 5795 *****************************************************************************/ 5796 int32_t 5797 em_oem_bits_config_pchlan(struct em_hw *hw, boolean_t d0_state) 5798 { 5799 int32_t ret_val = E1000_SUCCESS; 5800 uint32_t mac_reg; 5801 uint16_t oem_reg; 5802 uint16_t swfw = E1000_SWFW_PHY0_SM; 5803 5804 if (hw->mac_type < em_pchlan) 5805 return ret_val; 5806 5807 ret_val = em_swfw_sync_acquire(hw, swfw); 5808 if (ret_val) 5809 return ret_val; 5810 5811 if (hw->mac_type == em_pchlan) { 5812 mac_reg = E1000_READ_REG(hw, EXTCNF_CTRL); 5813 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) 5814 goto out; 5815 } 5816 5817 mac_reg = E1000_READ_REG(hw, FEXTNVM); 5818 if (!(mac_reg & FEXTNVM_SW_CONFIG_ICH8M)) 5819 goto out; 5820 5821 mac_reg = E1000_READ_REG(hw, PHY_CTRL); 5822 5823 ret_val = em_read_phy_reg(hw, HV_OEM_BITS, &oem_reg); 5824 if (ret_val) 5825 goto out; 5826 5827 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU); 5828 5829 if (d0_state) { 5830 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE) 5831 oem_reg |= HV_OEM_BITS_GBE_DIS; 5832 5833 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU) 5834 oem_reg |= HV_OEM_BITS_LPLU; 5835 /* Restart auto-neg to activate the bits */ 5836 if (!em_check_phy_reset_block(hw)) 5837 oem_reg |= HV_OEM_BITS_RESTART_AN; 5838 5839 } else { 5840 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE | 5841 E1000_PHY_CTRL_NOND0A_GBE_DISABLE)) 5842 oem_reg |= HV_OEM_BITS_GBE_DIS; 5843 5844 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU | 5845 E1000_PHY_CTRL_NOND0A_LPLU)) 5846 oem_reg |= HV_OEM_BITS_LPLU; 5847 } 5848 5849 ret_val = em_write_phy_reg(hw, HV_OEM_BITS, oem_reg); 5850 5851 out: 5852 em_swfw_sync_release(hw, swfw); 5853 5854 return ret_val; 5855 } 5856 5857 5858 /****************************************************************************** 5859 * Resets the PHY 5860 * 5861 * hw - Struct containing variables accessed by shared code 5862 * 5863 * Sets bit 15 of the MII Control register 5864 *****************************************************************************/ 5865 int32_t 5866 em_phy_reset(struct em_hw *hw) 5867 { 5868 int32_t ret_val; 5869 uint16_t phy_data; 5870 DEBUGFUNC("em_phy_reset"); 5871 /* 5872 * In the case of the phy reset being blocked, it's not an error, we 5873 * simply return success without performing the reset. 5874 */ 5875 ret_val = em_check_phy_reset_block(hw); 5876 if (ret_val) 5877 return E1000_SUCCESS; 5878 5879 switch (hw->phy_type) { 5880 case em_phy_igp: 5881 case em_phy_igp_2: 5882 case em_phy_igp_3: 5883 case em_phy_ife: 5884 ret_val = em_phy_hw_reset(hw); 5885 if (ret_val) 5886 return ret_val; 5887 break; 5888 default: 5889 ret_val = em_read_phy_reg(hw, PHY_CTRL, &phy_data); 5890 if (ret_val) 5891 return ret_val; 5892 5893 phy_data |= MII_CR_RESET; 5894 ret_val = em_write_phy_reg(hw, PHY_CTRL, phy_data); 5895 if (ret_val) 5896 return ret_val; 5897 5898 usec_delay(1); 5899 break; 5900 } 5901 5902 /* Allow time for h/w to get to a quiescent state after reset */ 5903 msec_delay(10); 5904 5905 if (hw->phy_type == em_phy_igp || hw->phy_type == em_phy_igp_2) 5906 em_phy_init_script(hw); 5907 5908 if (hw->mac_type == em_pchlan) { 5909 ret_val = em_hv_phy_workarounds_ich8lan(hw); 5910 if (ret_val) 5911 return ret_val; 5912 } else if (hw->mac_type == em_pch2lan) { 5913 ret_val = em_lv_phy_workarounds_ich8lan(hw); 5914 if (ret_val) 5915 return ret_val; 5916 } 5917 5918 if (hw->mac_type >= em_pchlan) { 5919 ret_val = em_oem_bits_config_pchlan(hw, TRUE); 5920 if (ret_val) 5921 return ret_val; 5922 } 5923 5924 /* Ungate automatic PHY configuration on non-managed 82579 */ 5925 if ((hw->mac_type == em_pch2lan) && 5926 !(E1000_READ_REG(hw, FWSM) & E1000_FWSM_FW_VALID)) { 5927 msec_delay(10); 5928 em_gate_hw_phy_config_ich8lan(hw, FALSE); 5929 } 5930 5931 if (hw->phy_id == M88E1512_E_PHY_ID) { 5932 ret_val = em_initialize_M88E1512_phy(hw); 5933 if (ret_val) 5934 return ret_val; 5935 } 5936 5937 return E1000_SUCCESS; 5938 } 5939 5940 /****************************************************************************** 5941 * Work-around for 82566 Kumeran PCS lock loss: 5942 * On link status change (i.e. PCI reset, speed change) and link is up and 5943 * speed is gigabit- 5944 * 0) if workaround is optionally disabled do nothing 5945 * 1) wait 1ms for Kumeran link to come up 5946 * 2) check Kumeran Diagnostic register PCS lock loss bit 5947 * 3) if not set the link is locked (all is good), otherwise... 5948 * 4) reset the PHY 5949 * 5) repeat up to 10 times 5950 * Note: this is only called for IGP3 copper when speed is 1gb. 5951 * 5952 * hw - struct containing variables accessed by shared code 5953 *****************************************************************************/ 5954 STATIC int32_t 5955 em_kumeran_lock_loss_workaround(struct em_hw *hw) 5956 { 5957 int32_t ret_val; 5958 int32_t reg; 5959 int32_t cnt; 5960 uint16_t phy_data; 5961 if (hw->kmrn_lock_loss_workaround_disabled) 5962 return E1000_SUCCESS; 5963 /* 5964 * Make sure link is up before proceeding. If not just return. 5965 * Attempting this while link is negotiating fouled up link stability 5966 */ 5967 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 5968 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 5969 5970 if (phy_data & MII_SR_LINK_STATUS) { 5971 for (cnt = 0; cnt < 10; cnt++) { 5972 /* read once to clear */ 5973 ret_val = em_read_phy_reg(hw, IGP3_KMRN_DIAG, 5974 &phy_data); 5975 if (ret_val) 5976 return ret_val; 5977 /* and again to get new status */ 5978 ret_val = em_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data); 5979 if (ret_val) 5980 return ret_val; 5981 5982 /* check for PCS lock */ 5983 if (!(phy_data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) 5984 return E1000_SUCCESS; 5985 5986 /* Issue PHY reset */ 5987 em_phy_hw_reset(hw); 5988 msec_delay_irq(5); 5989 } 5990 /* Disable GigE link negotiation */ 5991 reg = E1000_READ_REG(hw, PHY_CTRL); 5992 E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE 5993 | E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 5994 5995 /* unable to acquire PCS lock */ 5996 return E1000_ERR_PHY; 5997 } 5998 return E1000_SUCCESS; 5999 } 6000 6001 /****************************************************************************** 6002 * Reads and matches the expected PHY address for known PHY IDs 6003 * 6004 * hw - Struct containing variables accessed by shared code 6005 *****************************************************************************/ 6006 STATIC int32_t 6007 em_match_gig_phy(struct em_hw *hw) 6008 { 6009 int32_t phy_init_status, ret_val; 6010 uint16_t phy_id_high, phy_id_low; 6011 boolean_t match = FALSE; 6012 DEBUGFUNC("em_match_gig_phy"); 6013 6014 ret_val = em_read_phy_reg(hw, PHY_ID1, &phy_id_high); 6015 if (ret_val) 6016 return ret_val; 6017 6018 hw->phy_id = (uint32_t) (phy_id_high << 16); 6019 usec_delay(20); 6020 ret_val = em_read_phy_reg(hw, PHY_ID2, &phy_id_low); 6021 if (ret_val) 6022 return ret_val; 6023 6024 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK); 6025 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK; 6026 6027 switch (hw->mac_type) { 6028 case em_82543: 6029 if (hw->phy_id == M88E1000_E_PHY_ID) 6030 match = TRUE; 6031 break; 6032 case em_82544: 6033 if (hw->phy_id == M88E1000_I_PHY_ID) 6034 match = TRUE; 6035 break; 6036 case em_82540: 6037 case em_82545: 6038 case em_82545_rev_3: 6039 case em_82546: 6040 case em_82546_rev_3: 6041 if (hw->phy_id == M88E1011_I_PHY_ID) 6042 match = TRUE; 6043 break; 6044 case em_82541: 6045 case em_82541_rev_2: 6046 case em_82547: 6047 case em_82547_rev_2: 6048 if (hw->phy_id == IGP01E1000_I_PHY_ID) 6049 match = TRUE; 6050 break; 6051 case em_82573: 6052 if (hw->phy_id == M88E1111_I_PHY_ID) 6053 match = TRUE; 6054 break; 6055 case em_82574: 6056 if (hw->phy_id == BME1000_E_PHY_ID) 6057 match = TRUE; 6058 break; 6059 case em_82575: 6060 case em_82576: 6061 if (hw->phy_id == M88E1000_E_PHY_ID) 6062 match = TRUE; 6063 if (hw->phy_id == IGP01E1000_I_PHY_ID) 6064 match = TRUE; 6065 if (hw->phy_id == IGP03E1000_E_PHY_ID) 6066 match = TRUE; 6067 break; 6068 case em_82580: 6069 case em_i210: 6070 case em_i350: 6071 if (hw->phy_id == I82580_I_PHY_ID || 6072 hw->phy_id == I210_I_PHY_ID || 6073 hw->phy_id == I347AT4_E_PHY_ID || 6074 hw->phy_id == I350_I_PHY_ID || 6075 hw->phy_id == M88E1111_I_PHY_ID || 6076 hw->phy_id == M88E1112_E_PHY_ID || 6077 hw->phy_id == M88E1543_E_PHY_ID || 6078 hw->phy_id == M88E1512_E_PHY_ID) { 6079 uint32_t mdic; 6080 6081 mdic = EM_READ_REG(hw, E1000_MDICNFG); 6082 if (mdic & E1000_MDICNFG_EXT_MDIO) { 6083 mdic &= E1000_MDICNFG_PHY_MASK; 6084 hw->phy_addr = mdic >> E1000_MDICNFG_PHY_SHIFT; 6085 DEBUGOUT1("MDICNFG PHY ADDR %d", 6086 mdic >> E1000_MDICNFG_PHY_SHIFT); 6087 } 6088 match = TRUE; 6089 } 6090 break; 6091 case em_80003es2lan: 6092 if (hw->phy_id == GG82563_E_PHY_ID) 6093 match = TRUE; 6094 break; 6095 case em_ich8lan: 6096 case em_ich9lan: 6097 case em_ich10lan: 6098 case em_pchlan: 6099 case em_pch2lan: 6100 if (hw->phy_id == IGP03E1000_E_PHY_ID) 6101 match = TRUE; 6102 if (hw->phy_id == IFE_E_PHY_ID) 6103 match = TRUE; 6104 if (hw->phy_id == IFE_PLUS_E_PHY_ID) 6105 match = TRUE; 6106 if (hw->phy_id == IFE_C_E_PHY_ID) 6107 match = TRUE; 6108 if (hw->phy_id == BME1000_E_PHY_ID) 6109 match = TRUE; 6110 if (hw->phy_id == I82577_E_PHY_ID) 6111 match = TRUE; 6112 if (hw->phy_id == I82578_E_PHY_ID) 6113 match = TRUE; 6114 if (hw->phy_id == I82579_E_PHY_ID) 6115 match = TRUE; 6116 break; 6117 case em_pch_lpt: 6118 case em_pch_spt: 6119 case em_pch_cnp: 6120 case em_pch_tgp: 6121 case em_pch_adp: 6122 if (hw->phy_id == I217_E_PHY_ID) 6123 match = TRUE; 6124 break; 6125 case em_icp_xxxx: 6126 if (hw->phy_id == M88E1141_E_PHY_ID) 6127 match = TRUE; 6128 if (hw->phy_id == RTL8211_E_PHY_ID) 6129 match = TRUE; 6130 break; 6131 default: 6132 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type); 6133 return -E1000_ERR_CONFIG; 6134 } 6135 phy_init_status = em_set_phy_type(hw); 6136 6137 if ((match) && (phy_init_status == E1000_SUCCESS)) { 6138 DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id); 6139 return E1000_SUCCESS; 6140 } 6141 DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id); 6142 return -E1000_ERR_PHY; 6143 } 6144 6145 /****************************************************************************** 6146 * Probes the expected PHY address for known PHY IDs 6147 * 6148 * hw - Struct containing variables accessed by shared code 6149 *****************************************************************************/ 6150 STATIC int32_t 6151 em_detect_gig_phy(struct em_hw *hw) 6152 { 6153 int32_t ret_val, i; 6154 DEBUGFUNC("em_detect_gig_phy"); 6155 6156 if (hw->phy_id != 0) 6157 return E1000_SUCCESS; 6158 6159 /* default phy address, most phys reside here, but not all (ICH10) */ 6160 if (hw->mac_type != em_icp_xxxx) 6161 hw->phy_addr = 1; 6162 else 6163 hw->phy_addr = 0; /* There is a phy at phy_addr 0 on EP80579 */ 6164 6165 /* 6166 * The 82571 firmware may still be configuring the PHY. In this 6167 * case, we cannot access the PHY until the configuration is done. 6168 * So we explicitly set the PHY values. 6169 */ 6170 if (hw->mac_type == em_82571 || 6171 hw->mac_type == em_82572) { 6172 hw->phy_id = IGP01E1000_I_PHY_ID; 6173 hw->phy_type = em_phy_igp_2; 6174 return E1000_SUCCESS; 6175 } 6176 6177 /* 6178 * Some of the fiber cards dont have a phy, so we must exit cleanly 6179 * here 6180 */ 6181 if ((hw->media_type == em_media_type_fiber) && 6182 (hw->mac_type == em_82542_rev2_0 || 6183 hw->mac_type == em_82542_rev2_1 || 6184 hw->mac_type == em_82543 || 6185 hw->mac_type == em_82573 || 6186 hw->mac_type == em_82574 || 6187 hw->mac_type == em_80003es2lan)) { 6188 hw->phy_type = em_phy_undefined; 6189 return E1000_SUCCESS; 6190 } 6191 6192 if ((hw->media_type == em_media_type_internal_serdes || 6193 hw->media_type == em_media_type_fiber) && 6194 hw->mac_type >= em_82575) { 6195 hw->phy_type = em_phy_undefined; 6196 return E1000_SUCCESS; 6197 } 6198 6199 /* 6200 * Up to 82543 (incl), we need reset the phy, or it might not get 6201 * detected 6202 */ 6203 if (hw->mac_type <= em_82543) { 6204 ret_val = em_phy_hw_reset(hw); 6205 if (ret_val) 6206 return ret_val; 6207 } 6208 /* 6209 * ESB-2 PHY reads require em_phy_gg82563 to be set because of a 6210 * work- around that forces PHY page 0 to be set or the reads fail. 6211 * The rest of the code in this routine uses em_read_phy_reg to read 6212 * the PHY ID. So for ESB-2 we need to have this set so our reads 6213 * won't fail. If the attached PHY is not a em_phy_gg82563, the 6214 * routines below will figure this out as well. 6215 */ 6216 if (hw->mac_type == em_80003es2lan) 6217 hw->phy_type = em_phy_gg82563; 6218 6219 /* Power on SGMII phy if it is disabled */ 6220 if (hw->mac_type == em_82580 || hw->mac_type == em_i210 || 6221 hw->mac_type == em_i350) { 6222 uint32_t ctrl_ext = EM_READ_REG(hw, E1000_CTRL_EXT); 6223 EM_WRITE_REG(hw, E1000_CTRL_EXT, 6224 ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA); 6225 E1000_WRITE_FLUSH(hw); 6226 msec_delay(300); 6227 } 6228 6229 /* Read the PHY ID Registers to identify which PHY is onboard. */ 6230 for (i = 1; i < 8; i++) { 6231 /* 6232 * hw->phy_addr may be modified down in the call stack, 6233 * we can't use it as loop variable. 6234 */ 6235 hw->phy_addr = i; 6236 ret_val = em_match_gig_phy(hw); 6237 if (ret_val == E1000_SUCCESS) 6238 return E1000_SUCCESS; 6239 } 6240 return -E1000_ERR_PHY; 6241 } 6242 6243 /****************************************************************************** 6244 * Resets the PHY's DSP 6245 * 6246 * hw - Struct containing variables accessed by shared code 6247 *****************************************************************************/ 6248 static int32_t 6249 em_phy_reset_dsp(struct em_hw *hw) 6250 { 6251 int32_t ret_val; 6252 DEBUGFUNC("em_phy_reset_dsp"); 6253 6254 do { 6255 if (hw->phy_type != em_phy_gg82563) { 6256 ret_val = em_write_phy_reg(hw, 29, 0x001d); 6257 if (ret_val) 6258 break; 6259 } 6260 ret_val = em_write_phy_reg(hw, 30, 0x00c1); 6261 if (ret_val) 6262 break; 6263 ret_val = em_write_phy_reg(hw, 30, 0x0000); 6264 if (ret_val) 6265 break; 6266 ret_val = E1000_SUCCESS; 6267 } while (0); 6268 6269 return ret_val; 6270 } 6271 6272 /****************************************************************************** 6273 * Sets up eeprom variables in the hw struct. Must be called after mac_type 6274 * is configured. Additionally, if this is ICH8, the flash controller GbE 6275 * registers must be mapped, or this will crash. 6276 * 6277 * hw - Struct containing variables accessed by shared code 6278 *****************************************************************************/ 6279 int32_t 6280 em_init_eeprom_params(struct em_hw *hw) 6281 { 6282 struct em_eeprom_info *eeprom = &hw->eeprom; 6283 uint32_t eecd = E1000_READ_REG(hw, EECD); 6284 int32_t ret_val = E1000_SUCCESS; 6285 uint16_t eeprom_size; 6286 DEBUGFUNC("em_init_eeprom_params"); 6287 6288 switch (hw->mac_type) { 6289 case em_82542_rev2_0: 6290 case em_82542_rev2_1: 6291 case em_82543: 6292 case em_82544: 6293 eeprom->type = em_eeprom_microwire; 6294 eeprom->word_size = 64; 6295 eeprom->opcode_bits = 3; 6296 eeprom->address_bits = 6; 6297 eeprom->delay_usec = 50; 6298 eeprom->use_eerd = FALSE; 6299 eeprom->use_eewr = FALSE; 6300 break; 6301 case em_82540: 6302 case em_82545: 6303 case em_82545_rev_3: 6304 case em_icp_xxxx: 6305 case em_82546: 6306 case em_82546_rev_3: 6307 eeprom->type = em_eeprom_microwire; 6308 eeprom->opcode_bits = 3; 6309 eeprom->delay_usec = 50; 6310 if (eecd & E1000_EECD_SIZE) { 6311 eeprom->word_size = 256; 6312 eeprom->address_bits = 8; 6313 } else { 6314 eeprom->word_size = 64; 6315 eeprom->address_bits = 6; 6316 } 6317 eeprom->use_eerd = FALSE; 6318 eeprom->use_eewr = FALSE; 6319 break; 6320 case em_82541: 6321 case em_82541_rev_2: 6322 case em_82547: 6323 case em_82547_rev_2: 6324 if (eecd & E1000_EECD_TYPE) { 6325 eeprom->type = em_eeprom_spi; 6326 eeprom->opcode_bits = 8; 6327 eeprom->delay_usec = 1; 6328 if (eecd & E1000_EECD_ADDR_BITS) { 6329 eeprom->page_size = 32; 6330 eeprom->address_bits = 16; 6331 } else { 6332 eeprom->page_size = 8; 6333 eeprom->address_bits = 8; 6334 } 6335 } else { 6336 eeprom->type = em_eeprom_microwire; 6337 eeprom->opcode_bits = 3; 6338 eeprom->delay_usec = 50; 6339 if (eecd & E1000_EECD_ADDR_BITS) { 6340 eeprom->word_size = 256; 6341 eeprom->address_bits = 8; 6342 } else { 6343 eeprom->word_size = 64; 6344 eeprom->address_bits = 6; 6345 } 6346 } 6347 eeprom->use_eerd = FALSE; 6348 eeprom->use_eewr = FALSE; 6349 break; 6350 case em_82571: 6351 case em_82572: 6352 eeprom->type = em_eeprom_spi; 6353 eeprom->opcode_bits = 8; 6354 eeprom->delay_usec = 1; 6355 if (eecd & E1000_EECD_ADDR_BITS) { 6356 eeprom->page_size = 32; 6357 eeprom->address_bits = 16; 6358 } else { 6359 eeprom->page_size = 8; 6360 eeprom->address_bits = 8; 6361 } 6362 eeprom->use_eerd = FALSE; 6363 eeprom->use_eewr = FALSE; 6364 break; 6365 case em_82573: 6366 case em_82574: 6367 case em_82575: 6368 case em_82576: 6369 case em_82580: 6370 case em_i210: 6371 case em_i350: 6372 eeprom->type = em_eeprom_spi; 6373 eeprom->opcode_bits = 8; 6374 eeprom->delay_usec = 1; 6375 if (eecd & E1000_EECD_ADDR_BITS) { 6376 eeprom->page_size = 32; 6377 eeprom->address_bits = 16; 6378 } else { 6379 eeprom->page_size = 8; 6380 eeprom->address_bits = 8; 6381 } 6382 eeprom->use_eerd = TRUE; 6383 eeprom->use_eewr = TRUE; 6384 if (em_is_onboard_nvm_eeprom(hw) == FALSE) { 6385 eeprom->type = em_eeprom_flash; 6386 eeprom->word_size = 2048; 6387 /* 6388 * Ensure that the Autonomous FLASH update bit is 6389 * cleared due to Flash update issue on parts which 6390 * use a FLASH for NVM. 6391 */ 6392 eecd &= ~E1000_EECD_AUPDEN; 6393 E1000_WRITE_REG(hw, EECD, eecd); 6394 } 6395 if (em_get_flash_presence_i210(hw) == FALSE) { 6396 eeprom->type = em_eeprom_invm; 6397 eeprom->word_size = INVM_SIZE; 6398 eeprom->use_eerd = FALSE; 6399 eeprom->use_eewr = FALSE; 6400 } 6401 break; 6402 case em_80003es2lan: 6403 eeprom->type = em_eeprom_spi; 6404 eeprom->opcode_bits = 8; 6405 eeprom->delay_usec = 1; 6406 if (eecd & E1000_EECD_ADDR_BITS) { 6407 eeprom->page_size = 32; 6408 eeprom->address_bits = 16; 6409 } else { 6410 eeprom->page_size = 8; 6411 eeprom->address_bits = 8; 6412 } 6413 eeprom->use_eerd = TRUE; 6414 eeprom->use_eewr = FALSE; 6415 break; 6416 case em_ich8lan: 6417 case em_ich9lan: 6418 case em_ich10lan: 6419 case em_pchlan: 6420 case em_pch2lan: 6421 case em_pch_lpt: 6422 { 6423 int32_t i = 0; 6424 uint32_t flash_size = 6425 E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_GFPREG); 6426 eeprom->type = em_eeprom_ich8; 6427 eeprom->use_eerd = FALSE; 6428 eeprom->use_eewr = FALSE; 6429 eeprom->word_size = E1000_SHADOW_RAM_WORDS; 6430 /* 6431 * Zero the shadow RAM structure. But don't load it 6432 * from NVM so as to save time for driver init 6433 */ 6434 if (hw->eeprom_shadow_ram != NULL) { 6435 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 6436 hw->eeprom_shadow_ram[i].modified = 6437 FALSE; 6438 hw->eeprom_shadow_ram[i].eeprom_word = 6439 0xFFFF; 6440 } 6441 } 6442 hw->flash_base_addr = (flash_size & 6443 ICH_GFPREG_BASE_MASK) * ICH_FLASH_SECTOR_SIZE; 6444 6445 hw->flash_bank_size = ((flash_size >> 16) & 6446 ICH_GFPREG_BASE_MASK) + 1; 6447 hw->flash_bank_size -= (flash_size & 6448 ICH_GFPREG_BASE_MASK); 6449 6450 hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE; 6451 6452 hw->flash_bank_size /= 2 * sizeof(uint16_t); 6453 6454 break; 6455 } 6456 case em_pch_spt: 6457 case em_pch_cnp: 6458 case em_pch_tgp: 6459 case em_pch_adp: 6460 { 6461 int32_t i = 0; 6462 uint32_t flash_size = EM_READ_REG(hw, 0xc /* STRAP */); 6463 6464 eeprom->type = em_eeprom_ich8; 6465 eeprom->use_eerd = FALSE; 6466 eeprom->use_eewr = FALSE; 6467 eeprom->word_size = E1000_SHADOW_RAM_WORDS; 6468 /* 6469 * Zero the shadow RAM structure. But don't load it 6470 * from NVM so as to save time for driver init 6471 */ 6472 if (hw->eeprom_shadow_ram != NULL) { 6473 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 6474 hw->eeprom_shadow_ram[i].modified = 6475 FALSE; 6476 hw->eeprom_shadow_ram[i].eeprom_word = 6477 0xFFFF; 6478 } 6479 } 6480 hw->flash_base_addr = 0; 6481 flash_size = ((flash_size >> 1) & 0x1f) + 1; 6482 flash_size *= 4096; 6483 hw->flash_bank_size = flash_size / 4; 6484 } 6485 break; 6486 default: 6487 break; 6488 } 6489 6490 if (eeprom->type == em_eeprom_spi) { 6491 /* 6492 * eeprom_size will be an enum [0..8] that maps to eeprom 6493 * sizes 128B to 32KB (incremented by powers of 2). 6494 */ 6495 if (hw->mac_type <= em_82547_rev_2) { 6496 /* Set to default value for initial eeprom read. */ 6497 eeprom->word_size = 64; 6498 ret_val = em_read_eeprom(hw, EEPROM_CFG, 1, 6499 &eeprom_size); 6500 if (ret_val) 6501 return ret_val; 6502 eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> 6503 EEPROM_SIZE_SHIFT; 6504 /* 6505 * 256B eeprom size was not supported in earlier 6506 * hardware, so we bump eeprom_size up one to ensure 6507 * that "1" (which maps to 256B) is never the result 6508 * used in the shifting logic below. 6509 */ 6510 if (eeprom_size) 6511 eeprom_size++; 6512 } else { 6513 eeprom_size = (uint16_t) ( 6514 (eecd & E1000_EECD_SIZE_EX_MASK) >> 6515 E1000_EECD_SIZE_EX_SHIFT); 6516 } 6517 6518 /* EEPROM access above 16k is unsupported */ 6519 if (eeprom_size + EEPROM_WORD_SIZE_SHIFT > 6520 EEPROM_WORD_SIZE_SHIFT_MAX) { 6521 eeprom->word_size = 1 << EEPROM_WORD_SIZE_SHIFT_MAX; 6522 } else { 6523 eeprom->word_size = 1 << 6524 (eeprom_size + EEPROM_WORD_SIZE_SHIFT); 6525 } 6526 } 6527 return ret_val; 6528 } 6529 6530 /****************************************************************************** 6531 * Raises the EEPROM's clock input. 6532 * 6533 * hw - Struct containing variables accessed by shared code 6534 * eecd - EECD's current value 6535 *****************************************************************************/ 6536 static void 6537 em_raise_ee_clk(struct em_hw *hw, uint32_t *eecd) 6538 { 6539 /* 6540 * Raise the clock input to the EEPROM (by setting the SK bit), and 6541 * then wait <delay> microseconds. 6542 */ 6543 *eecd = *eecd | E1000_EECD_SK; 6544 E1000_WRITE_REG(hw, EECD, *eecd); 6545 E1000_WRITE_FLUSH(hw); 6546 usec_delay(hw->eeprom.delay_usec); 6547 } 6548 6549 /****************************************************************************** 6550 * Lowers the EEPROM's clock input. 6551 * 6552 * hw - Struct containing variables accessed by shared code 6553 * eecd - EECD's current value 6554 *****************************************************************************/ 6555 static void 6556 em_lower_ee_clk(struct em_hw *hw, uint32_t *eecd) 6557 { 6558 /* 6559 * Lower the clock input to the EEPROM (by clearing the SK bit), and 6560 * then wait 50 microseconds. 6561 */ 6562 *eecd = *eecd & ~E1000_EECD_SK; 6563 E1000_WRITE_REG(hw, EECD, *eecd); 6564 E1000_WRITE_FLUSH(hw); 6565 usec_delay(hw->eeprom.delay_usec); 6566 } 6567 6568 /****************************************************************************** 6569 * Shift data bits out to the EEPROM. 6570 * 6571 * hw - Struct containing variables accessed by shared code 6572 * data - data to send to the EEPROM 6573 * count - number of bits to shift out 6574 *****************************************************************************/ 6575 static void 6576 em_shift_out_ee_bits(struct em_hw *hw, uint16_t data, uint16_t count) 6577 { 6578 struct em_eeprom_info *eeprom = &hw->eeprom; 6579 uint32_t eecd; 6580 uint32_t mask; 6581 /* 6582 * We need to shift "count" bits out to the EEPROM. So, value in the 6583 * "data" parameter will be shifted out to the EEPROM one bit at a 6584 * time. In order to do this, "data" must be broken down into bits. 6585 */ 6586 mask = 0x01 << (count - 1); 6587 eecd = E1000_READ_REG(hw, EECD); 6588 if (eeprom->type == em_eeprom_microwire) { 6589 eecd &= ~E1000_EECD_DO; 6590 } else if (eeprom->type == em_eeprom_spi) { 6591 eecd |= E1000_EECD_DO; 6592 } 6593 do { 6594 /* 6595 * A "1" is shifted out to the EEPROM by setting bit "DI" to 6596 * a "1", and then raising and then lowering the clock (the 6597 * SK bit controls the clock input to the EEPROM). A "0" is 6598 * shifted out to the EEPROM by setting "DI" to "0" and then 6599 * raising and then lowering the clock. 6600 */ 6601 eecd &= ~E1000_EECD_DI; 6602 6603 if (data & mask) 6604 eecd |= E1000_EECD_DI; 6605 6606 E1000_WRITE_REG(hw, EECD, eecd); 6607 E1000_WRITE_FLUSH(hw); 6608 6609 usec_delay(eeprom->delay_usec); 6610 6611 em_raise_ee_clk(hw, &eecd); 6612 em_lower_ee_clk(hw, &eecd); 6613 6614 mask = mask >> 1; 6615 6616 } while (mask); 6617 6618 /* We leave the "DI" bit set to "0" when we leave this routine. */ 6619 eecd &= ~E1000_EECD_DI; 6620 E1000_WRITE_REG(hw, EECD, eecd); 6621 } 6622 6623 /****************************************************************************** 6624 * Shift data bits in from the EEPROM 6625 * 6626 * hw - Struct containing variables accessed by shared code 6627 *****************************************************************************/ 6628 static uint16_t 6629 em_shift_in_ee_bits(struct em_hw *hw, uint16_t count) 6630 { 6631 uint32_t eecd; 6632 uint32_t i; 6633 uint16_t data; 6634 /* 6635 * In order to read a register from the EEPROM, we need to shift 6636 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising 6637 * the clock input to the EEPROM (setting the SK bit), and then 6638 * reading the value of the "DO" bit. During this "shifting in" 6639 * process the "DI" bit should always be clear. 6640 */ 6641 6642 eecd = E1000_READ_REG(hw, EECD); 6643 6644 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 6645 data = 0; 6646 6647 for (i = 0; i < count; i++) { 6648 data = data << 1; 6649 em_raise_ee_clk(hw, &eecd); 6650 6651 eecd = E1000_READ_REG(hw, EECD); 6652 6653 eecd &= ~(E1000_EECD_DI); 6654 if (eecd & E1000_EECD_DO) 6655 data |= 1; 6656 6657 em_lower_ee_clk(hw, &eecd); 6658 } 6659 6660 return data; 6661 } 6662 /****************************************************************************** 6663 * Prepares EEPROM for access 6664 * 6665 * hw - Struct containing variables accessed by shared code 6666 * 6667 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This 6668 * function should be called before issuing a command to the EEPROM. 6669 *****************************************************************************/ 6670 static int32_t 6671 em_acquire_eeprom(struct em_hw *hw) 6672 { 6673 struct em_eeprom_info *eeprom = &hw->eeprom; 6674 uint32_t eecd, i = 0; 6675 DEBUGFUNC("em_acquire_eeprom"); 6676 6677 if (em_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM)) 6678 return -E1000_ERR_SWFW_SYNC; 6679 eecd = E1000_READ_REG(hw, EECD); 6680 6681 if ((hw->mac_type != em_82573) && (hw->mac_type != em_82574)) { 6682 /* Request EEPROM Access */ 6683 if (hw->mac_type > em_82544) { 6684 eecd |= E1000_EECD_REQ; 6685 E1000_WRITE_REG(hw, EECD, eecd); 6686 eecd = E1000_READ_REG(hw, EECD); 6687 while ((!(eecd & E1000_EECD_GNT)) && 6688 (i < E1000_EEPROM_GRANT_ATTEMPTS)) { 6689 i++; 6690 usec_delay(5); 6691 eecd = E1000_READ_REG(hw, EECD); 6692 } 6693 if (!(eecd & E1000_EECD_GNT)) { 6694 eecd &= ~E1000_EECD_REQ; 6695 E1000_WRITE_REG(hw, EECD, eecd); 6696 DEBUGOUT("Could not acquire EEPROM grant\n"); 6697 em_swfw_sync_release(hw, E1000_SWFW_EEP_SM); 6698 return -E1000_ERR_EEPROM; 6699 } 6700 } 6701 } 6702 6703 /* Setup EEPROM for Read/Write */ 6704 if (eeprom->type == em_eeprom_microwire) { 6705 /* Clear SK and DI */ 6706 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK); 6707 E1000_WRITE_REG(hw, EECD, eecd); 6708 6709 /* Set CS */ 6710 eecd |= E1000_EECD_CS; 6711 E1000_WRITE_REG(hw, EECD, eecd); 6712 } else if (eeprom->type == em_eeprom_spi) { 6713 /* Clear SK and CS */ 6714 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 6715 E1000_WRITE_REG(hw, EECD, eecd); 6716 usec_delay(1); 6717 } 6718 return E1000_SUCCESS; 6719 } 6720 6721 /****************************************************************************** 6722 * Returns EEPROM to a "standby" state 6723 * 6724 * hw - Struct containing variables accessed by shared code 6725 *****************************************************************************/ 6726 static void 6727 em_standby_eeprom(struct em_hw *hw) 6728 { 6729 struct em_eeprom_info *eeprom = &hw->eeprom; 6730 uint32_t eecd; 6731 eecd = E1000_READ_REG(hw, EECD); 6732 6733 if (eeprom->type == em_eeprom_microwire) { 6734 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 6735 E1000_WRITE_REG(hw, EECD, eecd); 6736 E1000_WRITE_FLUSH(hw); 6737 usec_delay(eeprom->delay_usec); 6738 6739 /* Clock high */ 6740 eecd |= E1000_EECD_SK; 6741 E1000_WRITE_REG(hw, EECD, eecd); 6742 E1000_WRITE_FLUSH(hw); 6743 usec_delay(eeprom->delay_usec); 6744 6745 /* Select EEPROM */ 6746 eecd |= E1000_EECD_CS; 6747 E1000_WRITE_REG(hw, EECD, eecd); 6748 E1000_WRITE_FLUSH(hw); 6749 usec_delay(eeprom->delay_usec); 6750 6751 /* Clock low */ 6752 eecd &= ~E1000_EECD_SK; 6753 E1000_WRITE_REG(hw, EECD, eecd); 6754 E1000_WRITE_FLUSH(hw); 6755 usec_delay(eeprom->delay_usec); 6756 } else if (eeprom->type == em_eeprom_spi) { 6757 /* Toggle CS to flush commands */ 6758 eecd |= E1000_EECD_CS; 6759 E1000_WRITE_REG(hw, EECD, eecd); 6760 E1000_WRITE_FLUSH(hw); 6761 usec_delay(eeprom->delay_usec); 6762 eecd &= ~E1000_EECD_CS; 6763 E1000_WRITE_REG(hw, EECD, eecd); 6764 E1000_WRITE_FLUSH(hw); 6765 usec_delay(eeprom->delay_usec); 6766 } 6767 } 6768 6769 /****************************************************************************** 6770 * Terminates a command by inverting the EEPROM's chip select pin 6771 * 6772 * hw - Struct containing variables accessed by shared code 6773 *****************************************************************************/ 6774 static void 6775 em_release_eeprom(struct em_hw *hw) 6776 { 6777 uint32_t eecd; 6778 DEBUGFUNC("em_release_eeprom"); 6779 6780 eecd = E1000_READ_REG(hw, EECD); 6781 6782 if (hw->eeprom.type == em_eeprom_spi) { 6783 eecd |= E1000_EECD_CS; /* Pull CS high */ 6784 eecd &= ~E1000_EECD_SK; /* Lower SCK */ 6785 6786 E1000_WRITE_REG(hw, EECD, eecd); 6787 6788 usec_delay(hw->eeprom.delay_usec); 6789 } else if (hw->eeprom.type == em_eeprom_microwire) { 6790 /* cleanup eeprom */ 6791 6792 /* CS on Microwire is active-high */ 6793 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); 6794 6795 E1000_WRITE_REG(hw, EECD, eecd); 6796 6797 /* Rising edge of clock */ 6798 eecd |= E1000_EECD_SK; 6799 E1000_WRITE_REG(hw, EECD, eecd); 6800 E1000_WRITE_FLUSH(hw); 6801 usec_delay(hw->eeprom.delay_usec); 6802 6803 /* Falling edge of clock */ 6804 eecd &= ~E1000_EECD_SK; 6805 E1000_WRITE_REG(hw, EECD, eecd); 6806 E1000_WRITE_FLUSH(hw); 6807 usec_delay(hw->eeprom.delay_usec); 6808 } 6809 /* Stop requesting EEPROM access */ 6810 if (hw->mac_type > em_82544) { 6811 eecd &= ~E1000_EECD_REQ; 6812 E1000_WRITE_REG(hw, EECD, eecd); 6813 } 6814 em_swfw_sync_release(hw, E1000_SWFW_EEP_SM); 6815 } 6816 6817 /****************************************************************************** 6818 * Reads a 16 bit word from the EEPROM. 6819 * 6820 * hw - Struct containing variables accessed by shared code 6821 *****************************************************************************/ 6822 STATIC int32_t 6823 em_spi_eeprom_ready(struct em_hw *hw) 6824 { 6825 uint16_t retry_count = 0; 6826 uint8_t spi_stat_reg; 6827 DEBUGFUNC("em_spi_eeprom_ready"); 6828 /* 6829 * Read "Status Register" repeatedly until the LSB is cleared. The 6830 * EEPROM will signal that the command has been completed by clearing 6831 * bit 0 of the internal status register. If it's not cleared within 6832 * 5 milliseconds, then error out. 6833 */ 6834 retry_count = 0; 6835 do { 6836 em_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI, 6837 hw->eeprom.opcode_bits); 6838 spi_stat_reg = (uint8_t) em_shift_in_ee_bits(hw, 8); 6839 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI)) 6840 break; 6841 6842 usec_delay(5); 6843 retry_count += 5; 6844 6845 em_standby_eeprom(hw); 6846 } while (retry_count < EEPROM_MAX_RETRY_SPI); 6847 /* 6848 * ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and 6849 * only 0-5mSec on 5V devices) 6850 */ 6851 if (retry_count >= EEPROM_MAX_RETRY_SPI) { 6852 DEBUGOUT("SPI EEPROM Status error\n"); 6853 return -E1000_ERR_EEPROM; 6854 } 6855 return E1000_SUCCESS; 6856 } 6857 6858 /****************************************************************************** 6859 * Reads a 16 bit word from the EEPROM. 6860 * 6861 * hw - Struct containing variables accessed by shared code 6862 * offset - offset of word in the EEPROM to read 6863 * data - word read from the EEPROM 6864 * words - number of words to read 6865 *****************************************************************************/ 6866 int32_t 6867 em_read_eeprom(struct em_hw *hw, uint16_t offset, uint16_t words, 6868 uint16_t *data) 6869 { 6870 struct em_eeprom_info *eeprom = &hw->eeprom; 6871 uint32_t i = 0; 6872 DEBUGFUNC("em_read_eeprom"); 6873 6874 /* If eeprom is not yet detected, do so now */ 6875 if (eeprom->word_size == 0) 6876 em_init_eeprom_params(hw); 6877 /* 6878 * A check for invalid values: offset too large, too many words, and 6879 * not enough words. 6880 */ 6881 if ((offset >= eeprom->word_size) || 6882 (words > eeprom->word_size - offset) || 6883 (words == 0)) { 6884 DEBUGOUT2("\"words\" parameter out of bounds. Words = %d," 6885 " size = %d\n", offset, eeprom->word_size); 6886 return -E1000_ERR_EEPROM; 6887 } 6888 /* 6889 * EEPROM's that don't use EERD to read require us to bit-bang the 6890 * SPI directly. In this case, we need to acquire the EEPROM so that 6891 * FW or other port software does not interrupt. 6892 */ 6893 if (em_is_onboard_nvm_eeprom(hw) == TRUE && 6894 em_get_flash_presence_i210(hw) == TRUE && 6895 hw->eeprom.use_eerd == FALSE) { 6896 /* Prepare the EEPROM for bit-bang reading */ 6897 if (em_acquire_eeprom(hw) != E1000_SUCCESS) 6898 return -E1000_ERR_EEPROM; 6899 } 6900 /* Eerd register EEPROM access requires no eeprom acquire/release */ 6901 if (eeprom->use_eerd == TRUE) 6902 return em_read_eeprom_eerd(hw, offset, words, data); 6903 6904 /* ICH EEPROM access is done via the ICH flash controller */ 6905 if (eeprom->type == em_eeprom_ich8) 6906 return em_read_eeprom_ich8(hw, offset, words, data); 6907 6908 /* Some i210/i211 have a special OTP chip */ 6909 if (eeprom->type == em_eeprom_invm) 6910 return em_read_invm_i210(hw, offset, words, data); 6911 6912 /* 6913 * Set up the SPI or Microwire EEPROM for bit-bang reading. We have 6914 * acquired the EEPROM at this point, so any returns should release it 6915 */ 6916 if (eeprom->type == em_eeprom_spi) { 6917 uint16_t word_in; 6918 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI; 6919 if (em_spi_eeprom_ready(hw)) { 6920 em_release_eeprom(hw); 6921 return -E1000_ERR_EEPROM; 6922 } 6923 em_standby_eeprom(hw); 6924 /* 6925 * Some SPI eeproms use the 8th address bit embedded in the 6926 * opcode 6927 */ 6928 if ((eeprom->address_bits == 8) && (offset >= 128)) 6929 read_opcode |= EEPROM_A8_OPCODE_SPI; 6930 6931 /* Send the READ command (opcode + addr) */ 6932 em_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits); 6933 em_shift_out_ee_bits(hw, (uint16_t) (offset * 2), 6934 eeprom->address_bits); 6935 /* 6936 * Read the data. The address of the eeprom internally 6937 * increments with each byte (spi) being read, saving on the 6938 * overhead of eeprom setup and tear-down. The address 6939 * counter will roll over if reading beyond the size of the 6940 * eeprom, thus allowing the entire memory to be read 6941 * starting from any offset. 6942 */ 6943 for (i = 0; i < words; i++) { 6944 word_in = em_shift_in_ee_bits(hw, 16); 6945 data[i] = (word_in >> 8) | (word_in << 8); 6946 } 6947 } else if (eeprom->type == em_eeprom_microwire) { 6948 for (i = 0; i < words; i++) { 6949 /* Send the READ command (opcode + addr) */ 6950 em_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE, 6951 eeprom->opcode_bits); 6952 em_shift_out_ee_bits(hw, (uint16_t) (offset + i), 6953 eeprom->address_bits); 6954 /* 6955 * Read the data. For microwire, each word requires 6956 * the overhead of eeprom setup and tear-down. 6957 */ 6958 data[i] = em_shift_in_ee_bits(hw, 16); 6959 em_standby_eeprom(hw); 6960 } 6961 } 6962 /* End this read operation */ 6963 em_release_eeprom(hw); 6964 6965 return E1000_SUCCESS; 6966 } 6967 6968 /****************************************************************************** 6969 * Reads a 16 bit word from the EEPROM using the EERD register. 6970 * 6971 * hw - Struct containing variables accessed by shared code 6972 * offset - offset of word in the EEPROM to read 6973 * data - word read from the EEPROM 6974 * words - number of words to read 6975 *****************************************************************************/ 6976 STATIC int32_t 6977 em_read_eeprom_eerd(struct em_hw *hw, uint16_t offset, uint16_t words, 6978 uint16_t *data) 6979 { 6980 uint32_t i, eerd = 0; 6981 int32_t error = 0; 6982 for (i = 0; i < words; i++) { 6983 eerd = ((offset + i) << E1000_EEPROM_RW_ADDR_SHIFT) + 6984 E1000_EEPROM_RW_REG_START; 6985 6986 E1000_WRITE_REG(hw, EERD, eerd); 6987 error = em_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ); 6988 6989 if (error) { 6990 break; 6991 } 6992 data[i] = (E1000_READ_REG(hw, EERD) >> 6993 E1000_EEPROM_RW_REG_DATA); 6994 6995 } 6996 6997 return error; 6998 } 6999 7000 /****************************************************************************** 7001 * Writes a 16 bit word from the EEPROM using the EEWR register. 7002 * 7003 * hw - Struct containing variables accessed by shared code 7004 * offset - offset of word in the EEPROM to read 7005 * data - word read from the EEPROM 7006 * words - number of words to read 7007 *****************************************************************************/ 7008 STATIC int32_t 7009 em_write_eeprom_eewr(struct em_hw *hw, uint16_t offset, uint16_t words, 7010 uint16_t *data) 7011 { 7012 uint32_t register_value = 0; 7013 uint32_t i = 0; 7014 int32_t error = 0; 7015 if (em_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM)) 7016 return -E1000_ERR_SWFW_SYNC; 7017 7018 for (i = 0; i < words; i++) { 7019 register_value = (data[i] << E1000_EEPROM_RW_REG_DATA) | 7020 ((offset + i) << E1000_EEPROM_RW_ADDR_SHIFT) | 7021 E1000_EEPROM_RW_REG_START; 7022 7023 error = em_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE); 7024 if (error) { 7025 break; 7026 } 7027 E1000_WRITE_REG(hw, EEWR, register_value); 7028 7029 error = em_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE); 7030 7031 if (error) { 7032 break; 7033 } 7034 } 7035 7036 em_swfw_sync_release(hw, E1000_SWFW_EEP_SM); 7037 return error; 7038 } 7039 7040 /****************************************************************************** 7041 * Polls the status bit (bit 1) of the EERD to determine when the read is done. 7042 * 7043 * hw - Struct containing variables accessed by shared code 7044 *****************************************************************************/ 7045 STATIC int32_t 7046 em_poll_eerd_eewr_done(struct em_hw *hw, int eerd) 7047 { 7048 uint32_t attempts = 100000; 7049 uint32_t i, reg = 0; 7050 int32_t done = E1000_ERR_EEPROM; 7051 for (i = 0; i < attempts; i++) { 7052 if (eerd == E1000_EEPROM_POLL_READ) 7053 reg = E1000_READ_REG(hw, EERD); 7054 else 7055 reg = E1000_READ_REG(hw, EEWR); 7056 7057 if (reg & E1000_EEPROM_RW_REG_DONE) { 7058 done = E1000_SUCCESS; 7059 break; 7060 } 7061 usec_delay(5); 7062 } 7063 7064 return done; 7065 } 7066 7067 /****************************************************************************** 7068 * Description: Determines if the onboard NVM is FLASH or EEPROM. 7069 * 7070 * hw - Struct containing variables accessed by shared code 7071 *****************************************************************************/ 7072 STATIC boolean_t 7073 em_is_onboard_nvm_eeprom(struct em_hw *hw) 7074 { 7075 uint32_t eecd = 0; 7076 DEBUGFUNC("em_is_onboard_nvm_eeprom"); 7077 7078 if (IS_ICH8(hw->mac_type)) 7079 return FALSE; 7080 7081 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) { 7082 eecd = E1000_READ_REG(hw, EECD); 7083 7084 /* Isolate bits 15 & 16 */ 7085 eecd = ((eecd >> 15) & 0x03); 7086 7087 /* If both bits are set, device is Flash type */ 7088 if (eecd == 0x03) { 7089 return FALSE; 7090 } 7091 } 7092 return TRUE; 7093 } 7094 7095 /****************************************************************************** 7096 * Check if flash device is detected. 7097 * 7098 * hw - Struct containing variables accessed by shared code 7099 *****************************************************************************/ 7100 boolean_t 7101 em_get_flash_presence_i210(struct em_hw *hw) 7102 { 7103 uint32_t eecd; 7104 DEBUGFUNC("em_get_flash_presence_i210"); 7105 7106 if (hw->mac_type != em_i210) 7107 return TRUE; 7108 7109 eecd = E1000_READ_REG(hw, EECD); 7110 7111 if (eecd & E1000_EECD_FLUPD) 7112 return TRUE; 7113 7114 return FALSE; 7115 } 7116 7117 /****************************************************************************** 7118 * Verifies that the EEPROM has a valid checksum 7119 * 7120 * hw - Struct containing variables accessed by shared code 7121 * 7122 * Reads the first 64 16 bit words of the EEPROM and sums the values read. 7123 * If the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is 7124 * valid. 7125 *****************************************************************************/ 7126 int32_t 7127 em_validate_eeprom_checksum(struct em_hw *hw) 7128 { 7129 uint16_t checksum = 0; 7130 uint16_t i, eeprom_data; 7131 uint16_t checksum_reg; 7132 DEBUGFUNC("em_validate_eeprom_checksum"); 7133 7134 checksum_reg = hw->mac_type != em_icp_xxxx ? 7135 EEPROM_CHECKSUM_REG : 7136 EEPROM_CHECKSUM_REG_ICP_xxxx; 7137 7138 if (((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) && 7139 (em_is_onboard_nvm_eeprom(hw) == FALSE)) { 7140 /* 7141 * Check bit 4 of word 10h. If it is 0, firmware is done 7142 * updating 10h-12h. Checksum may need to be fixed. 7143 */ 7144 em_read_eeprom(hw, 0x10, 1, &eeprom_data); 7145 if ((eeprom_data & 0x10) == 0) { 7146 /* 7147 * Read 0x23 and check bit 15. This bit is a 1 when 7148 * the checksum has already been fixed. If the 7149 * checksum is still wrong and this bit is a 1, we 7150 * need to return bad checksum. Otherwise, we need 7151 * to set this bit to a 1 and update the checksum. 7152 */ 7153 em_read_eeprom(hw, 0x23, 1, &eeprom_data); 7154 if ((eeprom_data & 0x8000) == 0) { 7155 eeprom_data |= 0x8000; 7156 em_write_eeprom(hw, 0x23, 1, &eeprom_data); 7157 em_update_eeprom_checksum(hw); 7158 } 7159 } 7160 } 7161 if (IS_ICH8(hw->mac_type)) { 7162 uint16_t word; 7163 uint16_t valid_csum_mask; 7164 7165 /* 7166 * Drivers must allocate the shadow ram structure for the 7167 * EEPROM checksum to be updated. Otherwise, this bit as 7168 * well as the checksum must both be set correctly for this 7169 * validation to pass. 7170 */ 7171 switch (hw->mac_type) { 7172 case em_pch_lpt: 7173 case em_pch_spt: 7174 case em_pch_cnp: 7175 case em_pch_tgp: 7176 case em_pch_adp: 7177 word = EEPROM_COMPAT; 7178 valid_csum_mask = EEPROM_COMPAT_VALID_CSUM; 7179 break; 7180 default: 7181 word = EEPROM_FUTURE_INIT_WORD1; 7182 valid_csum_mask = EEPROM_FUTURE_INIT_WORD1_VALID_CSUM; 7183 break; 7184 } 7185 em_read_eeprom(hw, word, 1, &eeprom_data); 7186 if ((eeprom_data & valid_csum_mask) == 0) { 7187 eeprom_data |= valid_csum_mask; 7188 em_write_eeprom(hw, word, 1, &eeprom_data); 7189 em_update_eeprom_checksum(hw); 7190 } 7191 } 7192 for (i = 0; i < (checksum_reg + 1); i++) { 7193 if (em_read_eeprom(hw, i, 1, &eeprom_data) < 0) { 7194 DEBUGOUT("EEPROM Read Error\n"); 7195 return -E1000_ERR_EEPROM; 7196 } 7197 checksum += eeprom_data; 7198 } 7199 7200 if (checksum == (uint16_t) EEPROM_SUM) 7201 return E1000_SUCCESS; 7202 else { 7203 DEBUGOUT("EEPROM Checksum Invalid\n"); 7204 return -E1000_ERR_EEPROM; 7205 } 7206 } 7207 7208 /****************************************************************************** 7209 * Calculates the EEPROM checksum and writes it to the EEPROM 7210 * 7211 * hw - Struct containing variables accessed by shared code 7212 * 7213 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA. 7214 * Writes the difference to word offset 63 of the EEPROM. 7215 *****************************************************************************/ 7216 int32_t 7217 em_update_eeprom_checksum(struct em_hw *hw) 7218 { 7219 uint32_t ctrl_ext; 7220 uint16_t checksum = 0; 7221 uint16_t i, eeprom_data; 7222 DEBUGFUNC("em_update_eeprom_checksum"); 7223 7224 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) { 7225 if (em_read_eeprom(hw, i, 1, &eeprom_data) < 0) { 7226 DEBUGOUT("EEPROM Read Error\n"); 7227 return -E1000_ERR_EEPROM; 7228 } 7229 checksum += eeprom_data; 7230 } 7231 checksum = (uint16_t) EEPROM_SUM - checksum; 7232 if (em_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) { 7233 DEBUGOUT("EEPROM Write Error\n"); 7234 return -E1000_ERR_EEPROM; 7235 } else if (hw->eeprom.type == em_eeprom_flash) { 7236 em_commit_shadow_ram(hw); 7237 } else if (hw->eeprom.type == em_eeprom_ich8) { 7238 em_commit_shadow_ram(hw); 7239 /* 7240 * Reload the EEPROM, or else modifications will not appear 7241 * until after next adapter reset. 7242 */ 7243 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 7244 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 7245 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 7246 msec_delay(10); 7247 } 7248 return E1000_SUCCESS; 7249 } 7250 7251 /****************************************************************************** 7252 * Parent function for writing words to the different EEPROM types. 7253 * 7254 * hw - Struct containing variables accessed by shared code 7255 * offset - offset within the EEPROM to be written to 7256 * words - number of words to write 7257 * data - 16 bit word to be written to the EEPROM 7258 * 7259 * If em_update_eeprom_checksum is not called after this function, the 7260 * EEPROM will most likely contain an invalid checksum. 7261 *****************************************************************************/ 7262 int32_t 7263 em_write_eeprom(struct em_hw *hw, uint16_t offset, uint16_t words, 7264 uint16_t *data) 7265 { 7266 struct em_eeprom_info *eeprom = &hw->eeprom; 7267 int32_t status = 0; 7268 DEBUGFUNC("em_write_eeprom"); 7269 7270 /* If eeprom is not yet detected, do so now */ 7271 if (eeprom->word_size == 0) 7272 em_init_eeprom_params(hw); 7273 /* 7274 * A check for invalid values: offset too large, too many words, and 7275 * not enough words. 7276 */ 7277 if ((offset >= eeprom->word_size) || 7278 (words > eeprom->word_size - offset) || 7279 (words == 0)) { 7280 DEBUGOUT("\"words\" parameter out of bounds\n"); 7281 return -E1000_ERR_EEPROM; 7282 } 7283 /* 82573/4 writes only through eewr */ 7284 if (eeprom->use_eewr == TRUE) 7285 return em_write_eeprom_eewr(hw, offset, words, data); 7286 7287 if (eeprom->type == em_eeprom_ich8) 7288 return em_write_eeprom_ich8(hw, offset, words, data); 7289 7290 /* Prepare the EEPROM for writing */ 7291 if (em_acquire_eeprom(hw) != E1000_SUCCESS) 7292 return -E1000_ERR_EEPROM; 7293 7294 if (eeprom->type == em_eeprom_microwire) { 7295 status = em_write_eeprom_microwire(hw, offset, words, data); 7296 } else { 7297 status = em_write_eeprom_spi(hw, offset, words, data); 7298 msec_delay(10); 7299 } 7300 7301 /* Done with writing */ 7302 em_release_eeprom(hw); 7303 7304 return status; 7305 } 7306 7307 /****************************************************************************** 7308 * Writes a 16 bit word to a given offset in an SPI EEPROM. 7309 * 7310 * hw - Struct containing variables accessed by shared code 7311 * offset - offset within the EEPROM to be written to 7312 * words - number of words to write 7313 * data - pointer to array of 8 bit words to be written to the EEPROM 7314 * 7315 *****************************************************************************/ 7316 STATIC int32_t 7317 em_write_eeprom_spi(struct em_hw *hw, uint16_t offset, uint16_t words, 7318 uint16_t *data) 7319 { 7320 struct em_eeprom_info *eeprom = &hw->eeprom; 7321 uint16_t widx = 0; 7322 DEBUGFUNC("em_write_eeprom_spi"); 7323 7324 while (widx < words) { 7325 uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI; 7326 if (em_spi_eeprom_ready(hw)) 7327 return -E1000_ERR_EEPROM; 7328 7329 em_standby_eeprom(hw); 7330 7331 /* Send the WRITE ENABLE command (8 bit opcode ) */ 7332 em_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI, 7333 eeprom->opcode_bits); 7334 7335 em_standby_eeprom(hw); 7336 /* 7337 * Some SPI eeproms use the 8th address bit embedded in the 7338 * opcode 7339 */ 7340 if ((eeprom->address_bits == 8) && (offset >= 128)) 7341 write_opcode |= EEPROM_A8_OPCODE_SPI; 7342 7343 /* Send the Write command (8-bit opcode + addr) */ 7344 em_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits); 7345 7346 em_shift_out_ee_bits(hw, (uint16_t) ((offset + widx) * 2), 7347 eeprom->address_bits); 7348 7349 /* Send the data */ 7350 /* 7351 * Loop to allow for up to whole page write (32 bytes) of 7352 * eeprom 7353 */ 7354 while (widx < words) { 7355 uint16_t word_out = data[widx]; 7356 word_out = (word_out >> 8) | (word_out << 8); 7357 em_shift_out_ee_bits(hw, word_out, 16); 7358 widx++; 7359 /* 7360 * Some larger eeprom sizes are capable of a 32-byte 7361 * PAGE WRITE operation, while the smaller eeproms 7362 * are capable of an 8-byte PAGE WRITE operation. 7363 * Break the inner loop to pass new address 7364 */ 7365 if ((((offset + widx) * 2) % eeprom->page_size) == 0) { 7366 em_standby_eeprom(hw); 7367 break; 7368 } 7369 } 7370 } 7371 7372 return E1000_SUCCESS; 7373 } 7374 7375 /****************************************************************************** 7376 * Writes a 16 bit word to a given offset in a Microwire EEPROM. 7377 * 7378 * hw - Struct containing variables accessed by shared code 7379 * offset - offset within the EEPROM to be written to 7380 * words - number of words to write 7381 * data - pointer to array of 16 bit words to be written to the EEPROM 7382 * 7383 *****************************************************************************/ 7384 STATIC int32_t 7385 em_write_eeprom_microwire(struct em_hw *hw, uint16_t offset, uint16_t words, 7386 uint16_t *data) 7387 { 7388 struct em_eeprom_info *eeprom = &hw->eeprom; 7389 uint32_t eecd; 7390 uint16_t words_written = 0; 7391 uint16_t i = 0; 7392 DEBUGFUNC("em_write_eeprom_microwire"); 7393 /* 7394 * Send the write enable command to the EEPROM (3-bit opcode plus 7395 * 6/8-bit dummy address beginning with 11). It's less work to 7396 * include the 11 of the dummy address as part of the opcode than it 7397 * is to shift it over the correct number of bits for the address. 7398 * This puts the EEPROM into write/erase mode. 7399 */ 7400 em_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE, 7401 (uint16_t) (eeprom->opcode_bits + 2)); 7402 7403 em_shift_out_ee_bits(hw, 0, (uint16_t) (eeprom->address_bits - 2)); 7404 7405 /* Prepare the EEPROM */ 7406 em_standby_eeprom(hw); 7407 7408 while (words_written < words) { 7409 /* Send the Write command (3-bit opcode + addr) */ 7410 em_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE, 7411 eeprom->opcode_bits); 7412 7413 em_shift_out_ee_bits(hw, (uint16_t) (offset + words_written), 7414 eeprom->address_bits); 7415 7416 /* Send the data */ 7417 em_shift_out_ee_bits(hw, data[words_written], 16); 7418 /* 7419 * Toggle the CS line. This in effect tells the EEPROM to 7420 * execute the previous command. 7421 */ 7422 em_standby_eeprom(hw); 7423 /* 7424 * Read DO repeatedly until it is high (equal to '1'). The 7425 * EEPROM will signal that the command has been completed by 7426 * raising the DO signal. If DO does not go high in 10 7427 * milliseconds, then error out. 7428 */ 7429 for (i = 0; i < 200; i++) { 7430 eecd = E1000_READ_REG(hw, EECD); 7431 if (eecd & E1000_EECD_DO) 7432 break; 7433 usec_delay(50); 7434 } 7435 if (i == 200) { 7436 DEBUGOUT("EEPROM Write did not complete\n"); 7437 return -E1000_ERR_EEPROM; 7438 } 7439 /* Recover from write */ 7440 em_standby_eeprom(hw); 7441 7442 words_written++; 7443 } 7444 /* 7445 * Send the write disable command to the EEPROM (3-bit opcode plus 7446 * 6/8-bit dummy address beginning with 10). It's less work to 7447 * include the 10 of the dummy address as part of the opcode than it 7448 * is to shift it over the correct number of bits for the address. 7449 * This takes the EEPROM out of write/erase mode. 7450 */ 7451 em_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE, 7452 (uint16_t) (eeprom->opcode_bits + 2)); 7453 7454 em_shift_out_ee_bits(hw, 0, (uint16_t) (eeprom->address_bits - 2)); 7455 7456 return E1000_SUCCESS; 7457 } 7458 7459 /****************************************************************************** 7460 * Flushes the cached eeprom to NVM. This is done by saving the modified values 7461 * in the eeprom cache and the non modified values in the currently active bank 7462 * to the new bank. 7463 * 7464 * hw - Struct containing variables accessed by shared code 7465 * offset - offset of word in the EEPROM to read 7466 * data - word read from the EEPROM 7467 * words - number of words to read 7468 *****************************************************************************/ 7469 STATIC int32_t 7470 em_commit_shadow_ram(struct em_hw *hw) 7471 { 7472 uint32_t attempts = 100000; 7473 uint32_t eecd = 0; 7474 uint32_t flop = 0; 7475 uint32_t i = 0; 7476 int32_t error = E1000_SUCCESS; 7477 uint32_t old_bank_offset = 0; 7478 uint32_t new_bank_offset = 0; 7479 uint8_t low_byte = 0; 7480 uint8_t high_byte = 0; 7481 boolean_t sector_write_failed = FALSE; 7482 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) { 7483 /* 7484 * The flop register will be used to determine if flash type 7485 * is STM 7486 */ 7487 flop = E1000_READ_REG(hw, FLOP); 7488 for (i = 0; i < attempts; i++) { 7489 eecd = E1000_READ_REG(hw, EECD); 7490 if ((eecd & E1000_EECD_FLUPD) == 0) { 7491 break; 7492 } 7493 usec_delay(5); 7494 } 7495 7496 if (i == attempts) { 7497 return -E1000_ERR_EEPROM; 7498 } 7499 /* 7500 * If STM opcode located in bits 15:8 of flop, reset firmware 7501 */ 7502 if ((flop & 0xFF00) == E1000_STM_OPCODE) { 7503 E1000_WRITE_REG(hw, HICR, E1000_HICR_FW_RESET); 7504 } 7505 /* Perform the flash update */ 7506 E1000_WRITE_REG(hw, EECD, eecd | E1000_EECD_FLUPD); 7507 7508 for (i = 0; i < attempts; i++) { 7509 eecd = E1000_READ_REG(hw, EECD); 7510 if ((eecd & E1000_EECD_FLUPD) == 0) { 7511 break; 7512 } 7513 usec_delay(5); 7514 } 7515 7516 if (i == attempts) { 7517 return -E1000_ERR_EEPROM; 7518 } 7519 } 7520 if ((hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) && 7521 hw->eeprom_shadow_ram != NULL) { 7522 /* 7523 * We're writing to the opposite bank so if we're on bank 1, 7524 * write to bank 0 etc. We also need to erase the segment 7525 * that is going to be written 7526 */ 7527 if (!(E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL)) { 7528 new_bank_offset = hw->flash_bank_size * 2; 7529 old_bank_offset = 0; 7530 em_erase_ich8_4k_segment(hw, 1); 7531 } else { 7532 old_bank_offset = hw->flash_bank_size * 2; 7533 new_bank_offset = 0; 7534 em_erase_ich8_4k_segment(hw, 0); 7535 } 7536 7537 sector_write_failed = FALSE; 7538 /* 7539 * Loop for every byte in the shadow RAM, which is in units 7540 * of words. 7541 */ 7542 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 7543 /* 7544 * Determine whether to write the value stored in the 7545 * other NVM bank or a modified value stored in the 7546 * shadow RAM 7547 */ 7548 if (hw->eeprom_shadow_ram[i].modified == TRUE) { 7549 low_byte = (uint8_t) 7550 hw->eeprom_shadow_ram[i].eeprom_word; 7551 usec_delay(100); 7552 error = em_verify_write_ich8_byte(hw, 7553 (i << 1) + new_bank_offset, low_byte); 7554 7555 if (error != E1000_SUCCESS) 7556 sector_write_failed = TRUE; 7557 else { 7558 high_byte = (uint8_t) 7559 (hw->eeprom_shadow_ram 7560 [i].eeprom_word >> 8); 7561 usec_delay(100); 7562 } 7563 } else { 7564 em_read_ich8_byte(hw, (i << 1) + 7565 old_bank_offset, &low_byte); 7566 usec_delay(100); 7567 error = em_verify_write_ich8_byte(hw, 7568 (i << 1) + new_bank_offset, low_byte); 7569 7570 if (error != E1000_SUCCESS) 7571 sector_write_failed = TRUE; 7572 else { 7573 em_read_ich8_byte(hw, (i << 1) + 7574 old_bank_offset + 1, &high_byte); 7575 usec_delay(100); 7576 } 7577 } 7578 /* 7579 * If the write of the low byte was successful, go 7580 * ahread and write the high byte while checking to 7581 * make sure that if it is the signature byte, then 7582 * it is handled properly 7583 */ 7584 if (sector_write_failed == FALSE) { 7585 /* 7586 * If the word is 0x13, then make sure the 7587 * signature bits (15:14) are 11b until the 7588 * commit has completed. This will allow us 7589 * to write 10b which indicates the signature 7590 * is valid. We want to do this after the 7591 * write has completed so that we don't mark 7592 * the segment valid while the write is still 7593 * in progress 7594 */ 7595 if (i == E1000_ICH_NVM_SIG_WORD) 7596 high_byte = E1000_ICH_NVM_VALID_SIG_MASK | 7597 high_byte; 7598 7599 error = em_verify_write_ich8_byte(hw, (i << 1) 7600 + new_bank_offset + 1, high_byte); 7601 if (error != E1000_SUCCESS) 7602 sector_write_failed = TRUE; 7603 7604 } else { 7605 /* 7606 * If the write failed then break from the 7607 * loop and return an error 7608 */ 7609 break; 7610 } 7611 } 7612 /* 7613 * Don't bother writing the segment valid bits if sector 7614 * programming failed. 7615 */ 7616 if (sector_write_failed == FALSE) { 7617 /* 7618 * Finally validate the new segment by setting bit 7619 * 15:14 to 10b in word 0x13 , this can be done 7620 * without an erase as well since these bits are 11 7621 * to start with and we need to change bit 14 to 0b 7622 */ 7623 em_read_ich8_byte(hw, E1000_ICH_NVM_SIG_WORD * 2 + 1 + 7624 new_bank_offset, &high_byte); 7625 high_byte &= 0xBF; 7626 error = em_verify_write_ich8_byte(hw, 7627 E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset, 7628 high_byte); 7629 /* 7630 * And invalidate the previously valid segment by 7631 * setting its signature word (0x13) high_byte to 0b. 7632 * This can be done without an erase because flash 7633 * erase sets all bits to 1's. We can write 1's to 7634 * 0's without an erase 7635 */ 7636 if (error == E1000_SUCCESS) { 7637 error = em_verify_write_ich8_byte(hw, 7638 E1000_ICH_NVM_SIG_WORD * 2 + 1 + 7639 old_bank_offset, 0); 7640 } 7641 /* Clear the now not used entry in the cache */ 7642 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 7643 hw->eeprom_shadow_ram[i].modified = FALSE; 7644 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF; 7645 } 7646 } 7647 } 7648 return error; 7649 } 7650 7651 /****************************************************************************** 7652 * Reads the adapter's part number from the EEPROM 7653 * 7654 * hw - Struct containing variables accessed by shared code 7655 * part_num - Adapter's part number 7656 *****************************************************************************/ 7657 int32_t 7658 em_read_part_num(struct em_hw *hw, uint32_t *part_num) 7659 { 7660 uint16_t offset = EEPROM_PBA_BYTE_1; 7661 uint16_t eeprom_data; 7662 DEBUGFUNC("em_read_part_num"); 7663 7664 /* Get word 0 from EEPROM */ 7665 if (em_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { 7666 DEBUGOUT("EEPROM Read Error\n"); 7667 return -E1000_ERR_EEPROM; 7668 } 7669 /* Save word 0 in upper half of part_num */ 7670 *part_num = (uint32_t)eeprom_data << 16; 7671 7672 /* Get word 1 from EEPROM */ 7673 if (em_read_eeprom(hw, ++offset, 1, &eeprom_data) < 0) { 7674 DEBUGOUT("EEPROM Read Error\n"); 7675 return -E1000_ERR_EEPROM; 7676 } 7677 /* Save word 1 in lower half of part_num */ 7678 *part_num |= eeprom_data; 7679 7680 return E1000_SUCCESS; 7681 } 7682 7683 /****************************************************************************** 7684 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the 7685 * second function of dual function devices 7686 * 7687 * hw - Struct containing variables accessed by shared code 7688 *****************************************************************************/ 7689 int32_t 7690 em_read_mac_addr(struct em_hw *hw) 7691 { 7692 uint16_t offset; 7693 uint16_t eeprom_data, i; 7694 uint16_t ia_base_addr = 0; 7695 DEBUGFUNC("em_read_mac_addr"); 7696 7697 if (hw->mac_type == em_icp_xxxx) { 7698 ia_base_addr = (uint16_t) 7699 EEPROM_IA_START_ICP_xxxx(hw->icp_xxxx_port_num); 7700 } else if (hw->mac_type == em_82580 || hw->mac_type == em_i350) { 7701 ia_base_addr = NVM_82580_LAN_FUNC_OFFSET(hw->bus_func); 7702 } 7703 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) { 7704 offset = i >> 1; 7705 if (em_read_eeprom(hw, offset + ia_base_addr, 1, &eeprom_data) 7706 < 0) { 7707 DEBUGOUT("EEPROM Read Error\n"); 7708 return -E1000_ERR_EEPROM; 7709 } 7710 hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF); 7711 hw->perm_mac_addr[i + 1] = (uint8_t) (eeprom_data >> 8); 7712 } 7713 7714 switch (hw->mac_type) { 7715 default: 7716 break; 7717 case em_82546: 7718 case em_82546_rev_3: 7719 case em_82571: 7720 case em_82575: 7721 case em_82576: 7722 case em_80003es2lan: 7723 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) 7724 hw->perm_mac_addr[5] ^= 0x01; 7725 break; 7726 } 7727 7728 for (i = 0; i < NODE_ADDRESS_SIZE; i++) 7729 hw->mac_addr[i] = hw->perm_mac_addr[i]; 7730 return E1000_SUCCESS; 7731 } 7732 7733 /****************************************************************************** 7734 * Explicitly disables jumbo frames and resets some PHY registers back to hw- 7735 * defaults. This is necessary in case the ethernet cable was inserted AFTER 7736 * the firmware initialized the PHY. Otherwise it is left in a state where 7737 * it is possible to transmit but not receive packets. Observed on I217-LM and 7738 * fixed in FreeBSD's sys/dev/e1000/e1000_ich8lan.c. 7739 * 7740 * hw - Struct containing variables accessed by shared code 7741 *****************************************************************************/ 7742 STATIC int32_t 7743 em_phy_no_cable_workaround(struct em_hw *hw) { 7744 int32_t ret_val, dft_ret_val; 7745 uint32_t mac_reg; 7746 uint16_t data, phy_reg; 7747 7748 /* disable Rx path while enabling workaround */ 7749 em_read_phy_reg(hw, I2_DFT_CTRL, &phy_reg); 7750 ret_val = em_write_phy_reg(hw, I2_DFT_CTRL, phy_reg | (1 << 14)); 7751 if (ret_val) 7752 return ret_val; 7753 7754 /* Write MAC register values back to h/w defaults */ 7755 mac_reg = E1000_READ_REG(hw, FFLT_DBG); 7756 mac_reg &= ~(0xF << 14); 7757 E1000_WRITE_REG(hw, FFLT_DBG, mac_reg); 7758 7759 mac_reg = E1000_READ_REG(hw, RCTL); 7760 mac_reg &= ~E1000_RCTL_SECRC; 7761 E1000_WRITE_REG(hw, RCTL, mac_reg); 7762 7763 ret_val = em_read_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_CTRL, &data); 7764 if (ret_val) 7765 goto out; 7766 ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_CTRL, 7767 data & ~(1 << 0)); 7768 if (ret_val) 7769 goto out; 7770 7771 ret_val = em_read_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL, &data); 7772 if (ret_val) 7773 goto out; 7774 7775 data &= ~(0xF << 8); 7776 data |= (0xB << 8); 7777 ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL, data); 7778 if (ret_val) 7779 goto out; 7780 7781 /* Write PHY register values back to h/w defaults */ 7782 em_read_phy_reg(hw, I2_SMBUS_CTRL, &data); 7783 data &= ~(0x7F << 5); 7784 ret_val = em_write_phy_reg(hw, I2_SMBUS_CTRL, data); 7785 if (ret_val) 7786 goto out; 7787 7788 em_read_phy_reg(hw, I2_MODE_CTRL, &data); 7789 data |= (1 << 13); 7790 ret_val = em_write_phy_reg(hw, I2_MODE_CTRL, data); 7791 if (ret_val) 7792 goto out; 7793 7794 /* 7795 * 776.20 and 776.23 are not documented in 7796 * i217-ethernet-controller-datasheet.pdf... 7797 */ 7798 em_read_phy_reg(hw, PHY_REG(776, 20), &data); 7799 data &= ~(0x3FF << 2); 7800 data |= (0x8 << 2); 7801 ret_val = em_write_phy_reg(hw, PHY_REG(776, 20), data); 7802 if (ret_val) 7803 goto out; 7804 7805 ret_val = em_write_phy_reg(hw, PHY_REG(776, 23), 0x7E00); 7806 if (ret_val) 7807 goto out; 7808 7809 em_read_phy_reg(hw, I2_PCIE_POWER_CTRL, &data); 7810 ret_val = em_write_phy_reg(hw, I2_PCIE_POWER_CTRL, data & ~(1 << 10)); 7811 if (ret_val) 7812 goto out; 7813 7814 out: 7815 /* re-enable Rx path after enabling workaround */ 7816 dft_ret_val = em_write_phy_reg(hw, I2_DFT_CTRL, phy_reg & ~(1 << 14)); 7817 if (ret_val) 7818 return ret_val; 7819 else 7820 return dft_ret_val; 7821 } 7822 7823 /****************************************************************************** 7824 * Initializes receive address filters. 7825 * 7826 * hw - Struct containing variables accessed by shared code 7827 * 7828 * Places the MAC address in receive address register 0 and clears the rest 7829 * of the receive address registers. Clears the multicast table. Assumes 7830 * the receiver is in reset when the routine is called. 7831 *****************************************************************************/ 7832 STATIC void 7833 em_init_rx_addrs(struct em_hw *hw) 7834 { 7835 uint32_t i; 7836 uint32_t rar_num; 7837 DEBUGFUNC("em_init_rx_addrs"); 7838 7839 if (hw->mac_type == em_pch_lpt || hw->mac_type == em_pch_spt || 7840 hw->mac_type == em_pch_cnp || hw->mac_type == em_pch_tgp || 7841 hw->mac_type == em_pch_adp || hw->mac_type == em_pch2lan) 7842 if (em_phy_no_cable_workaround(hw)) 7843 printf(" ...failed to apply em_phy_no_cable_" 7844 "workaround.\n"); 7845 7846 /* Setup the receive address. */ 7847 DEBUGOUT("Programming MAC Address into RAR[0]\n"); 7848 7849 em_rar_set(hw, hw->mac_addr, 0); 7850 7851 rar_num = E1000_RAR_ENTRIES; 7852 /* 7853 * Reserve a spot for the Locally Administered Address to work around 7854 * an 82571 issue in which a reset on one port will reload the MAC on 7855 * the other port. 7856 */ 7857 if ((hw->mac_type == em_82571) && (hw->laa_is_present == TRUE)) 7858 rar_num -= 1; 7859 if (IS_ICH8(hw->mac_type)) 7860 rar_num = E1000_RAR_ENTRIES_ICH8LAN; 7861 if (hw->mac_type == em_ich8lan) 7862 rar_num -= 1; 7863 if (hw->mac_type == em_82580) 7864 rar_num = E1000_RAR_ENTRIES_82580; 7865 if (hw->mac_type == em_i210) 7866 rar_num = E1000_RAR_ENTRIES_82575; 7867 if (hw->mac_type == em_i350) 7868 rar_num = E1000_RAR_ENTRIES_I350; 7869 7870 /* Zero out the other 15 receive addresses. */ 7871 DEBUGOUT("Clearing RAR[1-15]\n"); 7872 for (i = 1; i < rar_num; i++) { 7873 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 7874 E1000_WRITE_FLUSH(hw); 7875 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 7876 E1000_WRITE_FLUSH(hw); 7877 } 7878 } 7879 7880 /****************************************************************************** 7881 * Updates the MAC's list of multicast addresses. 7882 * 7883 * hw - Struct containing variables accessed by shared code 7884 * mc_addr_list - the list of new multicast addresses 7885 * mc_addr_count - number of addresses 7886 * pad - number of bytes between addresses in the list 7887 * rar_used_count - offset where to start adding mc addresses into the RAR's 7888 * 7889 * The given list replaces any existing list. Clears the last 15 receive 7890 * address registers and the multicast table. Uses receive address registers 7891 * for the first 15 multicast addresses, and hashes the rest into the 7892 * multicast table. 7893 *****************************************************************************/ 7894 void 7895 em_mc_addr_list_update(struct em_hw *hw, uint8_t *mc_addr_list, 7896 uint32_t mc_addr_count, uint32_t pad, uint32_t rar_used_count) 7897 { 7898 uint32_t hash_value; 7899 uint32_t i; 7900 uint32_t num_rar_entry; 7901 uint32_t num_mta_entry; 7902 DEBUGFUNC("em_mc_addr_list_update"); 7903 /* 7904 * Set the new number of MC addresses that we are being requested to 7905 * use. 7906 */ 7907 hw->num_mc_addrs = mc_addr_count; 7908 7909 /* Clear RAR[1-15] */ 7910 DEBUGOUT(" Clearing RAR[1-15]\n"); 7911 num_rar_entry = E1000_RAR_ENTRIES; 7912 if (IS_ICH8(hw->mac_type)) 7913 num_rar_entry = E1000_RAR_ENTRIES_ICH8LAN; 7914 if (hw->mac_type == em_ich8lan) 7915 num_rar_entry -= 1; 7916 /* 7917 * Reserve a spot for the Locally Administered Address to work around 7918 * an 82571 issue in which a reset on one port will reload the MAC on 7919 * the other port. 7920 */ 7921 if ((hw->mac_type == em_82571) && (hw->laa_is_present == TRUE)) 7922 num_rar_entry -= 1; 7923 7924 for (i = rar_used_count; i < num_rar_entry; i++) { 7925 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 7926 E1000_WRITE_FLUSH(hw); 7927 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 7928 E1000_WRITE_FLUSH(hw); 7929 } 7930 7931 /* Clear the MTA */ 7932 DEBUGOUT(" Clearing MTA\n"); 7933 num_mta_entry = E1000_NUM_MTA_REGISTERS; 7934 if (IS_ICH8(hw->mac_type)) 7935 num_mta_entry = E1000_NUM_MTA_REGISTERS_ICH8LAN; 7936 7937 for (i = 0; i < num_mta_entry; i++) { 7938 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 7939 E1000_WRITE_FLUSH(hw); 7940 } 7941 7942 /* Add the new addresses */ 7943 for (i = 0; i < mc_addr_count; i++) { 7944 DEBUGOUT(" Adding the multicast addresses:\n"); 7945 DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i, 7946 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad)], 7947 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 1], 7948 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 2], 7949 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 3], 7950 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 4], 7951 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 5]); 7952 7953 hash_value = em_hash_mc_addr(hw, mc_addr_list + 7954 (i * (ETH_LENGTH_OF_ADDRESS + pad))); 7955 7956 DEBUGOUT1(" Hash value = 0x%03X\n", hash_value); 7957 /* 7958 * Place this multicast address in the RAR if there is room, * 7959 * else put it in the MTA 7960 */ 7961 if (rar_used_count < num_rar_entry) { 7962 em_rar_set(hw, mc_addr_list + 7963 (i * (ETH_LENGTH_OF_ADDRESS + pad)), 7964 rar_used_count); 7965 rar_used_count++; 7966 } else { 7967 em_mta_set(hw, hash_value); 7968 } 7969 } 7970 DEBUGOUT("MC Update Complete\n"); 7971 } 7972 7973 /****************************************************************************** 7974 * Hashes an address to determine its location in the multicast table 7975 * 7976 * hw - Struct containing variables accessed by shared code 7977 * mc_addr - the multicast address to hash 7978 *****************************************************************************/ 7979 uint32_t 7980 em_hash_mc_addr(struct em_hw *hw, uint8_t *mc_addr) 7981 { 7982 uint32_t hash_value = 0; 7983 /* 7984 * The portion of the address that is used for the hash table is 7985 * determined by the mc_filter_type setting. 7986 */ 7987 switch (hw->mc_filter_type) { 7988 /* 7989 * [0] [1] [2] [3] [4] [5] 01 AA 00 12 34 56 LSB 7990 * MSB 7991 */ 7992 case 0: 7993 if (IS_ICH8(hw->mac_type)) { 7994 /* [47:38] i.e. 0x158 for above example address */ 7995 hash_value = ((mc_addr[4] >> 6) | 7996 (((uint16_t) mc_addr[5]) << 2)); 7997 } else { 7998 /* [47:36] i.e. 0x563 for above example address */ 7999 hash_value = ((mc_addr[4] >> 4) | 8000 (((uint16_t) mc_addr[5]) << 4)); 8001 } 8002 break; 8003 case 1: 8004 if (IS_ICH8(hw->mac_type)) { 8005 /* [46:37] i.e. 0x2B1 for above example address */ 8006 hash_value = ((mc_addr[4] >> 5) | 8007 (((uint16_t) mc_addr[5]) << 3)); 8008 } else { 8009 /* [46:35] i.e. 0xAC6 for above example address */ 8010 hash_value = ((mc_addr[4] >> 3) | 8011 (((uint16_t) mc_addr[5]) << 5)); 8012 } 8013 break; 8014 case 2: 8015 if (IS_ICH8(hw->mac_type)) { 8016 /* [45:36] i.e. 0x163 for above example address */ 8017 hash_value = ((mc_addr[4] >> 4) | 8018 (((uint16_t) mc_addr[5]) << 4)); 8019 } else { 8020 /* [45:34] i.e. 0x5D8 for above example address */ 8021 hash_value = ((mc_addr[4] >> 2) | 8022 (((uint16_t) mc_addr[5]) << 6)); 8023 } 8024 break; 8025 case 3: 8026 if (IS_ICH8(hw->mac_type)) { 8027 /* [43:34] i.e. 0x18D for above example address */ 8028 hash_value = ((mc_addr[4] >> 2) | 8029 (((uint16_t) mc_addr[5]) << 6)); 8030 } else { 8031 /* [43:32] i.e. 0x634 for above example address */ 8032 hash_value = ((mc_addr[4]) | 8033 (((uint16_t) mc_addr[5]) << 8)); 8034 } 8035 break; 8036 } 8037 8038 hash_value &= 0xFFF; 8039 if (IS_ICH8(hw->mac_type)) 8040 hash_value &= 0x3FF; 8041 8042 return hash_value; 8043 } 8044 8045 /****************************************************************************** 8046 * Sets the bit in the multicast table corresponding to the hash value. 8047 * 8048 * hw - Struct containing variables accessed by shared code 8049 * hash_value - Multicast address hash value 8050 *****************************************************************************/ 8051 void 8052 em_mta_set(struct em_hw *hw, uint32_t hash_value) 8053 { 8054 uint32_t hash_bit, hash_reg; 8055 uint32_t mta; 8056 uint32_t temp; 8057 /* 8058 * The MTA is a register array of 128 32-bit registers. It is treated 8059 * like an array of 4096 bits. We want to set bit 8060 * BitArray[hash_value]. So we figure out what register the bit is 8061 * in, read it, OR in the new bit, then write back the new value. 8062 * The register is determined by the upper 7 bits of the hash value 8063 * and the bit within that register are determined by the lower 5 8064 * bits of the value. 8065 */ 8066 hash_reg = (hash_value >> 5) & 0x7F; 8067 if (IS_ICH8(hw->mac_type)) 8068 hash_reg &= 0x1F; 8069 8070 hash_bit = hash_value & 0x1F; 8071 8072 mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg); 8073 8074 mta |= (1 << hash_bit); 8075 /* 8076 * If we are on an 82544 and we are trying to write an odd offset in 8077 * the MTA, save off the previous entry before writing and restore 8078 * the old value after writing. 8079 */ 8080 if ((hw->mac_type == em_82544) && ((hash_reg & 0x1) == 1)) { 8081 temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1)); 8082 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta); 8083 E1000_WRITE_FLUSH(hw); 8084 E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp); 8085 E1000_WRITE_FLUSH(hw); 8086 } else { 8087 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta); 8088 E1000_WRITE_FLUSH(hw); 8089 } 8090 } 8091 8092 /****************************************************************************** 8093 * Puts an ethernet address into a receive address register. 8094 * 8095 * hw - Struct containing variables accessed by shared code 8096 * addr - Address to put into receive address register 8097 * index - Receive address register to write 8098 *****************************************************************************/ 8099 void 8100 em_rar_set(struct em_hw *hw, uint8_t *addr, uint32_t index) 8101 { 8102 uint32_t rar_low, rar_high; 8103 /* 8104 * HW expects these in little endian so we reverse the byte order 8105 * from network order (big endian) to little endian 8106 */ 8107 rar_low = ((uint32_t) addr[0] | ((uint32_t) addr[1] << 8) | 8108 ((uint32_t) addr[2] << 16) | ((uint32_t) addr[3] << 24)); 8109 rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8)); 8110 /* 8111 * Disable Rx and flush all Rx frames before enabling RSS to avoid Rx 8112 * unit hang. 8113 * 8114 * Description: If there are any Rx frames queued up or otherwise 8115 * present in the HW before RSS is enabled, and then we enable RSS, 8116 * the HW Rx unit will hang. To work around this issue, we have to 8117 * disable receives and flush out all Rx frames before we enable RSS. 8118 * To do so, we modify we redirect all Rx traffic to manageability 8119 * and then reset the HW. This flushes away Rx frames, and (since the 8120 * redirections to manageability persists across resets) keeps new 8121 * ones from coming in while we work. Then, we clear the Address 8122 * Valid AV bit for all MAC addresses and undo the re-direction to 8123 * manageability. Now, frames are coming in again, but the MAC won't 8124 * accept them, so far so good. We now proceed to initialize RSS (if 8125 * necessary) and configure the Rx unit. Last, we re-enable the AV 8126 * bits and continue on our merry way. 8127 */ 8128 switch (hw->mac_type) { 8129 case em_82571: 8130 case em_82572: 8131 case em_80003es2lan: 8132 if (hw->leave_av_bit_off == TRUE) 8133 break; 8134 default: 8135 /* Indicate to hardware the Address is Valid. */ 8136 rar_high |= E1000_RAH_AV; 8137 break; 8138 } 8139 8140 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low); 8141 E1000_WRITE_FLUSH(hw); 8142 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high); 8143 E1000_WRITE_FLUSH(hw); 8144 } 8145 8146 /****************************************************************************** 8147 * Clears the VLAN filer table 8148 * 8149 * hw - Struct containing variables accessed by shared code 8150 *****************************************************************************/ 8151 STATIC void 8152 em_clear_vfta(struct em_hw *hw) 8153 { 8154 uint32_t offset; 8155 uint32_t vfta_value = 0; 8156 uint32_t vfta_offset = 0; 8157 uint32_t vfta_bit_in_reg = 0; 8158 if (IS_ICH8(hw->mac_type)) 8159 return; 8160 8161 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) { 8162 if (hw->mng_cookie.vlan_id != 0) { 8163 /* 8164 * The VFTA is a 4096b bit-field, each identifying a 8165 * single VLAN ID. The following operations 8166 * determine which 32b entry (i.e. offset) into the 8167 * array we want to set the VLAN ID (i.e. bit) of the 8168 * manageability unit. 8169 */ 8170 vfta_offset = (hw->mng_cookie.vlan_id >> 8171 E1000_VFTA_ENTRY_SHIFT) & E1000_VFTA_ENTRY_MASK; 8172 8173 vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id & 8174 E1000_VFTA_ENTRY_BIT_SHIFT_MASK); 8175 } 8176 } 8177 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 8178 /* 8179 * If the offset we want to clear is the same offset of the 8180 * manageability VLAN ID, then clear all bits except that of 8181 * the manageability unit 8182 */ 8183 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; 8184 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value); 8185 E1000_WRITE_FLUSH(hw); 8186 } 8187 } 8188 8189 /* 8190 * Due to hw errata, if the host tries to configure the VFTA register 8191 * while performing queries from the BMC or DMA, then the VFTA in some 8192 * cases won't be written. 8193 */ 8194 void 8195 em_clear_vfta_i350(struct em_hw *hw) 8196 { 8197 uint32_t offset; 8198 int i; 8199 8200 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 8201 for (i = 0; i < 10; i++) 8202 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0); 8203 E1000_WRITE_FLUSH(hw); 8204 } 8205 } 8206 8207 STATIC int32_t 8208 em_id_led_init(struct em_hw *hw) 8209 { 8210 uint32_t ledctl; 8211 const uint32_t ledctl_mask = 0x000000FF; 8212 const uint32_t ledctl_on = E1000_LEDCTL_MODE_LED_ON; 8213 const uint32_t ledctl_off = E1000_LEDCTL_MODE_LED_OFF; 8214 uint16_t eeprom_data, i, temp; 8215 const uint16_t led_mask = 0x0F; 8216 DEBUGFUNC("em_id_led_init"); 8217 8218 if (hw->mac_type < em_82540 || hw->mac_type == em_icp_xxxx) { 8219 /* Nothing to do */ 8220 return E1000_SUCCESS; 8221 } 8222 ledctl = E1000_READ_REG(hw, LEDCTL); 8223 hw->ledctl_default = ledctl; 8224 hw->ledctl_mode1 = hw->ledctl_default; 8225 hw->ledctl_mode2 = hw->ledctl_default; 8226 8227 if (em_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) { 8228 DEBUGOUT("EEPROM Read Error\n"); 8229 return -E1000_ERR_EEPROM; 8230 } 8231 if ((hw->mac_type == em_82573) && 8232 (eeprom_data == ID_LED_RESERVED_82573)) 8233 eeprom_data = ID_LED_DEFAULT_82573; 8234 else if ((eeprom_data == ID_LED_RESERVED_0000) || 8235 (eeprom_data == ID_LED_RESERVED_FFFF)) { 8236 if (hw->mac_type == em_ich8lan || 8237 hw->mac_type == em_ich9lan || 8238 hw->mac_type == em_ich10lan) // XXX 8239 eeprom_data = ID_LED_DEFAULT_ICH8LAN; 8240 else 8241 eeprom_data = ID_LED_DEFAULT; 8242 } 8243 for (i = 0; i < 4; i++) { 8244 temp = (eeprom_data >> (i << 2)) & led_mask; 8245 switch (temp) { 8246 case ID_LED_ON1_DEF2: 8247 case ID_LED_ON1_ON2: 8248 case ID_LED_ON1_OFF2: 8249 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 8250 hw->ledctl_mode1 |= ledctl_on << (i << 3); 8251 break; 8252 case ID_LED_OFF1_DEF2: 8253 case ID_LED_OFF1_ON2: 8254 case ID_LED_OFF1_OFF2: 8255 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 8256 hw->ledctl_mode1 |= ledctl_off << (i << 3); 8257 break; 8258 default: 8259 /* Do nothing */ 8260 break; 8261 } 8262 switch (temp) { 8263 case ID_LED_DEF1_ON2: 8264 case ID_LED_ON1_ON2: 8265 case ID_LED_OFF1_ON2: 8266 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 8267 hw->ledctl_mode2 |= ledctl_on << (i << 3); 8268 break; 8269 case ID_LED_DEF1_OFF2: 8270 case ID_LED_ON1_OFF2: 8271 case ID_LED_OFF1_OFF2: 8272 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 8273 hw->ledctl_mode2 |= ledctl_off << (i << 3); 8274 break; 8275 default: 8276 /* Do nothing */ 8277 break; 8278 } 8279 } 8280 return E1000_SUCCESS; 8281 } 8282 8283 /****************************************************************************** 8284 * Clears all hardware statistics counters. 8285 * 8286 * hw - Struct containing variables accessed by shared code 8287 *****************************************************************************/ 8288 void 8289 em_clear_hw_cntrs(struct em_hw *hw) 8290 { 8291 volatile uint32_t temp; 8292 temp = E1000_READ_REG(hw, CRCERRS); 8293 temp = E1000_READ_REG(hw, SYMERRS); 8294 temp = E1000_READ_REG(hw, MPC); 8295 temp = E1000_READ_REG(hw, SCC); 8296 temp = E1000_READ_REG(hw, ECOL); 8297 temp = E1000_READ_REG(hw, MCC); 8298 temp = E1000_READ_REG(hw, LATECOL); 8299 temp = E1000_READ_REG(hw, COLC); 8300 temp = E1000_READ_REG(hw, DC); 8301 temp = E1000_READ_REG(hw, SEC); 8302 temp = E1000_READ_REG(hw, RLEC); 8303 temp = E1000_READ_REG(hw, XONRXC); 8304 temp = E1000_READ_REG(hw, XONTXC); 8305 temp = E1000_READ_REG(hw, XOFFRXC); 8306 temp = E1000_READ_REG(hw, XOFFTXC); 8307 temp = E1000_READ_REG(hw, FCRUC); 8308 8309 if (!IS_ICH8(hw->mac_type)) { 8310 temp = E1000_READ_REG(hw, PRC64); 8311 temp = E1000_READ_REG(hw, PRC127); 8312 temp = E1000_READ_REG(hw, PRC255); 8313 temp = E1000_READ_REG(hw, PRC511); 8314 temp = E1000_READ_REG(hw, PRC1023); 8315 temp = E1000_READ_REG(hw, PRC1522); 8316 } 8317 temp = E1000_READ_REG(hw, GPRC); 8318 temp = E1000_READ_REG(hw, BPRC); 8319 temp = E1000_READ_REG(hw, MPRC); 8320 temp = E1000_READ_REG(hw, GPTC); 8321 temp = E1000_READ_REG(hw, GORCL); 8322 temp = E1000_READ_REG(hw, GORCH); 8323 temp = E1000_READ_REG(hw, GOTCL); 8324 temp = E1000_READ_REG(hw, GOTCH); 8325 temp = E1000_READ_REG(hw, RNBC); 8326 temp = E1000_READ_REG(hw, RUC); 8327 temp = E1000_READ_REG(hw, RFC); 8328 temp = E1000_READ_REG(hw, ROC); 8329 temp = E1000_READ_REG(hw, RJC); 8330 temp = E1000_READ_REG(hw, TORL); 8331 temp = E1000_READ_REG(hw, TORH); 8332 temp = E1000_READ_REG(hw, TOTL); 8333 temp = E1000_READ_REG(hw, TOTH); 8334 temp = E1000_READ_REG(hw, TPR); 8335 temp = E1000_READ_REG(hw, TPT); 8336 8337 if (!IS_ICH8(hw->mac_type)) { 8338 temp = E1000_READ_REG(hw, PTC64); 8339 temp = E1000_READ_REG(hw, PTC127); 8340 temp = E1000_READ_REG(hw, PTC255); 8341 temp = E1000_READ_REG(hw, PTC511); 8342 temp = E1000_READ_REG(hw, PTC1023); 8343 temp = E1000_READ_REG(hw, PTC1522); 8344 } 8345 temp = E1000_READ_REG(hw, MPTC); 8346 temp = E1000_READ_REG(hw, BPTC); 8347 8348 if (hw->mac_type < em_82543) 8349 return; 8350 8351 temp = E1000_READ_REG(hw, ALGNERRC); 8352 temp = E1000_READ_REG(hw, RXERRC); 8353 temp = E1000_READ_REG(hw, TNCRS); 8354 temp = E1000_READ_REG(hw, CEXTERR); 8355 temp = E1000_READ_REG(hw, TSCTC); 8356 temp = E1000_READ_REG(hw, TSCTFC); 8357 8358 if (hw->mac_type <= em_82544 8359 || hw->mac_type == em_icp_xxxx) 8360 return; 8361 8362 temp = E1000_READ_REG(hw, MGTPRC); 8363 temp = E1000_READ_REG(hw, MGTPDC); 8364 temp = E1000_READ_REG(hw, MGTPTC); 8365 8366 if (hw->mac_type <= em_82547_rev_2) 8367 return; 8368 8369 temp = E1000_READ_REG(hw, IAC); 8370 temp = E1000_READ_REG(hw, ICRXOC); 8371 8372 if (hw->phy_type == em_phy_82577 || 8373 hw->phy_type == em_phy_82578 || 8374 hw->phy_type == em_phy_82579 || 8375 hw->phy_type == em_phy_i217) { 8376 uint16_t phy_data; 8377 8378 em_read_phy_reg(hw, HV_SCC_UPPER, &phy_data); 8379 em_read_phy_reg(hw, HV_SCC_LOWER, &phy_data); 8380 em_read_phy_reg(hw, HV_ECOL_UPPER, &phy_data); 8381 em_read_phy_reg(hw, HV_ECOL_LOWER, &phy_data); 8382 em_read_phy_reg(hw, HV_MCC_UPPER, &phy_data); 8383 em_read_phy_reg(hw, HV_MCC_LOWER, &phy_data); 8384 em_read_phy_reg(hw, HV_LATECOL_UPPER, &phy_data); 8385 em_read_phy_reg(hw, HV_LATECOL_LOWER, &phy_data); 8386 em_read_phy_reg(hw, HV_COLC_UPPER, &phy_data); 8387 em_read_phy_reg(hw, HV_COLC_LOWER, &phy_data); 8388 em_read_phy_reg(hw, HV_DC_UPPER, &phy_data); 8389 em_read_phy_reg(hw, HV_DC_LOWER, &phy_data); 8390 em_read_phy_reg(hw, HV_TNCRS_UPPER, &phy_data); 8391 em_read_phy_reg(hw, HV_TNCRS_LOWER, &phy_data); 8392 } 8393 8394 if (hw->mac_type == em_ich8lan || 8395 hw->mac_type == em_ich9lan || 8396 hw->mac_type == em_ich10lan || 8397 hw->mac_type == em_pchlan || 8398 (hw->mac_type != em_pch2lan && hw->mac_type != em_pch_lpt && 8399 hw->mac_type != em_pch_spt && hw->mac_type != em_pch_cnp && 8400 hw->mac_type != em_pch_tgp && hw->mac_type != em_pch_adp)) 8401 return; 8402 8403 temp = E1000_READ_REG(hw, ICRXPTC); 8404 temp = E1000_READ_REG(hw, ICRXATC); 8405 temp = E1000_READ_REG(hw, ICTXPTC); 8406 temp = E1000_READ_REG(hw, ICTXATC); 8407 temp = E1000_READ_REG(hw, ICTXQEC); 8408 temp = E1000_READ_REG(hw, ICTXQMTC); 8409 temp = E1000_READ_REG(hw, ICRXDMTC); 8410 } 8411 8412 /****************************************************************************** 8413 * Gets the current PCI bus type, speed, and width of the hardware 8414 * 8415 * hw - Struct containing variables accessed by shared code 8416 *****************************************************************************/ 8417 void 8418 em_get_bus_info(struct em_hw *hw) 8419 { 8420 int32_t ret_val; 8421 uint16_t pci_ex_link_status; 8422 uint32_t status; 8423 switch (hw->mac_type) { 8424 case em_82542_rev2_0: 8425 case em_82542_rev2_1: 8426 hw->bus_type = em_bus_type_unknown; 8427 hw->bus_speed = em_bus_speed_unknown; 8428 hw->bus_width = em_bus_width_unknown; 8429 break; 8430 case em_icp_xxxx: 8431 hw->bus_type = em_bus_type_cpp; 8432 hw->bus_speed = em_bus_speed_unknown; 8433 hw->bus_width = em_bus_width_unknown; 8434 break; 8435 case em_82571: 8436 case em_82572: 8437 case em_82573: 8438 case em_82574: 8439 case em_82575: 8440 case em_82576: 8441 case em_82580: 8442 case em_80003es2lan: 8443 case em_i210: 8444 case em_i350: 8445 hw->bus_type = em_bus_type_pci_express; 8446 hw->bus_speed = em_bus_speed_2500; 8447 ret_val = em_read_pcie_cap_reg(hw, PCI_EX_LINK_STATUS, 8448 &pci_ex_link_status); 8449 if (ret_val) 8450 hw->bus_width = em_bus_width_unknown; 8451 else 8452 hw->bus_width = (pci_ex_link_status & 8453 PCI_EX_LINK_WIDTH_MASK) >> PCI_EX_LINK_WIDTH_SHIFT; 8454 break; 8455 case em_ich8lan: 8456 case em_ich9lan: 8457 case em_ich10lan: 8458 case em_pchlan: 8459 case em_pch2lan: 8460 case em_pch_lpt: 8461 case em_pch_spt: 8462 case em_pch_cnp: 8463 case em_pch_tgp: 8464 case em_pch_adp: 8465 hw->bus_type = em_bus_type_pci_express; 8466 hw->bus_speed = em_bus_speed_2500; 8467 hw->bus_width = em_bus_width_pciex_1; 8468 break; 8469 default: 8470 status = E1000_READ_REG(hw, STATUS); 8471 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ? 8472 em_bus_type_pcix : em_bus_type_pci; 8473 8474 if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) { 8475 hw->bus_speed = (hw->bus_type == em_bus_type_pci) ? 8476 em_bus_speed_66 : em_bus_speed_120; 8477 } else if (hw->bus_type == em_bus_type_pci) { 8478 hw->bus_speed = (status & E1000_STATUS_PCI66) ? 8479 em_bus_speed_66 : em_bus_speed_33; 8480 } else { 8481 switch (status & E1000_STATUS_PCIX_SPEED) { 8482 case E1000_STATUS_PCIX_SPEED_66: 8483 hw->bus_speed = em_bus_speed_66; 8484 break; 8485 case E1000_STATUS_PCIX_SPEED_100: 8486 hw->bus_speed = em_bus_speed_100; 8487 break; 8488 case E1000_STATUS_PCIX_SPEED_133: 8489 hw->bus_speed = em_bus_speed_133; 8490 break; 8491 default: 8492 hw->bus_speed = em_bus_speed_reserved; 8493 break; 8494 } 8495 } 8496 hw->bus_width = (status & E1000_STATUS_BUS64) ? 8497 em_bus_width_64 : em_bus_width_32; 8498 break; 8499 } 8500 } 8501 8502 /****************************************************************************** 8503 * Writes a value to one of the devices registers using port I/O (as opposed to 8504 * memory mapped I/O). Only 82544 and newer devices support port I/O. 8505 * 8506 * hw - Struct containing variables accessed by shared code 8507 * offset - offset to write to 8508 * value - value to write 8509 *****************************************************************************/ 8510 STATIC void 8511 em_write_reg_io(struct em_hw *hw, uint32_t offset, uint32_t value) 8512 { 8513 unsigned long io_addr = hw->io_base; 8514 unsigned long io_data = hw->io_base + 4; 8515 em_io_write(hw, io_addr, offset); 8516 em_io_write(hw, io_data, value); 8517 } 8518 8519 /****************************************************************************** 8520 * Estimates the cable length. 8521 * 8522 * hw - Struct containing variables accessed by shared code 8523 * min_length - The estimated minimum length 8524 * max_length - The estimated maximum length 8525 * 8526 * returns: - E1000_ERR_XXX 8527 * E1000_SUCCESS 8528 * 8529 * This function always returns a ranged length (minimum & maximum). 8530 * So for M88 phy's, this function interprets the one value returned from the 8531 * register to the minimum and maximum range. 8532 * For IGP phy's, the function calculates the range by the AGC registers. 8533 *****************************************************************************/ 8534 STATIC int32_t 8535 em_get_cable_length(struct em_hw *hw, uint16_t *min_length, 8536 uint16_t *max_length) 8537 { 8538 int32_t ret_val; 8539 uint16_t agc_value = 0; 8540 uint16_t i, phy_data; 8541 uint16_t cable_length; 8542 DEBUGFUNC("em_get_cable_length"); 8543 8544 *min_length = *max_length = 0; 8545 8546 /* Use old method for Phy older than IGP */ 8547 if (hw->phy_type == em_phy_m88 || 8548 hw->phy_type == em_phy_oem || 8549 hw->phy_type == em_phy_82578) { 8550 8551 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, 8552 &phy_data); 8553 if (ret_val) 8554 return ret_val; 8555 cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 8556 M88E1000_PSSR_CABLE_LENGTH_SHIFT; 8557 8558 /* Convert the enum value to ranged values */ 8559 switch (cable_length) { 8560 case em_cable_length_50: 8561 *min_length = 0; 8562 *max_length = em_igp_cable_length_50; 8563 break; 8564 case em_cable_length_50_80: 8565 *min_length = em_igp_cable_length_50; 8566 *max_length = em_igp_cable_length_80; 8567 break; 8568 case em_cable_length_80_110: 8569 *min_length = em_igp_cable_length_80; 8570 *max_length = em_igp_cable_length_110; 8571 break; 8572 case em_cable_length_110_140: 8573 *min_length = em_igp_cable_length_110; 8574 *max_length = em_igp_cable_length_140; 8575 break; 8576 case em_cable_length_140: 8577 *min_length = em_igp_cable_length_140; 8578 *max_length = em_igp_cable_length_170; 8579 break; 8580 default: 8581 return -E1000_ERR_PHY; 8582 break; 8583 } 8584 } else if (hw->phy_type == em_phy_rtl8211) { 8585 /* no cable length info on RTL8211, fake */ 8586 *min_length = 0; 8587 *max_length = em_igp_cable_length_50; 8588 } else if (hw->phy_type == em_phy_gg82563) { 8589 ret_val = em_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE, 8590 &phy_data); 8591 if (ret_val) 8592 return ret_val; 8593 cable_length = phy_data & GG82563_DSPD_CABLE_LENGTH; 8594 8595 switch (cable_length) { 8596 case em_gg_cable_length_60: 8597 *min_length = 0; 8598 *max_length = em_igp_cable_length_60; 8599 break; 8600 case em_gg_cable_length_60_115: 8601 *min_length = em_igp_cable_length_60; 8602 *max_length = em_igp_cable_length_115; 8603 break; 8604 case em_gg_cable_length_115_150: 8605 *min_length = em_igp_cable_length_115; 8606 *max_length = em_igp_cable_length_150; 8607 break; 8608 case em_gg_cable_length_150: 8609 *min_length = em_igp_cable_length_150; 8610 *max_length = em_igp_cable_length_180; 8611 break; 8612 default: 8613 return -E1000_ERR_PHY; 8614 break; 8615 } 8616 } else if (hw->phy_type == em_phy_igp) { /* For IGP PHY */ 8617 uint16_t cur_agc_value; 8618 uint16_t min_agc_value = 8619 IGP01E1000_AGC_LENGTH_TABLE_SIZE; 8620 uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = 8621 {IGP01E1000_PHY_AGC_A, IGP01E1000_PHY_AGC_B, 8622 IGP01E1000_PHY_AGC_C, IGP01E1000_PHY_AGC_D}; 8623 8624 /* Read the AGC registers for all channels */ 8625 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 8626 ret_val = em_read_phy_reg(hw, agc_reg_array[i], 8627 &phy_data); 8628 if (ret_val) 8629 return ret_val; 8630 8631 cur_agc_value = phy_data >> 8632 IGP01E1000_AGC_LENGTH_SHIFT; 8633 8634 /* Value bound check. */ 8635 if ((cur_agc_value >= 8636 IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) || 8637 (cur_agc_value == 0)) 8638 return -E1000_ERR_PHY; 8639 8640 agc_value += cur_agc_value; 8641 8642 /* Update minimal AGC value. */ 8643 if (min_agc_value > cur_agc_value) 8644 min_agc_value = cur_agc_value; 8645 } 8646 8647 /* Remove the minimal AGC result for length < 50m */ 8648 if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * 8649 em_igp_cable_length_50) { 8650 agc_value -= min_agc_value; 8651 8652 /* 8653 * Get the average length of the remaining 3 channels 8654 */ 8655 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1); 8656 } else { 8657 /* Get the average length of all the 4 channels. */ 8658 agc_value /= IGP01E1000_PHY_CHANNEL_NUM; 8659 } 8660 8661 /* Set the range of the calculated length. */ 8662 *min_length = ((em_igp_cable_length_table[agc_value] - 8663 IGP01E1000_AGC_RANGE) > 0) ? 8664 (em_igp_cable_length_table[agc_value] - 8665 IGP01E1000_AGC_RANGE) : 0; 8666 *max_length = em_igp_cable_length_table[agc_value] + 8667 IGP01E1000_AGC_RANGE; 8668 } else if (hw->phy_type == em_phy_igp_2 || 8669 hw->phy_type == em_phy_igp_3) { 8670 uint16_t cur_agc_index, max_agc_index = 0; 8671 uint16_t min_agc_index = IGP02E1000_AGC_LENGTH_TABLE_SIZE - 1; 8672 uint16_t agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = 8673 {IGP02E1000_PHY_AGC_A, IGP02E1000_PHY_AGC_B, 8674 IGP02E1000_PHY_AGC_C, IGP02E1000_PHY_AGC_D}; 8675 /* Read the AGC registers for all channels */ 8676 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { 8677 ret_val = em_read_phy_reg(hw, agc_reg_array[i], 8678 &phy_data); 8679 if (ret_val) 8680 return ret_val; 8681 /* 8682 * Getting bits 15:9, which represent the combination 8683 * of course and fine gain values. The result is a 8684 * number that can be put into the lookup table to 8685 * obtain the approximate cable length. 8686 */ 8687 cur_agc_index = (phy_data >> 8688 IGP02E1000_AGC_LENGTH_SHIFT) & 8689 IGP02E1000_AGC_LENGTH_MASK; 8690 8691 /* Array index bound check. */ 8692 if ((cur_agc_index >= IGP02E1000_AGC_LENGTH_TABLE_SIZE) 8693 || (cur_agc_index == 0)) 8694 return -E1000_ERR_PHY; 8695 8696 /* Remove min & max AGC values from calculation. */ 8697 if (em_igp_2_cable_length_table[min_agc_index] > 8698 em_igp_2_cable_length_table[cur_agc_index]) 8699 min_agc_index = cur_agc_index; 8700 if (em_igp_2_cable_length_table[max_agc_index] < 8701 em_igp_2_cable_length_table[cur_agc_index]) 8702 max_agc_index = cur_agc_index; 8703 8704 agc_value += em_igp_2_cable_length_table 8705 [cur_agc_index]; 8706 } 8707 8708 agc_value -= (em_igp_2_cable_length_table[min_agc_index] + 8709 em_igp_2_cable_length_table[max_agc_index]); 8710 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); 8711 /* 8712 * Calculate cable length with the error range of +/- 10 8713 * meters. 8714 */ 8715 *min_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ? 8716 (agc_value - IGP02E1000_AGC_RANGE) : 0; 8717 *max_length = agc_value + IGP02E1000_AGC_RANGE; 8718 } 8719 return E1000_SUCCESS; 8720 } 8721 8722 /****************************************************************************** 8723 * Check if Downshift occurred 8724 * 8725 * hw - Struct containing variables accessed by shared code 8726 * downshift - output parameter : 0 - No Downshift occurred. 8727 * 1 - Downshift occurred. 8728 * 8729 * returns: - E1000_ERR_XXX 8730 * E1000_SUCCESS 8731 * 8732 * For phy's older then IGP, this function reads the Downshift bit in the Phy 8733 * Specific Status register. For IGP phy's, it reads the Downgrade bit in the 8734 * Link Health register. In IGP this bit is latched high, so the driver must 8735 * read it immediately after link is established. 8736 *****************************************************************************/ 8737 STATIC int32_t 8738 em_check_downshift(struct em_hw *hw) 8739 { 8740 int32_t ret_val; 8741 uint16_t phy_data; 8742 DEBUGFUNC("em_check_downshift"); 8743 8744 if (hw->phy_type == em_phy_igp || 8745 hw->phy_type == em_phy_igp_3 || 8746 hw->phy_type == em_phy_igp_2) { 8747 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH, 8748 &phy_data); 8749 if (ret_val) 8750 return ret_val; 8751 8752 hw->speed_downgraded = (phy_data & 8753 IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0; 8754 } else if ((hw->phy_type == em_phy_m88) || 8755 (hw->phy_type == em_phy_gg82563) || 8756 (hw->phy_type == em_phy_oem) || 8757 (hw->phy_type == em_phy_82578)) { 8758 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, 8759 &phy_data); 8760 if (ret_val) 8761 return ret_val; 8762 8763 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >> 8764 M88E1000_PSSR_DOWNSHIFT_SHIFT; 8765 } else if (hw->phy_type == em_phy_ife) { 8766 /* em_phy_ife supports 10/100 speed only */ 8767 hw->speed_downgraded = FALSE; 8768 } 8769 return E1000_SUCCESS; 8770 } 8771 8772 /***************************************************************************** 8773 * 8774 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a 8775 * gigabit link is achieved to improve link quality. 8776 * 8777 * hw: Struct containing variables accessed by shared code 8778 * 8779 * returns: - E1000_ERR_PHY if fail to read/write the PHY 8780 * E1000_SUCCESS at any other case. 8781 * 8782 ****************************************************************************/ 8783 STATIC int32_t 8784 em_config_dsp_after_link_change(struct em_hw *hw, boolean_t link_up) 8785 { 8786 int32_t ret_val; 8787 uint16_t phy_data, phy_saved_data, speed, duplex, i; 8788 uint16_t dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = 8789 {IGP01E1000_PHY_AGC_PARAM_A, IGP01E1000_PHY_AGC_PARAM_B, 8790 IGP01E1000_PHY_AGC_PARAM_C, IGP01E1000_PHY_AGC_PARAM_D}; 8791 uint16_t min_length, max_length; 8792 DEBUGFUNC("em_config_dsp_after_link_change"); 8793 8794 if (hw->phy_type != em_phy_igp) 8795 return E1000_SUCCESS; 8796 8797 if (link_up) { 8798 ret_val = em_get_speed_and_duplex(hw, &speed, &duplex); 8799 if (ret_val) { 8800 DEBUGOUT("Error getting link speed and duplex\n"); 8801 return ret_val; 8802 } 8803 if (speed == SPEED_1000) { 8804 8805 ret_val = em_get_cable_length(hw, &min_length, &max_length); 8806 if (ret_val) 8807 return ret_val; 8808 8809 if ((hw->dsp_config_state == em_dsp_config_enabled) && 8810 min_length >= em_igp_cable_length_50) { 8811 8812 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; 8813 i++) { 8814 ret_val = em_read_phy_reg(hw, 8815 dsp_reg_array[i], &phy_data); 8816 if (ret_val) 8817 return ret_val; 8818 8819 phy_data &= 8820 ~IGP01E1000_PHY_EDAC_MU_INDEX; 8821 8822 ret_val = em_write_phy_reg(hw, 8823 dsp_reg_array[i], phy_data); 8824 if (ret_val) 8825 return ret_val; 8826 } 8827 hw->dsp_config_state = em_dsp_config_activated; 8828 } 8829 if ((hw->ffe_config_state == em_ffe_config_enabled) && 8830 (min_length < em_igp_cable_length_50)) { 8831 8832 uint16_t ffe_idle_err_timeout = 8833 FFE_IDLE_ERR_COUNT_TIMEOUT_20; 8834 uint32_t idle_errs = 0; 8835 /* clear previous idle error counts */ 8836 ret_val = em_read_phy_reg(hw, PHY_1000T_STATUS, 8837 &phy_data); 8838 if (ret_val) 8839 return ret_val; 8840 8841 for (i = 0; i < ffe_idle_err_timeout; i++) { 8842 usec_delay(1000); 8843 ret_val = em_read_phy_reg(hw, 8844 PHY_1000T_STATUS, &phy_data); 8845 if (ret_val) 8846 return ret_val; 8847 8848 idle_errs += (phy_data & 8849 SR_1000T_IDLE_ERROR_CNT); 8850 if (idle_errs > 8851 SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) { 8852 hw->ffe_config_state = 8853 em_ffe_config_active; 8854 8855 ret_val = em_write_phy_reg(hw, 8856 IGP01E1000_PHY_DSP_FFE, 8857 IGP01E1000_PHY_DSP_FFE_CM_CP); 8858 if (ret_val) 8859 return ret_val; 8860 break; 8861 } 8862 if (idle_errs) 8863 ffe_idle_err_timeout = 8864 FFE_IDLE_ERR_COUNT_TIMEOUT_100; 8865 } 8866 } 8867 } 8868 } else { 8869 if (hw->dsp_config_state == em_dsp_config_activated) { 8870 /* 8871 * Save off the current value of register 0x2F5B to 8872 * be restored at the end of the routines. 8873 */ 8874 ret_val = em_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 8875 8876 if (ret_val) 8877 return ret_val; 8878 8879 /* Disable the PHY transmitter */ 8880 ret_val = em_write_phy_reg(hw, 0x2F5B, 0x0003); 8881 8882 if (ret_val) 8883 return ret_val; 8884 8885 msec_delay_irq(20); 8886 8887 ret_val = em_write_phy_reg(hw, 0x0000, 8888 IGP01E1000_IEEE_FORCE_GIGA); 8889 if (ret_val) 8890 return ret_val; 8891 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 8892 ret_val = em_read_phy_reg(hw, dsp_reg_array[i], 8893 &phy_data); 8894 if (ret_val) 8895 return ret_val; 8896 8897 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; 8898 phy_data |= 8899 IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS; 8900 8901 ret_val = em_write_phy_reg(hw, 8902 dsp_reg_array[i], phy_data); 8903 if (ret_val) 8904 return ret_val; 8905 } 8906 8907 ret_val = em_write_phy_reg(hw, 0x0000, 8908 IGP01E1000_IEEE_RESTART_AUTONEG); 8909 if (ret_val) 8910 return ret_val; 8911 8912 msec_delay_irq(20); 8913 8914 /* Now enable the transmitter */ 8915 ret_val = em_write_phy_reg(hw, 0x2F5B, phy_saved_data); 8916 8917 if (ret_val) 8918 return ret_val; 8919 8920 hw->dsp_config_state = em_dsp_config_enabled; 8921 } 8922 if (hw->ffe_config_state == em_ffe_config_active) { 8923 /* 8924 * Save off the current value of register 0x2F5B to 8925 * be restored at the end of the routines. 8926 */ 8927 ret_val = em_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 8928 8929 if (ret_val) 8930 return ret_val; 8931 8932 /* Disable the PHY transmitter */ 8933 ret_val = em_write_phy_reg(hw, 0x2F5B, 0x0003); 8934 8935 if (ret_val) 8936 return ret_val; 8937 8938 msec_delay_irq(20); 8939 8940 ret_val = em_write_phy_reg(hw, 0x0000, 8941 IGP01E1000_IEEE_FORCE_GIGA); 8942 if (ret_val) 8943 return ret_val; 8944 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE, 8945 IGP01E1000_PHY_DSP_FFE_DEFAULT); 8946 if (ret_val) 8947 return ret_val; 8948 8949 ret_val = em_write_phy_reg(hw, 0x0000, 8950 IGP01E1000_IEEE_RESTART_AUTONEG); 8951 if (ret_val) 8952 return ret_val; 8953 8954 msec_delay_irq(20); 8955 8956 /* Now enable the transmitter */ 8957 ret_val = em_write_phy_reg(hw, 0x2F5B, phy_saved_data); 8958 8959 if (ret_val) 8960 return ret_val; 8961 8962 hw->ffe_config_state = em_ffe_config_enabled; 8963 } 8964 } 8965 return E1000_SUCCESS; 8966 } 8967 8968 /***************************************************************************** 8969 * Set PHY to class A mode 8970 * Assumes the following operations will follow to enable the new class mode. 8971 * 1. Do a PHY soft reset 8972 * 2. Restart auto-negotiation or force link. 8973 * 8974 * hw - Struct containing variables accessed by shared code 8975 ****************************************************************************/ 8976 static int32_t 8977 em_set_phy_mode(struct em_hw *hw) 8978 { 8979 int32_t ret_val; 8980 uint16_t eeprom_data; 8981 DEBUGFUNC("em_set_phy_mode"); 8982 8983 if ((hw->mac_type == em_82545_rev_3) && 8984 (hw->media_type == em_media_type_copper)) { 8985 ret_val = em_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, 8986 &eeprom_data); 8987 if (ret_val) { 8988 return ret_val; 8989 } 8990 if ((eeprom_data != EEPROM_RESERVED_WORD) && 8991 (eeprom_data & EEPROM_PHY_CLASS_A)) { 8992 ret_val = em_write_phy_reg(hw, 8993 M88E1000_PHY_PAGE_SELECT, 0x000B); 8994 if (ret_val) 8995 return ret_val; 8996 ret_val = em_write_phy_reg(hw, 8997 M88E1000_PHY_GEN_CONTROL, 0x8104); 8998 if (ret_val) 8999 return ret_val; 9000 9001 hw->phy_reset_disable = FALSE; 9002 } 9003 } 9004 return E1000_SUCCESS; 9005 } 9006 9007 /***************************************************************************** 9008 * 9009 * This function sets the lplu state according to the active flag. When 9010 * activating lplu this function also disables smart speed and vise versa. 9011 * lplu will not be activated unless the device autonegotiation advertisement 9012 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. 9013 * hw: Struct containing variables accessed by shared code 9014 * active - true to enable lplu false to disable lplu. 9015 * 9016 * returns: - E1000_ERR_PHY if fail to read/write the PHY 9017 * E1000_SUCCESS at any other case. 9018 * 9019 ****************************************************************************/ 9020 STATIC int32_t 9021 em_set_d3_lplu_state(struct em_hw *hw, boolean_t active) 9022 { 9023 uint32_t phy_ctrl = 0; 9024 int32_t ret_val; 9025 uint16_t phy_data; 9026 DEBUGFUNC("em_set_d3_lplu_state"); 9027 9028 if (hw->phy_type != em_phy_igp && hw->phy_type != em_phy_igp_2 9029 && hw->phy_type != em_phy_igp_3) 9030 return E1000_SUCCESS; 9031 /* 9032 * During driver activity LPLU should not be used or it will attain 9033 * link from the lowest speeds starting from 10Mbps. The capability 9034 * is used for Dx transitions and states 9035 */ 9036 if (hw->mac_type == em_82541_rev_2 || hw->mac_type == em_82547_rev_2) { 9037 ret_val = em_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data); 9038 if (ret_val) 9039 return ret_val; 9040 } else if (IS_ICH8(hw->mac_type)) { 9041 /* 9042 * MAC writes into PHY register based on the state transition 9043 * and start auto-negotiation. SW driver can overwrite the 9044 * settings in CSR PHY power control E1000_PHY_CTRL register. 9045 */ 9046 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); 9047 } else { 9048 ret_val = em_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, 9049 &phy_data); 9050 if (ret_val) 9051 return ret_val; 9052 } 9053 9054 if (!active) { 9055 if (hw->mac_type == em_82541_rev_2 || 9056 hw->mac_type == em_82547_rev_2) { 9057 phy_data &= ~IGP01E1000_GMII_FLEX_SPD; 9058 ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO, 9059 phy_data); 9060 if (ret_val) 9061 return ret_val; 9062 } else { 9063 if (IS_ICH8(hw->mac_type)) { 9064 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; 9065 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 9066 } else { 9067 phy_data &= ~IGP02E1000_PM_D3_LPLU; 9068 ret_val = em_write_phy_reg(hw, 9069 IGP02E1000_PHY_POWER_MGMT, phy_data); 9070 if (ret_val) 9071 return ret_val; 9072 } 9073 } 9074 /* 9075 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 9076 * during Dx states where the power conservation is most 9077 * important. During driver activity we should enable 9078 * SmartSpeed, so performance is maintained. 9079 */ 9080 if (hw->smart_speed == em_smart_speed_on) { 9081 ret_val = em_read_phy_reg(hw, 9082 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 9083 if (ret_val) 9084 return ret_val; 9085 9086 phy_data |= IGP01E1000_PSCFR_SMART_SPEED; 9087 ret_val = em_write_phy_reg(hw, 9088 IGP01E1000_PHY_PORT_CONFIG, phy_data); 9089 if (ret_val) 9090 return ret_val; 9091 } else if (hw->smart_speed == em_smart_speed_off) { 9092 ret_val = em_read_phy_reg(hw, 9093 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 9094 if (ret_val) 9095 return ret_val; 9096 9097 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 9098 ret_val = em_write_phy_reg(hw, 9099 IGP01E1000_PHY_PORT_CONFIG, phy_data); 9100 if (ret_val) 9101 return ret_val; 9102 } 9103 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) 9104 || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) || 9105 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) { 9106 9107 if (hw->mac_type == em_82541_rev_2 || 9108 hw->mac_type == em_82547_rev_2) { 9109 phy_data |= IGP01E1000_GMII_FLEX_SPD; 9110 ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO, 9111 phy_data); 9112 if (ret_val) 9113 return ret_val; 9114 } else { 9115 if (IS_ICH8(hw->mac_type)) { 9116 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; 9117 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 9118 } else { 9119 phy_data |= IGP02E1000_PM_D3_LPLU; 9120 ret_val = em_write_phy_reg(hw, 9121 IGP02E1000_PHY_POWER_MGMT, phy_data); 9122 if (ret_val) 9123 return ret_val; 9124 } 9125 } 9126 9127 /* When LPLU is enabled we should disable SmartSpeed */ 9128 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 9129 &phy_data); 9130 if (ret_val) 9131 return ret_val; 9132 9133 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 9134 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 9135 phy_data); 9136 if (ret_val) 9137 return ret_val; 9138 9139 } 9140 return E1000_SUCCESS; 9141 } 9142 9143 /***************************************************************************** 9144 * 9145 * This function sets the lplu d0 state according to the active flag. When 9146 * activating lplu this function also disables smart speed and vise versa. 9147 * lplu will not be activated unless the device autonegotiation advertisement 9148 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. 9149 * hw: Struct containing variables accessed by shared code 9150 * active - true to enable lplu false to disable lplu. 9151 * 9152 * returns: - E1000_ERR_PHY if fail to read/write the PHY 9153 * E1000_SUCCESS at any other case. 9154 * 9155 ****************************************************************************/ 9156 STATIC int32_t 9157 em_set_d0_lplu_state(struct em_hw *hw, boolean_t active) 9158 { 9159 uint32_t phy_ctrl = 0; 9160 int32_t ret_val; 9161 uint16_t phy_data; 9162 DEBUGFUNC("em_set_d0_lplu_state"); 9163 9164 if (hw->mac_type <= em_82547_rev_2) 9165 return E1000_SUCCESS; 9166 9167 if (IS_ICH8(hw->mac_type)) { 9168 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); 9169 } else { 9170 ret_val = em_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, 9171 &phy_data); 9172 if (ret_val) 9173 return ret_val; 9174 } 9175 9176 if (!active) { 9177 if (IS_ICH8(hw->mac_type)) { 9178 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; 9179 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 9180 } else { 9181 phy_data &= ~IGP02E1000_PM_D0_LPLU; 9182 ret_val = em_write_phy_reg(hw, 9183 IGP02E1000_PHY_POWER_MGMT, phy_data); 9184 if (ret_val) 9185 return ret_val; 9186 } 9187 /* 9188 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 9189 * during Dx states where the power conservation is most 9190 * important. During driver activity we should enable 9191 * SmartSpeed, so performance is maintained. 9192 */ 9193 if (hw->smart_speed == em_smart_speed_on) { 9194 ret_val = em_read_phy_reg(hw, 9195 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 9196 if (ret_val) 9197 return ret_val; 9198 9199 phy_data |= IGP01E1000_PSCFR_SMART_SPEED; 9200 ret_val = em_write_phy_reg(hw, 9201 IGP01E1000_PHY_PORT_CONFIG, phy_data); 9202 if (ret_val) 9203 return ret_val; 9204 } else if (hw->smart_speed == em_smart_speed_off) { 9205 ret_val = em_read_phy_reg(hw, 9206 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 9207 if (ret_val) 9208 return ret_val; 9209 9210 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 9211 ret_val = em_write_phy_reg(hw, 9212 IGP01E1000_PHY_PORT_CONFIG, phy_data); 9213 if (ret_val) 9214 return ret_val; 9215 } 9216 } else { 9217 if (IS_ICH8(hw->mac_type)) { 9218 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; 9219 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 9220 } else { 9221 phy_data |= IGP02E1000_PM_D0_LPLU; 9222 ret_val = em_write_phy_reg(hw, 9223 IGP02E1000_PHY_POWER_MGMT, phy_data); 9224 if (ret_val) 9225 return ret_val; 9226 } 9227 9228 /* When LPLU is enabled we should disable SmartSpeed */ 9229 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 9230 &phy_data); 9231 if (ret_val) 9232 return ret_val; 9233 9234 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 9235 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 9236 phy_data); 9237 if (ret_val) 9238 return ret_val; 9239 9240 } 9241 return E1000_SUCCESS; 9242 } 9243 9244 /*************************************************************************** 9245 * Set Low Power Link Up state 9246 * 9247 * Sets the LPLU state according to the active flag. For PCH, if OEM write 9248 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set 9249 * the phy speed. This function will manually set the LPLU bit and restart 9250 * auto-neg as hw would do. D3 and D0 LPLU will call the same function 9251 * since it configures the same bit. 9252 ***************************************************************************/ 9253 int32_t 9254 em_set_lplu_state_pchlan(struct em_hw *hw, boolean_t active) 9255 { 9256 int32_t ret_val = E1000_SUCCESS; 9257 uint16_t oem_reg; 9258 9259 DEBUGFUNC("e1000_set_lplu_state_pchlan"); 9260 9261 ret_val = em_read_phy_reg(hw, HV_OEM_BITS, &oem_reg); 9262 if (ret_val) 9263 goto out; 9264 9265 if (active) 9266 oem_reg |= HV_OEM_BITS_LPLU; 9267 else 9268 oem_reg &= ~HV_OEM_BITS_LPLU; 9269 9270 oem_reg |= HV_OEM_BITS_RESTART_AN; 9271 ret_val = em_write_phy_reg(hw, HV_OEM_BITS, oem_reg); 9272 9273 out: 9274 return ret_val; 9275 } 9276 9277 /****************************************************************************** 9278 * Change VCO speed register to improve Bit Error Rate performance of SERDES. 9279 * 9280 * hw - Struct containing variables accessed by shared code 9281 *****************************************************************************/ 9282 static int32_t 9283 em_set_vco_speed(struct em_hw *hw) 9284 { 9285 int32_t ret_val; 9286 uint16_t default_page = 0; 9287 uint16_t phy_data; 9288 DEBUGFUNC("em_set_vco_speed"); 9289 9290 switch (hw->mac_type) { 9291 case em_82545_rev_3: 9292 case em_82546_rev_3: 9293 break; 9294 default: 9295 return E1000_SUCCESS; 9296 } 9297 9298 /* Set PHY register 30, page 5, bit 8 to 0 */ 9299 9300 ret_val = em_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page); 9301 if (ret_val) 9302 return ret_val; 9303 9304 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005); 9305 if (ret_val) 9306 return ret_val; 9307 9308 ret_val = em_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); 9309 if (ret_val) 9310 return ret_val; 9311 9312 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8; 9313 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); 9314 if (ret_val) 9315 return ret_val; 9316 9317 /* Set PHY register 30, page 4, bit 11 to 1 */ 9318 9319 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004); 9320 if (ret_val) 9321 return ret_val; 9322 9323 ret_val = em_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); 9324 if (ret_val) 9325 return ret_val; 9326 9327 phy_data |= M88E1000_PHY_VCO_REG_BIT11; 9328 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); 9329 if (ret_val) 9330 return ret_val; 9331 9332 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page); 9333 if (ret_val) 9334 return ret_val; 9335 9336 return E1000_SUCCESS; 9337 } 9338 9339 /***************************************************************************** 9340 * This function reads the cookie from ARC ram. 9341 * 9342 * returns: - E1000_SUCCESS . 9343 ****************************************************************************/ 9344 STATIC int32_t 9345 em_host_if_read_cookie(struct em_hw *hw, uint8_t *buffer) 9346 { 9347 uint8_t i; 9348 uint32_t offset = E1000_MNG_DHCP_COOKIE_OFFSET; 9349 uint8_t length = E1000_MNG_DHCP_COOKIE_LENGTH; 9350 length = (length >> 2); 9351 offset = (offset >> 2); 9352 9353 for (i = 0; i < length; i++) { 9354 *((uint32_t *) buffer + i) = 9355 E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i); 9356 } 9357 return E1000_SUCCESS; 9358 } 9359 9360 /***************************************************************************** 9361 * This function checks whether the HOST IF is enabled for command operation 9362 * and also checks whether the previous command is completed. 9363 * It busy waits in case of previous command is not completed. 9364 * 9365 * returns: - E1000_ERR_HOST_INTERFACE_COMMAND in case if is not ready or 9366 * timeout 9367 * - E1000_SUCCESS for success. 9368 ****************************************************************************/ 9369 STATIC int32_t 9370 em_mng_enable_host_if(struct em_hw *hw) 9371 { 9372 uint32_t hicr; 9373 uint8_t i; 9374 /* Check that the host interface is enabled. */ 9375 hicr = E1000_READ_REG(hw, HICR); 9376 if ((hicr & E1000_HICR_EN) == 0) { 9377 DEBUGOUT("E1000_HOST_EN bit disabled.\n"); 9378 return -E1000_ERR_HOST_INTERFACE_COMMAND; 9379 } 9380 /* check the previous command is completed */ 9381 for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) { 9382 hicr = E1000_READ_REG(hw, HICR); 9383 if (!(hicr & E1000_HICR_C)) 9384 break; 9385 msec_delay_irq(1); 9386 } 9387 9388 if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) { 9389 DEBUGOUT("Previous command timeout failed .\n"); 9390 return -E1000_ERR_HOST_INTERFACE_COMMAND; 9391 } 9392 return E1000_SUCCESS; 9393 } 9394 9395 /***************************************************************************** 9396 * This function checks the mode of the firmware. 9397 * 9398 * returns - TRUE when the mode is IAMT or FALSE. 9399 ****************************************************************************/ 9400 boolean_t 9401 em_check_mng_mode(struct em_hw *hw) 9402 { 9403 uint32_t fwsm; 9404 fwsm = E1000_READ_REG(hw, FWSM); 9405 9406 if (IS_ICH8(hw->mac_type)) { 9407 if ((fwsm & E1000_FWSM_MODE_MASK) == 9408 (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) 9409 return TRUE; 9410 } else if ((fwsm & E1000_FWSM_MODE_MASK) == 9411 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) 9412 return TRUE; 9413 9414 return FALSE; 9415 } 9416 9417 /***************************************************************************** 9418 * This function calculates the checksum. 9419 * 9420 * returns - checksum of buffer contents. 9421 ****************************************************************************/ 9422 STATIC uint8_t 9423 em_calculate_mng_checksum(char *buffer, uint32_t length) 9424 { 9425 uint8_t sum = 0; 9426 uint32_t i; 9427 if (!buffer) 9428 return 0; 9429 9430 for (i = 0; i < length; i++) 9431 sum += buffer[i]; 9432 9433 return (uint8_t) (0 - sum); 9434 } 9435 9436 /***************************************************************************** 9437 * This function checks whether tx pkt filtering needs to be enabled or not. 9438 * 9439 * returns - TRUE for packet filtering or FALSE. 9440 ****************************************************************************/ 9441 boolean_t 9442 em_enable_tx_pkt_filtering(struct em_hw *hw) 9443 { 9444 /* called in init as well as watchdog timer functions */ 9445 int32_t ret_val, checksum; 9446 boolean_t tx_filter = FALSE; 9447 struct em_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie); 9448 uint8_t *buffer = (uint8_t *) & (hw->mng_cookie); 9449 if (em_check_mng_mode(hw)) { 9450 ret_val = em_mng_enable_host_if(hw); 9451 if (ret_val == E1000_SUCCESS) { 9452 ret_val = em_host_if_read_cookie(hw, buffer); 9453 if (ret_val == E1000_SUCCESS) { 9454 checksum = hdr->checksum; 9455 hdr->checksum = 0; 9456 if ((hdr->signature == E1000_IAMT_SIGNATURE) && 9457 checksum == em_calculate_mng_checksum( 9458 (char *) buffer, 9459 E1000_MNG_DHCP_COOKIE_LENGTH)) { 9460 if (hdr->status & 9461 E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT) 9462 tx_filter = TRUE; 9463 } else 9464 tx_filter = TRUE; 9465 } else 9466 tx_filter = TRUE; 9467 } 9468 } 9469 hw->tx_pkt_filtering = tx_filter; 9470 return tx_filter; 9471 } 9472 9473 static int32_t 9474 em_polarity_reversal_workaround(struct em_hw *hw) 9475 { 9476 int32_t ret_val; 9477 uint16_t mii_status_reg; 9478 uint16_t i; 9479 /* Polarity reversal workaround for forced 10F/10H links. */ 9480 9481 /* Disable the transmitter on the PHY */ 9482 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 9483 if (ret_val) 9484 return ret_val; 9485 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF); 9486 if (ret_val) 9487 return ret_val; 9488 9489 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 9490 if (ret_val) 9491 return ret_val; 9492 9493 /* This loop will early-out if the NO link condition has been met. */ 9494 for (i = PHY_FORCE_TIME; i > 0; i--) { 9495 /* 9496 * Read the MII Status Register and wait for Link Status bit 9497 * to be clear. 9498 */ 9499 9500 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 9501 if (ret_val) 9502 return ret_val; 9503 9504 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 9505 if (ret_val) 9506 return ret_val; 9507 9508 if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) 9509 break; 9510 msec_delay_irq(100); 9511 } 9512 9513 /* Recommended delay time after link has been lost */ 9514 msec_delay_irq(1000); 9515 9516 /* Now we will re-enable the transmitter on the PHY */ 9517 9518 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 9519 if (ret_val) 9520 return ret_val; 9521 msec_delay_irq(50); 9522 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0); 9523 if (ret_val) 9524 return ret_val; 9525 msec_delay_irq(50); 9526 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00); 9527 if (ret_val) 9528 return ret_val; 9529 msec_delay_irq(50); 9530 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000); 9531 if (ret_val) 9532 return ret_val; 9533 9534 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 9535 if (ret_val) 9536 return ret_val; 9537 9538 /* This loop will early-out if the link condition has been met. */ 9539 for (i = PHY_FORCE_TIME; i > 0; i--) { 9540 /* 9541 * Read the MII Status Register and wait for Link Status bit 9542 * to be set. 9543 */ 9544 9545 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 9546 if (ret_val) 9547 return ret_val; 9548 9549 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 9550 if (ret_val) 9551 return ret_val; 9552 9553 if (mii_status_reg & MII_SR_LINK_STATUS) 9554 break; 9555 msec_delay_irq(100); 9556 } 9557 return E1000_SUCCESS; 9558 } 9559 9560 /****************************************************************************** 9561 * 9562 * Disables PCI-Express master access. 9563 * 9564 * hw: Struct containing variables accessed by shared code 9565 * 9566 * returns: - none. 9567 * 9568 *****************************************************************************/ 9569 STATIC void 9570 em_set_pci_express_master_disable(struct em_hw *hw) 9571 { 9572 uint32_t ctrl; 9573 DEBUGFUNC("em_set_pci_express_master_disable"); 9574 9575 if (hw->bus_type != em_bus_type_pci_express) 9576 return; 9577 9578 ctrl = E1000_READ_REG(hw, CTRL); 9579 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; 9580 E1000_WRITE_REG(hw, CTRL, ctrl); 9581 } 9582 9583 /****************************************************************************** 9584 * 9585 * Disables PCI-Express master access and verifies there are no pending 9586 * requests 9587 * 9588 * hw: Struct containing variables accessed by shared code 9589 * 9590 * returns: - E1000_ERR_MASTER_REQUESTS_PENDING if master disable bit hasn't 9591 * caused the master requests to be disabled. 9592 * E1000_SUCCESS master requests disabled. 9593 * 9594 ******************************************************************************/ 9595 int32_t 9596 em_disable_pciex_master(struct em_hw *hw) 9597 { 9598 int32_t timeout = MASTER_DISABLE_TIMEOUT; /* 80ms */ 9599 DEBUGFUNC("em_disable_pciex_master"); 9600 9601 if (hw->bus_type != em_bus_type_pci_express) 9602 return E1000_SUCCESS; 9603 9604 em_set_pci_express_master_disable(hw); 9605 9606 while (timeout) { 9607 if (!(E1000_READ_REG(hw, STATUS) & 9608 E1000_STATUS_GIO_MASTER_ENABLE)) 9609 break; 9610 else 9611 usec_delay(100); 9612 timeout--; 9613 } 9614 9615 if (!timeout) { 9616 DEBUGOUT("Master requests are pending.\n"); 9617 return -E1000_ERR_MASTER_REQUESTS_PENDING; 9618 } 9619 return E1000_SUCCESS; 9620 } 9621 9622 /****************************************************************************** 9623 * 9624 * Check for EEPROM Auto Read bit done. 9625 * 9626 * hw: Struct containing variables accessed by shared code 9627 * 9628 * returns: - E1000_ERR_RESET if fail to reset MAC 9629 * E1000_SUCCESS at any other case. 9630 * 9631 ******************************************************************************/ 9632 STATIC int32_t 9633 em_get_auto_rd_done(struct em_hw *hw) 9634 { 9635 int32_t timeout = AUTO_READ_DONE_TIMEOUT; 9636 DEBUGFUNC("em_get_auto_rd_done"); 9637 9638 switch (hw->mac_type) { 9639 default: 9640 msec_delay(5); 9641 break; 9642 case em_82571: 9643 case em_82572: 9644 case em_82573: 9645 case em_82574: 9646 case em_82575: 9647 case em_82576: 9648 case em_82580: 9649 case em_80003es2lan: 9650 case em_i210: 9651 case em_i350: 9652 case em_ich8lan: 9653 case em_ich9lan: 9654 case em_ich10lan: 9655 case em_pchlan: 9656 case em_pch2lan: 9657 case em_pch_lpt: 9658 case em_pch_spt: 9659 case em_pch_cnp: 9660 case em_pch_tgp: 9661 case em_pch_adp: 9662 while (timeout) { 9663 if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD) 9664 break; 9665 else 9666 msec_delay(1); 9667 timeout--; 9668 } 9669 9670 if (!timeout) { 9671 DEBUGOUT("Auto read by HW from EEPROM has not" 9672 " completed.\n"); 9673 return -E1000_ERR_RESET; 9674 } 9675 break; 9676 } 9677 /* 9678 * PHY configuration from NVM just starts after EECD_AUTO_RD sets to 9679 * high. Need to wait for PHY configuration completion before 9680 * accessing NVM and PHY. 9681 */ 9682 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) 9683 msec_delay(25); 9684 9685 return E1000_SUCCESS; 9686 } 9687 9688 /*************************************************************************** 9689 * Checks if the PHY configuration is done 9690 * 9691 * hw: Struct containing variables accessed by shared code 9692 * 9693 * returns: - E1000_ERR_RESET if fail to reset MAC 9694 * E1000_SUCCESS at any other case. 9695 * 9696 ***************************************************************************/ 9697 STATIC int32_t 9698 em_get_phy_cfg_done(struct em_hw *hw) 9699 { 9700 int32_t timeout = PHY_CFG_TIMEOUT; 9701 uint32_t cfg_mask = E1000_NVM_CFG_DONE_PORT_0; 9702 DEBUGFUNC("em_get_phy_cfg_done"); 9703 9704 switch (hw->mac_type) { 9705 default: 9706 msec_delay_irq(10); 9707 break; 9708 case em_80003es2lan: 9709 case em_82575: 9710 case em_82576: 9711 case em_82580: 9712 case em_i350: 9713 switch (hw->bus_func) { 9714 case 1: 9715 cfg_mask = E1000_NVM_CFG_DONE_PORT_1; 9716 break; 9717 case 2: 9718 cfg_mask = E1000_NVM_CFG_DONE_PORT_2; 9719 break; 9720 case 3: 9721 cfg_mask = E1000_NVM_CFG_DONE_PORT_3; 9722 break; 9723 } 9724 /* FALLTHROUGH */ 9725 case em_82571: 9726 case em_82572: 9727 while (timeout) { 9728 if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask) 9729 break; 9730 else 9731 msec_delay(1); 9732 timeout--; 9733 } 9734 if (!timeout) { 9735 DEBUGOUT("MNG configuration cycle has not completed." 9736 "\n"); 9737 } 9738 break; 9739 } 9740 9741 return E1000_SUCCESS; 9742 } 9743 9744 /*************************************************************************** 9745 * 9746 * Using the combination of SMBI and SWESMBI semaphore bits when resetting 9747 * adapter or Eeprom access. 9748 * 9749 * hw: Struct containing variables accessed by shared code 9750 * 9751 * returns: - E1000_ERR_EEPROM if fail to access EEPROM. 9752 * E1000_SUCCESS at any other case. 9753 * 9754 ***************************************************************************/ 9755 STATIC int32_t 9756 em_get_hw_eeprom_semaphore(struct em_hw *hw) 9757 { 9758 int32_t timeout; 9759 uint32_t swsm; 9760 DEBUGFUNC("em_get_hw_eeprom_semaphore"); 9761 9762 if (!hw->eeprom_semaphore_present) 9763 return E1000_SUCCESS; 9764 9765 if (hw->mac_type == em_80003es2lan) { 9766 /* Get the SW semaphore. */ 9767 if (em_get_software_semaphore(hw) != E1000_SUCCESS) 9768 return -E1000_ERR_EEPROM; 9769 } 9770 /* Get the FW semaphore. */ 9771 timeout = hw->eeprom.word_size + 1; 9772 while (timeout) { 9773 swsm = E1000_READ_REG(hw, SWSM); 9774 swsm |= E1000_SWSM_SWESMBI; 9775 E1000_WRITE_REG(hw, SWSM, swsm); 9776 /* if we managed to set the bit we got the semaphore. */ 9777 swsm = E1000_READ_REG(hw, SWSM); 9778 if (swsm & E1000_SWSM_SWESMBI) 9779 break; 9780 9781 usec_delay(50); 9782 timeout--; 9783 } 9784 9785 if (!timeout) { 9786 /* Release semaphores */ 9787 em_put_hw_eeprom_semaphore(hw); 9788 DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set." 9789 "\n"); 9790 return -E1000_ERR_EEPROM; 9791 } 9792 return E1000_SUCCESS; 9793 } 9794 9795 /*************************************************************************** 9796 * This function clears HW semaphore bits. 9797 * 9798 * hw: Struct containing variables accessed by shared code 9799 * 9800 * returns: - None. 9801 * 9802 ***************************************************************************/ 9803 STATIC void 9804 em_put_hw_eeprom_semaphore(struct em_hw *hw) 9805 { 9806 uint32_t swsm; 9807 DEBUGFUNC("em_put_hw_eeprom_semaphore"); 9808 9809 if (!hw->eeprom_semaphore_present) 9810 return; 9811 9812 swsm = E1000_READ_REG(hw, SWSM); 9813 if (hw->mac_type == em_80003es2lan) { 9814 /* Release both semaphores. */ 9815 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 9816 } else 9817 swsm &= ~(E1000_SWSM_SWESMBI); 9818 E1000_WRITE_REG(hw, SWSM, swsm); 9819 } 9820 9821 /*************************************************************************** 9822 * 9823 * Obtaining software semaphore bit (SMBI) before resetting PHY. 9824 * 9825 * hw: Struct containing variables accessed by shared code 9826 * 9827 * returns: - E1000_ERR_RESET if fail to obtain semaphore. 9828 * E1000_SUCCESS at any other case. 9829 * 9830 ***************************************************************************/ 9831 STATIC int32_t 9832 em_get_software_semaphore(struct em_hw *hw) 9833 { 9834 int32_t timeout = hw->eeprom.word_size + 1; 9835 uint32_t swsm; 9836 DEBUGFUNC("em_get_software_semaphore"); 9837 9838 if (hw->mac_type != em_80003es2lan) 9839 return E1000_SUCCESS; 9840 9841 while (timeout) { 9842 swsm = E1000_READ_REG(hw, SWSM); 9843 /* 9844 * If SMBI bit cleared, it is now set and we hold the 9845 * semaphore 9846 */ 9847 if (!(swsm & E1000_SWSM_SMBI)) 9848 break; 9849 msec_delay_irq(1); 9850 timeout--; 9851 } 9852 9853 if (!timeout) { 9854 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 9855 return -E1000_ERR_RESET; 9856 } 9857 return E1000_SUCCESS; 9858 } 9859 9860 /*************************************************************************** 9861 * 9862 * Release semaphore bit (SMBI). 9863 * 9864 * hw: Struct containing variables accessed by shared code 9865 * 9866 ***************************************************************************/ 9867 STATIC void 9868 em_release_software_semaphore(struct em_hw *hw) 9869 { 9870 uint32_t swsm; 9871 DEBUGFUNC("em_release_software_semaphore"); 9872 9873 if (hw->mac_type != em_80003es2lan) 9874 return; 9875 9876 swsm = E1000_READ_REG(hw, SWSM); 9877 /* Release the SW semaphores. */ 9878 swsm &= ~E1000_SWSM_SMBI; 9879 E1000_WRITE_REG(hw, SWSM, swsm); 9880 } 9881 9882 /****************************************************************************** 9883 * Checks if PHY reset is blocked due to SOL/IDER session, for example. 9884 * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to 9885 * the caller to figure out how to deal with it. 9886 * 9887 * hw - Struct containing variables accessed by shared code 9888 * 9889 * returns: - E1000_BLK_PHY_RESET 9890 * E1000_SUCCESS 9891 * 9892 *****************************************************************************/ 9893 int32_t 9894 em_check_phy_reset_block(struct em_hw *hw) 9895 { 9896 uint32_t manc = 0; 9897 uint32_t fwsm = 0; 9898 DEBUGFUNC("em_check_phy_reset_block\n"); 9899 9900 if (IS_ICH8(hw->mac_type)) { 9901 int i = 0; 9902 int blocked = 0; 9903 do { 9904 fwsm = E1000_READ_REG(hw, FWSM); 9905 if (!(fwsm & E1000_FWSM_RSPCIPHY)) { 9906 blocked = 1; 9907 msec_delay(10); 9908 continue; 9909 } 9910 blocked = 0; 9911 } while (blocked && (i++ < 30)); 9912 return blocked ? E1000_BLK_PHY_RESET : E1000_SUCCESS; 9913 } 9914 if (hw->mac_type > em_82547_rev_2) 9915 manc = E1000_READ_REG(hw, MANC); 9916 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? 9917 E1000_BLK_PHY_RESET : E1000_SUCCESS; 9918 } 9919 9920 /****************************************************************************** 9921 * Configure PCI-Ex no-snoop 9922 * 9923 * hw - Struct containing variables accessed by shared code. 9924 * no_snoop - Bitmap of no-snoop events. 9925 * 9926 * returns: E1000_SUCCESS 9927 * 9928 *****************************************************************************/ 9929 STATIC int32_t 9930 em_set_pci_ex_no_snoop(struct em_hw *hw, uint32_t no_snoop) 9931 { 9932 uint32_t gcr_reg = 0; 9933 DEBUGFUNC("em_set_pci_ex_no_snoop"); 9934 9935 if (hw->bus_type == em_bus_type_unknown) 9936 em_get_bus_info(hw); 9937 9938 if (hw->bus_type != em_bus_type_pci_express) 9939 return E1000_SUCCESS; 9940 9941 if (no_snoop) { 9942 gcr_reg = E1000_READ_REG(hw, GCR); 9943 gcr_reg &= ~(PCI_EX_NO_SNOOP_ALL); 9944 gcr_reg |= no_snoop; 9945 E1000_WRITE_REG(hw, GCR, gcr_reg); 9946 } 9947 if (IS_ICH8(hw->mac_type)) { 9948 uint32_t ctrl_ext; 9949 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 9950 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 9951 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 9952 } 9953 return E1000_SUCCESS; 9954 } 9955 9956 /*************************************************************************** 9957 * 9958 * Get software semaphore FLAG bit (SWFLAG). 9959 * SWFLAG is used to synchronize the access to all shared resource between 9960 * SW, FW and HW. 9961 * 9962 * hw: Struct containing variables accessed by shared code 9963 * 9964 ***************************************************************************/ 9965 STATIC int32_t 9966 em_get_software_flag(struct em_hw *hw) 9967 { 9968 int32_t timeout = PHY_CFG_TIMEOUT; 9969 uint32_t extcnf_ctrl; 9970 DEBUGFUNC("em_get_software_flag"); 9971 9972 if (IS_ICH8(hw->mac_type)) { 9973 if (hw->sw_flag) { 9974 hw->sw_flag++; 9975 return E1000_SUCCESS; 9976 } 9977 while (timeout) { 9978 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 9979 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)) 9980 break; 9981 msec_delay_irq(1); 9982 timeout--; 9983 } 9984 if (!timeout) { 9985 printf("%s: SW has already locked the resource?\n", 9986 __func__); 9987 return -E1000_ERR_CONFIG; 9988 } 9989 timeout = SW_FLAG_TIMEOUT; 9990 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; 9991 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); 9992 9993 while (timeout) { 9994 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 9995 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) 9996 break; 9997 msec_delay_irq(1); 9998 timeout--; 9999 } 10000 10001 if (!timeout) { 10002 printf("Failed to acquire the semaphore, FW or HW " 10003 "has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n", 10004 E1000_READ_REG(hw, FWSM), extcnf_ctrl); 10005 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 10006 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); 10007 return -E1000_ERR_CONFIG; 10008 } 10009 } 10010 hw->sw_flag++; 10011 return E1000_SUCCESS; 10012 } 10013 10014 /*************************************************************************** 10015 * 10016 * Release software semaphore FLAG bit (SWFLAG). 10017 * SWFLAG is used to synchronize the access to all shared resource between 10018 * SW, FW and HW. 10019 * 10020 * hw: Struct containing variables accessed by shared code 10021 * 10022 ***************************************************************************/ 10023 STATIC void 10024 em_release_software_flag(struct em_hw *hw) 10025 { 10026 uint32_t extcnf_ctrl; 10027 DEBUGFUNC("em_release_software_flag"); 10028 10029 if (IS_ICH8(hw->mac_type)) { 10030 KASSERT(hw->sw_flag > 0); 10031 if (--hw->sw_flag > 0) 10032 return; 10033 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 10034 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 10035 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); 10036 } 10037 return; 10038 } 10039 10040 /** 10041 * em_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1 10042 * @hw: pointer to the HW structure 10043 * @bank: pointer to the variable that returns the active bank 10044 * 10045 * Reads signature byte from the NVM using the flash access registers. 10046 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank. 10047 **/ 10048 int32_t 10049 em_valid_nvm_bank_detect_ich8lan(struct em_hw *hw, uint32_t *bank) 10050 { 10051 uint32_t eecd; 10052 uint32_t bank1_offset = hw->flash_bank_size * sizeof(uint16_t); 10053 uint32_t act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1; 10054 uint32_t nvm_dword = 0; 10055 uint8_t sig_byte = 0; 10056 int32_t ret_val; 10057 10058 DEBUGFUNC("em_valid_nvm_bank_detect_ich8lan"); 10059 10060 switch (hw->mac_type) { 10061 case em_pch_spt: 10062 case em_pch_cnp: 10063 case em_pch_tgp: 10064 case em_pch_adp: 10065 bank1_offset = hw->flash_bank_size * 2; 10066 act_offset = E1000_ICH_NVM_SIG_WORD * 2; 10067 10068 /* set bank to 0 in case flash read fails. */ 10069 *bank = 0; 10070 10071 /* Check bank 0 */ 10072 ret_val = em_read_ich8_dword(hw, act_offset, &nvm_dword); 10073 if (ret_val) 10074 return ret_val; 10075 sig_byte = (uint8_t)((nvm_dword & 0xFF00) >> 8); 10076 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 10077 E1000_ICH_NVM_SIG_VALUE) { 10078 *bank = 0; 10079 return 0; 10080 } 10081 10082 /* Check bank 1 */ 10083 ret_val = em_read_ich8_dword(hw, act_offset + bank1_offset, 10084 &nvm_dword); 10085 if (ret_val) 10086 return ret_val; 10087 sig_byte = (uint8_t)((nvm_dword & 0xFF00) >> 8); 10088 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 10089 E1000_ICH_NVM_SIG_VALUE) { 10090 *bank = 1; 10091 return 0; 10092 } 10093 10094 DEBUGOUT("ERROR: No valid NVM bank present\n"); 10095 return -1; 10096 case em_ich8lan: 10097 case em_ich9lan: 10098 eecd = E1000_READ_REG(hw, EECD); 10099 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) == 10100 E1000_EECD_SEC1VAL_VALID_MASK) { 10101 if (eecd & E1000_EECD_SEC1VAL) 10102 *bank = 1; 10103 else 10104 *bank = 0; 10105 10106 return E1000_SUCCESS; 10107 } 10108 DEBUGOUT("Unable to determine valid NVM bank via EEC - reading flash signature\n"); 10109 /* fall-thru */ 10110 default: 10111 /* set bank to 0 in case flash read fails */ 10112 *bank = 0; 10113 10114 /* Check bank 0 */ 10115 ret_val = em_read_ich8_byte(hw, act_offset, 10116 &sig_byte); 10117 if (ret_val) 10118 return ret_val; 10119 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 10120 E1000_ICH_NVM_SIG_VALUE) { 10121 *bank = 0; 10122 return E1000_SUCCESS; 10123 } 10124 10125 /* Check bank 1 */ 10126 ret_val = em_read_ich8_byte(hw, act_offset + 10127 bank1_offset, 10128 &sig_byte); 10129 if (ret_val) 10130 return ret_val; 10131 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 10132 E1000_ICH_NVM_SIG_VALUE) { 10133 *bank = 1; 10134 return E1000_SUCCESS; 10135 } 10136 10137 DEBUGOUT("ERROR: No valid NVM bank present\n"); 10138 return -1; 10139 } 10140 } 10141 10142 STATIC int32_t 10143 em_read_eeprom_spt(struct em_hw *hw, uint16_t offset, uint16_t words, 10144 uint16_t *data) 10145 { 10146 int32_t error = E1000_SUCCESS; 10147 uint32_t flash_bank = 0; 10148 uint32_t act_offset = 0; 10149 uint32_t bank_offset = 0; 10150 uint32_t dword = 0; 10151 uint16_t i = 0, add; 10152 10153 /* 10154 * We need to know which is the valid flash bank. In the event that 10155 * we didn't allocate eeprom_shadow_ram, we may not be managing 10156 * flash_bank. So it cannot be trusted and needs to be updated with 10157 * each read. 10158 */ 10159 10160 if (hw->mac_type < em_pch_spt) 10161 return -E1000_ERR_EEPROM; 10162 10163 error = em_get_software_flag(hw); 10164 if (error != E1000_SUCCESS) 10165 return error; 10166 10167 error = em_valid_nvm_bank_detect_ich8lan(hw, &flash_bank); 10168 if (error != E1000_SUCCESS) { 10169 DEBUGOUT("Could not detect valid bank, assuming bank 0\n"); 10170 flash_bank = 0; 10171 } 10172 10173 /* 10174 * Adjust offset appropriately if we're on bank 1 - adjust for word 10175 * size 10176 */ 10177 bank_offset = flash_bank * (hw->flash_bank_size * 2); 10178 10179 for (i = add = 0; i < words; i += add) { 10180 if ((offset + i) % 2) { 10181 add = 1; 10182 if (hw->eeprom_shadow_ram != NULL 10183 && hw->eeprom_shadow_ram[offset + i].modified) { 10184 data[i] = 10185 hw->eeprom_shadow_ram[offset+i].eeprom_word; 10186 continue; 10187 } 10188 act_offset = bank_offset + (offset + i - 1) * 2; 10189 } else { 10190 add = 2; 10191 if (hw->eeprom_shadow_ram != NULL 10192 && hw->eeprom_shadow_ram[offset+i].modified 10193 && hw->eeprom_shadow_ram[offset+i+1].modified) { 10194 data[i] = hw->eeprom_shadow_ram[offset+i].eeprom_word; 10195 data[i+1] = hw->eeprom_shadow_ram[offset+i+1].eeprom_word; 10196 continue; 10197 } 10198 act_offset = bank_offset + (offset + i) * 2; 10199 } 10200 error = em_read_ich8_dword(hw, act_offset, &dword); 10201 if (error != E1000_SUCCESS) 10202 break; 10203 if (hw->eeprom_shadow_ram != NULL 10204 && hw->eeprom_shadow_ram[offset+i].modified) { 10205 data[i] = hw->eeprom_shadow_ram[offset+i].eeprom_word; 10206 } else { 10207 if (add == 1) 10208 data[i] = dword >> 16; 10209 else 10210 data[i] = dword & 0xFFFFUL; 10211 } 10212 if (add == 1 || words-i == 1) 10213 continue; 10214 if (hw->eeprom_shadow_ram != NULL 10215 && hw->eeprom_shadow_ram[offset+i+1].modified) { 10216 data[i+1] = 10217 hw->eeprom_shadow_ram[offset+i+1].eeprom_word; 10218 } else { 10219 data[i+1] = dword >> 16; 10220 } 10221 } 10222 10223 em_release_software_flag(hw); 10224 10225 return error; 10226 } 10227 10228 /****************************************************************************** 10229 * Reads a 16 bit word or words from the EEPROM using the ICH8's flash access 10230 * register. 10231 * 10232 * hw - Struct containing variables accessed by shared code 10233 * offset - offset of word in the EEPROM to read 10234 * data - word read from the EEPROM 10235 * words - number of words to read 10236 *****************************************************************************/ 10237 STATIC int32_t 10238 em_read_eeprom_ich8(struct em_hw *hw, uint16_t offset, uint16_t words, 10239 uint16_t *data) 10240 { 10241 int32_t error = E1000_SUCCESS; 10242 uint32_t flash_bank = 0; 10243 uint32_t act_offset = 0; 10244 uint32_t bank_offset = 0; 10245 uint16_t word = 0; 10246 uint16_t i = 0; 10247 /* 10248 * We need to know which is the valid flash bank. In the event that 10249 * we didn't allocate eeprom_shadow_ram, we may not be managing 10250 * flash_bank. So it cannot be trusted and needs to be updated with 10251 * each read. 10252 */ 10253 10254 if (hw->mac_type >= em_pch_spt) 10255 return em_read_eeprom_spt(hw, offset, words, data); 10256 10257 error = em_get_software_flag(hw); 10258 if (error != E1000_SUCCESS) 10259 return error; 10260 10261 error = em_valid_nvm_bank_detect_ich8lan(hw, &flash_bank); 10262 if (error != E1000_SUCCESS) { 10263 DEBUGOUT("Could not detect valid bank, assuming bank 0\n"); 10264 flash_bank = 0; 10265 } 10266 10267 /* 10268 * Adjust offset appropriately if we're on bank 1 - adjust for word 10269 * size 10270 */ 10271 bank_offset = flash_bank * (hw->flash_bank_size * 2); 10272 10273 for (i = 0; i < words; i++) { 10274 if (hw->eeprom_shadow_ram != NULL && 10275 hw->eeprom_shadow_ram[offset + i].modified == TRUE) { 10276 data[i] = 10277 hw->eeprom_shadow_ram[offset + i].eeprom_word; 10278 } else { 10279 /* The NVM part needs a byte offset, hence * 2 */ 10280 act_offset = bank_offset + ((offset + i) * 2); 10281 error = em_read_ich8_word(hw, act_offset, &word); 10282 if (error != E1000_SUCCESS) 10283 break; 10284 data[i] = word; 10285 } 10286 } 10287 10288 em_release_software_flag(hw); 10289 10290 return error; 10291 } 10292 10293 /****************************************************************************** 10294 * Writes a 16 bit word or words to the EEPROM using the ICH8's flash access 10295 * register. Actually, writes are written to the shadow ram cache in the hw 10296 * structure hw->em_shadow_ram. em_commit_shadow_ram flushes this to 10297 * the NVM, which occurs when the NVM checksum is updated. 10298 * 10299 * hw - Struct containing variables accessed by shared code 10300 * offset - offset of word in the EEPROM to write 10301 * words - number of words to write 10302 * data - words to write to the EEPROM 10303 *****************************************************************************/ 10304 STATIC int32_t 10305 em_write_eeprom_ich8(struct em_hw *hw, uint16_t offset, uint16_t words, 10306 uint16_t *data) 10307 { 10308 uint32_t i = 0; 10309 int32_t error = E1000_SUCCESS; 10310 error = em_get_software_flag(hw); 10311 if (error != E1000_SUCCESS) 10312 return error; 10313 /* 10314 * A driver can write to the NVM only if it has eeprom_shadow_ram 10315 * allocated. Subsequent reads to the modified words are read from 10316 * this cached structure as well. Writes will only go into this 10317 * cached structure unless it's followed by a call to 10318 * em_update_eeprom_checksum() where it will commit the changes and 10319 * clear the "modified" field. 10320 */ 10321 if (hw->eeprom_shadow_ram != NULL) { 10322 for (i = 0; i < words; i++) { 10323 if ((offset + i) < E1000_SHADOW_RAM_WORDS) { 10324 hw->eeprom_shadow_ram[offset + i].modified = 10325 TRUE; 10326 hw->eeprom_shadow_ram[offset + i].eeprom_word = 10327 data[i]; 10328 } else { 10329 error = -E1000_ERR_EEPROM; 10330 break; 10331 } 10332 } 10333 } else { 10334 /* 10335 * Drivers have the option to not allocate eeprom_shadow_ram 10336 * as long as they don't perform any NVM writes. An attempt 10337 * in doing so will result in this error. 10338 */ 10339 error = -E1000_ERR_EEPROM; 10340 } 10341 10342 em_release_software_flag(hw); 10343 10344 return error; 10345 } 10346 10347 /****************************************************************************** 10348 * This function does initial flash setup so that a new read/write/erase cycle 10349 * can be started. 10350 * 10351 * hw - The pointer to the hw structure 10352 ****************************************************************************/ 10353 STATIC int32_t 10354 em_ich8_cycle_init(struct em_hw *hw) 10355 { 10356 union ich8_hws_flash_status hsfsts; 10357 int32_t error = E1000_ERR_EEPROM; 10358 int32_t i = 0; 10359 DEBUGFUNC("em_ich8_cycle_init"); 10360 10361 if (hw->mac_type >= em_pch_spt) 10362 hsfsts.regval = E1000_READ_ICH_FLASH_REG32(hw, 10363 ICH_FLASH_HSFSTS) & 0xFFFFUL; 10364 else 10365 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, 10366 ICH_FLASH_HSFSTS); 10367 10368 /* May be check the Flash Des Valid bit in Hw status */ 10369 if (hsfsts.hsf_status.fldesvalid == 0) { 10370 DEBUGOUT("Flash descriptor invalid. SW Sequencing must be" 10371 " used."); 10372 return error; 10373 } 10374 /* Clear FCERR in Hw status by writing 1 */ 10375 /* Clear DAEL in Hw status by writing a 1 */ 10376 hsfsts.hsf_status.flcerr = 1; 10377 hsfsts.hsf_status.dael = 1; 10378 if (hw->mac_type >= em_pch_spt) 10379 E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_HSFSTS, 10380 hsfsts.regval & 0xFFFFUL); 10381 else 10382 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, 10383 hsfsts.regval); 10384 /* 10385 * Either we should have a hardware SPI cycle in progress bit to 10386 * check against, in order to start a new cycle or FDONE bit should 10387 * be changed in the hardware so that it is 1 after hardware reset, 10388 * which can then be used as an indication whether a cycle is in 10389 * progress or has been completed .. we should also have some 10390 * software semaphore mechanism to guard FDONE or the cycle in 10391 * progress bit so that two threads access to those bits can be 10392 * sequentiallized or a way so that 2 threads dont start the cycle at 10393 * the same time 10394 */ 10395 10396 if (hsfsts.hsf_status.flcinprog == 0) { 10397 /* 10398 * There is no cycle running at present, so we can start a 10399 * cycle 10400 */ 10401 /* Begin by setting Flash Cycle Done. */ 10402 hsfsts.hsf_status.flcdone = 1; 10403 if (hw->mac_type >= em_pch_spt) 10404 E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_HSFSTS, 10405 hsfsts.regval & 0xFFFFUL); 10406 else 10407 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, 10408 hsfsts.regval); 10409 error = E1000_SUCCESS; 10410 } else { 10411 /* 10412 * otherwise poll for sometime so the current cycle has a 10413 * chance to end before giving up. 10414 */ 10415 for (i = 0; i < ICH_FLASH_COMMAND_TIMEOUT; i++) { 10416 if (hw->mac_type >= em_pch_spt) 10417 hsfsts.regval = E1000_READ_ICH_FLASH_REG32( 10418 hw, ICH_FLASH_HSFSTS) & 0xFFFFUL; 10419 else 10420 hsfsts.regval = E1000_READ_ICH_FLASH_REG16( 10421 hw, ICH_FLASH_HSFSTS); 10422 if (hsfsts.hsf_status.flcinprog == 0) { 10423 error = E1000_SUCCESS; 10424 break; 10425 } 10426 usec_delay(1); 10427 } 10428 if (error == E1000_SUCCESS) { 10429 /* 10430 * Successful in waiting for previous cycle to 10431 * timeout, now set the Flash Cycle Done. 10432 */ 10433 hsfsts.hsf_status.flcdone = 1; 10434 if (hw->mac_type >= em_pch_spt) 10435 E1000_WRITE_ICH_FLASH_REG32(hw, 10436 ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFFUL); 10437 else 10438 E1000_WRITE_ICH_FLASH_REG16(hw, 10439 ICH_FLASH_HSFSTS, hsfsts.regval); 10440 } else { 10441 DEBUGOUT("Flash controller busy, cannot get access"); 10442 } 10443 } 10444 return error; 10445 } 10446 10447 /****************************************************************************** 10448 * This function starts a flash cycle and waits for its completion 10449 * 10450 * hw - The pointer to the hw structure 10451 *****************************************************************************/ 10452 STATIC int32_t 10453 em_ich8_flash_cycle(struct em_hw *hw, uint32_t timeout) 10454 { 10455 union ich8_hws_flash_ctrl hsflctl; 10456 union ich8_hws_flash_status hsfsts; 10457 int32_t error = E1000_ERR_EEPROM; 10458 uint32_t i = 0; 10459 10460 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ 10461 if (hw->mac_type >= em_pch_spt) 10462 hsflctl.regval = E1000_READ_ICH_FLASH_REG32(hw, 10463 ICH_FLASH_HSFSTS) >> 16; 10464 else 10465 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, 10466 ICH_FLASH_HSFCTL); 10467 hsflctl.hsf_ctrl.flcgo = 1; 10468 10469 if (hw->mac_type >= em_pch_spt) 10470 E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_HSFSTS, 10471 (uint32_t)hsflctl.regval << 16); 10472 else 10473 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, 10474 hsflctl.regval); 10475 10476 /* wait till FDONE bit is set to 1 */ 10477 do { 10478 if (hw->mac_type >= em_pch_spt) 10479 hsfsts.regval = E1000_READ_ICH_FLASH_REG32(hw, 10480 ICH_FLASH_HSFSTS) & 0xFFFFUL; 10481 else 10482 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, 10483 ICH_FLASH_HSFSTS); 10484 if (hsfsts.hsf_status.flcdone == 1) 10485 break; 10486 usec_delay(1); 10487 i++; 10488 } while (i < timeout); 10489 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) { 10490 error = E1000_SUCCESS; 10491 } 10492 return error; 10493 } 10494 10495 /****************************************************************************** 10496 * Reads a byte or word from the NVM using the ICH8 flash access registers. 10497 * 10498 * hw - The pointer to the hw structure 10499 * index - The index of the byte or word to read. 10500 * size - Size of data to read, 1=byte 2=word 10501 * data - Pointer to the word to store the value read. 10502 *****************************************************************************/ 10503 STATIC int32_t 10504 em_read_ich8_data(struct em_hw *hw, uint32_t index, uint32_t size, 10505 uint16_t *data) 10506 { 10507 union ich8_hws_flash_status hsfsts; 10508 union ich8_hws_flash_ctrl hsflctl; 10509 uint32_t flash_linear_address; 10510 uint32_t flash_data = 0; 10511 int32_t error = -E1000_ERR_EEPROM; 10512 int32_t count = 0; 10513 DEBUGFUNC("em_read_ich8_data"); 10514 10515 if (size < 1 || size > 2 || data == 0x0 || 10516 index > ICH_FLASH_LINEAR_ADDR_MASK) 10517 return error; 10518 10519 flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) + 10520 hw->flash_base_addr; 10521 10522 do { 10523 usec_delay(1); 10524 /* Steps */ 10525 error = em_ich8_cycle_init(hw); 10526 if (error != E1000_SUCCESS) 10527 break; 10528 10529 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, 10530 ICH_FLASH_HSFCTL); 10531 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 10532 hsflctl.hsf_ctrl.fldbcount = size - 1; 10533 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; 10534 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, 10535 hsflctl.regval); 10536 /* 10537 * Write the last 24 bits of index into Flash Linear address 10538 * field in Flash Address 10539 */ 10540 /* TODO: TBD maybe check the index against the size of flash */ 10541 10542 E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_FADDR, 10543 flash_linear_address); 10544 10545 error = em_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT); 10546 /* 10547 * Check if FCERR is set to 1, if set to 1, clear it and try 10548 * the whole sequence a few more times, else read in (shift 10549 * in) the Flash Data0, the order is least significant byte 10550 * first msb to lsb 10551 */ 10552 if (error == E1000_SUCCESS) { 10553 flash_data = E1000_READ_ICH_FLASH_REG(hw, 10554 ICH_FLASH_FDATA0); 10555 if (size == 1) { 10556 *data = (uint8_t) (flash_data & 0x000000FF); 10557 } else if (size == 2) { 10558 *data = (uint16_t) (flash_data & 0x0000FFFF); 10559 } 10560 break; 10561 } else { 10562 /* 10563 * If we've gotten here, then things are probably 10564 * completely hosed, but if the error condition is 10565 * detected, it won't hurt to give it another 10566 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 10567 */ 10568 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, 10569 ICH_FLASH_HSFSTS); 10570 if (hsfsts.hsf_status.flcerr == 1) { 10571 /* Repeat for some time before giving up. */ 10572 continue; 10573 } else if (hsfsts.hsf_status.flcdone == 0) { 10574 DEBUGOUT("Timeout error - flash cycle did not" 10575 " complete."); 10576 break; 10577 } 10578 } 10579 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 10580 10581 return error; 10582 } 10583 10584 STATIC int32_t 10585 em_read_ich8_data32(struct em_hw *hw, uint32_t offset, uint32_t *data) 10586 { 10587 union ich8_hws_flash_status hsfsts; 10588 union ich8_hws_flash_ctrl hsflctl; 10589 uint32_t flash_linear_address; 10590 int32_t error = -E1000_ERR_EEPROM; 10591 uint32_t count = 0; 10592 DEBUGFUNC("em_read_ich8_data32"); 10593 10594 if (hw->mac_type < em_pch_spt) 10595 return error; 10596 if (offset > ICH_FLASH_LINEAR_ADDR_MASK) 10597 return error; 10598 flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & offset) + 10599 hw->flash_base_addr; 10600 10601 do { 10602 usec_delay(1); 10603 /* Steps */ 10604 error = em_ich8_cycle_init(hw); 10605 if (error != E1000_SUCCESS) 10606 break; 10607 10608 /* 32 bit accesses in SPT. */ 10609 hsflctl.regval = E1000_READ_ICH_FLASH_REG32(hw, 10610 ICH_FLASH_HSFSTS) >> 16; 10611 10612 hsflctl.hsf_ctrl.fldbcount = sizeof(uint32_t) - 1; 10613 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; 10614 10615 E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_HSFSTS, 10616 (uint32_t)hsflctl.regval << 16); 10617 /* 10618 * Write the last 24 bits of offset into Flash Linear address 10619 * field in Flash Address 10620 */ 10621 /* TODO: TBD maybe check the offset against the size of flash */ 10622 10623 E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_FADDR, 10624 flash_linear_address); 10625 10626 error = em_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT); 10627 /* 10628 * Check if FCERR is set to 1, if set to 1, clear it and try 10629 * the whole sequence a few more times, else read in (shift 10630 * in) the Flash Data0, the order is least significant byte 10631 * first msb to lsb 10632 */ 10633 if (error == E1000_SUCCESS) { 10634 (*data) = (uint32_t)E1000_READ_ICH_FLASH_REG32(hw, 10635 ICH_FLASH_FDATA0); 10636 break; 10637 } else { 10638 /* 10639 * If we've gotten here, then things are probably 10640 * completely hosed, but if the error condition is 10641 * detected, it won't hurt to give it another 10642 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 10643 */ 10644 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, 10645 ICH_FLASH_HSFSTS); 10646 if (hsfsts.hsf_status.flcerr == 1) { 10647 /* Repeat for some time before giving up. */ 10648 continue; 10649 } else if (hsfsts.hsf_status.flcdone == 0) { 10650 DEBUGOUT("Timeout error - flash cycle did not" 10651 " complete."); 10652 break; 10653 } 10654 } 10655 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 10656 10657 return error; 10658 } 10659 10660 10661 /****************************************************************************** 10662 * Writes One /two bytes to the NVM using the ICH8 flash access registers. 10663 * 10664 * hw - The pointer to the hw structure 10665 * index - The index of the byte/word to write. 10666 * size - Size of data to read, 1=byte 2=word 10667 * data - The byte(s) to write to the NVM. 10668 *****************************************************************************/ 10669 STATIC int32_t 10670 em_write_ich8_data(struct em_hw *hw, uint32_t index, uint32_t size, 10671 uint16_t data) 10672 { 10673 union ich8_hws_flash_status hsfsts; 10674 union ich8_hws_flash_ctrl hsflctl; 10675 uint32_t flash_linear_address; 10676 uint32_t flash_data = 0; 10677 int32_t error = -E1000_ERR_EEPROM; 10678 int32_t count = 0; 10679 DEBUGFUNC("em_write_ich8_data"); 10680 10681 if (hw->mac_type >= em_pch_spt) 10682 return -E1000_ERR_EEPROM; 10683 if (size < 1 || size > 2 || data > size * 0xff || 10684 index > ICH_FLASH_LINEAR_ADDR_MASK) 10685 return error; 10686 10687 flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) + 10688 hw->flash_base_addr; 10689 10690 do { 10691 usec_delay(1); 10692 /* Steps */ 10693 error = em_ich8_cycle_init(hw); 10694 if (error != E1000_SUCCESS) 10695 break; 10696 10697 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, 10698 ICH_FLASH_HSFCTL); 10699 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 10700 hsflctl.hsf_ctrl.fldbcount = size - 1; 10701 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; 10702 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, 10703 hsflctl.regval); 10704 /* 10705 * Write the last 24 bits of index into Flash Linear address 10706 * field in Flash Address 10707 */ 10708 E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_FADDR, 10709 flash_linear_address); 10710 10711 if (size == 1) 10712 flash_data = (uint32_t) data & 0x00FF; 10713 else 10714 flash_data = (uint32_t) data; 10715 10716 E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_FDATA0, flash_data); 10717 /* 10718 * check if FCERR is set to 1 , if set to 1, clear it and try 10719 * the whole sequence a few more times else done 10720 */ 10721 error = em_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT); 10722 if (error == E1000_SUCCESS) { 10723 break; 10724 } else { 10725 /* 10726 * If we're here, then things are most likely 10727 * completely hosed, but if the error condition is 10728 * detected, it won't hurt to give it another 10729 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 10730 */ 10731 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, 10732 ICH_FLASH_HSFSTS); 10733 if (hsfsts.hsf_status.flcerr == 1) { 10734 /* Repeat for some time before giving up. */ 10735 continue; 10736 } else if (hsfsts.hsf_status.flcdone == 0) { 10737 DEBUGOUT("Timeout error - flash cycle did not" 10738 " complete."); 10739 break; 10740 } 10741 } 10742 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 10743 10744 return error; 10745 } 10746 10747 /****************************************************************************** 10748 * Reads a single byte from the NVM using the ICH8 flash access registers. 10749 * 10750 * hw - pointer to em_hw structure 10751 * index - The index of the byte to read. 10752 * data - Pointer to a byte to store the value read. 10753 *****************************************************************************/ 10754 STATIC int32_t 10755 em_read_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t *data) 10756 { 10757 int32_t status = E1000_SUCCESS; 10758 uint16_t word = 0; 10759 10760 if (hw->mac_type >= em_pch_spt) 10761 return -E1000_ERR_EEPROM; 10762 else 10763 status = em_read_ich8_data(hw, index, 1, &word); 10764 if (status == E1000_SUCCESS) { 10765 *data = (uint8_t) word; 10766 } 10767 return status; 10768 } 10769 10770 /****************************************************************************** 10771 * Writes a single byte to the NVM using the ICH8 flash access registers. 10772 * Performs verification by reading back the value and then going through 10773 * a retry algorithm before giving up. 10774 * 10775 * hw - pointer to em_hw structure 10776 * index - The index of the byte to write. 10777 * byte - The byte to write to the NVM. 10778 *****************************************************************************/ 10779 STATIC int32_t 10780 em_verify_write_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t byte) 10781 { 10782 int32_t error = E1000_SUCCESS; 10783 int32_t program_retries = 0; 10784 DEBUGOUT2("Byte := %2.2X Offset := %d\n", byte, index); 10785 10786 error = em_write_ich8_byte(hw, index, byte); 10787 10788 if (error != E1000_SUCCESS) { 10789 for (program_retries = 0; program_retries < 100; 10790 program_retries++) { 10791 DEBUGOUT2("Retrying \t Byte := %2.2X Offset := %d\n", 10792 byte, index); 10793 error = em_write_ich8_byte(hw, index, byte); 10794 usec_delay(100); 10795 if (error == E1000_SUCCESS) 10796 break; 10797 } 10798 } 10799 if (program_retries == 100) 10800 error = E1000_ERR_EEPROM; 10801 10802 return error; 10803 } 10804 10805 /****************************************************************************** 10806 * Writes a single byte to the NVM using the ICH8 flash access registers. 10807 * 10808 * hw - pointer to em_hw structure 10809 * index - The index of the byte to read. 10810 * data - The byte to write to the NVM. 10811 *****************************************************************************/ 10812 STATIC int32_t 10813 em_write_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t data) 10814 { 10815 int32_t status = E1000_SUCCESS; 10816 uint16_t word = (uint16_t) data; 10817 status = em_write_ich8_data(hw, index, 1, word); 10818 10819 return status; 10820 } 10821 10822 /****************************************************************************** 10823 * Reads a dword from the NVM using the ICH8 flash access registers. 10824 * 10825 * hw - pointer to em_hw structure 10826 * index - The starting BYTE index of the word to read. 10827 * data - Pointer to a word to store the value read. 10828 *****************************************************************************/ 10829 STATIC int32_t 10830 em_read_ich8_dword(struct em_hw *hw, uint32_t index, uint32_t *data) 10831 { 10832 int32_t status = E1000_SUCCESS; 10833 status = em_read_ich8_data32(hw, index, data); 10834 return status; 10835 } 10836 10837 /****************************************************************************** 10838 * Reads a word from the NVM using the ICH8 flash access registers. 10839 * 10840 * hw - pointer to em_hw structure 10841 * index - The starting byte index of the word to read. 10842 * data - Pointer to a word to store the value read. 10843 *****************************************************************************/ 10844 STATIC int32_t 10845 em_read_ich8_word(struct em_hw *hw, uint32_t index, uint16_t *data) 10846 { 10847 int32_t status = E1000_SUCCESS; 10848 status = em_read_ich8_data(hw, index, 2, data); 10849 return status; 10850 } 10851 10852 /****************************************************************************** 10853 * Erases the bank specified. Each bank may be a 4, 8 or 64k block. Banks are 0 10854 * based. 10855 * 10856 * hw - pointer to em_hw structure 10857 * bank - 0 for first bank, 1 for second bank 10858 * 10859 * Note that this function may actually erase as much as 8 or 64 KBytes. The 10860 * amount of NVM used in each bank is a *minimum* of 4 KBytes, but in fact the 10861 * bank size may be 4, 8 or 64 KBytes 10862 *****************************************************************************/ 10863 int32_t 10864 em_erase_ich8_4k_segment(struct em_hw *hw, uint32_t bank) 10865 { 10866 union ich8_hws_flash_status hsfsts; 10867 union ich8_hws_flash_ctrl hsflctl; 10868 uint32_t flash_linear_address; 10869 int32_t count = 0; 10870 int32_t error = E1000_ERR_EEPROM; 10871 int32_t iteration; 10872 int32_t sub_sector_size = 0; 10873 int32_t bank_size; 10874 int32_t j = 0; 10875 int32_t error_flag = 0; 10876 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 10877 /* 10878 * Determine HW Sector size: Read BERASE bits of Hw flash Status 10879 * register 10880 */ 10881 /* 10882 * 00: The Hw sector is 256 bytes, hence we need to erase 16 10883 * consecutive sectors. The start index for the nth Hw sector can be 10884 * calculated as bank * 4096 + n * 256 01: The Hw sector is 4K bytes, 10885 * hence we need to erase 1 sector. The start index for the nth Hw 10886 * sector can be calculated as bank * 4096 10: The HW sector is 8K 10887 * bytes 11: The Hw sector size is 64K bytes 10888 */ 10889 if (hsfsts.hsf_status.berasesz == 0x0) { 10890 /* Hw sector size 256 */ 10891 sub_sector_size = ICH_FLASH_SEG_SIZE_256; 10892 bank_size = ICH_FLASH_SECTOR_SIZE; 10893 iteration = ICH_FLASH_SECTOR_SIZE / ICH_FLASH_SEG_SIZE_256; 10894 } else if (hsfsts.hsf_status.berasesz == 0x1) { 10895 bank_size = ICH_FLASH_SEG_SIZE_4K; 10896 iteration = 1; 10897 } else if (hsfsts.hsf_status.berasesz == 0x2) { 10898 if (hw->mac_type == em_ich9lan) { 10899 uint32_t gfpreg, sector_base_addr, sector_end_addr; 10900 gfpreg = E1000_READ_ICH_FLASH_REG(hw, 10901 ICH_FLASH_GFPREG); 10902 /* 10903 * sector_X_addr is a "sector"-aligned address (4096 bytes) 10904 * Add 1 to sector_end_addr since this sector is included in 10905 * the overall size. 10906 */ 10907 sector_base_addr = gfpreg & ICH_GFPREG_BASE_MASK; 10908 sector_end_addr = 10909 ((gfpreg >> 16) & ICH_GFPREG_BASE_MASK) + 1; 10910 10911 /* 10912 * find total size of the NVM, then cut in half since the total 10913 * size represents two separate NVM banks. 10914 */ 10915 bank_size = (sector_end_addr - sector_base_addr) 10916 << ICH_FLASH_SECT_ADDR_SHIFT; 10917 bank_size /= 2; 10918 /* Word align */ 10919 bank_size = 10920 (bank_size / sizeof(uint16_t)) * sizeof(uint16_t); 10921 10922 sub_sector_size = ICH_FLASH_SEG_SIZE_8K; 10923 iteration = bank_size / ICH_FLASH_SEG_SIZE_8K; 10924 } else { 10925 return error; 10926 } 10927 } else if (hsfsts.hsf_status.berasesz == 0x3) { 10928 bank_size = ICH_FLASH_SEG_SIZE_64K; 10929 iteration = 1; 10930 } else { 10931 return error; 10932 } 10933 10934 for (j = 0; j < iteration; j++) { 10935 do { 10936 count++; 10937 /* Steps */ 10938 error = em_ich8_cycle_init(hw); 10939 if (error != E1000_SUCCESS) { 10940 error_flag = 1; 10941 break; 10942 } 10943 /* 10944 * Write a value 11 (block Erase) in Flash Cycle 10945 * field in Hw flash Control 10946 */ 10947 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, 10948 ICH_FLASH_HSFCTL); 10949 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE; 10950 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, 10951 hsflctl.regval); 10952 /* 10953 * Write the last 24 bits of an index within the 10954 * block into Flash Linear address field in Flash 10955 * Address. This probably needs to be calculated 10956 * here based off the on-chip erase sector size and 10957 * the software bank size (4, 8 or 64 KBytes) 10958 */ 10959 flash_linear_address = 10960 bank * bank_size + j * sub_sector_size; 10961 flash_linear_address += hw->flash_base_addr; 10962 flash_linear_address &= ICH_FLASH_LINEAR_ADDR_MASK; 10963 10964 E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_FADDR, 10965 flash_linear_address); 10966 10967 error = 10968 em_ich8_flash_cycle(hw, ICH_FLASH_ERASE_TIMEOUT); 10969 /* 10970 * Check if FCERR is set to 1. If 1, clear it and 10971 * try the whole sequence a few more times else Done 10972 */ 10973 if (error == E1000_SUCCESS) { 10974 break; 10975 } else { 10976 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, 10977 ICH_FLASH_HSFSTS); 10978 if (hsfsts.hsf_status.flcerr == 1) { 10979 /* 10980 * repeat for some time before giving 10981 * up 10982 */ 10983 continue; 10984 } else if (hsfsts.hsf_status.flcdone == 0) { 10985 error_flag = 1; 10986 break; 10987 } 10988 } 10989 } while ((count < ICH_FLASH_CYCLE_REPEAT_COUNT) && !error_flag); 10990 if (error_flag == 1) 10991 break; 10992 } 10993 if (error_flag != 1) 10994 error = E1000_SUCCESS; 10995 return error; 10996 } 10997 10998 /****************************************************************************** 10999 * Reads 16-bit words from the OTP. Return error when the word is not 11000 * stored in OTP. 11001 * 11002 * hw - Struct containing variables accessed by shared code 11003 * offset - offset of word in the OTP to read 11004 * data - word read from the OTP 11005 * words - number of words to read 11006 *****************************************************************************/ 11007 STATIC int32_t 11008 em_read_invm_i210(struct em_hw *hw, uint16_t offset, uint16_t words, 11009 uint16_t *data) 11010 { 11011 int32_t ret_val = E1000_SUCCESS; 11012 11013 switch (offset) 11014 { 11015 case EEPROM_MAC_ADDR_WORD0: 11016 case EEPROM_MAC_ADDR_WORD1: 11017 case EEPROM_MAC_ADDR_WORD2: 11018 /* Generate random MAC address if there's none. */ 11019 ret_val = em_read_invm_word_i210(hw, offset, data); 11020 if (ret_val != E1000_SUCCESS) { 11021 DEBUGOUT("MAC Addr not found in iNVM\n"); 11022 *data = 0xFFFF; 11023 ret_val = E1000_SUCCESS; 11024 } 11025 break; 11026 case EEPROM_INIT_CONTROL2_REG: 11027 ret_val = em_read_invm_word_i210(hw, offset, data); 11028 if (ret_val != E1000_SUCCESS) { 11029 *data = NVM_INIT_CTRL_2_DEFAULT_I211; 11030 ret_val = E1000_SUCCESS; 11031 } 11032 break; 11033 case EEPROM_INIT_CONTROL4_REG: 11034 ret_val = em_read_invm_word_i210(hw, offset, data); 11035 if (ret_val != E1000_SUCCESS) { 11036 *data = NVM_INIT_CTRL_4_DEFAULT_I211; 11037 ret_val = E1000_SUCCESS; 11038 } 11039 break; 11040 case EEPROM_LED_1_CFG: 11041 ret_val = em_read_invm_word_i210(hw, offset, data); 11042 if (ret_val != E1000_SUCCESS) { 11043 *data = NVM_LED_1_CFG_DEFAULT_I211; 11044 ret_val = E1000_SUCCESS; 11045 } 11046 break; 11047 case EEPROM_LED_0_2_CFG: 11048 ret_val = em_read_invm_word_i210(hw, offset, data); 11049 if (ret_val != E1000_SUCCESS) { 11050 *data = NVM_LED_0_2_CFG_DEFAULT_I211; 11051 ret_val = E1000_SUCCESS; 11052 } 11053 break; 11054 case EEPROM_ID_LED_SETTINGS: 11055 ret_val = em_read_invm_word_i210(hw, offset, data); 11056 if (ret_val != E1000_SUCCESS) { 11057 *data = ID_LED_RESERVED_FFFF; 11058 ret_val = E1000_SUCCESS; 11059 } 11060 break; 11061 default: 11062 DEBUGOUT1("NVM word 0x%02x is not mapped.\n", offset); 11063 *data = NVM_RESERVED_WORD; 11064 break; 11065 } 11066 11067 return ret_val; 11068 } 11069 11070 /****************************************************************************** 11071 * Reads 16-bit words from the OTP. Return error when the word is not 11072 * stored in OTP. 11073 * 11074 * hw - Struct containing variables accessed by shared code 11075 * offset - offset of word in the OTP to read 11076 * data - word read from the OTP 11077 *****************************************************************************/ 11078 STATIC int32_t 11079 em_read_invm_word_i210(struct em_hw *hw, uint16_t address, uint16_t *data) 11080 { 11081 int32_t error = -E1000_NOT_IMPLEMENTED; 11082 uint32_t invm_dword; 11083 uint16_t i; 11084 uint8_t record_type, word_address; 11085 11086 for (i = 0; i < INVM_SIZE; i++) { 11087 invm_dword = EM_READ_REG(hw, E1000_INVM_DATA_REG(i)); 11088 /* Get record type */ 11089 record_type = INVM_DWORD_TO_RECORD_TYPE(invm_dword); 11090 if (record_type == INVM_UNINITIALIZED_STRUCTURE) 11091 break; 11092 if (record_type == INVM_CSR_AUTOLOAD_STRUCTURE) 11093 i += INVM_CSR_AUTOLOAD_DATA_SIZE_IN_DWORDS; 11094 if (record_type == INVM_RSA_KEY_SHA256_STRUCTURE) 11095 i += INVM_RSA_KEY_SHA256_DATA_SIZE_IN_DWORDS; 11096 if (record_type == INVM_WORD_AUTOLOAD_STRUCTURE) { 11097 word_address = INVM_DWORD_TO_WORD_ADDRESS(invm_dword); 11098 if (word_address == address) { 11099 *data = INVM_DWORD_TO_WORD_DATA(invm_dword); 11100 error = E1000_SUCCESS; 11101 break; 11102 } 11103 } 11104 } 11105 11106 return error; 11107 } 11108 11109 STATIC int32_t 11110 em_init_lcd_from_nvm_config_region(struct em_hw *hw, uint32_t cnf_base_addr, 11111 uint32_t cnf_size) 11112 { 11113 uint32_t ret_val = E1000_SUCCESS; 11114 uint16_t word_addr, reg_data, reg_addr; 11115 uint16_t i; 11116 /* cnf_base_addr is in DWORD */ 11117 word_addr = (uint16_t) (cnf_base_addr << 1); 11118 11119 /* cnf_size is returned in size of dwords */ 11120 for (i = 0; i < cnf_size; i++) { 11121 ret_val = 11122 em_read_eeprom(hw, (word_addr + i * 2), 1, ®_data); 11123 if (ret_val) 11124 return ret_val; 11125 11126 ret_val = 11127 em_read_eeprom(hw, (word_addr + i * 2 + 1), 1, ®_addr); 11128 if (ret_val) 11129 return ret_val; 11130 11131 ret_val = em_get_software_flag(hw); 11132 if (ret_val != E1000_SUCCESS) 11133 return ret_val; 11134 11135 ret_val = 11136 em_write_phy_reg_ex(hw, (uint32_t) reg_addr, reg_data); 11137 11138 em_release_software_flag(hw); 11139 } 11140 11141 return ret_val; 11142 } 11143 11144 /****************************************************************************** 11145 * This function initializes the PHY from the NVM on ICH8 platforms. This 11146 * is needed due to an issue where the NVM configuration is not properly 11147 * autoloaded after power transitions. Therefore, after each PHY reset, we 11148 * will load the configuration data out of the NVM manually. 11149 * 11150 * hw: Struct containing variables accessed by shared code 11151 *****************************************************************************/ 11152 STATIC int32_t 11153 em_init_lcd_from_nvm(struct em_hw *hw) 11154 { 11155 uint32_t reg_data, cnf_base_addr, cnf_size, ret_val, loop, sw_cfg_mask; 11156 if (hw->phy_type != em_phy_igp_3) 11157 return E1000_SUCCESS; 11158 11159 /* Check if SW needs configure the PHY */ 11160 if (hw->device_id == E1000_DEV_ID_ICH8_IGP_M_AMT || 11161 hw->device_id == E1000_DEV_ID_ICH8_IGP_M || 11162 hw->mac_type == em_pchlan || 11163 hw->mac_type == em_pch2lan || 11164 hw->mac_type == em_pch_lpt || 11165 hw->mac_type == em_pch_spt || 11166 hw->mac_type == em_pch_cnp || 11167 hw->mac_type == em_pch_tgp || 11168 hw->mac_type == em_pch_adp) 11169 sw_cfg_mask = FEXTNVM_SW_CONFIG_ICH8M; 11170 else 11171 sw_cfg_mask = FEXTNVM_SW_CONFIG; 11172 11173 reg_data = E1000_READ_REG(hw, FEXTNVM); 11174 if (!(reg_data & sw_cfg_mask)) 11175 return E1000_SUCCESS; 11176 11177 /* Wait for basic configuration completes before proceeding */ 11178 loop = 0; 11179 do { 11180 reg_data = 11181 E1000_READ_REG(hw, STATUS) & E1000_STATUS_LAN_INIT_DONE; 11182 usec_delay(100); 11183 loop++; 11184 } while ((!reg_data) && (loop < 50)); 11185 11186 /* Clear the Init Done bit for the next init event */ 11187 reg_data = E1000_READ_REG(hw, STATUS); 11188 reg_data &= ~E1000_STATUS_LAN_INIT_DONE; 11189 E1000_WRITE_REG(hw, STATUS, reg_data); 11190 /* 11191 * Make sure HW does not configure LCD from PHY extended 11192 * configuration before SW configuration 11193 */ 11194 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL); 11195 if ((reg_data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) == 0x0000) { 11196 reg_data = E1000_READ_REG(hw, EXTCNF_SIZE); 11197 cnf_size = reg_data & E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH; 11198 cnf_size >>= 16; 11199 if (cnf_size) { 11200 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL); 11201 cnf_base_addr = reg_data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER; 11202 /* cnf_base_addr is in DWORD */ 11203 cnf_base_addr >>= 16; 11204 11205 /* Configure LCD from extended configuration region. */ 11206 ret_val = em_init_lcd_from_nvm_config_region(hw, 11207 cnf_base_addr, cnf_size); 11208 if (ret_val) 11209 return ret_val; 11210 } 11211 } 11212 return E1000_SUCCESS; 11213 } 11214 11215 /****************************************************************************** 11216 * em_set_pciex_completion_timeout - set pci-e completion timeout 11217 * 11218 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms, 11219 * however the hardware default for these parts is 500us to 1ms which is less 11220 * than the 10ms recommended by the pci-e spec. To address this we need to 11221 * increase the value to either 10ms to 200ms for capability version 1 config, 11222 * or 16ms to 55ms for version 2. 11223 * 11224 * * hw - pointer to em_hw structure 11225 *****************************************************************************/ 11226 int32_t 11227 em_set_pciex_completion_timeout(struct em_hw *hw) 11228 { 11229 uint32_t gcr = E1000_READ_REG(hw, GCR); 11230 int32_t ret_val = E1000_SUCCESS; 11231 11232 /* Only take action if timeout value is not set by system BIOS */ 11233 if (gcr & E1000_GCR_CMPL_TMOUT_MASK) 11234 goto out; 11235 11236 DEBUGOUT("PCIe completion timeout not set by system BIOS."); 11237 11238 /* 11239 * If capabilities version is type 1 we can write the 11240 * timeout of 10ms to 200ms through the GCR register 11241 */ 11242 11243 if (!(gcr & E1000_GCR_CAP_VER2)) { 11244 gcr |= E1000_GCR_CMPL_TMOUT_10ms; 11245 DEBUGOUT("PCIe capability version 1 detected, setting \ 11246 completion timeout to 10ms."); 11247 goto out; 11248 } 11249 11250 /* 11251 * For version 2 capabilities we need to write the config space 11252 * directly in order to set the completion timeout value for 11253 * 16ms to 55ms 11254 * 11255 * XXX: Implement em_*_pcie_cap_reg() first. 11256 */ 11257 #if 0 11258 ret_val = em_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 11259 &pciex_devctl2); 11260 11261 if (ret_val) 11262 goto out; 11263 11264 pciex_devctl2 |= PCIE_DEVICE_CONTROL2_16ms; 11265 11266 ret_val = em_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 11267 &pciex_devctl2); 11268 #endif 11269 11270 out: 11271 11272 /* Disable completion timeout resend */ 11273 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND; 11274 11275 DEBUGOUT("PCIe completion timeout resend disabled."); 11276 11277 E1000_WRITE_REG(hw, GCR, gcr); 11278 return ret_val; 11279 } 11280 11281 /*************************************************************************** 11282 * Set slow MDIO access mode 11283 ***************************************************************************/ 11284 static int32_t 11285 em_set_mdio_slow_mode_hv(struct em_hw *hw) 11286 { 11287 int32_t ret_val; 11288 uint16_t data; 11289 DEBUGFUNC("em_set_mdio_slow_mode_hv"); 11290 11291 ret_val = em_read_phy_reg(hw, HV_KMRN_MODE_CTRL, &data); 11292 if (ret_val) 11293 return ret_val; 11294 11295 data |= HV_KMRN_MDIO_SLOW; 11296 11297 ret_val = em_write_phy_reg(hw, HV_KMRN_MODE_CTRL, data); 11298 11299 return ret_val; 11300 } 11301 11302 /*************************************************************************** 11303 * A series of Phy workarounds to be done after every PHY reset. 11304 ***************************************************************************/ 11305 int32_t 11306 em_hv_phy_workarounds_ich8lan(struct em_hw *hw) 11307 { 11308 int32_t ret_val = E1000_SUCCESS; 11309 uint16_t phy_data; 11310 uint16_t swfw; 11311 DEBUGFUNC("em_hv_phy_workarounds_ich8lan"); 11312 11313 if (hw->mac_type != em_pchlan) 11314 goto out; 11315 11316 swfw = E1000_SWFW_PHY0_SM; 11317 11318 /* Set MDIO slow mode before any other MDIO access */ 11319 if (hw->phy_type == em_phy_82577 || 11320 hw->phy_type == em_phy_82578) { 11321 ret_val = em_set_mdio_slow_mode_hv(hw); 11322 if (ret_val) 11323 goto out; 11324 } 11325 11326 /* Hanksville M Phy init for IEEE. */ 11327 if ((hw->revision_id == 2) && 11328 (hw->phy_type == em_phy_82577) && 11329 ((hw->phy_revision == 2) || (hw->phy_revision == 3))) { 11330 em_write_phy_reg(hw, 0x10, 0x8823); 11331 em_write_phy_reg(hw, 0x11, 0x0018); 11332 em_write_phy_reg(hw, 0x10, 0x8824); 11333 em_write_phy_reg(hw, 0x11, 0x0016); 11334 em_write_phy_reg(hw, 0x10, 0x8825); 11335 em_write_phy_reg(hw, 0x11, 0x001A); 11336 em_write_phy_reg(hw, 0x10, 0x888C); 11337 em_write_phy_reg(hw, 0x11, 0x0007); 11338 em_write_phy_reg(hw, 0x10, 0x888D); 11339 em_write_phy_reg(hw, 0x11, 0x0007); 11340 em_write_phy_reg(hw, 0x10, 0x888E); 11341 em_write_phy_reg(hw, 0x11, 0x0007); 11342 em_write_phy_reg(hw, 0x10, 0x8827); 11343 em_write_phy_reg(hw, 0x11, 0x0001); 11344 em_write_phy_reg(hw, 0x10, 0x8835); 11345 em_write_phy_reg(hw, 0x11, 0x0001); 11346 em_write_phy_reg(hw, 0x10, 0x8834); 11347 em_write_phy_reg(hw, 0x11, 0x0001); 11348 em_write_phy_reg(hw, 0x10, 0x8833); 11349 em_write_phy_reg(hw, 0x11, 0x0002); 11350 } 11351 11352 if (((hw->phy_type == em_phy_82577) && 11353 ((hw->phy_revision == 1) || (hw->phy_revision == 2))) || 11354 ((hw->phy_type == em_phy_82578) && (hw->phy_revision == 1))) { 11355 /* Disable generation of early preamble */ 11356 ret_val = em_write_phy_reg(hw, PHY_REG(769, 25), 0x4431); 11357 if (ret_val) 11358 goto out; 11359 11360 /* Preamble tuning for SSC */ 11361 ret_val = em_write_phy_reg(hw, PHY_REG(770, 16), 0xA204); 11362 if (ret_val) 11363 goto out; 11364 } 11365 11366 if (hw->phy_type == em_phy_82578) { 11367 /* 11368 * Return registers to default by doing a soft reset then 11369 * writing 0x3140 to the control register. 11370 */ 11371 if (hw->phy_revision < 2) { 11372 em_phy_reset(hw); 11373 ret_val = em_write_phy_reg(hw, PHY_CTRL, 0x3140); 11374 } 11375 } 11376 11377 if ((hw->revision_id == 2) && 11378 (hw->phy_type == em_phy_82577) && 11379 ((hw->phy_revision == 2) || (hw->phy_revision == 3))) { 11380 /* 11381 * Workaround for OEM (GbE) not operating after reset - 11382 * restart AN (twice) 11383 */ 11384 ret_val = em_write_phy_reg(hw, PHY_REG(0, 25), 0x0400); 11385 if (ret_val) 11386 goto out; 11387 ret_val = em_write_phy_reg(hw, PHY_REG(0, 25), 0x0400); 11388 if (ret_val) 11389 goto out; 11390 } 11391 11392 /* Select page 0 */ 11393 ret_val = em_swfw_sync_acquire(hw, swfw); 11394 if (ret_val) 11395 goto out; 11396 11397 hw->phy_addr = 1; 11398 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT, 0); 11399 em_swfw_sync_release(hw, swfw); 11400 if (ret_val) 11401 goto out; 11402 11403 /* Workaround for link disconnects on a busy hub in half duplex */ 11404 ret_val = em_read_phy_reg(hw, 11405 PHY_REG(BM_PORT_CTRL_PAGE, 17), 11406 &phy_data); 11407 if (ret_val) 11408 goto release; 11409 ret_val = em_write_phy_reg(hw, 11410 PHY_REG(BM_PORT_CTRL_PAGE, 17), 11411 phy_data & 0x00FF); 11412 release: 11413 out: 11414 return ret_val; 11415 } 11416 11417 11418 /*************************************************************************** 11419 * Si workaround 11420 * 11421 * This function works around a Si bug where the link partner can get 11422 * a link up indication before the PHY does. If small packets are sent 11423 * by the link partner they can be placed in the packet buffer without 11424 * being properly accounted for by the PHY and will stall preventing 11425 * further packets from being received. The workaround is to clear the 11426 * packet buffer after the PHY detects link up. 11427 ***************************************************************************/ 11428 int32_t 11429 em_link_stall_workaround_hv(struct em_hw *hw) 11430 { 11431 int32_t ret_val = E1000_SUCCESS; 11432 uint16_t phy_data; 11433 11434 if (hw->phy_type != em_phy_82578) 11435 goto out; 11436 11437 /* Do not apply workaround if in PHY loopback bit 14 set */ 11438 em_read_phy_reg(hw, PHY_CTRL, &phy_data); 11439 if (phy_data & E1000_PHY_CTRL_LOOPBACK) 11440 goto out; 11441 11442 /* check if link is up and at 1Gbps */ 11443 ret_val = em_read_phy_reg(hw, BM_CS_STATUS, &phy_data); 11444 if (ret_val) 11445 goto out; 11446 11447 phy_data &= BM_CS_STATUS_LINK_UP | 11448 BM_CS_STATUS_RESOLVED | 11449 BM_CS_STATUS_SPEED_MASK; 11450 11451 if (phy_data != (BM_CS_STATUS_LINK_UP | 11452 BM_CS_STATUS_RESOLVED | 11453 BM_CS_STATUS_SPEED_1000)) 11454 goto out; 11455 11456 msec_delay(200); 11457 11458 /* flush the packets in the fifo buffer */ 11459 ret_val = em_write_phy_reg(hw, HV_MUX_DATA_CTRL, 11460 HV_MUX_DATA_CTRL_GEN_TO_MAC | HV_MUX_DATA_CTRL_FORCE_SPEED); 11461 if (ret_val) 11462 goto out; 11463 11464 ret_val = em_write_phy_reg(hw, HV_MUX_DATA_CTRL, 11465 HV_MUX_DATA_CTRL_GEN_TO_MAC); 11466 11467 out: 11468 return ret_val; 11469 } 11470 11471 /**************************************************************************** 11472 * K1 Si workaround 11473 * 11474 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning 11475 * from a lower speed. This workaround disables K1 whenever link is at 1Gig. 11476 * If link is down, the function will restore the default K1 setting located 11477 * in the NVM. 11478 ****************************************************************************/ 11479 int32_t 11480 em_k1_gig_workaround_hv(struct em_hw *hw, boolean_t link) 11481 { 11482 int32_t ret_val; 11483 uint16_t phy_data; 11484 boolean_t k1_enable; 11485 11486 DEBUGFUNC("em_k1_gig_workaround_hv"); 11487 11488 if (hw->mac_type != em_pchlan) 11489 return E1000_SUCCESS; 11490 11491 ret_val = em_read_eeprom_ich8(hw, E1000_NVM_K1_CONFIG, 1, &phy_data); 11492 if (ret_val) 11493 return ret_val; 11494 11495 k1_enable = phy_data & E1000_NVM_K1_ENABLE ? TRUE : FALSE; 11496 11497 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */ 11498 if (link) { 11499 if (hw->phy_type == em_phy_82578) { 11500 ret_val = em_read_phy_reg(hw, BM_CS_STATUS, 11501 &phy_data); 11502 if (ret_val) 11503 return ret_val; 11504 11505 phy_data &= BM_CS_STATUS_LINK_UP | 11506 BM_CS_STATUS_RESOLVED | 11507 BM_CS_STATUS_SPEED_MASK; 11508 11509 if (phy_data == (BM_CS_STATUS_LINK_UP | 11510 BM_CS_STATUS_RESOLVED | 11511 BM_CS_STATUS_SPEED_1000)) 11512 k1_enable = FALSE; 11513 } 11514 11515 if (hw->phy_type == em_phy_82577) { 11516 ret_val = em_read_phy_reg(hw, HV_M_STATUS, 11517 &phy_data); 11518 if (ret_val) 11519 return ret_val; 11520 11521 phy_data &= HV_M_STATUS_LINK_UP | 11522 HV_M_STATUS_AUTONEG_COMPLETE | 11523 HV_M_STATUS_SPEED_MASK; 11524 11525 if (phy_data == (HV_M_STATUS_LINK_UP | 11526 HV_M_STATUS_AUTONEG_COMPLETE | 11527 HV_M_STATUS_SPEED_1000)) 11528 k1_enable = FALSE; 11529 } 11530 11531 /* Link stall fix for link up */ 11532 ret_val = em_write_phy_reg(hw, PHY_REG(770, 19), 11533 0x0100); 11534 if (ret_val) 11535 return ret_val; 11536 11537 } else { 11538 /* Link stall fix for link down */ 11539 ret_val = em_write_phy_reg(hw, PHY_REG(770, 19), 11540 0x4100); 11541 if (ret_val) 11542 return ret_val; 11543 } 11544 11545 ret_val = em_configure_k1_ich8lan(hw, k1_enable); 11546 11547 return ret_val; 11548 } 11549 11550 /* Workaround to set the K1 beacon duration for 82579 parts */ 11551 int32_t 11552 em_k1_workaround_lv(struct em_hw *hw) 11553 { 11554 int32_t ret_val; 11555 uint16_t phy_data; 11556 uint32_t mac_reg; 11557 11558 ret_val = em_read_phy_reg(hw, BM_CS_STATUS, &phy_data); 11559 if (ret_val) 11560 return ret_val; 11561 11562 if ((phy_data & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) 11563 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) { 11564 mac_reg = E1000_READ_REG(hw, FEXTNVM4); 11565 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK; 11566 11567 if (phy_data & HV_M_STATUS_SPEED_1000) 11568 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC; 11569 else 11570 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC; 11571 11572 E1000_WRITE_REG(hw, FEXTNVM4, mac_reg); 11573 } 11574 11575 return E1000_SUCCESS; 11576 } 11577 11578 /** 11579 * em_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP 11580 * 11581 * When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications 11582 * preventing further DMA write requests. Workaround the issue by disabling 11583 * the de-assertion of the clock request when in 1Gbps mode. 11584 * Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link 11585 * speeds in order to avoid Tx hangs. 11586 **/ 11587 int32_t 11588 em_k1_workaround_lpt_lp(struct em_hw *hw, boolean_t link) 11589 { 11590 uint32_t fextnvm6 = E1000_READ_REG(hw, FEXTNVM6); 11591 uint32_t status = E1000_READ_REG(hw, STATUS); 11592 int32_t ret_val = E1000_SUCCESS; 11593 uint16_t reg; 11594 11595 if (link && (status & E1000_STATUS_SPEED_1000)) { 11596 ret_val = em_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 11597 ®); 11598 if (ret_val) 11599 return ret_val; 11600 11601 ret_val = em_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 11602 reg & ~E1000_KMRNCTRLSTA_K1_ENABLE); 11603 if (ret_val) 11604 return ret_val; 11605 11606 usec_delay(10); 11607 11608 E1000_WRITE_REG(hw, FEXTNVM6, 11609 fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK); 11610 11611 ret_val = em_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 11612 reg); 11613 } else { 11614 /* clear FEXTNVM6 bit 8 on link down or 10/100 */ 11615 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK; 11616 11617 if (!link || ((status & E1000_STATUS_SPEED_100) && 11618 (status & E1000_STATUS_FD))) 11619 goto update_fextnvm6; 11620 11621 ret_val = em_read_phy_reg(hw, I217_INBAND_CTRL, ®); 11622 if (ret_val) 11623 return ret_val; 11624 11625 /* Clear link status transmit timeout */ 11626 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK; 11627 11628 if (status & E1000_STATUS_SPEED_100) { 11629 /* Set inband Tx timeout to 5x10us for 100Half */ 11630 reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT; 11631 11632 /* Do not extend the K1 entry latency for 100Half */ 11633 fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION; 11634 } else { 11635 /* Set inband Tx timeout to 50x10us for 10Full/Half */ 11636 reg |= 50 << 11637 I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT; 11638 11639 /* Extend the K1 entry latency for 10 Mbps */ 11640 fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION; 11641 } 11642 11643 ret_val = em_write_phy_reg(hw, I217_INBAND_CTRL, reg); 11644 if (ret_val) 11645 return ret_val; 11646 11647 update_fextnvm6: 11648 E1000_WRITE_REG(hw, FEXTNVM6, fextnvm6); 11649 } 11650 11651 return ret_val; 11652 11653 } 11654 11655 11656 /*************************************************************************** 11657 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware 11658 * @hw: pointer to the HW structure 11659 * @gate: boolean set to TRUE to gate, FALSE to ungate 11660 * 11661 * Gate/ungate the automatic PHY configuration via hardware; perform 11662 * the configuration via software instead. 11663 ***************************************************************************/ 11664 void 11665 em_gate_hw_phy_config_ich8lan(struct em_hw *hw, boolean_t gate) 11666 { 11667 uint32_t extcnf_ctrl; 11668 11669 DEBUGFUNC("em_gate_hw_phy_config_ich8lan"); 11670 11671 if (hw->mac_type != em_pch2lan) 11672 return; 11673 11674 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 11675 11676 if (gate) 11677 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG; 11678 else 11679 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG; 11680 11681 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); 11682 } 11683 11684 /*************************************************************************** 11685 * Configure K1 power state 11686 * 11687 * Configure the K1 power state based on the provided parameter. 11688 * Assumes semaphore already acquired. 11689 * 11690 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 11691 ***************************************************************************/ 11692 int32_t 11693 em_configure_k1_ich8lan(struct em_hw *hw, boolean_t k1_enable) 11694 { 11695 int32_t ret_val = E1000_SUCCESS; 11696 uint32_t ctrl_reg = 0; 11697 uint32_t ctrl_ext = 0; 11698 uint32_t reg = 0; 11699 uint16_t kmrn_reg = 0; 11700 11701 ret_val = em_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 11702 &kmrn_reg); 11703 if (ret_val) 11704 goto out; 11705 11706 if (k1_enable) 11707 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE; 11708 else 11709 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE; 11710 11711 ret_val = em_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 11712 kmrn_reg); 11713 if (ret_val) 11714 goto out; 11715 11716 usec_delay(20); 11717 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 11718 ctrl_reg = E1000_READ_REG(hw, CTRL); 11719 11720 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 11721 reg |= E1000_CTRL_FRCSPD; 11722 E1000_WRITE_REG(hw, CTRL, reg); 11723 11724 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS); 11725 usec_delay(20); 11726 E1000_WRITE_REG(hw, CTRL, ctrl_reg); 11727 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 11728 usec_delay(20); 11729 11730 out: 11731 return ret_val; 11732 } 11733 11734 /*************************************************************************** 11735 * em_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be 11736 * done after every PHY reset. 11737 ***************************************************************************/ 11738 int32_t 11739 em_lv_phy_workarounds_ich8lan(struct em_hw *hw) 11740 { 11741 int32_t ret_val = E1000_SUCCESS; 11742 uint16_t swfw; 11743 11744 DEBUGFUNC("e1000_lv_phy_workarounds_ich8lan"); 11745 11746 if (hw->mac_type != em_pch2lan) 11747 goto out; 11748 11749 /* Set MDIO slow mode before any other MDIO access */ 11750 ret_val = em_set_mdio_slow_mode_hv(hw); 11751 11752 swfw = E1000_SWFW_PHY0_SM; 11753 ret_val = em_swfw_sync_acquire(hw, swfw); 11754 if (ret_val) 11755 goto out; 11756 ret_val = em_write_phy_reg(hw, I82579_EMI_ADDR, 11757 I82579_MSE_THRESHOLD); 11758 if (ret_val) 11759 goto release; 11760 /* set MSE higher to enable link to stay up when noise is high */ 11761 ret_val = em_write_phy_reg(hw, I82579_EMI_DATA, 11762 0x0034); 11763 if (ret_val) 11764 goto release; 11765 ret_val = em_write_phy_reg(hw, I82579_EMI_ADDR, 11766 I82579_MSE_LINK_DOWN); 11767 if (ret_val) 11768 goto release; 11769 /* drop link after 5 times MSE threshold was reached */ 11770 ret_val = em_write_phy_reg(hw, I82579_EMI_DATA, 11771 0x0005); 11772 release: 11773 em_swfw_sync_release(hw, swfw); 11774 11775 out: 11776 return ret_val; 11777 } 11778 11779 int32_t 11780 em_set_eee_i350(struct em_hw *hw) 11781 { 11782 int32_t ret_val = E1000_SUCCESS; 11783 uint32_t ipcnfg, eeer; 11784 11785 if ((hw->mac_type < em_i350) || 11786 (hw->media_type != em_media_type_copper)) 11787 goto out; 11788 ipcnfg = EM_READ_REG(hw, E1000_IPCNFG); 11789 eeer = EM_READ_REG(hw, E1000_EEER); 11790 11791 if (hw->eee_enable) { 11792 ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN); 11793 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN | 11794 E1000_EEER_LPI_FC); 11795 } else { 11796 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN); 11797 eeer &= ~(E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN | 11798 E1000_EEER_LPI_FC); 11799 } 11800 EM_WRITE_REG(hw, E1000_IPCNFG, ipcnfg); 11801 EM_WRITE_REG(hw, E1000_EEER, eeer); 11802 EM_READ_REG(hw, E1000_IPCNFG); 11803 EM_READ_REG(hw, E1000_EEER); 11804 out: 11805 return ret_val; 11806 } 11807 11808 /*************************************************************************** 11809 * em_set_eee_pchlan - Enable/disable EEE support 11810 * @hw: pointer to the HW structure 11811 * 11812 * Enable/disable EEE based on setting in dev_spec structure. The bits in 11813 * the LPI Control register will remain set only if/when link is up. 11814 ***************************************************************************/ 11815 int32_t 11816 em_set_eee_pchlan(struct em_hw *hw) 11817 { 11818 int32_t ret_val = E1000_SUCCESS; 11819 uint16_t phy_reg; 11820 11821 DEBUGFUNC("em_set_eee_pchlan"); 11822 11823 if (hw->phy_type != em_phy_82579 && 11824 hw->phy_type != em_phy_i217) 11825 goto out; 11826 11827 ret_val = em_read_phy_reg(hw, I82579_LPI_CTRL, &phy_reg); 11828 if (ret_val) 11829 goto out; 11830 11831 if (hw->eee_enable) 11832 phy_reg &= ~I82579_LPI_CTRL_ENABLE_MASK; 11833 else 11834 phy_reg |= I82579_LPI_CTRL_ENABLE_MASK; 11835 11836 ret_val = em_write_phy_reg(hw, I82579_LPI_CTRL, phy_reg); 11837 out: 11838 return ret_val; 11839 } 11840 11841 /** 11842 * em_initialize_M88E1512_phy - Initialize M88E1512 PHY 11843 * @hw: pointer to the HW structure 11844 * 11845 * Initialize Marvell 1512 to work correctly with Avoton. 11846 **/ 11847 int32_t 11848 em_initialize_M88E1512_phy(struct em_hw *hw) 11849 { 11850 int32_t ret_val = E1000_SUCCESS; 11851 11852 DEBUGFUNC("e1000_initialize_M88E1512_phy"); 11853 11854 /* Check if this is correct PHY. */ 11855 if (hw->phy_id != M88E1512_E_PHY_ID) 11856 goto out; 11857 11858 /* Switch to PHY page 0xFF. */ 11859 ret_val = em_write_phy_reg(hw, M88E1543_PAGE_ADDR, 0x00FF); 11860 if (ret_val) 11861 goto out; 11862 11863 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_2, 0x214B); 11864 if (ret_val) 11865 goto out; 11866 11867 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_1, 0x2144); 11868 if (ret_val) 11869 goto out; 11870 11871 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_2, 0x0C28); 11872 if (ret_val) 11873 goto out; 11874 11875 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_1, 0x2146); 11876 if (ret_val) 11877 goto out; 11878 11879 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_2, 0xB233); 11880 if (ret_val) 11881 goto out; 11882 11883 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_1, 0x214D); 11884 if (ret_val) 11885 goto out; 11886 11887 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_2, 0xCC0C); 11888 if (ret_val) 11889 goto out; 11890 11891 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_1, 0x2159); 11892 if (ret_val) 11893 goto out; 11894 11895 /* Switch to PHY page 0xFB. */ 11896 ret_val = em_write_phy_reg(hw, M88E1543_PAGE_ADDR, 0x00FB); 11897 if (ret_val) 11898 goto out; 11899 11900 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_3, 0x000D); 11901 if (ret_val) 11902 goto out; 11903 11904 /* Switch to PHY page 0x12. */ 11905 ret_val = em_write_phy_reg(hw, M88E1543_PAGE_ADDR, 0x12); 11906 if (ret_val) 11907 goto out; 11908 11909 /* Change mode to SGMII-to-Copper */ 11910 ret_val = em_write_phy_reg(hw, M88E1512_MODE, 0x8001); 11911 if (ret_val) 11912 goto out; 11913 11914 /* Return the PHY to page 0. */ 11915 ret_val = em_write_phy_reg(hw, M88E1543_PAGE_ADDR, 0); 11916 if (ret_val) 11917 goto out; 11918 11919 ret_val = em_phy_hw_reset(hw); 11920 if (ret_val) { 11921 DEBUGOUT("Error committing the PHY changes\n"); 11922 return ret_val; 11923 } 11924 11925 msec_delay(1000); 11926 out: 11927 return ret_val; 11928 } 11929 11930 uint32_t 11931 em_translate_82542_register(uint32_t reg) 11932 { 11933 /* 11934 * Some of the 82542 registers are located at different 11935 * offsets than they are in newer adapters. 11936 * Despite the difference in location, the registers 11937 * function in the same manner. 11938 */ 11939 switch (reg) { 11940 case E1000_RA: 11941 reg = 0x00040; 11942 break; 11943 case E1000_RDTR: 11944 reg = 0x00108; 11945 break; 11946 case E1000_RDBAL(0): 11947 reg = 0x00110; 11948 break; 11949 case E1000_RDBAH(0): 11950 reg = 0x00114; 11951 break; 11952 case E1000_RDLEN(0): 11953 reg = 0x00118; 11954 break; 11955 case E1000_RDH(0): 11956 reg = 0x00120; 11957 break; 11958 case E1000_RDT(0): 11959 reg = 0x00128; 11960 break; 11961 case E1000_RDBAL(1): 11962 reg = 0x00138; 11963 break; 11964 case E1000_RDBAH(1): 11965 reg = 0x0013C; 11966 break; 11967 case E1000_RDLEN(1): 11968 reg = 0x00140; 11969 break; 11970 case E1000_RDH(1): 11971 reg = 0x00148; 11972 break; 11973 case E1000_RDT(1): 11974 reg = 0x00150; 11975 break; 11976 case E1000_FCRTH: 11977 reg = 0x00160; 11978 break; 11979 case E1000_FCRTL: 11980 reg = 0x00168; 11981 break; 11982 case E1000_MTA: 11983 reg = 0x00200; 11984 break; 11985 case E1000_TDBAL(0): 11986 reg = 0x00420; 11987 break; 11988 case E1000_TDBAH(0): 11989 reg = 0x00424; 11990 break; 11991 case E1000_TDLEN(0): 11992 reg = 0x00428; 11993 break; 11994 case E1000_TDH(0): 11995 reg = 0x00430; 11996 break; 11997 case E1000_TDT(0): 11998 reg = 0x00438; 11999 break; 12000 case E1000_TIDV: 12001 reg = 0x00440; 12002 break; 12003 case E1000_VFTA: 12004 reg = 0x00600; 12005 break; 12006 case E1000_TDFH: 12007 reg = 0x08010; 12008 break; 12009 case E1000_TDFT: 12010 reg = 0x08018; 12011 break; 12012 default: 12013 break; 12014 } 12015 12016 return (reg); 12017 } 12018