1 /************************************************************************** 2 3 Copyright (c) 2001-2003, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ***************************************************************************/ 33 34 /* $FreeBSD: if_em.h,v 1.26 2004/09/01 23:22:41 pdeuskar Exp $ */ 35 /* $OpenBSD: if_em.h,v 1.75 2020/02/20 09:32:49 mpi Exp $ */ 36 37 #ifndef _EM_H_DEFINED_ 38 #define _EM_H_DEFINED_ 39 40 #include "bpfilter.h" 41 #include "vlan.h" 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/sockio.h> 46 #include <sys/mbuf.h> 47 #include <sys/malloc.h> 48 #include <sys/kernel.h> 49 #include <sys/device.h> 50 #include <sys/socket.h> 51 #include <sys/timeout.h> 52 #include <sys/atomic.h> 53 54 #include <net/if.h> 55 #include <net/if_media.h> 56 57 #include <netinet/in.h> 58 #include <netinet/ip.h> 59 #include <netinet/if_ether.h> 60 #include <netinet/tcp.h> 61 #include <netinet/udp.h> 62 63 #if NBPFILTER > 0 64 #include <net/bpf.h> 65 #endif 66 67 typedef int boolean_t; 68 #define TRUE 1 69 #define FALSE 0 70 71 #include <dev/pci/pcireg.h> 72 #include <dev/pci/pcivar.h> 73 #include <dev/pci/pcidevs.h> 74 75 #include <dev/pci/if_em_hw.h> 76 77 /* Tunables */ 78 79 /* 80 * EM_TXD: Maximum number of Transmit Descriptors 81 * Valid Range: 80-256 for 82542 and 82543-based adapters 82 * 80-4096 for others 83 * Default Value: 256 84 * This value is the number of transmit descriptors allocated by the driver. 85 * Increasing this value allows the driver to queue more transmits. Each 86 * descriptor is 16 bytes. 87 * Since TDLEN should be multiple of 128bytes, the number of transmit 88 * descriptors should meet the following condition. 89 * (num_tx_desc * sizeof(struct em_tx_desc)) % 128 == 0 90 */ 91 #define EM_MAX_TXD_82543 256 92 #define EM_MAX_TXD 512 93 94 /* 95 * EM_RXD - Maximum number of receive Descriptors 96 * Valid Range: 80-256 for 82542 and 82543-based adapters 97 * 80-4096 for others 98 * Default Value: 256 99 * This value is the number of receive descriptors allocated by the driver. 100 * Increasing this value allows the driver to buffer more incoming packets. 101 * Each descriptor is 16 bytes. A receive buffer is also allocated for each 102 * descriptor. The maximum MTU size is 16110. 103 * Since TDLEN should be multiple of 128bytes, the number of transmit 104 * descriptors should meet the following condition. 105 * (num_tx_desc * sizeof(struct em_tx_desc)) % 128 == 0 106 */ 107 #define EM_MAX_RXD_82543 256 108 #define EM_MAX_RXD 256 109 110 /* 111 * MAX_INTS_PER_SEC (ITR - Interrupt Throttle Register) 112 * The Interrupt Throttle Register (ITR) limits the delivery of interrupts 113 * to a reasonable rate by providing a guaranteed inter-interrupt delay 114 * between interrupts asserted by the Ethernet controller. 115 */ 116 #define MAX_INTS_PER_SEC 8000 117 #define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256) 118 119 /* 120 * EM_TIDV - Transmit Interrupt Delay Value 121 * Valid Range: 0-65535 (0=off) 122 * Default Value: 64 123 * This value delays the generation of transmit interrupts in units of 124 * 1.024 microseconds. Transmit interrupt reduction can improve CPU 125 * efficiency if properly tuned for specific network traffic. If the 126 * system is reporting dropped transmits, this value may be set too high 127 * causing the driver to run out of available transmit descriptors. 128 */ 129 #define EM_TIDV 64 130 131 /* 132 * EM_TADV - Transmit Absolute Interrupt Delay Value 133 * (Not valid for 82542/82543/82544) 134 * Valid Range: 0-65535 (0=off) 135 * Default Value: 64 136 * This value, in units of 1.024 microseconds, limits the delay in which a 137 * transmit interrupt is generated. Useful only if EM_TIDV is non-zero, 138 * this value ensures that an interrupt is generated after the initial 139 * packet is sent on the wire within the set amount of time. Proper tuning, 140 * along with EM_TIDV, may improve traffic throughput in specific 141 * network conditions. 142 */ 143 #define EM_TADV 64 144 145 /* 146 * EM_RDTR - Receive Interrupt Delay Timer (Packet Timer) 147 * Valid Range: 0-65535 (0=off) 148 * Default Value: 0 149 * This value delays the generation of receive interrupts in units of 1.024 150 * microseconds. Receive interrupt reduction can improve CPU efficiency if 151 * properly tuned for specific network traffic. Increasing this value adds 152 * extra latency to frame reception and can end up decreasing the throughput 153 * of TCP traffic. If the system is reporting dropped receives, this value 154 * may be set too high, causing the driver to run out of available receive 155 * descriptors. 156 * 157 * CAUTION: When setting EM_RDTR to a value other than 0, adapters 158 * may hang (stop transmitting) under certain network conditions. 159 * If this occurs a WATCHDOG message is logged in the system 160 * event log. In addition, the controller is automatically reset, 161 * restoring the network connection. To eliminate the potential 162 * for the hang ensure that EM_RDTR is set to 0. 163 */ 164 #define EM_RDTR 0 165 166 /* 167 * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544) 168 * Valid Range: 0-65535 (0=off) 169 * Default Value: 64 170 * This value, in units of 1.024 microseconds, limits the delay in which a 171 * receive interrupt is generated. Useful only if EM_RDTR is non-zero, 172 * this value ensures that an interrupt is generated after the initial 173 * packet is received within the set amount of time. Proper tuning, 174 * along with EM_RDTR, may improve traffic throughput in specific network 175 * conditions. 176 */ 177 #define EM_RADV 64 178 179 /* 180 * This parameter controls the duration of transmit watchdog timer. 181 */ 182 #define EM_TX_TIMEOUT 5 /* set to 5 seconds */ 183 184 /* 185 * Thise parameter controls the minimum number of available transmit 186 * descriptors needed before we attempt transmission of a packet. 187 */ 188 #define EM_TX_OP_THRESHOLD (sc->num_tx_desc / 32) 189 190 /* 191 * This parameter controls whether or not autonegotiation is enabled. 192 * 0 - Disable autonegotiation 193 * 1 - Enable autonegotiation 194 */ 195 #define DO_AUTO_NEG 1 196 197 /* 198 * This parameter control whether or not the driver will wait for 199 * autonegotiation to complete. 200 * 1 - Wait for autonegotiation to complete 201 * 0 - Don't wait for autonegotiation to complete 202 */ 203 #define WAIT_FOR_AUTO_NEG_DEFAULT 0 204 205 /* 206 * EM_MASTER_SLAVE is only defined to enable a workaround for a known 207 * compatibility issue with 82541/82547 devices and some switches. 208 * See the "Known Limitations" section of the README file for a complete 209 * description and a list of affected switches. 210 * 211 * 0 = Hardware default 212 * 1 = Master mode 213 * 2 = Slave mode 214 * 3 = Auto master/slave 215 */ 216 /* #define EM_MASTER_SLAVE 2 */ 217 218 /* Tunables -- End */ 219 220 #define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 221 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 222 ADVERTISE_1000_FULL) 223 224 #define EM_MMBA 0x0010 /* Mem base address */ 225 #define EM_FLASH 0x0014 /* Flash memory on ICH8 */ 226 #define EM_ROUNDUP(size, unit) (((size) + (unit) - 1) & ~((unit) - 1)) 227 228 #define EM_SMARTSPEED_DOWNSHIFT 3 229 #define EM_SMARTSPEED_MAX 15 230 231 #define MAX_NUM_MULTICAST_ADDRESSES 128 232 233 #define PCICFG_DESC_RING_STATUS 0xe4 234 #define FLUSH_DESC_REQUIRED 0x100 235 236 /* 237 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be 238 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will 239 * also optimize cache line size effect. H/W supports up to cache line size 128. 240 */ 241 #define EM_DBA_ALIGN 128 242 243 #define SPEED_MODE_BIT (1<<21) /* On PCI-E MACs only */ 244 245 /* Defines for printing debug information */ 246 #define DEBUG_INIT 0 247 #define DEBUG_IOCTL 0 248 #define DEBUG_HW 0 249 250 #define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 251 #define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 252 #define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 253 #define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 254 #define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 255 #define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 256 #define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 257 #define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 258 #define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 259 260 /* Supported RX Buffer Sizes */ 261 #define EM_RXBUFFER_2048 2048 262 #define EM_RXBUFFER_4096 4096 263 #define EM_RXBUFFER_8192 8192 264 #define EM_RXBUFFER_16384 16384 265 266 #define EM_MCLBYTES (EM_RXBUFFER_2048 + ETHER_ALIGN) 267 268 #define EM_MAX_SCATTER 64 269 #define EM_TSO_SIZE 65535 270 271 struct em_packet { 272 int pkt_eop; /* Index of the desc to watch */ 273 struct mbuf *pkt_m; 274 bus_dmamap_t pkt_map; /* bus_dma map for packet */ 275 }; 276 277 /* 278 * Bus dma allocation structure used by 279 * em_dma_malloc and em_dma_free. 280 */ 281 struct em_dma_alloc { 282 caddr_t dma_vaddr; 283 bus_dmamap_t dma_map; 284 bus_dma_segment_t dma_seg; 285 bus_size_t dma_size; 286 int dma_nseg; 287 }; 288 289 typedef enum _XSUM_CONTEXT_T { 290 OFFLOAD_NONE, 291 OFFLOAD_TCP_IP, 292 OFFLOAD_UDP_IP 293 } XSUM_CONTEXT_T; 294 295 /* For 82544 PCI-X Workaround */ 296 typedef struct _ADDRESS_LENGTH_PAIR 297 { 298 u_int64_t address; 299 u_int32_t length; 300 } ADDRESS_LENGTH_PAIR, *PADDRESS_LENGTH_PAIR; 301 302 typedef struct _DESCRIPTOR_PAIR 303 { 304 ADDRESS_LENGTH_PAIR descriptor[4]; 305 u_int32_t elements; 306 } DESC_ARRAY, *PDESC_ARRAY; 307 308 /* 309 * Receive definitions 310 * 311 * we have an array of num_rx_desc rx_desc (handled by the 312 * controller), and paired with an array of rx_buffers 313 * (at rx_buffer_area). 314 * The next pair to check on receive is at offset next_rx_desc_to_check 315 */ 316 struct em_rx { 317 struct em_dma_alloc sc_rx_dma; /* bus_dma glue for rx desc */ 318 struct em_rx_desc *sc_rx_desc_ring; 319 u_int sc_rx_desc_head; 320 u_int sc_rx_desc_tail; 321 struct em_packet *sc_rx_pkts_ring; 322 323 struct if_rxring sc_rx_ring; 324 325 /* 326 * First/last mbuf pointers, for 327 * collecting multisegment RX packets. 328 */ 329 struct mbuf *fmp; 330 struct mbuf *lmp; 331 332 /* Statistics */ 333 unsigned long dropped_pkts; 334 }; 335 336 /* 337 * Transmit definitions 338 * 339 * We have an array of num_tx_desc descriptors (handled 340 * by the controller) paired with an array of tx_buffers 341 * (at tx_buffer_area). 342 * The index of the next available descriptor is next_avail_tx_desc. 343 * The number of remaining tx_desc is num_tx_desc_avail. 344 */ 345 struct em_tx { 346 struct em_dma_alloc sc_tx_dma; /* bus_dma glue for tx desc */ 347 struct em_tx_desc *sc_tx_desc_ring; 348 u_int sc_tx_desc_head; 349 u_int sc_tx_desc_tail; 350 struct em_packet *sc_tx_pkts_ring; 351 352 u_int32_t sc_txd_cmd; 353 354 XSUM_CONTEXT_T active_checksum_context; 355 }; 356 357 struct em_softc; 358 struct em_queue { 359 struct em_softc *sc; 360 uint32_t me; /* queue index, also msix vector */ 361 362 struct em_tx tx; 363 struct em_rx rx; 364 365 struct timeout rx_refill; 366 }; 367 368 /* Our adapter structure */ 369 struct em_softc { 370 struct device sc_dev; 371 struct arpcom sc_ac; 372 373 bus_dma_tag_t sc_dmat; 374 375 struct em_hw hw; 376 377 /* OpenBSD operating-system-specific structures */ 378 struct em_osdep osdep; 379 struct ifmedia media; 380 int io_rid; 381 int legacy_irq; 382 383 void *sc_intrhand; 384 struct timeout em_intr_enable; 385 struct timeout timer_handle; 386 struct timeout tx_fifo_timer_handle; 387 388 /* Info about the board itself */ 389 u_int32_t part_num; 390 u_int8_t link_active; 391 u_int16_t link_speed; 392 u_int16_t link_duplex; 393 u_int32_t smartspeed; 394 u_int32_t tx_int_delay; 395 u_int32_t tx_abs_int_delay; 396 u_int32_t rx_int_delay; 397 u_int32_t rx_abs_int_delay; 398 399 u_int sc_tx_slots; 400 u_int sc_rx_slots; 401 u_int32_t sc_rx_buffer_len; 402 403 /* Misc stats maintained by the driver */ 404 unsigned long mbuf_alloc_failed; 405 unsigned long mbuf_cluster_failed; 406 unsigned long no_tx_desc_avail1; 407 unsigned long no_tx_desc_avail2; 408 unsigned long no_tx_map_avail; 409 unsigned long no_tx_dma_setup; 410 unsigned long watchdog_events; 411 unsigned long rx_overruns; 412 413 /* Used in for 82547 10Mb Half workaround */ 414 #define EM_PBA_BYTES_SHIFT 0xA 415 #define EM_TX_HEAD_ADDR_SHIFT 7 416 #define EM_PBA_TX_MASK 0xFFFF0000 417 #define EM_FIFO_HDR 0x10 418 419 #define EM_82547_PKT_THRESH 0x3e0 420 421 /* 422 * These are all 82547 members for the workaround. The chip is pretty 423 * old, single queue, so keep it here to avoid further changes. 424 */ 425 u_int32_t tx_fifo_size; 426 u_int32_t tx_fifo_head; 427 u_int32_t tx_fifo_head_addr; 428 u_int64_t tx_fifo_reset_cnt; 429 u_int64_t tx_fifo_wrk_cnt; 430 u_int32_t tx_head_addr; 431 432 /* For 82544 PCI-X Workaround */ 433 boolean_t pcix_82544; 434 struct em_hw_stats stats; 435 436 int num_queues; 437 struct em_queue *queues; 438 }; 439 440 #define DEVNAME(_sc) ((_sc)->sc_dev.dv_xname) 441 442 #endif /* _EM_H_DEFINED_ */ 443