1 /************************************************************************** 2 3 Copyright (c) 2001-2003, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ***************************************************************************/ 33 34 /* $FreeBSD: if_em.h,v 1.26 2004/09/01 23:22:41 pdeuskar Exp $ */ 35 /* $OpenBSD: if_em.h,v 1.52 2014/07/10 14:21:20 deraadt Exp $ */ 36 37 #ifndef _EM_H_DEFINED_ 38 #define _EM_H_DEFINED_ 39 40 #include "bpfilter.h" 41 #include "vlan.h" 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/sockio.h> 46 #include <sys/mbuf.h> 47 #include <sys/malloc.h> 48 #include <sys/kernel.h> 49 #include <sys/device.h> 50 #include <sys/socket.h> 51 #include <sys/timeout.h> 52 53 #include <net/if.h> 54 #include <net/if_dl.h> 55 #include <net/if_media.h> 56 57 #ifdef INET 58 #include <netinet/in.h> 59 #include <netinet/in_systm.h> 60 #include <netinet/ip.h> 61 #include <netinet/if_ether.h> 62 #include <netinet/tcp.h> 63 #include <netinet/udp.h> 64 #endif 65 66 #if NVLAN > 0 67 #include <net/if_types.h> 68 #include <net/if_vlan_var.h> 69 #endif 70 71 #if NBPFILTER > 0 72 #include <net/bpf.h> 73 #endif 74 75 typedef int boolean_t; 76 #define TRUE 1 77 #define FALSE 0 78 79 #include <dev/pci/pcireg.h> 80 #include <dev/pci/pcivar.h> 81 #include <dev/pci/pcidevs.h> 82 83 #include <dev/pci/if_em_hw.h> 84 85 /* Tunables */ 86 87 /* 88 * EM_TXD: Maximum number of Transmit Descriptors 89 * Valid Range: 80-256 for 82542 and 82543-based adapters 90 * 80-4096 for others 91 * Default Value: 256 92 * This value is the number of transmit descriptors allocated by the driver. 93 * Increasing this value allows the driver to queue more transmits. Each 94 * descriptor is 16 bytes. 95 * Since TDLEN should be multiple of 128bytes, the number of transmit 96 * descriptors should meet the following condition. 97 * (num_tx_desc * sizeof(struct em_tx_desc)) % 128 == 0 98 */ 99 #define EM_MAX_TXD_82543 256 100 #define EM_MAX_TXD 512 101 102 /* 103 * EM_RXD - Maximum number of receive Descriptors 104 * Valid Range: 80-256 for 82542 and 82543-based adapters 105 * 80-4096 for others 106 * Default Value: 256 107 * This value is the number of receive descriptors allocated by the driver. 108 * Increasing this value allows the driver to buffer more incoming packets. 109 * Each descriptor is 16 bytes. A receive buffer is also allocated for each 110 * descriptor. The maximum MTU size is 16110. 111 * Since TDLEN should be multiple of 128bytes, the number of transmit 112 * descriptors should meet the following condition. 113 * (num_tx_desc * sizeof(struct em_tx_desc)) % 128 == 0 114 */ 115 #define EM_MAX_RXD_82543 256 116 #define EM_MAX_RXD 256 117 118 /* 119 * MAX_INTS_PER_SEC (ITR - Interrupt Throttle Register) 120 * The Interrupt Throttle Register (ITR) limits the delivery of interrupts 121 * to a reasonable rate by providing a guaranteed inter-interrupt delay 122 * between interrupts asserted by the Ethernet controller. 123 */ 124 #define MAX_INTS_PER_SEC 8000 125 #define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256) 126 127 /* 128 * EM_TIDV - Transmit Interrupt Delay Value 129 * Valid Range: 0-65535 (0=off) 130 * Default Value: 64 131 * This value delays the generation of transmit interrupts in units of 132 * 1.024 microseconds. Transmit interrupt reduction can improve CPU 133 * efficiency if properly tuned for specific network traffic. If the 134 * system is reporting dropped transmits, this value may be set too high 135 * causing the driver to run out of available transmit descriptors. 136 */ 137 #define EM_TIDV 64 138 139 /* 140 * EM_TADV - Transmit Absolute Interrupt Delay Value 141 * (Not valid for 82542/82543/82544) 142 * Valid Range: 0-65535 (0=off) 143 * Default Value: 64 144 * This value, in units of 1.024 microseconds, limits the delay in which a 145 * transmit interrupt is generated. Useful only if EM_TIDV is non-zero, 146 * this value ensures that an interrupt is generated after the initial 147 * packet is sent on the wire within the set amount of time. Proper tuning, 148 * along with EM_TIDV, may improve traffic throughput in specific 149 * network conditions. 150 */ 151 #define EM_TADV 64 152 153 /* 154 * EM_RDTR - Receive Interrupt Delay Timer (Packet Timer) 155 * Valid Range: 0-65535 (0=off) 156 * Default Value: 0 157 * This value delays the generation of receive interrupts in units of 1.024 158 * microseconds. Receive interrupt reduction can improve CPU efficiency if 159 * properly tuned for specific network traffic. Increasing this value adds 160 * extra latency to frame reception and can end up decreasing the throughput 161 * of TCP traffic. If the system is reporting dropped receives, this value 162 * may be set too high, causing the driver to run out of available receive 163 * descriptors. 164 * 165 * CAUTION: When setting EM_RDTR to a value other than 0, adapters 166 * may hang (stop transmitting) under certain network conditions. 167 * If this occurs a WATCHDOG message is logged in the system 168 * event log. In addition, the controller is automatically reset, 169 * restoring the network connection. To eliminate the potential 170 * for the hang ensure that EM_RDTR is set to 0. 171 */ 172 #define EM_RDTR 0 173 174 /* 175 * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544) 176 * Valid Range: 0-65535 (0=off) 177 * Default Value: 64 178 * This value, in units of 1.024 microseconds, limits the delay in which a 179 * receive interrupt is generated. Useful only if EM_RDTR is non-zero, 180 * this value ensures that an interrupt is generated after the initial 181 * packet is received within the set amount of time. Proper tuning, 182 * along with EM_RDTR, may improve traffic throughput in specific network 183 * conditions. 184 */ 185 #define EM_RADV 64 186 187 /* 188 * This parameter controls the duration of transmit watchdog timer. 189 */ 190 #define EM_TX_TIMEOUT 5 /* set to 5 seconds */ 191 192 /* 193 * These parameters control when the driver calls the routine to reclaim 194 * transmit descriptors. 195 */ 196 #define EM_TX_CLEANUP_THRESHOLD (sc->num_tx_desc / 8) 197 #define EM_TX_OP_THRESHOLD (sc->num_tx_desc / 32) 198 199 /* 200 * This parameter controls whether or not autonegotiation is enabled. 201 * 0 - Disable autonegotiation 202 * 1 - Enable autonegotiation 203 */ 204 #define DO_AUTO_NEG 1 205 206 /* 207 * This parameter control whether or not the driver will wait for 208 * autonegotiation to complete. 209 * 1 - Wait for autonegotiation to complete 210 * 0 - Don't wait for autonegotiation to complete 211 */ 212 #define WAIT_FOR_AUTO_NEG_DEFAULT 0 213 214 /* 215 * EM_MASTER_SLAVE is only defined to enable a workaround for a known 216 * compatibility issue with 82541/82547 devices and some switches. 217 * See the "Known Limitations" section of the README file for a complete 218 * description and a list of affected switches. 219 * 220 * 0 = Hardware default 221 * 1 = Master mode 222 * 2 = Slave mode 223 * 3 = Auto master/slave 224 */ 225 /* #define EM_MASTER_SLAVE 2 */ 226 227 /* Tunables -- End */ 228 229 #define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 230 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 231 ADVERTISE_1000_FULL) 232 233 #define EM_MMBA 0x0010 /* Mem base address */ 234 #define EM_FLASH 0x0014 /* Flash memory on ICH8 */ 235 #define EM_ROUNDUP(size, unit) (((size) + (unit) - 1) & ~((unit) - 1)) 236 237 #define EM_SMARTSPEED_DOWNSHIFT 3 238 #define EM_SMARTSPEED_MAX 15 239 240 #define MAX_NUM_MULTICAST_ADDRESSES 128 241 242 /* 243 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be 244 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will 245 * also optimize cache line size effect. H/W supports up to cache line size 128. 246 */ 247 #define EM_DBA_ALIGN 128 248 249 #define SPEED_MODE_BIT (1<<21) /* On PCI-E MACs only */ 250 251 /* Defines for printing debug information */ 252 #define DEBUG_INIT 0 253 #define DEBUG_IOCTL 0 254 #define DEBUG_HW 0 255 256 #define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 257 #define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 258 #define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 259 #define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 260 #define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 261 #define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 262 #define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 263 #define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 264 #define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 265 266 /* Supported RX Buffer Sizes */ 267 #define EM_RXBUFFER_2048 2048 268 #define EM_RXBUFFER_4096 4096 269 #define EM_RXBUFFER_8192 8192 270 #define EM_RXBUFFER_16384 16384 271 272 #define EM_MAX_SCATTER 64 273 #define EM_TSO_SIZE 65535 274 275 struct em_buffer { 276 int next_eop; /* Index of the desc to watch */ 277 struct mbuf *m_head; 278 bus_dmamap_t map; /* bus_dma map for packet */ 279 }; 280 281 /* 282 * Bus dma allocation structure used by 283 * em_dma_malloc and em_dma_free. 284 */ 285 struct em_dma_alloc { 286 bus_addr_t dma_paddr; 287 caddr_t dma_vaddr; 288 bus_dma_tag_t dma_tag; 289 bus_dmamap_t dma_map; 290 bus_dma_segment_t dma_seg; 291 bus_size_t dma_size; 292 int dma_nseg; 293 }; 294 295 typedef enum _XSUM_CONTEXT_T { 296 OFFLOAD_NONE, 297 OFFLOAD_TCP_IP, 298 OFFLOAD_UDP_IP 299 } XSUM_CONTEXT_T; 300 301 /* For 82544 PCI-X Workaround */ 302 typedef struct _ADDRESS_LENGTH_PAIR 303 { 304 u_int64_t address; 305 u_int32_t length; 306 } ADDRESS_LENGTH_PAIR, *PADDRESS_LENGTH_PAIR; 307 308 typedef struct _DESCRIPTOR_PAIR 309 { 310 ADDRESS_LENGTH_PAIR descriptor[4]; 311 u_int32_t elements; 312 } DESC_ARRAY, *PDESC_ARRAY; 313 314 /* Our adapter structure */ 315 struct em_softc { 316 struct device sc_dv; 317 struct arpcom interface_data; 318 struct em_hw hw; 319 320 /* OpenBSD operating-system-specific structures */ 321 struct em_osdep osdep; 322 struct ifmedia media; 323 int io_rid; 324 325 void *sc_intrhand; 326 struct timeout em_intr_enable; 327 struct timeout timer_handle; 328 struct timeout tx_fifo_timer_handle; 329 330 #ifdef __STRICT_ALIGNMENT 331 /* Used for carrying forward alignment adjustments */ 332 unsigned char align_buf[ETHER_ALIGN]; /* tail of unaligned packet */ 333 u_int8_t align_buf_len; /* bytes in tail */ 334 #endif /* __STRICT_ALIGNMENT */ 335 336 /* Info about the board itself */ 337 u_int32_t part_num; 338 u_int8_t link_active; 339 u_int16_t link_speed; 340 u_int16_t link_duplex; 341 u_int32_t smartspeed; 342 u_int32_t tx_int_delay; 343 u_int32_t tx_abs_int_delay; 344 u_int32_t rx_int_delay; 345 u_int32_t rx_abs_int_delay; 346 347 XSUM_CONTEXT_T active_checksum_context; 348 349 /* 350 * Transmit definitions 351 * 352 * We have an array of num_tx_desc descriptors (handled 353 * by the controller) paired with an array of tx_buffers 354 * (at tx_buffer_area). 355 * The index of the next available descriptor is next_avail_tx_desc. 356 * The number of remaining tx_desc is num_tx_desc_avail. 357 */ 358 struct em_dma_alloc txdma; /* bus_dma glue for tx desc */ 359 struct em_tx_desc *tx_desc_base; 360 u_int32_t next_avail_tx_desc; 361 u_int32_t next_tx_to_clean; 362 volatile u_int16_t num_tx_desc_avail; 363 u_int16_t num_tx_desc; 364 u_int32_t txd_cmd; 365 struct em_buffer *tx_buffer_area; 366 bus_dma_tag_t txtag; /* dma tag for tx */ 367 368 /* 369 * Receive definitions 370 * 371 * we have an array of num_rx_desc rx_desc (handled by the 372 * controller), and paired with an array of rx_buffers 373 * (at rx_buffer_area). 374 * The next pair to check on receive is at offset next_rx_desc_to_check 375 */ 376 struct em_dma_alloc rxdma; /* bus_dma glue for rx desc */ 377 struct em_rx_desc *rx_desc_base; 378 struct if_rxring rx_ring; 379 u_int32_t next_rx_desc_to_check; 380 u_int32_t last_rx_desc_filled; 381 u_int32_t rx_buffer_len; 382 u_int16_t num_rx_desc; 383 struct em_buffer *rx_buffer_area; 384 bus_dma_tag_t rxtag; 385 386 /* 387 * First/last mbuf pointers, for 388 * collecting multisegment RX packets. 389 */ 390 struct mbuf *fmp; 391 struct mbuf *lmp; 392 393 /* Misc stats maintained by the driver */ 394 unsigned long dropped_pkts; 395 unsigned long mbuf_alloc_failed; 396 unsigned long mbuf_cluster_failed; 397 unsigned long no_tx_desc_avail1; 398 unsigned long no_tx_desc_avail2; 399 unsigned long no_tx_map_avail; 400 unsigned long no_tx_dma_setup; 401 unsigned long watchdog_events; 402 unsigned long rx_overruns; 403 404 /* Used in for 82547 10Mb Half workaround */ 405 #define EM_PBA_BYTES_SHIFT 0xA 406 #define EM_TX_HEAD_ADDR_SHIFT 7 407 #define EM_PBA_TX_MASK 0xFFFF0000 408 #define EM_FIFO_HDR 0x10 409 410 #define EM_82547_PKT_THRESH 0x3e0 411 412 u_int32_t tx_fifo_size; 413 u_int32_t tx_fifo_head; 414 u_int32_t tx_fifo_head_addr; 415 u_int64_t tx_fifo_reset_cnt; 416 u_int64_t tx_fifo_wrk_cnt; 417 u_int32_t tx_head_addr; 418 419 /* For 82544 PCI-X Workaround */ 420 boolean_t pcix_82544; 421 struct em_hw_stats stats; 422 }; 423 424 #endif /* _EM_H_DEFINED_ */ 425