1 /************************************************************************** 2 3 Copyright (c) 2001-2003, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ***************************************************************************/ 33 34 /* $FreeBSD: if_em.h,v 1.26 2004/09/01 23:22:41 pdeuskar Exp $ */ 35 /* $OpenBSD: if_em.h,v 1.78 2020/07/13 10:35:55 dlg Exp $ */ 36 37 #ifndef _EM_H_DEFINED_ 38 #define _EM_H_DEFINED_ 39 40 #include "bpfilter.h" 41 #include "vlan.h" 42 #include "kstat.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/sockio.h> 47 #include <sys/mbuf.h> 48 #include <sys/malloc.h> 49 #include <sys/kernel.h> 50 #include <sys/device.h> 51 #include <sys/socket.h> 52 #include <sys/timeout.h> 53 #include <sys/atomic.h> 54 #include <sys/kstat.h> 55 56 #include <net/if.h> 57 #include <net/if_media.h> 58 59 #include <netinet/in.h> 60 #include <netinet/ip.h> 61 #include <netinet/if_ether.h> 62 #include <netinet/tcp.h> 63 #include <netinet/udp.h> 64 65 #if NBPFILTER > 0 66 #include <net/bpf.h> 67 #endif 68 69 typedef int boolean_t; 70 #define TRUE 1 71 #define FALSE 0 72 73 #include <dev/pci/pcireg.h> 74 #include <dev/pci/pcivar.h> 75 #include <dev/pci/pcidevs.h> 76 77 #include <dev/pci/if_em_hw.h> 78 79 /* Tunables */ 80 81 /* 82 * EM_TXD: Maximum number of Transmit Descriptors 83 * Valid Range: 80-256 for 82542 and 82543-based adapters 84 * 80-4096 for others 85 * Default Value: 256 86 * This value is the number of transmit descriptors allocated by the driver. 87 * Increasing this value allows the driver to queue more transmits. Each 88 * descriptor is 16 bytes. 89 * Since TDLEN should be multiple of 128bytes, the number of transmit 90 * descriptors should meet the following condition. 91 * (num_tx_desc * sizeof(struct em_tx_desc)) % 128 == 0 92 */ 93 #define EM_MAX_TXD_82543 256 94 #define EM_MAX_TXD 512 95 96 /* 97 * EM_RXD - Maximum number of receive Descriptors 98 * Valid Range: 80-256 for 82542 and 82543-based adapters 99 * 80-4096 for others 100 * Default Value: 256 101 * This value is the number of receive descriptors allocated by the driver. 102 * Increasing this value allows the driver to buffer more incoming packets. 103 * Each descriptor is 16 bytes. A receive buffer is also allocated for each 104 * descriptor. The maximum MTU size is 16110. 105 * Since TDLEN should be multiple of 128bytes, the number of transmit 106 * descriptors should meet the following condition. 107 * (num_tx_desc * sizeof(struct em_tx_desc)) % 128 == 0 108 */ 109 #define EM_MAX_RXD_82543 256 110 #define EM_MAX_RXD 256 111 112 /* 113 * MAX_INTS_PER_SEC (ITR - Interrupt Throttle Register) 114 * The Interrupt Throttle Register (ITR) limits the delivery of interrupts 115 * to a reasonable rate by providing a guaranteed inter-interrupt delay 116 * between interrupts asserted by the Ethernet controller. 117 */ 118 #define MAX_INTS_PER_SEC 8000 119 #define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256) 120 121 /* 122 * EM_TIDV - Transmit Interrupt Delay Value 123 * Valid Range: 0-65535 (0=off) 124 * Default Value: 64 125 * This value delays the generation of transmit interrupts in units of 126 * 1.024 microseconds. Transmit interrupt reduction can improve CPU 127 * efficiency if properly tuned for specific network traffic. If the 128 * system is reporting dropped transmits, this value may be set too high 129 * causing the driver to run out of available transmit descriptors. 130 */ 131 #define EM_TIDV 64 132 133 /* 134 * EM_TADV - Transmit Absolute Interrupt Delay Value 135 * (Not valid for 82542/82543/82544) 136 * Valid Range: 0-65535 (0=off) 137 * Default Value: 64 138 * This value, in units of 1.024 microseconds, limits the delay in which a 139 * transmit interrupt is generated. Useful only if EM_TIDV is non-zero, 140 * this value ensures that an interrupt is generated after the initial 141 * packet is sent on the wire within the set amount of time. Proper tuning, 142 * along with EM_TIDV, may improve traffic throughput in specific 143 * network conditions. 144 */ 145 #define EM_TADV 64 146 147 /* 148 * EM_RDTR - Receive Interrupt Delay Timer (Packet Timer) 149 * Valid Range: 0-65535 (0=off) 150 * Default Value: 0 151 * This value delays the generation of receive interrupts in units of 1.024 152 * microseconds. Receive interrupt reduction can improve CPU efficiency if 153 * properly tuned for specific network traffic. Increasing this value adds 154 * extra latency to frame reception and can end up decreasing the throughput 155 * of TCP traffic. If the system is reporting dropped receives, this value 156 * may be set too high, causing the driver to run out of available receive 157 * descriptors. 158 * 159 * CAUTION: When setting EM_RDTR to a value other than 0, adapters 160 * may hang (stop transmitting) under certain network conditions. 161 * If this occurs a WATCHDOG message is logged in the system 162 * event log. In addition, the controller is automatically reset, 163 * restoring the network connection. To eliminate the potential 164 * for the hang ensure that EM_RDTR is set to 0. 165 */ 166 #define EM_RDTR 0 167 168 /* 169 * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544) 170 * Valid Range: 0-65535 (0=off) 171 * Default Value: 64 172 * This value, in units of 1.024 microseconds, limits the delay in which a 173 * receive interrupt is generated. Useful only if EM_RDTR is non-zero, 174 * this value ensures that an interrupt is generated after the initial 175 * packet is received within the set amount of time. Proper tuning, 176 * along with EM_RDTR, may improve traffic throughput in specific network 177 * conditions. 178 */ 179 #define EM_RADV 64 180 181 /* 182 * This parameter controls the duration of transmit watchdog timer. 183 */ 184 #define EM_TX_TIMEOUT 5 /* set to 5 seconds */ 185 186 /* 187 * Thise parameter controls the minimum number of available transmit 188 * descriptors needed before we attempt transmission of a packet. 189 */ 190 #define EM_TX_OP_THRESHOLD (sc->num_tx_desc / 32) 191 192 /* 193 * This parameter controls whether or not autonegotiation is enabled. 194 * 0 - Disable autonegotiation 195 * 1 - Enable autonegotiation 196 */ 197 #define DO_AUTO_NEG 1 198 199 /* 200 * This parameter control whether or not the driver will wait for 201 * autonegotiation to complete. 202 * 1 - Wait for autonegotiation to complete 203 * 0 - Don't wait for autonegotiation to complete 204 */ 205 #define WAIT_FOR_AUTO_NEG_DEFAULT 0 206 207 /* 208 * EM_MASTER_SLAVE is only defined to enable a workaround for a known 209 * compatibility issue with 82541/82547 devices and some switches. 210 * See the "Known Limitations" section of the README file for a complete 211 * description and a list of affected switches. 212 * 213 * 0 = Hardware default 214 * 1 = Master mode 215 * 2 = Slave mode 216 * 3 = Auto master/slave 217 */ 218 /* #define EM_MASTER_SLAVE 2 */ 219 220 /* Tunables -- End */ 221 222 #define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 223 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 224 ADVERTISE_1000_FULL) 225 226 #define EM_MMBA 0x0010 /* Mem base address */ 227 #define EM_FLASH 0x0014 /* Flash memory on ICH8 */ 228 #define EM_ROUNDUP(size, unit) (((size) + (unit) - 1) & ~((unit) - 1)) 229 230 #define EM_SMARTSPEED_DOWNSHIFT 3 231 #define EM_SMARTSPEED_MAX 15 232 233 #define MAX_NUM_MULTICAST_ADDRESSES 128 234 235 #define PCICFG_DESC_RING_STATUS 0xe4 236 #define FLUSH_DESC_REQUIRED 0x100 237 238 /* 239 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be 240 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will 241 * also optimize cache line size effect. H/W supports up to cache line size 128. 242 */ 243 #define EM_DBA_ALIGN 128 244 245 #define SPEED_MODE_BIT (1<<21) /* On PCI-E MACs only */ 246 247 /* Defines for printing debug information */ 248 #define DEBUG_INIT 0 249 #define DEBUG_IOCTL 0 250 #define DEBUG_HW 0 251 252 #define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 253 #define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 254 #define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 255 #define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 256 #define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 257 #define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 258 #define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 259 #define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 260 #define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 261 262 /* Supported RX Buffer Sizes */ 263 #define EM_RXBUFFER_2048 2048 264 #define EM_RXBUFFER_4096 4096 265 #define EM_RXBUFFER_8192 8192 266 #define EM_RXBUFFER_16384 16384 267 268 #define EM_MCLBYTES (EM_RXBUFFER_2048 + ETHER_ALIGN) 269 270 #define EM_MAX_SCATTER 64 271 #define EM_TSO_SIZE 65535 272 273 struct em_packet { 274 int pkt_eop; /* Index of the desc to watch */ 275 struct mbuf *pkt_m; 276 bus_dmamap_t pkt_map; /* bus_dma map for packet */ 277 }; 278 279 /* 280 * Bus dma allocation structure used by 281 * em_dma_malloc and em_dma_free. 282 */ 283 struct em_dma_alloc { 284 caddr_t dma_vaddr; 285 bus_dmamap_t dma_map; 286 bus_dma_segment_t dma_seg; 287 bus_size_t dma_size; 288 int dma_nseg; 289 }; 290 291 typedef enum _XSUM_CONTEXT_T { 292 OFFLOAD_NONE, 293 OFFLOAD_TCP_IP, 294 OFFLOAD_UDP_IP 295 } XSUM_CONTEXT_T; 296 297 /* For 82544 PCI-X Workaround */ 298 typedef struct _ADDRESS_LENGTH_PAIR 299 { 300 u_int64_t address; 301 u_int32_t length; 302 } ADDRESS_LENGTH_PAIR, *PADDRESS_LENGTH_PAIR; 303 304 typedef struct _DESCRIPTOR_PAIR 305 { 306 ADDRESS_LENGTH_PAIR descriptor[4]; 307 u_int32_t elements; 308 } DESC_ARRAY, *PDESC_ARRAY; 309 310 /* 311 * Receive definitions 312 * 313 * we have an array of num_rx_desc rx_desc (handled by the 314 * controller), and paired with an array of rx_buffers 315 * (at rx_buffer_area). 316 * The next pair to check on receive is at offset next_rx_desc_to_check 317 */ 318 struct em_rx { 319 struct em_dma_alloc sc_rx_dma; /* bus_dma glue for rx desc */ 320 struct em_rx_desc *sc_rx_desc_ring; 321 u_int sc_rx_desc_head; 322 u_int sc_rx_desc_tail; 323 struct em_packet *sc_rx_pkts_ring; 324 325 struct if_rxring sc_rx_ring; 326 327 /* 328 * First/last mbuf pointers, for 329 * collecting multisegment RX packets. 330 */ 331 struct mbuf *fmp; 332 struct mbuf *lmp; 333 334 /* Statistics */ 335 unsigned long dropped_pkts; 336 }; 337 338 /* 339 * Transmit definitions 340 * 341 * We have an array of num_tx_desc descriptors (handled 342 * by the controller) paired with an array of tx_buffers 343 * (at tx_buffer_area). 344 * The index of the next available descriptor is next_avail_tx_desc. 345 * The number of remaining tx_desc is num_tx_desc_avail. 346 */ 347 struct em_tx { 348 struct em_dma_alloc sc_tx_dma; /* bus_dma glue for tx desc */ 349 struct em_tx_desc *sc_tx_desc_ring; 350 u_int sc_tx_desc_head; 351 u_int sc_tx_desc_tail; 352 struct em_packet *sc_tx_pkts_ring; 353 354 u_int32_t sc_txd_cmd; 355 356 XSUM_CONTEXT_T active_checksum_context; 357 }; 358 359 struct em_softc; 360 struct em_queue { 361 struct em_softc *sc; 362 uint32_t me; /* queue index, also msix vector */ 363 uint32_t eims; /* msix only */ 364 void *tag; /* NULL in legacy, check sc_intrhand */ 365 char name[8]; 366 struct em_tx tx; 367 struct em_rx rx; 368 369 struct timeout rx_refill; 370 }; 371 372 373 #define FOREACH_QUEUE(_sc, _que) \ 374 for ((_que) = (_sc)->queues; \ 375 (_que) < ((_sc)->queues + (_sc)->num_queues); \ 376 (_que)++) 377 378 /* Our adapter structure */ 379 struct em_softc { 380 struct device sc_dev; 381 struct arpcom sc_ac; 382 383 bus_dma_tag_t sc_dmat; 384 385 struct em_hw hw; 386 387 /* OpenBSD operating-system-specific structures */ 388 struct em_osdep osdep; 389 struct ifmedia media; 390 int io_rid; 391 int legacy_irq; 392 393 void *sc_intrhand; 394 struct timeout em_intr_enable; 395 struct timeout timer_handle; 396 struct timeout tx_fifo_timer_handle; 397 398 /* Info about the board itself */ 399 u_int32_t part_num; 400 u_int8_t link_active; 401 u_int16_t link_speed; 402 u_int16_t link_duplex; 403 u_int32_t smartspeed; 404 u_int32_t tx_int_delay; 405 u_int32_t tx_abs_int_delay; 406 u_int32_t rx_int_delay; 407 u_int32_t rx_abs_int_delay; 408 409 u_int sc_tx_slots; 410 u_int sc_rx_slots; 411 u_int32_t sc_rx_buffer_len; 412 413 /* Misc stats maintained by the driver */ 414 unsigned long mbuf_alloc_failed; 415 unsigned long mbuf_cluster_failed; 416 unsigned long no_tx_desc_avail1; 417 unsigned long no_tx_desc_avail2; 418 unsigned long no_tx_map_avail; 419 unsigned long no_tx_dma_setup; 420 unsigned long watchdog_events; 421 unsigned long rx_overruns; 422 423 /* Used in for 82547 10Mb Half workaround */ 424 #define EM_PBA_BYTES_SHIFT 0xA 425 #define EM_TX_HEAD_ADDR_SHIFT 7 426 #define EM_PBA_TX_MASK 0xFFFF0000 427 #define EM_FIFO_HDR 0x10 428 429 #define EM_82547_PKT_THRESH 0x3e0 430 431 /* 432 * These are all 82547 members for the workaround. The chip is pretty 433 * old, single queue, so keep it here to avoid further changes. 434 */ 435 u_int32_t tx_fifo_size; 436 u_int32_t tx_fifo_head; 437 u_int32_t tx_fifo_head_addr; 438 u_int64_t tx_fifo_reset_cnt; 439 u_int64_t tx_fifo_wrk_cnt; 440 u_int32_t tx_head_addr; 441 442 /* For 82544 PCI-X Workaround */ 443 boolean_t pcix_82544; 444 445 int msix; 446 uint32_t msix_linkvec; 447 uint32_t msix_linkmask; 448 uint32_t msix_queuesmask; 449 int num_queues; 450 struct em_queue *queues; 451 452 struct kstat *kstat; 453 struct mutex kstat_mtx; 454 }; 455 456 #define DEVNAME(_sc) ((_sc)->sc_dev.dv_xname) 457 458 #endif /* _EM_H_DEFINED_ */ 459