1 /************************************************************************** 2 3 Copyright (c) 2001-2003, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ***************************************************************************/ 33 34 /* $OpenBSD: if_em.c,v 1.334 2017/01/24 03:57:35 dlg Exp $ */ 35 /* $FreeBSD: if_em.c,v 1.46 2004/09/29 18:28:28 mlaier Exp $ */ 36 37 #include <dev/pci/if_em.h> 38 #include <dev/pci/if_em_soc.h> 39 40 /********************************************************************* 41 * Driver version 42 *********************************************************************/ 43 44 #define EM_DRIVER_VERSION "6.2.9" 45 46 /********************************************************************* 47 * PCI Device ID Table 48 *********************************************************************/ 49 const struct pci_matchid em_devices[] = { 50 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80003ES2LAN_CPR_DPT }, 51 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80003ES2LAN_SDS_DPT }, 52 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80003ES2LAN_CPR_SPT }, 53 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80003ES2LAN_SDS_SPT }, 54 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM }, 55 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM_LOM }, 56 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP }, 57 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LOM }, 58 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LP }, 59 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI }, 60 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI_MOBILE }, 61 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541ER }, 62 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541ER_LOM }, 63 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI }, 64 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI_LF }, 65 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI_MOBILE }, 66 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82542 }, 67 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_COPPER }, 68 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_FIBER }, 69 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_COPPER }, 70 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_FIBER }, 71 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_COPPER }, 72 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_LOM }, 73 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_COPPER }, 74 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_FIBER }, 75 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_COPPER }, 76 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_FIBER }, 77 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_SERDES }, 78 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_COPPER }, 79 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_FIBER }, 80 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_QUAD_CPR }, 81 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_COPPER }, 82 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_FIBER }, 83 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_PCIE }, 84 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_QUAD_CPR }, 85 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_QUAD_CPR_K }, 86 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_SERDES }, 87 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_2 }, 88 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547EI }, 89 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547EI_MOBILE }, 90 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547GI }, 91 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_AF }, 92 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_AT }, 93 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_COPPER }, 94 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_FIBER }, 95 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_QUAD_CPR }, 96 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_QUAD_CPR_LP }, 97 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_QUAD_FBR }, 98 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_SERDES }, 99 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_SDS_DUAL }, 100 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_SDS_QUAD }, 101 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571PT_QUAD_CPR }, 102 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI_COPPER }, 103 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI_FIBER }, 104 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI_SERDES }, 105 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI }, 106 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573E }, 107 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573E_IAMT }, 108 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573E_PM }, 109 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573L }, 110 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573L_PL_1 }, 111 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573L_PL_2 }, 112 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573V_PM }, 113 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82574L }, 114 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82574LA }, 115 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82575EB_COPPER }, 116 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82575EB_SERDES }, 117 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82575GB_QUAD_CPR }, 118 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82575GB_QP_PM }, 119 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576 }, 120 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_FIBER }, 121 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_SERDES }, 122 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_QUAD_COPPER }, 123 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_QUAD_CU_ET2 }, 124 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_NS }, 125 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_NS_SERDES }, 126 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_SERDES_QUAD }, 127 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82577LC }, 128 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82577LM }, 129 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82578DC }, 130 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82578DM }, 131 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82579LM }, 132 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82579V }, 133 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_COPPER }, 134 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_FIBER }, 135 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_SERDES }, 136 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_SGMII }, 137 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_COPPER_NF }, 138 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_SERDES_NF }, 139 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I211_COPPER }, 140 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I217_LM }, 141 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I217_V }, 142 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_LM }, 143 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_LM_2 }, 144 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_LM_3 }, 145 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_V }, 146 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_V_2 }, 147 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_V_3 }, 148 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_LM }, 149 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_V }, 150 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_LM2 }, 151 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_V2 }, 152 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_COPPER }, 153 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_FIBER }, 154 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_SERDES }, 155 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_SGMII }, 156 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_COPPER_DUAL }, 157 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_QUAD_FIBER }, 158 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCC_SGMII }, 159 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCC_SERDES }, 160 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCC_BPLANE }, 161 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCC_SFP }, 162 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82583V }, 163 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I350_COPPER }, 164 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I350_FIBER }, 165 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I350_SERDES }, 166 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I350_SGMII }, 167 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I354_BP_1GBPS }, 168 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I354_BP_2_5GBPS }, 169 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I354_SGMII }, 170 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_82567V_3 }, 171 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_IFE }, 172 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_IFE_G }, 173 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_IFE_GT }, 174 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_IGP_AMT }, 175 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_IGP_C }, 176 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_IGP_M }, 177 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_IGP_M_AMT }, 178 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_BM }, 179 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IFE }, 180 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IFE_G }, 181 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IFE_GT }, 182 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IGP_AMT }, 183 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IGP_C }, 184 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IGP_M }, 185 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IGP_M_AMT }, 186 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IGP_M_V }, 187 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH10_D_BM_LF }, 188 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH10_D_BM_LM }, 189 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH10_R_BM_LF }, 190 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH10_R_BM_LM }, 191 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH10_R_BM_V }, 192 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EP80579_LAN_1 }, 193 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EP80579_LAN_2 }, 194 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EP80579_LAN_3 }, 195 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EP80579_LAN_4 }, 196 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EP80579_LAN_5 }, 197 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EP80579_LAN_6 } 198 }; 199 200 /********************************************************************* 201 * Function prototypes 202 *********************************************************************/ 203 int em_probe(struct device *, void *, void *); 204 void em_attach(struct device *, struct device *, void *); 205 void em_defer_attach(struct device*); 206 int em_detach(struct device *, int); 207 int em_activate(struct device *, int); 208 int em_intr(void *); 209 void em_start(struct ifqueue *); 210 int em_ioctl(struct ifnet *, u_long, caddr_t); 211 void em_watchdog(struct ifnet *); 212 void em_init(void *); 213 void em_stop(void *, int); 214 void em_media_status(struct ifnet *, struct ifmediareq *); 215 int em_media_change(struct ifnet *); 216 uint64_t em_flowstatus(struct em_softc *); 217 void em_identify_hardware(struct em_softc *); 218 int em_allocate_pci_resources(struct em_softc *); 219 void em_free_pci_resources(struct em_softc *); 220 void em_local_timer(void *); 221 int em_hardware_init(struct em_softc *); 222 void em_setup_interface(struct em_softc *); 223 int em_setup_transmit_structures(struct em_softc *); 224 void em_initialize_transmit_unit(struct em_softc *); 225 int em_setup_receive_structures(struct em_softc *); 226 void em_initialize_receive_unit(struct em_softc *); 227 void em_enable_intr(struct em_softc *); 228 void em_disable_intr(struct em_softc *); 229 void em_free_transmit_structures(struct em_softc *); 230 void em_free_receive_structures(struct em_softc *); 231 void em_update_stats_counters(struct em_softc *); 232 void em_disable_aspm(struct em_softc *); 233 void em_txeof(struct em_softc *); 234 int em_allocate_receive_structures(struct em_softc *); 235 int em_allocate_transmit_structures(struct em_softc *); 236 int em_rxfill(struct em_softc *); 237 int em_rxeof(struct em_softc *); 238 void em_receive_checksum(struct em_softc *, struct em_rx_desc *, 239 struct mbuf *); 240 u_int em_transmit_checksum_setup(struct em_softc *, struct mbuf *, u_int, 241 u_int32_t *, u_int32_t *); 242 void em_iff(struct em_softc *); 243 #ifdef EM_DEBUG 244 void em_print_hw_stats(struct em_softc *); 245 #endif 246 void em_update_link_status(struct em_softc *); 247 int em_get_buf(struct em_softc *, int); 248 void em_enable_hw_vlans(struct em_softc *); 249 u_int em_encap(struct em_softc *, struct mbuf *); 250 void em_smartspeed(struct em_softc *); 251 int em_82547_fifo_workaround(struct em_softc *, int); 252 void em_82547_update_fifo_head(struct em_softc *, int); 253 int em_82547_tx_fifo_reset(struct em_softc *); 254 void em_82547_move_tail(void *arg); 255 void em_82547_move_tail_locked(struct em_softc *); 256 int em_dma_malloc(struct em_softc *, bus_size_t, struct em_dma_alloc *); 257 void em_dma_free(struct em_softc *, struct em_dma_alloc *); 258 u_int32_t em_fill_descriptors(u_int64_t address, u_int32_t length, 259 PDESC_ARRAY desc_array); 260 void em_flush_tx_ring(struct em_softc *); 261 void em_flush_rx_ring(struct em_softc *); 262 void em_flush_desc_rings(struct em_softc *); 263 264 /********************************************************************* 265 * OpenBSD Device Interface Entry Points 266 *********************************************************************/ 267 268 struct cfattach em_ca = { 269 sizeof(struct em_softc), em_probe, em_attach, em_detach, 270 em_activate 271 }; 272 273 struct cfdriver em_cd = { 274 NULL, "em", DV_IFNET 275 }; 276 277 static int em_smart_pwr_down = FALSE; 278 279 /********************************************************************* 280 * Device identification routine 281 * 282 * em_probe determines if the driver should be loaded on 283 * adapter based on PCI vendor/device id of the adapter. 284 * 285 * return 0 on no match, positive on match 286 *********************************************************************/ 287 288 int 289 em_probe(struct device *parent, void *match, void *aux) 290 { 291 INIT_DEBUGOUT("em_probe: begin"); 292 293 return (pci_matchbyid((struct pci_attach_args *)aux, em_devices, 294 nitems(em_devices))); 295 } 296 297 void 298 em_defer_attach(struct device *self) 299 { 300 struct em_softc *sc = (struct em_softc *)self; 301 struct pci_attach_args *pa = &sc->osdep.em_pa; 302 pci_chipset_tag_t pc = pa->pa_pc; 303 void *gcu; 304 305 INIT_DEBUGOUT("em_defer_attach: begin"); 306 307 if ((gcu = em_lookup_gcu(self)) == 0) { 308 printf("%s: No GCU found, defered attachment failed\n", 309 DEVNAME(sc)); 310 311 if (sc->sc_intrhand) 312 pci_intr_disestablish(pc, sc->sc_intrhand); 313 sc->sc_intrhand = 0; 314 315 em_stop(sc, 1); 316 317 em_free_pci_resources(sc); 318 319 sc->sc_rx_desc_ring = NULL; 320 em_dma_free(sc, &sc->sc_rx_dma); 321 sc->sc_tx_desc_ring = NULL; 322 em_dma_free(sc, &sc->sc_tx_dma); 323 324 return; 325 } 326 327 sc->hw.gcu = gcu; 328 329 em_attach_miibus(self); 330 331 em_setup_interface(sc); 332 333 em_setup_link(&sc->hw); 334 335 em_update_link_status(sc); 336 } 337 338 /********************************************************************* 339 * Device initialization routine 340 * 341 * The attach entry point is called when the driver is being loaded. 342 * This routine identifies the type of hardware, allocates all resources 343 * and initializes the hardware. 344 * 345 *********************************************************************/ 346 347 void 348 em_attach(struct device *parent, struct device *self, void *aux) 349 { 350 struct pci_attach_args *pa = aux; 351 struct em_softc *sc; 352 int defer = 0; 353 354 INIT_DEBUGOUT("em_attach: begin"); 355 356 sc = (struct em_softc *)self; 357 sc->sc_dmat = pa->pa_dmat; 358 sc->osdep.em_pa = *pa; 359 360 timeout_set(&sc->timer_handle, em_local_timer, sc); 361 timeout_set(&sc->tx_fifo_timer_handle, em_82547_move_tail, sc); 362 363 /* Determine hardware revision */ 364 em_identify_hardware(sc); 365 366 /* 367 * Only use MSI on the newer PCIe parts, with the exception 368 * of 82571/82572 due to "Byte Enables 2 and 3 Are Not Set" errata 369 */ 370 if (sc->hw.mac_type <= em_82572) 371 sc->osdep.em_pa.pa_flags &= ~PCI_FLAGS_MSI_ENABLED; 372 373 /* Parameters (to be read from user) */ 374 if (sc->hw.mac_type >= em_82544) { 375 sc->sc_tx_slots = EM_MAX_TXD; 376 sc->sc_rx_slots = EM_MAX_RXD; 377 } else { 378 sc->sc_tx_slots = EM_MAX_TXD_82543; 379 sc->sc_rx_slots = EM_MAX_RXD_82543; 380 } 381 sc->tx_int_delay = EM_TIDV; 382 sc->tx_abs_int_delay = EM_TADV; 383 sc->rx_int_delay = EM_RDTR; 384 sc->rx_abs_int_delay = EM_RADV; 385 sc->hw.autoneg = DO_AUTO_NEG; 386 sc->hw.wait_autoneg_complete = WAIT_FOR_AUTO_NEG_DEFAULT; 387 sc->hw.autoneg_advertised = AUTONEG_ADV_DEFAULT; 388 sc->hw.tbi_compatibility_en = TRUE; 389 sc->sc_rx_buffer_len = EM_RXBUFFER_2048; 390 391 sc->hw.phy_init_script = 1; 392 sc->hw.phy_reset_disable = FALSE; 393 394 #ifndef EM_MASTER_SLAVE 395 sc->hw.master_slave = em_ms_hw_default; 396 #else 397 sc->hw.master_slave = EM_MASTER_SLAVE; 398 #endif 399 400 /* 401 * This controls when hardware reports transmit completion 402 * status. 403 */ 404 sc->hw.report_tx_early = 1; 405 406 if (em_allocate_pci_resources(sc)) 407 goto err_pci; 408 409 /* Initialize eeprom parameters */ 410 em_init_eeprom_params(&sc->hw); 411 412 /* 413 * Set the max frame size assuming standard Ethernet 414 * sized frames. 415 */ 416 switch (sc->hw.mac_type) { 417 case em_82573: 418 { 419 uint16_t eeprom_data = 0; 420 421 /* 422 * 82573 only supports Jumbo frames 423 * if ASPM is disabled. 424 */ 425 em_read_eeprom(&sc->hw, EEPROM_INIT_3GIO_3, 426 1, &eeprom_data); 427 if (eeprom_data & EEPROM_WORD1A_ASPM_MASK) { 428 sc->hw.max_frame_size = ETHER_MAX_LEN; 429 break; 430 } 431 /* Allow Jumbo frames */ 432 /* FALLTHROUGH */ 433 } 434 case em_82571: 435 case em_82572: 436 case em_82574: 437 case em_82575: 438 case em_82580: 439 case em_i210: 440 case em_i350: 441 case em_ich9lan: 442 case em_ich10lan: 443 case em_pch2lan: 444 case em_pch_lpt: 445 case em_pch_spt: 446 case em_80003es2lan: 447 /* 9K Jumbo Frame size */ 448 sc->hw.max_frame_size = 9234; 449 break; 450 case em_pchlan: 451 sc->hw.max_frame_size = 4096; 452 break; 453 case em_82542_rev2_0: 454 case em_82542_rev2_1: 455 case em_ich8lan: 456 /* Adapters that do not support Jumbo frames */ 457 sc->hw.max_frame_size = ETHER_MAX_LEN; 458 break; 459 default: 460 sc->hw.max_frame_size = 461 MAX_JUMBO_FRAME_SIZE; 462 } 463 464 sc->hw.min_frame_size = 465 ETHER_MIN_LEN + ETHER_CRC_LEN; 466 467 /* Allocate Transmit Descriptor ring */ 468 if (em_dma_malloc(sc, sc->sc_tx_slots * sizeof(struct em_tx_desc), 469 &sc->sc_tx_dma) != 0) { 470 printf("%s: Unable to allocate tx_desc memory\n", 471 DEVNAME(sc)); 472 goto err_tx_desc; 473 } 474 sc->sc_tx_desc_ring = (struct em_tx_desc *)sc->sc_tx_dma.dma_vaddr; 475 476 /* Allocate Receive Descriptor ring */ 477 if (em_dma_malloc(sc, sc->sc_rx_slots * sizeof(struct em_rx_desc), 478 &sc->sc_rx_dma) != 0) { 479 printf("%s: Unable to allocate rx_desc memory\n", 480 DEVNAME(sc)); 481 goto err_rx_desc; 482 } 483 sc->sc_rx_desc_ring = (struct em_rx_desc *)sc->sc_rx_dma.dma_vaddr; 484 485 /* Initialize the hardware */ 486 if ((defer = em_hardware_init(sc))) { 487 if (defer == EAGAIN) 488 config_defer(self, em_defer_attach); 489 else { 490 printf("%s: Unable to initialize the hardware\n", 491 DEVNAME(sc)); 492 goto err_hw_init; 493 } 494 } 495 496 if (sc->hw.mac_type == em_80003es2lan || sc->hw.mac_type == em_82575 || 497 sc->hw.mac_type == em_82580 || sc->hw.mac_type == em_i210 || 498 sc->hw.mac_type == em_i350) { 499 uint32_t reg = EM_READ_REG(&sc->hw, E1000_STATUS); 500 sc->hw.bus_func = (reg & E1000_STATUS_FUNC_MASK) >> 501 E1000_STATUS_FUNC_SHIFT; 502 503 switch (sc->hw.bus_func) { 504 case 0: 505 sc->hw.swfw = E1000_SWFW_PHY0_SM; 506 break; 507 case 1: 508 sc->hw.swfw = E1000_SWFW_PHY1_SM; 509 break; 510 case 2: 511 sc->hw.swfw = E1000_SWFW_PHY2_SM; 512 break; 513 case 3: 514 sc->hw.swfw = E1000_SWFW_PHY3_SM; 515 break; 516 } 517 } else { 518 sc->hw.bus_func = 0; 519 } 520 521 /* Copy the permanent MAC address out of the EEPROM */ 522 if (em_read_mac_addr(&sc->hw) < 0) { 523 printf("%s: EEPROM read error while reading mac address\n", 524 DEVNAME(sc)); 525 goto err_mac_addr; 526 } 527 528 bcopy(sc->hw.mac_addr, sc->sc_ac.ac_enaddr, ETHER_ADDR_LEN); 529 530 /* Setup OS specific network interface */ 531 if (!defer) 532 em_setup_interface(sc); 533 534 /* Initialize statistics */ 535 em_clear_hw_cntrs(&sc->hw); 536 #ifndef SMALL_KERNEL 537 em_update_stats_counters(sc); 538 #endif 539 sc->hw.get_link_status = 1; 540 if (!defer) 541 em_update_link_status(sc); 542 543 printf(", address %s\n", ether_sprintf(sc->sc_ac.ac_enaddr)); 544 545 /* Indicate SOL/IDER usage */ 546 if (em_check_phy_reset_block(&sc->hw)) 547 printf("%s: PHY reset is blocked due to SOL/IDER session.\n", 548 DEVNAME(sc)); 549 550 /* Identify 82544 on PCI-X */ 551 em_get_bus_info(&sc->hw); 552 if (sc->hw.bus_type == em_bus_type_pcix && 553 sc->hw.mac_type == em_82544) 554 sc->pcix_82544 = TRUE; 555 else 556 sc->pcix_82544 = FALSE; 557 558 sc->hw.icp_xxxx_is_link_up = FALSE; 559 560 INIT_DEBUGOUT("em_attach: end"); 561 return; 562 563 err_mac_addr: 564 err_hw_init: 565 sc->sc_rx_desc_ring = NULL; 566 em_dma_free(sc, &sc->sc_rx_dma); 567 err_rx_desc: 568 sc->sc_tx_desc_ring = NULL; 569 em_dma_free(sc, &sc->sc_tx_dma); 570 err_tx_desc: 571 err_pci: 572 em_free_pci_resources(sc); 573 } 574 575 /********************************************************************* 576 * Transmit entry point 577 * 578 * em_start is called by the stack to initiate a transmit. 579 * The driver will remain in this routine as long as there are 580 * packets to transmit and transmit resources are available. 581 * In case resources are not available stack is notified and 582 * the packet is requeued. 583 **********************************************************************/ 584 585 void 586 em_start(struct ifqueue *ifq) 587 { 588 struct ifnet *ifp = ifq->ifq_if; 589 struct em_softc *sc = ifp->if_softc; 590 u_int head, free, used; 591 struct mbuf *m; 592 int post = 0; 593 594 if (!sc->link_active) { 595 ifq_purge(ifq); 596 return; 597 } 598 599 /* calculate free space */ 600 head = sc->sc_tx_desc_head; 601 free = sc->sc_tx_desc_tail; 602 if (free <= head) 603 free += sc->sc_tx_slots; 604 free -= head; 605 606 if (sc->hw.mac_type != em_82547) { 607 bus_dmamap_sync(sc->sc_dmat, sc->sc_tx_dma.dma_map, 608 0, sc->sc_tx_dma.dma_map->dm_mapsize, 609 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 610 } 611 612 for (;;) { 613 /* use 2 because cksum setup can use an extra slot */ 614 if (EM_MAX_SCATTER + 2 > free) { 615 ifq_set_oactive(ifq); 616 break; 617 } 618 619 m = ifq_dequeue(ifq); 620 if (m == NULL) 621 break; 622 623 used = em_encap(sc, m); 624 if (used == 0) { 625 m_freem(m); 626 continue; 627 } 628 629 KASSERT(used <= free); 630 631 free -= used; 632 633 #if NBPFILTER > 0 634 /* Send a copy of the frame to the BPF listener */ 635 if (ifp->if_bpf) 636 bpf_mtap_ether(ifp->if_bpf, m, BPF_DIRECTION_OUT); 637 #endif 638 639 /* Set timeout in case hardware has problems transmitting */ 640 ifp->if_timer = EM_TX_TIMEOUT; 641 642 if (sc->hw.mac_type == em_82547) { 643 int len = m->m_pkthdr.len; 644 645 if (sc->link_duplex == HALF_DUPLEX) 646 em_82547_move_tail_locked(sc); 647 else { 648 E1000_WRITE_REG(&sc->hw, TDT, 649 sc->sc_tx_desc_head); 650 em_82547_update_fifo_head(sc, len); 651 } 652 } 653 654 post = 1; 655 } 656 657 if (sc->hw.mac_type != em_82547) { 658 bus_dmamap_sync(sc->sc_dmat, sc->sc_tx_dma.dma_map, 659 0, sc->sc_tx_dma.dma_map->dm_mapsize, 660 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 661 /* 662 * Advance the Transmit Descriptor Tail (Tdt), 663 * this tells the E1000 that this frame is 664 * available to transmit. 665 */ 666 if (post) 667 E1000_WRITE_REG(&sc->hw, TDT, sc->sc_tx_desc_head); 668 } 669 } 670 671 /********************************************************************* 672 * Ioctl entry point 673 * 674 * em_ioctl is called when the user wants to configure the 675 * interface. 676 * 677 * return 0 on success, positive on failure 678 **********************************************************************/ 679 680 int 681 em_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 682 { 683 int error = 0; 684 struct ifreq *ifr = (struct ifreq *) data; 685 struct em_softc *sc = ifp->if_softc; 686 int s; 687 688 s = splnet(); 689 690 switch (command) { 691 case SIOCSIFADDR: 692 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFADDR (Set Interface " 693 "Addr)"); 694 if (!(ifp->if_flags & IFF_UP)) { 695 ifp->if_flags |= IFF_UP; 696 em_init(sc); 697 } 698 break; 699 700 case SIOCSIFFLAGS: 701 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFFLAGS (Set Interface Flags)"); 702 if (ifp->if_flags & IFF_UP) { 703 if (ifp->if_flags & IFF_RUNNING) 704 error = ENETRESET; 705 else 706 em_init(sc); 707 } else { 708 if (ifp->if_flags & IFF_RUNNING) 709 em_stop(sc, 0); 710 } 711 break; 712 713 case SIOCSIFMEDIA: 714 /* Check SOL/IDER usage */ 715 if (em_check_phy_reset_block(&sc->hw)) { 716 printf("%s: Media change is blocked due to SOL/IDER session.\n", 717 DEVNAME(sc)); 718 break; 719 } 720 case SIOCGIFMEDIA: 721 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCxIFMEDIA (Get/Set Interface Media)"); 722 error = ifmedia_ioctl(ifp, ifr, &sc->media, command); 723 break; 724 725 case SIOCGIFRXR: 726 error = if_rxr_ioctl((struct if_rxrinfo *)ifr->ifr_data, 727 NULL, EM_MCLBYTES, &sc->sc_rx_ring); 728 break; 729 730 default: 731 error = ether_ioctl(ifp, &sc->sc_ac, command, data); 732 } 733 734 if (error == ENETRESET) { 735 if (ifp->if_flags & IFF_RUNNING) { 736 em_disable_intr(sc); 737 em_iff(sc); 738 if (sc->hw.mac_type == em_82542_rev2_0) 739 em_initialize_receive_unit(sc); 740 em_enable_intr(sc); 741 } 742 error = 0; 743 } 744 745 splx(s); 746 return (error); 747 } 748 749 /********************************************************************* 750 * Watchdog entry point 751 * 752 * This routine is called whenever hardware quits transmitting. 753 * 754 **********************************************************************/ 755 756 void 757 em_watchdog(struct ifnet *ifp) 758 { 759 struct em_softc *sc = ifp->if_softc; 760 761 /* If we are in this routine because of pause frames, then 762 * don't reset the hardware. 763 */ 764 if (E1000_READ_REG(&sc->hw, STATUS) & E1000_STATUS_TXOFF) { 765 ifp->if_timer = EM_TX_TIMEOUT; 766 return; 767 } 768 printf("%s: watchdog: head %u tail %u TDH %u TDT %u\n", 769 DEVNAME(sc), 770 sc->sc_tx_desc_head, sc->sc_tx_desc_tail, 771 E1000_READ_REG(&sc->hw, TDH), E1000_READ_REG(&sc->hw, TDT)); 772 773 em_init(sc); 774 775 sc->watchdog_events++; 776 } 777 778 /********************************************************************* 779 * Init entry point 780 * 781 * This routine is used in two ways. It is used by the stack as 782 * init entry point in network interface structure. It is also used 783 * by the driver as a hw/sw initialization routine to get to a 784 * consistent state. 785 * 786 **********************************************************************/ 787 788 void 789 em_init(void *arg) 790 { 791 struct em_softc *sc = arg; 792 struct ifnet *ifp = &sc->sc_ac.ac_if; 793 uint32_t pba; 794 int s; 795 796 s = splnet(); 797 798 INIT_DEBUGOUT("em_init: begin"); 799 800 em_stop(sc, 0); 801 802 /* 803 * Packet Buffer Allocation (PBA) 804 * Writing PBA sets the receive portion of the buffer 805 * the remainder is used for the transmit buffer. 806 * 807 * Devices before the 82547 had a Packet Buffer of 64K. 808 * Default allocation: PBA=48K for Rx, leaving 16K for Tx. 809 * After the 82547 the buffer was reduced to 40K. 810 * Default allocation: PBA=30K for Rx, leaving 10K for Tx. 811 * Note: default does not leave enough room for Jumbo Frame >10k. 812 */ 813 switch (sc->hw.mac_type) { 814 case em_82547: 815 case em_82547_rev_2: /* 82547: Total Packet Buffer is 40K */ 816 if (sc->hw.max_frame_size > EM_RXBUFFER_8192) 817 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 818 else 819 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 820 sc->tx_fifo_head = 0; 821 sc->tx_head_addr = pba << EM_TX_HEAD_ADDR_SHIFT; 822 sc->tx_fifo_size = (E1000_PBA_40K - pba) << EM_PBA_BYTES_SHIFT; 823 break; 824 case em_82571: 825 case em_82572: /* Total Packet Buffer on these is 48k */ 826 case em_82575: 827 case em_82580: 828 case em_80003es2lan: 829 case em_i350: 830 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 831 break; 832 case em_i210: 833 pba = E1000_PBA_34K; 834 break; 835 case em_82573: /* 82573: Total Packet Buffer is 32K */ 836 /* Jumbo frames not supported */ 837 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 838 break; 839 case em_82574: /* Total Packet Buffer is 40k */ 840 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */ 841 break; 842 case em_ich8lan: 843 pba = E1000_PBA_8K; 844 break; 845 case em_ich9lan: 846 case em_ich10lan: 847 /* Boost Receive side for jumbo frames */ 848 if (sc->hw.max_frame_size > EM_RXBUFFER_4096) 849 pba = E1000_PBA_14K; 850 else 851 pba = E1000_PBA_10K; 852 break; 853 case em_pchlan: 854 case em_pch2lan: 855 case em_pch_lpt: 856 case em_pch_spt: 857 pba = E1000_PBA_26K; 858 break; 859 default: 860 /* Devices before 82547 had a Packet Buffer of 64K. */ 861 if (sc->hw.max_frame_size > EM_RXBUFFER_8192) 862 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 863 else 864 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 865 } 866 INIT_DEBUGOUT1("em_init: pba=%dK",pba); 867 E1000_WRITE_REG(&sc->hw, PBA, pba); 868 869 /* Get the latest mac address, User can use a LAA */ 870 bcopy(sc->sc_ac.ac_enaddr, sc->hw.mac_addr, ETHER_ADDR_LEN); 871 872 /* Initialize the hardware */ 873 if (em_hardware_init(sc)) { 874 printf("%s: Unable to initialize the hardware\n", 875 DEVNAME(sc)); 876 splx(s); 877 return; 878 } 879 em_update_link_status(sc); 880 881 E1000_WRITE_REG(&sc->hw, VET, ETHERTYPE_VLAN); 882 if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) 883 em_enable_hw_vlans(sc); 884 885 /* Prepare transmit descriptors and buffers */ 886 if (em_setup_transmit_structures(sc)) { 887 printf("%s: Could not setup transmit structures\n", 888 DEVNAME(sc)); 889 em_stop(sc, 0); 890 splx(s); 891 return; 892 } 893 em_initialize_transmit_unit(sc); 894 895 /* Prepare receive descriptors and buffers */ 896 if (em_setup_receive_structures(sc)) { 897 printf("%s: Could not setup receive structures\n", 898 DEVNAME(sc)); 899 em_stop(sc, 0); 900 splx(s); 901 return; 902 } 903 em_initialize_receive_unit(sc); 904 905 /* Program promiscuous mode and multicast filters. */ 906 em_iff(sc); 907 908 ifp->if_flags |= IFF_RUNNING; 909 ifq_clr_oactive(&ifp->if_snd); 910 911 timeout_add_sec(&sc->timer_handle, 1); 912 em_clear_hw_cntrs(&sc->hw); 913 em_enable_intr(sc); 914 915 /* Don't reset the phy next time init gets called */ 916 sc->hw.phy_reset_disable = TRUE; 917 918 splx(s); 919 } 920 921 /********************************************************************* 922 * 923 * Interrupt Service routine 924 * 925 **********************************************************************/ 926 int 927 em_intr(void *arg) 928 { 929 struct em_softc *sc = arg; 930 struct ifnet *ifp = &sc->sc_ac.ac_if; 931 u_int32_t reg_icr, test_icr; 932 933 test_icr = reg_icr = E1000_READ_REG(&sc->hw, ICR); 934 if (sc->hw.mac_type >= em_82571) 935 test_icr = (reg_icr & E1000_ICR_INT_ASSERTED); 936 if (!test_icr) 937 return (0); 938 939 if (ifp->if_flags & IFF_RUNNING) { 940 em_txeof(sc); 941 942 if (em_rxeof(sc) || ISSET(reg_icr, E1000_ICR_RXO)) { 943 if (em_rxfill(sc)) { 944 E1000_WRITE_REG(&sc->hw, RDT, 945 sc->sc_rx_desc_head); 946 } 947 } 948 } 949 950 /* Link status change */ 951 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 952 KERNEL_LOCK(); 953 sc->hw.get_link_status = 1; 954 em_check_for_link(&sc->hw); 955 em_update_link_status(sc); 956 KERNEL_UNLOCK(); 957 } 958 959 return (1); 960 } 961 962 /********************************************************************* 963 * 964 * Media Ioctl callback 965 * 966 * This routine is called whenever the user queries the status of 967 * the interface using ifconfig. 968 * 969 **********************************************************************/ 970 void 971 em_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 972 { 973 struct em_softc *sc = ifp->if_softc; 974 uint64_t fiber_type = IFM_1000_SX; 975 u_int16_t gsr; 976 977 INIT_DEBUGOUT("em_media_status: begin"); 978 979 em_check_for_link(&sc->hw); 980 em_update_link_status(sc); 981 982 ifmr->ifm_status = IFM_AVALID; 983 ifmr->ifm_active = IFM_ETHER; 984 985 if (!sc->link_active) { 986 ifmr->ifm_active |= IFM_NONE; 987 return; 988 } 989 990 ifmr->ifm_status |= IFM_ACTIVE; 991 992 if (sc->hw.media_type == em_media_type_fiber || 993 sc->hw.media_type == em_media_type_internal_serdes) { 994 if (sc->hw.mac_type == em_82545) 995 fiber_type = IFM_1000_LX; 996 ifmr->ifm_active |= fiber_type | IFM_FDX; 997 } else { 998 switch (sc->link_speed) { 999 case 10: 1000 ifmr->ifm_active |= IFM_10_T; 1001 break; 1002 case 100: 1003 ifmr->ifm_active |= IFM_100_TX; 1004 break; 1005 case 1000: 1006 ifmr->ifm_active |= IFM_1000_T; 1007 break; 1008 } 1009 1010 if (sc->link_duplex == FULL_DUPLEX) 1011 ifmr->ifm_active |= em_flowstatus(sc) | IFM_FDX; 1012 else 1013 ifmr->ifm_active |= IFM_HDX; 1014 1015 if (IFM_SUBTYPE(ifmr->ifm_active) == IFM_1000_T) { 1016 em_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &gsr); 1017 if (gsr & SR_1000T_MS_CONFIG_RES) 1018 ifmr->ifm_active |= IFM_ETH_MASTER; 1019 } 1020 } 1021 } 1022 1023 /********************************************************************* 1024 * 1025 * Media Ioctl callback 1026 * 1027 * This routine is called when the user changes speed/duplex using 1028 * media/mediopt option with ifconfig. 1029 * 1030 **********************************************************************/ 1031 int 1032 em_media_change(struct ifnet *ifp) 1033 { 1034 struct em_softc *sc = ifp->if_softc; 1035 struct ifmedia *ifm = &sc->media; 1036 1037 INIT_DEBUGOUT("em_media_change: begin"); 1038 1039 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1040 return (EINVAL); 1041 1042 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1043 case IFM_AUTO: 1044 sc->hw.autoneg = DO_AUTO_NEG; 1045 sc->hw.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1046 break; 1047 case IFM_1000_LX: 1048 case IFM_1000_SX: 1049 case IFM_1000_T: 1050 sc->hw.autoneg = DO_AUTO_NEG; 1051 sc->hw.autoneg_advertised = ADVERTISE_1000_FULL; 1052 break; 1053 case IFM_100_TX: 1054 sc->hw.autoneg = FALSE; 1055 sc->hw.autoneg_advertised = 0; 1056 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1057 sc->hw.forced_speed_duplex = em_100_full; 1058 else 1059 sc->hw.forced_speed_duplex = em_100_half; 1060 break; 1061 case IFM_10_T: 1062 sc->hw.autoneg = FALSE; 1063 sc->hw.autoneg_advertised = 0; 1064 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1065 sc->hw.forced_speed_duplex = em_10_full; 1066 else 1067 sc->hw.forced_speed_duplex = em_10_half; 1068 break; 1069 default: 1070 printf("%s: Unsupported media type\n", DEVNAME(sc)); 1071 } 1072 1073 /* 1074 * As the speed/duplex settings may have changed we need to 1075 * reset the PHY. 1076 */ 1077 sc->hw.phy_reset_disable = FALSE; 1078 1079 em_init(sc); 1080 1081 return (0); 1082 } 1083 1084 uint64_t 1085 em_flowstatus(struct em_softc *sc) 1086 { 1087 u_int16_t ar, lpar; 1088 1089 if (sc->hw.media_type == em_media_type_fiber || 1090 sc->hw.media_type == em_media_type_internal_serdes) 1091 return (0); 1092 1093 em_read_phy_reg(&sc->hw, PHY_AUTONEG_ADV, &ar); 1094 em_read_phy_reg(&sc->hw, PHY_LP_ABILITY, &lpar); 1095 1096 if ((ar & NWAY_AR_PAUSE) && (lpar & NWAY_LPAR_PAUSE)) 1097 return (IFM_FLOW|IFM_ETH_TXPAUSE|IFM_ETH_RXPAUSE); 1098 else if (!(ar & NWAY_AR_PAUSE) && (ar & NWAY_AR_ASM_DIR) && 1099 (lpar & NWAY_LPAR_PAUSE) && (lpar & NWAY_LPAR_ASM_DIR)) 1100 return (IFM_FLOW|IFM_ETH_TXPAUSE); 1101 else if ((ar & NWAY_AR_PAUSE) && (ar & NWAY_AR_ASM_DIR) && 1102 !(lpar & NWAY_LPAR_PAUSE) && (lpar & NWAY_LPAR_ASM_DIR)) 1103 return (IFM_FLOW|IFM_ETH_RXPAUSE); 1104 1105 return (0); 1106 } 1107 1108 /********************************************************************* 1109 * 1110 * This routine maps the mbufs to tx descriptors. 1111 * 1112 * return 0 on success, positive on failure 1113 **********************************************************************/ 1114 u_int 1115 em_encap(struct em_softc *sc, struct mbuf *m) 1116 { 1117 struct em_packet *pkt; 1118 struct em_tx_desc *desc; 1119 bus_dmamap_t map; 1120 u_int32_t txd_upper, txd_lower; 1121 u_int head, last, used = 0; 1122 int i, j; 1123 1124 /* For 82544 Workaround */ 1125 DESC_ARRAY desc_array; 1126 u_int32_t array_elements; 1127 1128 /* get a dmamap for this packet from the next free slot */ 1129 head = sc->sc_tx_desc_head; 1130 pkt = &sc->sc_tx_pkts_ring[head]; 1131 map = pkt->pkt_map; 1132 1133 switch (bus_dmamap_load_mbuf(sc->sc_dmat, map, m, BUS_DMA_NOWAIT)) { 1134 case 0: 1135 break; 1136 case EFBIG: 1137 if (m_defrag(m, M_DONTWAIT) == 0 && 1138 bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1139 BUS_DMA_NOWAIT) == 0) 1140 break; 1141 1142 /* FALLTHROUGH */ 1143 default: 1144 sc->no_tx_dma_setup++; 1145 return (0); 1146 } 1147 1148 bus_dmamap_sync(sc->sc_dmat, map, 1149 0, map->dm_mapsize, 1150 BUS_DMASYNC_PREWRITE); 1151 1152 if (sc->hw.mac_type == em_82547) { 1153 bus_dmamap_sync(sc->sc_dmat, sc->sc_tx_dma.dma_map, 1154 0, sc->sc_tx_dma.dma_map->dm_mapsize, 1155 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1156 } 1157 1158 if (sc->hw.mac_type >= em_82543 && sc->hw.mac_type != em_82575 && 1159 sc->hw.mac_type != em_82580 && sc->hw.mac_type != em_i210 && 1160 sc->hw.mac_type != em_i350) { 1161 used += em_transmit_checksum_setup(sc, m, head, 1162 &txd_upper, &txd_lower); 1163 } else { 1164 txd_upper = txd_lower = 0; 1165 } 1166 1167 head += used; 1168 if (head >= sc->sc_tx_slots) 1169 head -= sc->sc_tx_slots; 1170 1171 for (i = 0; i < map->dm_nsegs; i++) { 1172 /* If sc is 82544 and on PCI-X bus */ 1173 if (sc->pcix_82544) { 1174 /* 1175 * Check the Address and Length combination and 1176 * split the data accordingly 1177 */ 1178 array_elements = em_fill_descriptors( 1179 map->dm_segs[i].ds_addr, map->dm_segs[i].ds_len, 1180 &desc_array); 1181 for (j = 0; j < array_elements; j++) { 1182 desc = &sc->sc_tx_desc_ring[head]; 1183 1184 desc->buffer_addr = htole64( 1185 desc_array.descriptor[j].address); 1186 desc->lower.data = htole32( 1187 (sc->sc_txd_cmd | txd_lower | 1188 (u_int16_t)desc_array.descriptor[j].length)); 1189 desc->upper.data = htole32(txd_upper); 1190 1191 last = head; 1192 if (++head == sc->sc_tx_slots) 1193 head = 0; 1194 1195 used++; 1196 } 1197 } else { 1198 desc = &sc->sc_tx_desc_ring[head]; 1199 1200 desc->buffer_addr = htole64(map->dm_segs[i].ds_addr); 1201 desc->lower.data = htole32(sc->sc_txd_cmd | 1202 txd_lower | map->dm_segs[i].ds_len); 1203 desc->upper.data = htole32(txd_upper); 1204 1205 last = head; 1206 if (++head == sc->sc_tx_slots) 1207 head = 0; 1208 1209 used++; 1210 } 1211 } 1212 1213 #if NVLAN > 0 1214 /* Find out if we are in VLAN mode */ 1215 if (m->m_flags & M_VLANTAG) { 1216 /* Set the VLAN id */ 1217 desc->upper.fields.special = htole16(m->m_pkthdr.ether_vtag); 1218 1219 /* Tell hardware to add tag */ 1220 desc->lower.data |= htole32(E1000_TXD_CMD_VLE); 1221 } 1222 #endif 1223 1224 /* mark the packet with the mbuf and last desc slot */ 1225 pkt->pkt_m = m; 1226 pkt->pkt_eop = last; 1227 1228 sc->sc_tx_desc_head = head; 1229 1230 /* 1231 * Last Descriptor of Packet 1232 * needs End Of Packet (EOP) 1233 * and Report Status (RS) 1234 */ 1235 desc->lower.data |= htole32(E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS); 1236 1237 if (sc->hw.mac_type == em_82547) { 1238 bus_dmamap_sync(sc->sc_dmat, sc->sc_tx_dma.dma_map, 1239 0, sc->sc_tx_dma.dma_map->dm_mapsize, 1240 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1241 } 1242 1243 return (used); 1244 } 1245 1246 /********************************************************************* 1247 * 1248 * 82547 workaround to avoid controller hang in half-duplex environment. 1249 * The workaround is to avoid queuing a large packet that would span 1250 * the internal Tx FIFO ring boundary. We need to reset the FIFO pointers 1251 * in this case. We do that only when FIFO is quiescent. 1252 * 1253 **********************************************************************/ 1254 void 1255 em_82547_move_tail_locked(struct em_softc *sc) 1256 { 1257 uint16_t hw_tdt; 1258 uint16_t sw_tdt; 1259 struct em_tx_desc *tx_desc; 1260 uint16_t length = 0; 1261 boolean_t eop = 0; 1262 1263 hw_tdt = E1000_READ_REG(&sc->hw, TDT); 1264 sw_tdt = sc->sc_tx_desc_head; 1265 1266 while (hw_tdt != sw_tdt) { 1267 tx_desc = &sc->sc_tx_desc_ring[hw_tdt]; 1268 length += tx_desc->lower.flags.length; 1269 eop = tx_desc->lower.data & E1000_TXD_CMD_EOP; 1270 if (++hw_tdt == sc->sc_tx_slots) 1271 hw_tdt = 0; 1272 1273 if (eop) { 1274 if (em_82547_fifo_workaround(sc, length)) { 1275 sc->tx_fifo_wrk_cnt++; 1276 timeout_add(&sc->tx_fifo_timer_handle, 1); 1277 break; 1278 } 1279 E1000_WRITE_REG(&sc->hw, TDT, hw_tdt); 1280 em_82547_update_fifo_head(sc, length); 1281 length = 0; 1282 } 1283 } 1284 } 1285 1286 void 1287 em_82547_move_tail(void *arg) 1288 { 1289 struct em_softc *sc = arg; 1290 int s; 1291 1292 s = splnet(); 1293 em_82547_move_tail_locked(sc); 1294 splx(s); 1295 } 1296 1297 int 1298 em_82547_fifo_workaround(struct em_softc *sc, int len) 1299 { 1300 int fifo_space, fifo_pkt_len; 1301 1302 fifo_pkt_len = EM_ROUNDUP(len + EM_FIFO_HDR, EM_FIFO_HDR); 1303 1304 if (sc->link_duplex == HALF_DUPLEX) { 1305 fifo_space = sc->tx_fifo_size - sc->tx_fifo_head; 1306 1307 if (fifo_pkt_len >= (EM_82547_PKT_THRESH + fifo_space)) { 1308 if (em_82547_tx_fifo_reset(sc)) 1309 return (0); 1310 else 1311 return (1); 1312 } 1313 } 1314 1315 return (0); 1316 } 1317 1318 void 1319 em_82547_update_fifo_head(struct em_softc *sc, int len) 1320 { 1321 int fifo_pkt_len = EM_ROUNDUP(len + EM_FIFO_HDR, EM_FIFO_HDR); 1322 1323 /* tx_fifo_head is always 16 byte aligned */ 1324 sc->tx_fifo_head += fifo_pkt_len; 1325 if (sc->tx_fifo_head >= sc->tx_fifo_size) 1326 sc->tx_fifo_head -= sc->tx_fifo_size; 1327 } 1328 1329 int 1330 em_82547_tx_fifo_reset(struct em_softc *sc) 1331 { 1332 uint32_t tctl; 1333 1334 if ((E1000_READ_REG(&sc->hw, TDT) == 1335 E1000_READ_REG(&sc->hw, TDH)) && 1336 (E1000_READ_REG(&sc->hw, TDFT) == 1337 E1000_READ_REG(&sc->hw, TDFH)) && 1338 (E1000_READ_REG(&sc->hw, TDFTS) == 1339 E1000_READ_REG(&sc->hw, TDFHS)) && 1340 (E1000_READ_REG(&sc->hw, TDFPC) == 0)) { 1341 1342 /* Disable TX unit */ 1343 tctl = E1000_READ_REG(&sc->hw, TCTL); 1344 E1000_WRITE_REG(&sc->hw, TCTL, tctl & ~E1000_TCTL_EN); 1345 1346 /* Reset FIFO pointers */ 1347 E1000_WRITE_REG(&sc->hw, TDFT, sc->tx_head_addr); 1348 E1000_WRITE_REG(&sc->hw, TDFH, sc->tx_head_addr); 1349 E1000_WRITE_REG(&sc->hw, TDFTS, sc->tx_head_addr); 1350 E1000_WRITE_REG(&sc->hw, TDFHS, sc->tx_head_addr); 1351 1352 /* Re-enable TX unit */ 1353 E1000_WRITE_REG(&sc->hw, TCTL, tctl); 1354 E1000_WRITE_FLUSH(&sc->hw); 1355 1356 sc->tx_fifo_head = 0; 1357 sc->tx_fifo_reset_cnt++; 1358 1359 return (TRUE); 1360 } else 1361 return (FALSE); 1362 } 1363 1364 void 1365 em_iff(struct em_softc *sc) 1366 { 1367 struct ifnet *ifp = &sc->sc_ac.ac_if; 1368 struct arpcom *ac = &sc->sc_ac; 1369 u_int32_t reg_rctl = 0; 1370 u_int8_t mta[MAX_NUM_MULTICAST_ADDRESSES * ETH_LENGTH_OF_ADDRESS]; 1371 struct ether_multi *enm; 1372 struct ether_multistep step; 1373 int i = 0; 1374 1375 IOCTL_DEBUGOUT("em_iff: begin"); 1376 1377 if (sc->hw.mac_type == em_82542_rev2_0) { 1378 reg_rctl = E1000_READ_REG(&sc->hw, RCTL); 1379 if (sc->hw.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1380 em_pci_clear_mwi(&sc->hw); 1381 reg_rctl |= E1000_RCTL_RST; 1382 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 1383 msec_delay(5); 1384 } 1385 1386 reg_rctl = E1000_READ_REG(&sc->hw, RCTL); 1387 reg_rctl &= ~(E1000_RCTL_MPE | E1000_RCTL_UPE); 1388 ifp->if_flags &= ~IFF_ALLMULTI; 1389 1390 if (ifp->if_flags & IFF_PROMISC || ac->ac_multirangecnt > 0 || 1391 ac->ac_multicnt > MAX_NUM_MULTICAST_ADDRESSES) { 1392 ifp->if_flags |= IFF_ALLMULTI; 1393 reg_rctl |= E1000_RCTL_MPE; 1394 if (ifp->if_flags & IFF_PROMISC) 1395 reg_rctl |= E1000_RCTL_UPE; 1396 } else { 1397 ETHER_FIRST_MULTI(step, ac, enm); 1398 while (enm != NULL) { 1399 bcopy(enm->enm_addrlo, mta + i, ETH_LENGTH_OF_ADDRESS); 1400 i += ETH_LENGTH_OF_ADDRESS; 1401 1402 ETHER_NEXT_MULTI(step, enm); 1403 } 1404 1405 em_mc_addr_list_update(&sc->hw, mta, ac->ac_multicnt, 0, 1); 1406 } 1407 1408 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 1409 1410 if (sc->hw.mac_type == em_82542_rev2_0) { 1411 reg_rctl = E1000_READ_REG(&sc->hw, RCTL); 1412 reg_rctl &= ~E1000_RCTL_RST; 1413 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 1414 msec_delay(5); 1415 if (sc->hw.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1416 em_pci_set_mwi(&sc->hw); 1417 } 1418 } 1419 1420 /********************************************************************* 1421 * Timer routine 1422 * 1423 * This routine checks for link status and updates statistics. 1424 * 1425 **********************************************************************/ 1426 1427 void 1428 em_local_timer(void *arg) 1429 { 1430 struct ifnet *ifp; 1431 struct em_softc *sc = arg; 1432 int s; 1433 1434 ifp = &sc->sc_ac.ac_if; 1435 1436 s = splnet(); 1437 1438 #ifndef SMALL_KERNEL 1439 em_update_stats_counters(sc); 1440 #ifdef EM_DEBUG 1441 if (ifp->if_flags & IFF_DEBUG && ifp->if_flags & IFF_RUNNING) 1442 em_print_hw_stats(sc); 1443 #endif 1444 #endif 1445 em_smartspeed(sc); 1446 1447 timeout_add_sec(&sc->timer_handle, 1); 1448 1449 splx(s); 1450 } 1451 1452 void 1453 em_update_link_status(struct em_softc *sc) 1454 { 1455 struct ifnet *ifp = &sc->sc_ac.ac_if; 1456 1457 if (E1000_READ_REG(&sc->hw, STATUS) & E1000_STATUS_LU) { 1458 if (sc->link_active == 0) { 1459 em_get_speed_and_duplex(&sc->hw, 1460 &sc->link_speed, 1461 &sc->link_duplex); 1462 /* Check if we may set SPEED_MODE bit on PCI-E */ 1463 if ((sc->link_speed == SPEED_1000) && 1464 ((sc->hw.mac_type == em_82571) || 1465 (sc->hw.mac_type == em_82572) || 1466 (sc->hw.mac_type == em_82575) || 1467 (sc->hw.mac_type == em_82580))) { 1468 int tarc0; 1469 1470 tarc0 = E1000_READ_REG(&sc->hw, TARC0); 1471 tarc0 |= SPEED_MODE_BIT; 1472 E1000_WRITE_REG(&sc->hw, TARC0, tarc0); 1473 } 1474 sc->link_active = 1; 1475 sc->smartspeed = 0; 1476 ifp->if_baudrate = IF_Mbps(sc->link_speed); 1477 } 1478 if (!LINK_STATE_IS_UP(ifp->if_link_state)) { 1479 if (sc->link_duplex == FULL_DUPLEX) 1480 ifp->if_link_state = LINK_STATE_FULL_DUPLEX; 1481 else 1482 ifp->if_link_state = LINK_STATE_HALF_DUPLEX; 1483 if_link_state_change(ifp); 1484 } 1485 } else { 1486 if (sc->link_active == 1) { 1487 ifp->if_baudrate = sc->link_speed = 0; 1488 sc->link_duplex = 0; 1489 sc->link_active = 0; 1490 } 1491 if (ifp->if_link_state != LINK_STATE_DOWN) { 1492 ifp->if_link_state = LINK_STATE_DOWN; 1493 if_link_state_change(ifp); 1494 } 1495 } 1496 } 1497 1498 /********************************************************************* 1499 * 1500 * This routine disables all traffic on the adapter by issuing a 1501 * global reset on the MAC and deallocates TX/RX buffers. 1502 * 1503 **********************************************************************/ 1504 1505 void 1506 em_stop(void *arg, int softonly) 1507 { 1508 struct em_softc *sc = arg; 1509 struct ifnet *ifp = &sc->sc_ac.ac_if; 1510 1511 /* Tell the stack that the interface is no longer active */ 1512 ifp->if_flags &= ~IFF_RUNNING; 1513 1514 INIT_DEBUGOUT("em_stop: begin"); 1515 1516 timeout_del(&sc->timer_handle); 1517 timeout_del(&sc->tx_fifo_timer_handle); 1518 1519 if (!softonly) 1520 em_disable_intr(sc); 1521 if (sc->hw.mac_type == em_pch_spt) 1522 em_flush_desc_rings(sc); 1523 if (!softonly) 1524 em_reset_hw(&sc->hw); 1525 1526 intr_barrier(sc->sc_intrhand); 1527 ifq_barrier(&ifp->if_snd); 1528 1529 KASSERT((ifp->if_flags & IFF_RUNNING) == 0); 1530 1531 ifq_clr_oactive(&ifp->if_snd); 1532 ifp->if_timer = 0; 1533 1534 em_free_transmit_structures(sc); 1535 em_free_receive_structures(sc); 1536 } 1537 1538 /********************************************************************* 1539 * 1540 * Determine hardware revision. 1541 * 1542 **********************************************************************/ 1543 void 1544 em_identify_hardware(struct em_softc *sc) 1545 { 1546 u_int32_t reg; 1547 struct pci_attach_args *pa = &sc->osdep.em_pa; 1548 1549 /* Make sure our PCI config space has the necessary stuff set */ 1550 sc->hw.pci_cmd_word = pci_conf_read(pa->pa_pc, pa->pa_tag, 1551 PCI_COMMAND_STATUS_REG); 1552 1553 /* Save off the information about this board */ 1554 sc->hw.vendor_id = PCI_VENDOR(pa->pa_id); 1555 sc->hw.device_id = PCI_PRODUCT(pa->pa_id); 1556 1557 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG); 1558 sc->hw.revision_id = PCI_REVISION(reg); 1559 1560 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 1561 sc->hw.subsystem_vendor_id = PCI_VENDOR(reg); 1562 sc->hw.subsystem_id = PCI_PRODUCT(reg); 1563 1564 /* Identify the MAC */ 1565 if (em_set_mac_type(&sc->hw)) 1566 printf("%s: Unknown MAC Type\n", DEVNAME(sc)); 1567 1568 if (sc->hw.mac_type == em_pchlan) 1569 sc->hw.revision_id = PCI_PRODUCT(pa->pa_id) & 0x0f; 1570 1571 if (sc->hw.mac_type == em_82541 || 1572 sc->hw.mac_type == em_82541_rev_2 || 1573 sc->hw.mac_type == em_82547 || 1574 sc->hw.mac_type == em_82547_rev_2) 1575 sc->hw.phy_init_script = TRUE; 1576 } 1577 1578 void 1579 em_legacy_irq_quirk_spt(struct em_softc *sc) 1580 { 1581 uint32_t reg; 1582 1583 /* Legacy interrupt: SPT needs a quirk. */ 1584 if (sc->hw.mac_type != em_pch_spt) 1585 return; 1586 if (sc->legacy_irq == 0) 1587 return; 1588 1589 reg = EM_READ_REG(&sc->hw, E1000_FEXTNVM7); 1590 reg |= E1000_FEXTNVM7_SIDE_CLK_UNGATE; 1591 EM_WRITE_REG(&sc->hw, E1000_FEXTNVM7, reg); 1592 1593 reg = EM_READ_REG(&sc->hw, E1000_FEXTNVM9); 1594 reg |= E1000_FEXTNVM9_IOSFSB_CLKGATE_DIS | 1595 E1000_FEXTNVM9_IOSFSB_CLKREQ_DIS; 1596 EM_WRITE_REG(&sc->hw, E1000_FEXTNVM9, reg); 1597 } 1598 1599 int 1600 em_allocate_pci_resources(struct em_softc *sc) 1601 { 1602 int val, rid; 1603 pci_intr_handle_t ih; 1604 const char *intrstr = NULL; 1605 struct pci_attach_args *pa = &sc->osdep.em_pa; 1606 pci_chipset_tag_t pc = pa->pa_pc; 1607 1608 val = pci_conf_read(pa->pa_pc, pa->pa_tag, EM_MMBA); 1609 if (PCI_MAPREG_TYPE(val) != PCI_MAPREG_TYPE_MEM) { 1610 printf(": mmba is not mem space\n"); 1611 return (ENXIO); 1612 } 1613 if (pci_mapreg_map(pa, EM_MMBA, PCI_MAPREG_MEM_TYPE(val), 0, 1614 &sc->osdep.mem_bus_space_tag, &sc->osdep.mem_bus_space_handle, 1615 &sc->osdep.em_membase, &sc->osdep.em_memsize, 0)) { 1616 printf(": cannot find mem space\n"); 1617 return (ENXIO); 1618 } 1619 1620 switch (sc->hw.mac_type) { 1621 case em_82544: 1622 case em_82540: 1623 case em_82545: 1624 case em_82546: 1625 case em_82541: 1626 case em_82541_rev_2: 1627 /* Figure out where our I/O BAR is ? */ 1628 for (rid = PCI_MAPREG_START; rid < PCI_MAPREG_END;) { 1629 val = pci_conf_read(pa->pa_pc, pa->pa_tag, rid); 1630 if (PCI_MAPREG_TYPE(val) == PCI_MAPREG_TYPE_IO) { 1631 sc->io_rid = rid; 1632 break; 1633 } 1634 rid += 4; 1635 if (PCI_MAPREG_MEM_TYPE(val) == 1636 PCI_MAPREG_MEM_TYPE_64BIT) 1637 rid += 4; /* skip high bits, too */ 1638 } 1639 1640 if (pci_mapreg_map(pa, rid, PCI_MAPREG_TYPE_IO, 0, 1641 &sc->osdep.io_bus_space_tag, &sc->osdep.io_bus_space_handle, 1642 &sc->osdep.em_iobase, &sc->osdep.em_iosize, 0)) { 1643 printf(": cannot find i/o space\n"); 1644 return (ENXIO); 1645 } 1646 1647 sc->hw.io_base = 0; 1648 break; 1649 default: 1650 break; 1651 } 1652 1653 sc->osdep.em_flashoffset = 0; 1654 /* for ICH8 and family we need to find the flash memory */ 1655 if (sc->hw.mac_type == em_pch_spt) { 1656 sc->osdep.flash_bus_space_tag = sc->osdep.mem_bus_space_tag; 1657 sc->osdep.flash_bus_space_handle = sc->osdep.mem_bus_space_handle; 1658 sc->osdep.em_flashbase = 0; 1659 sc->osdep.em_flashsize = 0; 1660 sc->osdep.em_flashoffset = 0xe000; 1661 } else if (IS_ICH8(sc->hw.mac_type)) { 1662 val = pci_conf_read(pa->pa_pc, pa->pa_tag, EM_FLASH); 1663 if (PCI_MAPREG_TYPE(val) != PCI_MAPREG_TYPE_MEM) { 1664 printf(": flash is not mem space\n"); 1665 return (ENXIO); 1666 } 1667 1668 if (pci_mapreg_map(pa, EM_FLASH, PCI_MAPREG_MEM_TYPE(val), 0, 1669 &sc->osdep.flash_bus_space_tag, &sc->osdep.flash_bus_space_handle, 1670 &sc->osdep.em_flashbase, &sc->osdep.em_flashsize, 0)) { 1671 printf(": cannot find mem space\n"); 1672 return (ENXIO); 1673 } 1674 } 1675 1676 sc->legacy_irq = 0; 1677 if (pci_intr_map_msi(pa, &ih)) { 1678 if (pci_intr_map(pa, &ih)) { 1679 printf(": couldn't map interrupt\n"); 1680 return (ENXIO); 1681 } 1682 sc->legacy_irq = 1; 1683 } 1684 1685 sc->osdep.dev = (struct device *)sc; 1686 sc->hw.back = &sc->osdep; 1687 1688 intrstr = pci_intr_string(pc, ih); 1689 sc->sc_intrhand = pci_intr_establish(pc, ih, IPL_NET | IPL_MPSAFE, 1690 em_intr, sc, DEVNAME(sc)); 1691 if (sc->sc_intrhand == NULL) { 1692 printf(": couldn't establish interrupt"); 1693 if (intrstr != NULL) 1694 printf(" at %s", intrstr); 1695 printf("\n"); 1696 return (ENXIO); 1697 } 1698 printf(": %s", intrstr); 1699 1700 /* 1701 * the ICP_xxxx device has multiple, duplicate register sets for 1702 * use when it is being used as a network processor. Disable those 1703 * registers here, as they are not necessary in this context and 1704 * can confuse the system 1705 */ 1706 if(sc->hw.mac_type == em_icp_xxxx) { 1707 int offset; 1708 pcireg_t val; 1709 1710 if (!pci_get_capability(sc->osdep.em_pa.pa_pc, 1711 sc->osdep.em_pa.pa_tag, PCI_CAP_ID_ST, &offset, &val)) { 1712 return (0); 1713 } 1714 offset += PCI_ST_SMIA_OFFSET; 1715 pci_conf_write(sc->osdep.em_pa.pa_pc, sc->osdep.em_pa.pa_tag, 1716 offset, 0x06); 1717 E1000_WRITE_REG(&sc->hw, IMC1, ~0x0); 1718 E1000_WRITE_REG(&sc->hw, IMC2, ~0x0); 1719 } 1720 return (0); 1721 } 1722 1723 void 1724 em_free_pci_resources(struct em_softc *sc) 1725 { 1726 struct pci_attach_args *pa = &sc->osdep.em_pa; 1727 pci_chipset_tag_t pc = pa->pa_pc; 1728 1729 if (sc->sc_intrhand) 1730 pci_intr_disestablish(pc, sc->sc_intrhand); 1731 sc->sc_intrhand = 0; 1732 1733 if (sc->osdep.em_flashbase) 1734 bus_space_unmap(sc->osdep.flash_bus_space_tag, sc->osdep.flash_bus_space_handle, 1735 sc->osdep.em_flashsize); 1736 sc->osdep.em_flashbase = 0; 1737 1738 if (sc->osdep.em_iobase) 1739 bus_space_unmap(sc->osdep.io_bus_space_tag, sc->osdep.io_bus_space_handle, 1740 sc->osdep.em_iosize); 1741 sc->osdep.em_iobase = 0; 1742 1743 if (sc->osdep.em_membase) 1744 bus_space_unmap(sc->osdep.mem_bus_space_tag, sc->osdep.mem_bus_space_handle, 1745 sc->osdep.em_memsize); 1746 sc->osdep.em_membase = 0; 1747 } 1748 1749 /********************************************************************* 1750 * 1751 * Initialize the hardware to a configuration as specified by the 1752 * em_softc structure. The controller is reset, the EEPROM is 1753 * verified, the MAC address is set, then the shared initialization 1754 * routines are called. 1755 * 1756 **********************************************************************/ 1757 int 1758 em_hardware_init(struct em_softc *sc) 1759 { 1760 uint32_t ret_val; 1761 u_int16_t rx_buffer_size; 1762 1763 INIT_DEBUGOUT("em_hardware_init: begin"); 1764 if (sc->hw.mac_type == em_pch_spt) 1765 em_flush_desc_rings(sc); 1766 /* Issue a global reset */ 1767 em_reset_hw(&sc->hw); 1768 1769 /* When hardware is reset, fifo_head is also reset */ 1770 sc->tx_fifo_head = 0; 1771 1772 /* Make sure we have a good EEPROM before we read from it */ 1773 if (em_get_flash_presence_i210(&sc->hw) && 1774 em_validate_eeprom_checksum(&sc->hw) < 0) { 1775 /* 1776 * Some PCIe parts fail the first check due to 1777 * the link being in sleep state, call it again, 1778 * if it fails a second time its a real issue. 1779 */ 1780 if (em_validate_eeprom_checksum(&sc->hw) < 0) { 1781 printf("%s: The EEPROM Checksum Is Not Valid\n", 1782 DEVNAME(sc)); 1783 return (EIO); 1784 } 1785 } 1786 1787 if (em_get_flash_presence_i210(&sc->hw) && 1788 em_read_part_num(&sc->hw, &(sc->part_num)) < 0) { 1789 printf("%s: EEPROM read error while reading part number\n", 1790 DEVNAME(sc)); 1791 return (EIO); 1792 } 1793 1794 /* Set up smart power down as default off on newer adapters */ 1795 if (!em_smart_pwr_down && 1796 (sc->hw.mac_type == em_82571 || 1797 sc->hw.mac_type == em_82572 || 1798 sc->hw.mac_type == em_82575 || 1799 sc->hw.mac_type == em_82580 || 1800 sc->hw.mac_type == em_i210 || 1801 sc->hw.mac_type == em_i350 )) { 1802 uint16_t phy_tmp = 0; 1803 1804 /* Speed up time to link by disabling smart power down */ 1805 em_read_phy_reg(&sc->hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 1806 phy_tmp &= ~IGP02E1000_PM_SPD; 1807 em_write_phy_reg(&sc->hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp); 1808 } 1809 1810 em_legacy_irq_quirk_spt(sc); 1811 1812 /* 1813 * These parameters control the automatic generation (Tx) and 1814 * response (Rx) to Ethernet PAUSE frames. 1815 * - High water mark should allow for at least two frames to be 1816 * received after sending an XOFF. 1817 * - Low water mark works best when it is very near the high water mark. 1818 * This allows the receiver to restart by sending XON when it has 1819 * drained a bit. Here we use an arbitary value of 1500 which will 1820 * restart after one full frame is pulled from the buffer. There 1821 * could be several smaller frames in the buffer and if so they will 1822 * not trigger the XON until their total number reduces the buffer 1823 * by 1500. 1824 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 1825 */ 1826 rx_buffer_size = ((E1000_READ_REG(&sc->hw, PBA) & 0xffff) << 10 ); 1827 1828 sc->hw.fc_high_water = rx_buffer_size - 1829 EM_ROUNDUP(sc->hw.max_frame_size, 1024); 1830 sc->hw.fc_low_water = sc->hw.fc_high_water - 1500; 1831 if (sc->hw.mac_type == em_80003es2lan) 1832 sc->hw.fc_pause_time = 0xFFFF; 1833 else 1834 sc->hw.fc_pause_time = 1000; 1835 sc->hw.fc_send_xon = TRUE; 1836 sc->hw.fc = E1000_FC_FULL; 1837 1838 em_disable_aspm(sc); 1839 1840 if ((ret_val = em_init_hw(&sc->hw)) != 0) { 1841 if (ret_val == E1000_DEFER_INIT) { 1842 INIT_DEBUGOUT("\nHardware Initialization Deferred "); 1843 return (EAGAIN); 1844 } 1845 printf("\n%s: Hardware Initialization Failed\n", 1846 DEVNAME(sc)); 1847 return (EIO); 1848 } 1849 1850 em_check_for_link(&sc->hw); 1851 1852 return (0); 1853 } 1854 1855 /********************************************************************* 1856 * 1857 * Setup networking device structure and register an interface. 1858 * 1859 **********************************************************************/ 1860 void 1861 em_setup_interface(struct em_softc *sc) 1862 { 1863 struct ifnet *ifp; 1864 uint64_t fiber_type = IFM_1000_SX; 1865 1866 INIT_DEBUGOUT("em_setup_interface: begin"); 1867 1868 ifp = &sc->sc_ac.ac_if; 1869 strlcpy(ifp->if_xname, DEVNAME(sc), IFNAMSIZ); 1870 ifp->if_softc = sc; 1871 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1872 ifp->if_xflags = IFXF_MPSAFE; 1873 ifp->if_ioctl = em_ioctl; 1874 ifp->if_qstart = em_start; 1875 ifp->if_watchdog = em_watchdog; 1876 ifp->if_hardmtu = 1877 sc->hw.max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN; 1878 IFQ_SET_MAXLEN(&ifp->if_snd, sc->sc_tx_slots - 1); 1879 1880 ifp->if_capabilities = IFCAP_VLAN_MTU; 1881 1882 #if NVLAN > 0 1883 if (sc->hw.mac_type != em_82575 && sc->hw.mac_type != em_82580 && 1884 sc->hw.mac_type != em_i210 && sc->hw.mac_type != em_i350) 1885 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 1886 #endif 1887 1888 if (sc->hw.mac_type >= em_82543 && sc->hw.mac_type != em_82575 && 1889 sc->hw.mac_type != em_82580 && sc->hw.mac_type != em_i210 && 1890 sc->hw.mac_type != em_i350) 1891 ifp->if_capabilities |= IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 1892 1893 /* 1894 * Specify the media types supported by this adapter and register 1895 * callbacks to update media and link information 1896 */ 1897 ifmedia_init(&sc->media, IFM_IMASK, em_media_change, 1898 em_media_status); 1899 if (sc->hw.media_type == em_media_type_fiber || 1900 sc->hw.media_type == em_media_type_internal_serdes) { 1901 if (sc->hw.mac_type == em_82545) 1902 fiber_type = IFM_1000_LX; 1903 ifmedia_add(&sc->media, IFM_ETHER | fiber_type | IFM_FDX, 1904 0, NULL); 1905 ifmedia_add(&sc->media, IFM_ETHER | fiber_type, 1906 0, NULL); 1907 } else { 1908 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL); 1909 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX, 1910 0, NULL); 1911 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 1912 0, NULL); 1913 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 1914 0, NULL); 1915 if (sc->hw.phy_type != em_phy_ife) { 1916 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 1917 0, NULL); 1918 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_T, 0, NULL); 1919 } 1920 } 1921 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL); 1922 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO); 1923 1924 if_attach(ifp); 1925 ether_ifattach(ifp); 1926 } 1927 1928 int 1929 em_detach(struct device *self, int flags) 1930 { 1931 struct em_softc *sc = (struct em_softc *)self; 1932 struct ifnet *ifp = &sc->sc_ac.ac_if; 1933 struct pci_attach_args *pa = &sc->osdep.em_pa; 1934 pci_chipset_tag_t pc = pa->pa_pc; 1935 1936 if (sc->sc_intrhand) 1937 pci_intr_disestablish(pc, sc->sc_intrhand); 1938 sc->sc_intrhand = 0; 1939 1940 em_stop(sc, 1); 1941 1942 em_free_pci_resources(sc); 1943 1944 if (sc->sc_rx_desc_ring != NULL) { 1945 sc->sc_rx_desc_ring = NULL; 1946 em_dma_free(sc, &sc->sc_rx_dma); 1947 } 1948 if (sc->sc_tx_desc_ring != NULL) { 1949 sc->sc_tx_desc_ring = NULL; 1950 em_dma_free(sc, &sc->sc_tx_dma); 1951 } 1952 1953 ether_ifdetach(ifp); 1954 if_detach(ifp); 1955 1956 return (0); 1957 } 1958 1959 int 1960 em_activate(struct device *self, int act) 1961 { 1962 struct em_softc *sc = (struct em_softc *)self; 1963 struct ifnet *ifp = &sc->sc_ac.ac_if; 1964 int rv = 0; 1965 1966 switch (act) { 1967 case DVACT_SUSPEND: 1968 if (ifp->if_flags & IFF_RUNNING) 1969 em_stop(sc, 0); 1970 /* We have no children atm, but we will soon */ 1971 rv = config_activate_children(self, act); 1972 break; 1973 case DVACT_RESUME: 1974 if (ifp->if_flags & IFF_UP) 1975 em_init(sc); 1976 break; 1977 default: 1978 rv = config_activate_children(self, act); 1979 break; 1980 } 1981 return (rv); 1982 } 1983 1984 /********************************************************************* 1985 * 1986 * Workaround for SmartSpeed on 82541 and 82547 controllers 1987 * 1988 **********************************************************************/ 1989 void 1990 em_smartspeed(struct em_softc *sc) 1991 { 1992 uint16_t phy_tmp; 1993 1994 if (sc->link_active || (sc->hw.phy_type != em_phy_igp) || 1995 !sc->hw.autoneg || !(sc->hw.autoneg_advertised & ADVERTISE_1000_FULL)) 1996 return; 1997 1998 if (sc->smartspeed == 0) { 1999 /* If Master/Slave config fault is asserted twice, 2000 * we assume back-to-back */ 2001 em_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2002 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2003 return; 2004 em_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2005 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2006 em_read_phy_reg(&sc->hw, PHY_1000T_CTRL, 2007 &phy_tmp); 2008 if (phy_tmp & CR_1000T_MS_ENABLE) { 2009 phy_tmp &= ~CR_1000T_MS_ENABLE; 2010 em_write_phy_reg(&sc->hw, 2011 PHY_1000T_CTRL, phy_tmp); 2012 sc->smartspeed++; 2013 if (sc->hw.autoneg && 2014 !em_phy_setup_autoneg(&sc->hw) && 2015 !em_read_phy_reg(&sc->hw, PHY_CTRL, 2016 &phy_tmp)) { 2017 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2018 MII_CR_RESTART_AUTO_NEG); 2019 em_write_phy_reg(&sc->hw, 2020 PHY_CTRL, phy_tmp); 2021 } 2022 } 2023 } 2024 return; 2025 } else if (sc->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 2026 /* If still no link, perhaps using 2/3 pair cable */ 2027 em_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp); 2028 phy_tmp |= CR_1000T_MS_ENABLE; 2029 em_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp); 2030 if (sc->hw.autoneg && 2031 !em_phy_setup_autoneg(&sc->hw) && 2032 !em_read_phy_reg(&sc->hw, PHY_CTRL, &phy_tmp)) { 2033 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2034 MII_CR_RESTART_AUTO_NEG); 2035 em_write_phy_reg(&sc->hw, PHY_CTRL, phy_tmp); 2036 } 2037 } 2038 /* Restart process after EM_SMARTSPEED_MAX iterations */ 2039 if (sc->smartspeed++ == EM_SMARTSPEED_MAX) 2040 sc->smartspeed = 0; 2041 } 2042 2043 /* 2044 * Manage DMA'able memory. 2045 */ 2046 int 2047 em_dma_malloc(struct em_softc *sc, bus_size_t size, struct em_dma_alloc *dma) 2048 { 2049 int r; 2050 2051 r = bus_dmamap_create(sc->sc_dmat, size, 1, 2052 size, 0, BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, &dma->dma_map); 2053 if (r != 0) 2054 return (r); 2055 2056 r = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, &dma->dma_seg, 2057 1, &dma->dma_nseg, BUS_DMA_WAITOK | BUS_DMA_ZERO); 2058 if (r != 0) 2059 goto destroy; 2060 2061 r = bus_dmamem_map(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg, size, 2062 &dma->dma_vaddr, BUS_DMA_WAITOK); 2063 if (r != 0) 2064 goto free; 2065 2066 r = bus_dmamap_load(sc->sc_dmat, dma->dma_map, dma->dma_vaddr, size, 2067 NULL, BUS_DMA_WAITOK); 2068 if (r != 0) 2069 goto unmap; 2070 2071 dma->dma_size = size; 2072 return (0); 2073 2074 unmap: 2075 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, size); 2076 free: 2077 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 2078 destroy: 2079 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 2080 2081 return (r); 2082 } 2083 2084 void 2085 em_dma_free(struct em_softc *sc, struct em_dma_alloc *dma) 2086 { 2087 bus_dmamap_unload(sc->sc_dmat, dma->dma_map); 2088 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, dma->dma_size); 2089 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 2090 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 2091 } 2092 2093 /********************************************************************* 2094 * 2095 * Allocate memory for tx_buffer structures. The tx_buffer stores all 2096 * the information needed to transmit a packet on the wire. 2097 * 2098 **********************************************************************/ 2099 int 2100 em_allocate_transmit_structures(struct em_softc *sc) 2101 { 2102 bus_dmamap_sync(sc->sc_dmat, sc->sc_tx_dma.dma_map, 2103 0, sc->sc_tx_dma.dma_map->dm_mapsize, 2104 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2105 2106 sc->sc_tx_pkts_ring = mallocarray(sc->sc_tx_slots, 2107 sizeof(*sc->sc_tx_pkts_ring), M_DEVBUF, M_NOWAIT | M_ZERO); 2108 if (sc->sc_tx_pkts_ring == NULL) { 2109 printf("%s: Unable to allocate tx_buffer memory\n", 2110 DEVNAME(sc)); 2111 return (ENOMEM); 2112 } 2113 2114 return (0); 2115 } 2116 2117 /********************************************************************* 2118 * 2119 * Allocate and initialize transmit structures. 2120 * 2121 **********************************************************************/ 2122 int 2123 em_setup_transmit_structures(struct em_softc *sc) 2124 { 2125 struct em_packet *pkt; 2126 int error, i; 2127 2128 if ((error = em_allocate_transmit_structures(sc)) != 0) 2129 goto fail; 2130 2131 bzero((void *) sc->sc_tx_desc_ring, 2132 (sizeof(struct em_tx_desc)) * sc->sc_tx_slots); 2133 2134 for (i = 0; i < sc->sc_tx_slots; i++) { 2135 pkt = &sc->sc_tx_pkts_ring[i]; 2136 error = bus_dmamap_create(sc->sc_dmat, MAX_JUMBO_FRAME_SIZE, 2137 EM_MAX_SCATTER / (sc->pcix_82544 ? 2 : 1), 2138 MAX_JUMBO_FRAME_SIZE, 0, BUS_DMA_NOWAIT, &pkt->pkt_map); 2139 if (error != 0) { 2140 printf("%s: Unable to create TX DMA map\n", 2141 DEVNAME(sc)); 2142 goto fail; 2143 } 2144 } 2145 2146 sc->sc_tx_desc_head = 0; 2147 sc->sc_tx_desc_tail = 0; 2148 2149 /* Set checksum context */ 2150 sc->active_checksum_context = OFFLOAD_NONE; 2151 2152 return (0); 2153 2154 fail: 2155 em_free_transmit_structures(sc); 2156 return (error); 2157 } 2158 2159 /********************************************************************* 2160 * 2161 * Enable transmit unit. 2162 * 2163 **********************************************************************/ 2164 void 2165 em_initialize_transmit_unit(struct em_softc *sc) 2166 { 2167 u_int32_t reg_tctl, reg_tipg = 0; 2168 u_int64_t bus_addr; 2169 2170 INIT_DEBUGOUT("em_initialize_transmit_unit: begin"); 2171 2172 /* Setup the Base and Length of the Tx Descriptor Ring */ 2173 bus_addr = sc->sc_tx_dma.dma_map->dm_segs[0].ds_addr; 2174 E1000_WRITE_REG(&sc->hw, TDLEN, 2175 sc->sc_tx_slots * 2176 sizeof(struct em_tx_desc)); 2177 E1000_WRITE_REG(&sc->hw, TDBAH, (u_int32_t)(bus_addr >> 32)); 2178 E1000_WRITE_REG(&sc->hw, TDBAL, (u_int32_t)bus_addr); 2179 2180 /* Setup the HW Tx Head and Tail descriptor pointers */ 2181 E1000_WRITE_REG(&sc->hw, TDT, 0); 2182 E1000_WRITE_REG(&sc->hw, TDH, 0); 2183 2184 HW_DEBUGOUT2("Base = %x, Length = %x\n", 2185 E1000_READ_REG(&sc->hw, TDBAL), 2186 E1000_READ_REG(&sc->hw, TDLEN)); 2187 2188 /* Set the default values for the Tx Inter Packet Gap timer */ 2189 switch (sc->hw.mac_type) { 2190 case em_82542_rev2_0: 2191 case em_82542_rev2_1: 2192 reg_tipg = DEFAULT_82542_TIPG_IPGT; 2193 reg_tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2194 reg_tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2195 break; 2196 case em_80003es2lan: 2197 reg_tipg = DEFAULT_82543_TIPG_IPGR1; 2198 reg_tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2199 break; 2200 default: 2201 if (sc->hw.media_type == em_media_type_fiber || 2202 sc->hw.media_type == em_media_type_internal_serdes) 2203 reg_tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 2204 else 2205 reg_tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 2206 reg_tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2207 reg_tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2208 } 2209 2210 2211 E1000_WRITE_REG(&sc->hw, TIPG, reg_tipg); 2212 E1000_WRITE_REG(&sc->hw, TIDV, sc->tx_int_delay); 2213 if (sc->hw.mac_type >= em_82540) 2214 E1000_WRITE_REG(&sc->hw, TADV, sc->tx_abs_int_delay); 2215 2216 /* Setup Transmit Descriptor Base Settings */ 2217 sc->sc_txd_cmd = E1000_TXD_CMD_IFCS; 2218 2219 if (sc->hw.mac_type == em_82575 || sc->hw.mac_type == em_82580 || 2220 sc->hw.mac_type == em_i210 || sc->hw.mac_type == em_i350) { 2221 /* 82575/6 need to enable the TX queue and lack the IDE bit */ 2222 reg_tctl = E1000_READ_REG(&sc->hw, TXDCTL); 2223 reg_tctl |= E1000_TXDCTL_QUEUE_ENABLE; 2224 E1000_WRITE_REG(&sc->hw, TXDCTL, reg_tctl); 2225 } else if (sc->tx_int_delay > 0) 2226 sc->sc_txd_cmd |= E1000_TXD_CMD_IDE; 2227 2228 /* Program the Transmit Control Register */ 2229 reg_tctl = E1000_TCTL_PSP | E1000_TCTL_EN | 2230 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 2231 if (sc->hw.mac_type >= em_82571) 2232 reg_tctl |= E1000_TCTL_MULR; 2233 if (sc->link_duplex == FULL_DUPLEX) 2234 reg_tctl |= E1000_FDX_COLLISION_DISTANCE << E1000_COLD_SHIFT; 2235 else 2236 reg_tctl |= E1000_HDX_COLLISION_DISTANCE << E1000_COLD_SHIFT; 2237 /* This write will effectively turn on the transmit unit */ 2238 E1000_WRITE_REG(&sc->hw, TCTL, reg_tctl); 2239 2240 /* SPT Si errata workaround to avoid data corruption */ 2241 2242 if (sc->hw.mac_type == em_pch_spt) { 2243 uint32_t reg_val; 2244 2245 reg_val = EM_READ_REG(&sc->hw, E1000_IOSFPC); 2246 reg_val |= E1000_RCTL_RDMTS_HEX; 2247 EM_WRITE_REG(&sc->hw, E1000_IOSFPC, reg_val); 2248 2249 reg_val = E1000_READ_REG(&sc->hw, TARC0); 2250 reg_val |= E1000_TARC0_CB_MULTIQ_3_REQ; 2251 E1000_WRITE_REG(&sc->hw, TARC0, reg_val); 2252 } 2253 } 2254 2255 /********************************************************************* 2256 * 2257 * Free all transmit related data structures. 2258 * 2259 **********************************************************************/ 2260 void 2261 em_free_transmit_structures(struct em_softc *sc) 2262 { 2263 struct em_packet *pkt; 2264 int i; 2265 2266 INIT_DEBUGOUT("free_transmit_structures: begin"); 2267 2268 if (sc->sc_tx_pkts_ring != NULL) { 2269 for (i = 0; i < sc->sc_tx_slots; i++) { 2270 pkt = &sc->sc_tx_pkts_ring[i]; 2271 2272 if (pkt->pkt_m != NULL) { 2273 bus_dmamap_sync(sc->sc_dmat, pkt->pkt_map, 2274 0, pkt->pkt_map->dm_mapsize, 2275 BUS_DMASYNC_POSTWRITE); 2276 bus_dmamap_unload(sc->sc_dmat, pkt->pkt_map); 2277 2278 m_freem(pkt->pkt_m); 2279 pkt->pkt_m = NULL; 2280 } 2281 2282 if (pkt->pkt_map != NULL) { 2283 bus_dmamap_destroy(sc->sc_dmat, pkt->pkt_map); 2284 pkt->pkt_map = NULL; 2285 } 2286 } 2287 2288 free(sc->sc_tx_pkts_ring, M_DEVBUF, 2289 sc->sc_tx_slots * sizeof(*sc->sc_tx_pkts_ring)); 2290 sc->sc_tx_pkts_ring = NULL; 2291 } 2292 2293 bus_dmamap_sync(sc->sc_dmat, sc->sc_tx_dma.dma_map, 2294 0, sc->sc_tx_dma.dma_map->dm_mapsize, 2295 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2296 } 2297 2298 /********************************************************************* 2299 * 2300 * The offload context needs to be set when we transfer the first 2301 * packet of a particular protocol (TCP/UDP). We change the 2302 * context only if the protocol type changes. 2303 * 2304 **********************************************************************/ 2305 u_int 2306 em_transmit_checksum_setup(struct em_softc *sc, struct mbuf *mp, u_int head, 2307 u_int32_t *txd_upper, u_int32_t *txd_lower) 2308 { 2309 struct em_context_desc *TXD; 2310 2311 if (mp->m_pkthdr.csum_flags & M_TCP_CSUM_OUT) { 2312 *txd_upper = E1000_TXD_POPTS_TXSM << 8; 2313 *txd_lower = E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 2314 if (sc->active_checksum_context == OFFLOAD_TCP_IP) 2315 return (0); 2316 else 2317 sc->active_checksum_context = OFFLOAD_TCP_IP; 2318 } else if (mp->m_pkthdr.csum_flags & M_UDP_CSUM_OUT) { 2319 *txd_upper = E1000_TXD_POPTS_TXSM << 8; 2320 *txd_lower = E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 2321 if (sc->active_checksum_context == OFFLOAD_UDP_IP) 2322 return (0); 2323 else 2324 sc->active_checksum_context = OFFLOAD_UDP_IP; 2325 } else { 2326 *txd_upper = 0; 2327 *txd_lower = 0; 2328 return (0); 2329 } 2330 2331 /* If we reach this point, the checksum offload context 2332 * needs to be reset. 2333 */ 2334 TXD = (struct em_context_desc *)&sc->sc_tx_desc_ring[head]; 2335 2336 TXD->lower_setup.ip_fields.ipcss = ETHER_HDR_LEN; 2337 TXD->lower_setup.ip_fields.ipcso = 2338 ETHER_HDR_LEN + offsetof(struct ip, ip_sum); 2339 TXD->lower_setup.ip_fields.ipcse = 2340 htole16(ETHER_HDR_LEN + sizeof(struct ip) - 1); 2341 2342 TXD->upper_setup.tcp_fields.tucss = 2343 ETHER_HDR_LEN + sizeof(struct ip); 2344 TXD->upper_setup.tcp_fields.tucse = htole16(0); 2345 2346 if (sc->active_checksum_context == OFFLOAD_TCP_IP) { 2347 TXD->upper_setup.tcp_fields.tucso = 2348 ETHER_HDR_LEN + sizeof(struct ip) + 2349 offsetof(struct tcphdr, th_sum); 2350 } else if (sc->active_checksum_context == OFFLOAD_UDP_IP) { 2351 TXD->upper_setup.tcp_fields.tucso = 2352 ETHER_HDR_LEN + sizeof(struct ip) + 2353 offsetof(struct udphdr, uh_sum); 2354 } 2355 2356 TXD->tcp_seg_setup.data = htole32(0); 2357 TXD->cmd_and_length = htole32(sc->sc_txd_cmd | E1000_TXD_CMD_DEXT); 2358 2359 return (1); 2360 } 2361 2362 /********************************************************************** 2363 * 2364 * Examine each tx_buffer in the used queue. If the hardware is done 2365 * processing the packet then free associated resources. The 2366 * tx_buffer is put back on the free queue. 2367 * 2368 **********************************************************************/ 2369 void 2370 em_txeof(struct em_softc *sc) 2371 { 2372 struct ifnet *ifp = &sc->sc_ac.ac_if; 2373 struct em_packet *pkt; 2374 struct em_tx_desc *desc; 2375 u_int head, tail; 2376 u_int free = 0; 2377 2378 head = sc->sc_tx_desc_head; 2379 tail = sc->sc_tx_desc_tail; 2380 2381 if (head == tail) 2382 return; 2383 2384 bus_dmamap_sync(sc->sc_dmat, sc->sc_tx_dma.dma_map, 2385 0, sc->sc_tx_dma.dma_map->dm_mapsize, 2386 BUS_DMASYNC_POSTREAD); 2387 2388 do { 2389 pkt = &sc->sc_tx_pkts_ring[tail]; 2390 desc = &sc->sc_tx_desc_ring[pkt->pkt_eop]; 2391 2392 if (!ISSET(desc->upper.fields.status, E1000_TXD_STAT_DD)) 2393 break; 2394 2395 bus_dmamap_sync(sc->sc_dmat, pkt->pkt_map, 2396 0, pkt->pkt_map->dm_mapsize, 2397 BUS_DMASYNC_POSTWRITE); 2398 bus_dmamap_unload(sc->sc_dmat, pkt->pkt_map); 2399 2400 KASSERT(pkt->pkt_m != NULL); 2401 2402 m_freem(pkt->pkt_m); 2403 pkt->pkt_m = NULL; 2404 2405 tail = pkt->pkt_eop; 2406 2407 if (++tail == sc->sc_tx_slots) 2408 tail = 0; 2409 2410 free++; 2411 } while (tail != head); 2412 2413 bus_dmamap_sync(sc->sc_dmat, sc->sc_tx_dma.dma_map, 2414 0, sc->sc_tx_dma.dma_map->dm_mapsize, 2415 BUS_DMASYNC_PREREAD); 2416 2417 if (free == 0) 2418 return; 2419 2420 sc->sc_tx_desc_tail = tail; 2421 2422 if (ifq_is_oactive(&ifp->if_snd)) 2423 ifq_restart(&ifp->if_snd); 2424 else if (tail == head) 2425 ifp->if_timer = 0; 2426 } 2427 2428 /********************************************************************* 2429 * 2430 * Get a buffer from system mbuf buffer pool. 2431 * 2432 **********************************************************************/ 2433 int 2434 em_get_buf(struct em_softc *sc, int i) 2435 { 2436 struct mbuf *m; 2437 struct em_packet *pkt; 2438 struct em_rx_desc *desc; 2439 int error; 2440 2441 pkt = &sc->sc_rx_pkts_ring[i]; 2442 desc = &sc->sc_rx_desc_ring[i]; 2443 2444 KASSERT(pkt->pkt_m == NULL); 2445 2446 m = MCLGETI(NULL, M_DONTWAIT, NULL, EM_MCLBYTES); 2447 if (m == NULL) { 2448 sc->mbuf_cluster_failed++; 2449 return (ENOBUFS); 2450 } 2451 m->m_len = m->m_pkthdr.len = EM_MCLBYTES; 2452 m_adj(m, ETHER_ALIGN); 2453 2454 error = bus_dmamap_load_mbuf(sc->sc_dmat, pkt->pkt_map, 2455 m, BUS_DMA_NOWAIT); 2456 if (error) { 2457 m_freem(m); 2458 return (error); 2459 } 2460 2461 bus_dmamap_sync(sc->sc_dmat, pkt->pkt_map, 2462 0, pkt->pkt_map->dm_mapsize, 2463 BUS_DMASYNC_PREREAD); 2464 pkt->pkt_m = m; 2465 2466 memset(desc, 0, sizeof(*desc)); 2467 htolem64(&desc->buffer_addr, pkt->pkt_map->dm_segs[0].ds_addr); 2468 2469 return (0); 2470 } 2471 2472 /********************************************************************* 2473 * 2474 * Allocate memory for rx_buffer structures. Since we use one 2475 * rx_buffer per received packet, the maximum number of rx_buffer's 2476 * that we'll need is equal to the number of receive descriptors 2477 * that we've allocated. 2478 * 2479 **********************************************************************/ 2480 int 2481 em_allocate_receive_structures(struct em_softc *sc) 2482 { 2483 struct em_packet *pkt; 2484 int i; 2485 int error; 2486 2487 sc->sc_rx_pkts_ring = mallocarray(sc->sc_rx_slots, 2488 sizeof(*sc->sc_rx_pkts_ring), M_DEVBUF, M_NOWAIT | M_ZERO); 2489 if (sc->sc_rx_pkts_ring == NULL) { 2490 printf("%s: Unable to allocate rx_buffer memory\n", 2491 DEVNAME(sc)); 2492 return (ENOMEM); 2493 } 2494 2495 bus_dmamap_sync(sc->sc_dmat, sc->sc_rx_dma.dma_map, 2496 0, sc->sc_rx_dma.dma_map->dm_mapsize, 2497 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2498 2499 for (i = 0; i < sc->sc_rx_slots; i++) { 2500 pkt = &sc->sc_rx_pkts_ring[i]; 2501 2502 error = bus_dmamap_create(sc->sc_dmat, EM_MCLBYTES, 1, 2503 EM_MCLBYTES, 0, BUS_DMA_NOWAIT, &pkt->pkt_map); 2504 if (error != 0) { 2505 printf("%s: em_allocate_receive_structures: " 2506 "bus_dmamap_create failed; error %u\n", 2507 DEVNAME(sc), error); 2508 goto fail; 2509 } 2510 2511 pkt->pkt_m = NULL; 2512 } 2513 2514 return (0); 2515 2516 fail: 2517 em_free_receive_structures(sc); 2518 return (error); 2519 } 2520 2521 /********************************************************************* 2522 * 2523 * Allocate and initialize receive structures. 2524 * 2525 **********************************************************************/ 2526 int 2527 em_setup_receive_structures(struct em_softc *sc) 2528 { 2529 struct ifnet *ifp = &sc->sc_ac.ac_if; 2530 u_int lwm; 2531 2532 memset(sc->sc_rx_desc_ring, 0, 2533 sc->sc_rx_slots * sizeof(*sc->sc_rx_desc_ring)); 2534 2535 if (em_allocate_receive_structures(sc)) 2536 return (ENOMEM); 2537 2538 /* Setup our descriptor pointers */ 2539 sc->sc_rx_desc_tail = 0; 2540 sc->sc_rx_desc_head = sc->sc_rx_slots - 1; 2541 2542 lwm = max(4, 2 * ((ifp->if_hardmtu / MCLBYTES) + 1)); 2543 if_rxr_init(&sc->sc_rx_ring, lwm, sc->sc_rx_slots); 2544 2545 if (em_rxfill(sc) == 0) { 2546 printf("%s: unable to fill any rx descriptors\n", 2547 DEVNAME(sc)); 2548 } 2549 2550 return (0); 2551 } 2552 2553 /********************************************************************* 2554 * 2555 * Enable receive unit. 2556 * 2557 **********************************************************************/ 2558 void 2559 em_initialize_receive_unit(struct em_softc *sc) 2560 { 2561 u_int32_t reg_rctl; 2562 u_int32_t reg_rxcsum; 2563 u_int64_t bus_addr; 2564 2565 INIT_DEBUGOUT("em_initialize_receive_unit: begin"); 2566 2567 /* Make sure receives are disabled while setting up the descriptor ring */ 2568 E1000_WRITE_REG(&sc->hw, RCTL, 0); 2569 2570 /* Set the Receive Delay Timer Register */ 2571 E1000_WRITE_REG(&sc->hw, RDTR, 2572 sc->rx_int_delay | E1000_RDT_FPDB); 2573 2574 if (sc->hw.mac_type >= em_82540) { 2575 if (sc->rx_int_delay) 2576 E1000_WRITE_REG(&sc->hw, RADV, sc->rx_abs_int_delay); 2577 2578 /* Set the interrupt throttling rate. Value is calculated 2579 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */ 2580 E1000_WRITE_REG(&sc->hw, ITR, DEFAULT_ITR); 2581 } 2582 2583 /* Setup the Base and Length of the Rx Descriptor Ring */ 2584 bus_addr = sc->sc_rx_dma.dma_map->dm_segs[0].ds_addr; 2585 E1000_WRITE_REG(&sc->hw, RDLEN, 2586 sc->sc_rx_slots * sizeof(*sc->sc_rx_desc_ring)); 2587 E1000_WRITE_REG(&sc->hw, RDBAH, (u_int32_t)(bus_addr >> 32)); 2588 E1000_WRITE_REG(&sc->hw, RDBAL, (u_int32_t)bus_addr); 2589 2590 /* Setup the Receive Control Register */ 2591 reg_rctl = E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO | 2592 E1000_RCTL_RDMTS_HALF | 2593 (sc->hw.mc_filter_type << E1000_RCTL_MO_SHIFT); 2594 2595 if (sc->hw.tbi_compatibility_on == TRUE) 2596 reg_rctl |= E1000_RCTL_SBP; 2597 2598 /* 2599 * The i350 has a bug where it always strips the CRC whether 2600 * asked to or not. So ask for stripped CRC here and 2601 * cope in rxeof 2602 */ 2603 if (sc->hw.mac_type == em_i210 || sc->hw.mac_type == em_i350) 2604 reg_rctl |= E1000_RCTL_SECRC; 2605 2606 switch (sc->sc_rx_buffer_len) { 2607 default: 2608 case EM_RXBUFFER_2048: 2609 reg_rctl |= E1000_RCTL_SZ_2048; 2610 break; 2611 case EM_RXBUFFER_4096: 2612 reg_rctl |= E1000_RCTL_SZ_4096|E1000_RCTL_BSEX|E1000_RCTL_LPE; 2613 break; 2614 case EM_RXBUFFER_8192: 2615 reg_rctl |= E1000_RCTL_SZ_8192|E1000_RCTL_BSEX|E1000_RCTL_LPE; 2616 break; 2617 case EM_RXBUFFER_16384: 2618 reg_rctl |= E1000_RCTL_SZ_16384|E1000_RCTL_BSEX|E1000_RCTL_LPE; 2619 break; 2620 } 2621 2622 if (sc->hw.max_frame_size != ETHER_MAX_LEN) 2623 reg_rctl |= E1000_RCTL_LPE; 2624 2625 /* Enable 82543 Receive Checksum Offload for TCP and UDP */ 2626 if (sc->hw.mac_type >= em_82543) { 2627 reg_rxcsum = E1000_READ_REG(&sc->hw, RXCSUM); 2628 reg_rxcsum |= (E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL); 2629 E1000_WRITE_REG(&sc->hw, RXCSUM, reg_rxcsum); 2630 } 2631 2632 /* 2633 * XXX TEMPORARY WORKAROUND: on some systems with 82573 2634 * long latencies are observed, like Lenovo X60. 2635 */ 2636 if (sc->hw.mac_type == em_82573) 2637 E1000_WRITE_REG(&sc->hw, RDTR, 0x20); 2638 2639 if (sc->hw.mac_type == em_82575 || sc->hw.mac_type == em_82580 || 2640 sc->hw.mac_type == em_i210 || sc->hw.mac_type == em_i350) { 2641 /* 82575/6 need to enable the RX queue */ 2642 uint32_t reg; 2643 reg = E1000_READ_REG(&sc->hw, RXDCTL); 2644 reg |= E1000_RXDCTL_QUEUE_ENABLE; 2645 E1000_WRITE_REG(&sc->hw, RXDCTL, reg); 2646 } 2647 2648 /* Enable Receives */ 2649 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 2650 2651 /* Setup the HW Rx Head and Tail Descriptor Pointers */ 2652 E1000_WRITE_REG(&sc->hw, RDH, 0); 2653 E1000_WRITE_REG(&sc->hw, RDT, sc->sc_rx_desc_head); 2654 } 2655 2656 /********************************************************************* 2657 * 2658 * Free receive related data structures. 2659 * 2660 **********************************************************************/ 2661 void 2662 em_free_receive_structures(struct em_softc *sc) 2663 { 2664 struct em_packet *pkt; 2665 int i; 2666 2667 INIT_DEBUGOUT("free_receive_structures: begin"); 2668 2669 if_rxr_init(&sc->sc_rx_ring, 0, 0); 2670 2671 bus_dmamap_sync(sc->sc_dmat, sc->sc_rx_dma.dma_map, 2672 0, sc->sc_rx_dma.dma_map->dm_mapsize, 2673 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2674 2675 if (sc->sc_rx_pkts_ring != NULL) { 2676 for (i = 0; i < sc->sc_rx_slots; i++) { 2677 pkt = &sc->sc_rx_pkts_ring[i]; 2678 if (pkt->pkt_m != NULL) { 2679 bus_dmamap_sync(sc->sc_dmat, pkt->pkt_map, 2680 0, pkt->pkt_map->dm_mapsize, 2681 BUS_DMASYNC_POSTREAD); 2682 bus_dmamap_unload(sc->sc_dmat, pkt->pkt_map); 2683 m_freem(pkt->pkt_m); 2684 pkt->pkt_m = NULL; 2685 } 2686 bus_dmamap_destroy(sc->sc_dmat, pkt->pkt_map); 2687 } 2688 2689 free(sc->sc_rx_pkts_ring, M_DEVBUF, 2690 sc->sc_rx_slots * sizeof(*sc->sc_rx_pkts_ring)); 2691 sc->sc_rx_pkts_ring = NULL; 2692 } 2693 2694 if (sc->fmp != NULL) { 2695 m_freem(sc->fmp); 2696 sc->fmp = NULL; 2697 sc->lmp = NULL; 2698 } 2699 } 2700 2701 int 2702 em_rxfill(struct em_softc *sc) 2703 { 2704 u_int slots; 2705 int post = 0; 2706 int i; 2707 2708 i = sc->sc_rx_desc_head; 2709 2710 bus_dmamap_sync(sc->sc_dmat, sc->sc_rx_dma.dma_map, 2711 0, sc->sc_rx_dma.dma_map->dm_mapsize, 2712 BUS_DMASYNC_POSTWRITE); 2713 2714 for (slots = if_rxr_get(&sc->sc_rx_ring, sc->sc_rx_slots); 2715 slots > 0; slots--) { 2716 if (++i == sc->sc_rx_slots) 2717 i = 0; 2718 2719 if (em_get_buf(sc, i) != 0) 2720 break; 2721 2722 sc->sc_rx_desc_head = i; 2723 post = 1; 2724 } 2725 2726 if_rxr_put(&sc->sc_rx_ring, slots); 2727 2728 bus_dmamap_sync(sc->sc_dmat, sc->sc_rx_dma.dma_map, 2729 0, sc->sc_rx_dma.dma_map->dm_mapsize, 2730 BUS_DMASYNC_PREWRITE); 2731 2732 return (post); 2733 } 2734 2735 /********************************************************************* 2736 * 2737 * This routine executes in interrupt context. It replenishes 2738 * the mbufs in the descriptor and sends data which has been 2739 * dma'ed into host memory to upper layer. 2740 * 2741 *********************************************************************/ 2742 int 2743 em_rxeof(struct em_softc *sc) 2744 { 2745 struct ifnet *ifp = &sc->sc_ac.ac_if; 2746 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 2747 struct mbuf *m; 2748 u_int8_t accept_frame = 0; 2749 u_int8_t eop = 0; 2750 u_int16_t len, desc_len, prev_len_adj; 2751 int i, rv = 0; 2752 2753 /* Pointer to the receive descriptor being examined. */ 2754 struct em_rx_desc *desc; 2755 struct em_packet *pkt; 2756 u_int8_t status; 2757 2758 if (if_rxr_inuse(&sc->sc_rx_ring) == 0) 2759 return (0); 2760 2761 i = sc->sc_rx_desc_tail; 2762 2763 bus_dmamap_sync(sc->sc_dmat, sc->sc_rx_dma.dma_map, 2764 0, sc->sc_rx_dma.dma_map->dm_mapsize, 2765 BUS_DMASYNC_POSTREAD); 2766 2767 do { 2768 m = NULL; 2769 2770 pkt = &sc->sc_rx_pkts_ring[i]; 2771 desc = &sc->sc_rx_desc_ring[i]; 2772 2773 status = desc->status; 2774 if (!ISSET(status, E1000_RXD_STAT_DD)) 2775 break; 2776 2777 /* pull the mbuf off the ring */ 2778 bus_dmamap_sync(sc->sc_dmat, pkt->pkt_map, 2779 0, pkt->pkt_map->dm_mapsize, 2780 BUS_DMASYNC_POSTREAD); 2781 bus_dmamap_unload(sc->sc_dmat, pkt->pkt_map); 2782 m = pkt->pkt_m; 2783 pkt->pkt_m = NULL; 2784 2785 KASSERT(m != NULL); 2786 2787 if_rxr_put(&sc->sc_rx_ring, 1); 2788 rv = 1; 2789 2790 accept_frame = 1; 2791 prev_len_adj = 0; 2792 desc_len = letoh16(desc->length); 2793 2794 if (status & E1000_RXD_STAT_EOP) { 2795 eop = 1; 2796 if (desc_len < ETHER_CRC_LEN) { 2797 len = 0; 2798 prev_len_adj = ETHER_CRC_LEN - desc_len; 2799 } else if (sc->hw.mac_type == em_i210 || 2800 sc->hw.mac_type == em_i350) 2801 len = desc_len; 2802 else 2803 len = desc_len - ETHER_CRC_LEN; 2804 } else { 2805 eop = 0; 2806 len = desc_len; 2807 } 2808 2809 if (desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK) { 2810 u_int8_t last_byte; 2811 u_int32_t pkt_len = desc_len; 2812 2813 if (sc->fmp != NULL) 2814 pkt_len += sc->fmp->m_pkthdr.len; 2815 2816 last_byte = *(mtod(m, caddr_t) + desc_len - 1); 2817 if (TBI_ACCEPT(&sc->hw, status, desc->errors, 2818 pkt_len, last_byte)) { 2819 #ifndef SMALL_KERNEL 2820 em_tbi_adjust_stats(&sc->hw, &sc->stats, 2821 pkt_len, sc->hw.mac_addr); 2822 #endif 2823 if (len > 0) 2824 len--; 2825 } else 2826 accept_frame = 0; 2827 } 2828 2829 if (accept_frame) { 2830 /* Assign correct length to the current fragment */ 2831 m->m_len = len; 2832 2833 if (sc->fmp == NULL) { 2834 m->m_pkthdr.len = m->m_len; 2835 sc->fmp = m; /* Store the first mbuf */ 2836 sc->lmp = m; 2837 } else { 2838 /* Chain mbuf's together */ 2839 m->m_flags &= ~M_PKTHDR; 2840 /* 2841 * Adjust length of previous mbuf in chain if 2842 * we received less than 4 bytes in the last 2843 * descriptor. 2844 */ 2845 if (prev_len_adj > 0) { 2846 sc->lmp->m_len -= prev_len_adj; 2847 sc->fmp->m_pkthdr.len -= prev_len_adj; 2848 } 2849 sc->lmp->m_next = m; 2850 sc->lmp = m; 2851 sc->fmp->m_pkthdr.len += m->m_len; 2852 } 2853 2854 if (eop) { 2855 m = sc->fmp; 2856 2857 em_receive_checksum(sc, desc, m); 2858 #if NVLAN > 0 2859 if (desc->status & E1000_RXD_STAT_VP) { 2860 m->m_pkthdr.ether_vtag = 2861 letoh16(desc->special); 2862 m->m_flags |= M_VLANTAG; 2863 } 2864 #endif 2865 ml_enqueue(&ml, m); 2866 2867 sc->fmp = NULL; 2868 sc->lmp = NULL; 2869 } 2870 } else { 2871 sc->dropped_pkts++; 2872 2873 if (sc->fmp != NULL) { 2874 m_freem(sc->fmp); 2875 sc->fmp = NULL; 2876 sc->lmp = NULL; 2877 } 2878 2879 m_freem(m); 2880 } 2881 2882 /* Advance our pointers to the next descriptor. */ 2883 if (++i == sc->sc_rx_slots) 2884 i = 0; 2885 } while (if_rxr_inuse(&sc->sc_rx_ring) > 0); 2886 2887 bus_dmamap_sync(sc->sc_dmat, sc->sc_rx_dma.dma_map, 2888 0, sc->sc_rx_dma.dma_map->dm_mapsize, 2889 BUS_DMASYNC_PREREAD); 2890 2891 sc->sc_rx_desc_tail = i; 2892 2893 if_input(ifp, &ml); 2894 2895 return (rv); 2896 } 2897 2898 /********************************************************************* 2899 * 2900 * Verify that the hardware indicated that the checksum is valid. 2901 * Inform the stack about the status of checksum so that stack 2902 * doesn't spend time verifying the checksum. 2903 * 2904 *********************************************************************/ 2905 void 2906 em_receive_checksum(struct em_softc *sc, struct em_rx_desc *rx_desc, 2907 struct mbuf *mp) 2908 { 2909 /* 82543 or newer only */ 2910 if ((sc->hw.mac_type < em_82543) || 2911 /* Ignore Checksum bit is set */ 2912 (rx_desc->status & E1000_RXD_STAT_IXSM)) { 2913 mp->m_pkthdr.csum_flags = 0; 2914 return; 2915 } 2916 2917 if (rx_desc->status & E1000_RXD_STAT_IPCS) { 2918 /* Did it pass? */ 2919 if (!(rx_desc->errors & E1000_RXD_ERR_IPE)) { 2920 /* IP Checksum Good */ 2921 mp->m_pkthdr.csum_flags = M_IPV4_CSUM_IN_OK; 2922 2923 } else 2924 mp->m_pkthdr.csum_flags = 0; 2925 } 2926 2927 if (rx_desc->status & E1000_RXD_STAT_TCPCS) { 2928 /* Did it pass? */ 2929 if (!(rx_desc->errors & E1000_RXD_ERR_TCPE)) 2930 mp->m_pkthdr.csum_flags |= 2931 M_TCP_CSUM_IN_OK | M_UDP_CSUM_IN_OK; 2932 } 2933 } 2934 2935 /* 2936 * This turns on the hardware offload of the VLAN 2937 * tag insertion and strip 2938 */ 2939 void 2940 em_enable_hw_vlans(struct em_softc *sc) 2941 { 2942 uint32_t ctrl; 2943 2944 ctrl = E1000_READ_REG(&sc->hw, CTRL); 2945 ctrl |= E1000_CTRL_VME; 2946 E1000_WRITE_REG(&sc->hw, CTRL, ctrl); 2947 } 2948 2949 void 2950 em_enable_intr(struct em_softc *sc) 2951 { 2952 E1000_WRITE_REG(&sc->hw, IMS, (IMS_ENABLE_MASK)); 2953 } 2954 2955 void 2956 em_disable_intr(struct em_softc *sc) 2957 { 2958 /* 2959 * The first version of 82542 had an errata where when link 2960 * was forced it would stay up even if the cable was disconnected 2961 * Sequence errors were used to detect the disconnect and then 2962 * the driver would unforce the link. This code is in the ISR. 2963 * For this to work correctly the Sequence error interrupt had 2964 * to be enabled all the time. 2965 */ 2966 2967 if (sc->hw.mac_type == em_82542_rev2_0) 2968 E1000_WRITE_REG(&sc->hw, IMC, (0xffffffff & ~E1000_IMC_RXSEQ)); 2969 else 2970 E1000_WRITE_REG(&sc->hw, IMC, 0xffffffff); 2971 } 2972 2973 void 2974 em_write_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t *value) 2975 { 2976 struct pci_attach_args *pa = &((struct em_osdep *)hw->back)->em_pa; 2977 pcireg_t val; 2978 2979 val = pci_conf_read(pa->pa_pc, pa->pa_tag, reg & ~0x3); 2980 if (reg & 0x2) { 2981 val &= 0x0000ffff; 2982 val |= (*value << 16); 2983 } else { 2984 val &= 0xffff0000; 2985 val |= *value; 2986 } 2987 pci_conf_write(pa->pa_pc, pa->pa_tag, reg & ~0x3, val); 2988 } 2989 2990 void 2991 em_read_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t *value) 2992 { 2993 struct pci_attach_args *pa = &((struct em_osdep *)hw->back)->em_pa; 2994 pcireg_t val; 2995 2996 val = pci_conf_read(pa->pa_pc, pa->pa_tag, reg & ~0x3); 2997 if (reg & 0x2) 2998 *value = (val >> 16) & 0xffff; 2999 else 3000 *value = val & 0xffff; 3001 } 3002 3003 void 3004 em_pci_set_mwi(struct em_hw *hw) 3005 { 3006 struct pci_attach_args *pa = &((struct em_osdep *)hw->back)->em_pa; 3007 3008 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 3009 (hw->pci_cmd_word | CMD_MEM_WRT_INVALIDATE)); 3010 } 3011 3012 void 3013 em_pci_clear_mwi(struct em_hw *hw) 3014 { 3015 struct pci_attach_args *pa = &((struct em_osdep *)hw->back)->em_pa; 3016 3017 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 3018 (hw->pci_cmd_word & ~CMD_MEM_WRT_INVALIDATE)); 3019 } 3020 3021 /* 3022 * We may eventually really do this, but its unnecessary 3023 * for now so we just return unsupported. 3024 */ 3025 int32_t 3026 em_read_pcie_cap_reg(struct em_hw *hw, uint32_t reg, uint16_t *value) 3027 { 3028 return -E1000_NOT_IMPLEMENTED; 3029 } 3030 3031 /********************************************************************* 3032 * 82544 Coexistence issue workaround. 3033 * There are 2 issues. 3034 * 1. Transmit Hang issue. 3035 * To detect this issue, following equation can be used... 3036 * SIZE[3:0] + ADDR[2:0] = SUM[3:0]. 3037 * If SUM[3:0] is in between 1 to 4, we will have this issue. 3038 * 3039 * 2. DAC issue. 3040 * To detect this issue, following equation can be used... 3041 * SIZE[3:0] + ADDR[2:0] = SUM[3:0]. 3042 * If SUM[3:0] is in between 9 to c, we will have this issue. 3043 * 3044 * 3045 * WORKAROUND: 3046 * Make sure we do not have ending address as 1,2,3,4(Hang) or 9,a,b,c (DAC) 3047 * 3048 *** *********************************************************************/ 3049 u_int32_t 3050 em_fill_descriptors(u_int64_t address, u_int32_t length, 3051 PDESC_ARRAY desc_array) 3052 { 3053 /* Since issue is sensitive to length and address.*/ 3054 /* Let us first check the address...*/ 3055 u_int32_t safe_terminator; 3056 if (length <= 4) { 3057 desc_array->descriptor[0].address = address; 3058 desc_array->descriptor[0].length = length; 3059 desc_array->elements = 1; 3060 return desc_array->elements; 3061 } 3062 safe_terminator = (u_int32_t)((((u_int32_t)address & 0x7) + (length & 0xF)) & 0xF); 3063 /* if it does not fall between 0x1 to 0x4 and 0x9 to 0xC then return */ 3064 if (safe_terminator == 0 || 3065 (safe_terminator > 4 && 3066 safe_terminator < 9) || 3067 (safe_terminator > 0xC && 3068 safe_terminator <= 0xF)) { 3069 desc_array->descriptor[0].address = address; 3070 desc_array->descriptor[0].length = length; 3071 desc_array->elements = 1; 3072 return desc_array->elements; 3073 } 3074 3075 desc_array->descriptor[0].address = address; 3076 desc_array->descriptor[0].length = length - 4; 3077 desc_array->descriptor[1].address = address + (length - 4); 3078 desc_array->descriptor[1].length = 4; 3079 desc_array->elements = 2; 3080 return desc_array->elements; 3081 } 3082 3083 /* 3084 * Disable the L0S and L1 LINK states. 3085 */ 3086 void 3087 em_disable_aspm(struct em_softc *sc) 3088 { 3089 int offset; 3090 pcireg_t val; 3091 3092 switch (sc->hw.mac_type) { 3093 case em_82571: 3094 case em_82572: 3095 case em_82573: 3096 case em_82574: 3097 break; 3098 default: 3099 return; 3100 } 3101 3102 if (!pci_get_capability(sc->osdep.em_pa.pa_pc, sc->osdep.em_pa.pa_tag, 3103 PCI_CAP_PCIEXPRESS, &offset, NULL)) 3104 return; 3105 3106 /* Disable PCIe Active State Power Management (ASPM). */ 3107 val = pci_conf_read(sc->osdep.em_pa.pa_pc, sc->osdep.em_pa.pa_tag, 3108 offset + PCI_PCIE_LCSR); 3109 3110 switch (sc->hw.mac_type) { 3111 case em_82571: 3112 case em_82572: 3113 val &= ~PCI_PCIE_LCSR_ASPM_L1; 3114 break; 3115 case em_82573: 3116 case em_82574: 3117 val &= ~(PCI_PCIE_LCSR_ASPM_L0S | 3118 PCI_PCIE_LCSR_ASPM_L1); 3119 break; 3120 default: 3121 break; 3122 } 3123 3124 pci_conf_write(sc->osdep.em_pa.pa_pc, sc->osdep.em_pa.pa_tag, 3125 offset + PCI_PCIE_LCSR, val); 3126 } 3127 3128 /* 3129 * em_flush_tx_ring - remove all descriptors from the tx_ring 3130 * 3131 * We want to clear all pending descriptors from the TX ring. 3132 * zeroing happens when the HW reads the regs. We assign the ring itself as 3133 * the data of the next descriptor. We don't care about the data we are about 3134 * to reset the HW. 3135 */ 3136 void 3137 em_flush_tx_ring(struct em_softc *sc) 3138 { 3139 uint32_t tctl, txd_lower = E1000_TXD_CMD_IFCS; 3140 uint16_t size = 512; 3141 struct em_tx_desc *txd; 3142 3143 KASSERT(sc->sc_tx_desc_ring != NULL); 3144 3145 tctl = EM_READ_REG(&sc->hw, E1000_TCTL); 3146 EM_WRITE_REG(&sc->hw, E1000_TCTL, tctl | E1000_TCTL_EN); 3147 3148 KASSERT(EM_READ_REG(&sc->hw, E1000_TDT) == sc->sc_tx_desc_head); 3149 3150 txd = &sc->sc_tx_desc_ring[sc->sc_tx_desc_head]; 3151 txd->buffer_addr = sc->sc_tx_dma.dma_map->dm_segs[0].ds_addr; 3152 txd->lower.data = htole32(txd_lower | size); 3153 txd->upper.data = 0; 3154 3155 /* flush descriptors to memory before notifying the HW */ 3156 bus_space_barrier(sc->osdep.mem_bus_space_tag, 3157 sc->osdep.mem_bus_space_handle, 0, 0, BUS_SPACE_BARRIER_WRITE); 3158 3159 if (++sc->sc_tx_desc_head == sc->sc_tx_slots) 3160 sc->sc_tx_desc_head = 0; 3161 3162 EM_WRITE_REG(&sc->hw, E1000_TDT, sc->sc_tx_desc_head); 3163 bus_space_barrier(sc->osdep.mem_bus_space_tag, sc->osdep.mem_bus_space_handle, 3164 0, 0, BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE); 3165 usec_delay(250); 3166 } 3167 3168 /* 3169 * em_flush_rx_ring - remove all descriptors from the rx_ring 3170 * 3171 * Mark all descriptors in the RX ring as consumed and disable the rx ring 3172 */ 3173 void 3174 em_flush_rx_ring(struct em_softc *sc) 3175 { 3176 uint32_t rctl, rxdctl; 3177 3178 rctl = EM_READ_REG(&sc->hw, E1000_RCTL); 3179 EM_WRITE_REG(&sc->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 3180 E1000_WRITE_FLUSH(&sc->hw); 3181 usec_delay(150); 3182 3183 rxdctl = EM_READ_REG(&sc->hw, E1000_RXDCTL); 3184 /* zero the lower 14 bits (prefetch and host thresholds) */ 3185 rxdctl &= 0xffffc000; 3186 /* 3187 * update thresholds: prefetch threshold to 31, host threshold to 1 3188 * and make sure the granularity is "descriptors" and not "cache lines" 3189 */ 3190 rxdctl |= (0x1F | (1 << 8) | E1000_RXDCTL_THRESH_UNIT_DESC); 3191 EM_WRITE_REG(&sc->hw, E1000_RXDCTL, rxdctl); 3192 3193 /* momentarily enable the RX ring for the changes to take effect */ 3194 EM_WRITE_REG(&sc->hw, E1000_RCTL, rctl | E1000_RCTL_EN); 3195 E1000_WRITE_FLUSH(&sc->hw); 3196 usec_delay(150); 3197 EM_WRITE_REG(&sc->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 3198 } 3199 3200 /* 3201 * em_flush_desc_rings - remove all descriptors from the descriptor rings 3202 * 3203 * In i219, the descriptor rings must be emptied before resetting the HW 3204 * or before changing the device state to D3 during runtime (runtime PM). 3205 * 3206 * Failure to do this will cause the HW to enter a unit hang state which can 3207 * only be released by PCI reset on the device 3208 * 3209 */ 3210 void 3211 em_flush_desc_rings(struct em_softc *sc) 3212 { 3213 struct pci_attach_args *pa = &sc->osdep.em_pa; 3214 uint32_t fextnvm11, tdlen; 3215 uint16_t hang_state; 3216 3217 /* First, disable MULR fix in FEXTNVM11 */ 3218 fextnvm11 = EM_READ_REG(&sc->hw, E1000_FEXTNVM11); 3219 fextnvm11 |= E1000_FEXTNVM11_DISABLE_MULR_FIX; 3220 EM_WRITE_REG(&sc->hw, E1000_FEXTNVM11, fextnvm11); 3221 3222 /* do nothing if we're not in faulty state, or if the queue is empty */ 3223 tdlen = EM_READ_REG(&sc->hw, E1000_TDLEN); 3224 hang_state = pci_conf_read(pa->pa_pc, pa->pa_tag, PCICFG_DESC_RING_STATUS); 3225 if (!(hang_state & FLUSH_DESC_REQUIRED) || !tdlen) 3226 return; 3227 em_flush_tx_ring(sc); 3228 3229 /* recheck, maybe the fault is caused by the rx ring */ 3230 hang_state = pci_conf_read(pa->pa_pc, pa->pa_tag, PCICFG_DESC_RING_STATUS); 3231 if (hang_state & FLUSH_DESC_REQUIRED) 3232 em_flush_rx_ring(sc); 3233 } 3234 3235 #ifndef SMALL_KERNEL 3236 /********************************************************************** 3237 * 3238 * Update the board statistics counters. 3239 * 3240 **********************************************************************/ 3241 void 3242 em_update_stats_counters(struct em_softc *sc) 3243 { 3244 struct ifnet *ifp = &sc->sc_ac.ac_if; 3245 3246 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, CRCERRS); 3247 sc->stats.mpc += E1000_READ_REG(&sc->hw, MPC); 3248 sc->stats.ecol += E1000_READ_REG(&sc->hw, ECOL); 3249 3250 sc->stats.latecol += E1000_READ_REG(&sc->hw, LATECOL); 3251 sc->stats.colc += E1000_READ_REG(&sc->hw, COLC); 3252 3253 sc->stats.ruc += E1000_READ_REG(&sc->hw, RUC); 3254 sc->stats.roc += E1000_READ_REG(&sc->hw, ROC); 3255 3256 if (sc->hw.mac_type >= em_82543) { 3257 sc->stats.algnerrc += 3258 E1000_READ_REG(&sc->hw, ALGNERRC); 3259 sc->stats.rxerrc += 3260 E1000_READ_REG(&sc->hw, RXERRC); 3261 sc->stats.cexterr += 3262 E1000_READ_REG(&sc->hw, CEXTERR); 3263 } 3264 3265 #ifdef EM_DEBUG 3266 if (sc->hw.media_type == em_media_type_copper || 3267 (E1000_READ_REG(&sc->hw, STATUS) & E1000_STATUS_LU)) { 3268 sc->stats.symerrs += E1000_READ_REG(&sc->hw, SYMERRS); 3269 sc->stats.sec += E1000_READ_REG(&sc->hw, SEC); 3270 } 3271 sc->stats.scc += E1000_READ_REG(&sc->hw, SCC); 3272 3273 sc->stats.mcc += E1000_READ_REG(&sc->hw, MCC); 3274 sc->stats.dc += E1000_READ_REG(&sc->hw, DC); 3275 sc->stats.rlec += E1000_READ_REG(&sc->hw, RLEC); 3276 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, XONRXC); 3277 sc->stats.xontxc += E1000_READ_REG(&sc->hw, XONTXC); 3278 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, XOFFRXC); 3279 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, XOFFTXC); 3280 sc->stats.fcruc += E1000_READ_REG(&sc->hw, FCRUC); 3281 sc->stats.prc64 += E1000_READ_REG(&sc->hw, PRC64); 3282 sc->stats.prc127 += E1000_READ_REG(&sc->hw, PRC127); 3283 sc->stats.prc255 += E1000_READ_REG(&sc->hw, PRC255); 3284 sc->stats.prc511 += E1000_READ_REG(&sc->hw, PRC511); 3285 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, PRC1023); 3286 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, PRC1522); 3287 sc->stats.gprc += E1000_READ_REG(&sc->hw, GPRC); 3288 sc->stats.bprc += E1000_READ_REG(&sc->hw, BPRC); 3289 sc->stats.mprc += E1000_READ_REG(&sc->hw, MPRC); 3290 sc->stats.gptc += E1000_READ_REG(&sc->hw, GPTC); 3291 3292 /* For the 64-bit byte counters the low dword must be read first. */ 3293 /* Both registers clear on the read of the high dword */ 3294 3295 sc->stats.gorcl += E1000_READ_REG(&sc->hw, GORCL); 3296 sc->stats.gorch += E1000_READ_REG(&sc->hw, GORCH); 3297 sc->stats.gotcl += E1000_READ_REG(&sc->hw, GOTCL); 3298 sc->stats.gotch += E1000_READ_REG(&sc->hw, GOTCH); 3299 3300 sc->stats.rnbc += E1000_READ_REG(&sc->hw, RNBC); 3301 sc->stats.rfc += E1000_READ_REG(&sc->hw, RFC); 3302 sc->stats.rjc += E1000_READ_REG(&sc->hw, RJC); 3303 3304 sc->stats.torl += E1000_READ_REG(&sc->hw, TORL); 3305 sc->stats.torh += E1000_READ_REG(&sc->hw, TORH); 3306 sc->stats.totl += E1000_READ_REG(&sc->hw, TOTL); 3307 sc->stats.toth += E1000_READ_REG(&sc->hw, TOTH); 3308 3309 sc->stats.tpr += E1000_READ_REG(&sc->hw, TPR); 3310 sc->stats.tpt += E1000_READ_REG(&sc->hw, TPT); 3311 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, PTC64); 3312 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, PTC127); 3313 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, PTC255); 3314 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, PTC511); 3315 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, PTC1023); 3316 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, PTC1522); 3317 sc->stats.mptc += E1000_READ_REG(&sc->hw, MPTC); 3318 sc->stats.bptc += E1000_READ_REG(&sc->hw, BPTC); 3319 3320 if (sc->hw.mac_type >= em_82543) { 3321 sc->stats.tncrs += 3322 E1000_READ_REG(&sc->hw, TNCRS); 3323 sc->stats.tsctc += 3324 E1000_READ_REG(&sc->hw, TSCTC); 3325 sc->stats.tsctfc += 3326 E1000_READ_REG(&sc->hw, TSCTFC); 3327 } 3328 #endif 3329 3330 /* Fill out the OS statistics structure */ 3331 ifp->if_collisions = sc->stats.colc; 3332 3333 /* Rx Errors */ 3334 ifp->if_ierrors = 3335 sc->dropped_pkts + 3336 sc->stats.rxerrc + 3337 sc->stats.crcerrs + 3338 sc->stats.algnerrc + 3339 sc->stats.ruc + sc->stats.roc + 3340 sc->stats.mpc + sc->stats.cexterr + 3341 sc->rx_overruns; 3342 3343 /* Tx Errors */ 3344 ifp->if_oerrors = sc->stats.ecol + sc->stats.latecol + 3345 sc->watchdog_events; 3346 } 3347 3348 #ifdef EM_DEBUG 3349 /********************************************************************** 3350 * 3351 * This routine is called only when IFF_DEBUG is enabled. 3352 * This routine provides a way to take a look at important statistics 3353 * maintained by the driver and hardware. 3354 * 3355 **********************************************************************/ 3356 void 3357 em_print_hw_stats(struct em_softc *sc) 3358 { 3359 const char * const unit = DEVNAME(sc); 3360 3361 printf("%s: Excessive collisions = %lld\n", unit, 3362 (long long)sc->stats.ecol); 3363 printf("%s: Symbol errors = %lld\n", unit, 3364 (long long)sc->stats.symerrs); 3365 printf("%s: Sequence errors = %lld\n", unit, 3366 (long long)sc->stats.sec); 3367 printf("%s: Defer count = %lld\n", unit, 3368 (long long)sc->stats.dc); 3369 3370 printf("%s: Missed Packets = %lld\n", unit, 3371 (long long)sc->stats.mpc); 3372 printf("%s: Receive No Buffers = %lld\n", unit, 3373 (long long)sc->stats.rnbc); 3374 /* RLEC is inaccurate on some hardware, calculate our own */ 3375 printf("%s: Receive Length Errors = %lld\n", unit, 3376 ((long long)sc->stats.roc + 3377 (long long)sc->stats.ruc)); 3378 printf("%s: Receive errors = %lld\n", unit, 3379 (long long)sc->stats.rxerrc); 3380 printf("%s: Crc errors = %lld\n", unit, 3381 (long long)sc->stats.crcerrs); 3382 printf("%s: Alignment errors = %lld\n", unit, 3383 (long long)sc->stats.algnerrc); 3384 printf("%s: Carrier extension errors = %lld\n", unit, 3385 (long long)sc->stats.cexterr); 3386 3387 printf("%s: RX overruns = %ld\n", unit, 3388 sc->rx_overruns); 3389 printf("%s: watchdog timeouts = %ld\n", unit, 3390 sc->watchdog_events); 3391 3392 printf("%s: XON Rcvd = %lld\n", unit, 3393 (long long)sc->stats.xonrxc); 3394 printf("%s: XON Xmtd = %lld\n", unit, 3395 (long long)sc->stats.xontxc); 3396 printf("%s: XOFF Rcvd = %lld\n", unit, 3397 (long long)sc->stats.xoffrxc); 3398 printf("%s: XOFF Xmtd = %lld\n", unit, 3399 (long long)sc->stats.xofftxc); 3400 3401 printf("%s: Good Packets Rcvd = %lld\n", unit, 3402 (long long)sc->stats.gprc); 3403 printf("%s: Good Packets Xmtd = %lld\n", unit, 3404 (long long)sc->stats.gptc); 3405 } 3406 #endif 3407 #endif /* !SMALL_KERNEL */ 3408