1 /************************************************************************** 2 3 Copyright (c) 2001-2003, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ***************************************************************************/ 33 34 /* $OpenBSD: if_em.c,v 1.336 2017/07/25 20:45:18 bluhm Exp $ */ 35 /* $FreeBSD: if_em.c,v 1.46 2004/09/29 18:28:28 mlaier Exp $ */ 36 37 #include <dev/pci/if_em.h> 38 #include <dev/pci/if_em_soc.h> 39 40 /********************************************************************* 41 * Driver version 42 *********************************************************************/ 43 44 #define EM_DRIVER_VERSION "6.2.9" 45 46 /********************************************************************* 47 * PCI Device ID Table 48 *********************************************************************/ 49 const struct pci_matchid em_devices[] = { 50 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80003ES2LAN_CPR_DPT }, 51 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80003ES2LAN_SDS_DPT }, 52 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80003ES2LAN_CPR_SPT }, 53 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80003ES2LAN_SDS_SPT }, 54 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM }, 55 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM_LOM }, 56 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP }, 57 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LOM }, 58 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LP }, 59 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI }, 60 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI_MOBILE }, 61 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541ER }, 62 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541ER_LOM }, 63 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI }, 64 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI_LF }, 65 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI_MOBILE }, 66 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82542 }, 67 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_COPPER }, 68 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_FIBER }, 69 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_COPPER }, 70 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_FIBER }, 71 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_COPPER }, 72 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_LOM }, 73 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_COPPER }, 74 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_FIBER }, 75 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_COPPER }, 76 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_FIBER }, 77 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_SERDES }, 78 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_COPPER }, 79 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_FIBER }, 80 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_QUAD_CPR }, 81 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_COPPER }, 82 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_FIBER }, 83 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_PCIE }, 84 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_QUAD_CPR }, 85 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_QUAD_CPR_K }, 86 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_SERDES }, 87 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_2 }, 88 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547EI }, 89 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547EI_MOBILE }, 90 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547GI }, 91 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_AF }, 92 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_AT }, 93 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_COPPER }, 94 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_FIBER }, 95 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_QUAD_CPR }, 96 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_QUAD_CPR_LP }, 97 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_QUAD_FBR }, 98 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_SERDES }, 99 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_SDS_DUAL }, 100 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_SDS_QUAD }, 101 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571PT_QUAD_CPR }, 102 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI_COPPER }, 103 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI_FIBER }, 104 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI_SERDES }, 105 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI }, 106 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573E }, 107 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573E_IAMT }, 108 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573E_PM }, 109 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573L }, 110 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573L_PL_1 }, 111 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573L_PL_2 }, 112 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573V_PM }, 113 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82574L }, 114 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82574LA }, 115 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82575EB_COPPER }, 116 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82575EB_SERDES }, 117 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82575GB_QUAD_CPR }, 118 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82575GB_QP_PM }, 119 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576 }, 120 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_FIBER }, 121 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_SERDES }, 122 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_QUAD_COPPER }, 123 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_QUAD_CU_ET2 }, 124 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_NS }, 125 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_NS_SERDES }, 126 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_SERDES_QUAD }, 127 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82577LC }, 128 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82577LM }, 129 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82578DC }, 130 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82578DM }, 131 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82579LM }, 132 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82579V }, 133 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_COPPER }, 134 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_FIBER }, 135 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_SERDES }, 136 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_SGMII }, 137 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_COPPER_NF }, 138 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_SERDES_NF }, 139 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I211_COPPER }, 140 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I217_LM }, 141 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I217_V }, 142 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_LM }, 143 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_LM_2 }, 144 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_LM_3 }, 145 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_V }, 146 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_V_2 }, 147 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_V_3 }, 148 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_LM }, 149 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_LM2 }, 150 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_LM3 }, 151 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_LM4 }, 152 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_LM5 }, 153 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_V }, 154 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_V2 }, 155 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_V4 }, 156 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_V5 }, 157 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_COPPER }, 158 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_FIBER }, 159 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_SERDES }, 160 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_SGMII }, 161 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_COPPER_DUAL }, 162 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_QUAD_FIBER }, 163 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCC_SGMII }, 164 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCC_SERDES }, 165 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCC_BPLANE }, 166 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCC_SFP }, 167 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82583V }, 168 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I350_COPPER }, 169 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I350_FIBER }, 170 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I350_SERDES }, 171 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I350_SGMII }, 172 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I354_BP_1GBPS }, 173 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I354_BP_2_5GBPS }, 174 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I354_SGMII }, 175 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_82567V_3 }, 176 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_IFE }, 177 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_IFE_G }, 178 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_IFE_GT }, 179 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_IGP_AMT }, 180 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_IGP_C }, 181 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_IGP_M }, 182 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_IGP_M_AMT }, 183 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_BM }, 184 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IFE }, 185 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IFE_G }, 186 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IFE_GT }, 187 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IGP_AMT }, 188 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IGP_C }, 189 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IGP_M }, 190 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IGP_M_AMT }, 191 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IGP_M_V }, 192 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH10_D_BM_LF }, 193 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH10_D_BM_LM }, 194 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH10_R_BM_LF }, 195 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH10_R_BM_LM }, 196 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH10_R_BM_V }, 197 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EP80579_LAN_1 }, 198 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EP80579_LAN_2 }, 199 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EP80579_LAN_3 }, 200 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EP80579_LAN_4 }, 201 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EP80579_LAN_5 }, 202 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EP80579_LAN_6 } 203 }; 204 205 /********************************************************************* 206 * Function prototypes 207 *********************************************************************/ 208 int em_probe(struct device *, void *, void *); 209 void em_attach(struct device *, struct device *, void *); 210 void em_defer_attach(struct device*); 211 int em_detach(struct device *, int); 212 int em_activate(struct device *, int); 213 int em_intr(void *); 214 void em_start(struct ifqueue *); 215 int em_ioctl(struct ifnet *, u_long, caddr_t); 216 void em_watchdog(struct ifnet *); 217 void em_init(void *); 218 void em_stop(void *, int); 219 void em_media_status(struct ifnet *, struct ifmediareq *); 220 int em_media_change(struct ifnet *); 221 uint64_t em_flowstatus(struct em_softc *); 222 void em_identify_hardware(struct em_softc *); 223 int em_allocate_pci_resources(struct em_softc *); 224 void em_free_pci_resources(struct em_softc *); 225 void em_local_timer(void *); 226 int em_hardware_init(struct em_softc *); 227 void em_setup_interface(struct em_softc *); 228 int em_setup_transmit_structures(struct em_softc *); 229 void em_initialize_transmit_unit(struct em_softc *); 230 int em_setup_receive_structures(struct em_softc *); 231 void em_initialize_receive_unit(struct em_softc *); 232 void em_enable_intr(struct em_softc *); 233 void em_disable_intr(struct em_softc *); 234 void em_free_transmit_structures(struct em_softc *); 235 void em_free_receive_structures(struct em_softc *); 236 void em_update_stats_counters(struct em_softc *); 237 void em_disable_aspm(struct em_softc *); 238 void em_txeof(struct em_softc *); 239 int em_allocate_receive_structures(struct em_softc *); 240 int em_allocate_transmit_structures(struct em_softc *); 241 int em_rxfill(struct em_softc *); 242 int em_rxeof(struct em_softc *); 243 void em_receive_checksum(struct em_softc *, struct em_rx_desc *, 244 struct mbuf *); 245 u_int em_transmit_checksum_setup(struct em_softc *, struct mbuf *, u_int, 246 u_int32_t *, u_int32_t *); 247 void em_iff(struct em_softc *); 248 #ifdef EM_DEBUG 249 void em_print_hw_stats(struct em_softc *); 250 #endif 251 void em_update_link_status(struct em_softc *); 252 int em_get_buf(struct em_softc *, int); 253 void em_enable_hw_vlans(struct em_softc *); 254 u_int em_encap(struct em_softc *, struct mbuf *); 255 void em_smartspeed(struct em_softc *); 256 int em_82547_fifo_workaround(struct em_softc *, int); 257 void em_82547_update_fifo_head(struct em_softc *, int); 258 int em_82547_tx_fifo_reset(struct em_softc *); 259 void em_82547_move_tail(void *arg); 260 void em_82547_move_tail_locked(struct em_softc *); 261 int em_dma_malloc(struct em_softc *, bus_size_t, struct em_dma_alloc *); 262 void em_dma_free(struct em_softc *, struct em_dma_alloc *); 263 u_int32_t em_fill_descriptors(u_int64_t address, u_int32_t length, 264 PDESC_ARRAY desc_array); 265 void em_flush_tx_ring(struct em_softc *); 266 void em_flush_rx_ring(struct em_softc *); 267 void em_flush_desc_rings(struct em_softc *); 268 269 /********************************************************************* 270 * OpenBSD Device Interface Entry Points 271 *********************************************************************/ 272 273 struct cfattach em_ca = { 274 sizeof(struct em_softc), em_probe, em_attach, em_detach, 275 em_activate 276 }; 277 278 struct cfdriver em_cd = { 279 NULL, "em", DV_IFNET 280 }; 281 282 static int em_smart_pwr_down = FALSE; 283 284 /********************************************************************* 285 * Device identification routine 286 * 287 * em_probe determines if the driver should be loaded on 288 * adapter based on PCI vendor/device id of the adapter. 289 * 290 * return 0 on no match, positive on match 291 *********************************************************************/ 292 293 int 294 em_probe(struct device *parent, void *match, void *aux) 295 { 296 INIT_DEBUGOUT("em_probe: begin"); 297 298 return (pci_matchbyid((struct pci_attach_args *)aux, em_devices, 299 nitems(em_devices))); 300 } 301 302 void 303 em_defer_attach(struct device *self) 304 { 305 struct em_softc *sc = (struct em_softc *)self; 306 struct pci_attach_args *pa = &sc->osdep.em_pa; 307 pci_chipset_tag_t pc = pa->pa_pc; 308 void *gcu; 309 310 INIT_DEBUGOUT("em_defer_attach: begin"); 311 312 if ((gcu = em_lookup_gcu(self)) == 0) { 313 printf("%s: No GCU found, defered attachment failed\n", 314 DEVNAME(sc)); 315 316 if (sc->sc_intrhand) 317 pci_intr_disestablish(pc, sc->sc_intrhand); 318 sc->sc_intrhand = 0; 319 320 em_stop(sc, 1); 321 322 em_free_pci_resources(sc); 323 324 sc->sc_rx_desc_ring = NULL; 325 em_dma_free(sc, &sc->sc_rx_dma); 326 sc->sc_tx_desc_ring = NULL; 327 em_dma_free(sc, &sc->sc_tx_dma); 328 329 return; 330 } 331 332 sc->hw.gcu = gcu; 333 334 em_attach_miibus(self); 335 336 em_setup_interface(sc); 337 338 em_setup_link(&sc->hw); 339 340 em_update_link_status(sc); 341 } 342 343 /********************************************************************* 344 * Device initialization routine 345 * 346 * The attach entry point is called when the driver is being loaded. 347 * This routine identifies the type of hardware, allocates all resources 348 * and initializes the hardware. 349 * 350 *********************************************************************/ 351 352 void 353 em_attach(struct device *parent, struct device *self, void *aux) 354 { 355 struct pci_attach_args *pa = aux; 356 struct em_softc *sc; 357 int defer = 0; 358 359 INIT_DEBUGOUT("em_attach: begin"); 360 361 sc = (struct em_softc *)self; 362 sc->sc_dmat = pa->pa_dmat; 363 sc->osdep.em_pa = *pa; 364 365 timeout_set(&sc->timer_handle, em_local_timer, sc); 366 timeout_set(&sc->tx_fifo_timer_handle, em_82547_move_tail, sc); 367 368 /* Determine hardware revision */ 369 em_identify_hardware(sc); 370 371 /* 372 * Only use MSI on the newer PCIe parts, with the exception 373 * of 82571/82572 due to "Byte Enables 2 and 3 Are Not Set" errata 374 */ 375 if (sc->hw.mac_type <= em_82572) 376 sc->osdep.em_pa.pa_flags &= ~PCI_FLAGS_MSI_ENABLED; 377 378 /* Parameters (to be read from user) */ 379 if (sc->hw.mac_type >= em_82544) { 380 sc->sc_tx_slots = EM_MAX_TXD; 381 sc->sc_rx_slots = EM_MAX_RXD; 382 } else { 383 sc->sc_tx_slots = EM_MAX_TXD_82543; 384 sc->sc_rx_slots = EM_MAX_RXD_82543; 385 } 386 sc->tx_int_delay = EM_TIDV; 387 sc->tx_abs_int_delay = EM_TADV; 388 sc->rx_int_delay = EM_RDTR; 389 sc->rx_abs_int_delay = EM_RADV; 390 sc->hw.autoneg = DO_AUTO_NEG; 391 sc->hw.wait_autoneg_complete = WAIT_FOR_AUTO_NEG_DEFAULT; 392 sc->hw.autoneg_advertised = AUTONEG_ADV_DEFAULT; 393 sc->hw.tbi_compatibility_en = TRUE; 394 sc->sc_rx_buffer_len = EM_RXBUFFER_2048; 395 396 sc->hw.phy_init_script = 1; 397 sc->hw.phy_reset_disable = FALSE; 398 399 #ifndef EM_MASTER_SLAVE 400 sc->hw.master_slave = em_ms_hw_default; 401 #else 402 sc->hw.master_slave = EM_MASTER_SLAVE; 403 #endif 404 405 /* 406 * This controls when hardware reports transmit completion 407 * status. 408 */ 409 sc->hw.report_tx_early = 1; 410 411 if (em_allocate_pci_resources(sc)) 412 goto err_pci; 413 414 /* Initialize eeprom parameters */ 415 em_init_eeprom_params(&sc->hw); 416 417 /* 418 * Set the max frame size assuming standard Ethernet 419 * sized frames. 420 */ 421 switch (sc->hw.mac_type) { 422 case em_82573: 423 { 424 uint16_t eeprom_data = 0; 425 426 /* 427 * 82573 only supports Jumbo frames 428 * if ASPM is disabled. 429 */ 430 em_read_eeprom(&sc->hw, EEPROM_INIT_3GIO_3, 431 1, &eeprom_data); 432 if (eeprom_data & EEPROM_WORD1A_ASPM_MASK) { 433 sc->hw.max_frame_size = ETHER_MAX_LEN; 434 break; 435 } 436 /* Allow Jumbo frames */ 437 /* FALLTHROUGH */ 438 } 439 case em_82571: 440 case em_82572: 441 case em_82574: 442 case em_82575: 443 case em_82580: 444 case em_i210: 445 case em_i350: 446 case em_ich9lan: 447 case em_ich10lan: 448 case em_pch2lan: 449 case em_pch_lpt: 450 case em_pch_spt: 451 case em_80003es2lan: 452 /* 9K Jumbo Frame size */ 453 sc->hw.max_frame_size = 9234; 454 break; 455 case em_pchlan: 456 sc->hw.max_frame_size = 4096; 457 break; 458 case em_82542_rev2_0: 459 case em_82542_rev2_1: 460 case em_ich8lan: 461 /* Adapters that do not support Jumbo frames */ 462 sc->hw.max_frame_size = ETHER_MAX_LEN; 463 break; 464 default: 465 sc->hw.max_frame_size = 466 MAX_JUMBO_FRAME_SIZE; 467 } 468 469 sc->hw.min_frame_size = 470 ETHER_MIN_LEN + ETHER_CRC_LEN; 471 472 /* Allocate Transmit Descriptor ring */ 473 if (em_dma_malloc(sc, sc->sc_tx_slots * sizeof(struct em_tx_desc), 474 &sc->sc_tx_dma) != 0) { 475 printf("%s: Unable to allocate tx_desc memory\n", 476 DEVNAME(sc)); 477 goto err_tx_desc; 478 } 479 sc->sc_tx_desc_ring = (struct em_tx_desc *)sc->sc_tx_dma.dma_vaddr; 480 481 /* Allocate Receive Descriptor ring */ 482 if (em_dma_malloc(sc, sc->sc_rx_slots * sizeof(struct em_rx_desc), 483 &sc->sc_rx_dma) != 0) { 484 printf("%s: Unable to allocate rx_desc memory\n", 485 DEVNAME(sc)); 486 goto err_rx_desc; 487 } 488 sc->sc_rx_desc_ring = (struct em_rx_desc *)sc->sc_rx_dma.dma_vaddr; 489 490 /* Initialize the hardware */ 491 if ((defer = em_hardware_init(sc))) { 492 if (defer == EAGAIN) 493 config_defer(self, em_defer_attach); 494 else { 495 printf("%s: Unable to initialize the hardware\n", 496 DEVNAME(sc)); 497 goto err_hw_init; 498 } 499 } 500 501 if (sc->hw.mac_type == em_80003es2lan || sc->hw.mac_type == em_82575 || 502 sc->hw.mac_type == em_82580 || sc->hw.mac_type == em_i210 || 503 sc->hw.mac_type == em_i350) { 504 uint32_t reg = EM_READ_REG(&sc->hw, E1000_STATUS); 505 sc->hw.bus_func = (reg & E1000_STATUS_FUNC_MASK) >> 506 E1000_STATUS_FUNC_SHIFT; 507 508 switch (sc->hw.bus_func) { 509 case 0: 510 sc->hw.swfw = E1000_SWFW_PHY0_SM; 511 break; 512 case 1: 513 sc->hw.swfw = E1000_SWFW_PHY1_SM; 514 break; 515 case 2: 516 sc->hw.swfw = E1000_SWFW_PHY2_SM; 517 break; 518 case 3: 519 sc->hw.swfw = E1000_SWFW_PHY3_SM; 520 break; 521 } 522 } else { 523 sc->hw.bus_func = 0; 524 } 525 526 /* Copy the permanent MAC address out of the EEPROM */ 527 if (em_read_mac_addr(&sc->hw) < 0) { 528 printf("%s: EEPROM read error while reading mac address\n", 529 DEVNAME(sc)); 530 goto err_mac_addr; 531 } 532 533 bcopy(sc->hw.mac_addr, sc->sc_ac.ac_enaddr, ETHER_ADDR_LEN); 534 535 /* Setup OS specific network interface */ 536 if (!defer) 537 em_setup_interface(sc); 538 539 /* Initialize statistics */ 540 em_clear_hw_cntrs(&sc->hw); 541 #ifndef SMALL_KERNEL 542 em_update_stats_counters(sc); 543 #endif 544 sc->hw.get_link_status = 1; 545 if (!defer) 546 em_update_link_status(sc); 547 548 printf(", address %s\n", ether_sprintf(sc->sc_ac.ac_enaddr)); 549 550 /* Indicate SOL/IDER usage */ 551 if (em_check_phy_reset_block(&sc->hw)) 552 printf("%s: PHY reset is blocked due to SOL/IDER session.\n", 553 DEVNAME(sc)); 554 555 /* Identify 82544 on PCI-X */ 556 em_get_bus_info(&sc->hw); 557 if (sc->hw.bus_type == em_bus_type_pcix && 558 sc->hw.mac_type == em_82544) 559 sc->pcix_82544 = TRUE; 560 else 561 sc->pcix_82544 = FALSE; 562 563 sc->hw.icp_xxxx_is_link_up = FALSE; 564 565 INIT_DEBUGOUT("em_attach: end"); 566 return; 567 568 err_mac_addr: 569 err_hw_init: 570 sc->sc_rx_desc_ring = NULL; 571 em_dma_free(sc, &sc->sc_rx_dma); 572 err_rx_desc: 573 sc->sc_tx_desc_ring = NULL; 574 em_dma_free(sc, &sc->sc_tx_dma); 575 err_tx_desc: 576 err_pci: 577 em_free_pci_resources(sc); 578 } 579 580 /********************************************************************* 581 * Transmit entry point 582 * 583 * em_start is called by the stack to initiate a transmit. 584 * The driver will remain in this routine as long as there are 585 * packets to transmit and transmit resources are available. 586 * In case resources are not available stack is notified and 587 * the packet is requeued. 588 **********************************************************************/ 589 590 void 591 em_start(struct ifqueue *ifq) 592 { 593 struct ifnet *ifp = ifq->ifq_if; 594 struct em_softc *sc = ifp->if_softc; 595 u_int head, free, used; 596 struct mbuf *m; 597 int post = 0; 598 599 if (!sc->link_active) { 600 ifq_purge(ifq); 601 return; 602 } 603 604 /* calculate free space */ 605 head = sc->sc_tx_desc_head; 606 free = sc->sc_tx_desc_tail; 607 if (free <= head) 608 free += sc->sc_tx_slots; 609 free -= head; 610 611 if (sc->hw.mac_type != em_82547) { 612 bus_dmamap_sync(sc->sc_dmat, sc->sc_tx_dma.dma_map, 613 0, sc->sc_tx_dma.dma_map->dm_mapsize, 614 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 615 } 616 617 for (;;) { 618 /* use 2 because cksum setup can use an extra slot */ 619 if (EM_MAX_SCATTER + 2 > free) { 620 ifq_set_oactive(ifq); 621 break; 622 } 623 624 m = ifq_dequeue(ifq); 625 if (m == NULL) 626 break; 627 628 used = em_encap(sc, m); 629 if (used == 0) { 630 m_freem(m); 631 continue; 632 } 633 634 KASSERT(used <= free); 635 636 free -= used; 637 638 #if NBPFILTER > 0 639 /* Send a copy of the frame to the BPF listener */ 640 if (ifp->if_bpf) 641 bpf_mtap_ether(ifp->if_bpf, m, BPF_DIRECTION_OUT); 642 #endif 643 644 /* Set timeout in case hardware has problems transmitting */ 645 ifp->if_timer = EM_TX_TIMEOUT; 646 647 if (sc->hw.mac_type == em_82547) { 648 int len = m->m_pkthdr.len; 649 650 if (sc->link_duplex == HALF_DUPLEX) 651 em_82547_move_tail_locked(sc); 652 else { 653 E1000_WRITE_REG(&sc->hw, TDT, 654 sc->sc_tx_desc_head); 655 em_82547_update_fifo_head(sc, len); 656 } 657 } 658 659 post = 1; 660 } 661 662 if (sc->hw.mac_type != em_82547) { 663 bus_dmamap_sync(sc->sc_dmat, sc->sc_tx_dma.dma_map, 664 0, sc->sc_tx_dma.dma_map->dm_mapsize, 665 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 666 /* 667 * Advance the Transmit Descriptor Tail (Tdt), 668 * this tells the E1000 that this frame is 669 * available to transmit. 670 */ 671 if (post) 672 E1000_WRITE_REG(&sc->hw, TDT, sc->sc_tx_desc_head); 673 } 674 } 675 676 /********************************************************************* 677 * Ioctl entry point 678 * 679 * em_ioctl is called when the user wants to configure the 680 * interface. 681 * 682 * return 0 on success, positive on failure 683 **********************************************************************/ 684 685 int 686 em_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 687 { 688 int error = 0; 689 struct ifreq *ifr = (struct ifreq *) data; 690 struct em_softc *sc = ifp->if_softc; 691 int s; 692 693 s = splnet(); 694 695 switch (command) { 696 case SIOCSIFADDR: 697 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFADDR (Set Interface " 698 "Addr)"); 699 if (!(ifp->if_flags & IFF_UP)) { 700 ifp->if_flags |= IFF_UP; 701 em_init(sc); 702 } 703 break; 704 705 case SIOCSIFFLAGS: 706 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFFLAGS (Set Interface Flags)"); 707 if (ifp->if_flags & IFF_UP) { 708 if (ifp->if_flags & IFF_RUNNING) 709 error = ENETRESET; 710 else 711 em_init(sc); 712 } else { 713 if (ifp->if_flags & IFF_RUNNING) 714 em_stop(sc, 0); 715 } 716 break; 717 718 case SIOCSIFMEDIA: 719 /* Check SOL/IDER usage */ 720 if (em_check_phy_reset_block(&sc->hw)) { 721 printf("%s: Media change is blocked due to SOL/IDER session.\n", 722 DEVNAME(sc)); 723 break; 724 } 725 case SIOCGIFMEDIA: 726 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCxIFMEDIA (Get/Set Interface Media)"); 727 error = ifmedia_ioctl(ifp, ifr, &sc->media, command); 728 break; 729 730 case SIOCGIFRXR: 731 error = if_rxr_ioctl((struct if_rxrinfo *)ifr->ifr_data, 732 NULL, EM_MCLBYTES, &sc->sc_rx_ring); 733 break; 734 735 default: 736 error = ether_ioctl(ifp, &sc->sc_ac, command, data); 737 } 738 739 if (error == ENETRESET) { 740 if (ifp->if_flags & IFF_RUNNING) { 741 em_disable_intr(sc); 742 em_iff(sc); 743 if (sc->hw.mac_type == em_82542_rev2_0) 744 em_initialize_receive_unit(sc); 745 em_enable_intr(sc); 746 } 747 error = 0; 748 } 749 750 splx(s); 751 return (error); 752 } 753 754 /********************************************************************* 755 * Watchdog entry point 756 * 757 * This routine is called whenever hardware quits transmitting. 758 * 759 **********************************************************************/ 760 761 void 762 em_watchdog(struct ifnet *ifp) 763 { 764 struct em_softc *sc = ifp->if_softc; 765 766 /* If we are in this routine because of pause frames, then 767 * don't reset the hardware. 768 */ 769 if (E1000_READ_REG(&sc->hw, STATUS) & E1000_STATUS_TXOFF) { 770 ifp->if_timer = EM_TX_TIMEOUT; 771 return; 772 } 773 printf("%s: watchdog: head %u tail %u TDH %u TDT %u\n", 774 DEVNAME(sc), 775 sc->sc_tx_desc_head, sc->sc_tx_desc_tail, 776 E1000_READ_REG(&sc->hw, TDH), E1000_READ_REG(&sc->hw, TDT)); 777 778 em_init(sc); 779 780 sc->watchdog_events++; 781 } 782 783 /********************************************************************* 784 * Init entry point 785 * 786 * This routine is used in two ways. It is used by the stack as 787 * init entry point in network interface structure. It is also used 788 * by the driver as a hw/sw initialization routine to get to a 789 * consistent state. 790 * 791 **********************************************************************/ 792 793 void 794 em_init(void *arg) 795 { 796 struct em_softc *sc = arg; 797 struct ifnet *ifp = &sc->sc_ac.ac_if; 798 uint32_t pba; 799 int s; 800 801 s = splnet(); 802 803 INIT_DEBUGOUT("em_init: begin"); 804 805 em_stop(sc, 0); 806 807 /* 808 * Packet Buffer Allocation (PBA) 809 * Writing PBA sets the receive portion of the buffer 810 * the remainder is used for the transmit buffer. 811 * 812 * Devices before the 82547 had a Packet Buffer of 64K. 813 * Default allocation: PBA=48K for Rx, leaving 16K for Tx. 814 * After the 82547 the buffer was reduced to 40K. 815 * Default allocation: PBA=30K for Rx, leaving 10K for Tx. 816 * Note: default does not leave enough room for Jumbo Frame >10k. 817 */ 818 switch (sc->hw.mac_type) { 819 case em_82547: 820 case em_82547_rev_2: /* 82547: Total Packet Buffer is 40K */ 821 if (sc->hw.max_frame_size > EM_RXBUFFER_8192) 822 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 823 else 824 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 825 sc->tx_fifo_head = 0; 826 sc->tx_head_addr = pba << EM_TX_HEAD_ADDR_SHIFT; 827 sc->tx_fifo_size = (E1000_PBA_40K - pba) << EM_PBA_BYTES_SHIFT; 828 break; 829 case em_82571: 830 case em_82572: /* Total Packet Buffer on these is 48k */ 831 case em_82575: 832 case em_82580: 833 case em_80003es2lan: 834 case em_i350: 835 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 836 break; 837 case em_i210: 838 pba = E1000_PBA_34K; 839 break; 840 case em_82573: /* 82573: Total Packet Buffer is 32K */ 841 /* Jumbo frames not supported */ 842 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 843 break; 844 case em_82574: /* Total Packet Buffer is 40k */ 845 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */ 846 break; 847 case em_ich8lan: 848 pba = E1000_PBA_8K; 849 break; 850 case em_ich9lan: 851 case em_ich10lan: 852 /* Boost Receive side for jumbo frames */ 853 if (sc->hw.max_frame_size > EM_RXBUFFER_4096) 854 pba = E1000_PBA_14K; 855 else 856 pba = E1000_PBA_10K; 857 break; 858 case em_pchlan: 859 case em_pch2lan: 860 case em_pch_lpt: 861 case em_pch_spt: 862 pba = E1000_PBA_26K; 863 break; 864 default: 865 /* Devices before 82547 had a Packet Buffer of 64K. */ 866 if (sc->hw.max_frame_size > EM_RXBUFFER_8192) 867 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 868 else 869 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 870 } 871 INIT_DEBUGOUT1("em_init: pba=%dK",pba); 872 E1000_WRITE_REG(&sc->hw, PBA, pba); 873 874 /* Get the latest mac address, User can use a LAA */ 875 bcopy(sc->sc_ac.ac_enaddr, sc->hw.mac_addr, ETHER_ADDR_LEN); 876 877 /* Initialize the hardware */ 878 if (em_hardware_init(sc)) { 879 printf("%s: Unable to initialize the hardware\n", 880 DEVNAME(sc)); 881 splx(s); 882 return; 883 } 884 em_update_link_status(sc); 885 886 E1000_WRITE_REG(&sc->hw, VET, ETHERTYPE_VLAN); 887 if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) 888 em_enable_hw_vlans(sc); 889 890 /* Prepare transmit descriptors and buffers */ 891 if (em_setup_transmit_structures(sc)) { 892 printf("%s: Could not setup transmit structures\n", 893 DEVNAME(sc)); 894 em_stop(sc, 0); 895 splx(s); 896 return; 897 } 898 em_initialize_transmit_unit(sc); 899 900 /* Prepare receive descriptors and buffers */ 901 if (em_setup_receive_structures(sc)) { 902 printf("%s: Could not setup receive structures\n", 903 DEVNAME(sc)); 904 em_stop(sc, 0); 905 splx(s); 906 return; 907 } 908 em_initialize_receive_unit(sc); 909 910 /* Program promiscuous mode and multicast filters. */ 911 em_iff(sc); 912 913 ifp->if_flags |= IFF_RUNNING; 914 ifq_clr_oactive(&ifp->if_snd); 915 916 timeout_add_sec(&sc->timer_handle, 1); 917 em_clear_hw_cntrs(&sc->hw); 918 em_enable_intr(sc); 919 920 /* Don't reset the phy next time init gets called */ 921 sc->hw.phy_reset_disable = TRUE; 922 923 splx(s); 924 } 925 926 /********************************************************************* 927 * 928 * Interrupt Service routine 929 * 930 **********************************************************************/ 931 int 932 em_intr(void *arg) 933 { 934 struct em_softc *sc = arg; 935 struct ifnet *ifp = &sc->sc_ac.ac_if; 936 u_int32_t reg_icr, test_icr; 937 938 test_icr = reg_icr = E1000_READ_REG(&sc->hw, ICR); 939 if (sc->hw.mac_type >= em_82571) 940 test_icr = (reg_icr & E1000_ICR_INT_ASSERTED); 941 if (!test_icr) 942 return (0); 943 944 if (ifp->if_flags & IFF_RUNNING) { 945 em_txeof(sc); 946 947 if (em_rxeof(sc) || ISSET(reg_icr, E1000_ICR_RXO)) { 948 if (em_rxfill(sc)) { 949 E1000_WRITE_REG(&sc->hw, RDT, 950 sc->sc_rx_desc_head); 951 } 952 } 953 } 954 955 /* Link status change */ 956 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 957 KERNEL_LOCK(); 958 sc->hw.get_link_status = 1; 959 em_check_for_link(&sc->hw); 960 em_update_link_status(sc); 961 KERNEL_UNLOCK(); 962 } 963 964 return (1); 965 } 966 967 /********************************************************************* 968 * 969 * Media Ioctl callback 970 * 971 * This routine is called whenever the user queries the status of 972 * the interface using ifconfig. 973 * 974 **********************************************************************/ 975 void 976 em_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 977 { 978 struct em_softc *sc = ifp->if_softc; 979 uint64_t fiber_type = IFM_1000_SX; 980 u_int16_t gsr; 981 982 INIT_DEBUGOUT("em_media_status: begin"); 983 984 em_check_for_link(&sc->hw); 985 em_update_link_status(sc); 986 987 ifmr->ifm_status = IFM_AVALID; 988 ifmr->ifm_active = IFM_ETHER; 989 990 if (!sc->link_active) { 991 ifmr->ifm_active |= IFM_NONE; 992 return; 993 } 994 995 ifmr->ifm_status |= IFM_ACTIVE; 996 997 if (sc->hw.media_type == em_media_type_fiber || 998 sc->hw.media_type == em_media_type_internal_serdes) { 999 if (sc->hw.mac_type == em_82545) 1000 fiber_type = IFM_1000_LX; 1001 ifmr->ifm_active |= fiber_type | IFM_FDX; 1002 } else { 1003 switch (sc->link_speed) { 1004 case 10: 1005 ifmr->ifm_active |= IFM_10_T; 1006 break; 1007 case 100: 1008 ifmr->ifm_active |= IFM_100_TX; 1009 break; 1010 case 1000: 1011 ifmr->ifm_active |= IFM_1000_T; 1012 break; 1013 } 1014 1015 if (sc->link_duplex == FULL_DUPLEX) 1016 ifmr->ifm_active |= em_flowstatus(sc) | IFM_FDX; 1017 else 1018 ifmr->ifm_active |= IFM_HDX; 1019 1020 if (IFM_SUBTYPE(ifmr->ifm_active) == IFM_1000_T) { 1021 em_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &gsr); 1022 if (gsr & SR_1000T_MS_CONFIG_RES) 1023 ifmr->ifm_active |= IFM_ETH_MASTER; 1024 } 1025 } 1026 } 1027 1028 /********************************************************************* 1029 * 1030 * Media Ioctl callback 1031 * 1032 * This routine is called when the user changes speed/duplex using 1033 * media/mediopt option with ifconfig. 1034 * 1035 **********************************************************************/ 1036 int 1037 em_media_change(struct ifnet *ifp) 1038 { 1039 struct em_softc *sc = ifp->if_softc; 1040 struct ifmedia *ifm = &sc->media; 1041 1042 INIT_DEBUGOUT("em_media_change: begin"); 1043 1044 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1045 return (EINVAL); 1046 1047 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1048 case IFM_AUTO: 1049 sc->hw.autoneg = DO_AUTO_NEG; 1050 sc->hw.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1051 break; 1052 case IFM_1000_LX: 1053 case IFM_1000_SX: 1054 case IFM_1000_T: 1055 sc->hw.autoneg = DO_AUTO_NEG; 1056 sc->hw.autoneg_advertised = ADVERTISE_1000_FULL; 1057 break; 1058 case IFM_100_TX: 1059 sc->hw.autoneg = FALSE; 1060 sc->hw.autoneg_advertised = 0; 1061 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1062 sc->hw.forced_speed_duplex = em_100_full; 1063 else 1064 sc->hw.forced_speed_duplex = em_100_half; 1065 break; 1066 case IFM_10_T: 1067 sc->hw.autoneg = FALSE; 1068 sc->hw.autoneg_advertised = 0; 1069 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1070 sc->hw.forced_speed_duplex = em_10_full; 1071 else 1072 sc->hw.forced_speed_duplex = em_10_half; 1073 break; 1074 default: 1075 printf("%s: Unsupported media type\n", DEVNAME(sc)); 1076 } 1077 1078 /* 1079 * As the speed/duplex settings may have changed we need to 1080 * reset the PHY. 1081 */ 1082 sc->hw.phy_reset_disable = FALSE; 1083 1084 em_init(sc); 1085 1086 return (0); 1087 } 1088 1089 uint64_t 1090 em_flowstatus(struct em_softc *sc) 1091 { 1092 u_int16_t ar, lpar; 1093 1094 if (sc->hw.media_type == em_media_type_fiber || 1095 sc->hw.media_type == em_media_type_internal_serdes) 1096 return (0); 1097 1098 em_read_phy_reg(&sc->hw, PHY_AUTONEG_ADV, &ar); 1099 em_read_phy_reg(&sc->hw, PHY_LP_ABILITY, &lpar); 1100 1101 if ((ar & NWAY_AR_PAUSE) && (lpar & NWAY_LPAR_PAUSE)) 1102 return (IFM_FLOW|IFM_ETH_TXPAUSE|IFM_ETH_RXPAUSE); 1103 else if (!(ar & NWAY_AR_PAUSE) && (ar & NWAY_AR_ASM_DIR) && 1104 (lpar & NWAY_LPAR_PAUSE) && (lpar & NWAY_LPAR_ASM_DIR)) 1105 return (IFM_FLOW|IFM_ETH_TXPAUSE); 1106 else if ((ar & NWAY_AR_PAUSE) && (ar & NWAY_AR_ASM_DIR) && 1107 !(lpar & NWAY_LPAR_PAUSE) && (lpar & NWAY_LPAR_ASM_DIR)) 1108 return (IFM_FLOW|IFM_ETH_RXPAUSE); 1109 1110 return (0); 1111 } 1112 1113 /********************************************************************* 1114 * 1115 * This routine maps the mbufs to tx descriptors. 1116 * 1117 * return 0 on success, positive on failure 1118 **********************************************************************/ 1119 u_int 1120 em_encap(struct em_softc *sc, struct mbuf *m) 1121 { 1122 struct em_packet *pkt; 1123 struct em_tx_desc *desc; 1124 bus_dmamap_t map; 1125 u_int32_t txd_upper, txd_lower; 1126 u_int head, last, used = 0; 1127 int i, j; 1128 1129 /* For 82544 Workaround */ 1130 DESC_ARRAY desc_array; 1131 u_int32_t array_elements; 1132 1133 /* get a dmamap for this packet from the next free slot */ 1134 head = sc->sc_tx_desc_head; 1135 pkt = &sc->sc_tx_pkts_ring[head]; 1136 map = pkt->pkt_map; 1137 1138 switch (bus_dmamap_load_mbuf(sc->sc_dmat, map, m, BUS_DMA_NOWAIT)) { 1139 case 0: 1140 break; 1141 case EFBIG: 1142 if (m_defrag(m, M_DONTWAIT) == 0 && 1143 bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1144 BUS_DMA_NOWAIT) == 0) 1145 break; 1146 1147 /* FALLTHROUGH */ 1148 default: 1149 sc->no_tx_dma_setup++; 1150 return (0); 1151 } 1152 1153 bus_dmamap_sync(sc->sc_dmat, map, 1154 0, map->dm_mapsize, 1155 BUS_DMASYNC_PREWRITE); 1156 1157 if (sc->hw.mac_type == em_82547) { 1158 bus_dmamap_sync(sc->sc_dmat, sc->sc_tx_dma.dma_map, 1159 0, sc->sc_tx_dma.dma_map->dm_mapsize, 1160 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1161 } 1162 1163 if (sc->hw.mac_type >= em_82543 && sc->hw.mac_type != em_82575 && 1164 sc->hw.mac_type != em_82580 && sc->hw.mac_type != em_i210 && 1165 sc->hw.mac_type != em_i350) { 1166 used += em_transmit_checksum_setup(sc, m, head, 1167 &txd_upper, &txd_lower); 1168 } else { 1169 txd_upper = txd_lower = 0; 1170 } 1171 1172 head += used; 1173 if (head >= sc->sc_tx_slots) 1174 head -= sc->sc_tx_slots; 1175 1176 for (i = 0; i < map->dm_nsegs; i++) { 1177 /* If sc is 82544 and on PCI-X bus */ 1178 if (sc->pcix_82544) { 1179 /* 1180 * Check the Address and Length combination and 1181 * split the data accordingly 1182 */ 1183 array_elements = em_fill_descriptors( 1184 map->dm_segs[i].ds_addr, map->dm_segs[i].ds_len, 1185 &desc_array); 1186 for (j = 0; j < array_elements; j++) { 1187 desc = &sc->sc_tx_desc_ring[head]; 1188 1189 desc->buffer_addr = htole64( 1190 desc_array.descriptor[j].address); 1191 desc->lower.data = htole32( 1192 (sc->sc_txd_cmd | txd_lower | 1193 (u_int16_t)desc_array.descriptor[j].length)); 1194 desc->upper.data = htole32(txd_upper); 1195 1196 last = head; 1197 if (++head == sc->sc_tx_slots) 1198 head = 0; 1199 1200 used++; 1201 } 1202 } else { 1203 desc = &sc->sc_tx_desc_ring[head]; 1204 1205 desc->buffer_addr = htole64(map->dm_segs[i].ds_addr); 1206 desc->lower.data = htole32(sc->sc_txd_cmd | 1207 txd_lower | map->dm_segs[i].ds_len); 1208 desc->upper.data = htole32(txd_upper); 1209 1210 last = head; 1211 if (++head == sc->sc_tx_slots) 1212 head = 0; 1213 1214 used++; 1215 } 1216 } 1217 1218 #if NVLAN > 0 1219 /* Find out if we are in VLAN mode */ 1220 if (m->m_flags & M_VLANTAG) { 1221 /* Set the VLAN id */ 1222 desc->upper.fields.special = htole16(m->m_pkthdr.ether_vtag); 1223 1224 /* Tell hardware to add tag */ 1225 desc->lower.data |= htole32(E1000_TXD_CMD_VLE); 1226 } 1227 #endif 1228 1229 /* mark the packet with the mbuf and last desc slot */ 1230 pkt->pkt_m = m; 1231 pkt->pkt_eop = last; 1232 1233 sc->sc_tx_desc_head = head; 1234 1235 /* 1236 * Last Descriptor of Packet 1237 * needs End Of Packet (EOP) 1238 * and Report Status (RS) 1239 */ 1240 desc->lower.data |= htole32(E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS); 1241 1242 if (sc->hw.mac_type == em_82547) { 1243 bus_dmamap_sync(sc->sc_dmat, sc->sc_tx_dma.dma_map, 1244 0, sc->sc_tx_dma.dma_map->dm_mapsize, 1245 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1246 } 1247 1248 return (used); 1249 } 1250 1251 /********************************************************************* 1252 * 1253 * 82547 workaround to avoid controller hang in half-duplex environment. 1254 * The workaround is to avoid queuing a large packet that would span 1255 * the internal Tx FIFO ring boundary. We need to reset the FIFO pointers 1256 * in this case. We do that only when FIFO is quiescent. 1257 * 1258 **********************************************************************/ 1259 void 1260 em_82547_move_tail_locked(struct em_softc *sc) 1261 { 1262 uint16_t hw_tdt; 1263 uint16_t sw_tdt; 1264 struct em_tx_desc *tx_desc; 1265 uint16_t length = 0; 1266 boolean_t eop = 0; 1267 1268 hw_tdt = E1000_READ_REG(&sc->hw, TDT); 1269 sw_tdt = sc->sc_tx_desc_head; 1270 1271 while (hw_tdt != sw_tdt) { 1272 tx_desc = &sc->sc_tx_desc_ring[hw_tdt]; 1273 length += tx_desc->lower.flags.length; 1274 eop = tx_desc->lower.data & E1000_TXD_CMD_EOP; 1275 if (++hw_tdt == sc->sc_tx_slots) 1276 hw_tdt = 0; 1277 1278 if (eop) { 1279 if (em_82547_fifo_workaround(sc, length)) { 1280 sc->tx_fifo_wrk_cnt++; 1281 timeout_add(&sc->tx_fifo_timer_handle, 1); 1282 break; 1283 } 1284 E1000_WRITE_REG(&sc->hw, TDT, hw_tdt); 1285 em_82547_update_fifo_head(sc, length); 1286 length = 0; 1287 } 1288 } 1289 } 1290 1291 void 1292 em_82547_move_tail(void *arg) 1293 { 1294 struct em_softc *sc = arg; 1295 int s; 1296 1297 s = splnet(); 1298 em_82547_move_tail_locked(sc); 1299 splx(s); 1300 } 1301 1302 int 1303 em_82547_fifo_workaround(struct em_softc *sc, int len) 1304 { 1305 int fifo_space, fifo_pkt_len; 1306 1307 fifo_pkt_len = EM_ROUNDUP(len + EM_FIFO_HDR, EM_FIFO_HDR); 1308 1309 if (sc->link_duplex == HALF_DUPLEX) { 1310 fifo_space = sc->tx_fifo_size - sc->tx_fifo_head; 1311 1312 if (fifo_pkt_len >= (EM_82547_PKT_THRESH + fifo_space)) { 1313 if (em_82547_tx_fifo_reset(sc)) 1314 return (0); 1315 else 1316 return (1); 1317 } 1318 } 1319 1320 return (0); 1321 } 1322 1323 void 1324 em_82547_update_fifo_head(struct em_softc *sc, int len) 1325 { 1326 int fifo_pkt_len = EM_ROUNDUP(len + EM_FIFO_HDR, EM_FIFO_HDR); 1327 1328 /* tx_fifo_head is always 16 byte aligned */ 1329 sc->tx_fifo_head += fifo_pkt_len; 1330 if (sc->tx_fifo_head >= sc->tx_fifo_size) 1331 sc->tx_fifo_head -= sc->tx_fifo_size; 1332 } 1333 1334 int 1335 em_82547_tx_fifo_reset(struct em_softc *sc) 1336 { 1337 uint32_t tctl; 1338 1339 if ((E1000_READ_REG(&sc->hw, TDT) == 1340 E1000_READ_REG(&sc->hw, TDH)) && 1341 (E1000_READ_REG(&sc->hw, TDFT) == 1342 E1000_READ_REG(&sc->hw, TDFH)) && 1343 (E1000_READ_REG(&sc->hw, TDFTS) == 1344 E1000_READ_REG(&sc->hw, TDFHS)) && 1345 (E1000_READ_REG(&sc->hw, TDFPC) == 0)) { 1346 1347 /* Disable TX unit */ 1348 tctl = E1000_READ_REG(&sc->hw, TCTL); 1349 E1000_WRITE_REG(&sc->hw, TCTL, tctl & ~E1000_TCTL_EN); 1350 1351 /* Reset FIFO pointers */ 1352 E1000_WRITE_REG(&sc->hw, TDFT, sc->tx_head_addr); 1353 E1000_WRITE_REG(&sc->hw, TDFH, sc->tx_head_addr); 1354 E1000_WRITE_REG(&sc->hw, TDFTS, sc->tx_head_addr); 1355 E1000_WRITE_REG(&sc->hw, TDFHS, sc->tx_head_addr); 1356 1357 /* Re-enable TX unit */ 1358 E1000_WRITE_REG(&sc->hw, TCTL, tctl); 1359 E1000_WRITE_FLUSH(&sc->hw); 1360 1361 sc->tx_fifo_head = 0; 1362 sc->tx_fifo_reset_cnt++; 1363 1364 return (TRUE); 1365 } else 1366 return (FALSE); 1367 } 1368 1369 void 1370 em_iff(struct em_softc *sc) 1371 { 1372 struct ifnet *ifp = &sc->sc_ac.ac_if; 1373 struct arpcom *ac = &sc->sc_ac; 1374 u_int32_t reg_rctl = 0; 1375 u_int8_t mta[MAX_NUM_MULTICAST_ADDRESSES * ETH_LENGTH_OF_ADDRESS]; 1376 struct ether_multi *enm; 1377 struct ether_multistep step; 1378 int i = 0; 1379 1380 IOCTL_DEBUGOUT("em_iff: begin"); 1381 1382 if (sc->hw.mac_type == em_82542_rev2_0) { 1383 reg_rctl = E1000_READ_REG(&sc->hw, RCTL); 1384 if (sc->hw.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1385 em_pci_clear_mwi(&sc->hw); 1386 reg_rctl |= E1000_RCTL_RST; 1387 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 1388 msec_delay(5); 1389 } 1390 1391 reg_rctl = E1000_READ_REG(&sc->hw, RCTL); 1392 reg_rctl &= ~(E1000_RCTL_MPE | E1000_RCTL_UPE); 1393 ifp->if_flags &= ~IFF_ALLMULTI; 1394 1395 if (ifp->if_flags & IFF_PROMISC || ac->ac_multirangecnt > 0 || 1396 ac->ac_multicnt > MAX_NUM_MULTICAST_ADDRESSES) { 1397 ifp->if_flags |= IFF_ALLMULTI; 1398 reg_rctl |= E1000_RCTL_MPE; 1399 if (ifp->if_flags & IFF_PROMISC) 1400 reg_rctl |= E1000_RCTL_UPE; 1401 } else { 1402 ETHER_FIRST_MULTI(step, ac, enm); 1403 while (enm != NULL) { 1404 bcopy(enm->enm_addrlo, mta + i, ETH_LENGTH_OF_ADDRESS); 1405 i += ETH_LENGTH_OF_ADDRESS; 1406 1407 ETHER_NEXT_MULTI(step, enm); 1408 } 1409 1410 em_mc_addr_list_update(&sc->hw, mta, ac->ac_multicnt, 0, 1); 1411 } 1412 1413 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 1414 1415 if (sc->hw.mac_type == em_82542_rev2_0) { 1416 reg_rctl = E1000_READ_REG(&sc->hw, RCTL); 1417 reg_rctl &= ~E1000_RCTL_RST; 1418 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 1419 msec_delay(5); 1420 if (sc->hw.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1421 em_pci_set_mwi(&sc->hw); 1422 } 1423 } 1424 1425 /********************************************************************* 1426 * Timer routine 1427 * 1428 * This routine checks for link status and updates statistics. 1429 * 1430 **********************************************************************/ 1431 1432 void 1433 em_local_timer(void *arg) 1434 { 1435 struct ifnet *ifp; 1436 struct em_softc *sc = arg; 1437 int s; 1438 1439 ifp = &sc->sc_ac.ac_if; 1440 1441 s = splnet(); 1442 1443 #ifndef SMALL_KERNEL 1444 em_update_stats_counters(sc); 1445 #ifdef EM_DEBUG 1446 if (ifp->if_flags & IFF_DEBUG && ifp->if_flags & IFF_RUNNING) 1447 em_print_hw_stats(sc); 1448 #endif 1449 #endif 1450 em_smartspeed(sc); 1451 1452 timeout_add_sec(&sc->timer_handle, 1); 1453 1454 splx(s); 1455 } 1456 1457 void 1458 em_update_link_status(struct em_softc *sc) 1459 { 1460 struct ifnet *ifp = &sc->sc_ac.ac_if; 1461 u_char link_state; 1462 1463 if (E1000_READ_REG(&sc->hw, STATUS) & E1000_STATUS_LU) { 1464 if (sc->link_active == 0) { 1465 em_get_speed_and_duplex(&sc->hw, 1466 &sc->link_speed, 1467 &sc->link_duplex); 1468 /* Check if we may set SPEED_MODE bit on PCI-E */ 1469 if ((sc->link_speed == SPEED_1000) && 1470 ((sc->hw.mac_type == em_82571) || 1471 (sc->hw.mac_type == em_82572) || 1472 (sc->hw.mac_type == em_82575) || 1473 (sc->hw.mac_type == em_82580))) { 1474 int tarc0; 1475 1476 tarc0 = E1000_READ_REG(&sc->hw, TARC0); 1477 tarc0 |= SPEED_MODE_BIT; 1478 E1000_WRITE_REG(&sc->hw, TARC0, tarc0); 1479 } 1480 sc->link_active = 1; 1481 sc->smartspeed = 0; 1482 ifp->if_baudrate = IF_Mbps(sc->link_speed); 1483 } 1484 link_state = (sc->link_duplex == FULL_DUPLEX) ? 1485 LINK_STATE_FULL_DUPLEX : LINK_STATE_HALF_DUPLEX; 1486 if (ifp->if_link_state != link_state) { 1487 ifp->if_link_state = link_state; 1488 if_link_state_change(ifp); 1489 } 1490 } else { 1491 if (sc->link_active == 1) { 1492 ifp->if_baudrate = sc->link_speed = 0; 1493 sc->link_duplex = 0; 1494 sc->link_active = 0; 1495 } 1496 if (ifp->if_link_state != LINK_STATE_DOWN) { 1497 ifp->if_link_state = LINK_STATE_DOWN; 1498 if_link_state_change(ifp); 1499 } 1500 } 1501 } 1502 1503 /********************************************************************* 1504 * 1505 * This routine disables all traffic on the adapter by issuing a 1506 * global reset on the MAC and deallocates TX/RX buffers. 1507 * 1508 **********************************************************************/ 1509 1510 void 1511 em_stop(void *arg, int softonly) 1512 { 1513 struct em_softc *sc = arg; 1514 struct ifnet *ifp = &sc->sc_ac.ac_if; 1515 1516 /* Tell the stack that the interface is no longer active */ 1517 ifp->if_flags &= ~IFF_RUNNING; 1518 1519 INIT_DEBUGOUT("em_stop: begin"); 1520 1521 timeout_del(&sc->timer_handle); 1522 timeout_del(&sc->tx_fifo_timer_handle); 1523 1524 if (!softonly) 1525 em_disable_intr(sc); 1526 if (sc->hw.mac_type == em_pch_spt) 1527 em_flush_desc_rings(sc); 1528 if (!softonly) 1529 em_reset_hw(&sc->hw); 1530 1531 intr_barrier(sc->sc_intrhand); 1532 ifq_barrier(&ifp->if_snd); 1533 1534 KASSERT((ifp->if_flags & IFF_RUNNING) == 0); 1535 1536 ifq_clr_oactive(&ifp->if_snd); 1537 ifp->if_timer = 0; 1538 1539 em_free_transmit_structures(sc); 1540 em_free_receive_structures(sc); 1541 } 1542 1543 /********************************************************************* 1544 * 1545 * Determine hardware revision. 1546 * 1547 **********************************************************************/ 1548 void 1549 em_identify_hardware(struct em_softc *sc) 1550 { 1551 u_int32_t reg; 1552 struct pci_attach_args *pa = &sc->osdep.em_pa; 1553 1554 /* Make sure our PCI config space has the necessary stuff set */ 1555 sc->hw.pci_cmd_word = pci_conf_read(pa->pa_pc, pa->pa_tag, 1556 PCI_COMMAND_STATUS_REG); 1557 1558 /* Save off the information about this board */ 1559 sc->hw.vendor_id = PCI_VENDOR(pa->pa_id); 1560 sc->hw.device_id = PCI_PRODUCT(pa->pa_id); 1561 1562 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG); 1563 sc->hw.revision_id = PCI_REVISION(reg); 1564 1565 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 1566 sc->hw.subsystem_vendor_id = PCI_VENDOR(reg); 1567 sc->hw.subsystem_id = PCI_PRODUCT(reg); 1568 1569 /* Identify the MAC */ 1570 if (em_set_mac_type(&sc->hw)) 1571 printf("%s: Unknown MAC Type\n", DEVNAME(sc)); 1572 1573 if (sc->hw.mac_type == em_pchlan) 1574 sc->hw.revision_id = PCI_PRODUCT(pa->pa_id) & 0x0f; 1575 1576 if (sc->hw.mac_type == em_82541 || 1577 sc->hw.mac_type == em_82541_rev_2 || 1578 sc->hw.mac_type == em_82547 || 1579 sc->hw.mac_type == em_82547_rev_2) 1580 sc->hw.phy_init_script = TRUE; 1581 } 1582 1583 void 1584 em_legacy_irq_quirk_spt(struct em_softc *sc) 1585 { 1586 uint32_t reg; 1587 1588 /* Legacy interrupt: SPT needs a quirk. */ 1589 if (sc->hw.mac_type != em_pch_spt) 1590 return; 1591 if (sc->legacy_irq == 0) 1592 return; 1593 1594 reg = EM_READ_REG(&sc->hw, E1000_FEXTNVM7); 1595 reg |= E1000_FEXTNVM7_SIDE_CLK_UNGATE; 1596 EM_WRITE_REG(&sc->hw, E1000_FEXTNVM7, reg); 1597 1598 reg = EM_READ_REG(&sc->hw, E1000_FEXTNVM9); 1599 reg |= E1000_FEXTNVM9_IOSFSB_CLKGATE_DIS | 1600 E1000_FEXTNVM9_IOSFSB_CLKREQ_DIS; 1601 EM_WRITE_REG(&sc->hw, E1000_FEXTNVM9, reg); 1602 } 1603 1604 int 1605 em_allocate_pci_resources(struct em_softc *sc) 1606 { 1607 int val, rid; 1608 pci_intr_handle_t ih; 1609 const char *intrstr = NULL; 1610 struct pci_attach_args *pa = &sc->osdep.em_pa; 1611 pci_chipset_tag_t pc = pa->pa_pc; 1612 1613 val = pci_conf_read(pa->pa_pc, pa->pa_tag, EM_MMBA); 1614 if (PCI_MAPREG_TYPE(val) != PCI_MAPREG_TYPE_MEM) { 1615 printf(": mmba is not mem space\n"); 1616 return (ENXIO); 1617 } 1618 if (pci_mapreg_map(pa, EM_MMBA, PCI_MAPREG_MEM_TYPE(val), 0, 1619 &sc->osdep.mem_bus_space_tag, &sc->osdep.mem_bus_space_handle, 1620 &sc->osdep.em_membase, &sc->osdep.em_memsize, 0)) { 1621 printf(": cannot find mem space\n"); 1622 return (ENXIO); 1623 } 1624 1625 switch (sc->hw.mac_type) { 1626 case em_82544: 1627 case em_82540: 1628 case em_82545: 1629 case em_82546: 1630 case em_82541: 1631 case em_82541_rev_2: 1632 /* Figure out where our I/O BAR is ? */ 1633 for (rid = PCI_MAPREG_START; rid < PCI_MAPREG_END;) { 1634 val = pci_conf_read(pa->pa_pc, pa->pa_tag, rid); 1635 if (PCI_MAPREG_TYPE(val) == PCI_MAPREG_TYPE_IO) { 1636 sc->io_rid = rid; 1637 break; 1638 } 1639 rid += 4; 1640 if (PCI_MAPREG_MEM_TYPE(val) == 1641 PCI_MAPREG_MEM_TYPE_64BIT) 1642 rid += 4; /* skip high bits, too */ 1643 } 1644 1645 if (pci_mapreg_map(pa, rid, PCI_MAPREG_TYPE_IO, 0, 1646 &sc->osdep.io_bus_space_tag, &sc->osdep.io_bus_space_handle, 1647 &sc->osdep.em_iobase, &sc->osdep.em_iosize, 0)) { 1648 printf(": cannot find i/o space\n"); 1649 return (ENXIO); 1650 } 1651 1652 sc->hw.io_base = 0; 1653 break; 1654 default: 1655 break; 1656 } 1657 1658 sc->osdep.em_flashoffset = 0; 1659 /* for ICH8 and family we need to find the flash memory */ 1660 if (sc->hw.mac_type == em_pch_spt) { 1661 sc->osdep.flash_bus_space_tag = sc->osdep.mem_bus_space_tag; 1662 sc->osdep.flash_bus_space_handle = sc->osdep.mem_bus_space_handle; 1663 sc->osdep.em_flashbase = 0; 1664 sc->osdep.em_flashsize = 0; 1665 sc->osdep.em_flashoffset = 0xe000; 1666 } else if (IS_ICH8(sc->hw.mac_type)) { 1667 val = pci_conf_read(pa->pa_pc, pa->pa_tag, EM_FLASH); 1668 if (PCI_MAPREG_TYPE(val) != PCI_MAPREG_TYPE_MEM) { 1669 printf(": flash is not mem space\n"); 1670 return (ENXIO); 1671 } 1672 1673 if (pci_mapreg_map(pa, EM_FLASH, PCI_MAPREG_MEM_TYPE(val), 0, 1674 &sc->osdep.flash_bus_space_tag, &sc->osdep.flash_bus_space_handle, 1675 &sc->osdep.em_flashbase, &sc->osdep.em_flashsize, 0)) { 1676 printf(": cannot find mem space\n"); 1677 return (ENXIO); 1678 } 1679 } 1680 1681 sc->legacy_irq = 0; 1682 if (pci_intr_map_msi(pa, &ih)) { 1683 if (pci_intr_map(pa, &ih)) { 1684 printf(": couldn't map interrupt\n"); 1685 return (ENXIO); 1686 } 1687 sc->legacy_irq = 1; 1688 } 1689 1690 sc->osdep.dev = (struct device *)sc; 1691 sc->hw.back = &sc->osdep; 1692 1693 intrstr = pci_intr_string(pc, ih); 1694 sc->sc_intrhand = pci_intr_establish(pc, ih, IPL_NET | IPL_MPSAFE, 1695 em_intr, sc, DEVNAME(sc)); 1696 if (sc->sc_intrhand == NULL) { 1697 printf(": couldn't establish interrupt"); 1698 if (intrstr != NULL) 1699 printf(" at %s", intrstr); 1700 printf("\n"); 1701 return (ENXIO); 1702 } 1703 printf(": %s", intrstr); 1704 1705 /* 1706 * the ICP_xxxx device has multiple, duplicate register sets for 1707 * use when it is being used as a network processor. Disable those 1708 * registers here, as they are not necessary in this context and 1709 * can confuse the system 1710 */ 1711 if(sc->hw.mac_type == em_icp_xxxx) { 1712 int offset; 1713 pcireg_t val; 1714 1715 if (!pci_get_capability(sc->osdep.em_pa.pa_pc, 1716 sc->osdep.em_pa.pa_tag, PCI_CAP_ID_ST, &offset, &val)) { 1717 return (0); 1718 } 1719 offset += PCI_ST_SMIA_OFFSET; 1720 pci_conf_write(sc->osdep.em_pa.pa_pc, sc->osdep.em_pa.pa_tag, 1721 offset, 0x06); 1722 E1000_WRITE_REG(&sc->hw, IMC1, ~0x0); 1723 E1000_WRITE_REG(&sc->hw, IMC2, ~0x0); 1724 } 1725 return (0); 1726 } 1727 1728 void 1729 em_free_pci_resources(struct em_softc *sc) 1730 { 1731 struct pci_attach_args *pa = &sc->osdep.em_pa; 1732 pci_chipset_tag_t pc = pa->pa_pc; 1733 1734 if (sc->sc_intrhand) 1735 pci_intr_disestablish(pc, sc->sc_intrhand); 1736 sc->sc_intrhand = 0; 1737 1738 if (sc->osdep.em_flashbase) 1739 bus_space_unmap(sc->osdep.flash_bus_space_tag, sc->osdep.flash_bus_space_handle, 1740 sc->osdep.em_flashsize); 1741 sc->osdep.em_flashbase = 0; 1742 1743 if (sc->osdep.em_iobase) 1744 bus_space_unmap(sc->osdep.io_bus_space_tag, sc->osdep.io_bus_space_handle, 1745 sc->osdep.em_iosize); 1746 sc->osdep.em_iobase = 0; 1747 1748 if (sc->osdep.em_membase) 1749 bus_space_unmap(sc->osdep.mem_bus_space_tag, sc->osdep.mem_bus_space_handle, 1750 sc->osdep.em_memsize); 1751 sc->osdep.em_membase = 0; 1752 } 1753 1754 /********************************************************************* 1755 * 1756 * Initialize the hardware to a configuration as specified by the 1757 * em_softc structure. The controller is reset, the EEPROM is 1758 * verified, the MAC address is set, then the shared initialization 1759 * routines are called. 1760 * 1761 **********************************************************************/ 1762 int 1763 em_hardware_init(struct em_softc *sc) 1764 { 1765 uint32_t ret_val; 1766 u_int16_t rx_buffer_size; 1767 1768 INIT_DEBUGOUT("em_hardware_init: begin"); 1769 if (sc->hw.mac_type == em_pch_spt) 1770 em_flush_desc_rings(sc); 1771 /* Issue a global reset */ 1772 em_reset_hw(&sc->hw); 1773 1774 /* When hardware is reset, fifo_head is also reset */ 1775 sc->tx_fifo_head = 0; 1776 1777 /* Make sure we have a good EEPROM before we read from it */ 1778 if (em_get_flash_presence_i210(&sc->hw) && 1779 em_validate_eeprom_checksum(&sc->hw) < 0) { 1780 /* 1781 * Some PCIe parts fail the first check due to 1782 * the link being in sleep state, call it again, 1783 * if it fails a second time its a real issue. 1784 */ 1785 if (em_validate_eeprom_checksum(&sc->hw) < 0) { 1786 printf("%s: The EEPROM Checksum Is Not Valid\n", 1787 DEVNAME(sc)); 1788 return (EIO); 1789 } 1790 } 1791 1792 if (em_get_flash_presence_i210(&sc->hw) && 1793 em_read_part_num(&sc->hw, &(sc->part_num)) < 0) { 1794 printf("%s: EEPROM read error while reading part number\n", 1795 DEVNAME(sc)); 1796 return (EIO); 1797 } 1798 1799 /* Set up smart power down as default off on newer adapters */ 1800 if (!em_smart_pwr_down && 1801 (sc->hw.mac_type == em_82571 || 1802 sc->hw.mac_type == em_82572 || 1803 sc->hw.mac_type == em_82575 || 1804 sc->hw.mac_type == em_82580 || 1805 sc->hw.mac_type == em_i210 || 1806 sc->hw.mac_type == em_i350 )) { 1807 uint16_t phy_tmp = 0; 1808 1809 /* Speed up time to link by disabling smart power down */ 1810 em_read_phy_reg(&sc->hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 1811 phy_tmp &= ~IGP02E1000_PM_SPD; 1812 em_write_phy_reg(&sc->hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp); 1813 } 1814 1815 em_legacy_irq_quirk_spt(sc); 1816 1817 /* 1818 * These parameters control the automatic generation (Tx) and 1819 * response (Rx) to Ethernet PAUSE frames. 1820 * - High water mark should allow for at least two frames to be 1821 * received after sending an XOFF. 1822 * - Low water mark works best when it is very near the high water mark. 1823 * This allows the receiver to restart by sending XON when it has 1824 * drained a bit. Here we use an arbitary value of 1500 which will 1825 * restart after one full frame is pulled from the buffer. There 1826 * could be several smaller frames in the buffer and if so they will 1827 * not trigger the XON until their total number reduces the buffer 1828 * by 1500. 1829 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 1830 */ 1831 rx_buffer_size = ((E1000_READ_REG(&sc->hw, PBA) & 0xffff) << 10 ); 1832 1833 sc->hw.fc_high_water = rx_buffer_size - 1834 EM_ROUNDUP(sc->hw.max_frame_size, 1024); 1835 sc->hw.fc_low_water = sc->hw.fc_high_water - 1500; 1836 if (sc->hw.mac_type == em_80003es2lan) 1837 sc->hw.fc_pause_time = 0xFFFF; 1838 else 1839 sc->hw.fc_pause_time = 1000; 1840 sc->hw.fc_send_xon = TRUE; 1841 sc->hw.fc = E1000_FC_FULL; 1842 1843 em_disable_aspm(sc); 1844 1845 if ((ret_val = em_init_hw(&sc->hw)) != 0) { 1846 if (ret_val == E1000_DEFER_INIT) { 1847 INIT_DEBUGOUT("\nHardware Initialization Deferred "); 1848 return (EAGAIN); 1849 } 1850 printf("\n%s: Hardware Initialization Failed\n", 1851 DEVNAME(sc)); 1852 return (EIO); 1853 } 1854 1855 em_check_for_link(&sc->hw); 1856 1857 return (0); 1858 } 1859 1860 /********************************************************************* 1861 * 1862 * Setup networking device structure and register an interface. 1863 * 1864 **********************************************************************/ 1865 void 1866 em_setup_interface(struct em_softc *sc) 1867 { 1868 struct ifnet *ifp; 1869 uint64_t fiber_type = IFM_1000_SX; 1870 1871 INIT_DEBUGOUT("em_setup_interface: begin"); 1872 1873 ifp = &sc->sc_ac.ac_if; 1874 strlcpy(ifp->if_xname, DEVNAME(sc), IFNAMSIZ); 1875 ifp->if_softc = sc; 1876 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1877 ifp->if_xflags = IFXF_MPSAFE; 1878 ifp->if_ioctl = em_ioctl; 1879 ifp->if_qstart = em_start; 1880 ifp->if_watchdog = em_watchdog; 1881 ifp->if_hardmtu = 1882 sc->hw.max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN; 1883 IFQ_SET_MAXLEN(&ifp->if_snd, sc->sc_tx_slots - 1); 1884 1885 ifp->if_capabilities = IFCAP_VLAN_MTU; 1886 1887 #if NVLAN > 0 1888 if (sc->hw.mac_type != em_82575 && sc->hw.mac_type != em_82580 && 1889 sc->hw.mac_type != em_i210 && sc->hw.mac_type != em_i350) 1890 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 1891 #endif 1892 1893 if (sc->hw.mac_type >= em_82543 && sc->hw.mac_type != em_82575 && 1894 sc->hw.mac_type != em_82580 && sc->hw.mac_type != em_i210 && 1895 sc->hw.mac_type != em_i350) 1896 ifp->if_capabilities |= IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 1897 1898 /* 1899 * Specify the media types supported by this adapter and register 1900 * callbacks to update media and link information 1901 */ 1902 ifmedia_init(&sc->media, IFM_IMASK, em_media_change, 1903 em_media_status); 1904 if (sc->hw.media_type == em_media_type_fiber || 1905 sc->hw.media_type == em_media_type_internal_serdes) { 1906 if (sc->hw.mac_type == em_82545) 1907 fiber_type = IFM_1000_LX; 1908 ifmedia_add(&sc->media, IFM_ETHER | fiber_type | IFM_FDX, 1909 0, NULL); 1910 ifmedia_add(&sc->media, IFM_ETHER | fiber_type, 1911 0, NULL); 1912 } else { 1913 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL); 1914 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX, 1915 0, NULL); 1916 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 1917 0, NULL); 1918 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 1919 0, NULL); 1920 if (sc->hw.phy_type != em_phy_ife) { 1921 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 1922 0, NULL); 1923 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_T, 0, NULL); 1924 } 1925 } 1926 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL); 1927 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO); 1928 1929 if_attach(ifp); 1930 ether_ifattach(ifp); 1931 } 1932 1933 int 1934 em_detach(struct device *self, int flags) 1935 { 1936 struct em_softc *sc = (struct em_softc *)self; 1937 struct ifnet *ifp = &sc->sc_ac.ac_if; 1938 struct pci_attach_args *pa = &sc->osdep.em_pa; 1939 pci_chipset_tag_t pc = pa->pa_pc; 1940 1941 if (sc->sc_intrhand) 1942 pci_intr_disestablish(pc, sc->sc_intrhand); 1943 sc->sc_intrhand = 0; 1944 1945 em_stop(sc, 1); 1946 1947 em_free_pci_resources(sc); 1948 1949 if (sc->sc_rx_desc_ring != NULL) { 1950 sc->sc_rx_desc_ring = NULL; 1951 em_dma_free(sc, &sc->sc_rx_dma); 1952 } 1953 if (sc->sc_tx_desc_ring != NULL) { 1954 sc->sc_tx_desc_ring = NULL; 1955 em_dma_free(sc, &sc->sc_tx_dma); 1956 } 1957 1958 ether_ifdetach(ifp); 1959 if_detach(ifp); 1960 1961 return (0); 1962 } 1963 1964 int 1965 em_activate(struct device *self, int act) 1966 { 1967 struct em_softc *sc = (struct em_softc *)self; 1968 struct ifnet *ifp = &sc->sc_ac.ac_if; 1969 int rv = 0; 1970 1971 switch (act) { 1972 case DVACT_SUSPEND: 1973 if (ifp->if_flags & IFF_RUNNING) 1974 em_stop(sc, 0); 1975 /* We have no children atm, but we will soon */ 1976 rv = config_activate_children(self, act); 1977 break; 1978 case DVACT_RESUME: 1979 if (ifp->if_flags & IFF_UP) 1980 em_init(sc); 1981 break; 1982 default: 1983 rv = config_activate_children(self, act); 1984 break; 1985 } 1986 return (rv); 1987 } 1988 1989 /********************************************************************* 1990 * 1991 * Workaround for SmartSpeed on 82541 and 82547 controllers 1992 * 1993 **********************************************************************/ 1994 void 1995 em_smartspeed(struct em_softc *sc) 1996 { 1997 uint16_t phy_tmp; 1998 1999 if (sc->link_active || (sc->hw.phy_type != em_phy_igp) || 2000 !sc->hw.autoneg || !(sc->hw.autoneg_advertised & ADVERTISE_1000_FULL)) 2001 return; 2002 2003 if (sc->smartspeed == 0) { 2004 /* If Master/Slave config fault is asserted twice, 2005 * we assume back-to-back */ 2006 em_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2007 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2008 return; 2009 em_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2010 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2011 em_read_phy_reg(&sc->hw, PHY_1000T_CTRL, 2012 &phy_tmp); 2013 if (phy_tmp & CR_1000T_MS_ENABLE) { 2014 phy_tmp &= ~CR_1000T_MS_ENABLE; 2015 em_write_phy_reg(&sc->hw, 2016 PHY_1000T_CTRL, phy_tmp); 2017 sc->smartspeed++; 2018 if (sc->hw.autoneg && 2019 !em_phy_setup_autoneg(&sc->hw) && 2020 !em_read_phy_reg(&sc->hw, PHY_CTRL, 2021 &phy_tmp)) { 2022 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2023 MII_CR_RESTART_AUTO_NEG); 2024 em_write_phy_reg(&sc->hw, 2025 PHY_CTRL, phy_tmp); 2026 } 2027 } 2028 } 2029 return; 2030 } else if (sc->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 2031 /* If still no link, perhaps using 2/3 pair cable */ 2032 em_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp); 2033 phy_tmp |= CR_1000T_MS_ENABLE; 2034 em_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp); 2035 if (sc->hw.autoneg && 2036 !em_phy_setup_autoneg(&sc->hw) && 2037 !em_read_phy_reg(&sc->hw, PHY_CTRL, &phy_tmp)) { 2038 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2039 MII_CR_RESTART_AUTO_NEG); 2040 em_write_phy_reg(&sc->hw, PHY_CTRL, phy_tmp); 2041 } 2042 } 2043 /* Restart process after EM_SMARTSPEED_MAX iterations */ 2044 if (sc->smartspeed++ == EM_SMARTSPEED_MAX) 2045 sc->smartspeed = 0; 2046 } 2047 2048 /* 2049 * Manage DMA'able memory. 2050 */ 2051 int 2052 em_dma_malloc(struct em_softc *sc, bus_size_t size, struct em_dma_alloc *dma) 2053 { 2054 int r; 2055 2056 r = bus_dmamap_create(sc->sc_dmat, size, 1, 2057 size, 0, BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, &dma->dma_map); 2058 if (r != 0) 2059 return (r); 2060 2061 r = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, &dma->dma_seg, 2062 1, &dma->dma_nseg, BUS_DMA_WAITOK | BUS_DMA_ZERO); 2063 if (r != 0) 2064 goto destroy; 2065 2066 r = bus_dmamem_map(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg, size, 2067 &dma->dma_vaddr, BUS_DMA_WAITOK); 2068 if (r != 0) 2069 goto free; 2070 2071 r = bus_dmamap_load(sc->sc_dmat, dma->dma_map, dma->dma_vaddr, size, 2072 NULL, BUS_DMA_WAITOK); 2073 if (r != 0) 2074 goto unmap; 2075 2076 dma->dma_size = size; 2077 return (0); 2078 2079 unmap: 2080 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, size); 2081 free: 2082 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 2083 destroy: 2084 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 2085 2086 return (r); 2087 } 2088 2089 void 2090 em_dma_free(struct em_softc *sc, struct em_dma_alloc *dma) 2091 { 2092 bus_dmamap_unload(sc->sc_dmat, dma->dma_map); 2093 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, dma->dma_size); 2094 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 2095 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 2096 } 2097 2098 /********************************************************************* 2099 * 2100 * Allocate memory for tx_buffer structures. The tx_buffer stores all 2101 * the information needed to transmit a packet on the wire. 2102 * 2103 **********************************************************************/ 2104 int 2105 em_allocate_transmit_structures(struct em_softc *sc) 2106 { 2107 bus_dmamap_sync(sc->sc_dmat, sc->sc_tx_dma.dma_map, 2108 0, sc->sc_tx_dma.dma_map->dm_mapsize, 2109 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2110 2111 sc->sc_tx_pkts_ring = mallocarray(sc->sc_tx_slots, 2112 sizeof(*sc->sc_tx_pkts_ring), M_DEVBUF, M_NOWAIT | M_ZERO); 2113 if (sc->sc_tx_pkts_ring == NULL) { 2114 printf("%s: Unable to allocate tx_buffer memory\n", 2115 DEVNAME(sc)); 2116 return (ENOMEM); 2117 } 2118 2119 return (0); 2120 } 2121 2122 /********************************************************************* 2123 * 2124 * Allocate and initialize transmit structures. 2125 * 2126 **********************************************************************/ 2127 int 2128 em_setup_transmit_structures(struct em_softc *sc) 2129 { 2130 struct em_packet *pkt; 2131 int error, i; 2132 2133 if ((error = em_allocate_transmit_structures(sc)) != 0) 2134 goto fail; 2135 2136 bzero((void *) sc->sc_tx_desc_ring, 2137 (sizeof(struct em_tx_desc)) * sc->sc_tx_slots); 2138 2139 for (i = 0; i < sc->sc_tx_slots; i++) { 2140 pkt = &sc->sc_tx_pkts_ring[i]; 2141 error = bus_dmamap_create(sc->sc_dmat, MAX_JUMBO_FRAME_SIZE, 2142 EM_MAX_SCATTER / (sc->pcix_82544 ? 2 : 1), 2143 MAX_JUMBO_FRAME_SIZE, 0, BUS_DMA_NOWAIT, &pkt->pkt_map); 2144 if (error != 0) { 2145 printf("%s: Unable to create TX DMA map\n", 2146 DEVNAME(sc)); 2147 goto fail; 2148 } 2149 } 2150 2151 sc->sc_tx_desc_head = 0; 2152 sc->sc_tx_desc_tail = 0; 2153 2154 /* Set checksum context */ 2155 sc->active_checksum_context = OFFLOAD_NONE; 2156 2157 return (0); 2158 2159 fail: 2160 em_free_transmit_structures(sc); 2161 return (error); 2162 } 2163 2164 /********************************************************************* 2165 * 2166 * Enable transmit unit. 2167 * 2168 **********************************************************************/ 2169 void 2170 em_initialize_transmit_unit(struct em_softc *sc) 2171 { 2172 u_int32_t reg_tctl, reg_tipg = 0; 2173 u_int64_t bus_addr; 2174 2175 INIT_DEBUGOUT("em_initialize_transmit_unit: begin"); 2176 2177 /* Setup the Base and Length of the Tx Descriptor Ring */ 2178 bus_addr = sc->sc_tx_dma.dma_map->dm_segs[0].ds_addr; 2179 E1000_WRITE_REG(&sc->hw, TDLEN, 2180 sc->sc_tx_slots * 2181 sizeof(struct em_tx_desc)); 2182 E1000_WRITE_REG(&sc->hw, TDBAH, (u_int32_t)(bus_addr >> 32)); 2183 E1000_WRITE_REG(&sc->hw, TDBAL, (u_int32_t)bus_addr); 2184 2185 /* Setup the HW Tx Head and Tail descriptor pointers */ 2186 E1000_WRITE_REG(&sc->hw, TDT, 0); 2187 E1000_WRITE_REG(&sc->hw, TDH, 0); 2188 2189 HW_DEBUGOUT2("Base = %x, Length = %x\n", 2190 E1000_READ_REG(&sc->hw, TDBAL), 2191 E1000_READ_REG(&sc->hw, TDLEN)); 2192 2193 /* Set the default values for the Tx Inter Packet Gap timer */ 2194 switch (sc->hw.mac_type) { 2195 case em_82542_rev2_0: 2196 case em_82542_rev2_1: 2197 reg_tipg = DEFAULT_82542_TIPG_IPGT; 2198 reg_tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2199 reg_tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2200 break; 2201 case em_80003es2lan: 2202 reg_tipg = DEFAULT_82543_TIPG_IPGR1; 2203 reg_tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2204 break; 2205 default: 2206 if (sc->hw.media_type == em_media_type_fiber || 2207 sc->hw.media_type == em_media_type_internal_serdes) 2208 reg_tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 2209 else 2210 reg_tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 2211 reg_tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2212 reg_tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2213 } 2214 2215 2216 E1000_WRITE_REG(&sc->hw, TIPG, reg_tipg); 2217 E1000_WRITE_REG(&sc->hw, TIDV, sc->tx_int_delay); 2218 if (sc->hw.mac_type >= em_82540) 2219 E1000_WRITE_REG(&sc->hw, TADV, sc->tx_abs_int_delay); 2220 2221 /* Setup Transmit Descriptor Base Settings */ 2222 sc->sc_txd_cmd = E1000_TXD_CMD_IFCS; 2223 2224 if (sc->hw.mac_type == em_82575 || sc->hw.mac_type == em_82580 || 2225 sc->hw.mac_type == em_i210 || sc->hw.mac_type == em_i350) { 2226 /* 82575/6 need to enable the TX queue and lack the IDE bit */ 2227 reg_tctl = E1000_READ_REG(&sc->hw, TXDCTL); 2228 reg_tctl |= E1000_TXDCTL_QUEUE_ENABLE; 2229 E1000_WRITE_REG(&sc->hw, TXDCTL, reg_tctl); 2230 } else if (sc->tx_int_delay > 0) 2231 sc->sc_txd_cmd |= E1000_TXD_CMD_IDE; 2232 2233 /* Program the Transmit Control Register */ 2234 reg_tctl = E1000_TCTL_PSP | E1000_TCTL_EN | 2235 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 2236 if (sc->hw.mac_type >= em_82571) 2237 reg_tctl |= E1000_TCTL_MULR; 2238 if (sc->link_duplex == FULL_DUPLEX) 2239 reg_tctl |= E1000_FDX_COLLISION_DISTANCE << E1000_COLD_SHIFT; 2240 else 2241 reg_tctl |= E1000_HDX_COLLISION_DISTANCE << E1000_COLD_SHIFT; 2242 /* This write will effectively turn on the transmit unit */ 2243 E1000_WRITE_REG(&sc->hw, TCTL, reg_tctl); 2244 2245 /* SPT Si errata workaround to avoid data corruption */ 2246 2247 if (sc->hw.mac_type == em_pch_spt) { 2248 uint32_t reg_val; 2249 2250 reg_val = EM_READ_REG(&sc->hw, E1000_IOSFPC); 2251 reg_val |= E1000_RCTL_RDMTS_HEX; 2252 EM_WRITE_REG(&sc->hw, E1000_IOSFPC, reg_val); 2253 2254 reg_val = E1000_READ_REG(&sc->hw, TARC0); 2255 reg_val |= E1000_TARC0_CB_MULTIQ_3_REQ; 2256 E1000_WRITE_REG(&sc->hw, TARC0, reg_val); 2257 } 2258 } 2259 2260 /********************************************************************* 2261 * 2262 * Free all transmit related data structures. 2263 * 2264 **********************************************************************/ 2265 void 2266 em_free_transmit_structures(struct em_softc *sc) 2267 { 2268 struct em_packet *pkt; 2269 int i; 2270 2271 INIT_DEBUGOUT("free_transmit_structures: begin"); 2272 2273 if (sc->sc_tx_pkts_ring != NULL) { 2274 for (i = 0; i < sc->sc_tx_slots; i++) { 2275 pkt = &sc->sc_tx_pkts_ring[i]; 2276 2277 if (pkt->pkt_m != NULL) { 2278 bus_dmamap_sync(sc->sc_dmat, pkt->pkt_map, 2279 0, pkt->pkt_map->dm_mapsize, 2280 BUS_DMASYNC_POSTWRITE); 2281 bus_dmamap_unload(sc->sc_dmat, pkt->pkt_map); 2282 2283 m_freem(pkt->pkt_m); 2284 pkt->pkt_m = NULL; 2285 } 2286 2287 if (pkt->pkt_map != NULL) { 2288 bus_dmamap_destroy(sc->sc_dmat, pkt->pkt_map); 2289 pkt->pkt_map = NULL; 2290 } 2291 } 2292 2293 free(sc->sc_tx_pkts_ring, M_DEVBUF, 2294 sc->sc_tx_slots * sizeof(*sc->sc_tx_pkts_ring)); 2295 sc->sc_tx_pkts_ring = NULL; 2296 } 2297 2298 bus_dmamap_sync(sc->sc_dmat, sc->sc_tx_dma.dma_map, 2299 0, sc->sc_tx_dma.dma_map->dm_mapsize, 2300 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2301 } 2302 2303 /********************************************************************* 2304 * 2305 * The offload context needs to be set when we transfer the first 2306 * packet of a particular protocol (TCP/UDP). We change the 2307 * context only if the protocol type changes. 2308 * 2309 **********************************************************************/ 2310 u_int 2311 em_transmit_checksum_setup(struct em_softc *sc, struct mbuf *mp, u_int head, 2312 u_int32_t *txd_upper, u_int32_t *txd_lower) 2313 { 2314 struct em_context_desc *TXD; 2315 2316 if (mp->m_pkthdr.csum_flags & M_TCP_CSUM_OUT) { 2317 *txd_upper = E1000_TXD_POPTS_TXSM << 8; 2318 *txd_lower = E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 2319 if (sc->active_checksum_context == OFFLOAD_TCP_IP) 2320 return (0); 2321 else 2322 sc->active_checksum_context = OFFLOAD_TCP_IP; 2323 } else if (mp->m_pkthdr.csum_flags & M_UDP_CSUM_OUT) { 2324 *txd_upper = E1000_TXD_POPTS_TXSM << 8; 2325 *txd_lower = E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 2326 if (sc->active_checksum_context == OFFLOAD_UDP_IP) 2327 return (0); 2328 else 2329 sc->active_checksum_context = OFFLOAD_UDP_IP; 2330 } else { 2331 *txd_upper = 0; 2332 *txd_lower = 0; 2333 return (0); 2334 } 2335 2336 /* If we reach this point, the checksum offload context 2337 * needs to be reset. 2338 */ 2339 TXD = (struct em_context_desc *)&sc->sc_tx_desc_ring[head]; 2340 2341 TXD->lower_setup.ip_fields.ipcss = ETHER_HDR_LEN; 2342 TXD->lower_setup.ip_fields.ipcso = 2343 ETHER_HDR_LEN + offsetof(struct ip, ip_sum); 2344 TXD->lower_setup.ip_fields.ipcse = 2345 htole16(ETHER_HDR_LEN + sizeof(struct ip) - 1); 2346 2347 TXD->upper_setup.tcp_fields.tucss = 2348 ETHER_HDR_LEN + sizeof(struct ip); 2349 TXD->upper_setup.tcp_fields.tucse = htole16(0); 2350 2351 if (sc->active_checksum_context == OFFLOAD_TCP_IP) { 2352 TXD->upper_setup.tcp_fields.tucso = 2353 ETHER_HDR_LEN + sizeof(struct ip) + 2354 offsetof(struct tcphdr, th_sum); 2355 } else if (sc->active_checksum_context == OFFLOAD_UDP_IP) { 2356 TXD->upper_setup.tcp_fields.tucso = 2357 ETHER_HDR_LEN + sizeof(struct ip) + 2358 offsetof(struct udphdr, uh_sum); 2359 } 2360 2361 TXD->tcp_seg_setup.data = htole32(0); 2362 TXD->cmd_and_length = htole32(sc->sc_txd_cmd | E1000_TXD_CMD_DEXT); 2363 2364 return (1); 2365 } 2366 2367 /********************************************************************** 2368 * 2369 * Examine each tx_buffer in the used queue. If the hardware is done 2370 * processing the packet then free associated resources. The 2371 * tx_buffer is put back on the free queue. 2372 * 2373 **********************************************************************/ 2374 void 2375 em_txeof(struct em_softc *sc) 2376 { 2377 struct ifnet *ifp = &sc->sc_ac.ac_if; 2378 struct em_packet *pkt; 2379 struct em_tx_desc *desc; 2380 u_int head, tail; 2381 u_int free = 0; 2382 2383 head = sc->sc_tx_desc_head; 2384 tail = sc->sc_tx_desc_tail; 2385 2386 if (head == tail) 2387 return; 2388 2389 bus_dmamap_sync(sc->sc_dmat, sc->sc_tx_dma.dma_map, 2390 0, sc->sc_tx_dma.dma_map->dm_mapsize, 2391 BUS_DMASYNC_POSTREAD); 2392 2393 do { 2394 pkt = &sc->sc_tx_pkts_ring[tail]; 2395 desc = &sc->sc_tx_desc_ring[pkt->pkt_eop]; 2396 2397 if (!ISSET(desc->upper.fields.status, E1000_TXD_STAT_DD)) 2398 break; 2399 2400 bus_dmamap_sync(sc->sc_dmat, pkt->pkt_map, 2401 0, pkt->pkt_map->dm_mapsize, 2402 BUS_DMASYNC_POSTWRITE); 2403 bus_dmamap_unload(sc->sc_dmat, pkt->pkt_map); 2404 2405 KASSERT(pkt->pkt_m != NULL); 2406 2407 m_freem(pkt->pkt_m); 2408 pkt->pkt_m = NULL; 2409 2410 tail = pkt->pkt_eop; 2411 2412 if (++tail == sc->sc_tx_slots) 2413 tail = 0; 2414 2415 free++; 2416 } while (tail != head); 2417 2418 bus_dmamap_sync(sc->sc_dmat, sc->sc_tx_dma.dma_map, 2419 0, sc->sc_tx_dma.dma_map->dm_mapsize, 2420 BUS_DMASYNC_PREREAD); 2421 2422 if (free == 0) 2423 return; 2424 2425 sc->sc_tx_desc_tail = tail; 2426 2427 if (ifq_is_oactive(&ifp->if_snd)) 2428 ifq_restart(&ifp->if_snd); 2429 else if (tail == head) 2430 ifp->if_timer = 0; 2431 } 2432 2433 /********************************************************************* 2434 * 2435 * Get a buffer from system mbuf buffer pool. 2436 * 2437 **********************************************************************/ 2438 int 2439 em_get_buf(struct em_softc *sc, int i) 2440 { 2441 struct mbuf *m; 2442 struct em_packet *pkt; 2443 struct em_rx_desc *desc; 2444 int error; 2445 2446 pkt = &sc->sc_rx_pkts_ring[i]; 2447 desc = &sc->sc_rx_desc_ring[i]; 2448 2449 KASSERT(pkt->pkt_m == NULL); 2450 2451 m = MCLGETI(NULL, M_DONTWAIT, NULL, EM_MCLBYTES); 2452 if (m == NULL) { 2453 sc->mbuf_cluster_failed++; 2454 return (ENOBUFS); 2455 } 2456 m->m_len = m->m_pkthdr.len = EM_MCLBYTES; 2457 m_adj(m, ETHER_ALIGN); 2458 2459 error = bus_dmamap_load_mbuf(sc->sc_dmat, pkt->pkt_map, 2460 m, BUS_DMA_NOWAIT); 2461 if (error) { 2462 m_freem(m); 2463 return (error); 2464 } 2465 2466 bus_dmamap_sync(sc->sc_dmat, pkt->pkt_map, 2467 0, pkt->pkt_map->dm_mapsize, 2468 BUS_DMASYNC_PREREAD); 2469 pkt->pkt_m = m; 2470 2471 memset(desc, 0, sizeof(*desc)); 2472 htolem64(&desc->buffer_addr, pkt->pkt_map->dm_segs[0].ds_addr); 2473 2474 return (0); 2475 } 2476 2477 /********************************************************************* 2478 * 2479 * Allocate memory for rx_buffer structures. Since we use one 2480 * rx_buffer per received packet, the maximum number of rx_buffer's 2481 * that we'll need is equal to the number of receive descriptors 2482 * that we've allocated. 2483 * 2484 **********************************************************************/ 2485 int 2486 em_allocate_receive_structures(struct em_softc *sc) 2487 { 2488 struct em_packet *pkt; 2489 int i; 2490 int error; 2491 2492 sc->sc_rx_pkts_ring = mallocarray(sc->sc_rx_slots, 2493 sizeof(*sc->sc_rx_pkts_ring), M_DEVBUF, M_NOWAIT | M_ZERO); 2494 if (sc->sc_rx_pkts_ring == NULL) { 2495 printf("%s: Unable to allocate rx_buffer memory\n", 2496 DEVNAME(sc)); 2497 return (ENOMEM); 2498 } 2499 2500 bus_dmamap_sync(sc->sc_dmat, sc->sc_rx_dma.dma_map, 2501 0, sc->sc_rx_dma.dma_map->dm_mapsize, 2502 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2503 2504 for (i = 0; i < sc->sc_rx_slots; i++) { 2505 pkt = &sc->sc_rx_pkts_ring[i]; 2506 2507 error = bus_dmamap_create(sc->sc_dmat, EM_MCLBYTES, 1, 2508 EM_MCLBYTES, 0, BUS_DMA_NOWAIT, &pkt->pkt_map); 2509 if (error != 0) { 2510 printf("%s: em_allocate_receive_structures: " 2511 "bus_dmamap_create failed; error %u\n", 2512 DEVNAME(sc), error); 2513 goto fail; 2514 } 2515 2516 pkt->pkt_m = NULL; 2517 } 2518 2519 return (0); 2520 2521 fail: 2522 em_free_receive_structures(sc); 2523 return (error); 2524 } 2525 2526 /********************************************************************* 2527 * 2528 * Allocate and initialize receive structures. 2529 * 2530 **********************************************************************/ 2531 int 2532 em_setup_receive_structures(struct em_softc *sc) 2533 { 2534 struct ifnet *ifp = &sc->sc_ac.ac_if; 2535 u_int lwm; 2536 2537 memset(sc->sc_rx_desc_ring, 0, 2538 sc->sc_rx_slots * sizeof(*sc->sc_rx_desc_ring)); 2539 2540 if (em_allocate_receive_structures(sc)) 2541 return (ENOMEM); 2542 2543 /* Setup our descriptor pointers */ 2544 sc->sc_rx_desc_tail = 0; 2545 sc->sc_rx_desc_head = sc->sc_rx_slots - 1; 2546 2547 lwm = max(4, 2 * ((ifp->if_hardmtu / MCLBYTES) + 1)); 2548 if_rxr_init(&sc->sc_rx_ring, lwm, sc->sc_rx_slots); 2549 2550 if (em_rxfill(sc) == 0) { 2551 printf("%s: unable to fill any rx descriptors\n", 2552 DEVNAME(sc)); 2553 } 2554 2555 return (0); 2556 } 2557 2558 /********************************************************************* 2559 * 2560 * Enable receive unit. 2561 * 2562 **********************************************************************/ 2563 void 2564 em_initialize_receive_unit(struct em_softc *sc) 2565 { 2566 u_int32_t reg_rctl; 2567 u_int32_t reg_rxcsum; 2568 u_int64_t bus_addr; 2569 2570 INIT_DEBUGOUT("em_initialize_receive_unit: begin"); 2571 2572 /* Make sure receives are disabled while setting up the descriptor ring */ 2573 E1000_WRITE_REG(&sc->hw, RCTL, 0); 2574 2575 /* Set the Receive Delay Timer Register */ 2576 E1000_WRITE_REG(&sc->hw, RDTR, 2577 sc->rx_int_delay | E1000_RDT_FPDB); 2578 2579 if (sc->hw.mac_type >= em_82540) { 2580 if (sc->rx_int_delay) 2581 E1000_WRITE_REG(&sc->hw, RADV, sc->rx_abs_int_delay); 2582 2583 /* Set the interrupt throttling rate. Value is calculated 2584 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */ 2585 E1000_WRITE_REG(&sc->hw, ITR, DEFAULT_ITR); 2586 } 2587 2588 /* Setup the Base and Length of the Rx Descriptor Ring */ 2589 bus_addr = sc->sc_rx_dma.dma_map->dm_segs[0].ds_addr; 2590 E1000_WRITE_REG(&sc->hw, RDLEN, 2591 sc->sc_rx_slots * sizeof(*sc->sc_rx_desc_ring)); 2592 E1000_WRITE_REG(&sc->hw, RDBAH, (u_int32_t)(bus_addr >> 32)); 2593 E1000_WRITE_REG(&sc->hw, RDBAL, (u_int32_t)bus_addr); 2594 2595 /* Setup the Receive Control Register */ 2596 reg_rctl = E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO | 2597 E1000_RCTL_RDMTS_HALF | 2598 (sc->hw.mc_filter_type << E1000_RCTL_MO_SHIFT); 2599 2600 if (sc->hw.tbi_compatibility_on == TRUE) 2601 reg_rctl |= E1000_RCTL_SBP; 2602 2603 /* 2604 * The i350 has a bug where it always strips the CRC whether 2605 * asked to or not. So ask for stripped CRC here and 2606 * cope in rxeof 2607 */ 2608 if (sc->hw.mac_type == em_i210 || sc->hw.mac_type == em_i350) 2609 reg_rctl |= E1000_RCTL_SECRC; 2610 2611 switch (sc->sc_rx_buffer_len) { 2612 default: 2613 case EM_RXBUFFER_2048: 2614 reg_rctl |= E1000_RCTL_SZ_2048; 2615 break; 2616 case EM_RXBUFFER_4096: 2617 reg_rctl |= E1000_RCTL_SZ_4096|E1000_RCTL_BSEX|E1000_RCTL_LPE; 2618 break; 2619 case EM_RXBUFFER_8192: 2620 reg_rctl |= E1000_RCTL_SZ_8192|E1000_RCTL_BSEX|E1000_RCTL_LPE; 2621 break; 2622 case EM_RXBUFFER_16384: 2623 reg_rctl |= E1000_RCTL_SZ_16384|E1000_RCTL_BSEX|E1000_RCTL_LPE; 2624 break; 2625 } 2626 2627 if (sc->hw.max_frame_size != ETHER_MAX_LEN) 2628 reg_rctl |= E1000_RCTL_LPE; 2629 2630 /* Enable 82543 Receive Checksum Offload for TCP and UDP */ 2631 if (sc->hw.mac_type >= em_82543) { 2632 reg_rxcsum = E1000_READ_REG(&sc->hw, RXCSUM); 2633 reg_rxcsum |= (E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL); 2634 E1000_WRITE_REG(&sc->hw, RXCSUM, reg_rxcsum); 2635 } 2636 2637 /* 2638 * XXX TEMPORARY WORKAROUND: on some systems with 82573 2639 * long latencies are observed, like Lenovo X60. 2640 */ 2641 if (sc->hw.mac_type == em_82573) 2642 E1000_WRITE_REG(&sc->hw, RDTR, 0x20); 2643 2644 if (sc->hw.mac_type == em_82575 || sc->hw.mac_type == em_82580 || 2645 sc->hw.mac_type == em_i210 || sc->hw.mac_type == em_i350) { 2646 /* 82575/6 need to enable the RX queue */ 2647 uint32_t reg; 2648 reg = E1000_READ_REG(&sc->hw, RXDCTL); 2649 reg |= E1000_RXDCTL_QUEUE_ENABLE; 2650 E1000_WRITE_REG(&sc->hw, RXDCTL, reg); 2651 } 2652 2653 /* Enable Receives */ 2654 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 2655 2656 /* Setup the HW Rx Head and Tail Descriptor Pointers */ 2657 E1000_WRITE_REG(&sc->hw, RDH, 0); 2658 E1000_WRITE_REG(&sc->hw, RDT, sc->sc_rx_desc_head); 2659 } 2660 2661 /********************************************************************* 2662 * 2663 * Free receive related data structures. 2664 * 2665 **********************************************************************/ 2666 void 2667 em_free_receive_structures(struct em_softc *sc) 2668 { 2669 struct em_packet *pkt; 2670 int i; 2671 2672 INIT_DEBUGOUT("free_receive_structures: begin"); 2673 2674 if_rxr_init(&sc->sc_rx_ring, 0, 0); 2675 2676 bus_dmamap_sync(sc->sc_dmat, sc->sc_rx_dma.dma_map, 2677 0, sc->sc_rx_dma.dma_map->dm_mapsize, 2678 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2679 2680 if (sc->sc_rx_pkts_ring != NULL) { 2681 for (i = 0; i < sc->sc_rx_slots; i++) { 2682 pkt = &sc->sc_rx_pkts_ring[i]; 2683 if (pkt->pkt_m != NULL) { 2684 bus_dmamap_sync(sc->sc_dmat, pkt->pkt_map, 2685 0, pkt->pkt_map->dm_mapsize, 2686 BUS_DMASYNC_POSTREAD); 2687 bus_dmamap_unload(sc->sc_dmat, pkt->pkt_map); 2688 m_freem(pkt->pkt_m); 2689 pkt->pkt_m = NULL; 2690 } 2691 bus_dmamap_destroy(sc->sc_dmat, pkt->pkt_map); 2692 } 2693 2694 free(sc->sc_rx_pkts_ring, M_DEVBUF, 2695 sc->sc_rx_slots * sizeof(*sc->sc_rx_pkts_ring)); 2696 sc->sc_rx_pkts_ring = NULL; 2697 } 2698 2699 if (sc->fmp != NULL) { 2700 m_freem(sc->fmp); 2701 sc->fmp = NULL; 2702 sc->lmp = NULL; 2703 } 2704 } 2705 2706 int 2707 em_rxfill(struct em_softc *sc) 2708 { 2709 u_int slots; 2710 int post = 0; 2711 int i; 2712 2713 i = sc->sc_rx_desc_head; 2714 2715 bus_dmamap_sync(sc->sc_dmat, sc->sc_rx_dma.dma_map, 2716 0, sc->sc_rx_dma.dma_map->dm_mapsize, 2717 BUS_DMASYNC_POSTWRITE); 2718 2719 for (slots = if_rxr_get(&sc->sc_rx_ring, sc->sc_rx_slots); 2720 slots > 0; slots--) { 2721 if (++i == sc->sc_rx_slots) 2722 i = 0; 2723 2724 if (em_get_buf(sc, i) != 0) 2725 break; 2726 2727 sc->sc_rx_desc_head = i; 2728 post = 1; 2729 } 2730 2731 if_rxr_put(&sc->sc_rx_ring, slots); 2732 2733 bus_dmamap_sync(sc->sc_dmat, sc->sc_rx_dma.dma_map, 2734 0, sc->sc_rx_dma.dma_map->dm_mapsize, 2735 BUS_DMASYNC_PREWRITE); 2736 2737 return (post); 2738 } 2739 2740 /********************************************************************* 2741 * 2742 * This routine executes in interrupt context. It replenishes 2743 * the mbufs in the descriptor and sends data which has been 2744 * dma'ed into host memory to upper layer. 2745 * 2746 *********************************************************************/ 2747 int 2748 em_rxeof(struct em_softc *sc) 2749 { 2750 struct ifnet *ifp = &sc->sc_ac.ac_if; 2751 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 2752 struct mbuf *m; 2753 u_int8_t accept_frame = 0; 2754 u_int8_t eop = 0; 2755 u_int16_t len, desc_len, prev_len_adj; 2756 int i, rv = 0; 2757 2758 /* Pointer to the receive descriptor being examined. */ 2759 struct em_rx_desc *desc; 2760 struct em_packet *pkt; 2761 u_int8_t status; 2762 2763 if (if_rxr_inuse(&sc->sc_rx_ring) == 0) 2764 return (0); 2765 2766 i = sc->sc_rx_desc_tail; 2767 2768 bus_dmamap_sync(sc->sc_dmat, sc->sc_rx_dma.dma_map, 2769 0, sc->sc_rx_dma.dma_map->dm_mapsize, 2770 BUS_DMASYNC_POSTREAD); 2771 2772 do { 2773 m = NULL; 2774 2775 pkt = &sc->sc_rx_pkts_ring[i]; 2776 desc = &sc->sc_rx_desc_ring[i]; 2777 2778 status = desc->status; 2779 if (!ISSET(status, E1000_RXD_STAT_DD)) 2780 break; 2781 2782 /* pull the mbuf off the ring */ 2783 bus_dmamap_sync(sc->sc_dmat, pkt->pkt_map, 2784 0, pkt->pkt_map->dm_mapsize, 2785 BUS_DMASYNC_POSTREAD); 2786 bus_dmamap_unload(sc->sc_dmat, pkt->pkt_map); 2787 m = pkt->pkt_m; 2788 pkt->pkt_m = NULL; 2789 2790 KASSERT(m != NULL); 2791 2792 if_rxr_put(&sc->sc_rx_ring, 1); 2793 rv = 1; 2794 2795 accept_frame = 1; 2796 prev_len_adj = 0; 2797 desc_len = letoh16(desc->length); 2798 2799 if (status & E1000_RXD_STAT_EOP) { 2800 eop = 1; 2801 if (desc_len < ETHER_CRC_LEN) { 2802 len = 0; 2803 prev_len_adj = ETHER_CRC_LEN - desc_len; 2804 } else if (sc->hw.mac_type == em_i210 || 2805 sc->hw.mac_type == em_i350) 2806 len = desc_len; 2807 else 2808 len = desc_len - ETHER_CRC_LEN; 2809 } else { 2810 eop = 0; 2811 len = desc_len; 2812 } 2813 2814 if (desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK) { 2815 u_int8_t last_byte; 2816 u_int32_t pkt_len = desc_len; 2817 2818 if (sc->fmp != NULL) 2819 pkt_len += sc->fmp->m_pkthdr.len; 2820 2821 last_byte = *(mtod(m, caddr_t) + desc_len - 1); 2822 if (TBI_ACCEPT(&sc->hw, status, desc->errors, 2823 pkt_len, last_byte)) { 2824 #ifndef SMALL_KERNEL 2825 em_tbi_adjust_stats(&sc->hw, &sc->stats, 2826 pkt_len, sc->hw.mac_addr); 2827 #endif 2828 if (len > 0) 2829 len--; 2830 } else 2831 accept_frame = 0; 2832 } 2833 2834 if (accept_frame) { 2835 /* Assign correct length to the current fragment */ 2836 m->m_len = len; 2837 2838 if (sc->fmp == NULL) { 2839 m->m_pkthdr.len = m->m_len; 2840 sc->fmp = m; /* Store the first mbuf */ 2841 sc->lmp = m; 2842 } else { 2843 /* Chain mbuf's together */ 2844 m->m_flags &= ~M_PKTHDR; 2845 /* 2846 * Adjust length of previous mbuf in chain if 2847 * we received less than 4 bytes in the last 2848 * descriptor. 2849 */ 2850 if (prev_len_adj > 0) { 2851 sc->lmp->m_len -= prev_len_adj; 2852 sc->fmp->m_pkthdr.len -= prev_len_adj; 2853 } 2854 sc->lmp->m_next = m; 2855 sc->lmp = m; 2856 sc->fmp->m_pkthdr.len += m->m_len; 2857 } 2858 2859 if (eop) { 2860 m = sc->fmp; 2861 2862 em_receive_checksum(sc, desc, m); 2863 #if NVLAN > 0 2864 if (desc->status & E1000_RXD_STAT_VP) { 2865 m->m_pkthdr.ether_vtag = 2866 letoh16(desc->special); 2867 m->m_flags |= M_VLANTAG; 2868 } 2869 #endif 2870 ml_enqueue(&ml, m); 2871 2872 sc->fmp = NULL; 2873 sc->lmp = NULL; 2874 } 2875 } else { 2876 sc->dropped_pkts++; 2877 2878 if (sc->fmp != NULL) { 2879 m_freem(sc->fmp); 2880 sc->fmp = NULL; 2881 sc->lmp = NULL; 2882 } 2883 2884 m_freem(m); 2885 } 2886 2887 /* Advance our pointers to the next descriptor. */ 2888 if (++i == sc->sc_rx_slots) 2889 i = 0; 2890 } while (if_rxr_inuse(&sc->sc_rx_ring) > 0); 2891 2892 bus_dmamap_sync(sc->sc_dmat, sc->sc_rx_dma.dma_map, 2893 0, sc->sc_rx_dma.dma_map->dm_mapsize, 2894 BUS_DMASYNC_PREREAD); 2895 2896 sc->sc_rx_desc_tail = i; 2897 2898 if_input(ifp, &ml); 2899 2900 return (rv); 2901 } 2902 2903 /********************************************************************* 2904 * 2905 * Verify that the hardware indicated that the checksum is valid. 2906 * Inform the stack about the status of checksum so that stack 2907 * doesn't spend time verifying the checksum. 2908 * 2909 *********************************************************************/ 2910 void 2911 em_receive_checksum(struct em_softc *sc, struct em_rx_desc *rx_desc, 2912 struct mbuf *mp) 2913 { 2914 /* 82543 or newer only */ 2915 if ((sc->hw.mac_type < em_82543) || 2916 /* Ignore Checksum bit is set */ 2917 (rx_desc->status & E1000_RXD_STAT_IXSM)) { 2918 mp->m_pkthdr.csum_flags = 0; 2919 return; 2920 } 2921 2922 if (rx_desc->status & E1000_RXD_STAT_IPCS) { 2923 /* Did it pass? */ 2924 if (!(rx_desc->errors & E1000_RXD_ERR_IPE)) { 2925 /* IP Checksum Good */ 2926 mp->m_pkthdr.csum_flags = M_IPV4_CSUM_IN_OK; 2927 2928 } else 2929 mp->m_pkthdr.csum_flags = 0; 2930 } 2931 2932 if (rx_desc->status & E1000_RXD_STAT_TCPCS) { 2933 /* Did it pass? */ 2934 if (!(rx_desc->errors & E1000_RXD_ERR_TCPE)) 2935 mp->m_pkthdr.csum_flags |= 2936 M_TCP_CSUM_IN_OK | M_UDP_CSUM_IN_OK; 2937 } 2938 } 2939 2940 /* 2941 * This turns on the hardware offload of the VLAN 2942 * tag insertion and strip 2943 */ 2944 void 2945 em_enable_hw_vlans(struct em_softc *sc) 2946 { 2947 uint32_t ctrl; 2948 2949 ctrl = E1000_READ_REG(&sc->hw, CTRL); 2950 ctrl |= E1000_CTRL_VME; 2951 E1000_WRITE_REG(&sc->hw, CTRL, ctrl); 2952 } 2953 2954 void 2955 em_enable_intr(struct em_softc *sc) 2956 { 2957 E1000_WRITE_REG(&sc->hw, IMS, (IMS_ENABLE_MASK)); 2958 } 2959 2960 void 2961 em_disable_intr(struct em_softc *sc) 2962 { 2963 /* 2964 * The first version of 82542 had an errata where when link 2965 * was forced it would stay up even if the cable was disconnected 2966 * Sequence errors were used to detect the disconnect and then 2967 * the driver would unforce the link. This code is in the ISR. 2968 * For this to work correctly the Sequence error interrupt had 2969 * to be enabled all the time. 2970 */ 2971 2972 if (sc->hw.mac_type == em_82542_rev2_0) 2973 E1000_WRITE_REG(&sc->hw, IMC, (0xffffffff & ~E1000_IMC_RXSEQ)); 2974 else 2975 E1000_WRITE_REG(&sc->hw, IMC, 0xffffffff); 2976 } 2977 2978 void 2979 em_write_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t *value) 2980 { 2981 struct pci_attach_args *pa = &((struct em_osdep *)hw->back)->em_pa; 2982 pcireg_t val; 2983 2984 val = pci_conf_read(pa->pa_pc, pa->pa_tag, reg & ~0x3); 2985 if (reg & 0x2) { 2986 val &= 0x0000ffff; 2987 val |= (*value << 16); 2988 } else { 2989 val &= 0xffff0000; 2990 val |= *value; 2991 } 2992 pci_conf_write(pa->pa_pc, pa->pa_tag, reg & ~0x3, val); 2993 } 2994 2995 void 2996 em_read_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t *value) 2997 { 2998 struct pci_attach_args *pa = &((struct em_osdep *)hw->back)->em_pa; 2999 pcireg_t val; 3000 3001 val = pci_conf_read(pa->pa_pc, pa->pa_tag, reg & ~0x3); 3002 if (reg & 0x2) 3003 *value = (val >> 16) & 0xffff; 3004 else 3005 *value = val & 0xffff; 3006 } 3007 3008 void 3009 em_pci_set_mwi(struct em_hw *hw) 3010 { 3011 struct pci_attach_args *pa = &((struct em_osdep *)hw->back)->em_pa; 3012 3013 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 3014 (hw->pci_cmd_word | CMD_MEM_WRT_INVALIDATE)); 3015 } 3016 3017 void 3018 em_pci_clear_mwi(struct em_hw *hw) 3019 { 3020 struct pci_attach_args *pa = &((struct em_osdep *)hw->back)->em_pa; 3021 3022 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 3023 (hw->pci_cmd_word & ~CMD_MEM_WRT_INVALIDATE)); 3024 } 3025 3026 /* 3027 * We may eventually really do this, but its unnecessary 3028 * for now so we just return unsupported. 3029 */ 3030 int32_t 3031 em_read_pcie_cap_reg(struct em_hw *hw, uint32_t reg, uint16_t *value) 3032 { 3033 return -E1000_NOT_IMPLEMENTED; 3034 } 3035 3036 /********************************************************************* 3037 * 82544 Coexistence issue workaround. 3038 * There are 2 issues. 3039 * 1. Transmit Hang issue. 3040 * To detect this issue, following equation can be used... 3041 * SIZE[3:0] + ADDR[2:0] = SUM[3:0]. 3042 * If SUM[3:0] is in between 1 to 4, we will have this issue. 3043 * 3044 * 2. DAC issue. 3045 * To detect this issue, following equation can be used... 3046 * SIZE[3:0] + ADDR[2:0] = SUM[3:0]. 3047 * If SUM[3:0] is in between 9 to c, we will have this issue. 3048 * 3049 * 3050 * WORKAROUND: 3051 * Make sure we do not have ending address as 1,2,3,4(Hang) or 9,a,b,c (DAC) 3052 * 3053 *** *********************************************************************/ 3054 u_int32_t 3055 em_fill_descriptors(u_int64_t address, u_int32_t length, 3056 PDESC_ARRAY desc_array) 3057 { 3058 /* Since issue is sensitive to length and address.*/ 3059 /* Let us first check the address...*/ 3060 u_int32_t safe_terminator; 3061 if (length <= 4) { 3062 desc_array->descriptor[0].address = address; 3063 desc_array->descriptor[0].length = length; 3064 desc_array->elements = 1; 3065 return desc_array->elements; 3066 } 3067 safe_terminator = (u_int32_t)((((u_int32_t)address & 0x7) + (length & 0xF)) & 0xF); 3068 /* if it does not fall between 0x1 to 0x4 and 0x9 to 0xC then return */ 3069 if (safe_terminator == 0 || 3070 (safe_terminator > 4 && 3071 safe_terminator < 9) || 3072 (safe_terminator > 0xC && 3073 safe_terminator <= 0xF)) { 3074 desc_array->descriptor[0].address = address; 3075 desc_array->descriptor[0].length = length; 3076 desc_array->elements = 1; 3077 return desc_array->elements; 3078 } 3079 3080 desc_array->descriptor[0].address = address; 3081 desc_array->descriptor[0].length = length - 4; 3082 desc_array->descriptor[1].address = address + (length - 4); 3083 desc_array->descriptor[1].length = 4; 3084 desc_array->elements = 2; 3085 return desc_array->elements; 3086 } 3087 3088 /* 3089 * Disable the L0S and L1 LINK states. 3090 */ 3091 void 3092 em_disable_aspm(struct em_softc *sc) 3093 { 3094 int offset; 3095 pcireg_t val; 3096 3097 switch (sc->hw.mac_type) { 3098 case em_82571: 3099 case em_82572: 3100 case em_82573: 3101 case em_82574: 3102 break; 3103 default: 3104 return; 3105 } 3106 3107 if (!pci_get_capability(sc->osdep.em_pa.pa_pc, sc->osdep.em_pa.pa_tag, 3108 PCI_CAP_PCIEXPRESS, &offset, NULL)) 3109 return; 3110 3111 /* Disable PCIe Active State Power Management (ASPM). */ 3112 val = pci_conf_read(sc->osdep.em_pa.pa_pc, sc->osdep.em_pa.pa_tag, 3113 offset + PCI_PCIE_LCSR); 3114 3115 switch (sc->hw.mac_type) { 3116 case em_82571: 3117 case em_82572: 3118 val &= ~PCI_PCIE_LCSR_ASPM_L1; 3119 break; 3120 case em_82573: 3121 case em_82574: 3122 val &= ~(PCI_PCIE_LCSR_ASPM_L0S | 3123 PCI_PCIE_LCSR_ASPM_L1); 3124 break; 3125 default: 3126 break; 3127 } 3128 3129 pci_conf_write(sc->osdep.em_pa.pa_pc, sc->osdep.em_pa.pa_tag, 3130 offset + PCI_PCIE_LCSR, val); 3131 } 3132 3133 /* 3134 * em_flush_tx_ring - remove all descriptors from the tx_ring 3135 * 3136 * We want to clear all pending descriptors from the TX ring. 3137 * zeroing happens when the HW reads the regs. We assign the ring itself as 3138 * the data of the next descriptor. We don't care about the data we are about 3139 * to reset the HW. 3140 */ 3141 void 3142 em_flush_tx_ring(struct em_softc *sc) 3143 { 3144 uint32_t tctl, txd_lower = E1000_TXD_CMD_IFCS; 3145 uint16_t size = 512; 3146 struct em_tx_desc *txd; 3147 3148 KASSERT(sc->sc_tx_desc_ring != NULL); 3149 3150 tctl = EM_READ_REG(&sc->hw, E1000_TCTL); 3151 EM_WRITE_REG(&sc->hw, E1000_TCTL, tctl | E1000_TCTL_EN); 3152 3153 KASSERT(EM_READ_REG(&sc->hw, E1000_TDT) == sc->sc_tx_desc_head); 3154 3155 txd = &sc->sc_tx_desc_ring[sc->sc_tx_desc_head]; 3156 txd->buffer_addr = sc->sc_tx_dma.dma_map->dm_segs[0].ds_addr; 3157 txd->lower.data = htole32(txd_lower | size); 3158 txd->upper.data = 0; 3159 3160 /* flush descriptors to memory before notifying the HW */ 3161 bus_space_barrier(sc->osdep.mem_bus_space_tag, 3162 sc->osdep.mem_bus_space_handle, 0, 0, BUS_SPACE_BARRIER_WRITE); 3163 3164 if (++sc->sc_tx_desc_head == sc->sc_tx_slots) 3165 sc->sc_tx_desc_head = 0; 3166 3167 EM_WRITE_REG(&sc->hw, E1000_TDT, sc->sc_tx_desc_head); 3168 bus_space_barrier(sc->osdep.mem_bus_space_tag, sc->osdep.mem_bus_space_handle, 3169 0, 0, BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE); 3170 usec_delay(250); 3171 } 3172 3173 /* 3174 * em_flush_rx_ring - remove all descriptors from the rx_ring 3175 * 3176 * Mark all descriptors in the RX ring as consumed and disable the rx ring 3177 */ 3178 void 3179 em_flush_rx_ring(struct em_softc *sc) 3180 { 3181 uint32_t rctl, rxdctl; 3182 3183 rctl = EM_READ_REG(&sc->hw, E1000_RCTL); 3184 EM_WRITE_REG(&sc->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 3185 E1000_WRITE_FLUSH(&sc->hw); 3186 usec_delay(150); 3187 3188 rxdctl = EM_READ_REG(&sc->hw, E1000_RXDCTL); 3189 /* zero the lower 14 bits (prefetch and host thresholds) */ 3190 rxdctl &= 0xffffc000; 3191 /* 3192 * update thresholds: prefetch threshold to 31, host threshold to 1 3193 * and make sure the granularity is "descriptors" and not "cache lines" 3194 */ 3195 rxdctl |= (0x1F | (1 << 8) | E1000_RXDCTL_THRESH_UNIT_DESC); 3196 EM_WRITE_REG(&sc->hw, E1000_RXDCTL, rxdctl); 3197 3198 /* momentarily enable the RX ring for the changes to take effect */ 3199 EM_WRITE_REG(&sc->hw, E1000_RCTL, rctl | E1000_RCTL_EN); 3200 E1000_WRITE_FLUSH(&sc->hw); 3201 usec_delay(150); 3202 EM_WRITE_REG(&sc->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 3203 } 3204 3205 /* 3206 * em_flush_desc_rings - remove all descriptors from the descriptor rings 3207 * 3208 * In i219, the descriptor rings must be emptied before resetting the HW 3209 * or before changing the device state to D3 during runtime (runtime PM). 3210 * 3211 * Failure to do this will cause the HW to enter a unit hang state which can 3212 * only be released by PCI reset on the device 3213 * 3214 */ 3215 void 3216 em_flush_desc_rings(struct em_softc *sc) 3217 { 3218 struct pci_attach_args *pa = &sc->osdep.em_pa; 3219 uint32_t fextnvm11, tdlen; 3220 uint16_t hang_state; 3221 3222 /* First, disable MULR fix in FEXTNVM11 */ 3223 fextnvm11 = EM_READ_REG(&sc->hw, E1000_FEXTNVM11); 3224 fextnvm11 |= E1000_FEXTNVM11_DISABLE_MULR_FIX; 3225 EM_WRITE_REG(&sc->hw, E1000_FEXTNVM11, fextnvm11); 3226 3227 /* do nothing if we're not in faulty state, or if the queue is empty */ 3228 tdlen = EM_READ_REG(&sc->hw, E1000_TDLEN); 3229 hang_state = pci_conf_read(pa->pa_pc, pa->pa_tag, PCICFG_DESC_RING_STATUS); 3230 if (!(hang_state & FLUSH_DESC_REQUIRED) || !tdlen) 3231 return; 3232 em_flush_tx_ring(sc); 3233 3234 /* recheck, maybe the fault is caused by the rx ring */ 3235 hang_state = pci_conf_read(pa->pa_pc, pa->pa_tag, PCICFG_DESC_RING_STATUS); 3236 if (hang_state & FLUSH_DESC_REQUIRED) 3237 em_flush_rx_ring(sc); 3238 } 3239 3240 #ifndef SMALL_KERNEL 3241 /********************************************************************** 3242 * 3243 * Update the board statistics counters. 3244 * 3245 **********************************************************************/ 3246 void 3247 em_update_stats_counters(struct em_softc *sc) 3248 { 3249 struct ifnet *ifp = &sc->sc_ac.ac_if; 3250 3251 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, CRCERRS); 3252 sc->stats.mpc += E1000_READ_REG(&sc->hw, MPC); 3253 sc->stats.ecol += E1000_READ_REG(&sc->hw, ECOL); 3254 3255 sc->stats.latecol += E1000_READ_REG(&sc->hw, LATECOL); 3256 sc->stats.colc += E1000_READ_REG(&sc->hw, COLC); 3257 3258 sc->stats.ruc += E1000_READ_REG(&sc->hw, RUC); 3259 sc->stats.roc += E1000_READ_REG(&sc->hw, ROC); 3260 3261 if (sc->hw.mac_type >= em_82543) { 3262 sc->stats.algnerrc += 3263 E1000_READ_REG(&sc->hw, ALGNERRC); 3264 sc->stats.rxerrc += 3265 E1000_READ_REG(&sc->hw, RXERRC); 3266 sc->stats.cexterr += 3267 E1000_READ_REG(&sc->hw, CEXTERR); 3268 } 3269 3270 #ifdef EM_DEBUG 3271 if (sc->hw.media_type == em_media_type_copper || 3272 (E1000_READ_REG(&sc->hw, STATUS) & E1000_STATUS_LU)) { 3273 sc->stats.symerrs += E1000_READ_REG(&sc->hw, SYMERRS); 3274 sc->stats.sec += E1000_READ_REG(&sc->hw, SEC); 3275 } 3276 sc->stats.scc += E1000_READ_REG(&sc->hw, SCC); 3277 3278 sc->stats.mcc += E1000_READ_REG(&sc->hw, MCC); 3279 sc->stats.dc += E1000_READ_REG(&sc->hw, DC); 3280 sc->stats.rlec += E1000_READ_REG(&sc->hw, RLEC); 3281 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, XONRXC); 3282 sc->stats.xontxc += E1000_READ_REG(&sc->hw, XONTXC); 3283 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, XOFFRXC); 3284 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, XOFFTXC); 3285 sc->stats.fcruc += E1000_READ_REG(&sc->hw, FCRUC); 3286 sc->stats.prc64 += E1000_READ_REG(&sc->hw, PRC64); 3287 sc->stats.prc127 += E1000_READ_REG(&sc->hw, PRC127); 3288 sc->stats.prc255 += E1000_READ_REG(&sc->hw, PRC255); 3289 sc->stats.prc511 += E1000_READ_REG(&sc->hw, PRC511); 3290 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, PRC1023); 3291 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, PRC1522); 3292 sc->stats.gprc += E1000_READ_REG(&sc->hw, GPRC); 3293 sc->stats.bprc += E1000_READ_REG(&sc->hw, BPRC); 3294 sc->stats.mprc += E1000_READ_REG(&sc->hw, MPRC); 3295 sc->stats.gptc += E1000_READ_REG(&sc->hw, GPTC); 3296 3297 /* For the 64-bit byte counters the low dword must be read first. */ 3298 /* Both registers clear on the read of the high dword */ 3299 3300 sc->stats.gorcl += E1000_READ_REG(&sc->hw, GORCL); 3301 sc->stats.gorch += E1000_READ_REG(&sc->hw, GORCH); 3302 sc->stats.gotcl += E1000_READ_REG(&sc->hw, GOTCL); 3303 sc->stats.gotch += E1000_READ_REG(&sc->hw, GOTCH); 3304 3305 sc->stats.rnbc += E1000_READ_REG(&sc->hw, RNBC); 3306 sc->stats.rfc += E1000_READ_REG(&sc->hw, RFC); 3307 sc->stats.rjc += E1000_READ_REG(&sc->hw, RJC); 3308 3309 sc->stats.torl += E1000_READ_REG(&sc->hw, TORL); 3310 sc->stats.torh += E1000_READ_REG(&sc->hw, TORH); 3311 sc->stats.totl += E1000_READ_REG(&sc->hw, TOTL); 3312 sc->stats.toth += E1000_READ_REG(&sc->hw, TOTH); 3313 3314 sc->stats.tpr += E1000_READ_REG(&sc->hw, TPR); 3315 sc->stats.tpt += E1000_READ_REG(&sc->hw, TPT); 3316 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, PTC64); 3317 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, PTC127); 3318 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, PTC255); 3319 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, PTC511); 3320 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, PTC1023); 3321 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, PTC1522); 3322 sc->stats.mptc += E1000_READ_REG(&sc->hw, MPTC); 3323 sc->stats.bptc += E1000_READ_REG(&sc->hw, BPTC); 3324 3325 if (sc->hw.mac_type >= em_82543) { 3326 sc->stats.tncrs += 3327 E1000_READ_REG(&sc->hw, TNCRS); 3328 sc->stats.tsctc += 3329 E1000_READ_REG(&sc->hw, TSCTC); 3330 sc->stats.tsctfc += 3331 E1000_READ_REG(&sc->hw, TSCTFC); 3332 } 3333 #endif 3334 3335 /* Fill out the OS statistics structure */ 3336 ifp->if_collisions = sc->stats.colc; 3337 3338 /* Rx Errors */ 3339 ifp->if_ierrors = 3340 sc->dropped_pkts + 3341 sc->stats.rxerrc + 3342 sc->stats.crcerrs + 3343 sc->stats.algnerrc + 3344 sc->stats.ruc + sc->stats.roc + 3345 sc->stats.mpc + sc->stats.cexterr + 3346 sc->rx_overruns; 3347 3348 /* Tx Errors */ 3349 ifp->if_oerrors = sc->stats.ecol + sc->stats.latecol + 3350 sc->watchdog_events; 3351 } 3352 3353 #ifdef EM_DEBUG 3354 /********************************************************************** 3355 * 3356 * This routine is called only when IFF_DEBUG is enabled. 3357 * This routine provides a way to take a look at important statistics 3358 * maintained by the driver and hardware. 3359 * 3360 **********************************************************************/ 3361 void 3362 em_print_hw_stats(struct em_softc *sc) 3363 { 3364 const char * const unit = DEVNAME(sc); 3365 3366 printf("%s: Excessive collisions = %lld\n", unit, 3367 (long long)sc->stats.ecol); 3368 printf("%s: Symbol errors = %lld\n", unit, 3369 (long long)sc->stats.symerrs); 3370 printf("%s: Sequence errors = %lld\n", unit, 3371 (long long)sc->stats.sec); 3372 printf("%s: Defer count = %lld\n", unit, 3373 (long long)sc->stats.dc); 3374 3375 printf("%s: Missed Packets = %lld\n", unit, 3376 (long long)sc->stats.mpc); 3377 printf("%s: Receive No Buffers = %lld\n", unit, 3378 (long long)sc->stats.rnbc); 3379 /* RLEC is inaccurate on some hardware, calculate our own */ 3380 printf("%s: Receive Length Errors = %lld\n", unit, 3381 ((long long)sc->stats.roc + 3382 (long long)sc->stats.ruc)); 3383 printf("%s: Receive errors = %lld\n", unit, 3384 (long long)sc->stats.rxerrc); 3385 printf("%s: Crc errors = %lld\n", unit, 3386 (long long)sc->stats.crcerrs); 3387 printf("%s: Alignment errors = %lld\n", unit, 3388 (long long)sc->stats.algnerrc); 3389 printf("%s: Carrier extension errors = %lld\n", unit, 3390 (long long)sc->stats.cexterr); 3391 3392 printf("%s: RX overruns = %ld\n", unit, 3393 sc->rx_overruns); 3394 printf("%s: watchdog timeouts = %ld\n", unit, 3395 sc->watchdog_events); 3396 3397 printf("%s: XON Rcvd = %lld\n", unit, 3398 (long long)sc->stats.xonrxc); 3399 printf("%s: XON Xmtd = %lld\n", unit, 3400 (long long)sc->stats.xontxc); 3401 printf("%s: XOFF Rcvd = %lld\n", unit, 3402 (long long)sc->stats.xoffrxc); 3403 printf("%s: XOFF Xmtd = %lld\n", unit, 3404 (long long)sc->stats.xofftxc); 3405 3406 printf("%s: Good Packets Rcvd = %lld\n", unit, 3407 (long long)sc->stats.gprc); 3408 printf("%s: Good Packets Xmtd = %lld\n", unit, 3409 (long long)sc->stats.gptc); 3410 } 3411 #endif 3412 #endif /* !SMALL_KERNEL */ 3413