1 /************************************************************************** 2 3 Copyright (c) 2001-2003, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ***************************************************************************/ 33 34 /* $OpenBSD: if_em.c,v 1.339 2018/03/16 06:30:50 jsg Exp $ */ 35 /* $FreeBSD: if_em.c,v 1.46 2004/09/29 18:28:28 mlaier Exp $ */ 36 37 #include <dev/pci/if_em.h> 38 #include <dev/pci/if_em_soc.h> 39 40 /********************************************************************* 41 * Driver version 42 *********************************************************************/ 43 44 #define EM_DRIVER_VERSION "6.2.9" 45 46 /********************************************************************* 47 * PCI Device ID Table 48 *********************************************************************/ 49 const struct pci_matchid em_devices[] = { 50 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80003ES2LAN_CPR_DPT }, 51 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80003ES2LAN_SDS_DPT }, 52 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80003ES2LAN_CPR_SPT }, 53 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80003ES2LAN_SDS_SPT }, 54 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM }, 55 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM_LOM }, 56 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP }, 57 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LOM }, 58 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LP }, 59 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI }, 60 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI_MOBILE }, 61 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541ER }, 62 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541ER_LOM }, 63 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI }, 64 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI_LF }, 65 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI_MOBILE }, 66 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82542 }, 67 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_COPPER }, 68 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_FIBER }, 69 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_COPPER }, 70 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_FIBER }, 71 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_COPPER }, 72 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_LOM }, 73 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_COPPER }, 74 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_FIBER }, 75 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_COPPER }, 76 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_FIBER }, 77 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_SERDES }, 78 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_COPPER }, 79 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_FIBER }, 80 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_QUAD_CPR }, 81 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_COPPER }, 82 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_FIBER }, 83 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_PCIE }, 84 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_QUAD_CPR }, 85 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_QUAD_CPR_K }, 86 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_SERDES }, 87 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_2 }, 88 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547EI }, 89 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547EI_MOBILE }, 90 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547GI }, 91 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_AF }, 92 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_AT }, 93 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_COPPER }, 94 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_FIBER }, 95 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_QUAD_CPR }, 96 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_QUAD_CPR_LP }, 97 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_QUAD_FBR }, 98 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_SERDES }, 99 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_SDS_DUAL }, 100 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_SDS_QUAD }, 101 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571PT_QUAD_CPR }, 102 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI_COPPER }, 103 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI_FIBER }, 104 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI_SERDES }, 105 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI }, 106 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573E }, 107 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573E_IAMT }, 108 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573E_PM }, 109 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573L }, 110 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573L_PL_1 }, 111 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573L_PL_2 }, 112 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573V_PM }, 113 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82574L }, 114 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82574LA }, 115 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82575EB_COPPER }, 116 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82575EB_SERDES }, 117 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82575GB_QUAD_CPR }, 118 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82575GB_QP_PM }, 119 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576 }, 120 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_FIBER }, 121 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_SERDES }, 122 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_QUAD_COPPER }, 123 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_QUAD_CU_ET2 }, 124 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_NS }, 125 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_NS_SERDES }, 126 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_SERDES_QUAD }, 127 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82577LC }, 128 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82577LM }, 129 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82578DC }, 130 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82578DM }, 131 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82579LM }, 132 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82579V }, 133 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_COPPER }, 134 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_COPPER_OEM1 }, 135 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_COPPER_IT }, 136 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_FIBER }, 137 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_SERDES }, 138 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_SGMII }, 139 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_COPPER_NF }, 140 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_SERDES_NF }, 141 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I211_COPPER }, 142 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I217_LM }, 143 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I217_V }, 144 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_LM }, 145 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_LM_2 }, 146 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_LM_3 }, 147 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_V }, 148 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_V_2 }, 149 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_V_3 }, 150 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_LM }, 151 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_LM2 }, 152 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_LM3 }, 153 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_LM4 }, 154 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_LM5 }, 155 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_LM6 }, 156 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_LM7 }, 157 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_LM8 }, 158 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_LM9 }, 159 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_V }, 160 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_V2 }, 161 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_V4 }, 162 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_V5 }, 163 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_V6 }, 164 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_V7 }, 165 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_V8 }, 166 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_V9 }, 167 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_COPPER }, 168 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_FIBER }, 169 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_SERDES }, 170 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_SGMII }, 171 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_COPPER_DUAL }, 172 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_QUAD_FIBER }, 173 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCC_SGMII }, 174 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCC_SERDES }, 175 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCC_BPLANE }, 176 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCC_SFP }, 177 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82583V }, 178 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I350_COPPER }, 179 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I350_FIBER }, 180 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I350_SERDES }, 181 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I350_SGMII }, 182 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I354_BP_1GBPS }, 183 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I354_BP_2_5GBPS }, 184 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I354_SGMII }, 185 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_82567V_3 }, 186 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_IFE }, 187 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_IFE_G }, 188 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_IFE_GT }, 189 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_IGP_AMT }, 190 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_IGP_C }, 191 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_IGP_M }, 192 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_IGP_M_AMT }, 193 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_BM }, 194 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IFE }, 195 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IFE_G }, 196 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IFE_GT }, 197 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IGP_AMT }, 198 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IGP_C }, 199 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IGP_M }, 200 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IGP_M_AMT }, 201 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IGP_M_V }, 202 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH10_D_BM_LF }, 203 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH10_D_BM_LM }, 204 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH10_D_BM_V }, 205 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH10_R_BM_LF }, 206 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH10_R_BM_LM }, 207 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH10_R_BM_V }, 208 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EP80579_LAN_1 }, 209 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EP80579_LAN_2 }, 210 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EP80579_LAN_3 }, 211 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EP80579_LAN_4 }, 212 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EP80579_LAN_5 }, 213 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EP80579_LAN_6 } 214 }; 215 216 /********************************************************************* 217 * Function prototypes 218 *********************************************************************/ 219 int em_probe(struct device *, void *, void *); 220 void em_attach(struct device *, struct device *, void *); 221 void em_defer_attach(struct device*); 222 int em_detach(struct device *, int); 223 int em_activate(struct device *, int); 224 int em_intr(void *); 225 void em_start(struct ifqueue *); 226 int em_ioctl(struct ifnet *, u_long, caddr_t); 227 void em_watchdog(struct ifnet *); 228 void em_init(void *); 229 void em_stop(void *, int); 230 void em_media_status(struct ifnet *, struct ifmediareq *); 231 int em_media_change(struct ifnet *); 232 uint64_t em_flowstatus(struct em_softc *); 233 void em_identify_hardware(struct em_softc *); 234 int em_allocate_pci_resources(struct em_softc *); 235 void em_free_pci_resources(struct em_softc *); 236 void em_local_timer(void *); 237 int em_hardware_init(struct em_softc *); 238 void em_setup_interface(struct em_softc *); 239 int em_setup_transmit_structures(struct em_softc *); 240 void em_initialize_transmit_unit(struct em_softc *); 241 int em_setup_receive_structures(struct em_softc *); 242 void em_initialize_receive_unit(struct em_softc *); 243 void em_enable_intr(struct em_softc *); 244 void em_disable_intr(struct em_softc *); 245 void em_free_transmit_structures(struct em_softc *); 246 void em_free_receive_structures(struct em_softc *); 247 void em_update_stats_counters(struct em_softc *); 248 void em_disable_aspm(struct em_softc *); 249 void em_txeof(struct em_softc *); 250 int em_allocate_receive_structures(struct em_softc *); 251 int em_allocate_transmit_structures(struct em_softc *); 252 int em_rxfill(struct em_softc *); 253 int em_rxeof(struct em_softc *); 254 void em_receive_checksum(struct em_softc *, struct em_rx_desc *, 255 struct mbuf *); 256 u_int em_transmit_checksum_setup(struct em_softc *, struct mbuf *, u_int, 257 u_int32_t *, u_int32_t *); 258 void em_iff(struct em_softc *); 259 #ifdef EM_DEBUG 260 void em_print_hw_stats(struct em_softc *); 261 #endif 262 void em_update_link_status(struct em_softc *); 263 int em_get_buf(struct em_softc *, int); 264 void em_enable_hw_vlans(struct em_softc *); 265 u_int em_encap(struct em_softc *, struct mbuf *); 266 void em_smartspeed(struct em_softc *); 267 int em_82547_fifo_workaround(struct em_softc *, int); 268 void em_82547_update_fifo_head(struct em_softc *, int); 269 int em_82547_tx_fifo_reset(struct em_softc *); 270 void em_82547_move_tail(void *arg); 271 void em_82547_move_tail_locked(struct em_softc *); 272 int em_dma_malloc(struct em_softc *, bus_size_t, struct em_dma_alloc *); 273 void em_dma_free(struct em_softc *, struct em_dma_alloc *); 274 u_int32_t em_fill_descriptors(u_int64_t address, u_int32_t length, 275 PDESC_ARRAY desc_array); 276 void em_flush_tx_ring(struct em_softc *); 277 void em_flush_rx_ring(struct em_softc *); 278 void em_flush_desc_rings(struct em_softc *); 279 280 /********************************************************************* 281 * OpenBSD Device Interface Entry Points 282 *********************************************************************/ 283 284 struct cfattach em_ca = { 285 sizeof(struct em_softc), em_probe, em_attach, em_detach, 286 em_activate 287 }; 288 289 struct cfdriver em_cd = { 290 NULL, "em", DV_IFNET 291 }; 292 293 static int em_smart_pwr_down = FALSE; 294 295 /********************************************************************* 296 * Device identification routine 297 * 298 * em_probe determines if the driver should be loaded on 299 * adapter based on PCI vendor/device id of the adapter. 300 * 301 * return 0 on no match, positive on match 302 *********************************************************************/ 303 304 int 305 em_probe(struct device *parent, void *match, void *aux) 306 { 307 INIT_DEBUGOUT("em_probe: begin"); 308 309 return (pci_matchbyid((struct pci_attach_args *)aux, em_devices, 310 nitems(em_devices))); 311 } 312 313 void 314 em_defer_attach(struct device *self) 315 { 316 struct em_softc *sc = (struct em_softc *)self; 317 struct pci_attach_args *pa = &sc->osdep.em_pa; 318 pci_chipset_tag_t pc = pa->pa_pc; 319 void *gcu; 320 321 INIT_DEBUGOUT("em_defer_attach: begin"); 322 323 if ((gcu = em_lookup_gcu(self)) == 0) { 324 printf("%s: No GCU found, defered attachment failed\n", 325 DEVNAME(sc)); 326 327 if (sc->sc_intrhand) 328 pci_intr_disestablish(pc, sc->sc_intrhand); 329 sc->sc_intrhand = 0; 330 331 em_stop(sc, 1); 332 333 em_free_pci_resources(sc); 334 335 sc->sc_rx_desc_ring = NULL; 336 em_dma_free(sc, &sc->sc_rx_dma); 337 sc->sc_tx_desc_ring = NULL; 338 em_dma_free(sc, &sc->sc_tx_dma); 339 340 return; 341 } 342 343 sc->hw.gcu = gcu; 344 345 em_attach_miibus(self); 346 347 em_setup_interface(sc); 348 349 em_setup_link(&sc->hw); 350 351 em_update_link_status(sc); 352 } 353 354 /********************************************************************* 355 * Device initialization routine 356 * 357 * The attach entry point is called when the driver is being loaded. 358 * This routine identifies the type of hardware, allocates all resources 359 * and initializes the hardware. 360 * 361 *********************************************************************/ 362 363 void 364 em_attach(struct device *parent, struct device *self, void *aux) 365 { 366 struct pci_attach_args *pa = aux; 367 struct em_softc *sc; 368 int defer = 0; 369 370 INIT_DEBUGOUT("em_attach: begin"); 371 372 sc = (struct em_softc *)self; 373 sc->sc_dmat = pa->pa_dmat; 374 sc->osdep.em_pa = *pa; 375 376 timeout_set(&sc->timer_handle, em_local_timer, sc); 377 timeout_set(&sc->tx_fifo_timer_handle, em_82547_move_tail, sc); 378 379 /* Determine hardware revision */ 380 em_identify_hardware(sc); 381 382 /* 383 * Only use MSI on the newer PCIe parts, with the exception 384 * of 82571/82572 due to "Byte Enables 2 and 3 Are Not Set" errata 385 */ 386 if (sc->hw.mac_type <= em_82572) 387 sc->osdep.em_pa.pa_flags &= ~PCI_FLAGS_MSI_ENABLED; 388 389 /* Parameters (to be read from user) */ 390 if (sc->hw.mac_type >= em_82544) { 391 sc->sc_tx_slots = EM_MAX_TXD; 392 sc->sc_rx_slots = EM_MAX_RXD; 393 } else { 394 sc->sc_tx_slots = EM_MAX_TXD_82543; 395 sc->sc_rx_slots = EM_MAX_RXD_82543; 396 } 397 sc->tx_int_delay = EM_TIDV; 398 sc->tx_abs_int_delay = EM_TADV; 399 sc->rx_int_delay = EM_RDTR; 400 sc->rx_abs_int_delay = EM_RADV; 401 sc->hw.autoneg = DO_AUTO_NEG; 402 sc->hw.wait_autoneg_complete = WAIT_FOR_AUTO_NEG_DEFAULT; 403 sc->hw.autoneg_advertised = AUTONEG_ADV_DEFAULT; 404 sc->hw.tbi_compatibility_en = TRUE; 405 sc->sc_rx_buffer_len = EM_RXBUFFER_2048; 406 407 sc->hw.phy_init_script = 1; 408 sc->hw.phy_reset_disable = FALSE; 409 410 #ifndef EM_MASTER_SLAVE 411 sc->hw.master_slave = em_ms_hw_default; 412 #else 413 sc->hw.master_slave = EM_MASTER_SLAVE; 414 #endif 415 416 /* 417 * This controls when hardware reports transmit completion 418 * status. 419 */ 420 sc->hw.report_tx_early = 1; 421 422 if (em_allocate_pci_resources(sc)) 423 goto err_pci; 424 425 /* Initialize eeprom parameters */ 426 em_init_eeprom_params(&sc->hw); 427 428 /* 429 * Set the max frame size assuming standard Ethernet 430 * sized frames. 431 */ 432 switch (sc->hw.mac_type) { 433 case em_82573: 434 { 435 uint16_t eeprom_data = 0; 436 437 /* 438 * 82573 only supports Jumbo frames 439 * if ASPM is disabled. 440 */ 441 em_read_eeprom(&sc->hw, EEPROM_INIT_3GIO_3, 442 1, &eeprom_data); 443 if (eeprom_data & EEPROM_WORD1A_ASPM_MASK) { 444 sc->hw.max_frame_size = ETHER_MAX_LEN; 445 break; 446 } 447 /* Allow Jumbo frames */ 448 /* FALLTHROUGH */ 449 } 450 case em_82571: 451 case em_82572: 452 case em_82574: 453 case em_82575: 454 case em_82580: 455 case em_i210: 456 case em_i350: 457 case em_ich9lan: 458 case em_ich10lan: 459 case em_pch2lan: 460 case em_pch_lpt: 461 case em_pch_spt: 462 case em_pch_cnp: 463 case em_80003es2lan: 464 /* 9K Jumbo Frame size */ 465 sc->hw.max_frame_size = 9234; 466 break; 467 case em_pchlan: 468 sc->hw.max_frame_size = 4096; 469 break; 470 case em_82542_rev2_0: 471 case em_82542_rev2_1: 472 case em_ich8lan: 473 /* Adapters that do not support Jumbo frames */ 474 sc->hw.max_frame_size = ETHER_MAX_LEN; 475 break; 476 default: 477 sc->hw.max_frame_size = 478 MAX_JUMBO_FRAME_SIZE; 479 } 480 481 sc->hw.min_frame_size = 482 ETHER_MIN_LEN + ETHER_CRC_LEN; 483 484 /* Allocate Transmit Descriptor ring */ 485 if (em_dma_malloc(sc, sc->sc_tx_slots * sizeof(struct em_tx_desc), 486 &sc->sc_tx_dma) != 0) { 487 printf("%s: Unable to allocate tx_desc memory\n", 488 DEVNAME(sc)); 489 goto err_tx_desc; 490 } 491 sc->sc_tx_desc_ring = (struct em_tx_desc *)sc->sc_tx_dma.dma_vaddr; 492 493 /* Allocate Receive Descriptor ring */ 494 if (em_dma_malloc(sc, sc->sc_rx_slots * sizeof(struct em_rx_desc), 495 &sc->sc_rx_dma) != 0) { 496 printf("%s: Unable to allocate rx_desc memory\n", 497 DEVNAME(sc)); 498 goto err_rx_desc; 499 } 500 sc->sc_rx_desc_ring = (struct em_rx_desc *)sc->sc_rx_dma.dma_vaddr; 501 502 /* Initialize the hardware */ 503 if ((defer = em_hardware_init(sc))) { 504 if (defer == EAGAIN) 505 config_defer(self, em_defer_attach); 506 else { 507 printf("%s: Unable to initialize the hardware\n", 508 DEVNAME(sc)); 509 goto err_hw_init; 510 } 511 } 512 513 if (sc->hw.mac_type == em_80003es2lan || sc->hw.mac_type == em_82575 || 514 sc->hw.mac_type == em_82580 || sc->hw.mac_type == em_i210 || 515 sc->hw.mac_type == em_i350) { 516 uint32_t reg = EM_READ_REG(&sc->hw, E1000_STATUS); 517 sc->hw.bus_func = (reg & E1000_STATUS_FUNC_MASK) >> 518 E1000_STATUS_FUNC_SHIFT; 519 520 switch (sc->hw.bus_func) { 521 case 0: 522 sc->hw.swfw = E1000_SWFW_PHY0_SM; 523 break; 524 case 1: 525 sc->hw.swfw = E1000_SWFW_PHY1_SM; 526 break; 527 case 2: 528 sc->hw.swfw = E1000_SWFW_PHY2_SM; 529 break; 530 case 3: 531 sc->hw.swfw = E1000_SWFW_PHY3_SM; 532 break; 533 } 534 } else { 535 sc->hw.bus_func = 0; 536 } 537 538 /* Copy the permanent MAC address out of the EEPROM */ 539 if (em_read_mac_addr(&sc->hw) < 0) { 540 printf("%s: EEPROM read error while reading mac address\n", 541 DEVNAME(sc)); 542 goto err_mac_addr; 543 } 544 545 bcopy(sc->hw.mac_addr, sc->sc_ac.ac_enaddr, ETHER_ADDR_LEN); 546 547 /* Setup OS specific network interface */ 548 if (!defer) 549 em_setup_interface(sc); 550 551 /* Initialize statistics */ 552 em_clear_hw_cntrs(&sc->hw); 553 #ifndef SMALL_KERNEL 554 em_update_stats_counters(sc); 555 #endif 556 sc->hw.get_link_status = 1; 557 if (!defer) 558 em_update_link_status(sc); 559 560 printf(", address %s\n", ether_sprintf(sc->sc_ac.ac_enaddr)); 561 562 /* Indicate SOL/IDER usage */ 563 if (em_check_phy_reset_block(&sc->hw)) 564 printf("%s: PHY reset is blocked due to SOL/IDER session.\n", 565 DEVNAME(sc)); 566 567 /* Identify 82544 on PCI-X */ 568 em_get_bus_info(&sc->hw); 569 if (sc->hw.bus_type == em_bus_type_pcix && 570 sc->hw.mac_type == em_82544) 571 sc->pcix_82544 = TRUE; 572 else 573 sc->pcix_82544 = FALSE; 574 575 sc->hw.icp_xxxx_is_link_up = FALSE; 576 577 INIT_DEBUGOUT("em_attach: end"); 578 return; 579 580 err_mac_addr: 581 err_hw_init: 582 sc->sc_rx_desc_ring = NULL; 583 em_dma_free(sc, &sc->sc_rx_dma); 584 err_rx_desc: 585 sc->sc_tx_desc_ring = NULL; 586 em_dma_free(sc, &sc->sc_tx_dma); 587 err_tx_desc: 588 err_pci: 589 em_free_pci_resources(sc); 590 } 591 592 /********************************************************************* 593 * Transmit entry point 594 * 595 * em_start is called by the stack to initiate a transmit. 596 * The driver will remain in this routine as long as there are 597 * packets to transmit and transmit resources are available. 598 * In case resources are not available stack is notified and 599 * the packet is requeued. 600 **********************************************************************/ 601 602 void 603 em_start(struct ifqueue *ifq) 604 { 605 struct ifnet *ifp = ifq->ifq_if; 606 struct em_softc *sc = ifp->if_softc; 607 u_int head, free, used; 608 struct mbuf *m; 609 int post = 0; 610 611 if (!sc->link_active) { 612 ifq_purge(ifq); 613 return; 614 } 615 616 /* calculate free space */ 617 head = sc->sc_tx_desc_head; 618 free = sc->sc_tx_desc_tail; 619 if (free <= head) 620 free += sc->sc_tx_slots; 621 free -= head; 622 623 if (sc->hw.mac_type != em_82547) { 624 bus_dmamap_sync(sc->sc_dmat, sc->sc_tx_dma.dma_map, 625 0, sc->sc_tx_dma.dma_map->dm_mapsize, 626 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 627 } 628 629 for (;;) { 630 /* use 2 because cksum setup can use an extra slot */ 631 if (EM_MAX_SCATTER + 2 > free) { 632 ifq_set_oactive(ifq); 633 break; 634 } 635 636 m = ifq_dequeue(ifq); 637 if (m == NULL) 638 break; 639 640 used = em_encap(sc, m); 641 if (used == 0) { 642 m_freem(m); 643 continue; 644 } 645 646 KASSERT(used <= free); 647 648 free -= used; 649 650 #if NBPFILTER > 0 651 /* Send a copy of the frame to the BPF listener */ 652 if (ifp->if_bpf) 653 bpf_mtap_ether(ifp->if_bpf, m, BPF_DIRECTION_OUT); 654 #endif 655 656 /* Set timeout in case hardware has problems transmitting */ 657 ifp->if_timer = EM_TX_TIMEOUT; 658 659 if (sc->hw.mac_type == em_82547) { 660 int len = m->m_pkthdr.len; 661 662 if (sc->link_duplex == HALF_DUPLEX) 663 em_82547_move_tail_locked(sc); 664 else { 665 E1000_WRITE_REG(&sc->hw, TDT, 666 sc->sc_tx_desc_head); 667 em_82547_update_fifo_head(sc, len); 668 } 669 } 670 671 post = 1; 672 } 673 674 if (sc->hw.mac_type != em_82547) { 675 bus_dmamap_sync(sc->sc_dmat, sc->sc_tx_dma.dma_map, 676 0, sc->sc_tx_dma.dma_map->dm_mapsize, 677 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 678 /* 679 * Advance the Transmit Descriptor Tail (Tdt), 680 * this tells the E1000 that this frame is 681 * available to transmit. 682 */ 683 if (post) 684 E1000_WRITE_REG(&sc->hw, TDT, sc->sc_tx_desc_head); 685 } 686 } 687 688 /********************************************************************* 689 * Ioctl entry point 690 * 691 * em_ioctl is called when the user wants to configure the 692 * interface. 693 * 694 * return 0 on success, positive on failure 695 **********************************************************************/ 696 697 int 698 em_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 699 { 700 int error = 0; 701 struct ifreq *ifr = (struct ifreq *) data; 702 struct em_softc *sc = ifp->if_softc; 703 int s; 704 705 s = splnet(); 706 707 switch (command) { 708 case SIOCSIFADDR: 709 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFADDR (Set Interface " 710 "Addr)"); 711 if (!(ifp->if_flags & IFF_UP)) { 712 ifp->if_flags |= IFF_UP; 713 em_init(sc); 714 } 715 break; 716 717 case SIOCSIFFLAGS: 718 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFFLAGS (Set Interface Flags)"); 719 if (ifp->if_flags & IFF_UP) { 720 if (ifp->if_flags & IFF_RUNNING) 721 error = ENETRESET; 722 else 723 em_init(sc); 724 } else { 725 if (ifp->if_flags & IFF_RUNNING) 726 em_stop(sc, 0); 727 } 728 break; 729 730 case SIOCSIFMEDIA: 731 /* Check SOL/IDER usage */ 732 if (em_check_phy_reset_block(&sc->hw)) { 733 printf("%s: Media change is blocked due to SOL/IDER session.\n", 734 DEVNAME(sc)); 735 break; 736 } 737 case SIOCGIFMEDIA: 738 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCxIFMEDIA (Get/Set Interface Media)"); 739 error = ifmedia_ioctl(ifp, ifr, &sc->media, command); 740 break; 741 742 case SIOCGIFRXR: 743 error = if_rxr_ioctl((struct if_rxrinfo *)ifr->ifr_data, 744 NULL, EM_MCLBYTES, &sc->sc_rx_ring); 745 break; 746 747 default: 748 error = ether_ioctl(ifp, &sc->sc_ac, command, data); 749 } 750 751 if (error == ENETRESET) { 752 if (ifp->if_flags & IFF_RUNNING) { 753 em_disable_intr(sc); 754 em_iff(sc); 755 if (sc->hw.mac_type == em_82542_rev2_0) 756 em_initialize_receive_unit(sc); 757 em_enable_intr(sc); 758 } 759 error = 0; 760 } 761 762 splx(s); 763 return (error); 764 } 765 766 /********************************************************************* 767 * Watchdog entry point 768 * 769 * This routine is called whenever hardware quits transmitting. 770 * 771 **********************************************************************/ 772 773 void 774 em_watchdog(struct ifnet *ifp) 775 { 776 struct em_softc *sc = ifp->if_softc; 777 778 /* If we are in this routine because of pause frames, then 779 * don't reset the hardware. 780 */ 781 if (E1000_READ_REG(&sc->hw, STATUS) & E1000_STATUS_TXOFF) { 782 ifp->if_timer = EM_TX_TIMEOUT; 783 return; 784 } 785 printf("%s: watchdog: head %u tail %u TDH %u TDT %u\n", 786 DEVNAME(sc), 787 sc->sc_tx_desc_head, sc->sc_tx_desc_tail, 788 E1000_READ_REG(&sc->hw, TDH), E1000_READ_REG(&sc->hw, TDT)); 789 790 em_init(sc); 791 792 sc->watchdog_events++; 793 } 794 795 /********************************************************************* 796 * Init entry point 797 * 798 * This routine is used in two ways. It is used by the stack as 799 * init entry point in network interface structure. It is also used 800 * by the driver as a hw/sw initialization routine to get to a 801 * consistent state. 802 * 803 **********************************************************************/ 804 805 void 806 em_init(void *arg) 807 { 808 struct em_softc *sc = arg; 809 struct ifnet *ifp = &sc->sc_ac.ac_if; 810 uint32_t pba; 811 int s; 812 813 s = splnet(); 814 815 INIT_DEBUGOUT("em_init: begin"); 816 817 em_stop(sc, 0); 818 819 /* 820 * Packet Buffer Allocation (PBA) 821 * Writing PBA sets the receive portion of the buffer 822 * the remainder is used for the transmit buffer. 823 * 824 * Devices before the 82547 had a Packet Buffer of 64K. 825 * Default allocation: PBA=48K for Rx, leaving 16K for Tx. 826 * After the 82547 the buffer was reduced to 40K. 827 * Default allocation: PBA=30K for Rx, leaving 10K for Tx. 828 * Note: default does not leave enough room for Jumbo Frame >10k. 829 */ 830 switch (sc->hw.mac_type) { 831 case em_82547: 832 case em_82547_rev_2: /* 82547: Total Packet Buffer is 40K */ 833 if (sc->hw.max_frame_size > EM_RXBUFFER_8192) 834 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 835 else 836 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 837 sc->tx_fifo_head = 0; 838 sc->tx_head_addr = pba << EM_TX_HEAD_ADDR_SHIFT; 839 sc->tx_fifo_size = (E1000_PBA_40K - pba) << EM_PBA_BYTES_SHIFT; 840 break; 841 case em_82571: 842 case em_82572: /* Total Packet Buffer on these is 48k */ 843 case em_82575: 844 case em_82580: 845 case em_80003es2lan: 846 case em_i350: 847 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 848 break; 849 case em_i210: 850 pba = E1000_PBA_34K; 851 break; 852 case em_82573: /* 82573: Total Packet Buffer is 32K */ 853 /* Jumbo frames not supported */ 854 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 855 break; 856 case em_82574: /* Total Packet Buffer is 40k */ 857 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */ 858 break; 859 case em_ich8lan: 860 pba = E1000_PBA_8K; 861 break; 862 case em_ich9lan: 863 case em_ich10lan: 864 /* Boost Receive side for jumbo frames */ 865 if (sc->hw.max_frame_size > EM_RXBUFFER_4096) 866 pba = E1000_PBA_14K; 867 else 868 pba = E1000_PBA_10K; 869 break; 870 case em_pchlan: 871 case em_pch2lan: 872 case em_pch_lpt: 873 case em_pch_spt: 874 case em_pch_cnp: 875 pba = E1000_PBA_26K; 876 break; 877 default: 878 /* Devices before 82547 had a Packet Buffer of 64K. */ 879 if (sc->hw.max_frame_size > EM_RXBUFFER_8192) 880 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 881 else 882 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 883 } 884 INIT_DEBUGOUT1("em_init: pba=%dK",pba); 885 E1000_WRITE_REG(&sc->hw, PBA, pba); 886 887 /* Get the latest mac address, User can use a LAA */ 888 bcopy(sc->sc_ac.ac_enaddr, sc->hw.mac_addr, ETHER_ADDR_LEN); 889 890 /* Initialize the hardware */ 891 if (em_hardware_init(sc)) { 892 printf("%s: Unable to initialize the hardware\n", 893 DEVNAME(sc)); 894 splx(s); 895 return; 896 } 897 em_update_link_status(sc); 898 899 E1000_WRITE_REG(&sc->hw, VET, ETHERTYPE_VLAN); 900 if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) 901 em_enable_hw_vlans(sc); 902 903 /* Prepare transmit descriptors and buffers */ 904 if (em_setup_transmit_structures(sc)) { 905 printf("%s: Could not setup transmit structures\n", 906 DEVNAME(sc)); 907 em_stop(sc, 0); 908 splx(s); 909 return; 910 } 911 em_initialize_transmit_unit(sc); 912 913 /* Prepare receive descriptors and buffers */ 914 if (em_setup_receive_structures(sc)) { 915 printf("%s: Could not setup receive structures\n", 916 DEVNAME(sc)); 917 em_stop(sc, 0); 918 splx(s); 919 return; 920 } 921 em_initialize_receive_unit(sc); 922 923 /* Program promiscuous mode and multicast filters. */ 924 em_iff(sc); 925 926 ifp->if_flags |= IFF_RUNNING; 927 ifq_clr_oactive(&ifp->if_snd); 928 929 timeout_add_sec(&sc->timer_handle, 1); 930 em_clear_hw_cntrs(&sc->hw); 931 em_enable_intr(sc); 932 933 /* Don't reset the phy next time init gets called */ 934 sc->hw.phy_reset_disable = TRUE; 935 936 splx(s); 937 } 938 939 /********************************************************************* 940 * 941 * Interrupt Service routine 942 * 943 **********************************************************************/ 944 int 945 em_intr(void *arg) 946 { 947 struct em_softc *sc = arg; 948 struct ifnet *ifp = &sc->sc_ac.ac_if; 949 u_int32_t reg_icr, test_icr; 950 951 test_icr = reg_icr = E1000_READ_REG(&sc->hw, ICR); 952 if (sc->hw.mac_type >= em_82571) 953 test_icr = (reg_icr & E1000_ICR_INT_ASSERTED); 954 if (!test_icr) 955 return (0); 956 957 if (ifp->if_flags & IFF_RUNNING) { 958 em_txeof(sc); 959 960 if (em_rxeof(sc) || ISSET(reg_icr, E1000_ICR_RXO)) { 961 if (em_rxfill(sc)) { 962 E1000_WRITE_REG(&sc->hw, RDT, 963 sc->sc_rx_desc_head); 964 } 965 } 966 } 967 968 /* Link status change */ 969 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 970 KERNEL_LOCK(); 971 sc->hw.get_link_status = 1; 972 em_check_for_link(&sc->hw); 973 em_update_link_status(sc); 974 KERNEL_UNLOCK(); 975 } 976 977 return (1); 978 } 979 980 /********************************************************************* 981 * 982 * Media Ioctl callback 983 * 984 * This routine is called whenever the user queries the status of 985 * the interface using ifconfig. 986 * 987 **********************************************************************/ 988 void 989 em_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 990 { 991 struct em_softc *sc = ifp->if_softc; 992 uint64_t fiber_type = IFM_1000_SX; 993 u_int16_t gsr; 994 995 INIT_DEBUGOUT("em_media_status: begin"); 996 997 em_check_for_link(&sc->hw); 998 em_update_link_status(sc); 999 1000 ifmr->ifm_status = IFM_AVALID; 1001 ifmr->ifm_active = IFM_ETHER; 1002 1003 if (!sc->link_active) { 1004 ifmr->ifm_active |= IFM_NONE; 1005 return; 1006 } 1007 1008 ifmr->ifm_status |= IFM_ACTIVE; 1009 1010 if (sc->hw.media_type == em_media_type_fiber || 1011 sc->hw.media_type == em_media_type_internal_serdes) { 1012 if (sc->hw.mac_type == em_82545) 1013 fiber_type = IFM_1000_LX; 1014 ifmr->ifm_active |= fiber_type | IFM_FDX; 1015 } else { 1016 switch (sc->link_speed) { 1017 case 10: 1018 ifmr->ifm_active |= IFM_10_T; 1019 break; 1020 case 100: 1021 ifmr->ifm_active |= IFM_100_TX; 1022 break; 1023 case 1000: 1024 ifmr->ifm_active |= IFM_1000_T; 1025 break; 1026 } 1027 1028 if (sc->link_duplex == FULL_DUPLEX) 1029 ifmr->ifm_active |= em_flowstatus(sc) | IFM_FDX; 1030 else 1031 ifmr->ifm_active |= IFM_HDX; 1032 1033 if (IFM_SUBTYPE(ifmr->ifm_active) == IFM_1000_T) { 1034 em_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &gsr); 1035 if (gsr & SR_1000T_MS_CONFIG_RES) 1036 ifmr->ifm_active |= IFM_ETH_MASTER; 1037 } 1038 } 1039 } 1040 1041 /********************************************************************* 1042 * 1043 * Media Ioctl callback 1044 * 1045 * This routine is called when the user changes speed/duplex using 1046 * media/mediopt option with ifconfig. 1047 * 1048 **********************************************************************/ 1049 int 1050 em_media_change(struct ifnet *ifp) 1051 { 1052 struct em_softc *sc = ifp->if_softc; 1053 struct ifmedia *ifm = &sc->media; 1054 1055 INIT_DEBUGOUT("em_media_change: begin"); 1056 1057 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1058 return (EINVAL); 1059 1060 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1061 case IFM_AUTO: 1062 sc->hw.autoneg = DO_AUTO_NEG; 1063 sc->hw.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1064 break; 1065 case IFM_1000_LX: 1066 case IFM_1000_SX: 1067 case IFM_1000_T: 1068 sc->hw.autoneg = DO_AUTO_NEG; 1069 sc->hw.autoneg_advertised = ADVERTISE_1000_FULL; 1070 break; 1071 case IFM_100_TX: 1072 sc->hw.autoneg = FALSE; 1073 sc->hw.autoneg_advertised = 0; 1074 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1075 sc->hw.forced_speed_duplex = em_100_full; 1076 else 1077 sc->hw.forced_speed_duplex = em_100_half; 1078 break; 1079 case IFM_10_T: 1080 sc->hw.autoneg = FALSE; 1081 sc->hw.autoneg_advertised = 0; 1082 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1083 sc->hw.forced_speed_duplex = em_10_full; 1084 else 1085 sc->hw.forced_speed_duplex = em_10_half; 1086 break; 1087 default: 1088 printf("%s: Unsupported media type\n", DEVNAME(sc)); 1089 } 1090 1091 /* 1092 * As the speed/duplex settings may have changed we need to 1093 * reset the PHY. 1094 */ 1095 sc->hw.phy_reset_disable = FALSE; 1096 1097 em_init(sc); 1098 1099 return (0); 1100 } 1101 1102 uint64_t 1103 em_flowstatus(struct em_softc *sc) 1104 { 1105 u_int16_t ar, lpar; 1106 1107 if (sc->hw.media_type == em_media_type_fiber || 1108 sc->hw.media_type == em_media_type_internal_serdes) 1109 return (0); 1110 1111 em_read_phy_reg(&sc->hw, PHY_AUTONEG_ADV, &ar); 1112 em_read_phy_reg(&sc->hw, PHY_LP_ABILITY, &lpar); 1113 1114 if ((ar & NWAY_AR_PAUSE) && (lpar & NWAY_LPAR_PAUSE)) 1115 return (IFM_FLOW|IFM_ETH_TXPAUSE|IFM_ETH_RXPAUSE); 1116 else if (!(ar & NWAY_AR_PAUSE) && (ar & NWAY_AR_ASM_DIR) && 1117 (lpar & NWAY_LPAR_PAUSE) && (lpar & NWAY_LPAR_ASM_DIR)) 1118 return (IFM_FLOW|IFM_ETH_TXPAUSE); 1119 else if ((ar & NWAY_AR_PAUSE) && (ar & NWAY_AR_ASM_DIR) && 1120 !(lpar & NWAY_LPAR_PAUSE) && (lpar & NWAY_LPAR_ASM_DIR)) 1121 return (IFM_FLOW|IFM_ETH_RXPAUSE); 1122 1123 return (0); 1124 } 1125 1126 /********************************************************************* 1127 * 1128 * This routine maps the mbufs to tx descriptors. 1129 * 1130 * return 0 on success, positive on failure 1131 **********************************************************************/ 1132 u_int 1133 em_encap(struct em_softc *sc, struct mbuf *m) 1134 { 1135 struct em_packet *pkt; 1136 struct em_tx_desc *desc; 1137 bus_dmamap_t map; 1138 u_int32_t txd_upper, txd_lower; 1139 u_int head, last, used = 0; 1140 int i, j; 1141 1142 /* For 82544 Workaround */ 1143 DESC_ARRAY desc_array; 1144 u_int32_t array_elements; 1145 1146 /* get a dmamap for this packet from the next free slot */ 1147 head = sc->sc_tx_desc_head; 1148 pkt = &sc->sc_tx_pkts_ring[head]; 1149 map = pkt->pkt_map; 1150 1151 switch (bus_dmamap_load_mbuf(sc->sc_dmat, map, m, BUS_DMA_NOWAIT)) { 1152 case 0: 1153 break; 1154 case EFBIG: 1155 if (m_defrag(m, M_DONTWAIT) == 0 && 1156 bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1157 BUS_DMA_NOWAIT) == 0) 1158 break; 1159 1160 /* FALLTHROUGH */ 1161 default: 1162 sc->no_tx_dma_setup++; 1163 return (0); 1164 } 1165 1166 bus_dmamap_sync(sc->sc_dmat, map, 1167 0, map->dm_mapsize, 1168 BUS_DMASYNC_PREWRITE); 1169 1170 if (sc->hw.mac_type == em_82547) { 1171 bus_dmamap_sync(sc->sc_dmat, sc->sc_tx_dma.dma_map, 1172 0, sc->sc_tx_dma.dma_map->dm_mapsize, 1173 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1174 } 1175 1176 if (sc->hw.mac_type >= em_82543 && sc->hw.mac_type != em_82575 && 1177 sc->hw.mac_type != em_82580 && sc->hw.mac_type != em_i210 && 1178 sc->hw.mac_type != em_i350) { 1179 used += em_transmit_checksum_setup(sc, m, head, 1180 &txd_upper, &txd_lower); 1181 } else { 1182 txd_upper = txd_lower = 0; 1183 } 1184 1185 head += used; 1186 if (head >= sc->sc_tx_slots) 1187 head -= sc->sc_tx_slots; 1188 1189 for (i = 0; i < map->dm_nsegs; i++) { 1190 /* If sc is 82544 and on PCI-X bus */ 1191 if (sc->pcix_82544) { 1192 /* 1193 * Check the Address and Length combination and 1194 * split the data accordingly 1195 */ 1196 array_elements = em_fill_descriptors( 1197 map->dm_segs[i].ds_addr, map->dm_segs[i].ds_len, 1198 &desc_array); 1199 for (j = 0; j < array_elements; j++) { 1200 desc = &sc->sc_tx_desc_ring[head]; 1201 1202 desc->buffer_addr = htole64( 1203 desc_array.descriptor[j].address); 1204 desc->lower.data = htole32( 1205 (sc->sc_txd_cmd | txd_lower | 1206 (u_int16_t)desc_array.descriptor[j].length)); 1207 desc->upper.data = htole32(txd_upper); 1208 1209 last = head; 1210 if (++head == sc->sc_tx_slots) 1211 head = 0; 1212 1213 used++; 1214 } 1215 } else { 1216 desc = &sc->sc_tx_desc_ring[head]; 1217 1218 desc->buffer_addr = htole64(map->dm_segs[i].ds_addr); 1219 desc->lower.data = htole32(sc->sc_txd_cmd | 1220 txd_lower | map->dm_segs[i].ds_len); 1221 desc->upper.data = htole32(txd_upper); 1222 1223 last = head; 1224 if (++head == sc->sc_tx_slots) 1225 head = 0; 1226 1227 used++; 1228 } 1229 } 1230 1231 #if NVLAN > 0 1232 /* Find out if we are in VLAN mode */ 1233 if (m->m_flags & M_VLANTAG) { 1234 /* Set the VLAN id */ 1235 desc->upper.fields.special = htole16(m->m_pkthdr.ether_vtag); 1236 1237 /* Tell hardware to add tag */ 1238 desc->lower.data |= htole32(E1000_TXD_CMD_VLE); 1239 } 1240 #endif 1241 1242 /* mark the packet with the mbuf and last desc slot */ 1243 pkt->pkt_m = m; 1244 pkt->pkt_eop = last; 1245 1246 sc->sc_tx_desc_head = head; 1247 1248 /* 1249 * Last Descriptor of Packet 1250 * needs End Of Packet (EOP) 1251 * and Report Status (RS) 1252 */ 1253 desc->lower.data |= htole32(E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS); 1254 1255 if (sc->hw.mac_type == em_82547) { 1256 bus_dmamap_sync(sc->sc_dmat, sc->sc_tx_dma.dma_map, 1257 0, sc->sc_tx_dma.dma_map->dm_mapsize, 1258 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1259 } 1260 1261 return (used); 1262 } 1263 1264 /********************************************************************* 1265 * 1266 * 82547 workaround to avoid controller hang in half-duplex environment. 1267 * The workaround is to avoid queuing a large packet that would span 1268 * the internal Tx FIFO ring boundary. We need to reset the FIFO pointers 1269 * in this case. We do that only when FIFO is quiescent. 1270 * 1271 **********************************************************************/ 1272 void 1273 em_82547_move_tail_locked(struct em_softc *sc) 1274 { 1275 uint16_t hw_tdt; 1276 uint16_t sw_tdt; 1277 struct em_tx_desc *tx_desc; 1278 uint16_t length = 0; 1279 boolean_t eop = 0; 1280 1281 hw_tdt = E1000_READ_REG(&sc->hw, TDT); 1282 sw_tdt = sc->sc_tx_desc_head; 1283 1284 while (hw_tdt != sw_tdt) { 1285 tx_desc = &sc->sc_tx_desc_ring[hw_tdt]; 1286 length += tx_desc->lower.flags.length; 1287 eop = tx_desc->lower.data & E1000_TXD_CMD_EOP; 1288 if (++hw_tdt == sc->sc_tx_slots) 1289 hw_tdt = 0; 1290 1291 if (eop) { 1292 if (em_82547_fifo_workaround(sc, length)) { 1293 sc->tx_fifo_wrk_cnt++; 1294 timeout_add(&sc->tx_fifo_timer_handle, 1); 1295 break; 1296 } 1297 E1000_WRITE_REG(&sc->hw, TDT, hw_tdt); 1298 em_82547_update_fifo_head(sc, length); 1299 length = 0; 1300 } 1301 } 1302 } 1303 1304 void 1305 em_82547_move_tail(void *arg) 1306 { 1307 struct em_softc *sc = arg; 1308 int s; 1309 1310 s = splnet(); 1311 em_82547_move_tail_locked(sc); 1312 splx(s); 1313 } 1314 1315 int 1316 em_82547_fifo_workaround(struct em_softc *sc, int len) 1317 { 1318 int fifo_space, fifo_pkt_len; 1319 1320 fifo_pkt_len = EM_ROUNDUP(len + EM_FIFO_HDR, EM_FIFO_HDR); 1321 1322 if (sc->link_duplex == HALF_DUPLEX) { 1323 fifo_space = sc->tx_fifo_size - sc->tx_fifo_head; 1324 1325 if (fifo_pkt_len >= (EM_82547_PKT_THRESH + fifo_space)) { 1326 if (em_82547_tx_fifo_reset(sc)) 1327 return (0); 1328 else 1329 return (1); 1330 } 1331 } 1332 1333 return (0); 1334 } 1335 1336 void 1337 em_82547_update_fifo_head(struct em_softc *sc, int len) 1338 { 1339 int fifo_pkt_len = EM_ROUNDUP(len + EM_FIFO_HDR, EM_FIFO_HDR); 1340 1341 /* tx_fifo_head is always 16 byte aligned */ 1342 sc->tx_fifo_head += fifo_pkt_len; 1343 if (sc->tx_fifo_head >= sc->tx_fifo_size) 1344 sc->tx_fifo_head -= sc->tx_fifo_size; 1345 } 1346 1347 int 1348 em_82547_tx_fifo_reset(struct em_softc *sc) 1349 { 1350 uint32_t tctl; 1351 1352 if ((E1000_READ_REG(&sc->hw, TDT) == 1353 E1000_READ_REG(&sc->hw, TDH)) && 1354 (E1000_READ_REG(&sc->hw, TDFT) == 1355 E1000_READ_REG(&sc->hw, TDFH)) && 1356 (E1000_READ_REG(&sc->hw, TDFTS) == 1357 E1000_READ_REG(&sc->hw, TDFHS)) && 1358 (E1000_READ_REG(&sc->hw, TDFPC) == 0)) { 1359 1360 /* Disable TX unit */ 1361 tctl = E1000_READ_REG(&sc->hw, TCTL); 1362 E1000_WRITE_REG(&sc->hw, TCTL, tctl & ~E1000_TCTL_EN); 1363 1364 /* Reset FIFO pointers */ 1365 E1000_WRITE_REG(&sc->hw, TDFT, sc->tx_head_addr); 1366 E1000_WRITE_REG(&sc->hw, TDFH, sc->tx_head_addr); 1367 E1000_WRITE_REG(&sc->hw, TDFTS, sc->tx_head_addr); 1368 E1000_WRITE_REG(&sc->hw, TDFHS, sc->tx_head_addr); 1369 1370 /* Re-enable TX unit */ 1371 E1000_WRITE_REG(&sc->hw, TCTL, tctl); 1372 E1000_WRITE_FLUSH(&sc->hw); 1373 1374 sc->tx_fifo_head = 0; 1375 sc->tx_fifo_reset_cnt++; 1376 1377 return (TRUE); 1378 } else 1379 return (FALSE); 1380 } 1381 1382 void 1383 em_iff(struct em_softc *sc) 1384 { 1385 struct ifnet *ifp = &sc->sc_ac.ac_if; 1386 struct arpcom *ac = &sc->sc_ac; 1387 u_int32_t reg_rctl = 0; 1388 u_int8_t mta[MAX_NUM_MULTICAST_ADDRESSES * ETH_LENGTH_OF_ADDRESS]; 1389 struct ether_multi *enm; 1390 struct ether_multistep step; 1391 int i = 0; 1392 1393 IOCTL_DEBUGOUT("em_iff: begin"); 1394 1395 if (sc->hw.mac_type == em_82542_rev2_0) { 1396 reg_rctl = E1000_READ_REG(&sc->hw, RCTL); 1397 if (sc->hw.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1398 em_pci_clear_mwi(&sc->hw); 1399 reg_rctl |= E1000_RCTL_RST; 1400 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 1401 msec_delay(5); 1402 } 1403 1404 reg_rctl = E1000_READ_REG(&sc->hw, RCTL); 1405 reg_rctl &= ~(E1000_RCTL_MPE | E1000_RCTL_UPE); 1406 ifp->if_flags &= ~IFF_ALLMULTI; 1407 1408 if (ifp->if_flags & IFF_PROMISC || ac->ac_multirangecnt > 0 || 1409 ac->ac_multicnt > MAX_NUM_MULTICAST_ADDRESSES) { 1410 ifp->if_flags |= IFF_ALLMULTI; 1411 reg_rctl |= E1000_RCTL_MPE; 1412 if (ifp->if_flags & IFF_PROMISC) 1413 reg_rctl |= E1000_RCTL_UPE; 1414 } else { 1415 ETHER_FIRST_MULTI(step, ac, enm); 1416 while (enm != NULL) { 1417 bcopy(enm->enm_addrlo, mta + i, ETH_LENGTH_OF_ADDRESS); 1418 i += ETH_LENGTH_OF_ADDRESS; 1419 1420 ETHER_NEXT_MULTI(step, enm); 1421 } 1422 1423 em_mc_addr_list_update(&sc->hw, mta, ac->ac_multicnt, 0, 1); 1424 } 1425 1426 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 1427 1428 if (sc->hw.mac_type == em_82542_rev2_0) { 1429 reg_rctl = E1000_READ_REG(&sc->hw, RCTL); 1430 reg_rctl &= ~E1000_RCTL_RST; 1431 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 1432 msec_delay(5); 1433 if (sc->hw.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1434 em_pci_set_mwi(&sc->hw); 1435 } 1436 } 1437 1438 /********************************************************************* 1439 * Timer routine 1440 * 1441 * This routine checks for link status and updates statistics. 1442 * 1443 **********************************************************************/ 1444 1445 void 1446 em_local_timer(void *arg) 1447 { 1448 struct ifnet *ifp; 1449 struct em_softc *sc = arg; 1450 int s; 1451 1452 ifp = &sc->sc_ac.ac_if; 1453 1454 s = splnet(); 1455 1456 #ifndef SMALL_KERNEL 1457 em_update_stats_counters(sc); 1458 #ifdef EM_DEBUG 1459 if (ifp->if_flags & IFF_DEBUG && ifp->if_flags & IFF_RUNNING) 1460 em_print_hw_stats(sc); 1461 #endif 1462 #endif 1463 em_smartspeed(sc); 1464 1465 timeout_add_sec(&sc->timer_handle, 1); 1466 1467 splx(s); 1468 } 1469 1470 void 1471 em_update_link_status(struct em_softc *sc) 1472 { 1473 struct ifnet *ifp = &sc->sc_ac.ac_if; 1474 u_char link_state; 1475 1476 if (E1000_READ_REG(&sc->hw, STATUS) & E1000_STATUS_LU) { 1477 if (sc->link_active == 0) { 1478 em_get_speed_and_duplex(&sc->hw, 1479 &sc->link_speed, 1480 &sc->link_duplex); 1481 /* Check if we may set SPEED_MODE bit on PCI-E */ 1482 if ((sc->link_speed == SPEED_1000) && 1483 ((sc->hw.mac_type == em_82571) || 1484 (sc->hw.mac_type == em_82572) || 1485 (sc->hw.mac_type == em_82575) || 1486 (sc->hw.mac_type == em_82580))) { 1487 int tarc0; 1488 1489 tarc0 = E1000_READ_REG(&sc->hw, TARC0); 1490 tarc0 |= SPEED_MODE_BIT; 1491 E1000_WRITE_REG(&sc->hw, TARC0, tarc0); 1492 } 1493 sc->link_active = 1; 1494 sc->smartspeed = 0; 1495 ifp->if_baudrate = IF_Mbps(sc->link_speed); 1496 } 1497 link_state = (sc->link_duplex == FULL_DUPLEX) ? 1498 LINK_STATE_FULL_DUPLEX : LINK_STATE_HALF_DUPLEX; 1499 if (ifp->if_link_state != link_state) { 1500 ifp->if_link_state = link_state; 1501 if_link_state_change(ifp); 1502 } 1503 } else { 1504 if (sc->link_active == 1) { 1505 ifp->if_baudrate = sc->link_speed = 0; 1506 sc->link_duplex = 0; 1507 sc->link_active = 0; 1508 } 1509 if (ifp->if_link_state != LINK_STATE_DOWN) { 1510 ifp->if_link_state = LINK_STATE_DOWN; 1511 if_link_state_change(ifp); 1512 } 1513 } 1514 } 1515 1516 /********************************************************************* 1517 * 1518 * This routine disables all traffic on the adapter by issuing a 1519 * global reset on the MAC and deallocates TX/RX buffers. 1520 * 1521 **********************************************************************/ 1522 1523 void 1524 em_stop(void *arg, int softonly) 1525 { 1526 struct em_softc *sc = arg; 1527 struct ifnet *ifp = &sc->sc_ac.ac_if; 1528 1529 /* Tell the stack that the interface is no longer active */ 1530 ifp->if_flags &= ~IFF_RUNNING; 1531 1532 INIT_DEBUGOUT("em_stop: begin"); 1533 1534 timeout_del(&sc->timer_handle); 1535 timeout_del(&sc->tx_fifo_timer_handle); 1536 1537 if (!softonly) 1538 em_disable_intr(sc); 1539 if (sc->hw.mac_type >= em_pch_spt) 1540 em_flush_desc_rings(sc); 1541 if (!softonly) 1542 em_reset_hw(&sc->hw); 1543 1544 intr_barrier(sc->sc_intrhand); 1545 ifq_barrier(&ifp->if_snd); 1546 1547 KASSERT((ifp->if_flags & IFF_RUNNING) == 0); 1548 1549 ifq_clr_oactive(&ifp->if_snd); 1550 ifp->if_timer = 0; 1551 1552 em_free_transmit_structures(sc); 1553 em_free_receive_structures(sc); 1554 } 1555 1556 /********************************************************************* 1557 * 1558 * Determine hardware revision. 1559 * 1560 **********************************************************************/ 1561 void 1562 em_identify_hardware(struct em_softc *sc) 1563 { 1564 u_int32_t reg; 1565 struct pci_attach_args *pa = &sc->osdep.em_pa; 1566 1567 /* Make sure our PCI config space has the necessary stuff set */ 1568 sc->hw.pci_cmd_word = pci_conf_read(pa->pa_pc, pa->pa_tag, 1569 PCI_COMMAND_STATUS_REG); 1570 1571 /* Save off the information about this board */ 1572 sc->hw.vendor_id = PCI_VENDOR(pa->pa_id); 1573 sc->hw.device_id = PCI_PRODUCT(pa->pa_id); 1574 1575 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG); 1576 sc->hw.revision_id = PCI_REVISION(reg); 1577 1578 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 1579 sc->hw.subsystem_vendor_id = PCI_VENDOR(reg); 1580 sc->hw.subsystem_id = PCI_PRODUCT(reg); 1581 1582 /* Identify the MAC */ 1583 if (em_set_mac_type(&sc->hw)) 1584 printf("%s: Unknown MAC Type\n", DEVNAME(sc)); 1585 1586 if (sc->hw.mac_type == em_pchlan) 1587 sc->hw.revision_id = PCI_PRODUCT(pa->pa_id) & 0x0f; 1588 1589 if (sc->hw.mac_type == em_82541 || 1590 sc->hw.mac_type == em_82541_rev_2 || 1591 sc->hw.mac_type == em_82547 || 1592 sc->hw.mac_type == em_82547_rev_2) 1593 sc->hw.phy_init_script = TRUE; 1594 } 1595 1596 void 1597 em_legacy_irq_quirk_spt(struct em_softc *sc) 1598 { 1599 uint32_t reg; 1600 1601 /* Legacy interrupt: SPT needs a quirk. */ 1602 if (sc->hw.mac_type != em_pch_spt && sc->hw.mac_type != em_pch_cnp) 1603 return; 1604 if (sc->legacy_irq == 0) 1605 return; 1606 1607 reg = EM_READ_REG(&sc->hw, E1000_FEXTNVM7); 1608 reg |= E1000_FEXTNVM7_SIDE_CLK_UNGATE; 1609 EM_WRITE_REG(&sc->hw, E1000_FEXTNVM7, reg); 1610 1611 reg = EM_READ_REG(&sc->hw, E1000_FEXTNVM9); 1612 reg |= E1000_FEXTNVM9_IOSFSB_CLKGATE_DIS | 1613 E1000_FEXTNVM9_IOSFSB_CLKREQ_DIS; 1614 EM_WRITE_REG(&sc->hw, E1000_FEXTNVM9, reg); 1615 } 1616 1617 int 1618 em_allocate_pci_resources(struct em_softc *sc) 1619 { 1620 int val, rid; 1621 pci_intr_handle_t ih; 1622 const char *intrstr = NULL; 1623 struct pci_attach_args *pa = &sc->osdep.em_pa; 1624 pci_chipset_tag_t pc = pa->pa_pc; 1625 1626 val = pci_conf_read(pa->pa_pc, pa->pa_tag, EM_MMBA); 1627 if (PCI_MAPREG_TYPE(val) != PCI_MAPREG_TYPE_MEM) { 1628 printf(": mmba is not mem space\n"); 1629 return (ENXIO); 1630 } 1631 if (pci_mapreg_map(pa, EM_MMBA, PCI_MAPREG_MEM_TYPE(val), 0, 1632 &sc->osdep.mem_bus_space_tag, &sc->osdep.mem_bus_space_handle, 1633 &sc->osdep.em_membase, &sc->osdep.em_memsize, 0)) { 1634 printf(": cannot find mem space\n"); 1635 return (ENXIO); 1636 } 1637 1638 switch (sc->hw.mac_type) { 1639 case em_82544: 1640 case em_82540: 1641 case em_82545: 1642 case em_82546: 1643 case em_82541: 1644 case em_82541_rev_2: 1645 /* Figure out where our I/O BAR is ? */ 1646 for (rid = PCI_MAPREG_START; rid < PCI_MAPREG_END;) { 1647 val = pci_conf_read(pa->pa_pc, pa->pa_tag, rid); 1648 if (PCI_MAPREG_TYPE(val) == PCI_MAPREG_TYPE_IO) { 1649 sc->io_rid = rid; 1650 break; 1651 } 1652 rid += 4; 1653 if (PCI_MAPREG_MEM_TYPE(val) == 1654 PCI_MAPREG_MEM_TYPE_64BIT) 1655 rid += 4; /* skip high bits, too */ 1656 } 1657 1658 if (pci_mapreg_map(pa, rid, PCI_MAPREG_TYPE_IO, 0, 1659 &sc->osdep.io_bus_space_tag, &sc->osdep.io_bus_space_handle, 1660 &sc->osdep.em_iobase, &sc->osdep.em_iosize, 0)) { 1661 printf(": cannot find i/o space\n"); 1662 return (ENXIO); 1663 } 1664 1665 sc->hw.io_base = 0; 1666 break; 1667 default: 1668 break; 1669 } 1670 1671 sc->osdep.em_flashoffset = 0; 1672 /* for ICH8 and family we need to find the flash memory */ 1673 if (sc->hw.mac_type >= em_pch_spt) { 1674 sc->osdep.flash_bus_space_tag = sc->osdep.mem_bus_space_tag; 1675 sc->osdep.flash_bus_space_handle = sc->osdep.mem_bus_space_handle; 1676 sc->osdep.em_flashbase = 0; 1677 sc->osdep.em_flashsize = 0; 1678 sc->osdep.em_flashoffset = 0xe000; 1679 } else if (IS_ICH8(sc->hw.mac_type)) { 1680 val = pci_conf_read(pa->pa_pc, pa->pa_tag, EM_FLASH); 1681 if (PCI_MAPREG_TYPE(val) != PCI_MAPREG_TYPE_MEM) { 1682 printf(": flash is not mem space\n"); 1683 return (ENXIO); 1684 } 1685 1686 if (pci_mapreg_map(pa, EM_FLASH, PCI_MAPREG_MEM_TYPE(val), 0, 1687 &sc->osdep.flash_bus_space_tag, &sc->osdep.flash_bus_space_handle, 1688 &sc->osdep.em_flashbase, &sc->osdep.em_flashsize, 0)) { 1689 printf(": cannot find mem space\n"); 1690 return (ENXIO); 1691 } 1692 } 1693 1694 sc->legacy_irq = 0; 1695 if (pci_intr_map_msi(pa, &ih)) { 1696 if (pci_intr_map(pa, &ih)) { 1697 printf(": couldn't map interrupt\n"); 1698 return (ENXIO); 1699 } 1700 sc->legacy_irq = 1; 1701 } 1702 1703 sc->osdep.dev = (struct device *)sc; 1704 sc->hw.back = &sc->osdep; 1705 1706 intrstr = pci_intr_string(pc, ih); 1707 sc->sc_intrhand = pci_intr_establish(pc, ih, IPL_NET | IPL_MPSAFE, 1708 em_intr, sc, DEVNAME(sc)); 1709 if (sc->sc_intrhand == NULL) { 1710 printf(": couldn't establish interrupt"); 1711 if (intrstr != NULL) 1712 printf(" at %s", intrstr); 1713 printf("\n"); 1714 return (ENXIO); 1715 } 1716 printf(": %s", intrstr); 1717 1718 /* 1719 * the ICP_xxxx device has multiple, duplicate register sets for 1720 * use when it is being used as a network processor. Disable those 1721 * registers here, as they are not necessary in this context and 1722 * can confuse the system 1723 */ 1724 if(sc->hw.mac_type == em_icp_xxxx) { 1725 int offset; 1726 pcireg_t val; 1727 1728 if (!pci_get_capability(sc->osdep.em_pa.pa_pc, 1729 sc->osdep.em_pa.pa_tag, PCI_CAP_ID_ST, &offset, &val)) { 1730 return (0); 1731 } 1732 offset += PCI_ST_SMIA_OFFSET; 1733 pci_conf_write(sc->osdep.em_pa.pa_pc, sc->osdep.em_pa.pa_tag, 1734 offset, 0x06); 1735 E1000_WRITE_REG(&sc->hw, IMC1, ~0x0); 1736 E1000_WRITE_REG(&sc->hw, IMC2, ~0x0); 1737 } 1738 return (0); 1739 } 1740 1741 void 1742 em_free_pci_resources(struct em_softc *sc) 1743 { 1744 struct pci_attach_args *pa = &sc->osdep.em_pa; 1745 pci_chipset_tag_t pc = pa->pa_pc; 1746 1747 if (sc->sc_intrhand) 1748 pci_intr_disestablish(pc, sc->sc_intrhand); 1749 sc->sc_intrhand = 0; 1750 1751 if (sc->osdep.em_flashbase) 1752 bus_space_unmap(sc->osdep.flash_bus_space_tag, sc->osdep.flash_bus_space_handle, 1753 sc->osdep.em_flashsize); 1754 sc->osdep.em_flashbase = 0; 1755 1756 if (sc->osdep.em_iobase) 1757 bus_space_unmap(sc->osdep.io_bus_space_tag, sc->osdep.io_bus_space_handle, 1758 sc->osdep.em_iosize); 1759 sc->osdep.em_iobase = 0; 1760 1761 if (sc->osdep.em_membase) 1762 bus_space_unmap(sc->osdep.mem_bus_space_tag, sc->osdep.mem_bus_space_handle, 1763 sc->osdep.em_memsize); 1764 sc->osdep.em_membase = 0; 1765 } 1766 1767 /********************************************************************* 1768 * 1769 * Initialize the hardware to a configuration as specified by the 1770 * em_softc structure. The controller is reset, the EEPROM is 1771 * verified, the MAC address is set, then the shared initialization 1772 * routines are called. 1773 * 1774 **********************************************************************/ 1775 int 1776 em_hardware_init(struct em_softc *sc) 1777 { 1778 uint32_t ret_val; 1779 u_int16_t rx_buffer_size; 1780 1781 INIT_DEBUGOUT("em_hardware_init: begin"); 1782 if (sc->hw.mac_type >= em_pch_spt) 1783 em_flush_desc_rings(sc); 1784 /* Issue a global reset */ 1785 em_reset_hw(&sc->hw); 1786 1787 /* When hardware is reset, fifo_head is also reset */ 1788 sc->tx_fifo_head = 0; 1789 1790 /* Make sure we have a good EEPROM before we read from it */ 1791 if (em_get_flash_presence_i210(&sc->hw) && 1792 em_validate_eeprom_checksum(&sc->hw) < 0) { 1793 /* 1794 * Some PCIe parts fail the first check due to 1795 * the link being in sleep state, call it again, 1796 * if it fails a second time its a real issue. 1797 */ 1798 if (em_validate_eeprom_checksum(&sc->hw) < 0) { 1799 printf("%s: The EEPROM Checksum Is Not Valid\n", 1800 DEVNAME(sc)); 1801 return (EIO); 1802 } 1803 } 1804 1805 if (em_get_flash_presence_i210(&sc->hw) && 1806 em_read_part_num(&sc->hw, &(sc->part_num)) < 0) { 1807 printf("%s: EEPROM read error while reading part number\n", 1808 DEVNAME(sc)); 1809 return (EIO); 1810 } 1811 1812 /* Set up smart power down as default off on newer adapters */ 1813 if (!em_smart_pwr_down && 1814 (sc->hw.mac_type == em_82571 || 1815 sc->hw.mac_type == em_82572 || 1816 sc->hw.mac_type == em_82575 || 1817 sc->hw.mac_type == em_82580 || 1818 sc->hw.mac_type == em_i210 || 1819 sc->hw.mac_type == em_i350 )) { 1820 uint16_t phy_tmp = 0; 1821 1822 /* Speed up time to link by disabling smart power down */ 1823 em_read_phy_reg(&sc->hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 1824 phy_tmp &= ~IGP02E1000_PM_SPD; 1825 em_write_phy_reg(&sc->hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp); 1826 } 1827 1828 em_legacy_irq_quirk_spt(sc); 1829 1830 /* 1831 * These parameters control the automatic generation (Tx) and 1832 * response (Rx) to Ethernet PAUSE frames. 1833 * - High water mark should allow for at least two frames to be 1834 * received after sending an XOFF. 1835 * - Low water mark works best when it is very near the high water mark. 1836 * This allows the receiver to restart by sending XON when it has 1837 * drained a bit. Here we use an arbitary value of 1500 which will 1838 * restart after one full frame is pulled from the buffer. There 1839 * could be several smaller frames in the buffer and if so they will 1840 * not trigger the XON until their total number reduces the buffer 1841 * by 1500. 1842 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 1843 */ 1844 rx_buffer_size = ((E1000_READ_REG(&sc->hw, PBA) & 0xffff) << 10 ); 1845 1846 sc->hw.fc_high_water = rx_buffer_size - 1847 EM_ROUNDUP(sc->hw.max_frame_size, 1024); 1848 sc->hw.fc_low_water = sc->hw.fc_high_water - 1500; 1849 if (sc->hw.mac_type == em_80003es2lan) 1850 sc->hw.fc_pause_time = 0xFFFF; 1851 else 1852 sc->hw.fc_pause_time = 1000; 1853 sc->hw.fc_send_xon = TRUE; 1854 sc->hw.fc = E1000_FC_FULL; 1855 1856 em_disable_aspm(sc); 1857 1858 if ((ret_val = em_init_hw(&sc->hw)) != 0) { 1859 if (ret_val == E1000_DEFER_INIT) { 1860 INIT_DEBUGOUT("\nHardware Initialization Deferred "); 1861 return (EAGAIN); 1862 } 1863 printf("\n%s: Hardware Initialization Failed\n", 1864 DEVNAME(sc)); 1865 return (EIO); 1866 } 1867 1868 em_check_for_link(&sc->hw); 1869 1870 return (0); 1871 } 1872 1873 /********************************************************************* 1874 * 1875 * Setup networking device structure and register an interface. 1876 * 1877 **********************************************************************/ 1878 void 1879 em_setup_interface(struct em_softc *sc) 1880 { 1881 struct ifnet *ifp; 1882 uint64_t fiber_type = IFM_1000_SX; 1883 1884 INIT_DEBUGOUT("em_setup_interface: begin"); 1885 1886 ifp = &sc->sc_ac.ac_if; 1887 strlcpy(ifp->if_xname, DEVNAME(sc), IFNAMSIZ); 1888 ifp->if_softc = sc; 1889 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1890 ifp->if_xflags = IFXF_MPSAFE; 1891 ifp->if_ioctl = em_ioctl; 1892 ifp->if_qstart = em_start; 1893 ifp->if_watchdog = em_watchdog; 1894 ifp->if_hardmtu = 1895 sc->hw.max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN; 1896 IFQ_SET_MAXLEN(&ifp->if_snd, sc->sc_tx_slots - 1); 1897 1898 ifp->if_capabilities = IFCAP_VLAN_MTU; 1899 1900 #if NVLAN > 0 1901 if (sc->hw.mac_type != em_82575 && sc->hw.mac_type != em_82580 && 1902 sc->hw.mac_type != em_i210 && sc->hw.mac_type != em_i350) 1903 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 1904 #endif 1905 1906 if (sc->hw.mac_type >= em_82543 && sc->hw.mac_type != em_82575 && 1907 sc->hw.mac_type != em_82580 && sc->hw.mac_type != em_i210 && 1908 sc->hw.mac_type != em_i350) 1909 ifp->if_capabilities |= IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 1910 1911 /* 1912 * Specify the media types supported by this adapter and register 1913 * callbacks to update media and link information 1914 */ 1915 ifmedia_init(&sc->media, IFM_IMASK, em_media_change, 1916 em_media_status); 1917 if (sc->hw.media_type == em_media_type_fiber || 1918 sc->hw.media_type == em_media_type_internal_serdes) { 1919 if (sc->hw.mac_type == em_82545) 1920 fiber_type = IFM_1000_LX; 1921 ifmedia_add(&sc->media, IFM_ETHER | fiber_type | IFM_FDX, 1922 0, NULL); 1923 ifmedia_add(&sc->media, IFM_ETHER | fiber_type, 1924 0, NULL); 1925 } else { 1926 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL); 1927 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX, 1928 0, NULL); 1929 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 1930 0, NULL); 1931 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 1932 0, NULL); 1933 if (sc->hw.phy_type != em_phy_ife) { 1934 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 1935 0, NULL); 1936 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_T, 0, NULL); 1937 } 1938 } 1939 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL); 1940 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO); 1941 1942 if_attach(ifp); 1943 ether_ifattach(ifp); 1944 } 1945 1946 int 1947 em_detach(struct device *self, int flags) 1948 { 1949 struct em_softc *sc = (struct em_softc *)self; 1950 struct ifnet *ifp = &sc->sc_ac.ac_if; 1951 struct pci_attach_args *pa = &sc->osdep.em_pa; 1952 pci_chipset_tag_t pc = pa->pa_pc; 1953 1954 if (sc->sc_intrhand) 1955 pci_intr_disestablish(pc, sc->sc_intrhand); 1956 sc->sc_intrhand = 0; 1957 1958 em_stop(sc, 1); 1959 1960 em_free_pci_resources(sc); 1961 1962 if (sc->sc_rx_desc_ring != NULL) { 1963 sc->sc_rx_desc_ring = NULL; 1964 em_dma_free(sc, &sc->sc_rx_dma); 1965 } 1966 if (sc->sc_tx_desc_ring != NULL) { 1967 sc->sc_tx_desc_ring = NULL; 1968 em_dma_free(sc, &sc->sc_tx_dma); 1969 } 1970 1971 ether_ifdetach(ifp); 1972 if_detach(ifp); 1973 1974 return (0); 1975 } 1976 1977 int 1978 em_activate(struct device *self, int act) 1979 { 1980 struct em_softc *sc = (struct em_softc *)self; 1981 struct ifnet *ifp = &sc->sc_ac.ac_if; 1982 int rv = 0; 1983 1984 switch (act) { 1985 case DVACT_SUSPEND: 1986 if (ifp->if_flags & IFF_RUNNING) 1987 em_stop(sc, 0); 1988 /* We have no children atm, but we will soon */ 1989 rv = config_activate_children(self, act); 1990 break; 1991 case DVACT_RESUME: 1992 if (ifp->if_flags & IFF_UP) 1993 em_init(sc); 1994 break; 1995 default: 1996 rv = config_activate_children(self, act); 1997 break; 1998 } 1999 return (rv); 2000 } 2001 2002 /********************************************************************* 2003 * 2004 * Workaround for SmartSpeed on 82541 and 82547 controllers 2005 * 2006 **********************************************************************/ 2007 void 2008 em_smartspeed(struct em_softc *sc) 2009 { 2010 uint16_t phy_tmp; 2011 2012 if (sc->link_active || (sc->hw.phy_type != em_phy_igp) || 2013 !sc->hw.autoneg || !(sc->hw.autoneg_advertised & ADVERTISE_1000_FULL)) 2014 return; 2015 2016 if (sc->smartspeed == 0) { 2017 /* If Master/Slave config fault is asserted twice, 2018 * we assume back-to-back */ 2019 em_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2020 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2021 return; 2022 em_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2023 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2024 em_read_phy_reg(&sc->hw, PHY_1000T_CTRL, 2025 &phy_tmp); 2026 if (phy_tmp & CR_1000T_MS_ENABLE) { 2027 phy_tmp &= ~CR_1000T_MS_ENABLE; 2028 em_write_phy_reg(&sc->hw, 2029 PHY_1000T_CTRL, phy_tmp); 2030 sc->smartspeed++; 2031 if (sc->hw.autoneg && 2032 !em_phy_setup_autoneg(&sc->hw) && 2033 !em_read_phy_reg(&sc->hw, PHY_CTRL, 2034 &phy_tmp)) { 2035 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2036 MII_CR_RESTART_AUTO_NEG); 2037 em_write_phy_reg(&sc->hw, 2038 PHY_CTRL, phy_tmp); 2039 } 2040 } 2041 } 2042 return; 2043 } else if (sc->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 2044 /* If still no link, perhaps using 2/3 pair cable */ 2045 em_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp); 2046 phy_tmp |= CR_1000T_MS_ENABLE; 2047 em_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp); 2048 if (sc->hw.autoneg && 2049 !em_phy_setup_autoneg(&sc->hw) && 2050 !em_read_phy_reg(&sc->hw, PHY_CTRL, &phy_tmp)) { 2051 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2052 MII_CR_RESTART_AUTO_NEG); 2053 em_write_phy_reg(&sc->hw, PHY_CTRL, phy_tmp); 2054 } 2055 } 2056 /* Restart process after EM_SMARTSPEED_MAX iterations */ 2057 if (sc->smartspeed++ == EM_SMARTSPEED_MAX) 2058 sc->smartspeed = 0; 2059 } 2060 2061 /* 2062 * Manage DMA'able memory. 2063 */ 2064 int 2065 em_dma_malloc(struct em_softc *sc, bus_size_t size, struct em_dma_alloc *dma) 2066 { 2067 int r; 2068 2069 r = bus_dmamap_create(sc->sc_dmat, size, 1, 2070 size, 0, BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, &dma->dma_map); 2071 if (r != 0) 2072 return (r); 2073 2074 r = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, &dma->dma_seg, 2075 1, &dma->dma_nseg, BUS_DMA_WAITOK | BUS_DMA_ZERO); 2076 if (r != 0) 2077 goto destroy; 2078 2079 r = bus_dmamem_map(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg, size, 2080 &dma->dma_vaddr, BUS_DMA_WAITOK); 2081 if (r != 0) 2082 goto free; 2083 2084 r = bus_dmamap_load(sc->sc_dmat, dma->dma_map, dma->dma_vaddr, size, 2085 NULL, BUS_DMA_WAITOK); 2086 if (r != 0) 2087 goto unmap; 2088 2089 dma->dma_size = size; 2090 return (0); 2091 2092 unmap: 2093 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, size); 2094 free: 2095 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 2096 destroy: 2097 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 2098 2099 return (r); 2100 } 2101 2102 void 2103 em_dma_free(struct em_softc *sc, struct em_dma_alloc *dma) 2104 { 2105 bus_dmamap_unload(sc->sc_dmat, dma->dma_map); 2106 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, dma->dma_size); 2107 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 2108 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 2109 } 2110 2111 /********************************************************************* 2112 * 2113 * Allocate memory for tx_buffer structures. The tx_buffer stores all 2114 * the information needed to transmit a packet on the wire. 2115 * 2116 **********************************************************************/ 2117 int 2118 em_allocate_transmit_structures(struct em_softc *sc) 2119 { 2120 bus_dmamap_sync(sc->sc_dmat, sc->sc_tx_dma.dma_map, 2121 0, sc->sc_tx_dma.dma_map->dm_mapsize, 2122 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2123 2124 sc->sc_tx_pkts_ring = mallocarray(sc->sc_tx_slots, 2125 sizeof(*sc->sc_tx_pkts_ring), M_DEVBUF, M_NOWAIT | M_ZERO); 2126 if (sc->sc_tx_pkts_ring == NULL) { 2127 printf("%s: Unable to allocate tx_buffer memory\n", 2128 DEVNAME(sc)); 2129 return (ENOMEM); 2130 } 2131 2132 return (0); 2133 } 2134 2135 /********************************************************************* 2136 * 2137 * Allocate and initialize transmit structures. 2138 * 2139 **********************************************************************/ 2140 int 2141 em_setup_transmit_structures(struct em_softc *sc) 2142 { 2143 struct em_packet *pkt; 2144 int error, i; 2145 2146 if ((error = em_allocate_transmit_structures(sc)) != 0) 2147 goto fail; 2148 2149 bzero((void *) sc->sc_tx_desc_ring, 2150 (sizeof(struct em_tx_desc)) * sc->sc_tx_slots); 2151 2152 for (i = 0; i < sc->sc_tx_slots; i++) { 2153 pkt = &sc->sc_tx_pkts_ring[i]; 2154 error = bus_dmamap_create(sc->sc_dmat, MAX_JUMBO_FRAME_SIZE, 2155 EM_MAX_SCATTER / (sc->pcix_82544 ? 2 : 1), 2156 MAX_JUMBO_FRAME_SIZE, 0, BUS_DMA_NOWAIT, &pkt->pkt_map); 2157 if (error != 0) { 2158 printf("%s: Unable to create TX DMA map\n", 2159 DEVNAME(sc)); 2160 goto fail; 2161 } 2162 } 2163 2164 sc->sc_tx_desc_head = 0; 2165 sc->sc_tx_desc_tail = 0; 2166 2167 /* Set checksum context */ 2168 sc->active_checksum_context = OFFLOAD_NONE; 2169 2170 return (0); 2171 2172 fail: 2173 em_free_transmit_structures(sc); 2174 return (error); 2175 } 2176 2177 /********************************************************************* 2178 * 2179 * Enable transmit unit. 2180 * 2181 **********************************************************************/ 2182 void 2183 em_initialize_transmit_unit(struct em_softc *sc) 2184 { 2185 u_int32_t reg_tctl, reg_tipg = 0; 2186 u_int64_t bus_addr; 2187 2188 INIT_DEBUGOUT("em_initialize_transmit_unit: begin"); 2189 2190 /* Setup the Base and Length of the Tx Descriptor Ring */ 2191 bus_addr = sc->sc_tx_dma.dma_map->dm_segs[0].ds_addr; 2192 E1000_WRITE_REG(&sc->hw, TDLEN, 2193 sc->sc_tx_slots * 2194 sizeof(struct em_tx_desc)); 2195 E1000_WRITE_REG(&sc->hw, TDBAH, (u_int32_t)(bus_addr >> 32)); 2196 E1000_WRITE_REG(&sc->hw, TDBAL, (u_int32_t)bus_addr); 2197 2198 /* Setup the HW Tx Head and Tail descriptor pointers */ 2199 E1000_WRITE_REG(&sc->hw, TDT, 0); 2200 E1000_WRITE_REG(&sc->hw, TDH, 0); 2201 2202 HW_DEBUGOUT2("Base = %x, Length = %x\n", 2203 E1000_READ_REG(&sc->hw, TDBAL), 2204 E1000_READ_REG(&sc->hw, TDLEN)); 2205 2206 /* Set the default values for the Tx Inter Packet Gap timer */ 2207 switch (sc->hw.mac_type) { 2208 case em_82542_rev2_0: 2209 case em_82542_rev2_1: 2210 reg_tipg = DEFAULT_82542_TIPG_IPGT; 2211 reg_tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2212 reg_tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2213 break; 2214 case em_80003es2lan: 2215 reg_tipg = DEFAULT_82543_TIPG_IPGR1; 2216 reg_tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2217 break; 2218 default: 2219 if (sc->hw.media_type == em_media_type_fiber || 2220 sc->hw.media_type == em_media_type_internal_serdes) 2221 reg_tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 2222 else 2223 reg_tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 2224 reg_tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2225 reg_tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2226 } 2227 2228 2229 E1000_WRITE_REG(&sc->hw, TIPG, reg_tipg); 2230 E1000_WRITE_REG(&sc->hw, TIDV, sc->tx_int_delay); 2231 if (sc->hw.mac_type >= em_82540) 2232 E1000_WRITE_REG(&sc->hw, TADV, sc->tx_abs_int_delay); 2233 2234 /* Setup Transmit Descriptor Base Settings */ 2235 sc->sc_txd_cmd = E1000_TXD_CMD_IFCS; 2236 2237 if (sc->hw.mac_type == em_82575 || sc->hw.mac_type == em_82580 || 2238 sc->hw.mac_type == em_i210 || sc->hw.mac_type == em_i350) { 2239 /* 82575/6 need to enable the TX queue and lack the IDE bit */ 2240 reg_tctl = E1000_READ_REG(&sc->hw, TXDCTL); 2241 reg_tctl |= E1000_TXDCTL_QUEUE_ENABLE; 2242 E1000_WRITE_REG(&sc->hw, TXDCTL, reg_tctl); 2243 } else if (sc->tx_int_delay > 0) 2244 sc->sc_txd_cmd |= E1000_TXD_CMD_IDE; 2245 2246 /* Program the Transmit Control Register */ 2247 reg_tctl = E1000_TCTL_PSP | E1000_TCTL_EN | 2248 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 2249 if (sc->hw.mac_type >= em_82571) 2250 reg_tctl |= E1000_TCTL_MULR; 2251 if (sc->link_duplex == FULL_DUPLEX) 2252 reg_tctl |= E1000_FDX_COLLISION_DISTANCE << E1000_COLD_SHIFT; 2253 else 2254 reg_tctl |= E1000_HDX_COLLISION_DISTANCE << E1000_COLD_SHIFT; 2255 /* This write will effectively turn on the transmit unit */ 2256 E1000_WRITE_REG(&sc->hw, TCTL, reg_tctl); 2257 2258 /* SPT Si errata workaround to avoid data corruption */ 2259 2260 if (sc->hw.mac_type == em_pch_spt) { 2261 uint32_t reg_val; 2262 2263 reg_val = EM_READ_REG(&sc->hw, E1000_IOSFPC); 2264 reg_val |= E1000_RCTL_RDMTS_HEX; 2265 EM_WRITE_REG(&sc->hw, E1000_IOSFPC, reg_val); 2266 2267 reg_val = E1000_READ_REG(&sc->hw, TARC0); 2268 reg_val |= E1000_TARC0_CB_MULTIQ_3_REQ; 2269 E1000_WRITE_REG(&sc->hw, TARC0, reg_val); 2270 } 2271 } 2272 2273 /********************************************************************* 2274 * 2275 * Free all transmit related data structures. 2276 * 2277 **********************************************************************/ 2278 void 2279 em_free_transmit_structures(struct em_softc *sc) 2280 { 2281 struct em_packet *pkt; 2282 int i; 2283 2284 INIT_DEBUGOUT("free_transmit_structures: begin"); 2285 2286 if (sc->sc_tx_pkts_ring != NULL) { 2287 for (i = 0; i < sc->sc_tx_slots; i++) { 2288 pkt = &sc->sc_tx_pkts_ring[i]; 2289 2290 if (pkt->pkt_m != NULL) { 2291 bus_dmamap_sync(sc->sc_dmat, pkt->pkt_map, 2292 0, pkt->pkt_map->dm_mapsize, 2293 BUS_DMASYNC_POSTWRITE); 2294 bus_dmamap_unload(sc->sc_dmat, pkt->pkt_map); 2295 2296 m_freem(pkt->pkt_m); 2297 pkt->pkt_m = NULL; 2298 } 2299 2300 if (pkt->pkt_map != NULL) { 2301 bus_dmamap_destroy(sc->sc_dmat, pkt->pkt_map); 2302 pkt->pkt_map = NULL; 2303 } 2304 } 2305 2306 free(sc->sc_tx_pkts_ring, M_DEVBUF, 2307 sc->sc_tx_slots * sizeof(*sc->sc_tx_pkts_ring)); 2308 sc->sc_tx_pkts_ring = NULL; 2309 } 2310 2311 bus_dmamap_sync(sc->sc_dmat, sc->sc_tx_dma.dma_map, 2312 0, sc->sc_tx_dma.dma_map->dm_mapsize, 2313 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2314 } 2315 2316 /********************************************************************* 2317 * 2318 * The offload context needs to be set when we transfer the first 2319 * packet of a particular protocol (TCP/UDP). We change the 2320 * context only if the protocol type changes. 2321 * 2322 **********************************************************************/ 2323 u_int 2324 em_transmit_checksum_setup(struct em_softc *sc, struct mbuf *mp, u_int head, 2325 u_int32_t *txd_upper, u_int32_t *txd_lower) 2326 { 2327 struct em_context_desc *TXD; 2328 2329 if (mp->m_pkthdr.csum_flags & M_TCP_CSUM_OUT) { 2330 *txd_upper = E1000_TXD_POPTS_TXSM << 8; 2331 *txd_lower = E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 2332 if (sc->active_checksum_context == OFFLOAD_TCP_IP) 2333 return (0); 2334 else 2335 sc->active_checksum_context = OFFLOAD_TCP_IP; 2336 } else if (mp->m_pkthdr.csum_flags & M_UDP_CSUM_OUT) { 2337 *txd_upper = E1000_TXD_POPTS_TXSM << 8; 2338 *txd_lower = E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 2339 if (sc->active_checksum_context == OFFLOAD_UDP_IP) 2340 return (0); 2341 else 2342 sc->active_checksum_context = OFFLOAD_UDP_IP; 2343 } else { 2344 *txd_upper = 0; 2345 *txd_lower = 0; 2346 return (0); 2347 } 2348 2349 /* If we reach this point, the checksum offload context 2350 * needs to be reset. 2351 */ 2352 TXD = (struct em_context_desc *)&sc->sc_tx_desc_ring[head]; 2353 2354 TXD->lower_setup.ip_fields.ipcss = ETHER_HDR_LEN; 2355 TXD->lower_setup.ip_fields.ipcso = 2356 ETHER_HDR_LEN + offsetof(struct ip, ip_sum); 2357 TXD->lower_setup.ip_fields.ipcse = 2358 htole16(ETHER_HDR_LEN + sizeof(struct ip) - 1); 2359 2360 TXD->upper_setup.tcp_fields.tucss = 2361 ETHER_HDR_LEN + sizeof(struct ip); 2362 TXD->upper_setup.tcp_fields.tucse = htole16(0); 2363 2364 if (sc->active_checksum_context == OFFLOAD_TCP_IP) { 2365 TXD->upper_setup.tcp_fields.tucso = 2366 ETHER_HDR_LEN + sizeof(struct ip) + 2367 offsetof(struct tcphdr, th_sum); 2368 } else if (sc->active_checksum_context == OFFLOAD_UDP_IP) { 2369 TXD->upper_setup.tcp_fields.tucso = 2370 ETHER_HDR_LEN + sizeof(struct ip) + 2371 offsetof(struct udphdr, uh_sum); 2372 } 2373 2374 TXD->tcp_seg_setup.data = htole32(0); 2375 TXD->cmd_and_length = htole32(sc->sc_txd_cmd | E1000_TXD_CMD_DEXT); 2376 2377 return (1); 2378 } 2379 2380 /********************************************************************** 2381 * 2382 * Examine each tx_buffer in the used queue. If the hardware is done 2383 * processing the packet then free associated resources. The 2384 * tx_buffer is put back on the free queue. 2385 * 2386 **********************************************************************/ 2387 void 2388 em_txeof(struct em_softc *sc) 2389 { 2390 struct ifnet *ifp = &sc->sc_ac.ac_if; 2391 struct em_packet *pkt; 2392 struct em_tx_desc *desc; 2393 u_int head, tail; 2394 u_int free = 0; 2395 2396 head = sc->sc_tx_desc_head; 2397 tail = sc->sc_tx_desc_tail; 2398 2399 if (head == tail) 2400 return; 2401 2402 bus_dmamap_sync(sc->sc_dmat, sc->sc_tx_dma.dma_map, 2403 0, sc->sc_tx_dma.dma_map->dm_mapsize, 2404 BUS_DMASYNC_POSTREAD); 2405 2406 do { 2407 pkt = &sc->sc_tx_pkts_ring[tail]; 2408 desc = &sc->sc_tx_desc_ring[pkt->pkt_eop]; 2409 2410 if (!ISSET(desc->upper.fields.status, E1000_TXD_STAT_DD)) 2411 break; 2412 2413 bus_dmamap_sync(sc->sc_dmat, pkt->pkt_map, 2414 0, pkt->pkt_map->dm_mapsize, 2415 BUS_DMASYNC_POSTWRITE); 2416 bus_dmamap_unload(sc->sc_dmat, pkt->pkt_map); 2417 2418 KASSERT(pkt->pkt_m != NULL); 2419 2420 m_freem(pkt->pkt_m); 2421 pkt->pkt_m = NULL; 2422 2423 tail = pkt->pkt_eop; 2424 2425 if (++tail == sc->sc_tx_slots) 2426 tail = 0; 2427 2428 free++; 2429 } while (tail != head); 2430 2431 bus_dmamap_sync(sc->sc_dmat, sc->sc_tx_dma.dma_map, 2432 0, sc->sc_tx_dma.dma_map->dm_mapsize, 2433 BUS_DMASYNC_PREREAD); 2434 2435 if (free == 0) 2436 return; 2437 2438 sc->sc_tx_desc_tail = tail; 2439 2440 if (ifq_is_oactive(&ifp->if_snd)) 2441 ifq_restart(&ifp->if_snd); 2442 else if (tail == head) 2443 ifp->if_timer = 0; 2444 } 2445 2446 /********************************************************************* 2447 * 2448 * Get a buffer from system mbuf buffer pool. 2449 * 2450 **********************************************************************/ 2451 int 2452 em_get_buf(struct em_softc *sc, int i) 2453 { 2454 struct mbuf *m; 2455 struct em_packet *pkt; 2456 struct em_rx_desc *desc; 2457 int error; 2458 2459 pkt = &sc->sc_rx_pkts_ring[i]; 2460 desc = &sc->sc_rx_desc_ring[i]; 2461 2462 KASSERT(pkt->pkt_m == NULL); 2463 2464 m = MCLGETI(NULL, M_DONTWAIT, NULL, EM_MCLBYTES); 2465 if (m == NULL) { 2466 sc->mbuf_cluster_failed++; 2467 return (ENOBUFS); 2468 } 2469 m->m_len = m->m_pkthdr.len = EM_MCLBYTES; 2470 m_adj(m, ETHER_ALIGN); 2471 2472 error = bus_dmamap_load_mbuf(sc->sc_dmat, pkt->pkt_map, 2473 m, BUS_DMA_NOWAIT); 2474 if (error) { 2475 m_freem(m); 2476 return (error); 2477 } 2478 2479 bus_dmamap_sync(sc->sc_dmat, pkt->pkt_map, 2480 0, pkt->pkt_map->dm_mapsize, 2481 BUS_DMASYNC_PREREAD); 2482 pkt->pkt_m = m; 2483 2484 memset(desc, 0, sizeof(*desc)); 2485 htolem64(&desc->buffer_addr, pkt->pkt_map->dm_segs[0].ds_addr); 2486 2487 return (0); 2488 } 2489 2490 /********************************************************************* 2491 * 2492 * Allocate memory for rx_buffer structures. Since we use one 2493 * rx_buffer per received packet, the maximum number of rx_buffer's 2494 * that we'll need is equal to the number of receive descriptors 2495 * that we've allocated. 2496 * 2497 **********************************************************************/ 2498 int 2499 em_allocate_receive_structures(struct em_softc *sc) 2500 { 2501 struct em_packet *pkt; 2502 int i; 2503 int error; 2504 2505 sc->sc_rx_pkts_ring = mallocarray(sc->sc_rx_slots, 2506 sizeof(*sc->sc_rx_pkts_ring), M_DEVBUF, M_NOWAIT | M_ZERO); 2507 if (sc->sc_rx_pkts_ring == NULL) { 2508 printf("%s: Unable to allocate rx_buffer memory\n", 2509 DEVNAME(sc)); 2510 return (ENOMEM); 2511 } 2512 2513 bus_dmamap_sync(sc->sc_dmat, sc->sc_rx_dma.dma_map, 2514 0, sc->sc_rx_dma.dma_map->dm_mapsize, 2515 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2516 2517 for (i = 0; i < sc->sc_rx_slots; i++) { 2518 pkt = &sc->sc_rx_pkts_ring[i]; 2519 2520 error = bus_dmamap_create(sc->sc_dmat, EM_MCLBYTES, 1, 2521 EM_MCLBYTES, 0, BUS_DMA_NOWAIT, &pkt->pkt_map); 2522 if (error != 0) { 2523 printf("%s: em_allocate_receive_structures: " 2524 "bus_dmamap_create failed; error %u\n", 2525 DEVNAME(sc), error); 2526 goto fail; 2527 } 2528 2529 pkt->pkt_m = NULL; 2530 } 2531 2532 return (0); 2533 2534 fail: 2535 em_free_receive_structures(sc); 2536 return (error); 2537 } 2538 2539 /********************************************************************* 2540 * 2541 * Allocate and initialize receive structures. 2542 * 2543 **********************************************************************/ 2544 int 2545 em_setup_receive_structures(struct em_softc *sc) 2546 { 2547 struct ifnet *ifp = &sc->sc_ac.ac_if; 2548 u_int lwm; 2549 2550 memset(sc->sc_rx_desc_ring, 0, 2551 sc->sc_rx_slots * sizeof(*sc->sc_rx_desc_ring)); 2552 2553 if (em_allocate_receive_structures(sc)) 2554 return (ENOMEM); 2555 2556 /* Setup our descriptor pointers */ 2557 sc->sc_rx_desc_tail = 0; 2558 sc->sc_rx_desc_head = sc->sc_rx_slots - 1; 2559 2560 lwm = max(4, 2 * ((ifp->if_hardmtu / MCLBYTES) + 1)); 2561 if_rxr_init(&sc->sc_rx_ring, lwm, sc->sc_rx_slots); 2562 2563 if (em_rxfill(sc) == 0) { 2564 printf("%s: unable to fill any rx descriptors\n", 2565 DEVNAME(sc)); 2566 } 2567 2568 return (0); 2569 } 2570 2571 /********************************************************************* 2572 * 2573 * Enable receive unit. 2574 * 2575 **********************************************************************/ 2576 void 2577 em_initialize_receive_unit(struct em_softc *sc) 2578 { 2579 u_int32_t reg_rctl; 2580 u_int32_t reg_rxcsum; 2581 u_int64_t bus_addr; 2582 2583 INIT_DEBUGOUT("em_initialize_receive_unit: begin"); 2584 2585 /* Make sure receives are disabled while setting up the descriptor ring */ 2586 E1000_WRITE_REG(&sc->hw, RCTL, 0); 2587 2588 /* Set the Receive Delay Timer Register */ 2589 E1000_WRITE_REG(&sc->hw, RDTR, 2590 sc->rx_int_delay | E1000_RDT_FPDB); 2591 2592 if (sc->hw.mac_type >= em_82540) { 2593 if (sc->rx_int_delay) 2594 E1000_WRITE_REG(&sc->hw, RADV, sc->rx_abs_int_delay); 2595 2596 /* Set the interrupt throttling rate. Value is calculated 2597 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */ 2598 E1000_WRITE_REG(&sc->hw, ITR, DEFAULT_ITR); 2599 } 2600 2601 /* Setup the Base and Length of the Rx Descriptor Ring */ 2602 bus_addr = sc->sc_rx_dma.dma_map->dm_segs[0].ds_addr; 2603 E1000_WRITE_REG(&sc->hw, RDLEN, 2604 sc->sc_rx_slots * sizeof(*sc->sc_rx_desc_ring)); 2605 E1000_WRITE_REG(&sc->hw, RDBAH, (u_int32_t)(bus_addr >> 32)); 2606 E1000_WRITE_REG(&sc->hw, RDBAL, (u_int32_t)bus_addr); 2607 2608 /* Setup the Receive Control Register */ 2609 reg_rctl = E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO | 2610 E1000_RCTL_RDMTS_HALF | 2611 (sc->hw.mc_filter_type << E1000_RCTL_MO_SHIFT); 2612 2613 if (sc->hw.tbi_compatibility_on == TRUE) 2614 reg_rctl |= E1000_RCTL_SBP; 2615 2616 /* 2617 * The i350 has a bug where it always strips the CRC whether 2618 * asked to or not. So ask for stripped CRC here and 2619 * cope in rxeof 2620 */ 2621 if (sc->hw.mac_type == em_i210 || sc->hw.mac_type == em_i350) 2622 reg_rctl |= E1000_RCTL_SECRC; 2623 2624 switch (sc->sc_rx_buffer_len) { 2625 default: 2626 case EM_RXBUFFER_2048: 2627 reg_rctl |= E1000_RCTL_SZ_2048; 2628 break; 2629 case EM_RXBUFFER_4096: 2630 reg_rctl |= E1000_RCTL_SZ_4096|E1000_RCTL_BSEX|E1000_RCTL_LPE; 2631 break; 2632 case EM_RXBUFFER_8192: 2633 reg_rctl |= E1000_RCTL_SZ_8192|E1000_RCTL_BSEX|E1000_RCTL_LPE; 2634 break; 2635 case EM_RXBUFFER_16384: 2636 reg_rctl |= E1000_RCTL_SZ_16384|E1000_RCTL_BSEX|E1000_RCTL_LPE; 2637 break; 2638 } 2639 2640 if (sc->hw.max_frame_size != ETHER_MAX_LEN) 2641 reg_rctl |= E1000_RCTL_LPE; 2642 2643 /* Enable 82543 Receive Checksum Offload for TCP and UDP */ 2644 if (sc->hw.mac_type >= em_82543) { 2645 reg_rxcsum = E1000_READ_REG(&sc->hw, RXCSUM); 2646 reg_rxcsum |= (E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL); 2647 E1000_WRITE_REG(&sc->hw, RXCSUM, reg_rxcsum); 2648 } 2649 2650 /* 2651 * XXX TEMPORARY WORKAROUND: on some systems with 82573 2652 * long latencies are observed, like Lenovo X60. 2653 */ 2654 if (sc->hw.mac_type == em_82573) 2655 E1000_WRITE_REG(&sc->hw, RDTR, 0x20); 2656 2657 if (sc->hw.mac_type == em_82575 || sc->hw.mac_type == em_82580 || 2658 sc->hw.mac_type == em_i210 || sc->hw.mac_type == em_i350) { 2659 /* 82575/6 need to enable the RX queue */ 2660 uint32_t reg; 2661 reg = E1000_READ_REG(&sc->hw, RXDCTL); 2662 reg |= E1000_RXDCTL_QUEUE_ENABLE; 2663 E1000_WRITE_REG(&sc->hw, RXDCTL, reg); 2664 } 2665 2666 /* Enable Receives */ 2667 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 2668 2669 /* Setup the HW Rx Head and Tail Descriptor Pointers */ 2670 E1000_WRITE_REG(&sc->hw, RDH, 0); 2671 E1000_WRITE_REG(&sc->hw, RDT, sc->sc_rx_desc_head); 2672 } 2673 2674 /********************************************************************* 2675 * 2676 * Free receive related data structures. 2677 * 2678 **********************************************************************/ 2679 void 2680 em_free_receive_structures(struct em_softc *sc) 2681 { 2682 struct em_packet *pkt; 2683 int i; 2684 2685 INIT_DEBUGOUT("free_receive_structures: begin"); 2686 2687 if_rxr_init(&sc->sc_rx_ring, 0, 0); 2688 2689 bus_dmamap_sync(sc->sc_dmat, sc->sc_rx_dma.dma_map, 2690 0, sc->sc_rx_dma.dma_map->dm_mapsize, 2691 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2692 2693 if (sc->sc_rx_pkts_ring != NULL) { 2694 for (i = 0; i < sc->sc_rx_slots; i++) { 2695 pkt = &sc->sc_rx_pkts_ring[i]; 2696 if (pkt->pkt_m != NULL) { 2697 bus_dmamap_sync(sc->sc_dmat, pkt->pkt_map, 2698 0, pkt->pkt_map->dm_mapsize, 2699 BUS_DMASYNC_POSTREAD); 2700 bus_dmamap_unload(sc->sc_dmat, pkt->pkt_map); 2701 m_freem(pkt->pkt_m); 2702 pkt->pkt_m = NULL; 2703 } 2704 bus_dmamap_destroy(sc->sc_dmat, pkt->pkt_map); 2705 } 2706 2707 free(sc->sc_rx_pkts_ring, M_DEVBUF, 2708 sc->sc_rx_slots * sizeof(*sc->sc_rx_pkts_ring)); 2709 sc->sc_rx_pkts_ring = NULL; 2710 } 2711 2712 if (sc->fmp != NULL) { 2713 m_freem(sc->fmp); 2714 sc->fmp = NULL; 2715 sc->lmp = NULL; 2716 } 2717 } 2718 2719 int 2720 em_rxfill(struct em_softc *sc) 2721 { 2722 u_int slots; 2723 int post = 0; 2724 int i; 2725 2726 i = sc->sc_rx_desc_head; 2727 2728 bus_dmamap_sync(sc->sc_dmat, sc->sc_rx_dma.dma_map, 2729 0, sc->sc_rx_dma.dma_map->dm_mapsize, 2730 BUS_DMASYNC_POSTWRITE); 2731 2732 for (slots = if_rxr_get(&sc->sc_rx_ring, sc->sc_rx_slots); 2733 slots > 0; slots--) { 2734 if (++i == sc->sc_rx_slots) 2735 i = 0; 2736 2737 if (em_get_buf(sc, i) != 0) 2738 break; 2739 2740 sc->sc_rx_desc_head = i; 2741 post = 1; 2742 } 2743 2744 if_rxr_put(&sc->sc_rx_ring, slots); 2745 2746 bus_dmamap_sync(sc->sc_dmat, sc->sc_rx_dma.dma_map, 2747 0, sc->sc_rx_dma.dma_map->dm_mapsize, 2748 BUS_DMASYNC_PREWRITE); 2749 2750 return (post); 2751 } 2752 2753 /********************************************************************* 2754 * 2755 * This routine executes in interrupt context. It replenishes 2756 * the mbufs in the descriptor and sends data which has been 2757 * dma'ed into host memory to upper layer. 2758 * 2759 *********************************************************************/ 2760 int 2761 em_rxeof(struct em_softc *sc) 2762 { 2763 struct ifnet *ifp = &sc->sc_ac.ac_if; 2764 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 2765 struct mbuf *m; 2766 u_int8_t accept_frame = 0; 2767 u_int8_t eop = 0; 2768 u_int16_t len, desc_len, prev_len_adj; 2769 int i, rv = 0; 2770 2771 /* Pointer to the receive descriptor being examined. */ 2772 struct em_rx_desc *desc; 2773 struct em_packet *pkt; 2774 u_int8_t status; 2775 2776 if (if_rxr_inuse(&sc->sc_rx_ring) == 0) 2777 return (0); 2778 2779 i = sc->sc_rx_desc_tail; 2780 2781 bus_dmamap_sync(sc->sc_dmat, sc->sc_rx_dma.dma_map, 2782 0, sc->sc_rx_dma.dma_map->dm_mapsize, 2783 BUS_DMASYNC_POSTREAD); 2784 2785 do { 2786 m = NULL; 2787 2788 pkt = &sc->sc_rx_pkts_ring[i]; 2789 desc = &sc->sc_rx_desc_ring[i]; 2790 2791 status = desc->status; 2792 if (!ISSET(status, E1000_RXD_STAT_DD)) 2793 break; 2794 2795 /* pull the mbuf off the ring */ 2796 bus_dmamap_sync(sc->sc_dmat, pkt->pkt_map, 2797 0, pkt->pkt_map->dm_mapsize, 2798 BUS_DMASYNC_POSTREAD); 2799 bus_dmamap_unload(sc->sc_dmat, pkt->pkt_map); 2800 m = pkt->pkt_m; 2801 pkt->pkt_m = NULL; 2802 2803 KASSERT(m != NULL); 2804 2805 if_rxr_put(&sc->sc_rx_ring, 1); 2806 rv = 1; 2807 2808 accept_frame = 1; 2809 prev_len_adj = 0; 2810 desc_len = letoh16(desc->length); 2811 2812 if (status & E1000_RXD_STAT_EOP) { 2813 eop = 1; 2814 if (desc_len < ETHER_CRC_LEN) { 2815 len = 0; 2816 prev_len_adj = ETHER_CRC_LEN - desc_len; 2817 } else if (sc->hw.mac_type == em_i210 || 2818 sc->hw.mac_type == em_i350) 2819 len = desc_len; 2820 else 2821 len = desc_len - ETHER_CRC_LEN; 2822 } else { 2823 eop = 0; 2824 len = desc_len; 2825 } 2826 2827 if (desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK) { 2828 u_int8_t last_byte; 2829 u_int32_t pkt_len = desc_len; 2830 2831 if (sc->fmp != NULL) 2832 pkt_len += sc->fmp->m_pkthdr.len; 2833 2834 last_byte = *(mtod(m, caddr_t) + desc_len - 1); 2835 if (TBI_ACCEPT(&sc->hw, status, desc->errors, 2836 pkt_len, last_byte)) { 2837 #ifndef SMALL_KERNEL 2838 em_tbi_adjust_stats(&sc->hw, &sc->stats, 2839 pkt_len, sc->hw.mac_addr); 2840 #endif 2841 if (len > 0) 2842 len--; 2843 } else 2844 accept_frame = 0; 2845 } 2846 2847 if (accept_frame) { 2848 /* Assign correct length to the current fragment */ 2849 m->m_len = len; 2850 2851 if (sc->fmp == NULL) { 2852 m->m_pkthdr.len = m->m_len; 2853 sc->fmp = m; /* Store the first mbuf */ 2854 sc->lmp = m; 2855 } else { 2856 /* Chain mbuf's together */ 2857 m->m_flags &= ~M_PKTHDR; 2858 /* 2859 * Adjust length of previous mbuf in chain if 2860 * we received less than 4 bytes in the last 2861 * descriptor. 2862 */ 2863 if (prev_len_adj > 0) { 2864 sc->lmp->m_len -= prev_len_adj; 2865 sc->fmp->m_pkthdr.len -= prev_len_adj; 2866 } 2867 sc->lmp->m_next = m; 2868 sc->lmp = m; 2869 sc->fmp->m_pkthdr.len += m->m_len; 2870 } 2871 2872 if (eop) { 2873 m = sc->fmp; 2874 2875 em_receive_checksum(sc, desc, m); 2876 #if NVLAN > 0 2877 if (desc->status & E1000_RXD_STAT_VP) { 2878 m->m_pkthdr.ether_vtag = 2879 letoh16(desc->special); 2880 m->m_flags |= M_VLANTAG; 2881 } 2882 #endif 2883 ml_enqueue(&ml, m); 2884 2885 sc->fmp = NULL; 2886 sc->lmp = NULL; 2887 } 2888 } else { 2889 sc->dropped_pkts++; 2890 2891 if (sc->fmp != NULL) { 2892 m_freem(sc->fmp); 2893 sc->fmp = NULL; 2894 sc->lmp = NULL; 2895 } 2896 2897 m_freem(m); 2898 } 2899 2900 /* Advance our pointers to the next descriptor. */ 2901 if (++i == sc->sc_rx_slots) 2902 i = 0; 2903 } while (if_rxr_inuse(&sc->sc_rx_ring) > 0); 2904 2905 bus_dmamap_sync(sc->sc_dmat, sc->sc_rx_dma.dma_map, 2906 0, sc->sc_rx_dma.dma_map->dm_mapsize, 2907 BUS_DMASYNC_PREREAD); 2908 2909 sc->sc_rx_desc_tail = i; 2910 2911 if_input(ifp, &ml); 2912 2913 return (rv); 2914 } 2915 2916 /********************************************************************* 2917 * 2918 * Verify that the hardware indicated that the checksum is valid. 2919 * Inform the stack about the status of checksum so that stack 2920 * doesn't spend time verifying the checksum. 2921 * 2922 *********************************************************************/ 2923 void 2924 em_receive_checksum(struct em_softc *sc, struct em_rx_desc *rx_desc, 2925 struct mbuf *mp) 2926 { 2927 /* 82543 or newer only */ 2928 if ((sc->hw.mac_type < em_82543) || 2929 /* Ignore Checksum bit is set */ 2930 (rx_desc->status & E1000_RXD_STAT_IXSM)) { 2931 mp->m_pkthdr.csum_flags = 0; 2932 return; 2933 } 2934 2935 if (rx_desc->status & E1000_RXD_STAT_IPCS) { 2936 /* Did it pass? */ 2937 if (!(rx_desc->errors & E1000_RXD_ERR_IPE)) { 2938 /* IP Checksum Good */ 2939 mp->m_pkthdr.csum_flags = M_IPV4_CSUM_IN_OK; 2940 2941 } else 2942 mp->m_pkthdr.csum_flags = 0; 2943 } 2944 2945 if (rx_desc->status & E1000_RXD_STAT_TCPCS) { 2946 /* Did it pass? */ 2947 if (!(rx_desc->errors & E1000_RXD_ERR_TCPE)) 2948 mp->m_pkthdr.csum_flags |= 2949 M_TCP_CSUM_IN_OK | M_UDP_CSUM_IN_OK; 2950 } 2951 } 2952 2953 /* 2954 * This turns on the hardware offload of the VLAN 2955 * tag insertion and strip 2956 */ 2957 void 2958 em_enable_hw_vlans(struct em_softc *sc) 2959 { 2960 uint32_t ctrl; 2961 2962 ctrl = E1000_READ_REG(&sc->hw, CTRL); 2963 ctrl |= E1000_CTRL_VME; 2964 E1000_WRITE_REG(&sc->hw, CTRL, ctrl); 2965 } 2966 2967 void 2968 em_enable_intr(struct em_softc *sc) 2969 { 2970 E1000_WRITE_REG(&sc->hw, IMS, (IMS_ENABLE_MASK)); 2971 } 2972 2973 void 2974 em_disable_intr(struct em_softc *sc) 2975 { 2976 /* 2977 * The first version of 82542 had an errata where when link 2978 * was forced it would stay up even if the cable was disconnected 2979 * Sequence errors were used to detect the disconnect and then 2980 * the driver would unforce the link. This code is in the ISR. 2981 * For this to work correctly the Sequence error interrupt had 2982 * to be enabled all the time. 2983 */ 2984 2985 if (sc->hw.mac_type == em_82542_rev2_0) 2986 E1000_WRITE_REG(&sc->hw, IMC, (0xffffffff & ~E1000_IMC_RXSEQ)); 2987 else 2988 E1000_WRITE_REG(&sc->hw, IMC, 0xffffffff); 2989 } 2990 2991 void 2992 em_write_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t *value) 2993 { 2994 struct pci_attach_args *pa = &((struct em_osdep *)hw->back)->em_pa; 2995 pcireg_t val; 2996 2997 val = pci_conf_read(pa->pa_pc, pa->pa_tag, reg & ~0x3); 2998 if (reg & 0x2) { 2999 val &= 0x0000ffff; 3000 val |= (*value << 16); 3001 } else { 3002 val &= 0xffff0000; 3003 val |= *value; 3004 } 3005 pci_conf_write(pa->pa_pc, pa->pa_tag, reg & ~0x3, val); 3006 } 3007 3008 void 3009 em_read_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t *value) 3010 { 3011 struct pci_attach_args *pa = &((struct em_osdep *)hw->back)->em_pa; 3012 pcireg_t val; 3013 3014 val = pci_conf_read(pa->pa_pc, pa->pa_tag, reg & ~0x3); 3015 if (reg & 0x2) 3016 *value = (val >> 16) & 0xffff; 3017 else 3018 *value = val & 0xffff; 3019 } 3020 3021 void 3022 em_pci_set_mwi(struct em_hw *hw) 3023 { 3024 struct pci_attach_args *pa = &((struct em_osdep *)hw->back)->em_pa; 3025 3026 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 3027 (hw->pci_cmd_word | CMD_MEM_WRT_INVALIDATE)); 3028 } 3029 3030 void 3031 em_pci_clear_mwi(struct em_hw *hw) 3032 { 3033 struct pci_attach_args *pa = &((struct em_osdep *)hw->back)->em_pa; 3034 3035 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 3036 (hw->pci_cmd_word & ~CMD_MEM_WRT_INVALIDATE)); 3037 } 3038 3039 /* 3040 * We may eventually really do this, but its unnecessary 3041 * for now so we just return unsupported. 3042 */ 3043 int32_t 3044 em_read_pcie_cap_reg(struct em_hw *hw, uint32_t reg, uint16_t *value) 3045 { 3046 return -E1000_NOT_IMPLEMENTED; 3047 } 3048 3049 /********************************************************************* 3050 * 82544 Coexistence issue workaround. 3051 * There are 2 issues. 3052 * 1. Transmit Hang issue. 3053 * To detect this issue, following equation can be used... 3054 * SIZE[3:0] + ADDR[2:0] = SUM[3:0]. 3055 * If SUM[3:0] is in between 1 to 4, we will have this issue. 3056 * 3057 * 2. DAC issue. 3058 * To detect this issue, following equation can be used... 3059 * SIZE[3:0] + ADDR[2:0] = SUM[3:0]. 3060 * If SUM[3:0] is in between 9 to c, we will have this issue. 3061 * 3062 * 3063 * WORKAROUND: 3064 * Make sure we do not have ending address as 1,2,3,4(Hang) or 9,a,b,c (DAC) 3065 * 3066 *** *********************************************************************/ 3067 u_int32_t 3068 em_fill_descriptors(u_int64_t address, u_int32_t length, 3069 PDESC_ARRAY desc_array) 3070 { 3071 /* Since issue is sensitive to length and address.*/ 3072 /* Let us first check the address...*/ 3073 u_int32_t safe_terminator; 3074 if (length <= 4) { 3075 desc_array->descriptor[0].address = address; 3076 desc_array->descriptor[0].length = length; 3077 desc_array->elements = 1; 3078 return desc_array->elements; 3079 } 3080 safe_terminator = (u_int32_t)((((u_int32_t)address & 0x7) + (length & 0xF)) & 0xF); 3081 /* if it does not fall between 0x1 to 0x4 and 0x9 to 0xC then return */ 3082 if (safe_terminator == 0 || 3083 (safe_terminator > 4 && 3084 safe_terminator < 9) || 3085 (safe_terminator > 0xC && 3086 safe_terminator <= 0xF)) { 3087 desc_array->descriptor[0].address = address; 3088 desc_array->descriptor[0].length = length; 3089 desc_array->elements = 1; 3090 return desc_array->elements; 3091 } 3092 3093 desc_array->descriptor[0].address = address; 3094 desc_array->descriptor[0].length = length - 4; 3095 desc_array->descriptor[1].address = address + (length - 4); 3096 desc_array->descriptor[1].length = 4; 3097 desc_array->elements = 2; 3098 return desc_array->elements; 3099 } 3100 3101 /* 3102 * Disable the L0S and L1 LINK states. 3103 */ 3104 void 3105 em_disable_aspm(struct em_softc *sc) 3106 { 3107 int offset; 3108 pcireg_t val; 3109 3110 switch (sc->hw.mac_type) { 3111 case em_82571: 3112 case em_82572: 3113 case em_82573: 3114 case em_82574: 3115 break; 3116 default: 3117 return; 3118 } 3119 3120 if (!pci_get_capability(sc->osdep.em_pa.pa_pc, sc->osdep.em_pa.pa_tag, 3121 PCI_CAP_PCIEXPRESS, &offset, NULL)) 3122 return; 3123 3124 /* Disable PCIe Active State Power Management (ASPM). */ 3125 val = pci_conf_read(sc->osdep.em_pa.pa_pc, sc->osdep.em_pa.pa_tag, 3126 offset + PCI_PCIE_LCSR); 3127 3128 switch (sc->hw.mac_type) { 3129 case em_82571: 3130 case em_82572: 3131 val &= ~PCI_PCIE_LCSR_ASPM_L1; 3132 break; 3133 case em_82573: 3134 case em_82574: 3135 val &= ~(PCI_PCIE_LCSR_ASPM_L0S | 3136 PCI_PCIE_LCSR_ASPM_L1); 3137 break; 3138 default: 3139 break; 3140 } 3141 3142 pci_conf_write(sc->osdep.em_pa.pa_pc, sc->osdep.em_pa.pa_tag, 3143 offset + PCI_PCIE_LCSR, val); 3144 } 3145 3146 /* 3147 * em_flush_tx_ring - remove all descriptors from the tx_ring 3148 * 3149 * We want to clear all pending descriptors from the TX ring. 3150 * zeroing happens when the HW reads the regs. We assign the ring itself as 3151 * the data of the next descriptor. We don't care about the data we are about 3152 * to reset the HW. 3153 */ 3154 void 3155 em_flush_tx_ring(struct em_softc *sc) 3156 { 3157 uint32_t tctl, txd_lower = E1000_TXD_CMD_IFCS; 3158 uint16_t size = 512; 3159 struct em_tx_desc *txd; 3160 3161 KASSERT(sc->sc_tx_desc_ring != NULL); 3162 3163 tctl = EM_READ_REG(&sc->hw, E1000_TCTL); 3164 EM_WRITE_REG(&sc->hw, E1000_TCTL, tctl | E1000_TCTL_EN); 3165 3166 KASSERT(EM_READ_REG(&sc->hw, E1000_TDT) == sc->sc_tx_desc_head); 3167 3168 txd = &sc->sc_tx_desc_ring[sc->sc_tx_desc_head]; 3169 txd->buffer_addr = sc->sc_tx_dma.dma_map->dm_segs[0].ds_addr; 3170 txd->lower.data = htole32(txd_lower | size); 3171 txd->upper.data = 0; 3172 3173 /* flush descriptors to memory before notifying the HW */ 3174 bus_space_barrier(sc->osdep.mem_bus_space_tag, 3175 sc->osdep.mem_bus_space_handle, 0, 0, BUS_SPACE_BARRIER_WRITE); 3176 3177 if (++sc->sc_tx_desc_head == sc->sc_tx_slots) 3178 sc->sc_tx_desc_head = 0; 3179 3180 EM_WRITE_REG(&sc->hw, E1000_TDT, sc->sc_tx_desc_head); 3181 bus_space_barrier(sc->osdep.mem_bus_space_tag, sc->osdep.mem_bus_space_handle, 3182 0, 0, BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE); 3183 usec_delay(250); 3184 } 3185 3186 /* 3187 * em_flush_rx_ring - remove all descriptors from the rx_ring 3188 * 3189 * Mark all descriptors in the RX ring as consumed and disable the rx ring 3190 */ 3191 void 3192 em_flush_rx_ring(struct em_softc *sc) 3193 { 3194 uint32_t rctl, rxdctl; 3195 3196 rctl = EM_READ_REG(&sc->hw, E1000_RCTL); 3197 EM_WRITE_REG(&sc->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 3198 E1000_WRITE_FLUSH(&sc->hw); 3199 usec_delay(150); 3200 3201 rxdctl = EM_READ_REG(&sc->hw, E1000_RXDCTL); 3202 /* zero the lower 14 bits (prefetch and host thresholds) */ 3203 rxdctl &= 0xffffc000; 3204 /* 3205 * update thresholds: prefetch threshold to 31, host threshold to 1 3206 * and make sure the granularity is "descriptors" and not "cache lines" 3207 */ 3208 rxdctl |= (0x1F | (1 << 8) | E1000_RXDCTL_THRESH_UNIT_DESC); 3209 EM_WRITE_REG(&sc->hw, E1000_RXDCTL, rxdctl); 3210 3211 /* momentarily enable the RX ring for the changes to take effect */ 3212 EM_WRITE_REG(&sc->hw, E1000_RCTL, rctl | E1000_RCTL_EN); 3213 E1000_WRITE_FLUSH(&sc->hw); 3214 usec_delay(150); 3215 EM_WRITE_REG(&sc->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 3216 } 3217 3218 /* 3219 * em_flush_desc_rings - remove all descriptors from the descriptor rings 3220 * 3221 * In i219, the descriptor rings must be emptied before resetting the HW 3222 * or before changing the device state to D3 during runtime (runtime PM). 3223 * 3224 * Failure to do this will cause the HW to enter a unit hang state which can 3225 * only be released by PCI reset on the device 3226 * 3227 */ 3228 void 3229 em_flush_desc_rings(struct em_softc *sc) 3230 { 3231 struct pci_attach_args *pa = &sc->osdep.em_pa; 3232 uint32_t fextnvm11, tdlen; 3233 uint16_t hang_state; 3234 3235 /* First, disable MULR fix in FEXTNVM11 */ 3236 fextnvm11 = EM_READ_REG(&sc->hw, E1000_FEXTNVM11); 3237 fextnvm11 |= E1000_FEXTNVM11_DISABLE_MULR_FIX; 3238 EM_WRITE_REG(&sc->hw, E1000_FEXTNVM11, fextnvm11); 3239 3240 /* do nothing if we're not in faulty state, or if the queue is empty */ 3241 tdlen = EM_READ_REG(&sc->hw, E1000_TDLEN); 3242 hang_state = pci_conf_read(pa->pa_pc, pa->pa_tag, PCICFG_DESC_RING_STATUS); 3243 if (!(hang_state & FLUSH_DESC_REQUIRED) || !tdlen) 3244 return; 3245 em_flush_tx_ring(sc); 3246 3247 /* recheck, maybe the fault is caused by the rx ring */ 3248 hang_state = pci_conf_read(pa->pa_pc, pa->pa_tag, PCICFG_DESC_RING_STATUS); 3249 if (hang_state & FLUSH_DESC_REQUIRED) 3250 em_flush_rx_ring(sc); 3251 } 3252 3253 #ifndef SMALL_KERNEL 3254 /********************************************************************** 3255 * 3256 * Update the board statistics counters. 3257 * 3258 **********************************************************************/ 3259 void 3260 em_update_stats_counters(struct em_softc *sc) 3261 { 3262 struct ifnet *ifp = &sc->sc_ac.ac_if; 3263 3264 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, CRCERRS); 3265 sc->stats.mpc += E1000_READ_REG(&sc->hw, MPC); 3266 sc->stats.ecol += E1000_READ_REG(&sc->hw, ECOL); 3267 3268 sc->stats.latecol += E1000_READ_REG(&sc->hw, LATECOL); 3269 sc->stats.colc += E1000_READ_REG(&sc->hw, COLC); 3270 3271 sc->stats.ruc += E1000_READ_REG(&sc->hw, RUC); 3272 sc->stats.roc += E1000_READ_REG(&sc->hw, ROC); 3273 3274 if (sc->hw.mac_type >= em_82543) { 3275 sc->stats.algnerrc += 3276 E1000_READ_REG(&sc->hw, ALGNERRC); 3277 sc->stats.rxerrc += 3278 E1000_READ_REG(&sc->hw, RXERRC); 3279 sc->stats.cexterr += 3280 E1000_READ_REG(&sc->hw, CEXTERR); 3281 } 3282 3283 #ifdef EM_DEBUG 3284 if (sc->hw.media_type == em_media_type_copper || 3285 (E1000_READ_REG(&sc->hw, STATUS) & E1000_STATUS_LU)) { 3286 sc->stats.symerrs += E1000_READ_REG(&sc->hw, SYMERRS); 3287 sc->stats.sec += E1000_READ_REG(&sc->hw, SEC); 3288 } 3289 sc->stats.scc += E1000_READ_REG(&sc->hw, SCC); 3290 3291 sc->stats.mcc += E1000_READ_REG(&sc->hw, MCC); 3292 sc->stats.dc += E1000_READ_REG(&sc->hw, DC); 3293 sc->stats.rlec += E1000_READ_REG(&sc->hw, RLEC); 3294 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, XONRXC); 3295 sc->stats.xontxc += E1000_READ_REG(&sc->hw, XONTXC); 3296 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, XOFFRXC); 3297 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, XOFFTXC); 3298 sc->stats.fcruc += E1000_READ_REG(&sc->hw, FCRUC); 3299 sc->stats.prc64 += E1000_READ_REG(&sc->hw, PRC64); 3300 sc->stats.prc127 += E1000_READ_REG(&sc->hw, PRC127); 3301 sc->stats.prc255 += E1000_READ_REG(&sc->hw, PRC255); 3302 sc->stats.prc511 += E1000_READ_REG(&sc->hw, PRC511); 3303 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, PRC1023); 3304 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, PRC1522); 3305 sc->stats.gprc += E1000_READ_REG(&sc->hw, GPRC); 3306 sc->stats.bprc += E1000_READ_REG(&sc->hw, BPRC); 3307 sc->stats.mprc += E1000_READ_REG(&sc->hw, MPRC); 3308 sc->stats.gptc += E1000_READ_REG(&sc->hw, GPTC); 3309 3310 /* For the 64-bit byte counters the low dword must be read first. */ 3311 /* Both registers clear on the read of the high dword */ 3312 3313 sc->stats.gorcl += E1000_READ_REG(&sc->hw, GORCL); 3314 sc->stats.gorch += E1000_READ_REG(&sc->hw, GORCH); 3315 sc->stats.gotcl += E1000_READ_REG(&sc->hw, GOTCL); 3316 sc->stats.gotch += E1000_READ_REG(&sc->hw, GOTCH); 3317 3318 sc->stats.rnbc += E1000_READ_REG(&sc->hw, RNBC); 3319 sc->stats.rfc += E1000_READ_REG(&sc->hw, RFC); 3320 sc->stats.rjc += E1000_READ_REG(&sc->hw, RJC); 3321 3322 sc->stats.torl += E1000_READ_REG(&sc->hw, TORL); 3323 sc->stats.torh += E1000_READ_REG(&sc->hw, TORH); 3324 sc->stats.totl += E1000_READ_REG(&sc->hw, TOTL); 3325 sc->stats.toth += E1000_READ_REG(&sc->hw, TOTH); 3326 3327 sc->stats.tpr += E1000_READ_REG(&sc->hw, TPR); 3328 sc->stats.tpt += E1000_READ_REG(&sc->hw, TPT); 3329 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, PTC64); 3330 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, PTC127); 3331 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, PTC255); 3332 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, PTC511); 3333 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, PTC1023); 3334 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, PTC1522); 3335 sc->stats.mptc += E1000_READ_REG(&sc->hw, MPTC); 3336 sc->stats.bptc += E1000_READ_REG(&sc->hw, BPTC); 3337 3338 if (sc->hw.mac_type >= em_82543) { 3339 sc->stats.tncrs += 3340 E1000_READ_REG(&sc->hw, TNCRS); 3341 sc->stats.tsctc += 3342 E1000_READ_REG(&sc->hw, TSCTC); 3343 sc->stats.tsctfc += 3344 E1000_READ_REG(&sc->hw, TSCTFC); 3345 } 3346 #endif 3347 3348 /* Fill out the OS statistics structure */ 3349 ifp->if_collisions = sc->stats.colc; 3350 3351 /* Rx Errors */ 3352 ifp->if_ierrors = 3353 sc->dropped_pkts + 3354 sc->stats.rxerrc + 3355 sc->stats.crcerrs + 3356 sc->stats.algnerrc + 3357 sc->stats.ruc + sc->stats.roc + 3358 sc->stats.mpc + sc->stats.cexterr + 3359 sc->rx_overruns; 3360 3361 /* Tx Errors */ 3362 ifp->if_oerrors = sc->stats.ecol + sc->stats.latecol + 3363 sc->watchdog_events; 3364 } 3365 3366 #ifdef EM_DEBUG 3367 /********************************************************************** 3368 * 3369 * This routine is called only when IFF_DEBUG is enabled. 3370 * This routine provides a way to take a look at important statistics 3371 * maintained by the driver and hardware. 3372 * 3373 **********************************************************************/ 3374 void 3375 em_print_hw_stats(struct em_softc *sc) 3376 { 3377 const char * const unit = DEVNAME(sc); 3378 3379 printf("%s: Excessive collisions = %lld\n", unit, 3380 (long long)sc->stats.ecol); 3381 printf("%s: Symbol errors = %lld\n", unit, 3382 (long long)sc->stats.symerrs); 3383 printf("%s: Sequence errors = %lld\n", unit, 3384 (long long)sc->stats.sec); 3385 printf("%s: Defer count = %lld\n", unit, 3386 (long long)sc->stats.dc); 3387 3388 printf("%s: Missed Packets = %lld\n", unit, 3389 (long long)sc->stats.mpc); 3390 printf("%s: Receive No Buffers = %lld\n", unit, 3391 (long long)sc->stats.rnbc); 3392 /* RLEC is inaccurate on some hardware, calculate our own */ 3393 printf("%s: Receive Length Errors = %lld\n", unit, 3394 ((long long)sc->stats.roc + 3395 (long long)sc->stats.ruc)); 3396 printf("%s: Receive errors = %lld\n", unit, 3397 (long long)sc->stats.rxerrc); 3398 printf("%s: Crc errors = %lld\n", unit, 3399 (long long)sc->stats.crcerrs); 3400 printf("%s: Alignment errors = %lld\n", unit, 3401 (long long)sc->stats.algnerrc); 3402 printf("%s: Carrier extension errors = %lld\n", unit, 3403 (long long)sc->stats.cexterr); 3404 3405 printf("%s: RX overruns = %ld\n", unit, 3406 sc->rx_overruns); 3407 printf("%s: watchdog timeouts = %ld\n", unit, 3408 sc->watchdog_events); 3409 3410 printf("%s: XON Rcvd = %lld\n", unit, 3411 (long long)sc->stats.xonrxc); 3412 printf("%s: XON Xmtd = %lld\n", unit, 3413 (long long)sc->stats.xontxc); 3414 printf("%s: XOFF Rcvd = %lld\n", unit, 3415 (long long)sc->stats.xoffrxc); 3416 printf("%s: XOFF Xmtd = %lld\n", unit, 3417 (long long)sc->stats.xofftxc); 3418 3419 printf("%s: Good Packets Rcvd = %lld\n", unit, 3420 (long long)sc->stats.gprc); 3421 printf("%s: Good Packets Xmtd = %lld\n", unit, 3422 (long long)sc->stats.gptc); 3423 } 3424 #endif 3425 #endif /* !SMALL_KERNEL */ 3426