1 /************************************************************************** 2 3 Copyright (c) 2001-2003, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ***************************************************************************/ 33 34 /* $OpenBSD: if_em.c,v 1.207 2009/01/27 09:17:51 dlg Exp $ */ 35 /* $FreeBSD: if_em.c,v 1.46 2004/09/29 18:28:28 mlaier Exp $ */ 36 37 #include <dev/pci/if_em.h> 38 39 #ifdef EM_DEBUG 40 /********************************************************************* 41 * Set this to one to display debug statistics 42 *********************************************************************/ 43 int em_display_debug_stats = 0; 44 #endif 45 46 /********************************************************************* 47 * Driver version 48 *********************************************************************/ 49 50 #define EM_DRIVER_VERSION "6.2.9" 51 52 /********************************************************************* 53 * PCI Device ID Table 54 *********************************************************************/ 55 const struct pci_matchid em_devices[] = { 56 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80003ES2LAN_CPR_DPT }, 57 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80003ES2LAN_SDS_DPT }, 58 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80003ES2LAN_CPR_SPT }, 59 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80003ES2LAN_SDS_SPT }, 60 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM }, 61 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM_LOM }, 62 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP }, 63 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LOM }, 64 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LP }, 65 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI }, 66 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI_MOBILE }, 67 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541ER }, 68 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541ER_LOM }, 69 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI }, 70 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI_LF }, 71 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI_MOBILE }, 72 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82542 }, 73 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_COPPER }, 74 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_FIBER }, 75 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_COPPER }, 76 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_FIBER }, 77 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_COPPER }, 78 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_LOM }, 79 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_COPPER }, 80 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_FIBER }, 81 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_COPPER }, 82 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_FIBER }, 83 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_SERDES }, 84 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_COPPER }, 85 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_FIBER }, 86 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_QUAD_CPR }, 87 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_COPPER }, 88 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_FIBER }, 89 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_PCIE }, 90 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_QUAD_CPR }, 91 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_QUAD_CPR_K }, 92 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_SERDES }, 93 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_2 }, 94 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547EI }, 95 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547EI_MOBILE }, 96 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547GI }, 97 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_AF }, 98 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_AT }, 99 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_COPPER }, 100 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_FIBER }, 101 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_QUAD_CPR }, 102 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_QUAD_CPR_LP }, 103 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_QUAD_FBR }, 104 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_SERDES }, 105 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_SDS_DUAL }, 106 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_SDS_QUAD }, 107 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571PT_QUAD_CPR }, 108 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI_COPPER }, 109 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI_FIBER }, 110 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI_SERDES }, 111 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI }, 112 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573E }, 113 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573E_IAMT }, 114 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573E_PM }, 115 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573L }, 116 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573L_PL_1 }, 117 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573L_PL_2 }, 118 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573V_PM }, 119 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_IFE }, 120 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_IFE_G }, 121 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_IFE_GT }, 122 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_IGP_AMT }, 123 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_IGP_C }, 124 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_IGP_M }, 125 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_IGP_M_AMT }, 126 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IFE }, 127 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IFE_G }, 128 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IFE_GT }, 129 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IGP_AMT }, 130 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IGP_C }, 131 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IGP_M }, 132 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IGP_M_AMT } 133 }; 134 135 /********************************************************************* 136 * Function prototypes 137 *********************************************************************/ 138 int em_probe(struct device *, void *, void *); 139 void em_attach(struct device *, struct device *, void *); 140 void em_shutdown(void *); 141 int em_intr(void *); 142 void em_power(int, void *); 143 void em_start(struct ifnet *); 144 int em_ioctl(struct ifnet *, u_long, caddr_t); 145 void em_watchdog(struct ifnet *); 146 void em_init(void *); 147 void em_stop(void *); 148 void em_media_status(struct ifnet *, struct ifmediareq *); 149 int em_media_change(struct ifnet *); 150 int em_flowstatus(struct em_softc *); 151 void em_identify_hardware(struct em_softc *); 152 int em_allocate_pci_resources(struct em_softc *); 153 void em_free_pci_resources(struct em_softc *); 154 void em_local_timer(void *); 155 int em_hardware_init(struct em_softc *); 156 void em_setup_interface(struct em_softc *); 157 int em_setup_transmit_structures(struct em_softc *); 158 void em_initialize_transmit_unit(struct em_softc *); 159 int em_setup_receive_structures(struct em_softc *); 160 void em_initialize_receive_unit(struct em_softc *); 161 void em_enable_intr(struct em_softc *); 162 void em_disable_intr(struct em_softc *); 163 void em_free_transmit_structures(struct em_softc *); 164 void em_free_receive_structures(struct em_softc *); 165 void em_update_stats_counters(struct em_softc *); 166 void em_txeof(struct em_softc *); 167 int em_allocate_receive_structures(struct em_softc *); 168 int em_allocate_transmit_structures(struct em_softc *); 169 #ifdef __STRICT_ALIGNMENT 170 void em_realign(struct em_softc *, struct mbuf *, u_int16_t *); 171 #else 172 #define em_realign(a, b, c) /* a, b, c */ 173 #endif 174 int em_rxfill(struct em_softc *); 175 void em_rxeof(struct em_softc *, int); 176 void em_receive_checksum(struct em_softc *, struct em_rx_desc *, 177 struct mbuf *); 178 #ifdef EM_CSUM_OFFLOAD 179 void em_transmit_checksum_setup(struct em_softc *, struct mbuf *, 180 u_int32_t *, u_int32_t *); 181 #endif 182 void em_set_promisc(struct em_softc *); 183 void em_set_multi(struct em_softc *); 184 #ifdef EM_DEBUG 185 void em_print_hw_stats(struct em_softc *); 186 #endif 187 void em_update_link_status(struct em_softc *); 188 int em_get_buf(struct em_softc *, int); 189 void em_enable_hw_vlans(struct em_softc *); 190 int em_encap(struct em_softc *, struct mbuf *); 191 void em_smartspeed(struct em_softc *); 192 int em_82547_fifo_workaround(struct em_softc *, int); 193 void em_82547_update_fifo_head(struct em_softc *, int); 194 int em_82547_tx_fifo_reset(struct em_softc *); 195 void em_82547_move_tail(void *arg); 196 void em_82547_move_tail_locked(struct em_softc *); 197 int em_dma_malloc(struct em_softc *, bus_size_t, struct em_dma_alloc *, 198 int); 199 void em_dma_free(struct em_softc *, struct em_dma_alloc *); 200 int em_is_valid_ether_addr(u_int8_t *); 201 u_int32_t em_fill_descriptors(u_int64_t address, u_int32_t length, 202 PDESC_ARRAY desc_array); 203 204 /********************************************************************* 205 * OpenBSD Device Interface Entry Points 206 *********************************************************************/ 207 208 struct cfattach em_ca = { 209 sizeof(struct em_softc), em_probe, em_attach 210 }; 211 212 struct cfdriver em_cd = { 213 0, "em", DV_IFNET 214 }; 215 216 static int em_smart_pwr_down = FALSE; 217 218 /********************************************************************* 219 * Device identification routine 220 * 221 * em_probe determines if the driver should be loaded on 222 * adapter based on PCI vendor/device id of the adapter. 223 * 224 * return 0 on no match, positive on match 225 *********************************************************************/ 226 227 int 228 em_probe(struct device *parent, void *match, void *aux) 229 { 230 INIT_DEBUGOUT("em_probe: begin"); 231 232 return (pci_matchbyid((struct pci_attach_args *)aux, em_devices, 233 sizeof(em_devices)/sizeof(em_devices[0]))); 234 } 235 236 /********************************************************************* 237 * Device initialization routine 238 * 239 * The attach entry point is called when the driver is being loaded. 240 * This routine identifies the type of hardware, allocates all resources 241 * and initializes the hardware. 242 * 243 *********************************************************************/ 244 245 void 246 em_attach(struct device *parent, struct device *self, void *aux) 247 { 248 struct pci_attach_args *pa = aux; 249 struct em_softc *sc; 250 int tsize, rsize; 251 252 INIT_DEBUGOUT("em_attach: begin"); 253 254 sc = (struct em_softc *)self; 255 sc->osdep.em_pa = *pa; 256 257 timeout_set(&sc->timer_handle, em_local_timer, sc); 258 timeout_set(&sc->tx_fifo_timer_handle, em_82547_move_tail, sc); 259 260 /* Determine hardware revision */ 261 em_identify_hardware(sc); 262 263 /* Parameters (to be read from user) */ 264 if (sc->hw.mac_type >= em_82544) { 265 sc->num_tx_desc = EM_MAX_TXD; 266 sc->num_rx_desc = EM_MAX_RXD; 267 } else { 268 sc->num_tx_desc = EM_MAX_TXD_82543; 269 sc->num_rx_desc = EM_MAX_RXD_82543; 270 } 271 sc->tx_int_delay = EM_TIDV; 272 sc->tx_abs_int_delay = EM_TADV; 273 sc->rx_int_delay = EM_RDTR; 274 sc->rx_abs_int_delay = EM_RADV; 275 sc->hw.autoneg = DO_AUTO_NEG; 276 sc->hw.wait_autoneg_complete = WAIT_FOR_AUTO_NEG_DEFAULT; 277 sc->hw.autoneg_advertised = AUTONEG_ADV_DEFAULT; 278 sc->hw.tbi_compatibility_en = TRUE; 279 sc->rx_buffer_len = EM_RXBUFFER_2048; 280 281 sc->hw.phy_init_script = 1; 282 sc->hw.phy_reset_disable = FALSE; 283 284 #ifndef EM_MASTER_SLAVE 285 sc->hw.master_slave = em_ms_hw_default; 286 #else 287 sc->hw.master_slave = EM_MASTER_SLAVE; 288 #endif 289 290 /* 291 * This controls when hardware reports transmit completion 292 * status. 293 */ 294 sc->hw.report_tx_early = 1; 295 296 if (em_allocate_pci_resources(sc)) { 297 printf("%s: Allocation of PCI resources failed\n", 298 sc->sc_dv.dv_xname); 299 goto err_pci; 300 } 301 302 /* Initialize eeprom parameters */ 303 em_init_eeprom_params(&sc->hw); 304 305 /* 306 * Set the max frame size assuming standard Ethernet 307 * sized frames. 308 */ 309 switch (sc->hw.mac_type) { 310 case em_82573: 311 { 312 uint16_t eeprom_data = 0; 313 314 /* 315 * 82573 only supports Jumbo frames 316 * if ASPM is disabled. 317 */ 318 em_read_eeprom(&sc->hw, EEPROM_INIT_3GIO_3, 319 1, &eeprom_data); 320 if (eeprom_data & EEPROM_WORD1A_ASPM_MASK) { 321 sc->hw.max_frame_size = ETHER_MAX_LEN; 322 break; 323 } 324 /* Allow Jumbo frames - FALLTHROUGH */ 325 } 326 case em_82571: 327 case em_82572: 328 case em_ich9lan: 329 case em_80003es2lan: /* Limit Jumbo Frame size */ 330 sc->hw.max_frame_size = 9234; 331 break; 332 /* Adapters that do not support Jumbo frames */ 333 case em_82542_rev2_0: 334 case em_82542_rev2_1: 335 case em_ich8lan: 336 sc->hw.max_frame_size = ETHER_MAX_LEN; 337 break; 338 default: 339 sc->hw.max_frame_size = 340 MAX_JUMBO_FRAME_SIZE; 341 } 342 343 sc->hw.min_frame_size = 344 ETHER_MIN_LEN + ETHER_CRC_LEN; 345 346 if (sc->hw.mac_type >= em_82544) 347 tsize = EM_ROUNDUP(sc->num_tx_desc * sizeof(struct em_tx_desc), 348 EM_MAX_TXD * sizeof(struct em_tx_desc)); 349 else 350 tsize = EM_ROUNDUP(sc->num_tx_desc * sizeof(struct em_tx_desc), 351 EM_MAX_TXD_82543 * sizeof(struct em_tx_desc)); 352 tsize = EM_ROUNDUP(tsize, PAGE_SIZE); 353 354 /* Allocate Transmit Descriptor ring */ 355 if (em_dma_malloc(sc, tsize, &sc->txdma, BUS_DMA_NOWAIT)) { 356 printf("%s: Unable to allocate tx_desc memory\n", 357 sc->sc_dv.dv_xname); 358 goto err_tx_desc; 359 } 360 sc->tx_desc_base = (struct em_tx_desc *)sc->txdma.dma_vaddr; 361 362 if (sc->hw.mac_type >= em_82544) 363 rsize = EM_ROUNDUP(sc->num_rx_desc * sizeof(struct em_rx_desc), 364 EM_MAX_RXD * sizeof(struct em_rx_desc)); 365 else 366 rsize = EM_ROUNDUP(sc->num_rx_desc * sizeof(struct em_rx_desc), 367 EM_MAX_RXD_82543 * sizeof(struct em_rx_desc)); 368 rsize = EM_ROUNDUP(rsize, PAGE_SIZE); 369 370 /* Allocate Receive Descriptor ring */ 371 if (em_dma_malloc(sc, rsize, &sc->rxdma, BUS_DMA_NOWAIT)) { 372 printf("%s: Unable to allocate rx_desc memory\n", 373 sc->sc_dv.dv_xname); 374 goto err_rx_desc; 375 } 376 sc->rx_desc_base = (struct em_rx_desc *) sc->rxdma.dma_vaddr; 377 378 /* Initialize the hardware */ 379 if (em_hardware_init(sc)) { 380 printf("%s: Unable to initialize the hardware\n", 381 sc->sc_dv.dv_xname); 382 goto err_hw_init; 383 } 384 385 /* Copy the permanent MAC address out of the EEPROM */ 386 if (em_read_mac_addr(&sc->hw) < 0) { 387 printf("%s: EEPROM read error while reading mac address\n", 388 sc->sc_dv.dv_xname); 389 goto err_mac_addr; 390 } 391 392 if (!em_is_valid_ether_addr(sc->hw.mac_addr)) { 393 printf("%s: Invalid mac address\n", sc->sc_dv.dv_xname); 394 goto err_mac_addr; 395 } 396 397 bcopy(sc->hw.mac_addr, sc->interface_data.ac_enaddr, 398 ETHER_ADDR_LEN); 399 400 /* Setup OS specific network interface */ 401 em_setup_interface(sc); 402 403 /* Initialize statistics */ 404 em_clear_hw_cntrs(&sc->hw); 405 em_update_stats_counters(sc); 406 sc->hw.get_link_status = 1; 407 em_update_link_status(sc); 408 409 printf(", address %s\n", ether_sprintf(sc->interface_data.ac_enaddr)); 410 411 /* Indicate SOL/IDER usage */ 412 if (em_check_phy_reset_block(&sc->hw)) 413 printf("%s: PHY reset is blocked due to SOL/IDER session.\n", 414 sc->sc_dv.dv_xname); 415 416 /* Identify 82544 on PCI-X */ 417 em_get_bus_info(&sc->hw); 418 if (sc->hw.bus_type == em_bus_type_pcix && 419 sc->hw.mac_type == em_82544) 420 sc->pcix_82544 = TRUE; 421 else 422 sc->pcix_82544 = FALSE; 423 INIT_DEBUGOUT("em_attach: end"); 424 sc->sc_powerhook = powerhook_establish(em_power, sc); 425 sc->sc_shutdownhook = shutdownhook_establish(em_shutdown, sc); 426 return; 427 428 err_mac_addr: 429 err_hw_init: 430 em_dma_free(sc, &sc->rxdma); 431 err_rx_desc: 432 em_dma_free(sc, &sc->txdma); 433 err_tx_desc: 434 err_pci: 435 em_free_pci_resources(sc); 436 } 437 438 void 439 em_power(int why, void *arg) 440 { 441 struct em_softc *sc = (struct em_softc *)arg; 442 struct ifnet *ifp; 443 444 if (why == PWR_RESUME) { 445 ifp = &sc->interface_data.ac_if; 446 if (ifp->if_flags & IFF_UP) 447 em_init(sc); 448 } 449 } 450 451 /********************************************************************* 452 * 453 * Shutdown entry point 454 * 455 **********************************************************************/ 456 457 void 458 em_shutdown(void *arg) 459 { 460 struct em_softc *sc = arg; 461 462 em_stop(sc); 463 } 464 465 /********************************************************************* 466 * Transmit entry point 467 * 468 * em_start is called by the stack to initiate a transmit. 469 * The driver will remain in this routine as long as there are 470 * packets to transmit and transmit resources are available. 471 * In case resources are not available stack is notified and 472 * the packet is requeued. 473 **********************************************************************/ 474 475 void 476 em_start(struct ifnet *ifp) 477 { 478 struct mbuf *m_head; 479 struct em_softc *sc = ifp->if_softc; 480 int post = 0; 481 482 if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING) 483 return; 484 485 if (!sc->link_active) 486 return; 487 488 if (sc->hw.mac_type != em_82547) { 489 bus_dmamap_sync(sc->txdma.dma_tag, sc->txdma.dma_map, 0, 490 sc->txdma.dma_map->dm_mapsize, 491 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 492 } 493 494 for (;;) { 495 IFQ_POLL(&ifp->if_snd, m_head); 496 if (m_head == NULL) 497 break; 498 499 if (em_encap(sc, m_head)) { 500 ifp->if_flags |= IFF_OACTIVE; 501 break; 502 } 503 504 IFQ_DEQUEUE(&ifp->if_snd, m_head); 505 506 #if NBPFILTER > 0 507 /* Send a copy of the frame to the BPF listener */ 508 if (ifp->if_bpf) 509 bpf_mtap_ether(ifp->if_bpf, m_head, BPF_DIRECTION_OUT); 510 #endif 511 512 /* Set timeout in case hardware has problems transmitting */ 513 ifp->if_timer = EM_TX_TIMEOUT; 514 515 post = 1; 516 } 517 518 if (sc->hw.mac_type != em_82547) { 519 bus_dmamap_sync(sc->txdma.dma_tag, sc->txdma.dma_map, 0, 520 sc->txdma.dma_map->dm_mapsize, 521 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 522 /* 523 * Advance the Transmit Descriptor Tail (Tdt), 524 * this tells the E1000 that this frame is 525 * available to transmit. 526 */ 527 if (post) 528 E1000_WRITE_REG(&sc->hw, TDT, sc->next_avail_tx_desc); 529 } 530 } 531 532 /********************************************************************* 533 * Ioctl entry point 534 * 535 * em_ioctl is called when the user wants to configure the 536 * interface. 537 * 538 * return 0 on success, positive on failure 539 **********************************************************************/ 540 541 int 542 em_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 543 { 544 int error = 0; 545 struct ifreq *ifr = (struct ifreq *) data; 546 struct ifaddr *ifa = (struct ifaddr *)data; 547 struct em_softc *sc = ifp->if_softc; 548 int s; 549 550 s = splnet(); 551 552 switch (command) { 553 case SIOCSIFADDR: 554 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFADDR (Set Interface " 555 "Addr)"); 556 if (!(ifp->if_flags & IFF_UP)) { 557 ifp->if_flags |= IFF_UP; 558 em_init(sc); 559 } 560 #ifdef INET 561 if (ifa->ifa_addr->sa_family == AF_INET) 562 arp_ifinit(&sc->interface_data, ifa); 563 #endif /* INET */ 564 break; 565 566 case SIOCSIFFLAGS: 567 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFFLAGS (Set Interface Flags)"); 568 if (ifp->if_flags & IFF_UP) { 569 /* 570 * If only the PROMISC or ALLMULTI flag changes, then 571 * don't do a full re-init of the chip, just update 572 * the Rx filter. 573 */ 574 if ((ifp->if_flags & IFF_RUNNING) && 575 ((ifp->if_flags ^ sc->if_flags) & 576 (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 577 em_set_promisc(sc); 578 } else { 579 if (!(ifp->if_flags & IFF_RUNNING)) 580 em_init(sc); 581 } 582 } else { 583 if (ifp->if_flags & IFF_RUNNING) 584 em_stop(sc); 585 } 586 sc->if_flags = ifp->if_flags; 587 break; 588 589 case SIOCSIFMEDIA: 590 /* Check SOL/IDER usage */ 591 if (em_check_phy_reset_block(&sc->hw)) { 592 printf("%s: Media change is blocked due to SOL/IDER session.\n", 593 sc->sc_dv.dv_xname); 594 break; 595 } 596 case SIOCGIFMEDIA: 597 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCxIFMEDIA (Get/Set Interface Media)"); 598 error = ifmedia_ioctl(ifp, ifr, &sc->media, command); 599 break; 600 601 default: 602 error = ether_ioctl(ifp, &sc->interface_data, command, data); 603 } 604 605 if (error == ENETRESET) { 606 if (ifp->if_flags & IFF_RUNNING) { 607 em_disable_intr(sc); 608 em_set_multi(sc); 609 if (sc->hw.mac_type == em_82542_rev2_0) 610 em_initialize_receive_unit(sc); 611 em_enable_intr(sc); 612 } 613 error = 0; 614 } 615 616 splx(s); 617 return (error); 618 } 619 620 /********************************************************************* 621 * Watchdog entry point 622 * 623 * This routine is called whenever hardware quits transmitting. 624 * 625 **********************************************************************/ 626 627 void 628 em_watchdog(struct ifnet *ifp) 629 { 630 struct em_softc *sc = ifp->if_softc; 631 632 /* If we are in this routine because of pause frames, then 633 * don't reset the hardware. 634 */ 635 if (E1000_READ_REG(&sc->hw, STATUS) & E1000_STATUS_TXOFF) { 636 ifp->if_timer = EM_TX_TIMEOUT; 637 return; 638 } 639 640 printf("%s: watchdog timeout -- resetting\n", sc->sc_dv.dv_xname); 641 642 em_init(sc); 643 644 sc->watchdog_events++; 645 } 646 647 /********************************************************************* 648 * Init entry point 649 * 650 * This routine is used in two ways. It is used by the stack as 651 * init entry point in network interface structure. It is also used 652 * by the driver as a hw/sw initialization routine to get to a 653 * consistent state. 654 * 655 **********************************************************************/ 656 657 void 658 em_init(void *arg) 659 { 660 struct em_softc *sc = arg; 661 struct ifnet *ifp = &sc->interface_data.ac_if; 662 uint32_t pba; 663 int s; 664 665 s = splnet(); 666 667 INIT_DEBUGOUT("em_init: begin"); 668 669 em_stop(sc); 670 671 /* 672 * Packet Buffer Allocation (PBA) 673 * Writing PBA sets the receive portion of the buffer 674 * the remainder is used for the transmit buffer. 675 * 676 * Devices before the 82547 had a Packet Buffer of 64K. 677 * Default allocation: PBA=48K for Rx, leaving 16K for Tx. 678 * After the 82547 the buffer was reduced to 40K. 679 * Default allocation: PBA=30K for Rx, leaving 10K for Tx. 680 * Note: default does not leave enough room for Jumbo Frame >10k. 681 */ 682 switch (sc->hw.mac_type) { 683 case em_82547: 684 case em_82547_rev_2: /* 82547: Total Packet Buffer is 40K */ 685 if (sc->hw.max_frame_size > EM_RXBUFFER_8192) 686 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 687 else 688 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 689 sc->tx_fifo_head = 0; 690 sc->tx_head_addr = pba << EM_TX_HEAD_ADDR_SHIFT; 691 sc->tx_fifo_size = (E1000_PBA_40K - pba) << EM_PBA_BYTES_SHIFT; 692 break; 693 case em_82571: 694 case em_82572: /* Total Packet Buffer on these is 48k */ 695 case em_80003es2lan: 696 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 697 break; 698 case em_82573: /* 82573: Total Packet Buffer is 32K */ 699 /* Jumbo frames not supported */ 700 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 701 break; 702 case em_ich8lan: 703 pba = E1000_PBA_8K; 704 break; 705 case em_ich9lan: 706 pba = E1000_PBA_10K; 707 break; 708 default: 709 /* Devices before 82547 had a Packet Buffer of 64K. */ 710 if (sc->hw.max_frame_size > EM_RXBUFFER_8192) 711 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 712 else 713 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 714 } 715 INIT_DEBUGOUT1("em_init: pba=%dK",pba); 716 E1000_WRITE_REG(&sc->hw, PBA, pba); 717 718 /* Get the latest mac address, User can use a LAA */ 719 bcopy(sc->interface_data.ac_enaddr, sc->hw.mac_addr, 720 ETHER_ADDR_LEN); 721 722 /* Initialize the hardware */ 723 if (em_hardware_init(sc)) { 724 printf("%s: Unable to initialize the hardware\n", 725 sc->sc_dv.dv_xname); 726 splx(s); 727 return; 728 } 729 em_update_link_status(sc); 730 731 E1000_WRITE_REG(&sc->hw, VET, ETHERTYPE_VLAN); 732 if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) 733 em_enable_hw_vlans(sc); 734 735 /* Prepare transmit descriptors and buffers */ 736 if (em_setup_transmit_structures(sc)) { 737 printf("%s: Could not setup transmit structures\n", 738 sc->sc_dv.dv_xname); 739 em_stop(sc); 740 splx(s); 741 return; 742 } 743 em_initialize_transmit_unit(sc); 744 745 /* Setup Multicast table */ 746 em_set_multi(sc); 747 748 /* Prepare receive descriptors and buffers */ 749 if (em_setup_receive_structures(sc)) { 750 printf("%s: Could not setup receive structures\n", 751 sc->sc_dv.dv_xname); 752 em_stop(sc); 753 splx(s); 754 return; 755 } 756 em_initialize_receive_unit(sc); 757 758 /* Don't lose promiscuous settings */ 759 em_set_promisc(sc); 760 761 ifp->if_flags |= IFF_RUNNING; 762 ifp->if_flags &= ~IFF_OACTIVE; 763 764 timeout_add_sec(&sc->timer_handle, 1); 765 em_clear_hw_cntrs(&sc->hw); 766 em_enable_intr(sc); 767 768 /* Don't reset the phy next time init gets called */ 769 sc->hw.phy_reset_disable = TRUE; 770 771 splx(s); 772 } 773 774 /********************************************************************* 775 * 776 * Interrupt Service routine 777 * 778 **********************************************************************/ 779 int 780 em_intr(void *arg) 781 { 782 struct em_softc *sc = arg; 783 struct ifnet *ifp; 784 u_int32_t reg_icr, test_icr; 785 int claimed = 0; 786 int refill; 787 788 ifp = &sc->interface_data.ac_if; 789 790 for (;;) { 791 test_icr = reg_icr = E1000_READ_REG(&sc->hw, ICR); 792 if (sc->hw.mac_type >= em_82571) 793 test_icr = (reg_icr & E1000_ICR_INT_ASSERTED); 794 if (!test_icr) 795 break; 796 797 claimed = 1; 798 refill = 0; 799 800 if (ifp->if_flags & IFF_RUNNING) { 801 em_rxeof(sc, -1); 802 em_txeof(sc); 803 refill = 1; 804 } 805 806 /* Link status change */ 807 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 808 timeout_del(&sc->timer_handle); 809 sc->hw.get_link_status = 1; 810 em_check_for_link(&sc->hw); 811 em_update_link_status(sc); 812 timeout_add_sec(&sc->timer_handle, 1); 813 } 814 815 if (reg_icr & E1000_ICR_RXO) { 816 sc->rx_overruns++; 817 ifp->if_ierrors++; 818 refill = 1; 819 } 820 821 if (refill && em_rxfill(sc)) { 822 /* Advance the Rx Queue #0 "Tail Pointer". */ 823 E1000_WRITE_REG(&sc->hw, RDT, sc->last_rx_desc_filled); 824 } 825 } 826 827 if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd)) 828 em_start(ifp); 829 830 return (claimed); 831 } 832 833 /********************************************************************* 834 * 835 * Media Ioctl callback 836 * 837 * This routine is called whenever the user queries the status of 838 * the interface using ifconfig. 839 * 840 **********************************************************************/ 841 void 842 em_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 843 { 844 struct em_softc *sc = ifp->if_softc; 845 u_char fiber_type = IFM_1000_SX; 846 u_int16_t gsr; 847 848 INIT_DEBUGOUT("em_media_status: begin"); 849 850 em_check_for_link(&sc->hw); 851 em_update_link_status(sc); 852 853 ifmr->ifm_status = IFM_AVALID; 854 ifmr->ifm_active = IFM_ETHER; 855 856 if (!sc->link_active) { 857 ifmr->ifm_active |= IFM_NONE; 858 return; 859 } 860 861 ifmr->ifm_status |= IFM_ACTIVE; 862 863 if (sc->hw.media_type == em_media_type_fiber || 864 sc->hw.media_type == em_media_type_internal_serdes) { 865 if (sc->hw.mac_type == em_82545) 866 fiber_type = IFM_1000_LX; 867 ifmr->ifm_active |= fiber_type | IFM_FDX; 868 } else { 869 switch (sc->link_speed) { 870 case 10: 871 ifmr->ifm_active |= IFM_10_T; 872 break; 873 case 100: 874 ifmr->ifm_active |= IFM_100_TX; 875 break; 876 case 1000: 877 ifmr->ifm_active |= IFM_1000_T; 878 break; 879 } 880 881 if (sc->link_duplex == FULL_DUPLEX) 882 ifmr->ifm_active |= em_flowstatus(sc) | IFM_FDX; 883 else 884 ifmr->ifm_active |= IFM_HDX; 885 886 if (IFM_SUBTYPE(ifmr->ifm_active) == IFM_1000_T) { 887 em_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &gsr); 888 if (gsr & SR_1000T_MS_CONFIG_RES) 889 ifmr->ifm_active |= IFM_ETH_MASTER; 890 } 891 } 892 } 893 894 /********************************************************************* 895 * 896 * Media Ioctl callback 897 * 898 * This routine is called when the user changes speed/duplex using 899 * media/mediopt option with ifconfig. 900 * 901 **********************************************************************/ 902 int 903 em_media_change(struct ifnet *ifp) 904 { 905 struct em_softc *sc = ifp->if_softc; 906 struct ifmedia *ifm = &sc->media; 907 908 INIT_DEBUGOUT("em_media_change: begin"); 909 910 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 911 return (EINVAL); 912 913 switch (IFM_SUBTYPE(ifm->ifm_media)) { 914 case IFM_AUTO: 915 sc->hw.autoneg = DO_AUTO_NEG; 916 sc->hw.autoneg_advertised = AUTONEG_ADV_DEFAULT; 917 break; 918 case IFM_1000_LX: 919 case IFM_1000_SX: 920 case IFM_1000_T: 921 sc->hw.autoneg = DO_AUTO_NEG; 922 sc->hw.autoneg_advertised = ADVERTISE_1000_FULL; 923 break; 924 case IFM_100_TX: 925 sc->hw.autoneg = FALSE; 926 sc->hw.autoneg_advertised = 0; 927 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 928 sc->hw.forced_speed_duplex = em_100_full; 929 else 930 sc->hw.forced_speed_duplex = em_100_half; 931 break; 932 case IFM_10_T: 933 sc->hw.autoneg = FALSE; 934 sc->hw.autoneg_advertised = 0; 935 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 936 sc->hw.forced_speed_duplex = em_10_full; 937 else 938 sc->hw.forced_speed_duplex = em_10_half; 939 break; 940 default: 941 printf("%s: Unsupported media type\n", sc->sc_dv.dv_xname); 942 } 943 944 /* 945 * As the speed/duplex settings may have changed we need to 946 * reset the PHY. 947 */ 948 sc->hw.phy_reset_disable = FALSE; 949 950 em_init(sc); 951 952 return (0); 953 } 954 955 int 956 em_flowstatus(struct em_softc *sc) 957 { 958 u_int16_t ar, lpar; 959 960 if (sc->hw.media_type == em_media_type_fiber || 961 sc->hw.media_type == em_media_type_internal_serdes) 962 return (0); 963 964 em_read_phy_reg(&sc->hw, PHY_AUTONEG_ADV, &ar); 965 em_read_phy_reg(&sc->hw, PHY_LP_ABILITY, &lpar); 966 967 if ((ar & NWAY_AR_PAUSE) && (lpar & NWAY_LPAR_PAUSE)) 968 return (IFM_FLOW|IFM_ETH_TXPAUSE|IFM_ETH_RXPAUSE); 969 else if (!(ar & NWAY_AR_PAUSE) && (ar & NWAY_AR_ASM_DIR) && 970 (lpar & NWAY_LPAR_PAUSE) && (lpar & NWAY_LPAR_ASM_DIR)) 971 return (IFM_FLOW|IFM_ETH_TXPAUSE); 972 else if ((ar & NWAY_AR_PAUSE) && (ar & NWAY_AR_ASM_DIR) && 973 !(lpar & NWAY_LPAR_PAUSE) && (lpar & NWAY_LPAR_ASM_DIR)) 974 return (IFM_FLOW|IFM_ETH_RXPAUSE); 975 976 return (0); 977 } 978 979 /********************************************************************* 980 * 981 * This routine maps the mbufs to tx descriptors. 982 * 983 * return 0 on success, positive on failure 984 **********************************************************************/ 985 int 986 em_encap(struct em_softc *sc, struct mbuf *m_head) 987 { 988 u_int32_t txd_upper; 989 u_int32_t txd_lower, txd_used = 0, txd_saved = 0; 990 int i, j, first, error = 0, last = 0; 991 bus_dmamap_t map; 992 993 /* For 82544 Workaround */ 994 DESC_ARRAY desc_array; 995 u_int32_t array_elements; 996 u_int32_t counter; 997 998 struct em_buffer *tx_buffer, *tx_buffer_mapped; 999 struct em_tx_desc *current_tx_desc = NULL; 1000 1001 /* 1002 * Force a cleanup if number of TX descriptors 1003 * available hits the threshold 1004 */ 1005 if (sc->num_tx_desc_avail <= EM_TX_CLEANUP_THRESHOLD) { 1006 em_txeof(sc); 1007 /* Now do we at least have a minimal? */ 1008 if (sc->num_tx_desc_avail <= EM_TX_OP_THRESHOLD) { 1009 sc->no_tx_desc_avail1++; 1010 return (ENOBUFS); 1011 } 1012 } 1013 1014 if (sc->hw.mac_type == em_82547) { 1015 bus_dmamap_sync(sc->txdma.dma_tag, sc->txdma.dma_map, 0, 1016 sc->txdma.dma_map->dm_mapsize, 1017 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1018 } 1019 1020 /* 1021 * Map the packet for DMA. 1022 * 1023 * Capture the first descriptor index, 1024 * this descriptor will have the index 1025 * of the EOP which is the only one that 1026 * no gets a DONE bit writeback. 1027 */ 1028 first = sc->next_avail_tx_desc; 1029 tx_buffer = &sc->tx_buffer_area[first]; 1030 tx_buffer_mapped = tx_buffer; 1031 map = tx_buffer->map; 1032 1033 error = bus_dmamap_load_mbuf(sc->txtag, map, m_head, BUS_DMA_NOWAIT); 1034 if (error != 0) { 1035 sc->no_tx_dma_setup++; 1036 goto loaderr; 1037 } 1038 EM_KASSERT(map->dm_nsegs!= 0, ("em_encap: empty packet")); 1039 1040 if (map->dm_nsegs > sc->num_tx_desc_avail - 2) 1041 goto fail; 1042 1043 #ifdef EM_CSUM_OFFLOAD 1044 if (sc->hw.mac_type >= em_82543) 1045 em_transmit_checksum_setup(sc, m_head, &txd_upper, &txd_lower); 1046 else 1047 txd_upper = txd_lower = 0; 1048 #else 1049 txd_upper = txd_lower = 0; 1050 #endif 1051 1052 i = sc->next_avail_tx_desc; 1053 if (sc->pcix_82544) 1054 txd_saved = i; 1055 1056 for (j = 0; j < map->dm_nsegs; j++) { 1057 /* If sc is 82544 and on PCI-X bus */ 1058 if (sc->pcix_82544) { 1059 /* 1060 * Check the Address and Length combination and 1061 * split the data accordingly 1062 */ 1063 array_elements = em_fill_descriptors(map->dm_segs[j].ds_addr, 1064 map->dm_segs[j].ds_len, 1065 &desc_array); 1066 for (counter = 0; counter < array_elements; counter++) { 1067 if (txd_used == sc->num_tx_desc_avail) { 1068 sc->next_avail_tx_desc = txd_saved; 1069 goto fail; 1070 } 1071 tx_buffer = &sc->tx_buffer_area[i]; 1072 current_tx_desc = &sc->tx_desc_base[i]; 1073 current_tx_desc->buffer_addr = htole64( 1074 desc_array.descriptor[counter].address); 1075 current_tx_desc->lower.data = htole32( 1076 (sc->txd_cmd | txd_lower | 1077 (u_int16_t)desc_array.descriptor[counter].length)); 1078 current_tx_desc->upper.data = htole32((txd_upper)); 1079 last = i; 1080 if (++i == sc->num_tx_desc) 1081 i = 0; 1082 1083 tx_buffer->m_head = NULL; 1084 tx_buffer->next_eop = -1; 1085 txd_used++; 1086 } 1087 } else { 1088 tx_buffer = &sc->tx_buffer_area[i]; 1089 current_tx_desc = &sc->tx_desc_base[i]; 1090 1091 current_tx_desc->buffer_addr = htole64(map->dm_segs[j].ds_addr); 1092 current_tx_desc->lower.data = htole32( 1093 sc->txd_cmd | txd_lower | map->dm_segs[j].ds_len); 1094 current_tx_desc->upper.data = htole32(txd_upper); 1095 last = i; 1096 if (++i == sc->num_tx_desc) 1097 i = 0; 1098 1099 tx_buffer->m_head = NULL; 1100 tx_buffer->next_eop = -1; 1101 } 1102 } 1103 1104 sc->next_avail_tx_desc = i; 1105 if (sc->pcix_82544) 1106 sc->num_tx_desc_avail -= txd_used; 1107 else 1108 sc->num_tx_desc_avail -= map->dm_nsegs; 1109 1110 #if NVLAN > 0 1111 /* Find out if we are in VLAN mode */ 1112 if (m_head->m_flags & M_VLANTAG) { 1113 /* Set the VLAN id */ 1114 current_tx_desc->upper.fields.special = 1115 htole16(m_head->m_pkthdr.ether_vtag); 1116 1117 /* Tell hardware to add tag */ 1118 current_tx_desc->lower.data |= htole32(E1000_TXD_CMD_VLE); 1119 } 1120 #endif 1121 1122 tx_buffer->m_head = m_head; 1123 tx_buffer_mapped->map = tx_buffer->map; 1124 tx_buffer->map = map; 1125 bus_dmamap_sync(sc->txtag, map, 0, map->dm_mapsize, 1126 BUS_DMASYNC_PREWRITE); 1127 1128 /* 1129 * Last Descriptor of Packet 1130 * needs End Of Packet (EOP) 1131 * and Report Status (RS) 1132 */ 1133 current_tx_desc->lower.data |= 1134 htole32(E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS); 1135 1136 /* 1137 * Keep track in the first buffer which 1138 * descriptor will be written back 1139 */ 1140 tx_buffer = &sc->tx_buffer_area[first]; 1141 tx_buffer->next_eop = last; 1142 1143 /* 1144 * Advance the Transmit Descriptor Tail (Tdt), 1145 * this tells the E1000 that this frame is 1146 * available to transmit. 1147 */ 1148 if (sc->hw.mac_type == em_82547) { 1149 bus_dmamap_sync(sc->txdma.dma_tag, sc->txdma.dma_map, 0, 1150 sc->txdma.dma_map->dm_mapsize, 1151 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1152 if (sc->link_duplex == HALF_DUPLEX) 1153 em_82547_move_tail_locked(sc); 1154 else { 1155 E1000_WRITE_REG(&sc->hw, TDT, i); 1156 em_82547_update_fifo_head(sc, m_head->m_pkthdr.len); 1157 } 1158 } 1159 1160 return (0); 1161 1162 fail: 1163 sc->no_tx_desc_avail2++; 1164 bus_dmamap_unload(sc->txtag, map); 1165 error = ENOBUFS; 1166 loaderr: 1167 if (sc->hw.mac_type == em_82547) { 1168 bus_dmamap_sync(sc->txdma.dma_tag, sc->txdma.dma_map, 0, 1169 sc->txdma.dma_map->dm_mapsize, 1170 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1171 } 1172 return (error); 1173 } 1174 1175 /********************************************************************* 1176 * 1177 * 82547 workaround to avoid controller hang in half-duplex environment. 1178 * The workaround is to avoid queuing a large packet that would span 1179 * the internal Tx FIFO ring boundary. We need to reset the FIFO pointers 1180 * in this case. We do that only when FIFO is quiescent. 1181 * 1182 **********************************************************************/ 1183 void 1184 em_82547_move_tail_locked(struct em_softc *sc) 1185 { 1186 uint16_t hw_tdt; 1187 uint16_t sw_tdt; 1188 struct em_tx_desc *tx_desc; 1189 uint16_t length = 0; 1190 boolean_t eop = 0; 1191 1192 hw_tdt = E1000_READ_REG(&sc->hw, TDT); 1193 sw_tdt = sc->next_avail_tx_desc; 1194 1195 while (hw_tdt != sw_tdt) { 1196 tx_desc = &sc->tx_desc_base[hw_tdt]; 1197 length += tx_desc->lower.flags.length; 1198 eop = tx_desc->lower.data & E1000_TXD_CMD_EOP; 1199 if (++hw_tdt == sc->num_tx_desc) 1200 hw_tdt = 0; 1201 1202 if (eop) { 1203 if (em_82547_fifo_workaround(sc, length)) { 1204 sc->tx_fifo_wrk_cnt++; 1205 timeout_add(&sc->tx_fifo_timer_handle, 1); 1206 break; 1207 } 1208 E1000_WRITE_REG(&sc->hw, TDT, hw_tdt); 1209 em_82547_update_fifo_head(sc, length); 1210 length = 0; 1211 } 1212 } 1213 } 1214 1215 void 1216 em_82547_move_tail(void *arg) 1217 { 1218 struct em_softc *sc = arg; 1219 int s; 1220 1221 s = splnet(); 1222 em_82547_move_tail_locked(sc); 1223 splx(s); 1224 } 1225 1226 int 1227 em_82547_fifo_workaround(struct em_softc *sc, int len) 1228 { 1229 int fifo_space, fifo_pkt_len; 1230 1231 fifo_pkt_len = EM_ROUNDUP(len + EM_FIFO_HDR, EM_FIFO_HDR); 1232 1233 if (sc->link_duplex == HALF_DUPLEX) { 1234 fifo_space = sc->tx_fifo_size - sc->tx_fifo_head; 1235 1236 if (fifo_pkt_len >= (EM_82547_PKT_THRESH + fifo_space)) { 1237 if (em_82547_tx_fifo_reset(sc)) 1238 return (0); 1239 else 1240 return (1); 1241 } 1242 } 1243 1244 return (0); 1245 } 1246 1247 void 1248 em_82547_update_fifo_head(struct em_softc *sc, int len) 1249 { 1250 int fifo_pkt_len = EM_ROUNDUP(len + EM_FIFO_HDR, EM_FIFO_HDR); 1251 1252 /* tx_fifo_head is always 16 byte aligned */ 1253 sc->tx_fifo_head += fifo_pkt_len; 1254 if (sc->tx_fifo_head >= sc->tx_fifo_size) 1255 sc->tx_fifo_head -= sc->tx_fifo_size; 1256 } 1257 1258 int 1259 em_82547_tx_fifo_reset(struct em_softc *sc) 1260 { 1261 uint32_t tctl; 1262 1263 if ((E1000_READ_REG(&sc->hw, TDT) == 1264 E1000_READ_REG(&sc->hw, TDH)) && 1265 (E1000_READ_REG(&sc->hw, TDFT) == 1266 E1000_READ_REG(&sc->hw, TDFH)) && 1267 (E1000_READ_REG(&sc->hw, TDFTS) == 1268 E1000_READ_REG(&sc->hw, TDFHS)) && 1269 (E1000_READ_REG(&sc->hw, TDFPC) == 0)) { 1270 1271 /* Disable TX unit */ 1272 tctl = E1000_READ_REG(&sc->hw, TCTL); 1273 E1000_WRITE_REG(&sc->hw, TCTL, tctl & ~E1000_TCTL_EN); 1274 1275 /* Reset FIFO pointers */ 1276 E1000_WRITE_REG(&sc->hw, TDFT, sc->tx_head_addr); 1277 E1000_WRITE_REG(&sc->hw, TDFH, sc->tx_head_addr); 1278 E1000_WRITE_REG(&sc->hw, TDFTS, sc->tx_head_addr); 1279 E1000_WRITE_REG(&sc->hw, TDFHS, sc->tx_head_addr); 1280 1281 /* Re-enable TX unit */ 1282 E1000_WRITE_REG(&sc->hw, TCTL, tctl); 1283 E1000_WRITE_FLUSH(&sc->hw); 1284 1285 sc->tx_fifo_head = 0; 1286 sc->tx_fifo_reset_cnt++; 1287 1288 return (TRUE); 1289 } else 1290 return (FALSE); 1291 } 1292 1293 void 1294 em_set_promisc(struct em_softc *sc) 1295 { 1296 u_int32_t reg_rctl; 1297 struct ifnet *ifp = &sc->interface_data.ac_if; 1298 1299 reg_rctl = E1000_READ_REG(&sc->hw, RCTL); 1300 1301 if (ifp->if_flags & IFF_PROMISC) { 1302 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1303 } else if (ifp->if_flags & IFF_ALLMULTI) { 1304 reg_rctl |= E1000_RCTL_MPE; 1305 reg_rctl &= ~E1000_RCTL_UPE; 1306 } else { 1307 reg_rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE); 1308 } 1309 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 1310 } 1311 1312 /********************************************************************* 1313 * Multicast Update 1314 * 1315 * This routine is called whenever multicast address list is updated. 1316 * 1317 **********************************************************************/ 1318 1319 void 1320 em_set_multi(struct em_softc *sc) 1321 { 1322 u_int32_t reg_rctl = 0; 1323 u_int8_t mta[MAX_NUM_MULTICAST_ADDRESSES * ETH_LENGTH_OF_ADDRESS]; 1324 struct ifnet *ifp = &sc->interface_data.ac_if; 1325 struct arpcom *ac = &sc->interface_data; 1326 struct ether_multi *enm; 1327 struct ether_multistep step; 1328 int i = 0; 1329 1330 IOCTL_DEBUGOUT("em_set_multi: begin"); 1331 ifp->if_flags &= ~IFF_ALLMULTI; 1332 1333 if (sc->hw.mac_type == em_82542_rev2_0) { 1334 reg_rctl = E1000_READ_REG(&sc->hw, RCTL); 1335 if (sc->hw.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1336 em_pci_clear_mwi(&sc->hw); 1337 reg_rctl |= E1000_RCTL_RST; 1338 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 1339 msec_delay(5); 1340 } 1341 1342 reg_rctl = E1000_READ_REG(&sc->hw, RCTL); 1343 if (ac->ac_multirangecnt > 0 || 1344 ac->ac_multicnt > MAX_NUM_MULTICAST_ADDRESSES) { 1345 ifp->if_flags |= IFF_ALLMULTI; 1346 reg_rctl |= E1000_RCTL_MPE; 1347 } else { 1348 ETHER_FIRST_MULTI(step, ac, enm); 1349 1350 while (enm != NULL) { 1351 bcopy(enm->enm_addrlo, mta + i, ETH_LENGTH_OF_ADDRESS); 1352 i += ETH_LENGTH_OF_ADDRESS; 1353 1354 ETHER_NEXT_MULTI(step, enm); 1355 } 1356 1357 em_mc_addr_list_update(&sc->hw, mta, ac->ac_multicnt, 0, 1); 1358 reg_rctl &= ~E1000_RCTL_MPE; 1359 } 1360 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 1361 1362 if (sc->hw.mac_type == em_82542_rev2_0) { 1363 reg_rctl = E1000_READ_REG(&sc->hw, RCTL); 1364 reg_rctl &= ~E1000_RCTL_RST; 1365 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 1366 msec_delay(5); 1367 if (sc->hw.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1368 em_pci_set_mwi(&sc->hw); 1369 } 1370 } 1371 1372 /********************************************************************* 1373 * Timer routine 1374 * 1375 * This routine checks for link status and updates statistics. 1376 * 1377 **********************************************************************/ 1378 1379 void 1380 em_local_timer(void *arg) 1381 { 1382 struct ifnet *ifp; 1383 struct em_softc *sc = arg; 1384 int s; 1385 1386 ifp = &sc->interface_data.ac_if; 1387 1388 s = splnet(); 1389 1390 em_check_for_link(&sc->hw); 1391 em_update_link_status(sc); 1392 em_update_stats_counters(sc); 1393 #ifdef EM_DEBUG 1394 if (em_display_debug_stats && ifp->if_flags & IFF_RUNNING) 1395 em_print_hw_stats(sc); 1396 #endif 1397 em_smartspeed(sc); 1398 1399 timeout_add_sec(&sc->timer_handle, 1); 1400 1401 splx(s); 1402 } 1403 1404 void 1405 em_update_link_status(struct em_softc *sc) 1406 { 1407 struct ifnet *ifp = &sc->interface_data.ac_if; 1408 1409 if (E1000_READ_REG(&sc->hw, STATUS) & E1000_STATUS_LU) { 1410 if (sc->link_active == 0) { 1411 em_get_speed_and_duplex(&sc->hw, 1412 &sc->link_speed, 1413 &sc->link_duplex); 1414 /* Check if we may set SPEED_MODE bit on PCI-E */ 1415 if ((sc->link_speed == SPEED_1000) && 1416 ((sc->hw.mac_type == em_82571) || 1417 (sc->hw.mac_type == em_82572))) { 1418 int tarc0; 1419 1420 tarc0 = E1000_READ_REG(&sc->hw, TARC0); 1421 tarc0 |= SPEED_MODE_BIT; 1422 E1000_WRITE_REG(&sc->hw, TARC0, tarc0); 1423 } 1424 sc->link_active = 1; 1425 sc->smartspeed = 0; 1426 ifp->if_baudrate = sc->link_speed * 1000000; 1427 } 1428 if (!LINK_STATE_IS_UP(ifp->if_link_state)) { 1429 if (sc->link_duplex == FULL_DUPLEX) 1430 ifp->if_link_state = LINK_STATE_FULL_DUPLEX; 1431 else 1432 ifp->if_link_state = LINK_STATE_HALF_DUPLEX; 1433 if_link_state_change(ifp); 1434 } 1435 } else { 1436 if (sc->link_active == 1) { 1437 ifp->if_baudrate = sc->link_speed = 0; 1438 sc->link_duplex = 0; 1439 sc->link_active = 0; 1440 } 1441 if (ifp->if_link_state != LINK_STATE_DOWN) { 1442 ifp->if_link_state = LINK_STATE_DOWN; 1443 if_link_state_change(ifp); 1444 } 1445 } 1446 } 1447 1448 /********************************************************************* 1449 * 1450 * This routine disables all traffic on the adapter by issuing a 1451 * global reset on the MAC and deallocates TX/RX buffers. 1452 * 1453 **********************************************************************/ 1454 1455 void 1456 em_stop(void *arg) 1457 { 1458 struct ifnet *ifp; 1459 struct em_softc *sc = arg; 1460 ifp = &sc->interface_data.ac_if; 1461 1462 /* Tell the stack that the interface is no longer active */ 1463 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1464 1465 INIT_DEBUGOUT("em_stop: begin"); 1466 em_disable_intr(sc); 1467 em_reset_hw(&sc->hw); 1468 timeout_del(&sc->timer_handle); 1469 timeout_del(&sc->tx_fifo_timer_handle); 1470 1471 em_free_transmit_structures(sc); 1472 em_free_receive_structures(sc); 1473 } 1474 1475 /********************************************************************* 1476 * 1477 * Determine hardware revision. 1478 * 1479 **********************************************************************/ 1480 void 1481 em_identify_hardware(struct em_softc *sc) 1482 { 1483 u_int32_t reg; 1484 struct pci_attach_args *pa = &sc->osdep.em_pa; 1485 1486 /* Make sure our PCI config space has the necessary stuff set */ 1487 sc->hw.pci_cmd_word = pci_conf_read(pa->pa_pc, pa->pa_tag, 1488 PCI_COMMAND_STATUS_REG); 1489 1490 /* Save off the information about this board */ 1491 sc->hw.vendor_id = PCI_VENDOR(pa->pa_id); 1492 sc->hw.device_id = PCI_PRODUCT(pa->pa_id); 1493 1494 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG); 1495 sc->hw.revision_id = PCI_REVISION(reg); 1496 1497 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 1498 sc->hw.subsystem_vendor_id = PCI_VENDOR(reg); 1499 sc->hw.subsystem_id = PCI_PRODUCT(reg); 1500 1501 /* Identify the MAC */ 1502 if (em_set_mac_type(&sc->hw)) 1503 printf("%s: Unknown MAC Type\n", sc->sc_dv.dv_xname); 1504 1505 if (sc->hw.mac_type == em_82541 || 1506 sc->hw.mac_type == em_82541_rev_2 || 1507 sc->hw.mac_type == em_82547 || 1508 sc->hw.mac_type == em_82547_rev_2) 1509 sc->hw.phy_init_script = TRUE; 1510 } 1511 1512 int 1513 em_allocate_pci_resources(struct em_softc *sc) 1514 { 1515 int val, rid; 1516 pci_intr_handle_t ih; 1517 const char *intrstr = NULL; 1518 struct pci_attach_args *pa = &sc->osdep.em_pa; 1519 pci_chipset_tag_t pc = pa->pa_pc; 1520 1521 val = pci_conf_read(pa->pa_pc, pa->pa_tag, EM_MMBA); 1522 if (PCI_MAPREG_TYPE(val) != PCI_MAPREG_TYPE_MEM) { 1523 printf(": mmba is not mem space\n"); 1524 return (ENXIO); 1525 } 1526 if (pci_mapreg_map(pa, EM_MMBA, PCI_MAPREG_MEM_TYPE(val), 0, 1527 &sc->osdep.mem_bus_space_tag, &sc->osdep.mem_bus_space_handle, 1528 &sc->osdep.em_membase, &sc->osdep.em_memsize, 0)) { 1529 printf(": cannot find mem space\n"); 1530 return (ENXIO); 1531 } 1532 1533 if (sc->hw.mac_type > em_82543) { 1534 /* Figure out where our I/O BAR is ? */ 1535 for (rid = PCI_MAPREG_START; rid < PCI_MAPREG_END;) { 1536 val = pci_conf_read(pa->pa_pc, pa->pa_tag, rid); 1537 if (PCI_MAPREG_TYPE(val) == PCI_MAPREG_TYPE_IO) { 1538 sc->io_rid = rid; 1539 break; 1540 } 1541 rid += 4; 1542 if (PCI_MAPREG_MEM_TYPE(val) == 1543 PCI_MAPREG_MEM_TYPE_64BIT) 1544 rid += 4; /* skip high bits, too */ 1545 } 1546 1547 if (pci_mapreg_map(pa, rid, PCI_MAPREG_TYPE_IO, 0, 1548 &sc->osdep.io_bus_space_tag, &sc->osdep.io_bus_space_handle, 1549 &sc->osdep.em_iobase, &sc->osdep.em_iosize, 0)) { 1550 printf(": cannot find i/o space\n"); 1551 return (ENXIO); 1552 } 1553 1554 sc->hw.io_base = 0; 1555 } 1556 1557 /* for ICH8 and family we need to find the flash memory */ 1558 if (sc->hw.mac_type == em_ich8lan || 1559 sc->hw.mac_type == em_ich9lan) { 1560 val = pci_conf_read(pa->pa_pc, pa->pa_tag, EM_FLASH); 1561 if (PCI_MAPREG_TYPE(val) != PCI_MAPREG_TYPE_MEM) { 1562 printf(": flash is not mem space\n"); 1563 return (ENXIO); 1564 } 1565 1566 if (pci_mapreg_map(pa, EM_FLASH, PCI_MAPREG_MEM_TYPE(val), 0, 1567 &sc->osdep.flash_bus_space_tag, &sc->osdep.flash_bus_space_handle, 1568 &sc->osdep.em_flashbase, &sc->osdep.em_flashsize, 0)) { 1569 printf(": cannot find mem space\n"); 1570 return (ENXIO); 1571 } 1572 } 1573 1574 if (pci_intr_map(pa, &ih)) { 1575 printf(": couldn't map interrupt\n"); 1576 return (ENXIO); 1577 } 1578 1579 sc->hw.back = &sc->osdep; 1580 1581 intrstr = pci_intr_string(pc, ih); 1582 sc->sc_intrhand = pci_intr_establish(pc, ih, IPL_NET, em_intr, sc, 1583 sc->sc_dv.dv_xname); 1584 if (sc->sc_intrhand == NULL) { 1585 printf(": couldn't establish interrupt"); 1586 if (intrstr != NULL) 1587 printf(" at %s", intrstr); 1588 printf("\n"); 1589 return (ENXIO); 1590 } 1591 printf(": %s", intrstr); 1592 1593 return (0); 1594 } 1595 1596 void 1597 em_free_pci_resources(struct em_softc *sc) 1598 { 1599 struct pci_attach_args *pa = &sc->osdep.em_pa; 1600 pci_chipset_tag_t pc = pa->pa_pc; 1601 1602 if (sc->sc_intrhand) 1603 pci_intr_disestablish(pc, sc->sc_intrhand); 1604 sc->sc_intrhand = 0; 1605 1606 if (sc->osdep.em_flashbase) 1607 bus_space_unmap(sc->osdep.flash_bus_space_tag, sc->osdep.flash_bus_space_handle, 1608 sc->osdep.em_flashsize); 1609 sc->osdep.em_flashbase = 0; 1610 1611 if (sc->osdep.em_iobase) 1612 bus_space_unmap(sc->osdep.io_bus_space_tag, sc->osdep.io_bus_space_handle, 1613 sc->osdep.em_iosize); 1614 sc->osdep.em_iobase = 0; 1615 1616 if (sc->osdep.em_membase) 1617 bus_space_unmap(sc->osdep.mem_bus_space_tag, sc->osdep.mem_bus_space_handle, 1618 sc->osdep.em_memsize); 1619 sc->osdep.em_membase = 0; 1620 } 1621 1622 /********************************************************************* 1623 * 1624 * Initialize the hardware to a configuration as specified by the 1625 * em_softc structure. The controller is reset, the EEPROM is 1626 * verified, the MAC address is set, then the shared initialization 1627 * routines are called. 1628 * 1629 **********************************************************************/ 1630 int 1631 em_hardware_init(struct em_softc *sc) 1632 { 1633 u_int16_t rx_buffer_size; 1634 1635 INIT_DEBUGOUT("em_hardware_init: begin"); 1636 /* Issue a global reset */ 1637 em_reset_hw(&sc->hw); 1638 1639 /* When hardware is reset, fifo_head is also reset */ 1640 sc->tx_fifo_head = 0; 1641 1642 /* Make sure we have a good EEPROM before we read from it */ 1643 if (em_validate_eeprom_checksum(&sc->hw) < 0) { 1644 /* 1645 * Some PCIe parts fail the first check due to 1646 * the link being in sleep state, call it again, 1647 * if it fails a second time its a real issue. 1648 */ 1649 if (em_validate_eeprom_checksum(&sc->hw) < 0) { 1650 printf("%s: The EEPROM Checksum Is Not Valid\n", 1651 sc->sc_dv.dv_xname); 1652 return (EIO); 1653 } 1654 } 1655 1656 if (em_read_part_num(&sc->hw, &(sc->part_num)) < 0) { 1657 printf("%s: EEPROM read error while reading part number\n", 1658 sc->sc_dv.dv_xname); 1659 return (EIO); 1660 } 1661 1662 /* Set up smart power down as default off on newer adapters */ 1663 if (!em_smart_pwr_down && 1664 (sc->hw.mac_type == em_82571 || 1665 sc->hw.mac_type == em_82572)) { 1666 uint16_t phy_tmp = 0; 1667 1668 /* Speed up time to link by disabling smart power down */ 1669 em_read_phy_reg(&sc->hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 1670 phy_tmp &= ~IGP02E1000_PM_SPD; 1671 em_write_phy_reg(&sc->hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp); 1672 } 1673 1674 /* 1675 * These parameters control the automatic generation (Tx) and 1676 * response (Rx) to Ethernet PAUSE frames. 1677 * - High water mark should allow for at least two frames to be 1678 * received after sending an XOFF. 1679 * - Low water mark works best when it is very near the high water mark. 1680 * This allows the receiver to restart by sending XON when it has 1681 * drained a bit. Here we use an arbitary value of 1500 which will 1682 * restart after one full frame is pulled from the buffer. There 1683 * could be several smaller frames in the buffer and if so they will 1684 * not trigger the XON until their total number reduces the buffer 1685 * by 1500. 1686 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 1687 */ 1688 rx_buffer_size = ((E1000_READ_REG(&sc->hw, PBA) & 0xffff) << 10 ); 1689 1690 sc->hw.fc_high_water = rx_buffer_size - 1691 EM_ROUNDUP(sc->hw.max_frame_size, 1024); 1692 sc->hw.fc_low_water = sc->hw.fc_high_water - 1500; 1693 if (sc->hw.mac_type == em_80003es2lan) 1694 sc->hw.fc_pause_time = 0xFFFF; 1695 else 1696 sc->hw.fc_pause_time = 1000; 1697 sc->hw.fc_send_xon = TRUE; 1698 sc->hw.fc = E1000_FC_FULL; 1699 1700 if (em_init_hw(&sc->hw) < 0) { 1701 printf("%s: Hardware Initialization Failed", 1702 sc->sc_dv.dv_xname); 1703 return (EIO); 1704 } 1705 1706 em_check_for_link(&sc->hw); 1707 1708 return (0); 1709 } 1710 1711 /********************************************************************* 1712 * 1713 * Setup networking device structure and register an interface. 1714 * 1715 **********************************************************************/ 1716 void 1717 em_setup_interface(struct em_softc *sc) 1718 { 1719 struct ifnet *ifp; 1720 u_char fiber_type = IFM_1000_SX; 1721 1722 INIT_DEBUGOUT("em_setup_interface: begin"); 1723 1724 ifp = &sc->interface_data.ac_if; 1725 strlcpy(ifp->if_xname, sc->sc_dv.dv_xname, IFNAMSIZ); 1726 ifp->if_softc = sc; 1727 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1728 ifp->if_ioctl = em_ioctl; 1729 ifp->if_start = em_start; 1730 ifp->if_watchdog = em_watchdog; 1731 ifp->if_hardmtu = 1732 sc->hw.max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN; 1733 IFQ_SET_MAXLEN(&ifp->if_snd, sc->num_tx_desc - 1); 1734 IFQ_SET_READY(&ifp->if_snd); 1735 1736 m_clsetwms(ifp, MCLBYTES, 4, sc->num_rx_desc); 1737 1738 ifp->if_capabilities = IFCAP_VLAN_MTU; 1739 1740 #if NVLAN > 0 1741 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 1742 #endif 1743 1744 #ifdef EM_CSUM_OFFLOAD 1745 if (sc->hw.mac_type >= em_82543) 1746 ifp->if_capabilities |= IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4; 1747 #endif 1748 1749 /* 1750 * Specify the media types supported by this adapter and register 1751 * callbacks to update media and link information 1752 */ 1753 ifmedia_init(&sc->media, IFM_IMASK, em_media_change, 1754 em_media_status); 1755 if (sc->hw.media_type == em_media_type_fiber || 1756 sc->hw.media_type == em_media_type_internal_serdes) { 1757 if (sc->hw.mac_type == em_82545) 1758 fiber_type = IFM_1000_LX; 1759 ifmedia_add(&sc->media, IFM_ETHER | fiber_type | IFM_FDX, 1760 0, NULL); 1761 ifmedia_add(&sc->media, IFM_ETHER | fiber_type, 1762 0, NULL); 1763 } else { 1764 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL); 1765 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX, 1766 0, NULL); 1767 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 1768 0, NULL); 1769 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 1770 0, NULL); 1771 if (sc->hw.phy_type != em_phy_ife) { 1772 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 1773 0, NULL); 1774 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_T, 0, NULL); 1775 } 1776 } 1777 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL); 1778 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO); 1779 1780 if_attach(ifp); 1781 ether_ifattach(ifp); 1782 } 1783 1784 1785 /********************************************************************* 1786 * 1787 * Workaround for SmartSpeed on 82541 and 82547 controllers 1788 * 1789 **********************************************************************/ 1790 void 1791 em_smartspeed(struct em_softc *sc) 1792 { 1793 uint16_t phy_tmp; 1794 1795 if (sc->link_active || (sc->hw.phy_type != em_phy_igp) || 1796 !sc->hw.autoneg || !(sc->hw.autoneg_advertised & ADVERTISE_1000_FULL)) 1797 return; 1798 1799 if (sc->smartspeed == 0) { 1800 /* If Master/Slave config fault is asserted twice, 1801 * we assume back-to-back */ 1802 em_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 1803 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 1804 return; 1805 em_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 1806 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 1807 em_read_phy_reg(&sc->hw, PHY_1000T_CTRL, 1808 &phy_tmp); 1809 if (phy_tmp & CR_1000T_MS_ENABLE) { 1810 phy_tmp &= ~CR_1000T_MS_ENABLE; 1811 em_write_phy_reg(&sc->hw, 1812 PHY_1000T_CTRL, phy_tmp); 1813 sc->smartspeed++; 1814 if (sc->hw.autoneg && 1815 !em_phy_setup_autoneg(&sc->hw) && 1816 !em_read_phy_reg(&sc->hw, PHY_CTRL, 1817 &phy_tmp)) { 1818 phy_tmp |= (MII_CR_AUTO_NEG_EN | 1819 MII_CR_RESTART_AUTO_NEG); 1820 em_write_phy_reg(&sc->hw, 1821 PHY_CTRL, phy_tmp); 1822 } 1823 } 1824 } 1825 return; 1826 } else if (sc->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 1827 /* If still no link, perhaps using 2/3 pair cable */ 1828 em_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp); 1829 phy_tmp |= CR_1000T_MS_ENABLE; 1830 em_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp); 1831 if (sc->hw.autoneg && 1832 !em_phy_setup_autoneg(&sc->hw) && 1833 !em_read_phy_reg(&sc->hw, PHY_CTRL, &phy_tmp)) { 1834 phy_tmp |= (MII_CR_AUTO_NEG_EN | 1835 MII_CR_RESTART_AUTO_NEG); 1836 em_write_phy_reg(&sc->hw, PHY_CTRL, phy_tmp); 1837 } 1838 } 1839 /* Restart process after EM_SMARTSPEED_MAX iterations */ 1840 if (sc->smartspeed++ == EM_SMARTSPEED_MAX) 1841 sc->smartspeed = 0; 1842 } 1843 1844 /* 1845 * Manage DMA'able memory. 1846 */ 1847 int 1848 em_dma_malloc(struct em_softc *sc, bus_size_t size, 1849 struct em_dma_alloc *dma, int mapflags) 1850 { 1851 int r; 1852 1853 dma->dma_tag = sc->osdep.em_pa.pa_dmat; 1854 r = bus_dmamap_create(dma->dma_tag, size, 1, 1855 size, 0, BUS_DMA_NOWAIT, &dma->dma_map); 1856 if (r != 0) { 1857 printf("%s: em_dma_malloc: bus_dmamap_create failed; " 1858 "error %u\n", sc->sc_dv.dv_xname, r); 1859 goto fail_0; 1860 } 1861 1862 r = bus_dmamem_alloc(dma->dma_tag, size, PAGE_SIZE, 0, &dma->dma_seg, 1863 1, &dma->dma_nseg, BUS_DMA_NOWAIT); 1864 if (r != 0) { 1865 printf("%s: em_dma_malloc: bus_dmammem_alloc failed; " 1866 "size %lu, error %d\n", sc->sc_dv.dv_xname, 1867 (unsigned long)size, r); 1868 goto fail_1; 1869 } 1870 1871 r = bus_dmamem_map(dma->dma_tag, &dma->dma_seg, dma->dma_nseg, size, 1872 &dma->dma_vaddr, BUS_DMA_NOWAIT); 1873 if (r != 0) { 1874 printf("%s: em_dma_malloc: bus_dmammem_map failed; " 1875 "size %lu, error %d\n", sc->sc_dv.dv_xname, 1876 (unsigned long)size, r); 1877 goto fail_2; 1878 } 1879 1880 r = bus_dmamap_load(sc->osdep.em_pa.pa_dmat, dma->dma_map, 1881 dma->dma_vaddr, size, NULL, 1882 mapflags | BUS_DMA_NOWAIT); 1883 if (r != 0) { 1884 printf("%s: em_dma_malloc: bus_dmamap_load failed; " 1885 "error %u\n", sc->sc_dv.dv_xname, r); 1886 goto fail_3; 1887 } 1888 1889 dma->dma_size = size; 1890 return (0); 1891 1892 fail_3: 1893 bus_dmamem_unmap(dma->dma_tag, dma->dma_vaddr, size); 1894 fail_2: 1895 bus_dmamem_free(dma->dma_tag, &dma->dma_seg, dma->dma_nseg); 1896 fail_1: 1897 bus_dmamap_destroy(dma->dma_tag, dma->dma_map); 1898 fail_0: 1899 dma->dma_map = NULL; 1900 dma->dma_tag = NULL; 1901 1902 return (r); 1903 } 1904 1905 void 1906 em_dma_free(struct em_softc *sc, struct em_dma_alloc *dma) 1907 { 1908 if (dma->dma_tag == NULL) 1909 return; 1910 1911 if (dma->dma_map != NULL) { 1912 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 0, 1913 dma->dma_map->dm_mapsize, 1914 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1915 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1916 bus_dmamem_unmap(dma->dma_tag, dma->dma_vaddr, dma->dma_size); 1917 bus_dmamem_free(dma->dma_tag, &dma->dma_seg, dma->dma_nseg); 1918 bus_dmamap_destroy(dma->dma_tag, dma->dma_map); 1919 } 1920 dma->dma_tag = NULL; 1921 } 1922 1923 /********************************************************************* 1924 * 1925 * Allocate memory for tx_buffer structures. The tx_buffer stores all 1926 * the information needed to transmit a packet on the wire. 1927 * 1928 **********************************************************************/ 1929 int 1930 em_allocate_transmit_structures(struct em_softc *sc) 1931 { 1932 if (!(sc->tx_buffer_area = malloc(sizeof(struct em_buffer) * 1933 sc->num_tx_desc, M_DEVBUF, M_NOWAIT | M_ZERO))) { 1934 printf("%s: Unable to allocate tx_buffer memory\n", 1935 sc->sc_dv.dv_xname); 1936 return (ENOMEM); 1937 } 1938 1939 return (0); 1940 } 1941 1942 /********************************************************************* 1943 * 1944 * Allocate and initialize transmit structures. 1945 * 1946 **********************************************************************/ 1947 int 1948 em_setup_transmit_structures(struct em_softc *sc) 1949 { 1950 struct em_buffer *tx_buffer; 1951 int error, i; 1952 1953 if ((error = em_allocate_transmit_structures(sc)) != 0) 1954 goto fail; 1955 1956 bzero((void *) sc->tx_desc_base, 1957 (sizeof(struct em_tx_desc)) * sc->num_tx_desc); 1958 1959 sc->txtag = sc->osdep.em_pa.pa_dmat; 1960 1961 tx_buffer = sc->tx_buffer_area; 1962 for (i = 0; i < sc->num_tx_desc; i++) { 1963 error = bus_dmamap_create(sc->txtag, MAX_JUMBO_FRAME_SIZE, 1964 EM_MAX_SCATTER, MAX_JUMBO_FRAME_SIZE, 0, 1965 BUS_DMA_NOWAIT, &tx_buffer->map); 1966 if (error != 0) { 1967 printf("%s: Unable to create TX DMA map\n", 1968 sc->sc_dv.dv_xname); 1969 goto fail; 1970 } 1971 tx_buffer++; 1972 } 1973 1974 sc->next_avail_tx_desc = 0; 1975 sc->next_tx_to_clean = 0; 1976 1977 /* Set number of descriptors available */ 1978 sc->num_tx_desc_avail = sc->num_tx_desc; 1979 1980 /* Set checksum context */ 1981 sc->active_checksum_context = OFFLOAD_NONE; 1982 bus_dmamap_sync(sc->txdma.dma_tag, sc->txdma.dma_map, 0, 1983 sc->txdma.dma_size, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1984 1985 return (0); 1986 1987 fail: 1988 em_free_transmit_structures(sc); 1989 return (error); 1990 } 1991 1992 /********************************************************************* 1993 * 1994 * Enable transmit unit. 1995 * 1996 **********************************************************************/ 1997 void 1998 em_initialize_transmit_unit(struct em_softc *sc) 1999 { 2000 u_int32_t reg_tctl, reg_tipg = 0; 2001 u_int64_t bus_addr; 2002 2003 INIT_DEBUGOUT("em_initialize_transmit_unit: begin"); 2004 2005 /* Setup the Base and Length of the Tx Descriptor Ring */ 2006 bus_addr = sc->txdma.dma_map->dm_segs[0].ds_addr; 2007 E1000_WRITE_REG(&sc->hw, TDLEN, 2008 sc->num_tx_desc * 2009 sizeof(struct em_tx_desc)); 2010 E1000_WRITE_REG(&sc->hw, TDBAH, (u_int32_t)(bus_addr >> 32)); 2011 E1000_WRITE_REG(&sc->hw, TDBAL, (u_int32_t)bus_addr); 2012 2013 /* Setup the HW Tx Head and Tail descriptor pointers */ 2014 E1000_WRITE_REG(&sc->hw, TDT, 0); 2015 E1000_WRITE_REG(&sc->hw, TDH, 0); 2016 2017 HW_DEBUGOUT2("Base = %x, Length = %x\n", 2018 E1000_READ_REG(&sc->hw, TDBAL), 2019 E1000_READ_REG(&sc->hw, TDLEN)); 2020 2021 /* Set the default values for the Tx Inter Packet Gap timer */ 2022 switch (sc->hw.mac_type) { 2023 case em_82542_rev2_0: 2024 case em_82542_rev2_1: 2025 reg_tipg = DEFAULT_82542_TIPG_IPGT; 2026 reg_tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2027 reg_tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2028 break; 2029 case em_80003es2lan: 2030 reg_tipg = DEFAULT_82543_TIPG_IPGR1; 2031 reg_tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2032 break; 2033 default: 2034 if (sc->hw.media_type == em_media_type_fiber || 2035 sc->hw.media_type == em_media_type_internal_serdes) 2036 reg_tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 2037 else 2038 reg_tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 2039 reg_tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2040 reg_tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2041 } 2042 2043 E1000_WRITE_REG(&sc->hw, TIPG, reg_tipg); 2044 E1000_WRITE_REG(&sc->hw, TIDV, sc->tx_int_delay); 2045 if (sc->hw.mac_type >= em_82540) 2046 E1000_WRITE_REG(&sc->hw, TADV, sc->tx_abs_int_delay); 2047 2048 /* Program the Transmit Control Register */ 2049 reg_tctl = E1000_TCTL_PSP | E1000_TCTL_EN | 2050 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 2051 if (sc->hw.mac_type >= em_82571) 2052 reg_tctl |= E1000_TCTL_MULR; 2053 if (sc->link_duplex == FULL_DUPLEX) 2054 reg_tctl |= E1000_FDX_COLLISION_DISTANCE << E1000_COLD_SHIFT; 2055 else 2056 reg_tctl |= E1000_HDX_COLLISION_DISTANCE << E1000_COLD_SHIFT; 2057 /* This write will effectively turn on the transmit unit */ 2058 E1000_WRITE_REG(&sc->hw, TCTL, reg_tctl); 2059 2060 /* Setup Transmit Descriptor Base Settings */ 2061 sc->txd_cmd = E1000_TXD_CMD_IFCS; 2062 2063 if (sc->tx_int_delay > 0) 2064 sc->txd_cmd |= E1000_TXD_CMD_IDE; 2065 } 2066 2067 /********************************************************************* 2068 * 2069 * Free all transmit related data structures. 2070 * 2071 **********************************************************************/ 2072 void 2073 em_free_transmit_structures(struct em_softc *sc) 2074 { 2075 struct em_buffer *tx_buffer; 2076 int i; 2077 2078 INIT_DEBUGOUT("free_transmit_structures: begin"); 2079 2080 if (sc->tx_buffer_area != NULL) { 2081 tx_buffer = sc->tx_buffer_area; 2082 for (i = 0; i < sc->num_tx_desc; i++, tx_buffer++) { 2083 if (tx_buffer->map != NULL && 2084 tx_buffer->map->dm_nsegs > 0) { 2085 bus_dmamap_sync(sc->txtag, tx_buffer->map, 2086 0, tx_buffer->map->dm_mapsize, 2087 BUS_DMASYNC_POSTWRITE); 2088 bus_dmamap_unload(sc->txtag, 2089 tx_buffer->map); 2090 } 2091 if (tx_buffer->m_head != NULL) { 2092 m_freem(tx_buffer->m_head); 2093 tx_buffer->m_head = NULL; 2094 } 2095 if (tx_buffer->map != NULL) { 2096 bus_dmamap_destroy(sc->txtag, 2097 tx_buffer->map); 2098 tx_buffer->map = NULL; 2099 } 2100 } 2101 } 2102 if (sc->tx_buffer_area != NULL) { 2103 free(sc->tx_buffer_area, M_DEVBUF); 2104 sc->tx_buffer_area = NULL; 2105 } 2106 if (sc->txtag != NULL) 2107 sc->txtag = NULL; 2108 } 2109 2110 #ifdef EM_CSUM_OFFLOAD 2111 /********************************************************************* 2112 * 2113 * The offload context needs to be set when we transfer the first 2114 * packet of a particular protocol (TCP/UDP). We change the 2115 * context only if the protocol type changes. 2116 * 2117 **********************************************************************/ 2118 void 2119 em_transmit_checksum_setup(struct em_softc *sc, struct mbuf *mp, 2120 u_int32_t *txd_upper, u_int32_t *txd_lower) 2121 { 2122 struct em_context_desc *TXD; 2123 struct em_buffer *tx_buffer; 2124 int curr_txd; 2125 2126 if (mp->m_pkthdr.csum_flags) { 2127 if (mp->m_pkthdr.csum_flags & M_TCPV4_CSUM_OUT) { 2128 *txd_upper = E1000_TXD_POPTS_TXSM << 8; 2129 *txd_lower = E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 2130 if (sc->active_checksum_context == OFFLOAD_TCP_IP) 2131 return; 2132 else 2133 sc->active_checksum_context = OFFLOAD_TCP_IP; 2134 } else if (mp->m_pkthdr.csum_flags & M_UDPV4_CSUM_OUT) { 2135 *txd_upper = E1000_TXD_POPTS_TXSM << 8; 2136 *txd_lower = E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 2137 if (sc->active_checksum_context == OFFLOAD_UDP_IP) 2138 return; 2139 else 2140 sc->active_checksum_context = OFFLOAD_UDP_IP; 2141 } else { 2142 *txd_upper = 0; 2143 *txd_lower = 0; 2144 return; 2145 } 2146 } else { 2147 *txd_upper = 0; 2148 *txd_lower = 0; 2149 return; 2150 } 2151 2152 /* If we reach this point, the checksum offload context 2153 * needs to be reset. 2154 */ 2155 curr_txd = sc->next_avail_tx_desc; 2156 tx_buffer = &sc->tx_buffer_area[curr_txd]; 2157 TXD = (struct em_context_desc *) &sc->tx_desc_base[curr_txd]; 2158 2159 TXD->lower_setup.ip_fields.ipcss = ETHER_HDR_LEN; 2160 TXD->lower_setup.ip_fields.ipcso = 2161 ETHER_HDR_LEN + offsetof(struct ip, ip_sum); 2162 TXD->lower_setup.ip_fields.ipcse = 2163 htole16(ETHER_HDR_LEN + sizeof(struct ip) - 1); 2164 2165 TXD->upper_setup.tcp_fields.tucss = 2166 ETHER_HDR_LEN + sizeof(struct ip); 2167 TXD->upper_setup.tcp_fields.tucse = htole16(0); 2168 2169 if (sc->active_checksum_context == OFFLOAD_TCP_IP) { 2170 TXD->upper_setup.tcp_fields.tucso = 2171 ETHER_HDR_LEN + sizeof(struct ip) + 2172 offsetof(struct tcphdr, th_sum); 2173 } else if (sc->active_checksum_context == OFFLOAD_UDP_IP) { 2174 TXD->upper_setup.tcp_fields.tucso = 2175 ETHER_HDR_LEN + sizeof(struct ip) + 2176 offsetof(struct udphdr, uh_sum); 2177 } 2178 2179 TXD->tcp_seg_setup.data = htole32(0); 2180 TXD->cmd_and_length = htole32(sc->txd_cmd | E1000_TXD_CMD_DEXT); 2181 2182 tx_buffer->m_head = NULL; 2183 tx_buffer->next_eop = -1; 2184 2185 if (++curr_txd == sc->num_tx_desc) 2186 curr_txd = 0; 2187 2188 sc->num_tx_desc_avail--; 2189 sc->next_avail_tx_desc = curr_txd; 2190 } 2191 #endif /* EM_CSUM_OFFLOAD */ 2192 2193 /********************************************************************** 2194 * 2195 * Examine each tx_buffer in the used queue. If the hardware is done 2196 * processing the packet then free associated resources. The 2197 * tx_buffer is put back on the free queue. 2198 * 2199 **********************************************************************/ 2200 void 2201 em_txeof(struct em_softc *sc) 2202 { 2203 int first, last, done, num_avail; 2204 struct em_buffer *tx_buffer; 2205 struct em_tx_desc *tx_desc, *eop_desc; 2206 struct ifnet *ifp = &sc->interface_data.ac_if; 2207 2208 if (sc->num_tx_desc_avail == sc->num_tx_desc) 2209 return; 2210 2211 num_avail = sc->num_tx_desc_avail; 2212 first = sc->next_tx_to_clean; 2213 tx_desc = &sc->tx_desc_base[first]; 2214 tx_buffer = &sc->tx_buffer_area[first]; 2215 last = tx_buffer->next_eop; 2216 eop_desc = &sc->tx_desc_base[last]; 2217 2218 /* 2219 * What this does is get the index of the 2220 * first descriptor AFTER the EOP of the 2221 * first packet, that way we can do the 2222 * simple comparison on the inner while loop. 2223 */ 2224 if (++last == sc->num_tx_desc) 2225 last = 0; 2226 done = last; 2227 2228 bus_dmamap_sync(sc->txdma.dma_tag, sc->txdma.dma_map, 0, 2229 sc->txdma.dma_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 2230 while (eop_desc->upper.fields.status & E1000_TXD_STAT_DD) { 2231 /* We clean the range of the packet */ 2232 while (first != done) { 2233 tx_desc->upper.data = 0; 2234 tx_desc->lower.data = 0; 2235 num_avail++; 2236 2237 if (tx_buffer->m_head != NULL) { 2238 ifp->if_opackets++; 2239 if (tx_buffer->map->dm_nsegs > 0) { 2240 bus_dmamap_sync(sc->txtag, 2241 tx_buffer->map, 0, 2242 tx_buffer->map->dm_mapsize, 2243 BUS_DMASYNC_POSTWRITE); 2244 bus_dmamap_unload(sc->txtag, 2245 tx_buffer->map); 2246 } 2247 m_freem(tx_buffer->m_head); 2248 tx_buffer->m_head = NULL; 2249 } 2250 tx_buffer->next_eop = -1; 2251 2252 if (++first == sc->num_tx_desc) 2253 first = 0; 2254 2255 tx_buffer = &sc->tx_buffer_area[first]; 2256 tx_desc = &sc->tx_desc_base[first]; 2257 } 2258 /* See if we can continue to the next packet */ 2259 last = tx_buffer->next_eop; 2260 if (last != -1) { 2261 eop_desc = &sc->tx_desc_base[last]; 2262 /* Get new done point */ 2263 if (++last == sc->num_tx_desc) 2264 last = 0; 2265 done = last; 2266 } else 2267 break; 2268 } 2269 bus_dmamap_sync(sc->txdma.dma_tag, sc->txdma.dma_map, 0, 2270 sc->txdma.dma_map->dm_mapsize, 2271 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2272 2273 sc->next_tx_to_clean = first; 2274 2275 /* 2276 * If we have enough room, clear IFF_OACTIVE to tell the stack 2277 * that it is OK to send packets. 2278 * If there are no pending descriptors, clear the timeout. Otherwise, 2279 * if some descriptors have been freed, restart the timeout. 2280 */ 2281 if (num_avail > EM_TX_CLEANUP_THRESHOLD) 2282 ifp->if_flags &= ~IFF_OACTIVE; 2283 2284 /* All clean, turn off the timer */ 2285 if (num_avail == sc->num_tx_desc) 2286 ifp->if_timer = 0; 2287 /* Some cleaned, reset the timer */ 2288 else if (num_avail != sc->num_tx_desc_avail) 2289 ifp->if_timer = EM_TX_TIMEOUT; 2290 2291 sc->num_tx_desc_avail = num_avail; 2292 } 2293 2294 /********************************************************************* 2295 * 2296 * Get a buffer from system mbuf buffer pool. 2297 * 2298 **********************************************************************/ 2299 int 2300 em_get_buf(struct em_softc *sc, int i) 2301 { 2302 struct mbuf *m; 2303 struct em_buffer *pkt; 2304 struct em_rx_desc *desc; 2305 int error; 2306 2307 pkt = &sc->rx_buffer_area[i]; 2308 desc = &sc->rx_desc_base[i]; 2309 2310 if (pkt->m_head != NULL) { 2311 printf("%s: em_get_buf: slot %d already has an mbuf\n", 2312 sc->sc_dv.dv_xname, i); 2313 return (ENOBUFS); 2314 } 2315 2316 MGETHDR(m, M_DONTWAIT, MT_DATA); 2317 if (m == NULL) { 2318 sc->mbuf_alloc_failed++; 2319 return (ENOBUFS); 2320 } 2321 MCLGETI(m, M_DONTWAIT, &sc->interface_data.ac_if, MCLBYTES); 2322 if ((m->m_flags & M_EXT) == 0) { 2323 m_freem(m); 2324 sc->mbuf_cluster_failed++; 2325 return (ENOBUFS); 2326 } 2327 m->m_len = m->m_pkthdr.len = MCLBYTES; 2328 if (sc->hw.max_frame_size <= (MCLBYTES - ETHER_ALIGN)) 2329 m_adj(m, ETHER_ALIGN); 2330 2331 error = bus_dmamap_load_mbuf(sc->rxtag, pkt->map, m, BUS_DMA_NOWAIT); 2332 if (error) { 2333 m_freem(m); 2334 return (error); 2335 } 2336 2337 bus_dmamap_sync(sc->rxtag, pkt->map, 0, pkt->map->dm_mapsize, 2338 BUS_DMASYNC_PREREAD); 2339 pkt->m_head = m; 2340 2341 bus_dmamap_sync(sc->rxdma.dma_tag, sc->rxdma.dma_map, 2342 sizeof(*desc) * i, sizeof(*desc), BUS_DMASYNC_POSTWRITE); 2343 2344 bzero(desc, sizeof(*desc)); 2345 desc->buffer_addr = htole64(pkt->map->dm_segs[0].ds_addr); 2346 2347 bus_dmamap_sync(sc->rxdma.dma_tag, sc->rxdma.dma_map, 2348 sizeof(*desc) * i, sizeof(*desc), BUS_DMASYNC_PREWRITE); 2349 2350 sc->rx_ndescs++; 2351 2352 return (0); 2353 } 2354 2355 /********************************************************************* 2356 * 2357 * Allocate memory for rx_buffer structures. Since we use one 2358 * rx_buffer per received packet, the maximum number of rx_buffer's 2359 * that we'll need is equal to the number of receive descriptors 2360 * that we've allocated. 2361 * 2362 **********************************************************************/ 2363 int 2364 em_allocate_receive_structures(struct em_softc *sc) 2365 { 2366 int i, error; 2367 struct em_buffer *rx_buffer; 2368 2369 if (!(sc->rx_buffer_area = malloc(sizeof(struct em_buffer) * 2370 sc->num_rx_desc, M_DEVBUF, M_NOWAIT | M_ZERO))) { 2371 printf("%s: Unable to allocate rx_buffer memory\n", 2372 sc->sc_dv.dv_xname); 2373 return (ENOMEM); 2374 } 2375 2376 sc->rxtag = sc->osdep.em_pa.pa_dmat; 2377 2378 rx_buffer = sc->rx_buffer_area; 2379 for (i = 0; i < sc->num_rx_desc; i++, rx_buffer++) { 2380 error = bus_dmamap_create(sc->rxtag, MCLBYTES, 1, 2381 MCLBYTES, 0, BUS_DMA_NOWAIT, &rx_buffer->map); 2382 if (error != 0) { 2383 printf("%s: em_allocate_receive_structures: " 2384 "bus_dmamap_create failed; error %u\n", 2385 sc->sc_dv.dv_xname, error); 2386 goto fail; 2387 } 2388 rx_buffer->m_head = NULL; 2389 } 2390 bus_dmamap_sync(sc->rxdma.dma_tag, sc->rxdma.dma_map, 0, 2391 sc->rxdma.dma_map->dm_mapsize, 2392 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2393 2394 return (0); 2395 2396 fail: 2397 em_free_receive_structures(sc); 2398 return (error); 2399 } 2400 2401 /********************************************************************* 2402 * 2403 * Allocate and initialize receive structures. 2404 * 2405 **********************************************************************/ 2406 int 2407 em_setup_receive_structures(struct em_softc *sc) 2408 { 2409 bzero((void *) sc->rx_desc_base, 2410 (sizeof(struct em_rx_desc)) * sc->num_rx_desc); 2411 2412 if (em_allocate_receive_structures(sc)) 2413 return (ENOMEM); 2414 2415 /* Setup our descriptor pointers */ 2416 sc->next_rx_desc_to_check = 0; 2417 sc->last_rx_desc_filled = sc->num_rx_desc - 1; 2418 2419 em_rxfill(sc); 2420 if (sc->rx_ndescs < 1) { 2421 printf("%s: unable to fill any rx descriptors\n", 2422 sc->sc_dv.dv_xname); 2423 } 2424 2425 return (0); 2426 } 2427 2428 /********************************************************************* 2429 * 2430 * Enable receive unit. 2431 * 2432 **********************************************************************/ 2433 void 2434 em_initialize_receive_unit(struct em_softc *sc) 2435 { 2436 u_int32_t reg_rctl; 2437 u_int32_t reg_rxcsum; 2438 u_int64_t bus_addr; 2439 2440 INIT_DEBUGOUT("em_initialize_receive_unit: begin"); 2441 2442 /* Make sure receives are disabled while setting up the descriptor ring */ 2443 E1000_WRITE_REG(&sc->hw, RCTL, 0); 2444 2445 /* Set the Receive Delay Timer Register */ 2446 E1000_WRITE_REG(&sc->hw, RDTR, 2447 sc->rx_int_delay | E1000_RDT_FPDB); 2448 2449 if (sc->hw.mac_type >= em_82540) { 2450 if (sc->rx_int_delay) 2451 E1000_WRITE_REG(&sc->hw, RADV, sc->rx_abs_int_delay); 2452 2453 /* Set the interrupt throttling rate. Value is calculated 2454 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */ 2455 E1000_WRITE_REG(&sc->hw, ITR, DEFAULT_ITR); 2456 } 2457 2458 /* Setup the Base and Length of the Rx Descriptor Ring */ 2459 bus_addr = sc->rxdma.dma_map->dm_segs[0].ds_addr; 2460 E1000_WRITE_REG(&sc->hw, RDLEN, sc->num_rx_desc * 2461 sizeof(struct em_rx_desc)); 2462 E1000_WRITE_REG(&sc->hw, RDBAH, (u_int32_t)(bus_addr >> 32)); 2463 E1000_WRITE_REG(&sc->hw, RDBAL, (u_int32_t)bus_addr); 2464 2465 /* Setup the Receive Control Register */ 2466 reg_rctl = E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO | 2467 E1000_RCTL_RDMTS_HALF | 2468 (sc->hw.mc_filter_type << E1000_RCTL_MO_SHIFT); 2469 2470 if (sc->hw.tbi_compatibility_on == TRUE) 2471 reg_rctl |= E1000_RCTL_SBP; 2472 2473 switch (sc->rx_buffer_len) { 2474 default: 2475 case EM_RXBUFFER_2048: 2476 reg_rctl |= E1000_RCTL_SZ_2048; 2477 break; 2478 case EM_RXBUFFER_4096: 2479 reg_rctl |= E1000_RCTL_SZ_4096|E1000_RCTL_BSEX|E1000_RCTL_LPE; 2480 break; 2481 case EM_RXBUFFER_8192: 2482 reg_rctl |= E1000_RCTL_SZ_8192|E1000_RCTL_BSEX|E1000_RCTL_LPE; 2483 break; 2484 case EM_RXBUFFER_16384: 2485 reg_rctl |= E1000_RCTL_SZ_16384|E1000_RCTL_BSEX|E1000_RCTL_LPE; 2486 break; 2487 } 2488 2489 if (sc->hw.max_frame_size != ETHER_MAX_LEN) 2490 reg_rctl |= E1000_RCTL_LPE; 2491 2492 /* Enable 82543 Receive Checksum Offload for TCP and UDP */ 2493 if (sc->hw.mac_type >= em_82543) { 2494 reg_rxcsum = E1000_READ_REG(&sc->hw, RXCSUM); 2495 reg_rxcsum |= (E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL); 2496 E1000_WRITE_REG(&sc->hw, RXCSUM, reg_rxcsum); 2497 } 2498 2499 /* Enable Receives */ 2500 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 2501 2502 /* Setup the HW Rx Head and Tail Descriptor Pointers */ 2503 E1000_WRITE_REG(&sc->hw, RDH, 0); 2504 E1000_WRITE_REG(&sc->hw, RDT, sc->last_rx_desc_filled); 2505 } 2506 2507 /********************************************************************* 2508 * 2509 * Free receive related data structures. 2510 * 2511 **********************************************************************/ 2512 void 2513 em_free_receive_structures(struct em_softc *sc) 2514 { 2515 struct em_buffer *rx_buffer; 2516 int i; 2517 2518 INIT_DEBUGOUT("free_receive_structures: begin"); 2519 2520 if (sc->rx_buffer_area != NULL) { 2521 rx_buffer = sc->rx_buffer_area; 2522 for (i = 0; i < sc->num_rx_desc; i++, rx_buffer++) { 2523 if (rx_buffer->m_head != NULL) { 2524 bus_dmamap_sync(sc->rxtag, rx_buffer->map, 2525 0, rx_buffer->map->dm_mapsize, 2526 BUS_DMASYNC_POSTREAD); 2527 bus_dmamap_unload(sc->rxtag, rx_buffer->map); 2528 m_freem(rx_buffer->m_head); 2529 rx_buffer->m_head = NULL; 2530 } 2531 bus_dmamap_destroy(sc->rxtag, rx_buffer->map); 2532 } 2533 } 2534 if (sc->rx_buffer_area != NULL) { 2535 free(sc->rx_buffer_area, M_DEVBUF); 2536 sc->rx_buffer_area = NULL; 2537 } 2538 if (sc->rxtag != NULL) 2539 sc->rxtag = NULL; 2540 2541 if (sc->fmp != NULL) { 2542 m_freem(sc->fmp); 2543 sc->fmp = NULL; 2544 sc->lmp = NULL; 2545 } 2546 } 2547 2548 #ifdef __STRICT_ALIGNMENT 2549 void 2550 em_realign(struct em_softc *sc, struct mbuf *m, u_int16_t *prev_len_adj) 2551 { 2552 unsigned char tmp_align_buf[ETHER_ALIGN]; 2553 int tmp_align_buf_len = 0; 2554 2555 /* 2556 * The Ethernet payload is not 32-bit aligned when 2557 * Jumbo packets are enabled, so on architectures with 2558 * strict alignment we need to shift the entire packet 2559 * ETHER_ALIGN bytes. Ugh. 2560 */ 2561 if (sc->hw.max_frame_size <= (MCLBYTES - ETHER_ALIGN)) 2562 return; 2563 2564 if (*prev_len_adj > sc->align_buf_len) 2565 *prev_len_adj -= sc->align_buf_len; 2566 else 2567 *prev_len_adj = 0; 2568 2569 if (m->m_len > (MCLBYTES - ETHER_ALIGN)) { 2570 bcopy(m->m_data + (MCLBYTES - ETHER_ALIGN), 2571 &tmp_align_buf, ETHER_ALIGN); 2572 tmp_align_buf_len = m->m_len - 2573 (MCLBYTES - ETHER_ALIGN); 2574 m->m_len -= ETHER_ALIGN; 2575 } 2576 2577 if (m->m_len) { 2578 bcopy(m->m_data, m->m_data + ETHER_ALIGN, m->m_len); 2579 if (!sc->align_buf_len) 2580 m->m_data += ETHER_ALIGN; 2581 } 2582 2583 if (sc->align_buf_len) { 2584 m->m_len += sc->align_buf_len; 2585 bcopy(&sc->align_buf, m->m_data, sc->align_buf_len); 2586 } 2587 2588 if (tmp_align_buf_len) 2589 bcopy(&tmp_align_buf, &sc->align_buf, tmp_align_buf_len); 2590 2591 sc->align_buf_len = tmp_align_buf_len; 2592 } 2593 #endif /* __STRICT_ALIGNMENT */ 2594 2595 int 2596 em_rxfill(struct em_softc *sc) 2597 { 2598 int post = 0; 2599 int i; 2600 2601 i = sc->last_rx_desc_filled; 2602 2603 while (sc->rx_ndescs < sc->num_rx_desc) { 2604 if (++i == sc->num_rx_desc) 2605 i = 0; 2606 2607 if (em_get_buf(sc, i) != 0) 2608 break; 2609 2610 sc->last_rx_desc_filled = i; 2611 post = 1; 2612 } 2613 2614 return (post); 2615 } 2616 2617 /********************************************************************* 2618 * 2619 * This routine executes in interrupt context. It replenishes 2620 * the mbufs in the descriptor and sends data which has been 2621 * dma'ed into host memory to upper layer. 2622 * 2623 * We loop at most count times if count is > 0, or until done if 2624 * count < 0. 2625 * 2626 *********************************************************************/ 2627 void 2628 em_rxeof(struct em_softc *sc, int count) 2629 { 2630 struct ifnet *ifp = &sc->interface_data.ac_if; 2631 struct mbuf *m; 2632 u_int8_t accept_frame = 0; 2633 u_int8_t eop = 0; 2634 u_int16_t len, desc_len, prev_len_adj; 2635 int i; 2636 2637 /* Pointer to the receive descriptor being examined. */ 2638 struct em_rx_desc *desc; 2639 struct em_buffer *pkt; 2640 u_int8_t status; 2641 2642 ifp = &sc->interface_data.ac_if; 2643 2644 if (!ISSET(ifp->if_flags, IFF_RUNNING)) 2645 return; 2646 2647 i = sc->next_rx_desc_to_check; 2648 2649 while (count != 0 && sc->rx_ndescs > 0) { 2650 m = NULL; 2651 2652 desc = &sc->rx_desc_base[i]; 2653 pkt = &sc->rx_buffer_area[i]; 2654 2655 bus_dmamap_sync(sc->rxdma.dma_tag, sc->rxdma.dma_map, 2656 sizeof(*desc) * i, sizeof(*desc), 2657 BUS_DMASYNC_POSTREAD); 2658 2659 status = desc->status; 2660 if (!ISSET(status, E1000_RXD_STAT_DD)) { 2661 bus_dmamap_sync(sc->rxdma.dma_tag, sc->rxdma.dma_map, 2662 sizeof(*desc) * i, sizeof(*desc), 2663 BUS_DMASYNC_PREREAD); 2664 break; 2665 } 2666 2667 /* pull the mbuf off the ring */ 2668 bus_dmamap_sync(sc->rxtag, pkt->map, 0, pkt->map->dm_mapsize, 2669 BUS_DMASYNC_POSTREAD); 2670 bus_dmamap_unload(sc->rxtag, pkt->map); 2671 m = pkt->m_head; 2672 pkt->m_head = NULL; 2673 2674 if (m == NULL) { 2675 panic("em_rxeof: NULL mbuf in slot %d " 2676 "(nrx %d, filled %d)", i, sc->rx_ndescs, 2677 sc->last_rx_desc_filled); 2678 } 2679 2680 m_cluncount(m, 1); 2681 sc->rx_ndescs--; 2682 2683 accept_frame = 1; 2684 prev_len_adj = 0; 2685 desc_len = letoh16(desc->length); 2686 2687 if (status & E1000_RXD_STAT_EOP) { 2688 count--; 2689 eop = 1; 2690 if (desc_len < ETHER_CRC_LEN) { 2691 len = 0; 2692 prev_len_adj = ETHER_CRC_LEN - desc_len; 2693 } else 2694 len = desc_len - ETHER_CRC_LEN; 2695 } else { 2696 eop = 0; 2697 len = desc_len; 2698 } 2699 2700 if (desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK) { 2701 u_int8_t last_byte; 2702 u_int32_t pkt_len = desc_len; 2703 2704 if (sc->fmp != NULL) 2705 pkt_len += sc->fmp->m_pkthdr.len; 2706 2707 last_byte = *(mtod(m, caddr_t) + desc_len - 1); 2708 if (TBI_ACCEPT(&sc->hw, status, desc->errors, 2709 pkt_len, last_byte)) { 2710 em_tbi_adjust_stats(&sc->hw, &sc->stats, 2711 pkt_len, sc->hw.mac_addr); 2712 if (len > 0) 2713 len--; 2714 } else 2715 accept_frame = 0; 2716 } 2717 2718 if (accept_frame) { 2719 /* Assign correct length to the current fragment */ 2720 m->m_len = len; 2721 2722 em_realign(sc, m, &prev_len_adj); /* STRICT_ALIGN */ 2723 2724 if (sc->fmp == NULL) { 2725 m->m_pkthdr.len = m->m_len; 2726 sc->fmp = m; /* Store the first mbuf */ 2727 sc->lmp = m; 2728 } else { 2729 /* Chain mbuf's together */ 2730 m->m_flags &= ~M_PKTHDR; 2731 /* 2732 * Adjust length of previous mbuf in chain if 2733 * we received less than 4 bytes in the last 2734 * descriptor. 2735 */ 2736 if (prev_len_adj > 0) { 2737 sc->lmp->m_len -= prev_len_adj; 2738 sc->fmp->m_pkthdr.len -= prev_len_adj; 2739 } 2740 sc->lmp->m_next = m; 2741 sc->lmp = m; 2742 sc->fmp->m_pkthdr.len += m->m_len; 2743 } 2744 2745 if (eop) { 2746 ifp->if_ipackets++; 2747 2748 m = sc->fmp; 2749 m->m_pkthdr.rcvif = ifp; 2750 2751 em_receive_checksum(sc, desc, m); 2752 #if NVLAN > 0 2753 if (desc->status & E1000_RXD_STAT_VP) { 2754 m->m_pkthdr.ether_vtag = 2755 (desc->special & 2756 E1000_RXD_SPC_VLAN_MASK); 2757 m->m_flags |= M_VLANTAG; 2758 } 2759 #endif 2760 #if NBPFILTER > 0 2761 if (ifp->if_bpf) { 2762 bpf_mtap_ether(ifp->if_bpf, m, 2763 BPF_DIRECTION_IN); 2764 } 2765 #endif 2766 2767 ether_input_mbuf(ifp, m); 2768 2769 sc->fmp = NULL; 2770 sc->lmp = NULL; 2771 } 2772 } else { 2773 sc->dropped_pkts++; 2774 2775 if (sc->fmp != NULL) { 2776 m_freem(sc->fmp); 2777 sc->fmp = NULL; 2778 sc->lmp = NULL; 2779 } 2780 2781 m_freem(m); 2782 } 2783 2784 bus_dmamap_sync(sc->rxdma.dma_tag, sc->rxdma.dma_map, 2785 sizeof(*desc) * i, sizeof(*desc), 2786 BUS_DMASYNC_PREREAD); 2787 2788 /* Advance our pointers to the next descriptor. */ 2789 if (++i == sc->num_rx_desc) 2790 i = 0; 2791 } 2792 sc->next_rx_desc_to_check = i; 2793 } 2794 2795 /********************************************************************* 2796 * 2797 * Verify that the hardware indicated that the checksum is valid. 2798 * Inform the stack about the status of checksum so that stack 2799 * doesn't spend time verifying the checksum. 2800 * 2801 *********************************************************************/ 2802 void 2803 em_receive_checksum(struct em_softc *sc, struct em_rx_desc *rx_desc, 2804 struct mbuf *mp) 2805 { 2806 /* 82543 or newer only */ 2807 if ((sc->hw.mac_type < em_82543) || 2808 /* Ignore Checksum bit is set */ 2809 (rx_desc->status & E1000_RXD_STAT_IXSM)) { 2810 mp->m_pkthdr.csum_flags = 0; 2811 return; 2812 } 2813 2814 if (rx_desc->status & E1000_RXD_STAT_IPCS) { 2815 /* Did it pass? */ 2816 if (!(rx_desc->errors & E1000_RXD_ERR_IPE)) { 2817 /* IP Checksum Good */ 2818 mp->m_pkthdr.csum_flags = M_IPV4_CSUM_IN_OK; 2819 2820 } else 2821 mp->m_pkthdr.csum_flags = 0; 2822 } 2823 2824 if (rx_desc->status & E1000_RXD_STAT_TCPCS) { 2825 /* Did it pass? */ 2826 if (!(rx_desc->errors & E1000_RXD_ERR_TCPE)) 2827 mp->m_pkthdr.csum_flags |= 2828 M_TCP_CSUM_IN_OK | M_UDP_CSUM_IN_OK; 2829 } 2830 } 2831 2832 /* 2833 * This turns on the hardware offload of the VLAN 2834 * tag insertion and strip 2835 */ 2836 void 2837 em_enable_hw_vlans(struct em_softc *sc) 2838 { 2839 uint32_t ctrl; 2840 2841 ctrl = E1000_READ_REG(&sc->hw, CTRL); 2842 ctrl |= E1000_CTRL_VME; 2843 E1000_WRITE_REG(&sc->hw, CTRL, ctrl); 2844 } 2845 2846 void 2847 em_enable_intr(struct em_softc *sc) 2848 { 2849 E1000_WRITE_REG(&sc->hw, IMS, (IMS_ENABLE_MASK)); 2850 } 2851 2852 void 2853 em_disable_intr(struct em_softc *sc) 2854 { 2855 /* 2856 * The first version of 82542 had an errata where when link 2857 * was forced it would stay up even if the cable was disconnected 2858 * Sequence errors were used to detect the disconnect and then 2859 * the driver would unforce the link. This code is in the ISR. 2860 * For this to work correctly the Sequence error interrupt had 2861 * to be enabled all the time. 2862 */ 2863 2864 if (sc->hw.mac_type == em_82542_rev2_0) 2865 E1000_WRITE_REG(&sc->hw, IMC, (0xffffffff & ~E1000_IMC_RXSEQ)); 2866 else 2867 E1000_WRITE_REG(&sc->hw, IMC, 0xffffffff); 2868 } 2869 2870 int 2871 em_is_valid_ether_addr(u_int8_t *addr) 2872 { 2873 const char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 2874 2875 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) 2876 return (FALSE); 2877 2878 return (TRUE); 2879 } 2880 2881 void 2882 em_write_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t *value) 2883 { 2884 struct pci_attach_args *pa = &((struct em_osdep *)hw->back)->em_pa; 2885 pci_chipset_tag_t pc = pa->pa_pc; 2886 /* Should we do read/mask/write...? 16 vs 32 bit!!! */ 2887 pci_conf_write(pc, pa->pa_tag, reg, *value); 2888 } 2889 2890 void 2891 em_read_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t *value) 2892 { 2893 struct pci_attach_args *pa = &((struct em_osdep *)hw->back)->em_pa; 2894 pci_chipset_tag_t pc = pa->pa_pc; 2895 *value = pci_conf_read(pc, pa->pa_tag, reg); 2896 } 2897 2898 void 2899 em_pci_set_mwi(struct em_hw *hw) 2900 { 2901 struct pci_attach_args *pa = &((struct em_osdep *)hw->back)->em_pa; 2902 pci_chipset_tag_t pc = pa->pa_pc; 2903 /* Should we do read/mask/write...? 16 vs 32 bit!!! */ 2904 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 2905 (hw->pci_cmd_word | CMD_MEM_WRT_INVALIDATE)); 2906 } 2907 2908 void 2909 em_pci_clear_mwi(struct em_hw *hw) 2910 { 2911 struct pci_attach_args *pa = &((struct em_osdep *)hw->back)->em_pa; 2912 pci_chipset_tag_t pc = pa->pa_pc; 2913 /* Should we do read/mask/write...? 16 vs 32 bit!!! */ 2914 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 2915 (hw->pci_cmd_word & ~CMD_MEM_WRT_INVALIDATE)); 2916 } 2917 2918 /* 2919 * We may eventually really do this, but its unnecessary 2920 * for now so we just return unsupported. 2921 */ 2922 int32_t 2923 em_read_pcie_cap_reg(struct em_hw *hw, uint32_t reg, uint16_t *value) 2924 { 2925 return -E1000_NOT_IMPLEMENTED; 2926 } 2927 2928 /********************************************************************* 2929 * 82544 Coexistence issue workaround. 2930 * There are 2 issues. 2931 * 1. Transmit Hang issue. 2932 * To detect this issue, following equation can be used... 2933 * SIZE[3:0] + ADDR[2:0] = SUM[3:0]. 2934 * If SUM[3:0] is in between 1 to 4, we will have this issue. 2935 * 2936 * 2. DAC issue. 2937 * To detect this issue, following equation can be used... 2938 * SIZE[3:0] + ADDR[2:0] = SUM[3:0]. 2939 * If SUM[3:0] is in between 9 to c, we will have this issue. 2940 * 2941 * 2942 * WORKAROUND: 2943 * Make sure we do not have ending address as 1,2,3,4(Hang) or 9,a,b,c (DAC) 2944 * 2945 *** *********************************************************************/ 2946 u_int32_t 2947 em_fill_descriptors(u_int64_t address, u_int32_t length, 2948 PDESC_ARRAY desc_array) 2949 { 2950 /* Since issue is sensitive to length and address.*/ 2951 /* Let us first check the address...*/ 2952 u_int32_t safe_terminator; 2953 if (length <= 4) { 2954 desc_array->descriptor[0].address = address; 2955 desc_array->descriptor[0].length = length; 2956 desc_array->elements = 1; 2957 return desc_array->elements; 2958 } 2959 safe_terminator = (u_int32_t)((((u_int32_t)address & 0x7) + (length & 0xF)) & 0xF); 2960 /* if it does not fall between 0x1 to 0x4 and 0x9 to 0xC then return */ 2961 if (safe_terminator == 0 || 2962 (safe_terminator > 4 && 2963 safe_terminator < 9) || 2964 (safe_terminator > 0xC && 2965 safe_terminator <= 0xF)) { 2966 desc_array->descriptor[0].address = address; 2967 desc_array->descriptor[0].length = length; 2968 desc_array->elements = 1; 2969 return desc_array->elements; 2970 } 2971 2972 desc_array->descriptor[0].address = address; 2973 desc_array->descriptor[0].length = length - 4; 2974 desc_array->descriptor[1].address = address + (length - 4); 2975 desc_array->descriptor[1].length = 4; 2976 desc_array->elements = 2; 2977 return desc_array->elements; 2978 } 2979 2980 /********************************************************************** 2981 * 2982 * Update the board statistics counters. 2983 * 2984 **********************************************************************/ 2985 void 2986 em_update_stats_counters(struct em_softc *sc) 2987 { 2988 struct ifnet *ifp; 2989 2990 if (sc->hw.media_type == em_media_type_copper || 2991 (E1000_READ_REG(&sc->hw, STATUS) & E1000_STATUS_LU)) { 2992 sc->stats.symerrs += E1000_READ_REG(&sc->hw, SYMERRS); 2993 sc->stats.sec += E1000_READ_REG(&sc->hw, SEC); 2994 } 2995 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, CRCERRS); 2996 sc->stats.mpc += E1000_READ_REG(&sc->hw, MPC); 2997 sc->stats.scc += E1000_READ_REG(&sc->hw, SCC); 2998 sc->stats.ecol += E1000_READ_REG(&sc->hw, ECOL); 2999 3000 sc->stats.mcc += E1000_READ_REG(&sc->hw, MCC); 3001 sc->stats.latecol += E1000_READ_REG(&sc->hw, LATECOL); 3002 sc->stats.colc += E1000_READ_REG(&sc->hw, COLC); 3003 sc->stats.dc += E1000_READ_REG(&sc->hw, DC); 3004 sc->stats.rlec += E1000_READ_REG(&sc->hw, RLEC); 3005 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, XONRXC); 3006 sc->stats.xontxc += E1000_READ_REG(&sc->hw, XONTXC); 3007 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, XOFFRXC); 3008 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, XOFFTXC); 3009 sc->stats.fcruc += E1000_READ_REG(&sc->hw, FCRUC); 3010 sc->stats.prc64 += E1000_READ_REG(&sc->hw, PRC64); 3011 sc->stats.prc127 += E1000_READ_REG(&sc->hw, PRC127); 3012 sc->stats.prc255 += E1000_READ_REG(&sc->hw, PRC255); 3013 sc->stats.prc511 += E1000_READ_REG(&sc->hw, PRC511); 3014 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, PRC1023); 3015 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, PRC1522); 3016 sc->stats.gprc += E1000_READ_REG(&sc->hw, GPRC); 3017 sc->stats.bprc += E1000_READ_REG(&sc->hw, BPRC); 3018 sc->stats.mprc += E1000_READ_REG(&sc->hw, MPRC); 3019 sc->stats.gptc += E1000_READ_REG(&sc->hw, GPTC); 3020 3021 /* For the 64-bit byte counters the low dword must be read first. */ 3022 /* Both registers clear on the read of the high dword */ 3023 3024 sc->stats.gorcl += E1000_READ_REG(&sc->hw, GORCL); 3025 sc->stats.gorch += E1000_READ_REG(&sc->hw, GORCH); 3026 sc->stats.gotcl += E1000_READ_REG(&sc->hw, GOTCL); 3027 sc->stats.gotch += E1000_READ_REG(&sc->hw, GOTCH); 3028 3029 sc->stats.rnbc += E1000_READ_REG(&sc->hw, RNBC); 3030 sc->stats.ruc += E1000_READ_REG(&sc->hw, RUC); 3031 sc->stats.rfc += E1000_READ_REG(&sc->hw, RFC); 3032 sc->stats.roc += E1000_READ_REG(&sc->hw, ROC); 3033 sc->stats.rjc += E1000_READ_REG(&sc->hw, RJC); 3034 3035 sc->stats.torl += E1000_READ_REG(&sc->hw, TORL); 3036 sc->stats.torh += E1000_READ_REG(&sc->hw, TORH); 3037 sc->stats.totl += E1000_READ_REG(&sc->hw, TOTL); 3038 sc->stats.toth += E1000_READ_REG(&sc->hw, TOTH); 3039 3040 sc->stats.tpr += E1000_READ_REG(&sc->hw, TPR); 3041 sc->stats.tpt += E1000_READ_REG(&sc->hw, TPT); 3042 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, PTC64); 3043 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, PTC127); 3044 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, PTC255); 3045 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, PTC511); 3046 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, PTC1023); 3047 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, PTC1522); 3048 sc->stats.mptc += E1000_READ_REG(&sc->hw, MPTC); 3049 sc->stats.bptc += E1000_READ_REG(&sc->hw, BPTC); 3050 3051 if (sc->hw.mac_type >= em_82543) { 3052 sc->stats.algnerrc += 3053 E1000_READ_REG(&sc->hw, ALGNERRC); 3054 sc->stats.rxerrc += 3055 E1000_READ_REG(&sc->hw, RXERRC); 3056 sc->stats.tncrs += 3057 E1000_READ_REG(&sc->hw, TNCRS); 3058 sc->stats.cexterr += 3059 E1000_READ_REG(&sc->hw, CEXTERR); 3060 sc->stats.tsctc += 3061 E1000_READ_REG(&sc->hw, TSCTC); 3062 sc->stats.tsctfc += 3063 E1000_READ_REG(&sc->hw, TSCTFC); 3064 } 3065 ifp = &sc->interface_data.ac_if; 3066 3067 /* Fill out the OS statistics structure */ 3068 ifp->if_collisions = sc->stats.colc; 3069 3070 /* Rx Errors */ 3071 ifp->if_ierrors = 3072 sc->dropped_pkts + 3073 sc->stats.rxerrc + 3074 sc->stats.crcerrs + 3075 sc->stats.algnerrc + 3076 sc->stats.ruc + sc->stats.roc + 3077 sc->stats.mpc + sc->stats.cexterr + 3078 sc->rx_overruns; 3079 3080 /* Tx Errors */ 3081 ifp->if_oerrors = sc->stats.ecol + sc->stats.latecol + 3082 sc->watchdog_events; 3083 } 3084 3085 #ifdef EM_DEBUG 3086 /********************************************************************** 3087 * 3088 * This routine is called only when em_display_debug_stats is enabled. 3089 * This routine provides a way to take a look at important statistics 3090 * maintained by the driver and hardware. 3091 * 3092 **********************************************************************/ 3093 void 3094 em_print_hw_stats(struct em_softc *sc) 3095 { 3096 const char * const unit = sc->sc_dv.dv_xname; 3097 3098 printf("%s: Excessive collisions = %lld\n", unit, 3099 (long long)sc->stats.ecol); 3100 printf("%s: Symbol errors = %lld\n", unit, 3101 (long long)sc->stats.symerrs); 3102 printf("%s: Sequence errors = %lld\n", unit, 3103 (long long)sc->stats.sec); 3104 printf("%s: Defer count = %lld\n", unit, 3105 (long long)sc->stats.dc); 3106 3107 printf("%s: Missed Packets = %lld\n", unit, 3108 (long long)sc->stats.mpc); 3109 printf("%s: Receive No Buffers = %lld\n", unit, 3110 (long long)sc->stats.rnbc); 3111 /* RLEC is inaccurate on some hardware, calculate our own */ 3112 printf("%s: Receive Length Errors = %lld\n", unit, 3113 ((long long)sc->stats.roc + 3114 (long long)sc->stats.ruc)); 3115 printf("%s: Receive errors = %lld\n", unit, 3116 (long long)sc->stats.rxerrc); 3117 printf("%s: Crc errors = %lld\n", unit, 3118 (long long)sc->stats.crcerrs); 3119 printf("%s: Alignment errors = %lld\n", unit, 3120 (long long)sc->stats.algnerrc); 3121 printf("%s: Carrier extension errors = %lld\n", unit, 3122 (long long)sc->stats.cexterr); 3123 3124 printf("%s: RX overruns = %ld\n", unit, 3125 sc->rx_overruns); 3126 printf("%s: watchdog timeouts = %ld\n", unit, 3127 sc->watchdog_events); 3128 3129 printf("%s: XON Rcvd = %lld\n", unit, 3130 (long long)sc->stats.xonrxc); 3131 printf("%s: XON Xmtd = %lld\n", unit, 3132 (long long)sc->stats.xontxc); 3133 printf("%s: XOFF Rcvd = %lld\n", unit, 3134 (long long)sc->stats.xoffrxc); 3135 printf("%s: XOFF Xmtd = %lld\n", unit, 3136 (long long)sc->stats.xofftxc); 3137 3138 printf("%s: Good Packets Rcvd = %lld\n", unit, 3139 (long long)sc->stats.gprc); 3140 printf("%s: Good Packets Xmtd = %lld\n", unit, 3141 (long long)sc->stats.gptc); 3142 } 3143 #endif 3144