1 /************************************************************************** 2 3 Copyright (c) 2001-2003, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ***************************************************************************/ 33 34 /* $OpenBSD: if_em.c,v 1.346 2020/03/03 10:43:29 mpi Exp $ */ 35 /* $FreeBSD: if_em.c,v 1.46 2004/09/29 18:28:28 mlaier Exp $ */ 36 37 #include <dev/pci/if_em.h> 38 #include <dev/pci/if_em_soc.h> 39 40 /********************************************************************* 41 * Driver version 42 *********************************************************************/ 43 44 #define EM_DRIVER_VERSION "6.2.9" 45 46 /********************************************************************* 47 * PCI Device ID Table 48 *********************************************************************/ 49 const struct pci_matchid em_devices[] = { 50 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80003ES2LAN_CPR_DPT }, 51 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80003ES2LAN_SDS_DPT }, 52 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80003ES2LAN_CPR_SPT }, 53 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80003ES2LAN_SDS_SPT }, 54 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM }, 55 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM_LOM }, 56 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP }, 57 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LOM }, 58 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LP }, 59 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI }, 60 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI_MOBILE }, 61 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541ER }, 62 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541ER_LOM }, 63 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI }, 64 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI_LF }, 65 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI_MOBILE }, 66 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82542 }, 67 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_COPPER }, 68 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_FIBER }, 69 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_COPPER }, 70 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_FIBER }, 71 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_COPPER }, 72 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_LOM }, 73 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_COPPER }, 74 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_FIBER }, 75 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_COPPER }, 76 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_FIBER }, 77 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_SERDES }, 78 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_COPPER }, 79 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_FIBER }, 80 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_QUAD_CPR }, 81 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_COPPER }, 82 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_FIBER }, 83 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_PCIE }, 84 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_QUAD_CPR }, 85 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_QUAD_CPR_K }, 86 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_SERDES }, 87 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_2 }, 88 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547EI }, 89 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547EI_MOBILE }, 90 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547GI }, 91 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_AF }, 92 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_AT }, 93 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_COPPER }, 94 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_FIBER }, 95 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_QUAD_CPR }, 96 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_QUAD_CPR_LP }, 97 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_QUAD_FBR }, 98 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_SERDES }, 99 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_SDS_DUAL }, 100 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_SDS_QUAD }, 101 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571PT_QUAD_CPR }, 102 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI_COPPER }, 103 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI_FIBER }, 104 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI_SERDES }, 105 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI }, 106 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573E }, 107 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573E_IAMT }, 108 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573E_PM }, 109 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573L }, 110 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573L_PL_1 }, 111 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573L_PL_2 }, 112 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573V_PM }, 113 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82574L }, 114 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82574LA }, 115 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82575EB_COPPER }, 116 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82575EB_SERDES }, 117 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82575GB_QUAD_CPR }, 118 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82575GB_QP_PM }, 119 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576 }, 120 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_FIBER }, 121 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_SERDES }, 122 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_QUAD_COPPER }, 123 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_QUAD_CU_ET2 }, 124 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_NS }, 125 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_NS_SERDES }, 126 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_SERDES_QUAD }, 127 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82577LC }, 128 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82577LM }, 129 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82578DC }, 130 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82578DM }, 131 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82579LM }, 132 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82579V }, 133 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_COPPER }, 134 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_COPPER_OEM1 }, 135 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_COPPER_IT }, 136 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_FIBER }, 137 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_SERDES }, 138 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_SGMII }, 139 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_COPPER_NF }, 140 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_SERDES_NF }, 141 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I211_COPPER }, 142 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I217_LM }, 143 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I217_V }, 144 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_LM }, 145 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_LM_2 }, 146 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_LM_3 }, 147 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_V }, 148 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_V_2 }, 149 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_V_3 }, 150 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_LM }, 151 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_LM2 }, 152 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_LM3 }, 153 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_LM4 }, 154 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_LM5 }, 155 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_LM6 }, 156 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_LM7 }, 157 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_LM8 }, 158 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_LM9 }, 159 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_LM10 }, 160 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_LM11 }, 161 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_LM12 }, 162 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_LM13 }, 163 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_LM14 }, 164 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_LM15 }, 165 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_V }, 166 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_V2 }, 167 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_V4 }, 168 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_V5 }, 169 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_V6 }, 170 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_V7 }, 171 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_V8 }, 172 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_V9 }, 173 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_V10 }, 174 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_V11 }, 175 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_V12 }, 176 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_V13 }, 177 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_V14 }, 178 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_COPPER }, 179 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_FIBER }, 180 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_SERDES }, 181 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_SGMII }, 182 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_COPPER_DUAL }, 183 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_QUAD_FIBER }, 184 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCC_SGMII }, 185 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCC_SERDES }, 186 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCC_BPLANE }, 187 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCC_SFP }, 188 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82583V }, 189 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I350_COPPER }, 190 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I350_FIBER }, 191 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I350_SERDES }, 192 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I350_SGMII }, 193 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I354_BP_1GBPS }, 194 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I354_BP_2_5GBPS }, 195 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I354_SGMII }, 196 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_82567V_3 }, 197 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_IFE }, 198 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_IFE_G }, 199 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_IFE_GT }, 200 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_IGP_AMT }, 201 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_IGP_C }, 202 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_IGP_M }, 203 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_IGP_M_AMT }, 204 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_BM }, 205 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IFE }, 206 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IFE_G }, 207 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IFE_GT }, 208 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IGP_AMT }, 209 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IGP_C }, 210 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IGP_M }, 211 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IGP_M_AMT }, 212 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IGP_M_V }, 213 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH10_D_BM_LF }, 214 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH10_D_BM_LM }, 215 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH10_D_BM_V }, 216 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH10_R_BM_LF }, 217 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH10_R_BM_LM }, 218 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH10_R_BM_V }, 219 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EP80579_LAN_1 }, 220 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EP80579_LAN_2 }, 221 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EP80579_LAN_3 }, 222 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EP80579_LAN_4 }, 223 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EP80579_LAN_5 }, 224 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EP80579_LAN_6 } 225 }; 226 227 /********************************************************************* 228 * Function prototypes 229 *********************************************************************/ 230 int em_probe(struct device *, void *, void *); 231 void em_attach(struct device *, struct device *, void *); 232 void em_defer_attach(struct device*); 233 int em_detach(struct device *, int); 234 int em_activate(struct device *, int); 235 int em_intr(void *); 236 void em_start(struct ifqueue *); 237 int em_ioctl(struct ifnet *, u_long, caddr_t); 238 void em_watchdog(struct ifnet *); 239 void em_init(void *); 240 void em_stop(void *, int); 241 void em_media_status(struct ifnet *, struct ifmediareq *); 242 int em_media_change(struct ifnet *); 243 uint64_t em_flowstatus(struct em_softc *); 244 void em_identify_hardware(struct em_softc *); 245 int em_allocate_pci_resources(struct em_softc *); 246 void em_free_pci_resources(struct em_softc *); 247 void em_local_timer(void *); 248 int em_hardware_init(struct em_softc *); 249 void em_setup_interface(struct em_softc *); 250 int em_setup_transmit_structures(struct em_softc *); 251 void em_initialize_transmit_unit(struct em_softc *); 252 int em_setup_receive_structures(struct em_softc *); 253 void em_initialize_receive_unit(struct em_softc *); 254 void em_enable_intr(struct em_softc *); 255 void em_disable_intr(struct em_softc *); 256 void em_free_transmit_structures(struct em_softc *); 257 void em_free_receive_structures(struct em_softc *); 258 void em_update_stats_counters(struct em_softc *); 259 void em_disable_aspm(struct em_softc *); 260 void em_txeof(struct em_queue *); 261 int em_allocate_receive_structures(struct em_softc *); 262 int em_allocate_transmit_structures(struct em_softc *); 263 int em_allocate_desc_rings(struct em_softc *); 264 int em_rxfill(struct em_queue *); 265 void em_rxrefill(void *); 266 int em_rxeof(struct em_queue *); 267 void em_receive_checksum(struct em_softc *, struct em_rx_desc *, 268 struct mbuf *); 269 u_int em_transmit_checksum_setup(struct em_queue *, struct mbuf *, u_int, 270 u_int32_t *, u_int32_t *); 271 void em_iff(struct em_softc *); 272 #ifdef EM_DEBUG 273 void em_print_hw_stats(struct em_softc *); 274 #endif 275 void em_update_link_status(struct em_softc *); 276 int em_get_buf(struct em_queue *, int); 277 void em_enable_hw_vlans(struct em_softc *); 278 u_int em_encap(struct em_queue *, struct mbuf *); 279 void em_smartspeed(struct em_softc *); 280 int em_82547_fifo_workaround(struct em_softc *, int); 281 void em_82547_update_fifo_head(struct em_softc *, int); 282 int em_82547_tx_fifo_reset(struct em_softc *); 283 void em_82547_move_tail(void *arg); 284 void em_82547_move_tail_locked(struct em_softc *); 285 int em_dma_malloc(struct em_softc *, bus_size_t, struct em_dma_alloc *); 286 void em_dma_free(struct em_softc *, struct em_dma_alloc *); 287 u_int32_t em_fill_descriptors(u_int64_t address, u_int32_t length, 288 PDESC_ARRAY desc_array); 289 void em_flush_tx_ring(struct em_queue *); 290 void em_flush_rx_ring(struct em_queue *); 291 void em_flush_desc_rings(struct em_softc *); 292 293 /********************************************************************* 294 * OpenBSD Device Interface Entry Points 295 *********************************************************************/ 296 297 struct cfattach em_ca = { 298 sizeof(struct em_softc), em_probe, em_attach, em_detach, 299 em_activate 300 }; 301 302 struct cfdriver em_cd = { 303 NULL, "em", DV_IFNET 304 }; 305 306 static int em_smart_pwr_down = FALSE; 307 308 /********************************************************************* 309 * Device identification routine 310 * 311 * em_probe determines if the driver should be loaded on 312 * adapter based on PCI vendor/device id of the adapter. 313 * 314 * return 0 on no match, positive on match 315 *********************************************************************/ 316 317 int 318 em_probe(struct device *parent, void *match, void *aux) 319 { 320 INIT_DEBUGOUT("em_probe: begin"); 321 322 return (pci_matchbyid((struct pci_attach_args *)aux, em_devices, 323 nitems(em_devices))); 324 } 325 326 void 327 em_defer_attach(struct device *self) 328 { 329 struct em_softc *sc = (struct em_softc *)self; 330 struct pci_attach_args *pa = &sc->osdep.em_pa; 331 pci_chipset_tag_t pc = pa->pa_pc; 332 void *gcu; 333 334 INIT_DEBUGOUT("em_defer_attach: begin"); 335 336 if ((gcu = em_lookup_gcu(self)) == 0) { 337 printf("%s: No GCU found, defered attachment failed\n", 338 DEVNAME(sc)); 339 340 if (sc->sc_intrhand) 341 pci_intr_disestablish(pc, sc->sc_intrhand); 342 sc->sc_intrhand = 0; 343 344 em_stop(sc, 1); 345 346 em_free_pci_resources(sc); 347 348 return; 349 } 350 351 sc->hw.gcu = gcu; 352 353 em_attach_miibus(self); 354 355 em_setup_interface(sc); 356 357 em_setup_link(&sc->hw); 358 359 em_update_link_status(sc); 360 } 361 362 /********************************************************************* 363 * Device initialization routine 364 * 365 * The attach entry point is called when the driver is being loaded. 366 * This routine identifies the type of hardware, allocates all resources 367 * and initializes the hardware. 368 * 369 *********************************************************************/ 370 371 void 372 em_attach(struct device *parent, struct device *self, void *aux) 373 { 374 struct pci_attach_args *pa = aux; 375 struct em_softc *sc; 376 int defer = 0; 377 378 INIT_DEBUGOUT("em_attach: begin"); 379 380 sc = (struct em_softc *)self; 381 sc->sc_dmat = pa->pa_dmat; 382 sc->osdep.em_pa = *pa; 383 384 timeout_set(&sc->timer_handle, em_local_timer, sc); 385 timeout_set(&sc->tx_fifo_timer_handle, em_82547_move_tail, sc); 386 387 /* Determine hardware revision */ 388 em_identify_hardware(sc); 389 390 /* 391 * Only use MSI on the newer PCIe parts, with the exception 392 * of 82571/82572 due to "Byte Enables 2 and 3 Are Not Set" errata 393 */ 394 if (sc->hw.mac_type <= em_82572) 395 sc->osdep.em_pa.pa_flags &= ~PCI_FLAGS_MSI_ENABLED; 396 397 /* Parameters (to be read from user) */ 398 if (sc->hw.mac_type >= em_82544) { 399 sc->sc_tx_slots = EM_MAX_TXD; 400 sc->sc_rx_slots = EM_MAX_RXD; 401 } else { 402 sc->sc_tx_slots = EM_MAX_TXD_82543; 403 sc->sc_rx_slots = EM_MAX_RXD_82543; 404 } 405 sc->tx_int_delay = EM_TIDV; 406 sc->tx_abs_int_delay = EM_TADV; 407 sc->rx_int_delay = EM_RDTR; 408 sc->rx_abs_int_delay = EM_RADV; 409 sc->hw.autoneg = DO_AUTO_NEG; 410 sc->hw.wait_autoneg_complete = WAIT_FOR_AUTO_NEG_DEFAULT; 411 sc->hw.autoneg_advertised = AUTONEG_ADV_DEFAULT; 412 sc->hw.tbi_compatibility_en = TRUE; 413 sc->sc_rx_buffer_len = EM_RXBUFFER_2048; 414 415 sc->hw.phy_init_script = 1; 416 sc->hw.phy_reset_disable = FALSE; 417 418 #ifndef EM_MASTER_SLAVE 419 sc->hw.master_slave = em_ms_hw_default; 420 #else 421 sc->hw.master_slave = EM_MASTER_SLAVE; 422 #endif 423 424 /* 425 * This controls when hardware reports transmit completion 426 * status. 427 */ 428 sc->hw.report_tx_early = 1; 429 430 if (em_allocate_pci_resources(sc)) 431 goto err_pci; 432 433 /* Initialize eeprom parameters */ 434 em_init_eeprom_params(&sc->hw); 435 436 /* 437 * Set the max frame size assuming standard Ethernet 438 * sized frames. 439 */ 440 switch (sc->hw.mac_type) { 441 case em_82573: 442 { 443 uint16_t eeprom_data = 0; 444 445 /* 446 * 82573 only supports Jumbo frames 447 * if ASPM is disabled. 448 */ 449 em_read_eeprom(&sc->hw, EEPROM_INIT_3GIO_3, 450 1, &eeprom_data); 451 if (eeprom_data & EEPROM_WORD1A_ASPM_MASK) { 452 sc->hw.max_frame_size = ETHER_MAX_LEN; 453 break; 454 } 455 /* Allow Jumbo frames */ 456 /* FALLTHROUGH */ 457 } 458 case em_82571: 459 case em_82572: 460 case em_82574: 461 case em_82575: 462 case em_82576: 463 case em_82580: 464 case em_i210: 465 case em_i350: 466 case em_ich9lan: 467 case em_ich10lan: 468 case em_pch2lan: 469 case em_pch_lpt: 470 case em_pch_spt: 471 case em_pch_cnp: 472 case em_80003es2lan: 473 /* 9K Jumbo Frame size */ 474 sc->hw.max_frame_size = 9234; 475 break; 476 case em_pchlan: 477 sc->hw.max_frame_size = 4096; 478 break; 479 case em_82542_rev2_0: 480 case em_82542_rev2_1: 481 case em_ich8lan: 482 /* Adapters that do not support Jumbo frames */ 483 sc->hw.max_frame_size = ETHER_MAX_LEN; 484 break; 485 default: 486 sc->hw.max_frame_size = 487 MAX_JUMBO_FRAME_SIZE; 488 } 489 490 sc->hw.min_frame_size = 491 ETHER_MIN_LEN + ETHER_CRC_LEN; 492 493 if (em_allocate_desc_rings(sc) != 0) { 494 printf("%s: Unable to allocate descriptor ring memory\n", 495 DEVNAME(sc)); 496 goto err_pci; 497 } 498 499 /* Initialize the hardware */ 500 if ((defer = em_hardware_init(sc))) { 501 if (defer == EAGAIN) 502 config_defer(self, em_defer_attach); 503 else { 504 printf("%s: Unable to initialize the hardware\n", 505 DEVNAME(sc)); 506 goto err_pci; 507 } 508 } 509 510 if (sc->hw.mac_type == em_80003es2lan || sc->hw.mac_type == em_82575 || 511 sc->hw.mac_type == em_82576 || 512 sc->hw.mac_type == em_82580 || sc->hw.mac_type == em_i210 || 513 sc->hw.mac_type == em_i350) { 514 uint32_t reg = EM_READ_REG(&sc->hw, E1000_STATUS); 515 sc->hw.bus_func = (reg & E1000_STATUS_FUNC_MASK) >> 516 E1000_STATUS_FUNC_SHIFT; 517 518 switch (sc->hw.bus_func) { 519 case 0: 520 sc->hw.swfw = E1000_SWFW_PHY0_SM; 521 break; 522 case 1: 523 sc->hw.swfw = E1000_SWFW_PHY1_SM; 524 break; 525 case 2: 526 sc->hw.swfw = E1000_SWFW_PHY2_SM; 527 break; 528 case 3: 529 sc->hw.swfw = E1000_SWFW_PHY3_SM; 530 break; 531 } 532 } else { 533 sc->hw.bus_func = 0; 534 } 535 536 /* Copy the permanent MAC address out of the EEPROM */ 537 if (em_read_mac_addr(&sc->hw) < 0) { 538 printf("%s: EEPROM read error while reading mac address\n", 539 DEVNAME(sc)); 540 goto err_pci; 541 } 542 543 bcopy(sc->hw.mac_addr, sc->sc_ac.ac_enaddr, ETHER_ADDR_LEN); 544 545 /* Setup OS specific network interface */ 546 if (!defer) 547 em_setup_interface(sc); 548 549 /* Initialize statistics */ 550 em_clear_hw_cntrs(&sc->hw); 551 #ifndef SMALL_KERNEL 552 em_update_stats_counters(sc); 553 #endif 554 sc->hw.get_link_status = 1; 555 if (!defer) 556 em_update_link_status(sc); 557 558 #ifdef EM_DEBUG 559 printf(", mac %#x phy %#x", sc->hw.mac_type, sc->hw.phy_type); 560 #endif 561 printf(", address %s\n", ether_sprintf(sc->sc_ac.ac_enaddr)); 562 563 /* Indicate SOL/IDER usage */ 564 if (em_check_phy_reset_block(&sc->hw)) 565 printf("%s: PHY reset is blocked due to SOL/IDER session.\n", 566 DEVNAME(sc)); 567 568 /* Identify 82544 on PCI-X */ 569 em_get_bus_info(&sc->hw); 570 if (sc->hw.bus_type == em_bus_type_pcix && 571 sc->hw.mac_type == em_82544) 572 sc->pcix_82544 = TRUE; 573 else 574 sc->pcix_82544 = FALSE; 575 576 sc->hw.icp_xxxx_is_link_up = FALSE; 577 578 INIT_DEBUGOUT("em_attach: end"); 579 return; 580 581 err_pci: 582 em_free_pci_resources(sc); 583 } 584 585 /********************************************************************* 586 * Transmit entry point 587 * 588 * em_start is called by the stack to initiate a transmit. 589 * The driver will remain in this routine as long as there are 590 * packets to transmit and transmit resources are available. 591 * In case resources are not available stack is notified and 592 * the packet is requeued. 593 **********************************************************************/ 594 595 void 596 em_start(struct ifqueue *ifq) 597 { 598 struct ifnet *ifp = ifq->ifq_if; 599 struct em_softc *sc = ifp->if_softc; 600 u_int head, free, used; 601 struct mbuf *m; 602 int post = 0; 603 struct em_queue *que = sc->queues; /* Use only first queue. */ 604 605 if (!sc->link_active) { 606 ifq_purge(ifq); 607 return; 608 } 609 610 /* calculate free space */ 611 head = que->tx.sc_tx_desc_head; 612 free = que->tx.sc_tx_desc_tail; 613 if (free <= head) 614 free += sc->sc_tx_slots; 615 free -= head; 616 617 if (sc->hw.mac_type != em_82547) { 618 bus_dmamap_sync(sc->sc_dmat, que->tx.sc_tx_dma.dma_map, 619 0, que->tx.sc_tx_dma.dma_map->dm_mapsize, 620 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 621 } 622 623 for (;;) { 624 /* use 2 because cksum setup can use an extra slot */ 625 if (EM_MAX_SCATTER + 2 > free) { 626 ifq_set_oactive(ifq); 627 break; 628 } 629 630 m = ifq_dequeue(ifq); 631 if (m == NULL) 632 break; 633 634 used = em_encap(que, m); 635 if (used == 0) { 636 m_freem(m); 637 continue; 638 } 639 640 KASSERT(used <= free); 641 642 free -= used; 643 644 #if NBPFILTER > 0 645 /* Send a copy of the frame to the BPF listener */ 646 if (ifp->if_bpf) 647 bpf_mtap_ether(ifp->if_bpf, m, BPF_DIRECTION_OUT); 648 #endif 649 650 /* Set timeout in case hardware has problems transmitting */ 651 ifp->if_timer = EM_TX_TIMEOUT; 652 653 if (sc->hw.mac_type == em_82547) { 654 int len = m->m_pkthdr.len; 655 656 if (sc->link_duplex == HALF_DUPLEX) 657 em_82547_move_tail_locked(sc); 658 else { 659 E1000_WRITE_REG(&sc->hw, TDT(que->me), 660 que->tx.sc_tx_desc_head); 661 em_82547_update_fifo_head(sc, len); 662 } 663 } 664 665 post = 1; 666 } 667 668 if (sc->hw.mac_type != em_82547) { 669 bus_dmamap_sync(sc->sc_dmat, que->tx.sc_tx_dma.dma_map, 670 0, que->tx.sc_tx_dma.dma_map->dm_mapsize, 671 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 672 /* 673 * Advance the Transmit Descriptor Tail (Tdt), 674 * this tells the E1000 that this frame is 675 * available to transmit. 676 */ 677 if (post) 678 E1000_WRITE_REG(&sc->hw, TDT(que->me), 679 que->tx.sc_tx_desc_head); 680 } 681 } 682 683 /********************************************************************* 684 * Ioctl entry point 685 * 686 * em_ioctl is called when the user wants to configure the 687 * interface. 688 * 689 * return 0 on success, positive on failure 690 **********************************************************************/ 691 692 int 693 em_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 694 { 695 int error = 0; 696 struct ifreq *ifr = (struct ifreq *) data; 697 struct em_softc *sc = ifp->if_softc; 698 int s; 699 700 s = splnet(); 701 702 switch (command) { 703 case SIOCSIFADDR: 704 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFADDR (Set Interface " 705 "Addr)"); 706 if (!(ifp->if_flags & IFF_UP)) { 707 ifp->if_flags |= IFF_UP; 708 em_init(sc); 709 } 710 break; 711 712 case SIOCSIFFLAGS: 713 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFFLAGS (Set Interface Flags)"); 714 if (ifp->if_flags & IFF_UP) { 715 if (ifp->if_flags & IFF_RUNNING) 716 error = ENETRESET; 717 else 718 em_init(sc); 719 } else { 720 if (ifp->if_flags & IFF_RUNNING) 721 em_stop(sc, 0); 722 } 723 break; 724 725 case SIOCSIFMEDIA: 726 /* Check SOL/IDER usage */ 727 if (em_check_phy_reset_block(&sc->hw)) { 728 printf("%s: Media change is blocked due to SOL/IDER session.\n", 729 DEVNAME(sc)); 730 break; 731 } 732 case SIOCGIFMEDIA: 733 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCxIFMEDIA (Get/Set Interface Media)"); 734 error = ifmedia_ioctl(ifp, ifr, &sc->media, command); 735 break; 736 737 case SIOCGIFRXR: 738 error = if_rxr_ioctl((struct if_rxrinfo *)ifr->ifr_data, 739 NULL, EM_MCLBYTES, &sc->queues->rx.sc_rx_ring); 740 break; 741 742 default: 743 error = ether_ioctl(ifp, &sc->sc_ac, command, data); 744 } 745 746 if (error == ENETRESET) { 747 if (ifp->if_flags & IFF_RUNNING) { 748 em_disable_intr(sc); 749 em_iff(sc); 750 if (sc->hw.mac_type == em_82542_rev2_0) 751 em_initialize_receive_unit(sc); 752 em_enable_intr(sc); 753 } 754 error = 0; 755 } 756 757 splx(s); 758 return (error); 759 } 760 761 /********************************************************************* 762 * Watchdog entry point 763 * 764 * This routine is called whenever hardware quits transmitting. 765 * 766 **********************************************************************/ 767 768 void 769 em_watchdog(struct ifnet *ifp) 770 { 771 struct em_softc *sc = ifp->if_softc; 772 struct em_queue *que = sc->queues; /* Use only first queue. */ 773 774 775 /* If we are in this routine because of pause frames, then 776 * don't reset the hardware. 777 */ 778 if (E1000_READ_REG(&sc->hw, STATUS) & E1000_STATUS_TXOFF) { 779 ifp->if_timer = EM_TX_TIMEOUT; 780 return; 781 } 782 printf("%s: watchdog: head %u tail %u TDH %u TDT %u\n", 783 DEVNAME(sc), 784 que->tx.sc_tx_desc_head, que->tx.sc_tx_desc_tail, 785 E1000_READ_REG(&sc->hw, TDH(que->me)), 786 E1000_READ_REG(&sc->hw, TDT(que->me))); 787 788 em_init(sc); 789 790 sc->watchdog_events++; 791 } 792 793 /********************************************************************* 794 * Init entry point 795 * 796 * This routine is used in two ways. It is used by the stack as 797 * init entry point in network interface structure. It is also used 798 * by the driver as a hw/sw initialization routine to get to a 799 * consistent state. 800 * 801 **********************************************************************/ 802 803 void 804 em_init(void *arg) 805 { 806 struct em_softc *sc = arg; 807 struct ifnet *ifp = &sc->sc_ac.ac_if; 808 uint32_t pba; 809 int s; 810 811 s = splnet(); 812 813 INIT_DEBUGOUT("em_init: begin"); 814 815 em_stop(sc, 0); 816 817 /* 818 * Packet Buffer Allocation (PBA) 819 * Writing PBA sets the receive portion of the buffer 820 * the remainder is used for the transmit buffer. 821 * 822 * Devices before the 82547 had a Packet Buffer of 64K. 823 * Default allocation: PBA=48K for Rx, leaving 16K for Tx. 824 * After the 82547 the buffer was reduced to 40K. 825 * Default allocation: PBA=30K for Rx, leaving 10K for Tx. 826 * Note: default does not leave enough room for Jumbo Frame >10k. 827 */ 828 switch (sc->hw.mac_type) { 829 case em_82547: 830 case em_82547_rev_2: /* 82547: Total Packet Buffer is 40K */ 831 if (sc->hw.max_frame_size > EM_RXBUFFER_8192) 832 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 833 else 834 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 835 sc->tx_fifo_head = 0; 836 sc->tx_head_addr = pba << EM_TX_HEAD_ADDR_SHIFT; 837 sc->tx_fifo_size = (E1000_PBA_40K - pba) << EM_PBA_BYTES_SHIFT; 838 break; 839 case em_82571: 840 case em_82572: /* Total Packet Buffer on these is 48k */ 841 case em_82575: 842 case em_82576: 843 case em_82580: 844 case em_80003es2lan: 845 case em_i350: 846 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 847 break; 848 case em_i210: 849 pba = E1000_PBA_34K; 850 break; 851 case em_82573: /* 82573: Total Packet Buffer is 32K */ 852 /* Jumbo frames not supported */ 853 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 854 break; 855 case em_82574: /* Total Packet Buffer is 40k */ 856 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */ 857 break; 858 case em_ich8lan: 859 pba = E1000_PBA_8K; 860 break; 861 case em_ich9lan: 862 case em_ich10lan: 863 /* Boost Receive side for jumbo frames */ 864 if (sc->hw.max_frame_size > EM_RXBUFFER_4096) 865 pba = E1000_PBA_14K; 866 else 867 pba = E1000_PBA_10K; 868 break; 869 case em_pchlan: 870 case em_pch2lan: 871 case em_pch_lpt: 872 case em_pch_spt: 873 case em_pch_cnp: 874 pba = E1000_PBA_26K; 875 break; 876 default: 877 /* Devices before 82547 had a Packet Buffer of 64K. */ 878 if (sc->hw.max_frame_size > EM_RXBUFFER_8192) 879 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 880 else 881 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 882 } 883 INIT_DEBUGOUT1("em_init: pba=%dK",pba); 884 E1000_WRITE_REG(&sc->hw, PBA, pba); 885 886 /* Get the latest mac address, User can use a LAA */ 887 bcopy(sc->sc_ac.ac_enaddr, sc->hw.mac_addr, ETHER_ADDR_LEN); 888 889 /* Initialize the hardware */ 890 if (em_hardware_init(sc)) { 891 printf("%s: Unable to initialize the hardware\n", 892 DEVNAME(sc)); 893 splx(s); 894 return; 895 } 896 em_update_link_status(sc); 897 898 E1000_WRITE_REG(&sc->hw, VET, ETHERTYPE_VLAN); 899 if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) 900 em_enable_hw_vlans(sc); 901 902 /* Prepare transmit descriptors and buffers */ 903 if (em_setup_transmit_structures(sc)) { 904 printf("%s: Could not setup transmit structures\n", 905 DEVNAME(sc)); 906 em_stop(sc, 0); 907 splx(s); 908 return; 909 } 910 em_initialize_transmit_unit(sc); 911 912 /* Prepare receive descriptors and buffers */ 913 if (em_setup_receive_structures(sc)) { 914 printf("%s: Could not setup receive structures\n", 915 DEVNAME(sc)); 916 em_stop(sc, 0); 917 splx(s); 918 return; 919 } 920 em_initialize_receive_unit(sc); 921 922 /* Program promiscuous mode and multicast filters. */ 923 em_iff(sc); 924 925 ifp->if_flags |= IFF_RUNNING; 926 ifq_clr_oactive(&ifp->if_snd); 927 928 timeout_add_sec(&sc->timer_handle, 1); 929 em_clear_hw_cntrs(&sc->hw); 930 em_enable_intr(sc); 931 932 /* Don't reset the phy next time init gets called */ 933 sc->hw.phy_reset_disable = TRUE; 934 935 splx(s); 936 } 937 938 /********************************************************************* 939 * 940 * Interrupt Service routine 941 * 942 **********************************************************************/ 943 int 944 em_intr(void *arg) 945 { 946 struct em_softc *sc = arg; 947 struct em_queue *que = sc->queues; /* single queue */ 948 struct ifnet *ifp = &sc->sc_ac.ac_if; 949 u_int32_t reg_icr, test_icr; 950 951 test_icr = reg_icr = E1000_READ_REG(&sc->hw, ICR); 952 if (sc->hw.mac_type >= em_82571) 953 test_icr = (reg_icr & E1000_ICR_INT_ASSERTED); 954 if (!test_icr) 955 return (0); 956 957 if (ifp->if_flags & IFF_RUNNING) { 958 em_txeof(que); 959 if (em_rxeof(que)) 960 em_rxrefill(que); 961 } 962 963 /* Link status change */ 964 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 965 KERNEL_LOCK(); 966 sc->hw.get_link_status = 1; 967 em_check_for_link(&sc->hw); 968 em_update_link_status(sc); 969 KERNEL_UNLOCK(); 970 } 971 972 return (1); 973 } 974 975 /********************************************************************* 976 * 977 * Media Ioctl callback 978 * 979 * This routine is called whenever the user queries the status of 980 * the interface using ifconfig. 981 * 982 **********************************************************************/ 983 void 984 em_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 985 { 986 struct em_softc *sc = ifp->if_softc; 987 uint64_t fiber_type = IFM_1000_SX; 988 u_int16_t gsr; 989 990 INIT_DEBUGOUT("em_media_status: begin"); 991 992 em_check_for_link(&sc->hw); 993 em_update_link_status(sc); 994 995 ifmr->ifm_status = IFM_AVALID; 996 ifmr->ifm_active = IFM_ETHER; 997 998 if (!sc->link_active) { 999 ifmr->ifm_active |= IFM_NONE; 1000 return; 1001 } 1002 1003 ifmr->ifm_status |= IFM_ACTIVE; 1004 1005 if (sc->hw.media_type == em_media_type_fiber || 1006 sc->hw.media_type == em_media_type_internal_serdes) { 1007 if (sc->hw.mac_type == em_82545) 1008 fiber_type = IFM_1000_LX; 1009 ifmr->ifm_active |= fiber_type | IFM_FDX; 1010 } else { 1011 switch (sc->link_speed) { 1012 case 10: 1013 ifmr->ifm_active |= IFM_10_T; 1014 break; 1015 case 100: 1016 ifmr->ifm_active |= IFM_100_TX; 1017 break; 1018 case 1000: 1019 ifmr->ifm_active |= IFM_1000_T; 1020 break; 1021 } 1022 1023 if (sc->link_duplex == FULL_DUPLEX) 1024 ifmr->ifm_active |= em_flowstatus(sc) | IFM_FDX; 1025 else 1026 ifmr->ifm_active |= IFM_HDX; 1027 1028 if (IFM_SUBTYPE(ifmr->ifm_active) == IFM_1000_T) { 1029 em_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &gsr); 1030 if (gsr & SR_1000T_MS_CONFIG_RES) 1031 ifmr->ifm_active |= IFM_ETH_MASTER; 1032 } 1033 } 1034 } 1035 1036 /********************************************************************* 1037 * 1038 * Media Ioctl callback 1039 * 1040 * This routine is called when the user changes speed/duplex using 1041 * media/mediopt option with ifconfig. 1042 * 1043 **********************************************************************/ 1044 int 1045 em_media_change(struct ifnet *ifp) 1046 { 1047 struct em_softc *sc = ifp->if_softc; 1048 struct ifmedia *ifm = &sc->media; 1049 1050 INIT_DEBUGOUT("em_media_change: begin"); 1051 1052 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1053 return (EINVAL); 1054 1055 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1056 case IFM_AUTO: 1057 sc->hw.autoneg = DO_AUTO_NEG; 1058 sc->hw.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1059 break; 1060 case IFM_1000_LX: 1061 case IFM_1000_SX: 1062 case IFM_1000_T: 1063 sc->hw.autoneg = DO_AUTO_NEG; 1064 sc->hw.autoneg_advertised = ADVERTISE_1000_FULL; 1065 break; 1066 case IFM_100_TX: 1067 sc->hw.autoneg = FALSE; 1068 sc->hw.autoneg_advertised = 0; 1069 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1070 sc->hw.forced_speed_duplex = em_100_full; 1071 else 1072 sc->hw.forced_speed_duplex = em_100_half; 1073 break; 1074 case IFM_10_T: 1075 sc->hw.autoneg = FALSE; 1076 sc->hw.autoneg_advertised = 0; 1077 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1078 sc->hw.forced_speed_duplex = em_10_full; 1079 else 1080 sc->hw.forced_speed_duplex = em_10_half; 1081 break; 1082 default: 1083 printf("%s: Unsupported media type\n", DEVNAME(sc)); 1084 } 1085 1086 /* 1087 * As the speed/duplex settings may have changed we need to 1088 * reset the PHY. 1089 */ 1090 sc->hw.phy_reset_disable = FALSE; 1091 1092 em_init(sc); 1093 1094 return (0); 1095 } 1096 1097 uint64_t 1098 em_flowstatus(struct em_softc *sc) 1099 { 1100 u_int16_t ar, lpar; 1101 1102 if (sc->hw.media_type == em_media_type_fiber || 1103 sc->hw.media_type == em_media_type_internal_serdes) 1104 return (0); 1105 1106 em_read_phy_reg(&sc->hw, PHY_AUTONEG_ADV, &ar); 1107 em_read_phy_reg(&sc->hw, PHY_LP_ABILITY, &lpar); 1108 1109 if ((ar & NWAY_AR_PAUSE) && (lpar & NWAY_LPAR_PAUSE)) 1110 return (IFM_FLOW|IFM_ETH_TXPAUSE|IFM_ETH_RXPAUSE); 1111 else if (!(ar & NWAY_AR_PAUSE) && (ar & NWAY_AR_ASM_DIR) && 1112 (lpar & NWAY_LPAR_PAUSE) && (lpar & NWAY_LPAR_ASM_DIR)) 1113 return (IFM_FLOW|IFM_ETH_TXPAUSE); 1114 else if ((ar & NWAY_AR_PAUSE) && (ar & NWAY_AR_ASM_DIR) && 1115 !(lpar & NWAY_LPAR_PAUSE) && (lpar & NWAY_LPAR_ASM_DIR)) 1116 return (IFM_FLOW|IFM_ETH_RXPAUSE); 1117 1118 return (0); 1119 } 1120 1121 /********************************************************************* 1122 * 1123 * This routine maps the mbufs to tx descriptors. 1124 * 1125 * return 0 on success, positive on failure 1126 **********************************************************************/ 1127 u_int 1128 em_encap(struct em_queue *que, struct mbuf *m) 1129 { 1130 struct em_softc *sc = que->sc; 1131 struct em_packet *pkt; 1132 struct em_tx_desc *desc; 1133 bus_dmamap_t map; 1134 u_int32_t txd_upper, txd_lower; 1135 u_int head, last, used = 0; 1136 int i, j; 1137 1138 /* For 82544 Workaround */ 1139 DESC_ARRAY desc_array; 1140 u_int32_t array_elements; 1141 1142 /* get a dmamap for this packet from the next free slot */ 1143 head = que->tx.sc_tx_desc_head; 1144 pkt = &que->tx.sc_tx_pkts_ring[head]; 1145 map = pkt->pkt_map; 1146 1147 switch (bus_dmamap_load_mbuf(sc->sc_dmat, map, m, BUS_DMA_NOWAIT)) { 1148 case 0: 1149 break; 1150 case EFBIG: 1151 if (m_defrag(m, M_DONTWAIT) == 0 && 1152 bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1153 BUS_DMA_NOWAIT) == 0) 1154 break; 1155 1156 /* FALLTHROUGH */ 1157 default: 1158 sc->no_tx_dma_setup++; 1159 return (0); 1160 } 1161 1162 bus_dmamap_sync(sc->sc_dmat, map, 1163 0, map->dm_mapsize, 1164 BUS_DMASYNC_PREWRITE); 1165 1166 if (sc->hw.mac_type == em_82547) { 1167 bus_dmamap_sync(sc->sc_dmat, que->tx.sc_tx_dma.dma_map, 1168 0, que->tx.sc_tx_dma.dma_map->dm_mapsize, 1169 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1170 } 1171 1172 if (sc->hw.mac_type >= em_82543 && sc->hw.mac_type != em_82575 && 1173 sc->hw.mac_type != em_82576 && 1174 sc->hw.mac_type != em_82580 && sc->hw.mac_type != em_i210 && 1175 sc->hw.mac_type != em_i350) { 1176 used += em_transmit_checksum_setup(que, m, head, 1177 &txd_upper, &txd_lower); 1178 } else { 1179 txd_upper = txd_lower = 0; 1180 } 1181 1182 head += used; 1183 if (head >= sc->sc_tx_slots) 1184 head -= sc->sc_tx_slots; 1185 1186 for (i = 0; i < map->dm_nsegs; i++) { 1187 /* If sc is 82544 and on PCI-X bus */ 1188 if (sc->pcix_82544) { 1189 /* 1190 * Check the Address and Length combination and 1191 * split the data accordingly 1192 */ 1193 array_elements = em_fill_descriptors( 1194 map->dm_segs[i].ds_addr, map->dm_segs[i].ds_len, 1195 &desc_array); 1196 for (j = 0; j < array_elements; j++) { 1197 desc = &que->tx.sc_tx_desc_ring[head]; 1198 1199 desc->buffer_addr = htole64( 1200 desc_array.descriptor[j].address); 1201 desc->lower.data = htole32( 1202 (que->tx.sc_txd_cmd | txd_lower | 1203 (u_int16_t)desc_array.descriptor[j].length)); 1204 desc->upper.data = htole32(txd_upper); 1205 1206 last = head; 1207 if (++head == sc->sc_tx_slots) 1208 head = 0; 1209 1210 used++; 1211 } 1212 } else { 1213 desc = &que->tx.sc_tx_desc_ring[head]; 1214 1215 desc->buffer_addr = htole64(map->dm_segs[i].ds_addr); 1216 desc->lower.data = htole32(que->tx.sc_txd_cmd | 1217 txd_lower | map->dm_segs[i].ds_len); 1218 desc->upper.data = htole32(txd_upper); 1219 1220 last = head; 1221 if (++head == sc->sc_tx_slots) 1222 head = 0; 1223 1224 used++; 1225 } 1226 } 1227 1228 #if NVLAN > 0 1229 /* Find out if we are in VLAN mode */ 1230 if (m->m_flags & M_VLANTAG) { 1231 /* Set the VLAN id */ 1232 desc->upper.fields.special = htole16(m->m_pkthdr.ether_vtag); 1233 1234 /* Tell hardware to add tag */ 1235 desc->lower.data |= htole32(E1000_TXD_CMD_VLE); 1236 } 1237 #endif 1238 1239 /* mark the packet with the mbuf and last desc slot */ 1240 pkt->pkt_m = m; 1241 pkt->pkt_eop = last; 1242 1243 que->tx.sc_tx_desc_head = head; 1244 1245 /* 1246 * Last Descriptor of Packet 1247 * needs End Of Packet (EOP) 1248 * and Report Status (RS) 1249 */ 1250 desc->lower.data |= htole32(E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS); 1251 1252 if (sc->hw.mac_type == em_82547) { 1253 bus_dmamap_sync(sc->sc_dmat, que->tx.sc_tx_dma.dma_map, 1254 0, que->tx.sc_tx_dma.dma_map->dm_mapsize, 1255 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1256 } 1257 1258 return (used); 1259 } 1260 1261 /********************************************************************* 1262 * 1263 * 82547 workaround to avoid controller hang in half-duplex environment. 1264 * The workaround is to avoid queuing a large packet that would span 1265 * the internal Tx FIFO ring boundary. We need to reset the FIFO pointers 1266 * in this case. We do that only when FIFO is quiescent. 1267 * 1268 **********************************************************************/ 1269 void 1270 em_82547_move_tail_locked(struct em_softc *sc) 1271 { 1272 uint16_t hw_tdt; 1273 uint16_t sw_tdt; 1274 struct em_tx_desc *tx_desc; 1275 uint16_t length = 0; 1276 boolean_t eop = 0; 1277 struct em_queue *que = sc->queues; /* single queue chip */ 1278 1279 hw_tdt = E1000_READ_REG(&sc->hw, TDT(que->me)); 1280 sw_tdt = que->tx.sc_tx_desc_head; 1281 1282 while (hw_tdt != sw_tdt) { 1283 tx_desc = &que->tx.sc_tx_desc_ring[hw_tdt]; 1284 length += tx_desc->lower.flags.length; 1285 eop = tx_desc->lower.data & E1000_TXD_CMD_EOP; 1286 if (++hw_tdt == sc->sc_tx_slots) 1287 hw_tdt = 0; 1288 1289 if (eop) { 1290 if (em_82547_fifo_workaround(sc, length)) { 1291 sc->tx_fifo_wrk_cnt++; 1292 timeout_add(&sc->tx_fifo_timer_handle, 1); 1293 break; 1294 } 1295 E1000_WRITE_REG(&sc->hw, TDT(que->me), hw_tdt); 1296 em_82547_update_fifo_head(sc, length); 1297 length = 0; 1298 } 1299 } 1300 } 1301 1302 void 1303 em_82547_move_tail(void *arg) 1304 { 1305 struct em_softc *sc = arg; 1306 int s; 1307 1308 s = splnet(); 1309 em_82547_move_tail_locked(sc); 1310 splx(s); 1311 } 1312 1313 int 1314 em_82547_fifo_workaround(struct em_softc *sc, int len) 1315 { 1316 int fifo_space, fifo_pkt_len; 1317 1318 fifo_pkt_len = EM_ROUNDUP(len + EM_FIFO_HDR, EM_FIFO_HDR); 1319 1320 if (sc->link_duplex == HALF_DUPLEX) { 1321 fifo_space = sc->tx_fifo_size - sc->tx_fifo_head; 1322 1323 if (fifo_pkt_len >= (EM_82547_PKT_THRESH + fifo_space)) { 1324 if (em_82547_tx_fifo_reset(sc)) 1325 return (0); 1326 else 1327 return (1); 1328 } 1329 } 1330 1331 return (0); 1332 } 1333 1334 void 1335 em_82547_update_fifo_head(struct em_softc *sc, int len) 1336 { 1337 int fifo_pkt_len = EM_ROUNDUP(len + EM_FIFO_HDR, EM_FIFO_HDR); 1338 1339 /* tx_fifo_head is always 16 byte aligned */ 1340 sc->tx_fifo_head += fifo_pkt_len; 1341 if (sc->tx_fifo_head >= sc->tx_fifo_size) 1342 sc->tx_fifo_head -= sc->tx_fifo_size; 1343 } 1344 1345 int 1346 em_82547_tx_fifo_reset(struct em_softc *sc) 1347 { 1348 uint32_t tctl; 1349 struct em_queue *que = sc->queues; /* single queue chip */ 1350 1351 if ((E1000_READ_REG(&sc->hw, TDT(que->me)) == 1352 E1000_READ_REG(&sc->hw, TDH(que->me))) && 1353 (E1000_READ_REG(&sc->hw, TDFT) == 1354 E1000_READ_REG(&sc->hw, TDFH)) && 1355 (E1000_READ_REG(&sc->hw, TDFTS) == 1356 E1000_READ_REG(&sc->hw, TDFHS)) && 1357 (E1000_READ_REG(&sc->hw, TDFPC) == 0)) { 1358 1359 /* Disable TX unit */ 1360 tctl = E1000_READ_REG(&sc->hw, TCTL); 1361 E1000_WRITE_REG(&sc->hw, TCTL, tctl & ~E1000_TCTL_EN); 1362 1363 /* Reset FIFO pointers */ 1364 E1000_WRITE_REG(&sc->hw, TDFT, sc->tx_head_addr); 1365 E1000_WRITE_REG(&sc->hw, TDFH, sc->tx_head_addr); 1366 E1000_WRITE_REG(&sc->hw, TDFTS, sc->tx_head_addr); 1367 E1000_WRITE_REG(&sc->hw, TDFHS, sc->tx_head_addr); 1368 1369 /* Re-enable TX unit */ 1370 E1000_WRITE_REG(&sc->hw, TCTL, tctl); 1371 E1000_WRITE_FLUSH(&sc->hw); 1372 1373 sc->tx_fifo_head = 0; 1374 sc->tx_fifo_reset_cnt++; 1375 1376 return (TRUE); 1377 } else 1378 return (FALSE); 1379 } 1380 1381 void 1382 em_iff(struct em_softc *sc) 1383 { 1384 struct ifnet *ifp = &sc->sc_ac.ac_if; 1385 struct arpcom *ac = &sc->sc_ac; 1386 u_int32_t reg_rctl = 0; 1387 u_int8_t mta[MAX_NUM_MULTICAST_ADDRESSES * ETH_LENGTH_OF_ADDRESS]; 1388 struct ether_multi *enm; 1389 struct ether_multistep step; 1390 int i = 0; 1391 1392 IOCTL_DEBUGOUT("em_iff: begin"); 1393 1394 if (sc->hw.mac_type == em_82542_rev2_0) { 1395 reg_rctl = E1000_READ_REG(&sc->hw, RCTL); 1396 if (sc->hw.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1397 em_pci_clear_mwi(&sc->hw); 1398 reg_rctl |= E1000_RCTL_RST; 1399 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 1400 msec_delay(5); 1401 } 1402 1403 reg_rctl = E1000_READ_REG(&sc->hw, RCTL); 1404 reg_rctl &= ~(E1000_RCTL_MPE | E1000_RCTL_UPE); 1405 ifp->if_flags &= ~IFF_ALLMULTI; 1406 1407 if (ifp->if_flags & IFF_PROMISC || ac->ac_multirangecnt > 0 || 1408 ac->ac_multicnt > MAX_NUM_MULTICAST_ADDRESSES) { 1409 ifp->if_flags |= IFF_ALLMULTI; 1410 reg_rctl |= E1000_RCTL_MPE; 1411 if (ifp->if_flags & IFF_PROMISC) 1412 reg_rctl |= E1000_RCTL_UPE; 1413 } else { 1414 ETHER_FIRST_MULTI(step, ac, enm); 1415 while (enm != NULL) { 1416 bcopy(enm->enm_addrlo, mta + i, ETH_LENGTH_OF_ADDRESS); 1417 i += ETH_LENGTH_OF_ADDRESS; 1418 1419 ETHER_NEXT_MULTI(step, enm); 1420 } 1421 1422 em_mc_addr_list_update(&sc->hw, mta, ac->ac_multicnt, 0, 1); 1423 } 1424 1425 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 1426 1427 if (sc->hw.mac_type == em_82542_rev2_0) { 1428 reg_rctl = E1000_READ_REG(&sc->hw, RCTL); 1429 reg_rctl &= ~E1000_RCTL_RST; 1430 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 1431 msec_delay(5); 1432 if (sc->hw.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1433 em_pci_set_mwi(&sc->hw); 1434 } 1435 } 1436 1437 /********************************************************************* 1438 * Timer routine 1439 * 1440 * This routine checks for link status and updates statistics. 1441 * 1442 **********************************************************************/ 1443 1444 void 1445 em_local_timer(void *arg) 1446 { 1447 struct ifnet *ifp; 1448 struct em_softc *sc = arg; 1449 int s; 1450 1451 ifp = &sc->sc_ac.ac_if; 1452 1453 s = splnet(); 1454 1455 #ifndef SMALL_KERNEL 1456 em_update_stats_counters(sc); 1457 #ifdef EM_DEBUG 1458 if (ifp->if_flags & IFF_DEBUG && ifp->if_flags & IFF_RUNNING) 1459 em_print_hw_stats(sc); 1460 #endif 1461 #endif 1462 em_smartspeed(sc); 1463 1464 timeout_add_sec(&sc->timer_handle, 1); 1465 1466 splx(s); 1467 } 1468 1469 void 1470 em_update_link_status(struct em_softc *sc) 1471 { 1472 struct ifnet *ifp = &sc->sc_ac.ac_if; 1473 u_char link_state; 1474 1475 if (E1000_READ_REG(&sc->hw, STATUS) & E1000_STATUS_LU) { 1476 if (sc->link_active == 0) { 1477 em_get_speed_and_duplex(&sc->hw, 1478 &sc->link_speed, 1479 &sc->link_duplex); 1480 /* Check if we may set SPEED_MODE bit on PCI-E */ 1481 if ((sc->link_speed == SPEED_1000) && 1482 ((sc->hw.mac_type == em_82571) || 1483 (sc->hw.mac_type == em_82572) || 1484 (sc->hw.mac_type == em_82575) || 1485 (sc->hw.mac_type == em_82576) || 1486 (sc->hw.mac_type == em_82580))) { 1487 int tarc0; 1488 1489 tarc0 = E1000_READ_REG(&sc->hw, TARC0); 1490 tarc0 |= SPEED_MODE_BIT; 1491 E1000_WRITE_REG(&sc->hw, TARC0, tarc0); 1492 } 1493 sc->link_active = 1; 1494 sc->smartspeed = 0; 1495 ifp->if_baudrate = IF_Mbps(sc->link_speed); 1496 } 1497 link_state = (sc->link_duplex == FULL_DUPLEX) ? 1498 LINK_STATE_FULL_DUPLEX : LINK_STATE_HALF_DUPLEX; 1499 } else { 1500 if (sc->link_active == 1) { 1501 ifp->if_baudrate = sc->link_speed = 0; 1502 sc->link_duplex = 0; 1503 sc->link_active = 0; 1504 } 1505 link_state = LINK_STATE_DOWN; 1506 } 1507 if (ifp->if_link_state != link_state) { 1508 ifp->if_link_state = link_state; 1509 if_link_state_change(ifp); 1510 } 1511 } 1512 1513 /********************************************************************* 1514 * 1515 * This routine disables all traffic on the adapter by issuing a 1516 * global reset on the MAC and deallocates TX/RX buffers. 1517 * 1518 **********************************************************************/ 1519 1520 void 1521 em_stop(void *arg, int softonly) 1522 { 1523 struct em_softc *sc = arg; 1524 struct em_queue *que = sc->queues; /* Use only first queue. */ 1525 struct ifnet *ifp = &sc->sc_ac.ac_if; 1526 1527 /* Tell the stack that the interface is no longer active */ 1528 ifp->if_flags &= ~IFF_RUNNING; 1529 1530 INIT_DEBUGOUT("em_stop: begin"); 1531 1532 timeout_del(&que->rx_refill); 1533 timeout_del(&sc->timer_handle); 1534 timeout_del(&sc->tx_fifo_timer_handle); 1535 1536 if (!softonly) 1537 em_disable_intr(sc); 1538 if (sc->hw.mac_type >= em_pch_spt) 1539 em_flush_desc_rings(sc); 1540 if (!softonly) 1541 em_reset_hw(&sc->hw); 1542 1543 intr_barrier(sc->sc_intrhand); 1544 ifq_barrier(&ifp->if_snd); 1545 1546 KASSERT((ifp->if_flags & IFF_RUNNING) == 0); 1547 1548 ifq_clr_oactive(&ifp->if_snd); 1549 ifp->if_timer = 0; 1550 1551 em_free_transmit_structures(sc); 1552 em_free_receive_structures(sc); 1553 } 1554 1555 /********************************************************************* 1556 * 1557 * Determine hardware revision. 1558 * 1559 **********************************************************************/ 1560 void 1561 em_identify_hardware(struct em_softc *sc) 1562 { 1563 u_int32_t reg; 1564 struct pci_attach_args *pa = &sc->osdep.em_pa; 1565 1566 /* Make sure our PCI config space has the necessary stuff set */ 1567 sc->hw.pci_cmd_word = pci_conf_read(pa->pa_pc, pa->pa_tag, 1568 PCI_COMMAND_STATUS_REG); 1569 1570 /* Save off the information about this board */ 1571 sc->hw.vendor_id = PCI_VENDOR(pa->pa_id); 1572 sc->hw.device_id = PCI_PRODUCT(pa->pa_id); 1573 1574 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG); 1575 sc->hw.revision_id = PCI_REVISION(reg); 1576 1577 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 1578 sc->hw.subsystem_vendor_id = PCI_VENDOR(reg); 1579 sc->hw.subsystem_id = PCI_PRODUCT(reg); 1580 1581 /* Identify the MAC */ 1582 if (em_set_mac_type(&sc->hw)) 1583 printf("%s: Unknown MAC Type\n", DEVNAME(sc)); 1584 1585 if (sc->hw.mac_type == em_pchlan) 1586 sc->hw.revision_id = PCI_PRODUCT(pa->pa_id) & 0x0f; 1587 1588 if (sc->hw.mac_type == em_82541 || 1589 sc->hw.mac_type == em_82541_rev_2 || 1590 sc->hw.mac_type == em_82547 || 1591 sc->hw.mac_type == em_82547_rev_2) 1592 sc->hw.phy_init_script = TRUE; 1593 } 1594 1595 void 1596 em_legacy_irq_quirk_spt(struct em_softc *sc) 1597 { 1598 uint32_t reg; 1599 1600 /* Legacy interrupt: SPT needs a quirk. */ 1601 if (sc->hw.mac_type != em_pch_spt && sc->hw.mac_type != em_pch_cnp) 1602 return; 1603 if (sc->legacy_irq == 0) 1604 return; 1605 1606 reg = EM_READ_REG(&sc->hw, E1000_FEXTNVM7); 1607 reg |= E1000_FEXTNVM7_SIDE_CLK_UNGATE; 1608 EM_WRITE_REG(&sc->hw, E1000_FEXTNVM7, reg); 1609 1610 reg = EM_READ_REG(&sc->hw, E1000_FEXTNVM9); 1611 reg |= E1000_FEXTNVM9_IOSFSB_CLKGATE_DIS | 1612 E1000_FEXTNVM9_IOSFSB_CLKREQ_DIS; 1613 EM_WRITE_REG(&sc->hw, E1000_FEXTNVM9, reg); 1614 } 1615 1616 int 1617 em_allocate_pci_resources(struct em_softc *sc) 1618 { 1619 int val, rid; 1620 pci_intr_handle_t ih; 1621 const char *intrstr = NULL; 1622 struct pci_attach_args *pa = &sc->osdep.em_pa; 1623 pci_chipset_tag_t pc = pa->pa_pc; 1624 struct em_queue *que = NULL; 1625 1626 val = pci_conf_read(pa->pa_pc, pa->pa_tag, EM_MMBA); 1627 if (PCI_MAPREG_TYPE(val) != PCI_MAPREG_TYPE_MEM) { 1628 printf(": mmba is not mem space\n"); 1629 return (ENXIO); 1630 } 1631 if (pci_mapreg_map(pa, EM_MMBA, PCI_MAPREG_MEM_TYPE(val), 0, 1632 &sc->osdep.mem_bus_space_tag, &sc->osdep.mem_bus_space_handle, 1633 &sc->osdep.em_membase, &sc->osdep.em_memsize, 0)) { 1634 printf(": cannot find mem space\n"); 1635 return (ENXIO); 1636 } 1637 1638 switch (sc->hw.mac_type) { 1639 case em_82544: 1640 case em_82540: 1641 case em_82545: 1642 case em_82546: 1643 case em_82541: 1644 case em_82541_rev_2: 1645 /* Figure out where our I/O BAR is ? */ 1646 for (rid = PCI_MAPREG_START; rid < PCI_MAPREG_END;) { 1647 val = pci_conf_read(pa->pa_pc, pa->pa_tag, rid); 1648 if (PCI_MAPREG_TYPE(val) == PCI_MAPREG_TYPE_IO) { 1649 sc->io_rid = rid; 1650 break; 1651 } 1652 rid += 4; 1653 if (PCI_MAPREG_MEM_TYPE(val) == 1654 PCI_MAPREG_MEM_TYPE_64BIT) 1655 rid += 4; /* skip high bits, too */ 1656 } 1657 1658 if (pci_mapreg_map(pa, rid, PCI_MAPREG_TYPE_IO, 0, 1659 &sc->osdep.io_bus_space_tag, &sc->osdep.io_bus_space_handle, 1660 &sc->osdep.em_iobase, &sc->osdep.em_iosize, 0)) { 1661 printf(": cannot find i/o space\n"); 1662 return (ENXIO); 1663 } 1664 1665 sc->hw.io_base = 0; 1666 break; 1667 default: 1668 break; 1669 } 1670 1671 sc->osdep.em_flashoffset = 0; 1672 /* for ICH8 and family we need to find the flash memory */ 1673 if (sc->hw.mac_type >= em_pch_spt) { 1674 sc->osdep.flash_bus_space_tag = sc->osdep.mem_bus_space_tag; 1675 sc->osdep.flash_bus_space_handle = sc->osdep.mem_bus_space_handle; 1676 sc->osdep.em_flashbase = 0; 1677 sc->osdep.em_flashsize = 0; 1678 sc->osdep.em_flashoffset = 0xe000; 1679 } else if (IS_ICH8(sc->hw.mac_type)) { 1680 val = pci_conf_read(pa->pa_pc, pa->pa_tag, EM_FLASH); 1681 if (PCI_MAPREG_TYPE(val) != PCI_MAPREG_TYPE_MEM) { 1682 printf(": flash is not mem space\n"); 1683 return (ENXIO); 1684 } 1685 1686 if (pci_mapreg_map(pa, EM_FLASH, PCI_MAPREG_MEM_TYPE(val), 0, 1687 &sc->osdep.flash_bus_space_tag, &sc->osdep.flash_bus_space_handle, 1688 &sc->osdep.em_flashbase, &sc->osdep.em_flashsize, 0)) { 1689 printf(": cannot find mem space\n"); 1690 return (ENXIO); 1691 } 1692 } 1693 1694 /* Only one queue for the moment. */ 1695 que = malloc(sizeof(struct em_queue), M_DEVBUF, M_NOWAIT | M_ZERO); 1696 if (que == NULL) { 1697 printf(": unable to allocate queue memory\n"); 1698 return (ENOMEM); 1699 } 1700 que->me = 0; 1701 que->sc = sc; 1702 timeout_set(&que->rx_refill, em_rxrefill, que); 1703 1704 sc->queues = que; 1705 sc->num_queues = 1; 1706 sc->legacy_irq = 0; 1707 if (pci_intr_map_msi(pa, &ih)) { 1708 if (pci_intr_map(pa, &ih)) { 1709 printf(": couldn't map interrupt\n"); 1710 return (ENXIO); 1711 } 1712 sc->legacy_irq = 1; 1713 } 1714 1715 sc->osdep.dev = (struct device *)sc; 1716 sc->hw.back = &sc->osdep; 1717 1718 intrstr = pci_intr_string(pc, ih); 1719 sc->sc_intrhand = pci_intr_establish(pc, ih, IPL_NET | IPL_MPSAFE, 1720 em_intr, sc, DEVNAME(sc)); 1721 if (sc->sc_intrhand == NULL) { 1722 printf(": couldn't establish interrupt"); 1723 if (intrstr != NULL) 1724 printf(" at %s", intrstr); 1725 printf("\n"); 1726 return (ENXIO); 1727 } 1728 printf(": %s", intrstr); 1729 1730 /* 1731 * the ICP_xxxx device has multiple, duplicate register sets for 1732 * use when it is being used as a network processor. Disable those 1733 * registers here, as they are not necessary in this context and 1734 * can confuse the system 1735 */ 1736 if(sc->hw.mac_type == em_icp_xxxx) { 1737 int offset; 1738 pcireg_t val; 1739 1740 if (!pci_get_capability(sc->osdep.em_pa.pa_pc, 1741 sc->osdep.em_pa.pa_tag, PCI_CAP_ID_ST, &offset, &val)) { 1742 return (0); 1743 } 1744 offset += PCI_ST_SMIA_OFFSET; 1745 pci_conf_write(sc->osdep.em_pa.pa_pc, sc->osdep.em_pa.pa_tag, 1746 offset, 0x06); 1747 E1000_WRITE_REG(&sc->hw, IMC1, ~0x0); 1748 E1000_WRITE_REG(&sc->hw, IMC2, ~0x0); 1749 } 1750 return (0); 1751 } 1752 1753 void 1754 em_free_pci_resources(struct em_softc *sc) 1755 { 1756 struct pci_attach_args *pa = &sc->osdep.em_pa; 1757 pci_chipset_tag_t pc = pa->pa_pc; 1758 struct em_queue *que = NULL; 1759 if (sc->sc_intrhand) 1760 pci_intr_disestablish(pc, sc->sc_intrhand); 1761 sc->sc_intrhand = 0; 1762 1763 if (sc->osdep.em_flashbase) 1764 bus_space_unmap(sc->osdep.flash_bus_space_tag, sc->osdep.flash_bus_space_handle, 1765 sc->osdep.em_flashsize); 1766 sc->osdep.em_flashbase = 0; 1767 1768 if (sc->osdep.em_iobase) 1769 bus_space_unmap(sc->osdep.io_bus_space_tag, sc->osdep.io_bus_space_handle, 1770 sc->osdep.em_iosize); 1771 sc->osdep.em_iobase = 0; 1772 1773 if (sc->osdep.em_membase) 1774 bus_space_unmap(sc->osdep.mem_bus_space_tag, sc->osdep.mem_bus_space_handle, 1775 sc->osdep.em_memsize); 1776 sc->osdep.em_membase = 0; 1777 1778 que = sc->queues; /* Use only first queue. */ 1779 if (que->rx.sc_rx_desc_ring != NULL) { 1780 que->rx.sc_rx_desc_ring = NULL; 1781 em_dma_free(sc, &que->rx.sc_rx_dma); 1782 } 1783 if (que->tx.sc_tx_desc_ring != NULL) { 1784 que->tx.sc_tx_desc_ring = NULL; 1785 em_dma_free(sc, &que->tx.sc_tx_dma); 1786 } 1787 if (sc->queues) 1788 free(sc->queues, M_DEVBUF, 1789 sc->num_queues * sizeof(struct em_queue)); 1790 sc->num_queues = 0; 1791 sc->queues = NULL; 1792 } 1793 1794 /********************************************************************* 1795 * 1796 * Initialize the hardware to a configuration as specified by the 1797 * em_softc structure. The controller is reset, the EEPROM is 1798 * verified, the MAC address is set, then the shared initialization 1799 * routines are called. 1800 * 1801 **********************************************************************/ 1802 int 1803 em_hardware_init(struct em_softc *sc) 1804 { 1805 uint32_t ret_val; 1806 u_int16_t rx_buffer_size; 1807 1808 INIT_DEBUGOUT("em_hardware_init: begin"); 1809 if (sc->hw.mac_type >= em_pch_spt) 1810 em_flush_desc_rings(sc); 1811 /* Issue a global reset */ 1812 em_reset_hw(&sc->hw); 1813 1814 /* When hardware is reset, fifo_head is also reset */ 1815 sc->tx_fifo_head = 0; 1816 1817 /* Make sure we have a good EEPROM before we read from it */ 1818 if (em_get_flash_presence_i210(&sc->hw) && 1819 em_validate_eeprom_checksum(&sc->hw) < 0) { 1820 /* 1821 * Some PCIe parts fail the first check due to 1822 * the link being in sleep state, call it again, 1823 * if it fails a second time its a real issue. 1824 */ 1825 if (em_validate_eeprom_checksum(&sc->hw) < 0) { 1826 printf("%s: The EEPROM Checksum Is Not Valid\n", 1827 DEVNAME(sc)); 1828 return (EIO); 1829 } 1830 } 1831 1832 if (em_get_flash_presence_i210(&sc->hw) && 1833 em_read_part_num(&sc->hw, &(sc->part_num)) < 0) { 1834 printf("%s: EEPROM read error while reading part number\n", 1835 DEVNAME(sc)); 1836 return (EIO); 1837 } 1838 1839 /* Set up smart power down as default off on newer adapters */ 1840 if (!em_smart_pwr_down && 1841 (sc->hw.mac_type == em_82571 || 1842 sc->hw.mac_type == em_82572 || 1843 sc->hw.mac_type == em_82575 || 1844 sc->hw.mac_type == em_82576 || 1845 sc->hw.mac_type == em_82580 || 1846 sc->hw.mac_type == em_i210 || 1847 sc->hw.mac_type == em_i350 )) { 1848 uint16_t phy_tmp = 0; 1849 1850 /* Speed up time to link by disabling smart power down */ 1851 em_read_phy_reg(&sc->hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 1852 phy_tmp &= ~IGP02E1000_PM_SPD; 1853 em_write_phy_reg(&sc->hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp); 1854 } 1855 1856 em_legacy_irq_quirk_spt(sc); 1857 1858 /* 1859 * These parameters control the automatic generation (Tx) and 1860 * response (Rx) to Ethernet PAUSE frames. 1861 * - High water mark should allow for at least two frames to be 1862 * received after sending an XOFF. 1863 * - Low water mark works best when it is very near the high water mark. 1864 * This allows the receiver to restart by sending XON when it has 1865 * drained a bit. Here we use an arbitary value of 1500 which will 1866 * restart after one full frame is pulled from the buffer. There 1867 * could be several smaller frames in the buffer and if so they will 1868 * not trigger the XON until their total number reduces the buffer 1869 * by 1500. 1870 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 1871 */ 1872 rx_buffer_size = ((E1000_READ_REG(&sc->hw, PBA) & 0xffff) << 10 ); 1873 1874 sc->hw.fc_high_water = rx_buffer_size - 1875 EM_ROUNDUP(sc->hw.max_frame_size, 1024); 1876 sc->hw.fc_low_water = sc->hw.fc_high_water - 1500; 1877 if (sc->hw.mac_type == em_80003es2lan) 1878 sc->hw.fc_pause_time = 0xFFFF; 1879 else 1880 sc->hw.fc_pause_time = 1000; 1881 sc->hw.fc_send_xon = TRUE; 1882 sc->hw.fc = E1000_FC_FULL; 1883 1884 em_disable_aspm(sc); 1885 1886 if ((ret_val = em_init_hw(&sc->hw)) != 0) { 1887 if (ret_val == E1000_DEFER_INIT) { 1888 INIT_DEBUGOUT("\nHardware Initialization Deferred "); 1889 return (EAGAIN); 1890 } 1891 printf("\n%s: Hardware Initialization Failed: %d\n", 1892 DEVNAME(sc), ret_val); 1893 return (EIO); 1894 } 1895 1896 em_check_for_link(&sc->hw); 1897 1898 return (0); 1899 } 1900 1901 /********************************************************************* 1902 * 1903 * Setup networking device structure and register an interface. 1904 * 1905 **********************************************************************/ 1906 void 1907 em_setup_interface(struct em_softc *sc) 1908 { 1909 struct ifnet *ifp; 1910 uint64_t fiber_type = IFM_1000_SX; 1911 1912 INIT_DEBUGOUT("em_setup_interface: begin"); 1913 1914 ifp = &sc->sc_ac.ac_if; 1915 strlcpy(ifp->if_xname, DEVNAME(sc), IFNAMSIZ); 1916 ifp->if_softc = sc; 1917 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1918 ifp->if_xflags = IFXF_MPSAFE; 1919 ifp->if_ioctl = em_ioctl; 1920 ifp->if_qstart = em_start; 1921 ifp->if_watchdog = em_watchdog; 1922 ifp->if_hardmtu = 1923 sc->hw.max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN; 1924 IFQ_SET_MAXLEN(&ifp->if_snd, sc->sc_tx_slots - 1); 1925 1926 ifp->if_capabilities = IFCAP_VLAN_MTU; 1927 1928 #if NVLAN > 0 1929 if (sc->hw.mac_type != em_82575 && sc->hw.mac_type != em_82580 && 1930 sc->hw.mac_type != em_82576 && 1931 sc->hw.mac_type != em_i210 && sc->hw.mac_type != em_i350) 1932 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 1933 #endif 1934 1935 if (sc->hw.mac_type >= em_82543 && sc->hw.mac_type != em_82575 && 1936 sc->hw.mac_type != em_82576 && 1937 sc->hw.mac_type != em_82580 && sc->hw.mac_type != em_i210 && 1938 sc->hw.mac_type != em_i350) 1939 ifp->if_capabilities |= IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 1940 1941 /* 1942 * Specify the media types supported by this adapter and register 1943 * callbacks to update media and link information 1944 */ 1945 ifmedia_init(&sc->media, IFM_IMASK, em_media_change, 1946 em_media_status); 1947 if (sc->hw.media_type == em_media_type_fiber || 1948 sc->hw.media_type == em_media_type_internal_serdes) { 1949 if (sc->hw.mac_type == em_82545) 1950 fiber_type = IFM_1000_LX; 1951 ifmedia_add(&sc->media, IFM_ETHER | fiber_type | IFM_FDX, 1952 0, NULL); 1953 ifmedia_add(&sc->media, IFM_ETHER | fiber_type, 1954 0, NULL); 1955 } else { 1956 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL); 1957 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX, 1958 0, NULL); 1959 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 1960 0, NULL); 1961 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 1962 0, NULL); 1963 if (sc->hw.phy_type != em_phy_ife) { 1964 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 1965 0, NULL); 1966 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_T, 0, NULL); 1967 } 1968 } 1969 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL); 1970 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO); 1971 1972 if_attach(ifp); 1973 ether_ifattach(ifp); 1974 } 1975 1976 int 1977 em_detach(struct device *self, int flags) 1978 { 1979 struct em_softc *sc = (struct em_softc *)self; 1980 struct ifnet *ifp = &sc->sc_ac.ac_if; 1981 struct pci_attach_args *pa = &sc->osdep.em_pa; 1982 pci_chipset_tag_t pc = pa->pa_pc; 1983 1984 if (sc->sc_intrhand) 1985 pci_intr_disestablish(pc, sc->sc_intrhand); 1986 sc->sc_intrhand = 0; 1987 1988 em_stop(sc, 1); 1989 1990 em_free_pci_resources(sc); 1991 1992 ether_ifdetach(ifp); 1993 if_detach(ifp); 1994 1995 return (0); 1996 } 1997 1998 int 1999 em_activate(struct device *self, int act) 2000 { 2001 struct em_softc *sc = (struct em_softc *)self; 2002 struct ifnet *ifp = &sc->sc_ac.ac_if; 2003 int rv = 0; 2004 2005 switch (act) { 2006 case DVACT_SUSPEND: 2007 if (ifp->if_flags & IFF_RUNNING) 2008 em_stop(sc, 0); 2009 /* We have no children atm, but we will soon */ 2010 rv = config_activate_children(self, act); 2011 break; 2012 case DVACT_RESUME: 2013 if (ifp->if_flags & IFF_UP) 2014 em_init(sc); 2015 break; 2016 default: 2017 rv = config_activate_children(self, act); 2018 break; 2019 } 2020 return (rv); 2021 } 2022 2023 /********************************************************************* 2024 * 2025 * Workaround for SmartSpeed on 82541 and 82547 controllers 2026 * 2027 **********************************************************************/ 2028 void 2029 em_smartspeed(struct em_softc *sc) 2030 { 2031 uint16_t phy_tmp; 2032 2033 if (sc->link_active || (sc->hw.phy_type != em_phy_igp) || 2034 !sc->hw.autoneg || !(sc->hw.autoneg_advertised & ADVERTISE_1000_FULL)) 2035 return; 2036 2037 if (sc->smartspeed == 0) { 2038 /* If Master/Slave config fault is asserted twice, 2039 * we assume back-to-back */ 2040 em_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2041 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2042 return; 2043 em_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2044 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2045 em_read_phy_reg(&sc->hw, PHY_1000T_CTRL, 2046 &phy_tmp); 2047 if (phy_tmp & CR_1000T_MS_ENABLE) { 2048 phy_tmp &= ~CR_1000T_MS_ENABLE; 2049 em_write_phy_reg(&sc->hw, 2050 PHY_1000T_CTRL, phy_tmp); 2051 sc->smartspeed++; 2052 if (sc->hw.autoneg && 2053 !em_phy_setup_autoneg(&sc->hw) && 2054 !em_read_phy_reg(&sc->hw, PHY_CTRL, 2055 &phy_tmp)) { 2056 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2057 MII_CR_RESTART_AUTO_NEG); 2058 em_write_phy_reg(&sc->hw, 2059 PHY_CTRL, phy_tmp); 2060 } 2061 } 2062 } 2063 return; 2064 } else if (sc->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 2065 /* If still no link, perhaps using 2/3 pair cable */ 2066 em_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp); 2067 phy_tmp |= CR_1000T_MS_ENABLE; 2068 em_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp); 2069 if (sc->hw.autoneg && 2070 !em_phy_setup_autoneg(&sc->hw) && 2071 !em_read_phy_reg(&sc->hw, PHY_CTRL, &phy_tmp)) { 2072 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2073 MII_CR_RESTART_AUTO_NEG); 2074 em_write_phy_reg(&sc->hw, PHY_CTRL, phy_tmp); 2075 } 2076 } 2077 /* Restart process after EM_SMARTSPEED_MAX iterations */ 2078 if (sc->smartspeed++ == EM_SMARTSPEED_MAX) 2079 sc->smartspeed = 0; 2080 } 2081 2082 /* 2083 * Manage DMA'able memory. 2084 */ 2085 int 2086 em_dma_malloc(struct em_softc *sc, bus_size_t size, struct em_dma_alloc *dma) 2087 { 2088 int r; 2089 2090 r = bus_dmamap_create(sc->sc_dmat, size, 1, 2091 size, 0, BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, &dma->dma_map); 2092 if (r != 0) 2093 return (r); 2094 2095 r = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, &dma->dma_seg, 2096 1, &dma->dma_nseg, BUS_DMA_WAITOK | BUS_DMA_ZERO); 2097 if (r != 0) 2098 goto destroy; 2099 2100 r = bus_dmamem_map(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg, size, 2101 &dma->dma_vaddr, BUS_DMA_WAITOK); 2102 if (r != 0) 2103 goto free; 2104 2105 r = bus_dmamap_load(sc->sc_dmat, dma->dma_map, dma->dma_vaddr, size, 2106 NULL, BUS_DMA_WAITOK); 2107 if (r != 0) 2108 goto unmap; 2109 2110 dma->dma_size = size; 2111 return (0); 2112 2113 unmap: 2114 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, size); 2115 free: 2116 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 2117 destroy: 2118 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 2119 2120 return (r); 2121 } 2122 2123 void 2124 em_dma_free(struct em_softc *sc, struct em_dma_alloc *dma) 2125 { 2126 bus_dmamap_unload(sc->sc_dmat, dma->dma_map); 2127 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, dma->dma_size); 2128 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 2129 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 2130 } 2131 2132 /********************************************************************* 2133 * 2134 * Allocate memory for tx_buffer structures. The tx_buffer stores all 2135 * the information needed to transmit a packet on the wire. 2136 * 2137 **********************************************************************/ 2138 int 2139 em_allocate_transmit_structures(struct em_softc *sc) 2140 { 2141 struct em_queue *que = sc->queues; /* Use only first queue. */ 2142 2143 bus_dmamap_sync(sc->sc_dmat, que->tx.sc_tx_dma.dma_map, 2144 0, que->tx.sc_tx_dma.dma_map->dm_mapsize, 2145 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2146 2147 que->tx.sc_tx_pkts_ring = mallocarray(sc->sc_tx_slots, 2148 sizeof(*que->tx.sc_tx_pkts_ring), M_DEVBUF, M_NOWAIT | M_ZERO); 2149 if (que->tx.sc_tx_pkts_ring == NULL) { 2150 printf("%s: Unable to allocate tx_buffer memory\n", 2151 DEVNAME(sc)); 2152 return (ENOMEM); 2153 } 2154 2155 return (0); 2156 } 2157 2158 /********************************************************************* 2159 * 2160 * Allocate and initialize transmit structures. 2161 * 2162 **********************************************************************/ 2163 int 2164 em_setup_transmit_structures(struct em_softc *sc) 2165 { 2166 struct em_queue *que = sc->queues; /* Use only first queue. */ 2167 struct em_packet *pkt; 2168 int error, i; 2169 2170 if ((error = em_allocate_transmit_structures(sc)) != 0) 2171 goto fail; 2172 2173 bzero((void *) que->tx.sc_tx_desc_ring, 2174 (sizeof(struct em_tx_desc)) * sc->sc_tx_slots); 2175 2176 for (i = 0; i < sc->sc_tx_slots; i++) { 2177 pkt = &que->tx.sc_tx_pkts_ring[i]; 2178 error = bus_dmamap_create(sc->sc_dmat, MAX_JUMBO_FRAME_SIZE, 2179 EM_MAX_SCATTER / (sc->pcix_82544 ? 2 : 1), 2180 MAX_JUMBO_FRAME_SIZE, 0, BUS_DMA_NOWAIT, &pkt->pkt_map); 2181 if (error != 0) { 2182 printf("%s: Unable to create TX DMA map\n", 2183 DEVNAME(sc)); 2184 goto fail; 2185 } 2186 } 2187 2188 que->tx.sc_tx_desc_head = 0; 2189 que->tx.sc_tx_desc_tail = 0; 2190 2191 /* Set checksum context */ 2192 que->tx.active_checksum_context = OFFLOAD_NONE; 2193 2194 return (0); 2195 2196 fail: 2197 em_free_transmit_structures(sc); 2198 return (error); 2199 } 2200 2201 /********************************************************************* 2202 * 2203 * Enable transmit unit. 2204 * 2205 **********************************************************************/ 2206 void 2207 em_initialize_transmit_unit(struct em_softc *sc) 2208 { 2209 struct em_queue *que = sc->queues; /* Use only first queue. */ 2210 u_int32_t reg_tctl, reg_tipg = 0; 2211 u_int64_t bus_addr; 2212 2213 INIT_DEBUGOUT("em_initialize_transmit_unit: begin"); 2214 2215 /* Setup the Base and Length of the Tx Descriptor Ring */ 2216 bus_addr = que->tx.sc_tx_dma.dma_map->dm_segs[0].ds_addr; 2217 E1000_WRITE_REG(&sc->hw, TDLEN(que->me), 2218 sc->sc_tx_slots * 2219 sizeof(struct em_tx_desc)); 2220 E1000_WRITE_REG(&sc->hw, TDBAH(que->me), (u_int32_t)(bus_addr >> 32)); 2221 E1000_WRITE_REG(&sc->hw, TDBAL(que->me), (u_int32_t)bus_addr); 2222 2223 /* Setup the HW Tx Head and Tail descriptor pointers */ 2224 E1000_WRITE_REG(&sc->hw, TDT(que->me), 0); 2225 E1000_WRITE_REG(&sc->hw, TDH(que->me), 0); 2226 2227 HW_DEBUGOUT2("Base = %x, Length = %x\n", 2228 E1000_READ_REG(&sc->hw, TDBAL(que->me)), 2229 E1000_READ_REG(&sc->hw, TDLEN(que->me))); 2230 2231 /* Set the default values for the Tx Inter Packet Gap timer */ 2232 switch (sc->hw.mac_type) { 2233 case em_82542_rev2_0: 2234 case em_82542_rev2_1: 2235 reg_tipg = DEFAULT_82542_TIPG_IPGT; 2236 reg_tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2237 reg_tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2238 break; 2239 case em_80003es2lan: 2240 reg_tipg = DEFAULT_82543_TIPG_IPGR1; 2241 reg_tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2242 break; 2243 default: 2244 if (sc->hw.media_type == em_media_type_fiber || 2245 sc->hw.media_type == em_media_type_internal_serdes) 2246 reg_tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 2247 else 2248 reg_tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 2249 reg_tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2250 reg_tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2251 } 2252 2253 2254 E1000_WRITE_REG(&sc->hw, TIPG, reg_tipg); 2255 E1000_WRITE_REG(&sc->hw, TIDV, sc->tx_int_delay); 2256 if (sc->hw.mac_type >= em_82540) 2257 E1000_WRITE_REG(&sc->hw, TADV, sc->tx_abs_int_delay); 2258 2259 /* Setup Transmit Descriptor Base Settings */ 2260 que->tx.sc_txd_cmd = E1000_TXD_CMD_IFCS; 2261 2262 if (sc->hw.mac_type == em_82575 || sc->hw.mac_type == em_82580 || 2263 sc->hw.mac_type == em_82576 || 2264 sc->hw.mac_type == em_i210 || sc->hw.mac_type == em_i350) { 2265 /* 82575/6 need to enable the TX queue and lack the IDE bit */ 2266 reg_tctl = E1000_READ_REG(&sc->hw, TXDCTL(que->me)); 2267 reg_tctl |= E1000_TXDCTL_QUEUE_ENABLE; 2268 E1000_WRITE_REG(&sc->hw, TXDCTL(que->me), reg_tctl); 2269 } else if (sc->tx_int_delay > 0) 2270 que->tx.sc_txd_cmd |= E1000_TXD_CMD_IDE; 2271 2272 /* Program the Transmit Control Register */ 2273 reg_tctl = E1000_TCTL_PSP | E1000_TCTL_EN | 2274 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 2275 if (sc->hw.mac_type >= em_82571) 2276 reg_tctl |= E1000_TCTL_MULR; 2277 if (sc->link_duplex == FULL_DUPLEX) 2278 reg_tctl |= E1000_FDX_COLLISION_DISTANCE << E1000_COLD_SHIFT; 2279 else 2280 reg_tctl |= E1000_HDX_COLLISION_DISTANCE << E1000_COLD_SHIFT; 2281 /* This write will effectively turn on the transmit unit */ 2282 E1000_WRITE_REG(&sc->hw, TCTL, reg_tctl); 2283 2284 /* SPT Si errata workaround to avoid data corruption */ 2285 2286 if (sc->hw.mac_type == em_pch_spt) { 2287 uint32_t reg_val; 2288 2289 reg_val = EM_READ_REG(&sc->hw, E1000_IOSFPC); 2290 reg_val |= E1000_RCTL_RDMTS_HEX; 2291 EM_WRITE_REG(&sc->hw, E1000_IOSFPC, reg_val); 2292 2293 reg_val = E1000_READ_REG(&sc->hw, TARC0); 2294 /* i218-i219 Specification Update 1.5.4.5 */ 2295 reg_val &= ~E1000_TARC0_CB_MULTIQ_3_REQ; 2296 reg_val |= E1000_TARC0_CB_MULTIQ_2_REQ; 2297 E1000_WRITE_REG(&sc->hw, TARC0, reg_val); 2298 } 2299 } 2300 2301 /********************************************************************* 2302 * 2303 * Free all transmit related data structures. 2304 * 2305 **********************************************************************/ 2306 void 2307 em_free_transmit_structures(struct em_softc *sc) 2308 { 2309 struct em_queue *que = sc->queues; /* Use only first queue. */ 2310 struct em_packet *pkt; 2311 int i; 2312 2313 INIT_DEBUGOUT("free_transmit_structures: begin"); 2314 2315 if (que->tx.sc_tx_pkts_ring != NULL) { 2316 for (i = 0; i < sc->sc_tx_slots; i++) { 2317 pkt = &que->tx.sc_tx_pkts_ring[i]; 2318 2319 if (pkt->pkt_m != NULL) { 2320 bus_dmamap_sync(sc->sc_dmat, pkt->pkt_map, 2321 0, pkt->pkt_map->dm_mapsize, 2322 BUS_DMASYNC_POSTWRITE); 2323 bus_dmamap_unload(sc->sc_dmat, pkt->pkt_map); 2324 2325 m_freem(pkt->pkt_m); 2326 pkt->pkt_m = NULL; 2327 } 2328 2329 if (pkt->pkt_map != NULL) { 2330 bus_dmamap_destroy(sc->sc_dmat, pkt->pkt_map); 2331 pkt->pkt_map = NULL; 2332 } 2333 } 2334 2335 free(que->tx.sc_tx_pkts_ring, M_DEVBUF, 2336 sc->sc_tx_slots * sizeof(*que->tx.sc_tx_pkts_ring)); 2337 que->tx.sc_tx_pkts_ring = NULL; 2338 } 2339 2340 bus_dmamap_sync(sc->sc_dmat, que->tx.sc_tx_dma.dma_map, 2341 0, que->tx.sc_tx_dma.dma_map->dm_mapsize, 2342 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2343 } 2344 2345 /********************************************************************* 2346 * 2347 * The offload context needs to be set when we transfer the first 2348 * packet of a particular protocol (TCP/UDP). We change the 2349 * context only if the protocol type changes. 2350 * 2351 **********************************************************************/ 2352 u_int 2353 em_transmit_checksum_setup(struct em_queue *que, struct mbuf *mp, u_int head, 2354 u_int32_t *txd_upper, u_int32_t *txd_lower) 2355 { 2356 struct em_context_desc *TXD; 2357 2358 if (mp->m_pkthdr.csum_flags & M_TCP_CSUM_OUT) { 2359 *txd_upper = E1000_TXD_POPTS_TXSM << 8; 2360 *txd_lower = E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 2361 if (que->tx.active_checksum_context == OFFLOAD_TCP_IP) 2362 return (0); 2363 else 2364 que->tx.active_checksum_context = OFFLOAD_TCP_IP; 2365 } else if (mp->m_pkthdr.csum_flags & M_UDP_CSUM_OUT) { 2366 *txd_upper = E1000_TXD_POPTS_TXSM << 8; 2367 *txd_lower = E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 2368 if (que->tx.active_checksum_context == OFFLOAD_UDP_IP) 2369 return (0); 2370 else 2371 que->tx.active_checksum_context = OFFLOAD_UDP_IP; 2372 } else { 2373 *txd_upper = 0; 2374 *txd_lower = 0; 2375 return (0); 2376 } 2377 2378 /* If we reach this point, the checksum offload context 2379 * needs to be reset. 2380 */ 2381 TXD = (struct em_context_desc *)&que->tx.sc_tx_desc_ring[head]; 2382 2383 TXD->lower_setup.ip_fields.ipcss = ETHER_HDR_LEN; 2384 TXD->lower_setup.ip_fields.ipcso = 2385 ETHER_HDR_LEN + offsetof(struct ip, ip_sum); 2386 TXD->lower_setup.ip_fields.ipcse = 2387 htole16(ETHER_HDR_LEN + sizeof(struct ip) - 1); 2388 2389 TXD->upper_setup.tcp_fields.tucss = 2390 ETHER_HDR_LEN + sizeof(struct ip); 2391 TXD->upper_setup.tcp_fields.tucse = htole16(0); 2392 2393 if (que->tx.active_checksum_context == OFFLOAD_TCP_IP) { 2394 TXD->upper_setup.tcp_fields.tucso = 2395 ETHER_HDR_LEN + sizeof(struct ip) + 2396 offsetof(struct tcphdr, th_sum); 2397 } else if (que->tx.active_checksum_context == OFFLOAD_UDP_IP) { 2398 TXD->upper_setup.tcp_fields.tucso = 2399 ETHER_HDR_LEN + sizeof(struct ip) + 2400 offsetof(struct udphdr, uh_sum); 2401 } 2402 2403 TXD->tcp_seg_setup.data = htole32(0); 2404 TXD->cmd_and_length = htole32(que->tx.sc_txd_cmd | E1000_TXD_CMD_DEXT); 2405 2406 return (1); 2407 } 2408 2409 /********************************************************************** 2410 * 2411 * Examine each tx_buffer in the used queue. If the hardware is done 2412 * processing the packet then free associated resources. The 2413 * tx_buffer is put back on the free queue. 2414 * 2415 **********************************************************************/ 2416 void 2417 em_txeof(struct em_queue *que) 2418 { 2419 struct em_softc *sc = que->sc; 2420 struct ifnet *ifp = &sc->sc_ac.ac_if; 2421 struct em_packet *pkt; 2422 struct em_tx_desc *desc; 2423 u_int head, tail; 2424 u_int free = 0; 2425 2426 head = que->tx.sc_tx_desc_head; 2427 tail = que->tx.sc_tx_desc_tail; 2428 2429 if (head == tail) 2430 return; 2431 2432 bus_dmamap_sync(sc->sc_dmat, que->tx.sc_tx_dma.dma_map, 2433 0, que->tx.sc_tx_dma.dma_map->dm_mapsize, 2434 BUS_DMASYNC_POSTREAD); 2435 2436 do { 2437 pkt = &que->tx.sc_tx_pkts_ring[tail]; 2438 desc = &que->tx.sc_tx_desc_ring[pkt->pkt_eop]; 2439 2440 if (!ISSET(desc->upper.fields.status, E1000_TXD_STAT_DD)) 2441 break; 2442 2443 bus_dmamap_sync(sc->sc_dmat, pkt->pkt_map, 2444 0, pkt->pkt_map->dm_mapsize, 2445 BUS_DMASYNC_POSTWRITE); 2446 bus_dmamap_unload(sc->sc_dmat, pkt->pkt_map); 2447 2448 KASSERT(pkt->pkt_m != NULL); 2449 2450 m_freem(pkt->pkt_m); 2451 pkt->pkt_m = NULL; 2452 2453 tail = pkt->pkt_eop; 2454 2455 if (++tail == sc->sc_tx_slots) 2456 tail = 0; 2457 2458 free++; 2459 } while (tail != head); 2460 2461 bus_dmamap_sync(sc->sc_dmat, que->tx.sc_tx_dma.dma_map, 2462 0, que->tx.sc_tx_dma.dma_map->dm_mapsize, 2463 BUS_DMASYNC_PREREAD); 2464 2465 if (free == 0) 2466 return; 2467 2468 que->tx.sc_tx_desc_tail = tail; 2469 2470 if (ifq_is_oactive(&ifp->if_snd)) 2471 ifq_restart(&ifp->if_snd); 2472 else if (tail == head) 2473 ifp->if_timer = 0; 2474 } 2475 2476 /********************************************************************* 2477 * 2478 * Get a buffer from system mbuf buffer pool. 2479 * 2480 **********************************************************************/ 2481 int 2482 em_get_buf(struct em_queue *que, int i) 2483 { 2484 struct em_softc *sc = que->sc; 2485 struct mbuf *m; 2486 struct em_packet *pkt; 2487 struct em_rx_desc *desc; 2488 int error; 2489 2490 pkt = &que->rx.sc_rx_pkts_ring[i]; 2491 desc = &que->rx.sc_rx_desc_ring[i]; 2492 2493 KASSERT(pkt->pkt_m == NULL); 2494 2495 m = MCLGETI(NULL, M_DONTWAIT, NULL, EM_MCLBYTES); 2496 if (m == NULL) { 2497 sc->mbuf_cluster_failed++; 2498 return (ENOBUFS); 2499 } 2500 m->m_len = m->m_pkthdr.len = EM_MCLBYTES; 2501 m_adj(m, ETHER_ALIGN); 2502 2503 error = bus_dmamap_load_mbuf(sc->sc_dmat, pkt->pkt_map, 2504 m, BUS_DMA_NOWAIT); 2505 if (error) { 2506 m_freem(m); 2507 return (error); 2508 } 2509 2510 bus_dmamap_sync(sc->sc_dmat, pkt->pkt_map, 2511 0, pkt->pkt_map->dm_mapsize, 2512 BUS_DMASYNC_PREREAD); 2513 pkt->pkt_m = m; 2514 2515 memset(desc, 0, sizeof(*desc)); 2516 htolem64(&desc->buffer_addr, pkt->pkt_map->dm_segs[0].ds_addr); 2517 2518 return (0); 2519 } 2520 2521 /********************************************************************* 2522 * 2523 * Allocate memory for rx_buffer structures. Since we use one 2524 * rx_buffer per received packet, the maximum number of rx_buffer's 2525 * that we'll need is equal to the number of receive descriptors 2526 * that we've allocated. 2527 * 2528 **********************************************************************/ 2529 int 2530 em_allocate_receive_structures(struct em_softc *sc) 2531 { 2532 struct em_queue *que = sc->queues; /* Use only first queue. */ 2533 struct em_packet *pkt; 2534 int i; 2535 int error; 2536 2537 que->rx.sc_rx_pkts_ring = mallocarray(sc->sc_rx_slots, 2538 sizeof(*que->rx.sc_rx_pkts_ring), M_DEVBUF, M_NOWAIT | M_ZERO); 2539 if (que->rx.sc_rx_pkts_ring == NULL) { 2540 printf("%s: Unable to allocate rx_buffer memory\n", 2541 DEVNAME(sc)); 2542 return (ENOMEM); 2543 } 2544 2545 bus_dmamap_sync(sc->sc_dmat, que->rx.sc_rx_dma.dma_map, 2546 0, que->rx.sc_rx_dma.dma_map->dm_mapsize, 2547 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2548 2549 for (i = 0; i < sc->sc_rx_slots; i++) { 2550 pkt = &que->rx.sc_rx_pkts_ring[i]; 2551 2552 error = bus_dmamap_create(sc->sc_dmat, EM_MCLBYTES, 1, 2553 EM_MCLBYTES, 0, BUS_DMA_NOWAIT, &pkt->pkt_map); 2554 if (error != 0) { 2555 printf("%s: em_allocate_receive_structures: " 2556 "bus_dmamap_create failed; error %u\n", 2557 DEVNAME(sc), error); 2558 goto fail; 2559 } 2560 2561 pkt->pkt_m = NULL; 2562 } 2563 2564 return (0); 2565 2566 fail: 2567 em_free_receive_structures(sc); 2568 return (error); 2569 } 2570 2571 /********************************************************************* 2572 * 2573 * Allocate and initialize receive structures. 2574 * 2575 **********************************************************************/ 2576 int 2577 em_setup_receive_structures(struct em_softc *sc) 2578 { 2579 struct em_queue *que = sc->queues; /* Use only first queue. */ 2580 struct ifnet *ifp = &sc->sc_ac.ac_if; 2581 u_int lwm; 2582 2583 if (em_allocate_receive_structures(sc)) 2584 return (ENOMEM); 2585 2586 memset(que->rx.sc_rx_desc_ring, 0, 2587 sc->sc_rx_slots * sizeof(*que->rx.sc_rx_desc_ring)); 2588 2589 /* Setup our descriptor pointers */ 2590 que->rx.sc_rx_desc_tail = 0; 2591 que->rx.sc_rx_desc_head = sc->sc_rx_slots - 1; 2592 2593 lwm = max(4, 2 * ((ifp->if_hardmtu / MCLBYTES) + 1)); 2594 if_rxr_init(&que->rx.sc_rx_ring, lwm, sc->sc_rx_slots); 2595 2596 if (em_rxfill(que) == 0) { 2597 printf("%s: unable to fill any rx descriptors\n", 2598 DEVNAME(sc)); 2599 } 2600 2601 return (0); 2602 } 2603 2604 /********************************************************************* 2605 * 2606 * Enable receive unit. 2607 * 2608 **********************************************************************/ 2609 void 2610 em_initialize_receive_unit(struct em_softc *sc) 2611 { 2612 struct em_queue *que = sc->queues; /* Use only first queue. */ 2613 u_int32_t reg_rctl; 2614 u_int32_t reg_rxcsum; 2615 u_int64_t bus_addr; 2616 2617 INIT_DEBUGOUT("em_initialize_receive_unit: begin"); 2618 2619 /* Make sure receives are disabled while setting up the descriptor ring */ 2620 E1000_WRITE_REG(&sc->hw, RCTL, 0); 2621 2622 /* Set the Receive Delay Timer Register */ 2623 E1000_WRITE_REG(&sc->hw, RDTR, 2624 sc->rx_int_delay | E1000_RDT_FPDB); 2625 2626 if (sc->hw.mac_type >= em_82540) { 2627 if (sc->rx_int_delay) 2628 E1000_WRITE_REG(&sc->hw, RADV, sc->rx_abs_int_delay); 2629 2630 /* Set the interrupt throttling rate. Value is calculated 2631 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */ 2632 E1000_WRITE_REG(&sc->hw, ITR, DEFAULT_ITR); 2633 } 2634 2635 /* Setup the Receive Control Register */ 2636 reg_rctl = E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO | 2637 E1000_RCTL_RDMTS_HALF | 2638 (sc->hw.mc_filter_type << E1000_RCTL_MO_SHIFT); 2639 2640 if (sc->hw.tbi_compatibility_on == TRUE) 2641 reg_rctl |= E1000_RCTL_SBP; 2642 2643 /* 2644 * The i350 has a bug where it always strips the CRC whether 2645 * asked to or not. So ask for stripped CRC here and 2646 * cope in rxeof 2647 */ 2648 if (sc->hw.mac_type == em_i210 || sc->hw.mac_type == em_i350) 2649 reg_rctl |= E1000_RCTL_SECRC; 2650 2651 switch (sc->sc_rx_buffer_len) { 2652 default: 2653 case EM_RXBUFFER_2048: 2654 reg_rctl |= E1000_RCTL_SZ_2048; 2655 break; 2656 case EM_RXBUFFER_4096: 2657 reg_rctl |= E1000_RCTL_SZ_4096|E1000_RCTL_BSEX|E1000_RCTL_LPE; 2658 break; 2659 case EM_RXBUFFER_8192: 2660 reg_rctl |= E1000_RCTL_SZ_8192|E1000_RCTL_BSEX|E1000_RCTL_LPE; 2661 break; 2662 case EM_RXBUFFER_16384: 2663 reg_rctl |= E1000_RCTL_SZ_16384|E1000_RCTL_BSEX|E1000_RCTL_LPE; 2664 break; 2665 } 2666 2667 if (sc->hw.max_frame_size != ETHER_MAX_LEN) 2668 reg_rctl |= E1000_RCTL_LPE; 2669 2670 /* Enable 82543 Receive Checksum Offload for TCP and UDP */ 2671 if (sc->hw.mac_type >= em_82543) { 2672 reg_rxcsum = E1000_READ_REG(&sc->hw, RXCSUM); 2673 reg_rxcsum |= (E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL); 2674 E1000_WRITE_REG(&sc->hw, RXCSUM, reg_rxcsum); 2675 } 2676 2677 /* 2678 * XXX TEMPORARY WORKAROUND: on some systems with 82573 2679 * long latencies are observed, like Lenovo X60. 2680 */ 2681 if (sc->hw.mac_type == em_82573) 2682 E1000_WRITE_REG(&sc->hw, RDTR, 0x20); 2683 2684 /* Setup the Base and Length of the Rx Descriptor Ring */ 2685 bus_addr = que->rx.sc_rx_dma.dma_map->dm_segs[0].ds_addr; 2686 E1000_WRITE_REG(&sc->hw, RDLEN(que->me), 2687 sc->sc_rx_slots * sizeof(*que->rx.sc_rx_desc_ring)); 2688 E1000_WRITE_REG(&sc->hw, RDBAH(que->me), (u_int32_t)(bus_addr >> 32)); 2689 E1000_WRITE_REG(&sc->hw, RDBAL(que->me), (u_int32_t)bus_addr); 2690 2691 if (sc->hw.mac_type == em_82575 || sc->hw.mac_type == em_82580 || 2692 sc->hw.mac_type == em_82576 || 2693 sc->hw.mac_type == em_i210 || sc->hw.mac_type == em_i350) { 2694 /* 82575/6 need to enable the RX queue */ 2695 uint32_t reg; 2696 reg = E1000_READ_REG(&sc->hw, RXDCTL(que->me)); 2697 reg |= E1000_RXDCTL_QUEUE_ENABLE; 2698 E1000_WRITE_REG(&sc->hw, RXDCTL(que->me), reg); 2699 } 2700 2701 /* Enable Receives */ 2702 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 2703 2704 /* Setup the HW Rx Head and Tail Descriptor Pointers */ 2705 E1000_WRITE_REG(&sc->hw, RDH(que->me), 0); 2706 E1000_WRITE_REG(&sc->hw, RDT(que->me), que->rx.sc_rx_desc_head); 2707 } 2708 2709 /********************************************************************* 2710 * 2711 * Free receive related data structures. 2712 * 2713 **********************************************************************/ 2714 void 2715 em_free_receive_structures(struct em_softc *sc) 2716 { 2717 struct em_queue *que = sc->queues; /* Use only first queue. */ 2718 struct em_packet *pkt; 2719 int i; 2720 2721 INIT_DEBUGOUT("free_receive_structures: begin"); 2722 2723 if_rxr_init(&que->rx.sc_rx_ring, 0, 0); 2724 2725 bus_dmamap_sync(sc->sc_dmat, que->rx.sc_rx_dma.dma_map, 2726 0, que->rx.sc_rx_dma.dma_map->dm_mapsize, 2727 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2728 2729 if (que->rx.sc_rx_pkts_ring != NULL) { 2730 for (i = 0; i < sc->sc_rx_slots; i++) { 2731 pkt = &que->rx.sc_rx_pkts_ring[i]; 2732 if (pkt->pkt_m != NULL) { 2733 bus_dmamap_sync(sc->sc_dmat, pkt->pkt_map, 2734 0, pkt->pkt_map->dm_mapsize, 2735 BUS_DMASYNC_POSTREAD); 2736 bus_dmamap_unload(sc->sc_dmat, pkt->pkt_map); 2737 m_freem(pkt->pkt_m); 2738 pkt->pkt_m = NULL; 2739 } 2740 bus_dmamap_destroy(sc->sc_dmat, pkt->pkt_map); 2741 } 2742 2743 free(que->rx.sc_rx_pkts_ring, M_DEVBUF, 2744 sc->sc_rx_slots * sizeof(*que->rx.sc_rx_pkts_ring)); 2745 que->rx.sc_rx_pkts_ring = NULL; 2746 } 2747 2748 if (que->rx.fmp != NULL) { 2749 m_freem(que->rx.fmp); 2750 que->rx.fmp = NULL; 2751 que->rx.lmp = NULL; 2752 } 2753 } 2754 2755 int 2756 em_rxfill(struct em_queue *que) 2757 { 2758 struct em_softc *sc = que->sc; 2759 u_int slots; 2760 int post = 0; 2761 int i; 2762 2763 i = que->rx.sc_rx_desc_head; 2764 2765 bus_dmamap_sync(sc->sc_dmat, que->rx.sc_rx_dma.dma_map, 2766 0, que->rx.sc_rx_dma.dma_map->dm_mapsize, 2767 BUS_DMASYNC_POSTWRITE); 2768 2769 for (slots = if_rxr_get(&que->rx.sc_rx_ring, sc->sc_rx_slots); 2770 slots > 0; slots--) { 2771 if (++i == sc->sc_rx_slots) 2772 i = 0; 2773 2774 if (em_get_buf(que, i) != 0) 2775 break; 2776 2777 que->rx.sc_rx_desc_head = i; 2778 post = 1; 2779 } 2780 2781 if_rxr_put(&que->rx.sc_rx_ring, slots); 2782 2783 bus_dmamap_sync(sc->sc_dmat, que->rx.sc_rx_dma.dma_map, 2784 0, que->rx.sc_rx_dma.dma_map->dm_mapsize, 2785 BUS_DMASYNC_PREWRITE); 2786 2787 return (post); 2788 } 2789 2790 void 2791 em_rxrefill(void *arg) 2792 { 2793 struct em_queue *que = arg; 2794 struct em_softc *sc = que->sc; 2795 2796 if (em_rxfill(que)) 2797 E1000_WRITE_REG(&sc->hw, RDT(que->me), que->rx.sc_rx_desc_head); 2798 else if (if_rxr_inuse(&que->rx.sc_rx_ring) == 0) 2799 timeout_add(&que->rx_refill, 1); 2800 } 2801 2802 /********************************************************************* 2803 * 2804 * This routine executes in interrupt context. It replenishes 2805 * the mbufs in the descriptor and sends data which has been 2806 * dma'ed into host memory to upper layer. 2807 * 2808 *********************************************************************/ 2809 int 2810 em_rxeof(struct em_queue *que) 2811 { 2812 struct em_softc *sc = que->sc; 2813 struct ifnet *ifp = &sc->sc_ac.ac_if; 2814 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 2815 struct mbuf *m; 2816 u_int8_t accept_frame = 0; 2817 u_int8_t eop = 0; 2818 u_int16_t len, desc_len, prev_len_adj; 2819 int i, rv = 0; 2820 2821 /* Pointer to the receive descriptor being examined. */ 2822 struct em_rx_desc *desc; 2823 struct em_packet *pkt; 2824 u_int8_t status; 2825 2826 if (if_rxr_inuse(&que->rx.sc_rx_ring) == 0) 2827 return (0); 2828 2829 i = que->rx.sc_rx_desc_tail; 2830 2831 bus_dmamap_sync(sc->sc_dmat, que->rx.sc_rx_dma.dma_map, 2832 0, que->rx.sc_rx_dma.dma_map->dm_mapsize, 2833 BUS_DMASYNC_POSTREAD); 2834 2835 do { 2836 m = NULL; 2837 2838 pkt = &que->rx.sc_rx_pkts_ring[i]; 2839 desc = &que->rx.sc_rx_desc_ring[i]; 2840 2841 status = desc->status; 2842 if (!ISSET(status, E1000_RXD_STAT_DD)) 2843 break; 2844 2845 /* pull the mbuf off the ring */ 2846 bus_dmamap_sync(sc->sc_dmat, pkt->pkt_map, 2847 0, pkt->pkt_map->dm_mapsize, 2848 BUS_DMASYNC_POSTREAD); 2849 bus_dmamap_unload(sc->sc_dmat, pkt->pkt_map); 2850 m = pkt->pkt_m; 2851 pkt->pkt_m = NULL; 2852 2853 KASSERT(m != NULL); 2854 2855 if_rxr_put(&que->rx.sc_rx_ring, 1); 2856 rv = 1; 2857 2858 accept_frame = 1; 2859 prev_len_adj = 0; 2860 desc_len = letoh16(desc->length); 2861 2862 if (status & E1000_RXD_STAT_EOP) { 2863 eop = 1; 2864 if (desc_len < ETHER_CRC_LEN) { 2865 len = 0; 2866 prev_len_adj = ETHER_CRC_LEN - desc_len; 2867 } else if (sc->hw.mac_type == em_i210 || 2868 sc->hw.mac_type == em_i350) 2869 len = desc_len; 2870 else 2871 len = desc_len - ETHER_CRC_LEN; 2872 } else { 2873 eop = 0; 2874 len = desc_len; 2875 } 2876 2877 if (desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK) { 2878 u_int8_t last_byte; 2879 u_int32_t pkt_len = desc_len; 2880 2881 if (que->rx.fmp != NULL) 2882 pkt_len += que->rx.fmp->m_pkthdr.len; 2883 2884 last_byte = *(mtod(m, caddr_t) + desc_len - 1); 2885 if (TBI_ACCEPT(&sc->hw, status, desc->errors, 2886 pkt_len, last_byte)) { 2887 #ifndef SMALL_KERNEL 2888 em_tbi_adjust_stats(&sc->hw, &sc->stats, 2889 pkt_len, sc->hw.mac_addr); 2890 #endif 2891 if (len > 0) 2892 len--; 2893 } else 2894 accept_frame = 0; 2895 } 2896 2897 if (accept_frame) { 2898 /* Assign correct length to the current fragment */ 2899 m->m_len = len; 2900 2901 if (que->rx.fmp == NULL) { 2902 m->m_pkthdr.len = m->m_len; 2903 que->rx.fmp = m; /* Store the first mbuf */ 2904 que->rx.lmp = m; 2905 } else { 2906 /* Chain mbuf's together */ 2907 m->m_flags &= ~M_PKTHDR; 2908 /* 2909 * Adjust length of previous mbuf in chain if 2910 * we received less than 4 bytes in the last 2911 * descriptor. 2912 */ 2913 if (prev_len_adj > 0) { 2914 que->rx.lmp->m_len -= prev_len_adj; 2915 que->rx.fmp->m_pkthdr.len -= prev_len_adj; 2916 } 2917 que->rx.lmp->m_next = m; 2918 que->rx.lmp = m; 2919 que->rx.fmp->m_pkthdr.len += m->m_len; 2920 } 2921 2922 if (eop) { 2923 m = que->rx.fmp; 2924 2925 em_receive_checksum(sc, desc, m); 2926 #if NVLAN > 0 2927 if (desc->status & E1000_RXD_STAT_VP) { 2928 m->m_pkthdr.ether_vtag = 2929 letoh16(desc->special); 2930 m->m_flags |= M_VLANTAG; 2931 } 2932 #endif 2933 ml_enqueue(&ml, m); 2934 2935 que->rx.fmp = NULL; 2936 que->rx.lmp = NULL; 2937 } 2938 } else { 2939 que->rx.dropped_pkts++; 2940 2941 if (que->rx.fmp != NULL) { 2942 m_freem(que->rx.fmp); 2943 que->rx.fmp = NULL; 2944 que->rx.lmp = NULL; 2945 } 2946 2947 m_freem(m); 2948 } 2949 2950 /* Advance our pointers to the next descriptor. */ 2951 if (++i == sc->sc_rx_slots) 2952 i = 0; 2953 } while (if_rxr_inuse(&que->rx.sc_rx_ring) > 0); 2954 2955 bus_dmamap_sync(sc->sc_dmat, que->rx.sc_rx_dma.dma_map, 2956 0, que->rx.sc_rx_dma.dma_map->dm_mapsize, 2957 BUS_DMASYNC_PREREAD); 2958 2959 que->rx.sc_rx_desc_tail = i; 2960 2961 if_input(ifp, &ml); 2962 2963 return (rv); 2964 } 2965 2966 /********************************************************************* 2967 * 2968 * Verify that the hardware indicated that the checksum is valid. 2969 * Inform the stack about the status of checksum so that stack 2970 * doesn't spend time verifying the checksum. 2971 * 2972 *********************************************************************/ 2973 void 2974 em_receive_checksum(struct em_softc *sc, struct em_rx_desc *rx_desc, 2975 struct mbuf *mp) 2976 { 2977 /* 82543 or newer only */ 2978 if ((sc->hw.mac_type < em_82543) || 2979 /* Ignore Checksum bit is set */ 2980 (rx_desc->status & E1000_RXD_STAT_IXSM)) { 2981 mp->m_pkthdr.csum_flags = 0; 2982 return; 2983 } 2984 2985 if (rx_desc->status & E1000_RXD_STAT_IPCS) { 2986 /* Did it pass? */ 2987 if (!(rx_desc->errors & E1000_RXD_ERR_IPE)) { 2988 /* IP Checksum Good */ 2989 mp->m_pkthdr.csum_flags = M_IPV4_CSUM_IN_OK; 2990 2991 } else 2992 mp->m_pkthdr.csum_flags = 0; 2993 } 2994 2995 if (rx_desc->status & E1000_RXD_STAT_TCPCS) { 2996 /* Did it pass? */ 2997 if (!(rx_desc->errors & E1000_RXD_ERR_TCPE)) 2998 mp->m_pkthdr.csum_flags |= 2999 M_TCP_CSUM_IN_OK | M_UDP_CSUM_IN_OK; 3000 } 3001 } 3002 3003 /* 3004 * This turns on the hardware offload of the VLAN 3005 * tag insertion and strip 3006 */ 3007 void 3008 em_enable_hw_vlans(struct em_softc *sc) 3009 { 3010 uint32_t ctrl; 3011 3012 ctrl = E1000_READ_REG(&sc->hw, CTRL); 3013 ctrl |= E1000_CTRL_VME; 3014 E1000_WRITE_REG(&sc->hw, CTRL, ctrl); 3015 } 3016 3017 void 3018 em_enable_intr(struct em_softc *sc) 3019 { 3020 E1000_WRITE_REG(&sc->hw, IMS, (IMS_ENABLE_MASK)); 3021 } 3022 3023 void 3024 em_disable_intr(struct em_softc *sc) 3025 { 3026 /* 3027 * The first version of 82542 had an errata where when link 3028 * was forced it would stay up even if the cable was disconnected 3029 * Sequence errors were used to detect the disconnect and then 3030 * the driver would unforce the link. This code is in the ISR. 3031 * For this to work correctly the Sequence error interrupt had 3032 * to be enabled all the time. 3033 */ 3034 3035 if (sc->hw.mac_type == em_82542_rev2_0) 3036 E1000_WRITE_REG(&sc->hw, IMC, (0xffffffff & ~E1000_IMC_RXSEQ)); 3037 else 3038 E1000_WRITE_REG(&sc->hw, IMC, 0xffffffff); 3039 } 3040 3041 void 3042 em_write_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t *value) 3043 { 3044 struct pci_attach_args *pa = &((struct em_osdep *)hw->back)->em_pa; 3045 pcireg_t val; 3046 3047 val = pci_conf_read(pa->pa_pc, pa->pa_tag, reg & ~0x3); 3048 if (reg & 0x2) { 3049 val &= 0x0000ffff; 3050 val |= (*value << 16); 3051 } else { 3052 val &= 0xffff0000; 3053 val |= *value; 3054 } 3055 pci_conf_write(pa->pa_pc, pa->pa_tag, reg & ~0x3, val); 3056 } 3057 3058 void 3059 em_read_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t *value) 3060 { 3061 struct pci_attach_args *pa = &((struct em_osdep *)hw->back)->em_pa; 3062 pcireg_t val; 3063 3064 val = pci_conf_read(pa->pa_pc, pa->pa_tag, reg & ~0x3); 3065 if (reg & 0x2) 3066 *value = (val >> 16) & 0xffff; 3067 else 3068 *value = val & 0xffff; 3069 } 3070 3071 void 3072 em_pci_set_mwi(struct em_hw *hw) 3073 { 3074 struct pci_attach_args *pa = &((struct em_osdep *)hw->back)->em_pa; 3075 3076 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 3077 (hw->pci_cmd_word | CMD_MEM_WRT_INVALIDATE)); 3078 } 3079 3080 void 3081 em_pci_clear_mwi(struct em_hw *hw) 3082 { 3083 struct pci_attach_args *pa = &((struct em_osdep *)hw->back)->em_pa; 3084 3085 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 3086 (hw->pci_cmd_word & ~CMD_MEM_WRT_INVALIDATE)); 3087 } 3088 3089 /* 3090 * We may eventually really do this, but its unnecessary 3091 * for now so we just return unsupported. 3092 */ 3093 int32_t 3094 em_read_pcie_cap_reg(struct em_hw *hw, uint32_t reg, uint16_t *value) 3095 { 3096 return -E1000_NOT_IMPLEMENTED; 3097 } 3098 3099 /********************************************************************* 3100 * 82544 Coexistence issue workaround. 3101 * There are 2 issues. 3102 * 1. Transmit Hang issue. 3103 * To detect this issue, following equation can be used... 3104 * SIZE[3:0] + ADDR[2:0] = SUM[3:0]. 3105 * If SUM[3:0] is in between 1 to 4, we will have this issue. 3106 * 3107 * 2. DAC issue. 3108 * To detect this issue, following equation can be used... 3109 * SIZE[3:0] + ADDR[2:0] = SUM[3:0]. 3110 * If SUM[3:0] is in between 9 to c, we will have this issue. 3111 * 3112 * 3113 * WORKAROUND: 3114 * Make sure we do not have ending address as 1,2,3,4(Hang) or 9,a,b,c (DAC) 3115 * 3116 *** *********************************************************************/ 3117 u_int32_t 3118 em_fill_descriptors(u_int64_t address, u_int32_t length, 3119 PDESC_ARRAY desc_array) 3120 { 3121 /* Since issue is sensitive to length and address.*/ 3122 /* Let us first check the address...*/ 3123 u_int32_t safe_terminator; 3124 if (length <= 4) { 3125 desc_array->descriptor[0].address = address; 3126 desc_array->descriptor[0].length = length; 3127 desc_array->elements = 1; 3128 return desc_array->elements; 3129 } 3130 safe_terminator = (u_int32_t)((((u_int32_t)address & 0x7) + (length & 0xF)) & 0xF); 3131 /* if it does not fall between 0x1 to 0x4 and 0x9 to 0xC then return */ 3132 if (safe_terminator == 0 || 3133 (safe_terminator > 4 && 3134 safe_terminator < 9) || 3135 (safe_terminator > 0xC && 3136 safe_terminator <= 0xF)) { 3137 desc_array->descriptor[0].address = address; 3138 desc_array->descriptor[0].length = length; 3139 desc_array->elements = 1; 3140 return desc_array->elements; 3141 } 3142 3143 desc_array->descriptor[0].address = address; 3144 desc_array->descriptor[0].length = length - 4; 3145 desc_array->descriptor[1].address = address + (length - 4); 3146 desc_array->descriptor[1].length = 4; 3147 desc_array->elements = 2; 3148 return desc_array->elements; 3149 } 3150 3151 /* 3152 * Disable the L0S and L1 LINK states. 3153 */ 3154 void 3155 em_disable_aspm(struct em_softc *sc) 3156 { 3157 int offset; 3158 pcireg_t val; 3159 3160 switch (sc->hw.mac_type) { 3161 case em_82571: 3162 case em_82572: 3163 case em_82573: 3164 case em_82574: 3165 break; 3166 default: 3167 return; 3168 } 3169 3170 if (!pci_get_capability(sc->osdep.em_pa.pa_pc, sc->osdep.em_pa.pa_tag, 3171 PCI_CAP_PCIEXPRESS, &offset, NULL)) 3172 return; 3173 3174 /* Disable PCIe Active State Power Management (ASPM). */ 3175 val = pci_conf_read(sc->osdep.em_pa.pa_pc, sc->osdep.em_pa.pa_tag, 3176 offset + PCI_PCIE_LCSR); 3177 3178 switch (sc->hw.mac_type) { 3179 case em_82571: 3180 case em_82572: 3181 val &= ~PCI_PCIE_LCSR_ASPM_L1; 3182 break; 3183 case em_82573: 3184 case em_82574: 3185 val &= ~(PCI_PCIE_LCSR_ASPM_L0S | 3186 PCI_PCIE_LCSR_ASPM_L1); 3187 break; 3188 default: 3189 break; 3190 } 3191 3192 pci_conf_write(sc->osdep.em_pa.pa_pc, sc->osdep.em_pa.pa_tag, 3193 offset + PCI_PCIE_LCSR, val); 3194 } 3195 3196 /* 3197 * em_flush_tx_ring - remove all descriptors from the tx_ring 3198 * 3199 * We want to clear all pending descriptors from the TX ring. 3200 * zeroing happens when the HW reads the regs. We assign the ring itself as 3201 * the data of the next descriptor. We don't care about the data we are about 3202 * to reset the HW. 3203 */ 3204 void 3205 em_flush_tx_ring(struct em_queue *que) 3206 { 3207 struct em_softc *sc = que->sc; 3208 uint32_t tctl, txd_lower = E1000_TXD_CMD_IFCS; 3209 uint16_t size = 512; 3210 struct em_tx_desc *txd; 3211 3212 KASSERT(que->tx.sc_tx_desc_ring != NULL); 3213 3214 tctl = EM_READ_REG(&sc->hw, E1000_TCTL); 3215 EM_WRITE_REG(&sc->hw, E1000_TCTL, tctl | E1000_TCTL_EN); 3216 3217 KASSERT(EM_READ_REG(&sc->hw, E1000_TDT(que->me)) == que->tx.sc_tx_desc_head); 3218 3219 txd = &que->tx.sc_tx_desc_ring[que->tx.sc_tx_desc_head]; 3220 txd->buffer_addr = que->tx.sc_tx_dma.dma_map->dm_segs[0].ds_addr; 3221 txd->lower.data = htole32(txd_lower | size); 3222 txd->upper.data = 0; 3223 3224 /* flush descriptors to memory before notifying the HW */ 3225 bus_space_barrier(sc->osdep.mem_bus_space_tag, 3226 sc->osdep.mem_bus_space_handle, 0, 0, BUS_SPACE_BARRIER_WRITE); 3227 3228 if (++que->tx.sc_tx_desc_head == sc->sc_tx_slots) 3229 que->tx.sc_tx_desc_head = 0; 3230 3231 EM_WRITE_REG(&sc->hw, E1000_TDT(que->me), que->tx.sc_tx_desc_head); 3232 bus_space_barrier(sc->osdep.mem_bus_space_tag, sc->osdep.mem_bus_space_handle, 3233 0, 0, BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE); 3234 usec_delay(250); 3235 } 3236 3237 /* 3238 * em_flush_rx_ring - remove all descriptors from the rx_ring 3239 * 3240 * Mark all descriptors in the RX ring as consumed and disable the rx ring 3241 */ 3242 void 3243 em_flush_rx_ring(struct em_queue *que) 3244 { 3245 uint32_t rctl, rxdctl; 3246 struct em_softc *sc = que->sc; 3247 3248 rctl = EM_READ_REG(&sc->hw, E1000_RCTL); 3249 EM_WRITE_REG(&sc->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 3250 E1000_WRITE_FLUSH(&sc->hw); 3251 usec_delay(150); 3252 3253 rxdctl = EM_READ_REG(&sc->hw, E1000_RXDCTL(que->me)); 3254 /* zero the lower 14 bits (prefetch and host thresholds) */ 3255 rxdctl &= 0xffffc000; 3256 /* 3257 * update thresholds: prefetch threshold to 31, host threshold to 1 3258 * and make sure the granularity is "descriptors" and not "cache lines" 3259 */ 3260 rxdctl |= (0x1F | (1 << 8) | E1000_RXDCTL_THRESH_UNIT_DESC); 3261 EM_WRITE_REG(&sc->hw, E1000_RXDCTL(que->me), rxdctl); 3262 3263 /* momentarily enable the RX ring for the changes to take effect */ 3264 EM_WRITE_REG(&sc->hw, E1000_RCTL, rctl | E1000_RCTL_EN); 3265 E1000_WRITE_FLUSH(&sc->hw); 3266 usec_delay(150); 3267 EM_WRITE_REG(&sc->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 3268 } 3269 3270 /* 3271 * em_flush_desc_rings - remove all descriptors from the descriptor rings 3272 * 3273 * In i219, the descriptor rings must be emptied before resetting the HW 3274 * or before changing the device state to D3 during runtime (runtime PM). 3275 * 3276 * Failure to do this will cause the HW to enter a unit hang state which can 3277 * only be released by PCI reset on the device 3278 * 3279 */ 3280 void 3281 em_flush_desc_rings(struct em_softc *sc) 3282 { 3283 struct em_queue *que = sc->queues; /* Use only first queue. */ 3284 struct pci_attach_args *pa = &sc->osdep.em_pa; 3285 uint32_t fextnvm11, tdlen; 3286 uint16_t hang_state; 3287 3288 /* First, disable MULR fix in FEXTNVM11 */ 3289 fextnvm11 = EM_READ_REG(&sc->hw, E1000_FEXTNVM11); 3290 fextnvm11 |= E1000_FEXTNVM11_DISABLE_MULR_FIX; 3291 EM_WRITE_REG(&sc->hw, E1000_FEXTNVM11, fextnvm11); 3292 3293 /* do nothing if we're not in faulty state, or if the queue is empty */ 3294 tdlen = EM_READ_REG(&sc->hw, E1000_TDLEN(que->me)); 3295 hang_state = pci_conf_read(pa->pa_pc, pa->pa_tag, PCICFG_DESC_RING_STATUS); 3296 if (!(hang_state & FLUSH_DESC_REQUIRED) || !tdlen) 3297 return; 3298 em_flush_tx_ring(que); 3299 3300 /* recheck, maybe the fault is caused by the rx ring */ 3301 hang_state = pci_conf_read(pa->pa_pc, pa->pa_tag, PCICFG_DESC_RING_STATUS); 3302 if (hang_state & FLUSH_DESC_REQUIRED) 3303 em_flush_rx_ring(que); 3304 } 3305 3306 #ifndef SMALL_KERNEL 3307 /********************************************************************** 3308 * 3309 * Update the board statistics counters. 3310 * 3311 **********************************************************************/ 3312 void 3313 em_update_stats_counters(struct em_softc *sc) 3314 { 3315 struct em_queue *que = sc->queues; /* Use only first queue. */ 3316 struct ifnet *ifp = &sc->sc_ac.ac_if; 3317 3318 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, CRCERRS); 3319 sc->stats.mpc += E1000_READ_REG(&sc->hw, MPC); 3320 sc->stats.ecol += E1000_READ_REG(&sc->hw, ECOL); 3321 3322 sc->stats.latecol += E1000_READ_REG(&sc->hw, LATECOL); 3323 sc->stats.colc += E1000_READ_REG(&sc->hw, COLC); 3324 3325 sc->stats.ruc += E1000_READ_REG(&sc->hw, RUC); 3326 sc->stats.roc += E1000_READ_REG(&sc->hw, ROC); 3327 3328 if (sc->hw.mac_type >= em_82543) { 3329 sc->stats.algnerrc += 3330 E1000_READ_REG(&sc->hw, ALGNERRC); 3331 sc->stats.rxerrc += 3332 E1000_READ_REG(&sc->hw, RXERRC); 3333 sc->stats.cexterr += 3334 E1000_READ_REG(&sc->hw, CEXTERR); 3335 } 3336 3337 #ifdef EM_DEBUG 3338 if (sc->hw.media_type == em_media_type_copper || 3339 (E1000_READ_REG(&sc->hw, STATUS) & E1000_STATUS_LU)) { 3340 sc->stats.symerrs += E1000_READ_REG(&sc->hw, SYMERRS); 3341 sc->stats.sec += E1000_READ_REG(&sc->hw, SEC); 3342 } 3343 sc->stats.scc += E1000_READ_REG(&sc->hw, SCC); 3344 3345 sc->stats.mcc += E1000_READ_REG(&sc->hw, MCC); 3346 sc->stats.dc += E1000_READ_REG(&sc->hw, DC); 3347 sc->stats.rlec += E1000_READ_REG(&sc->hw, RLEC); 3348 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, XONRXC); 3349 sc->stats.xontxc += E1000_READ_REG(&sc->hw, XONTXC); 3350 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, XOFFRXC); 3351 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, XOFFTXC); 3352 sc->stats.fcruc += E1000_READ_REG(&sc->hw, FCRUC); 3353 sc->stats.prc64 += E1000_READ_REG(&sc->hw, PRC64); 3354 sc->stats.prc127 += E1000_READ_REG(&sc->hw, PRC127); 3355 sc->stats.prc255 += E1000_READ_REG(&sc->hw, PRC255); 3356 sc->stats.prc511 += E1000_READ_REG(&sc->hw, PRC511); 3357 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, PRC1023); 3358 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, PRC1522); 3359 sc->stats.gprc += E1000_READ_REG(&sc->hw, GPRC); 3360 sc->stats.bprc += E1000_READ_REG(&sc->hw, BPRC); 3361 sc->stats.mprc += E1000_READ_REG(&sc->hw, MPRC); 3362 sc->stats.gptc += E1000_READ_REG(&sc->hw, GPTC); 3363 3364 /* For the 64-bit byte counters the low dword must be read first. */ 3365 /* Both registers clear on the read of the high dword */ 3366 3367 sc->stats.gorcl += E1000_READ_REG(&sc->hw, GORCL); 3368 sc->stats.gorch += E1000_READ_REG(&sc->hw, GORCH); 3369 sc->stats.gotcl += E1000_READ_REG(&sc->hw, GOTCL); 3370 sc->stats.gotch += E1000_READ_REG(&sc->hw, GOTCH); 3371 3372 sc->stats.rnbc += E1000_READ_REG(&sc->hw, RNBC); 3373 sc->stats.rfc += E1000_READ_REG(&sc->hw, RFC); 3374 sc->stats.rjc += E1000_READ_REG(&sc->hw, RJC); 3375 3376 sc->stats.torl += E1000_READ_REG(&sc->hw, TORL); 3377 sc->stats.torh += E1000_READ_REG(&sc->hw, TORH); 3378 sc->stats.totl += E1000_READ_REG(&sc->hw, TOTL); 3379 sc->stats.toth += E1000_READ_REG(&sc->hw, TOTH); 3380 3381 sc->stats.tpr += E1000_READ_REG(&sc->hw, TPR); 3382 sc->stats.tpt += E1000_READ_REG(&sc->hw, TPT); 3383 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, PTC64); 3384 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, PTC127); 3385 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, PTC255); 3386 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, PTC511); 3387 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, PTC1023); 3388 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, PTC1522); 3389 sc->stats.mptc += E1000_READ_REG(&sc->hw, MPTC); 3390 sc->stats.bptc += E1000_READ_REG(&sc->hw, BPTC); 3391 sc->stats.sdpc += E1000_READ_REG(&sc->hw, SDPC); 3392 sc->stats.mngpdc += E1000_READ_REG(&sc->hw, MGTPDC); 3393 sc->stats.mngprc += E1000_READ_REG(&sc->hw, MGTPRC); 3394 sc->stats.mngptc += E1000_READ_REG(&sc->hw, MGTPTC); 3395 sc->stats.b2ospc += E1000_READ_REG(&sc->hw, B2OSPC); 3396 sc->stats.o2bgptc += E1000_READ_REG(&sc->hw, O2BGPTC); 3397 sc->stats.b2ogprc += E1000_READ_REG(&sc->hw, B2OGPRC); 3398 sc->stats.o2bspc += E1000_READ_REG(&sc->hw, O2BSPC); 3399 sc->stats.rpthc += E1000_READ_REG(&sc->hw, RPTHC); 3400 3401 if (sc->hw.mac_type >= em_82543) { 3402 sc->stats.tncrs += 3403 E1000_READ_REG(&sc->hw, TNCRS); 3404 sc->stats.tsctc += 3405 E1000_READ_REG(&sc->hw, TSCTC); 3406 sc->stats.tsctfc += 3407 E1000_READ_REG(&sc->hw, TSCTFC); 3408 } 3409 #endif 3410 3411 /* Fill out the OS statistics structure */ 3412 ifp->if_collisions = sc->stats.colc; 3413 3414 /* Rx Errors */ 3415 ifp->if_ierrors = 3416 que->rx.dropped_pkts + 3417 sc->stats.rxerrc + 3418 sc->stats.crcerrs + 3419 sc->stats.algnerrc + 3420 sc->stats.ruc + sc->stats.roc + 3421 sc->stats.mpc + sc->stats.cexterr + 3422 sc->rx_overruns; 3423 3424 /* Tx Errors */ 3425 ifp->if_oerrors = sc->stats.ecol + sc->stats.latecol + 3426 sc->watchdog_events; 3427 } 3428 3429 #ifdef EM_DEBUG 3430 /********************************************************************** 3431 * 3432 * This routine is called only when IFF_DEBUG is enabled. 3433 * This routine provides a way to take a look at important statistics 3434 * maintained by the driver and hardware. 3435 * 3436 **********************************************************************/ 3437 void 3438 em_print_hw_stats(struct em_softc *sc) 3439 { 3440 const char * const unit = DEVNAME(sc); 3441 3442 printf("%s: Excessive collisions = %lld\n", unit, 3443 (long long)sc->stats.ecol); 3444 printf("%s: Symbol errors = %lld\n", unit, 3445 (long long)sc->stats.symerrs); 3446 printf("%s: Sequence errors = %lld\n", unit, 3447 (long long)sc->stats.sec); 3448 printf("%s: Defer count = %lld\n", unit, 3449 (long long)sc->stats.dc); 3450 3451 printf("%s: Missed Packets = %lld\n", unit, 3452 (long long)sc->stats.mpc); 3453 printf("%s: Receive No Buffers = %lld\n", unit, 3454 (long long)sc->stats.rnbc); 3455 /* RLEC is inaccurate on some hardware, calculate our own */ 3456 printf("%s: Receive Length Errors = %lld\n", unit, 3457 ((long long)sc->stats.roc + 3458 (long long)sc->stats.ruc)); 3459 printf("%s: Receive errors = %lld\n", unit, 3460 (long long)sc->stats.rxerrc); 3461 printf("%s: Crc errors = %lld\n", unit, 3462 (long long)sc->stats.crcerrs); 3463 printf("%s: Alignment errors = %lld\n", unit, 3464 (long long)sc->stats.algnerrc); 3465 printf("%s: Carrier extension errors = %lld\n", unit, 3466 (long long)sc->stats.cexterr); 3467 3468 printf("%s: RX overruns = %ld\n", unit, 3469 sc->rx_overruns); 3470 printf("%s: watchdog timeouts = %ld\n", unit, 3471 sc->watchdog_events); 3472 3473 printf("%s: XON Rcvd = %lld\n", unit, 3474 (long long)sc->stats.xonrxc); 3475 printf("%s: XON Xmtd = %lld\n", unit, 3476 (long long)sc->stats.xontxc); 3477 printf("%s: XOFF Rcvd = %lld\n", unit, 3478 (long long)sc->stats.xoffrxc); 3479 printf("%s: XOFF Xmtd = %lld\n", unit, 3480 (long long)sc->stats.xofftxc); 3481 3482 printf("%s: Good Packets Rcvd = %lld\n", unit, 3483 (long long)sc->stats.gprc); 3484 printf("%s: Good Packets Xmtd = %lld\n", unit, 3485 (long long)sc->stats.gptc); 3486 printf("%s: Switch Drop Packet Count = %lld\n", unit, 3487 (long long)sc->stats.sdpc); 3488 printf("%s: Management Packets Dropped Count = %lld\n", unit, 3489 (long long)sc->stats.mngptc); 3490 printf("%s: Management Packets Received Count = %lld\n", unit, 3491 (long long)sc->stats.mngprc); 3492 printf("%s: Management Packets Transmitted Count = %lld\n", unit, 3493 (long long)sc->stats.mngptc); 3494 printf("%s: OS2BMC Packets Sent by MC Count = %lld\n", unit, 3495 (long long)sc->stats.b2ospc); 3496 printf("%s: OS2BMC Packets Received by MC Count = %lld\n", unit, 3497 (long long)sc->stats.o2bgptc); 3498 printf("%s: OS2BMC Packets Received by Host Count = %lld\n", unit, 3499 (long long)sc->stats.b2ogprc); 3500 printf("%s: OS2BMC Packets Transmitted by Host Count = %lld\n", unit, 3501 (long long)sc->stats.o2bspc); 3502 printf("%s: Multicast Packets Received Count = %lld\n", unit, 3503 (long long)sc->stats.mprc); 3504 printf("%s: Rx Packets to Host Count = %lld\n", unit, 3505 (long long)sc->stats.rpthc); 3506 } 3507 #endif 3508 #endif /* !SMALL_KERNEL */ 3509 3510 int 3511 em_allocate_desc_rings(struct em_softc *sc) 3512 { 3513 struct em_queue *que = sc->queues; /* Use only first queue. */ 3514 3515 /* Allocate Transmit Descriptor ring */ 3516 if (em_dma_malloc(sc, sc->sc_tx_slots * sizeof(struct em_tx_desc), 3517 &que->tx.sc_tx_dma) != 0) { 3518 printf("%s: Unable to allocate tx_desc memory\n", 3519 DEVNAME(sc)); 3520 return (ENOMEM); 3521 } 3522 que->tx.sc_tx_desc_ring = 3523 (struct em_tx_desc *)que->tx.sc_tx_dma.dma_vaddr; 3524 3525 /* Allocate Receive Descriptor ring */ 3526 if (em_dma_malloc(sc, sc->sc_rx_slots * sizeof(struct em_rx_desc), 3527 &que->rx.sc_rx_dma) != 0) { 3528 printf("%s: Unable to allocate rx_desc memory\n", 3529 DEVNAME(sc)); 3530 return (ENOMEM); 3531 } 3532 que->rx.sc_rx_desc_ring = 3533 (struct em_rx_desc *)que->rx.sc_rx_dma.dma_vaddr; 3534 3535 return (0); 3536 } 3537