1 /************************************************************************** 2 3 Copyright (c) 2001-2003, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ***************************************************************************/ 33 34 /* $OpenBSD: if_em.c,v 1.338 2018/03/10 04:41:36 jsg Exp $ */ 35 /* $FreeBSD: if_em.c,v 1.46 2004/09/29 18:28:28 mlaier Exp $ */ 36 37 #include <dev/pci/if_em.h> 38 #include <dev/pci/if_em_soc.h> 39 40 /********************************************************************* 41 * Driver version 42 *********************************************************************/ 43 44 #define EM_DRIVER_VERSION "6.2.9" 45 46 /********************************************************************* 47 * PCI Device ID Table 48 *********************************************************************/ 49 const struct pci_matchid em_devices[] = { 50 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80003ES2LAN_CPR_DPT }, 51 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80003ES2LAN_SDS_DPT }, 52 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80003ES2LAN_CPR_SPT }, 53 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80003ES2LAN_SDS_SPT }, 54 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM }, 55 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM_LOM }, 56 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP }, 57 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LOM }, 58 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LP }, 59 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI }, 60 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI_MOBILE }, 61 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541ER }, 62 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541ER_LOM }, 63 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI }, 64 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI_LF }, 65 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI_MOBILE }, 66 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82542 }, 67 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_COPPER }, 68 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_FIBER }, 69 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_COPPER }, 70 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_FIBER }, 71 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_COPPER }, 72 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_LOM }, 73 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_COPPER }, 74 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_FIBER }, 75 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_COPPER }, 76 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_FIBER }, 77 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_SERDES }, 78 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_COPPER }, 79 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_FIBER }, 80 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_QUAD_CPR }, 81 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_COPPER }, 82 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_FIBER }, 83 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_PCIE }, 84 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_QUAD_CPR }, 85 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_QUAD_CPR_K }, 86 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_SERDES }, 87 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_2 }, 88 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547EI }, 89 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547EI_MOBILE }, 90 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547GI }, 91 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_AF }, 92 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_AT }, 93 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_COPPER }, 94 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_FIBER }, 95 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_QUAD_CPR }, 96 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_QUAD_CPR_LP }, 97 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_QUAD_FBR }, 98 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_SERDES }, 99 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_SDS_DUAL }, 100 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_SDS_QUAD }, 101 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571PT_QUAD_CPR }, 102 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI_COPPER }, 103 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI_FIBER }, 104 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI_SERDES }, 105 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI }, 106 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573E }, 107 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573E_IAMT }, 108 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573E_PM }, 109 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573L }, 110 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573L_PL_1 }, 111 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573L_PL_2 }, 112 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573V_PM }, 113 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82574L }, 114 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82574LA }, 115 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82575EB_COPPER }, 116 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82575EB_SERDES }, 117 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82575GB_QUAD_CPR }, 118 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82575GB_QP_PM }, 119 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576 }, 120 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_FIBER }, 121 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_SERDES }, 122 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_QUAD_COPPER }, 123 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_QUAD_CU_ET2 }, 124 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_NS }, 125 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_NS_SERDES }, 126 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_SERDES_QUAD }, 127 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82577LC }, 128 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82577LM }, 129 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82578DC }, 130 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82578DM }, 131 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82579LM }, 132 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82579V }, 133 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_COPPER }, 134 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_COPPER_OEM1 }, 135 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_COPPER_IT }, 136 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_FIBER }, 137 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_SERDES }, 138 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_SGMII }, 139 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_COPPER_NF }, 140 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_SERDES_NF }, 141 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I211_COPPER }, 142 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I217_LM }, 143 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I217_V }, 144 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_LM }, 145 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_LM_2 }, 146 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_LM_3 }, 147 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_V }, 148 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_V_2 }, 149 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_V_3 }, 150 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_LM }, 151 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_LM2 }, 152 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_LM3 }, 153 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_LM4 }, 154 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_LM5 }, 155 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_V }, 156 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_V2 }, 157 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_V4 }, 158 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_V5 }, 159 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_COPPER }, 160 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_FIBER }, 161 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_SERDES }, 162 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_SGMII }, 163 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_COPPER_DUAL }, 164 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_QUAD_FIBER }, 165 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCC_SGMII }, 166 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCC_SERDES }, 167 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCC_BPLANE }, 168 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCC_SFP }, 169 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82583V }, 170 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I350_COPPER }, 171 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I350_FIBER }, 172 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I350_SERDES }, 173 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I350_SGMII }, 174 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I354_BP_1GBPS }, 175 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I354_BP_2_5GBPS }, 176 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I354_SGMII }, 177 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_82567V_3 }, 178 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_IFE }, 179 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_IFE_G }, 180 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_IFE_GT }, 181 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_IGP_AMT }, 182 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_IGP_C }, 183 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_IGP_M }, 184 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_IGP_M_AMT }, 185 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_BM }, 186 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IFE }, 187 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IFE_G }, 188 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IFE_GT }, 189 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IGP_AMT }, 190 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IGP_C }, 191 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IGP_M }, 192 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IGP_M_AMT }, 193 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IGP_M_V }, 194 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH10_D_BM_LF }, 195 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH10_D_BM_LM }, 196 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH10_D_BM_V }, 197 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH10_R_BM_LF }, 198 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH10_R_BM_LM }, 199 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH10_R_BM_V }, 200 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EP80579_LAN_1 }, 201 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EP80579_LAN_2 }, 202 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EP80579_LAN_3 }, 203 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EP80579_LAN_4 }, 204 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EP80579_LAN_5 }, 205 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EP80579_LAN_6 } 206 }; 207 208 /********************************************************************* 209 * Function prototypes 210 *********************************************************************/ 211 int em_probe(struct device *, void *, void *); 212 void em_attach(struct device *, struct device *, void *); 213 void em_defer_attach(struct device*); 214 int em_detach(struct device *, int); 215 int em_activate(struct device *, int); 216 int em_intr(void *); 217 void em_start(struct ifqueue *); 218 int em_ioctl(struct ifnet *, u_long, caddr_t); 219 void em_watchdog(struct ifnet *); 220 void em_init(void *); 221 void em_stop(void *, int); 222 void em_media_status(struct ifnet *, struct ifmediareq *); 223 int em_media_change(struct ifnet *); 224 uint64_t em_flowstatus(struct em_softc *); 225 void em_identify_hardware(struct em_softc *); 226 int em_allocate_pci_resources(struct em_softc *); 227 void em_free_pci_resources(struct em_softc *); 228 void em_local_timer(void *); 229 int em_hardware_init(struct em_softc *); 230 void em_setup_interface(struct em_softc *); 231 int em_setup_transmit_structures(struct em_softc *); 232 void em_initialize_transmit_unit(struct em_softc *); 233 int em_setup_receive_structures(struct em_softc *); 234 void em_initialize_receive_unit(struct em_softc *); 235 void em_enable_intr(struct em_softc *); 236 void em_disable_intr(struct em_softc *); 237 void em_free_transmit_structures(struct em_softc *); 238 void em_free_receive_structures(struct em_softc *); 239 void em_update_stats_counters(struct em_softc *); 240 void em_disable_aspm(struct em_softc *); 241 void em_txeof(struct em_softc *); 242 int em_allocate_receive_structures(struct em_softc *); 243 int em_allocate_transmit_structures(struct em_softc *); 244 int em_rxfill(struct em_softc *); 245 int em_rxeof(struct em_softc *); 246 void em_receive_checksum(struct em_softc *, struct em_rx_desc *, 247 struct mbuf *); 248 u_int em_transmit_checksum_setup(struct em_softc *, struct mbuf *, u_int, 249 u_int32_t *, u_int32_t *); 250 void em_iff(struct em_softc *); 251 #ifdef EM_DEBUG 252 void em_print_hw_stats(struct em_softc *); 253 #endif 254 void em_update_link_status(struct em_softc *); 255 int em_get_buf(struct em_softc *, int); 256 void em_enable_hw_vlans(struct em_softc *); 257 u_int em_encap(struct em_softc *, struct mbuf *); 258 void em_smartspeed(struct em_softc *); 259 int em_82547_fifo_workaround(struct em_softc *, int); 260 void em_82547_update_fifo_head(struct em_softc *, int); 261 int em_82547_tx_fifo_reset(struct em_softc *); 262 void em_82547_move_tail(void *arg); 263 void em_82547_move_tail_locked(struct em_softc *); 264 int em_dma_malloc(struct em_softc *, bus_size_t, struct em_dma_alloc *); 265 void em_dma_free(struct em_softc *, struct em_dma_alloc *); 266 u_int32_t em_fill_descriptors(u_int64_t address, u_int32_t length, 267 PDESC_ARRAY desc_array); 268 void em_flush_tx_ring(struct em_softc *); 269 void em_flush_rx_ring(struct em_softc *); 270 void em_flush_desc_rings(struct em_softc *); 271 272 /********************************************************************* 273 * OpenBSD Device Interface Entry Points 274 *********************************************************************/ 275 276 struct cfattach em_ca = { 277 sizeof(struct em_softc), em_probe, em_attach, em_detach, 278 em_activate 279 }; 280 281 struct cfdriver em_cd = { 282 NULL, "em", DV_IFNET 283 }; 284 285 static int em_smart_pwr_down = FALSE; 286 287 /********************************************************************* 288 * Device identification routine 289 * 290 * em_probe determines if the driver should be loaded on 291 * adapter based on PCI vendor/device id of the adapter. 292 * 293 * return 0 on no match, positive on match 294 *********************************************************************/ 295 296 int 297 em_probe(struct device *parent, void *match, void *aux) 298 { 299 INIT_DEBUGOUT("em_probe: begin"); 300 301 return (pci_matchbyid((struct pci_attach_args *)aux, em_devices, 302 nitems(em_devices))); 303 } 304 305 void 306 em_defer_attach(struct device *self) 307 { 308 struct em_softc *sc = (struct em_softc *)self; 309 struct pci_attach_args *pa = &sc->osdep.em_pa; 310 pci_chipset_tag_t pc = pa->pa_pc; 311 void *gcu; 312 313 INIT_DEBUGOUT("em_defer_attach: begin"); 314 315 if ((gcu = em_lookup_gcu(self)) == 0) { 316 printf("%s: No GCU found, defered attachment failed\n", 317 DEVNAME(sc)); 318 319 if (sc->sc_intrhand) 320 pci_intr_disestablish(pc, sc->sc_intrhand); 321 sc->sc_intrhand = 0; 322 323 em_stop(sc, 1); 324 325 em_free_pci_resources(sc); 326 327 sc->sc_rx_desc_ring = NULL; 328 em_dma_free(sc, &sc->sc_rx_dma); 329 sc->sc_tx_desc_ring = NULL; 330 em_dma_free(sc, &sc->sc_tx_dma); 331 332 return; 333 } 334 335 sc->hw.gcu = gcu; 336 337 em_attach_miibus(self); 338 339 em_setup_interface(sc); 340 341 em_setup_link(&sc->hw); 342 343 em_update_link_status(sc); 344 } 345 346 /********************************************************************* 347 * Device initialization routine 348 * 349 * The attach entry point is called when the driver is being loaded. 350 * This routine identifies the type of hardware, allocates all resources 351 * and initializes the hardware. 352 * 353 *********************************************************************/ 354 355 void 356 em_attach(struct device *parent, struct device *self, void *aux) 357 { 358 struct pci_attach_args *pa = aux; 359 struct em_softc *sc; 360 int defer = 0; 361 362 INIT_DEBUGOUT("em_attach: begin"); 363 364 sc = (struct em_softc *)self; 365 sc->sc_dmat = pa->pa_dmat; 366 sc->osdep.em_pa = *pa; 367 368 timeout_set(&sc->timer_handle, em_local_timer, sc); 369 timeout_set(&sc->tx_fifo_timer_handle, em_82547_move_tail, sc); 370 371 /* Determine hardware revision */ 372 em_identify_hardware(sc); 373 374 /* 375 * Only use MSI on the newer PCIe parts, with the exception 376 * of 82571/82572 due to "Byte Enables 2 and 3 Are Not Set" errata 377 */ 378 if (sc->hw.mac_type <= em_82572) 379 sc->osdep.em_pa.pa_flags &= ~PCI_FLAGS_MSI_ENABLED; 380 381 /* Parameters (to be read from user) */ 382 if (sc->hw.mac_type >= em_82544) { 383 sc->sc_tx_slots = EM_MAX_TXD; 384 sc->sc_rx_slots = EM_MAX_RXD; 385 } else { 386 sc->sc_tx_slots = EM_MAX_TXD_82543; 387 sc->sc_rx_slots = EM_MAX_RXD_82543; 388 } 389 sc->tx_int_delay = EM_TIDV; 390 sc->tx_abs_int_delay = EM_TADV; 391 sc->rx_int_delay = EM_RDTR; 392 sc->rx_abs_int_delay = EM_RADV; 393 sc->hw.autoneg = DO_AUTO_NEG; 394 sc->hw.wait_autoneg_complete = WAIT_FOR_AUTO_NEG_DEFAULT; 395 sc->hw.autoneg_advertised = AUTONEG_ADV_DEFAULT; 396 sc->hw.tbi_compatibility_en = TRUE; 397 sc->sc_rx_buffer_len = EM_RXBUFFER_2048; 398 399 sc->hw.phy_init_script = 1; 400 sc->hw.phy_reset_disable = FALSE; 401 402 #ifndef EM_MASTER_SLAVE 403 sc->hw.master_slave = em_ms_hw_default; 404 #else 405 sc->hw.master_slave = EM_MASTER_SLAVE; 406 #endif 407 408 /* 409 * This controls when hardware reports transmit completion 410 * status. 411 */ 412 sc->hw.report_tx_early = 1; 413 414 if (em_allocate_pci_resources(sc)) 415 goto err_pci; 416 417 /* Initialize eeprom parameters */ 418 em_init_eeprom_params(&sc->hw); 419 420 /* 421 * Set the max frame size assuming standard Ethernet 422 * sized frames. 423 */ 424 switch (sc->hw.mac_type) { 425 case em_82573: 426 { 427 uint16_t eeprom_data = 0; 428 429 /* 430 * 82573 only supports Jumbo frames 431 * if ASPM is disabled. 432 */ 433 em_read_eeprom(&sc->hw, EEPROM_INIT_3GIO_3, 434 1, &eeprom_data); 435 if (eeprom_data & EEPROM_WORD1A_ASPM_MASK) { 436 sc->hw.max_frame_size = ETHER_MAX_LEN; 437 break; 438 } 439 /* Allow Jumbo frames */ 440 /* FALLTHROUGH */ 441 } 442 case em_82571: 443 case em_82572: 444 case em_82574: 445 case em_82575: 446 case em_82580: 447 case em_i210: 448 case em_i350: 449 case em_ich9lan: 450 case em_ich10lan: 451 case em_pch2lan: 452 case em_pch_lpt: 453 case em_pch_spt: 454 case em_80003es2lan: 455 /* 9K Jumbo Frame size */ 456 sc->hw.max_frame_size = 9234; 457 break; 458 case em_pchlan: 459 sc->hw.max_frame_size = 4096; 460 break; 461 case em_82542_rev2_0: 462 case em_82542_rev2_1: 463 case em_ich8lan: 464 /* Adapters that do not support Jumbo frames */ 465 sc->hw.max_frame_size = ETHER_MAX_LEN; 466 break; 467 default: 468 sc->hw.max_frame_size = 469 MAX_JUMBO_FRAME_SIZE; 470 } 471 472 sc->hw.min_frame_size = 473 ETHER_MIN_LEN + ETHER_CRC_LEN; 474 475 /* Allocate Transmit Descriptor ring */ 476 if (em_dma_malloc(sc, sc->sc_tx_slots * sizeof(struct em_tx_desc), 477 &sc->sc_tx_dma) != 0) { 478 printf("%s: Unable to allocate tx_desc memory\n", 479 DEVNAME(sc)); 480 goto err_tx_desc; 481 } 482 sc->sc_tx_desc_ring = (struct em_tx_desc *)sc->sc_tx_dma.dma_vaddr; 483 484 /* Allocate Receive Descriptor ring */ 485 if (em_dma_malloc(sc, sc->sc_rx_slots * sizeof(struct em_rx_desc), 486 &sc->sc_rx_dma) != 0) { 487 printf("%s: Unable to allocate rx_desc memory\n", 488 DEVNAME(sc)); 489 goto err_rx_desc; 490 } 491 sc->sc_rx_desc_ring = (struct em_rx_desc *)sc->sc_rx_dma.dma_vaddr; 492 493 /* Initialize the hardware */ 494 if ((defer = em_hardware_init(sc))) { 495 if (defer == EAGAIN) 496 config_defer(self, em_defer_attach); 497 else { 498 printf("%s: Unable to initialize the hardware\n", 499 DEVNAME(sc)); 500 goto err_hw_init; 501 } 502 } 503 504 if (sc->hw.mac_type == em_80003es2lan || sc->hw.mac_type == em_82575 || 505 sc->hw.mac_type == em_82580 || sc->hw.mac_type == em_i210 || 506 sc->hw.mac_type == em_i350) { 507 uint32_t reg = EM_READ_REG(&sc->hw, E1000_STATUS); 508 sc->hw.bus_func = (reg & E1000_STATUS_FUNC_MASK) >> 509 E1000_STATUS_FUNC_SHIFT; 510 511 switch (sc->hw.bus_func) { 512 case 0: 513 sc->hw.swfw = E1000_SWFW_PHY0_SM; 514 break; 515 case 1: 516 sc->hw.swfw = E1000_SWFW_PHY1_SM; 517 break; 518 case 2: 519 sc->hw.swfw = E1000_SWFW_PHY2_SM; 520 break; 521 case 3: 522 sc->hw.swfw = E1000_SWFW_PHY3_SM; 523 break; 524 } 525 } else { 526 sc->hw.bus_func = 0; 527 } 528 529 /* Copy the permanent MAC address out of the EEPROM */ 530 if (em_read_mac_addr(&sc->hw) < 0) { 531 printf("%s: EEPROM read error while reading mac address\n", 532 DEVNAME(sc)); 533 goto err_mac_addr; 534 } 535 536 bcopy(sc->hw.mac_addr, sc->sc_ac.ac_enaddr, ETHER_ADDR_LEN); 537 538 /* Setup OS specific network interface */ 539 if (!defer) 540 em_setup_interface(sc); 541 542 /* Initialize statistics */ 543 em_clear_hw_cntrs(&sc->hw); 544 #ifndef SMALL_KERNEL 545 em_update_stats_counters(sc); 546 #endif 547 sc->hw.get_link_status = 1; 548 if (!defer) 549 em_update_link_status(sc); 550 551 printf(", address %s\n", ether_sprintf(sc->sc_ac.ac_enaddr)); 552 553 /* Indicate SOL/IDER usage */ 554 if (em_check_phy_reset_block(&sc->hw)) 555 printf("%s: PHY reset is blocked due to SOL/IDER session.\n", 556 DEVNAME(sc)); 557 558 /* Identify 82544 on PCI-X */ 559 em_get_bus_info(&sc->hw); 560 if (sc->hw.bus_type == em_bus_type_pcix && 561 sc->hw.mac_type == em_82544) 562 sc->pcix_82544 = TRUE; 563 else 564 sc->pcix_82544 = FALSE; 565 566 sc->hw.icp_xxxx_is_link_up = FALSE; 567 568 INIT_DEBUGOUT("em_attach: end"); 569 return; 570 571 err_mac_addr: 572 err_hw_init: 573 sc->sc_rx_desc_ring = NULL; 574 em_dma_free(sc, &sc->sc_rx_dma); 575 err_rx_desc: 576 sc->sc_tx_desc_ring = NULL; 577 em_dma_free(sc, &sc->sc_tx_dma); 578 err_tx_desc: 579 err_pci: 580 em_free_pci_resources(sc); 581 } 582 583 /********************************************************************* 584 * Transmit entry point 585 * 586 * em_start is called by the stack to initiate a transmit. 587 * The driver will remain in this routine as long as there are 588 * packets to transmit and transmit resources are available. 589 * In case resources are not available stack is notified and 590 * the packet is requeued. 591 **********************************************************************/ 592 593 void 594 em_start(struct ifqueue *ifq) 595 { 596 struct ifnet *ifp = ifq->ifq_if; 597 struct em_softc *sc = ifp->if_softc; 598 u_int head, free, used; 599 struct mbuf *m; 600 int post = 0; 601 602 if (!sc->link_active) { 603 ifq_purge(ifq); 604 return; 605 } 606 607 /* calculate free space */ 608 head = sc->sc_tx_desc_head; 609 free = sc->sc_tx_desc_tail; 610 if (free <= head) 611 free += sc->sc_tx_slots; 612 free -= head; 613 614 if (sc->hw.mac_type != em_82547) { 615 bus_dmamap_sync(sc->sc_dmat, sc->sc_tx_dma.dma_map, 616 0, sc->sc_tx_dma.dma_map->dm_mapsize, 617 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 618 } 619 620 for (;;) { 621 /* use 2 because cksum setup can use an extra slot */ 622 if (EM_MAX_SCATTER + 2 > free) { 623 ifq_set_oactive(ifq); 624 break; 625 } 626 627 m = ifq_dequeue(ifq); 628 if (m == NULL) 629 break; 630 631 used = em_encap(sc, m); 632 if (used == 0) { 633 m_freem(m); 634 continue; 635 } 636 637 KASSERT(used <= free); 638 639 free -= used; 640 641 #if NBPFILTER > 0 642 /* Send a copy of the frame to the BPF listener */ 643 if (ifp->if_bpf) 644 bpf_mtap_ether(ifp->if_bpf, m, BPF_DIRECTION_OUT); 645 #endif 646 647 /* Set timeout in case hardware has problems transmitting */ 648 ifp->if_timer = EM_TX_TIMEOUT; 649 650 if (sc->hw.mac_type == em_82547) { 651 int len = m->m_pkthdr.len; 652 653 if (sc->link_duplex == HALF_DUPLEX) 654 em_82547_move_tail_locked(sc); 655 else { 656 E1000_WRITE_REG(&sc->hw, TDT, 657 sc->sc_tx_desc_head); 658 em_82547_update_fifo_head(sc, len); 659 } 660 } 661 662 post = 1; 663 } 664 665 if (sc->hw.mac_type != em_82547) { 666 bus_dmamap_sync(sc->sc_dmat, sc->sc_tx_dma.dma_map, 667 0, sc->sc_tx_dma.dma_map->dm_mapsize, 668 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 669 /* 670 * Advance the Transmit Descriptor Tail (Tdt), 671 * this tells the E1000 that this frame is 672 * available to transmit. 673 */ 674 if (post) 675 E1000_WRITE_REG(&sc->hw, TDT, sc->sc_tx_desc_head); 676 } 677 } 678 679 /********************************************************************* 680 * Ioctl entry point 681 * 682 * em_ioctl is called when the user wants to configure the 683 * interface. 684 * 685 * return 0 on success, positive on failure 686 **********************************************************************/ 687 688 int 689 em_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 690 { 691 int error = 0; 692 struct ifreq *ifr = (struct ifreq *) data; 693 struct em_softc *sc = ifp->if_softc; 694 int s; 695 696 s = splnet(); 697 698 switch (command) { 699 case SIOCSIFADDR: 700 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFADDR (Set Interface " 701 "Addr)"); 702 if (!(ifp->if_flags & IFF_UP)) { 703 ifp->if_flags |= IFF_UP; 704 em_init(sc); 705 } 706 break; 707 708 case SIOCSIFFLAGS: 709 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFFLAGS (Set Interface Flags)"); 710 if (ifp->if_flags & IFF_UP) { 711 if (ifp->if_flags & IFF_RUNNING) 712 error = ENETRESET; 713 else 714 em_init(sc); 715 } else { 716 if (ifp->if_flags & IFF_RUNNING) 717 em_stop(sc, 0); 718 } 719 break; 720 721 case SIOCSIFMEDIA: 722 /* Check SOL/IDER usage */ 723 if (em_check_phy_reset_block(&sc->hw)) { 724 printf("%s: Media change is blocked due to SOL/IDER session.\n", 725 DEVNAME(sc)); 726 break; 727 } 728 case SIOCGIFMEDIA: 729 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCxIFMEDIA (Get/Set Interface Media)"); 730 error = ifmedia_ioctl(ifp, ifr, &sc->media, command); 731 break; 732 733 case SIOCGIFRXR: 734 error = if_rxr_ioctl((struct if_rxrinfo *)ifr->ifr_data, 735 NULL, EM_MCLBYTES, &sc->sc_rx_ring); 736 break; 737 738 default: 739 error = ether_ioctl(ifp, &sc->sc_ac, command, data); 740 } 741 742 if (error == ENETRESET) { 743 if (ifp->if_flags & IFF_RUNNING) { 744 em_disable_intr(sc); 745 em_iff(sc); 746 if (sc->hw.mac_type == em_82542_rev2_0) 747 em_initialize_receive_unit(sc); 748 em_enable_intr(sc); 749 } 750 error = 0; 751 } 752 753 splx(s); 754 return (error); 755 } 756 757 /********************************************************************* 758 * Watchdog entry point 759 * 760 * This routine is called whenever hardware quits transmitting. 761 * 762 **********************************************************************/ 763 764 void 765 em_watchdog(struct ifnet *ifp) 766 { 767 struct em_softc *sc = ifp->if_softc; 768 769 /* If we are in this routine because of pause frames, then 770 * don't reset the hardware. 771 */ 772 if (E1000_READ_REG(&sc->hw, STATUS) & E1000_STATUS_TXOFF) { 773 ifp->if_timer = EM_TX_TIMEOUT; 774 return; 775 } 776 printf("%s: watchdog: head %u tail %u TDH %u TDT %u\n", 777 DEVNAME(sc), 778 sc->sc_tx_desc_head, sc->sc_tx_desc_tail, 779 E1000_READ_REG(&sc->hw, TDH), E1000_READ_REG(&sc->hw, TDT)); 780 781 em_init(sc); 782 783 sc->watchdog_events++; 784 } 785 786 /********************************************************************* 787 * Init entry point 788 * 789 * This routine is used in two ways. It is used by the stack as 790 * init entry point in network interface structure. It is also used 791 * by the driver as a hw/sw initialization routine to get to a 792 * consistent state. 793 * 794 **********************************************************************/ 795 796 void 797 em_init(void *arg) 798 { 799 struct em_softc *sc = arg; 800 struct ifnet *ifp = &sc->sc_ac.ac_if; 801 uint32_t pba; 802 int s; 803 804 s = splnet(); 805 806 INIT_DEBUGOUT("em_init: begin"); 807 808 em_stop(sc, 0); 809 810 /* 811 * Packet Buffer Allocation (PBA) 812 * Writing PBA sets the receive portion of the buffer 813 * the remainder is used for the transmit buffer. 814 * 815 * Devices before the 82547 had a Packet Buffer of 64K. 816 * Default allocation: PBA=48K for Rx, leaving 16K for Tx. 817 * After the 82547 the buffer was reduced to 40K. 818 * Default allocation: PBA=30K for Rx, leaving 10K for Tx. 819 * Note: default does not leave enough room for Jumbo Frame >10k. 820 */ 821 switch (sc->hw.mac_type) { 822 case em_82547: 823 case em_82547_rev_2: /* 82547: Total Packet Buffer is 40K */ 824 if (sc->hw.max_frame_size > EM_RXBUFFER_8192) 825 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 826 else 827 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 828 sc->tx_fifo_head = 0; 829 sc->tx_head_addr = pba << EM_TX_HEAD_ADDR_SHIFT; 830 sc->tx_fifo_size = (E1000_PBA_40K - pba) << EM_PBA_BYTES_SHIFT; 831 break; 832 case em_82571: 833 case em_82572: /* Total Packet Buffer on these is 48k */ 834 case em_82575: 835 case em_82580: 836 case em_80003es2lan: 837 case em_i350: 838 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 839 break; 840 case em_i210: 841 pba = E1000_PBA_34K; 842 break; 843 case em_82573: /* 82573: Total Packet Buffer is 32K */ 844 /* Jumbo frames not supported */ 845 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 846 break; 847 case em_82574: /* Total Packet Buffer is 40k */ 848 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */ 849 break; 850 case em_ich8lan: 851 pba = E1000_PBA_8K; 852 break; 853 case em_ich9lan: 854 case em_ich10lan: 855 /* Boost Receive side for jumbo frames */ 856 if (sc->hw.max_frame_size > EM_RXBUFFER_4096) 857 pba = E1000_PBA_14K; 858 else 859 pba = E1000_PBA_10K; 860 break; 861 case em_pchlan: 862 case em_pch2lan: 863 case em_pch_lpt: 864 case em_pch_spt: 865 pba = E1000_PBA_26K; 866 break; 867 default: 868 /* Devices before 82547 had a Packet Buffer of 64K. */ 869 if (sc->hw.max_frame_size > EM_RXBUFFER_8192) 870 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 871 else 872 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 873 } 874 INIT_DEBUGOUT1("em_init: pba=%dK",pba); 875 E1000_WRITE_REG(&sc->hw, PBA, pba); 876 877 /* Get the latest mac address, User can use a LAA */ 878 bcopy(sc->sc_ac.ac_enaddr, sc->hw.mac_addr, ETHER_ADDR_LEN); 879 880 /* Initialize the hardware */ 881 if (em_hardware_init(sc)) { 882 printf("%s: Unable to initialize the hardware\n", 883 DEVNAME(sc)); 884 splx(s); 885 return; 886 } 887 em_update_link_status(sc); 888 889 E1000_WRITE_REG(&sc->hw, VET, ETHERTYPE_VLAN); 890 if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) 891 em_enable_hw_vlans(sc); 892 893 /* Prepare transmit descriptors and buffers */ 894 if (em_setup_transmit_structures(sc)) { 895 printf("%s: Could not setup transmit structures\n", 896 DEVNAME(sc)); 897 em_stop(sc, 0); 898 splx(s); 899 return; 900 } 901 em_initialize_transmit_unit(sc); 902 903 /* Prepare receive descriptors and buffers */ 904 if (em_setup_receive_structures(sc)) { 905 printf("%s: Could not setup receive structures\n", 906 DEVNAME(sc)); 907 em_stop(sc, 0); 908 splx(s); 909 return; 910 } 911 em_initialize_receive_unit(sc); 912 913 /* Program promiscuous mode and multicast filters. */ 914 em_iff(sc); 915 916 ifp->if_flags |= IFF_RUNNING; 917 ifq_clr_oactive(&ifp->if_snd); 918 919 timeout_add_sec(&sc->timer_handle, 1); 920 em_clear_hw_cntrs(&sc->hw); 921 em_enable_intr(sc); 922 923 /* Don't reset the phy next time init gets called */ 924 sc->hw.phy_reset_disable = TRUE; 925 926 splx(s); 927 } 928 929 /********************************************************************* 930 * 931 * Interrupt Service routine 932 * 933 **********************************************************************/ 934 int 935 em_intr(void *arg) 936 { 937 struct em_softc *sc = arg; 938 struct ifnet *ifp = &sc->sc_ac.ac_if; 939 u_int32_t reg_icr, test_icr; 940 941 test_icr = reg_icr = E1000_READ_REG(&sc->hw, ICR); 942 if (sc->hw.mac_type >= em_82571) 943 test_icr = (reg_icr & E1000_ICR_INT_ASSERTED); 944 if (!test_icr) 945 return (0); 946 947 if (ifp->if_flags & IFF_RUNNING) { 948 em_txeof(sc); 949 950 if (em_rxeof(sc) || ISSET(reg_icr, E1000_ICR_RXO)) { 951 if (em_rxfill(sc)) { 952 E1000_WRITE_REG(&sc->hw, RDT, 953 sc->sc_rx_desc_head); 954 } 955 } 956 } 957 958 /* Link status change */ 959 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 960 KERNEL_LOCK(); 961 sc->hw.get_link_status = 1; 962 em_check_for_link(&sc->hw); 963 em_update_link_status(sc); 964 KERNEL_UNLOCK(); 965 } 966 967 return (1); 968 } 969 970 /********************************************************************* 971 * 972 * Media Ioctl callback 973 * 974 * This routine is called whenever the user queries the status of 975 * the interface using ifconfig. 976 * 977 **********************************************************************/ 978 void 979 em_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 980 { 981 struct em_softc *sc = ifp->if_softc; 982 uint64_t fiber_type = IFM_1000_SX; 983 u_int16_t gsr; 984 985 INIT_DEBUGOUT("em_media_status: begin"); 986 987 em_check_for_link(&sc->hw); 988 em_update_link_status(sc); 989 990 ifmr->ifm_status = IFM_AVALID; 991 ifmr->ifm_active = IFM_ETHER; 992 993 if (!sc->link_active) { 994 ifmr->ifm_active |= IFM_NONE; 995 return; 996 } 997 998 ifmr->ifm_status |= IFM_ACTIVE; 999 1000 if (sc->hw.media_type == em_media_type_fiber || 1001 sc->hw.media_type == em_media_type_internal_serdes) { 1002 if (sc->hw.mac_type == em_82545) 1003 fiber_type = IFM_1000_LX; 1004 ifmr->ifm_active |= fiber_type | IFM_FDX; 1005 } else { 1006 switch (sc->link_speed) { 1007 case 10: 1008 ifmr->ifm_active |= IFM_10_T; 1009 break; 1010 case 100: 1011 ifmr->ifm_active |= IFM_100_TX; 1012 break; 1013 case 1000: 1014 ifmr->ifm_active |= IFM_1000_T; 1015 break; 1016 } 1017 1018 if (sc->link_duplex == FULL_DUPLEX) 1019 ifmr->ifm_active |= em_flowstatus(sc) | IFM_FDX; 1020 else 1021 ifmr->ifm_active |= IFM_HDX; 1022 1023 if (IFM_SUBTYPE(ifmr->ifm_active) == IFM_1000_T) { 1024 em_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &gsr); 1025 if (gsr & SR_1000T_MS_CONFIG_RES) 1026 ifmr->ifm_active |= IFM_ETH_MASTER; 1027 } 1028 } 1029 } 1030 1031 /********************************************************************* 1032 * 1033 * Media Ioctl callback 1034 * 1035 * This routine is called when the user changes speed/duplex using 1036 * media/mediopt option with ifconfig. 1037 * 1038 **********************************************************************/ 1039 int 1040 em_media_change(struct ifnet *ifp) 1041 { 1042 struct em_softc *sc = ifp->if_softc; 1043 struct ifmedia *ifm = &sc->media; 1044 1045 INIT_DEBUGOUT("em_media_change: begin"); 1046 1047 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1048 return (EINVAL); 1049 1050 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1051 case IFM_AUTO: 1052 sc->hw.autoneg = DO_AUTO_NEG; 1053 sc->hw.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1054 break; 1055 case IFM_1000_LX: 1056 case IFM_1000_SX: 1057 case IFM_1000_T: 1058 sc->hw.autoneg = DO_AUTO_NEG; 1059 sc->hw.autoneg_advertised = ADVERTISE_1000_FULL; 1060 break; 1061 case IFM_100_TX: 1062 sc->hw.autoneg = FALSE; 1063 sc->hw.autoneg_advertised = 0; 1064 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1065 sc->hw.forced_speed_duplex = em_100_full; 1066 else 1067 sc->hw.forced_speed_duplex = em_100_half; 1068 break; 1069 case IFM_10_T: 1070 sc->hw.autoneg = FALSE; 1071 sc->hw.autoneg_advertised = 0; 1072 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1073 sc->hw.forced_speed_duplex = em_10_full; 1074 else 1075 sc->hw.forced_speed_duplex = em_10_half; 1076 break; 1077 default: 1078 printf("%s: Unsupported media type\n", DEVNAME(sc)); 1079 } 1080 1081 /* 1082 * As the speed/duplex settings may have changed we need to 1083 * reset the PHY. 1084 */ 1085 sc->hw.phy_reset_disable = FALSE; 1086 1087 em_init(sc); 1088 1089 return (0); 1090 } 1091 1092 uint64_t 1093 em_flowstatus(struct em_softc *sc) 1094 { 1095 u_int16_t ar, lpar; 1096 1097 if (sc->hw.media_type == em_media_type_fiber || 1098 sc->hw.media_type == em_media_type_internal_serdes) 1099 return (0); 1100 1101 em_read_phy_reg(&sc->hw, PHY_AUTONEG_ADV, &ar); 1102 em_read_phy_reg(&sc->hw, PHY_LP_ABILITY, &lpar); 1103 1104 if ((ar & NWAY_AR_PAUSE) && (lpar & NWAY_LPAR_PAUSE)) 1105 return (IFM_FLOW|IFM_ETH_TXPAUSE|IFM_ETH_RXPAUSE); 1106 else if (!(ar & NWAY_AR_PAUSE) && (ar & NWAY_AR_ASM_DIR) && 1107 (lpar & NWAY_LPAR_PAUSE) && (lpar & NWAY_LPAR_ASM_DIR)) 1108 return (IFM_FLOW|IFM_ETH_TXPAUSE); 1109 else if ((ar & NWAY_AR_PAUSE) && (ar & NWAY_AR_ASM_DIR) && 1110 !(lpar & NWAY_LPAR_PAUSE) && (lpar & NWAY_LPAR_ASM_DIR)) 1111 return (IFM_FLOW|IFM_ETH_RXPAUSE); 1112 1113 return (0); 1114 } 1115 1116 /********************************************************************* 1117 * 1118 * This routine maps the mbufs to tx descriptors. 1119 * 1120 * return 0 on success, positive on failure 1121 **********************************************************************/ 1122 u_int 1123 em_encap(struct em_softc *sc, struct mbuf *m) 1124 { 1125 struct em_packet *pkt; 1126 struct em_tx_desc *desc; 1127 bus_dmamap_t map; 1128 u_int32_t txd_upper, txd_lower; 1129 u_int head, last, used = 0; 1130 int i, j; 1131 1132 /* For 82544 Workaround */ 1133 DESC_ARRAY desc_array; 1134 u_int32_t array_elements; 1135 1136 /* get a dmamap for this packet from the next free slot */ 1137 head = sc->sc_tx_desc_head; 1138 pkt = &sc->sc_tx_pkts_ring[head]; 1139 map = pkt->pkt_map; 1140 1141 switch (bus_dmamap_load_mbuf(sc->sc_dmat, map, m, BUS_DMA_NOWAIT)) { 1142 case 0: 1143 break; 1144 case EFBIG: 1145 if (m_defrag(m, M_DONTWAIT) == 0 && 1146 bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1147 BUS_DMA_NOWAIT) == 0) 1148 break; 1149 1150 /* FALLTHROUGH */ 1151 default: 1152 sc->no_tx_dma_setup++; 1153 return (0); 1154 } 1155 1156 bus_dmamap_sync(sc->sc_dmat, map, 1157 0, map->dm_mapsize, 1158 BUS_DMASYNC_PREWRITE); 1159 1160 if (sc->hw.mac_type == em_82547) { 1161 bus_dmamap_sync(sc->sc_dmat, sc->sc_tx_dma.dma_map, 1162 0, sc->sc_tx_dma.dma_map->dm_mapsize, 1163 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1164 } 1165 1166 if (sc->hw.mac_type >= em_82543 && sc->hw.mac_type != em_82575 && 1167 sc->hw.mac_type != em_82580 && sc->hw.mac_type != em_i210 && 1168 sc->hw.mac_type != em_i350) { 1169 used += em_transmit_checksum_setup(sc, m, head, 1170 &txd_upper, &txd_lower); 1171 } else { 1172 txd_upper = txd_lower = 0; 1173 } 1174 1175 head += used; 1176 if (head >= sc->sc_tx_slots) 1177 head -= sc->sc_tx_slots; 1178 1179 for (i = 0; i < map->dm_nsegs; i++) { 1180 /* If sc is 82544 and on PCI-X bus */ 1181 if (sc->pcix_82544) { 1182 /* 1183 * Check the Address and Length combination and 1184 * split the data accordingly 1185 */ 1186 array_elements = em_fill_descriptors( 1187 map->dm_segs[i].ds_addr, map->dm_segs[i].ds_len, 1188 &desc_array); 1189 for (j = 0; j < array_elements; j++) { 1190 desc = &sc->sc_tx_desc_ring[head]; 1191 1192 desc->buffer_addr = htole64( 1193 desc_array.descriptor[j].address); 1194 desc->lower.data = htole32( 1195 (sc->sc_txd_cmd | txd_lower | 1196 (u_int16_t)desc_array.descriptor[j].length)); 1197 desc->upper.data = htole32(txd_upper); 1198 1199 last = head; 1200 if (++head == sc->sc_tx_slots) 1201 head = 0; 1202 1203 used++; 1204 } 1205 } else { 1206 desc = &sc->sc_tx_desc_ring[head]; 1207 1208 desc->buffer_addr = htole64(map->dm_segs[i].ds_addr); 1209 desc->lower.data = htole32(sc->sc_txd_cmd | 1210 txd_lower | map->dm_segs[i].ds_len); 1211 desc->upper.data = htole32(txd_upper); 1212 1213 last = head; 1214 if (++head == sc->sc_tx_slots) 1215 head = 0; 1216 1217 used++; 1218 } 1219 } 1220 1221 #if NVLAN > 0 1222 /* Find out if we are in VLAN mode */ 1223 if (m->m_flags & M_VLANTAG) { 1224 /* Set the VLAN id */ 1225 desc->upper.fields.special = htole16(m->m_pkthdr.ether_vtag); 1226 1227 /* Tell hardware to add tag */ 1228 desc->lower.data |= htole32(E1000_TXD_CMD_VLE); 1229 } 1230 #endif 1231 1232 /* mark the packet with the mbuf and last desc slot */ 1233 pkt->pkt_m = m; 1234 pkt->pkt_eop = last; 1235 1236 sc->sc_tx_desc_head = head; 1237 1238 /* 1239 * Last Descriptor of Packet 1240 * needs End Of Packet (EOP) 1241 * and Report Status (RS) 1242 */ 1243 desc->lower.data |= htole32(E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS); 1244 1245 if (sc->hw.mac_type == em_82547) { 1246 bus_dmamap_sync(sc->sc_dmat, sc->sc_tx_dma.dma_map, 1247 0, sc->sc_tx_dma.dma_map->dm_mapsize, 1248 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1249 } 1250 1251 return (used); 1252 } 1253 1254 /********************************************************************* 1255 * 1256 * 82547 workaround to avoid controller hang in half-duplex environment. 1257 * The workaround is to avoid queuing a large packet that would span 1258 * the internal Tx FIFO ring boundary. We need to reset the FIFO pointers 1259 * in this case. We do that only when FIFO is quiescent. 1260 * 1261 **********************************************************************/ 1262 void 1263 em_82547_move_tail_locked(struct em_softc *sc) 1264 { 1265 uint16_t hw_tdt; 1266 uint16_t sw_tdt; 1267 struct em_tx_desc *tx_desc; 1268 uint16_t length = 0; 1269 boolean_t eop = 0; 1270 1271 hw_tdt = E1000_READ_REG(&sc->hw, TDT); 1272 sw_tdt = sc->sc_tx_desc_head; 1273 1274 while (hw_tdt != sw_tdt) { 1275 tx_desc = &sc->sc_tx_desc_ring[hw_tdt]; 1276 length += tx_desc->lower.flags.length; 1277 eop = tx_desc->lower.data & E1000_TXD_CMD_EOP; 1278 if (++hw_tdt == sc->sc_tx_slots) 1279 hw_tdt = 0; 1280 1281 if (eop) { 1282 if (em_82547_fifo_workaround(sc, length)) { 1283 sc->tx_fifo_wrk_cnt++; 1284 timeout_add(&sc->tx_fifo_timer_handle, 1); 1285 break; 1286 } 1287 E1000_WRITE_REG(&sc->hw, TDT, hw_tdt); 1288 em_82547_update_fifo_head(sc, length); 1289 length = 0; 1290 } 1291 } 1292 } 1293 1294 void 1295 em_82547_move_tail(void *arg) 1296 { 1297 struct em_softc *sc = arg; 1298 int s; 1299 1300 s = splnet(); 1301 em_82547_move_tail_locked(sc); 1302 splx(s); 1303 } 1304 1305 int 1306 em_82547_fifo_workaround(struct em_softc *sc, int len) 1307 { 1308 int fifo_space, fifo_pkt_len; 1309 1310 fifo_pkt_len = EM_ROUNDUP(len + EM_FIFO_HDR, EM_FIFO_HDR); 1311 1312 if (sc->link_duplex == HALF_DUPLEX) { 1313 fifo_space = sc->tx_fifo_size - sc->tx_fifo_head; 1314 1315 if (fifo_pkt_len >= (EM_82547_PKT_THRESH + fifo_space)) { 1316 if (em_82547_tx_fifo_reset(sc)) 1317 return (0); 1318 else 1319 return (1); 1320 } 1321 } 1322 1323 return (0); 1324 } 1325 1326 void 1327 em_82547_update_fifo_head(struct em_softc *sc, int len) 1328 { 1329 int fifo_pkt_len = EM_ROUNDUP(len + EM_FIFO_HDR, EM_FIFO_HDR); 1330 1331 /* tx_fifo_head is always 16 byte aligned */ 1332 sc->tx_fifo_head += fifo_pkt_len; 1333 if (sc->tx_fifo_head >= sc->tx_fifo_size) 1334 sc->tx_fifo_head -= sc->tx_fifo_size; 1335 } 1336 1337 int 1338 em_82547_tx_fifo_reset(struct em_softc *sc) 1339 { 1340 uint32_t tctl; 1341 1342 if ((E1000_READ_REG(&sc->hw, TDT) == 1343 E1000_READ_REG(&sc->hw, TDH)) && 1344 (E1000_READ_REG(&sc->hw, TDFT) == 1345 E1000_READ_REG(&sc->hw, TDFH)) && 1346 (E1000_READ_REG(&sc->hw, TDFTS) == 1347 E1000_READ_REG(&sc->hw, TDFHS)) && 1348 (E1000_READ_REG(&sc->hw, TDFPC) == 0)) { 1349 1350 /* Disable TX unit */ 1351 tctl = E1000_READ_REG(&sc->hw, TCTL); 1352 E1000_WRITE_REG(&sc->hw, TCTL, tctl & ~E1000_TCTL_EN); 1353 1354 /* Reset FIFO pointers */ 1355 E1000_WRITE_REG(&sc->hw, TDFT, sc->tx_head_addr); 1356 E1000_WRITE_REG(&sc->hw, TDFH, sc->tx_head_addr); 1357 E1000_WRITE_REG(&sc->hw, TDFTS, sc->tx_head_addr); 1358 E1000_WRITE_REG(&sc->hw, TDFHS, sc->tx_head_addr); 1359 1360 /* Re-enable TX unit */ 1361 E1000_WRITE_REG(&sc->hw, TCTL, tctl); 1362 E1000_WRITE_FLUSH(&sc->hw); 1363 1364 sc->tx_fifo_head = 0; 1365 sc->tx_fifo_reset_cnt++; 1366 1367 return (TRUE); 1368 } else 1369 return (FALSE); 1370 } 1371 1372 void 1373 em_iff(struct em_softc *sc) 1374 { 1375 struct ifnet *ifp = &sc->sc_ac.ac_if; 1376 struct arpcom *ac = &sc->sc_ac; 1377 u_int32_t reg_rctl = 0; 1378 u_int8_t mta[MAX_NUM_MULTICAST_ADDRESSES * ETH_LENGTH_OF_ADDRESS]; 1379 struct ether_multi *enm; 1380 struct ether_multistep step; 1381 int i = 0; 1382 1383 IOCTL_DEBUGOUT("em_iff: begin"); 1384 1385 if (sc->hw.mac_type == em_82542_rev2_0) { 1386 reg_rctl = E1000_READ_REG(&sc->hw, RCTL); 1387 if (sc->hw.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1388 em_pci_clear_mwi(&sc->hw); 1389 reg_rctl |= E1000_RCTL_RST; 1390 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 1391 msec_delay(5); 1392 } 1393 1394 reg_rctl = E1000_READ_REG(&sc->hw, RCTL); 1395 reg_rctl &= ~(E1000_RCTL_MPE | E1000_RCTL_UPE); 1396 ifp->if_flags &= ~IFF_ALLMULTI; 1397 1398 if (ifp->if_flags & IFF_PROMISC || ac->ac_multirangecnt > 0 || 1399 ac->ac_multicnt > MAX_NUM_MULTICAST_ADDRESSES) { 1400 ifp->if_flags |= IFF_ALLMULTI; 1401 reg_rctl |= E1000_RCTL_MPE; 1402 if (ifp->if_flags & IFF_PROMISC) 1403 reg_rctl |= E1000_RCTL_UPE; 1404 } else { 1405 ETHER_FIRST_MULTI(step, ac, enm); 1406 while (enm != NULL) { 1407 bcopy(enm->enm_addrlo, mta + i, ETH_LENGTH_OF_ADDRESS); 1408 i += ETH_LENGTH_OF_ADDRESS; 1409 1410 ETHER_NEXT_MULTI(step, enm); 1411 } 1412 1413 em_mc_addr_list_update(&sc->hw, mta, ac->ac_multicnt, 0, 1); 1414 } 1415 1416 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 1417 1418 if (sc->hw.mac_type == em_82542_rev2_0) { 1419 reg_rctl = E1000_READ_REG(&sc->hw, RCTL); 1420 reg_rctl &= ~E1000_RCTL_RST; 1421 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 1422 msec_delay(5); 1423 if (sc->hw.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1424 em_pci_set_mwi(&sc->hw); 1425 } 1426 } 1427 1428 /********************************************************************* 1429 * Timer routine 1430 * 1431 * This routine checks for link status and updates statistics. 1432 * 1433 **********************************************************************/ 1434 1435 void 1436 em_local_timer(void *arg) 1437 { 1438 struct ifnet *ifp; 1439 struct em_softc *sc = arg; 1440 int s; 1441 1442 ifp = &sc->sc_ac.ac_if; 1443 1444 s = splnet(); 1445 1446 #ifndef SMALL_KERNEL 1447 em_update_stats_counters(sc); 1448 #ifdef EM_DEBUG 1449 if (ifp->if_flags & IFF_DEBUG && ifp->if_flags & IFF_RUNNING) 1450 em_print_hw_stats(sc); 1451 #endif 1452 #endif 1453 em_smartspeed(sc); 1454 1455 timeout_add_sec(&sc->timer_handle, 1); 1456 1457 splx(s); 1458 } 1459 1460 void 1461 em_update_link_status(struct em_softc *sc) 1462 { 1463 struct ifnet *ifp = &sc->sc_ac.ac_if; 1464 u_char link_state; 1465 1466 if (E1000_READ_REG(&sc->hw, STATUS) & E1000_STATUS_LU) { 1467 if (sc->link_active == 0) { 1468 em_get_speed_and_duplex(&sc->hw, 1469 &sc->link_speed, 1470 &sc->link_duplex); 1471 /* Check if we may set SPEED_MODE bit on PCI-E */ 1472 if ((sc->link_speed == SPEED_1000) && 1473 ((sc->hw.mac_type == em_82571) || 1474 (sc->hw.mac_type == em_82572) || 1475 (sc->hw.mac_type == em_82575) || 1476 (sc->hw.mac_type == em_82580))) { 1477 int tarc0; 1478 1479 tarc0 = E1000_READ_REG(&sc->hw, TARC0); 1480 tarc0 |= SPEED_MODE_BIT; 1481 E1000_WRITE_REG(&sc->hw, TARC0, tarc0); 1482 } 1483 sc->link_active = 1; 1484 sc->smartspeed = 0; 1485 ifp->if_baudrate = IF_Mbps(sc->link_speed); 1486 } 1487 link_state = (sc->link_duplex == FULL_DUPLEX) ? 1488 LINK_STATE_FULL_DUPLEX : LINK_STATE_HALF_DUPLEX; 1489 if (ifp->if_link_state != link_state) { 1490 ifp->if_link_state = link_state; 1491 if_link_state_change(ifp); 1492 } 1493 } else { 1494 if (sc->link_active == 1) { 1495 ifp->if_baudrate = sc->link_speed = 0; 1496 sc->link_duplex = 0; 1497 sc->link_active = 0; 1498 } 1499 if (ifp->if_link_state != LINK_STATE_DOWN) { 1500 ifp->if_link_state = LINK_STATE_DOWN; 1501 if_link_state_change(ifp); 1502 } 1503 } 1504 } 1505 1506 /********************************************************************* 1507 * 1508 * This routine disables all traffic on the adapter by issuing a 1509 * global reset on the MAC and deallocates TX/RX buffers. 1510 * 1511 **********************************************************************/ 1512 1513 void 1514 em_stop(void *arg, int softonly) 1515 { 1516 struct em_softc *sc = arg; 1517 struct ifnet *ifp = &sc->sc_ac.ac_if; 1518 1519 /* Tell the stack that the interface is no longer active */ 1520 ifp->if_flags &= ~IFF_RUNNING; 1521 1522 INIT_DEBUGOUT("em_stop: begin"); 1523 1524 timeout_del(&sc->timer_handle); 1525 timeout_del(&sc->tx_fifo_timer_handle); 1526 1527 if (!softonly) 1528 em_disable_intr(sc); 1529 if (sc->hw.mac_type == em_pch_spt) 1530 em_flush_desc_rings(sc); 1531 if (!softonly) 1532 em_reset_hw(&sc->hw); 1533 1534 intr_barrier(sc->sc_intrhand); 1535 ifq_barrier(&ifp->if_snd); 1536 1537 KASSERT((ifp->if_flags & IFF_RUNNING) == 0); 1538 1539 ifq_clr_oactive(&ifp->if_snd); 1540 ifp->if_timer = 0; 1541 1542 em_free_transmit_structures(sc); 1543 em_free_receive_structures(sc); 1544 } 1545 1546 /********************************************************************* 1547 * 1548 * Determine hardware revision. 1549 * 1550 **********************************************************************/ 1551 void 1552 em_identify_hardware(struct em_softc *sc) 1553 { 1554 u_int32_t reg; 1555 struct pci_attach_args *pa = &sc->osdep.em_pa; 1556 1557 /* Make sure our PCI config space has the necessary stuff set */ 1558 sc->hw.pci_cmd_word = pci_conf_read(pa->pa_pc, pa->pa_tag, 1559 PCI_COMMAND_STATUS_REG); 1560 1561 /* Save off the information about this board */ 1562 sc->hw.vendor_id = PCI_VENDOR(pa->pa_id); 1563 sc->hw.device_id = PCI_PRODUCT(pa->pa_id); 1564 1565 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG); 1566 sc->hw.revision_id = PCI_REVISION(reg); 1567 1568 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 1569 sc->hw.subsystem_vendor_id = PCI_VENDOR(reg); 1570 sc->hw.subsystem_id = PCI_PRODUCT(reg); 1571 1572 /* Identify the MAC */ 1573 if (em_set_mac_type(&sc->hw)) 1574 printf("%s: Unknown MAC Type\n", DEVNAME(sc)); 1575 1576 if (sc->hw.mac_type == em_pchlan) 1577 sc->hw.revision_id = PCI_PRODUCT(pa->pa_id) & 0x0f; 1578 1579 if (sc->hw.mac_type == em_82541 || 1580 sc->hw.mac_type == em_82541_rev_2 || 1581 sc->hw.mac_type == em_82547 || 1582 sc->hw.mac_type == em_82547_rev_2) 1583 sc->hw.phy_init_script = TRUE; 1584 } 1585 1586 void 1587 em_legacy_irq_quirk_spt(struct em_softc *sc) 1588 { 1589 uint32_t reg; 1590 1591 /* Legacy interrupt: SPT needs a quirk. */ 1592 if (sc->hw.mac_type != em_pch_spt) 1593 return; 1594 if (sc->legacy_irq == 0) 1595 return; 1596 1597 reg = EM_READ_REG(&sc->hw, E1000_FEXTNVM7); 1598 reg |= E1000_FEXTNVM7_SIDE_CLK_UNGATE; 1599 EM_WRITE_REG(&sc->hw, E1000_FEXTNVM7, reg); 1600 1601 reg = EM_READ_REG(&sc->hw, E1000_FEXTNVM9); 1602 reg |= E1000_FEXTNVM9_IOSFSB_CLKGATE_DIS | 1603 E1000_FEXTNVM9_IOSFSB_CLKREQ_DIS; 1604 EM_WRITE_REG(&sc->hw, E1000_FEXTNVM9, reg); 1605 } 1606 1607 int 1608 em_allocate_pci_resources(struct em_softc *sc) 1609 { 1610 int val, rid; 1611 pci_intr_handle_t ih; 1612 const char *intrstr = NULL; 1613 struct pci_attach_args *pa = &sc->osdep.em_pa; 1614 pci_chipset_tag_t pc = pa->pa_pc; 1615 1616 val = pci_conf_read(pa->pa_pc, pa->pa_tag, EM_MMBA); 1617 if (PCI_MAPREG_TYPE(val) != PCI_MAPREG_TYPE_MEM) { 1618 printf(": mmba is not mem space\n"); 1619 return (ENXIO); 1620 } 1621 if (pci_mapreg_map(pa, EM_MMBA, PCI_MAPREG_MEM_TYPE(val), 0, 1622 &sc->osdep.mem_bus_space_tag, &sc->osdep.mem_bus_space_handle, 1623 &sc->osdep.em_membase, &sc->osdep.em_memsize, 0)) { 1624 printf(": cannot find mem space\n"); 1625 return (ENXIO); 1626 } 1627 1628 switch (sc->hw.mac_type) { 1629 case em_82544: 1630 case em_82540: 1631 case em_82545: 1632 case em_82546: 1633 case em_82541: 1634 case em_82541_rev_2: 1635 /* Figure out where our I/O BAR is ? */ 1636 for (rid = PCI_MAPREG_START; rid < PCI_MAPREG_END;) { 1637 val = pci_conf_read(pa->pa_pc, pa->pa_tag, rid); 1638 if (PCI_MAPREG_TYPE(val) == PCI_MAPREG_TYPE_IO) { 1639 sc->io_rid = rid; 1640 break; 1641 } 1642 rid += 4; 1643 if (PCI_MAPREG_MEM_TYPE(val) == 1644 PCI_MAPREG_MEM_TYPE_64BIT) 1645 rid += 4; /* skip high bits, too */ 1646 } 1647 1648 if (pci_mapreg_map(pa, rid, PCI_MAPREG_TYPE_IO, 0, 1649 &sc->osdep.io_bus_space_tag, &sc->osdep.io_bus_space_handle, 1650 &sc->osdep.em_iobase, &sc->osdep.em_iosize, 0)) { 1651 printf(": cannot find i/o space\n"); 1652 return (ENXIO); 1653 } 1654 1655 sc->hw.io_base = 0; 1656 break; 1657 default: 1658 break; 1659 } 1660 1661 sc->osdep.em_flashoffset = 0; 1662 /* for ICH8 and family we need to find the flash memory */ 1663 if (sc->hw.mac_type == em_pch_spt) { 1664 sc->osdep.flash_bus_space_tag = sc->osdep.mem_bus_space_tag; 1665 sc->osdep.flash_bus_space_handle = sc->osdep.mem_bus_space_handle; 1666 sc->osdep.em_flashbase = 0; 1667 sc->osdep.em_flashsize = 0; 1668 sc->osdep.em_flashoffset = 0xe000; 1669 } else if (IS_ICH8(sc->hw.mac_type)) { 1670 val = pci_conf_read(pa->pa_pc, pa->pa_tag, EM_FLASH); 1671 if (PCI_MAPREG_TYPE(val) != PCI_MAPREG_TYPE_MEM) { 1672 printf(": flash is not mem space\n"); 1673 return (ENXIO); 1674 } 1675 1676 if (pci_mapreg_map(pa, EM_FLASH, PCI_MAPREG_MEM_TYPE(val), 0, 1677 &sc->osdep.flash_bus_space_tag, &sc->osdep.flash_bus_space_handle, 1678 &sc->osdep.em_flashbase, &sc->osdep.em_flashsize, 0)) { 1679 printf(": cannot find mem space\n"); 1680 return (ENXIO); 1681 } 1682 } 1683 1684 sc->legacy_irq = 0; 1685 if (pci_intr_map_msi(pa, &ih)) { 1686 if (pci_intr_map(pa, &ih)) { 1687 printf(": couldn't map interrupt\n"); 1688 return (ENXIO); 1689 } 1690 sc->legacy_irq = 1; 1691 } 1692 1693 sc->osdep.dev = (struct device *)sc; 1694 sc->hw.back = &sc->osdep; 1695 1696 intrstr = pci_intr_string(pc, ih); 1697 sc->sc_intrhand = pci_intr_establish(pc, ih, IPL_NET | IPL_MPSAFE, 1698 em_intr, sc, DEVNAME(sc)); 1699 if (sc->sc_intrhand == NULL) { 1700 printf(": couldn't establish interrupt"); 1701 if (intrstr != NULL) 1702 printf(" at %s", intrstr); 1703 printf("\n"); 1704 return (ENXIO); 1705 } 1706 printf(": %s", intrstr); 1707 1708 /* 1709 * the ICP_xxxx device has multiple, duplicate register sets for 1710 * use when it is being used as a network processor. Disable those 1711 * registers here, as they are not necessary in this context and 1712 * can confuse the system 1713 */ 1714 if(sc->hw.mac_type == em_icp_xxxx) { 1715 int offset; 1716 pcireg_t val; 1717 1718 if (!pci_get_capability(sc->osdep.em_pa.pa_pc, 1719 sc->osdep.em_pa.pa_tag, PCI_CAP_ID_ST, &offset, &val)) { 1720 return (0); 1721 } 1722 offset += PCI_ST_SMIA_OFFSET; 1723 pci_conf_write(sc->osdep.em_pa.pa_pc, sc->osdep.em_pa.pa_tag, 1724 offset, 0x06); 1725 E1000_WRITE_REG(&sc->hw, IMC1, ~0x0); 1726 E1000_WRITE_REG(&sc->hw, IMC2, ~0x0); 1727 } 1728 return (0); 1729 } 1730 1731 void 1732 em_free_pci_resources(struct em_softc *sc) 1733 { 1734 struct pci_attach_args *pa = &sc->osdep.em_pa; 1735 pci_chipset_tag_t pc = pa->pa_pc; 1736 1737 if (sc->sc_intrhand) 1738 pci_intr_disestablish(pc, sc->sc_intrhand); 1739 sc->sc_intrhand = 0; 1740 1741 if (sc->osdep.em_flashbase) 1742 bus_space_unmap(sc->osdep.flash_bus_space_tag, sc->osdep.flash_bus_space_handle, 1743 sc->osdep.em_flashsize); 1744 sc->osdep.em_flashbase = 0; 1745 1746 if (sc->osdep.em_iobase) 1747 bus_space_unmap(sc->osdep.io_bus_space_tag, sc->osdep.io_bus_space_handle, 1748 sc->osdep.em_iosize); 1749 sc->osdep.em_iobase = 0; 1750 1751 if (sc->osdep.em_membase) 1752 bus_space_unmap(sc->osdep.mem_bus_space_tag, sc->osdep.mem_bus_space_handle, 1753 sc->osdep.em_memsize); 1754 sc->osdep.em_membase = 0; 1755 } 1756 1757 /********************************************************************* 1758 * 1759 * Initialize the hardware to a configuration as specified by the 1760 * em_softc structure. The controller is reset, the EEPROM is 1761 * verified, the MAC address is set, then the shared initialization 1762 * routines are called. 1763 * 1764 **********************************************************************/ 1765 int 1766 em_hardware_init(struct em_softc *sc) 1767 { 1768 uint32_t ret_val; 1769 u_int16_t rx_buffer_size; 1770 1771 INIT_DEBUGOUT("em_hardware_init: begin"); 1772 if (sc->hw.mac_type == em_pch_spt) 1773 em_flush_desc_rings(sc); 1774 /* Issue a global reset */ 1775 em_reset_hw(&sc->hw); 1776 1777 /* When hardware is reset, fifo_head is also reset */ 1778 sc->tx_fifo_head = 0; 1779 1780 /* Make sure we have a good EEPROM before we read from it */ 1781 if (em_get_flash_presence_i210(&sc->hw) && 1782 em_validate_eeprom_checksum(&sc->hw) < 0) { 1783 /* 1784 * Some PCIe parts fail the first check due to 1785 * the link being in sleep state, call it again, 1786 * if it fails a second time its a real issue. 1787 */ 1788 if (em_validate_eeprom_checksum(&sc->hw) < 0) { 1789 printf("%s: The EEPROM Checksum Is Not Valid\n", 1790 DEVNAME(sc)); 1791 return (EIO); 1792 } 1793 } 1794 1795 if (em_get_flash_presence_i210(&sc->hw) && 1796 em_read_part_num(&sc->hw, &(sc->part_num)) < 0) { 1797 printf("%s: EEPROM read error while reading part number\n", 1798 DEVNAME(sc)); 1799 return (EIO); 1800 } 1801 1802 /* Set up smart power down as default off on newer adapters */ 1803 if (!em_smart_pwr_down && 1804 (sc->hw.mac_type == em_82571 || 1805 sc->hw.mac_type == em_82572 || 1806 sc->hw.mac_type == em_82575 || 1807 sc->hw.mac_type == em_82580 || 1808 sc->hw.mac_type == em_i210 || 1809 sc->hw.mac_type == em_i350 )) { 1810 uint16_t phy_tmp = 0; 1811 1812 /* Speed up time to link by disabling smart power down */ 1813 em_read_phy_reg(&sc->hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 1814 phy_tmp &= ~IGP02E1000_PM_SPD; 1815 em_write_phy_reg(&sc->hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp); 1816 } 1817 1818 em_legacy_irq_quirk_spt(sc); 1819 1820 /* 1821 * These parameters control the automatic generation (Tx) and 1822 * response (Rx) to Ethernet PAUSE frames. 1823 * - High water mark should allow for at least two frames to be 1824 * received after sending an XOFF. 1825 * - Low water mark works best when it is very near the high water mark. 1826 * This allows the receiver to restart by sending XON when it has 1827 * drained a bit. Here we use an arbitary value of 1500 which will 1828 * restart after one full frame is pulled from the buffer. There 1829 * could be several smaller frames in the buffer and if so they will 1830 * not trigger the XON until their total number reduces the buffer 1831 * by 1500. 1832 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 1833 */ 1834 rx_buffer_size = ((E1000_READ_REG(&sc->hw, PBA) & 0xffff) << 10 ); 1835 1836 sc->hw.fc_high_water = rx_buffer_size - 1837 EM_ROUNDUP(sc->hw.max_frame_size, 1024); 1838 sc->hw.fc_low_water = sc->hw.fc_high_water - 1500; 1839 if (sc->hw.mac_type == em_80003es2lan) 1840 sc->hw.fc_pause_time = 0xFFFF; 1841 else 1842 sc->hw.fc_pause_time = 1000; 1843 sc->hw.fc_send_xon = TRUE; 1844 sc->hw.fc = E1000_FC_FULL; 1845 1846 em_disable_aspm(sc); 1847 1848 if ((ret_val = em_init_hw(&sc->hw)) != 0) { 1849 if (ret_val == E1000_DEFER_INIT) { 1850 INIT_DEBUGOUT("\nHardware Initialization Deferred "); 1851 return (EAGAIN); 1852 } 1853 printf("\n%s: Hardware Initialization Failed\n", 1854 DEVNAME(sc)); 1855 return (EIO); 1856 } 1857 1858 em_check_for_link(&sc->hw); 1859 1860 return (0); 1861 } 1862 1863 /********************************************************************* 1864 * 1865 * Setup networking device structure and register an interface. 1866 * 1867 **********************************************************************/ 1868 void 1869 em_setup_interface(struct em_softc *sc) 1870 { 1871 struct ifnet *ifp; 1872 uint64_t fiber_type = IFM_1000_SX; 1873 1874 INIT_DEBUGOUT("em_setup_interface: begin"); 1875 1876 ifp = &sc->sc_ac.ac_if; 1877 strlcpy(ifp->if_xname, DEVNAME(sc), IFNAMSIZ); 1878 ifp->if_softc = sc; 1879 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1880 ifp->if_xflags = IFXF_MPSAFE; 1881 ifp->if_ioctl = em_ioctl; 1882 ifp->if_qstart = em_start; 1883 ifp->if_watchdog = em_watchdog; 1884 ifp->if_hardmtu = 1885 sc->hw.max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN; 1886 IFQ_SET_MAXLEN(&ifp->if_snd, sc->sc_tx_slots - 1); 1887 1888 ifp->if_capabilities = IFCAP_VLAN_MTU; 1889 1890 #if NVLAN > 0 1891 if (sc->hw.mac_type != em_82575 && sc->hw.mac_type != em_82580 && 1892 sc->hw.mac_type != em_i210 && sc->hw.mac_type != em_i350) 1893 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 1894 #endif 1895 1896 if (sc->hw.mac_type >= em_82543 && sc->hw.mac_type != em_82575 && 1897 sc->hw.mac_type != em_82580 && sc->hw.mac_type != em_i210 && 1898 sc->hw.mac_type != em_i350) 1899 ifp->if_capabilities |= IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 1900 1901 /* 1902 * Specify the media types supported by this adapter and register 1903 * callbacks to update media and link information 1904 */ 1905 ifmedia_init(&sc->media, IFM_IMASK, em_media_change, 1906 em_media_status); 1907 if (sc->hw.media_type == em_media_type_fiber || 1908 sc->hw.media_type == em_media_type_internal_serdes) { 1909 if (sc->hw.mac_type == em_82545) 1910 fiber_type = IFM_1000_LX; 1911 ifmedia_add(&sc->media, IFM_ETHER | fiber_type | IFM_FDX, 1912 0, NULL); 1913 ifmedia_add(&sc->media, IFM_ETHER | fiber_type, 1914 0, NULL); 1915 } else { 1916 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL); 1917 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX, 1918 0, NULL); 1919 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 1920 0, NULL); 1921 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 1922 0, NULL); 1923 if (sc->hw.phy_type != em_phy_ife) { 1924 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 1925 0, NULL); 1926 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_T, 0, NULL); 1927 } 1928 } 1929 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL); 1930 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO); 1931 1932 if_attach(ifp); 1933 ether_ifattach(ifp); 1934 } 1935 1936 int 1937 em_detach(struct device *self, int flags) 1938 { 1939 struct em_softc *sc = (struct em_softc *)self; 1940 struct ifnet *ifp = &sc->sc_ac.ac_if; 1941 struct pci_attach_args *pa = &sc->osdep.em_pa; 1942 pci_chipset_tag_t pc = pa->pa_pc; 1943 1944 if (sc->sc_intrhand) 1945 pci_intr_disestablish(pc, sc->sc_intrhand); 1946 sc->sc_intrhand = 0; 1947 1948 em_stop(sc, 1); 1949 1950 em_free_pci_resources(sc); 1951 1952 if (sc->sc_rx_desc_ring != NULL) { 1953 sc->sc_rx_desc_ring = NULL; 1954 em_dma_free(sc, &sc->sc_rx_dma); 1955 } 1956 if (sc->sc_tx_desc_ring != NULL) { 1957 sc->sc_tx_desc_ring = NULL; 1958 em_dma_free(sc, &sc->sc_tx_dma); 1959 } 1960 1961 ether_ifdetach(ifp); 1962 if_detach(ifp); 1963 1964 return (0); 1965 } 1966 1967 int 1968 em_activate(struct device *self, int act) 1969 { 1970 struct em_softc *sc = (struct em_softc *)self; 1971 struct ifnet *ifp = &sc->sc_ac.ac_if; 1972 int rv = 0; 1973 1974 switch (act) { 1975 case DVACT_SUSPEND: 1976 if (ifp->if_flags & IFF_RUNNING) 1977 em_stop(sc, 0); 1978 /* We have no children atm, but we will soon */ 1979 rv = config_activate_children(self, act); 1980 break; 1981 case DVACT_RESUME: 1982 if (ifp->if_flags & IFF_UP) 1983 em_init(sc); 1984 break; 1985 default: 1986 rv = config_activate_children(self, act); 1987 break; 1988 } 1989 return (rv); 1990 } 1991 1992 /********************************************************************* 1993 * 1994 * Workaround for SmartSpeed on 82541 and 82547 controllers 1995 * 1996 **********************************************************************/ 1997 void 1998 em_smartspeed(struct em_softc *sc) 1999 { 2000 uint16_t phy_tmp; 2001 2002 if (sc->link_active || (sc->hw.phy_type != em_phy_igp) || 2003 !sc->hw.autoneg || !(sc->hw.autoneg_advertised & ADVERTISE_1000_FULL)) 2004 return; 2005 2006 if (sc->smartspeed == 0) { 2007 /* If Master/Slave config fault is asserted twice, 2008 * we assume back-to-back */ 2009 em_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2010 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2011 return; 2012 em_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2013 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2014 em_read_phy_reg(&sc->hw, PHY_1000T_CTRL, 2015 &phy_tmp); 2016 if (phy_tmp & CR_1000T_MS_ENABLE) { 2017 phy_tmp &= ~CR_1000T_MS_ENABLE; 2018 em_write_phy_reg(&sc->hw, 2019 PHY_1000T_CTRL, phy_tmp); 2020 sc->smartspeed++; 2021 if (sc->hw.autoneg && 2022 !em_phy_setup_autoneg(&sc->hw) && 2023 !em_read_phy_reg(&sc->hw, PHY_CTRL, 2024 &phy_tmp)) { 2025 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2026 MII_CR_RESTART_AUTO_NEG); 2027 em_write_phy_reg(&sc->hw, 2028 PHY_CTRL, phy_tmp); 2029 } 2030 } 2031 } 2032 return; 2033 } else if (sc->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 2034 /* If still no link, perhaps using 2/3 pair cable */ 2035 em_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp); 2036 phy_tmp |= CR_1000T_MS_ENABLE; 2037 em_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp); 2038 if (sc->hw.autoneg && 2039 !em_phy_setup_autoneg(&sc->hw) && 2040 !em_read_phy_reg(&sc->hw, PHY_CTRL, &phy_tmp)) { 2041 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2042 MII_CR_RESTART_AUTO_NEG); 2043 em_write_phy_reg(&sc->hw, PHY_CTRL, phy_tmp); 2044 } 2045 } 2046 /* Restart process after EM_SMARTSPEED_MAX iterations */ 2047 if (sc->smartspeed++ == EM_SMARTSPEED_MAX) 2048 sc->smartspeed = 0; 2049 } 2050 2051 /* 2052 * Manage DMA'able memory. 2053 */ 2054 int 2055 em_dma_malloc(struct em_softc *sc, bus_size_t size, struct em_dma_alloc *dma) 2056 { 2057 int r; 2058 2059 r = bus_dmamap_create(sc->sc_dmat, size, 1, 2060 size, 0, BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, &dma->dma_map); 2061 if (r != 0) 2062 return (r); 2063 2064 r = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, &dma->dma_seg, 2065 1, &dma->dma_nseg, BUS_DMA_WAITOK | BUS_DMA_ZERO); 2066 if (r != 0) 2067 goto destroy; 2068 2069 r = bus_dmamem_map(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg, size, 2070 &dma->dma_vaddr, BUS_DMA_WAITOK); 2071 if (r != 0) 2072 goto free; 2073 2074 r = bus_dmamap_load(sc->sc_dmat, dma->dma_map, dma->dma_vaddr, size, 2075 NULL, BUS_DMA_WAITOK); 2076 if (r != 0) 2077 goto unmap; 2078 2079 dma->dma_size = size; 2080 return (0); 2081 2082 unmap: 2083 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, size); 2084 free: 2085 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 2086 destroy: 2087 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 2088 2089 return (r); 2090 } 2091 2092 void 2093 em_dma_free(struct em_softc *sc, struct em_dma_alloc *dma) 2094 { 2095 bus_dmamap_unload(sc->sc_dmat, dma->dma_map); 2096 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, dma->dma_size); 2097 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 2098 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 2099 } 2100 2101 /********************************************************************* 2102 * 2103 * Allocate memory for tx_buffer structures. The tx_buffer stores all 2104 * the information needed to transmit a packet on the wire. 2105 * 2106 **********************************************************************/ 2107 int 2108 em_allocate_transmit_structures(struct em_softc *sc) 2109 { 2110 bus_dmamap_sync(sc->sc_dmat, sc->sc_tx_dma.dma_map, 2111 0, sc->sc_tx_dma.dma_map->dm_mapsize, 2112 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2113 2114 sc->sc_tx_pkts_ring = mallocarray(sc->sc_tx_slots, 2115 sizeof(*sc->sc_tx_pkts_ring), M_DEVBUF, M_NOWAIT | M_ZERO); 2116 if (sc->sc_tx_pkts_ring == NULL) { 2117 printf("%s: Unable to allocate tx_buffer memory\n", 2118 DEVNAME(sc)); 2119 return (ENOMEM); 2120 } 2121 2122 return (0); 2123 } 2124 2125 /********************************************************************* 2126 * 2127 * Allocate and initialize transmit structures. 2128 * 2129 **********************************************************************/ 2130 int 2131 em_setup_transmit_structures(struct em_softc *sc) 2132 { 2133 struct em_packet *pkt; 2134 int error, i; 2135 2136 if ((error = em_allocate_transmit_structures(sc)) != 0) 2137 goto fail; 2138 2139 bzero((void *) sc->sc_tx_desc_ring, 2140 (sizeof(struct em_tx_desc)) * sc->sc_tx_slots); 2141 2142 for (i = 0; i < sc->sc_tx_slots; i++) { 2143 pkt = &sc->sc_tx_pkts_ring[i]; 2144 error = bus_dmamap_create(sc->sc_dmat, MAX_JUMBO_FRAME_SIZE, 2145 EM_MAX_SCATTER / (sc->pcix_82544 ? 2 : 1), 2146 MAX_JUMBO_FRAME_SIZE, 0, BUS_DMA_NOWAIT, &pkt->pkt_map); 2147 if (error != 0) { 2148 printf("%s: Unable to create TX DMA map\n", 2149 DEVNAME(sc)); 2150 goto fail; 2151 } 2152 } 2153 2154 sc->sc_tx_desc_head = 0; 2155 sc->sc_tx_desc_tail = 0; 2156 2157 /* Set checksum context */ 2158 sc->active_checksum_context = OFFLOAD_NONE; 2159 2160 return (0); 2161 2162 fail: 2163 em_free_transmit_structures(sc); 2164 return (error); 2165 } 2166 2167 /********************************************************************* 2168 * 2169 * Enable transmit unit. 2170 * 2171 **********************************************************************/ 2172 void 2173 em_initialize_transmit_unit(struct em_softc *sc) 2174 { 2175 u_int32_t reg_tctl, reg_tipg = 0; 2176 u_int64_t bus_addr; 2177 2178 INIT_DEBUGOUT("em_initialize_transmit_unit: begin"); 2179 2180 /* Setup the Base and Length of the Tx Descriptor Ring */ 2181 bus_addr = sc->sc_tx_dma.dma_map->dm_segs[0].ds_addr; 2182 E1000_WRITE_REG(&sc->hw, TDLEN, 2183 sc->sc_tx_slots * 2184 sizeof(struct em_tx_desc)); 2185 E1000_WRITE_REG(&sc->hw, TDBAH, (u_int32_t)(bus_addr >> 32)); 2186 E1000_WRITE_REG(&sc->hw, TDBAL, (u_int32_t)bus_addr); 2187 2188 /* Setup the HW Tx Head and Tail descriptor pointers */ 2189 E1000_WRITE_REG(&sc->hw, TDT, 0); 2190 E1000_WRITE_REG(&sc->hw, TDH, 0); 2191 2192 HW_DEBUGOUT2("Base = %x, Length = %x\n", 2193 E1000_READ_REG(&sc->hw, TDBAL), 2194 E1000_READ_REG(&sc->hw, TDLEN)); 2195 2196 /* Set the default values for the Tx Inter Packet Gap timer */ 2197 switch (sc->hw.mac_type) { 2198 case em_82542_rev2_0: 2199 case em_82542_rev2_1: 2200 reg_tipg = DEFAULT_82542_TIPG_IPGT; 2201 reg_tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2202 reg_tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2203 break; 2204 case em_80003es2lan: 2205 reg_tipg = DEFAULT_82543_TIPG_IPGR1; 2206 reg_tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2207 break; 2208 default: 2209 if (sc->hw.media_type == em_media_type_fiber || 2210 sc->hw.media_type == em_media_type_internal_serdes) 2211 reg_tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 2212 else 2213 reg_tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 2214 reg_tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2215 reg_tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2216 } 2217 2218 2219 E1000_WRITE_REG(&sc->hw, TIPG, reg_tipg); 2220 E1000_WRITE_REG(&sc->hw, TIDV, sc->tx_int_delay); 2221 if (sc->hw.mac_type >= em_82540) 2222 E1000_WRITE_REG(&sc->hw, TADV, sc->tx_abs_int_delay); 2223 2224 /* Setup Transmit Descriptor Base Settings */ 2225 sc->sc_txd_cmd = E1000_TXD_CMD_IFCS; 2226 2227 if (sc->hw.mac_type == em_82575 || sc->hw.mac_type == em_82580 || 2228 sc->hw.mac_type == em_i210 || sc->hw.mac_type == em_i350) { 2229 /* 82575/6 need to enable the TX queue and lack the IDE bit */ 2230 reg_tctl = E1000_READ_REG(&sc->hw, TXDCTL); 2231 reg_tctl |= E1000_TXDCTL_QUEUE_ENABLE; 2232 E1000_WRITE_REG(&sc->hw, TXDCTL, reg_tctl); 2233 } else if (sc->tx_int_delay > 0) 2234 sc->sc_txd_cmd |= E1000_TXD_CMD_IDE; 2235 2236 /* Program the Transmit Control Register */ 2237 reg_tctl = E1000_TCTL_PSP | E1000_TCTL_EN | 2238 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 2239 if (sc->hw.mac_type >= em_82571) 2240 reg_tctl |= E1000_TCTL_MULR; 2241 if (sc->link_duplex == FULL_DUPLEX) 2242 reg_tctl |= E1000_FDX_COLLISION_DISTANCE << E1000_COLD_SHIFT; 2243 else 2244 reg_tctl |= E1000_HDX_COLLISION_DISTANCE << E1000_COLD_SHIFT; 2245 /* This write will effectively turn on the transmit unit */ 2246 E1000_WRITE_REG(&sc->hw, TCTL, reg_tctl); 2247 2248 /* SPT Si errata workaround to avoid data corruption */ 2249 2250 if (sc->hw.mac_type == em_pch_spt) { 2251 uint32_t reg_val; 2252 2253 reg_val = EM_READ_REG(&sc->hw, E1000_IOSFPC); 2254 reg_val |= E1000_RCTL_RDMTS_HEX; 2255 EM_WRITE_REG(&sc->hw, E1000_IOSFPC, reg_val); 2256 2257 reg_val = E1000_READ_REG(&sc->hw, TARC0); 2258 reg_val |= E1000_TARC0_CB_MULTIQ_3_REQ; 2259 E1000_WRITE_REG(&sc->hw, TARC0, reg_val); 2260 } 2261 } 2262 2263 /********************************************************************* 2264 * 2265 * Free all transmit related data structures. 2266 * 2267 **********************************************************************/ 2268 void 2269 em_free_transmit_structures(struct em_softc *sc) 2270 { 2271 struct em_packet *pkt; 2272 int i; 2273 2274 INIT_DEBUGOUT("free_transmit_structures: begin"); 2275 2276 if (sc->sc_tx_pkts_ring != NULL) { 2277 for (i = 0; i < sc->sc_tx_slots; i++) { 2278 pkt = &sc->sc_tx_pkts_ring[i]; 2279 2280 if (pkt->pkt_m != NULL) { 2281 bus_dmamap_sync(sc->sc_dmat, pkt->pkt_map, 2282 0, pkt->pkt_map->dm_mapsize, 2283 BUS_DMASYNC_POSTWRITE); 2284 bus_dmamap_unload(sc->sc_dmat, pkt->pkt_map); 2285 2286 m_freem(pkt->pkt_m); 2287 pkt->pkt_m = NULL; 2288 } 2289 2290 if (pkt->pkt_map != NULL) { 2291 bus_dmamap_destroy(sc->sc_dmat, pkt->pkt_map); 2292 pkt->pkt_map = NULL; 2293 } 2294 } 2295 2296 free(sc->sc_tx_pkts_ring, M_DEVBUF, 2297 sc->sc_tx_slots * sizeof(*sc->sc_tx_pkts_ring)); 2298 sc->sc_tx_pkts_ring = NULL; 2299 } 2300 2301 bus_dmamap_sync(sc->sc_dmat, sc->sc_tx_dma.dma_map, 2302 0, sc->sc_tx_dma.dma_map->dm_mapsize, 2303 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2304 } 2305 2306 /********************************************************************* 2307 * 2308 * The offload context needs to be set when we transfer the first 2309 * packet of a particular protocol (TCP/UDP). We change the 2310 * context only if the protocol type changes. 2311 * 2312 **********************************************************************/ 2313 u_int 2314 em_transmit_checksum_setup(struct em_softc *sc, struct mbuf *mp, u_int head, 2315 u_int32_t *txd_upper, u_int32_t *txd_lower) 2316 { 2317 struct em_context_desc *TXD; 2318 2319 if (mp->m_pkthdr.csum_flags & M_TCP_CSUM_OUT) { 2320 *txd_upper = E1000_TXD_POPTS_TXSM << 8; 2321 *txd_lower = E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 2322 if (sc->active_checksum_context == OFFLOAD_TCP_IP) 2323 return (0); 2324 else 2325 sc->active_checksum_context = OFFLOAD_TCP_IP; 2326 } else if (mp->m_pkthdr.csum_flags & M_UDP_CSUM_OUT) { 2327 *txd_upper = E1000_TXD_POPTS_TXSM << 8; 2328 *txd_lower = E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 2329 if (sc->active_checksum_context == OFFLOAD_UDP_IP) 2330 return (0); 2331 else 2332 sc->active_checksum_context = OFFLOAD_UDP_IP; 2333 } else { 2334 *txd_upper = 0; 2335 *txd_lower = 0; 2336 return (0); 2337 } 2338 2339 /* If we reach this point, the checksum offload context 2340 * needs to be reset. 2341 */ 2342 TXD = (struct em_context_desc *)&sc->sc_tx_desc_ring[head]; 2343 2344 TXD->lower_setup.ip_fields.ipcss = ETHER_HDR_LEN; 2345 TXD->lower_setup.ip_fields.ipcso = 2346 ETHER_HDR_LEN + offsetof(struct ip, ip_sum); 2347 TXD->lower_setup.ip_fields.ipcse = 2348 htole16(ETHER_HDR_LEN + sizeof(struct ip) - 1); 2349 2350 TXD->upper_setup.tcp_fields.tucss = 2351 ETHER_HDR_LEN + sizeof(struct ip); 2352 TXD->upper_setup.tcp_fields.tucse = htole16(0); 2353 2354 if (sc->active_checksum_context == OFFLOAD_TCP_IP) { 2355 TXD->upper_setup.tcp_fields.tucso = 2356 ETHER_HDR_LEN + sizeof(struct ip) + 2357 offsetof(struct tcphdr, th_sum); 2358 } else if (sc->active_checksum_context == OFFLOAD_UDP_IP) { 2359 TXD->upper_setup.tcp_fields.tucso = 2360 ETHER_HDR_LEN + sizeof(struct ip) + 2361 offsetof(struct udphdr, uh_sum); 2362 } 2363 2364 TXD->tcp_seg_setup.data = htole32(0); 2365 TXD->cmd_and_length = htole32(sc->sc_txd_cmd | E1000_TXD_CMD_DEXT); 2366 2367 return (1); 2368 } 2369 2370 /********************************************************************** 2371 * 2372 * Examine each tx_buffer in the used queue. If the hardware is done 2373 * processing the packet then free associated resources. The 2374 * tx_buffer is put back on the free queue. 2375 * 2376 **********************************************************************/ 2377 void 2378 em_txeof(struct em_softc *sc) 2379 { 2380 struct ifnet *ifp = &sc->sc_ac.ac_if; 2381 struct em_packet *pkt; 2382 struct em_tx_desc *desc; 2383 u_int head, tail; 2384 u_int free = 0; 2385 2386 head = sc->sc_tx_desc_head; 2387 tail = sc->sc_tx_desc_tail; 2388 2389 if (head == tail) 2390 return; 2391 2392 bus_dmamap_sync(sc->sc_dmat, sc->sc_tx_dma.dma_map, 2393 0, sc->sc_tx_dma.dma_map->dm_mapsize, 2394 BUS_DMASYNC_POSTREAD); 2395 2396 do { 2397 pkt = &sc->sc_tx_pkts_ring[tail]; 2398 desc = &sc->sc_tx_desc_ring[pkt->pkt_eop]; 2399 2400 if (!ISSET(desc->upper.fields.status, E1000_TXD_STAT_DD)) 2401 break; 2402 2403 bus_dmamap_sync(sc->sc_dmat, pkt->pkt_map, 2404 0, pkt->pkt_map->dm_mapsize, 2405 BUS_DMASYNC_POSTWRITE); 2406 bus_dmamap_unload(sc->sc_dmat, pkt->pkt_map); 2407 2408 KASSERT(pkt->pkt_m != NULL); 2409 2410 m_freem(pkt->pkt_m); 2411 pkt->pkt_m = NULL; 2412 2413 tail = pkt->pkt_eop; 2414 2415 if (++tail == sc->sc_tx_slots) 2416 tail = 0; 2417 2418 free++; 2419 } while (tail != head); 2420 2421 bus_dmamap_sync(sc->sc_dmat, sc->sc_tx_dma.dma_map, 2422 0, sc->sc_tx_dma.dma_map->dm_mapsize, 2423 BUS_DMASYNC_PREREAD); 2424 2425 if (free == 0) 2426 return; 2427 2428 sc->sc_tx_desc_tail = tail; 2429 2430 if (ifq_is_oactive(&ifp->if_snd)) 2431 ifq_restart(&ifp->if_snd); 2432 else if (tail == head) 2433 ifp->if_timer = 0; 2434 } 2435 2436 /********************************************************************* 2437 * 2438 * Get a buffer from system mbuf buffer pool. 2439 * 2440 **********************************************************************/ 2441 int 2442 em_get_buf(struct em_softc *sc, int i) 2443 { 2444 struct mbuf *m; 2445 struct em_packet *pkt; 2446 struct em_rx_desc *desc; 2447 int error; 2448 2449 pkt = &sc->sc_rx_pkts_ring[i]; 2450 desc = &sc->sc_rx_desc_ring[i]; 2451 2452 KASSERT(pkt->pkt_m == NULL); 2453 2454 m = MCLGETI(NULL, M_DONTWAIT, NULL, EM_MCLBYTES); 2455 if (m == NULL) { 2456 sc->mbuf_cluster_failed++; 2457 return (ENOBUFS); 2458 } 2459 m->m_len = m->m_pkthdr.len = EM_MCLBYTES; 2460 m_adj(m, ETHER_ALIGN); 2461 2462 error = bus_dmamap_load_mbuf(sc->sc_dmat, pkt->pkt_map, 2463 m, BUS_DMA_NOWAIT); 2464 if (error) { 2465 m_freem(m); 2466 return (error); 2467 } 2468 2469 bus_dmamap_sync(sc->sc_dmat, pkt->pkt_map, 2470 0, pkt->pkt_map->dm_mapsize, 2471 BUS_DMASYNC_PREREAD); 2472 pkt->pkt_m = m; 2473 2474 memset(desc, 0, sizeof(*desc)); 2475 htolem64(&desc->buffer_addr, pkt->pkt_map->dm_segs[0].ds_addr); 2476 2477 return (0); 2478 } 2479 2480 /********************************************************************* 2481 * 2482 * Allocate memory for rx_buffer structures. Since we use one 2483 * rx_buffer per received packet, the maximum number of rx_buffer's 2484 * that we'll need is equal to the number of receive descriptors 2485 * that we've allocated. 2486 * 2487 **********************************************************************/ 2488 int 2489 em_allocate_receive_structures(struct em_softc *sc) 2490 { 2491 struct em_packet *pkt; 2492 int i; 2493 int error; 2494 2495 sc->sc_rx_pkts_ring = mallocarray(sc->sc_rx_slots, 2496 sizeof(*sc->sc_rx_pkts_ring), M_DEVBUF, M_NOWAIT | M_ZERO); 2497 if (sc->sc_rx_pkts_ring == NULL) { 2498 printf("%s: Unable to allocate rx_buffer memory\n", 2499 DEVNAME(sc)); 2500 return (ENOMEM); 2501 } 2502 2503 bus_dmamap_sync(sc->sc_dmat, sc->sc_rx_dma.dma_map, 2504 0, sc->sc_rx_dma.dma_map->dm_mapsize, 2505 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2506 2507 for (i = 0; i < sc->sc_rx_slots; i++) { 2508 pkt = &sc->sc_rx_pkts_ring[i]; 2509 2510 error = bus_dmamap_create(sc->sc_dmat, EM_MCLBYTES, 1, 2511 EM_MCLBYTES, 0, BUS_DMA_NOWAIT, &pkt->pkt_map); 2512 if (error != 0) { 2513 printf("%s: em_allocate_receive_structures: " 2514 "bus_dmamap_create failed; error %u\n", 2515 DEVNAME(sc), error); 2516 goto fail; 2517 } 2518 2519 pkt->pkt_m = NULL; 2520 } 2521 2522 return (0); 2523 2524 fail: 2525 em_free_receive_structures(sc); 2526 return (error); 2527 } 2528 2529 /********************************************************************* 2530 * 2531 * Allocate and initialize receive structures. 2532 * 2533 **********************************************************************/ 2534 int 2535 em_setup_receive_structures(struct em_softc *sc) 2536 { 2537 struct ifnet *ifp = &sc->sc_ac.ac_if; 2538 u_int lwm; 2539 2540 memset(sc->sc_rx_desc_ring, 0, 2541 sc->sc_rx_slots * sizeof(*sc->sc_rx_desc_ring)); 2542 2543 if (em_allocate_receive_structures(sc)) 2544 return (ENOMEM); 2545 2546 /* Setup our descriptor pointers */ 2547 sc->sc_rx_desc_tail = 0; 2548 sc->sc_rx_desc_head = sc->sc_rx_slots - 1; 2549 2550 lwm = max(4, 2 * ((ifp->if_hardmtu / MCLBYTES) + 1)); 2551 if_rxr_init(&sc->sc_rx_ring, lwm, sc->sc_rx_slots); 2552 2553 if (em_rxfill(sc) == 0) { 2554 printf("%s: unable to fill any rx descriptors\n", 2555 DEVNAME(sc)); 2556 } 2557 2558 return (0); 2559 } 2560 2561 /********************************************************************* 2562 * 2563 * Enable receive unit. 2564 * 2565 **********************************************************************/ 2566 void 2567 em_initialize_receive_unit(struct em_softc *sc) 2568 { 2569 u_int32_t reg_rctl; 2570 u_int32_t reg_rxcsum; 2571 u_int64_t bus_addr; 2572 2573 INIT_DEBUGOUT("em_initialize_receive_unit: begin"); 2574 2575 /* Make sure receives are disabled while setting up the descriptor ring */ 2576 E1000_WRITE_REG(&sc->hw, RCTL, 0); 2577 2578 /* Set the Receive Delay Timer Register */ 2579 E1000_WRITE_REG(&sc->hw, RDTR, 2580 sc->rx_int_delay | E1000_RDT_FPDB); 2581 2582 if (sc->hw.mac_type >= em_82540) { 2583 if (sc->rx_int_delay) 2584 E1000_WRITE_REG(&sc->hw, RADV, sc->rx_abs_int_delay); 2585 2586 /* Set the interrupt throttling rate. Value is calculated 2587 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */ 2588 E1000_WRITE_REG(&sc->hw, ITR, DEFAULT_ITR); 2589 } 2590 2591 /* Setup the Base and Length of the Rx Descriptor Ring */ 2592 bus_addr = sc->sc_rx_dma.dma_map->dm_segs[0].ds_addr; 2593 E1000_WRITE_REG(&sc->hw, RDLEN, 2594 sc->sc_rx_slots * sizeof(*sc->sc_rx_desc_ring)); 2595 E1000_WRITE_REG(&sc->hw, RDBAH, (u_int32_t)(bus_addr >> 32)); 2596 E1000_WRITE_REG(&sc->hw, RDBAL, (u_int32_t)bus_addr); 2597 2598 /* Setup the Receive Control Register */ 2599 reg_rctl = E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO | 2600 E1000_RCTL_RDMTS_HALF | 2601 (sc->hw.mc_filter_type << E1000_RCTL_MO_SHIFT); 2602 2603 if (sc->hw.tbi_compatibility_on == TRUE) 2604 reg_rctl |= E1000_RCTL_SBP; 2605 2606 /* 2607 * The i350 has a bug where it always strips the CRC whether 2608 * asked to or not. So ask for stripped CRC here and 2609 * cope in rxeof 2610 */ 2611 if (sc->hw.mac_type == em_i210 || sc->hw.mac_type == em_i350) 2612 reg_rctl |= E1000_RCTL_SECRC; 2613 2614 switch (sc->sc_rx_buffer_len) { 2615 default: 2616 case EM_RXBUFFER_2048: 2617 reg_rctl |= E1000_RCTL_SZ_2048; 2618 break; 2619 case EM_RXBUFFER_4096: 2620 reg_rctl |= E1000_RCTL_SZ_4096|E1000_RCTL_BSEX|E1000_RCTL_LPE; 2621 break; 2622 case EM_RXBUFFER_8192: 2623 reg_rctl |= E1000_RCTL_SZ_8192|E1000_RCTL_BSEX|E1000_RCTL_LPE; 2624 break; 2625 case EM_RXBUFFER_16384: 2626 reg_rctl |= E1000_RCTL_SZ_16384|E1000_RCTL_BSEX|E1000_RCTL_LPE; 2627 break; 2628 } 2629 2630 if (sc->hw.max_frame_size != ETHER_MAX_LEN) 2631 reg_rctl |= E1000_RCTL_LPE; 2632 2633 /* Enable 82543 Receive Checksum Offload for TCP and UDP */ 2634 if (sc->hw.mac_type >= em_82543) { 2635 reg_rxcsum = E1000_READ_REG(&sc->hw, RXCSUM); 2636 reg_rxcsum |= (E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL); 2637 E1000_WRITE_REG(&sc->hw, RXCSUM, reg_rxcsum); 2638 } 2639 2640 /* 2641 * XXX TEMPORARY WORKAROUND: on some systems with 82573 2642 * long latencies are observed, like Lenovo X60. 2643 */ 2644 if (sc->hw.mac_type == em_82573) 2645 E1000_WRITE_REG(&sc->hw, RDTR, 0x20); 2646 2647 if (sc->hw.mac_type == em_82575 || sc->hw.mac_type == em_82580 || 2648 sc->hw.mac_type == em_i210 || sc->hw.mac_type == em_i350) { 2649 /* 82575/6 need to enable the RX queue */ 2650 uint32_t reg; 2651 reg = E1000_READ_REG(&sc->hw, RXDCTL); 2652 reg |= E1000_RXDCTL_QUEUE_ENABLE; 2653 E1000_WRITE_REG(&sc->hw, RXDCTL, reg); 2654 } 2655 2656 /* Enable Receives */ 2657 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 2658 2659 /* Setup the HW Rx Head and Tail Descriptor Pointers */ 2660 E1000_WRITE_REG(&sc->hw, RDH, 0); 2661 E1000_WRITE_REG(&sc->hw, RDT, sc->sc_rx_desc_head); 2662 } 2663 2664 /********************************************************************* 2665 * 2666 * Free receive related data structures. 2667 * 2668 **********************************************************************/ 2669 void 2670 em_free_receive_structures(struct em_softc *sc) 2671 { 2672 struct em_packet *pkt; 2673 int i; 2674 2675 INIT_DEBUGOUT("free_receive_structures: begin"); 2676 2677 if_rxr_init(&sc->sc_rx_ring, 0, 0); 2678 2679 bus_dmamap_sync(sc->sc_dmat, sc->sc_rx_dma.dma_map, 2680 0, sc->sc_rx_dma.dma_map->dm_mapsize, 2681 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2682 2683 if (sc->sc_rx_pkts_ring != NULL) { 2684 for (i = 0; i < sc->sc_rx_slots; i++) { 2685 pkt = &sc->sc_rx_pkts_ring[i]; 2686 if (pkt->pkt_m != NULL) { 2687 bus_dmamap_sync(sc->sc_dmat, pkt->pkt_map, 2688 0, pkt->pkt_map->dm_mapsize, 2689 BUS_DMASYNC_POSTREAD); 2690 bus_dmamap_unload(sc->sc_dmat, pkt->pkt_map); 2691 m_freem(pkt->pkt_m); 2692 pkt->pkt_m = NULL; 2693 } 2694 bus_dmamap_destroy(sc->sc_dmat, pkt->pkt_map); 2695 } 2696 2697 free(sc->sc_rx_pkts_ring, M_DEVBUF, 2698 sc->sc_rx_slots * sizeof(*sc->sc_rx_pkts_ring)); 2699 sc->sc_rx_pkts_ring = NULL; 2700 } 2701 2702 if (sc->fmp != NULL) { 2703 m_freem(sc->fmp); 2704 sc->fmp = NULL; 2705 sc->lmp = NULL; 2706 } 2707 } 2708 2709 int 2710 em_rxfill(struct em_softc *sc) 2711 { 2712 u_int slots; 2713 int post = 0; 2714 int i; 2715 2716 i = sc->sc_rx_desc_head; 2717 2718 bus_dmamap_sync(sc->sc_dmat, sc->sc_rx_dma.dma_map, 2719 0, sc->sc_rx_dma.dma_map->dm_mapsize, 2720 BUS_DMASYNC_POSTWRITE); 2721 2722 for (slots = if_rxr_get(&sc->sc_rx_ring, sc->sc_rx_slots); 2723 slots > 0; slots--) { 2724 if (++i == sc->sc_rx_slots) 2725 i = 0; 2726 2727 if (em_get_buf(sc, i) != 0) 2728 break; 2729 2730 sc->sc_rx_desc_head = i; 2731 post = 1; 2732 } 2733 2734 if_rxr_put(&sc->sc_rx_ring, slots); 2735 2736 bus_dmamap_sync(sc->sc_dmat, sc->sc_rx_dma.dma_map, 2737 0, sc->sc_rx_dma.dma_map->dm_mapsize, 2738 BUS_DMASYNC_PREWRITE); 2739 2740 return (post); 2741 } 2742 2743 /********************************************************************* 2744 * 2745 * This routine executes in interrupt context. It replenishes 2746 * the mbufs in the descriptor and sends data which has been 2747 * dma'ed into host memory to upper layer. 2748 * 2749 *********************************************************************/ 2750 int 2751 em_rxeof(struct em_softc *sc) 2752 { 2753 struct ifnet *ifp = &sc->sc_ac.ac_if; 2754 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 2755 struct mbuf *m; 2756 u_int8_t accept_frame = 0; 2757 u_int8_t eop = 0; 2758 u_int16_t len, desc_len, prev_len_adj; 2759 int i, rv = 0; 2760 2761 /* Pointer to the receive descriptor being examined. */ 2762 struct em_rx_desc *desc; 2763 struct em_packet *pkt; 2764 u_int8_t status; 2765 2766 if (if_rxr_inuse(&sc->sc_rx_ring) == 0) 2767 return (0); 2768 2769 i = sc->sc_rx_desc_tail; 2770 2771 bus_dmamap_sync(sc->sc_dmat, sc->sc_rx_dma.dma_map, 2772 0, sc->sc_rx_dma.dma_map->dm_mapsize, 2773 BUS_DMASYNC_POSTREAD); 2774 2775 do { 2776 m = NULL; 2777 2778 pkt = &sc->sc_rx_pkts_ring[i]; 2779 desc = &sc->sc_rx_desc_ring[i]; 2780 2781 status = desc->status; 2782 if (!ISSET(status, E1000_RXD_STAT_DD)) 2783 break; 2784 2785 /* pull the mbuf off the ring */ 2786 bus_dmamap_sync(sc->sc_dmat, pkt->pkt_map, 2787 0, pkt->pkt_map->dm_mapsize, 2788 BUS_DMASYNC_POSTREAD); 2789 bus_dmamap_unload(sc->sc_dmat, pkt->pkt_map); 2790 m = pkt->pkt_m; 2791 pkt->pkt_m = NULL; 2792 2793 KASSERT(m != NULL); 2794 2795 if_rxr_put(&sc->sc_rx_ring, 1); 2796 rv = 1; 2797 2798 accept_frame = 1; 2799 prev_len_adj = 0; 2800 desc_len = letoh16(desc->length); 2801 2802 if (status & E1000_RXD_STAT_EOP) { 2803 eop = 1; 2804 if (desc_len < ETHER_CRC_LEN) { 2805 len = 0; 2806 prev_len_adj = ETHER_CRC_LEN - desc_len; 2807 } else if (sc->hw.mac_type == em_i210 || 2808 sc->hw.mac_type == em_i350) 2809 len = desc_len; 2810 else 2811 len = desc_len - ETHER_CRC_LEN; 2812 } else { 2813 eop = 0; 2814 len = desc_len; 2815 } 2816 2817 if (desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK) { 2818 u_int8_t last_byte; 2819 u_int32_t pkt_len = desc_len; 2820 2821 if (sc->fmp != NULL) 2822 pkt_len += sc->fmp->m_pkthdr.len; 2823 2824 last_byte = *(mtod(m, caddr_t) + desc_len - 1); 2825 if (TBI_ACCEPT(&sc->hw, status, desc->errors, 2826 pkt_len, last_byte)) { 2827 #ifndef SMALL_KERNEL 2828 em_tbi_adjust_stats(&sc->hw, &sc->stats, 2829 pkt_len, sc->hw.mac_addr); 2830 #endif 2831 if (len > 0) 2832 len--; 2833 } else 2834 accept_frame = 0; 2835 } 2836 2837 if (accept_frame) { 2838 /* Assign correct length to the current fragment */ 2839 m->m_len = len; 2840 2841 if (sc->fmp == NULL) { 2842 m->m_pkthdr.len = m->m_len; 2843 sc->fmp = m; /* Store the first mbuf */ 2844 sc->lmp = m; 2845 } else { 2846 /* Chain mbuf's together */ 2847 m->m_flags &= ~M_PKTHDR; 2848 /* 2849 * Adjust length of previous mbuf in chain if 2850 * we received less than 4 bytes in the last 2851 * descriptor. 2852 */ 2853 if (prev_len_adj > 0) { 2854 sc->lmp->m_len -= prev_len_adj; 2855 sc->fmp->m_pkthdr.len -= prev_len_adj; 2856 } 2857 sc->lmp->m_next = m; 2858 sc->lmp = m; 2859 sc->fmp->m_pkthdr.len += m->m_len; 2860 } 2861 2862 if (eop) { 2863 m = sc->fmp; 2864 2865 em_receive_checksum(sc, desc, m); 2866 #if NVLAN > 0 2867 if (desc->status & E1000_RXD_STAT_VP) { 2868 m->m_pkthdr.ether_vtag = 2869 letoh16(desc->special); 2870 m->m_flags |= M_VLANTAG; 2871 } 2872 #endif 2873 ml_enqueue(&ml, m); 2874 2875 sc->fmp = NULL; 2876 sc->lmp = NULL; 2877 } 2878 } else { 2879 sc->dropped_pkts++; 2880 2881 if (sc->fmp != NULL) { 2882 m_freem(sc->fmp); 2883 sc->fmp = NULL; 2884 sc->lmp = NULL; 2885 } 2886 2887 m_freem(m); 2888 } 2889 2890 /* Advance our pointers to the next descriptor. */ 2891 if (++i == sc->sc_rx_slots) 2892 i = 0; 2893 } while (if_rxr_inuse(&sc->sc_rx_ring) > 0); 2894 2895 bus_dmamap_sync(sc->sc_dmat, sc->sc_rx_dma.dma_map, 2896 0, sc->sc_rx_dma.dma_map->dm_mapsize, 2897 BUS_DMASYNC_PREREAD); 2898 2899 sc->sc_rx_desc_tail = i; 2900 2901 if_input(ifp, &ml); 2902 2903 return (rv); 2904 } 2905 2906 /********************************************************************* 2907 * 2908 * Verify that the hardware indicated that the checksum is valid. 2909 * Inform the stack about the status of checksum so that stack 2910 * doesn't spend time verifying the checksum. 2911 * 2912 *********************************************************************/ 2913 void 2914 em_receive_checksum(struct em_softc *sc, struct em_rx_desc *rx_desc, 2915 struct mbuf *mp) 2916 { 2917 /* 82543 or newer only */ 2918 if ((sc->hw.mac_type < em_82543) || 2919 /* Ignore Checksum bit is set */ 2920 (rx_desc->status & E1000_RXD_STAT_IXSM)) { 2921 mp->m_pkthdr.csum_flags = 0; 2922 return; 2923 } 2924 2925 if (rx_desc->status & E1000_RXD_STAT_IPCS) { 2926 /* Did it pass? */ 2927 if (!(rx_desc->errors & E1000_RXD_ERR_IPE)) { 2928 /* IP Checksum Good */ 2929 mp->m_pkthdr.csum_flags = M_IPV4_CSUM_IN_OK; 2930 2931 } else 2932 mp->m_pkthdr.csum_flags = 0; 2933 } 2934 2935 if (rx_desc->status & E1000_RXD_STAT_TCPCS) { 2936 /* Did it pass? */ 2937 if (!(rx_desc->errors & E1000_RXD_ERR_TCPE)) 2938 mp->m_pkthdr.csum_flags |= 2939 M_TCP_CSUM_IN_OK | M_UDP_CSUM_IN_OK; 2940 } 2941 } 2942 2943 /* 2944 * This turns on the hardware offload of the VLAN 2945 * tag insertion and strip 2946 */ 2947 void 2948 em_enable_hw_vlans(struct em_softc *sc) 2949 { 2950 uint32_t ctrl; 2951 2952 ctrl = E1000_READ_REG(&sc->hw, CTRL); 2953 ctrl |= E1000_CTRL_VME; 2954 E1000_WRITE_REG(&sc->hw, CTRL, ctrl); 2955 } 2956 2957 void 2958 em_enable_intr(struct em_softc *sc) 2959 { 2960 E1000_WRITE_REG(&sc->hw, IMS, (IMS_ENABLE_MASK)); 2961 } 2962 2963 void 2964 em_disable_intr(struct em_softc *sc) 2965 { 2966 /* 2967 * The first version of 82542 had an errata where when link 2968 * was forced it would stay up even if the cable was disconnected 2969 * Sequence errors were used to detect the disconnect and then 2970 * the driver would unforce the link. This code is in the ISR. 2971 * For this to work correctly the Sequence error interrupt had 2972 * to be enabled all the time. 2973 */ 2974 2975 if (sc->hw.mac_type == em_82542_rev2_0) 2976 E1000_WRITE_REG(&sc->hw, IMC, (0xffffffff & ~E1000_IMC_RXSEQ)); 2977 else 2978 E1000_WRITE_REG(&sc->hw, IMC, 0xffffffff); 2979 } 2980 2981 void 2982 em_write_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t *value) 2983 { 2984 struct pci_attach_args *pa = &((struct em_osdep *)hw->back)->em_pa; 2985 pcireg_t val; 2986 2987 val = pci_conf_read(pa->pa_pc, pa->pa_tag, reg & ~0x3); 2988 if (reg & 0x2) { 2989 val &= 0x0000ffff; 2990 val |= (*value << 16); 2991 } else { 2992 val &= 0xffff0000; 2993 val |= *value; 2994 } 2995 pci_conf_write(pa->pa_pc, pa->pa_tag, reg & ~0x3, val); 2996 } 2997 2998 void 2999 em_read_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t *value) 3000 { 3001 struct pci_attach_args *pa = &((struct em_osdep *)hw->back)->em_pa; 3002 pcireg_t val; 3003 3004 val = pci_conf_read(pa->pa_pc, pa->pa_tag, reg & ~0x3); 3005 if (reg & 0x2) 3006 *value = (val >> 16) & 0xffff; 3007 else 3008 *value = val & 0xffff; 3009 } 3010 3011 void 3012 em_pci_set_mwi(struct em_hw *hw) 3013 { 3014 struct pci_attach_args *pa = &((struct em_osdep *)hw->back)->em_pa; 3015 3016 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 3017 (hw->pci_cmd_word | CMD_MEM_WRT_INVALIDATE)); 3018 } 3019 3020 void 3021 em_pci_clear_mwi(struct em_hw *hw) 3022 { 3023 struct pci_attach_args *pa = &((struct em_osdep *)hw->back)->em_pa; 3024 3025 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 3026 (hw->pci_cmd_word & ~CMD_MEM_WRT_INVALIDATE)); 3027 } 3028 3029 /* 3030 * We may eventually really do this, but its unnecessary 3031 * for now so we just return unsupported. 3032 */ 3033 int32_t 3034 em_read_pcie_cap_reg(struct em_hw *hw, uint32_t reg, uint16_t *value) 3035 { 3036 return -E1000_NOT_IMPLEMENTED; 3037 } 3038 3039 /********************************************************************* 3040 * 82544 Coexistence issue workaround. 3041 * There are 2 issues. 3042 * 1. Transmit Hang issue. 3043 * To detect this issue, following equation can be used... 3044 * SIZE[3:0] + ADDR[2:0] = SUM[3:0]. 3045 * If SUM[3:0] is in between 1 to 4, we will have this issue. 3046 * 3047 * 2. DAC issue. 3048 * To detect this issue, following equation can be used... 3049 * SIZE[3:0] + ADDR[2:0] = SUM[3:0]. 3050 * If SUM[3:0] is in between 9 to c, we will have this issue. 3051 * 3052 * 3053 * WORKAROUND: 3054 * Make sure we do not have ending address as 1,2,3,4(Hang) or 9,a,b,c (DAC) 3055 * 3056 *** *********************************************************************/ 3057 u_int32_t 3058 em_fill_descriptors(u_int64_t address, u_int32_t length, 3059 PDESC_ARRAY desc_array) 3060 { 3061 /* Since issue is sensitive to length and address.*/ 3062 /* Let us first check the address...*/ 3063 u_int32_t safe_terminator; 3064 if (length <= 4) { 3065 desc_array->descriptor[0].address = address; 3066 desc_array->descriptor[0].length = length; 3067 desc_array->elements = 1; 3068 return desc_array->elements; 3069 } 3070 safe_terminator = (u_int32_t)((((u_int32_t)address & 0x7) + (length & 0xF)) & 0xF); 3071 /* if it does not fall between 0x1 to 0x4 and 0x9 to 0xC then return */ 3072 if (safe_terminator == 0 || 3073 (safe_terminator > 4 && 3074 safe_terminator < 9) || 3075 (safe_terminator > 0xC && 3076 safe_terminator <= 0xF)) { 3077 desc_array->descriptor[0].address = address; 3078 desc_array->descriptor[0].length = length; 3079 desc_array->elements = 1; 3080 return desc_array->elements; 3081 } 3082 3083 desc_array->descriptor[0].address = address; 3084 desc_array->descriptor[0].length = length - 4; 3085 desc_array->descriptor[1].address = address + (length - 4); 3086 desc_array->descriptor[1].length = 4; 3087 desc_array->elements = 2; 3088 return desc_array->elements; 3089 } 3090 3091 /* 3092 * Disable the L0S and L1 LINK states. 3093 */ 3094 void 3095 em_disable_aspm(struct em_softc *sc) 3096 { 3097 int offset; 3098 pcireg_t val; 3099 3100 switch (sc->hw.mac_type) { 3101 case em_82571: 3102 case em_82572: 3103 case em_82573: 3104 case em_82574: 3105 break; 3106 default: 3107 return; 3108 } 3109 3110 if (!pci_get_capability(sc->osdep.em_pa.pa_pc, sc->osdep.em_pa.pa_tag, 3111 PCI_CAP_PCIEXPRESS, &offset, NULL)) 3112 return; 3113 3114 /* Disable PCIe Active State Power Management (ASPM). */ 3115 val = pci_conf_read(sc->osdep.em_pa.pa_pc, sc->osdep.em_pa.pa_tag, 3116 offset + PCI_PCIE_LCSR); 3117 3118 switch (sc->hw.mac_type) { 3119 case em_82571: 3120 case em_82572: 3121 val &= ~PCI_PCIE_LCSR_ASPM_L1; 3122 break; 3123 case em_82573: 3124 case em_82574: 3125 val &= ~(PCI_PCIE_LCSR_ASPM_L0S | 3126 PCI_PCIE_LCSR_ASPM_L1); 3127 break; 3128 default: 3129 break; 3130 } 3131 3132 pci_conf_write(sc->osdep.em_pa.pa_pc, sc->osdep.em_pa.pa_tag, 3133 offset + PCI_PCIE_LCSR, val); 3134 } 3135 3136 /* 3137 * em_flush_tx_ring - remove all descriptors from the tx_ring 3138 * 3139 * We want to clear all pending descriptors from the TX ring. 3140 * zeroing happens when the HW reads the regs. We assign the ring itself as 3141 * the data of the next descriptor. We don't care about the data we are about 3142 * to reset the HW. 3143 */ 3144 void 3145 em_flush_tx_ring(struct em_softc *sc) 3146 { 3147 uint32_t tctl, txd_lower = E1000_TXD_CMD_IFCS; 3148 uint16_t size = 512; 3149 struct em_tx_desc *txd; 3150 3151 KASSERT(sc->sc_tx_desc_ring != NULL); 3152 3153 tctl = EM_READ_REG(&sc->hw, E1000_TCTL); 3154 EM_WRITE_REG(&sc->hw, E1000_TCTL, tctl | E1000_TCTL_EN); 3155 3156 KASSERT(EM_READ_REG(&sc->hw, E1000_TDT) == sc->sc_tx_desc_head); 3157 3158 txd = &sc->sc_tx_desc_ring[sc->sc_tx_desc_head]; 3159 txd->buffer_addr = sc->sc_tx_dma.dma_map->dm_segs[0].ds_addr; 3160 txd->lower.data = htole32(txd_lower | size); 3161 txd->upper.data = 0; 3162 3163 /* flush descriptors to memory before notifying the HW */ 3164 bus_space_barrier(sc->osdep.mem_bus_space_tag, 3165 sc->osdep.mem_bus_space_handle, 0, 0, BUS_SPACE_BARRIER_WRITE); 3166 3167 if (++sc->sc_tx_desc_head == sc->sc_tx_slots) 3168 sc->sc_tx_desc_head = 0; 3169 3170 EM_WRITE_REG(&sc->hw, E1000_TDT, sc->sc_tx_desc_head); 3171 bus_space_barrier(sc->osdep.mem_bus_space_tag, sc->osdep.mem_bus_space_handle, 3172 0, 0, BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE); 3173 usec_delay(250); 3174 } 3175 3176 /* 3177 * em_flush_rx_ring - remove all descriptors from the rx_ring 3178 * 3179 * Mark all descriptors in the RX ring as consumed and disable the rx ring 3180 */ 3181 void 3182 em_flush_rx_ring(struct em_softc *sc) 3183 { 3184 uint32_t rctl, rxdctl; 3185 3186 rctl = EM_READ_REG(&sc->hw, E1000_RCTL); 3187 EM_WRITE_REG(&sc->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 3188 E1000_WRITE_FLUSH(&sc->hw); 3189 usec_delay(150); 3190 3191 rxdctl = EM_READ_REG(&sc->hw, E1000_RXDCTL); 3192 /* zero the lower 14 bits (prefetch and host thresholds) */ 3193 rxdctl &= 0xffffc000; 3194 /* 3195 * update thresholds: prefetch threshold to 31, host threshold to 1 3196 * and make sure the granularity is "descriptors" and not "cache lines" 3197 */ 3198 rxdctl |= (0x1F | (1 << 8) | E1000_RXDCTL_THRESH_UNIT_DESC); 3199 EM_WRITE_REG(&sc->hw, E1000_RXDCTL, rxdctl); 3200 3201 /* momentarily enable the RX ring for the changes to take effect */ 3202 EM_WRITE_REG(&sc->hw, E1000_RCTL, rctl | E1000_RCTL_EN); 3203 E1000_WRITE_FLUSH(&sc->hw); 3204 usec_delay(150); 3205 EM_WRITE_REG(&sc->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 3206 } 3207 3208 /* 3209 * em_flush_desc_rings - remove all descriptors from the descriptor rings 3210 * 3211 * In i219, the descriptor rings must be emptied before resetting the HW 3212 * or before changing the device state to D3 during runtime (runtime PM). 3213 * 3214 * Failure to do this will cause the HW to enter a unit hang state which can 3215 * only be released by PCI reset on the device 3216 * 3217 */ 3218 void 3219 em_flush_desc_rings(struct em_softc *sc) 3220 { 3221 struct pci_attach_args *pa = &sc->osdep.em_pa; 3222 uint32_t fextnvm11, tdlen; 3223 uint16_t hang_state; 3224 3225 /* First, disable MULR fix in FEXTNVM11 */ 3226 fextnvm11 = EM_READ_REG(&sc->hw, E1000_FEXTNVM11); 3227 fextnvm11 |= E1000_FEXTNVM11_DISABLE_MULR_FIX; 3228 EM_WRITE_REG(&sc->hw, E1000_FEXTNVM11, fextnvm11); 3229 3230 /* do nothing if we're not in faulty state, or if the queue is empty */ 3231 tdlen = EM_READ_REG(&sc->hw, E1000_TDLEN); 3232 hang_state = pci_conf_read(pa->pa_pc, pa->pa_tag, PCICFG_DESC_RING_STATUS); 3233 if (!(hang_state & FLUSH_DESC_REQUIRED) || !tdlen) 3234 return; 3235 em_flush_tx_ring(sc); 3236 3237 /* recheck, maybe the fault is caused by the rx ring */ 3238 hang_state = pci_conf_read(pa->pa_pc, pa->pa_tag, PCICFG_DESC_RING_STATUS); 3239 if (hang_state & FLUSH_DESC_REQUIRED) 3240 em_flush_rx_ring(sc); 3241 } 3242 3243 #ifndef SMALL_KERNEL 3244 /********************************************************************** 3245 * 3246 * Update the board statistics counters. 3247 * 3248 **********************************************************************/ 3249 void 3250 em_update_stats_counters(struct em_softc *sc) 3251 { 3252 struct ifnet *ifp = &sc->sc_ac.ac_if; 3253 3254 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, CRCERRS); 3255 sc->stats.mpc += E1000_READ_REG(&sc->hw, MPC); 3256 sc->stats.ecol += E1000_READ_REG(&sc->hw, ECOL); 3257 3258 sc->stats.latecol += E1000_READ_REG(&sc->hw, LATECOL); 3259 sc->stats.colc += E1000_READ_REG(&sc->hw, COLC); 3260 3261 sc->stats.ruc += E1000_READ_REG(&sc->hw, RUC); 3262 sc->stats.roc += E1000_READ_REG(&sc->hw, ROC); 3263 3264 if (sc->hw.mac_type >= em_82543) { 3265 sc->stats.algnerrc += 3266 E1000_READ_REG(&sc->hw, ALGNERRC); 3267 sc->stats.rxerrc += 3268 E1000_READ_REG(&sc->hw, RXERRC); 3269 sc->stats.cexterr += 3270 E1000_READ_REG(&sc->hw, CEXTERR); 3271 } 3272 3273 #ifdef EM_DEBUG 3274 if (sc->hw.media_type == em_media_type_copper || 3275 (E1000_READ_REG(&sc->hw, STATUS) & E1000_STATUS_LU)) { 3276 sc->stats.symerrs += E1000_READ_REG(&sc->hw, SYMERRS); 3277 sc->stats.sec += E1000_READ_REG(&sc->hw, SEC); 3278 } 3279 sc->stats.scc += E1000_READ_REG(&sc->hw, SCC); 3280 3281 sc->stats.mcc += E1000_READ_REG(&sc->hw, MCC); 3282 sc->stats.dc += E1000_READ_REG(&sc->hw, DC); 3283 sc->stats.rlec += E1000_READ_REG(&sc->hw, RLEC); 3284 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, XONRXC); 3285 sc->stats.xontxc += E1000_READ_REG(&sc->hw, XONTXC); 3286 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, XOFFRXC); 3287 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, XOFFTXC); 3288 sc->stats.fcruc += E1000_READ_REG(&sc->hw, FCRUC); 3289 sc->stats.prc64 += E1000_READ_REG(&sc->hw, PRC64); 3290 sc->stats.prc127 += E1000_READ_REG(&sc->hw, PRC127); 3291 sc->stats.prc255 += E1000_READ_REG(&sc->hw, PRC255); 3292 sc->stats.prc511 += E1000_READ_REG(&sc->hw, PRC511); 3293 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, PRC1023); 3294 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, PRC1522); 3295 sc->stats.gprc += E1000_READ_REG(&sc->hw, GPRC); 3296 sc->stats.bprc += E1000_READ_REG(&sc->hw, BPRC); 3297 sc->stats.mprc += E1000_READ_REG(&sc->hw, MPRC); 3298 sc->stats.gptc += E1000_READ_REG(&sc->hw, GPTC); 3299 3300 /* For the 64-bit byte counters the low dword must be read first. */ 3301 /* Both registers clear on the read of the high dword */ 3302 3303 sc->stats.gorcl += E1000_READ_REG(&sc->hw, GORCL); 3304 sc->stats.gorch += E1000_READ_REG(&sc->hw, GORCH); 3305 sc->stats.gotcl += E1000_READ_REG(&sc->hw, GOTCL); 3306 sc->stats.gotch += E1000_READ_REG(&sc->hw, GOTCH); 3307 3308 sc->stats.rnbc += E1000_READ_REG(&sc->hw, RNBC); 3309 sc->stats.rfc += E1000_READ_REG(&sc->hw, RFC); 3310 sc->stats.rjc += E1000_READ_REG(&sc->hw, RJC); 3311 3312 sc->stats.torl += E1000_READ_REG(&sc->hw, TORL); 3313 sc->stats.torh += E1000_READ_REG(&sc->hw, TORH); 3314 sc->stats.totl += E1000_READ_REG(&sc->hw, TOTL); 3315 sc->stats.toth += E1000_READ_REG(&sc->hw, TOTH); 3316 3317 sc->stats.tpr += E1000_READ_REG(&sc->hw, TPR); 3318 sc->stats.tpt += E1000_READ_REG(&sc->hw, TPT); 3319 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, PTC64); 3320 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, PTC127); 3321 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, PTC255); 3322 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, PTC511); 3323 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, PTC1023); 3324 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, PTC1522); 3325 sc->stats.mptc += E1000_READ_REG(&sc->hw, MPTC); 3326 sc->stats.bptc += E1000_READ_REG(&sc->hw, BPTC); 3327 3328 if (sc->hw.mac_type >= em_82543) { 3329 sc->stats.tncrs += 3330 E1000_READ_REG(&sc->hw, TNCRS); 3331 sc->stats.tsctc += 3332 E1000_READ_REG(&sc->hw, TSCTC); 3333 sc->stats.tsctfc += 3334 E1000_READ_REG(&sc->hw, TSCTFC); 3335 } 3336 #endif 3337 3338 /* Fill out the OS statistics structure */ 3339 ifp->if_collisions = sc->stats.colc; 3340 3341 /* Rx Errors */ 3342 ifp->if_ierrors = 3343 sc->dropped_pkts + 3344 sc->stats.rxerrc + 3345 sc->stats.crcerrs + 3346 sc->stats.algnerrc + 3347 sc->stats.ruc + sc->stats.roc + 3348 sc->stats.mpc + sc->stats.cexterr + 3349 sc->rx_overruns; 3350 3351 /* Tx Errors */ 3352 ifp->if_oerrors = sc->stats.ecol + sc->stats.latecol + 3353 sc->watchdog_events; 3354 } 3355 3356 #ifdef EM_DEBUG 3357 /********************************************************************** 3358 * 3359 * This routine is called only when IFF_DEBUG is enabled. 3360 * This routine provides a way to take a look at important statistics 3361 * maintained by the driver and hardware. 3362 * 3363 **********************************************************************/ 3364 void 3365 em_print_hw_stats(struct em_softc *sc) 3366 { 3367 const char * const unit = DEVNAME(sc); 3368 3369 printf("%s: Excessive collisions = %lld\n", unit, 3370 (long long)sc->stats.ecol); 3371 printf("%s: Symbol errors = %lld\n", unit, 3372 (long long)sc->stats.symerrs); 3373 printf("%s: Sequence errors = %lld\n", unit, 3374 (long long)sc->stats.sec); 3375 printf("%s: Defer count = %lld\n", unit, 3376 (long long)sc->stats.dc); 3377 3378 printf("%s: Missed Packets = %lld\n", unit, 3379 (long long)sc->stats.mpc); 3380 printf("%s: Receive No Buffers = %lld\n", unit, 3381 (long long)sc->stats.rnbc); 3382 /* RLEC is inaccurate on some hardware, calculate our own */ 3383 printf("%s: Receive Length Errors = %lld\n", unit, 3384 ((long long)sc->stats.roc + 3385 (long long)sc->stats.ruc)); 3386 printf("%s: Receive errors = %lld\n", unit, 3387 (long long)sc->stats.rxerrc); 3388 printf("%s: Crc errors = %lld\n", unit, 3389 (long long)sc->stats.crcerrs); 3390 printf("%s: Alignment errors = %lld\n", unit, 3391 (long long)sc->stats.algnerrc); 3392 printf("%s: Carrier extension errors = %lld\n", unit, 3393 (long long)sc->stats.cexterr); 3394 3395 printf("%s: RX overruns = %ld\n", unit, 3396 sc->rx_overruns); 3397 printf("%s: watchdog timeouts = %ld\n", unit, 3398 sc->watchdog_events); 3399 3400 printf("%s: XON Rcvd = %lld\n", unit, 3401 (long long)sc->stats.xonrxc); 3402 printf("%s: XON Xmtd = %lld\n", unit, 3403 (long long)sc->stats.xontxc); 3404 printf("%s: XOFF Rcvd = %lld\n", unit, 3405 (long long)sc->stats.xoffrxc); 3406 printf("%s: XOFF Xmtd = %lld\n", unit, 3407 (long long)sc->stats.xofftxc); 3408 3409 printf("%s: Good Packets Rcvd = %lld\n", unit, 3410 (long long)sc->stats.gprc); 3411 printf("%s: Good Packets Xmtd = %lld\n", unit, 3412 (long long)sc->stats.gptc); 3413 } 3414 #endif 3415 #endif /* !SMALL_KERNEL */ 3416