1 /************************************************************************** 2 3 Copyright (c) 2001-2003, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ***************************************************************************/ 33 34 /* $OpenBSD: if_em.c,v 1.333 2017/01/22 10:17:38 dlg Exp $ */ 35 /* $FreeBSD: if_em.c,v 1.46 2004/09/29 18:28:28 mlaier Exp $ */ 36 37 #include <dev/pci/if_em.h> 38 #include <dev/pci/if_em_soc.h> 39 40 /********************************************************************* 41 * Driver version 42 *********************************************************************/ 43 44 #define EM_DRIVER_VERSION "6.2.9" 45 46 /********************************************************************* 47 * PCI Device ID Table 48 *********************************************************************/ 49 const struct pci_matchid em_devices[] = { 50 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80003ES2LAN_CPR_DPT }, 51 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80003ES2LAN_SDS_DPT }, 52 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80003ES2LAN_CPR_SPT }, 53 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80003ES2LAN_SDS_SPT }, 54 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM }, 55 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM_LOM }, 56 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP }, 57 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LOM }, 58 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LP }, 59 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI }, 60 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI_MOBILE }, 61 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541ER }, 62 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541ER_LOM }, 63 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI }, 64 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI_LF }, 65 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI_MOBILE }, 66 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82542 }, 67 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_COPPER }, 68 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_FIBER }, 69 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_COPPER }, 70 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_FIBER }, 71 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_COPPER }, 72 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_LOM }, 73 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_COPPER }, 74 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_FIBER }, 75 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_COPPER }, 76 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_FIBER }, 77 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_SERDES }, 78 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_COPPER }, 79 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_FIBER }, 80 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_QUAD_CPR }, 81 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_COPPER }, 82 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_FIBER }, 83 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_PCIE }, 84 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_QUAD_CPR }, 85 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_QUAD_CPR_K }, 86 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_SERDES }, 87 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_2 }, 88 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547EI }, 89 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547EI_MOBILE }, 90 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547GI }, 91 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_AF }, 92 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_AT }, 93 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_COPPER }, 94 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_FIBER }, 95 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_QUAD_CPR }, 96 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_QUAD_CPR_LP }, 97 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_QUAD_FBR }, 98 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_SERDES }, 99 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_SDS_DUAL }, 100 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_SDS_QUAD }, 101 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571PT_QUAD_CPR }, 102 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI_COPPER }, 103 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI_FIBER }, 104 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI_SERDES }, 105 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI }, 106 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573E }, 107 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573E_IAMT }, 108 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573E_PM }, 109 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573L }, 110 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573L_PL_1 }, 111 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573L_PL_2 }, 112 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573V_PM }, 113 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82574L }, 114 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82574LA }, 115 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82575EB_COPPER }, 116 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82575EB_SERDES }, 117 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82575GB_QUAD_CPR }, 118 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82575GB_QP_PM }, 119 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576 }, 120 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_FIBER }, 121 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_SERDES }, 122 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_QUAD_COPPER }, 123 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_QUAD_CU_ET2 }, 124 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_NS }, 125 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_NS_SERDES }, 126 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_SERDES_QUAD }, 127 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82577LC }, 128 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82577LM }, 129 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82578DC }, 130 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82578DM }, 131 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82579LM }, 132 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82579V }, 133 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_COPPER }, 134 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_FIBER }, 135 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_SERDES }, 136 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_SGMII }, 137 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_COPPER_NF }, 138 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_SERDES_NF }, 139 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I211_COPPER }, 140 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I217_LM }, 141 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I217_V }, 142 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_LM }, 143 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_LM_2 }, 144 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_LM_3 }, 145 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_V }, 146 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_V_2 }, 147 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_V_3 }, 148 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_LM }, 149 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_V }, 150 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_LM2 }, 151 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_V2 }, 152 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_COPPER }, 153 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_FIBER }, 154 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_SERDES }, 155 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_SGMII }, 156 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_COPPER_DUAL }, 157 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_QUAD_FIBER }, 158 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCC_SGMII }, 159 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCC_SERDES }, 160 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCC_BPLANE }, 161 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCC_SFP }, 162 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82583V }, 163 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I350_COPPER }, 164 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I350_FIBER }, 165 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I350_SERDES }, 166 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I350_SGMII }, 167 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I354_BP_1GBPS }, 168 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I354_BP_2_5GBPS }, 169 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I354_SGMII }, 170 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_82567V_3 }, 171 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_IFE }, 172 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_IFE_G }, 173 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_IFE_GT }, 174 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_IGP_AMT }, 175 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_IGP_C }, 176 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_IGP_M }, 177 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_IGP_M_AMT }, 178 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_BM }, 179 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IFE }, 180 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IFE_G }, 181 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IFE_GT }, 182 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IGP_AMT }, 183 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IGP_C }, 184 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IGP_M }, 185 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IGP_M_AMT }, 186 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IGP_M_V }, 187 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH10_D_BM_LF }, 188 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH10_D_BM_LM }, 189 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH10_R_BM_LF }, 190 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH10_R_BM_LM }, 191 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH10_R_BM_V }, 192 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EP80579_LAN_1 }, 193 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EP80579_LAN_2 }, 194 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EP80579_LAN_3 }, 195 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EP80579_LAN_4 }, 196 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EP80579_LAN_5 }, 197 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EP80579_LAN_6 } 198 }; 199 200 /********************************************************************* 201 * Function prototypes 202 *********************************************************************/ 203 int em_probe(struct device *, void *, void *); 204 void em_attach(struct device *, struct device *, void *); 205 void em_defer_attach(struct device*); 206 int em_detach(struct device *, int); 207 int em_activate(struct device *, int); 208 int em_intr(void *); 209 void em_start(struct ifnet *); 210 int em_ioctl(struct ifnet *, u_long, caddr_t); 211 void em_watchdog(struct ifnet *); 212 void em_init(void *); 213 void em_stop(void *, int); 214 void em_media_status(struct ifnet *, struct ifmediareq *); 215 int em_media_change(struct ifnet *); 216 uint64_t em_flowstatus(struct em_softc *); 217 void em_identify_hardware(struct em_softc *); 218 int em_allocate_pci_resources(struct em_softc *); 219 void em_free_pci_resources(struct em_softc *); 220 void em_local_timer(void *); 221 int em_hardware_init(struct em_softc *); 222 void em_setup_interface(struct em_softc *); 223 int em_setup_transmit_structures(struct em_softc *); 224 void em_initialize_transmit_unit(struct em_softc *); 225 int em_setup_receive_structures(struct em_softc *); 226 void em_initialize_receive_unit(struct em_softc *); 227 void em_enable_intr(struct em_softc *); 228 void em_disable_intr(struct em_softc *); 229 void em_free_transmit_structures(struct em_softc *); 230 void em_free_receive_structures(struct em_softc *); 231 void em_update_stats_counters(struct em_softc *); 232 void em_disable_aspm(struct em_softc *); 233 void em_txeof(struct em_softc *); 234 int em_allocate_receive_structures(struct em_softc *); 235 int em_allocate_transmit_structures(struct em_softc *); 236 int em_rxfill(struct em_softc *); 237 int em_rxeof(struct em_softc *); 238 void em_receive_checksum(struct em_softc *, struct em_rx_desc *, 239 struct mbuf *); 240 u_int em_transmit_checksum_setup(struct em_softc *, struct mbuf *, u_int, 241 u_int32_t *, u_int32_t *); 242 void em_iff(struct em_softc *); 243 #ifdef EM_DEBUG 244 void em_print_hw_stats(struct em_softc *); 245 #endif 246 void em_update_link_status(struct em_softc *); 247 int em_get_buf(struct em_softc *, int); 248 void em_enable_hw_vlans(struct em_softc *); 249 u_int em_encap(struct em_softc *, struct mbuf *); 250 void em_smartspeed(struct em_softc *); 251 int em_82547_fifo_workaround(struct em_softc *, int); 252 void em_82547_update_fifo_head(struct em_softc *, int); 253 int em_82547_tx_fifo_reset(struct em_softc *); 254 void em_82547_move_tail(void *arg); 255 void em_82547_move_tail_locked(struct em_softc *); 256 int em_dma_malloc(struct em_softc *, bus_size_t, struct em_dma_alloc *); 257 void em_dma_free(struct em_softc *, struct em_dma_alloc *); 258 u_int32_t em_fill_descriptors(u_int64_t address, u_int32_t length, 259 PDESC_ARRAY desc_array); 260 void em_flush_tx_ring(struct em_softc *); 261 void em_flush_rx_ring(struct em_softc *); 262 void em_flush_desc_rings(struct em_softc *); 263 264 /********************************************************************* 265 * OpenBSD Device Interface Entry Points 266 *********************************************************************/ 267 268 struct cfattach em_ca = { 269 sizeof(struct em_softc), em_probe, em_attach, em_detach, 270 em_activate 271 }; 272 273 struct cfdriver em_cd = { 274 NULL, "em", DV_IFNET 275 }; 276 277 static int em_smart_pwr_down = FALSE; 278 279 /********************************************************************* 280 * Device identification routine 281 * 282 * em_probe determines if the driver should be loaded on 283 * adapter based on PCI vendor/device id of the adapter. 284 * 285 * return 0 on no match, positive on match 286 *********************************************************************/ 287 288 int 289 em_probe(struct device *parent, void *match, void *aux) 290 { 291 INIT_DEBUGOUT("em_probe: begin"); 292 293 return (pci_matchbyid((struct pci_attach_args *)aux, em_devices, 294 nitems(em_devices))); 295 } 296 297 void 298 em_defer_attach(struct device *self) 299 { 300 struct em_softc *sc = (struct em_softc *)self; 301 struct pci_attach_args *pa = &sc->osdep.em_pa; 302 pci_chipset_tag_t pc = pa->pa_pc; 303 void *gcu; 304 305 INIT_DEBUGOUT("em_defer_attach: begin"); 306 307 if ((gcu = em_lookup_gcu(self)) == 0) { 308 printf("%s: No GCU found, defered attachment failed\n", 309 DEVNAME(sc)); 310 311 if (sc->sc_intrhand) 312 pci_intr_disestablish(pc, sc->sc_intrhand); 313 sc->sc_intrhand = 0; 314 315 em_stop(sc, 1); 316 317 em_free_pci_resources(sc); 318 319 sc->sc_rx_desc_ring = NULL; 320 em_dma_free(sc, &sc->sc_rx_dma); 321 sc->sc_tx_desc_ring = NULL; 322 em_dma_free(sc, &sc->sc_tx_dma); 323 324 return; 325 } 326 327 sc->hw.gcu = gcu; 328 329 em_attach_miibus(self); 330 331 em_setup_interface(sc); 332 333 em_setup_link(&sc->hw); 334 335 em_update_link_status(sc); 336 } 337 338 /********************************************************************* 339 * Device initialization routine 340 * 341 * The attach entry point is called when the driver is being loaded. 342 * This routine identifies the type of hardware, allocates all resources 343 * and initializes the hardware. 344 * 345 *********************************************************************/ 346 347 void 348 em_attach(struct device *parent, struct device *self, void *aux) 349 { 350 struct pci_attach_args *pa = aux; 351 struct em_softc *sc; 352 int defer = 0; 353 354 INIT_DEBUGOUT("em_attach: begin"); 355 356 sc = (struct em_softc *)self; 357 sc->sc_dmat = pa->pa_dmat; 358 sc->osdep.em_pa = *pa; 359 360 timeout_set(&sc->timer_handle, em_local_timer, sc); 361 timeout_set(&sc->tx_fifo_timer_handle, em_82547_move_tail, sc); 362 363 /* Determine hardware revision */ 364 em_identify_hardware(sc); 365 366 /* 367 * Only use MSI on the newer PCIe parts, with the exception 368 * of 82571/82572 due to "Byte Enables 2 and 3 Are Not Set" errata 369 */ 370 if (sc->hw.mac_type <= em_82572) 371 sc->osdep.em_pa.pa_flags &= ~PCI_FLAGS_MSI_ENABLED; 372 373 /* Parameters (to be read from user) */ 374 if (sc->hw.mac_type >= em_82544) { 375 sc->sc_tx_slots = EM_MAX_TXD; 376 sc->sc_rx_slots = EM_MAX_RXD; 377 } else { 378 sc->sc_tx_slots = EM_MAX_TXD_82543; 379 sc->sc_rx_slots = EM_MAX_RXD_82543; 380 } 381 sc->tx_int_delay = EM_TIDV; 382 sc->tx_abs_int_delay = EM_TADV; 383 sc->rx_int_delay = EM_RDTR; 384 sc->rx_abs_int_delay = EM_RADV; 385 sc->hw.autoneg = DO_AUTO_NEG; 386 sc->hw.wait_autoneg_complete = WAIT_FOR_AUTO_NEG_DEFAULT; 387 sc->hw.autoneg_advertised = AUTONEG_ADV_DEFAULT; 388 sc->hw.tbi_compatibility_en = TRUE; 389 sc->sc_rx_buffer_len = EM_RXBUFFER_2048; 390 391 sc->hw.phy_init_script = 1; 392 sc->hw.phy_reset_disable = FALSE; 393 394 #ifndef EM_MASTER_SLAVE 395 sc->hw.master_slave = em_ms_hw_default; 396 #else 397 sc->hw.master_slave = EM_MASTER_SLAVE; 398 #endif 399 400 /* 401 * This controls when hardware reports transmit completion 402 * status. 403 */ 404 sc->hw.report_tx_early = 1; 405 406 if (em_allocate_pci_resources(sc)) 407 goto err_pci; 408 409 /* Initialize eeprom parameters */ 410 em_init_eeprom_params(&sc->hw); 411 412 /* 413 * Set the max frame size assuming standard Ethernet 414 * sized frames. 415 */ 416 switch (sc->hw.mac_type) { 417 case em_82573: 418 { 419 uint16_t eeprom_data = 0; 420 421 /* 422 * 82573 only supports Jumbo frames 423 * if ASPM is disabled. 424 */ 425 em_read_eeprom(&sc->hw, EEPROM_INIT_3GIO_3, 426 1, &eeprom_data); 427 if (eeprom_data & EEPROM_WORD1A_ASPM_MASK) { 428 sc->hw.max_frame_size = ETHER_MAX_LEN; 429 break; 430 } 431 /* Allow Jumbo frames */ 432 /* FALLTHROUGH */ 433 } 434 case em_82571: 435 case em_82572: 436 case em_82574: 437 case em_82575: 438 case em_82580: 439 case em_i210: 440 case em_i350: 441 case em_ich9lan: 442 case em_ich10lan: 443 case em_pch2lan: 444 case em_pch_lpt: 445 case em_pch_spt: 446 case em_80003es2lan: 447 /* 9K Jumbo Frame size */ 448 sc->hw.max_frame_size = 9234; 449 break; 450 case em_pchlan: 451 sc->hw.max_frame_size = 4096; 452 break; 453 case em_82542_rev2_0: 454 case em_82542_rev2_1: 455 case em_ich8lan: 456 /* Adapters that do not support Jumbo frames */ 457 sc->hw.max_frame_size = ETHER_MAX_LEN; 458 break; 459 default: 460 sc->hw.max_frame_size = 461 MAX_JUMBO_FRAME_SIZE; 462 } 463 464 sc->hw.min_frame_size = 465 ETHER_MIN_LEN + ETHER_CRC_LEN; 466 467 /* Allocate Transmit Descriptor ring */ 468 if (em_dma_malloc(sc, sc->sc_tx_slots * sizeof(struct em_tx_desc), 469 &sc->sc_tx_dma) != 0) { 470 printf("%s: Unable to allocate tx_desc memory\n", 471 DEVNAME(sc)); 472 goto err_tx_desc; 473 } 474 sc->sc_tx_desc_ring = (struct em_tx_desc *)sc->sc_tx_dma.dma_vaddr; 475 476 /* Allocate Receive Descriptor ring */ 477 if (em_dma_malloc(sc, sc->sc_rx_slots * sizeof(struct em_rx_desc), 478 &sc->sc_rx_dma) != 0) { 479 printf("%s: Unable to allocate rx_desc memory\n", 480 DEVNAME(sc)); 481 goto err_rx_desc; 482 } 483 sc->sc_rx_desc_ring = (struct em_rx_desc *)sc->sc_rx_dma.dma_vaddr; 484 485 /* Initialize the hardware */ 486 if ((defer = em_hardware_init(sc))) { 487 if (defer == EAGAIN) 488 config_defer(self, em_defer_attach); 489 else { 490 printf("%s: Unable to initialize the hardware\n", 491 DEVNAME(sc)); 492 goto err_hw_init; 493 } 494 } 495 496 if (sc->hw.mac_type == em_80003es2lan || sc->hw.mac_type == em_82575 || 497 sc->hw.mac_type == em_82580 || sc->hw.mac_type == em_i210 || 498 sc->hw.mac_type == em_i350) { 499 uint32_t reg = EM_READ_REG(&sc->hw, E1000_STATUS); 500 sc->hw.bus_func = (reg & E1000_STATUS_FUNC_MASK) >> 501 E1000_STATUS_FUNC_SHIFT; 502 503 switch (sc->hw.bus_func) { 504 case 0: 505 sc->hw.swfw = E1000_SWFW_PHY0_SM; 506 break; 507 case 1: 508 sc->hw.swfw = E1000_SWFW_PHY1_SM; 509 break; 510 case 2: 511 sc->hw.swfw = E1000_SWFW_PHY2_SM; 512 break; 513 case 3: 514 sc->hw.swfw = E1000_SWFW_PHY3_SM; 515 break; 516 } 517 } else { 518 sc->hw.bus_func = 0; 519 } 520 521 /* Copy the permanent MAC address out of the EEPROM */ 522 if (em_read_mac_addr(&sc->hw) < 0) { 523 printf("%s: EEPROM read error while reading mac address\n", 524 DEVNAME(sc)); 525 goto err_mac_addr; 526 } 527 528 bcopy(sc->hw.mac_addr, sc->sc_ac.ac_enaddr, ETHER_ADDR_LEN); 529 530 /* Setup OS specific network interface */ 531 if (!defer) 532 em_setup_interface(sc); 533 534 /* Initialize statistics */ 535 em_clear_hw_cntrs(&sc->hw); 536 #ifndef SMALL_KERNEL 537 em_update_stats_counters(sc); 538 #endif 539 sc->hw.get_link_status = 1; 540 if (!defer) 541 em_update_link_status(sc); 542 543 printf(", address %s\n", ether_sprintf(sc->sc_ac.ac_enaddr)); 544 545 /* Indicate SOL/IDER usage */ 546 if (em_check_phy_reset_block(&sc->hw)) 547 printf("%s: PHY reset is blocked due to SOL/IDER session.\n", 548 DEVNAME(sc)); 549 550 /* Identify 82544 on PCI-X */ 551 em_get_bus_info(&sc->hw); 552 if (sc->hw.bus_type == em_bus_type_pcix && 553 sc->hw.mac_type == em_82544) 554 sc->pcix_82544 = TRUE; 555 else 556 sc->pcix_82544 = FALSE; 557 558 sc->hw.icp_xxxx_is_link_up = FALSE; 559 560 INIT_DEBUGOUT("em_attach: end"); 561 return; 562 563 err_mac_addr: 564 err_hw_init: 565 sc->sc_rx_desc_ring = NULL; 566 em_dma_free(sc, &sc->sc_rx_dma); 567 err_rx_desc: 568 sc->sc_tx_desc_ring = NULL; 569 em_dma_free(sc, &sc->sc_tx_dma); 570 err_tx_desc: 571 err_pci: 572 em_free_pci_resources(sc); 573 } 574 575 /********************************************************************* 576 * Transmit entry point 577 * 578 * em_start is called by the stack to initiate a transmit. 579 * The driver will remain in this routine as long as there are 580 * packets to transmit and transmit resources are available. 581 * In case resources are not available stack is notified and 582 * the packet is requeued. 583 **********************************************************************/ 584 585 void 586 em_start(struct ifnet *ifp) 587 { 588 struct em_softc *sc = ifp->if_softc; 589 u_int head, free, used; 590 struct mbuf *m; 591 int post = 0; 592 593 if (!sc->link_active) { 594 IFQ_PURGE(&ifp->if_snd); 595 return; 596 } 597 598 /* calculate free space */ 599 head = sc->sc_tx_desc_head; 600 free = sc->sc_tx_desc_tail; 601 if (free <= head) 602 free += sc->sc_tx_slots; 603 free -= head; 604 605 if (sc->hw.mac_type != em_82547) { 606 bus_dmamap_sync(sc->sc_dmat, sc->sc_tx_dma.dma_map, 607 0, sc->sc_tx_dma.dma_map->dm_mapsize, 608 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 609 } 610 611 for (;;) { 612 /* use 2 because cksum setup can use an extra slot */ 613 if (EM_MAX_SCATTER + 2 > free) { 614 ifq_set_oactive(&ifp->if_snd); 615 break; 616 } 617 618 m = ifq_dequeue(&ifp->if_snd); 619 if (m == NULL) 620 break; 621 622 used = em_encap(sc, m); 623 if (used == 0) { 624 m_freem(m); 625 continue; 626 } 627 628 KASSERT(used <= free); 629 630 free -= used; 631 632 #if NBPFILTER > 0 633 /* Send a copy of the frame to the BPF listener */ 634 if (ifp->if_bpf) 635 bpf_mtap_ether(ifp->if_bpf, m, BPF_DIRECTION_OUT); 636 #endif 637 638 /* Set timeout in case hardware has problems transmitting */ 639 ifp->if_timer = EM_TX_TIMEOUT; 640 641 if (sc->hw.mac_type == em_82547) { 642 int len = m->m_pkthdr.len; 643 644 if (sc->link_duplex == HALF_DUPLEX) 645 em_82547_move_tail_locked(sc); 646 else { 647 E1000_WRITE_REG(&sc->hw, TDT, 648 sc->sc_tx_desc_head); 649 em_82547_update_fifo_head(sc, len); 650 } 651 } 652 653 post = 1; 654 } 655 656 if (sc->hw.mac_type != em_82547) { 657 bus_dmamap_sync(sc->sc_dmat, sc->sc_tx_dma.dma_map, 658 0, sc->sc_tx_dma.dma_map->dm_mapsize, 659 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 660 /* 661 * Advance the Transmit Descriptor Tail (Tdt), 662 * this tells the E1000 that this frame is 663 * available to transmit. 664 */ 665 if (post) 666 E1000_WRITE_REG(&sc->hw, TDT, sc->sc_tx_desc_head); 667 } 668 } 669 670 /********************************************************************* 671 * Ioctl entry point 672 * 673 * em_ioctl is called when the user wants to configure the 674 * interface. 675 * 676 * return 0 on success, positive on failure 677 **********************************************************************/ 678 679 int 680 em_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 681 { 682 int error = 0; 683 struct ifreq *ifr = (struct ifreq *) data; 684 struct em_softc *sc = ifp->if_softc; 685 int s; 686 687 s = splnet(); 688 689 switch (command) { 690 case SIOCSIFADDR: 691 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFADDR (Set Interface " 692 "Addr)"); 693 if (!(ifp->if_flags & IFF_UP)) { 694 ifp->if_flags |= IFF_UP; 695 em_init(sc); 696 } 697 break; 698 699 case SIOCSIFFLAGS: 700 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFFLAGS (Set Interface Flags)"); 701 if (ifp->if_flags & IFF_UP) { 702 if (ifp->if_flags & IFF_RUNNING) 703 error = ENETRESET; 704 else 705 em_init(sc); 706 } else { 707 if (ifp->if_flags & IFF_RUNNING) 708 em_stop(sc, 0); 709 } 710 break; 711 712 case SIOCSIFMEDIA: 713 /* Check SOL/IDER usage */ 714 if (em_check_phy_reset_block(&sc->hw)) { 715 printf("%s: Media change is blocked due to SOL/IDER session.\n", 716 DEVNAME(sc)); 717 break; 718 } 719 case SIOCGIFMEDIA: 720 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCxIFMEDIA (Get/Set Interface Media)"); 721 error = ifmedia_ioctl(ifp, ifr, &sc->media, command); 722 break; 723 724 case SIOCGIFRXR: 725 error = if_rxr_ioctl((struct if_rxrinfo *)ifr->ifr_data, 726 NULL, EM_MCLBYTES, &sc->sc_rx_ring); 727 break; 728 729 default: 730 error = ether_ioctl(ifp, &sc->sc_ac, command, data); 731 } 732 733 if (error == ENETRESET) { 734 if (ifp->if_flags & IFF_RUNNING) { 735 em_disable_intr(sc); 736 em_iff(sc); 737 if (sc->hw.mac_type == em_82542_rev2_0) 738 em_initialize_receive_unit(sc); 739 em_enable_intr(sc); 740 } 741 error = 0; 742 } 743 744 splx(s); 745 return (error); 746 } 747 748 /********************************************************************* 749 * Watchdog entry point 750 * 751 * This routine is called whenever hardware quits transmitting. 752 * 753 **********************************************************************/ 754 755 void 756 em_watchdog(struct ifnet *ifp) 757 { 758 struct em_softc *sc = ifp->if_softc; 759 760 /* If we are in this routine because of pause frames, then 761 * don't reset the hardware. 762 */ 763 if (E1000_READ_REG(&sc->hw, STATUS) & E1000_STATUS_TXOFF) { 764 ifp->if_timer = EM_TX_TIMEOUT; 765 return; 766 } 767 printf("%s: watchdog: head %u tail %u TDH %u TDT %u\n", 768 DEVNAME(sc), 769 sc->sc_tx_desc_head, sc->sc_tx_desc_tail, 770 E1000_READ_REG(&sc->hw, TDH), E1000_READ_REG(&sc->hw, TDT)); 771 772 em_init(sc); 773 774 sc->watchdog_events++; 775 } 776 777 /********************************************************************* 778 * Init entry point 779 * 780 * This routine is used in two ways. It is used by the stack as 781 * init entry point in network interface structure. It is also used 782 * by the driver as a hw/sw initialization routine to get to a 783 * consistent state. 784 * 785 **********************************************************************/ 786 787 void 788 em_init(void *arg) 789 { 790 struct em_softc *sc = arg; 791 struct ifnet *ifp = &sc->sc_ac.ac_if; 792 uint32_t pba; 793 int s; 794 795 s = splnet(); 796 797 INIT_DEBUGOUT("em_init: begin"); 798 799 em_stop(sc, 0); 800 801 /* 802 * Packet Buffer Allocation (PBA) 803 * Writing PBA sets the receive portion of the buffer 804 * the remainder is used for the transmit buffer. 805 * 806 * Devices before the 82547 had a Packet Buffer of 64K. 807 * Default allocation: PBA=48K for Rx, leaving 16K for Tx. 808 * After the 82547 the buffer was reduced to 40K. 809 * Default allocation: PBA=30K for Rx, leaving 10K for Tx. 810 * Note: default does not leave enough room for Jumbo Frame >10k. 811 */ 812 switch (sc->hw.mac_type) { 813 case em_82547: 814 case em_82547_rev_2: /* 82547: Total Packet Buffer is 40K */ 815 if (sc->hw.max_frame_size > EM_RXBUFFER_8192) 816 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 817 else 818 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 819 sc->tx_fifo_head = 0; 820 sc->tx_head_addr = pba << EM_TX_HEAD_ADDR_SHIFT; 821 sc->tx_fifo_size = (E1000_PBA_40K - pba) << EM_PBA_BYTES_SHIFT; 822 break; 823 case em_82571: 824 case em_82572: /* Total Packet Buffer on these is 48k */ 825 case em_82575: 826 case em_82580: 827 case em_80003es2lan: 828 case em_i350: 829 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 830 break; 831 case em_i210: 832 pba = E1000_PBA_34K; 833 break; 834 case em_82573: /* 82573: Total Packet Buffer is 32K */ 835 /* Jumbo frames not supported */ 836 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 837 break; 838 case em_82574: /* Total Packet Buffer is 40k */ 839 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */ 840 break; 841 case em_ich8lan: 842 pba = E1000_PBA_8K; 843 break; 844 case em_ich9lan: 845 case em_ich10lan: 846 /* Boost Receive side for jumbo frames */ 847 if (sc->hw.max_frame_size > EM_RXBUFFER_4096) 848 pba = E1000_PBA_14K; 849 else 850 pba = E1000_PBA_10K; 851 break; 852 case em_pchlan: 853 case em_pch2lan: 854 case em_pch_lpt: 855 case em_pch_spt: 856 pba = E1000_PBA_26K; 857 break; 858 default: 859 /* Devices before 82547 had a Packet Buffer of 64K. */ 860 if (sc->hw.max_frame_size > EM_RXBUFFER_8192) 861 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 862 else 863 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 864 } 865 INIT_DEBUGOUT1("em_init: pba=%dK",pba); 866 E1000_WRITE_REG(&sc->hw, PBA, pba); 867 868 /* Get the latest mac address, User can use a LAA */ 869 bcopy(sc->sc_ac.ac_enaddr, sc->hw.mac_addr, ETHER_ADDR_LEN); 870 871 /* Initialize the hardware */ 872 if (em_hardware_init(sc)) { 873 printf("%s: Unable to initialize the hardware\n", 874 DEVNAME(sc)); 875 splx(s); 876 return; 877 } 878 em_update_link_status(sc); 879 880 E1000_WRITE_REG(&sc->hw, VET, ETHERTYPE_VLAN); 881 if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) 882 em_enable_hw_vlans(sc); 883 884 /* Prepare transmit descriptors and buffers */ 885 if (em_setup_transmit_structures(sc)) { 886 printf("%s: Could not setup transmit structures\n", 887 DEVNAME(sc)); 888 em_stop(sc, 0); 889 splx(s); 890 return; 891 } 892 em_initialize_transmit_unit(sc); 893 894 /* Prepare receive descriptors and buffers */ 895 if (em_setup_receive_structures(sc)) { 896 printf("%s: Could not setup receive structures\n", 897 DEVNAME(sc)); 898 em_stop(sc, 0); 899 splx(s); 900 return; 901 } 902 em_initialize_receive_unit(sc); 903 904 /* Program promiscuous mode and multicast filters. */ 905 em_iff(sc); 906 907 ifp->if_flags |= IFF_RUNNING; 908 ifq_clr_oactive(&ifp->if_snd); 909 910 timeout_add_sec(&sc->timer_handle, 1); 911 em_clear_hw_cntrs(&sc->hw); 912 em_enable_intr(sc); 913 914 /* Don't reset the phy next time init gets called */ 915 sc->hw.phy_reset_disable = TRUE; 916 917 splx(s); 918 } 919 920 /********************************************************************* 921 * 922 * Interrupt Service routine 923 * 924 **********************************************************************/ 925 int 926 em_intr(void *arg) 927 { 928 struct em_softc *sc = arg; 929 struct ifnet *ifp = &sc->sc_ac.ac_if; 930 u_int32_t reg_icr, test_icr; 931 932 test_icr = reg_icr = E1000_READ_REG(&sc->hw, ICR); 933 if (sc->hw.mac_type >= em_82571) 934 test_icr = (reg_icr & E1000_ICR_INT_ASSERTED); 935 if (!test_icr) 936 return (0); 937 938 if (ifp->if_flags & IFF_RUNNING) { 939 em_txeof(sc); 940 941 if (em_rxeof(sc) || ISSET(reg_icr, E1000_ICR_RXO)) { 942 if (em_rxfill(sc)) { 943 E1000_WRITE_REG(&sc->hw, RDT, 944 sc->sc_rx_desc_head); 945 } 946 } 947 } 948 949 /* Link status change */ 950 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 951 KERNEL_LOCK(); 952 sc->hw.get_link_status = 1; 953 em_check_for_link(&sc->hw); 954 em_update_link_status(sc); 955 KERNEL_UNLOCK(); 956 } 957 958 return (1); 959 } 960 961 /********************************************************************* 962 * 963 * Media Ioctl callback 964 * 965 * This routine is called whenever the user queries the status of 966 * the interface using ifconfig. 967 * 968 **********************************************************************/ 969 void 970 em_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 971 { 972 struct em_softc *sc = ifp->if_softc; 973 uint64_t fiber_type = IFM_1000_SX; 974 u_int16_t gsr; 975 976 INIT_DEBUGOUT("em_media_status: begin"); 977 978 em_check_for_link(&sc->hw); 979 em_update_link_status(sc); 980 981 ifmr->ifm_status = IFM_AVALID; 982 ifmr->ifm_active = IFM_ETHER; 983 984 if (!sc->link_active) { 985 ifmr->ifm_active |= IFM_NONE; 986 return; 987 } 988 989 ifmr->ifm_status |= IFM_ACTIVE; 990 991 if (sc->hw.media_type == em_media_type_fiber || 992 sc->hw.media_type == em_media_type_internal_serdes) { 993 if (sc->hw.mac_type == em_82545) 994 fiber_type = IFM_1000_LX; 995 ifmr->ifm_active |= fiber_type | IFM_FDX; 996 } else { 997 switch (sc->link_speed) { 998 case 10: 999 ifmr->ifm_active |= IFM_10_T; 1000 break; 1001 case 100: 1002 ifmr->ifm_active |= IFM_100_TX; 1003 break; 1004 case 1000: 1005 ifmr->ifm_active |= IFM_1000_T; 1006 break; 1007 } 1008 1009 if (sc->link_duplex == FULL_DUPLEX) 1010 ifmr->ifm_active |= em_flowstatus(sc) | IFM_FDX; 1011 else 1012 ifmr->ifm_active |= IFM_HDX; 1013 1014 if (IFM_SUBTYPE(ifmr->ifm_active) == IFM_1000_T) { 1015 em_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &gsr); 1016 if (gsr & SR_1000T_MS_CONFIG_RES) 1017 ifmr->ifm_active |= IFM_ETH_MASTER; 1018 } 1019 } 1020 } 1021 1022 /********************************************************************* 1023 * 1024 * Media Ioctl callback 1025 * 1026 * This routine is called when the user changes speed/duplex using 1027 * media/mediopt option with ifconfig. 1028 * 1029 **********************************************************************/ 1030 int 1031 em_media_change(struct ifnet *ifp) 1032 { 1033 struct em_softc *sc = ifp->if_softc; 1034 struct ifmedia *ifm = &sc->media; 1035 1036 INIT_DEBUGOUT("em_media_change: begin"); 1037 1038 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1039 return (EINVAL); 1040 1041 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1042 case IFM_AUTO: 1043 sc->hw.autoneg = DO_AUTO_NEG; 1044 sc->hw.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1045 break; 1046 case IFM_1000_LX: 1047 case IFM_1000_SX: 1048 case IFM_1000_T: 1049 sc->hw.autoneg = DO_AUTO_NEG; 1050 sc->hw.autoneg_advertised = ADVERTISE_1000_FULL; 1051 break; 1052 case IFM_100_TX: 1053 sc->hw.autoneg = FALSE; 1054 sc->hw.autoneg_advertised = 0; 1055 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1056 sc->hw.forced_speed_duplex = em_100_full; 1057 else 1058 sc->hw.forced_speed_duplex = em_100_half; 1059 break; 1060 case IFM_10_T: 1061 sc->hw.autoneg = FALSE; 1062 sc->hw.autoneg_advertised = 0; 1063 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1064 sc->hw.forced_speed_duplex = em_10_full; 1065 else 1066 sc->hw.forced_speed_duplex = em_10_half; 1067 break; 1068 default: 1069 printf("%s: Unsupported media type\n", DEVNAME(sc)); 1070 } 1071 1072 /* 1073 * As the speed/duplex settings may have changed we need to 1074 * reset the PHY. 1075 */ 1076 sc->hw.phy_reset_disable = FALSE; 1077 1078 em_init(sc); 1079 1080 return (0); 1081 } 1082 1083 uint64_t 1084 em_flowstatus(struct em_softc *sc) 1085 { 1086 u_int16_t ar, lpar; 1087 1088 if (sc->hw.media_type == em_media_type_fiber || 1089 sc->hw.media_type == em_media_type_internal_serdes) 1090 return (0); 1091 1092 em_read_phy_reg(&sc->hw, PHY_AUTONEG_ADV, &ar); 1093 em_read_phy_reg(&sc->hw, PHY_LP_ABILITY, &lpar); 1094 1095 if ((ar & NWAY_AR_PAUSE) && (lpar & NWAY_LPAR_PAUSE)) 1096 return (IFM_FLOW|IFM_ETH_TXPAUSE|IFM_ETH_RXPAUSE); 1097 else if (!(ar & NWAY_AR_PAUSE) && (ar & NWAY_AR_ASM_DIR) && 1098 (lpar & NWAY_LPAR_PAUSE) && (lpar & NWAY_LPAR_ASM_DIR)) 1099 return (IFM_FLOW|IFM_ETH_TXPAUSE); 1100 else if ((ar & NWAY_AR_PAUSE) && (ar & NWAY_AR_ASM_DIR) && 1101 !(lpar & NWAY_LPAR_PAUSE) && (lpar & NWAY_LPAR_ASM_DIR)) 1102 return (IFM_FLOW|IFM_ETH_RXPAUSE); 1103 1104 return (0); 1105 } 1106 1107 /********************************************************************* 1108 * 1109 * This routine maps the mbufs to tx descriptors. 1110 * 1111 * return 0 on success, positive on failure 1112 **********************************************************************/ 1113 u_int 1114 em_encap(struct em_softc *sc, struct mbuf *m) 1115 { 1116 struct em_packet *pkt; 1117 struct em_tx_desc *desc; 1118 bus_dmamap_t map; 1119 u_int32_t txd_upper, txd_lower; 1120 u_int head, last, used = 0; 1121 int i, j; 1122 1123 /* For 82544 Workaround */ 1124 DESC_ARRAY desc_array; 1125 u_int32_t array_elements; 1126 1127 /* get a dmamap for this packet from the next free slot */ 1128 head = sc->sc_tx_desc_head; 1129 pkt = &sc->sc_tx_pkts_ring[head]; 1130 map = pkt->pkt_map; 1131 1132 switch (bus_dmamap_load_mbuf(sc->sc_dmat, map, m, BUS_DMA_NOWAIT)) { 1133 case 0: 1134 break; 1135 case EFBIG: 1136 if (m_defrag(m, M_DONTWAIT) == 0 && 1137 bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1138 BUS_DMA_NOWAIT) == 0) 1139 break; 1140 1141 /* FALLTHROUGH */ 1142 default: 1143 sc->no_tx_dma_setup++; 1144 return (0); 1145 } 1146 1147 bus_dmamap_sync(sc->sc_dmat, map, 1148 0, map->dm_mapsize, 1149 BUS_DMASYNC_PREWRITE); 1150 1151 if (sc->hw.mac_type == em_82547) { 1152 bus_dmamap_sync(sc->sc_dmat, sc->sc_tx_dma.dma_map, 1153 0, sc->sc_tx_dma.dma_map->dm_mapsize, 1154 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1155 } 1156 1157 if (sc->hw.mac_type >= em_82543 && sc->hw.mac_type != em_82575 && 1158 sc->hw.mac_type != em_82580 && sc->hw.mac_type != em_i210 && 1159 sc->hw.mac_type != em_i350) { 1160 used += em_transmit_checksum_setup(sc, m, head, 1161 &txd_upper, &txd_lower); 1162 } else { 1163 txd_upper = txd_lower = 0; 1164 } 1165 1166 head += used; 1167 if (head >= sc->sc_tx_slots) 1168 head -= sc->sc_tx_slots; 1169 1170 for (i = 0; i < map->dm_nsegs; i++) { 1171 /* If sc is 82544 and on PCI-X bus */ 1172 if (sc->pcix_82544) { 1173 /* 1174 * Check the Address and Length combination and 1175 * split the data accordingly 1176 */ 1177 array_elements = em_fill_descriptors( 1178 map->dm_segs[i].ds_addr, map->dm_segs[i].ds_len, 1179 &desc_array); 1180 for (j = 0; j < array_elements; j++) { 1181 desc = &sc->sc_tx_desc_ring[head]; 1182 1183 desc->buffer_addr = htole64( 1184 desc_array.descriptor[j].address); 1185 desc->lower.data = htole32( 1186 (sc->sc_txd_cmd | txd_lower | 1187 (u_int16_t)desc_array.descriptor[j].length)); 1188 desc->upper.data = htole32(txd_upper); 1189 1190 last = head; 1191 if (++head == sc->sc_tx_slots) 1192 head = 0; 1193 1194 used++; 1195 } 1196 } else { 1197 desc = &sc->sc_tx_desc_ring[head]; 1198 1199 desc->buffer_addr = htole64(map->dm_segs[i].ds_addr); 1200 desc->lower.data = htole32(sc->sc_txd_cmd | 1201 txd_lower | map->dm_segs[i].ds_len); 1202 desc->upper.data = htole32(txd_upper); 1203 1204 last = head; 1205 if (++head == sc->sc_tx_slots) 1206 head = 0; 1207 1208 used++; 1209 } 1210 } 1211 1212 #if NVLAN > 0 1213 /* Find out if we are in VLAN mode */ 1214 if (m->m_flags & M_VLANTAG) { 1215 /* Set the VLAN id */ 1216 desc->upper.fields.special = htole16(m->m_pkthdr.ether_vtag); 1217 1218 /* Tell hardware to add tag */ 1219 desc->lower.data |= htole32(E1000_TXD_CMD_VLE); 1220 } 1221 #endif 1222 1223 /* mark the packet with the mbuf and last desc slot */ 1224 pkt->pkt_m = m; 1225 pkt->pkt_eop = last; 1226 1227 sc->sc_tx_desc_head = head; 1228 1229 /* 1230 * Last Descriptor of Packet 1231 * needs End Of Packet (EOP) 1232 * and Report Status (RS) 1233 */ 1234 desc->lower.data |= htole32(E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS); 1235 1236 if (sc->hw.mac_type == em_82547) { 1237 bus_dmamap_sync(sc->sc_dmat, sc->sc_tx_dma.dma_map, 1238 0, sc->sc_tx_dma.dma_map->dm_mapsize, 1239 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1240 } 1241 1242 return (used); 1243 } 1244 1245 /********************************************************************* 1246 * 1247 * 82547 workaround to avoid controller hang in half-duplex environment. 1248 * The workaround is to avoid queuing a large packet that would span 1249 * the internal Tx FIFO ring boundary. We need to reset the FIFO pointers 1250 * in this case. We do that only when FIFO is quiescent. 1251 * 1252 **********************************************************************/ 1253 void 1254 em_82547_move_tail_locked(struct em_softc *sc) 1255 { 1256 uint16_t hw_tdt; 1257 uint16_t sw_tdt; 1258 struct em_tx_desc *tx_desc; 1259 uint16_t length = 0; 1260 boolean_t eop = 0; 1261 1262 hw_tdt = E1000_READ_REG(&sc->hw, TDT); 1263 sw_tdt = sc->sc_tx_desc_head; 1264 1265 while (hw_tdt != sw_tdt) { 1266 tx_desc = &sc->sc_tx_desc_ring[hw_tdt]; 1267 length += tx_desc->lower.flags.length; 1268 eop = tx_desc->lower.data & E1000_TXD_CMD_EOP; 1269 if (++hw_tdt == sc->sc_tx_slots) 1270 hw_tdt = 0; 1271 1272 if (eop) { 1273 if (em_82547_fifo_workaround(sc, length)) { 1274 sc->tx_fifo_wrk_cnt++; 1275 timeout_add(&sc->tx_fifo_timer_handle, 1); 1276 break; 1277 } 1278 E1000_WRITE_REG(&sc->hw, TDT, hw_tdt); 1279 em_82547_update_fifo_head(sc, length); 1280 length = 0; 1281 } 1282 } 1283 } 1284 1285 void 1286 em_82547_move_tail(void *arg) 1287 { 1288 struct em_softc *sc = arg; 1289 int s; 1290 1291 s = splnet(); 1292 em_82547_move_tail_locked(sc); 1293 splx(s); 1294 } 1295 1296 int 1297 em_82547_fifo_workaround(struct em_softc *sc, int len) 1298 { 1299 int fifo_space, fifo_pkt_len; 1300 1301 fifo_pkt_len = EM_ROUNDUP(len + EM_FIFO_HDR, EM_FIFO_HDR); 1302 1303 if (sc->link_duplex == HALF_DUPLEX) { 1304 fifo_space = sc->tx_fifo_size - sc->tx_fifo_head; 1305 1306 if (fifo_pkt_len >= (EM_82547_PKT_THRESH + fifo_space)) { 1307 if (em_82547_tx_fifo_reset(sc)) 1308 return (0); 1309 else 1310 return (1); 1311 } 1312 } 1313 1314 return (0); 1315 } 1316 1317 void 1318 em_82547_update_fifo_head(struct em_softc *sc, int len) 1319 { 1320 int fifo_pkt_len = EM_ROUNDUP(len + EM_FIFO_HDR, EM_FIFO_HDR); 1321 1322 /* tx_fifo_head is always 16 byte aligned */ 1323 sc->tx_fifo_head += fifo_pkt_len; 1324 if (sc->tx_fifo_head >= sc->tx_fifo_size) 1325 sc->tx_fifo_head -= sc->tx_fifo_size; 1326 } 1327 1328 int 1329 em_82547_tx_fifo_reset(struct em_softc *sc) 1330 { 1331 uint32_t tctl; 1332 1333 if ((E1000_READ_REG(&sc->hw, TDT) == 1334 E1000_READ_REG(&sc->hw, TDH)) && 1335 (E1000_READ_REG(&sc->hw, TDFT) == 1336 E1000_READ_REG(&sc->hw, TDFH)) && 1337 (E1000_READ_REG(&sc->hw, TDFTS) == 1338 E1000_READ_REG(&sc->hw, TDFHS)) && 1339 (E1000_READ_REG(&sc->hw, TDFPC) == 0)) { 1340 1341 /* Disable TX unit */ 1342 tctl = E1000_READ_REG(&sc->hw, TCTL); 1343 E1000_WRITE_REG(&sc->hw, TCTL, tctl & ~E1000_TCTL_EN); 1344 1345 /* Reset FIFO pointers */ 1346 E1000_WRITE_REG(&sc->hw, TDFT, sc->tx_head_addr); 1347 E1000_WRITE_REG(&sc->hw, TDFH, sc->tx_head_addr); 1348 E1000_WRITE_REG(&sc->hw, TDFTS, sc->tx_head_addr); 1349 E1000_WRITE_REG(&sc->hw, TDFHS, sc->tx_head_addr); 1350 1351 /* Re-enable TX unit */ 1352 E1000_WRITE_REG(&sc->hw, TCTL, tctl); 1353 E1000_WRITE_FLUSH(&sc->hw); 1354 1355 sc->tx_fifo_head = 0; 1356 sc->tx_fifo_reset_cnt++; 1357 1358 return (TRUE); 1359 } else 1360 return (FALSE); 1361 } 1362 1363 void 1364 em_iff(struct em_softc *sc) 1365 { 1366 struct ifnet *ifp = &sc->sc_ac.ac_if; 1367 struct arpcom *ac = &sc->sc_ac; 1368 u_int32_t reg_rctl = 0; 1369 u_int8_t mta[MAX_NUM_MULTICAST_ADDRESSES * ETH_LENGTH_OF_ADDRESS]; 1370 struct ether_multi *enm; 1371 struct ether_multistep step; 1372 int i = 0; 1373 1374 IOCTL_DEBUGOUT("em_iff: begin"); 1375 1376 if (sc->hw.mac_type == em_82542_rev2_0) { 1377 reg_rctl = E1000_READ_REG(&sc->hw, RCTL); 1378 if (sc->hw.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1379 em_pci_clear_mwi(&sc->hw); 1380 reg_rctl |= E1000_RCTL_RST; 1381 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 1382 msec_delay(5); 1383 } 1384 1385 reg_rctl = E1000_READ_REG(&sc->hw, RCTL); 1386 reg_rctl &= ~(E1000_RCTL_MPE | E1000_RCTL_UPE); 1387 ifp->if_flags &= ~IFF_ALLMULTI; 1388 1389 if (ifp->if_flags & IFF_PROMISC || ac->ac_multirangecnt > 0 || 1390 ac->ac_multicnt > MAX_NUM_MULTICAST_ADDRESSES) { 1391 ifp->if_flags |= IFF_ALLMULTI; 1392 reg_rctl |= E1000_RCTL_MPE; 1393 if (ifp->if_flags & IFF_PROMISC) 1394 reg_rctl |= E1000_RCTL_UPE; 1395 } else { 1396 ETHER_FIRST_MULTI(step, ac, enm); 1397 while (enm != NULL) { 1398 bcopy(enm->enm_addrlo, mta + i, ETH_LENGTH_OF_ADDRESS); 1399 i += ETH_LENGTH_OF_ADDRESS; 1400 1401 ETHER_NEXT_MULTI(step, enm); 1402 } 1403 1404 em_mc_addr_list_update(&sc->hw, mta, ac->ac_multicnt, 0, 1); 1405 } 1406 1407 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 1408 1409 if (sc->hw.mac_type == em_82542_rev2_0) { 1410 reg_rctl = E1000_READ_REG(&sc->hw, RCTL); 1411 reg_rctl &= ~E1000_RCTL_RST; 1412 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 1413 msec_delay(5); 1414 if (sc->hw.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1415 em_pci_set_mwi(&sc->hw); 1416 } 1417 } 1418 1419 /********************************************************************* 1420 * Timer routine 1421 * 1422 * This routine checks for link status and updates statistics. 1423 * 1424 **********************************************************************/ 1425 1426 void 1427 em_local_timer(void *arg) 1428 { 1429 struct ifnet *ifp; 1430 struct em_softc *sc = arg; 1431 int s; 1432 1433 ifp = &sc->sc_ac.ac_if; 1434 1435 s = splnet(); 1436 1437 #ifndef SMALL_KERNEL 1438 em_update_stats_counters(sc); 1439 #ifdef EM_DEBUG 1440 if (ifp->if_flags & IFF_DEBUG && ifp->if_flags & IFF_RUNNING) 1441 em_print_hw_stats(sc); 1442 #endif 1443 #endif 1444 em_smartspeed(sc); 1445 1446 timeout_add_sec(&sc->timer_handle, 1); 1447 1448 splx(s); 1449 } 1450 1451 void 1452 em_update_link_status(struct em_softc *sc) 1453 { 1454 struct ifnet *ifp = &sc->sc_ac.ac_if; 1455 1456 if (E1000_READ_REG(&sc->hw, STATUS) & E1000_STATUS_LU) { 1457 if (sc->link_active == 0) { 1458 em_get_speed_and_duplex(&sc->hw, 1459 &sc->link_speed, 1460 &sc->link_duplex); 1461 /* Check if we may set SPEED_MODE bit on PCI-E */ 1462 if ((sc->link_speed == SPEED_1000) && 1463 ((sc->hw.mac_type == em_82571) || 1464 (sc->hw.mac_type == em_82572) || 1465 (sc->hw.mac_type == em_82575) || 1466 (sc->hw.mac_type == em_82580))) { 1467 int tarc0; 1468 1469 tarc0 = E1000_READ_REG(&sc->hw, TARC0); 1470 tarc0 |= SPEED_MODE_BIT; 1471 E1000_WRITE_REG(&sc->hw, TARC0, tarc0); 1472 } 1473 sc->link_active = 1; 1474 sc->smartspeed = 0; 1475 ifp->if_baudrate = IF_Mbps(sc->link_speed); 1476 } 1477 if (!LINK_STATE_IS_UP(ifp->if_link_state)) { 1478 if (sc->link_duplex == FULL_DUPLEX) 1479 ifp->if_link_state = LINK_STATE_FULL_DUPLEX; 1480 else 1481 ifp->if_link_state = LINK_STATE_HALF_DUPLEX; 1482 if_link_state_change(ifp); 1483 } 1484 } else { 1485 if (sc->link_active == 1) { 1486 ifp->if_baudrate = sc->link_speed = 0; 1487 sc->link_duplex = 0; 1488 sc->link_active = 0; 1489 } 1490 if (ifp->if_link_state != LINK_STATE_DOWN) { 1491 ifp->if_link_state = LINK_STATE_DOWN; 1492 if_link_state_change(ifp); 1493 } 1494 } 1495 } 1496 1497 /********************************************************************* 1498 * 1499 * This routine disables all traffic on the adapter by issuing a 1500 * global reset on the MAC and deallocates TX/RX buffers. 1501 * 1502 **********************************************************************/ 1503 1504 void 1505 em_stop(void *arg, int softonly) 1506 { 1507 struct em_softc *sc = arg; 1508 struct ifnet *ifp = &sc->sc_ac.ac_if; 1509 1510 /* Tell the stack that the interface is no longer active */ 1511 ifp->if_flags &= ~IFF_RUNNING; 1512 1513 INIT_DEBUGOUT("em_stop: begin"); 1514 1515 timeout_del(&sc->timer_handle); 1516 timeout_del(&sc->tx_fifo_timer_handle); 1517 1518 if (!softonly) 1519 em_disable_intr(sc); 1520 if (sc->hw.mac_type == em_pch_spt) 1521 em_flush_desc_rings(sc); 1522 if (!softonly) 1523 em_reset_hw(&sc->hw); 1524 1525 intr_barrier(sc->sc_intrhand); 1526 ifq_barrier(&ifp->if_snd); 1527 1528 KASSERT((ifp->if_flags & IFF_RUNNING) == 0); 1529 1530 ifq_clr_oactive(&ifp->if_snd); 1531 ifp->if_timer = 0; 1532 1533 em_free_transmit_structures(sc); 1534 em_free_receive_structures(sc); 1535 } 1536 1537 /********************************************************************* 1538 * 1539 * Determine hardware revision. 1540 * 1541 **********************************************************************/ 1542 void 1543 em_identify_hardware(struct em_softc *sc) 1544 { 1545 u_int32_t reg; 1546 struct pci_attach_args *pa = &sc->osdep.em_pa; 1547 1548 /* Make sure our PCI config space has the necessary stuff set */ 1549 sc->hw.pci_cmd_word = pci_conf_read(pa->pa_pc, pa->pa_tag, 1550 PCI_COMMAND_STATUS_REG); 1551 1552 /* Save off the information about this board */ 1553 sc->hw.vendor_id = PCI_VENDOR(pa->pa_id); 1554 sc->hw.device_id = PCI_PRODUCT(pa->pa_id); 1555 1556 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG); 1557 sc->hw.revision_id = PCI_REVISION(reg); 1558 1559 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 1560 sc->hw.subsystem_vendor_id = PCI_VENDOR(reg); 1561 sc->hw.subsystem_id = PCI_PRODUCT(reg); 1562 1563 /* Identify the MAC */ 1564 if (em_set_mac_type(&sc->hw)) 1565 printf("%s: Unknown MAC Type\n", DEVNAME(sc)); 1566 1567 if (sc->hw.mac_type == em_pchlan) 1568 sc->hw.revision_id = PCI_PRODUCT(pa->pa_id) & 0x0f; 1569 1570 if (sc->hw.mac_type == em_82541 || 1571 sc->hw.mac_type == em_82541_rev_2 || 1572 sc->hw.mac_type == em_82547 || 1573 sc->hw.mac_type == em_82547_rev_2) 1574 sc->hw.phy_init_script = TRUE; 1575 } 1576 1577 void 1578 em_legacy_irq_quirk_spt(struct em_softc *sc) 1579 { 1580 uint32_t reg; 1581 1582 /* Legacy interrupt: SPT needs a quirk. */ 1583 if (sc->hw.mac_type != em_pch_spt) 1584 return; 1585 if (sc->legacy_irq == 0) 1586 return; 1587 1588 reg = EM_READ_REG(&sc->hw, E1000_FEXTNVM7); 1589 reg |= E1000_FEXTNVM7_SIDE_CLK_UNGATE; 1590 EM_WRITE_REG(&sc->hw, E1000_FEXTNVM7, reg); 1591 1592 reg = EM_READ_REG(&sc->hw, E1000_FEXTNVM9); 1593 reg |= E1000_FEXTNVM9_IOSFSB_CLKGATE_DIS | 1594 E1000_FEXTNVM9_IOSFSB_CLKREQ_DIS; 1595 EM_WRITE_REG(&sc->hw, E1000_FEXTNVM9, reg); 1596 } 1597 1598 int 1599 em_allocate_pci_resources(struct em_softc *sc) 1600 { 1601 int val, rid; 1602 pci_intr_handle_t ih; 1603 const char *intrstr = NULL; 1604 struct pci_attach_args *pa = &sc->osdep.em_pa; 1605 pci_chipset_tag_t pc = pa->pa_pc; 1606 1607 val = pci_conf_read(pa->pa_pc, pa->pa_tag, EM_MMBA); 1608 if (PCI_MAPREG_TYPE(val) != PCI_MAPREG_TYPE_MEM) { 1609 printf(": mmba is not mem space\n"); 1610 return (ENXIO); 1611 } 1612 if (pci_mapreg_map(pa, EM_MMBA, PCI_MAPREG_MEM_TYPE(val), 0, 1613 &sc->osdep.mem_bus_space_tag, &sc->osdep.mem_bus_space_handle, 1614 &sc->osdep.em_membase, &sc->osdep.em_memsize, 0)) { 1615 printf(": cannot find mem space\n"); 1616 return (ENXIO); 1617 } 1618 1619 switch (sc->hw.mac_type) { 1620 case em_82544: 1621 case em_82540: 1622 case em_82545: 1623 case em_82546: 1624 case em_82541: 1625 case em_82541_rev_2: 1626 /* Figure out where our I/O BAR is ? */ 1627 for (rid = PCI_MAPREG_START; rid < PCI_MAPREG_END;) { 1628 val = pci_conf_read(pa->pa_pc, pa->pa_tag, rid); 1629 if (PCI_MAPREG_TYPE(val) == PCI_MAPREG_TYPE_IO) { 1630 sc->io_rid = rid; 1631 break; 1632 } 1633 rid += 4; 1634 if (PCI_MAPREG_MEM_TYPE(val) == 1635 PCI_MAPREG_MEM_TYPE_64BIT) 1636 rid += 4; /* skip high bits, too */ 1637 } 1638 1639 if (pci_mapreg_map(pa, rid, PCI_MAPREG_TYPE_IO, 0, 1640 &sc->osdep.io_bus_space_tag, &sc->osdep.io_bus_space_handle, 1641 &sc->osdep.em_iobase, &sc->osdep.em_iosize, 0)) { 1642 printf(": cannot find i/o space\n"); 1643 return (ENXIO); 1644 } 1645 1646 sc->hw.io_base = 0; 1647 break; 1648 default: 1649 break; 1650 } 1651 1652 sc->osdep.em_flashoffset = 0; 1653 /* for ICH8 and family we need to find the flash memory */ 1654 if (sc->hw.mac_type == em_pch_spt) { 1655 sc->osdep.flash_bus_space_tag = sc->osdep.mem_bus_space_tag; 1656 sc->osdep.flash_bus_space_handle = sc->osdep.mem_bus_space_handle; 1657 sc->osdep.em_flashbase = 0; 1658 sc->osdep.em_flashsize = 0; 1659 sc->osdep.em_flashoffset = 0xe000; 1660 } else if (IS_ICH8(sc->hw.mac_type)) { 1661 val = pci_conf_read(pa->pa_pc, pa->pa_tag, EM_FLASH); 1662 if (PCI_MAPREG_TYPE(val) != PCI_MAPREG_TYPE_MEM) { 1663 printf(": flash is not mem space\n"); 1664 return (ENXIO); 1665 } 1666 1667 if (pci_mapreg_map(pa, EM_FLASH, PCI_MAPREG_MEM_TYPE(val), 0, 1668 &sc->osdep.flash_bus_space_tag, &sc->osdep.flash_bus_space_handle, 1669 &sc->osdep.em_flashbase, &sc->osdep.em_flashsize, 0)) { 1670 printf(": cannot find mem space\n"); 1671 return (ENXIO); 1672 } 1673 } 1674 1675 sc->legacy_irq = 0; 1676 if (pci_intr_map_msi(pa, &ih)) { 1677 if (pci_intr_map(pa, &ih)) { 1678 printf(": couldn't map interrupt\n"); 1679 return (ENXIO); 1680 } 1681 sc->legacy_irq = 1; 1682 } 1683 1684 sc->osdep.dev = (struct device *)sc; 1685 sc->hw.back = &sc->osdep; 1686 1687 intrstr = pci_intr_string(pc, ih); 1688 sc->sc_intrhand = pci_intr_establish(pc, ih, IPL_NET | IPL_MPSAFE, 1689 em_intr, sc, DEVNAME(sc)); 1690 if (sc->sc_intrhand == NULL) { 1691 printf(": couldn't establish interrupt"); 1692 if (intrstr != NULL) 1693 printf(" at %s", intrstr); 1694 printf("\n"); 1695 return (ENXIO); 1696 } 1697 printf(": %s", intrstr); 1698 1699 /* 1700 * the ICP_xxxx device has multiple, duplicate register sets for 1701 * use when it is being used as a network processor. Disable those 1702 * registers here, as they are not necessary in this context and 1703 * can confuse the system 1704 */ 1705 if(sc->hw.mac_type == em_icp_xxxx) { 1706 int offset; 1707 pcireg_t val; 1708 1709 if (!pci_get_capability(sc->osdep.em_pa.pa_pc, 1710 sc->osdep.em_pa.pa_tag, PCI_CAP_ID_ST, &offset, &val)) { 1711 return (0); 1712 } 1713 offset += PCI_ST_SMIA_OFFSET; 1714 pci_conf_write(sc->osdep.em_pa.pa_pc, sc->osdep.em_pa.pa_tag, 1715 offset, 0x06); 1716 E1000_WRITE_REG(&sc->hw, IMC1, ~0x0); 1717 E1000_WRITE_REG(&sc->hw, IMC2, ~0x0); 1718 } 1719 return (0); 1720 } 1721 1722 void 1723 em_free_pci_resources(struct em_softc *sc) 1724 { 1725 struct pci_attach_args *pa = &sc->osdep.em_pa; 1726 pci_chipset_tag_t pc = pa->pa_pc; 1727 1728 if (sc->sc_intrhand) 1729 pci_intr_disestablish(pc, sc->sc_intrhand); 1730 sc->sc_intrhand = 0; 1731 1732 if (sc->osdep.em_flashbase) 1733 bus_space_unmap(sc->osdep.flash_bus_space_tag, sc->osdep.flash_bus_space_handle, 1734 sc->osdep.em_flashsize); 1735 sc->osdep.em_flashbase = 0; 1736 1737 if (sc->osdep.em_iobase) 1738 bus_space_unmap(sc->osdep.io_bus_space_tag, sc->osdep.io_bus_space_handle, 1739 sc->osdep.em_iosize); 1740 sc->osdep.em_iobase = 0; 1741 1742 if (sc->osdep.em_membase) 1743 bus_space_unmap(sc->osdep.mem_bus_space_tag, sc->osdep.mem_bus_space_handle, 1744 sc->osdep.em_memsize); 1745 sc->osdep.em_membase = 0; 1746 } 1747 1748 /********************************************************************* 1749 * 1750 * Initialize the hardware to a configuration as specified by the 1751 * em_softc structure. The controller is reset, the EEPROM is 1752 * verified, the MAC address is set, then the shared initialization 1753 * routines are called. 1754 * 1755 **********************************************************************/ 1756 int 1757 em_hardware_init(struct em_softc *sc) 1758 { 1759 uint32_t ret_val; 1760 u_int16_t rx_buffer_size; 1761 1762 INIT_DEBUGOUT("em_hardware_init: begin"); 1763 if (sc->hw.mac_type == em_pch_spt) 1764 em_flush_desc_rings(sc); 1765 /* Issue a global reset */ 1766 em_reset_hw(&sc->hw); 1767 1768 /* When hardware is reset, fifo_head is also reset */ 1769 sc->tx_fifo_head = 0; 1770 1771 /* Make sure we have a good EEPROM before we read from it */ 1772 if (em_get_flash_presence_i210(&sc->hw) && 1773 em_validate_eeprom_checksum(&sc->hw) < 0) { 1774 /* 1775 * Some PCIe parts fail the first check due to 1776 * the link being in sleep state, call it again, 1777 * if it fails a second time its a real issue. 1778 */ 1779 if (em_validate_eeprom_checksum(&sc->hw) < 0) { 1780 printf("%s: The EEPROM Checksum Is Not Valid\n", 1781 DEVNAME(sc)); 1782 return (EIO); 1783 } 1784 } 1785 1786 if (em_get_flash_presence_i210(&sc->hw) && 1787 em_read_part_num(&sc->hw, &(sc->part_num)) < 0) { 1788 printf("%s: EEPROM read error while reading part number\n", 1789 DEVNAME(sc)); 1790 return (EIO); 1791 } 1792 1793 /* Set up smart power down as default off on newer adapters */ 1794 if (!em_smart_pwr_down && 1795 (sc->hw.mac_type == em_82571 || 1796 sc->hw.mac_type == em_82572 || 1797 sc->hw.mac_type == em_82575 || 1798 sc->hw.mac_type == em_82580 || 1799 sc->hw.mac_type == em_i210 || 1800 sc->hw.mac_type == em_i350 )) { 1801 uint16_t phy_tmp = 0; 1802 1803 /* Speed up time to link by disabling smart power down */ 1804 em_read_phy_reg(&sc->hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 1805 phy_tmp &= ~IGP02E1000_PM_SPD; 1806 em_write_phy_reg(&sc->hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp); 1807 } 1808 1809 em_legacy_irq_quirk_spt(sc); 1810 1811 /* 1812 * These parameters control the automatic generation (Tx) and 1813 * response (Rx) to Ethernet PAUSE frames. 1814 * - High water mark should allow for at least two frames to be 1815 * received after sending an XOFF. 1816 * - Low water mark works best when it is very near the high water mark. 1817 * This allows the receiver to restart by sending XON when it has 1818 * drained a bit. Here we use an arbitary value of 1500 which will 1819 * restart after one full frame is pulled from the buffer. There 1820 * could be several smaller frames in the buffer and if so they will 1821 * not trigger the XON until their total number reduces the buffer 1822 * by 1500. 1823 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 1824 */ 1825 rx_buffer_size = ((E1000_READ_REG(&sc->hw, PBA) & 0xffff) << 10 ); 1826 1827 sc->hw.fc_high_water = rx_buffer_size - 1828 EM_ROUNDUP(sc->hw.max_frame_size, 1024); 1829 sc->hw.fc_low_water = sc->hw.fc_high_water - 1500; 1830 if (sc->hw.mac_type == em_80003es2lan) 1831 sc->hw.fc_pause_time = 0xFFFF; 1832 else 1833 sc->hw.fc_pause_time = 1000; 1834 sc->hw.fc_send_xon = TRUE; 1835 sc->hw.fc = E1000_FC_FULL; 1836 1837 em_disable_aspm(sc); 1838 1839 if ((ret_val = em_init_hw(&sc->hw)) != 0) { 1840 if (ret_val == E1000_DEFER_INIT) { 1841 INIT_DEBUGOUT("\nHardware Initialization Deferred "); 1842 return (EAGAIN); 1843 } 1844 printf("\n%s: Hardware Initialization Failed\n", 1845 DEVNAME(sc)); 1846 return (EIO); 1847 } 1848 1849 em_check_for_link(&sc->hw); 1850 1851 return (0); 1852 } 1853 1854 /********************************************************************* 1855 * 1856 * Setup networking device structure and register an interface. 1857 * 1858 **********************************************************************/ 1859 void 1860 em_setup_interface(struct em_softc *sc) 1861 { 1862 struct ifnet *ifp; 1863 uint64_t fiber_type = IFM_1000_SX; 1864 1865 INIT_DEBUGOUT("em_setup_interface: begin"); 1866 1867 ifp = &sc->sc_ac.ac_if; 1868 strlcpy(ifp->if_xname, DEVNAME(sc), IFNAMSIZ); 1869 ifp->if_softc = sc; 1870 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1871 ifp->if_xflags = IFXF_MPSAFE; 1872 ifp->if_ioctl = em_ioctl; 1873 ifp->if_start = em_start; 1874 ifp->if_watchdog = em_watchdog; 1875 ifp->if_hardmtu = 1876 sc->hw.max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN; 1877 IFQ_SET_MAXLEN(&ifp->if_snd, sc->sc_tx_slots - 1); 1878 1879 ifp->if_capabilities = IFCAP_VLAN_MTU; 1880 1881 #if NVLAN > 0 1882 if (sc->hw.mac_type != em_82575 && sc->hw.mac_type != em_82580 && 1883 sc->hw.mac_type != em_i210 && sc->hw.mac_type != em_i350) 1884 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 1885 #endif 1886 1887 if (sc->hw.mac_type >= em_82543 && sc->hw.mac_type != em_82575 && 1888 sc->hw.mac_type != em_82580 && sc->hw.mac_type != em_i210 && 1889 sc->hw.mac_type != em_i350) 1890 ifp->if_capabilities |= IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 1891 1892 /* 1893 * Specify the media types supported by this adapter and register 1894 * callbacks to update media and link information 1895 */ 1896 ifmedia_init(&sc->media, IFM_IMASK, em_media_change, 1897 em_media_status); 1898 if (sc->hw.media_type == em_media_type_fiber || 1899 sc->hw.media_type == em_media_type_internal_serdes) { 1900 if (sc->hw.mac_type == em_82545) 1901 fiber_type = IFM_1000_LX; 1902 ifmedia_add(&sc->media, IFM_ETHER | fiber_type | IFM_FDX, 1903 0, NULL); 1904 ifmedia_add(&sc->media, IFM_ETHER | fiber_type, 1905 0, NULL); 1906 } else { 1907 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL); 1908 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX, 1909 0, NULL); 1910 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 1911 0, NULL); 1912 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 1913 0, NULL); 1914 if (sc->hw.phy_type != em_phy_ife) { 1915 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 1916 0, NULL); 1917 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_T, 0, NULL); 1918 } 1919 } 1920 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL); 1921 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO); 1922 1923 if_attach(ifp); 1924 ether_ifattach(ifp); 1925 } 1926 1927 int 1928 em_detach(struct device *self, int flags) 1929 { 1930 struct em_softc *sc = (struct em_softc *)self; 1931 struct ifnet *ifp = &sc->sc_ac.ac_if; 1932 struct pci_attach_args *pa = &sc->osdep.em_pa; 1933 pci_chipset_tag_t pc = pa->pa_pc; 1934 1935 if (sc->sc_intrhand) 1936 pci_intr_disestablish(pc, sc->sc_intrhand); 1937 sc->sc_intrhand = 0; 1938 1939 em_stop(sc, 1); 1940 1941 em_free_pci_resources(sc); 1942 1943 if (sc->sc_rx_desc_ring != NULL) { 1944 sc->sc_rx_desc_ring = NULL; 1945 em_dma_free(sc, &sc->sc_rx_dma); 1946 } 1947 if (sc->sc_tx_desc_ring != NULL) { 1948 sc->sc_tx_desc_ring = NULL; 1949 em_dma_free(sc, &sc->sc_tx_dma); 1950 } 1951 1952 ether_ifdetach(ifp); 1953 if_detach(ifp); 1954 1955 return (0); 1956 } 1957 1958 int 1959 em_activate(struct device *self, int act) 1960 { 1961 struct em_softc *sc = (struct em_softc *)self; 1962 struct ifnet *ifp = &sc->sc_ac.ac_if; 1963 int rv = 0; 1964 1965 switch (act) { 1966 case DVACT_SUSPEND: 1967 if (ifp->if_flags & IFF_RUNNING) 1968 em_stop(sc, 0); 1969 /* We have no children atm, but we will soon */ 1970 rv = config_activate_children(self, act); 1971 break; 1972 case DVACT_RESUME: 1973 if (ifp->if_flags & IFF_UP) 1974 em_init(sc); 1975 break; 1976 default: 1977 rv = config_activate_children(self, act); 1978 break; 1979 } 1980 return (rv); 1981 } 1982 1983 /********************************************************************* 1984 * 1985 * Workaround for SmartSpeed on 82541 and 82547 controllers 1986 * 1987 **********************************************************************/ 1988 void 1989 em_smartspeed(struct em_softc *sc) 1990 { 1991 uint16_t phy_tmp; 1992 1993 if (sc->link_active || (sc->hw.phy_type != em_phy_igp) || 1994 !sc->hw.autoneg || !(sc->hw.autoneg_advertised & ADVERTISE_1000_FULL)) 1995 return; 1996 1997 if (sc->smartspeed == 0) { 1998 /* If Master/Slave config fault is asserted twice, 1999 * we assume back-to-back */ 2000 em_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2001 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2002 return; 2003 em_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2004 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2005 em_read_phy_reg(&sc->hw, PHY_1000T_CTRL, 2006 &phy_tmp); 2007 if (phy_tmp & CR_1000T_MS_ENABLE) { 2008 phy_tmp &= ~CR_1000T_MS_ENABLE; 2009 em_write_phy_reg(&sc->hw, 2010 PHY_1000T_CTRL, phy_tmp); 2011 sc->smartspeed++; 2012 if (sc->hw.autoneg && 2013 !em_phy_setup_autoneg(&sc->hw) && 2014 !em_read_phy_reg(&sc->hw, PHY_CTRL, 2015 &phy_tmp)) { 2016 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2017 MII_CR_RESTART_AUTO_NEG); 2018 em_write_phy_reg(&sc->hw, 2019 PHY_CTRL, phy_tmp); 2020 } 2021 } 2022 } 2023 return; 2024 } else if (sc->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 2025 /* If still no link, perhaps using 2/3 pair cable */ 2026 em_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp); 2027 phy_tmp |= CR_1000T_MS_ENABLE; 2028 em_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp); 2029 if (sc->hw.autoneg && 2030 !em_phy_setup_autoneg(&sc->hw) && 2031 !em_read_phy_reg(&sc->hw, PHY_CTRL, &phy_tmp)) { 2032 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2033 MII_CR_RESTART_AUTO_NEG); 2034 em_write_phy_reg(&sc->hw, PHY_CTRL, phy_tmp); 2035 } 2036 } 2037 /* Restart process after EM_SMARTSPEED_MAX iterations */ 2038 if (sc->smartspeed++ == EM_SMARTSPEED_MAX) 2039 sc->smartspeed = 0; 2040 } 2041 2042 /* 2043 * Manage DMA'able memory. 2044 */ 2045 int 2046 em_dma_malloc(struct em_softc *sc, bus_size_t size, struct em_dma_alloc *dma) 2047 { 2048 int r; 2049 2050 r = bus_dmamap_create(sc->sc_dmat, size, 1, 2051 size, 0, BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, &dma->dma_map); 2052 if (r != 0) 2053 return (r); 2054 2055 r = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, &dma->dma_seg, 2056 1, &dma->dma_nseg, BUS_DMA_WAITOK | BUS_DMA_ZERO); 2057 if (r != 0) 2058 goto destroy; 2059 2060 r = bus_dmamem_map(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg, size, 2061 &dma->dma_vaddr, BUS_DMA_WAITOK); 2062 if (r != 0) 2063 goto free; 2064 2065 r = bus_dmamap_load(sc->sc_dmat, dma->dma_map, dma->dma_vaddr, size, 2066 NULL, BUS_DMA_WAITOK); 2067 if (r != 0) 2068 goto unmap; 2069 2070 dma->dma_size = size; 2071 return (0); 2072 2073 unmap: 2074 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, size); 2075 free: 2076 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 2077 destroy: 2078 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 2079 2080 return (r); 2081 } 2082 2083 void 2084 em_dma_free(struct em_softc *sc, struct em_dma_alloc *dma) 2085 { 2086 bus_dmamap_unload(sc->sc_dmat, dma->dma_map); 2087 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, dma->dma_size); 2088 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 2089 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 2090 } 2091 2092 /********************************************************************* 2093 * 2094 * Allocate memory for tx_buffer structures. The tx_buffer stores all 2095 * the information needed to transmit a packet on the wire. 2096 * 2097 **********************************************************************/ 2098 int 2099 em_allocate_transmit_structures(struct em_softc *sc) 2100 { 2101 bus_dmamap_sync(sc->sc_dmat, sc->sc_tx_dma.dma_map, 2102 0, sc->sc_tx_dma.dma_map->dm_mapsize, 2103 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2104 2105 sc->sc_tx_pkts_ring = mallocarray(sc->sc_tx_slots, 2106 sizeof(*sc->sc_tx_pkts_ring), M_DEVBUF, M_NOWAIT | M_ZERO); 2107 if (sc->sc_tx_pkts_ring == NULL) { 2108 printf("%s: Unable to allocate tx_buffer memory\n", 2109 DEVNAME(sc)); 2110 return (ENOMEM); 2111 } 2112 2113 return (0); 2114 } 2115 2116 /********************************************************************* 2117 * 2118 * Allocate and initialize transmit structures. 2119 * 2120 **********************************************************************/ 2121 int 2122 em_setup_transmit_structures(struct em_softc *sc) 2123 { 2124 struct em_packet *pkt; 2125 int error, i; 2126 2127 if ((error = em_allocate_transmit_structures(sc)) != 0) 2128 goto fail; 2129 2130 bzero((void *) sc->sc_tx_desc_ring, 2131 (sizeof(struct em_tx_desc)) * sc->sc_tx_slots); 2132 2133 for (i = 0; i < sc->sc_tx_slots; i++) { 2134 pkt = &sc->sc_tx_pkts_ring[i]; 2135 error = bus_dmamap_create(sc->sc_dmat, MAX_JUMBO_FRAME_SIZE, 2136 EM_MAX_SCATTER / (sc->pcix_82544 ? 2 : 1), 2137 MAX_JUMBO_FRAME_SIZE, 0, BUS_DMA_NOWAIT, &pkt->pkt_map); 2138 if (error != 0) { 2139 printf("%s: Unable to create TX DMA map\n", 2140 DEVNAME(sc)); 2141 goto fail; 2142 } 2143 } 2144 2145 sc->sc_tx_desc_head = 0; 2146 sc->sc_tx_desc_tail = 0; 2147 2148 /* Set checksum context */ 2149 sc->active_checksum_context = OFFLOAD_NONE; 2150 2151 return (0); 2152 2153 fail: 2154 em_free_transmit_structures(sc); 2155 return (error); 2156 } 2157 2158 /********************************************************************* 2159 * 2160 * Enable transmit unit. 2161 * 2162 **********************************************************************/ 2163 void 2164 em_initialize_transmit_unit(struct em_softc *sc) 2165 { 2166 u_int32_t reg_tctl, reg_tipg = 0; 2167 u_int64_t bus_addr; 2168 2169 INIT_DEBUGOUT("em_initialize_transmit_unit: begin"); 2170 2171 /* Setup the Base and Length of the Tx Descriptor Ring */ 2172 bus_addr = sc->sc_tx_dma.dma_map->dm_segs[0].ds_addr; 2173 E1000_WRITE_REG(&sc->hw, TDLEN, 2174 sc->sc_tx_slots * 2175 sizeof(struct em_tx_desc)); 2176 E1000_WRITE_REG(&sc->hw, TDBAH, (u_int32_t)(bus_addr >> 32)); 2177 E1000_WRITE_REG(&sc->hw, TDBAL, (u_int32_t)bus_addr); 2178 2179 /* Setup the HW Tx Head and Tail descriptor pointers */ 2180 E1000_WRITE_REG(&sc->hw, TDT, 0); 2181 E1000_WRITE_REG(&sc->hw, TDH, 0); 2182 2183 HW_DEBUGOUT2("Base = %x, Length = %x\n", 2184 E1000_READ_REG(&sc->hw, TDBAL), 2185 E1000_READ_REG(&sc->hw, TDLEN)); 2186 2187 /* Set the default values for the Tx Inter Packet Gap timer */ 2188 switch (sc->hw.mac_type) { 2189 case em_82542_rev2_0: 2190 case em_82542_rev2_1: 2191 reg_tipg = DEFAULT_82542_TIPG_IPGT; 2192 reg_tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2193 reg_tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2194 break; 2195 case em_80003es2lan: 2196 reg_tipg = DEFAULT_82543_TIPG_IPGR1; 2197 reg_tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2198 break; 2199 default: 2200 if (sc->hw.media_type == em_media_type_fiber || 2201 sc->hw.media_type == em_media_type_internal_serdes) 2202 reg_tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 2203 else 2204 reg_tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 2205 reg_tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2206 reg_tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2207 } 2208 2209 2210 E1000_WRITE_REG(&sc->hw, TIPG, reg_tipg); 2211 E1000_WRITE_REG(&sc->hw, TIDV, sc->tx_int_delay); 2212 if (sc->hw.mac_type >= em_82540) 2213 E1000_WRITE_REG(&sc->hw, TADV, sc->tx_abs_int_delay); 2214 2215 /* Setup Transmit Descriptor Base Settings */ 2216 sc->sc_txd_cmd = E1000_TXD_CMD_IFCS; 2217 2218 if (sc->hw.mac_type == em_82575 || sc->hw.mac_type == em_82580 || 2219 sc->hw.mac_type == em_i210 || sc->hw.mac_type == em_i350) { 2220 /* 82575/6 need to enable the TX queue and lack the IDE bit */ 2221 reg_tctl = E1000_READ_REG(&sc->hw, TXDCTL); 2222 reg_tctl |= E1000_TXDCTL_QUEUE_ENABLE; 2223 E1000_WRITE_REG(&sc->hw, TXDCTL, reg_tctl); 2224 } else if (sc->tx_int_delay > 0) 2225 sc->sc_txd_cmd |= E1000_TXD_CMD_IDE; 2226 2227 /* Program the Transmit Control Register */ 2228 reg_tctl = E1000_TCTL_PSP | E1000_TCTL_EN | 2229 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 2230 if (sc->hw.mac_type >= em_82571) 2231 reg_tctl |= E1000_TCTL_MULR; 2232 if (sc->link_duplex == FULL_DUPLEX) 2233 reg_tctl |= E1000_FDX_COLLISION_DISTANCE << E1000_COLD_SHIFT; 2234 else 2235 reg_tctl |= E1000_HDX_COLLISION_DISTANCE << E1000_COLD_SHIFT; 2236 /* This write will effectively turn on the transmit unit */ 2237 E1000_WRITE_REG(&sc->hw, TCTL, reg_tctl); 2238 2239 /* SPT Si errata workaround to avoid data corruption */ 2240 2241 if (sc->hw.mac_type == em_pch_spt) { 2242 uint32_t reg_val; 2243 2244 reg_val = EM_READ_REG(&sc->hw, E1000_IOSFPC); 2245 reg_val |= E1000_RCTL_RDMTS_HEX; 2246 EM_WRITE_REG(&sc->hw, E1000_IOSFPC, reg_val); 2247 2248 reg_val = E1000_READ_REG(&sc->hw, TARC0); 2249 reg_val |= E1000_TARC0_CB_MULTIQ_3_REQ; 2250 E1000_WRITE_REG(&sc->hw, TARC0, reg_val); 2251 } 2252 } 2253 2254 /********************************************************************* 2255 * 2256 * Free all transmit related data structures. 2257 * 2258 **********************************************************************/ 2259 void 2260 em_free_transmit_structures(struct em_softc *sc) 2261 { 2262 struct em_packet *pkt; 2263 int i; 2264 2265 INIT_DEBUGOUT("free_transmit_structures: begin"); 2266 2267 if (sc->sc_tx_pkts_ring != NULL) { 2268 for (i = 0; i < sc->sc_tx_slots; i++) { 2269 pkt = &sc->sc_tx_pkts_ring[i]; 2270 2271 if (pkt->pkt_m != NULL) { 2272 bus_dmamap_sync(sc->sc_dmat, pkt->pkt_map, 2273 0, pkt->pkt_map->dm_mapsize, 2274 BUS_DMASYNC_POSTWRITE); 2275 bus_dmamap_unload(sc->sc_dmat, pkt->pkt_map); 2276 2277 m_freem(pkt->pkt_m); 2278 pkt->pkt_m = NULL; 2279 } 2280 2281 if (pkt->pkt_map != NULL) { 2282 bus_dmamap_destroy(sc->sc_dmat, pkt->pkt_map); 2283 pkt->pkt_map = NULL; 2284 } 2285 } 2286 2287 free(sc->sc_tx_pkts_ring, M_DEVBUF, 2288 sc->sc_tx_slots * sizeof(*sc->sc_tx_pkts_ring)); 2289 sc->sc_tx_pkts_ring = NULL; 2290 } 2291 2292 bus_dmamap_sync(sc->sc_dmat, sc->sc_tx_dma.dma_map, 2293 0, sc->sc_tx_dma.dma_map->dm_mapsize, 2294 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2295 } 2296 2297 /********************************************************************* 2298 * 2299 * The offload context needs to be set when we transfer the first 2300 * packet of a particular protocol (TCP/UDP). We change the 2301 * context only if the protocol type changes. 2302 * 2303 **********************************************************************/ 2304 u_int 2305 em_transmit_checksum_setup(struct em_softc *sc, struct mbuf *mp, u_int head, 2306 u_int32_t *txd_upper, u_int32_t *txd_lower) 2307 { 2308 struct em_context_desc *TXD; 2309 2310 if (mp->m_pkthdr.csum_flags & M_TCP_CSUM_OUT) { 2311 *txd_upper = E1000_TXD_POPTS_TXSM << 8; 2312 *txd_lower = E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 2313 if (sc->active_checksum_context == OFFLOAD_TCP_IP) 2314 return (0); 2315 else 2316 sc->active_checksum_context = OFFLOAD_TCP_IP; 2317 } else if (mp->m_pkthdr.csum_flags & M_UDP_CSUM_OUT) { 2318 *txd_upper = E1000_TXD_POPTS_TXSM << 8; 2319 *txd_lower = E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 2320 if (sc->active_checksum_context == OFFLOAD_UDP_IP) 2321 return (0); 2322 else 2323 sc->active_checksum_context = OFFLOAD_UDP_IP; 2324 } else { 2325 *txd_upper = 0; 2326 *txd_lower = 0; 2327 return (0); 2328 } 2329 2330 /* If we reach this point, the checksum offload context 2331 * needs to be reset. 2332 */ 2333 TXD = (struct em_context_desc *)&sc->sc_tx_desc_ring[head]; 2334 2335 TXD->lower_setup.ip_fields.ipcss = ETHER_HDR_LEN; 2336 TXD->lower_setup.ip_fields.ipcso = 2337 ETHER_HDR_LEN + offsetof(struct ip, ip_sum); 2338 TXD->lower_setup.ip_fields.ipcse = 2339 htole16(ETHER_HDR_LEN + sizeof(struct ip) - 1); 2340 2341 TXD->upper_setup.tcp_fields.tucss = 2342 ETHER_HDR_LEN + sizeof(struct ip); 2343 TXD->upper_setup.tcp_fields.tucse = htole16(0); 2344 2345 if (sc->active_checksum_context == OFFLOAD_TCP_IP) { 2346 TXD->upper_setup.tcp_fields.tucso = 2347 ETHER_HDR_LEN + sizeof(struct ip) + 2348 offsetof(struct tcphdr, th_sum); 2349 } else if (sc->active_checksum_context == OFFLOAD_UDP_IP) { 2350 TXD->upper_setup.tcp_fields.tucso = 2351 ETHER_HDR_LEN + sizeof(struct ip) + 2352 offsetof(struct udphdr, uh_sum); 2353 } 2354 2355 TXD->tcp_seg_setup.data = htole32(0); 2356 TXD->cmd_and_length = htole32(sc->sc_txd_cmd | E1000_TXD_CMD_DEXT); 2357 2358 return (1); 2359 } 2360 2361 /********************************************************************** 2362 * 2363 * Examine each tx_buffer in the used queue. If the hardware is done 2364 * processing the packet then free associated resources. The 2365 * tx_buffer is put back on the free queue. 2366 * 2367 **********************************************************************/ 2368 void 2369 em_txeof(struct em_softc *sc) 2370 { 2371 struct ifnet *ifp = &sc->sc_ac.ac_if; 2372 struct em_packet *pkt; 2373 struct em_tx_desc *desc; 2374 u_int head, tail; 2375 u_int free = 0; 2376 2377 head = sc->sc_tx_desc_head; 2378 tail = sc->sc_tx_desc_tail; 2379 2380 if (head == tail) 2381 return; 2382 2383 bus_dmamap_sync(sc->sc_dmat, sc->sc_tx_dma.dma_map, 2384 0, sc->sc_tx_dma.dma_map->dm_mapsize, 2385 BUS_DMASYNC_POSTREAD); 2386 2387 do { 2388 pkt = &sc->sc_tx_pkts_ring[tail]; 2389 desc = &sc->sc_tx_desc_ring[pkt->pkt_eop]; 2390 2391 if (!ISSET(desc->upper.fields.status, E1000_TXD_STAT_DD)) 2392 break; 2393 2394 bus_dmamap_sync(sc->sc_dmat, pkt->pkt_map, 2395 0, pkt->pkt_map->dm_mapsize, 2396 BUS_DMASYNC_POSTWRITE); 2397 bus_dmamap_unload(sc->sc_dmat, pkt->pkt_map); 2398 2399 KASSERT(pkt->pkt_m != NULL); 2400 2401 m_freem(pkt->pkt_m); 2402 pkt->pkt_m = NULL; 2403 2404 tail = pkt->pkt_eop; 2405 2406 if (++tail == sc->sc_tx_slots) 2407 tail = 0; 2408 2409 free++; 2410 } while (tail != head); 2411 2412 bus_dmamap_sync(sc->sc_dmat, sc->sc_tx_dma.dma_map, 2413 0, sc->sc_tx_dma.dma_map->dm_mapsize, 2414 BUS_DMASYNC_PREREAD); 2415 2416 if (free == 0) 2417 return; 2418 2419 sc->sc_tx_desc_tail = tail; 2420 2421 if (ifq_is_oactive(&ifp->if_snd)) 2422 ifq_restart(&ifp->if_snd); 2423 else if (tail == head) 2424 ifp->if_timer = 0; 2425 } 2426 2427 /********************************************************************* 2428 * 2429 * Get a buffer from system mbuf buffer pool. 2430 * 2431 **********************************************************************/ 2432 int 2433 em_get_buf(struct em_softc *sc, int i) 2434 { 2435 struct mbuf *m; 2436 struct em_packet *pkt; 2437 struct em_rx_desc *desc; 2438 int error; 2439 2440 pkt = &sc->sc_rx_pkts_ring[i]; 2441 desc = &sc->sc_rx_desc_ring[i]; 2442 2443 KASSERT(pkt->pkt_m == NULL); 2444 2445 m = MCLGETI(NULL, M_DONTWAIT, NULL, EM_MCLBYTES); 2446 if (m == NULL) { 2447 sc->mbuf_cluster_failed++; 2448 return (ENOBUFS); 2449 } 2450 m->m_len = m->m_pkthdr.len = EM_MCLBYTES; 2451 m_adj(m, ETHER_ALIGN); 2452 2453 error = bus_dmamap_load_mbuf(sc->sc_dmat, pkt->pkt_map, 2454 m, BUS_DMA_NOWAIT); 2455 if (error) { 2456 m_freem(m); 2457 return (error); 2458 } 2459 2460 bus_dmamap_sync(sc->sc_dmat, pkt->pkt_map, 2461 0, pkt->pkt_map->dm_mapsize, 2462 BUS_DMASYNC_PREREAD); 2463 pkt->pkt_m = m; 2464 2465 memset(desc, 0, sizeof(*desc)); 2466 htolem64(&desc->buffer_addr, pkt->pkt_map->dm_segs[0].ds_addr); 2467 2468 return (0); 2469 } 2470 2471 /********************************************************************* 2472 * 2473 * Allocate memory for rx_buffer structures. Since we use one 2474 * rx_buffer per received packet, the maximum number of rx_buffer's 2475 * that we'll need is equal to the number of receive descriptors 2476 * that we've allocated. 2477 * 2478 **********************************************************************/ 2479 int 2480 em_allocate_receive_structures(struct em_softc *sc) 2481 { 2482 struct em_packet *pkt; 2483 int i; 2484 int error; 2485 2486 sc->sc_rx_pkts_ring = mallocarray(sc->sc_rx_slots, 2487 sizeof(*sc->sc_rx_pkts_ring), M_DEVBUF, M_NOWAIT | M_ZERO); 2488 if (sc->sc_rx_pkts_ring == NULL) { 2489 printf("%s: Unable to allocate rx_buffer memory\n", 2490 DEVNAME(sc)); 2491 return (ENOMEM); 2492 } 2493 2494 bus_dmamap_sync(sc->sc_dmat, sc->sc_rx_dma.dma_map, 2495 0, sc->sc_rx_dma.dma_map->dm_mapsize, 2496 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2497 2498 for (i = 0; i < sc->sc_rx_slots; i++) { 2499 pkt = &sc->sc_rx_pkts_ring[i]; 2500 2501 error = bus_dmamap_create(sc->sc_dmat, EM_MCLBYTES, 1, 2502 EM_MCLBYTES, 0, BUS_DMA_NOWAIT, &pkt->pkt_map); 2503 if (error != 0) { 2504 printf("%s: em_allocate_receive_structures: " 2505 "bus_dmamap_create failed; error %u\n", 2506 DEVNAME(sc), error); 2507 goto fail; 2508 } 2509 2510 pkt->pkt_m = NULL; 2511 } 2512 2513 return (0); 2514 2515 fail: 2516 em_free_receive_structures(sc); 2517 return (error); 2518 } 2519 2520 /********************************************************************* 2521 * 2522 * Allocate and initialize receive structures. 2523 * 2524 **********************************************************************/ 2525 int 2526 em_setup_receive_structures(struct em_softc *sc) 2527 { 2528 struct ifnet *ifp = &sc->sc_ac.ac_if; 2529 u_int lwm; 2530 2531 memset(sc->sc_rx_desc_ring, 0, 2532 sc->sc_rx_slots * sizeof(*sc->sc_rx_desc_ring)); 2533 2534 if (em_allocate_receive_structures(sc)) 2535 return (ENOMEM); 2536 2537 /* Setup our descriptor pointers */ 2538 sc->sc_rx_desc_tail = 0; 2539 sc->sc_rx_desc_head = sc->sc_rx_slots - 1; 2540 2541 lwm = max(4, 2 * ((ifp->if_hardmtu / MCLBYTES) + 1)); 2542 if_rxr_init(&sc->sc_rx_ring, lwm, sc->sc_rx_slots); 2543 2544 if (em_rxfill(sc) == 0) { 2545 printf("%s: unable to fill any rx descriptors\n", 2546 DEVNAME(sc)); 2547 } 2548 2549 return (0); 2550 } 2551 2552 /********************************************************************* 2553 * 2554 * Enable receive unit. 2555 * 2556 **********************************************************************/ 2557 void 2558 em_initialize_receive_unit(struct em_softc *sc) 2559 { 2560 u_int32_t reg_rctl; 2561 u_int32_t reg_rxcsum; 2562 u_int64_t bus_addr; 2563 2564 INIT_DEBUGOUT("em_initialize_receive_unit: begin"); 2565 2566 /* Make sure receives are disabled while setting up the descriptor ring */ 2567 E1000_WRITE_REG(&sc->hw, RCTL, 0); 2568 2569 /* Set the Receive Delay Timer Register */ 2570 E1000_WRITE_REG(&sc->hw, RDTR, 2571 sc->rx_int_delay | E1000_RDT_FPDB); 2572 2573 if (sc->hw.mac_type >= em_82540) { 2574 if (sc->rx_int_delay) 2575 E1000_WRITE_REG(&sc->hw, RADV, sc->rx_abs_int_delay); 2576 2577 /* Set the interrupt throttling rate. Value is calculated 2578 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */ 2579 E1000_WRITE_REG(&sc->hw, ITR, DEFAULT_ITR); 2580 } 2581 2582 /* Setup the Base and Length of the Rx Descriptor Ring */ 2583 bus_addr = sc->sc_rx_dma.dma_map->dm_segs[0].ds_addr; 2584 E1000_WRITE_REG(&sc->hw, RDLEN, 2585 sc->sc_rx_slots * sizeof(*sc->sc_rx_desc_ring)); 2586 E1000_WRITE_REG(&sc->hw, RDBAH, (u_int32_t)(bus_addr >> 32)); 2587 E1000_WRITE_REG(&sc->hw, RDBAL, (u_int32_t)bus_addr); 2588 2589 /* Setup the Receive Control Register */ 2590 reg_rctl = E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO | 2591 E1000_RCTL_RDMTS_HALF | 2592 (sc->hw.mc_filter_type << E1000_RCTL_MO_SHIFT); 2593 2594 if (sc->hw.tbi_compatibility_on == TRUE) 2595 reg_rctl |= E1000_RCTL_SBP; 2596 2597 /* 2598 * The i350 has a bug where it always strips the CRC whether 2599 * asked to or not. So ask for stripped CRC here and 2600 * cope in rxeof 2601 */ 2602 if (sc->hw.mac_type == em_i210 || sc->hw.mac_type == em_i350) 2603 reg_rctl |= E1000_RCTL_SECRC; 2604 2605 switch (sc->sc_rx_buffer_len) { 2606 default: 2607 case EM_RXBUFFER_2048: 2608 reg_rctl |= E1000_RCTL_SZ_2048; 2609 break; 2610 case EM_RXBUFFER_4096: 2611 reg_rctl |= E1000_RCTL_SZ_4096|E1000_RCTL_BSEX|E1000_RCTL_LPE; 2612 break; 2613 case EM_RXBUFFER_8192: 2614 reg_rctl |= E1000_RCTL_SZ_8192|E1000_RCTL_BSEX|E1000_RCTL_LPE; 2615 break; 2616 case EM_RXBUFFER_16384: 2617 reg_rctl |= E1000_RCTL_SZ_16384|E1000_RCTL_BSEX|E1000_RCTL_LPE; 2618 break; 2619 } 2620 2621 if (sc->hw.max_frame_size != ETHER_MAX_LEN) 2622 reg_rctl |= E1000_RCTL_LPE; 2623 2624 /* Enable 82543 Receive Checksum Offload for TCP and UDP */ 2625 if (sc->hw.mac_type >= em_82543) { 2626 reg_rxcsum = E1000_READ_REG(&sc->hw, RXCSUM); 2627 reg_rxcsum |= (E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL); 2628 E1000_WRITE_REG(&sc->hw, RXCSUM, reg_rxcsum); 2629 } 2630 2631 /* 2632 * XXX TEMPORARY WORKAROUND: on some systems with 82573 2633 * long latencies are observed, like Lenovo X60. 2634 */ 2635 if (sc->hw.mac_type == em_82573) 2636 E1000_WRITE_REG(&sc->hw, RDTR, 0x20); 2637 2638 if (sc->hw.mac_type == em_82575 || sc->hw.mac_type == em_82580 || 2639 sc->hw.mac_type == em_i210 || sc->hw.mac_type == em_i350) { 2640 /* 82575/6 need to enable the RX queue */ 2641 uint32_t reg; 2642 reg = E1000_READ_REG(&sc->hw, RXDCTL); 2643 reg |= E1000_RXDCTL_QUEUE_ENABLE; 2644 E1000_WRITE_REG(&sc->hw, RXDCTL, reg); 2645 } 2646 2647 /* Enable Receives */ 2648 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 2649 2650 /* Setup the HW Rx Head and Tail Descriptor Pointers */ 2651 E1000_WRITE_REG(&sc->hw, RDH, 0); 2652 E1000_WRITE_REG(&sc->hw, RDT, sc->sc_rx_desc_head); 2653 } 2654 2655 /********************************************************************* 2656 * 2657 * Free receive related data structures. 2658 * 2659 **********************************************************************/ 2660 void 2661 em_free_receive_structures(struct em_softc *sc) 2662 { 2663 struct em_packet *pkt; 2664 int i; 2665 2666 INIT_DEBUGOUT("free_receive_structures: begin"); 2667 2668 if_rxr_init(&sc->sc_rx_ring, 0, 0); 2669 2670 bus_dmamap_sync(sc->sc_dmat, sc->sc_rx_dma.dma_map, 2671 0, sc->sc_rx_dma.dma_map->dm_mapsize, 2672 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2673 2674 if (sc->sc_rx_pkts_ring != NULL) { 2675 for (i = 0; i < sc->sc_rx_slots; i++) { 2676 pkt = &sc->sc_rx_pkts_ring[i]; 2677 if (pkt->pkt_m != NULL) { 2678 bus_dmamap_sync(sc->sc_dmat, pkt->pkt_map, 2679 0, pkt->pkt_map->dm_mapsize, 2680 BUS_DMASYNC_POSTREAD); 2681 bus_dmamap_unload(sc->sc_dmat, pkt->pkt_map); 2682 m_freem(pkt->pkt_m); 2683 pkt->pkt_m = NULL; 2684 } 2685 bus_dmamap_destroy(sc->sc_dmat, pkt->pkt_map); 2686 } 2687 2688 free(sc->sc_rx_pkts_ring, M_DEVBUF, 2689 sc->sc_rx_slots * sizeof(*sc->sc_rx_pkts_ring)); 2690 sc->sc_rx_pkts_ring = NULL; 2691 } 2692 2693 if (sc->fmp != NULL) { 2694 m_freem(sc->fmp); 2695 sc->fmp = NULL; 2696 sc->lmp = NULL; 2697 } 2698 } 2699 2700 int 2701 em_rxfill(struct em_softc *sc) 2702 { 2703 u_int slots; 2704 int post = 0; 2705 int i; 2706 2707 i = sc->sc_rx_desc_head; 2708 2709 bus_dmamap_sync(sc->sc_dmat, sc->sc_rx_dma.dma_map, 2710 0, sc->sc_rx_dma.dma_map->dm_mapsize, 2711 BUS_DMASYNC_POSTWRITE); 2712 2713 for (slots = if_rxr_get(&sc->sc_rx_ring, sc->sc_rx_slots); 2714 slots > 0; slots--) { 2715 if (++i == sc->sc_rx_slots) 2716 i = 0; 2717 2718 if (em_get_buf(sc, i) != 0) 2719 break; 2720 2721 sc->sc_rx_desc_head = i; 2722 post = 1; 2723 } 2724 2725 if_rxr_put(&sc->sc_rx_ring, slots); 2726 2727 bus_dmamap_sync(sc->sc_dmat, sc->sc_rx_dma.dma_map, 2728 0, sc->sc_rx_dma.dma_map->dm_mapsize, 2729 BUS_DMASYNC_PREWRITE); 2730 2731 return (post); 2732 } 2733 2734 /********************************************************************* 2735 * 2736 * This routine executes in interrupt context. It replenishes 2737 * the mbufs in the descriptor and sends data which has been 2738 * dma'ed into host memory to upper layer. 2739 * 2740 *********************************************************************/ 2741 int 2742 em_rxeof(struct em_softc *sc) 2743 { 2744 struct ifnet *ifp = &sc->sc_ac.ac_if; 2745 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 2746 struct mbuf *m; 2747 u_int8_t accept_frame = 0; 2748 u_int8_t eop = 0; 2749 u_int16_t len, desc_len, prev_len_adj; 2750 int i, rv = 0; 2751 2752 /* Pointer to the receive descriptor being examined. */ 2753 struct em_rx_desc *desc; 2754 struct em_packet *pkt; 2755 u_int8_t status; 2756 2757 if (if_rxr_inuse(&sc->sc_rx_ring) == 0) 2758 return (0); 2759 2760 i = sc->sc_rx_desc_tail; 2761 2762 bus_dmamap_sync(sc->sc_dmat, sc->sc_rx_dma.dma_map, 2763 0, sc->sc_rx_dma.dma_map->dm_mapsize, 2764 BUS_DMASYNC_POSTREAD); 2765 2766 do { 2767 m = NULL; 2768 2769 pkt = &sc->sc_rx_pkts_ring[i]; 2770 desc = &sc->sc_rx_desc_ring[i]; 2771 2772 status = desc->status; 2773 if (!ISSET(status, E1000_RXD_STAT_DD)) 2774 break; 2775 2776 /* pull the mbuf off the ring */ 2777 bus_dmamap_sync(sc->sc_dmat, pkt->pkt_map, 2778 0, pkt->pkt_map->dm_mapsize, 2779 BUS_DMASYNC_POSTREAD); 2780 bus_dmamap_unload(sc->sc_dmat, pkt->pkt_map); 2781 m = pkt->pkt_m; 2782 pkt->pkt_m = NULL; 2783 2784 KASSERT(m != NULL); 2785 2786 if_rxr_put(&sc->sc_rx_ring, 1); 2787 rv = 1; 2788 2789 accept_frame = 1; 2790 prev_len_adj = 0; 2791 desc_len = letoh16(desc->length); 2792 2793 if (status & E1000_RXD_STAT_EOP) { 2794 eop = 1; 2795 if (desc_len < ETHER_CRC_LEN) { 2796 len = 0; 2797 prev_len_adj = ETHER_CRC_LEN - desc_len; 2798 } else if (sc->hw.mac_type == em_i210 || 2799 sc->hw.mac_type == em_i350) 2800 len = desc_len; 2801 else 2802 len = desc_len - ETHER_CRC_LEN; 2803 } else { 2804 eop = 0; 2805 len = desc_len; 2806 } 2807 2808 if (desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK) { 2809 u_int8_t last_byte; 2810 u_int32_t pkt_len = desc_len; 2811 2812 if (sc->fmp != NULL) 2813 pkt_len += sc->fmp->m_pkthdr.len; 2814 2815 last_byte = *(mtod(m, caddr_t) + desc_len - 1); 2816 if (TBI_ACCEPT(&sc->hw, status, desc->errors, 2817 pkt_len, last_byte)) { 2818 #ifndef SMALL_KERNEL 2819 em_tbi_adjust_stats(&sc->hw, &sc->stats, 2820 pkt_len, sc->hw.mac_addr); 2821 #endif 2822 if (len > 0) 2823 len--; 2824 } else 2825 accept_frame = 0; 2826 } 2827 2828 if (accept_frame) { 2829 /* Assign correct length to the current fragment */ 2830 m->m_len = len; 2831 2832 if (sc->fmp == NULL) { 2833 m->m_pkthdr.len = m->m_len; 2834 sc->fmp = m; /* Store the first mbuf */ 2835 sc->lmp = m; 2836 } else { 2837 /* Chain mbuf's together */ 2838 m->m_flags &= ~M_PKTHDR; 2839 /* 2840 * Adjust length of previous mbuf in chain if 2841 * we received less than 4 bytes in the last 2842 * descriptor. 2843 */ 2844 if (prev_len_adj > 0) { 2845 sc->lmp->m_len -= prev_len_adj; 2846 sc->fmp->m_pkthdr.len -= prev_len_adj; 2847 } 2848 sc->lmp->m_next = m; 2849 sc->lmp = m; 2850 sc->fmp->m_pkthdr.len += m->m_len; 2851 } 2852 2853 if (eop) { 2854 m = sc->fmp; 2855 2856 em_receive_checksum(sc, desc, m); 2857 #if NVLAN > 0 2858 if (desc->status & E1000_RXD_STAT_VP) { 2859 m->m_pkthdr.ether_vtag = 2860 letoh16(desc->special); 2861 m->m_flags |= M_VLANTAG; 2862 } 2863 #endif 2864 ml_enqueue(&ml, m); 2865 2866 sc->fmp = NULL; 2867 sc->lmp = NULL; 2868 } 2869 } else { 2870 sc->dropped_pkts++; 2871 2872 if (sc->fmp != NULL) { 2873 m_freem(sc->fmp); 2874 sc->fmp = NULL; 2875 sc->lmp = NULL; 2876 } 2877 2878 m_freem(m); 2879 } 2880 2881 /* Advance our pointers to the next descriptor. */ 2882 if (++i == sc->sc_rx_slots) 2883 i = 0; 2884 } while (if_rxr_inuse(&sc->sc_rx_ring) > 0); 2885 2886 bus_dmamap_sync(sc->sc_dmat, sc->sc_rx_dma.dma_map, 2887 0, sc->sc_rx_dma.dma_map->dm_mapsize, 2888 BUS_DMASYNC_PREREAD); 2889 2890 sc->sc_rx_desc_tail = i; 2891 2892 if_input(ifp, &ml); 2893 2894 return (rv); 2895 } 2896 2897 /********************************************************************* 2898 * 2899 * Verify that the hardware indicated that the checksum is valid. 2900 * Inform the stack about the status of checksum so that stack 2901 * doesn't spend time verifying the checksum. 2902 * 2903 *********************************************************************/ 2904 void 2905 em_receive_checksum(struct em_softc *sc, struct em_rx_desc *rx_desc, 2906 struct mbuf *mp) 2907 { 2908 /* 82543 or newer only */ 2909 if ((sc->hw.mac_type < em_82543) || 2910 /* Ignore Checksum bit is set */ 2911 (rx_desc->status & E1000_RXD_STAT_IXSM)) { 2912 mp->m_pkthdr.csum_flags = 0; 2913 return; 2914 } 2915 2916 if (rx_desc->status & E1000_RXD_STAT_IPCS) { 2917 /* Did it pass? */ 2918 if (!(rx_desc->errors & E1000_RXD_ERR_IPE)) { 2919 /* IP Checksum Good */ 2920 mp->m_pkthdr.csum_flags = M_IPV4_CSUM_IN_OK; 2921 2922 } else 2923 mp->m_pkthdr.csum_flags = 0; 2924 } 2925 2926 if (rx_desc->status & E1000_RXD_STAT_TCPCS) { 2927 /* Did it pass? */ 2928 if (!(rx_desc->errors & E1000_RXD_ERR_TCPE)) 2929 mp->m_pkthdr.csum_flags |= 2930 M_TCP_CSUM_IN_OK | M_UDP_CSUM_IN_OK; 2931 } 2932 } 2933 2934 /* 2935 * This turns on the hardware offload of the VLAN 2936 * tag insertion and strip 2937 */ 2938 void 2939 em_enable_hw_vlans(struct em_softc *sc) 2940 { 2941 uint32_t ctrl; 2942 2943 ctrl = E1000_READ_REG(&sc->hw, CTRL); 2944 ctrl |= E1000_CTRL_VME; 2945 E1000_WRITE_REG(&sc->hw, CTRL, ctrl); 2946 } 2947 2948 void 2949 em_enable_intr(struct em_softc *sc) 2950 { 2951 E1000_WRITE_REG(&sc->hw, IMS, (IMS_ENABLE_MASK)); 2952 } 2953 2954 void 2955 em_disable_intr(struct em_softc *sc) 2956 { 2957 /* 2958 * The first version of 82542 had an errata where when link 2959 * was forced it would stay up even if the cable was disconnected 2960 * Sequence errors were used to detect the disconnect and then 2961 * the driver would unforce the link. This code is in the ISR. 2962 * For this to work correctly the Sequence error interrupt had 2963 * to be enabled all the time. 2964 */ 2965 2966 if (sc->hw.mac_type == em_82542_rev2_0) 2967 E1000_WRITE_REG(&sc->hw, IMC, (0xffffffff & ~E1000_IMC_RXSEQ)); 2968 else 2969 E1000_WRITE_REG(&sc->hw, IMC, 0xffffffff); 2970 } 2971 2972 void 2973 em_write_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t *value) 2974 { 2975 struct pci_attach_args *pa = &((struct em_osdep *)hw->back)->em_pa; 2976 pcireg_t val; 2977 2978 val = pci_conf_read(pa->pa_pc, pa->pa_tag, reg & ~0x3); 2979 if (reg & 0x2) { 2980 val &= 0x0000ffff; 2981 val |= (*value << 16); 2982 } else { 2983 val &= 0xffff0000; 2984 val |= *value; 2985 } 2986 pci_conf_write(pa->pa_pc, pa->pa_tag, reg & ~0x3, val); 2987 } 2988 2989 void 2990 em_read_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t *value) 2991 { 2992 struct pci_attach_args *pa = &((struct em_osdep *)hw->back)->em_pa; 2993 pcireg_t val; 2994 2995 val = pci_conf_read(pa->pa_pc, pa->pa_tag, reg & ~0x3); 2996 if (reg & 0x2) 2997 *value = (val >> 16) & 0xffff; 2998 else 2999 *value = val & 0xffff; 3000 } 3001 3002 void 3003 em_pci_set_mwi(struct em_hw *hw) 3004 { 3005 struct pci_attach_args *pa = &((struct em_osdep *)hw->back)->em_pa; 3006 3007 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 3008 (hw->pci_cmd_word | CMD_MEM_WRT_INVALIDATE)); 3009 } 3010 3011 void 3012 em_pci_clear_mwi(struct em_hw *hw) 3013 { 3014 struct pci_attach_args *pa = &((struct em_osdep *)hw->back)->em_pa; 3015 3016 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 3017 (hw->pci_cmd_word & ~CMD_MEM_WRT_INVALIDATE)); 3018 } 3019 3020 /* 3021 * We may eventually really do this, but its unnecessary 3022 * for now so we just return unsupported. 3023 */ 3024 int32_t 3025 em_read_pcie_cap_reg(struct em_hw *hw, uint32_t reg, uint16_t *value) 3026 { 3027 return -E1000_NOT_IMPLEMENTED; 3028 } 3029 3030 /********************************************************************* 3031 * 82544 Coexistence issue workaround. 3032 * There are 2 issues. 3033 * 1. Transmit Hang issue. 3034 * To detect this issue, following equation can be used... 3035 * SIZE[3:0] + ADDR[2:0] = SUM[3:0]. 3036 * If SUM[3:0] is in between 1 to 4, we will have this issue. 3037 * 3038 * 2. DAC issue. 3039 * To detect this issue, following equation can be used... 3040 * SIZE[3:0] + ADDR[2:0] = SUM[3:0]. 3041 * If SUM[3:0] is in between 9 to c, we will have this issue. 3042 * 3043 * 3044 * WORKAROUND: 3045 * Make sure we do not have ending address as 1,2,3,4(Hang) or 9,a,b,c (DAC) 3046 * 3047 *** *********************************************************************/ 3048 u_int32_t 3049 em_fill_descriptors(u_int64_t address, u_int32_t length, 3050 PDESC_ARRAY desc_array) 3051 { 3052 /* Since issue is sensitive to length and address.*/ 3053 /* Let us first check the address...*/ 3054 u_int32_t safe_terminator; 3055 if (length <= 4) { 3056 desc_array->descriptor[0].address = address; 3057 desc_array->descriptor[0].length = length; 3058 desc_array->elements = 1; 3059 return desc_array->elements; 3060 } 3061 safe_terminator = (u_int32_t)((((u_int32_t)address & 0x7) + (length & 0xF)) & 0xF); 3062 /* if it does not fall between 0x1 to 0x4 and 0x9 to 0xC then return */ 3063 if (safe_terminator == 0 || 3064 (safe_terminator > 4 && 3065 safe_terminator < 9) || 3066 (safe_terminator > 0xC && 3067 safe_terminator <= 0xF)) { 3068 desc_array->descriptor[0].address = address; 3069 desc_array->descriptor[0].length = length; 3070 desc_array->elements = 1; 3071 return desc_array->elements; 3072 } 3073 3074 desc_array->descriptor[0].address = address; 3075 desc_array->descriptor[0].length = length - 4; 3076 desc_array->descriptor[1].address = address + (length - 4); 3077 desc_array->descriptor[1].length = 4; 3078 desc_array->elements = 2; 3079 return desc_array->elements; 3080 } 3081 3082 /* 3083 * Disable the L0S and L1 LINK states. 3084 */ 3085 void 3086 em_disable_aspm(struct em_softc *sc) 3087 { 3088 int offset; 3089 pcireg_t val; 3090 3091 switch (sc->hw.mac_type) { 3092 case em_82571: 3093 case em_82572: 3094 case em_82573: 3095 case em_82574: 3096 break; 3097 default: 3098 return; 3099 } 3100 3101 if (!pci_get_capability(sc->osdep.em_pa.pa_pc, sc->osdep.em_pa.pa_tag, 3102 PCI_CAP_PCIEXPRESS, &offset, NULL)) 3103 return; 3104 3105 /* Disable PCIe Active State Power Management (ASPM). */ 3106 val = pci_conf_read(sc->osdep.em_pa.pa_pc, sc->osdep.em_pa.pa_tag, 3107 offset + PCI_PCIE_LCSR); 3108 3109 switch (sc->hw.mac_type) { 3110 case em_82571: 3111 case em_82572: 3112 val &= ~PCI_PCIE_LCSR_ASPM_L1; 3113 break; 3114 case em_82573: 3115 case em_82574: 3116 val &= ~(PCI_PCIE_LCSR_ASPM_L0S | 3117 PCI_PCIE_LCSR_ASPM_L1); 3118 break; 3119 default: 3120 break; 3121 } 3122 3123 pci_conf_write(sc->osdep.em_pa.pa_pc, sc->osdep.em_pa.pa_tag, 3124 offset + PCI_PCIE_LCSR, val); 3125 } 3126 3127 /* 3128 * em_flush_tx_ring - remove all descriptors from the tx_ring 3129 * 3130 * We want to clear all pending descriptors from the TX ring. 3131 * zeroing happens when the HW reads the regs. We assign the ring itself as 3132 * the data of the next descriptor. We don't care about the data we are about 3133 * to reset the HW. 3134 */ 3135 void 3136 em_flush_tx_ring(struct em_softc *sc) 3137 { 3138 uint32_t tctl, txd_lower = E1000_TXD_CMD_IFCS; 3139 uint16_t size = 512; 3140 struct em_tx_desc *txd; 3141 3142 KASSERT(sc->sc_tx_desc_ring != NULL); 3143 3144 tctl = EM_READ_REG(&sc->hw, E1000_TCTL); 3145 EM_WRITE_REG(&sc->hw, E1000_TCTL, tctl | E1000_TCTL_EN); 3146 3147 KASSERT(EM_READ_REG(&sc->hw, E1000_TDT) == sc->sc_tx_desc_head); 3148 3149 txd = &sc->sc_tx_desc_ring[sc->sc_tx_desc_head]; 3150 txd->buffer_addr = sc->sc_tx_dma.dma_map->dm_segs[0].ds_addr; 3151 txd->lower.data = htole32(txd_lower | size); 3152 txd->upper.data = 0; 3153 3154 /* flush descriptors to memory before notifying the HW */ 3155 bus_space_barrier(sc->osdep.mem_bus_space_tag, 3156 sc->osdep.mem_bus_space_handle, 0, 0, BUS_SPACE_BARRIER_WRITE); 3157 3158 if (++sc->sc_tx_desc_head == sc->sc_tx_slots) 3159 sc->sc_tx_desc_head = 0; 3160 3161 EM_WRITE_REG(&sc->hw, E1000_TDT, sc->sc_tx_desc_head); 3162 bus_space_barrier(sc->osdep.mem_bus_space_tag, sc->osdep.mem_bus_space_handle, 3163 0, 0, BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE); 3164 usec_delay(250); 3165 } 3166 3167 /* 3168 * em_flush_rx_ring - remove all descriptors from the rx_ring 3169 * 3170 * Mark all descriptors in the RX ring as consumed and disable the rx ring 3171 */ 3172 void 3173 em_flush_rx_ring(struct em_softc *sc) 3174 { 3175 uint32_t rctl, rxdctl; 3176 3177 rctl = EM_READ_REG(&sc->hw, E1000_RCTL); 3178 EM_WRITE_REG(&sc->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 3179 E1000_WRITE_FLUSH(&sc->hw); 3180 usec_delay(150); 3181 3182 rxdctl = EM_READ_REG(&sc->hw, E1000_RXDCTL); 3183 /* zero the lower 14 bits (prefetch and host thresholds) */ 3184 rxdctl &= 0xffffc000; 3185 /* 3186 * update thresholds: prefetch threshold to 31, host threshold to 1 3187 * and make sure the granularity is "descriptors" and not "cache lines" 3188 */ 3189 rxdctl |= (0x1F | (1 << 8) | E1000_RXDCTL_THRESH_UNIT_DESC); 3190 EM_WRITE_REG(&sc->hw, E1000_RXDCTL, rxdctl); 3191 3192 /* momentarily enable the RX ring for the changes to take effect */ 3193 EM_WRITE_REG(&sc->hw, E1000_RCTL, rctl | E1000_RCTL_EN); 3194 E1000_WRITE_FLUSH(&sc->hw); 3195 usec_delay(150); 3196 EM_WRITE_REG(&sc->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 3197 } 3198 3199 /* 3200 * em_flush_desc_rings - remove all descriptors from the descriptor rings 3201 * 3202 * In i219, the descriptor rings must be emptied before resetting the HW 3203 * or before changing the device state to D3 during runtime (runtime PM). 3204 * 3205 * Failure to do this will cause the HW to enter a unit hang state which can 3206 * only be released by PCI reset on the device 3207 * 3208 */ 3209 void 3210 em_flush_desc_rings(struct em_softc *sc) 3211 { 3212 struct pci_attach_args *pa = &sc->osdep.em_pa; 3213 uint32_t fextnvm11, tdlen; 3214 uint16_t hang_state; 3215 3216 /* First, disable MULR fix in FEXTNVM11 */ 3217 fextnvm11 = EM_READ_REG(&sc->hw, E1000_FEXTNVM11); 3218 fextnvm11 |= E1000_FEXTNVM11_DISABLE_MULR_FIX; 3219 EM_WRITE_REG(&sc->hw, E1000_FEXTNVM11, fextnvm11); 3220 3221 /* do nothing if we're not in faulty state, or if the queue is empty */ 3222 tdlen = EM_READ_REG(&sc->hw, E1000_TDLEN); 3223 hang_state = pci_conf_read(pa->pa_pc, pa->pa_tag, PCICFG_DESC_RING_STATUS); 3224 if (!(hang_state & FLUSH_DESC_REQUIRED) || !tdlen) 3225 return; 3226 em_flush_tx_ring(sc); 3227 3228 /* recheck, maybe the fault is caused by the rx ring */ 3229 hang_state = pci_conf_read(pa->pa_pc, pa->pa_tag, PCICFG_DESC_RING_STATUS); 3230 if (hang_state & FLUSH_DESC_REQUIRED) 3231 em_flush_rx_ring(sc); 3232 } 3233 3234 #ifndef SMALL_KERNEL 3235 /********************************************************************** 3236 * 3237 * Update the board statistics counters. 3238 * 3239 **********************************************************************/ 3240 void 3241 em_update_stats_counters(struct em_softc *sc) 3242 { 3243 struct ifnet *ifp = &sc->sc_ac.ac_if; 3244 3245 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, CRCERRS); 3246 sc->stats.mpc += E1000_READ_REG(&sc->hw, MPC); 3247 sc->stats.ecol += E1000_READ_REG(&sc->hw, ECOL); 3248 3249 sc->stats.latecol += E1000_READ_REG(&sc->hw, LATECOL); 3250 sc->stats.colc += E1000_READ_REG(&sc->hw, COLC); 3251 3252 sc->stats.ruc += E1000_READ_REG(&sc->hw, RUC); 3253 sc->stats.roc += E1000_READ_REG(&sc->hw, ROC); 3254 3255 if (sc->hw.mac_type >= em_82543) { 3256 sc->stats.algnerrc += 3257 E1000_READ_REG(&sc->hw, ALGNERRC); 3258 sc->stats.rxerrc += 3259 E1000_READ_REG(&sc->hw, RXERRC); 3260 sc->stats.cexterr += 3261 E1000_READ_REG(&sc->hw, CEXTERR); 3262 } 3263 3264 #ifdef EM_DEBUG 3265 if (sc->hw.media_type == em_media_type_copper || 3266 (E1000_READ_REG(&sc->hw, STATUS) & E1000_STATUS_LU)) { 3267 sc->stats.symerrs += E1000_READ_REG(&sc->hw, SYMERRS); 3268 sc->stats.sec += E1000_READ_REG(&sc->hw, SEC); 3269 } 3270 sc->stats.scc += E1000_READ_REG(&sc->hw, SCC); 3271 3272 sc->stats.mcc += E1000_READ_REG(&sc->hw, MCC); 3273 sc->stats.dc += E1000_READ_REG(&sc->hw, DC); 3274 sc->stats.rlec += E1000_READ_REG(&sc->hw, RLEC); 3275 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, XONRXC); 3276 sc->stats.xontxc += E1000_READ_REG(&sc->hw, XONTXC); 3277 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, XOFFRXC); 3278 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, XOFFTXC); 3279 sc->stats.fcruc += E1000_READ_REG(&sc->hw, FCRUC); 3280 sc->stats.prc64 += E1000_READ_REG(&sc->hw, PRC64); 3281 sc->stats.prc127 += E1000_READ_REG(&sc->hw, PRC127); 3282 sc->stats.prc255 += E1000_READ_REG(&sc->hw, PRC255); 3283 sc->stats.prc511 += E1000_READ_REG(&sc->hw, PRC511); 3284 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, PRC1023); 3285 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, PRC1522); 3286 sc->stats.gprc += E1000_READ_REG(&sc->hw, GPRC); 3287 sc->stats.bprc += E1000_READ_REG(&sc->hw, BPRC); 3288 sc->stats.mprc += E1000_READ_REG(&sc->hw, MPRC); 3289 sc->stats.gptc += E1000_READ_REG(&sc->hw, GPTC); 3290 3291 /* For the 64-bit byte counters the low dword must be read first. */ 3292 /* Both registers clear on the read of the high dword */ 3293 3294 sc->stats.gorcl += E1000_READ_REG(&sc->hw, GORCL); 3295 sc->stats.gorch += E1000_READ_REG(&sc->hw, GORCH); 3296 sc->stats.gotcl += E1000_READ_REG(&sc->hw, GOTCL); 3297 sc->stats.gotch += E1000_READ_REG(&sc->hw, GOTCH); 3298 3299 sc->stats.rnbc += E1000_READ_REG(&sc->hw, RNBC); 3300 sc->stats.rfc += E1000_READ_REG(&sc->hw, RFC); 3301 sc->stats.rjc += E1000_READ_REG(&sc->hw, RJC); 3302 3303 sc->stats.torl += E1000_READ_REG(&sc->hw, TORL); 3304 sc->stats.torh += E1000_READ_REG(&sc->hw, TORH); 3305 sc->stats.totl += E1000_READ_REG(&sc->hw, TOTL); 3306 sc->stats.toth += E1000_READ_REG(&sc->hw, TOTH); 3307 3308 sc->stats.tpr += E1000_READ_REG(&sc->hw, TPR); 3309 sc->stats.tpt += E1000_READ_REG(&sc->hw, TPT); 3310 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, PTC64); 3311 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, PTC127); 3312 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, PTC255); 3313 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, PTC511); 3314 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, PTC1023); 3315 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, PTC1522); 3316 sc->stats.mptc += E1000_READ_REG(&sc->hw, MPTC); 3317 sc->stats.bptc += E1000_READ_REG(&sc->hw, BPTC); 3318 3319 if (sc->hw.mac_type >= em_82543) { 3320 sc->stats.tncrs += 3321 E1000_READ_REG(&sc->hw, TNCRS); 3322 sc->stats.tsctc += 3323 E1000_READ_REG(&sc->hw, TSCTC); 3324 sc->stats.tsctfc += 3325 E1000_READ_REG(&sc->hw, TSCTFC); 3326 } 3327 #endif 3328 3329 /* Fill out the OS statistics structure */ 3330 ifp->if_collisions = sc->stats.colc; 3331 3332 /* Rx Errors */ 3333 ifp->if_ierrors = 3334 sc->dropped_pkts + 3335 sc->stats.rxerrc + 3336 sc->stats.crcerrs + 3337 sc->stats.algnerrc + 3338 sc->stats.ruc + sc->stats.roc + 3339 sc->stats.mpc + sc->stats.cexterr + 3340 sc->rx_overruns; 3341 3342 /* Tx Errors */ 3343 ifp->if_oerrors = sc->stats.ecol + sc->stats.latecol + 3344 sc->watchdog_events; 3345 } 3346 3347 #ifdef EM_DEBUG 3348 /********************************************************************** 3349 * 3350 * This routine is called only when IFF_DEBUG is enabled. 3351 * This routine provides a way to take a look at important statistics 3352 * maintained by the driver and hardware. 3353 * 3354 **********************************************************************/ 3355 void 3356 em_print_hw_stats(struct em_softc *sc) 3357 { 3358 const char * const unit = DEVNAME(sc); 3359 3360 printf("%s: Excessive collisions = %lld\n", unit, 3361 (long long)sc->stats.ecol); 3362 printf("%s: Symbol errors = %lld\n", unit, 3363 (long long)sc->stats.symerrs); 3364 printf("%s: Sequence errors = %lld\n", unit, 3365 (long long)sc->stats.sec); 3366 printf("%s: Defer count = %lld\n", unit, 3367 (long long)sc->stats.dc); 3368 3369 printf("%s: Missed Packets = %lld\n", unit, 3370 (long long)sc->stats.mpc); 3371 printf("%s: Receive No Buffers = %lld\n", unit, 3372 (long long)sc->stats.rnbc); 3373 /* RLEC is inaccurate on some hardware, calculate our own */ 3374 printf("%s: Receive Length Errors = %lld\n", unit, 3375 ((long long)sc->stats.roc + 3376 (long long)sc->stats.ruc)); 3377 printf("%s: Receive errors = %lld\n", unit, 3378 (long long)sc->stats.rxerrc); 3379 printf("%s: Crc errors = %lld\n", unit, 3380 (long long)sc->stats.crcerrs); 3381 printf("%s: Alignment errors = %lld\n", unit, 3382 (long long)sc->stats.algnerrc); 3383 printf("%s: Carrier extension errors = %lld\n", unit, 3384 (long long)sc->stats.cexterr); 3385 3386 printf("%s: RX overruns = %ld\n", unit, 3387 sc->rx_overruns); 3388 printf("%s: watchdog timeouts = %ld\n", unit, 3389 sc->watchdog_events); 3390 3391 printf("%s: XON Rcvd = %lld\n", unit, 3392 (long long)sc->stats.xonrxc); 3393 printf("%s: XON Xmtd = %lld\n", unit, 3394 (long long)sc->stats.xontxc); 3395 printf("%s: XOFF Rcvd = %lld\n", unit, 3396 (long long)sc->stats.xoffrxc); 3397 printf("%s: XOFF Xmtd = %lld\n", unit, 3398 (long long)sc->stats.xofftxc); 3399 3400 printf("%s: Good Packets Rcvd = %lld\n", unit, 3401 (long long)sc->stats.gprc); 3402 printf("%s: Good Packets Xmtd = %lld\n", unit, 3403 (long long)sc->stats.gptc); 3404 } 3405 #endif 3406 #endif /* !SMALL_KERNEL */ 3407