1 /************************************************************************** 2 3 Copyright (c) 2001-2003, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ***************************************************************************/ 33 34 /* $OpenBSD: if_em.c,v 1.227 2009/10/11 19:24:48 dms Exp $ */ 35 /* $FreeBSD: if_em.c,v 1.46 2004/09/29 18:28:28 mlaier Exp $ */ 36 37 #include <dev/pci/if_em.h> 38 39 #ifdef EM_DEBUG 40 /********************************************************************* 41 * Set this to one to display debug statistics 42 *********************************************************************/ 43 int em_display_debug_stats = 0; 44 #endif 45 46 /********************************************************************* 47 * Driver version 48 *********************************************************************/ 49 50 #define EM_DRIVER_VERSION "6.2.9" 51 52 /********************************************************************* 53 * PCI Device ID Table 54 *********************************************************************/ 55 const struct pci_matchid em_devices[] = { 56 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80003ES2LAN_CPR_DPT }, 57 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80003ES2LAN_SDS_DPT }, 58 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80003ES2LAN_CPR_SPT }, 59 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80003ES2LAN_SDS_SPT }, 60 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM }, 61 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM_LOM }, 62 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP }, 63 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LOM }, 64 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LP }, 65 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI }, 66 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI_MOBILE }, 67 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541ER }, 68 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541ER_LOM }, 69 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI }, 70 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI_LF }, 71 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI_MOBILE }, 72 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82542 }, 73 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_COPPER }, 74 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_FIBER }, 75 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_COPPER }, 76 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_FIBER }, 77 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_COPPER }, 78 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_LOM }, 79 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_COPPER }, 80 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_FIBER }, 81 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_COPPER }, 82 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_FIBER }, 83 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_SERDES }, 84 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_COPPER }, 85 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_FIBER }, 86 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_QUAD_CPR }, 87 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_COPPER }, 88 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_FIBER }, 89 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_PCIE }, 90 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_QUAD_CPR }, 91 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_QUAD_CPR_K }, 92 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_SERDES }, 93 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_2 }, 94 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547EI }, 95 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547EI_MOBILE }, 96 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547GI }, 97 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_AF }, 98 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_AT }, 99 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_COPPER }, 100 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_FIBER }, 101 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_QUAD_CPR }, 102 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_QUAD_CPR_LP }, 103 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_QUAD_FBR }, 104 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_SERDES }, 105 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_SDS_DUAL }, 106 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_SDS_QUAD }, 107 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571PT_QUAD_CPR }, 108 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI_COPPER }, 109 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI_FIBER }, 110 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI_SERDES }, 111 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI }, 112 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573E }, 113 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573E_IAMT }, 114 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573E_PM }, 115 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573L }, 116 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573L_PL_1 }, 117 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573L_PL_2 }, 118 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573V_PM }, 119 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82574L }, 120 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82575EB_COPPER }, 121 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82575EB_SERDES }, 122 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82575GB_QUAD_CPR }, 123 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576 }, 124 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_FIBER }, 125 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_SERDES }, 126 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_QUAD_COPPER }, 127 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_NS }, 128 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_IFE }, 129 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_IFE_G }, 130 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_IFE_GT }, 131 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_IGP_AMT }, 132 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_IGP_C }, 133 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_IGP_M }, 134 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_IGP_M_AMT }, 135 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_BM }, 136 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IFE }, 137 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IFE_G }, 138 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IFE_GT }, 139 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IGP_AMT }, 140 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IGP_C }, 141 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IGP_M }, 142 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IGP_M_AMT }, 143 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IGP_M_V }, 144 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH10_D_BM_LF }, 145 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH10_D_BM_LM }, 146 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH10_R_BM_LF }, 147 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH10_R_BM_LM }, 148 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH10_R_BM_V } 149 }; 150 151 /********************************************************************* 152 * Function prototypes 153 *********************************************************************/ 154 int em_probe(struct device *, void *, void *); 155 void em_attach(struct device *, struct device *, void *); 156 int em_detach(struct device *, int); 157 int em_intr(void *); 158 void em_power(int, void *); 159 void em_start(struct ifnet *); 160 int em_ioctl(struct ifnet *, u_long, caddr_t); 161 void em_watchdog(struct ifnet *); 162 void em_init(void *); 163 void em_stop(void *); 164 void em_media_status(struct ifnet *, struct ifmediareq *); 165 int em_media_change(struct ifnet *); 166 int em_flowstatus(struct em_softc *); 167 void em_identify_hardware(struct em_softc *); 168 int em_allocate_pci_resources(struct em_softc *); 169 void em_free_pci_resources(struct em_softc *); 170 void em_local_timer(void *); 171 int em_hardware_init(struct em_softc *); 172 void em_setup_interface(struct em_softc *); 173 int em_setup_transmit_structures(struct em_softc *); 174 void em_initialize_transmit_unit(struct em_softc *); 175 int em_setup_receive_structures(struct em_softc *); 176 void em_initialize_receive_unit(struct em_softc *); 177 void em_enable_intr(struct em_softc *); 178 void em_disable_intr(struct em_softc *); 179 void em_free_transmit_structures(struct em_softc *); 180 void em_free_receive_structures(struct em_softc *); 181 void em_update_stats_counters(struct em_softc *); 182 void em_txeof(struct em_softc *); 183 int em_allocate_receive_structures(struct em_softc *); 184 int em_allocate_transmit_structures(struct em_softc *); 185 #ifdef __STRICT_ALIGNMENT 186 void em_realign(struct em_softc *, struct mbuf *, u_int16_t *); 187 #else 188 #define em_realign(a, b, c) /* a, b, c */ 189 #endif 190 int em_rxfill(struct em_softc *); 191 void em_rxeof(struct em_softc *, int); 192 void em_receive_checksum(struct em_softc *, struct em_rx_desc *, 193 struct mbuf *); 194 #ifdef EM_CSUM_OFFLOAD 195 void em_transmit_checksum_setup(struct em_softc *, struct mbuf *, 196 u_int32_t *, u_int32_t *); 197 #endif 198 void em_iff(struct em_softc *); 199 #ifdef EM_DEBUG 200 void em_print_hw_stats(struct em_softc *); 201 #endif 202 void em_update_link_status(struct em_softc *); 203 int em_get_buf(struct em_softc *, int); 204 void em_enable_hw_vlans(struct em_softc *); 205 int em_encap(struct em_softc *, struct mbuf *); 206 void em_smartspeed(struct em_softc *); 207 int em_82547_fifo_workaround(struct em_softc *, int); 208 void em_82547_update_fifo_head(struct em_softc *, int); 209 int em_82547_tx_fifo_reset(struct em_softc *); 210 void em_82547_move_tail(void *arg); 211 void em_82547_move_tail_locked(struct em_softc *); 212 int em_dma_malloc(struct em_softc *, bus_size_t, struct em_dma_alloc *, 213 int); 214 void em_dma_free(struct em_softc *, struct em_dma_alloc *); 215 int em_is_valid_ether_addr(u_int8_t *); 216 u_int32_t em_fill_descriptors(u_int64_t address, u_int32_t length, 217 PDESC_ARRAY desc_array); 218 219 /********************************************************************* 220 * OpenBSD Device Interface Entry Points 221 *********************************************************************/ 222 223 struct cfattach em_ca = { 224 sizeof(struct em_softc), em_probe, em_attach, em_detach 225 }; 226 227 struct cfdriver em_cd = { 228 NULL, "em", DV_IFNET 229 }; 230 231 static int em_smart_pwr_down = FALSE; 232 233 /********************************************************************* 234 * Device identification routine 235 * 236 * em_probe determines if the driver should be loaded on 237 * adapter based on PCI vendor/device id of the adapter. 238 * 239 * return 0 on no match, positive on match 240 *********************************************************************/ 241 242 int 243 em_probe(struct device *parent, void *match, void *aux) 244 { 245 INIT_DEBUGOUT("em_probe: begin"); 246 247 return (pci_matchbyid((struct pci_attach_args *)aux, em_devices, 248 sizeof(em_devices)/sizeof(em_devices[0]))); 249 } 250 251 /********************************************************************* 252 * Device initialization routine 253 * 254 * The attach entry point is called when the driver is being loaded. 255 * This routine identifies the type of hardware, allocates all resources 256 * and initializes the hardware. 257 * 258 *********************************************************************/ 259 260 void 261 em_attach(struct device *parent, struct device *self, void *aux) 262 { 263 struct pci_attach_args *pa = aux; 264 struct em_softc *sc; 265 int tsize, rsize; 266 267 INIT_DEBUGOUT("em_attach: begin"); 268 269 sc = (struct em_softc *)self; 270 sc->osdep.em_pa = *pa; 271 272 timeout_set(&sc->timer_handle, em_local_timer, sc); 273 timeout_set(&sc->tx_fifo_timer_handle, em_82547_move_tail, sc); 274 275 /* Determine hardware revision */ 276 em_identify_hardware(sc); 277 278 /* Parameters (to be read from user) */ 279 if (sc->hw.mac_type >= em_82544) { 280 sc->num_tx_desc = EM_MAX_TXD; 281 sc->num_rx_desc = EM_MAX_RXD; 282 } else { 283 sc->num_tx_desc = EM_MAX_TXD_82543; 284 sc->num_rx_desc = EM_MAX_RXD_82543; 285 } 286 sc->tx_int_delay = EM_TIDV; 287 sc->tx_abs_int_delay = EM_TADV; 288 sc->rx_int_delay = EM_RDTR; 289 sc->rx_abs_int_delay = EM_RADV; 290 sc->hw.autoneg = DO_AUTO_NEG; 291 sc->hw.wait_autoneg_complete = WAIT_FOR_AUTO_NEG_DEFAULT; 292 sc->hw.autoneg_advertised = AUTONEG_ADV_DEFAULT; 293 sc->hw.tbi_compatibility_en = TRUE; 294 sc->rx_buffer_len = EM_RXBUFFER_2048; 295 296 sc->hw.phy_init_script = 1; 297 sc->hw.phy_reset_disable = FALSE; 298 299 #ifndef EM_MASTER_SLAVE 300 sc->hw.master_slave = em_ms_hw_default; 301 #else 302 sc->hw.master_slave = EM_MASTER_SLAVE; 303 #endif 304 305 /* 306 * This controls when hardware reports transmit completion 307 * status. 308 */ 309 sc->hw.report_tx_early = 1; 310 311 if (em_allocate_pci_resources(sc)) 312 goto err_pci; 313 314 /* Initialize eeprom parameters */ 315 em_init_eeprom_params(&sc->hw); 316 317 /* 318 * Set the max frame size assuming standard Ethernet 319 * sized frames. 320 */ 321 switch (sc->hw.mac_type) { 322 case em_82573: 323 { 324 uint16_t eeprom_data = 0; 325 326 /* 327 * 82573 only supports Jumbo frames 328 * if ASPM is disabled. 329 */ 330 em_read_eeprom(&sc->hw, EEPROM_INIT_3GIO_3, 331 1, &eeprom_data); 332 if (eeprom_data & EEPROM_WORD1A_ASPM_MASK) { 333 sc->hw.max_frame_size = ETHER_MAX_LEN; 334 break; 335 } 336 /* Allow Jumbo frames */ 337 /* FALLTHROUGH */ 338 } 339 case em_82571: 340 case em_82572: 341 case em_82574: 342 case em_82575: 343 case em_ich9lan: 344 case em_ich10lan: 345 case em_80003es2lan: 346 /* Limit Jumbo Frame size */ 347 sc->hw.max_frame_size = 9234; 348 break; 349 case em_82542_rev2_0: 350 case em_82542_rev2_1: 351 case em_ich8lan: 352 /* Adapters that do not support Jumbo frames */ 353 sc->hw.max_frame_size = ETHER_MAX_LEN; 354 break; 355 default: 356 sc->hw.max_frame_size = 357 MAX_JUMBO_FRAME_SIZE; 358 } 359 360 sc->hw.min_frame_size = 361 ETHER_MIN_LEN + ETHER_CRC_LEN; 362 363 if (sc->hw.mac_type >= em_82544) 364 tsize = EM_ROUNDUP(sc->num_tx_desc * sizeof(struct em_tx_desc), 365 EM_MAX_TXD * sizeof(struct em_tx_desc)); 366 else 367 tsize = EM_ROUNDUP(sc->num_tx_desc * sizeof(struct em_tx_desc), 368 EM_MAX_TXD_82543 * sizeof(struct em_tx_desc)); 369 tsize = EM_ROUNDUP(tsize, PAGE_SIZE); 370 371 /* Allocate Transmit Descriptor ring */ 372 if (em_dma_malloc(sc, tsize, &sc->txdma, BUS_DMA_NOWAIT)) { 373 printf("%s: Unable to allocate tx_desc memory\n", 374 sc->sc_dv.dv_xname); 375 goto err_tx_desc; 376 } 377 sc->tx_desc_base = (struct em_tx_desc *)sc->txdma.dma_vaddr; 378 379 if (sc->hw.mac_type >= em_82544) 380 rsize = EM_ROUNDUP(sc->num_rx_desc * sizeof(struct em_rx_desc), 381 EM_MAX_RXD * sizeof(struct em_rx_desc)); 382 else 383 rsize = EM_ROUNDUP(sc->num_rx_desc * sizeof(struct em_rx_desc), 384 EM_MAX_RXD_82543 * sizeof(struct em_rx_desc)); 385 rsize = EM_ROUNDUP(rsize, PAGE_SIZE); 386 387 /* Allocate Receive Descriptor ring */ 388 if (em_dma_malloc(sc, rsize, &sc->rxdma, BUS_DMA_NOWAIT)) { 389 printf("%s: Unable to allocate rx_desc memory\n", 390 sc->sc_dv.dv_xname); 391 goto err_rx_desc; 392 } 393 sc->rx_desc_base = (struct em_rx_desc *) sc->rxdma.dma_vaddr; 394 395 /* Initialize the hardware */ 396 if (em_hardware_init(sc)) { 397 printf("%s: Unable to initialize the hardware\n", 398 sc->sc_dv.dv_xname); 399 goto err_hw_init; 400 } 401 402 /* Copy the permanent MAC address out of the EEPROM */ 403 if (em_read_mac_addr(&sc->hw) < 0) { 404 printf("%s: EEPROM read error while reading mac address\n", 405 sc->sc_dv.dv_xname); 406 goto err_mac_addr; 407 } 408 409 if (!em_is_valid_ether_addr(sc->hw.mac_addr)) { 410 printf("%s: Invalid mac address\n", sc->sc_dv.dv_xname); 411 goto err_mac_addr; 412 } 413 414 bcopy(sc->hw.mac_addr, sc->interface_data.ac_enaddr, 415 ETHER_ADDR_LEN); 416 417 /* Setup OS specific network interface */ 418 em_setup_interface(sc); 419 420 /* Initialize statistics */ 421 em_clear_hw_cntrs(&sc->hw); 422 em_update_stats_counters(sc); 423 sc->hw.get_link_status = 1; 424 em_update_link_status(sc); 425 426 printf(", address %s\n", ether_sprintf(sc->interface_data.ac_enaddr)); 427 428 /* Indicate SOL/IDER usage */ 429 if (em_check_phy_reset_block(&sc->hw)) 430 printf("%s: PHY reset is blocked due to SOL/IDER session.\n", 431 sc->sc_dv.dv_xname); 432 433 /* Identify 82544 on PCI-X */ 434 em_get_bus_info(&sc->hw); 435 if (sc->hw.bus_type == em_bus_type_pcix && 436 sc->hw.mac_type == em_82544) 437 sc->pcix_82544 = TRUE; 438 else 439 sc->pcix_82544 = FALSE; 440 INIT_DEBUGOUT("em_attach: end"); 441 sc->sc_powerhook = powerhook_establish(em_power, sc); 442 return; 443 444 err_mac_addr: 445 err_hw_init: 446 em_dma_free(sc, &sc->rxdma); 447 err_rx_desc: 448 em_dma_free(sc, &sc->txdma); 449 err_tx_desc: 450 err_pci: 451 em_free_pci_resources(sc); 452 } 453 454 void 455 em_power(int why, void *arg) 456 { 457 struct em_softc *sc = (struct em_softc *)arg; 458 struct ifnet *ifp; 459 460 if (why == PWR_RESUME) { 461 ifp = &sc->interface_data.ac_if; 462 if (ifp->if_flags & IFF_UP) 463 em_init(sc); 464 } 465 } 466 467 /********************************************************************* 468 * Transmit entry point 469 * 470 * em_start is called by the stack to initiate a transmit. 471 * The driver will remain in this routine as long as there are 472 * packets to transmit and transmit resources are available. 473 * In case resources are not available stack is notified and 474 * the packet is requeued. 475 **********************************************************************/ 476 477 void 478 em_start(struct ifnet *ifp) 479 { 480 struct mbuf *m_head; 481 struct em_softc *sc = ifp->if_softc; 482 int post = 0; 483 484 if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING) 485 return; 486 487 if (!sc->link_active) 488 return; 489 490 if (sc->hw.mac_type != em_82547) { 491 bus_dmamap_sync(sc->txdma.dma_tag, sc->txdma.dma_map, 0, 492 sc->txdma.dma_map->dm_mapsize, 493 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 494 } 495 496 for (;;) { 497 IFQ_POLL(&ifp->if_snd, m_head); 498 if (m_head == NULL) 499 break; 500 501 if (em_encap(sc, m_head)) { 502 ifp->if_flags |= IFF_OACTIVE; 503 break; 504 } 505 506 IFQ_DEQUEUE(&ifp->if_snd, m_head); 507 508 #if NBPFILTER > 0 509 /* Send a copy of the frame to the BPF listener */ 510 if (ifp->if_bpf) 511 bpf_mtap_ether(ifp->if_bpf, m_head, BPF_DIRECTION_OUT); 512 #endif 513 514 /* Set timeout in case hardware has problems transmitting */ 515 ifp->if_timer = EM_TX_TIMEOUT; 516 517 post = 1; 518 } 519 520 if (sc->hw.mac_type != em_82547) { 521 bus_dmamap_sync(sc->txdma.dma_tag, sc->txdma.dma_map, 0, 522 sc->txdma.dma_map->dm_mapsize, 523 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 524 /* 525 * Advance the Transmit Descriptor Tail (Tdt), 526 * this tells the E1000 that this frame is 527 * available to transmit. 528 */ 529 if (post) 530 E1000_WRITE_REG(&sc->hw, TDT, sc->next_avail_tx_desc); 531 } 532 } 533 534 /********************************************************************* 535 * Ioctl entry point 536 * 537 * em_ioctl is called when the user wants to configure the 538 * interface. 539 * 540 * return 0 on success, positive on failure 541 **********************************************************************/ 542 543 int 544 em_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 545 { 546 int error = 0; 547 struct ifreq *ifr = (struct ifreq *) data; 548 struct ifaddr *ifa = (struct ifaddr *)data; 549 struct em_softc *sc = ifp->if_softc; 550 int s; 551 552 s = splnet(); 553 554 switch (command) { 555 case SIOCSIFADDR: 556 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFADDR (Set Interface " 557 "Addr)"); 558 if (!(ifp->if_flags & IFF_UP)) { 559 ifp->if_flags |= IFF_UP; 560 em_init(sc); 561 } 562 #ifdef INET 563 if (ifa->ifa_addr->sa_family == AF_INET) 564 arp_ifinit(&sc->interface_data, ifa); 565 #endif /* INET */ 566 break; 567 568 case SIOCSIFFLAGS: 569 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFFLAGS (Set Interface Flags)"); 570 if (ifp->if_flags & IFF_UP) { 571 if (ifp->if_flags & IFF_RUNNING) 572 error = ENETRESET; 573 else 574 em_init(sc); 575 } else { 576 if (ifp->if_flags & IFF_RUNNING) 577 em_stop(sc); 578 } 579 break; 580 581 case SIOCSIFMEDIA: 582 /* Check SOL/IDER usage */ 583 if (em_check_phy_reset_block(&sc->hw)) { 584 printf("%s: Media change is blocked due to SOL/IDER session.\n", 585 sc->sc_dv.dv_xname); 586 break; 587 } 588 case SIOCGIFMEDIA: 589 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCxIFMEDIA (Get/Set Interface Media)"); 590 error = ifmedia_ioctl(ifp, ifr, &sc->media, command); 591 break; 592 593 default: 594 error = ether_ioctl(ifp, &sc->interface_data, command, data); 595 } 596 597 if (error == ENETRESET) { 598 if (ifp->if_flags & IFF_RUNNING) { 599 em_disable_intr(sc); 600 em_iff(sc); 601 if (sc->hw.mac_type == em_82542_rev2_0) 602 em_initialize_receive_unit(sc); 603 em_enable_intr(sc); 604 } 605 error = 0; 606 } 607 608 splx(s); 609 return (error); 610 } 611 612 /********************************************************************* 613 * Watchdog entry point 614 * 615 * This routine is called whenever hardware quits transmitting. 616 * 617 **********************************************************************/ 618 619 void 620 em_watchdog(struct ifnet *ifp) 621 { 622 struct em_softc *sc = ifp->if_softc; 623 624 /* If we are in this routine because of pause frames, then 625 * don't reset the hardware. 626 */ 627 if (E1000_READ_REG(&sc->hw, STATUS) & E1000_STATUS_TXOFF) { 628 ifp->if_timer = EM_TX_TIMEOUT; 629 return; 630 } 631 632 printf("%s: watchdog timeout -- resetting\n", sc->sc_dv.dv_xname); 633 634 em_init(sc); 635 636 sc->watchdog_events++; 637 } 638 639 /********************************************************************* 640 * Init entry point 641 * 642 * This routine is used in two ways. It is used by the stack as 643 * init entry point in network interface structure. It is also used 644 * by the driver as a hw/sw initialization routine to get to a 645 * consistent state. 646 * 647 **********************************************************************/ 648 649 void 650 em_init(void *arg) 651 { 652 struct em_softc *sc = arg; 653 struct ifnet *ifp = &sc->interface_data.ac_if; 654 uint32_t pba; 655 int s; 656 657 s = splnet(); 658 659 INIT_DEBUGOUT("em_init: begin"); 660 661 em_stop(sc); 662 663 /* 664 * Packet Buffer Allocation (PBA) 665 * Writing PBA sets the receive portion of the buffer 666 * the remainder is used for the transmit buffer. 667 * 668 * Devices before the 82547 had a Packet Buffer of 64K. 669 * Default allocation: PBA=48K for Rx, leaving 16K for Tx. 670 * After the 82547 the buffer was reduced to 40K. 671 * Default allocation: PBA=30K for Rx, leaving 10K for Tx. 672 * Note: default does not leave enough room for Jumbo Frame >10k. 673 */ 674 switch (sc->hw.mac_type) { 675 case em_82547: 676 case em_82547_rev_2: /* 82547: Total Packet Buffer is 40K */ 677 if (sc->hw.max_frame_size > EM_RXBUFFER_8192) 678 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 679 else 680 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 681 sc->tx_fifo_head = 0; 682 sc->tx_head_addr = pba << EM_TX_HEAD_ADDR_SHIFT; 683 sc->tx_fifo_size = (E1000_PBA_40K - pba) << EM_PBA_BYTES_SHIFT; 684 break; 685 case em_82571: 686 case em_82572: /* Total Packet Buffer on these is 48k */ 687 case em_82575: 688 case em_80003es2lan: 689 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 690 break; 691 case em_82573: /* 82573: Total Packet Buffer is 32K */ 692 /* Jumbo frames not supported */ 693 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 694 break; 695 case em_82574: /* Total Packet Buffer is 40k */ 696 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 697 break; 698 case em_ich8lan: 699 pba = E1000_PBA_8K; 700 break; 701 case em_ich9lan: 702 case em_ich10lan: 703 pba = E1000_PBA_10K; 704 break; 705 default: 706 /* Devices before 82547 had a Packet Buffer of 64K. */ 707 if (sc->hw.max_frame_size > EM_RXBUFFER_8192) 708 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 709 else 710 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 711 } 712 INIT_DEBUGOUT1("em_init: pba=%dK",pba); 713 E1000_WRITE_REG(&sc->hw, PBA, pba); 714 715 /* Get the latest mac address, User can use a LAA */ 716 bcopy(sc->interface_data.ac_enaddr, sc->hw.mac_addr, 717 ETHER_ADDR_LEN); 718 719 /* Initialize the hardware */ 720 if (em_hardware_init(sc)) { 721 printf("%s: Unable to initialize the hardware\n", 722 sc->sc_dv.dv_xname); 723 splx(s); 724 return; 725 } 726 em_update_link_status(sc); 727 728 E1000_WRITE_REG(&sc->hw, VET, ETHERTYPE_VLAN); 729 if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) 730 em_enable_hw_vlans(sc); 731 732 /* Prepare transmit descriptors and buffers */ 733 if (em_setup_transmit_structures(sc)) { 734 printf("%s: Could not setup transmit structures\n", 735 sc->sc_dv.dv_xname); 736 em_stop(sc); 737 splx(s); 738 return; 739 } 740 em_initialize_transmit_unit(sc); 741 742 /* Prepare receive descriptors and buffers */ 743 if (em_setup_receive_structures(sc)) { 744 printf("%s: Could not setup receive structures\n", 745 sc->sc_dv.dv_xname); 746 em_stop(sc); 747 splx(s); 748 return; 749 } 750 em_initialize_receive_unit(sc); 751 752 /* Program promiscuous mode and multicast filters. */ 753 em_iff(sc); 754 755 ifp->if_flags |= IFF_RUNNING; 756 ifp->if_flags &= ~IFF_OACTIVE; 757 758 timeout_add_sec(&sc->timer_handle, 1); 759 em_clear_hw_cntrs(&sc->hw); 760 em_enable_intr(sc); 761 762 /* Don't reset the phy next time init gets called */ 763 sc->hw.phy_reset_disable = TRUE; 764 765 splx(s); 766 } 767 768 /********************************************************************* 769 * 770 * Interrupt Service routine 771 * 772 **********************************************************************/ 773 int 774 em_intr(void *arg) 775 { 776 struct em_softc *sc = arg; 777 struct ifnet *ifp; 778 u_int32_t reg_icr, test_icr; 779 int claimed = 0; 780 int refill; 781 782 ifp = &sc->interface_data.ac_if; 783 784 for (;;) { 785 test_icr = reg_icr = E1000_READ_REG(&sc->hw, ICR); 786 if (sc->hw.mac_type >= em_82571) 787 test_icr = (reg_icr & E1000_ICR_INT_ASSERTED); 788 if (!test_icr) 789 break; 790 791 claimed = 1; 792 refill = 0; 793 794 if (ifp->if_flags & IFF_RUNNING) { 795 em_rxeof(sc, -1); 796 em_txeof(sc); 797 refill = 1; 798 } 799 800 /* Link status change */ 801 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 802 timeout_del(&sc->timer_handle); 803 sc->hw.get_link_status = 1; 804 em_check_for_link(&sc->hw); 805 em_update_link_status(sc); 806 timeout_add_sec(&sc->timer_handle, 1); 807 } 808 809 if (reg_icr & E1000_ICR_RXO) { 810 sc->rx_overruns++; 811 refill = 1; 812 } 813 814 if (refill && em_rxfill(sc)) { 815 /* Advance the Rx Queue #0 "Tail Pointer". */ 816 E1000_WRITE_REG(&sc->hw, RDT, sc->last_rx_desc_filled); 817 } 818 } 819 820 if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd)) 821 em_start(ifp); 822 823 return (claimed); 824 } 825 826 /********************************************************************* 827 * 828 * Media Ioctl callback 829 * 830 * This routine is called whenever the user queries the status of 831 * the interface using ifconfig. 832 * 833 **********************************************************************/ 834 void 835 em_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 836 { 837 struct em_softc *sc = ifp->if_softc; 838 u_char fiber_type = IFM_1000_SX; 839 u_int16_t gsr; 840 841 INIT_DEBUGOUT("em_media_status: begin"); 842 843 em_check_for_link(&sc->hw); 844 em_update_link_status(sc); 845 846 ifmr->ifm_status = IFM_AVALID; 847 ifmr->ifm_active = IFM_ETHER; 848 849 if (!sc->link_active) { 850 ifmr->ifm_active |= IFM_NONE; 851 return; 852 } 853 854 ifmr->ifm_status |= IFM_ACTIVE; 855 856 if (sc->hw.media_type == em_media_type_fiber || 857 sc->hw.media_type == em_media_type_internal_serdes) { 858 if (sc->hw.mac_type == em_82545) 859 fiber_type = IFM_1000_LX; 860 ifmr->ifm_active |= fiber_type | IFM_FDX; 861 } else { 862 switch (sc->link_speed) { 863 case 10: 864 ifmr->ifm_active |= IFM_10_T; 865 break; 866 case 100: 867 ifmr->ifm_active |= IFM_100_TX; 868 break; 869 case 1000: 870 ifmr->ifm_active |= IFM_1000_T; 871 break; 872 } 873 874 if (sc->link_duplex == FULL_DUPLEX) 875 ifmr->ifm_active |= em_flowstatus(sc) | IFM_FDX; 876 else 877 ifmr->ifm_active |= IFM_HDX; 878 879 if (IFM_SUBTYPE(ifmr->ifm_active) == IFM_1000_T) { 880 em_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &gsr); 881 if (gsr & SR_1000T_MS_CONFIG_RES) 882 ifmr->ifm_active |= IFM_ETH_MASTER; 883 } 884 } 885 } 886 887 /********************************************************************* 888 * 889 * Media Ioctl callback 890 * 891 * This routine is called when the user changes speed/duplex using 892 * media/mediopt option with ifconfig. 893 * 894 **********************************************************************/ 895 int 896 em_media_change(struct ifnet *ifp) 897 { 898 struct em_softc *sc = ifp->if_softc; 899 struct ifmedia *ifm = &sc->media; 900 901 INIT_DEBUGOUT("em_media_change: begin"); 902 903 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 904 return (EINVAL); 905 906 switch (IFM_SUBTYPE(ifm->ifm_media)) { 907 case IFM_AUTO: 908 sc->hw.autoneg = DO_AUTO_NEG; 909 sc->hw.autoneg_advertised = AUTONEG_ADV_DEFAULT; 910 break; 911 case IFM_1000_LX: 912 case IFM_1000_SX: 913 case IFM_1000_T: 914 sc->hw.autoneg = DO_AUTO_NEG; 915 sc->hw.autoneg_advertised = ADVERTISE_1000_FULL; 916 break; 917 case IFM_100_TX: 918 sc->hw.autoneg = FALSE; 919 sc->hw.autoneg_advertised = 0; 920 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 921 sc->hw.forced_speed_duplex = em_100_full; 922 else 923 sc->hw.forced_speed_duplex = em_100_half; 924 break; 925 case IFM_10_T: 926 sc->hw.autoneg = FALSE; 927 sc->hw.autoneg_advertised = 0; 928 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 929 sc->hw.forced_speed_duplex = em_10_full; 930 else 931 sc->hw.forced_speed_duplex = em_10_half; 932 break; 933 default: 934 printf("%s: Unsupported media type\n", sc->sc_dv.dv_xname); 935 } 936 937 /* 938 * As the speed/duplex settings may have changed we need to 939 * reset the PHY. 940 */ 941 sc->hw.phy_reset_disable = FALSE; 942 943 em_init(sc); 944 945 return (0); 946 } 947 948 int 949 em_flowstatus(struct em_softc *sc) 950 { 951 u_int16_t ar, lpar; 952 953 if (sc->hw.media_type == em_media_type_fiber || 954 sc->hw.media_type == em_media_type_internal_serdes) 955 return (0); 956 957 em_read_phy_reg(&sc->hw, PHY_AUTONEG_ADV, &ar); 958 em_read_phy_reg(&sc->hw, PHY_LP_ABILITY, &lpar); 959 960 if ((ar & NWAY_AR_PAUSE) && (lpar & NWAY_LPAR_PAUSE)) 961 return (IFM_FLOW|IFM_ETH_TXPAUSE|IFM_ETH_RXPAUSE); 962 else if (!(ar & NWAY_AR_PAUSE) && (ar & NWAY_AR_ASM_DIR) && 963 (lpar & NWAY_LPAR_PAUSE) && (lpar & NWAY_LPAR_ASM_DIR)) 964 return (IFM_FLOW|IFM_ETH_TXPAUSE); 965 else if ((ar & NWAY_AR_PAUSE) && (ar & NWAY_AR_ASM_DIR) && 966 !(lpar & NWAY_LPAR_PAUSE) && (lpar & NWAY_LPAR_ASM_DIR)) 967 return (IFM_FLOW|IFM_ETH_RXPAUSE); 968 969 return (0); 970 } 971 972 /********************************************************************* 973 * 974 * This routine maps the mbufs to tx descriptors. 975 * 976 * return 0 on success, positive on failure 977 **********************************************************************/ 978 int 979 em_encap(struct em_softc *sc, struct mbuf *m_head) 980 { 981 u_int32_t txd_upper; 982 u_int32_t txd_lower, txd_used = 0, txd_saved = 0; 983 int i, j, first, error = 0, last = 0; 984 bus_dmamap_t map; 985 986 /* For 82544 Workaround */ 987 DESC_ARRAY desc_array; 988 u_int32_t array_elements; 989 u_int32_t counter; 990 991 struct em_buffer *tx_buffer, *tx_buffer_mapped; 992 struct em_tx_desc *current_tx_desc = NULL; 993 994 /* 995 * Force a cleanup if number of TX descriptors 996 * available hits the threshold 997 */ 998 if (sc->num_tx_desc_avail <= EM_TX_CLEANUP_THRESHOLD) { 999 em_txeof(sc); 1000 /* Now do we at least have a minimal? */ 1001 if (sc->num_tx_desc_avail <= EM_TX_OP_THRESHOLD) { 1002 sc->no_tx_desc_avail1++; 1003 return (ENOBUFS); 1004 } 1005 } 1006 1007 if (sc->hw.mac_type == em_82547) { 1008 bus_dmamap_sync(sc->txdma.dma_tag, sc->txdma.dma_map, 0, 1009 sc->txdma.dma_map->dm_mapsize, 1010 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1011 } 1012 1013 /* 1014 * Map the packet for DMA. 1015 * 1016 * Capture the first descriptor index, 1017 * this descriptor will have the index 1018 * of the EOP which is the only one that 1019 * no gets a DONE bit writeback. 1020 */ 1021 first = sc->next_avail_tx_desc; 1022 tx_buffer = &sc->tx_buffer_area[first]; 1023 tx_buffer_mapped = tx_buffer; 1024 map = tx_buffer->map; 1025 1026 error = bus_dmamap_load_mbuf(sc->txtag, map, m_head, BUS_DMA_NOWAIT); 1027 if (error != 0) { 1028 sc->no_tx_dma_setup++; 1029 goto loaderr; 1030 } 1031 EM_KASSERT(map->dm_nsegs!= 0, ("em_encap: empty packet")); 1032 1033 if (map->dm_nsegs > sc->num_tx_desc_avail - 2) 1034 goto fail; 1035 1036 #ifdef EM_CSUM_OFFLOAD 1037 if (sc->hw.mac_type >= em_82543) 1038 em_transmit_checksum_setup(sc, m_head, &txd_upper, &txd_lower); 1039 else 1040 txd_upper = txd_lower = 0; 1041 #else 1042 txd_upper = txd_lower = 0; 1043 #endif 1044 1045 i = sc->next_avail_tx_desc; 1046 if (sc->pcix_82544) 1047 txd_saved = i; 1048 1049 for (j = 0; j < map->dm_nsegs; j++) { 1050 /* If sc is 82544 and on PCI-X bus */ 1051 if (sc->pcix_82544) { 1052 /* 1053 * Check the Address and Length combination and 1054 * split the data accordingly 1055 */ 1056 array_elements = em_fill_descriptors(map->dm_segs[j].ds_addr, 1057 map->dm_segs[j].ds_len, 1058 &desc_array); 1059 for (counter = 0; counter < array_elements; counter++) { 1060 if (txd_used == sc->num_tx_desc_avail) { 1061 sc->next_avail_tx_desc = txd_saved; 1062 goto fail; 1063 } 1064 tx_buffer = &sc->tx_buffer_area[i]; 1065 current_tx_desc = &sc->tx_desc_base[i]; 1066 current_tx_desc->buffer_addr = htole64( 1067 desc_array.descriptor[counter].address); 1068 current_tx_desc->lower.data = htole32( 1069 (sc->txd_cmd | txd_lower | 1070 (u_int16_t)desc_array.descriptor[counter].length)); 1071 current_tx_desc->upper.data = htole32((txd_upper)); 1072 last = i; 1073 if (++i == sc->num_tx_desc) 1074 i = 0; 1075 1076 tx_buffer->m_head = NULL; 1077 tx_buffer->next_eop = -1; 1078 txd_used++; 1079 } 1080 } else { 1081 tx_buffer = &sc->tx_buffer_area[i]; 1082 current_tx_desc = &sc->tx_desc_base[i]; 1083 1084 current_tx_desc->buffer_addr = htole64(map->dm_segs[j].ds_addr); 1085 current_tx_desc->lower.data = htole32( 1086 sc->txd_cmd | txd_lower | map->dm_segs[j].ds_len); 1087 current_tx_desc->upper.data = htole32(txd_upper); 1088 last = i; 1089 if (++i == sc->num_tx_desc) 1090 i = 0; 1091 1092 tx_buffer->m_head = NULL; 1093 tx_buffer->next_eop = -1; 1094 } 1095 } 1096 1097 sc->next_avail_tx_desc = i; 1098 if (sc->pcix_82544) 1099 sc->num_tx_desc_avail -= txd_used; 1100 else 1101 sc->num_tx_desc_avail -= map->dm_nsegs; 1102 1103 #if NVLAN > 0 1104 /* Find out if we are in VLAN mode */ 1105 if (m_head->m_flags & M_VLANTAG) { 1106 /* Set the VLAN id */ 1107 current_tx_desc->upper.fields.special = 1108 htole16(m_head->m_pkthdr.ether_vtag); 1109 1110 /* Tell hardware to add tag */ 1111 current_tx_desc->lower.data |= htole32(E1000_TXD_CMD_VLE); 1112 } 1113 #endif 1114 1115 tx_buffer->m_head = m_head; 1116 tx_buffer_mapped->map = tx_buffer->map; 1117 tx_buffer->map = map; 1118 bus_dmamap_sync(sc->txtag, map, 0, map->dm_mapsize, 1119 BUS_DMASYNC_PREWRITE); 1120 1121 /* 1122 * Last Descriptor of Packet 1123 * needs End Of Packet (EOP) 1124 * and Report Status (RS) 1125 */ 1126 current_tx_desc->lower.data |= 1127 htole32(E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS); 1128 1129 /* 1130 * Keep track in the first buffer which 1131 * descriptor will be written back 1132 */ 1133 tx_buffer = &sc->tx_buffer_area[first]; 1134 tx_buffer->next_eop = last; 1135 1136 /* 1137 * Advance the Transmit Descriptor Tail (Tdt), 1138 * this tells the E1000 that this frame is 1139 * available to transmit. 1140 */ 1141 if (sc->hw.mac_type == em_82547) { 1142 bus_dmamap_sync(sc->txdma.dma_tag, sc->txdma.dma_map, 0, 1143 sc->txdma.dma_map->dm_mapsize, 1144 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1145 if (sc->link_duplex == HALF_DUPLEX) 1146 em_82547_move_tail_locked(sc); 1147 else { 1148 E1000_WRITE_REG(&sc->hw, TDT, i); 1149 em_82547_update_fifo_head(sc, m_head->m_pkthdr.len); 1150 } 1151 } 1152 1153 return (0); 1154 1155 fail: 1156 sc->no_tx_desc_avail2++; 1157 bus_dmamap_unload(sc->txtag, map); 1158 error = ENOBUFS; 1159 loaderr: 1160 if (sc->hw.mac_type == em_82547) { 1161 bus_dmamap_sync(sc->txdma.dma_tag, sc->txdma.dma_map, 0, 1162 sc->txdma.dma_map->dm_mapsize, 1163 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1164 } 1165 return (error); 1166 } 1167 1168 /********************************************************************* 1169 * 1170 * 82547 workaround to avoid controller hang in half-duplex environment. 1171 * The workaround is to avoid queuing a large packet that would span 1172 * the internal Tx FIFO ring boundary. We need to reset the FIFO pointers 1173 * in this case. We do that only when FIFO is quiescent. 1174 * 1175 **********************************************************************/ 1176 void 1177 em_82547_move_tail_locked(struct em_softc *sc) 1178 { 1179 uint16_t hw_tdt; 1180 uint16_t sw_tdt; 1181 struct em_tx_desc *tx_desc; 1182 uint16_t length = 0; 1183 boolean_t eop = 0; 1184 1185 hw_tdt = E1000_READ_REG(&sc->hw, TDT); 1186 sw_tdt = sc->next_avail_tx_desc; 1187 1188 while (hw_tdt != sw_tdt) { 1189 tx_desc = &sc->tx_desc_base[hw_tdt]; 1190 length += tx_desc->lower.flags.length; 1191 eop = tx_desc->lower.data & E1000_TXD_CMD_EOP; 1192 if (++hw_tdt == sc->num_tx_desc) 1193 hw_tdt = 0; 1194 1195 if (eop) { 1196 if (em_82547_fifo_workaround(sc, length)) { 1197 sc->tx_fifo_wrk_cnt++; 1198 timeout_add(&sc->tx_fifo_timer_handle, 1); 1199 break; 1200 } 1201 E1000_WRITE_REG(&sc->hw, TDT, hw_tdt); 1202 em_82547_update_fifo_head(sc, length); 1203 length = 0; 1204 } 1205 } 1206 } 1207 1208 void 1209 em_82547_move_tail(void *arg) 1210 { 1211 struct em_softc *sc = arg; 1212 int s; 1213 1214 s = splnet(); 1215 em_82547_move_tail_locked(sc); 1216 splx(s); 1217 } 1218 1219 int 1220 em_82547_fifo_workaround(struct em_softc *sc, int len) 1221 { 1222 int fifo_space, fifo_pkt_len; 1223 1224 fifo_pkt_len = EM_ROUNDUP(len + EM_FIFO_HDR, EM_FIFO_HDR); 1225 1226 if (sc->link_duplex == HALF_DUPLEX) { 1227 fifo_space = sc->tx_fifo_size - sc->tx_fifo_head; 1228 1229 if (fifo_pkt_len >= (EM_82547_PKT_THRESH + fifo_space)) { 1230 if (em_82547_tx_fifo_reset(sc)) 1231 return (0); 1232 else 1233 return (1); 1234 } 1235 } 1236 1237 return (0); 1238 } 1239 1240 void 1241 em_82547_update_fifo_head(struct em_softc *sc, int len) 1242 { 1243 int fifo_pkt_len = EM_ROUNDUP(len + EM_FIFO_HDR, EM_FIFO_HDR); 1244 1245 /* tx_fifo_head is always 16 byte aligned */ 1246 sc->tx_fifo_head += fifo_pkt_len; 1247 if (sc->tx_fifo_head >= sc->tx_fifo_size) 1248 sc->tx_fifo_head -= sc->tx_fifo_size; 1249 } 1250 1251 int 1252 em_82547_tx_fifo_reset(struct em_softc *sc) 1253 { 1254 uint32_t tctl; 1255 1256 if ((E1000_READ_REG(&sc->hw, TDT) == 1257 E1000_READ_REG(&sc->hw, TDH)) && 1258 (E1000_READ_REG(&sc->hw, TDFT) == 1259 E1000_READ_REG(&sc->hw, TDFH)) && 1260 (E1000_READ_REG(&sc->hw, TDFTS) == 1261 E1000_READ_REG(&sc->hw, TDFHS)) && 1262 (E1000_READ_REG(&sc->hw, TDFPC) == 0)) { 1263 1264 /* Disable TX unit */ 1265 tctl = E1000_READ_REG(&sc->hw, TCTL); 1266 E1000_WRITE_REG(&sc->hw, TCTL, tctl & ~E1000_TCTL_EN); 1267 1268 /* Reset FIFO pointers */ 1269 E1000_WRITE_REG(&sc->hw, TDFT, sc->tx_head_addr); 1270 E1000_WRITE_REG(&sc->hw, TDFH, sc->tx_head_addr); 1271 E1000_WRITE_REG(&sc->hw, TDFTS, sc->tx_head_addr); 1272 E1000_WRITE_REG(&sc->hw, TDFHS, sc->tx_head_addr); 1273 1274 /* Re-enable TX unit */ 1275 E1000_WRITE_REG(&sc->hw, TCTL, tctl); 1276 E1000_WRITE_FLUSH(&sc->hw); 1277 1278 sc->tx_fifo_head = 0; 1279 sc->tx_fifo_reset_cnt++; 1280 1281 return (TRUE); 1282 } else 1283 return (FALSE); 1284 } 1285 1286 void 1287 em_iff(struct em_softc *sc) 1288 { 1289 struct ifnet *ifp = &sc->interface_data.ac_if; 1290 struct arpcom *ac = &sc->interface_data; 1291 u_int32_t reg_rctl = 0; 1292 u_int8_t mta[MAX_NUM_MULTICAST_ADDRESSES * ETH_LENGTH_OF_ADDRESS]; 1293 struct ether_multi *enm; 1294 struct ether_multistep step; 1295 int i = 0; 1296 1297 IOCTL_DEBUGOUT("em_iff: begin"); 1298 1299 if (sc->hw.mac_type == em_82542_rev2_0) { 1300 reg_rctl = E1000_READ_REG(&sc->hw, RCTL); 1301 if (sc->hw.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1302 em_pci_clear_mwi(&sc->hw); 1303 reg_rctl |= E1000_RCTL_RST; 1304 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 1305 msec_delay(5); 1306 } 1307 1308 reg_rctl = E1000_READ_REG(&sc->hw, RCTL); 1309 reg_rctl &= ~(E1000_RCTL_MPE | E1000_RCTL_UPE); 1310 ifp->if_flags &= ~IFF_ALLMULTI; 1311 1312 if (ifp->if_flags & IFF_PROMISC || ac->ac_multirangecnt > 0 || 1313 ac->ac_multicnt > MAX_NUM_MULTICAST_ADDRESSES) { 1314 ifp->if_flags |= IFF_ALLMULTI; 1315 reg_rctl |= E1000_RCTL_MPE; 1316 if (ifp->if_flags & IFF_PROMISC) 1317 reg_rctl |= E1000_RCTL_UPE; 1318 } else { 1319 ETHER_FIRST_MULTI(step, ac, enm); 1320 while (enm != NULL) { 1321 bcopy(enm->enm_addrlo, mta + i, ETH_LENGTH_OF_ADDRESS); 1322 i += ETH_LENGTH_OF_ADDRESS; 1323 1324 ETHER_NEXT_MULTI(step, enm); 1325 } 1326 1327 em_mc_addr_list_update(&sc->hw, mta, ac->ac_multicnt, 0, 1); 1328 } 1329 1330 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 1331 1332 if (sc->hw.mac_type == em_82542_rev2_0) { 1333 reg_rctl = E1000_READ_REG(&sc->hw, RCTL); 1334 reg_rctl &= ~E1000_RCTL_RST; 1335 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 1336 msec_delay(5); 1337 if (sc->hw.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1338 em_pci_set_mwi(&sc->hw); 1339 } 1340 } 1341 1342 /********************************************************************* 1343 * Timer routine 1344 * 1345 * This routine checks for link status and updates statistics. 1346 * 1347 **********************************************************************/ 1348 1349 void 1350 em_local_timer(void *arg) 1351 { 1352 struct ifnet *ifp; 1353 struct em_softc *sc = arg; 1354 int s; 1355 1356 ifp = &sc->interface_data.ac_if; 1357 1358 s = splnet(); 1359 1360 em_check_for_link(&sc->hw); 1361 em_update_link_status(sc); 1362 em_update_stats_counters(sc); 1363 #ifdef EM_DEBUG 1364 if (em_display_debug_stats && ifp->if_flags & IFF_RUNNING) 1365 em_print_hw_stats(sc); 1366 #endif 1367 em_smartspeed(sc); 1368 1369 timeout_add_sec(&sc->timer_handle, 1); 1370 1371 splx(s); 1372 } 1373 1374 void 1375 em_update_link_status(struct em_softc *sc) 1376 { 1377 struct ifnet *ifp = &sc->interface_data.ac_if; 1378 1379 if (E1000_READ_REG(&sc->hw, STATUS) & E1000_STATUS_LU) { 1380 if (sc->link_active == 0) { 1381 em_get_speed_and_duplex(&sc->hw, 1382 &sc->link_speed, 1383 &sc->link_duplex); 1384 /* Check if we may set SPEED_MODE bit on PCI-E */ 1385 if ((sc->link_speed == SPEED_1000) && 1386 ((sc->hw.mac_type == em_82571) || 1387 (sc->hw.mac_type == em_82572) || 1388 (sc->hw.mac_type == em_82575))) { 1389 int tarc0; 1390 1391 tarc0 = E1000_READ_REG(&sc->hw, TARC0); 1392 tarc0 |= SPEED_MODE_BIT; 1393 E1000_WRITE_REG(&sc->hw, TARC0, tarc0); 1394 } 1395 sc->link_active = 1; 1396 sc->smartspeed = 0; 1397 ifp->if_baudrate = sc->link_speed * 1000000; 1398 } 1399 if (!LINK_STATE_IS_UP(ifp->if_link_state)) { 1400 if (sc->link_duplex == FULL_DUPLEX) 1401 ifp->if_link_state = LINK_STATE_FULL_DUPLEX; 1402 else 1403 ifp->if_link_state = LINK_STATE_HALF_DUPLEX; 1404 if_link_state_change(ifp); 1405 } 1406 } else { 1407 if (sc->link_active == 1) { 1408 ifp->if_baudrate = sc->link_speed = 0; 1409 sc->link_duplex = 0; 1410 sc->link_active = 0; 1411 } 1412 if (ifp->if_link_state != LINK_STATE_DOWN) { 1413 ifp->if_link_state = LINK_STATE_DOWN; 1414 if_link_state_change(ifp); 1415 } 1416 } 1417 } 1418 1419 /********************************************************************* 1420 * 1421 * This routine disables all traffic on the adapter by issuing a 1422 * global reset on the MAC and deallocates TX/RX buffers. 1423 * 1424 **********************************************************************/ 1425 1426 void 1427 em_stop(void *arg) 1428 { 1429 struct ifnet *ifp; 1430 struct em_softc *sc = arg; 1431 ifp = &sc->interface_data.ac_if; 1432 1433 /* Tell the stack that the interface is no longer active */ 1434 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1435 1436 INIT_DEBUGOUT("em_stop: begin"); 1437 em_disable_intr(sc); 1438 em_reset_hw(&sc->hw); 1439 timeout_del(&sc->timer_handle); 1440 timeout_del(&sc->tx_fifo_timer_handle); 1441 1442 em_free_transmit_structures(sc); 1443 em_free_receive_structures(sc); 1444 } 1445 1446 /********************************************************************* 1447 * 1448 * Determine hardware revision. 1449 * 1450 **********************************************************************/ 1451 void 1452 em_identify_hardware(struct em_softc *sc) 1453 { 1454 u_int32_t reg; 1455 struct pci_attach_args *pa = &sc->osdep.em_pa; 1456 1457 /* Make sure our PCI config space has the necessary stuff set */ 1458 sc->hw.pci_cmd_word = pci_conf_read(pa->pa_pc, pa->pa_tag, 1459 PCI_COMMAND_STATUS_REG); 1460 1461 /* Save off the information about this board */ 1462 sc->hw.vendor_id = PCI_VENDOR(pa->pa_id); 1463 sc->hw.device_id = PCI_PRODUCT(pa->pa_id); 1464 1465 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG); 1466 sc->hw.revision_id = PCI_REVISION(reg); 1467 1468 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 1469 sc->hw.subsystem_vendor_id = PCI_VENDOR(reg); 1470 sc->hw.subsystem_id = PCI_PRODUCT(reg); 1471 1472 /* Identify the MAC */ 1473 if (em_set_mac_type(&sc->hw)) 1474 printf("%s: Unknown MAC Type\n", sc->sc_dv.dv_xname); 1475 1476 if (sc->hw.mac_type == em_82541 || 1477 sc->hw.mac_type == em_82541_rev_2 || 1478 sc->hw.mac_type == em_82547 || 1479 sc->hw.mac_type == em_82547_rev_2) 1480 sc->hw.phy_init_script = TRUE; 1481 } 1482 1483 int 1484 em_allocate_pci_resources(struct em_softc *sc) 1485 { 1486 int val, rid; 1487 pci_intr_handle_t ih; 1488 const char *intrstr = NULL; 1489 struct pci_attach_args *pa = &sc->osdep.em_pa; 1490 pci_chipset_tag_t pc = pa->pa_pc; 1491 1492 val = pci_conf_read(pa->pa_pc, pa->pa_tag, EM_MMBA); 1493 if (PCI_MAPREG_TYPE(val) != PCI_MAPREG_TYPE_MEM) { 1494 printf(": mmba is not mem space\n"); 1495 return (ENXIO); 1496 } 1497 if (pci_mapreg_map(pa, EM_MMBA, PCI_MAPREG_MEM_TYPE(val), 0, 1498 &sc->osdep.mem_bus_space_tag, &sc->osdep.mem_bus_space_handle, 1499 &sc->osdep.em_membase, &sc->osdep.em_memsize, 0)) { 1500 printf(": cannot find mem space\n"); 1501 return (ENXIO); 1502 } 1503 1504 if (sc->hw.mac_type > em_82543) { 1505 /* Figure out where our I/O BAR is ? */ 1506 for (rid = PCI_MAPREG_START; rid < PCI_MAPREG_END;) { 1507 val = pci_conf_read(pa->pa_pc, pa->pa_tag, rid); 1508 if (PCI_MAPREG_TYPE(val) == PCI_MAPREG_TYPE_IO) { 1509 sc->io_rid = rid; 1510 break; 1511 } 1512 rid += 4; 1513 if (PCI_MAPREG_MEM_TYPE(val) == 1514 PCI_MAPREG_MEM_TYPE_64BIT) 1515 rid += 4; /* skip high bits, too */ 1516 } 1517 1518 if (pci_mapreg_map(pa, rid, PCI_MAPREG_TYPE_IO, 0, 1519 &sc->osdep.io_bus_space_tag, &sc->osdep.io_bus_space_handle, 1520 &sc->osdep.em_iobase, &sc->osdep.em_iosize, 0)) { 1521 printf(": cannot find i/o space\n"); 1522 return (ENXIO); 1523 } 1524 1525 sc->hw.io_base = 0; 1526 } 1527 1528 /* for ICH8 and family we need to find the flash memory */ 1529 if (sc->hw.mac_type == em_ich8lan || 1530 sc->hw.mac_type == em_ich9lan || 1531 sc->hw.mac_type == em_ich10lan) { 1532 val = pci_conf_read(pa->pa_pc, pa->pa_tag, EM_FLASH); 1533 if (PCI_MAPREG_TYPE(val) != PCI_MAPREG_TYPE_MEM) { 1534 printf(": flash is not mem space\n"); 1535 return (ENXIO); 1536 } 1537 1538 if (pci_mapreg_map(pa, EM_FLASH, PCI_MAPREG_MEM_TYPE(val), 0, 1539 &sc->osdep.flash_bus_space_tag, &sc->osdep.flash_bus_space_handle, 1540 &sc->osdep.em_flashbase, &sc->osdep.em_flashsize, 0)) { 1541 printf(": cannot find mem space\n"); 1542 return (ENXIO); 1543 } 1544 } 1545 1546 if (pci_intr_map(pa, &ih)) { 1547 printf(": couldn't map interrupt\n"); 1548 return (ENXIO); 1549 } 1550 1551 sc->hw.back = &sc->osdep; 1552 1553 intrstr = pci_intr_string(pc, ih); 1554 sc->sc_intrhand = pci_intr_establish(pc, ih, IPL_NET, em_intr, sc, 1555 sc->sc_dv.dv_xname); 1556 if (sc->sc_intrhand == NULL) { 1557 printf(": couldn't establish interrupt"); 1558 if (intrstr != NULL) 1559 printf(" at %s", intrstr); 1560 printf("\n"); 1561 return (ENXIO); 1562 } 1563 printf(": %s", intrstr); 1564 1565 return (0); 1566 } 1567 1568 void 1569 em_free_pci_resources(struct em_softc *sc) 1570 { 1571 struct pci_attach_args *pa = &sc->osdep.em_pa; 1572 pci_chipset_tag_t pc = pa->pa_pc; 1573 1574 if (sc->sc_intrhand) 1575 pci_intr_disestablish(pc, sc->sc_intrhand); 1576 sc->sc_intrhand = 0; 1577 1578 if (sc->osdep.em_flashbase) 1579 bus_space_unmap(sc->osdep.flash_bus_space_tag, sc->osdep.flash_bus_space_handle, 1580 sc->osdep.em_flashsize); 1581 sc->osdep.em_flashbase = 0; 1582 1583 if (sc->osdep.em_iobase) 1584 bus_space_unmap(sc->osdep.io_bus_space_tag, sc->osdep.io_bus_space_handle, 1585 sc->osdep.em_iosize); 1586 sc->osdep.em_iobase = 0; 1587 1588 if (sc->osdep.em_membase) 1589 bus_space_unmap(sc->osdep.mem_bus_space_tag, sc->osdep.mem_bus_space_handle, 1590 sc->osdep.em_memsize); 1591 sc->osdep.em_membase = 0; 1592 } 1593 1594 /********************************************************************* 1595 * 1596 * Initialize the hardware to a configuration as specified by the 1597 * em_softc structure. The controller is reset, the EEPROM is 1598 * verified, the MAC address is set, then the shared initialization 1599 * routines are called. 1600 * 1601 **********************************************************************/ 1602 int 1603 em_hardware_init(struct em_softc *sc) 1604 { 1605 u_int16_t rx_buffer_size; 1606 1607 INIT_DEBUGOUT("em_hardware_init: begin"); 1608 /* Issue a global reset */ 1609 em_reset_hw(&sc->hw); 1610 1611 /* When hardware is reset, fifo_head is also reset */ 1612 sc->tx_fifo_head = 0; 1613 1614 /* Make sure we have a good EEPROM before we read from it */ 1615 if (em_validate_eeprom_checksum(&sc->hw) < 0) { 1616 /* 1617 * Some PCIe parts fail the first check due to 1618 * the link being in sleep state, call it again, 1619 * if it fails a second time its a real issue. 1620 */ 1621 if (em_validate_eeprom_checksum(&sc->hw) < 0) { 1622 printf("%s: The EEPROM Checksum Is Not Valid\n", 1623 sc->sc_dv.dv_xname); 1624 return (EIO); 1625 } 1626 } 1627 1628 if (em_read_part_num(&sc->hw, &(sc->part_num)) < 0) { 1629 printf("%s: EEPROM read error while reading part number\n", 1630 sc->sc_dv.dv_xname); 1631 return (EIO); 1632 } 1633 1634 /* Set up smart power down as default off on newer adapters */ 1635 if (!em_smart_pwr_down && 1636 (sc->hw.mac_type == em_82571 || 1637 sc->hw.mac_type == em_82572 || 1638 sc->hw.mac_type == em_82575)) { 1639 uint16_t phy_tmp = 0; 1640 1641 /* Speed up time to link by disabling smart power down */ 1642 em_read_phy_reg(&sc->hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 1643 phy_tmp &= ~IGP02E1000_PM_SPD; 1644 em_write_phy_reg(&sc->hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp); 1645 } 1646 1647 /* 1648 * These parameters control the automatic generation (Tx) and 1649 * response (Rx) to Ethernet PAUSE frames. 1650 * - High water mark should allow for at least two frames to be 1651 * received after sending an XOFF. 1652 * - Low water mark works best when it is very near the high water mark. 1653 * This allows the receiver to restart by sending XON when it has 1654 * drained a bit. Here we use an arbitary value of 1500 which will 1655 * restart after one full frame is pulled from the buffer. There 1656 * could be several smaller frames in the buffer and if so they will 1657 * not trigger the XON until their total number reduces the buffer 1658 * by 1500. 1659 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 1660 */ 1661 rx_buffer_size = ((E1000_READ_REG(&sc->hw, PBA) & 0xffff) << 10 ); 1662 1663 sc->hw.fc_high_water = rx_buffer_size - 1664 EM_ROUNDUP(sc->hw.max_frame_size, 1024); 1665 sc->hw.fc_low_water = sc->hw.fc_high_water - 1500; 1666 if (sc->hw.mac_type == em_80003es2lan) 1667 sc->hw.fc_pause_time = 0xFFFF; 1668 else 1669 sc->hw.fc_pause_time = 1000; 1670 sc->hw.fc_send_xon = TRUE; 1671 sc->hw.fc = E1000_FC_FULL; 1672 1673 if (em_init_hw(&sc->hw) < 0) { 1674 printf("%s: Hardware Initialization Failed", 1675 sc->sc_dv.dv_xname); 1676 return (EIO); 1677 } 1678 1679 em_check_for_link(&sc->hw); 1680 1681 return (0); 1682 } 1683 1684 /********************************************************************* 1685 * 1686 * Setup networking device structure and register an interface. 1687 * 1688 **********************************************************************/ 1689 void 1690 em_setup_interface(struct em_softc *sc) 1691 { 1692 struct ifnet *ifp; 1693 u_char fiber_type = IFM_1000_SX; 1694 1695 INIT_DEBUGOUT("em_setup_interface: begin"); 1696 1697 ifp = &sc->interface_data.ac_if; 1698 strlcpy(ifp->if_xname, sc->sc_dv.dv_xname, IFNAMSIZ); 1699 ifp->if_softc = sc; 1700 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1701 ifp->if_ioctl = em_ioctl; 1702 ifp->if_start = em_start; 1703 ifp->if_watchdog = em_watchdog; 1704 ifp->if_hardmtu = 1705 sc->hw.max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN; 1706 IFQ_SET_MAXLEN(&ifp->if_snd, sc->num_tx_desc - 1); 1707 IFQ_SET_READY(&ifp->if_snd); 1708 1709 m_clsetwms(ifp, MCLBYTES, 4, sc->num_rx_desc); 1710 1711 ifp->if_capabilities = IFCAP_VLAN_MTU; 1712 1713 #if NVLAN > 0 1714 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 1715 #endif 1716 1717 #ifdef EM_CSUM_OFFLOAD 1718 if (sc->hw.mac_type >= em_82543) 1719 ifp->if_capabilities |= IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4; 1720 #endif 1721 1722 /* 1723 * Specify the media types supported by this adapter and register 1724 * callbacks to update media and link information 1725 */ 1726 ifmedia_init(&sc->media, IFM_IMASK, em_media_change, 1727 em_media_status); 1728 if (sc->hw.media_type == em_media_type_fiber || 1729 sc->hw.media_type == em_media_type_internal_serdes) { 1730 if (sc->hw.mac_type == em_82545) 1731 fiber_type = IFM_1000_LX; 1732 ifmedia_add(&sc->media, IFM_ETHER | fiber_type | IFM_FDX, 1733 0, NULL); 1734 ifmedia_add(&sc->media, IFM_ETHER | fiber_type, 1735 0, NULL); 1736 } else { 1737 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL); 1738 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX, 1739 0, NULL); 1740 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 1741 0, NULL); 1742 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 1743 0, NULL); 1744 if (sc->hw.phy_type != em_phy_ife) { 1745 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 1746 0, NULL); 1747 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_T, 0, NULL); 1748 } 1749 } 1750 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL); 1751 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO); 1752 1753 if_attach(ifp); 1754 ether_ifattach(ifp); 1755 } 1756 1757 int 1758 em_detach(struct device *self, int flags) 1759 { 1760 struct em_softc *sc = (struct em_softc *)self; 1761 struct ifnet *ifp = &sc->interface_data.ac_if; 1762 1763 timeout_del(&sc->timer_handle); 1764 timeout_del(&sc->tx_fifo_timer_handle); 1765 1766 em_free_pci_resources(sc); 1767 em_dma_free(sc, &sc->rxdma); 1768 em_dma_free(sc, &sc->txdma); 1769 1770 ether_ifdetach(ifp); 1771 if_detach(ifp); 1772 1773 if (sc->sc_powerhook != NULL) 1774 powerhook_disestablish(sc->sc_powerhook); 1775 1776 return (0); 1777 } 1778 1779 1780 /********************************************************************* 1781 * 1782 * Workaround for SmartSpeed on 82541 and 82547 controllers 1783 * 1784 **********************************************************************/ 1785 void 1786 em_smartspeed(struct em_softc *sc) 1787 { 1788 uint16_t phy_tmp; 1789 1790 if (sc->link_active || (sc->hw.phy_type != em_phy_igp) || 1791 !sc->hw.autoneg || !(sc->hw.autoneg_advertised & ADVERTISE_1000_FULL)) 1792 return; 1793 1794 if (sc->smartspeed == 0) { 1795 /* If Master/Slave config fault is asserted twice, 1796 * we assume back-to-back */ 1797 em_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 1798 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 1799 return; 1800 em_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 1801 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 1802 em_read_phy_reg(&sc->hw, PHY_1000T_CTRL, 1803 &phy_tmp); 1804 if (phy_tmp & CR_1000T_MS_ENABLE) { 1805 phy_tmp &= ~CR_1000T_MS_ENABLE; 1806 em_write_phy_reg(&sc->hw, 1807 PHY_1000T_CTRL, phy_tmp); 1808 sc->smartspeed++; 1809 if (sc->hw.autoneg && 1810 !em_phy_setup_autoneg(&sc->hw) && 1811 !em_read_phy_reg(&sc->hw, PHY_CTRL, 1812 &phy_tmp)) { 1813 phy_tmp |= (MII_CR_AUTO_NEG_EN | 1814 MII_CR_RESTART_AUTO_NEG); 1815 em_write_phy_reg(&sc->hw, 1816 PHY_CTRL, phy_tmp); 1817 } 1818 } 1819 } 1820 return; 1821 } else if (sc->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 1822 /* If still no link, perhaps using 2/3 pair cable */ 1823 em_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp); 1824 phy_tmp |= CR_1000T_MS_ENABLE; 1825 em_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp); 1826 if (sc->hw.autoneg && 1827 !em_phy_setup_autoneg(&sc->hw) && 1828 !em_read_phy_reg(&sc->hw, PHY_CTRL, &phy_tmp)) { 1829 phy_tmp |= (MII_CR_AUTO_NEG_EN | 1830 MII_CR_RESTART_AUTO_NEG); 1831 em_write_phy_reg(&sc->hw, PHY_CTRL, phy_tmp); 1832 } 1833 } 1834 /* Restart process after EM_SMARTSPEED_MAX iterations */ 1835 if (sc->smartspeed++ == EM_SMARTSPEED_MAX) 1836 sc->smartspeed = 0; 1837 } 1838 1839 /* 1840 * Manage DMA'able memory. 1841 */ 1842 int 1843 em_dma_malloc(struct em_softc *sc, bus_size_t size, 1844 struct em_dma_alloc *dma, int mapflags) 1845 { 1846 int r; 1847 1848 dma->dma_tag = sc->osdep.em_pa.pa_dmat; 1849 r = bus_dmamap_create(dma->dma_tag, size, 1, 1850 size, 0, BUS_DMA_NOWAIT, &dma->dma_map); 1851 if (r != 0) { 1852 printf("%s: em_dma_malloc: bus_dmamap_create failed; " 1853 "error %u\n", sc->sc_dv.dv_xname, r); 1854 goto fail_0; 1855 } 1856 1857 r = bus_dmamem_alloc(dma->dma_tag, size, PAGE_SIZE, 0, &dma->dma_seg, 1858 1, &dma->dma_nseg, BUS_DMA_NOWAIT); 1859 if (r != 0) { 1860 printf("%s: em_dma_malloc: bus_dmammem_alloc failed; " 1861 "size %lu, error %d\n", sc->sc_dv.dv_xname, 1862 (unsigned long)size, r); 1863 goto fail_1; 1864 } 1865 1866 r = bus_dmamem_map(dma->dma_tag, &dma->dma_seg, dma->dma_nseg, size, 1867 &dma->dma_vaddr, BUS_DMA_NOWAIT); 1868 if (r != 0) { 1869 printf("%s: em_dma_malloc: bus_dmammem_map failed; " 1870 "size %lu, error %d\n", sc->sc_dv.dv_xname, 1871 (unsigned long)size, r); 1872 goto fail_2; 1873 } 1874 1875 r = bus_dmamap_load(sc->osdep.em_pa.pa_dmat, dma->dma_map, 1876 dma->dma_vaddr, size, NULL, 1877 mapflags | BUS_DMA_NOWAIT); 1878 if (r != 0) { 1879 printf("%s: em_dma_malloc: bus_dmamap_load failed; " 1880 "error %u\n", sc->sc_dv.dv_xname, r); 1881 goto fail_3; 1882 } 1883 1884 dma->dma_size = size; 1885 return (0); 1886 1887 fail_3: 1888 bus_dmamem_unmap(dma->dma_tag, dma->dma_vaddr, size); 1889 fail_2: 1890 bus_dmamem_free(dma->dma_tag, &dma->dma_seg, dma->dma_nseg); 1891 fail_1: 1892 bus_dmamap_destroy(dma->dma_tag, dma->dma_map); 1893 fail_0: 1894 dma->dma_map = NULL; 1895 dma->dma_tag = NULL; 1896 1897 return (r); 1898 } 1899 1900 void 1901 em_dma_free(struct em_softc *sc, struct em_dma_alloc *dma) 1902 { 1903 if (dma->dma_tag == NULL) 1904 return; 1905 1906 if (dma->dma_map != NULL) { 1907 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 0, 1908 dma->dma_map->dm_mapsize, 1909 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1910 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1911 bus_dmamem_unmap(dma->dma_tag, dma->dma_vaddr, dma->dma_size); 1912 bus_dmamem_free(dma->dma_tag, &dma->dma_seg, dma->dma_nseg); 1913 bus_dmamap_destroy(dma->dma_tag, dma->dma_map); 1914 } 1915 dma->dma_tag = NULL; 1916 } 1917 1918 /********************************************************************* 1919 * 1920 * Allocate memory for tx_buffer structures. The tx_buffer stores all 1921 * the information needed to transmit a packet on the wire. 1922 * 1923 **********************************************************************/ 1924 int 1925 em_allocate_transmit_structures(struct em_softc *sc) 1926 { 1927 if (!(sc->tx_buffer_area = malloc(sizeof(struct em_buffer) * 1928 sc->num_tx_desc, M_DEVBUF, M_NOWAIT | M_ZERO))) { 1929 printf("%s: Unable to allocate tx_buffer memory\n", 1930 sc->sc_dv.dv_xname); 1931 return (ENOMEM); 1932 } 1933 1934 return (0); 1935 } 1936 1937 /********************************************************************* 1938 * 1939 * Allocate and initialize transmit structures. 1940 * 1941 **********************************************************************/ 1942 int 1943 em_setup_transmit_structures(struct em_softc *sc) 1944 { 1945 struct em_buffer *tx_buffer; 1946 int error, i; 1947 1948 if ((error = em_allocate_transmit_structures(sc)) != 0) 1949 goto fail; 1950 1951 bzero((void *) sc->tx_desc_base, 1952 (sizeof(struct em_tx_desc)) * sc->num_tx_desc); 1953 1954 sc->txtag = sc->osdep.em_pa.pa_dmat; 1955 1956 tx_buffer = sc->tx_buffer_area; 1957 for (i = 0; i < sc->num_tx_desc; i++) { 1958 error = bus_dmamap_create(sc->txtag, MAX_JUMBO_FRAME_SIZE, 1959 EM_MAX_SCATTER, MAX_JUMBO_FRAME_SIZE, 0, 1960 BUS_DMA_NOWAIT, &tx_buffer->map); 1961 if (error != 0) { 1962 printf("%s: Unable to create TX DMA map\n", 1963 sc->sc_dv.dv_xname); 1964 goto fail; 1965 } 1966 tx_buffer++; 1967 } 1968 1969 sc->next_avail_tx_desc = 0; 1970 sc->next_tx_to_clean = 0; 1971 1972 /* Set number of descriptors available */ 1973 sc->num_tx_desc_avail = sc->num_tx_desc; 1974 1975 /* Set checksum context */ 1976 sc->active_checksum_context = OFFLOAD_NONE; 1977 bus_dmamap_sync(sc->txdma.dma_tag, sc->txdma.dma_map, 0, 1978 sc->txdma.dma_size, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1979 1980 return (0); 1981 1982 fail: 1983 em_free_transmit_structures(sc); 1984 return (error); 1985 } 1986 1987 /********************************************************************* 1988 * 1989 * Enable transmit unit. 1990 * 1991 **********************************************************************/ 1992 void 1993 em_initialize_transmit_unit(struct em_softc *sc) 1994 { 1995 u_int32_t reg_tctl, reg_tipg = 0; 1996 u_int64_t bus_addr; 1997 1998 INIT_DEBUGOUT("em_initialize_transmit_unit: begin"); 1999 2000 /* Setup the Base and Length of the Tx Descriptor Ring */ 2001 bus_addr = sc->txdma.dma_map->dm_segs[0].ds_addr; 2002 E1000_WRITE_REG(&sc->hw, TDLEN, 2003 sc->num_tx_desc * 2004 sizeof(struct em_tx_desc)); 2005 E1000_WRITE_REG(&sc->hw, TDBAH, (u_int32_t)(bus_addr >> 32)); 2006 E1000_WRITE_REG(&sc->hw, TDBAL, (u_int32_t)bus_addr); 2007 2008 /* Setup the HW Tx Head and Tail descriptor pointers */ 2009 E1000_WRITE_REG(&sc->hw, TDT, 0); 2010 E1000_WRITE_REG(&sc->hw, TDH, 0); 2011 2012 HW_DEBUGOUT2("Base = %x, Length = %x\n", 2013 E1000_READ_REG(&sc->hw, TDBAL), 2014 E1000_READ_REG(&sc->hw, TDLEN)); 2015 2016 /* Set the default values for the Tx Inter Packet Gap timer */ 2017 switch (sc->hw.mac_type) { 2018 case em_82542_rev2_0: 2019 case em_82542_rev2_1: 2020 reg_tipg = DEFAULT_82542_TIPG_IPGT; 2021 reg_tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2022 reg_tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2023 break; 2024 case em_80003es2lan: 2025 reg_tipg = DEFAULT_82543_TIPG_IPGR1; 2026 reg_tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2027 break; 2028 default: 2029 if (sc->hw.media_type == em_media_type_fiber || 2030 sc->hw.media_type == em_media_type_internal_serdes) 2031 reg_tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 2032 else 2033 reg_tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 2034 reg_tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2035 reg_tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2036 } 2037 2038 2039 E1000_WRITE_REG(&sc->hw, TIPG, reg_tipg); 2040 E1000_WRITE_REG(&sc->hw, TIDV, sc->tx_int_delay); 2041 if (sc->hw.mac_type >= em_82540) 2042 E1000_WRITE_REG(&sc->hw, TADV, sc->tx_abs_int_delay); 2043 2044 /* Setup Transmit Descriptor Base Settings */ 2045 sc->txd_cmd = E1000_TXD_CMD_IFCS; 2046 2047 if (sc->hw.mac_type == em_82575) { 2048 /* 82575/6 need to enable the TX queue and lack the IDE bit */ 2049 reg_tctl = E1000_READ_REG(&sc->hw, TXDCTL); 2050 reg_tctl |= E1000_TXDCTL_QUEUE_ENABLE; 2051 E1000_WRITE_REG(&sc->hw, TXDCTL, reg_tctl); 2052 } else if (sc->tx_int_delay > 0) 2053 sc->txd_cmd |= E1000_TXD_CMD_IDE; 2054 2055 /* Program the Transmit Control Register */ 2056 reg_tctl = E1000_TCTL_PSP | E1000_TCTL_EN | 2057 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 2058 if (sc->hw.mac_type >= em_82571) 2059 reg_tctl |= E1000_TCTL_MULR; 2060 if (sc->link_duplex == FULL_DUPLEX) 2061 reg_tctl |= E1000_FDX_COLLISION_DISTANCE << E1000_COLD_SHIFT; 2062 else 2063 reg_tctl |= E1000_HDX_COLLISION_DISTANCE << E1000_COLD_SHIFT; 2064 /* This write will effectively turn on the transmit unit */ 2065 E1000_WRITE_REG(&sc->hw, TCTL, reg_tctl); 2066 } 2067 2068 /********************************************************************* 2069 * 2070 * Free all transmit related data structures. 2071 * 2072 **********************************************************************/ 2073 void 2074 em_free_transmit_structures(struct em_softc *sc) 2075 { 2076 struct em_buffer *tx_buffer; 2077 int i; 2078 2079 INIT_DEBUGOUT("free_transmit_structures: begin"); 2080 2081 if (sc->tx_buffer_area != NULL) { 2082 tx_buffer = sc->tx_buffer_area; 2083 for (i = 0; i < sc->num_tx_desc; i++, tx_buffer++) { 2084 if (tx_buffer->map != NULL && 2085 tx_buffer->map->dm_nsegs > 0) { 2086 bus_dmamap_sync(sc->txtag, tx_buffer->map, 2087 0, tx_buffer->map->dm_mapsize, 2088 BUS_DMASYNC_POSTWRITE); 2089 bus_dmamap_unload(sc->txtag, 2090 tx_buffer->map); 2091 } 2092 if (tx_buffer->m_head != NULL) { 2093 m_freem(tx_buffer->m_head); 2094 tx_buffer->m_head = NULL; 2095 } 2096 if (tx_buffer->map != NULL) { 2097 bus_dmamap_destroy(sc->txtag, 2098 tx_buffer->map); 2099 tx_buffer->map = NULL; 2100 } 2101 } 2102 } 2103 if (sc->tx_buffer_area != NULL) { 2104 free(sc->tx_buffer_area, M_DEVBUF); 2105 sc->tx_buffer_area = NULL; 2106 } 2107 if (sc->txtag != NULL) 2108 sc->txtag = NULL; 2109 } 2110 2111 #ifdef EM_CSUM_OFFLOAD 2112 /********************************************************************* 2113 * 2114 * The offload context needs to be set when we transfer the first 2115 * packet of a particular protocol (TCP/UDP). We change the 2116 * context only if the protocol type changes. 2117 * 2118 **********************************************************************/ 2119 void 2120 em_transmit_checksum_setup(struct em_softc *sc, struct mbuf *mp, 2121 u_int32_t *txd_upper, u_int32_t *txd_lower) 2122 { 2123 struct em_context_desc *TXD; 2124 struct em_buffer *tx_buffer; 2125 int curr_txd; 2126 2127 if (mp->m_pkthdr.csum_flags) { 2128 if (mp->m_pkthdr.csum_flags & M_TCPV4_CSUM_OUT) { 2129 *txd_upper = E1000_TXD_POPTS_TXSM << 8; 2130 *txd_lower = E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 2131 if (sc->active_checksum_context == OFFLOAD_TCP_IP) 2132 return; 2133 else 2134 sc->active_checksum_context = OFFLOAD_TCP_IP; 2135 } else if (mp->m_pkthdr.csum_flags & M_UDPV4_CSUM_OUT) { 2136 *txd_upper = E1000_TXD_POPTS_TXSM << 8; 2137 *txd_lower = E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 2138 if (sc->active_checksum_context == OFFLOAD_UDP_IP) 2139 return; 2140 else 2141 sc->active_checksum_context = OFFLOAD_UDP_IP; 2142 } else { 2143 *txd_upper = 0; 2144 *txd_lower = 0; 2145 return; 2146 } 2147 } else { 2148 *txd_upper = 0; 2149 *txd_lower = 0; 2150 return; 2151 } 2152 2153 /* If we reach this point, the checksum offload context 2154 * needs to be reset. 2155 */ 2156 curr_txd = sc->next_avail_tx_desc; 2157 tx_buffer = &sc->tx_buffer_area[curr_txd]; 2158 TXD = (struct em_context_desc *) &sc->tx_desc_base[curr_txd]; 2159 2160 TXD->lower_setup.ip_fields.ipcss = ETHER_HDR_LEN; 2161 TXD->lower_setup.ip_fields.ipcso = 2162 ETHER_HDR_LEN + offsetof(struct ip, ip_sum); 2163 TXD->lower_setup.ip_fields.ipcse = 2164 htole16(ETHER_HDR_LEN + sizeof(struct ip) - 1); 2165 2166 TXD->upper_setup.tcp_fields.tucss = 2167 ETHER_HDR_LEN + sizeof(struct ip); 2168 TXD->upper_setup.tcp_fields.tucse = htole16(0); 2169 2170 if (sc->active_checksum_context == OFFLOAD_TCP_IP) { 2171 TXD->upper_setup.tcp_fields.tucso = 2172 ETHER_HDR_LEN + sizeof(struct ip) + 2173 offsetof(struct tcphdr, th_sum); 2174 } else if (sc->active_checksum_context == OFFLOAD_UDP_IP) { 2175 TXD->upper_setup.tcp_fields.tucso = 2176 ETHER_HDR_LEN + sizeof(struct ip) + 2177 offsetof(struct udphdr, uh_sum); 2178 } 2179 2180 TXD->tcp_seg_setup.data = htole32(0); 2181 TXD->cmd_and_length = htole32(sc->txd_cmd | E1000_TXD_CMD_DEXT); 2182 2183 tx_buffer->m_head = NULL; 2184 tx_buffer->next_eop = -1; 2185 2186 if (++curr_txd == sc->num_tx_desc) 2187 curr_txd = 0; 2188 2189 sc->num_tx_desc_avail--; 2190 sc->next_avail_tx_desc = curr_txd; 2191 } 2192 #endif /* EM_CSUM_OFFLOAD */ 2193 2194 /********************************************************************** 2195 * 2196 * Examine each tx_buffer in the used queue. If the hardware is done 2197 * processing the packet then free associated resources. The 2198 * tx_buffer is put back on the free queue. 2199 * 2200 **********************************************************************/ 2201 void 2202 em_txeof(struct em_softc *sc) 2203 { 2204 int first, last, done, num_avail; 2205 struct em_buffer *tx_buffer; 2206 struct em_tx_desc *tx_desc, *eop_desc; 2207 struct ifnet *ifp = &sc->interface_data.ac_if; 2208 2209 if (sc->num_tx_desc_avail == sc->num_tx_desc) 2210 return; 2211 2212 num_avail = sc->num_tx_desc_avail; 2213 first = sc->next_tx_to_clean; 2214 tx_desc = &sc->tx_desc_base[first]; 2215 tx_buffer = &sc->tx_buffer_area[first]; 2216 last = tx_buffer->next_eop; 2217 eop_desc = &sc->tx_desc_base[last]; 2218 2219 /* 2220 * What this does is get the index of the 2221 * first descriptor AFTER the EOP of the 2222 * first packet, that way we can do the 2223 * simple comparison on the inner while loop. 2224 */ 2225 if (++last == sc->num_tx_desc) 2226 last = 0; 2227 done = last; 2228 2229 bus_dmamap_sync(sc->txdma.dma_tag, sc->txdma.dma_map, 0, 2230 sc->txdma.dma_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 2231 while (eop_desc->upper.fields.status & E1000_TXD_STAT_DD) { 2232 /* We clean the range of the packet */ 2233 while (first != done) { 2234 tx_desc->upper.data = 0; 2235 tx_desc->lower.data = 0; 2236 num_avail++; 2237 2238 if (tx_buffer->m_head != NULL) { 2239 ifp->if_opackets++; 2240 if (tx_buffer->map->dm_nsegs > 0) { 2241 bus_dmamap_sync(sc->txtag, 2242 tx_buffer->map, 0, 2243 tx_buffer->map->dm_mapsize, 2244 BUS_DMASYNC_POSTWRITE); 2245 bus_dmamap_unload(sc->txtag, 2246 tx_buffer->map); 2247 } 2248 m_freem(tx_buffer->m_head); 2249 tx_buffer->m_head = NULL; 2250 } 2251 tx_buffer->next_eop = -1; 2252 2253 if (++first == sc->num_tx_desc) 2254 first = 0; 2255 2256 tx_buffer = &sc->tx_buffer_area[first]; 2257 tx_desc = &sc->tx_desc_base[first]; 2258 } 2259 /* See if we can continue to the next packet */ 2260 last = tx_buffer->next_eop; 2261 if (last != -1) { 2262 eop_desc = &sc->tx_desc_base[last]; 2263 /* Get new done point */ 2264 if (++last == sc->num_tx_desc) 2265 last = 0; 2266 done = last; 2267 } else 2268 break; 2269 } 2270 bus_dmamap_sync(sc->txdma.dma_tag, sc->txdma.dma_map, 0, 2271 sc->txdma.dma_map->dm_mapsize, 2272 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2273 2274 sc->next_tx_to_clean = first; 2275 2276 /* 2277 * If we have enough room, clear IFF_OACTIVE to tell the stack 2278 * that it is OK to send packets. 2279 * If there are no pending descriptors, clear the timeout. Otherwise, 2280 * if some descriptors have been freed, restart the timeout. 2281 */ 2282 if (num_avail > EM_TX_CLEANUP_THRESHOLD) 2283 ifp->if_flags &= ~IFF_OACTIVE; 2284 2285 /* All clean, turn off the timer */ 2286 if (num_avail == sc->num_tx_desc) 2287 ifp->if_timer = 0; 2288 /* Some cleaned, reset the timer */ 2289 else if (num_avail != sc->num_tx_desc_avail) 2290 ifp->if_timer = EM_TX_TIMEOUT; 2291 2292 sc->num_tx_desc_avail = num_avail; 2293 } 2294 2295 /********************************************************************* 2296 * 2297 * Get a buffer from system mbuf buffer pool. 2298 * 2299 **********************************************************************/ 2300 int 2301 em_get_buf(struct em_softc *sc, int i) 2302 { 2303 struct mbuf *m; 2304 struct em_buffer *pkt; 2305 struct em_rx_desc *desc; 2306 int error; 2307 2308 pkt = &sc->rx_buffer_area[i]; 2309 desc = &sc->rx_desc_base[i]; 2310 2311 if (pkt->m_head != NULL) { 2312 printf("%s: em_get_buf: slot %d already has an mbuf\n", 2313 sc->sc_dv.dv_xname, i); 2314 return (ENOBUFS); 2315 } 2316 2317 m = MCLGETI(NULL, M_DONTWAIT, &sc->interface_data.ac_if, MCLBYTES); 2318 if (!m) { 2319 sc->mbuf_cluster_failed++; 2320 return (ENOBUFS); 2321 } 2322 m->m_len = m->m_pkthdr.len = MCLBYTES; 2323 if (sc->hw.max_frame_size <= (MCLBYTES - ETHER_ALIGN)) 2324 m_adj(m, ETHER_ALIGN); 2325 2326 error = bus_dmamap_load_mbuf(sc->rxtag, pkt->map, m, BUS_DMA_NOWAIT); 2327 if (error) { 2328 m_freem(m); 2329 return (error); 2330 } 2331 2332 bus_dmamap_sync(sc->rxtag, pkt->map, 0, pkt->map->dm_mapsize, 2333 BUS_DMASYNC_PREREAD); 2334 pkt->m_head = m; 2335 2336 bus_dmamap_sync(sc->rxdma.dma_tag, sc->rxdma.dma_map, 2337 sizeof(*desc) * i, sizeof(*desc), BUS_DMASYNC_POSTWRITE); 2338 2339 bzero(desc, sizeof(*desc)); 2340 desc->buffer_addr = htole64(pkt->map->dm_segs[0].ds_addr); 2341 2342 bus_dmamap_sync(sc->rxdma.dma_tag, sc->rxdma.dma_map, 2343 sizeof(*desc) * i, sizeof(*desc), BUS_DMASYNC_PREWRITE); 2344 2345 sc->rx_ndescs++; 2346 2347 return (0); 2348 } 2349 2350 /********************************************************************* 2351 * 2352 * Allocate memory for rx_buffer structures. Since we use one 2353 * rx_buffer per received packet, the maximum number of rx_buffer's 2354 * that we'll need is equal to the number of receive descriptors 2355 * that we've allocated. 2356 * 2357 **********************************************************************/ 2358 int 2359 em_allocate_receive_structures(struct em_softc *sc) 2360 { 2361 int i, error; 2362 struct em_buffer *rx_buffer; 2363 2364 if (!(sc->rx_buffer_area = malloc(sizeof(struct em_buffer) * 2365 sc->num_rx_desc, M_DEVBUF, M_NOWAIT | M_ZERO))) { 2366 printf("%s: Unable to allocate rx_buffer memory\n", 2367 sc->sc_dv.dv_xname); 2368 return (ENOMEM); 2369 } 2370 2371 sc->rxtag = sc->osdep.em_pa.pa_dmat; 2372 2373 rx_buffer = sc->rx_buffer_area; 2374 for (i = 0; i < sc->num_rx_desc; i++, rx_buffer++) { 2375 error = bus_dmamap_create(sc->rxtag, MCLBYTES, 1, 2376 MCLBYTES, 0, BUS_DMA_NOWAIT, &rx_buffer->map); 2377 if (error != 0) { 2378 printf("%s: em_allocate_receive_structures: " 2379 "bus_dmamap_create failed; error %u\n", 2380 sc->sc_dv.dv_xname, error); 2381 goto fail; 2382 } 2383 rx_buffer->m_head = NULL; 2384 } 2385 bus_dmamap_sync(sc->rxdma.dma_tag, sc->rxdma.dma_map, 0, 2386 sc->rxdma.dma_map->dm_mapsize, 2387 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2388 2389 return (0); 2390 2391 fail: 2392 em_free_receive_structures(sc); 2393 return (error); 2394 } 2395 2396 /********************************************************************* 2397 * 2398 * Allocate and initialize receive structures. 2399 * 2400 **********************************************************************/ 2401 int 2402 em_setup_receive_structures(struct em_softc *sc) 2403 { 2404 bzero((void *) sc->rx_desc_base, 2405 (sizeof(struct em_rx_desc)) * sc->num_rx_desc); 2406 2407 if (em_allocate_receive_structures(sc)) 2408 return (ENOMEM); 2409 2410 /* Setup our descriptor pointers */ 2411 sc->next_rx_desc_to_check = 0; 2412 sc->last_rx_desc_filled = sc->num_rx_desc - 1; 2413 2414 em_rxfill(sc); 2415 if (sc->rx_ndescs < 1) { 2416 printf("%s: unable to fill any rx descriptors\n", 2417 sc->sc_dv.dv_xname); 2418 } 2419 2420 return (0); 2421 } 2422 2423 /********************************************************************* 2424 * 2425 * Enable receive unit. 2426 * 2427 **********************************************************************/ 2428 void 2429 em_initialize_receive_unit(struct em_softc *sc) 2430 { 2431 u_int32_t reg_rctl; 2432 u_int32_t reg_rxcsum; 2433 u_int64_t bus_addr; 2434 2435 INIT_DEBUGOUT("em_initialize_receive_unit: begin"); 2436 2437 /* Make sure receives are disabled while setting up the descriptor ring */ 2438 E1000_WRITE_REG(&sc->hw, RCTL, 0); 2439 2440 /* Set the Receive Delay Timer Register */ 2441 E1000_WRITE_REG(&sc->hw, RDTR, 2442 sc->rx_int_delay | E1000_RDT_FPDB); 2443 2444 if (sc->hw.mac_type >= em_82540) { 2445 if (sc->rx_int_delay) 2446 E1000_WRITE_REG(&sc->hw, RADV, sc->rx_abs_int_delay); 2447 2448 /* Set the interrupt throttling rate. Value is calculated 2449 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */ 2450 E1000_WRITE_REG(&sc->hw, ITR, DEFAULT_ITR); 2451 } 2452 2453 /* Setup the Base and Length of the Rx Descriptor Ring */ 2454 bus_addr = sc->rxdma.dma_map->dm_segs[0].ds_addr; 2455 E1000_WRITE_REG(&sc->hw, RDLEN, sc->num_rx_desc * 2456 sizeof(struct em_rx_desc)); 2457 E1000_WRITE_REG(&sc->hw, RDBAH, (u_int32_t)(bus_addr >> 32)); 2458 E1000_WRITE_REG(&sc->hw, RDBAL, (u_int32_t)bus_addr); 2459 2460 /* Setup the Receive Control Register */ 2461 reg_rctl = E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO | 2462 E1000_RCTL_RDMTS_HALF | 2463 (sc->hw.mc_filter_type << E1000_RCTL_MO_SHIFT); 2464 2465 if (sc->hw.tbi_compatibility_on == TRUE) 2466 reg_rctl |= E1000_RCTL_SBP; 2467 2468 switch (sc->rx_buffer_len) { 2469 default: 2470 case EM_RXBUFFER_2048: 2471 reg_rctl |= E1000_RCTL_SZ_2048; 2472 break; 2473 case EM_RXBUFFER_4096: 2474 reg_rctl |= E1000_RCTL_SZ_4096|E1000_RCTL_BSEX|E1000_RCTL_LPE; 2475 break; 2476 case EM_RXBUFFER_8192: 2477 reg_rctl |= E1000_RCTL_SZ_8192|E1000_RCTL_BSEX|E1000_RCTL_LPE; 2478 break; 2479 case EM_RXBUFFER_16384: 2480 reg_rctl |= E1000_RCTL_SZ_16384|E1000_RCTL_BSEX|E1000_RCTL_LPE; 2481 break; 2482 } 2483 2484 if (sc->hw.max_frame_size != ETHER_MAX_LEN) 2485 reg_rctl |= E1000_RCTL_LPE; 2486 2487 /* Enable 82543 Receive Checksum Offload for TCP and UDP */ 2488 if (sc->hw.mac_type >= em_82543) { 2489 reg_rxcsum = E1000_READ_REG(&sc->hw, RXCSUM); 2490 reg_rxcsum |= (E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL); 2491 E1000_WRITE_REG(&sc->hw, RXCSUM, reg_rxcsum); 2492 } 2493 2494 /* Enable Receives */ 2495 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl); 2496 2497 /* Setup the HW Rx Head and Tail Descriptor Pointers */ 2498 E1000_WRITE_REG(&sc->hw, RDH, 0); 2499 E1000_WRITE_REG(&sc->hw, RDT, sc->last_rx_desc_filled); 2500 } 2501 2502 /********************************************************************* 2503 * 2504 * Free receive related data structures. 2505 * 2506 **********************************************************************/ 2507 void 2508 em_free_receive_structures(struct em_softc *sc) 2509 { 2510 struct em_buffer *rx_buffer; 2511 int i; 2512 2513 INIT_DEBUGOUT("free_receive_structures: begin"); 2514 2515 if (sc->rx_buffer_area != NULL) { 2516 rx_buffer = sc->rx_buffer_area; 2517 for (i = 0; i < sc->num_rx_desc; i++, rx_buffer++) { 2518 if (rx_buffer->m_head != NULL) { 2519 bus_dmamap_sync(sc->rxtag, rx_buffer->map, 2520 0, rx_buffer->map->dm_mapsize, 2521 BUS_DMASYNC_POSTREAD); 2522 bus_dmamap_unload(sc->rxtag, rx_buffer->map); 2523 m_freem(rx_buffer->m_head); 2524 rx_buffer->m_head = NULL; 2525 } 2526 bus_dmamap_destroy(sc->rxtag, rx_buffer->map); 2527 } 2528 } 2529 if (sc->rx_buffer_area != NULL) { 2530 free(sc->rx_buffer_area, M_DEVBUF); 2531 sc->rx_buffer_area = NULL; 2532 } 2533 if (sc->rxtag != NULL) 2534 sc->rxtag = NULL; 2535 2536 if (sc->fmp != NULL) { 2537 m_freem(sc->fmp); 2538 sc->fmp = NULL; 2539 sc->lmp = NULL; 2540 } 2541 } 2542 2543 #ifdef __STRICT_ALIGNMENT 2544 void 2545 em_realign(struct em_softc *sc, struct mbuf *m, u_int16_t *prev_len_adj) 2546 { 2547 unsigned char tmp_align_buf[ETHER_ALIGN]; 2548 int tmp_align_buf_len = 0; 2549 2550 /* 2551 * The Ethernet payload is not 32-bit aligned when 2552 * Jumbo packets are enabled, so on architectures with 2553 * strict alignment we need to shift the entire packet 2554 * ETHER_ALIGN bytes. Ugh. 2555 */ 2556 if (sc->hw.max_frame_size <= (MCLBYTES - ETHER_ALIGN)) 2557 return; 2558 2559 if (*prev_len_adj > sc->align_buf_len) 2560 *prev_len_adj -= sc->align_buf_len; 2561 else 2562 *prev_len_adj = 0; 2563 2564 if (m->m_len > (MCLBYTES - ETHER_ALIGN)) { 2565 bcopy(m->m_data + (MCLBYTES - ETHER_ALIGN), 2566 &tmp_align_buf, ETHER_ALIGN); 2567 tmp_align_buf_len = m->m_len - 2568 (MCLBYTES - ETHER_ALIGN); 2569 m->m_len -= ETHER_ALIGN; 2570 } 2571 2572 if (m->m_len) { 2573 bcopy(m->m_data, m->m_data + ETHER_ALIGN, m->m_len); 2574 if (!sc->align_buf_len) 2575 m->m_data += ETHER_ALIGN; 2576 } 2577 2578 if (sc->align_buf_len) { 2579 m->m_len += sc->align_buf_len; 2580 bcopy(&sc->align_buf, m->m_data, sc->align_buf_len); 2581 } 2582 2583 if (tmp_align_buf_len) 2584 bcopy(&tmp_align_buf, &sc->align_buf, tmp_align_buf_len); 2585 2586 sc->align_buf_len = tmp_align_buf_len; 2587 } 2588 #endif /* __STRICT_ALIGNMENT */ 2589 2590 int 2591 em_rxfill(struct em_softc *sc) 2592 { 2593 int post = 0; 2594 int i; 2595 2596 i = sc->last_rx_desc_filled; 2597 2598 while (sc->rx_ndescs < sc->num_rx_desc) { 2599 if (++i == sc->num_rx_desc) 2600 i = 0; 2601 2602 if (em_get_buf(sc, i) != 0) 2603 break; 2604 2605 sc->last_rx_desc_filled = i; 2606 post = 1; 2607 } 2608 2609 return (post); 2610 } 2611 2612 /********************************************************************* 2613 * 2614 * This routine executes in interrupt context. It replenishes 2615 * the mbufs in the descriptor and sends data which has been 2616 * dma'ed into host memory to upper layer. 2617 * 2618 * We loop at most count times if count is > 0, or until done if 2619 * count < 0. 2620 * 2621 *********************************************************************/ 2622 void 2623 em_rxeof(struct em_softc *sc, int count) 2624 { 2625 struct ifnet *ifp = &sc->interface_data.ac_if; 2626 struct mbuf *m; 2627 u_int8_t accept_frame = 0; 2628 u_int8_t eop = 0; 2629 u_int16_t len, desc_len, prev_len_adj; 2630 int i; 2631 2632 /* Pointer to the receive descriptor being examined. */ 2633 struct em_rx_desc *desc; 2634 struct em_buffer *pkt; 2635 u_int8_t status; 2636 2637 ifp = &sc->interface_data.ac_if; 2638 2639 if (!ISSET(ifp->if_flags, IFF_RUNNING)) 2640 return; 2641 2642 i = sc->next_rx_desc_to_check; 2643 2644 while (count != 0 && sc->rx_ndescs > 0) { 2645 m = NULL; 2646 2647 desc = &sc->rx_desc_base[i]; 2648 pkt = &sc->rx_buffer_area[i]; 2649 2650 bus_dmamap_sync(sc->rxdma.dma_tag, sc->rxdma.dma_map, 2651 sizeof(*desc) * i, sizeof(*desc), 2652 BUS_DMASYNC_POSTREAD); 2653 2654 status = desc->status; 2655 if (!ISSET(status, E1000_RXD_STAT_DD)) { 2656 bus_dmamap_sync(sc->rxdma.dma_tag, sc->rxdma.dma_map, 2657 sizeof(*desc) * i, sizeof(*desc), 2658 BUS_DMASYNC_PREREAD); 2659 break; 2660 } 2661 2662 /* pull the mbuf off the ring */ 2663 bus_dmamap_sync(sc->rxtag, pkt->map, 0, pkt->map->dm_mapsize, 2664 BUS_DMASYNC_POSTREAD); 2665 bus_dmamap_unload(sc->rxtag, pkt->map); 2666 m = pkt->m_head; 2667 pkt->m_head = NULL; 2668 2669 if (m == NULL) { 2670 panic("em_rxeof: NULL mbuf in slot %d " 2671 "(nrx %d, filled %d)", i, sc->rx_ndescs, 2672 sc->last_rx_desc_filled); 2673 } 2674 2675 m_cluncount(m, 1); 2676 sc->rx_ndescs--; 2677 2678 accept_frame = 1; 2679 prev_len_adj = 0; 2680 desc_len = letoh16(desc->length); 2681 2682 if (status & E1000_RXD_STAT_EOP) { 2683 count--; 2684 eop = 1; 2685 if (desc_len < ETHER_CRC_LEN) { 2686 len = 0; 2687 prev_len_adj = ETHER_CRC_LEN - desc_len; 2688 } else 2689 len = desc_len - ETHER_CRC_LEN; 2690 } else { 2691 eop = 0; 2692 len = desc_len; 2693 } 2694 2695 if (desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK) { 2696 u_int8_t last_byte; 2697 u_int32_t pkt_len = desc_len; 2698 2699 if (sc->fmp != NULL) 2700 pkt_len += sc->fmp->m_pkthdr.len; 2701 2702 last_byte = *(mtod(m, caddr_t) + desc_len - 1); 2703 if (TBI_ACCEPT(&sc->hw, status, desc->errors, 2704 pkt_len, last_byte)) { 2705 em_tbi_adjust_stats(&sc->hw, &sc->stats, 2706 pkt_len, sc->hw.mac_addr); 2707 if (len > 0) 2708 len--; 2709 } else 2710 accept_frame = 0; 2711 } 2712 2713 if (accept_frame) { 2714 /* Assign correct length to the current fragment */ 2715 m->m_len = len; 2716 2717 em_realign(sc, m, &prev_len_adj); /* STRICT_ALIGN */ 2718 2719 if (sc->fmp == NULL) { 2720 m->m_pkthdr.len = m->m_len; 2721 sc->fmp = m; /* Store the first mbuf */ 2722 sc->lmp = m; 2723 } else { 2724 /* Chain mbuf's together */ 2725 m->m_flags &= ~M_PKTHDR; 2726 /* 2727 * Adjust length of previous mbuf in chain if 2728 * we received less than 4 bytes in the last 2729 * descriptor. 2730 */ 2731 if (prev_len_adj > 0) { 2732 sc->lmp->m_len -= prev_len_adj; 2733 sc->fmp->m_pkthdr.len -= prev_len_adj; 2734 } 2735 sc->lmp->m_next = m; 2736 sc->lmp = m; 2737 sc->fmp->m_pkthdr.len += m->m_len; 2738 } 2739 2740 if (eop) { 2741 ifp->if_ipackets++; 2742 2743 m = sc->fmp; 2744 m->m_pkthdr.rcvif = ifp; 2745 2746 em_receive_checksum(sc, desc, m); 2747 #if NVLAN > 0 2748 if (desc->status & E1000_RXD_STAT_VP) { 2749 m->m_pkthdr.ether_vtag = 2750 (letoh16(desc->special) & 2751 E1000_RXD_SPC_VLAN_MASK); 2752 m->m_flags |= M_VLANTAG; 2753 } 2754 #endif 2755 #if NBPFILTER > 0 2756 if (ifp->if_bpf) { 2757 bpf_mtap_ether(ifp->if_bpf, m, 2758 BPF_DIRECTION_IN); 2759 } 2760 #endif 2761 2762 ether_input_mbuf(ifp, m); 2763 2764 sc->fmp = NULL; 2765 sc->lmp = NULL; 2766 } 2767 } else { 2768 sc->dropped_pkts++; 2769 2770 if (sc->fmp != NULL) { 2771 m_freem(sc->fmp); 2772 sc->fmp = NULL; 2773 sc->lmp = NULL; 2774 } 2775 2776 m_freem(m); 2777 } 2778 2779 bus_dmamap_sync(sc->rxdma.dma_tag, sc->rxdma.dma_map, 2780 sizeof(*desc) * i, sizeof(*desc), 2781 BUS_DMASYNC_PREREAD); 2782 2783 /* Advance our pointers to the next descriptor. */ 2784 if (++i == sc->num_rx_desc) 2785 i = 0; 2786 } 2787 sc->next_rx_desc_to_check = i; 2788 } 2789 2790 /********************************************************************* 2791 * 2792 * Verify that the hardware indicated that the checksum is valid. 2793 * Inform the stack about the status of checksum so that stack 2794 * doesn't spend time verifying the checksum. 2795 * 2796 *********************************************************************/ 2797 void 2798 em_receive_checksum(struct em_softc *sc, struct em_rx_desc *rx_desc, 2799 struct mbuf *mp) 2800 { 2801 /* 82543 or newer only */ 2802 if ((sc->hw.mac_type < em_82543) || 2803 /* Ignore Checksum bit is set */ 2804 (rx_desc->status & E1000_RXD_STAT_IXSM)) { 2805 mp->m_pkthdr.csum_flags = 0; 2806 return; 2807 } 2808 2809 if (rx_desc->status & E1000_RXD_STAT_IPCS) { 2810 /* Did it pass? */ 2811 if (!(rx_desc->errors & E1000_RXD_ERR_IPE)) { 2812 /* IP Checksum Good */ 2813 mp->m_pkthdr.csum_flags = M_IPV4_CSUM_IN_OK; 2814 2815 } else 2816 mp->m_pkthdr.csum_flags = 0; 2817 } 2818 2819 if (rx_desc->status & E1000_RXD_STAT_TCPCS) { 2820 /* Did it pass? */ 2821 if (!(rx_desc->errors & E1000_RXD_ERR_TCPE)) 2822 mp->m_pkthdr.csum_flags |= 2823 M_TCP_CSUM_IN_OK | M_UDP_CSUM_IN_OK; 2824 } 2825 } 2826 2827 /* 2828 * This turns on the hardware offload of the VLAN 2829 * tag insertion and strip 2830 */ 2831 void 2832 em_enable_hw_vlans(struct em_softc *sc) 2833 { 2834 uint32_t ctrl; 2835 2836 ctrl = E1000_READ_REG(&sc->hw, CTRL); 2837 ctrl |= E1000_CTRL_VME; 2838 E1000_WRITE_REG(&sc->hw, CTRL, ctrl); 2839 } 2840 2841 void 2842 em_enable_intr(struct em_softc *sc) 2843 { 2844 E1000_WRITE_REG(&sc->hw, IMS, (IMS_ENABLE_MASK)); 2845 } 2846 2847 void 2848 em_disable_intr(struct em_softc *sc) 2849 { 2850 /* 2851 * The first version of 82542 had an errata where when link 2852 * was forced it would stay up even if the cable was disconnected 2853 * Sequence errors were used to detect the disconnect and then 2854 * the driver would unforce the link. This code is in the ISR. 2855 * For this to work correctly the Sequence error interrupt had 2856 * to be enabled all the time. 2857 */ 2858 2859 if (sc->hw.mac_type == em_82542_rev2_0) 2860 E1000_WRITE_REG(&sc->hw, IMC, (0xffffffff & ~E1000_IMC_RXSEQ)); 2861 else 2862 E1000_WRITE_REG(&sc->hw, IMC, 0xffffffff); 2863 } 2864 2865 int 2866 em_is_valid_ether_addr(u_int8_t *addr) 2867 { 2868 const char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 2869 2870 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) 2871 return (FALSE); 2872 2873 return (TRUE); 2874 } 2875 2876 void 2877 em_write_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t *value) 2878 { 2879 struct pci_attach_args *pa = &((struct em_osdep *)hw->back)->em_pa; 2880 pci_chipset_tag_t pc = pa->pa_pc; 2881 /* Should we do read/mask/write...? 16 vs 32 bit!!! */ 2882 pci_conf_write(pc, pa->pa_tag, reg, *value); 2883 } 2884 2885 void 2886 em_read_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t *value) 2887 { 2888 struct pci_attach_args *pa = &((struct em_osdep *)hw->back)->em_pa; 2889 pci_chipset_tag_t pc = pa->pa_pc; 2890 *value = pci_conf_read(pc, pa->pa_tag, reg); 2891 } 2892 2893 void 2894 em_pci_set_mwi(struct em_hw *hw) 2895 { 2896 struct pci_attach_args *pa = &((struct em_osdep *)hw->back)->em_pa; 2897 pci_chipset_tag_t pc = pa->pa_pc; 2898 /* Should we do read/mask/write...? 16 vs 32 bit!!! */ 2899 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 2900 (hw->pci_cmd_word | CMD_MEM_WRT_INVALIDATE)); 2901 } 2902 2903 void 2904 em_pci_clear_mwi(struct em_hw *hw) 2905 { 2906 struct pci_attach_args *pa = &((struct em_osdep *)hw->back)->em_pa; 2907 pci_chipset_tag_t pc = pa->pa_pc; 2908 /* Should we do read/mask/write...? 16 vs 32 bit!!! */ 2909 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 2910 (hw->pci_cmd_word & ~CMD_MEM_WRT_INVALIDATE)); 2911 } 2912 2913 /* 2914 * We may eventually really do this, but its unnecessary 2915 * for now so we just return unsupported. 2916 */ 2917 int32_t 2918 em_read_pcie_cap_reg(struct em_hw *hw, uint32_t reg, uint16_t *value) 2919 { 2920 return -E1000_NOT_IMPLEMENTED; 2921 } 2922 2923 /********************************************************************* 2924 * 82544 Coexistence issue workaround. 2925 * There are 2 issues. 2926 * 1. Transmit Hang issue. 2927 * To detect this issue, following equation can be used... 2928 * SIZE[3:0] + ADDR[2:0] = SUM[3:0]. 2929 * If SUM[3:0] is in between 1 to 4, we will have this issue. 2930 * 2931 * 2. DAC issue. 2932 * To detect this issue, following equation can be used... 2933 * SIZE[3:0] + ADDR[2:0] = SUM[3:0]. 2934 * If SUM[3:0] is in between 9 to c, we will have this issue. 2935 * 2936 * 2937 * WORKAROUND: 2938 * Make sure we do not have ending address as 1,2,3,4(Hang) or 9,a,b,c (DAC) 2939 * 2940 *** *********************************************************************/ 2941 u_int32_t 2942 em_fill_descriptors(u_int64_t address, u_int32_t length, 2943 PDESC_ARRAY desc_array) 2944 { 2945 /* Since issue is sensitive to length and address.*/ 2946 /* Let us first check the address...*/ 2947 u_int32_t safe_terminator; 2948 if (length <= 4) { 2949 desc_array->descriptor[0].address = address; 2950 desc_array->descriptor[0].length = length; 2951 desc_array->elements = 1; 2952 return desc_array->elements; 2953 } 2954 safe_terminator = (u_int32_t)((((u_int32_t)address & 0x7) + (length & 0xF)) & 0xF); 2955 /* if it does not fall between 0x1 to 0x4 and 0x9 to 0xC then return */ 2956 if (safe_terminator == 0 || 2957 (safe_terminator > 4 && 2958 safe_terminator < 9) || 2959 (safe_terminator > 0xC && 2960 safe_terminator <= 0xF)) { 2961 desc_array->descriptor[0].address = address; 2962 desc_array->descriptor[0].length = length; 2963 desc_array->elements = 1; 2964 return desc_array->elements; 2965 } 2966 2967 desc_array->descriptor[0].address = address; 2968 desc_array->descriptor[0].length = length - 4; 2969 desc_array->descriptor[1].address = address + (length - 4); 2970 desc_array->descriptor[1].length = 4; 2971 desc_array->elements = 2; 2972 return desc_array->elements; 2973 } 2974 2975 /********************************************************************** 2976 * 2977 * Update the board statistics counters. 2978 * 2979 **********************************************************************/ 2980 void 2981 em_update_stats_counters(struct em_softc *sc) 2982 { 2983 struct ifnet *ifp; 2984 2985 if (sc->hw.media_type == em_media_type_copper || 2986 (E1000_READ_REG(&sc->hw, STATUS) & E1000_STATUS_LU)) { 2987 sc->stats.symerrs += E1000_READ_REG(&sc->hw, SYMERRS); 2988 sc->stats.sec += E1000_READ_REG(&sc->hw, SEC); 2989 } 2990 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, CRCERRS); 2991 sc->stats.mpc += E1000_READ_REG(&sc->hw, MPC); 2992 sc->stats.scc += E1000_READ_REG(&sc->hw, SCC); 2993 sc->stats.ecol += E1000_READ_REG(&sc->hw, ECOL); 2994 2995 sc->stats.mcc += E1000_READ_REG(&sc->hw, MCC); 2996 sc->stats.latecol += E1000_READ_REG(&sc->hw, LATECOL); 2997 sc->stats.colc += E1000_READ_REG(&sc->hw, COLC); 2998 sc->stats.dc += E1000_READ_REG(&sc->hw, DC); 2999 sc->stats.rlec += E1000_READ_REG(&sc->hw, RLEC); 3000 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, XONRXC); 3001 sc->stats.xontxc += E1000_READ_REG(&sc->hw, XONTXC); 3002 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, XOFFRXC); 3003 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, XOFFTXC); 3004 sc->stats.fcruc += E1000_READ_REG(&sc->hw, FCRUC); 3005 sc->stats.prc64 += E1000_READ_REG(&sc->hw, PRC64); 3006 sc->stats.prc127 += E1000_READ_REG(&sc->hw, PRC127); 3007 sc->stats.prc255 += E1000_READ_REG(&sc->hw, PRC255); 3008 sc->stats.prc511 += E1000_READ_REG(&sc->hw, PRC511); 3009 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, PRC1023); 3010 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, PRC1522); 3011 sc->stats.gprc += E1000_READ_REG(&sc->hw, GPRC); 3012 sc->stats.bprc += E1000_READ_REG(&sc->hw, BPRC); 3013 sc->stats.mprc += E1000_READ_REG(&sc->hw, MPRC); 3014 sc->stats.gptc += E1000_READ_REG(&sc->hw, GPTC); 3015 3016 /* For the 64-bit byte counters the low dword must be read first. */ 3017 /* Both registers clear on the read of the high dword */ 3018 3019 sc->stats.gorcl += E1000_READ_REG(&sc->hw, GORCL); 3020 sc->stats.gorch += E1000_READ_REG(&sc->hw, GORCH); 3021 sc->stats.gotcl += E1000_READ_REG(&sc->hw, GOTCL); 3022 sc->stats.gotch += E1000_READ_REG(&sc->hw, GOTCH); 3023 3024 sc->stats.rnbc += E1000_READ_REG(&sc->hw, RNBC); 3025 sc->stats.ruc += E1000_READ_REG(&sc->hw, RUC); 3026 sc->stats.rfc += E1000_READ_REG(&sc->hw, RFC); 3027 sc->stats.roc += E1000_READ_REG(&sc->hw, ROC); 3028 sc->stats.rjc += E1000_READ_REG(&sc->hw, RJC); 3029 3030 sc->stats.torl += E1000_READ_REG(&sc->hw, TORL); 3031 sc->stats.torh += E1000_READ_REG(&sc->hw, TORH); 3032 sc->stats.totl += E1000_READ_REG(&sc->hw, TOTL); 3033 sc->stats.toth += E1000_READ_REG(&sc->hw, TOTH); 3034 3035 sc->stats.tpr += E1000_READ_REG(&sc->hw, TPR); 3036 sc->stats.tpt += E1000_READ_REG(&sc->hw, TPT); 3037 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, PTC64); 3038 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, PTC127); 3039 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, PTC255); 3040 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, PTC511); 3041 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, PTC1023); 3042 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, PTC1522); 3043 sc->stats.mptc += E1000_READ_REG(&sc->hw, MPTC); 3044 sc->stats.bptc += E1000_READ_REG(&sc->hw, BPTC); 3045 3046 if (sc->hw.mac_type >= em_82543) { 3047 sc->stats.algnerrc += 3048 E1000_READ_REG(&sc->hw, ALGNERRC); 3049 sc->stats.rxerrc += 3050 E1000_READ_REG(&sc->hw, RXERRC); 3051 sc->stats.tncrs += 3052 E1000_READ_REG(&sc->hw, TNCRS); 3053 sc->stats.cexterr += 3054 E1000_READ_REG(&sc->hw, CEXTERR); 3055 sc->stats.tsctc += 3056 E1000_READ_REG(&sc->hw, TSCTC); 3057 sc->stats.tsctfc += 3058 E1000_READ_REG(&sc->hw, TSCTFC); 3059 } 3060 ifp = &sc->interface_data.ac_if; 3061 3062 /* Fill out the OS statistics structure */ 3063 ifp->if_collisions = sc->stats.colc; 3064 3065 /* Rx Errors */ 3066 ifp->if_ierrors = 3067 sc->dropped_pkts + 3068 sc->stats.rxerrc + 3069 sc->stats.crcerrs + 3070 sc->stats.algnerrc + 3071 sc->stats.ruc + sc->stats.roc + 3072 sc->stats.mpc + sc->stats.cexterr + 3073 sc->rx_overruns; 3074 3075 /* Tx Errors */ 3076 ifp->if_oerrors = sc->stats.ecol + sc->stats.latecol + 3077 sc->watchdog_events; 3078 } 3079 3080 #ifdef EM_DEBUG 3081 /********************************************************************** 3082 * 3083 * This routine is called only when em_display_debug_stats is enabled. 3084 * This routine provides a way to take a look at important statistics 3085 * maintained by the driver and hardware. 3086 * 3087 **********************************************************************/ 3088 void 3089 em_print_hw_stats(struct em_softc *sc) 3090 { 3091 const char * const unit = sc->sc_dv.dv_xname; 3092 3093 printf("%s: Excessive collisions = %lld\n", unit, 3094 (long long)sc->stats.ecol); 3095 printf("%s: Symbol errors = %lld\n", unit, 3096 (long long)sc->stats.symerrs); 3097 printf("%s: Sequence errors = %lld\n", unit, 3098 (long long)sc->stats.sec); 3099 printf("%s: Defer count = %lld\n", unit, 3100 (long long)sc->stats.dc); 3101 3102 printf("%s: Missed Packets = %lld\n", unit, 3103 (long long)sc->stats.mpc); 3104 printf("%s: Receive No Buffers = %lld\n", unit, 3105 (long long)sc->stats.rnbc); 3106 /* RLEC is inaccurate on some hardware, calculate our own */ 3107 printf("%s: Receive Length Errors = %lld\n", unit, 3108 ((long long)sc->stats.roc + 3109 (long long)sc->stats.ruc)); 3110 printf("%s: Receive errors = %lld\n", unit, 3111 (long long)sc->stats.rxerrc); 3112 printf("%s: Crc errors = %lld\n", unit, 3113 (long long)sc->stats.crcerrs); 3114 printf("%s: Alignment errors = %lld\n", unit, 3115 (long long)sc->stats.algnerrc); 3116 printf("%s: Carrier extension errors = %lld\n", unit, 3117 (long long)sc->stats.cexterr); 3118 3119 printf("%s: RX overruns = %ld\n", unit, 3120 sc->rx_overruns); 3121 printf("%s: watchdog timeouts = %ld\n", unit, 3122 sc->watchdog_events); 3123 3124 printf("%s: XON Rcvd = %lld\n", unit, 3125 (long long)sc->stats.xonrxc); 3126 printf("%s: XON Xmtd = %lld\n", unit, 3127 (long long)sc->stats.xontxc); 3128 printf("%s: XOFF Rcvd = %lld\n", unit, 3129 (long long)sc->stats.xoffrxc); 3130 printf("%s: XOFF Xmtd = %lld\n", unit, 3131 (long long)sc->stats.xofftxc); 3132 3133 printf("%s: Good Packets Rcvd = %lld\n", unit, 3134 (long long)sc->stats.gprc); 3135 printf("%s: Good Packets Xmtd = %lld\n", unit, 3136 (long long)sc->stats.gptc); 3137 } 3138 #endif 3139