1 /* $OpenBSD: if_cas.c,v 1.21 2008/09/10 14:01:22 blambert Exp $ */ 2 3 /* 4 * 5 * Copyright (C) 2007 Mark Kettenis. 6 * Copyright (C) 2001 Eduardo Horvath. 7 * All rights reserved. 8 * 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 */ 32 33 /* 34 * Driver for Sun Cassini ethernet controllers. 35 * 36 * There are basically two variants of this chip: Cassini and 37 * Cassini+. We can distinguish between the two by revision: 0x10 and 38 * up are Cassini+. The most important difference is that Cassini+ 39 * has a second RX descriptor ring. Cassini+ will not work without 40 * configuring that second ring. However, since we don't use it we 41 * don't actually fill the descriptors, and only hand off the first 42 * four to the chip. 43 */ 44 45 #include "bpfilter.h" 46 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/timeout.h> 50 #include <sys/mbuf.h> 51 #include <sys/syslog.h> 52 #include <sys/malloc.h> 53 #include <sys/kernel.h> 54 #include <sys/socket.h> 55 #include <sys/ioctl.h> 56 #include <sys/errno.h> 57 #include <sys/device.h> 58 59 #include <machine/endian.h> 60 61 #include <net/if.h> 62 #include <net/if_dl.h> 63 #include <net/if_media.h> 64 65 #ifdef INET 66 #include <netinet/in.h> 67 #include <netinet/if_ether.h> 68 #endif 69 70 #if NBPFILTER > 0 71 #include <net/bpf.h> 72 #endif 73 74 #include <machine/bus.h> 75 #include <machine/intr.h> 76 77 #include <dev/mii/mii.h> 78 #include <dev/mii/miivar.h> 79 #include <dev/mii/mii_bitbang.h> 80 81 #include <dev/pci/if_casreg.h> 82 #include <dev/pci/if_casvar.h> 83 84 #include <dev/pci/pcivar.h> 85 #include <dev/pci/pcireg.h> 86 #include <dev/pci/pcidevs.h> 87 88 #ifdef __sparc64__ 89 #include <dev/ofw/openfirm.h> 90 #endif 91 92 #define TRIES 10000 93 94 struct cfdriver cas_cd = { 95 NULL, "cas", DV_IFNET 96 }; 97 98 int cas_match(struct device *, void *, void *); 99 void cas_attach(struct device *, struct device *, void *); 100 int cas_pci_enaddr(struct cas_softc *, struct pci_attach_args *); 101 102 struct cfattach cas_ca = { 103 sizeof(struct cas_softc), cas_match, cas_attach 104 }; 105 106 void cas_config(struct cas_softc *); 107 void cas_start(struct ifnet *); 108 void cas_stop(struct ifnet *, int); 109 int cas_ioctl(struct ifnet *, u_long, caddr_t); 110 void cas_tick(void *); 111 void cas_watchdog(struct ifnet *); 112 void cas_shutdown(void *); 113 int cas_init(struct ifnet *); 114 void cas_init_regs(struct cas_softc *); 115 int cas_ringsize(int); 116 int cas_cringsize(int); 117 int cas_meminit(struct cas_softc *); 118 void cas_mifinit(struct cas_softc *); 119 int cas_bitwait(struct cas_softc *, bus_space_handle_t, int, 120 u_int32_t, u_int32_t); 121 void cas_reset(struct cas_softc *); 122 int cas_reset_rx(struct cas_softc *); 123 int cas_reset_tx(struct cas_softc *); 124 int cas_disable_rx(struct cas_softc *); 125 int cas_disable_tx(struct cas_softc *); 126 void cas_rxdrain(struct cas_softc *); 127 int cas_add_rxbuf(struct cas_softc *, int idx); 128 void cas_setladrf(struct cas_softc *); 129 int cas_encap(struct cas_softc *, struct mbuf *, u_int32_t *); 130 131 /* MII methods & callbacks */ 132 int cas_mii_readreg(struct device *, int, int); 133 void cas_mii_writereg(struct device *, int, int, int); 134 void cas_mii_statchg(struct device *); 135 int cas_pcs_readreg(struct device *, int, int); 136 void cas_pcs_writereg(struct device *, int, int, int); 137 138 int cas_mediachange(struct ifnet *); 139 void cas_mediastatus(struct ifnet *, struct ifmediareq *); 140 141 int cas_eint(struct cas_softc *, u_int); 142 int cas_rint(struct cas_softc *); 143 int cas_tint(struct cas_softc *, u_int32_t); 144 int cas_pint(struct cas_softc *); 145 int cas_intr(void *); 146 147 #ifdef CAS_DEBUG 148 #define DPRINTF(sc, x) if ((sc)->sc_arpcom.ac_if.if_flags & IFF_DEBUG) \ 149 printf x 150 #else 151 #define DPRINTF(sc, x) /* nothing */ 152 #endif 153 154 const struct pci_matchid cas_pci_devices[] = { 155 { PCI_VENDOR_SUN, PCI_PRODUCT_SUN_CASSINI }, 156 { PCI_VENDOR_NS, PCI_PRODUCT_NS_SATURN } 157 }; 158 159 int 160 cas_match(struct device *parent, void *cf, void *aux) 161 { 162 return (pci_matchbyid((struct pci_attach_args *)aux, cas_pci_devices, 163 sizeof(cas_pci_devices)/sizeof(cas_pci_devices[0]))); 164 } 165 166 #define PROMHDR_PTR_DATA 0x18 167 #define PROMDATA_PTR_VPD 0x08 168 #define PROMDATA_DATA2 0x0a 169 170 static const u_int8_t cas_promhdr[] = { 0x55, 0xaa }; 171 static const u_int8_t cas_promdat[] = { 172 'P', 'C', 'I', 'R', 173 PCI_VENDOR_SUN & 0xff, PCI_VENDOR_SUN >> 8, 174 PCI_PRODUCT_SUN_CASSINI & 0xff, PCI_PRODUCT_SUN_CASSINI >> 8 175 }; 176 177 static const u_int8_t cas_promdat2[] = { 178 0x18, 0x00, /* structure length */ 179 0x00, /* structure revision */ 180 0x00, /* interface revision */ 181 PCI_SUBCLASS_NETWORK_ETHERNET, /* subclass code */ 182 PCI_CLASS_NETWORK /* class code */ 183 }; 184 185 int 186 cas_pci_enaddr(struct cas_softc *sc, struct pci_attach_args *pa) 187 { 188 struct pci_vpd_largeres *res; 189 struct pci_vpd *vpd; 190 bus_space_handle_t romh; 191 bus_space_tag_t romt; 192 bus_size_t romsize; 193 u_int8_t buf[32], *desc; 194 pcireg_t address, mask; 195 int dataoff, vpdoff, len; 196 int rv = -1; 197 198 address = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_ROM_REG); 199 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_ROM_REG, 0xfffffffe); 200 mask = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_ROM_REG); 201 address |= PCI_ROM_ENABLE; 202 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_ROM_REG, address); 203 204 romt = pa->pa_memt; 205 romsize = PCI_ROM_SIZE(mask); 206 if (bus_space_map(romt, PCI_ROM_ADDR(address), romsize, 0, &romh)) { 207 romsize = 0; 208 goto fail; 209 } 210 211 bus_space_read_region_1(romt, romh, 0, buf, sizeof(buf)); 212 if (bcmp(buf, cas_promhdr, sizeof(cas_promhdr))) 213 goto fail; 214 215 dataoff = buf[PROMHDR_PTR_DATA] | (buf[PROMHDR_PTR_DATA + 1] << 8); 216 if (dataoff < 0x1c) 217 goto fail; 218 219 bus_space_read_region_1(romt, romh, dataoff, buf, sizeof(buf)); 220 if (bcmp(buf, cas_promdat, sizeof(cas_promdat)) || 221 bcmp(buf + PROMDATA_DATA2, cas_promdat2, sizeof(cas_promdat2))) 222 goto fail; 223 224 vpdoff = buf[PROMDATA_PTR_VPD] | (buf[PROMDATA_PTR_VPD + 1] << 8); 225 if (vpdoff < 0x1c) 226 goto fail; 227 228 next: 229 bus_space_read_region_1(romt, romh, vpdoff, buf, sizeof(buf)); 230 if (!PCI_VPDRES_ISLARGE(buf[0])) 231 goto fail; 232 233 res = (struct pci_vpd_largeres *)buf; 234 vpdoff += sizeof(*res); 235 236 len = ((res->vpdres_len_msb << 8) + res->vpdres_len_lsb); 237 switch(PCI_VPDRES_LARGE_NAME(res->vpdres_byte0)) { 238 case PCI_VPDRES_TYPE_IDENTIFIER_STRING: 239 /* Skip identifier string. */ 240 vpdoff += len; 241 goto next; 242 243 case PCI_VPDRES_TYPE_VPD: 244 while (len > 0) { 245 bus_space_read_region_1(romt, romh, vpdoff, 246 buf, sizeof(buf)); 247 248 vpd = (struct pci_vpd *)buf; 249 vpdoff += sizeof(*vpd) + vpd->vpd_len; 250 len -= sizeof(*vpd) + vpd->vpd_len; 251 252 /* 253 * We're looking for an "Enhanced" VPD... 254 */ 255 if (vpd->vpd_key0 != 'Z') 256 continue; 257 258 desc = buf + sizeof(*vpd); 259 260 /* 261 * ...which is an instance property... 262 */ 263 if (desc[0] != 'I') 264 continue; 265 desc += 3; 266 267 /* 268 * ...that's a byte array with the proper 269 * length for a MAC address... 270 */ 271 if (desc[0] != 'B' || desc[1] != ETHER_ADDR_LEN) 272 continue; 273 desc += 2; 274 275 /* 276 * ...named "local-mac-address". 277 */ 278 if (strcmp(desc, "local-mac-address") != 0) 279 continue; 280 desc += strlen("local-mac-address") + 1; 281 282 bcopy(desc, sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN); 283 rv = 0; 284 } 285 break; 286 287 default: 288 goto fail; 289 } 290 291 fail: 292 if (romsize != 0) 293 bus_space_unmap(romt, romh, romsize); 294 295 address = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_ROM_REG); 296 address &= ~PCI_ROM_ENABLE; 297 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_ROM_REG, address); 298 299 return (rv); 300 } 301 302 void 303 cas_attach(struct device *parent, struct device *self, void *aux) 304 { 305 struct pci_attach_args *pa = aux; 306 struct cas_softc *sc = (void *)self; 307 pci_intr_handle_t ih; 308 #ifdef __sparc64__ 309 /* XXX the following declarations should be elsewhere */ 310 extern void myetheraddr(u_char *); 311 #endif 312 const char *intrstr = NULL; 313 bus_size_t size; 314 int gotenaddr = 0; 315 316 sc->sc_rev = PCI_REVISION(pa->pa_class); 317 sc->sc_dmatag = pa->pa_dmat; 318 319 #define PCI_CAS_BASEADDR 0x10 320 if (pci_mapreg_map(pa, PCI_CAS_BASEADDR, PCI_MAPREG_TYPE_MEM, 0, 321 &sc->sc_memt, &sc->sc_memh, NULL, &size, 0) != 0) { 322 printf(": could not map registers\n"); 323 return; 324 } 325 326 if (cas_pci_enaddr(sc, pa) == 0) 327 gotenaddr = 1; 328 329 #ifdef __sparc64__ 330 if (!gotenaddr) { 331 if (OF_getprop(PCITAG_NODE(pa->pa_tag), "local-mac-address", 332 sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN) <= 0) 333 myetheraddr(sc->sc_arpcom.ac_enaddr); 334 gotenaddr = 1; 335 } 336 #endif 337 #ifdef __powerpc__ 338 if (!gotenaddr) { 339 pci_ether_hw_addr(pa->pa_pc, sc->sc_arpcom.ac_enaddr); 340 gotenaddr = 1; 341 } 342 #endif 343 344 sc->sc_burst = 16; /* XXX */ 345 346 if (pci_intr_map(pa, &ih) != 0) { 347 printf(": couldn't map interrupt\n"); 348 bus_space_unmap(sc->sc_memt, sc->sc_memh, size); 349 return; 350 } 351 intrstr = pci_intr_string(pa->pa_pc, ih); 352 sc->sc_ih = pci_intr_establish(pa->pa_pc, 353 ih, IPL_NET, cas_intr, sc, self->dv_xname); 354 if (sc->sc_ih == NULL) { 355 printf(": couldn't establish interrupt"); 356 if (intrstr != NULL) 357 printf(" at %s", intrstr); 358 printf("\n"); 359 bus_space_unmap(sc->sc_memt, sc->sc_memh, size); 360 return; 361 } 362 363 printf(": %s", intrstr); 364 365 /* 366 * call the main configure 367 */ 368 cas_config(sc); 369 } 370 371 /* 372 * cas_config: 373 * 374 * Attach a Cassini interface to the system. 375 */ 376 void 377 cas_config(struct cas_softc *sc) 378 { 379 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 380 struct mii_data *mii = &sc->sc_mii; 381 struct mii_softc *child; 382 int i, error; 383 384 /* Make sure the chip is stopped. */ 385 ifp->if_softc = sc; 386 cas_reset(sc); 387 388 /* 389 * Allocate the control data structures, and create and load the 390 * DMA map for it. 391 */ 392 if ((error = bus_dmamem_alloc(sc->sc_dmatag, 393 sizeof(struct cas_control_data), CAS_PAGE_SIZE, 0, &sc->sc_cdseg, 394 1, &sc->sc_cdnseg, 0)) != 0) { 395 printf("\n%s: unable to allocate control data, error = %d\n", 396 sc->sc_dev.dv_xname, error); 397 goto fail_0; 398 } 399 400 /* XXX should map this in with correct endianness */ 401 if ((error = bus_dmamem_map(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg, 402 sizeof(struct cas_control_data), (caddr_t *)&sc->sc_control_data, 403 BUS_DMA_COHERENT)) != 0) { 404 printf("\n%s: unable to map control data, error = %d\n", 405 sc->sc_dev.dv_xname, error); 406 goto fail_1; 407 } 408 409 if ((error = bus_dmamap_create(sc->sc_dmatag, 410 sizeof(struct cas_control_data), 1, 411 sizeof(struct cas_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 412 printf("\n%s: unable to create control data DMA map, " 413 "error = %d\n", sc->sc_dev.dv_xname, error); 414 goto fail_2; 415 } 416 417 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_cddmamap, 418 sc->sc_control_data, sizeof(struct cas_control_data), NULL, 419 0)) != 0) { 420 printf("\n%s: unable to load control data DMA map, error = %d\n", 421 sc->sc_dev.dv_xname, error); 422 goto fail_3; 423 } 424 425 bzero(sc->sc_control_data, sizeof(struct cas_control_data)); 426 427 /* 428 * Create the receive buffer DMA maps. 429 */ 430 for (i = 0; i < CAS_NRXDESC; i++) { 431 bus_dma_segment_t seg; 432 caddr_t kva; 433 int rseg; 434 435 if ((error = bus_dmamem_alloc(sc->sc_dmatag, CAS_PAGE_SIZE, 436 CAS_PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 437 printf("\n%s: unable to alloc rx DMA mem %d, " 438 "error = %d\n", sc->sc_dev.dv_xname, i, error); 439 goto fail_5; 440 } 441 sc->sc_rxsoft[i].rxs_dmaseg = seg; 442 443 if ((error = bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 444 CAS_PAGE_SIZE, &kva, BUS_DMA_NOWAIT)) != 0) { 445 printf("\n%s: unable to alloc rx DMA mem %d, " 446 "error = %d\n", sc->sc_dev.dv_xname, i, error); 447 goto fail_5; 448 } 449 sc->sc_rxsoft[i].rxs_kva = kva; 450 451 if ((error = bus_dmamap_create(sc->sc_dmatag, CAS_PAGE_SIZE, 1, 452 CAS_PAGE_SIZE, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 453 printf("\n%s: unable to create rx DMA map %d, " 454 "error = %d\n", sc->sc_dev.dv_xname, i, error); 455 goto fail_5; 456 } 457 458 if ((error = bus_dmamap_load(sc->sc_dmatag, 459 sc->sc_rxsoft[i].rxs_dmamap, kva, CAS_PAGE_SIZE, NULL, 460 BUS_DMA_NOWAIT)) != 0) { 461 printf("\n%s: unable to load rx DMA map %d, " 462 "error = %d\n", sc->sc_dev.dv_xname, i, error); 463 goto fail_5; 464 } 465 } 466 467 /* 468 * Create the transmit buffer DMA maps. 469 */ 470 for (i = 0; i < CAS_NTXDESC; i++) { 471 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 472 CAS_NTXSEGS, MCLBYTES, 0, BUS_DMA_NOWAIT, 473 &sc->sc_txd[i].sd_map)) != 0) { 474 printf("\n%s: unable to create tx DMA map %d, " 475 "error = %d\n", sc->sc_dev.dv_xname, i, error); 476 goto fail_6; 477 } 478 sc->sc_txd[i].sd_mbuf = NULL; 479 } 480 481 /* 482 * From this point forward, the attachment cannot fail. A failure 483 * before this point releases all resources that may have been 484 * allocated. 485 */ 486 487 /* Announce ourselves. */ 488 printf(", address %s\n", ether_sprintf(sc->sc_arpcom.ac_enaddr)); 489 490 /* Get RX FIFO size */ 491 sc->sc_rxfifosize = 16 * 1024; 492 493 /* Initialize ifnet structure. */ 494 strlcpy(ifp->if_xname, sc->sc_dev.dv_xname, sizeof ifp->if_xname); 495 ifp->if_softc = sc; 496 ifp->if_flags = 497 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 498 ifp->if_start = cas_start; 499 ifp->if_ioctl = cas_ioctl; 500 ifp->if_watchdog = cas_watchdog; 501 IFQ_SET_MAXLEN(&ifp->if_snd, CAS_NTXDESC - 1); 502 IFQ_SET_READY(&ifp->if_snd); 503 504 ifp->if_capabilities = IFCAP_VLAN_MTU; 505 506 /* Initialize ifmedia structures and MII info */ 507 mii->mii_ifp = ifp; 508 mii->mii_readreg = cas_mii_readreg; 509 mii->mii_writereg = cas_mii_writereg; 510 mii->mii_statchg = cas_mii_statchg; 511 512 ifmedia_init(&mii->mii_media, 0, cas_mediachange, cas_mediastatus); 513 514 bus_space_write_4(sc->sc_memt, sc->sc_memh, CAS_MII_DATAPATH_MODE, 0); 515 516 cas_mifinit(sc); 517 518 if (sc->sc_mif_config & CAS_MIF_CONFIG_MDI1) { 519 sc->sc_mif_config |= CAS_MIF_CONFIG_PHY_SEL; 520 bus_space_write_4(sc->sc_memt, sc->sc_memh, 521 CAS_MIF_CONFIG, sc->sc_mif_config); 522 } 523 524 mii_attach(&sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 525 MII_OFFSET_ANY, 0); 526 527 child = LIST_FIRST(&mii->mii_phys); 528 if (child == NULL && 529 sc->sc_mif_config & (CAS_MIF_CONFIG_MDI0|CAS_MIF_CONFIG_MDI1)) { 530 /* 531 * Try the external PCS SERDES if we didn't find any 532 * MII devices. 533 */ 534 bus_space_write_4(sc->sc_memt, sc->sc_memh, 535 CAS_MII_DATAPATH_MODE, CAS_MII_DATAPATH_SERDES); 536 537 bus_space_write_4(sc->sc_memt, sc->sc_memh, 538 CAS_MII_CONFIG, CAS_MII_CONFIG_ENABLE); 539 540 mii->mii_readreg = cas_pcs_readreg; 541 mii->mii_writereg = cas_pcs_writereg; 542 543 mii_attach(&sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 544 MII_OFFSET_ANY, MIIF_NOISOLATE); 545 } 546 547 child = LIST_FIRST(&mii->mii_phys); 548 if (child == NULL) { 549 /* No PHY attached */ 550 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 551 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 552 } else { 553 /* 554 * Walk along the list of attached MII devices and 555 * establish an `MII instance' to `phy number' 556 * mapping. We'll use this mapping in media change 557 * requests to determine which phy to use to program 558 * the MIF configuration register. 559 */ 560 for (; child != NULL; child = LIST_NEXT(child, mii_list)) { 561 /* 562 * Note: we support just two PHYs: the built-in 563 * internal device and an external on the MII 564 * connector. 565 */ 566 if (child->mii_phy > 1 || child->mii_inst > 1) { 567 printf("%s: cannot accommodate MII device %s" 568 " at phy %d, instance %d\n", 569 sc->sc_dev.dv_xname, 570 child->mii_dev.dv_xname, 571 child->mii_phy, child->mii_inst); 572 continue; 573 } 574 575 sc->sc_phys[child->mii_inst] = child->mii_phy; 576 } 577 578 /* 579 * XXX - we can really do the following ONLY if the 580 * phy indeed has the auto negotiation capability!! 581 */ 582 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_AUTO); 583 } 584 585 /* Attach the interface. */ 586 if_attach(ifp); 587 ether_ifattach(ifp); 588 589 sc->sc_sh = shutdownhook_establish(cas_shutdown, sc); 590 if (sc->sc_sh == NULL) 591 panic("cas_config: can't establish shutdownhook"); 592 593 timeout_set(&sc->sc_tick_ch, cas_tick, sc); 594 return; 595 596 /* 597 * Free any resources we've allocated during the failed attach 598 * attempt. Do this in reverse order and fall through. 599 */ 600 fail_6: 601 for (i = 0; i < CAS_NTXDESC; i++) { 602 if (sc->sc_txd[i].sd_map != NULL) 603 bus_dmamap_destroy(sc->sc_dmatag, 604 sc->sc_txd[i].sd_map); 605 } 606 fail_5: 607 for (i = 0; i < CAS_NRXDESC; i++) { 608 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 609 bus_dmamap_destroy(sc->sc_dmatag, 610 sc->sc_rxsoft[i].rxs_dmamap); 611 } 612 bus_dmamap_unload(sc->sc_dmatag, sc->sc_cddmamap); 613 fail_3: 614 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_cddmamap); 615 fail_2: 616 bus_dmamem_unmap(sc->sc_dmatag, (caddr_t)sc->sc_control_data, 617 sizeof(struct cas_control_data)); 618 fail_1: 619 bus_dmamem_free(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg); 620 fail_0: 621 return; 622 } 623 624 625 void 626 cas_tick(void *arg) 627 { 628 struct cas_softc *sc = arg; 629 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 630 bus_space_tag_t t = sc->sc_memt; 631 bus_space_handle_t mac = sc->sc_memh; 632 int s; 633 u_int32_t v; 634 635 /* unload collisions counters */ 636 v = bus_space_read_4(t, mac, CAS_MAC_EXCESS_COLL_CNT) + 637 bus_space_read_4(t, mac, CAS_MAC_LATE_COLL_CNT); 638 ifp->if_collisions += v + 639 bus_space_read_4(t, mac, CAS_MAC_NORM_COLL_CNT) + 640 bus_space_read_4(t, mac, CAS_MAC_FIRST_COLL_CNT); 641 ifp->if_oerrors += v; 642 643 /* read error counters */ 644 ifp->if_ierrors += 645 bus_space_read_4(t, mac, CAS_MAC_RX_LEN_ERR_CNT) + 646 bus_space_read_4(t, mac, CAS_MAC_RX_ALIGN_ERR) + 647 bus_space_read_4(t, mac, CAS_MAC_RX_CRC_ERR_CNT) + 648 bus_space_read_4(t, mac, CAS_MAC_RX_CODE_VIOL); 649 650 /* clear the hardware counters */ 651 bus_space_write_4(t, mac, CAS_MAC_NORM_COLL_CNT, 0); 652 bus_space_write_4(t, mac, CAS_MAC_FIRST_COLL_CNT, 0); 653 bus_space_write_4(t, mac, CAS_MAC_EXCESS_COLL_CNT, 0); 654 bus_space_write_4(t, mac, CAS_MAC_LATE_COLL_CNT, 0); 655 bus_space_write_4(t, mac, CAS_MAC_RX_LEN_ERR_CNT, 0); 656 bus_space_write_4(t, mac, CAS_MAC_RX_ALIGN_ERR, 0); 657 bus_space_write_4(t, mac, CAS_MAC_RX_CRC_ERR_CNT, 0); 658 bus_space_write_4(t, mac, CAS_MAC_RX_CODE_VIOL, 0); 659 660 s = splnet(); 661 mii_tick(&sc->sc_mii); 662 splx(s); 663 664 timeout_add_sec(&sc->sc_tick_ch, 1); 665 } 666 667 int 668 cas_bitwait(struct cas_softc *sc, bus_space_handle_t h, int r, 669 u_int32_t clr, u_int32_t set) 670 { 671 int i; 672 u_int32_t reg; 673 674 for (i = TRIES; i--; DELAY(100)) { 675 reg = bus_space_read_4(sc->sc_memt, h, r); 676 if ((reg & clr) == 0 && (reg & set) == set) 677 return (1); 678 } 679 680 return (0); 681 } 682 683 void 684 cas_reset(struct cas_softc *sc) 685 { 686 bus_space_tag_t t = sc->sc_memt; 687 bus_space_handle_t h = sc->sc_memh; 688 int s; 689 690 s = splnet(); 691 DPRINTF(sc, ("%s: cas_reset\n", sc->sc_dev.dv_xname)); 692 cas_reset_rx(sc); 693 cas_reset_tx(sc); 694 695 /* Do a full reset */ 696 bus_space_write_4(t, h, CAS_RESET, 697 CAS_RESET_RX | CAS_RESET_TX | CAS_RESET_BLOCK_PCS); 698 if (!cas_bitwait(sc, h, CAS_RESET, CAS_RESET_RX | CAS_RESET_TX, 0)) 699 printf("%s: cannot reset device\n", sc->sc_dev.dv_xname); 700 splx(s); 701 } 702 703 704 /* 705 * cas_rxdrain: 706 * 707 * Drain the receive queue. 708 */ 709 void 710 cas_rxdrain(struct cas_softc *sc) 711 { 712 /* Nothing to do yet. */ 713 } 714 715 /* 716 * Reset the whole thing. 717 */ 718 void 719 cas_stop(struct ifnet *ifp, int disable) 720 { 721 struct cas_softc *sc = (struct cas_softc *)ifp->if_softc; 722 struct cas_sxd *sd; 723 u_int32_t i; 724 725 DPRINTF(sc, ("%s: cas_stop\n", sc->sc_dev.dv_xname)); 726 727 timeout_del(&sc->sc_tick_ch); 728 729 /* 730 * Mark the interface down and cancel the watchdog timer. 731 */ 732 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 733 ifp->if_timer = 0; 734 735 mii_down(&sc->sc_mii); 736 737 cas_reset_rx(sc); 738 cas_reset_tx(sc); 739 740 /* 741 * Release any queued transmit buffers. 742 */ 743 for (i = 0; i < CAS_NTXDESC; i++) { 744 sd = &sc->sc_txd[i]; 745 if (sd->sd_mbuf != NULL) { 746 bus_dmamap_sync(sc->sc_dmatag, sd->sd_map, 0, 747 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 748 bus_dmamap_unload(sc->sc_dmatag, sd->sd_map); 749 m_freem(sd->sd_mbuf); 750 sd->sd_mbuf = NULL; 751 } 752 } 753 sc->sc_tx_cnt = sc->sc_tx_prod = sc->sc_tx_cons = 0; 754 755 if (disable) 756 cas_rxdrain(sc); 757 } 758 759 760 /* 761 * Reset the receiver 762 */ 763 int 764 cas_reset_rx(struct cas_softc *sc) 765 { 766 bus_space_tag_t t = sc->sc_memt; 767 bus_space_handle_t h = sc->sc_memh; 768 769 /* 770 * Resetting while DMA is in progress can cause a bus hang, so we 771 * disable DMA first. 772 */ 773 cas_disable_rx(sc); 774 bus_space_write_4(t, h, CAS_RX_CONFIG, 0); 775 /* Wait till it finishes */ 776 if (!cas_bitwait(sc, h, CAS_RX_CONFIG, 1, 0)) 777 printf("%s: cannot disable rx dma\n", sc->sc_dev.dv_xname); 778 /* Wait 5ms extra. */ 779 delay(5000); 780 781 /* Finally, reset the ERX */ 782 bus_space_write_4(t, h, CAS_RESET, CAS_RESET_RX); 783 /* Wait till it finishes */ 784 if (!cas_bitwait(sc, h, CAS_RESET, CAS_RESET_RX, 0)) { 785 printf("%s: cannot reset receiver\n", sc->sc_dev.dv_xname); 786 return (1); 787 } 788 return (0); 789 } 790 791 792 /* 793 * Reset the transmitter 794 */ 795 int 796 cas_reset_tx(struct cas_softc *sc) 797 { 798 bus_space_tag_t t = sc->sc_memt; 799 bus_space_handle_t h = sc->sc_memh; 800 801 /* 802 * Resetting while DMA is in progress can cause a bus hang, so we 803 * disable DMA first. 804 */ 805 cas_disable_tx(sc); 806 bus_space_write_4(t, h, CAS_TX_CONFIG, 0); 807 /* Wait till it finishes */ 808 if (!cas_bitwait(sc, h, CAS_TX_CONFIG, 1, 0)) 809 printf("%s: cannot disable tx dma\n", sc->sc_dev.dv_xname); 810 /* Wait 5ms extra. */ 811 delay(5000); 812 813 /* Finally, reset the ETX */ 814 bus_space_write_4(t, h, CAS_RESET, CAS_RESET_TX); 815 /* Wait till it finishes */ 816 if (!cas_bitwait(sc, h, CAS_RESET, CAS_RESET_TX, 0)) { 817 printf("%s: cannot reset transmitter\n", 818 sc->sc_dev.dv_xname); 819 return (1); 820 } 821 return (0); 822 } 823 824 /* 825 * disable receiver. 826 */ 827 int 828 cas_disable_rx(struct cas_softc *sc) 829 { 830 bus_space_tag_t t = sc->sc_memt; 831 bus_space_handle_t h = sc->sc_memh; 832 u_int32_t cfg; 833 834 /* Flip the enable bit */ 835 cfg = bus_space_read_4(t, h, CAS_MAC_RX_CONFIG); 836 cfg &= ~CAS_MAC_RX_ENABLE; 837 bus_space_write_4(t, h, CAS_MAC_RX_CONFIG, cfg); 838 839 /* Wait for it to finish */ 840 return (cas_bitwait(sc, h, CAS_MAC_RX_CONFIG, CAS_MAC_RX_ENABLE, 0)); 841 } 842 843 /* 844 * disable transmitter. 845 */ 846 int 847 cas_disable_tx(struct cas_softc *sc) 848 { 849 bus_space_tag_t t = sc->sc_memt; 850 bus_space_handle_t h = sc->sc_memh; 851 u_int32_t cfg; 852 853 /* Flip the enable bit */ 854 cfg = bus_space_read_4(t, h, CAS_MAC_TX_CONFIG); 855 cfg &= ~CAS_MAC_TX_ENABLE; 856 bus_space_write_4(t, h, CAS_MAC_TX_CONFIG, cfg); 857 858 /* Wait for it to finish */ 859 return (cas_bitwait(sc, h, CAS_MAC_TX_CONFIG, CAS_MAC_TX_ENABLE, 0)); 860 } 861 862 /* 863 * Initialize interface. 864 */ 865 int 866 cas_meminit(struct cas_softc *sc) 867 { 868 struct cas_rxsoft *rxs; 869 int i, error; 870 871 rxs = (void *)&error; 872 873 /* 874 * Initialize the transmit descriptor ring. 875 */ 876 for (i = 0; i < CAS_NTXDESC; i++) { 877 sc->sc_txdescs[i].cd_flags = 0; 878 sc->sc_txdescs[i].cd_addr = 0; 879 } 880 CAS_CDTXSYNC(sc, 0, CAS_NTXDESC, 881 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 882 883 /* 884 * Initialize the receive descriptor and receive job 885 * descriptor rings. 886 */ 887 for (i = 0; i < CAS_NRXDESC; i++) 888 CAS_INIT_RXDESC(sc, i, i); 889 sc->sc_rxdptr = 0; 890 sc->sc_rxptr = 0; 891 892 /* 893 * Initialize the receive completion ring. 894 */ 895 for (i = 0; i < CAS_NRXCOMP; i++) { 896 sc->sc_rxcomps[i].cc_word[0] = 0; 897 sc->sc_rxcomps[i].cc_word[1] = 0; 898 sc->sc_rxcomps[i].cc_word[2] = 0; 899 sc->sc_rxcomps[i].cc_word[3] = CAS_DMA_WRITE(CAS_RC3_OWN); 900 CAS_CDRXCSYNC(sc, i, 901 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 902 } 903 904 return (0); 905 } 906 907 int 908 cas_ringsize(int sz) 909 { 910 switch (sz) { 911 case 32: 912 return CAS_RING_SZ_32; 913 case 64: 914 return CAS_RING_SZ_64; 915 case 128: 916 return CAS_RING_SZ_128; 917 case 256: 918 return CAS_RING_SZ_256; 919 case 512: 920 return CAS_RING_SZ_512; 921 case 1024: 922 return CAS_RING_SZ_1024; 923 case 2048: 924 return CAS_RING_SZ_2048; 925 case 4096: 926 return CAS_RING_SZ_4096; 927 case 8192: 928 return CAS_RING_SZ_8192; 929 default: 930 printf("cas: invalid Receive Descriptor ring size %d\n", sz); 931 return CAS_RING_SZ_32; 932 } 933 } 934 935 int 936 cas_cringsize(int sz) 937 { 938 int i; 939 940 for (i = 0; i < 9; i++) 941 if (sz == (128 << i)) 942 return i; 943 944 printf("cas: invalid completion ring size %d\n", sz); 945 return 128; 946 } 947 948 /* 949 * Initialization of interface; set up initialization block 950 * and transmit/receive descriptor rings. 951 */ 952 int 953 cas_init(struct ifnet *ifp) 954 { 955 struct cas_softc *sc = (struct cas_softc *)ifp->if_softc; 956 bus_space_tag_t t = sc->sc_memt; 957 bus_space_handle_t h = sc->sc_memh; 958 int s; 959 u_int max_frame_size; 960 u_int32_t v; 961 962 s = splnet(); 963 964 DPRINTF(sc, ("%s: cas_init: calling stop\n", sc->sc_dev.dv_xname)); 965 /* 966 * Initialization sequence. The numbered steps below correspond 967 * to the sequence outlined in section 6.3.5.1 in the Ethernet 968 * Channel Engine manual (part of the PCIO manual). 969 * See also the STP2002-STQ document from Sun Microsystems. 970 */ 971 972 /* step 1 & 2. Reset the Ethernet Channel */ 973 cas_stop(ifp, 0); 974 cas_reset(sc); 975 DPRINTF(sc, ("%s: cas_init: restarting\n", sc->sc_dev.dv_xname)); 976 977 /* Re-initialize the MIF */ 978 cas_mifinit(sc); 979 980 /* step 3. Setup data structures in host memory */ 981 cas_meminit(sc); 982 983 /* step 4. TX MAC registers & counters */ 984 cas_init_regs(sc); 985 max_frame_size = ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN; 986 v = (max_frame_size) | (0x2000 << 16) /* Burst size */; 987 bus_space_write_4(t, h, CAS_MAC_MAC_MAX_FRAME, v); 988 989 /* step 5. RX MAC registers & counters */ 990 cas_setladrf(sc); 991 992 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 993 KASSERT((CAS_CDTXADDR(sc, 0) & 0x1fff) == 0); 994 bus_space_write_4(t, h, CAS_TX_RING_PTR_HI, 995 (((uint64_t)CAS_CDTXADDR(sc,0)) >> 32)); 996 bus_space_write_4(t, h, CAS_TX_RING_PTR_LO, CAS_CDTXADDR(sc, 0)); 997 998 KASSERT((CAS_CDRXADDR(sc, 0) & 0x1fff) == 0); 999 bus_space_write_4(t, h, CAS_RX_DRING_PTR_HI, 1000 (((uint64_t)CAS_CDRXADDR(sc,0)) >> 32)); 1001 bus_space_write_4(t, h, CAS_RX_DRING_PTR_LO, CAS_CDRXADDR(sc, 0)); 1002 1003 KASSERT((CAS_CDRXCADDR(sc, 0) & 0x1fff) == 0); 1004 bus_space_write_4(t, h, CAS_RX_CRING_PTR_HI, 1005 (((uint64_t)CAS_CDRXCADDR(sc,0)) >> 32)); 1006 bus_space_write_4(t, h, CAS_RX_CRING_PTR_LO, CAS_CDRXCADDR(sc, 0)); 1007 1008 if (CAS_PLUS(sc)) { 1009 KASSERT((CAS_CDRXADDR2(sc, 0) & 0x1fff) == 0); 1010 bus_space_write_4(t, h, CAS_RX_DRING_PTR_HI2, 1011 (((uint64_t)CAS_CDRXADDR2(sc,0)) >> 32)); 1012 bus_space_write_4(t, h, CAS_RX_DRING_PTR_LO2, 1013 CAS_CDRXADDR2(sc, 0)); 1014 } 1015 1016 /* step 8. Global Configuration & Interrupt Mask */ 1017 bus_space_write_4(t, h, CAS_INTMASK, 1018 ~(CAS_INTR_TX_INTME|CAS_INTR_TX_EMPTY| 1019 CAS_INTR_TX_TAG_ERR| 1020 CAS_INTR_RX_DONE|CAS_INTR_RX_NOBUF| 1021 CAS_INTR_RX_TAG_ERR| 1022 CAS_INTR_RX_COMP_FULL|CAS_INTR_PCS| 1023 CAS_INTR_MAC_CONTROL|CAS_INTR_MIF| 1024 CAS_INTR_BERR)); 1025 bus_space_write_4(t, h, CAS_MAC_RX_MASK, 1026 CAS_MAC_RX_DONE|CAS_MAC_RX_FRAME_CNT); 1027 bus_space_write_4(t, h, CAS_MAC_TX_MASK, CAS_MAC_TX_XMIT_DONE); 1028 bus_space_write_4(t, h, CAS_MAC_CONTROL_MASK, 0); /* XXXX */ 1029 1030 /* step 9. ETX Configuration: use mostly default values */ 1031 1032 /* Enable DMA */ 1033 v = cas_ringsize(CAS_NTXDESC /*XXX*/) << 10; 1034 bus_space_write_4(t, h, CAS_TX_CONFIG, 1035 v|CAS_TX_CONFIG_TXDMA_EN|(1<<24)|(1<<29)); 1036 bus_space_write_4(t, h, CAS_TX_KICK, 0); 1037 1038 /* step 10. ERX Configuration */ 1039 1040 /* Encode Receive Descriptor ring size */ 1041 v = cas_ringsize(CAS_NRXDESC) << CAS_RX_CONFIG_RXDRNG_SZ_SHIFT; 1042 if (CAS_PLUS(sc)) 1043 v |= cas_ringsize(32) << CAS_RX_CONFIG_RXDRNG2_SZ_SHIFT; 1044 1045 /* Encode Receive Completion ring size */ 1046 v |= cas_cringsize(CAS_NRXCOMP) << CAS_RX_CONFIG_RXCRNG_SZ_SHIFT; 1047 1048 /* Enable DMA */ 1049 bus_space_write_4(t, h, CAS_RX_CONFIG, 1050 v|(2<<CAS_RX_CONFIG_FBOFF_SHFT)|CAS_RX_CONFIG_RXDMA_EN); 1051 1052 /* 1053 * The following value is for an OFF Threshold of about 3/4 full 1054 * and an ON Threshold of 1/4 full. 1055 */ 1056 bus_space_write_4(t, h, CAS_RX_PAUSE_THRESH, 1057 (3 * sc->sc_rxfifosize / 256) | 1058 ( (sc->sc_rxfifosize / 256) << 12)); 1059 bus_space_write_4(t, h, CAS_RX_BLANKING, (6<<12)|6); 1060 1061 /* step 11. Configure Media */ 1062 mii_mediachg(&sc->sc_mii); 1063 1064 /* step 12. RX_MAC Configuration Register */ 1065 v = bus_space_read_4(t, h, CAS_MAC_RX_CONFIG); 1066 v |= CAS_MAC_RX_ENABLE | CAS_MAC_RX_STRIP_CRC; 1067 bus_space_write_4(t, h, CAS_MAC_RX_CONFIG, v); 1068 1069 /* step 14. Issue Transmit Pending command */ 1070 1071 /* step 15. Give the receiver a swift kick */ 1072 bus_space_write_4(t, h, CAS_RX_KICK, CAS_NRXDESC-4); 1073 if (CAS_PLUS(sc)) 1074 bus_space_write_4(t, h, CAS_RX_KICK2, 4); 1075 1076 /* Start the one second timer. */ 1077 timeout_add_sec(&sc->sc_tick_ch, 1); 1078 1079 ifp->if_flags |= IFF_RUNNING; 1080 ifp->if_flags &= ~IFF_OACTIVE; 1081 ifp->if_timer = 0; 1082 splx(s); 1083 1084 return (0); 1085 } 1086 1087 void 1088 cas_init_regs(struct cas_softc *sc) 1089 { 1090 bus_space_tag_t t = sc->sc_memt; 1091 bus_space_handle_t h = sc->sc_memh; 1092 u_int32_t v, r; 1093 1094 /* These regs are not cleared on reset */ 1095 sc->sc_inited = 0; 1096 if (!sc->sc_inited) { 1097 1098 /* Wooo. Magic values. */ 1099 bus_space_write_4(t, h, CAS_MAC_IPG0, 0); 1100 bus_space_write_4(t, h, CAS_MAC_IPG1, 8); 1101 bus_space_write_4(t, h, CAS_MAC_IPG2, 4); 1102 1103 bus_space_write_4(t, h, CAS_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 1104 /* Max frame and max burst size */ 1105 v = ETHER_MAX_LEN | (0x2000 << 16) /* Burst size */; 1106 bus_space_write_4(t, h, CAS_MAC_MAC_MAX_FRAME, v); 1107 1108 bus_space_write_4(t, h, CAS_MAC_PREAMBLE_LEN, 0x7); 1109 bus_space_write_4(t, h, CAS_MAC_JAM_SIZE, 0x4); 1110 bus_space_write_4(t, h, CAS_MAC_ATTEMPT_LIMIT, 0x10); 1111 /* Dunno.... */ 1112 bus_space_write_4(t, h, CAS_MAC_CONTROL_TYPE, 0x8088); 1113 bus_space_write_4(t, h, CAS_MAC_RANDOM_SEED, 1114 ((sc->sc_arpcom.ac_enaddr[5]<<8)|sc->sc_arpcom.ac_enaddr[4])&0x3ff); 1115 1116 /* Secondary MAC addresses set to 0:0:0:0:0:0 */ 1117 for (r = CAS_MAC_ADDR3; r < CAS_MAC_ADDR42; r += 4) 1118 bus_space_write_4(t, h, r, 0); 1119 1120 /* MAC control addr set to 0:1:c2:0:1:80 */ 1121 bus_space_write_4(t, h, CAS_MAC_ADDR42, 0x0001); 1122 bus_space_write_4(t, h, CAS_MAC_ADDR43, 0xc200); 1123 bus_space_write_4(t, h, CAS_MAC_ADDR44, 0x0180); 1124 1125 /* MAC filter addr set to 0:0:0:0:0:0 */ 1126 bus_space_write_4(t, h, CAS_MAC_ADDR_FILTER0, 0); 1127 bus_space_write_4(t, h, CAS_MAC_ADDR_FILTER1, 0); 1128 bus_space_write_4(t, h, CAS_MAC_ADDR_FILTER2, 0); 1129 1130 bus_space_write_4(t, h, CAS_MAC_ADR_FLT_MASK1_2, 0); 1131 bus_space_write_4(t, h, CAS_MAC_ADR_FLT_MASK0, 0); 1132 1133 /* Hash table initialized to 0 */ 1134 for (r = CAS_MAC_HASH0; r <= CAS_MAC_HASH15; r += 4) 1135 bus_space_write_4(t, h, r, 0); 1136 1137 sc->sc_inited = 1; 1138 } 1139 1140 /* Counters need to be zeroed */ 1141 bus_space_write_4(t, h, CAS_MAC_NORM_COLL_CNT, 0); 1142 bus_space_write_4(t, h, CAS_MAC_FIRST_COLL_CNT, 0); 1143 bus_space_write_4(t, h, CAS_MAC_EXCESS_COLL_CNT, 0); 1144 bus_space_write_4(t, h, CAS_MAC_LATE_COLL_CNT, 0); 1145 bus_space_write_4(t, h, CAS_MAC_DEFER_TMR_CNT, 0); 1146 bus_space_write_4(t, h, CAS_MAC_PEAK_ATTEMPTS, 0); 1147 bus_space_write_4(t, h, CAS_MAC_RX_FRAME_COUNT, 0); 1148 bus_space_write_4(t, h, CAS_MAC_RX_LEN_ERR_CNT, 0); 1149 bus_space_write_4(t, h, CAS_MAC_RX_ALIGN_ERR, 0); 1150 bus_space_write_4(t, h, CAS_MAC_RX_CRC_ERR_CNT, 0); 1151 bus_space_write_4(t, h, CAS_MAC_RX_CODE_VIOL, 0); 1152 1153 /* Un-pause stuff */ 1154 bus_space_write_4(t, h, CAS_MAC_SEND_PAUSE_CMD, 0); 1155 1156 /* 1157 * Set the station address. 1158 */ 1159 bus_space_write_4(t, h, CAS_MAC_ADDR0, 1160 (sc->sc_arpcom.ac_enaddr[4]<<8) | sc->sc_arpcom.ac_enaddr[5]); 1161 bus_space_write_4(t, h, CAS_MAC_ADDR1, 1162 (sc->sc_arpcom.ac_enaddr[2]<<8) | sc->sc_arpcom.ac_enaddr[3]); 1163 bus_space_write_4(t, h, CAS_MAC_ADDR2, 1164 (sc->sc_arpcom.ac_enaddr[0]<<8) | sc->sc_arpcom.ac_enaddr[1]); 1165 } 1166 1167 /* 1168 * Receive interrupt. 1169 */ 1170 int 1171 cas_rint(struct cas_softc *sc) 1172 { 1173 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1174 bus_space_tag_t t = sc->sc_memt; 1175 bus_space_handle_t h = sc->sc_memh; 1176 struct cas_rxsoft *rxs; 1177 struct mbuf *m; 1178 u_int64_t word[4]; 1179 int len, off, idx; 1180 int i, skip; 1181 caddr_t cp; 1182 1183 for (i = sc->sc_rxptr;; i = CAS_NEXTRX(i + skip)) { 1184 CAS_CDRXCSYNC(sc, i, 1185 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1186 1187 word[0] = CAS_DMA_READ(sc->sc_rxcomps[i].cc_word[0]); 1188 word[1] = CAS_DMA_READ(sc->sc_rxcomps[i].cc_word[1]); 1189 word[2] = CAS_DMA_READ(sc->sc_rxcomps[i].cc_word[2]); 1190 word[3] = CAS_DMA_READ(sc->sc_rxcomps[i].cc_word[3]); 1191 1192 /* Stop if the hardware still owns the descriptor. */ 1193 if ((word[0] & CAS_RC0_TYPE) == 0 || word[3] & CAS_RC3_OWN) 1194 break; 1195 1196 len = CAS_RC1_HDR_LEN(word[1]); 1197 if (len > 0) { 1198 off = CAS_RC1_HDR_OFF(word[1]); 1199 idx = CAS_RC1_HDR_IDX(word[1]); 1200 rxs = &sc->sc_rxsoft[idx]; 1201 1202 DPRINTF(sc, ("hdr at idx %d, off %d, len %d\n", 1203 idx, off, len)); 1204 1205 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1206 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1207 1208 cp = rxs->rxs_kva + off * 256; 1209 m = m_devget(cp, len + ETHER_ALIGN, 0, ifp, NULL); 1210 1211 if (word[0] & CAS_RC0_RELEASE_HDR) 1212 cas_add_rxbuf(sc, idx); 1213 1214 if (m != NULL) { 1215 m_adj(m, ETHER_ALIGN); 1216 1217 #if NBPFILTER > 0 1218 /* 1219 * Pass this up to any BPF listeners, but only 1220 * pass it up the stack if its for us. 1221 */ 1222 if (ifp->if_bpf) 1223 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_IN); 1224 #endif /* NBPFILTER > 0 */ 1225 1226 ifp->if_ipackets++; 1227 ether_input_mbuf(ifp, m); 1228 } else 1229 ifp->if_ierrors++; 1230 } 1231 1232 len = CAS_RC0_DATA_LEN(word[0]); 1233 if (len > 0) { 1234 off = CAS_RC0_DATA_OFF(word[0]); 1235 idx = CAS_RC0_DATA_IDX(word[0]); 1236 rxs = &sc->sc_rxsoft[idx]; 1237 1238 DPRINTF(sc, ("data at idx %d, off %d, len %d\n", 1239 idx, off, len)); 1240 1241 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1242 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1243 1244 /* XXX We should not be copying the packet here. */ 1245 cp = rxs->rxs_kva + off; 1246 m = m_devget(cp, len + ETHER_ALIGN, 0, ifp, NULL); 1247 1248 if (word[0] & CAS_RC0_RELEASE_DATA) 1249 cas_add_rxbuf(sc, idx); 1250 1251 if (m != NULL) { 1252 m_adj(m, ETHER_ALIGN); 1253 1254 #if NBPFILTER > 0 1255 /* 1256 * Pass this up to any BPF listeners, but only 1257 * pass it up the stack if its for us. 1258 */ 1259 if (ifp->if_bpf) 1260 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_IN); 1261 #endif /* NBPFILTER > 0 */ 1262 1263 ifp->if_ipackets++; 1264 ether_input_mbuf(ifp, m); 1265 } else 1266 ifp->if_ierrors++; 1267 } 1268 1269 if (word[0] & CAS_RC0_SPLIT) 1270 printf("split packet\n"); 1271 1272 skip = CAS_RC0_SKIP(word[0]); 1273 } 1274 1275 while (sc->sc_rxptr != i) { 1276 sc->sc_rxcomps[sc->sc_rxptr].cc_word[0] = 0; 1277 sc->sc_rxcomps[sc->sc_rxptr].cc_word[1] = 0; 1278 sc->sc_rxcomps[sc->sc_rxptr].cc_word[2] = 0; 1279 sc->sc_rxcomps[sc->sc_rxptr].cc_word[3] = 1280 CAS_DMA_WRITE(CAS_RC3_OWN); 1281 CAS_CDRXCSYNC(sc, sc->sc_rxptr, 1282 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1283 1284 sc->sc_rxptr = CAS_NEXTRX(sc->sc_rxptr); 1285 } 1286 1287 bus_space_write_4(t, h, CAS_RX_COMP_TAIL, sc->sc_rxptr); 1288 1289 DPRINTF(sc, ("cas_rint: done sc->rxptr %d, complete %d\n", 1290 sc->sc_rxptr, bus_space_read_4(t, h, CAS_RX_COMPLETION))); 1291 1292 return (1); 1293 } 1294 1295 /* 1296 * cas_add_rxbuf: 1297 * 1298 * Add a receive buffer to the indicated descriptor. 1299 */ 1300 int 1301 cas_add_rxbuf(struct cas_softc *sc, int idx) 1302 { 1303 bus_space_tag_t t = sc->sc_memt; 1304 bus_space_handle_t h = sc->sc_memh; 1305 1306 CAS_INIT_RXDESC(sc, sc->sc_rxdptr, idx); 1307 1308 if ((sc->sc_rxdptr % 4) == 0) 1309 bus_space_write_4(t, h, CAS_RX_KICK, sc->sc_rxdptr); 1310 1311 if (++sc->sc_rxdptr == CAS_NRXDESC) 1312 sc->sc_rxdptr = 0; 1313 1314 return (0); 1315 } 1316 1317 int 1318 cas_eint(struct cas_softc *sc, u_int status) 1319 { 1320 if ((status & CAS_INTR_MIF) != 0) { 1321 #ifdef CAS_DEBUG 1322 printf("%s: link status changed\n", sc->sc_dev.dv_xname); 1323 #endif 1324 return (1); 1325 } 1326 1327 printf("%s: status=%b\n", sc->sc_dev.dv_xname, status, CAS_INTR_BITS); 1328 return (1); 1329 } 1330 1331 int 1332 cas_pint(struct cas_softc *sc) 1333 { 1334 bus_space_tag_t t = sc->sc_memt; 1335 bus_space_handle_t seb = sc->sc_memh; 1336 u_int32_t status; 1337 1338 status = bus_space_read_4(t, seb, CAS_MII_INTERRUP_STATUS); 1339 status |= bus_space_read_4(t, seb, CAS_MII_INTERRUP_STATUS); 1340 #ifdef CAS_DEBUG 1341 if (status) 1342 printf("%s: link status changed\n", sc->sc_dev.dv_xname); 1343 #endif 1344 return (1); 1345 } 1346 1347 int 1348 cas_intr(void *v) 1349 { 1350 struct cas_softc *sc = (struct cas_softc *)v; 1351 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1352 bus_space_tag_t t = sc->sc_memt; 1353 bus_space_handle_t seb = sc->sc_memh; 1354 u_int32_t status; 1355 int r = 0; 1356 1357 status = bus_space_read_4(t, seb, CAS_STATUS); 1358 DPRINTF(sc, ("%s: cas_intr: cplt %xstatus %b\n", 1359 sc->sc_dev.dv_xname, (status>>19), status, CAS_INTR_BITS)); 1360 1361 if ((status & CAS_INTR_PCS) != 0) 1362 r |= cas_pint(sc); 1363 1364 if ((status & (CAS_INTR_TX_TAG_ERR | CAS_INTR_RX_TAG_ERR | 1365 CAS_INTR_RX_COMP_FULL | CAS_INTR_BERR)) != 0) 1366 r |= cas_eint(sc, status); 1367 1368 if ((status & (CAS_INTR_TX_EMPTY | CAS_INTR_TX_INTME)) != 0) 1369 r |= cas_tint(sc, status); 1370 1371 if ((status & (CAS_INTR_RX_DONE | CAS_INTR_RX_NOBUF)) != 0) 1372 r |= cas_rint(sc); 1373 1374 /* We should eventually do more than just print out error stats. */ 1375 if (status & CAS_INTR_TX_MAC) { 1376 int txstat = bus_space_read_4(t, seb, CAS_MAC_TX_STATUS); 1377 #ifdef CAS_DEBUG 1378 if (txstat & ~CAS_MAC_TX_XMIT_DONE) 1379 printf("%s: MAC tx fault, status %x\n", 1380 sc->sc_dev.dv_xname, txstat); 1381 #endif 1382 if (txstat & (CAS_MAC_TX_UNDERRUN | CAS_MAC_TX_PKT_TOO_LONG)) 1383 cas_init(ifp); 1384 } 1385 if (status & CAS_INTR_RX_MAC) { 1386 int rxstat = bus_space_read_4(t, seb, CAS_MAC_RX_STATUS); 1387 #ifdef CAS_DEBUG 1388 if (rxstat & ~CAS_MAC_RX_DONE) 1389 printf("%s: MAC rx fault, status %x\n", 1390 sc->sc_dev.dv_xname, rxstat); 1391 #endif 1392 /* 1393 * On some chip revisions CAS_MAC_RX_OVERFLOW happen often 1394 * due to a silicon bug so handle them silently. 1395 */ 1396 if (rxstat & CAS_MAC_RX_OVERFLOW) { 1397 ifp->if_ierrors++; 1398 cas_init(ifp); 1399 } 1400 #ifdef CAS_DEBUG 1401 else if (rxstat & ~(CAS_MAC_RX_DONE | CAS_MAC_RX_FRAME_CNT)) 1402 printf("%s: MAC rx fault, status %x\n", 1403 sc->sc_dev.dv_xname, rxstat); 1404 #endif 1405 } 1406 return (r); 1407 } 1408 1409 1410 void 1411 cas_watchdog(struct ifnet *ifp) 1412 { 1413 struct cas_softc *sc = ifp->if_softc; 1414 1415 DPRINTF(sc, ("cas_watchdog: CAS_RX_CONFIG %x CAS_MAC_RX_STATUS %x " 1416 "CAS_MAC_RX_CONFIG %x\n", 1417 bus_space_read_4(sc->sc_memt, sc->sc_memh, CAS_RX_CONFIG), 1418 bus_space_read_4(sc->sc_memt, sc->sc_memh, CAS_MAC_RX_STATUS), 1419 bus_space_read_4(sc->sc_memt, sc->sc_memh, CAS_MAC_RX_CONFIG))); 1420 1421 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1422 ++ifp->if_oerrors; 1423 1424 /* Try to get more packets going. */ 1425 cas_init(ifp); 1426 } 1427 1428 /* 1429 * Initialize the MII Management Interface 1430 */ 1431 void 1432 cas_mifinit(struct cas_softc *sc) 1433 { 1434 bus_space_tag_t t = sc->sc_memt; 1435 bus_space_handle_t mif = sc->sc_memh; 1436 1437 /* Configure the MIF in frame mode */ 1438 sc->sc_mif_config = bus_space_read_4(t, mif, CAS_MIF_CONFIG); 1439 sc->sc_mif_config &= ~CAS_MIF_CONFIG_BB_ENA; 1440 bus_space_write_4(t, mif, CAS_MIF_CONFIG, sc->sc_mif_config); 1441 } 1442 1443 /* 1444 * MII interface 1445 * 1446 * The Cassini MII interface supports at least three different operating modes: 1447 * 1448 * Bitbang mode is implemented using data, clock and output enable registers. 1449 * 1450 * Frame mode is implemented by loading a complete frame into the frame 1451 * register and polling the valid bit for completion. 1452 * 1453 * Polling mode uses the frame register but completion is indicated by 1454 * an interrupt. 1455 * 1456 */ 1457 int 1458 cas_mii_readreg(struct device *self, int phy, int reg) 1459 { 1460 struct cas_softc *sc = (void *)self; 1461 bus_space_tag_t t = sc->sc_memt; 1462 bus_space_handle_t mif = sc->sc_memh; 1463 int n; 1464 u_int32_t v; 1465 1466 #ifdef CAS_DEBUG 1467 if (sc->sc_debug) 1468 printf("cas_mii_readreg: phy %d reg %d\n", phy, reg); 1469 #endif 1470 1471 /* Construct the frame command */ 1472 v = (reg << CAS_MIF_REG_SHIFT) | (phy << CAS_MIF_PHY_SHIFT) | 1473 CAS_MIF_FRAME_READ; 1474 1475 bus_space_write_4(t, mif, CAS_MIF_FRAME, v); 1476 for (n = 0; n < 100; n++) { 1477 DELAY(1); 1478 v = bus_space_read_4(t, mif, CAS_MIF_FRAME); 1479 if (v & CAS_MIF_FRAME_TA0) 1480 return (v & CAS_MIF_FRAME_DATA); 1481 } 1482 1483 printf("%s: mii_read timeout\n", sc->sc_dev.dv_xname); 1484 return (0); 1485 } 1486 1487 void 1488 cas_mii_writereg(struct device *self, int phy, int reg, int val) 1489 { 1490 struct cas_softc *sc = (void *)self; 1491 bus_space_tag_t t = sc->sc_memt; 1492 bus_space_handle_t mif = sc->sc_memh; 1493 int n; 1494 u_int32_t v; 1495 1496 #ifdef CAS_DEBUG 1497 if (sc->sc_debug) 1498 printf("cas_mii_writereg: phy %d reg %d val %x\n", 1499 phy, reg, val); 1500 #endif 1501 1502 /* Construct the frame command */ 1503 v = CAS_MIF_FRAME_WRITE | 1504 (phy << CAS_MIF_PHY_SHIFT) | 1505 (reg << CAS_MIF_REG_SHIFT) | 1506 (val & CAS_MIF_FRAME_DATA); 1507 1508 bus_space_write_4(t, mif, CAS_MIF_FRAME, v); 1509 for (n = 0; n < 100; n++) { 1510 DELAY(1); 1511 v = bus_space_read_4(t, mif, CAS_MIF_FRAME); 1512 if (v & CAS_MIF_FRAME_TA0) 1513 return; 1514 } 1515 1516 printf("%s: mii_write timeout\n", sc->sc_dev.dv_xname); 1517 } 1518 1519 void 1520 cas_mii_statchg(struct device *dev) 1521 { 1522 struct cas_softc *sc = (void *)dev; 1523 #ifdef CAS_DEBUG 1524 int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1525 #endif 1526 bus_space_tag_t t = sc->sc_memt; 1527 bus_space_handle_t mac = sc->sc_memh; 1528 u_int32_t v; 1529 1530 #ifdef CAS_DEBUG 1531 if (sc->sc_debug) 1532 printf("cas_mii_statchg: status change: phy = %d\n", 1533 sc->sc_phys[instance]); 1534 #endif 1535 1536 /* Set tx full duplex options */ 1537 bus_space_write_4(t, mac, CAS_MAC_TX_CONFIG, 0); 1538 delay(10000); /* reg must be cleared and delay before changing. */ 1539 v = CAS_MAC_TX_ENA_IPG0|CAS_MAC_TX_NGU|CAS_MAC_TX_NGU_LIMIT| 1540 CAS_MAC_TX_ENABLE; 1541 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) { 1542 v |= CAS_MAC_TX_IGN_CARRIER|CAS_MAC_TX_IGN_COLLIS; 1543 } 1544 bus_space_write_4(t, mac, CAS_MAC_TX_CONFIG, v); 1545 1546 /* XIF Configuration */ 1547 v = CAS_MAC_XIF_TX_MII_ENA; 1548 v |= CAS_MAC_XIF_LINK_LED; 1549 1550 /* MII needs echo disable if half duplex. */ 1551 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1552 /* turn on full duplex LED */ 1553 v |= CAS_MAC_XIF_FDPLX_LED; 1554 else 1555 /* half duplex -- disable echo */ 1556 v |= CAS_MAC_XIF_ECHO_DISABL; 1557 1558 switch (IFM_SUBTYPE(sc->sc_mii.mii_media_active)) { 1559 case IFM_1000_T: /* Gigabit using GMII interface */ 1560 case IFM_1000_SX: 1561 v |= CAS_MAC_XIF_GMII_MODE; 1562 break; 1563 default: 1564 v &= ~CAS_MAC_XIF_GMII_MODE; 1565 } 1566 bus_space_write_4(t, mac, CAS_MAC_XIF_CONFIG, v); 1567 } 1568 1569 int 1570 cas_pcs_readreg(struct device *self, int phy, int reg) 1571 { 1572 struct cas_softc *sc = (void *)self; 1573 bus_space_tag_t t = sc->sc_memt; 1574 bus_space_handle_t pcs = sc->sc_memh; 1575 1576 #ifdef CAS_DEBUG 1577 if (sc->sc_debug) 1578 printf("cas_pcs_readreg: phy %d reg %d\n", phy, reg); 1579 #endif 1580 1581 if (phy != CAS_PHYAD_EXTERNAL) 1582 return (0); 1583 1584 switch (reg) { 1585 case MII_BMCR: 1586 reg = CAS_MII_CONTROL; 1587 break; 1588 case MII_BMSR: 1589 reg = CAS_MII_STATUS; 1590 break; 1591 case MII_ANAR: 1592 reg = CAS_MII_ANAR; 1593 break; 1594 case MII_ANLPAR: 1595 reg = CAS_MII_ANLPAR; 1596 break; 1597 case MII_EXTSR: 1598 return (EXTSR_1000XFDX|EXTSR_1000XHDX); 1599 default: 1600 return (0); 1601 } 1602 1603 return bus_space_read_4(t, pcs, reg); 1604 } 1605 1606 void 1607 cas_pcs_writereg(struct device *self, int phy, int reg, int val) 1608 { 1609 struct cas_softc *sc = (void *)self; 1610 bus_space_tag_t t = sc->sc_memt; 1611 bus_space_handle_t pcs = sc->sc_memh; 1612 int reset = 0; 1613 1614 #ifdef CAS_DEBUG 1615 if (sc->sc_debug) 1616 printf("cas_pcs_writereg: phy %d reg %d val %x\n", 1617 phy, reg, val); 1618 #endif 1619 1620 if (phy != CAS_PHYAD_EXTERNAL) 1621 return; 1622 1623 if (reg == MII_ANAR) 1624 bus_space_write_4(t, pcs, CAS_MII_CONFIG, 0); 1625 1626 switch (reg) { 1627 case MII_BMCR: 1628 reset = (val & CAS_MII_CONTROL_RESET); 1629 reg = CAS_MII_CONTROL; 1630 break; 1631 case MII_BMSR: 1632 reg = CAS_MII_STATUS; 1633 break; 1634 case MII_ANAR: 1635 reg = CAS_MII_ANAR; 1636 break; 1637 case MII_ANLPAR: 1638 reg = CAS_MII_ANLPAR; 1639 break; 1640 default: 1641 return; 1642 } 1643 1644 bus_space_write_4(t, pcs, reg, val); 1645 1646 if (reset) 1647 cas_bitwait(sc, pcs, CAS_MII_CONTROL, CAS_MII_CONTROL_RESET, 0); 1648 1649 if (reg == CAS_MII_ANAR || reset) 1650 bus_space_write_4(t, pcs, CAS_MII_CONFIG, 1651 CAS_MII_CONFIG_ENABLE); 1652 } 1653 1654 int 1655 cas_mediachange(struct ifnet *ifp) 1656 { 1657 struct cas_softc *sc = ifp->if_softc; 1658 struct mii_data *mii = &sc->sc_mii; 1659 1660 if (mii->mii_instance) { 1661 struct mii_softc *miisc; 1662 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1663 mii_phy_reset(miisc); 1664 } 1665 1666 return (mii_mediachg(&sc->sc_mii)); 1667 } 1668 1669 void 1670 cas_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1671 { 1672 struct cas_softc *sc = ifp->if_softc; 1673 1674 mii_pollstat(&sc->sc_mii); 1675 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1676 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1677 } 1678 1679 /* 1680 * Process an ioctl request. 1681 */ 1682 int 1683 cas_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1684 { 1685 struct cas_softc *sc = ifp->if_softc; 1686 struct ifaddr *ifa = (struct ifaddr *)data; 1687 struct ifreq *ifr = (struct ifreq *)data; 1688 int s, error = 0; 1689 1690 s = splnet(); 1691 1692 if ((error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data)) > 0) { 1693 splx(s); 1694 return (error); 1695 } 1696 1697 switch (cmd) { 1698 1699 case SIOCSIFADDR: 1700 ifp->if_flags |= IFF_UP; 1701 if ((ifp->if_flags & IFF_RUNNING) == 0) 1702 cas_init(ifp); 1703 #ifdef INET 1704 if (ifa->ifa_addr->sa_family == AF_INET) 1705 arp_ifinit(&sc->sc_arpcom, ifa); 1706 #endif 1707 break; 1708 1709 case SIOCSIFFLAGS: 1710 if (ifp->if_flags & IFF_UP) { 1711 if ((ifp->if_flags & IFF_RUNNING) && 1712 ((ifp->if_flags ^ sc->sc_if_flags) & 1713 (IFF_ALLMULTI | IFF_PROMISC)) != 0) 1714 cas_setladrf(sc); 1715 else { 1716 if ((ifp->if_flags & IFF_RUNNING) == 0) 1717 cas_init(ifp); 1718 } 1719 } else { 1720 if (ifp->if_flags & IFF_RUNNING) 1721 cas_stop(ifp, 1); 1722 } 1723 sc->sc_if_flags = ifp->if_flags; 1724 1725 #ifdef CAS_DEBUG 1726 sc->sc_debug = (ifp->if_flags & IFF_DEBUG) != 0 ? 1 : 0; 1727 #endif 1728 break; 1729 1730 case SIOCSIFMTU: 1731 if (ifr->ifr_mtu > ETHERMTU || ifr->ifr_mtu < ETHERMIN) { 1732 error = EINVAL; 1733 } else if (ifp->if_mtu != ifr->ifr_mtu) { 1734 ifp->if_mtu = ifr->ifr_mtu; 1735 } 1736 break; 1737 1738 case SIOCADDMULTI: 1739 case SIOCDELMULTI: 1740 error = (cmd == SIOCADDMULTI) ? 1741 ether_addmulti(ifr, &sc->sc_arpcom) : 1742 ether_delmulti(ifr, &sc->sc_arpcom); 1743 1744 if (error == ENETRESET) { 1745 /* 1746 * Multicast list has changed; set the hardware filter 1747 * accordingly. 1748 */ 1749 if (ifp->if_flags & IFF_RUNNING) 1750 cas_setladrf(sc); 1751 error = 0; 1752 } 1753 break; 1754 1755 case SIOCGIFMEDIA: 1756 case SIOCSIFMEDIA: 1757 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1758 break; 1759 1760 default: 1761 error = ENOTTY; 1762 break; 1763 } 1764 1765 splx(s); 1766 return (error); 1767 } 1768 1769 1770 void 1771 cas_shutdown(void *arg) 1772 { 1773 struct cas_softc *sc = (struct cas_softc *)arg; 1774 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1775 1776 cas_stop(ifp, 1); 1777 } 1778 1779 /* 1780 * Set up the logical address filter. 1781 */ 1782 void 1783 cas_setladrf(struct cas_softc *sc) 1784 { 1785 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1786 struct ether_multi *enm; 1787 struct ether_multistep step; 1788 struct arpcom *ac = &sc->sc_arpcom; 1789 bus_space_tag_t t = sc->sc_memt; 1790 bus_space_handle_t h = sc->sc_memh; 1791 u_int32_t crc, hash[16], v; 1792 int i; 1793 1794 /* Get current RX configuration */ 1795 v = bus_space_read_4(t, h, CAS_MAC_RX_CONFIG); 1796 1797 1798 /* 1799 * Turn off promiscuous mode, promiscuous group mode (all multicast), 1800 * and hash filter. Depending on the case, the right bit will be 1801 * enabled. 1802 */ 1803 v &= ~(CAS_MAC_RX_PROMISCUOUS|CAS_MAC_RX_HASH_FILTER| 1804 CAS_MAC_RX_PROMISC_GRP); 1805 1806 if ((ifp->if_flags & IFF_PROMISC) != 0) { 1807 /* Turn on promiscuous mode */ 1808 v |= CAS_MAC_RX_PROMISCUOUS; 1809 ifp->if_flags |= IFF_ALLMULTI; 1810 goto chipit; 1811 } 1812 1813 /* 1814 * Set up multicast address filter by passing all multicast addresses 1815 * through a crc generator, and then using the high order 8 bits as an 1816 * index into the 256 bit logical address filter. The high order 4 1817 * bits selects the word, while the other 4 bits select the bit within 1818 * the word (where bit 0 is the MSB). 1819 */ 1820 1821 /* Clear hash table */ 1822 for (i = 0; i < 16; i++) 1823 hash[i] = 0; 1824 1825 1826 ETHER_FIRST_MULTI(step, ac, enm); 1827 while (enm != NULL) { 1828 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1829 /* 1830 * We must listen to a range of multicast addresses. 1831 * For now, just accept all multicasts, rather than 1832 * trying to set only those filter bits needed to match 1833 * the range. (At this time, the only use of address 1834 * ranges is for IP multicast routing, for which the 1835 * range is big enough to require all bits set.) 1836 * XXX use the addr filter for this 1837 */ 1838 ifp->if_flags |= IFF_ALLMULTI; 1839 v |= CAS_MAC_RX_PROMISC_GRP; 1840 goto chipit; 1841 } 1842 1843 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1844 1845 /* Just want the 8 most significant bits. */ 1846 crc >>= 24; 1847 1848 /* Set the corresponding bit in the filter. */ 1849 hash[crc >> 4] |= 1 << (15 - (crc & 15)); 1850 1851 ETHER_NEXT_MULTI(step, enm); 1852 } 1853 1854 v |= CAS_MAC_RX_HASH_FILTER; 1855 ifp->if_flags &= ~IFF_ALLMULTI; 1856 1857 /* Now load the hash table into the chip (if we are using it) */ 1858 for (i = 0; i < 16; i++) { 1859 bus_space_write_4(t, h, 1860 CAS_MAC_HASH0 + i * (CAS_MAC_HASH1-CAS_MAC_HASH0), 1861 hash[i]); 1862 } 1863 1864 chipit: 1865 bus_space_write_4(t, h, CAS_MAC_RX_CONFIG, v); 1866 } 1867 1868 int 1869 cas_encap(struct cas_softc *sc, struct mbuf *mhead, u_int32_t *bixp) 1870 { 1871 u_int64_t flags; 1872 u_int32_t cur, frag, i; 1873 bus_dmamap_t map; 1874 1875 cur = frag = *bixp; 1876 map = sc->sc_txd[cur].sd_map; 1877 1878 if (bus_dmamap_load_mbuf(sc->sc_dmatag, map, mhead, 1879 BUS_DMA_NOWAIT) != 0) { 1880 return (ENOBUFS); 1881 } 1882 1883 if ((sc->sc_tx_cnt + map->dm_nsegs) > (CAS_NTXDESC - 2)) { 1884 bus_dmamap_unload(sc->sc_dmatag, map); 1885 return (ENOBUFS); 1886 } 1887 1888 bus_dmamap_sync(sc->sc_dmatag, map, 0, map->dm_mapsize, 1889 BUS_DMASYNC_PREWRITE); 1890 1891 for (i = 0; i < map->dm_nsegs; i++) { 1892 sc->sc_txdescs[frag].cd_addr = 1893 CAS_DMA_WRITE(map->dm_segs[i].ds_addr); 1894 flags = (map->dm_segs[i].ds_len & CAS_TD_BUFSIZE) | 1895 (i == 0 ? CAS_TD_START_OF_PACKET : 0) | 1896 ((i == (map->dm_nsegs - 1)) ? CAS_TD_END_OF_PACKET : 0); 1897 sc->sc_txdescs[frag].cd_flags = CAS_DMA_WRITE(flags); 1898 bus_dmamap_sync(sc->sc_dmatag, sc->sc_cddmamap, 1899 CAS_CDTXOFF(frag), sizeof(struct cas_desc), 1900 BUS_DMASYNC_PREWRITE); 1901 cur = frag; 1902 if (++frag == CAS_NTXDESC) 1903 frag = 0; 1904 } 1905 1906 sc->sc_tx_cnt += map->dm_nsegs; 1907 sc->sc_txd[*bixp].sd_map = sc->sc_txd[cur].sd_map; 1908 sc->sc_txd[cur].sd_map = map; 1909 sc->sc_txd[cur].sd_mbuf = mhead; 1910 1911 bus_space_write_4(sc->sc_memt, sc->sc_memh, CAS_TX_KICK, frag); 1912 1913 *bixp = frag; 1914 1915 /* sync descriptors */ 1916 1917 return (0); 1918 } 1919 1920 /* 1921 * Transmit interrupt. 1922 */ 1923 int 1924 cas_tint(struct cas_softc *sc, u_int32_t status) 1925 { 1926 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1927 struct cas_sxd *sd; 1928 u_int32_t cons, comp; 1929 1930 comp = bus_space_read_4(sc->sc_memt, sc->sc_memh, CAS_TX_COMPLETION); 1931 cons = sc->sc_tx_cons; 1932 while (cons != comp) { 1933 sd = &sc->sc_txd[cons]; 1934 if (sd->sd_mbuf != NULL) { 1935 bus_dmamap_sync(sc->sc_dmatag, sd->sd_map, 0, 1936 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1937 bus_dmamap_unload(sc->sc_dmatag, sd->sd_map); 1938 m_freem(sd->sd_mbuf); 1939 sd->sd_mbuf = NULL; 1940 ifp->if_opackets++; 1941 } 1942 sc->sc_tx_cnt--; 1943 if (++cons == CAS_NTXDESC) 1944 cons = 0; 1945 } 1946 sc->sc_tx_cons = cons; 1947 1948 if (sc->sc_tx_cnt < CAS_NTXDESC - 2) 1949 ifp->if_flags &= ~IFF_OACTIVE; 1950 if (sc->sc_tx_cnt == 0) 1951 ifp->if_timer = 0; 1952 1953 cas_start(ifp); 1954 1955 return (1); 1956 } 1957 1958 void 1959 cas_start(struct ifnet *ifp) 1960 { 1961 struct cas_softc *sc = ifp->if_softc; 1962 struct mbuf *m; 1963 u_int32_t bix; 1964 1965 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1966 return; 1967 1968 bix = sc->sc_tx_prod; 1969 while (sc->sc_txd[bix].sd_mbuf == NULL) { 1970 IFQ_POLL(&ifp->if_snd, m); 1971 if (m == NULL) 1972 break; 1973 1974 #if NBPFILTER > 0 1975 /* 1976 * If BPF is listening on this interface, let it see the 1977 * packet before we commit it to the wire. 1978 */ 1979 if (ifp->if_bpf) 1980 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT); 1981 #endif 1982 1983 /* 1984 * Encapsulate this packet and start it going... 1985 * or fail... 1986 */ 1987 if (cas_encap(sc, m, &bix)) { 1988 ifp->if_flags |= IFF_OACTIVE; 1989 break; 1990 } 1991 1992 IFQ_DEQUEUE(&ifp->if_snd, m); 1993 ifp->if_timer = 5; 1994 } 1995 1996 sc->sc_tx_prod = bix; 1997 } 1998