1 /* $OpenBSD: if_cas.c,v 1.27 2009/07/23 19:35:32 kettenis Exp $ */ 2 3 /* 4 * 5 * Copyright (C) 2007 Mark Kettenis. 6 * Copyright (C) 2001 Eduardo Horvath. 7 * All rights reserved. 8 * 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 */ 32 33 /* 34 * Driver for Sun Cassini ethernet controllers. 35 * 36 * There are basically two variants of this chip: Cassini and 37 * Cassini+. We can distinguish between the two by revision: 0x10 and 38 * up are Cassini+. The most important difference is that Cassini+ 39 * has a second RX descriptor ring. Cassini+ will not work without 40 * configuring that second ring. However, since we don't use it we 41 * don't actually fill the descriptors, and only hand off the first 42 * four to the chip. 43 */ 44 45 #include "bpfilter.h" 46 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/timeout.h> 50 #include <sys/mbuf.h> 51 #include <sys/syslog.h> 52 #include <sys/malloc.h> 53 #include <sys/kernel.h> 54 #include <sys/socket.h> 55 #include <sys/ioctl.h> 56 #include <sys/errno.h> 57 #include <sys/device.h> 58 59 #include <machine/endian.h> 60 61 #include <net/if.h> 62 #include <net/if_dl.h> 63 #include <net/if_media.h> 64 65 #ifdef INET 66 #include <netinet/in.h> 67 #include <netinet/if_ether.h> 68 #endif 69 70 #if NBPFILTER > 0 71 #include <net/bpf.h> 72 #endif 73 74 #include <machine/bus.h> 75 #include <machine/intr.h> 76 77 #include <dev/mii/mii.h> 78 #include <dev/mii/miivar.h> 79 #include <dev/mii/mii_bitbang.h> 80 81 #include <dev/pci/if_casreg.h> 82 #include <dev/pci/if_casvar.h> 83 84 #include <dev/pci/pcivar.h> 85 #include <dev/pci/pcireg.h> 86 #include <dev/pci/pcidevs.h> 87 88 #ifdef __sparc64__ 89 #include <dev/ofw/openfirm.h> 90 #endif 91 92 #define TRIES 10000 93 94 struct cfdriver cas_cd = { 95 NULL, "cas", DV_IFNET 96 }; 97 98 int cas_match(struct device *, void *, void *); 99 void cas_attach(struct device *, struct device *, void *); 100 int cas_pci_enaddr(struct cas_softc *, struct pci_attach_args *); 101 102 struct cfattach cas_ca = { 103 sizeof(struct cas_softc), cas_match, cas_attach 104 }; 105 106 void cas_config(struct cas_softc *); 107 void cas_start(struct ifnet *); 108 void cas_stop(struct ifnet *, int); 109 int cas_ioctl(struct ifnet *, u_long, caddr_t); 110 void cas_tick(void *); 111 void cas_watchdog(struct ifnet *); 112 void cas_shutdown(void *); 113 int cas_init(struct ifnet *); 114 void cas_init_regs(struct cas_softc *); 115 int cas_ringsize(int); 116 int cas_cringsize(int); 117 int cas_meminit(struct cas_softc *); 118 void cas_mifinit(struct cas_softc *); 119 int cas_bitwait(struct cas_softc *, bus_space_handle_t, int, 120 u_int32_t, u_int32_t); 121 void cas_reset(struct cas_softc *); 122 int cas_reset_rx(struct cas_softc *); 123 int cas_reset_tx(struct cas_softc *); 124 int cas_disable_rx(struct cas_softc *); 125 int cas_disable_tx(struct cas_softc *); 126 void cas_rxdrain(struct cas_softc *); 127 int cas_add_rxbuf(struct cas_softc *, int idx); 128 void cas_setladrf(struct cas_softc *); 129 int cas_encap(struct cas_softc *, struct mbuf *, u_int32_t *); 130 131 /* MII methods & callbacks */ 132 int cas_mii_readreg(struct device *, int, int); 133 void cas_mii_writereg(struct device *, int, int, int); 134 void cas_mii_statchg(struct device *); 135 int cas_pcs_readreg(struct device *, int, int); 136 void cas_pcs_writereg(struct device *, int, int, int); 137 138 int cas_mediachange(struct ifnet *); 139 void cas_mediastatus(struct ifnet *, struct ifmediareq *); 140 141 int cas_eint(struct cas_softc *, u_int); 142 int cas_rint(struct cas_softc *); 143 int cas_tint(struct cas_softc *, u_int32_t); 144 int cas_pint(struct cas_softc *); 145 int cas_intr(void *); 146 147 #ifdef CAS_DEBUG 148 #define DPRINTF(sc, x) if ((sc)->sc_arpcom.ac_if.if_flags & IFF_DEBUG) \ 149 printf x 150 #else 151 #define DPRINTF(sc, x) /* nothing */ 152 #endif 153 154 const struct pci_matchid cas_pci_devices[] = { 155 { PCI_VENDOR_SUN, PCI_PRODUCT_SUN_CASSINI }, 156 { PCI_VENDOR_NS, PCI_PRODUCT_NS_SATURN } 157 }; 158 159 int 160 cas_match(struct device *parent, void *cf, void *aux) 161 { 162 return (pci_matchbyid((struct pci_attach_args *)aux, cas_pci_devices, 163 sizeof(cas_pci_devices)/sizeof(cas_pci_devices[0]))); 164 } 165 166 #define PROMHDR_PTR_DATA 0x18 167 #define PROMDATA_PTR_VPD 0x08 168 #define PROMDATA_DATA2 0x0a 169 170 static const u_int8_t cas_promhdr[] = { 0x55, 0xaa }; 171 static const u_int8_t cas_promdat[] = { 172 'P', 'C', 'I', 'R', 173 PCI_VENDOR_SUN & 0xff, PCI_VENDOR_SUN >> 8, 174 PCI_PRODUCT_SUN_CASSINI & 0xff, PCI_PRODUCT_SUN_CASSINI >> 8 175 }; 176 177 static const u_int8_t cas_promdat2[] = { 178 0x18, 0x00, /* structure length */ 179 0x00, /* structure revision */ 180 0x00, /* interface revision */ 181 PCI_SUBCLASS_NETWORK_ETHERNET, /* subclass code */ 182 PCI_CLASS_NETWORK /* class code */ 183 }; 184 185 int 186 cas_pci_enaddr(struct cas_softc *sc, struct pci_attach_args *pa) 187 { 188 struct pci_vpd_largeres *res; 189 struct pci_vpd *vpd; 190 bus_space_handle_t romh; 191 bus_space_tag_t romt; 192 bus_size_t romsize = 0; 193 u_int8_t buf[32], *desc; 194 pcireg_t address; 195 int dataoff, vpdoff, len; 196 int rv = -1; 197 198 if (pci_mapreg_map(pa, PCI_ROM_REG, PCI_MAPREG_TYPE_MEM, 0, 199 &romt, &romh, 0, &romsize, 0)) 200 return (-1); 201 202 address = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_ROM_REG); 203 address |= PCI_ROM_ENABLE; 204 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_ROM_REG, address); 205 206 bus_space_read_region_1(romt, romh, 0, buf, sizeof(buf)); 207 if (bcmp(buf, cas_promhdr, sizeof(cas_promhdr))) 208 goto fail; 209 210 dataoff = buf[PROMHDR_PTR_DATA] | (buf[PROMHDR_PTR_DATA + 1] << 8); 211 if (dataoff < 0x1c) 212 goto fail; 213 214 bus_space_read_region_1(romt, romh, dataoff, buf, sizeof(buf)); 215 if (bcmp(buf, cas_promdat, sizeof(cas_promdat)) || 216 bcmp(buf + PROMDATA_DATA2, cas_promdat2, sizeof(cas_promdat2))) 217 goto fail; 218 219 vpdoff = buf[PROMDATA_PTR_VPD] | (buf[PROMDATA_PTR_VPD + 1] << 8); 220 if (vpdoff < 0x1c) 221 goto fail; 222 223 next: 224 bus_space_read_region_1(romt, romh, vpdoff, buf, sizeof(buf)); 225 if (!PCI_VPDRES_ISLARGE(buf[0])) 226 goto fail; 227 228 res = (struct pci_vpd_largeres *)buf; 229 vpdoff += sizeof(*res); 230 231 len = ((res->vpdres_len_msb << 8) + res->vpdres_len_lsb); 232 switch(PCI_VPDRES_LARGE_NAME(res->vpdres_byte0)) { 233 case PCI_VPDRES_TYPE_IDENTIFIER_STRING: 234 /* Skip identifier string. */ 235 vpdoff += len; 236 goto next; 237 238 case PCI_VPDRES_TYPE_VPD: 239 while (len > 0) { 240 bus_space_read_region_1(romt, romh, vpdoff, 241 buf, sizeof(buf)); 242 243 vpd = (struct pci_vpd *)buf; 244 vpdoff += sizeof(*vpd) + vpd->vpd_len; 245 len -= sizeof(*vpd) + vpd->vpd_len; 246 247 /* 248 * We're looking for an "Enhanced" VPD... 249 */ 250 if (vpd->vpd_key0 != 'Z') 251 continue; 252 253 desc = buf + sizeof(*vpd); 254 255 /* 256 * ...which is an instance property... 257 */ 258 if (desc[0] != 'I') 259 continue; 260 desc += 3; 261 262 /* 263 * ...that's a byte array with the proper 264 * length for a MAC address... 265 */ 266 if (desc[0] != 'B' || desc[1] != ETHER_ADDR_LEN) 267 continue; 268 desc += 2; 269 270 /* 271 * ...named "local-mac-address". 272 */ 273 if (strcmp(desc, "local-mac-address") != 0) 274 continue; 275 desc += strlen("local-mac-address") + 1; 276 277 bcopy(desc, sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN); 278 rv = 0; 279 } 280 break; 281 282 default: 283 goto fail; 284 } 285 286 fail: 287 if (romsize != 0) 288 bus_space_unmap(romt, romh, romsize); 289 290 address = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_ROM_REG); 291 address &= ~PCI_ROM_ENABLE; 292 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_ROM_REG, address); 293 294 return (rv); 295 } 296 297 void 298 cas_attach(struct device *parent, struct device *self, void *aux) 299 { 300 struct pci_attach_args *pa = aux; 301 struct cas_softc *sc = (void *)self; 302 pci_intr_handle_t ih; 303 #ifdef __sparc64__ 304 /* XXX the following declarations should be elsewhere */ 305 extern void myetheraddr(u_char *); 306 #endif 307 const char *intrstr = NULL; 308 bus_size_t size; 309 int gotenaddr = 0; 310 311 sc->sc_rev = PCI_REVISION(pa->pa_class); 312 sc->sc_dmatag = pa->pa_dmat; 313 314 #define PCI_CAS_BASEADDR 0x10 315 if (pci_mapreg_map(pa, PCI_CAS_BASEADDR, PCI_MAPREG_TYPE_MEM, 0, 316 &sc->sc_memt, &sc->sc_memh, NULL, &size, 0) != 0) { 317 printf(": can't map registers\n"); 318 return; 319 } 320 321 if (cas_pci_enaddr(sc, pa) == 0) 322 gotenaddr = 1; 323 324 #ifdef __sparc64__ 325 if (!gotenaddr) { 326 if (OF_getprop(PCITAG_NODE(pa->pa_tag), "local-mac-address", 327 sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN) <= 0) 328 myetheraddr(sc->sc_arpcom.ac_enaddr); 329 gotenaddr = 1; 330 } 331 #endif 332 #ifdef __powerpc__ 333 if (!gotenaddr) { 334 pci_ether_hw_addr(pa->pa_pc, sc->sc_arpcom.ac_enaddr); 335 gotenaddr = 1; 336 } 337 #endif 338 339 sc->sc_burst = 16; /* XXX */ 340 341 if (pci_intr_map(pa, &ih) != 0) { 342 printf(": couldn't map interrupt\n"); 343 bus_space_unmap(sc->sc_memt, sc->sc_memh, size); 344 return; 345 } 346 intrstr = pci_intr_string(pa->pa_pc, ih); 347 sc->sc_ih = pci_intr_establish(pa->pa_pc, 348 ih, IPL_NET, cas_intr, sc, self->dv_xname); 349 if (sc->sc_ih == NULL) { 350 printf(": couldn't establish interrupt"); 351 if (intrstr != NULL) 352 printf(" at %s", intrstr); 353 printf("\n"); 354 bus_space_unmap(sc->sc_memt, sc->sc_memh, size); 355 return; 356 } 357 358 printf(": %s", intrstr); 359 360 /* 361 * call the main configure 362 */ 363 cas_config(sc); 364 } 365 366 /* 367 * cas_config: 368 * 369 * Attach a Cassini interface to the system. 370 */ 371 void 372 cas_config(struct cas_softc *sc) 373 { 374 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 375 struct mii_data *mii = &sc->sc_mii; 376 struct mii_softc *child; 377 int i, error; 378 379 /* Make sure the chip is stopped. */ 380 ifp->if_softc = sc; 381 cas_reset(sc); 382 383 /* 384 * Allocate the control data structures, and create and load the 385 * DMA map for it. 386 */ 387 if ((error = bus_dmamem_alloc(sc->sc_dmatag, 388 sizeof(struct cas_control_data), CAS_PAGE_SIZE, 0, &sc->sc_cdseg, 389 1, &sc->sc_cdnseg, 0)) != 0) { 390 printf("\n%s: unable to allocate control data, error = %d\n", 391 sc->sc_dev.dv_xname, error); 392 goto fail_0; 393 } 394 395 /* XXX should map this in with correct endianness */ 396 if ((error = bus_dmamem_map(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg, 397 sizeof(struct cas_control_data), (caddr_t *)&sc->sc_control_data, 398 BUS_DMA_COHERENT)) != 0) { 399 printf("\n%s: unable to map control data, error = %d\n", 400 sc->sc_dev.dv_xname, error); 401 goto fail_1; 402 } 403 404 if ((error = bus_dmamap_create(sc->sc_dmatag, 405 sizeof(struct cas_control_data), 1, 406 sizeof(struct cas_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 407 printf("\n%s: unable to create control data DMA map, " 408 "error = %d\n", sc->sc_dev.dv_xname, error); 409 goto fail_2; 410 } 411 412 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_cddmamap, 413 sc->sc_control_data, sizeof(struct cas_control_data), NULL, 414 0)) != 0) { 415 printf("\n%s: unable to load control data DMA map, error = %d\n", 416 sc->sc_dev.dv_xname, error); 417 goto fail_3; 418 } 419 420 bzero(sc->sc_control_data, sizeof(struct cas_control_data)); 421 422 /* 423 * Create the receive buffer DMA maps. 424 */ 425 for (i = 0; i < CAS_NRXDESC; i++) { 426 bus_dma_segment_t seg; 427 caddr_t kva; 428 int rseg; 429 430 if ((error = bus_dmamem_alloc(sc->sc_dmatag, CAS_PAGE_SIZE, 431 CAS_PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 432 printf("\n%s: unable to alloc rx DMA mem %d, " 433 "error = %d\n", sc->sc_dev.dv_xname, i, error); 434 goto fail_5; 435 } 436 sc->sc_rxsoft[i].rxs_dmaseg = seg; 437 438 if ((error = bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 439 CAS_PAGE_SIZE, &kva, BUS_DMA_NOWAIT)) != 0) { 440 printf("\n%s: unable to alloc rx DMA mem %d, " 441 "error = %d\n", sc->sc_dev.dv_xname, i, error); 442 goto fail_5; 443 } 444 sc->sc_rxsoft[i].rxs_kva = kva; 445 446 if ((error = bus_dmamap_create(sc->sc_dmatag, CAS_PAGE_SIZE, 1, 447 CAS_PAGE_SIZE, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 448 printf("\n%s: unable to create rx DMA map %d, " 449 "error = %d\n", sc->sc_dev.dv_xname, i, error); 450 goto fail_5; 451 } 452 453 if ((error = bus_dmamap_load(sc->sc_dmatag, 454 sc->sc_rxsoft[i].rxs_dmamap, kva, CAS_PAGE_SIZE, NULL, 455 BUS_DMA_NOWAIT)) != 0) { 456 printf("\n%s: unable to load rx DMA map %d, " 457 "error = %d\n", sc->sc_dev.dv_xname, i, error); 458 goto fail_5; 459 } 460 } 461 462 /* 463 * Create the transmit buffer DMA maps. 464 */ 465 for (i = 0; i < CAS_NTXDESC; i++) { 466 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 467 CAS_NTXSEGS, MCLBYTES, 0, BUS_DMA_NOWAIT, 468 &sc->sc_txd[i].sd_map)) != 0) { 469 printf("\n%s: unable to create tx DMA map %d, " 470 "error = %d\n", sc->sc_dev.dv_xname, i, error); 471 goto fail_6; 472 } 473 sc->sc_txd[i].sd_mbuf = NULL; 474 } 475 476 /* 477 * From this point forward, the attachment cannot fail. A failure 478 * before this point releases all resources that may have been 479 * allocated. 480 */ 481 482 /* Announce ourselves. */ 483 printf(", address %s\n", ether_sprintf(sc->sc_arpcom.ac_enaddr)); 484 485 /* Get RX FIFO size */ 486 sc->sc_rxfifosize = 16 * 1024; 487 488 /* Initialize ifnet structure. */ 489 strlcpy(ifp->if_xname, sc->sc_dev.dv_xname, sizeof ifp->if_xname); 490 ifp->if_softc = sc; 491 ifp->if_flags = 492 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 493 ifp->if_start = cas_start; 494 ifp->if_ioctl = cas_ioctl; 495 ifp->if_watchdog = cas_watchdog; 496 IFQ_SET_MAXLEN(&ifp->if_snd, CAS_NTXDESC - 1); 497 IFQ_SET_READY(&ifp->if_snd); 498 499 ifp->if_capabilities = IFCAP_VLAN_MTU; 500 501 /* Initialize ifmedia structures and MII info */ 502 mii->mii_ifp = ifp; 503 mii->mii_readreg = cas_mii_readreg; 504 mii->mii_writereg = cas_mii_writereg; 505 mii->mii_statchg = cas_mii_statchg; 506 507 ifmedia_init(&mii->mii_media, 0, cas_mediachange, cas_mediastatus); 508 509 bus_space_write_4(sc->sc_memt, sc->sc_memh, CAS_MII_DATAPATH_MODE, 0); 510 511 cas_mifinit(sc); 512 513 if (sc->sc_mif_config & CAS_MIF_CONFIG_MDI1) { 514 sc->sc_mif_config |= CAS_MIF_CONFIG_PHY_SEL; 515 bus_space_write_4(sc->sc_memt, sc->sc_memh, 516 CAS_MIF_CONFIG, sc->sc_mif_config); 517 } 518 519 mii_attach(&sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 520 MII_OFFSET_ANY, 0); 521 522 child = LIST_FIRST(&mii->mii_phys); 523 if (child == NULL && 524 sc->sc_mif_config & (CAS_MIF_CONFIG_MDI0|CAS_MIF_CONFIG_MDI1)) { 525 /* 526 * Try the external PCS SERDES if we didn't find any 527 * MII devices. 528 */ 529 bus_space_write_4(sc->sc_memt, sc->sc_memh, 530 CAS_MII_DATAPATH_MODE, CAS_MII_DATAPATH_SERDES); 531 532 bus_space_write_4(sc->sc_memt, sc->sc_memh, 533 CAS_MII_CONFIG, CAS_MII_CONFIG_ENABLE); 534 535 mii->mii_readreg = cas_pcs_readreg; 536 mii->mii_writereg = cas_pcs_writereg; 537 538 mii_attach(&sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 539 MII_OFFSET_ANY, MIIF_NOISOLATE); 540 } 541 542 child = LIST_FIRST(&mii->mii_phys); 543 if (child == NULL) { 544 /* No PHY attached */ 545 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 546 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 547 } else { 548 /* 549 * Walk along the list of attached MII devices and 550 * establish an `MII instance' to `phy number' 551 * mapping. We'll use this mapping in media change 552 * requests to determine which phy to use to program 553 * the MIF configuration register. 554 */ 555 for (; child != NULL; child = LIST_NEXT(child, mii_list)) { 556 /* 557 * Note: we support just two PHYs: the built-in 558 * internal device and an external on the MII 559 * connector. 560 */ 561 if (child->mii_phy > 1 || child->mii_inst > 1) { 562 printf("%s: cannot accommodate MII device %s" 563 " at phy %d, instance %d\n", 564 sc->sc_dev.dv_xname, 565 child->mii_dev.dv_xname, 566 child->mii_phy, child->mii_inst); 567 continue; 568 } 569 570 sc->sc_phys[child->mii_inst] = child->mii_phy; 571 } 572 573 /* 574 * XXX - we can really do the following ONLY if the 575 * phy indeed has the auto negotiation capability!! 576 */ 577 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_AUTO); 578 } 579 580 /* Attach the interface. */ 581 if_attach(ifp); 582 ether_ifattach(ifp); 583 584 sc->sc_sh = shutdownhook_establish(cas_shutdown, sc); 585 if (sc->sc_sh == NULL) 586 panic("cas_config: can't establish shutdownhook"); 587 588 timeout_set(&sc->sc_tick_ch, cas_tick, sc); 589 return; 590 591 /* 592 * Free any resources we've allocated during the failed attach 593 * attempt. Do this in reverse order and fall through. 594 */ 595 fail_6: 596 for (i = 0; i < CAS_NTXDESC; i++) { 597 if (sc->sc_txd[i].sd_map != NULL) 598 bus_dmamap_destroy(sc->sc_dmatag, 599 sc->sc_txd[i].sd_map); 600 } 601 fail_5: 602 for (i = 0; i < CAS_NRXDESC; i++) { 603 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 604 bus_dmamap_destroy(sc->sc_dmatag, 605 sc->sc_rxsoft[i].rxs_dmamap); 606 } 607 bus_dmamap_unload(sc->sc_dmatag, sc->sc_cddmamap); 608 fail_3: 609 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_cddmamap); 610 fail_2: 611 bus_dmamem_unmap(sc->sc_dmatag, (caddr_t)sc->sc_control_data, 612 sizeof(struct cas_control_data)); 613 fail_1: 614 bus_dmamem_free(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg); 615 fail_0: 616 return; 617 } 618 619 620 void 621 cas_tick(void *arg) 622 { 623 struct cas_softc *sc = arg; 624 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 625 bus_space_tag_t t = sc->sc_memt; 626 bus_space_handle_t mac = sc->sc_memh; 627 int s; 628 u_int32_t v; 629 630 /* unload collisions counters */ 631 v = bus_space_read_4(t, mac, CAS_MAC_EXCESS_COLL_CNT) + 632 bus_space_read_4(t, mac, CAS_MAC_LATE_COLL_CNT); 633 ifp->if_collisions += v + 634 bus_space_read_4(t, mac, CAS_MAC_NORM_COLL_CNT) + 635 bus_space_read_4(t, mac, CAS_MAC_FIRST_COLL_CNT); 636 ifp->if_oerrors += v; 637 638 /* read error counters */ 639 ifp->if_ierrors += 640 bus_space_read_4(t, mac, CAS_MAC_RX_LEN_ERR_CNT) + 641 bus_space_read_4(t, mac, CAS_MAC_RX_ALIGN_ERR) + 642 bus_space_read_4(t, mac, CAS_MAC_RX_CRC_ERR_CNT) + 643 bus_space_read_4(t, mac, CAS_MAC_RX_CODE_VIOL); 644 645 /* clear the hardware counters */ 646 bus_space_write_4(t, mac, CAS_MAC_NORM_COLL_CNT, 0); 647 bus_space_write_4(t, mac, CAS_MAC_FIRST_COLL_CNT, 0); 648 bus_space_write_4(t, mac, CAS_MAC_EXCESS_COLL_CNT, 0); 649 bus_space_write_4(t, mac, CAS_MAC_LATE_COLL_CNT, 0); 650 bus_space_write_4(t, mac, CAS_MAC_RX_LEN_ERR_CNT, 0); 651 bus_space_write_4(t, mac, CAS_MAC_RX_ALIGN_ERR, 0); 652 bus_space_write_4(t, mac, CAS_MAC_RX_CRC_ERR_CNT, 0); 653 bus_space_write_4(t, mac, CAS_MAC_RX_CODE_VIOL, 0); 654 655 s = splnet(); 656 mii_tick(&sc->sc_mii); 657 splx(s); 658 659 timeout_add_sec(&sc->sc_tick_ch, 1); 660 } 661 662 int 663 cas_bitwait(struct cas_softc *sc, bus_space_handle_t h, int r, 664 u_int32_t clr, u_int32_t set) 665 { 666 int i; 667 u_int32_t reg; 668 669 for (i = TRIES; i--; DELAY(100)) { 670 reg = bus_space_read_4(sc->sc_memt, h, r); 671 if ((reg & clr) == 0 && (reg & set) == set) 672 return (1); 673 } 674 675 return (0); 676 } 677 678 void 679 cas_reset(struct cas_softc *sc) 680 { 681 bus_space_tag_t t = sc->sc_memt; 682 bus_space_handle_t h = sc->sc_memh; 683 int s; 684 685 s = splnet(); 686 DPRINTF(sc, ("%s: cas_reset\n", sc->sc_dev.dv_xname)); 687 cas_reset_rx(sc); 688 cas_reset_tx(sc); 689 690 /* Do a full reset */ 691 bus_space_write_4(t, h, CAS_RESET, 692 CAS_RESET_RX | CAS_RESET_TX | CAS_RESET_BLOCK_PCS); 693 if (!cas_bitwait(sc, h, CAS_RESET, CAS_RESET_RX | CAS_RESET_TX, 0)) 694 printf("%s: cannot reset device\n", sc->sc_dev.dv_xname); 695 splx(s); 696 } 697 698 699 /* 700 * cas_rxdrain: 701 * 702 * Drain the receive queue. 703 */ 704 void 705 cas_rxdrain(struct cas_softc *sc) 706 { 707 /* Nothing to do yet. */ 708 } 709 710 /* 711 * Reset the whole thing. 712 */ 713 void 714 cas_stop(struct ifnet *ifp, int disable) 715 { 716 struct cas_softc *sc = (struct cas_softc *)ifp->if_softc; 717 struct cas_sxd *sd; 718 u_int32_t i; 719 720 DPRINTF(sc, ("%s: cas_stop\n", sc->sc_dev.dv_xname)); 721 722 timeout_del(&sc->sc_tick_ch); 723 724 /* 725 * Mark the interface down and cancel the watchdog timer. 726 */ 727 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 728 ifp->if_timer = 0; 729 730 mii_down(&sc->sc_mii); 731 732 cas_reset_rx(sc); 733 cas_reset_tx(sc); 734 735 /* 736 * Release any queued transmit buffers. 737 */ 738 for (i = 0; i < CAS_NTXDESC; i++) { 739 sd = &sc->sc_txd[i]; 740 if (sd->sd_mbuf != NULL) { 741 bus_dmamap_sync(sc->sc_dmatag, sd->sd_map, 0, 742 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 743 bus_dmamap_unload(sc->sc_dmatag, sd->sd_map); 744 m_freem(sd->sd_mbuf); 745 sd->sd_mbuf = NULL; 746 } 747 } 748 sc->sc_tx_cnt = sc->sc_tx_prod = sc->sc_tx_cons = 0; 749 750 if (disable) 751 cas_rxdrain(sc); 752 } 753 754 755 /* 756 * Reset the receiver 757 */ 758 int 759 cas_reset_rx(struct cas_softc *sc) 760 { 761 bus_space_tag_t t = sc->sc_memt; 762 bus_space_handle_t h = sc->sc_memh; 763 764 /* 765 * Resetting while DMA is in progress can cause a bus hang, so we 766 * disable DMA first. 767 */ 768 cas_disable_rx(sc); 769 bus_space_write_4(t, h, CAS_RX_CONFIG, 0); 770 /* Wait till it finishes */ 771 if (!cas_bitwait(sc, h, CAS_RX_CONFIG, 1, 0)) 772 printf("%s: cannot disable rx dma\n", sc->sc_dev.dv_xname); 773 /* Wait 5ms extra. */ 774 delay(5000); 775 776 /* Finally, reset the ERX */ 777 bus_space_write_4(t, h, CAS_RESET, CAS_RESET_RX); 778 /* Wait till it finishes */ 779 if (!cas_bitwait(sc, h, CAS_RESET, CAS_RESET_RX, 0)) { 780 printf("%s: cannot reset receiver\n", sc->sc_dev.dv_xname); 781 return (1); 782 } 783 return (0); 784 } 785 786 787 /* 788 * Reset the transmitter 789 */ 790 int 791 cas_reset_tx(struct cas_softc *sc) 792 { 793 bus_space_tag_t t = sc->sc_memt; 794 bus_space_handle_t h = sc->sc_memh; 795 796 /* 797 * Resetting while DMA is in progress can cause a bus hang, so we 798 * disable DMA first. 799 */ 800 cas_disable_tx(sc); 801 bus_space_write_4(t, h, CAS_TX_CONFIG, 0); 802 /* Wait till it finishes */ 803 if (!cas_bitwait(sc, h, CAS_TX_CONFIG, 1, 0)) 804 printf("%s: cannot disable tx dma\n", sc->sc_dev.dv_xname); 805 /* Wait 5ms extra. */ 806 delay(5000); 807 808 /* Finally, reset the ETX */ 809 bus_space_write_4(t, h, CAS_RESET, CAS_RESET_TX); 810 /* Wait till it finishes */ 811 if (!cas_bitwait(sc, h, CAS_RESET, CAS_RESET_TX, 0)) { 812 printf("%s: cannot reset transmitter\n", 813 sc->sc_dev.dv_xname); 814 return (1); 815 } 816 return (0); 817 } 818 819 /* 820 * disable receiver. 821 */ 822 int 823 cas_disable_rx(struct cas_softc *sc) 824 { 825 bus_space_tag_t t = sc->sc_memt; 826 bus_space_handle_t h = sc->sc_memh; 827 u_int32_t cfg; 828 829 /* Flip the enable bit */ 830 cfg = bus_space_read_4(t, h, CAS_MAC_RX_CONFIG); 831 cfg &= ~CAS_MAC_RX_ENABLE; 832 bus_space_write_4(t, h, CAS_MAC_RX_CONFIG, cfg); 833 834 /* Wait for it to finish */ 835 return (cas_bitwait(sc, h, CAS_MAC_RX_CONFIG, CAS_MAC_RX_ENABLE, 0)); 836 } 837 838 /* 839 * disable transmitter. 840 */ 841 int 842 cas_disable_tx(struct cas_softc *sc) 843 { 844 bus_space_tag_t t = sc->sc_memt; 845 bus_space_handle_t h = sc->sc_memh; 846 u_int32_t cfg; 847 848 /* Flip the enable bit */ 849 cfg = bus_space_read_4(t, h, CAS_MAC_TX_CONFIG); 850 cfg &= ~CAS_MAC_TX_ENABLE; 851 bus_space_write_4(t, h, CAS_MAC_TX_CONFIG, cfg); 852 853 /* Wait for it to finish */ 854 return (cas_bitwait(sc, h, CAS_MAC_TX_CONFIG, CAS_MAC_TX_ENABLE, 0)); 855 } 856 857 /* 858 * Initialize interface. 859 */ 860 int 861 cas_meminit(struct cas_softc *sc) 862 { 863 struct cas_rxsoft *rxs; 864 int i, error; 865 866 rxs = (void *)&error; 867 868 /* 869 * Initialize the transmit descriptor ring. 870 */ 871 for (i = 0; i < CAS_NTXDESC; i++) { 872 sc->sc_txdescs[i].cd_flags = 0; 873 sc->sc_txdescs[i].cd_addr = 0; 874 } 875 CAS_CDTXSYNC(sc, 0, CAS_NTXDESC, 876 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 877 878 /* 879 * Initialize the receive descriptor and receive job 880 * descriptor rings. 881 */ 882 for (i = 0; i < CAS_NRXDESC; i++) 883 CAS_INIT_RXDESC(sc, i, i); 884 sc->sc_rxdptr = 0; 885 sc->sc_rxptr = 0; 886 887 /* 888 * Initialize the receive completion ring. 889 */ 890 for (i = 0; i < CAS_NRXCOMP; i++) { 891 sc->sc_rxcomps[i].cc_word[0] = 0; 892 sc->sc_rxcomps[i].cc_word[1] = 0; 893 sc->sc_rxcomps[i].cc_word[2] = 0; 894 sc->sc_rxcomps[i].cc_word[3] = CAS_DMA_WRITE(CAS_RC3_OWN); 895 CAS_CDRXCSYNC(sc, i, 896 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 897 } 898 899 return (0); 900 } 901 902 int 903 cas_ringsize(int sz) 904 { 905 switch (sz) { 906 case 32: 907 return CAS_RING_SZ_32; 908 case 64: 909 return CAS_RING_SZ_64; 910 case 128: 911 return CAS_RING_SZ_128; 912 case 256: 913 return CAS_RING_SZ_256; 914 case 512: 915 return CAS_RING_SZ_512; 916 case 1024: 917 return CAS_RING_SZ_1024; 918 case 2048: 919 return CAS_RING_SZ_2048; 920 case 4096: 921 return CAS_RING_SZ_4096; 922 case 8192: 923 return CAS_RING_SZ_8192; 924 default: 925 printf("cas: invalid Receive Descriptor ring size %d\n", sz); 926 return CAS_RING_SZ_32; 927 } 928 } 929 930 int 931 cas_cringsize(int sz) 932 { 933 int i; 934 935 for (i = 0; i < 9; i++) 936 if (sz == (128 << i)) 937 return i; 938 939 printf("cas: invalid completion ring size %d\n", sz); 940 return 128; 941 } 942 943 /* 944 * Initialization of interface; set up initialization block 945 * and transmit/receive descriptor rings. 946 */ 947 int 948 cas_init(struct ifnet *ifp) 949 { 950 struct cas_softc *sc = (struct cas_softc *)ifp->if_softc; 951 bus_space_tag_t t = sc->sc_memt; 952 bus_space_handle_t h = sc->sc_memh; 953 int s; 954 u_int max_frame_size; 955 u_int32_t v; 956 957 s = splnet(); 958 959 DPRINTF(sc, ("%s: cas_init: calling stop\n", sc->sc_dev.dv_xname)); 960 /* 961 * Initialization sequence. The numbered steps below correspond 962 * to the sequence outlined in section 6.3.5.1 in the Ethernet 963 * Channel Engine manual (part of the PCIO manual). 964 * See also the STP2002-STQ document from Sun Microsystems. 965 */ 966 967 /* step 1 & 2. Reset the Ethernet Channel */ 968 cas_stop(ifp, 0); 969 cas_reset(sc); 970 DPRINTF(sc, ("%s: cas_init: restarting\n", sc->sc_dev.dv_xname)); 971 972 /* Re-initialize the MIF */ 973 cas_mifinit(sc); 974 975 /* step 3. Setup data structures in host memory */ 976 cas_meminit(sc); 977 978 /* step 4. TX MAC registers & counters */ 979 cas_init_regs(sc); 980 max_frame_size = ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN; 981 v = (max_frame_size) | (0x2000 << 16) /* Burst size */; 982 bus_space_write_4(t, h, CAS_MAC_MAC_MAX_FRAME, v); 983 984 /* step 5. RX MAC registers & counters */ 985 cas_setladrf(sc); 986 987 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 988 KASSERT((CAS_CDTXADDR(sc, 0) & 0x1fff) == 0); 989 bus_space_write_4(t, h, CAS_TX_RING_PTR_HI, 990 (((uint64_t)CAS_CDTXADDR(sc,0)) >> 32)); 991 bus_space_write_4(t, h, CAS_TX_RING_PTR_LO, CAS_CDTXADDR(sc, 0)); 992 993 KASSERT((CAS_CDRXADDR(sc, 0) & 0x1fff) == 0); 994 bus_space_write_4(t, h, CAS_RX_DRING_PTR_HI, 995 (((uint64_t)CAS_CDRXADDR(sc,0)) >> 32)); 996 bus_space_write_4(t, h, CAS_RX_DRING_PTR_LO, CAS_CDRXADDR(sc, 0)); 997 998 KASSERT((CAS_CDRXCADDR(sc, 0) & 0x1fff) == 0); 999 bus_space_write_4(t, h, CAS_RX_CRING_PTR_HI, 1000 (((uint64_t)CAS_CDRXCADDR(sc,0)) >> 32)); 1001 bus_space_write_4(t, h, CAS_RX_CRING_PTR_LO, CAS_CDRXCADDR(sc, 0)); 1002 1003 if (CAS_PLUS(sc)) { 1004 KASSERT((CAS_CDRXADDR2(sc, 0) & 0x1fff) == 0); 1005 bus_space_write_4(t, h, CAS_RX_DRING_PTR_HI2, 1006 (((uint64_t)CAS_CDRXADDR2(sc,0)) >> 32)); 1007 bus_space_write_4(t, h, CAS_RX_DRING_PTR_LO2, 1008 CAS_CDRXADDR2(sc, 0)); 1009 } 1010 1011 /* step 8. Global Configuration & Interrupt Mask */ 1012 bus_space_write_4(t, h, CAS_INTMASK, 1013 ~(CAS_INTR_TX_INTME|CAS_INTR_TX_EMPTY| 1014 CAS_INTR_TX_TAG_ERR| 1015 CAS_INTR_RX_DONE|CAS_INTR_RX_NOBUF| 1016 CAS_INTR_RX_TAG_ERR| 1017 CAS_INTR_RX_COMP_FULL|CAS_INTR_PCS| 1018 CAS_INTR_MAC_CONTROL|CAS_INTR_MIF| 1019 CAS_INTR_BERR)); 1020 bus_space_write_4(t, h, CAS_MAC_RX_MASK, 1021 CAS_MAC_RX_DONE|CAS_MAC_RX_FRAME_CNT); 1022 bus_space_write_4(t, h, CAS_MAC_TX_MASK, CAS_MAC_TX_XMIT_DONE); 1023 bus_space_write_4(t, h, CAS_MAC_CONTROL_MASK, 0); /* XXXX */ 1024 1025 /* step 9. ETX Configuration: use mostly default values */ 1026 1027 /* Enable DMA */ 1028 v = cas_ringsize(CAS_NTXDESC /*XXX*/) << 10; 1029 bus_space_write_4(t, h, CAS_TX_CONFIG, 1030 v|CAS_TX_CONFIG_TXDMA_EN|(1<<24)|(1<<29)); 1031 bus_space_write_4(t, h, CAS_TX_KICK, 0); 1032 1033 /* step 10. ERX Configuration */ 1034 1035 /* Encode Receive Descriptor ring size */ 1036 v = cas_ringsize(CAS_NRXDESC) << CAS_RX_CONFIG_RXDRNG_SZ_SHIFT; 1037 if (CAS_PLUS(sc)) 1038 v |= cas_ringsize(32) << CAS_RX_CONFIG_RXDRNG2_SZ_SHIFT; 1039 1040 /* Encode Receive Completion ring size */ 1041 v |= cas_cringsize(CAS_NRXCOMP) << CAS_RX_CONFIG_RXCRNG_SZ_SHIFT; 1042 1043 /* Enable DMA */ 1044 bus_space_write_4(t, h, CAS_RX_CONFIG, 1045 v|(2<<CAS_RX_CONFIG_FBOFF_SHFT)|CAS_RX_CONFIG_RXDMA_EN); 1046 1047 /* 1048 * The following value is for an OFF Threshold of about 3/4 full 1049 * and an ON Threshold of 1/4 full. 1050 */ 1051 bus_space_write_4(t, h, CAS_RX_PAUSE_THRESH, 1052 (3 * sc->sc_rxfifosize / 256) | 1053 ( (sc->sc_rxfifosize / 256) << 12)); 1054 bus_space_write_4(t, h, CAS_RX_BLANKING, (6<<12)|6); 1055 1056 /* step 11. Configure Media */ 1057 mii_mediachg(&sc->sc_mii); 1058 1059 /* step 12. RX_MAC Configuration Register */ 1060 v = bus_space_read_4(t, h, CAS_MAC_RX_CONFIG); 1061 v |= CAS_MAC_RX_ENABLE | CAS_MAC_RX_STRIP_CRC; 1062 bus_space_write_4(t, h, CAS_MAC_RX_CONFIG, v); 1063 1064 /* step 14. Issue Transmit Pending command */ 1065 1066 /* step 15. Give the receiver a swift kick */ 1067 bus_space_write_4(t, h, CAS_RX_KICK, CAS_NRXDESC-4); 1068 if (CAS_PLUS(sc)) 1069 bus_space_write_4(t, h, CAS_RX_KICK2, 4); 1070 1071 /* Start the one second timer. */ 1072 timeout_add_sec(&sc->sc_tick_ch, 1); 1073 1074 ifp->if_flags |= IFF_RUNNING; 1075 ifp->if_flags &= ~IFF_OACTIVE; 1076 ifp->if_timer = 0; 1077 splx(s); 1078 1079 return (0); 1080 } 1081 1082 void 1083 cas_init_regs(struct cas_softc *sc) 1084 { 1085 bus_space_tag_t t = sc->sc_memt; 1086 bus_space_handle_t h = sc->sc_memh; 1087 u_int32_t v, r; 1088 1089 /* These regs are not cleared on reset */ 1090 sc->sc_inited = 0; 1091 if (!sc->sc_inited) { 1092 1093 /* Wooo. Magic values. */ 1094 bus_space_write_4(t, h, CAS_MAC_IPG0, 0); 1095 bus_space_write_4(t, h, CAS_MAC_IPG1, 8); 1096 bus_space_write_4(t, h, CAS_MAC_IPG2, 4); 1097 1098 bus_space_write_4(t, h, CAS_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 1099 /* Max frame and max burst size */ 1100 v = ETHER_MAX_LEN | (0x2000 << 16) /* Burst size */; 1101 bus_space_write_4(t, h, CAS_MAC_MAC_MAX_FRAME, v); 1102 1103 bus_space_write_4(t, h, CAS_MAC_PREAMBLE_LEN, 0x7); 1104 bus_space_write_4(t, h, CAS_MAC_JAM_SIZE, 0x4); 1105 bus_space_write_4(t, h, CAS_MAC_ATTEMPT_LIMIT, 0x10); 1106 /* Dunno.... */ 1107 bus_space_write_4(t, h, CAS_MAC_CONTROL_TYPE, 0x8088); 1108 bus_space_write_4(t, h, CAS_MAC_RANDOM_SEED, 1109 ((sc->sc_arpcom.ac_enaddr[5]<<8)|sc->sc_arpcom.ac_enaddr[4])&0x3ff); 1110 1111 /* Secondary MAC addresses set to 0:0:0:0:0:0 */ 1112 for (r = CAS_MAC_ADDR3; r < CAS_MAC_ADDR42; r += 4) 1113 bus_space_write_4(t, h, r, 0); 1114 1115 /* MAC control addr set to 0:1:c2:0:1:80 */ 1116 bus_space_write_4(t, h, CAS_MAC_ADDR42, 0x0001); 1117 bus_space_write_4(t, h, CAS_MAC_ADDR43, 0xc200); 1118 bus_space_write_4(t, h, CAS_MAC_ADDR44, 0x0180); 1119 1120 /* MAC filter addr set to 0:0:0:0:0:0 */ 1121 bus_space_write_4(t, h, CAS_MAC_ADDR_FILTER0, 0); 1122 bus_space_write_4(t, h, CAS_MAC_ADDR_FILTER1, 0); 1123 bus_space_write_4(t, h, CAS_MAC_ADDR_FILTER2, 0); 1124 1125 bus_space_write_4(t, h, CAS_MAC_ADR_FLT_MASK1_2, 0); 1126 bus_space_write_4(t, h, CAS_MAC_ADR_FLT_MASK0, 0); 1127 1128 /* Hash table initialized to 0 */ 1129 for (r = CAS_MAC_HASH0; r <= CAS_MAC_HASH15; r += 4) 1130 bus_space_write_4(t, h, r, 0); 1131 1132 sc->sc_inited = 1; 1133 } 1134 1135 /* Counters need to be zeroed */ 1136 bus_space_write_4(t, h, CAS_MAC_NORM_COLL_CNT, 0); 1137 bus_space_write_4(t, h, CAS_MAC_FIRST_COLL_CNT, 0); 1138 bus_space_write_4(t, h, CAS_MAC_EXCESS_COLL_CNT, 0); 1139 bus_space_write_4(t, h, CAS_MAC_LATE_COLL_CNT, 0); 1140 bus_space_write_4(t, h, CAS_MAC_DEFER_TMR_CNT, 0); 1141 bus_space_write_4(t, h, CAS_MAC_PEAK_ATTEMPTS, 0); 1142 bus_space_write_4(t, h, CAS_MAC_RX_FRAME_COUNT, 0); 1143 bus_space_write_4(t, h, CAS_MAC_RX_LEN_ERR_CNT, 0); 1144 bus_space_write_4(t, h, CAS_MAC_RX_ALIGN_ERR, 0); 1145 bus_space_write_4(t, h, CAS_MAC_RX_CRC_ERR_CNT, 0); 1146 bus_space_write_4(t, h, CAS_MAC_RX_CODE_VIOL, 0); 1147 1148 /* Un-pause stuff */ 1149 bus_space_write_4(t, h, CAS_MAC_SEND_PAUSE_CMD, 0); 1150 1151 /* 1152 * Set the station address. 1153 */ 1154 bus_space_write_4(t, h, CAS_MAC_ADDR0, 1155 (sc->sc_arpcom.ac_enaddr[4]<<8) | sc->sc_arpcom.ac_enaddr[5]); 1156 bus_space_write_4(t, h, CAS_MAC_ADDR1, 1157 (sc->sc_arpcom.ac_enaddr[2]<<8) | sc->sc_arpcom.ac_enaddr[3]); 1158 bus_space_write_4(t, h, CAS_MAC_ADDR2, 1159 (sc->sc_arpcom.ac_enaddr[0]<<8) | sc->sc_arpcom.ac_enaddr[1]); 1160 } 1161 1162 /* 1163 * Receive interrupt. 1164 */ 1165 int 1166 cas_rint(struct cas_softc *sc) 1167 { 1168 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1169 bus_space_tag_t t = sc->sc_memt; 1170 bus_space_handle_t h = sc->sc_memh; 1171 struct cas_rxsoft *rxs; 1172 struct mbuf *m; 1173 u_int64_t word[4]; 1174 int len, off, idx; 1175 int i, skip; 1176 caddr_t cp; 1177 1178 for (i = sc->sc_rxptr;; i = CAS_NEXTRX(i + skip)) { 1179 CAS_CDRXCSYNC(sc, i, 1180 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1181 1182 word[0] = CAS_DMA_READ(sc->sc_rxcomps[i].cc_word[0]); 1183 word[1] = CAS_DMA_READ(sc->sc_rxcomps[i].cc_word[1]); 1184 word[2] = CAS_DMA_READ(sc->sc_rxcomps[i].cc_word[2]); 1185 word[3] = CAS_DMA_READ(sc->sc_rxcomps[i].cc_word[3]); 1186 1187 /* Stop if the hardware still owns the descriptor. */ 1188 if ((word[0] & CAS_RC0_TYPE) == 0 || word[3] & CAS_RC3_OWN) 1189 break; 1190 1191 len = CAS_RC1_HDR_LEN(word[1]); 1192 if (len > 0) { 1193 off = CAS_RC1_HDR_OFF(word[1]); 1194 idx = CAS_RC1_HDR_IDX(word[1]); 1195 rxs = &sc->sc_rxsoft[idx]; 1196 1197 DPRINTF(sc, ("hdr at idx %d, off %d, len %d\n", 1198 idx, off, len)); 1199 1200 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1201 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1202 1203 cp = rxs->rxs_kva + off * 256 + ETHER_ALIGN; 1204 m = m_devget(cp, len, ETHER_ALIGN, ifp, NULL); 1205 1206 if (word[0] & CAS_RC0_RELEASE_HDR) 1207 cas_add_rxbuf(sc, idx); 1208 1209 if (m != NULL) { 1210 1211 #if NBPFILTER > 0 1212 /* 1213 * Pass this up to any BPF listeners, but only 1214 * pass it up the stack if its for us. 1215 */ 1216 if (ifp->if_bpf) 1217 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_IN); 1218 #endif /* NBPFILTER > 0 */ 1219 1220 ifp->if_ipackets++; 1221 ether_input_mbuf(ifp, m); 1222 } else 1223 ifp->if_ierrors++; 1224 } 1225 1226 len = CAS_RC0_DATA_LEN(word[0]); 1227 if (len > 0) { 1228 off = CAS_RC0_DATA_OFF(word[0]); 1229 idx = CAS_RC0_DATA_IDX(word[0]); 1230 rxs = &sc->sc_rxsoft[idx]; 1231 1232 DPRINTF(sc, ("data at idx %d, off %d, len %d\n", 1233 idx, off, len)); 1234 1235 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1236 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1237 1238 /* XXX We should not be copying the packet here. */ 1239 cp = rxs->rxs_kva + off + ETHER_ALIGN; 1240 m = m_devget(cp, len, ETHER_ALIGN, ifp, NULL); 1241 1242 if (word[0] & CAS_RC0_RELEASE_DATA) 1243 cas_add_rxbuf(sc, idx); 1244 1245 if (m != NULL) { 1246 #if NBPFILTER > 0 1247 /* 1248 * Pass this up to any BPF listeners, but only 1249 * pass it up the stack if its for us. 1250 */ 1251 if (ifp->if_bpf) 1252 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_IN); 1253 #endif /* NBPFILTER > 0 */ 1254 1255 ifp->if_ipackets++; 1256 ether_input_mbuf(ifp, m); 1257 } else 1258 ifp->if_ierrors++; 1259 } 1260 1261 if (word[0] & CAS_RC0_SPLIT) 1262 printf("split packet\n"); 1263 1264 skip = CAS_RC0_SKIP(word[0]); 1265 } 1266 1267 while (sc->sc_rxptr != i) { 1268 sc->sc_rxcomps[sc->sc_rxptr].cc_word[0] = 0; 1269 sc->sc_rxcomps[sc->sc_rxptr].cc_word[1] = 0; 1270 sc->sc_rxcomps[sc->sc_rxptr].cc_word[2] = 0; 1271 sc->sc_rxcomps[sc->sc_rxptr].cc_word[3] = 1272 CAS_DMA_WRITE(CAS_RC3_OWN); 1273 CAS_CDRXCSYNC(sc, sc->sc_rxptr, 1274 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1275 1276 sc->sc_rxptr = CAS_NEXTRX(sc->sc_rxptr); 1277 } 1278 1279 bus_space_write_4(t, h, CAS_RX_COMP_TAIL, sc->sc_rxptr); 1280 1281 DPRINTF(sc, ("cas_rint: done sc->rxptr %d, complete %d\n", 1282 sc->sc_rxptr, bus_space_read_4(t, h, CAS_RX_COMPLETION))); 1283 1284 return (1); 1285 } 1286 1287 /* 1288 * cas_add_rxbuf: 1289 * 1290 * Add a receive buffer to the indicated descriptor. 1291 */ 1292 int 1293 cas_add_rxbuf(struct cas_softc *sc, int idx) 1294 { 1295 bus_space_tag_t t = sc->sc_memt; 1296 bus_space_handle_t h = sc->sc_memh; 1297 1298 CAS_INIT_RXDESC(sc, sc->sc_rxdptr, idx); 1299 1300 if ((sc->sc_rxdptr % 4) == 0) 1301 bus_space_write_4(t, h, CAS_RX_KICK, sc->sc_rxdptr); 1302 1303 if (++sc->sc_rxdptr == CAS_NRXDESC) 1304 sc->sc_rxdptr = 0; 1305 1306 return (0); 1307 } 1308 1309 int 1310 cas_eint(struct cas_softc *sc, u_int status) 1311 { 1312 if ((status & CAS_INTR_MIF) != 0) { 1313 #ifdef CAS_DEBUG 1314 printf("%s: link status changed\n", sc->sc_dev.dv_xname); 1315 #endif 1316 return (1); 1317 } 1318 1319 printf("%s: status=%b\n", sc->sc_dev.dv_xname, status, CAS_INTR_BITS); 1320 return (1); 1321 } 1322 1323 int 1324 cas_pint(struct cas_softc *sc) 1325 { 1326 bus_space_tag_t t = sc->sc_memt; 1327 bus_space_handle_t seb = sc->sc_memh; 1328 u_int32_t status; 1329 1330 status = bus_space_read_4(t, seb, CAS_MII_INTERRUP_STATUS); 1331 status |= bus_space_read_4(t, seb, CAS_MII_INTERRUP_STATUS); 1332 #ifdef CAS_DEBUG 1333 if (status) 1334 printf("%s: link status changed\n", sc->sc_dev.dv_xname); 1335 #endif 1336 return (1); 1337 } 1338 1339 int 1340 cas_intr(void *v) 1341 { 1342 struct cas_softc *sc = (struct cas_softc *)v; 1343 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1344 bus_space_tag_t t = sc->sc_memt; 1345 bus_space_handle_t seb = sc->sc_memh; 1346 u_int32_t status; 1347 int r = 0; 1348 1349 status = bus_space_read_4(t, seb, CAS_STATUS); 1350 DPRINTF(sc, ("%s: cas_intr: cplt %xstatus %b\n", 1351 sc->sc_dev.dv_xname, (status>>19), status, CAS_INTR_BITS)); 1352 1353 if ((status & CAS_INTR_PCS) != 0) 1354 r |= cas_pint(sc); 1355 1356 if ((status & (CAS_INTR_TX_TAG_ERR | CAS_INTR_RX_TAG_ERR | 1357 CAS_INTR_RX_COMP_FULL | CAS_INTR_BERR)) != 0) 1358 r |= cas_eint(sc, status); 1359 1360 if ((status & (CAS_INTR_TX_EMPTY | CAS_INTR_TX_INTME)) != 0) 1361 r |= cas_tint(sc, status); 1362 1363 if ((status & (CAS_INTR_RX_DONE | CAS_INTR_RX_NOBUF)) != 0) 1364 r |= cas_rint(sc); 1365 1366 /* We should eventually do more than just print out error stats. */ 1367 if (status & CAS_INTR_TX_MAC) { 1368 int txstat = bus_space_read_4(t, seb, CAS_MAC_TX_STATUS); 1369 #ifdef CAS_DEBUG 1370 if (txstat & ~CAS_MAC_TX_XMIT_DONE) 1371 printf("%s: MAC tx fault, status %x\n", 1372 sc->sc_dev.dv_xname, txstat); 1373 #endif 1374 if (txstat & (CAS_MAC_TX_UNDERRUN | CAS_MAC_TX_PKT_TOO_LONG)) 1375 cas_init(ifp); 1376 } 1377 if (status & CAS_INTR_RX_MAC) { 1378 int rxstat = bus_space_read_4(t, seb, CAS_MAC_RX_STATUS); 1379 #ifdef CAS_DEBUG 1380 if (rxstat & ~CAS_MAC_RX_DONE) 1381 printf("%s: MAC rx fault, status %x\n", 1382 sc->sc_dev.dv_xname, rxstat); 1383 #endif 1384 /* 1385 * On some chip revisions CAS_MAC_RX_OVERFLOW happen often 1386 * due to a silicon bug so handle them silently. 1387 */ 1388 if (rxstat & CAS_MAC_RX_OVERFLOW) { 1389 ifp->if_ierrors++; 1390 cas_init(ifp); 1391 } 1392 #ifdef CAS_DEBUG 1393 else if (rxstat & ~(CAS_MAC_RX_DONE | CAS_MAC_RX_FRAME_CNT)) 1394 printf("%s: MAC rx fault, status %x\n", 1395 sc->sc_dev.dv_xname, rxstat); 1396 #endif 1397 } 1398 return (r); 1399 } 1400 1401 1402 void 1403 cas_watchdog(struct ifnet *ifp) 1404 { 1405 struct cas_softc *sc = ifp->if_softc; 1406 1407 DPRINTF(sc, ("cas_watchdog: CAS_RX_CONFIG %x CAS_MAC_RX_STATUS %x " 1408 "CAS_MAC_RX_CONFIG %x\n", 1409 bus_space_read_4(sc->sc_memt, sc->sc_memh, CAS_RX_CONFIG), 1410 bus_space_read_4(sc->sc_memt, sc->sc_memh, CAS_MAC_RX_STATUS), 1411 bus_space_read_4(sc->sc_memt, sc->sc_memh, CAS_MAC_RX_CONFIG))); 1412 1413 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1414 ++ifp->if_oerrors; 1415 1416 /* Try to get more packets going. */ 1417 cas_init(ifp); 1418 } 1419 1420 /* 1421 * Initialize the MII Management Interface 1422 */ 1423 void 1424 cas_mifinit(struct cas_softc *sc) 1425 { 1426 bus_space_tag_t t = sc->sc_memt; 1427 bus_space_handle_t mif = sc->sc_memh; 1428 1429 /* Configure the MIF in frame mode */ 1430 sc->sc_mif_config = bus_space_read_4(t, mif, CAS_MIF_CONFIG); 1431 sc->sc_mif_config &= ~CAS_MIF_CONFIG_BB_ENA; 1432 bus_space_write_4(t, mif, CAS_MIF_CONFIG, sc->sc_mif_config); 1433 } 1434 1435 /* 1436 * MII interface 1437 * 1438 * The Cassini MII interface supports at least three different operating modes: 1439 * 1440 * Bitbang mode is implemented using data, clock and output enable registers. 1441 * 1442 * Frame mode is implemented by loading a complete frame into the frame 1443 * register and polling the valid bit for completion. 1444 * 1445 * Polling mode uses the frame register but completion is indicated by 1446 * an interrupt. 1447 * 1448 */ 1449 int 1450 cas_mii_readreg(struct device *self, int phy, int reg) 1451 { 1452 struct cas_softc *sc = (void *)self; 1453 bus_space_tag_t t = sc->sc_memt; 1454 bus_space_handle_t mif = sc->sc_memh; 1455 int n; 1456 u_int32_t v; 1457 1458 #ifdef CAS_DEBUG 1459 if (sc->sc_debug) 1460 printf("cas_mii_readreg: phy %d reg %d\n", phy, reg); 1461 #endif 1462 1463 /* Construct the frame command */ 1464 v = (reg << CAS_MIF_REG_SHIFT) | (phy << CAS_MIF_PHY_SHIFT) | 1465 CAS_MIF_FRAME_READ; 1466 1467 bus_space_write_4(t, mif, CAS_MIF_FRAME, v); 1468 for (n = 0; n < 100; n++) { 1469 DELAY(1); 1470 v = bus_space_read_4(t, mif, CAS_MIF_FRAME); 1471 if (v & CAS_MIF_FRAME_TA0) 1472 return (v & CAS_MIF_FRAME_DATA); 1473 } 1474 1475 printf("%s: mii_read timeout\n", sc->sc_dev.dv_xname); 1476 return (0); 1477 } 1478 1479 void 1480 cas_mii_writereg(struct device *self, int phy, int reg, int val) 1481 { 1482 struct cas_softc *sc = (void *)self; 1483 bus_space_tag_t t = sc->sc_memt; 1484 bus_space_handle_t mif = sc->sc_memh; 1485 int n; 1486 u_int32_t v; 1487 1488 #ifdef CAS_DEBUG 1489 if (sc->sc_debug) 1490 printf("cas_mii_writereg: phy %d reg %d val %x\n", 1491 phy, reg, val); 1492 #endif 1493 1494 /* Construct the frame command */ 1495 v = CAS_MIF_FRAME_WRITE | 1496 (phy << CAS_MIF_PHY_SHIFT) | 1497 (reg << CAS_MIF_REG_SHIFT) | 1498 (val & CAS_MIF_FRAME_DATA); 1499 1500 bus_space_write_4(t, mif, CAS_MIF_FRAME, v); 1501 for (n = 0; n < 100; n++) { 1502 DELAY(1); 1503 v = bus_space_read_4(t, mif, CAS_MIF_FRAME); 1504 if (v & CAS_MIF_FRAME_TA0) 1505 return; 1506 } 1507 1508 printf("%s: mii_write timeout\n", sc->sc_dev.dv_xname); 1509 } 1510 1511 void 1512 cas_mii_statchg(struct device *dev) 1513 { 1514 struct cas_softc *sc = (void *)dev; 1515 #ifdef CAS_DEBUG 1516 int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1517 #endif 1518 bus_space_tag_t t = sc->sc_memt; 1519 bus_space_handle_t mac = sc->sc_memh; 1520 u_int32_t v; 1521 1522 #ifdef CAS_DEBUG 1523 if (sc->sc_debug) 1524 printf("cas_mii_statchg: status change: phy = %d\n", 1525 sc->sc_phys[instance]); 1526 #endif 1527 1528 /* Set tx full duplex options */ 1529 bus_space_write_4(t, mac, CAS_MAC_TX_CONFIG, 0); 1530 delay(10000); /* reg must be cleared and delay before changing. */ 1531 v = CAS_MAC_TX_ENA_IPG0|CAS_MAC_TX_NGU|CAS_MAC_TX_NGU_LIMIT| 1532 CAS_MAC_TX_ENABLE; 1533 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) { 1534 v |= CAS_MAC_TX_IGN_CARRIER|CAS_MAC_TX_IGN_COLLIS; 1535 } 1536 bus_space_write_4(t, mac, CAS_MAC_TX_CONFIG, v); 1537 1538 /* XIF Configuration */ 1539 v = CAS_MAC_XIF_TX_MII_ENA; 1540 v |= CAS_MAC_XIF_LINK_LED; 1541 1542 /* MII needs echo disable if half duplex. */ 1543 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1544 /* turn on full duplex LED */ 1545 v |= CAS_MAC_XIF_FDPLX_LED; 1546 else 1547 /* half duplex -- disable echo */ 1548 v |= CAS_MAC_XIF_ECHO_DISABL; 1549 1550 switch (IFM_SUBTYPE(sc->sc_mii.mii_media_active)) { 1551 case IFM_1000_T: /* Gigabit using GMII interface */ 1552 case IFM_1000_SX: 1553 v |= CAS_MAC_XIF_GMII_MODE; 1554 break; 1555 default: 1556 v &= ~CAS_MAC_XIF_GMII_MODE; 1557 } 1558 bus_space_write_4(t, mac, CAS_MAC_XIF_CONFIG, v); 1559 } 1560 1561 int 1562 cas_pcs_readreg(struct device *self, int phy, int reg) 1563 { 1564 struct cas_softc *sc = (void *)self; 1565 bus_space_tag_t t = sc->sc_memt; 1566 bus_space_handle_t pcs = sc->sc_memh; 1567 1568 #ifdef CAS_DEBUG 1569 if (sc->sc_debug) 1570 printf("cas_pcs_readreg: phy %d reg %d\n", phy, reg); 1571 #endif 1572 1573 if (phy != CAS_PHYAD_EXTERNAL) 1574 return (0); 1575 1576 switch (reg) { 1577 case MII_BMCR: 1578 reg = CAS_MII_CONTROL; 1579 break; 1580 case MII_BMSR: 1581 reg = CAS_MII_STATUS; 1582 break; 1583 case MII_ANAR: 1584 reg = CAS_MII_ANAR; 1585 break; 1586 case MII_ANLPAR: 1587 reg = CAS_MII_ANLPAR; 1588 break; 1589 case MII_EXTSR: 1590 return (EXTSR_1000XFDX|EXTSR_1000XHDX); 1591 default: 1592 return (0); 1593 } 1594 1595 return bus_space_read_4(t, pcs, reg); 1596 } 1597 1598 void 1599 cas_pcs_writereg(struct device *self, int phy, int reg, int val) 1600 { 1601 struct cas_softc *sc = (void *)self; 1602 bus_space_tag_t t = sc->sc_memt; 1603 bus_space_handle_t pcs = sc->sc_memh; 1604 int reset = 0; 1605 1606 #ifdef CAS_DEBUG 1607 if (sc->sc_debug) 1608 printf("cas_pcs_writereg: phy %d reg %d val %x\n", 1609 phy, reg, val); 1610 #endif 1611 1612 if (phy != CAS_PHYAD_EXTERNAL) 1613 return; 1614 1615 if (reg == MII_ANAR) 1616 bus_space_write_4(t, pcs, CAS_MII_CONFIG, 0); 1617 1618 switch (reg) { 1619 case MII_BMCR: 1620 reset = (val & CAS_MII_CONTROL_RESET); 1621 reg = CAS_MII_CONTROL; 1622 break; 1623 case MII_BMSR: 1624 reg = CAS_MII_STATUS; 1625 break; 1626 case MII_ANAR: 1627 reg = CAS_MII_ANAR; 1628 break; 1629 case MII_ANLPAR: 1630 reg = CAS_MII_ANLPAR; 1631 break; 1632 default: 1633 return; 1634 } 1635 1636 bus_space_write_4(t, pcs, reg, val); 1637 1638 if (reset) 1639 cas_bitwait(sc, pcs, CAS_MII_CONTROL, CAS_MII_CONTROL_RESET, 0); 1640 1641 if (reg == CAS_MII_ANAR || reset) 1642 bus_space_write_4(t, pcs, CAS_MII_CONFIG, 1643 CAS_MII_CONFIG_ENABLE); 1644 } 1645 1646 int 1647 cas_mediachange(struct ifnet *ifp) 1648 { 1649 struct cas_softc *sc = ifp->if_softc; 1650 struct mii_data *mii = &sc->sc_mii; 1651 1652 if (mii->mii_instance) { 1653 struct mii_softc *miisc; 1654 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1655 mii_phy_reset(miisc); 1656 } 1657 1658 return (mii_mediachg(&sc->sc_mii)); 1659 } 1660 1661 void 1662 cas_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1663 { 1664 struct cas_softc *sc = ifp->if_softc; 1665 1666 mii_pollstat(&sc->sc_mii); 1667 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1668 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1669 } 1670 1671 /* 1672 * Process an ioctl request. 1673 */ 1674 int 1675 cas_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1676 { 1677 struct cas_softc *sc = ifp->if_softc; 1678 struct ifaddr *ifa = (struct ifaddr *)data; 1679 struct ifreq *ifr = (struct ifreq *)data; 1680 int s, error = 0; 1681 1682 s = splnet(); 1683 1684 switch (cmd) { 1685 case SIOCSIFADDR: 1686 ifp->if_flags |= IFF_UP; 1687 if ((ifp->if_flags & IFF_RUNNING) == 0) 1688 cas_init(ifp); 1689 #ifdef INET 1690 if (ifa->ifa_addr->sa_family == AF_INET) 1691 arp_ifinit(&sc->sc_arpcom, ifa); 1692 #endif 1693 break; 1694 1695 case SIOCSIFFLAGS: 1696 if (ifp->if_flags & IFF_UP) { 1697 if (ifp->if_flags & IFF_RUNNING) 1698 error = ENETRESET; 1699 else 1700 cas_init(ifp); 1701 } else { 1702 if (ifp->if_flags & IFF_RUNNING) 1703 cas_stop(ifp, 1); 1704 } 1705 #ifdef CAS_DEBUG 1706 sc->sc_debug = (ifp->if_flags & IFF_DEBUG) != 0 ? 1 : 0; 1707 #endif 1708 break; 1709 1710 case SIOCGIFMEDIA: 1711 case SIOCSIFMEDIA: 1712 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1713 break; 1714 1715 default: 1716 error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data); 1717 } 1718 1719 if (error == ENETRESET) { 1720 if (ifp->if_flags & IFF_RUNNING) 1721 cas_setladrf(sc); 1722 error = 0; 1723 } 1724 1725 splx(s); 1726 return (error); 1727 } 1728 1729 1730 void 1731 cas_shutdown(void *arg) 1732 { 1733 struct cas_softc *sc = (struct cas_softc *)arg; 1734 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1735 1736 cas_stop(ifp, 1); 1737 } 1738 1739 /* 1740 * Set up the logical address filter. 1741 */ 1742 void 1743 cas_setladrf(struct cas_softc *sc) 1744 { 1745 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1746 struct ether_multi *enm; 1747 struct ether_multistep step; 1748 struct arpcom *ac = &sc->sc_arpcom; 1749 bus_space_tag_t t = sc->sc_memt; 1750 bus_space_handle_t h = sc->sc_memh; 1751 u_int32_t crc, hash[16], v; 1752 int i; 1753 1754 /* Get current RX configuration */ 1755 v = bus_space_read_4(t, h, CAS_MAC_RX_CONFIG); 1756 1757 1758 /* 1759 * Turn off promiscuous mode, promiscuous group mode (all multicast), 1760 * and hash filter. Depending on the case, the right bit will be 1761 * enabled. 1762 */ 1763 v &= ~(CAS_MAC_RX_PROMISCUOUS|CAS_MAC_RX_HASH_FILTER| 1764 CAS_MAC_RX_PROMISC_GRP); 1765 1766 if ((ifp->if_flags & IFF_PROMISC) != 0) { 1767 /* Turn on promiscuous mode */ 1768 v |= CAS_MAC_RX_PROMISCUOUS; 1769 ifp->if_flags |= IFF_ALLMULTI; 1770 goto chipit; 1771 } 1772 1773 /* 1774 * Set up multicast address filter by passing all multicast addresses 1775 * through a crc generator, and then using the high order 8 bits as an 1776 * index into the 256 bit logical address filter. The high order 4 1777 * bits selects the word, while the other 4 bits select the bit within 1778 * the word (where bit 0 is the MSB). 1779 */ 1780 1781 /* Clear hash table */ 1782 for (i = 0; i < 16; i++) 1783 hash[i] = 0; 1784 1785 1786 ETHER_FIRST_MULTI(step, ac, enm); 1787 while (enm != NULL) { 1788 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1789 /* 1790 * We must listen to a range of multicast addresses. 1791 * For now, just accept all multicasts, rather than 1792 * trying to set only those filter bits needed to match 1793 * the range. (At this time, the only use of address 1794 * ranges is for IP multicast routing, for which the 1795 * range is big enough to require all bits set.) 1796 * XXX use the addr filter for this 1797 */ 1798 ifp->if_flags |= IFF_ALLMULTI; 1799 v |= CAS_MAC_RX_PROMISC_GRP; 1800 goto chipit; 1801 } 1802 1803 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1804 1805 /* Just want the 8 most significant bits. */ 1806 crc >>= 24; 1807 1808 /* Set the corresponding bit in the filter. */ 1809 hash[crc >> 4] |= 1 << (15 - (crc & 15)); 1810 1811 ETHER_NEXT_MULTI(step, enm); 1812 } 1813 1814 v |= CAS_MAC_RX_HASH_FILTER; 1815 ifp->if_flags &= ~IFF_ALLMULTI; 1816 1817 /* Now load the hash table into the chip (if we are using it) */ 1818 for (i = 0; i < 16; i++) { 1819 bus_space_write_4(t, h, 1820 CAS_MAC_HASH0 + i * (CAS_MAC_HASH1-CAS_MAC_HASH0), 1821 hash[i]); 1822 } 1823 1824 chipit: 1825 bus_space_write_4(t, h, CAS_MAC_RX_CONFIG, v); 1826 } 1827 1828 int 1829 cas_encap(struct cas_softc *sc, struct mbuf *mhead, u_int32_t *bixp) 1830 { 1831 u_int64_t flags; 1832 u_int32_t cur, frag, i; 1833 bus_dmamap_t map; 1834 1835 cur = frag = *bixp; 1836 map = sc->sc_txd[cur].sd_map; 1837 1838 if (bus_dmamap_load_mbuf(sc->sc_dmatag, map, mhead, 1839 BUS_DMA_NOWAIT) != 0) { 1840 return (ENOBUFS); 1841 } 1842 1843 if ((sc->sc_tx_cnt + map->dm_nsegs) > (CAS_NTXDESC - 2)) { 1844 bus_dmamap_unload(sc->sc_dmatag, map); 1845 return (ENOBUFS); 1846 } 1847 1848 bus_dmamap_sync(sc->sc_dmatag, map, 0, map->dm_mapsize, 1849 BUS_DMASYNC_PREWRITE); 1850 1851 for (i = 0; i < map->dm_nsegs; i++) { 1852 sc->sc_txdescs[frag].cd_addr = 1853 CAS_DMA_WRITE(map->dm_segs[i].ds_addr); 1854 flags = (map->dm_segs[i].ds_len & CAS_TD_BUFSIZE) | 1855 (i == 0 ? CAS_TD_START_OF_PACKET : 0) | 1856 ((i == (map->dm_nsegs - 1)) ? CAS_TD_END_OF_PACKET : 0); 1857 sc->sc_txdescs[frag].cd_flags = CAS_DMA_WRITE(flags); 1858 bus_dmamap_sync(sc->sc_dmatag, sc->sc_cddmamap, 1859 CAS_CDTXOFF(frag), sizeof(struct cas_desc), 1860 BUS_DMASYNC_PREWRITE); 1861 cur = frag; 1862 if (++frag == CAS_NTXDESC) 1863 frag = 0; 1864 } 1865 1866 sc->sc_tx_cnt += map->dm_nsegs; 1867 sc->sc_txd[*bixp].sd_map = sc->sc_txd[cur].sd_map; 1868 sc->sc_txd[cur].sd_map = map; 1869 sc->sc_txd[cur].sd_mbuf = mhead; 1870 1871 bus_space_write_4(sc->sc_memt, sc->sc_memh, CAS_TX_KICK, frag); 1872 1873 *bixp = frag; 1874 1875 /* sync descriptors */ 1876 1877 return (0); 1878 } 1879 1880 /* 1881 * Transmit interrupt. 1882 */ 1883 int 1884 cas_tint(struct cas_softc *sc, u_int32_t status) 1885 { 1886 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1887 struct cas_sxd *sd; 1888 u_int32_t cons, comp; 1889 1890 comp = bus_space_read_4(sc->sc_memt, sc->sc_memh, CAS_TX_COMPLETION); 1891 cons = sc->sc_tx_cons; 1892 while (cons != comp) { 1893 sd = &sc->sc_txd[cons]; 1894 if (sd->sd_mbuf != NULL) { 1895 bus_dmamap_sync(sc->sc_dmatag, sd->sd_map, 0, 1896 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1897 bus_dmamap_unload(sc->sc_dmatag, sd->sd_map); 1898 m_freem(sd->sd_mbuf); 1899 sd->sd_mbuf = NULL; 1900 ifp->if_opackets++; 1901 } 1902 sc->sc_tx_cnt--; 1903 if (++cons == CAS_NTXDESC) 1904 cons = 0; 1905 } 1906 sc->sc_tx_cons = cons; 1907 1908 if (sc->sc_tx_cnt < CAS_NTXDESC - 2) 1909 ifp->if_flags &= ~IFF_OACTIVE; 1910 if (sc->sc_tx_cnt == 0) 1911 ifp->if_timer = 0; 1912 1913 cas_start(ifp); 1914 1915 return (1); 1916 } 1917 1918 void 1919 cas_start(struct ifnet *ifp) 1920 { 1921 struct cas_softc *sc = ifp->if_softc; 1922 struct mbuf *m; 1923 u_int32_t bix; 1924 1925 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1926 return; 1927 1928 bix = sc->sc_tx_prod; 1929 while (sc->sc_txd[bix].sd_mbuf == NULL) { 1930 IFQ_POLL(&ifp->if_snd, m); 1931 if (m == NULL) 1932 break; 1933 1934 #if NBPFILTER > 0 1935 /* 1936 * If BPF is listening on this interface, let it see the 1937 * packet before we commit it to the wire. 1938 */ 1939 if (ifp->if_bpf) 1940 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT); 1941 #endif 1942 1943 /* 1944 * Encapsulate this packet and start it going... 1945 * or fail... 1946 */ 1947 if (cas_encap(sc, m, &bix)) { 1948 ifp->if_flags |= IFF_OACTIVE; 1949 break; 1950 } 1951 1952 IFQ_DEQUEUE(&ifp->if_snd, m); 1953 ifp->if_timer = 5; 1954 } 1955 1956 sc->sc_tx_prod = bix; 1957 } 1958