1 /* $OpenBSD: if_bwfm_pci.h,v 1.6 2021/02/26 12:28:46 patrick Exp $ */ 2 /* 3 * Copyright (c) 2010-2016 Broadcom Corporation 4 * Copyright (c) 2017 Patrick Wildt <patrick@blueri.se> 5 * 6 * Permission to use, copy, modify, and/or distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* Registers */ 20 #define BWFM_PCI_BAR0_WINDOW 0x80 21 #define BWFM_PCI_BAR0_REG_SIZE 0x1000 22 23 #define BWFM_PCI_ARMCR4REG_BANKIDX 0x40 24 #define BWFM_PCI_ARMCR4REG_BANKPDA 0x4C 25 26 #define BWFM_PCI_PCIE2REG_INTMASK 0x24 27 #define BWFM_PCI_PCIE2REG_MAILBOXINT 0x48 28 #define BWFM_PCI_PCIE2REG_MAILBOXMASK 0x4C 29 #define BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_FN0_0 0x0100 30 #define BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_FN0_1 0x0200 31 #define BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H0_DB0 0x10000 32 #define BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H0_DB1 0x20000 33 #define BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H1_DB0 0x40000 34 #define BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H1_DB1 0x80000 35 #define BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H2_DB0 0x100000 36 #define BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H2_DB1 0x200000 37 #define BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H3_DB0 0x400000 38 #define BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H3_DB1 0x800000 39 #define BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H_DB \ 40 (BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H0_DB0 | \ 41 BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H0_DB1 | \ 42 BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H1_DB0 | \ 43 BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H1_DB1 | \ 44 BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H2_DB0 | \ 45 BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H2_DB1 | \ 46 BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H3_DB0 | \ 47 BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H3_DB1) 48 #define BWFM_PCI_PCIE2REG_CONFIGADDR 0x120 49 #define BWFM_PCI_PCIE2REG_CONFIGDATA 0x124 50 #define BWFM_PCI_PCIE2REG_H2D_MAILBOX_0 0x140 51 #define BWFM_PCI_PCIE2REG_H2D_MAILBOX_1 0x144 52 53 #define BWFM_PCI_64_PCIE2REG_INTMASK 0xC14 54 #define BWFM_PCI_64_PCIE2REG_MAILBOXINT 0xC30 55 #define BWFM_PCI_64_PCIE2REG_MAILBOXMASK 0xC34 56 #define BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H0_DB0 1 57 #define BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H0_DB1 2 58 #define BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H1_DB0 4 59 #define BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H1_DB1 8 60 #define BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H2_DB0 0x10 61 #define BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H2_DB1 0x20 62 #define BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H3_DB0 0x40 63 #define BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H3_DB1 0x80 64 #define BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H4_DB0 0x100 65 #define BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H4_DB1 0x200 66 #define BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H5_DB0 0x400 67 #define BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H5_DB1 0x800 68 #define BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H6_DB0 0x1000 69 #define BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H6_DB1 0x2000 70 #define BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H7_DB0 0x4000 71 #define BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H7_DB1 0x8000 72 #define BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H_DB \ 73 (BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H0_DB0 | \ 74 BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H0_DB1 | \ 75 BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H1_DB0 | \ 76 BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H1_DB1 | \ 77 BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H2_DB0 | \ 78 BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H2_DB1 | \ 79 BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H3_DB0 | \ 80 BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H3_DB1 | \ 81 BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H4_DB0 | \ 82 BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H4_DB1 | \ 83 BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H5_DB0 | \ 84 BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H5_DB1 | \ 85 BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H6_DB0 | \ 86 BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H6_DB1 | \ 87 BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H7_DB0 | \ 88 BWFM_PCI_64_PCIE2REG_MAILBOXMASK_INT_D2H7_DB1) 89 #define BWFM_PCI_64_PCIE2REG_H2D_MAILBOX_0 0xA20 90 #define BWFM_PCI_64_PCIE2REG_H2D_MAILBOX_1 0xA24 91 92 #define BWFM_PCI_CFGREG_STATUS_CMD 0x004 93 #define BWFM_PCI_CFGREG_PM_CSR 0x04C 94 #define BWFM_PCI_CFGREG_MSI_CAP 0x058 95 #define BWFM_PCI_CFGREG_MSI_ADDR_L 0x05C 96 #define BWFM_PCI_CFGREG_MSI_ADDR_H 0x060 97 #define BWFM_PCI_CFGREG_MSI_DATA 0x064 98 #define BWFM_PCI_CFGREG_LINK_STATUS_CTRL 0x0BC 99 #define BWFM_PCI_CFGREG_LINK_STATUS_CTRL_ASPM_ENAB 0x3 100 #define BWFM_PCI_CFGREG_LINK_STATUS_CTRL2 0x0DC 101 #define BWFM_PCI_CFGREG_RBAR_CTRL 0x228 102 #define BWFM_PCI_CFGREG_PML1_SUB_CTRL1 0x248 103 #define BWFM_PCI_CFGREG_REG_BAR2_CONFIG 0x4E0 104 #define BWFM_PCI_CFGREG_REG_BAR3_CONFIG 0x4F4 105 106 #define BWFM_RAMSIZE 0x6c 107 #define BWFM_RAMSIZE_MAGIC 0x534d4152 /* SMAR */ 108 109 #define BWFM_SHARED_INFO 0x000 110 #define BWFM_SHARED_INFO_MIN_VERSION 5 111 #define BWFM_SHARED_INFO_MAX_VERSION 7 112 #define BWFM_SHARED_INFO_VERSION_MASK 0x00FF 113 #define BWFM_SHARED_INFO_DMA_INDEX 0x10000 114 #define BWFM_SHARED_INFO_DMA_2B_IDX 0x100000 115 #define BWFM_SHARED_INFO_HOSTRDY_DB1 0x10000000 116 #define BWFM_SHARED_CONSOLE_ADDR 0x14 117 #define BWFM_SHARED_MAX_RXBUFPOST 0x22 118 #define BWFM_SHARED_MAX_RXBUFPOST_DEFAULT 255 119 #define BWFM_SHARED_RX_DATAOFFSET 0x24 120 #define BWFM_SHARED_HTOD_MB_DATA_ADDR 0x28 121 #define BWFM_SHARED_DTOH_MB_DATA_ADDR 0x2c 122 #define BWFM_SHARED_RING_INFO_ADDR 0x30 123 #define BWFM_SHARED_DMA_SCRATCH_LEN 0x34 124 #define BWFM_SHARED_DMA_SCRATCH_ADDR_LOW 0x38 125 #define BWFM_SHARED_DMA_SCRATCH_ADDR_HIGH 0x3c 126 #define BWFM_SHARED_DMA_RINGUPD_LEN 0x40 127 #define BWFM_SHARED_DMA_RINGUPD_ADDR_LOW 0x44 128 #define BWFM_SHARED_DMA_RINGUPD_ADDR_HIGH 0x48 129 130 #define BWFM_RING_MAX_ITEM 0x04 131 #define BWFM_RING_LEN_ITEMS 0x06 132 #define BWFM_RING_MEM_BASE_ADDR_LOW 0x08 133 #define BWFM_RING_MEM_BASE_ADDR_HIGH 0x0c 134 #define BWFM_RING_MEM_SZ 16 135 136 #define BWFM_CONSOLE_BUFADDR 0x08 137 #define BWFM_CONSOLE_BUFSIZE 0x0c 138 #define BWFM_CONSOLE_WRITEIDX 0x10 139 140 struct bwfm_pci_ringinfo { 141 uint32_t ringmem; 142 uint32_t h2d_w_idx_ptr; 143 uint32_t h2d_r_idx_ptr; 144 uint32_t d2h_w_idx_ptr; 145 uint32_t d2h_r_idx_ptr; 146 uint32_t h2d_w_idx_hostaddr_low; 147 uint32_t h2d_w_idx_hostaddr_high; 148 uint32_t h2d_r_idx_hostaddr_low; 149 uint32_t h2d_r_idx_hostaddr_high; 150 uint32_t d2h_w_idx_hostaddr_low; 151 uint32_t d2h_w_idx_hostaddr_high; 152 uint32_t d2h_r_idx_hostaddr_low; 153 uint32_t d2h_r_idx_hostaddr_high; 154 uint16_t max_flowrings; 155 uint16_t max_submissionrings; 156 uint16_t max_completionrings; 157 }; 158 159 /* Msgbuf defines */ 160 #define MSGBUF_IOCTL_RESP_TIMEOUT 2000 /* msecs */ 161 #define MSGBUF_IOCTL_REQ_PKTID 0xFFFE 162 #define MSGBUF_MAX_PKT_SIZE 2048 163 #define MSGBUF_MAX_CTL_PKT_SIZE 8192 164 165 #define MSGBUF_TYPE_GEN_STATUS 0x1 166 #define MSGBUF_TYPE_RING_STATUS 0x2 167 #define MSGBUF_TYPE_FLOW_RING_CREATE 0x3 168 #define MSGBUF_TYPE_FLOW_RING_CREATE_CMPLT 0x4 169 #define MSGBUF_TYPE_FLOW_RING_DELETE 0x5 170 #define MSGBUF_TYPE_FLOW_RING_DELETE_CMPLT 0x6 171 #define MSGBUF_TYPE_FLOW_RING_FLUSH 0x7 172 #define MSGBUF_TYPE_FLOW_RING_FLUSH_CMPLT 0x8 173 #define MSGBUF_TYPE_IOCTLPTR_REQ 0x9 174 #define MSGBUF_TYPE_IOCTLPTR_REQ_ACK 0xA 175 #define MSGBUF_TYPE_IOCTLRESP_BUF_POST 0xB 176 #define MSGBUF_TYPE_IOCTL_CMPLT 0xC 177 #define MSGBUF_TYPE_EVENT_BUF_POST 0xD 178 #define MSGBUF_TYPE_WL_EVENT 0xE 179 #define MSGBUF_TYPE_TX_POST 0xF 180 #define MSGBUF_TYPE_TX_STATUS 0x10 181 #define MSGBUF_TYPE_RXBUF_POST 0x11 182 #define MSGBUF_TYPE_RX_CMPLT 0x12 183 #define MSGBUF_TYPE_LPBK_DMAXFER 0x13 184 #define MSGBUF_TYPE_LPBK_DMAXFER_CMPLT 0x14 185 186 struct msgbuf_common_hdr { 187 uint8_t msgtype; 188 uint8_t ifidx; 189 uint8_t flags; 190 uint8_t rsvd0; 191 uint32_t request_id; 192 }; 193 194 struct msgbuf_buf_addr { 195 uint32_t low_addr; 196 uint32_t high_addr; 197 }; 198 199 struct msgbuf_ioctl_req_hdr { 200 struct msgbuf_common_hdr msg; 201 uint32_t cmd; 202 uint16_t trans_id; 203 uint16_t input_buf_len; 204 uint16_t output_buf_len; 205 uint16_t rsvd0[3]; 206 struct msgbuf_buf_addr req_buf_addr; 207 uint32_t rsvd1[2]; 208 }; 209 210 struct msgbuf_tx_msghdr { 211 struct msgbuf_common_hdr msg; 212 uint8_t txhdr[ETHER_HDR_LEN]; 213 uint8_t flags; 214 #define BWFM_MSGBUF_PKT_FLAGS_FRAME_802_3 (1 << 0) 215 #define BWFM_MSGBUF_PKT_FLAGS_PRIO_SHIFT 5 216 uint8_t seg_cnt; 217 struct msgbuf_buf_addr metadata_buf_addr; 218 struct msgbuf_buf_addr data_buf_addr; 219 uint16_t metadata_buf_len; 220 uint16_t data_len; 221 uint32_t rsvd0; 222 }; 223 224 struct msgbuf_rx_bufpost { 225 struct msgbuf_common_hdr msg; 226 uint16_t metadata_buf_len; 227 uint16_t data_buf_len; 228 uint32_t rsvd0; 229 struct msgbuf_buf_addr metadata_buf_addr; 230 struct msgbuf_buf_addr data_buf_addr; 231 }; 232 233 struct msgbuf_rx_ioctl_resp_or_event { 234 struct msgbuf_common_hdr msg; 235 uint16_t host_buf_len; 236 uint16_t rsvd0[3]; 237 struct msgbuf_buf_addr host_buf_addr; 238 uint32_t rsvd1[4]; 239 }; 240 241 struct msgbuf_completion_hdr { 242 uint16_t status; 243 uint16_t flow_ring_id; 244 }; 245 246 struct msgbuf_rx_event { 247 struct msgbuf_common_hdr msg; 248 struct msgbuf_completion_hdr compl_hdr; 249 uint16_t event_data_len; 250 uint16_t seqnum; 251 uint16_t rsvd0[4]; 252 }; 253 254 struct msgbuf_ioctl_resp_hdr { 255 struct msgbuf_common_hdr msg; 256 struct msgbuf_completion_hdr compl_hdr; 257 uint16_t resp_len; 258 uint16_t trans_id; 259 uint32_t cmd; 260 uint32_t rsvd0; 261 }; 262 263 struct msgbuf_tx_status { 264 struct msgbuf_common_hdr msg; 265 struct msgbuf_completion_hdr compl_hdr; 266 uint16_t metadata_len; 267 uint16_t tx_status; 268 }; 269 270 struct msgbuf_rx_complete { 271 struct msgbuf_common_hdr msg; 272 struct msgbuf_completion_hdr compl_hdr; 273 uint16_t metadata_len; 274 uint16_t data_len; 275 uint16_t data_offset; 276 uint16_t flags; 277 uint32_t rx_status_0; 278 uint32_t rx_status_1; 279 uint32_t rsvd0; 280 }; 281 282 struct msgbuf_tx_flowring_create_req { 283 struct msgbuf_common_hdr msg; 284 uint8_t da[ETHER_ADDR_LEN]; 285 uint8_t sa[ETHER_ADDR_LEN]; 286 uint8_t tid; 287 uint8_t if_flags; 288 uint16_t flow_ring_id; 289 uint8_t tc; 290 uint8_t priority; 291 uint16_t int_vector; 292 uint16_t max_items; 293 uint16_t len_item; 294 struct msgbuf_buf_addr flow_ring_addr; 295 }; 296 297 struct msgbuf_tx_flowring_delete_req { 298 struct msgbuf_common_hdr msg; 299 uint16_t flow_ring_id; 300 uint16_t reason; 301 uint32_t rsvd0[7]; 302 }; 303 304 struct msgbuf_flowring_create_resp { 305 struct msgbuf_common_hdr msg; 306 struct msgbuf_completion_hdr compl_hdr; 307 uint32_t rsvd0[3]; 308 }; 309 310 struct msgbuf_flowring_delete_resp { 311 struct msgbuf_common_hdr msg; 312 struct msgbuf_completion_hdr compl_hdr; 313 uint32_t rsvd0[3]; 314 }; 315 316 struct msgbuf_flowring_flush_resp { 317 struct msgbuf_common_hdr msg; 318 struct msgbuf_completion_hdr compl_hdr; 319 uint32_t rsvd0[3]; 320 }; 321