1 /* $OpenBSD: if_bge.c,v 1.307 2011/06/22 16:44:27 tedu Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul@windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bge.c,v 1.25 2002/11/14 23:54:49 sam Exp $ 36 */ 37 38 /* 39 * Broadcom BCM57xx/BCM590x family ethernet driver for OpenBSD. 40 * 41 * Written by Bill Paul <wpaul@windriver.com> 42 * Senior Engineer, Wind River Systems 43 */ 44 45 /* 46 * The Broadcom BCM5700 is based on technology originally developed by 47 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 48 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 49 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 50 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, Jumbo 51 * frames, highly configurable RX filtering, and 16 RX and TX queues 52 * (which, along with RX filter rules, can be used for QOS applications). 53 * Other features, such as TCP segmentation, may be available as part 54 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 55 * firmware images can be stored in hardware and need not be compiled 56 * into the driver. 57 * 58 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 59 * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus. 60 * 61 * The BCM5701 is a single-chip solution incorporating both the BCM5700 62 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 63 * does not support external SSRAM. 64 * 65 * Broadcom also produces a variation of the BCM5700 under the "Altima" 66 * brand name, which is functionally similar but lacks PCI-X support. 67 * 68 * Without external SSRAM, you can only have at most 4 TX rings, 69 * and the use of the mini RX ring is disabled. This seems to imply 70 * that these features are simply not available on the BCM5701. As a 71 * result, this driver does not implement any support for the mini RX 72 * ring. 73 */ 74 75 #include "bpfilter.h" 76 #include "vlan.h" 77 78 #include <sys/param.h> 79 #include <sys/systm.h> 80 #include <sys/sockio.h> 81 #include <sys/mbuf.h> 82 #include <sys/malloc.h> 83 #include <sys/kernel.h> 84 #include <sys/device.h> 85 #include <sys/timeout.h> 86 #include <sys/socket.h> 87 88 #include <net/if.h> 89 #include <net/if_dl.h> 90 #include <net/if_media.h> 91 92 #ifdef INET 93 #include <netinet/in.h> 94 #include <netinet/in_systm.h> 95 #include <netinet/in_var.h> 96 #include <netinet/ip.h> 97 #include <netinet/if_ether.h> 98 #endif 99 100 #if NVLAN > 0 101 #include <net/if_types.h> 102 #include <net/if_vlan_var.h> 103 #endif 104 105 #if NBPFILTER > 0 106 #include <net/bpf.h> 107 #endif 108 109 #ifdef __sparc64__ 110 #include <sparc64/autoconf.h> 111 #include <dev/ofw/openfirm.h> 112 #endif 113 114 #include <dev/pci/pcireg.h> 115 #include <dev/pci/pcivar.h> 116 #include <dev/pci/pcidevs.h> 117 118 #include <dev/mii/mii.h> 119 #include <dev/mii/miivar.h> 120 #include <dev/mii/miidevs.h> 121 #include <dev/mii/brgphyreg.h> 122 123 #include <dev/pci/if_bgereg.h> 124 125 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 126 127 const struct bge_revision * bge_lookup_rev(u_int32_t); 128 int bge_probe(struct device *, void *, void *); 129 void bge_attach(struct device *, struct device *, void *); 130 int bge_activate(struct device *, int); 131 132 struct cfattach bge_ca = { 133 sizeof(struct bge_softc), bge_probe, bge_attach, NULL, bge_activate 134 }; 135 136 struct cfdriver bge_cd = { 137 NULL, "bge", DV_IFNET 138 }; 139 140 void bge_txeof(struct bge_softc *); 141 void bge_rxeof(struct bge_softc *); 142 143 void bge_tick(void *); 144 void bge_stats_update(struct bge_softc *); 145 void bge_stats_update_regs(struct bge_softc *); 146 int bge_cksum_pad(struct mbuf *); 147 int bge_encap(struct bge_softc *, struct mbuf *, u_int32_t *); 148 int bge_compact_dma_runt(struct mbuf *); 149 150 int bge_intr(void *); 151 void bge_start(struct ifnet *); 152 int bge_ioctl(struct ifnet *, u_long, caddr_t); 153 void bge_init(void *); 154 void bge_stop_block(struct bge_softc *, bus_size_t, u_int32_t); 155 void bge_stop(struct bge_softc *); 156 void bge_watchdog(struct ifnet *); 157 int bge_ifmedia_upd(struct ifnet *); 158 void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 159 160 u_int8_t bge_nvram_getbyte(struct bge_softc *, int, u_int8_t *); 161 int bge_read_nvram(struct bge_softc *, caddr_t, int, int); 162 u_int8_t bge_eeprom_getbyte(struct bge_softc *, int, u_int8_t *); 163 int bge_read_eeprom(struct bge_softc *, caddr_t, int, int); 164 165 void bge_iff(struct bge_softc *); 166 167 int bge_newbuf_jumbo(struct bge_softc *, int); 168 int bge_init_rx_ring_jumbo(struct bge_softc *); 169 void bge_fill_rx_ring_jumbo(struct bge_softc *); 170 void bge_free_rx_ring_jumbo(struct bge_softc *); 171 172 int bge_newbuf(struct bge_softc *, int); 173 int bge_init_rx_ring_std(struct bge_softc *); 174 void bge_rxtick(void *); 175 void bge_fill_rx_ring_std(struct bge_softc *); 176 void bge_free_rx_ring_std(struct bge_softc *); 177 178 void bge_free_tx_ring(struct bge_softc *); 179 int bge_init_tx_ring(struct bge_softc *); 180 181 void bge_chipinit(struct bge_softc *); 182 int bge_blockinit(struct bge_softc *); 183 184 u_int32_t bge_readmem_ind(struct bge_softc *, int); 185 void bge_writemem_ind(struct bge_softc *, int, int); 186 void bge_writereg_ind(struct bge_softc *, int, int); 187 void bge_writembx(struct bge_softc *, int, int); 188 189 int bge_miibus_readreg(struct device *, int, int); 190 void bge_miibus_writereg(struct device *, int, int, int); 191 void bge_miibus_statchg(struct device *); 192 193 void bge_reset(struct bge_softc *); 194 void bge_link_upd(struct bge_softc *); 195 196 #ifdef BGE_DEBUG 197 #define DPRINTF(x) do { if (bgedebug) printf x; } while (0) 198 #define DPRINTFN(n,x) do { if (bgedebug >= (n)) printf x; } while (0) 199 int bgedebug = 0; 200 #else 201 #define DPRINTF(x) 202 #define DPRINTFN(n,x) 203 #endif 204 205 /* 206 * Various supported device vendors/types and their names. Note: the 207 * spec seems to indicate that the hardware still has Alteon's vendor 208 * ID burned into it, though it will always be overridden by the vendor 209 * ID in the EEPROM. Just to be safe, we cover all possibilities. 210 */ 211 const struct pci_matchid bge_devices[] = { 212 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5700 }, 213 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5701 }, 214 215 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1000 }, 216 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1001 }, 217 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1003 }, 218 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC9100 }, 219 220 { PCI_VENDOR_APPLE, PCI_PRODUCT_APPLE_BCM5701 }, 221 222 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5700 }, 223 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5701 }, 224 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702 }, 225 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702_ALT }, 226 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702X }, 227 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703 }, 228 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703_ALT }, 229 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703X }, 230 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704C }, 231 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S }, 232 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S_ALT }, 233 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705 }, 234 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705F }, 235 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705K }, 236 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M }, 237 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M_ALT }, 238 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714 }, 239 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714S }, 240 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715 }, 241 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715S }, 242 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5717 }, 243 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5718 }, 244 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5720 }, 245 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5721 }, 246 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5722 }, 247 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5723 }, 248 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5724 }, 249 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750 }, 250 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750M }, 251 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751 }, 252 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751F }, 253 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751M }, 254 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752 }, 255 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752M }, 256 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753 }, 257 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753F }, 258 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753M }, 259 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754 }, 260 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754M }, 261 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755 }, 262 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755M }, 263 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5756 }, 264 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761 }, 265 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761E }, 266 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761S }, 267 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761SE }, 268 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5764 }, 269 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780 }, 270 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780S }, 271 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5781 }, 272 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5782 }, 273 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5784 }, 274 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5785F }, 275 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5785G }, 276 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5786 }, 277 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787 }, 278 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787F }, 279 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787M }, 280 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5788 }, 281 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5789 }, 282 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901 }, 283 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901A2 }, 284 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5903M }, 285 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5906 }, 286 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5906M }, 287 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57760 }, 288 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57761 }, 289 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57765 }, 290 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57780 }, 291 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57781 }, 292 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57785 }, 293 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57788 }, 294 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57790 }, 295 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57791 }, 296 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57795 }, 297 298 { PCI_VENDOR_FUJITSU, PCI_PRODUCT_FUJITSU_PW008GE4 }, 299 { PCI_VENDOR_FUJITSU, PCI_PRODUCT_FUJITSU_PW008GE5 }, 300 { PCI_VENDOR_FUJITSU, PCI_PRODUCT_FUJITSU_PP250_450_LAN }, 301 302 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9D21 }, 303 304 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C996 } 305 }; 306 307 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_5705_PLUS) 308 #define BGE_IS_5750_PLUS(sc) ((sc)->bge_flags & BGE_5750_PLUS) 309 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_5755_PLUS) 310 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_5700_FAMILY) 311 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_5714_FAMILY) 312 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_JUMBO_CAPABLE) 313 314 static const struct bge_revision { 315 u_int32_t br_chipid; 316 const char *br_name; 317 } bge_revisions[] = { 318 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 319 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 320 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 321 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 322 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 323 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 324 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 325 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 326 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 327 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 328 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 329 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 330 /* the 5702 and 5703 share the same ASIC ID */ 331 { BGE_CHIPID_BCM5703_A0, "BCM5702/5703 A0" }, 332 { BGE_CHIPID_BCM5703_A1, "BCM5702/5703 A1" }, 333 { BGE_CHIPID_BCM5703_A2, "BCM5702/5703 A2" }, 334 { BGE_CHIPID_BCM5703_A3, "BCM5702/5703 A3" }, 335 { BGE_CHIPID_BCM5703_B0, "BCM5702/5703 B0" }, 336 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 337 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 338 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 339 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 340 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 341 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 342 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 343 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 344 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 345 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 346 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 347 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 348 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 349 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 350 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 351 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 352 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 353 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 354 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 355 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 356 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 357 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 358 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 359 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 360 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 361 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 362 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 363 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 364 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 365 { BGE_CHIPID_BCM5755_C0, "BCM5755 C0" }, 366 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" }, 367 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" }, 368 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" }, 369 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" }, 370 /* the 5754 and 5787 share the same ASIC ID */ 371 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 372 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 373 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 374 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 375 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 376 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" }, 377 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" }, 378 379 { 0, NULL } 380 }; 381 382 /* 383 * Some defaults for major revisions, so that newer steppings 384 * that we don't know about have a shot at working. 385 */ 386 static const struct bge_revision bge_majorrevs[] = { 387 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 388 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 389 /* 5702 and 5703 share the same ASIC ID */ 390 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 391 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 392 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 393 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 394 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 395 { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 396 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 397 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 398 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 399 { BGE_ASICREV_BCM5761, "unknown BCM5761" }, 400 { BGE_ASICREV_BCM5784, "unknown BCM5784" }, 401 { BGE_ASICREV_BCM5785, "unknown BCM5785" }, 402 /* 5754 and 5787 share the same ASIC ID */ 403 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 404 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 405 { BGE_ASICREV_BCM57780, "unknown BCM57780" }, 406 { BGE_ASICREV_BCM5717, "unknown BCM5717" }, 407 { BGE_ASICREV_BCM57765, "unknown BCM57765" }, 408 409 { 0, NULL } 410 }; 411 412 u_int32_t 413 bge_readmem_ind(struct bge_softc *sc, int off) 414 { 415 struct pci_attach_args *pa = &(sc->bge_pa); 416 417 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_BASEADDR, off); 418 return (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_DATA)); 419 } 420 421 void 422 bge_writemem_ind(struct bge_softc *sc, int off, int val) 423 { 424 struct pci_attach_args *pa = &(sc->bge_pa); 425 426 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_BASEADDR, off); 427 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_DATA, val); 428 } 429 430 void 431 bge_writereg_ind(struct bge_softc *sc, int off, int val) 432 { 433 struct pci_attach_args *pa = &(sc->bge_pa); 434 435 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_BASEADDR, off); 436 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_DATA, val); 437 } 438 439 void 440 bge_writembx(struct bge_softc *sc, int off, int val) 441 { 442 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 443 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 444 445 CSR_WRITE_4(sc, off, val); 446 } 447 448 u_int8_t 449 bge_nvram_getbyte(struct bge_softc *sc, int addr, u_int8_t *dest) 450 { 451 u_int32_t access, byte = 0; 452 int i; 453 454 /* Lock. */ 455 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 456 for (i = 0; i < 8000; i++) { 457 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 458 break; 459 DELAY(20); 460 } 461 if (i == 8000) 462 return (1); 463 464 /* Enable access. */ 465 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 466 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 467 468 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 469 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 470 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 471 DELAY(10); 472 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 473 DELAY(10); 474 break; 475 } 476 } 477 478 if (i == BGE_TIMEOUT * 10) { 479 printf("%s: nvram read timed out\n", sc->bge_dev.dv_xname); 480 return (1); 481 } 482 483 /* Get result. */ 484 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 485 486 *dest = (swap32(byte) >> ((addr % 4) * 8)) & 0xFF; 487 488 /* Disable access. */ 489 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 490 491 /* Unlock. */ 492 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 493 CSR_READ_4(sc, BGE_NVRAM_SWARB); 494 495 return (0); 496 } 497 498 /* 499 * Read a sequence of bytes from NVRAM. 500 */ 501 502 int 503 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt) 504 { 505 int err = 0, i; 506 u_int8_t byte = 0; 507 508 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906) 509 return (1); 510 511 for (i = 0; i < cnt; i++) { 512 err = bge_nvram_getbyte(sc, off + i, &byte); 513 if (err) 514 break; 515 *(dest + i) = byte; 516 } 517 518 return (err ? 1 : 0); 519 } 520 521 /* 522 * Read a byte of data stored in the EEPROM at address 'addr.' The 523 * BCM570x supports both the traditional bitbang interface and an 524 * auto access interface for reading the EEPROM. We use the auto 525 * access method. 526 */ 527 u_int8_t 528 bge_eeprom_getbyte(struct bge_softc *sc, int addr, u_int8_t *dest) 529 { 530 int i; 531 u_int32_t byte = 0; 532 533 /* 534 * Enable use of auto EEPROM access so we can avoid 535 * having to use the bitbang method. 536 */ 537 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 538 539 /* Reset the EEPROM, load the clock period. */ 540 CSR_WRITE_4(sc, BGE_EE_ADDR, 541 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 542 DELAY(20); 543 544 /* Issue the read EEPROM command. */ 545 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 546 547 /* Wait for completion */ 548 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 549 DELAY(10); 550 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 551 break; 552 } 553 554 if (i == BGE_TIMEOUT * 10) { 555 printf("%s: eeprom read timed out\n", sc->bge_dev.dv_xname); 556 return (1); 557 } 558 559 /* Get result. */ 560 byte = CSR_READ_4(sc, BGE_EE_DATA); 561 562 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 563 564 return (0); 565 } 566 567 /* 568 * Read a sequence of bytes from the EEPROM. 569 */ 570 int 571 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt) 572 { 573 int err = 0, i; 574 u_int8_t byte = 0; 575 576 for (i = 0; i < cnt; i++) { 577 err = bge_eeprom_getbyte(sc, off + i, &byte); 578 if (err) 579 break; 580 *(dest + i) = byte; 581 } 582 583 return (err ? 1 : 0); 584 } 585 586 int 587 bge_miibus_readreg(struct device *dev, int phy, int reg) 588 { 589 struct bge_softc *sc = (struct bge_softc *)dev; 590 u_int32_t val, autopoll; 591 int i; 592 593 /* 594 * Broadcom's own driver always assumes the internal 595 * PHY is at GMII address 1. On some chips, the PHY responds 596 * to accesses at all addresses, which could cause us to 597 * bogusly attach the PHY 32 times at probe type. Always 598 * restricting the lookup to address 1 is simpler than 599 * trying to figure out which chips revisions should be 600 * special-cased. 601 */ 602 if (phy != 1) 603 return (0); 604 605 /* Reading with autopolling on may trigger PCI errors */ 606 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 607 if (autopoll & BGE_MIMODE_AUTOPOLL) { 608 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 609 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 610 DELAY(40); 611 } 612 613 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY| 614 BGE_MIPHY(phy)|BGE_MIREG(reg)); 615 616 for (i = 0; i < 200; i++) { 617 delay(1); 618 val = CSR_READ_4(sc, BGE_MI_COMM); 619 if (!(val & BGE_MICOMM_BUSY)) 620 break; 621 delay(10); 622 } 623 624 if (i == 200) { 625 printf("%s: PHY read timed out\n", sc->bge_dev.dv_xname); 626 val = 0; 627 goto done; 628 } 629 630 val = CSR_READ_4(sc, BGE_MI_COMM); 631 632 done: 633 if (autopoll & BGE_MIMODE_AUTOPOLL) { 634 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 635 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 636 DELAY(40); 637 } 638 639 if (val & BGE_MICOMM_READFAIL) 640 return (0); 641 642 return (val & 0xFFFF); 643 } 644 645 void 646 bge_miibus_writereg(struct device *dev, int phy, int reg, int val) 647 { 648 struct bge_softc *sc = (struct bge_softc *)dev; 649 u_int32_t autopoll; 650 int i; 651 652 /* Reading with autopolling on may trigger PCI errors */ 653 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 654 if (autopoll & BGE_MIMODE_AUTOPOLL) { 655 DELAY(40); 656 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 657 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 658 DELAY(10); /* 40 usec is supposed to be adequate */ 659 } 660 661 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY| 662 BGE_MIPHY(phy)|BGE_MIREG(reg)|val); 663 664 for (i = 0; i < 200; i++) { 665 delay(1); 666 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) 667 break; 668 delay(10); 669 } 670 671 if (autopoll & BGE_MIMODE_AUTOPOLL) { 672 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 673 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 674 DELAY(40); 675 } 676 677 if (i == 200) { 678 printf("%s: PHY read timed out\n", sc->bge_dev.dv_xname); 679 } 680 } 681 682 void 683 bge_miibus_statchg(struct device *dev) 684 { 685 struct bge_softc *sc = (struct bge_softc *)dev; 686 struct mii_data *mii = &sc->bge_mii; 687 688 /* 689 * Get flow control negotiation result. 690 */ 691 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 692 (mii->mii_media_active & IFM_ETH_FMASK) != sc->bge_flowflags) { 693 sc->bge_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 694 mii->mii_media_active &= ~IFM_ETH_FMASK; 695 } 696 697 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 698 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 699 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 700 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 701 else 702 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 703 704 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 705 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 706 else 707 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 708 709 /* 710 * 802.3x flow control 711 */ 712 if (sc->bge_flowflags & IFM_ETH_RXPAUSE) 713 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE); 714 else 715 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE); 716 717 if (sc->bge_flowflags & IFM_ETH_TXPAUSE) 718 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE); 719 else 720 BGE_CLRBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE); 721 } 722 723 /* 724 * Intialize a standard receive ring descriptor. 725 */ 726 int 727 bge_newbuf(struct bge_softc *sc, int i) 728 { 729 bus_dmamap_t dmap = sc->bge_cdata.bge_rx_std_map[i]; 730 struct bge_rx_bd *r = &sc->bge_rdata->bge_rx_std_ring[i]; 731 struct mbuf *m; 732 int error; 733 734 m = MCLGETI(NULL, M_DONTWAIT, &sc->arpcom.ac_if, MCLBYTES); 735 if (!m) 736 return (ENOBUFS); 737 m->m_len = m->m_pkthdr.len = MCLBYTES; 738 if (!(sc->bge_flags & BGE_RX_ALIGNBUG)) 739 m_adj(m, ETHER_ALIGN); 740 741 error = bus_dmamap_load_mbuf(sc->bge_dmatag, dmap, m, 742 BUS_DMA_READ|BUS_DMA_NOWAIT); 743 if (error) { 744 m_freem(m); 745 return (ENOBUFS); 746 } 747 748 bus_dmamap_sync(sc->bge_dmatag, dmap, 0, dmap->dm_mapsize, 749 BUS_DMASYNC_PREREAD); 750 sc->bge_cdata.bge_rx_std_chain[i] = m; 751 752 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 753 offsetof(struct bge_ring_data, bge_rx_std_ring) + 754 i * sizeof (struct bge_rx_bd), 755 sizeof (struct bge_rx_bd), 756 BUS_DMASYNC_POSTWRITE); 757 758 BGE_HOSTADDR(r->bge_addr, dmap->dm_segs[0].ds_addr); 759 r->bge_flags = BGE_RXBDFLAG_END; 760 r->bge_len = m->m_len; 761 r->bge_idx = i; 762 763 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 764 offsetof(struct bge_ring_data, bge_rx_std_ring) + 765 i * sizeof (struct bge_rx_bd), 766 sizeof (struct bge_rx_bd), 767 BUS_DMASYNC_PREWRITE); 768 769 sc->bge_std_cnt++; 770 771 return (0); 772 } 773 774 /* 775 * Initialize a Jumbo receive ring descriptor. 776 */ 777 int 778 bge_newbuf_jumbo(struct bge_softc *sc, int i) 779 { 780 bus_dmamap_t dmap = sc->bge_cdata.bge_rx_jumbo_map[i]; 781 struct bge_ext_rx_bd *r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 782 struct mbuf *m; 783 int error; 784 785 m = MCLGETI(NULL, M_DONTWAIT, &sc->arpcom.ac_if, BGE_JLEN); 786 if (!m) 787 return (ENOBUFS); 788 m->m_len = m->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 789 if (!(sc->bge_flags & BGE_RX_ALIGNBUG)) 790 m_adj(m, ETHER_ALIGN); 791 792 error = bus_dmamap_load_mbuf(sc->bge_dmatag, dmap, m, 793 BUS_DMA_READ|BUS_DMA_NOWAIT); 794 if (error) { 795 m_freem(m); 796 return (ENOBUFS); 797 } 798 799 bus_dmamap_sync(sc->bge_dmatag, dmap, 0, dmap->dm_mapsize, 800 BUS_DMASYNC_PREREAD); 801 sc->bge_cdata.bge_rx_jumbo_chain[i] = m; 802 803 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 804 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 805 i * sizeof (struct bge_ext_rx_bd), 806 sizeof (struct bge_ext_rx_bd), 807 BUS_DMASYNC_POSTWRITE); 808 809 /* 810 * Fill in the extended RX buffer descriptor. 811 */ 812 r->bge_bd.bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END; 813 r->bge_bd.bge_idx = i; 814 r->bge_len3 = r->bge_len2 = r->bge_len1 = 0; 815 switch (dmap->dm_nsegs) { 816 case 4: 817 BGE_HOSTADDR(r->bge_addr3, dmap->dm_segs[3].ds_addr); 818 r->bge_len3 = dmap->dm_segs[3].ds_len; 819 /* FALLTHROUGH */ 820 case 3: 821 BGE_HOSTADDR(r->bge_addr2, dmap->dm_segs[2].ds_addr); 822 r->bge_len2 = dmap->dm_segs[2].ds_len; 823 /* FALLTHROUGH */ 824 case 2: 825 BGE_HOSTADDR(r->bge_addr1, dmap->dm_segs[1].ds_addr); 826 r->bge_len1 = dmap->dm_segs[1].ds_len; 827 /* FALLTHROUGH */ 828 case 1: 829 BGE_HOSTADDR(r->bge_bd.bge_addr, dmap->dm_segs[0].ds_addr); 830 r->bge_bd.bge_len = dmap->dm_segs[0].ds_len; 831 break; 832 default: 833 panic("%s: %d segments", __func__, dmap->dm_nsegs); 834 } 835 836 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 837 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 838 i * sizeof (struct bge_ext_rx_bd), 839 sizeof (struct bge_ext_rx_bd), 840 BUS_DMASYNC_PREWRITE); 841 842 sc->bge_jumbo_cnt++; 843 844 return (0); 845 } 846 847 /* 848 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 849 * that's 1MB or memory, which is a lot. For now, we fill only the first 850 * 256 ring entries and hope that our CPU is fast enough to keep up with 851 * the NIC. 852 */ 853 int 854 bge_init_rx_ring_std(struct bge_softc *sc) 855 { 856 int i; 857 858 if (ISSET(sc->bge_flags, BGE_RXRING_VALID)) 859 return (0); 860 861 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 862 if (bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, MCLBYTES, 0, 863 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 864 &sc->bge_cdata.bge_rx_std_map[i]) != 0) { 865 printf("%s: unable to create dmamap for slot %d\n", 866 sc->bge_dev.dv_xname, i); 867 goto uncreate; 868 } 869 bzero(&sc->bge_rdata->bge_rx_std_ring[i], 870 sizeof(struct bge_rx_bd)); 871 } 872 873 sc->bge_std = BGE_STD_RX_RING_CNT - 1; 874 sc->bge_std_cnt = 0; 875 bge_fill_rx_ring_std(sc); 876 877 SET(sc->bge_flags, BGE_RXRING_VALID); 878 879 return (0); 880 881 uncreate: 882 while (--i) { 883 bus_dmamap_destroy(sc->bge_dmatag, 884 sc->bge_cdata.bge_rx_std_map[i]); 885 } 886 return (1); 887 } 888 889 void 890 bge_rxtick(void *arg) 891 { 892 struct bge_softc *sc = arg; 893 int s; 894 895 s = splnet(); 896 if (ISSET(sc->bge_flags, BGE_RXRING_VALID) && 897 sc->bge_std_cnt <= 8) 898 bge_fill_rx_ring_std(sc); 899 if (ISSET(sc->bge_flags, BGE_JUMBO_RXRING_VALID) && 900 sc->bge_jumbo_cnt <= 8) 901 bge_fill_rx_ring_jumbo(sc); 902 splx(s); 903 } 904 905 void 906 bge_fill_rx_ring_std(struct bge_softc *sc) 907 { 908 int i; 909 int post = 0; 910 911 i = sc->bge_std; 912 while (sc->bge_std_cnt < BGE_STD_RX_RING_CNT) { 913 BGE_INC(i, BGE_STD_RX_RING_CNT); 914 915 if (bge_newbuf(sc, i) != 0) 916 break; 917 918 sc->bge_std = i; 919 post = 1; 920 } 921 922 if (post) 923 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 924 925 /* 926 * bge always needs more than 8 packets on the ring. if we cant do 927 * that now, then try again later. 928 */ 929 if (sc->bge_std_cnt <= 8) 930 timeout_add(&sc->bge_rxtimeout, 1); 931 } 932 933 void 934 bge_free_rx_ring_std(struct bge_softc *sc) 935 { 936 bus_dmamap_t dmap; 937 struct mbuf *m; 938 int i; 939 940 if (!ISSET(sc->bge_flags, BGE_RXRING_VALID)) 941 return; 942 943 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 944 dmap = sc->bge_cdata.bge_rx_std_map[i]; 945 m = sc->bge_cdata.bge_rx_std_chain[i]; 946 if (m != NULL) { 947 bus_dmamap_sync(sc->bge_dmatag, dmap, 0, 948 dmap->dm_mapsize, BUS_DMASYNC_POSTREAD); 949 bus_dmamap_unload(sc->bge_dmatag, dmap); 950 m_freem(m); 951 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 952 } 953 bus_dmamap_destroy(sc->bge_dmatag, dmap); 954 sc->bge_cdata.bge_rx_std_map[i] = NULL; 955 bzero(&sc->bge_rdata->bge_rx_std_ring[i], 956 sizeof(struct bge_rx_bd)); 957 } 958 959 CLR(sc->bge_flags, BGE_RXRING_VALID); 960 } 961 962 int 963 bge_init_rx_ring_jumbo(struct bge_softc *sc) 964 { 965 volatile struct bge_rcb *rcb; 966 int i; 967 968 if (ISSET(sc->bge_flags, BGE_JUMBO_RXRING_VALID)) 969 return (0); 970 971 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 972 if (bus_dmamap_create(sc->bge_dmatag, BGE_JLEN, 4, BGE_JLEN, 0, 973 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 974 &sc->bge_cdata.bge_rx_jumbo_map[i]) != 0) { 975 printf("%s: unable to create dmamap for slot %d\n", 976 sc->bge_dev.dv_xname, i); 977 goto uncreate; 978 } 979 bzero(&sc->bge_rdata->bge_rx_jumbo_ring[i], 980 sizeof(struct bge_ext_rx_bd)); 981 } 982 983 sc->bge_jumbo = BGE_JUMBO_RX_RING_CNT - 1; 984 sc->bge_jumbo_cnt = 0; 985 bge_fill_rx_ring_jumbo(sc); 986 987 SET(sc->bge_flags, BGE_JUMBO_RXRING_VALID); 988 989 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 990 rcb->bge_maxlen_flags = 991 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_USE_EXT_RX_BD); 992 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 993 994 return (0); 995 996 uncreate: 997 while (--i) { 998 bus_dmamap_destroy(sc->bge_dmatag, 999 sc->bge_cdata.bge_rx_jumbo_map[i]); 1000 } 1001 return (1); 1002 } 1003 1004 void 1005 bge_fill_rx_ring_jumbo(struct bge_softc *sc) 1006 { 1007 int i; 1008 int post = 0; 1009 1010 i = sc->bge_jumbo; 1011 while (sc->bge_jumbo_cnt < BGE_JUMBO_RX_RING_CNT) { 1012 BGE_INC(i, BGE_JUMBO_RX_RING_CNT); 1013 1014 if (bge_newbuf_jumbo(sc, i) != 0) 1015 break; 1016 1017 sc->bge_jumbo = i; 1018 post = 1; 1019 } 1020 1021 if (post) 1022 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1023 1024 /* 1025 * bge always needs more than 8 packets on the ring. if we cant do 1026 * that now, then try again later. 1027 */ 1028 if (sc->bge_jumbo_cnt <= 8) 1029 timeout_add(&sc->bge_rxtimeout, 1); 1030 } 1031 1032 void 1033 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1034 { 1035 bus_dmamap_t dmap; 1036 struct mbuf *m; 1037 int i; 1038 1039 if (!ISSET(sc->bge_flags, BGE_JUMBO_RXRING_VALID)) 1040 return; 1041 1042 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1043 dmap = sc->bge_cdata.bge_rx_jumbo_map[i]; 1044 m = sc->bge_cdata.bge_rx_jumbo_chain[i]; 1045 if (m != NULL) { 1046 bus_dmamap_sync(sc->bge_dmatag, dmap, 0, 1047 dmap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1048 bus_dmamap_unload(sc->bge_dmatag, dmap); 1049 m_freem(m); 1050 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1051 } 1052 bus_dmamap_destroy(sc->bge_dmatag, dmap); 1053 sc->bge_cdata.bge_rx_jumbo_map[i] = NULL; 1054 bzero(&sc->bge_rdata->bge_rx_jumbo_ring[i], 1055 sizeof(struct bge_ext_rx_bd)); 1056 } 1057 1058 CLR(sc->bge_flags, BGE_JUMBO_RXRING_VALID); 1059 } 1060 1061 void 1062 bge_free_tx_ring(struct bge_softc *sc) 1063 { 1064 int i; 1065 struct txdmamap_pool_entry *dma; 1066 1067 if (!(sc->bge_flags & BGE_TXRING_VALID)) 1068 return; 1069 1070 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1071 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1072 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1073 sc->bge_cdata.bge_tx_chain[i] = NULL; 1074 SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1075 link); 1076 sc->txdma[i] = 0; 1077 } 1078 bzero(&sc->bge_rdata->bge_tx_ring[i], 1079 sizeof(struct bge_tx_bd)); 1080 } 1081 1082 while ((dma = SLIST_FIRST(&sc->txdma_list))) { 1083 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 1084 bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap); 1085 free(dma, M_DEVBUF); 1086 } 1087 1088 sc->bge_flags &= ~BGE_TXRING_VALID; 1089 } 1090 1091 int 1092 bge_init_tx_ring(struct bge_softc *sc) 1093 { 1094 int i; 1095 bus_dmamap_t dmamap; 1096 struct txdmamap_pool_entry *dma; 1097 1098 if (sc->bge_flags & BGE_TXRING_VALID) 1099 return (0); 1100 1101 sc->bge_txcnt = 0; 1102 sc->bge_tx_saved_considx = 0; 1103 1104 /* Initialize transmit producer index for host-memory send ring. */ 1105 sc->bge_tx_prodidx = 0; 1106 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1107 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1108 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1109 1110 /* NIC-memory send ring not used; initialize to zero. */ 1111 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1112 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1113 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1114 1115 SLIST_INIT(&sc->txdma_list); 1116 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1117 if (bus_dmamap_create(sc->bge_dmatag, BGE_JLEN, 1118 BGE_NTXSEG, BGE_JLEN, 0, BUS_DMA_NOWAIT, 1119 &dmamap)) 1120 return (ENOBUFS); 1121 if (dmamap == NULL) 1122 panic("dmamap NULL in bge_init_tx_ring"); 1123 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1124 if (dma == NULL) { 1125 printf("%s: can't alloc txdmamap_pool_entry\n", 1126 sc->bge_dev.dv_xname); 1127 bus_dmamap_destroy(sc->bge_dmatag, dmamap); 1128 return (ENOMEM); 1129 } 1130 dma->dmamap = dmamap; 1131 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 1132 } 1133 1134 sc->bge_flags |= BGE_TXRING_VALID; 1135 1136 return (0); 1137 } 1138 1139 void 1140 bge_iff(struct bge_softc *sc) 1141 { 1142 struct arpcom *ac = &sc->arpcom; 1143 struct ifnet *ifp = &ac->ac_if; 1144 struct ether_multi *enm; 1145 struct ether_multistep step; 1146 u_int8_t hashes[16]; 1147 u_int32_t h, rxmode; 1148 1149 /* First, zot all the existing filters. */ 1150 rxmode = CSR_READ_4(sc, BGE_RX_MODE) & ~BGE_RXMODE_RX_PROMISC; 1151 ifp->if_flags &= ~IFF_ALLMULTI; 1152 memset(hashes, 0x00, sizeof(hashes)); 1153 1154 if (ifp->if_flags & IFF_PROMISC) { 1155 ifp->if_flags |= IFF_ALLMULTI; 1156 rxmode |= BGE_RXMODE_RX_PROMISC; 1157 } else if (ac->ac_multirangecnt > 0) { 1158 ifp->if_flags |= IFF_ALLMULTI; 1159 memset(hashes, 0xff, sizeof(hashes)); 1160 } else { 1161 ETHER_FIRST_MULTI(step, ac, enm); 1162 while (enm != NULL) { 1163 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1164 1165 setbit(hashes, h & 0x7F); 1166 1167 ETHER_NEXT_MULTI(step, enm); 1168 } 1169 } 1170 1171 bus_space_write_raw_region_4(sc->bge_btag, sc->bge_bhandle, BGE_MAR0, 1172 hashes, sizeof(hashes)); 1173 CSR_WRITE_4(sc, BGE_RX_MODE, rxmode); 1174 } 1175 1176 /* 1177 * Do endian, PCI and DMA initialization. 1178 */ 1179 void 1180 bge_chipinit(struct bge_softc *sc) 1181 { 1182 struct pci_attach_args *pa = &(sc->bge_pa); 1183 u_int32_t dma_rw_ctl; 1184 int i; 1185 1186 /* Set endianness before we access any non-PCI registers. */ 1187 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL, 1188 BGE_INIT); 1189 1190 /* Clear the MAC control register */ 1191 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1192 1193 /* 1194 * Clear the MAC statistics block in the NIC's 1195 * internal memory. 1196 */ 1197 for (i = BGE_STATS_BLOCK; 1198 i < BGE_STATS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1199 BGE_MEMWIN_WRITE(pa->pa_pc, pa->pa_tag, i, 0); 1200 1201 for (i = BGE_STATUS_BLOCK; 1202 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1203 BGE_MEMWIN_WRITE(pa->pa_pc, pa->pa_tag, i, 0); 1204 1205 /* 1206 * Set up the PCI DMA control register. 1207 */ 1208 dma_rw_ctl = BGE_PCIDMARWCTL_RD_CMD_SHIFT(6) | 1209 BGE_PCIDMARWCTL_WR_CMD_SHIFT(7); 1210 1211 if (sc->bge_flags & BGE_PCIE) { 1212 /* Read watermark not used, 128 bytes for write. */ 1213 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1214 } else if (sc->bge_flags & BGE_PCIX) { 1215 /* PCI-X bus */ 1216 if (BGE_IS_5714_FAMILY(sc)) { 1217 /* 256 bytes for read and write. */ 1218 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) | 1219 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2); 1220 1221 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780) 1222 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 1223 else 1224 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 1225 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 1226 /* 1536 bytes for read, 384 bytes for write. */ 1227 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 1228 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1229 } else { 1230 /* 384 bytes for read and write. */ 1231 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) | 1232 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) | 1233 (0x0F); 1234 } 1235 1236 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 1237 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 1238 u_int32_t tmp; 1239 1240 /* Set ONEDMA_ATONCE for hardware workaround. */ 1241 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f; 1242 if (tmp == 6 || tmp == 7) 1243 dma_rw_ctl |= 1244 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 1245 1246 /* Set PCI-X DMA write workaround. */ 1247 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 1248 } 1249 } else { 1250 /* Conventional PCI bus: 256 bytes for read and write. */ 1251 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 1252 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 1253 1254 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5705 && 1255 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5750) 1256 dma_rw_ctl |= 0x0F; 1257 } 1258 1259 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 1260 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) 1261 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 1262 BGE_PCIDMARWCTL_ASRT_ALL_BE; 1263 1264 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 1265 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 1266 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 1267 1268 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, dma_rw_ctl); 1269 1270 /* 1271 * Set up general mode register. 1272 */ 1273 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS| 1274 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS| 1275 BGE_MODECTL_TX_NO_PHDR_CSUM); 1276 1277 /* 1278 * BCM5701 B5 have a bug causing data corruption when using 1279 * 64-bit DMA reads, which can be terminated early and then 1280 * completed later as 32-bit accesses, in combination with 1281 * certain bridges. 1282 */ 1283 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 1284 sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 1285 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_FORCE_PCI32); 1286 1287 /* 1288 * Disable memory write invalidate. Apparently it is not supported 1289 * properly by these devices. 1290 */ 1291 PCI_CLRBIT(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 1292 PCI_COMMAND_INVALIDATE_ENABLE); 1293 1294 #ifdef __brokenalpha__ 1295 /* 1296 * Must insure that we do not cross an 8K (bytes) boundary 1297 * for DMA reads. Our highest limit is 1K bytes. This is a 1298 * restriction on some ALPHA platforms with early revision 1299 * 21174 PCI chipsets, such as the AlphaPC 164lx 1300 */ 1301 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1302 BGE_PCI_READ_BNDRY_1024); 1303 #endif 1304 1305 /* Set the timer prescaler (always 66MHz) */ 1306 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); 1307 1308 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 1309 DELAY(40); /* XXX */ 1310 1311 /* Put PHY into ready state */ 1312 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 1313 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */ 1314 DELAY(40); 1315 } 1316 } 1317 1318 int 1319 bge_blockinit(struct bge_softc *sc) 1320 { 1321 volatile struct bge_rcb *rcb; 1322 vaddr_t rcb_addr; 1323 int i; 1324 bge_hostaddr taddr; 1325 u_int32_t val; 1326 1327 /* 1328 * Initialize the memory window pointer register so that 1329 * we can access the first 32K of internal NIC RAM. This will 1330 * allow us to set up the TX send ring RCBs and the RX return 1331 * ring RCBs, plus other things which live in NIC memory. 1332 */ 1333 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0); 1334 1335 /* Configure mbuf memory pool */ 1336 if (BGE_IS_5700_FAMILY(sc)) { 1337 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1338 BGE_BUFFPOOL_1); 1339 1340 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 1341 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1342 else 1343 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1344 1345 /* Configure DMA resource pool */ 1346 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 1347 BGE_DMA_DESCRIPTORS); 1348 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1349 } 1350 1351 /* Configure mbuf pool watermarks */ 1352 /* new Broadcom docs strongly recommend these: */ 1353 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 1354 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57765) { 1355 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1356 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a); 1357 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0); 1358 } else if (BGE_IS_5705_PLUS(sc)) { 1359 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1360 1361 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 1362 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 1363 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 1364 } else { 1365 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 1366 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1367 } 1368 } else { 1369 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1370 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1371 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1372 } 1373 1374 /* Configure DMA resource watermarks */ 1375 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1376 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1377 1378 /* Enable buffer manager */ 1379 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1380 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN); 1381 1382 /* Poll for buffer manager start indication */ 1383 for (i = 0; i < 2000; i++) { 1384 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1385 break; 1386 DELAY(10); 1387 } 1388 1389 if (i == 2000) { 1390 printf("%s: buffer manager failed to start\n", 1391 sc->bge_dev.dv_xname); 1392 return (ENXIO); 1393 } 1394 1395 /* Enable flow-through queues */ 1396 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1397 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1398 1399 /* Wait until queue initialization is complete */ 1400 for (i = 0; i < 2000; i++) { 1401 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1402 break; 1403 DELAY(10); 1404 } 1405 1406 if (i == 2000) { 1407 printf("%s: flow-through queue init failed\n", 1408 sc->bge_dev.dv_xname); 1409 return (ENXIO); 1410 } 1411 1412 /* Initialize the standard RX ring control block */ 1413 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 1414 BGE_HOSTADDR(rcb->bge_hostaddr, BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); 1415 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 1416 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57765) 1417 rcb->bge_maxlen_flags = (BGE_RCB_MAXLEN_FLAGS(512, 0) | 1418 (ETHER_MAX_DIX_LEN << 2)); 1419 else if (BGE_IS_5705_PLUS(sc)) 1420 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 1421 else 1422 rcb->bge_maxlen_flags = 1423 BGE_RCB_MAXLEN_FLAGS(ETHER_MAX_DIX_LEN, 0); 1424 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1425 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 1426 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 1427 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1428 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 1429 1430 /* 1431 * Initialize the Jumbo RX ring control block 1432 * We set the 'ring disabled' bit in the flags 1433 * field until we're actually ready to start 1434 * using this ring (i.e. once we set the MTU 1435 * high enough to require it). 1436 */ 1437 if (BGE_IS_JUMBO_CAPABLE(sc)) { 1438 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1439 BGE_HOSTADDR(rcb->bge_hostaddr, 1440 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); 1441 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 1442 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED); 1443 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1444 1445 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 1446 rcb->bge_hostaddr.bge_addr_hi); 1447 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 1448 rcb->bge_hostaddr.bge_addr_lo); 1449 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 1450 rcb->bge_maxlen_flags); 1451 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, 1452 rcb->bge_nicaddr); 1453 1454 /* Set up dummy disabled mini ring RCB */ 1455 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 1456 rcb->bge_maxlen_flags = 1457 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 1458 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 1459 rcb->bge_maxlen_flags); 1460 1461 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1462 offsetof(struct bge_ring_data, bge_info), 1463 sizeof (struct bge_gib), 1464 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1465 } 1466 1467 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */ 1468 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 1469 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 || 1470 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 || 1471 sc->bge_chipid == BGE_CHIPID_BCM5906_A2) 1472 CSR_WRITE_4(sc, BGE_ISO_PKT_TX, 1473 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2); 1474 } 1475 /* 1476 * Set the BD ring replenish thresholds. The recommended 1477 * values are 1/8th the number of descriptors allocated to 1478 * each ring, but since we try to avoid filling the entire 1479 * ring we set these to the minimal value of 8. This needs to 1480 * be done on several of the supported chip revisions anyway, 1481 * to work around HW bugs. 1482 */ 1483 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, 8); 1484 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, 8); 1485 1486 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 1487 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57765) { 1488 CSR_WRITE_4(sc, BGE_STD_REPL_LWM, 4); 1489 CSR_WRITE_4(sc, BGE_JUMBO_REPL_LWM, 4); 1490 } 1491 1492 /* 1493 * Disable all unused send rings by setting the 'ring disabled' 1494 * bit in the flags field of all the TX send ring control blocks. 1495 * These are located in NIC memory. 1496 */ 1497 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1498 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 1499 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1500 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 1501 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 1502 rcb_addr += sizeof(struct bge_rcb); 1503 } 1504 1505 /* Configure TX RCB 0 (we use only the first ring) */ 1506 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1507 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 1508 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1509 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1510 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 1511 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 1512 if (BGE_IS_5700_FAMILY(sc)) 1513 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1514 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 1515 1516 /* Disable all unused RX return rings */ 1517 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1518 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 1519 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 1520 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 1521 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1522 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 1523 BGE_RCB_FLAG_RING_DISABLED)); 1524 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 1525 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 1526 (i * (sizeof(u_int64_t))), 0); 1527 rcb_addr += sizeof(struct bge_rcb); 1528 } 1529 1530 /* Initialize RX ring indexes */ 1531 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1532 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1533 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1534 1535 /* 1536 * Set up RX return ring 0 1537 * Note that the NIC address for RX return rings is 0x00000000. 1538 * The return rings live entirely within the host, so the 1539 * nicaddr field in the RCB isn't used. 1540 */ 1541 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1542 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 1543 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1544 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1545 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 1546 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 1547 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 1548 1549 /* Set random backoff seed for TX */ 1550 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1551 sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] + 1552 sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] + 1553 sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] + 1554 BGE_TX_BACKOFF_SEED_MASK); 1555 1556 /* Set inter-packet gap */ 1557 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 1558 1559 /* 1560 * Specify which ring to use for packets that don't match 1561 * any RX rules. 1562 */ 1563 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1564 1565 /* 1566 * Configure number of RX lists. One interrupt distribution 1567 * list, sixteen active lists, one bad frames class. 1568 */ 1569 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1570 1571 /* Inialize RX list placement stats mask. */ 1572 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1573 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1574 1575 /* Disable host coalescing until we get it set up */ 1576 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1577 1578 /* Poll to make sure it's shut down. */ 1579 for (i = 0; i < 2000; i++) { 1580 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 1581 break; 1582 DELAY(10); 1583 } 1584 1585 if (i == 2000) { 1586 printf("%s: host coalescing engine failed to idle\n", 1587 sc->bge_dev.dv_xname); 1588 return (ENXIO); 1589 } 1590 1591 /* Set up host coalescing defaults */ 1592 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 1593 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 1594 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 1595 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 1596 if (BGE_IS_5700_FAMILY(sc)) { 1597 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 1598 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 1599 } 1600 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 1601 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 1602 1603 /* Set up address of statistics block */ 1604 if (BGE_IS_5700_FAMILY(sc)) { 1605 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 0); 1606 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, 1607 BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 1608 1609 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 1610 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 1611 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 1612 } 1613 1614 /* Set up address of status block */ 1615 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_status_block)); 1616 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); 1617 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); 1618 1619 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 1620 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 1621 1622 /* Turn on host coalescing state machine */ 1623 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 1624 1625 /* Turn on RX BD completion state machine and enable attentions */ 1626 CSR_WRITE_4(sc, BGE_RBDC_MODE, 1627 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN); 1628 1629 /* Turn on RX list placement state machine */ 1630 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 1631 1632 /* Turn on RX list selector state machine. */ 1633 if (BGE_IS_5700_FAMILY(sc)) 1634 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 1635 1636 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 1637 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 1638 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 1639 BGE_MACMODE_FRMHDR_DMA_ENB; 1640 1641 if (sc->bge_flags & BGE_PHY_FIBER_TBI) 1642 val |= BGE_PORTMODE_TBI; 1643 else if (sc->bge_flags & BGE_PHY_FIBER_MII) 1644 val |= BGE_PORTMODE_GMII; 1645 else 1646 val |= BGE_PORTMODE_MII; 1647 1648 /* Turn on DMA, clear stats */ 1649 CSR_WRITE_4(sc, BGE_MAC_MODE, val); 1650 1651 /* Set misc. local control, enable interrupts on attentions */ 1652 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 1653 1654 #ifdef notdef 1655 /* Assert GPIO pins for PHY reset */ 1656 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 1657 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 1658 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 1659 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 1660 #endif 1661 1662 /* Turn on DMA completion state machine */ 1663 if (BGE_IS_5700_FAMILY(sc)) 1664 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 1665 1666 val = BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS; 1667 1668 /* Enable host coalescing bug fix. */ 1669 if (BGE_IS_5755_PLUS(sc)) 1670 val |= BGE_WDMAMODE_STATUS_TAG_FIX; 1671 1672 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) 1673 val |= BGE_WDMAMODE_BURST_ALL_DATA; 1674 1675 /* Turn on write DMA state machine */ 1676 CSR_WRITE_4(sc, BGE_WDMA_MODE, val); 1677 1678 val = BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS; 1679 1680 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717) 1681 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS; 1682 1683 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 1684 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 1685 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 1686 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 1687 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 1688 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 1689 1690 if (sc->bge_flags & BGE_PCIE) 1691 val |= BGE_RDMAMODE_FIFO_LONG_BURST; 1692 1693 /* Turn on read DMA state machine */ 1694 CSR_WRITE_4(sc, BGE_RDMA_MODE, val); 1695 1696 /* Turn on RX data completion state machine */ 1697 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 1698 1699 /* Turn on RX BD initiator state machine */ 1700 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 1701 1702 /* Turn on RX data and RX BD initiator state machine */ 1703 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 1704 1705 /* Turn on Mbuf cluster free state machine */ 1706 if (BGE_IS_5700_FAMILY(sc)) 1707 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 1708 1709 /* Turn on send BD completion state machine */ 1710 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 1711 1712 val = BGE_SDCMODE_ENABLE; 1713 1714 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 1715 val |= BGE_SDCMODE_CDELAY; 1716 1717 /* Turn on send data completion state machine */ 1718 CSR_WRITE_4(sc, BGE_SDC_MODE, val); 1719 1720 /* Turn on send data initiator state machine */ 1721 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 1722 1723 /* Turn on send BD initiator state machine */ 1724 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 1725 1726 /* Turn on send BD selector state machine */ 1727 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 1728 1729 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 1730 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 1731 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER); 1732 1733 /* ack/clear link change events */ 1734 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 1735 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 1736 BGE_MACSTAT_LINK_CHANGED); 1737 1738 /* Enable PHY auto polling (for MII/GMII only) */ 1739 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 1740 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 1741 } else { 1742 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1743 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16); 1744 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) 1745 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 1746 BGE_EVTENB_MI_INTERRUPT); 1747 } 1748 1749 /* 1750 * Clear any pending link state attention. 1751 * Otherwise some link state change events may be lost until attention 1752 * is cleared by bge_intr() -> bge_link_upd() sequence. 1753 * It's not necessary on newer BCM chips - perhaps enabling link 1754 * state change attentions implies clearing pending attention. 1755 */ 1756 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 1757 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 1758 BGE_MACSTAT_LINK_CHANGED); 1759 1760 /* Enable link state change attentions. */ 1761 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 1762 1763 return (0); 1764 } 1765 1766 const struct bge_revision * 1767 bge_lookup_rev(u_int32_t chipid) 1768 { 1769 const struct bge_revision *br; 1770 1771 for (br = bge_revisions; br->br_name != NULL; br++) { 1772 if (br->br_chipid == chipid) 1773 return (br); 1774 } 1775 1776 for (br = bge_majorrevs; br->br_name != NULL; br++) { 1777 if (br->br_chipid == BGE_ASICREV(chipid)) 1778 return (br); 1779 } 1780 1781 return (NULL); 1782 } 1783 1784 /* 1785 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 1786 * against our list and return its name if we find a match. Note 1787 * that since the Broadcom controller contains VPD support, we 1788 * can get the device name string from the controller itself instead 1789 * of the compiled-in string. This is a little slow, but it guarantees 1790 * we'll always announce the right product name. 1791 */ 1792 int 1793 bge_probe(struct device *parent, void *match, void *aux) 1794 { 1795 return (pci_matchbyid(aux, bge_devices, nitems(bge_devices))); 1796 } 1797 1798 void 1799 bge_attach(struct device *parent, struct device *self, void *aux) 1800 { 1801 struct bge_softc *sc = (struct bge_softc *)self; 1802 struct pci_attach_args *pa = aux; 1803 pci_chipset_tag_t pc = pa->pa_pc; 1804 const struct bge_revision *br; 1805 pcireg_t pm_ctl, memtype, subid, reg; 1806 pci_intr_handle_t ih; 1807 const char *intrstr = NULL; 1808 bus_size_t size; 1809 bus_dma_segment_t seg; 1810 int rseg, gotenaddr = 0, aspm_off; 1811 u_int32_t hwcfg = 0; 1812 u_int32_t mac_addr = 0; 1813 u_int32_t misccfg; 1814 struct ifnet *ifp; 1815 caddr_t kva; 1816 #ifdef __sparc64__ 1817 char name[32]; 1818 #endif 1819 1820 sc->bge_pa = *pa; 1821 1822 subid = pci_conf_read(pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 1823 1824 /* 1825 * Map control/status registers. 1826 */ 1827 DPRINTFN(5, ("Map control/status regs\n")); 1828 1829 DPRINTFN(5, ("pci_mapreg_map\n")); 1830 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR0); 1831 if (pci_mapreg_map(pa, BGE_PCI_BAR0, memtype, 0, &sc->bge_btag, 1832 &sc->bge_bhandle, NULL, &size, 0)) { 1833 printf(": can't find mem space\n"); 1834 return; 1835 } 1836 1837 DPRINTFN(5, ("pci_intr_map\n")); 1838 if (pci_intr_map(pa, &ih)) { 1839 printf(": couldn't map interrupt\n"); 1840 goto fail_1; 1841 } 1842 1843 DPRINTFN(5, ("pci_intr_string\n")); 1844 intrstr = pci_intr_string(pc, ih); 1845 1846 /* 1847 * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?) 1848 * can clobber the chip's PCI config-space power control registers, 1849 * leaving the card in D3 powersave state. 1850 * We do not have memory-mapped registers in this state, 1851 * so force device into D0 state before starting initialization. 1852 */ 1853 pm_ctl = pci_conf_read(pc, pa->pa_tag, BGE_PCI_PWRMGMT_CMD); 1854 pm_ctl &= ~(PCI_PWR_D0|PCI_PWR_D1|PCI_PWR_D2|PCI_PWR_D3); 1855 pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */ 1856 pci_conf_write(pc, pa->pa_tag, BGE_PCI_PWRMGMT_CMD, pm_ctl); 1857 DELAY(1000); /* 27 usec is allegedly sufficent */ 1858 1859 /* 1860 * Save ASIC rev. 1861 */ 1862 sc->bge_chipid = 1863 (pci_conf_read(pc, pa->pa_tag, BGE_PCI_MISC_CTL) 1864 >> BGE_PCIMISCCTL_ASICREV_SHIFT); 1865 1866 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_USE_PRODID_REG) { 1867 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5717 || 1868 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5718 || 1869 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5724) 1870 sc->bge_chipid = pci_conf_read(pc, pa->pa_tag, 1871 BGE_PCI_GEN2_PRODID_ASICREV); 1872 else if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57761 || 1873 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57765 || 1874 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57781 || 1875 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57785 || 1876 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57791 || 1877 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57795) 1878 sc->bge_chipid = pci_conf_read(pc, pa->pa_tag, 1879 BGE_PCI_GEN15_PRODID_ASICREV); 1880 else 1881 sc->bge_chipid = pci_conf_read(pc, pa->pa_tag, 1882 BGE_PCI_PRODID_ASICREV); 1883 } 1884 1885 printf(", "); 1886 br = bge_lookup_rev(sc->bge_chipid); 1887 if (br == NULL) 1888 printf("unknown ASIC (0x%x)", sc->bge_chipid); 1889 else 1890 printf("%s (0x%x)", br->br_name, sc->bge_chipid); 1891 1892 /* 1893 * PCI Express or PCI-X controller check. 1894 */ 1895 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIEXPRESS, 1896 &aspm_off, NULL) != 0) { 1897 /* Disable PCIe Active State Power Management (ASPM). */ 1898 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, 1899 aspm_off + PCI_PCIE_LCSR); 1900 reg &= ~(PCI_PCIE_LCSR_ASPM_L0S | PCI_PCIE_LCSR_ASPM_L1); 1901 pci_conf_write(pa->pa_pc, pa->pa_tag, 1902 aspm_off + PCI_PCIE_LCSR, reg); 1903 sc->bge_flags |= BGE_PCIE; 1904 } else { 1905 if ((pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE) & 1906 BGE_PCISTATE_PCI_BUSMODE) == 0) 1907 sc->bge_flags |= BGE_PCIX; 1908 } 1909 1910 /* 1911 * SEEPROM check. 1912 */ 1913 #ifdef __sparc64__ 1914 /* 1915 * Onboard interfaces on UltraSPARC systems generally don't 1916 * have a SEEPROM fitted. These interfaces, and cards that 1917 * have FCode, are named "network" by the PROM, whereas cards 1918 * without FCode show up as "ethernet". Since we don't really 1919 * need the information from the SEEPROM on cards that have 1920 * FCode it's fine to pretend they don't have one. 1921 */ 1922 if (OF_getprop(PCITAG_NODE(pa->pa_tag), "name", name, 1923 sizeof(name)) > 0 && strcmp(name, "network") == 0) 1924 sc->bge_flags |= BGE_NO_EEPROM; 1925 #endif 1926 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 1927 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 || 1928 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 1929 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 1930 sc->bge_flags |= BGE_5700_FAMILY; 1931 1932 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5714_A0 || 1933 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780 || 1934 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5714) 1935 sc->bge_flags |= BGE_5714_FAMILY; 1936 1937 /* Intentionally exclude BGE_ASICREV_BCM5906 */ 1938 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 1939 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 1940 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 1941 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 1942 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 1943 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787 || 1944 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57765 || 1945 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 1946 sc->bge_flags |= BGE_5755_PLUS; 1947 1948 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750 || 1949 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 1950 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 || 1951 BGE_IS_5755_PLUS(sc) || 1952 BGE_IS_5714_FAMILY(sc)) 1953 sc->bge_flags |= BGE_5750_PLUS; 1954 1955 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 || 1956 BGE_IS_5750_PLUS(sc)) 1957 sc->bge_flags |= BGE_5705_PLUS; 1958 1959 /* 1960 * When using the BCM5701 in PCI-X mode, data corruption has 1961 * been observed in the first few bytes of some received packets. 1962 * Aligning the packet buffer in memory eliminates the corruption. 1963 * Unfortunately, this misaligns the packet payloads. On platforms 1964 * which do not support unaligned accesses, we will realign the 1965 * payloads by copying the received packets. 1966 */ 1967 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 1968 sc->bge_flags & BGE_PCIX) 1969 sc->bge_flags |= BGE_RX_ALIGNBUG; 1970 1971 if (BGE_IS_5700_FAMILY(sc)) 1972 sc->bge_flags |= BGE_JUMBO_CAPABLE; 1973 1974 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 1975 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) && 1976 PCI_VENDOR(subid) == DELL_VENDORID) 1977 sc->bge_flags |= BGE_NO_3LED; 1978 1979 misccfg = CSR_READ_4(sc, BGE_MISC_CFG); 1980 misccfg &= BGE_MISCCFG_BOARD_ID_MASK; 1981 1982 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 1983 (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 1984 misccfg == BGE_MISCCFG_BOARD_ID_5788M)) 1985 sc->bge_flags |= BGE_IS_5788; 1986 1987 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 && 1988 (misccfg == 0x4000 || misccfg == 0x8000)) || 1989 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 1990 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 1991 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901 || 1992 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901A2 || 1993 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5705F)) || 1994 (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 1995 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5751F || 1996 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5753F || 1997 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5787F)) || 1998 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57790 || 1999 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 2000 sc->bge_flags |= BGE_10_100_ONLY; 2001 2002 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 2003 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 2004 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 2005 sc->bge_chipid != BGE_CHIPID_BCM5705_A1)) || 2006 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 2007 sc->bge_flags |= BGE_NO_ETH_WIRE_SPEED; 2008 2009 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 2010 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 2011 sc->bge_flags |= BGE_PHY_CRC_BUG; 2012 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5703_AX || 2013 BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_AX) 2014 sc->bge_flags |= BGE_PHY_ADC_BUG; 2015 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 2016 sc->bge_flags |= BGE_PHY_5704_A0_BUG; 2017 2018 if ((BGE_IS_5705_PLUS(sc)) && 2019 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906 && 2020 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717 && 2021 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785 && 2022 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57765 && 2023 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57780) { 2024 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 2025 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 2026 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2027 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) { 2028 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5722 && 2029 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5756) 2030 sc->bge_flags |= BGE_PHY_JITTER_BUG; 2031 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5755M) 2032 sc->bge_flags |= BGE_PHY_ADJUST_TRIM; 2033 } else 2034 sc->bge_flags |= BGE_PHY_BER_BUG; 2035 } 2036 2037 /* Try to reset the chip. */ 2038 DPRINTFN(5, ("bge_reset\n")); 2039 bge_reset(sc); 2040 2041 bge_chipinit(sc); 2042 2043 #ifdef __sparc64__ 2044 if (!gotenaddr) { 2045 if (OF_getprop(PCITAG_NODE(pa->pa_tag), "local-mac-address", 2046 sc->arpcom.ac_enaddr, ETHER_ADDR_LEN) == ETHER_ADDR_LEN) 2047 gotenaddr = 1; 2048 } 2049 #endif 2050 2051 /* 2052 * Get station address from the EEPROM. 2053 */ 2054 if (!gotenaddr) { 2055 mac_addr = bge_readmem_ind(sc, 0x0c14); 2056 if ((mac_addr >> 16) == 0x484b) { 2057 sc->arpcom.ac_enaddr[0] = (u_char)(mac_addr >> 8); 2058 sc->arpcom.ac_enaddr[1] = (u_char)mac_addr; 2059 mac_addr = bge_readmem_ind(sc, 0x0c18); 2060 sc->arpcom.ac_enaddr[2] = (u_char)(mac_addr >> 24); 2061 sc->arpcom.ac_enaddr[3] = (u_char)(mac_addr >> 16); 2062 sc->arpcom.ac_enaddr[4] = (u_char)(mac_addr >> 8); 2063 sc->arpcom.ac_enaddr[5] = (u_char)mac_addr; 2064 gotenaddr = 1; 2065 } 2066 } 2067 if (!gotenaddr) { 2068 int mac_offset = BGE_EE_MAC_OFFSET; 2069 2070 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 2071 mac_offset = BGE_EE_MAC_OFFSET_5906; 2072 2073 if (bge_read_nvram(sc, (caddr_t)&sc->arpcom.ac_enaddr, 2074 mac_offset + 2, ETHER_ADDR_LEN) == 0) 2075 gotenaddr = 1; 2076 } 2077 if (!gotenaddr && (!(sc->bge_flags & BGE_NO_EEPROM))) { 2078 if (bge_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 2079 BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN) == 0) 2080 gotenaddr = 1; 2081 } 2082 2083 #ifdef __sparc64__ 2084 if (!gotenaddr) { 2085 extern void myetheraddr(u_char *); 2086 2087 myetheraddr(sc->arpcom.ac_enaddr); 2088 gotenaddr = 1; 2089 } 2090 #endif 2091 2092 if (!gotenaddr) { 2093 printf(": failed to read station address\n"); 2094 goto fail_1; 2095 } 2096 2097 /* Allocate the general information block and ring buffers. */ 2098 sc->bge_dmatag = pa->pa_dmat; 2099 DPRINTFN(5, ("bus_dmamem_alloc\n")); 2100 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 2101 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 2102 printf(": can't alloc rx buffers\n"); 2103 goto fail_1; 2104 } 2105 DPRINTFN(5, ("bus_dmamem_map\n")); 2106 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, 2107 sizeof(struct bge_ring_data), &kva, 2108 BUS_DMA_NOWAIT)) { 2109 printf(": can't map dma buffers (%lu bytes)\n", 2110 sizeof(struct bge_ring_data)); 2111 goto fail_2; 2112 } 2113 DPRINTFN(5, ("bus_dmamem_create\n")); 2114 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 2115 sizeof(struct bge_ring_data), 0, 2116 BUS_DMA_NOWAIT, &sc->bge_ring_map)) { 2117 printf(": can't create dma map\n"); 2118 goto fail_3; 2119 } 2120 DPRINTFN(5, ("bus_dmamem_load\n")); 2121 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 2122 sizeof(struct bge_ring_data), NULL, 2123 BUS_DMA_NOWAIT)) { 2124 goto fail_4; 2125 } 2126 2127 DPRINTFN(5, ("bzero\n")); 2128 sc->bge_rdata = (struct bge_ring_data *)kva; 2129 2130 bzero(sc->bge_rdata, sizeof(struct bge_ring_data)); 2131 2132 /* Set default tuneable values. */ 2133 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 2134 sc->bge_rx_coal_ticks = 150; 2135 sc->bge_rx_max_coal_bds = 64; 2136 sc->bge_tx_coal_ticks = 300; 2137 sc->bge_tx_max_coal_bds = 400; 2138 2139 /* 5705 limits RX return ring to 512 entries. */ 2140 if (BGE_IS_5700_FAMILY(sc) || 2141 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2142 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57765) 2143 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 2144 else 2145 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 2146 2147 /* Set up ifnet structure */ 2148 ifp = &sc->arpcom.ac_if; 2149 ifp->if_softc = sc; 2150 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2151 ifp->if_ioctl = bge_ioctl; 2152 ifp->if_start = bge_start; 2153 ifp->if_watchdog = bge_watchdog; 2154 IFQ_SET_MAXLEN(&ifp->if_snd, BGE_TX_RING_CNT - 1); 2155 IFQ_SET_READY(&ifp->if_snd); 2156 2157 /* lwm must be greater than the replenish threshold */ 2158 m_clsetwms(ifp, MCLBYTES, 17, BGE_STD_RX_RING_CNT); 2159 m_clsetwms(ifp, BGE_JLEN, 17, BGE_JUMBO_RX_RING_CNT); 2160 2161 DPRINTFN(5, ("bcopy\n")); 2162 bcopy(sc->bge_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 2163 2164 ifp->if_capabilities = IFCAP_VLAN_MTU; 2165 2166 #if NVLAN > 0 2167 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 2168 #endif 2169 2170 /* 2171 * 5700 B0 chips do not support checksumming correctly due 2172 * to hardware bugs. 2173 */ 2174 if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) 2175 ifp->if_capabilities |= IFCAP_CSUM_IPv4; 2176 #if 0 /* TCP/UDP checksum offload breaks with pf(4) */ 2177 ifp->if_capabilities |= IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4; 2178 #endif 2179 2180 if (BGE_IS_JUMBO_CAPABLE(sc)) 2181 ifp->if_hardmtu = BGE_JUMBO_MTU; 2182 2183 /* 2184 * Do MII setup. 2185 */ 2186 DPRINTFN(5, ("mii setup\n")); 2187 sc->bge_mii.mii_ifp = ifp; 2188 sc->bge_mii.mii_readreg = bge_miibus_readreg; 2189 sc->bge_mii.mii_writereg = bge_miibus_writereg; 2190 sc->bge_mii.mii_statchg = bge_miibus_statchg; 2191 2192 /* 2193 * Figure out what sort of media we have by checking the hardware 2194 * config word in the first 32K of internal NIC memory, or fall back to 2195 * examining the EEPROM if necessary. Note: on some BCM5700 cards, 2196 * this value seems to be unset. If that's the case, we have to rely on 2197 * identifying the NIC by its PCI subsystem ID, as we do below for the 2198 * SysKonnect SK-9D41. 2199 */ 2200 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) 2201 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG); 2202 else if (!(sc->bge_flags & BGE_NO_EEPROM)) { 2203 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET, 2204 sizeof(hwcfg))) { 2205 printf(": failed to read media type\n"); 2206 goto fail_5; 2207 } 2208 hwcfg = ntohl(hwcfg); 2209 } 2210 2211 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 2212 if (PCI_PRODUCT(subid) == SK_SUBSYSID_9D41 || 2213 (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 2214 if (BGE_IS_5714_FAMILY(sc) || 2215 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717) 2216 sc->bge_flags |= BGE_PHY_FIBER_MII; 2217 else 2218 sc->bge_flags |= BGE_PHY_FIBER_TBI; 2219 } 2220 2221 /* Hookup IRQ last. */ 2222 DPRINTFN(5, ("pci_intr_establish\n")); 2223 sc->bge_intrhand = pci_intr_establish(pc, ih, IPL_NET, bge_intr, sc, 2224 sc->bge_dev.dv_xname); 2225 if (sc->bge_intrhand == NULL) { 2226 printf(": couldn't establish interrupt"); 2227 if (intrstr != NULL) 2228 printf(" at %s", intrstr); 2229 printf("\n"); 2230 goto fail_5; 2231 } 2232 2233 /* 2234 * A Broadcom chip was detected. Inform the world. 2235 */ 2236 printf(": %s, address %s\n", intrstr, 2237 ether_sprintf(sc->arpcom.ac_enaddr)); 2238 2239 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 2240 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 2241 bge_ifmedia_sts); 2242 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 2243 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX|IFM_FDX, 2244 0, NULL); 2245 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 2246 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO); 2247 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 2248 } else { 2249 int mii_flags; 2250 2251 /* 2252 * Do transceiver setup. 2253 */ 2254 ifmedia_init(&sc->bge_mii.mii_media, 0, bge_ifmedia_upd, 2255 bge_ifmedia_sts); 2256 mii_flags = MIIF_DOPAUSE; 2257 if (sc->bge_flags & BGE_PHY_FIBER_MII) 2258 mii_flags |= MIIF_HAVEFIBER; 2259 mii_attach(&sc->bge_dev, &sc->bge_mii, 0xffffffff, 2260 MII_PHY_ANY, MII_OFFSET_ANY, mii_flags); 2261 2262 if (LIST_FIRST(&sc->bge_mii.mii_phys) == NULL) { 2263 printf("%s: no PHY found!\n", sc->bge_dev.dv_xname); 2264 ifmedia_add(&sc->bge_mii.mii_media, 2265 IFM_ETHER|IFM_MANUAL, 0, NULL); 2266 ifmedia_set(&sc->bge_mii.mii_media, 2267 IFM_ETHER|IFM_MANUAL); 2268 } else 2269 ifmedia_set(&sc->bge_mii.mii_media, 2270 IFM_ETHER|IFM_AUTO); 2271 } 2272 2273 /* 2274 * Call MI attach routine. 2275 */ 2276 if_attach(ifp); 2277 ether_ifattach(ifp); 2278 2279 timeout_set(&sc->bge_timeout, bge_tick, sc); 2280 timeout_set(&sc->bge_rxtimeout, bge_rxtick, sc); 2281 return; 2282 2283 fail_5: 2284 bus_dmamap_unload(sc->bge_dmatag, sc->bge_ring_map); 2285 2286 fail_4: 2287 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 2288 2289 fail_3: 2290 bus_dmamem_unmap(sc->bge_dmatag, kva, 2291 sizeof(struct bge_ring_data)); 2292 2293 fail_2: 2294 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 2295 2296 fail_1: 2297 bus_space_unmap(sc->bge_btag, sc->bge_bhandle, size); 2298 } 2299 2300 int 2301 bge_activate(struct device *self, int act) 2302 { 2303 struct bge_softc *sc = (struct bge_softc *)self; 2304 struct ifnet *ifp = &sc->arpcom.ac_if; 2305 int rv = 0; 2306 2307 switch (act) { 2308 case DVACT_QUIESCE: 2309 rv = config_activate_children(self, act); 2310 break; 2311 case DVACT_SUSPEND: 2312 rv = config_activate_children(self, act); 2313 if (ifp->if_flags & IFF_RUNNING) 2314 bge_stop(sc); 2315 break; 2316 case DVACT_RESUME: 2317 if (ifp->if_flags & IFF_UP) 2318 bge_init(sc); 2319 rv = config_activate_children(self, act); 2320 break; 2321 } 2322 return (rv); 2323 } 2324 2325 void 2326 bge_reset(struct bge_softc *sc) 2327 { 2328 struct pci_attach_args *pa = &sc->bge_pa; 2329 pcireg_t cachesize, command, pcistate, new_pcistate; 2330 u_int32_t reset; 2331 int i, val = 0; 2332 2333 /* Save some important PCI state. */ 2334 cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ); 2335 command = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD); 2336 pcistate = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE); 2337 2338 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL, 2339 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 2340 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW); 2341 2342 /* Disable fastboot on controllers that support it. */ 2343 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 2344 BGE_IS_5755_PLUS(sc)) 2345 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0); 2346 2347 reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1); 2348 2349 if (sc->bge_flags & BGE_PCIE) { 2350 if (CSR_READ_4(sc, 0x7e2c) == 0x60) { 2351 /* PCI Express 1.0 system */ 2352 CSR_WRITE_4(sc, 0x7e2c, 0x20); 2353 } 2354 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 2355 /* 2356 * Prevent PCI Express link training 2357 * during global reset. 2358 */ 2359 CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29)); 2360 reset |= (1<<29); 2361 } 2362 } 2363 2364 /* 2365 * Set GPHY Power Down Override to leave GPHY 2366 * powered up in D0 uninitialized. 2367 */ 2368 if (BGE_IS_5705_PLUS(sc)) 2369 reset |= BGE_MISCCFG_KEEP_GPHY_POWER; 2370 2371 /* Issue global reset */ 2372 bge_writereg_ind(sc, BGE_MISC_CFG, reset); 2373 2374 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2375 u_int32_t status, ctrl; 2376 2377 status = CSR_READ_4(sc, BGE_VCPU_STATUS); 2378 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 2379 status | BGE_VCPU_STATUS_DRV_RESET); 2380 ctrl = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 2381 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 2382 ctrl & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 2383 2384 sc->bge_flags |= BGE_NO_EEPROM; 2385 } 2386 2387 DELAY(1000); 2388 2389 if (sc->bge_flags & BGE_PCIE) { 2390 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 2391 pcireg_t v; 2392 2393 DELAY(500000); /* wait for link training to complete */ 2394 v = pci_conf_read(pa->pa_pc, pa->pa_tag, 0xc4); 2395 pci_conf_write(pa->pa_pc, pa->pa_tag, 0xc4, v | (1<<15)); 2396 } 2397 2398 /* 2399 * Set PCI Express max payload size to 128 bytes 2400 * and clear error status. 2401 */ 2402 pci_conf_write(pa->pa_pc, pa->pa_tag, 2403 BGE_PCI_CONF_DEV_CTRL, 0xf5000); 2404 } 2405 2406 /* Reset some of the PCI state that got zapped by reset */ 2407 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL, 2408 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 2409 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW); 2410 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ, cachesize); 2411 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD, command); 2412 bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1)); 2413 2414 /* Enable memory arbiter. */ 2415 if (BGE_IS_5714_FAMILY(sc)) { 2416 u_int32_t val; 2417 2418 val = CSR_READ_4(sc, BGE_MARB_MODE); 2419 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val); 2420 } else 2421 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 2422 2423 /* 2424 * Prevent PXE restart: write a magic number to the 2425 * general communications memory at 0xB50. 2426 */ 2427 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 2428 2429 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2430 for (i = 0; i < BGE_TIMEOUT; i++) { 2431 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 2432 if (val & BGE_VCPU_STATUS_INIT_DONE) 2433 break; 2434 DELAY(100); 2435 } 2436 2437 if (i >= BGE_TIMEOUT) 2438 printf("%s: reset timed out\n", sc->bge_dev.dv_xname); 2439 } else { 2440 /* 2441 * Poll until we see 1's complement of the magic number. 2442 * This indicates that the firmware initialization 2443 * is complete. We expect this to fail if no SEEPROM 2444 * is fitted. 2445 */ 2446 for (i = 0; i < BGE_TIMEOUT; i++) { 2447 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 2448 if (val == ~BGE_MAGIC_NUMBER) 2449 break; 2450 DELAY(10); 2451 } 2452 2453 if (i >= BGE_TIMEOUT && (!(sc->bge_flags & BGE_NO_EEPROM))) 2454 printf("%s: firmware handshake timed out\n", 2455 sc->bge_dev.dv_xname); 2456 } 2457 2458 /* 2459 * XXX Wait for the value of the PCISTATE register to 2460 * return to its original pre-reset state. This is a 2461 * fairly good indicator of reset completion. If we don't 2462 * wait for the reset to fully complete, trying to read 2463 * from the device's non-PCI registers may yield garbage 2464 * results. 2465 */ 2466 for (i = 0; i < BGE_TIMEOUT; i++) { 2467 new_pcistate = pci_conf_read(pa->pa_pc, pa->pa_tag, 2468 BGE_PCI_PCISTATE); 2469 if ((new_pcistate & ~BGE_PCISTATE_RESERVED) == 2470 (pcistate & ~BGE_PCISTATE_RESERVED)) 2471 break; 2472 DELAY(10); 2473 } 2474 if ((new_pcistate & ~BGE_PCISTATE_RESERVED) != 2475 (pcistate & ~BGE_PCISTATE_RESERVED)) { 2476 DPRINTFN(5, ("%s: pcistate failed to revert\n", 2477 sc->bge_dev.dv_xname)); 2478 } 2479 2480 /* Fix up byte swapping */ 2481 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS); 2482 2483 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 2484 2485 /* 2486 * The 5704 in TBI mode apparently needs some special 2487 * adjustment to insure the SERDES drive level is set 2488 * to 1.2V. 2489 */ 2490 if (sc->bge_flags & BGE_PHY_FIBER_TBI && 2491 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 2492 u_int32_t serdescfg; 2493 2494 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG); 2495 serdescfg = (serdescfg & ~0xFFF) | 0x880; 2496 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg); 2497 } 2498 2499 if (sc->bge_flags & BGE_PCIE && 2500 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 && 2501 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717 && 2502 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785 && 2503 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57765) { 2504 u_int32_t v; 2505 2506 /* Enable PCI Express bug fix */ 2507 v = CSR_READ_4(sc, 0x7c00); 2508 CSR_WRITE_4(sc, 0x7c00, v | (1<<25)); 2509 } 2510 DELAY(10000); 2511 } 2512 2513 /* 2514 * Frame reception handling. This is called if there's a frame 2515 * on the receive return list. 2516 * 2517 * Note: we have to be able to handle two possibilities here: 2518 * 1) the frame is from the jumbo receive ring 2519 * 2) the frame is from the standard receive ring 2520 */ 2521 2522 void 2523 bge_rxeof(struct bge_softc *sc) 2524 { 2525 struct ifnet *ifp; 2526 uint16_t rx_prod, rx_cons; 2527 int stdcnt = 0, jumbocnt = 0; 2528 bus_dmamap_t dmamap; 2529 bus_addr_t offset, toff; 2530 bus_size_t tlen; 2531 int tosync; 2532 2533 rx_cons = sc->bge_rx_saved_considx; 2534 rx_prod = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx; 2535 2536 /* Nothing to do */ 2537 if (rx_cons == rx_prod) 2538 return; 2539 2540 ifp = &sc->arpcom.ac_if; 2541 2542 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2543 offsetof(struct bge_ring_data, bge_status_block), 2544 sizeof (struct bge_status_block), 2545 BUS_DMASYNC_POSTREAD); 2546 2547 offset = offsetof(struct bge_ring_data, bge_rx_return_ring); 2548 tosync = rx_prod - rx_cons; 2549 2550 toff = offset + (rx_cons * sizeof (struct bge_rx_bd)); 2551 2552 if (tosync < 0) { 2553 tlen = (sc->bge_return_ring_cnt - rx_cons) * 2554 sizeof (struct bge_rx_bd); 2555 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2556 toff, tlen, BUS_DMASYNC_POSTREAD); 2557 tosync = -tosync; 2558 } 2559 2560 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2561 offset, tosync * sizeof (struct bge_rx_bd), 2562 BUS_DMASYNC_POSTREAD); 2563 2564 while (rx_cons != rx_prod) { 2565 struct bge_rx_bd *cur_rx; 2566 u_int32_t rxidx; 2567 struct mbuf *m = NULL; 2568 2569 cur_rx = &sc->bge_rdata->bge_rx_return_ring[rx_cons]; 2570 2571 rxidx = cur_rx->bge_idx; 2572 BGE_INC(rx_cons, sc->bge_return_ring_cnt); 2573 2574 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 2575 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 2576 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 2577 2578 jumbocnt++; 2579 sc->bge_jumbo_cnt--; 2580 2581 dmamap = sc->bge_cdata.bge_rx_jumbo_map[rxidx]; 2582 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, 2583 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2584 bus_dmamap_unload(sc->bge_dmatag, dmamap); 2585 2586 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2587 m_freem(m); 2588 continue; 2589 } 2590 } else { 2591 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 2592 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 2593 2594 stdcnt++; 2595 sc->bge_std_cnt--; 2596 2597 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx]; 2598 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, 2599 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2600 bus_dmamap_unload(sc->bge_dmatag, dmamap); 2601 2602 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2603 m_freem(m); 2604 continue; 2605 } 2606 } 2607 2608 ifp->if_ipackets++; 2609 #ifdef __STRICT_ALIGNMENT 2610 /* 2611 * The i386 allows unaligned accesses, but for other 2612 * platforms we must make sure the payload is aligned. 2613 */ 2614 if (sc->bge_flags & BGE_RX_ALIGNBUG) { 2615 bcopy(m->m_data, m->m_data + ETHER_ALIGN, 2616 cur_rx->bge_len); 2617 m->m_data += ETHER_ALIGN; 2618 } 2619 #endif 2620 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 2621 m->m_pkthdr.rcvif = ifp; 2622 2623 /* 2624 * 5700 B0 chips do not support checksumming correctly due 2625 * to hardware bugs. 2626 */ 2627 if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) { 2628 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) { 2629 if (cur_rx->bge_ip_csum == 0xFFFF) 2630 m->m_pkthdr.csum_flags |= 2631 M_IPV4_CSUM_IN_OK; 2632 else 2633 m->m_pkthdr.csum_flags |= 2634 M_IPV4_CSUM_IN_BAD; 2635 } 2636 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 2637 m->m_pkthdr.len >= ETHER_MIN_NOPAD) { 2638 if (cur_rx->bge_tcp_udp_csum == 0xFFFF) 2639 m->m_pkthdr.csum_flags |= 2640 M_TCP_CSUM_IN_OK|M_UDP_CSUM_IN_OK; 2641 } 2642 } 2643 2644 #if NVLAN > 0 2645 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 2646 m->m_pkthdr.ether_vtag = cur_rx->bge_vlan_tag; 2647 m->m_flags |= M_VLANTAG; 2648 } 2649 #endif 2650 2651 #if NBPFILTER > 0 2652 /* 2653 * Handle BPF listeners. Let the BPF user see the packet. 2654 */ 2655 if (ifp->if_bpf) 2656 bpf_mtap_ether(ifp->if_bpf, m, BPF_DIRECTION_IN); 2657 #endif 2658 2659 ether_input_mbuf(ifp, m); 2660 } 2661 2662 sc->bge_rx_saved_considx = rx_cons; 2663 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 2664 if (stdcnt) 2665 bge_fill_rx_ring_std(sc); 2666 if (jumbocnt) 2667 bge_fill_rx_ring_jumbo(sc); 2668 } 2669 2670 void 2671 bge_txeof(struct bge_softc *sc) 2672 { 2673 struct bge_tx_bd *cur_tx = NULL; 2674 struct ifnet *ifp; 2675 struct txdmamap_pool_entry *dma; 2676 bus_addr_t offset, toff; 2677 bus_size_t tlen; 2678 int tosync; 2679 struct mbuf *m; 2680 2681 /* Nothing to do */ 2682 if (sc->bge_tx_saved_considx == 2683 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) 2684 return; 2685 2686 ifp = &sc->arpcom.ac_if; 2687 2688 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2689 offsetof(struct bge_ring_data, bge_status_block), 2690 sizeof (struct bge_status_block), 2691 BUS_DMASYNC_POSTREAD); 2692 2693 offset = offsetof(struct bge_ring_data, bge_tx_ring); 2694 tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx - 2695 sc->bge_tx_saved_considx; 2696 2697 toff = offset + (sc->bge_tx_saved_considx * sizeof (struct bge_tx_bd)); 2698 2699 if (tosync < 0) { 2700 tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) * 2701 sizeof (struct bge_tx_bd); 2702 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2703 toff, tlen, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2704 tosync = -tosync; 2705 } 2706 2707 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2708 offset, tosync * sizeof (struct bge_tx_bd), 2709 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2710 2711 /* 2712 * Go through our tx ring and free mbufs for those 2713 * frames that have been sent. 2714 */ 2715 while (sc->bge_tx_saved_considx != 2716 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 2717 u_int32_t idx = 0; 2718 2719 idx = sc->bge_tx_saved_considx; 2720 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 2721 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 2722 ifp->if_opackets++; 2723 m = sc->bge_cdata.bge_tx_chain[idx]; 2724 if (m != NULL) { 2725 sc->bge_cdata.bge_tx_chain[idx] = NULL; 2726 dma = sc->txdma[idx]; 2727 bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 0, 2728 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2729 bus_dmamap_unload(sc->bge_dmatag, dma->dmamap); 2730 SLIST_INSERT_HEAD(&sc->txdma_list, dma, link); 2731 sc->txdma[idx] = NULL; 2732 2733 m_freem(m); 2734 } 2735 sc->bge_txcnt--; 2736 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 2737 } 2738 2739 if (sc->bge_txcnt < BGE_TX_RING_CNT - 16) 2740 ifp->if_flags &= ~IFF_OACTIVE; 2741 if (sc->bge_txcnt == 0) 2742 ifp->if_timer = 0; 2743 } 2744 2745 int 2746 bge_intr(void *xsc) 2747 { 2748 struct bge_softc *sc; 2749 struct ifnet *ifp; 2750 u_int32_t statusword; 2751 2752 sc = xsc; 2753 ifp = &sc->arpcom.ac_if; 2754 2755 /* It is possible for the interrupt to arrive before 2756 * the status block is updated prior to the interrupt. 2757 * Reading the PCI State register will confirm whether the 2758 * interrupt is ours and will flush the status block. 2759 */ 2760 2761 /* read status word from status block */ 2762 statusword = sc->bge_rdata->bge_status_block.bge_status; 2763 2764 if ((statusword & BGE_STATFLAG_UPDATED) || 2765 (!(CSR_READ_4(sc, BGE_PCI_PCISTATE) & BGE_PCISTATE_INTR_NOT_ACTIVE))) { 2766 2767 /* Ack interrupt and stop others from occurring. */ 2768 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 2769 2770 /* clear status word */ 2771 sc->bge_rdata->bge_status_block.bge_status = 0; 2772 2773 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 2774 statusword & BGE_STATFLAG_LINKSTATE_CHANGED || 2775 BGE_STS_BIT(sc, BGE_STS_LINK_EVT)) 2776 bge_link_upd(sc); 2777 2778 if (ifp->if_flags & IFF_RUNNING) { 2779 /* Check RX return ring producer/consumer */ 2780 bge_rxeof(sc); 2781 2782 /* Check TX ring producer/consumer */ 2783 bge_txeof(sc); 2784 } 2785 2786 /* Re-enable interrupts. */ 2787 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 2788 2789 bge_start(ifp); 2790 2791 return (1); 2792 } else 2793 return (0); 2794 } 2795 2796 void 2797 bge_tick(void *xsc) 2798 { 2799 struct bge_softc *sc = xsc; 2800 struct mii_data *mii = &sc->bge_mii; 2801 int s; 2802 2803 s = splnet(); 2804 2805 if (BGE_IS_5705_PLUS(sc)) 2806 bge_stats_update_regs(sc); 2807 else 2808 bge_stats_update(sc); 2809 2810 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 2811 /* 2812 * Since in TBI mode auto-polling can't be used we should poll 2813 * link status manually. Here we register pending link event 2814 * and trigger interrupt. 2815 */ 2816 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 2817 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 2818 } else { 2819 /* 2820 * Do not touch PHY if we have link up. This could break 2821 * IPMI/ASF mode or produce extra input errors. 2822 * (extra input errors was reported for bcm5701 & bcm5704). 2823 */ 2824 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 2825 mii_tick(mii); 2826 } 2827 2828 timeout_add_sec(&sc->bge_timeout, 1); 2829 2830 splx(s); 2831 } 2832 2833 void 2834 bge_stats_update_regs(struct bge_softc *sc) 2835 { 2836 struct ifnet *ifp = &sc->arpcom.ac_if; 2837 2838 ifp->if_collisions += CSR_READ_4(sc, BGE_MAC_STATS + 2839 offsetof(struct bge_mac_stats_regs, etherStatsCollisions)); 2840 2841 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 2842 2843 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 2844 2845 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 2846 } 2847 2848 void 2849 bge_stats_update(struct bge_softc *sc) 2850 { 2851 struct ifnet *ifp = &sc->arpcom.ac_if; 2852 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 2853 u_int32_t cnt; 2854 2855 #define READ_STAT(sc, stats, stat) \ 2856 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 2857 2858 cnt = READ_STAT(sc, stats, txstats.etherStatsCollisions.bge_addr_lo); 2859 ifp->if_collisions += (u_int32_t)(cnt - sc->bge_tx_collisions); 2860 sc->bge_tx_collisions = cnt; 2861 2862 cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo); 2863 ifp->if_ierrors += (u_int32_t)(cnt - sc->bge_rx_discards); 2864 sc->bge_rx_discards = cnt; 2865 2866 cnt = READ_STAT(sc, stats, ifInErrors.bge_addr_lo); 2867 ifp->if_ierrors += (u_int32_t)(cnt - sc->bge_rx_inerrors); 2868 sc->bge_rx_inerrors = cnt; 2869 2870 cnt = READ_STAT(sc, stats, nicNoMoreRxBDs.bge_addr_lo); 2871 ifp->if_ierrors += (u_int32_t)(cnt - sc->bge_rx_overruns); 2872 sc->bge_rx_overruns = cnt; 2873 2874 cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo); 2875 ifp->if_oerrors += (u_int32_t)(cnt - sc->bge_tx_discards); 2876 sc->bge_tx_discards = cnt; 2877 2878 #undef READ_STAT 2879 } 2880 2881 /* 2882 * Compact outbound packets to avoid bug with DMA segments less than 8 bytes. 2883 */ 2884 int 2885 bge_compact_dma_runt(struct mbuf *pkt) 2886 { 2887 struct mbuf *m, *prev, *n = NULL; 2888 int totlen, newprevlen; 2889 2890 prev = NULL; 2891 totlen = 0; 2892 2893 for (m = pkt; m != NULL; prev = m,m = m->m_next) { 2894 int mlen = m->m_len; 2895 int shortfall = 8 - mlen ; 2896 2897 totlen += mlen; 2898 if (mlen == 0) 2899 continue; 2900 if (mlen >= 8) 2901 continue; 2902 2903 /* If we get here, mbuf data is too small for DMA engine. 2904 * Try to fix by shuffling data to prev or next in chain. 2905 * If that fails, do a compacting deep-copy of the whole chain. 2906 */ 2907 2908 /* Internal frag. If fits in prev, copy it there. */ 2909 if (prev && M_TRAILINGSPACE(prev) >= m->m_len) { 2910 bcopy(m->m_data, prev->m_data+prev->m_len, mlen); 2911 prev->m_len += mlen; 2912 m->m_len = 0; 2913 /* XXX stitch chain */ 2914 prev->m_next = m_free(m); 2915 m = prev; 2916 continue; 2917 } else if (m->m_next != NULL && 2918 M_TRAILINGSPACE(m) >= shortfall && 2919 m->m_next->m_len >= (8 + shortfall)) { 2920 /* m is writable and have enough data in next, pull up. */ 2921 2922 bcopy(m->m_next->m_data, m->m_data+m->m_len, shortfall); 2923 m->m_len += shortfall; 2924 m->m_next->m_len -= shortfall; 2925 m->m_next->m_data += shortfall; 2926 } else if (m->m_next == NULL || 1) { 2927 /* Got a runt at the very end of the packet. 2928 * borrow data from the tail of the preceding mbuf and 2929 * update its length in-place. (The original data is still 2930 * valid, so we can do this even if prev is not writable.) 2931 */ 2932 2933 /* if we'd make prev a runt, just move all of its data. */ 2934 #ifdef DEBUG 2935 KASSERT(prev != NULL /*, ("runt but null PREV")*/); 2936 KASSERT(prev->m_len >= 8 /*, ("runt prev")*/); 2937 #endif 2938 if ((prev->m_len - shortfall) < 8) 2939 shortfall = prev->m_len; 2940 2941 newprevlen = prev->m_len - shortfall; 2942 2943 MGET(n, M_NOWAIT, MT_DATA); 2944 if (n == NULL) 2945 return (ENOBUFS); 2946 KASSERT(m->m_len + shortfall < MLEN 2947 /*, 2948 ("runt %d +prev %d too big\n", m->m_len, shortfall)*/); 2949 2950 /* first copy the data we're stealing from prev */ 2951 bcopy(prev->m_data + newprevlen, n->m_data, shortfall); 2952 2953 /* update prev->m_len accordingly */ 2954 prev->m_len -= shortfall; 2955 2956 /* copy data from runt m */ 2957 bcopy(m->m_data, n->m_data + shortfall, m->m_len); 2958 2959 /* n holds what we stole from prev, plus m */ 2960 n->m_len = shortfall + m->m_len; 2961 2962 /* stitch n into chain and free m */ 2963 n->m_next = m->m_next; 2964 prev->m_next = n; 2965 /* KASSERT(m->m_next == NULL); */ 2966 m->m_next = NULL; 2967 m_free(m); 2968 m = n; /* for continuing loop */ 2969 } 2970 } 2971 return (0); 2972 } 2973 2974 /* 2975 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 2976 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 2977 * but when such padded frames employ the bge IP/TCP checksum offload, 2978 * the hardware checksum assist gives incorrect results (possibly 2979 * from incorporating its own padding into the UDP/TCP checksum; who knows). 2980 * If we pad such runts with zeros, the onboard checksum comes out correct. 2981 */ 2982 int 2983 bge_cksum_pad(struct mbuf *m) 2984 { 2985 int padlen = ETHER_MIN_NOPAD - m->m_pkthdr.len; 2986 struct mbuf *last; 2987 2988 /* If there's only the packet-header and we can pad there, use it. */ 2989 if (m->m_pkthdr.len == m->m_len && M_TRAILINGSPACE(m) >= padlen) { 2990 last = m; 2991 } else { 2992 /* 2993 * Walk packet chain to find last mbuf. We will either 2994 * pad there, or append a new mbuf and pad it. 2995 */ 2996 for (last = m; last->m_next != NULL; last = last->m_next); 2997 if (M_TRAILINGSPACE(last) < padlen) { 2998 /* Allocate new empty mbuf, pad it. Compact later. */ 2999 struct mbuf *n; 3000 3001 MGET(n, M_DONTWAIT, MT_DATA); 3002 if (n == NULL) 3003 return (ENOBUFS); 3004 n->m_len = 0; 3005 last->m_next = n; 3006 last = n; 3007 } 3008 } 3009 3010 /* Now zero the pad area, to avoid the bge cksum-assist bug. */ 3011 memset(mtod(last, caddr_t) + last->m_len, 0, padlen); 3012 last->m_len += padlen; 3013 m->m_pkthdr.len += padlen; 3014 3015 return (0); 3016 } 3017 3018 /* 3019 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 3020 * pointers to descriptors. 3021 */ 3022 int 3023 bge_encap(struct bge_softc *sc, struct mbuf *m_head, u_int32_t *txidx) 3024 { 3025 struct bge_tx_bd *f = NULL; 3026 u_int32_t frag, cur; 3027 u_int16_t csum_flags = 0; 3028 struct txdmamap_pool_entry *dma; 3029 bus_dmamap_t dmamap; 3030 int i = 0; 3031 3032 cur = frag = *txidx; 3033 3034 if (m_head->m_pkthdr.csum_flags) { 3035 if (m_head->m_pkthdr.csum_flags & M_IPV4_CSUM_OUT) 3036 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 3037 if (m_head->m_pkthdr.csum_flags & (M_TCP_CSUM_OUT | 3038 M_UDP_CSUM_OUT)) { 3039 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 3040 if (m_head->m_pkthdr.len < ETHER_MIN_NOPAD && 3041 bge_cksum_pad(m_head) != 0) 3042 return (ENOBUFS); 3043 } 3044 } 3045 3046 if (!(BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX)) 3047 goto doit; 3048 3049 /* 3050 * bcm5700 Revision B silicon cannot handle DMA descriptors with 3051 * less than eight bytes. If we encounter a teeny mbuf 3052 * at the end of a chain, we can pad. Otherwise, copy. 3053 */ 3054 if (bge_compact_dma_runt(m_head) != 0) 3055 return (ENOBUFS); 3056 3057 doit: 3058 dma = SLIST_FIRST(&sc->txdma_list); 3059 if (dma == NULL) 3060 return (ENOBUFS); 3061 dmamap = dma->dmamap; 3062 3063 /* 3064 * Start packing the mbufs in this chain into 3065 * the fragment pointers. Stop when we run out 3066 * of fragments or hit the end of the mbuf chain. 3067 */ 3068 if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_head, 3069 BUS_DMA_NOWAIT)) 3070 return (ENOBUFS); 3071 3072 /* Check if we have enough free send BDs. */ 3073 if (sc->bge_txcnt + dmamap->dm_nsegs >= BGE_TX_RING_CNT) 3074 goto fail_unload; 3075 3076 for (i = 0; i < dmamap->dm_nsegs; i++) { 3077 f = &sc->bge_rdata->bge_tx_ring[frag]; 3078 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 3079 break; 3080 BGE_HOSTADDR(f->bge_addr, dmamap->dm_segs[i].ds_addr); 3081 f->bge_len = dmamap->dm_segs[i].ds_len; 3082 f->bge_flags = csum_flags; 3083 f->bge_vlan_tag = 0; 3084 #if NVLAN > 0 3085 if (m_head->m_flags & M_VLANTAG) { 3086 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 3087 f->bge_vlan_tag = m_head->m_pkthdr.ether_vtag; 3088 } 3089 #endif 3090 cur = frag; 3091 BGE_INC(frag, BGE_TX_RING_CNT); 3092 } 3093 3094 if (i < dmamap->dm_nsegs) 3095 goto fail_unload; 3096 3097 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 3098 BUS_DMASYNC_PREWRITE); 3099 3100 if (frag == sc->bge_tx_saved_considx) 3101 goto fail_unload; 3102 3103 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 3104 sc->bge_cdata.bge_tx_chain[cur] = m_head; 3105 SLIST_REMOVE_HEAD(&sc->txdma_list, link); 3106 sc->txdma[cur] = dma; 3107 sc->bge_txcnt += dmamap->dm_nsegs; 3108 3109 *txidx = frag; 3110 3111 return (0); 3112 3113 fail_unload: 3114 bus_dmamap_unload(sc->bge_dmatag, dmamap); 3115 3116 return (ENOBUFS); 3117 } 3118 3119 /* 3120 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3121 * to the mbuf data regions directly in the transmit descriptors. 3122 */ 3123 void 3124 bge_start(struct ifnet *ifp) 3125 { 3126 struct bge_softc *sc; 3127 struct mbuf *m_head; 3128 u_int32_t prodidx; 3129 int pkts; 3130 3131 sc = ifp->if_softc; 3132 3133 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 3134 return; 3135 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 3136 return; 3137 3138 prodidx = sc->bge_tx_prodidx; 3139 3140 for (pkts = 0; !IFQ_IS_EMPTY(&ifp->if_snd);) { 3141 if (sc->bge_txcnt > BGE_TX_RING_CNT - 16) { 3142 ifp->if_flags |= IFF_OACTIVE; 3143 break; 3144 } 3145 3146 IFQ_POLL(&ifp->if_snd, m_head); 3147 if (m_head == NULL) 3148 break; 3149 3150 /* 3151 * Pack the data into the transmit ring. If we 3152 * don't have room, set the OACTIVE flag and wait 3153 * for the NIC to drain the ring. 3154 */ 3155 if (bge_encap(sc, m_head, &prodidx)) { 3156 ifp->if_flags |= IFF_OACTIVE; 3157 break; 3158 } 3159 3160 /* now we are committed to transmit the packet */ 3161 IFQ_DEQUEUE(&ifp->if_snd, m_head); 3162 pkts++; 3163 3164 #if NBPFILTER > 0 3165 /* 3166 * If there's a BPF listener, bounce a copy of this frame 3167 * to him. 3168 */ 3169 if (ifp->if_bpf) 3170 bpf_mtap_ether(ifp->if_bpf, m_head, BPF_DIRECTION_OUT); 3171 #endif 3172 } 3173 if (pkts == 0) 3174 return; 3175 3176 /* Transmit */ 3177 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3178 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 3179 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3180 3181 sc->bge_tx_prodidx = prodidx; 3182 3183 /* 3184 * Set a timeout in case the chip goes out to lunch. 3185 */ 3186 ifp->if_timer = 5; 3187 } 3188 3189 void 3190 bge_init(void *xsc) 3191 { 3192 struct bge_softc *sc = xsc; 3193 struct ifnet *ifp; 3194 u_int16_t *m; 3195 u_int32_t rxmode; 3196 int s; 3197 3198 s = splnet(); 3199 3200 ifp = &sc->arpcom.ac_if; 3201 3202 /* Cancel pending I/O and flush buffers. */ 3203 bge_stop(sc); 3204 bge_reset(sc); 3205 bge_chipinit(sc); 3206 3207 /* 3208 * Init the various state machines, ring 3209 * control blocks and firmware. 3210 */ 3211 if (bge_blockinit(sc)) { 3212 printf("%s: initialization failure\n", sc->bge_dev.dv_xname); 3213 splx(s); 3214 return; 3215 } 3216 3217 /* Specify MRU. */ 3218 if (BGE_IS_JUMBO_CAPABLE(sc)) 3219 CSR_WRITE_4(sc, BGE_RX_MTU, 3220 BGE_JUMBO_FRAMELEN + ETHER_VLAN_ENCAP_LEN); 3221 else 3222 CSR_WRITE_4(sc, BGE_RX_MTU, 3223 ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN); 3224 3225 /* Load our MAC address. */ 3226 m = (u_int16_t *)&sc->arpcom.ac_enaddr[0]; 3227 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 3228 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 3229 3230 if (!(ifp->if_capabilities & IFCAP_VLAN_HWTAGGING)) { 3231 /* Disable hardware decapsulation of VLAN frames. */ 3232 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG); 3233 } 3234 3235 /* Program promiscuous mode and multicast filters. */ 3236 bge_iff(sc); 3237 3238 /* Init RX ring. */ 3239 bge_init_rx_ring_std(sc); 3240 3241 /* 3242 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 3243 * memory to insure that the chip has in fact read the first 3244 * entry of the ring. 3245 */ 3246 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 3247 u_int32_t v, i; 3248 for (i = 0; i < 10; i++) { 3249 DELAY(20); 3250 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 3251 if (v == (MCLBYTES - ETHER_ALIGN)) 3252 break; 3253 } 3254 if (i == 10) 3255 printf("%s: 5705 A0 chip failed to load RX ring\n", 3256 sc->bge_dev.dv_xname); 3257 } 3258 3259 /* Init Jumbo RX ring. */ 3260 if (BGE_IS_JUMBO_CAPABLE(sc)) 3261 bge_init_rx_ring_jumbo(sc); 3262 3263 /* Init our RX return ring index */ 3264 sc->bge_rx_saved_considx = 0; 3265 3266 /* Init our RX/TX stat counters. */ 3267 sc->bge_tx_collisions = 0; 3268 sc->bge_rx_discards = 0; 3269 sc->bge_rx_inerrors = 0; 3270 sc->bge_rx_overruns = 0; 3271 sc->bge_tx_discards = 0; 3272 3273 /* Init TX ring. */ 3274 bge_init_tx_ring(sc); 3275 3276 /* Turn on transmitter */ 3277 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 3278 3279 rxmode = BGE_RXMODE_ENABLE; 3280 3281 if (BGE_IS_5755_PLUS(sc)) 3282 rxmode |= BGE_RXMODE_RX_IPV6_CSUM_ENABLE; 3283 3284 /* Turn on receiver */ 3285 BGE_SETBIT(sc, BGE_RX_MODE, rxmode); 3286 3287 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2); 3288 3289 /* Tell firmware we're alive. */ 3290 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3291 3292 /* Enable host interrupts. */ 3293 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 3294 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 3295 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 3296 3297 bge_ifmedia_upd(ifp); 3298 3299 ifp->if_flags |= IFF_RUNNING; 3300 ifp->if_flags &= ~IFF_OACTIVE; 3301 3302 splx(s); 3303 3304 timeout_add_sec(&sc->bge_timeout, 1); 3305 } 3306 3307 /* 3308 * Set media options. 3309 */ 3310 int 3311 bge_ifmedia_upd(struct ifnet *ifp) 3312 { 3313 struct bge_softc *sc = ifp->if_softc; 3314 struct mii_data *mii = &sc->bge_mii; 3315 struct ifmedia *ifm = &sc->bge_ifmedia; 3316 3317 /* If this is a 1000baseX NIC, enable the TBI port. */ 3318 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 3319 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 3320 return (EINVAL); 3321 switch(IFM_SUBTYPE(ifm->ifm_media)) { 3322 case IFM_AUTO: 3323 /* 3324 * The BCM5704 ASIC appears to have a special 3325 * mechanism for programming the autoneg 3326 * advertisement registers in TBI mode. 3327 */ 3328 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 3329 u_int32_t sgdig; 3330 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 3331 if (sgdig & BGE_SGDIGSTS_DONE) { 3332 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 3333 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 3334 sgdig |= BGE_SGDIGCFG_AUTO | 3335 BGE_SGDIGCFG_PAUSE_CAP | 3336 BGE_SGDIGCFG_ASYM_PAUSE; 3337 CSR_WRITE_4(sc, BGE_SGDIG_CFG, 3338 sgdig | BGE_SGDIGCFG_SEND); 3339 DELAY(5); 3340 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig); 3341 } 3342 } 3343 break; 3344 case IFM_1000_SX: 3345 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3346 BGE_CLRBIT(sc, BGE_MAC_MODE, 3347 BGE_MACMODE_HALF_DUPLEX); 3348 } else { 3349 BGE_SETBIT(sc, BGE_MAC_MODE, 3350 BGE_MACMODE_HALF_DUPLEX); 3351 } 3352 break; 3353 default: 3354 return (EINVAL); 3355 } 3356 /* XXX 802.3x flow control for 1000BASE-SX */ 3357 return (0); 3358 } 3359 3360 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 3361 if (mii->mii_instance) { 3362 struct mii_softc *miisc; 3363 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 3364 mii_phy_reset(miisc); 3365 } 3366 mii_mediachg(mii); 3367 3368 /* 3369 * Force an interrupt so that we will call bge_link_upd 3370 * if needed and clear any pending link state attention. 3371 * Without this we are not getting any further interrupts 3372 * for link state changes and thus will not UP the link and 3373 * not be able to send in bge_start. The only way to get 3374 * things working was to receive a packet and get a RX intr. 3375 */ 3376 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3377 sc->bge_flags & BGE_IS_5788) 3378 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 3379 else 3380 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 3381 3382 return (0); 3383 } 3384 3385 /* 3386 * Report current media status. 3387 */ 3388 void 3389 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3390 { 3391 struct bge_softc *sc = ifp->if_softc; 3392 struct mii_data *mii = &sc->bge_mii; 3393 3394 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 3395 ifmr->ifm_status = IFM_AVALID; 3396 ifmr->ifm_active = IFM_ETHER; 3397 if (CSR_READ_4(sc, BGE_MAC_STS) & 3398 BGE_MACSTAT_TBI_PCS_SYNCHED) { 3399 ifmr->ifm_status |= IFM_ACTIVE; 3400 } else { 3401 ifmr->ifm_active |= IFM_NONE; 3402 return; 3403 } 3404 ifmr->ifm_active |= IFM_1000_SX; 3405 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 3406 ifmr->ifm_active |= IFM_HDX; 3407 else 3408 ifmr->ifm_active |= IFM_FDX; 3409 return; 3410 } 3411 3412 mii_pollstat(mii); 3413 ifmr->ifm_status = mii->mii_media_status; 3414 ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) | 3415 sc->bge_flowflags; 3416 } 3417 3418 int 3419 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3420 { 3421 struct bge_softc *sc = ifp->if_softc; 3422 struct ifaddr *ifa = (struct ifaddr *) data; 3423 struct ifreq *ifr = (struct ifreq *) data; 3424 int s, error = 0; 3425 struct mii_data *mii; 3426 3427 s = splnet(); 3428 3429 switch(command) { 3430 case SIOCSIFADDR: 3431 ifp->if_flags |= IFF_UP; 3432 if (!(ifp->if_flags & IFF_RUNNING)) 3433 bge_init(sc); 3434 #ifdef INET 3435 if (ifa->ifa_addr->sa_family == AF_INET) 3436 arp_ifinit(&sc->arpcom, ifa); 3437 #endif /* INET */ 3438 break; 3439 3440 case SIOCSIFFLAGS: 3441 if (ifp->if_flags & IFF_UP) { 3442 if (ifp->if_flags & IFF_RUNNING) 3443 error = ENETRESET; 3444 else 3445 bge_init(sc); 3446 } else { 3447 if (ifp->if_flags & IFF_RUNNING) 3448 bge_stop(sc); 3449 } 3450 break; 3451 3452 case SIOCSIFMEDIA: 3453 /* XXX Flow control is not supported for 1000BASE-SX */ 3454 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 3455 ifr->ifr_media &= ~IFM_ETH_FMASK; 3456 sc->bge_flowflags = 0; 3457 } 3458 3459 /* Flow control requires full-duplex mode. */ 3460 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 3461 (ifr->ifr_media & IFM_FDX) == 0) { 3462 ifr->ifr_media &= ~IFM_ETH_FMASK; 3463 } 3464 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 3465 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 3466 /* We can do both TXPAUSE and RXPAUSE. */ 3467 ifr->ifr_media |= 3468 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 3469 } 3470 sc->bge_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 3471 } 3472 /* FALLTHROUGH */ 3473 case SIOCGIFMEDIA: 3474 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 3475 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 3476 command); 3477 } else { 3478 mii = &sc->bge_mii; 3479 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 3480 command); 3481 } 3482 break; 3483 3484 default: 3485 error = ether_ioctl(ifp, &sc->arpcom, command, data); 3486 } 3487 3488 if (error == ENETRESET) { 3489 if (ifp->if_flags & IFF_RUNNING) 3490 bge_iff(sc); 3491 error = 0; 3492 } 3493 3494 splx(s); 3495 return (error); 3496 } 3497 3498 void 3499 bge_watchdog(struct ifnet *ifp) 3500 { 3501 struct bge_softc *sc; 3502 3503 sc = ifp->if_softc; 3504 3505 printf("%s: watchdog timeout -- resetting\n", sc->bge_dev.dv_xname); 3506 3507 bge_init(sc); 3508 3509 ifp->if_oerrors++; 3510 } 3511 3512 void 3513 bge_stop_block(struct bge_softc *sc, bus_size_t reg, u_int32_t bit) 3514 { 3515 int i; 3516 3517 BGE_CLRBIT(sc, reg, bit); 3518 3519 for (i = 0; i < BGE_TIMEOUT; i++) { 3520 if ((CSR_READ_4(sc, reg) & bit) == 0) 3521 return; 3522 delay(100); 3523 } 3524 3525 DPRINTFN(5, ("%s: block failed to stop: reg 0x%lx, bit 0x%08x\n", 3526 sc->bge_dev.dv_xname, (u_long) reg, bit)); 3527 } 3528 3529 /* 3530 * Stop the adapter and free any mbufs allocated to the 3531 * RX and TX lists. 3532 */ 3533 void 3534 bge_stop(struct bge_softc *sc) 3535 { 3536 struct ifnet *ifp = &sc->arpcom.ac_if; 3537 struct ifmedia_entry *ifm; 3538 struct mii_data *mii; 3539 int mtmp, itmp; 3540 3541 timeout_del(&sc->bge_timeout); 3542 timeout_del(&sc->bge_rxtimeout); 3543 3544 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3545 3546 /* 3547 * Disable all of the receiver blocks 3548 */ 3549 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 3550 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 3551 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 3552 if (BGE_IS_5700_FAMILY(sc)) 3553 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 3554 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 3555 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 3556 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 3557 3558 /* 3559 * Disable all of the transmit blocks 3560 */ 3561 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 3562 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 3563 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 3564 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 3565 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 3566 if (BGE_IS_5700_FAMILY(sc)) 3567 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 3568 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 3569 3570 /* 3571 * Shut down all of the memory managers and related 3572 * state machines. 3573 */ 3574 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 3575 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 3576 if (BGE_IS_5700_FAMILY(sc)) 3577 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 3578 3579 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 3580 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 3581 3582 if (BGE_IS_5700_FAMILY(sc)) { 3583 bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 3584 bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 3585 } 3586 3587 /* Disable host interrupts. */ 3588 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 3589 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 3590 3591 /* 3592 * Tell firmware we're shutting down. 3593 */ 3594 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3595 3596 /* Free the RX lists. */ 3597 bge_free_rx_ring_std(sc); 3598 3599 /* Free jumbo RX list. */ 3600 if (BGE_IS_JUMBO_CAPABLE(sc)) 3601 bge_free_rx_ring_jumbo(sc); 3602 3603 /* Free TX buffers. */ 3604 bge_free_tx_ring(sc); 3605 3606 /* 3607 * Isolate/power down the PHY, but leave the media selection 3608 * unchanged so that things will be put back to normal when 3609 * we bring the interface back up. 3610 */ 3611 if (!(sc->bge_flags & BGE_PHY_FIBER_TBI)) { 3612 mii = &sc->bge_mii; 3613 itmp = ifp->if_flags; 3614 ifp->if_flags |= IFF_UP; 3615 ifm = mii->mii_media.ifm_cur; 3616 mtmp = ifm->ifm_media; 3617 ifm->ifm_media = IFM_ETHER|IFM_NONE; 3618 mii_mediachg(mii); 3619 ifm->ifm_media = mtmp; 3620 ifp->if_flags = itmp; 3621 } 3622 3623 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 3624 3625 /* Clear MAC's link state (PHY may still have link UP). */ 3626 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 3627 } 3628 3629 void 3630 bge_link_upd(struct bge_softc *sc) 3631 { 3632 struct ifnet *ifp = &sc->arpcom.ac_if; 3633 struct mii_data *mii = &sc->bge_mii; 3634 u_int32_t status; 3635 int link; 3636 3637 /* Clear 'pending link event' flag */ 3638 BGE_STS_CLRBIT(sc, BGE_STS_LINK_EVT); 3639 3640 /* 3641 * Process link state changes. 3642 * Grrr. The link status word in the status block does 3643 * not work correctly on the BCM5700 rev AX and BX chips, 3644 * according to all available information. Hence, we have 3645 * to enable MII interrupts in order to properly obtain 3646 * async link changes. Unfortunately, this also means that 3647 * we have to read the MAC status register to detect link 3648 * changes, thereby adding an additional register access to 3649 * the interrupt handler. 3650 * 3651 */ 3652 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) { 3653 status = CSR_READ_4(sc, BGE_MAC_STS); 3654 if (status & BGE_MACSTAT_MI_INTERRUPT) { 3655 mii_pollstat(mii); 3656 3657 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 3658 mii->mii_media_status & IFM_ACTIVE && 3659 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 3660 BGE_STS_SETBIT(sc, BGE_STS_LINK); 3661 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 3662 (!(mii->mii_media_status & IFM_ACTIVE) || 3663 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 3664 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 3665 3666 /* Clear the interrupt */ 3667 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 3668 BGE_EVTENB_MI_INTERRUPT); 3669 bge_miibus_readreg(&sc->bge_dev, 1, BRGPHY_MII_ISR); 3670 bge_miibus_writereg(&sc->bge_dev, 1, BRGPHY_MII_IMR, 3671 BRGPHY_INTRS); 3672 } 3673 return; 3674 } 3675 3676 if (sc->bge_flags & BGE_PHY_FIBER_TBI) { 3677 status = CSR_READ_4(sc, BGE_MAC_STS); 3678 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 3679 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) { 3680 BGE_STS_SETBIT(sc, BGE_STS_LINK); 3681 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 3682 BGE_CLRBIT(sc, BGE_MAC_MODE, 3683 BGE_MACMODE_TBI_SEND_CFGS); 3684 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 3685 status = CSR_READ_4(sc, BGE_MAC_MODE); 3686 ifp->if_link_state = 3687 (status & BGE_MACMODE_HALF_DUPLEX) ? 3688 LINK_STATE_HALF_DUPLEX : 3689 LINK_STATE_FULL_DUPLEX; 3690 if_link_state_change(ifp); 3691 ifp->if_baudrate = IF_Gbps(1); 3692 } 3693 } else if (BGE_STS_BIT(sc, BGE_STS_LINK)) { 3694 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 3695 ifp->if_link_state = LINK_STATE_DOWN; 3696 if_link_state_change(ifp); 3697 ifp->if_baudrate = 0; 3698 } 3699 /* 3700 * Discard link events for MII/GMII cards if MI auto-polling disabled. 3701 * This should not happen since mii callouts are locked now, but 3702 * we keep this check for debug. 3703 */ 3704 } else if (BGE_STS_BIT(sc, BGE_STS_AUTOPOLL)) { 3705 /* 3706 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit 3707 * in status word always set. Workaround this bug by reading 3708 * PHY link status directly. 3709 */ 3710 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK)? 3711 BGE_STS_LINK : 0; 3712 3713 if (BGE_STS_BIT(sc, BGE_STS_LINK) != link) { 3714 mii_pollstat(mii); 3715 3716 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 3717 mii->mii_media_status & IFM_ACTIVE && 3718 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 3719 BGE_STS_SETBIT(sc, BGE_STS_LINK); 3720 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 3721 (!(mii->mii_media_status & IFM_ACTIVE) || 3722 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 3723 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 3724 } 3725 } 3726 3727 /* Clear the attention */ 3728 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 3729 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 3730 BGE_MACSTAT_LINK_CHANGED); 3731 } 3732