1 /* $OpenBSD: if_bge.c,v 1.4 2001/12/24 18:30:43 mickey Exp $ */ 2 /* 3 * Copyright (c) 2001 Wind River Systems 4 * Copyright (c) 1997, 1998, 1999, 2001 5 * Bill Paul <wpaul@windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.2 2001/09/28 18:56:57 wpaul Exp $ 35 */ 36 37 /* 38 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD. 39 * 40 * Written by Bill Paul <wpaul@windriver.com> 41 * Senior Engineer, Wind River Systems 42 */ 43 44 /* 45 * The Broadcom BCM5700 is based on technology originally developed by 46 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 47 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 48 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 49 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 50 * frames, highly configurable RX filtering, and 16 RX and TX queues 51 * (which, along with RX filter rules, can be used for QOS applications). 52 * Other features, such as TCP segmentation, may be available as part 53 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 54 * firmware images can be stored in hardware and need not be compiled 55 * into the driver. 56 * 57 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 58 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus. 59 * 60 * The BCM5701 is a single-chip solution incorporating both the BCM5700 61 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5700 62 * does not support external SSRAM. 63 * 64 * Broadcom also produces a variation of the BCM5700 under the "Altima" 65 * brand name, which is functionally similar but lacks PCI-X support. 66 * 67 * Without external SSRAM, you can only have at most 4 TX rings, 68 * and the use of the mini RX ring is disabled. This seems to imply 69 * that these features are simply not available on the BCM5701. As a 70 * result, this driver does not implement any support for the mini RX 71 * ring. 72 */ 73 74 #include "bpfilter.h" 75 #include "vlan.h" 76 77 #include <sys/param.h> 78 #include <sys/systm.h> 79 #include <sys/sockio.h> 80 #include <sys/mbuf.h> 81 #include <sys/malloc.h> 82 #include <sys/kernel.h> 83 #include <sys/device.h> 84 #include <sys/socket.h> 85 86 #include <net/if.h> 87 #include <net/if_dl.h> 88 #include <net/if_media.h> 89 90 #ifdef INET 91 #include <netinet/in.h> 92 #include <netinet/in_systm.h> 93 #include <netinet/in_var.h> 94 #include <netinet/ip.h> 95 #include <netinet/if_ether.h> 96 #endif 97 98 #if NVLAN > 0 99 #include <net/if_types.h> 100 #include <net/if_vlan_var.h> 101 #endif 102 103 #if NBPFILTER > 0 104 #include <net/bpf.h> 105 #endif 106 107 #include <dev/pci/pcireg.h> 108 #include <dev/pci/pcivar.h> 109 #include <dev/pci/pcidevs.h> 110 111 #include <dev/mii/mii.h> 112 #include <dev/mii/miivar.h> 113 #include <dev/mii/miidevs.h> 114 #include <dev/mii/brgphyreg.h> 115 116 #include <dev/pci/if_bgereg.h> 117 118 /* #define BGE_CHECKSUM */ 119 120 int bge_probe __P((struct device *, void *, void *)); 121 void bge_attach __P((struct device *, struct device *, void *)); 122 void bge_release_resources __P((struct bge_softc *)); 123 void bge_txeof __P((struct bge_softc *)); 124 void bge_rxeof __P((struct bge_softc *)); 125 126 void bge_tick __P((void *)); 127 void bge_stats_update __P((struct bge_softc *)); 128 int bge_encap __P((struct bge_softc *, struct mbuf *, u_int32_t *)); 129 130 int bge_intr __P((void *)); 131 void bge_start __P((struct ifnet *)); 132 int bge_ioctl __P((struct ifnet *, u_long, caddr_t)); 133 void bge_init __P((void *)); 134 void bge_stop __P((struct bge_softc *)); 135 void bge_watchdog __P((struct ifnet *)); 136 void bge_shutdown __P((void *)); 137 int bge_ifmedia_upd __P((struct ifnet *)); 138 void bge_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 139 140 u_int8_t bge_eeprom_getbyte __P((struct bge_softc *, 141 int, u_int8_t *)); 142 int bge_read_eeprom __P((struct bge_softc *, caddr_t, int, int)); 143 144 u_int32_t bge_crc __P((struct bge_softc *, caddr_t)); 145 void bge_setmulti __P((struct bge_softc *)); 146 147 void bge_handle_events __P((struct bge_softc *)); 148 int bge_alloc_jumbo_mem __P((struct bge_softc *)); 149 void bge_free_jumbo_mem __P((struct bge_softc *)); 150 void *bge_jalloc __P((struct bge_softc *)); 151 void bge_jfree __P((caddr_t, u_int, void *)); 152 int bge_newbuf_std __P((struct bge_softc *, int, struct mbuf *)); 153 int bge_newbuf_jumbo __P((struct bge_softc *, int, struct mbuf *)); 154 int bge_init_rx_ring_std __P((struct bge_softc *)); 155 void bge_free_rx_ring_std __P((struct bge_softc *)); 156 int bge_init_rx_ring_jumbo __P((struct bge_softc *)); 157 void bge_free_rx_ring_jumbo __P((struct bge_softc *)); 158 void bge_free_tx_ring __P((struct bge_softc *)); 159 int bge_init_tx_ring __P((struct bge_softc *)); 160 161 int bge_chipinit __P((struct bge_softc *)); 162 int bge_blockinit __P((struct bge_softc *)); 163 164 u_int8_t bge_vpd_readbyte __P((struct bge_softc *, int)); 165 void bge_vpd_read_res __P((struct bge_softc *, struct vpd_res *, int)); 166 void bge_vpd_read __P((struct bge_softc *)); 167 168 u_int32_t bge_readmem_ind __P((struct bge_softc *, int)); 169 void bge_writemem_ind __P((struct bge_softc *, int, int)); 170 #ifdef notdef 171 u_int32_t bge_readreg_ind __P((struct bge_softc *, int)); 172 #endif 173 void bge_writereg_ind __P((struct bge_softc *, int, int)); 174 175 int bge_miibus_readreg __P((struct device *, int, int)); 176 void bge_miibus_writereg __P((struct device *, int, int, int)); 177 void bge_miibus_statchg __P((struct device *)); 178 179 void bge_reset __P((struct bge_softc *)); 180 void bge_phy_hack __P((struct bge_softc *)); 181 182 #define BGE_DEBUG 183 #ifdef BGE_DEBUG 184 #define DPRINTF(x) if (bgedebug) printf x 185 #define DPRINTFN(n,x) if (bgedebug >= (n)) printf x 186 int bgedebug = 0; 187 #else 188 #define DPRINTF(x) 189 #define DPRINTFN(n,x) 190 #endif 191 192 u_int32_t 193 bge_readmem_ind(sc, off) 194 struct bge_softc *sc; 195 int off; 196 { 197 struct pci_attach_args *pa = &(sc->bge_pa); 198 199 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_BASEADDR, off); 200 return (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_DATA)); 201 } 202 203 void 204 bge_writemem_ind(sc, off, val) 205 struct bge_softc *sc; 206 int off, val; 207 { 208 struct pci_attach_args *pa = &(sc->bge_pa); 209 210 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_BASEADDR, off); 211 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_DATA, val); 212 } 213 214 #ifdef notdef 215 u_int32_t 216 bge_readreg_ind(sc, off) 217 struct bge_softc *sc; 218 int off; 219 { 220 struct pci_attach_args *pa = &(sc->bge_pa); 221 222 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_BASEADDR, off); 223 return(pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_DATA)); 224 } 225 #endif 226 227 void 228 bge_writereg_ind(sc, off, val) 229 struct bge_softc *sc; 230 int off, val; 231 { 232 struct pci_attach_args *pa = &(sc->bge_pa); 233 234 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_BASEADDR, off); 235 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_DATA, val); 236 } 237 238 u_int8_t 239 bge_vpd_readbyte(sc, addr) 240 struct bge_softc *sc; 241 int addr; 242 { 243 int i; 244 u_int32_t val; 245 struct pci_attach_args *pa = &(sc->bge_pa); 246 247 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_ADDR, addr); 248 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 249 DELAY(10); 250 if (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_ADDR) & 251 BGE_VPD_FLAG) 252 break; 253 } 254 255 if (i == BGE_TIMEOUT) { 256 printf("%s: VPD read timed out\n", sc->bge_dev.dv_xname); 257 return(0); 258 } 259 260 val = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_DATA); 261 262 return((val >> ((addr % 4) * 8)) & 0xFF); 263 } 264 265 void 266 bge_vpd_read_res(sc, res, addr) 267 struct bge_softc *sc; 268 struct vpd_res *res; 269 int addr; 270 { 271 int i; 272 u_int8_t *ptr; 273 274 ptr = (u_int8_t *)res; 275 for (i = 0; i < sizeof(struct vpd_res); i++) 276 ptr[i] = bge_vpd_readbyte(sc, i + addr); 277 } 278 279 void 280 bge_vpd_read(sc) 281 struct bge_softc *sc; 282 { 283 int pos = 0, i; 284 struct vpd_res res; 285 286 if (sc->bge_vpd_prodname != NULL) 287 free(sc->bge_vpd_prodname, M_DEVBUF); 288 if (sc->bge_vpd_readonly != NULL) 289 free(sc->bge_vpd_readonly, M_DEVBUF); 290 sc->bge_vpd_prodname = NULL; 291 sc->bge_vpd_readonly = NULL; 292 293 bge_vpd_read_res(sc, &res, pos); 294 295 if (res.vr_id != VPD_RES_ID) { 296 printf("%s: bad VPD resource id: expected %x got %x\n", 297 sc->bge_dev.dv_xname, VPD_RES_ID, res.vr_id); 298 return; 299 } 300 301 pos += sizeof(res); 302 sc->bge_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 303 for (i = 0; i < res.vr_len; i++) 304 sc->bge_vpd_prodname[i] = bge_vpd_readbyte(sc, i + pos); 305 sc->bge_vpd_prodname[i] = '\0'; 306 pos += i; 307 308 bge_vpd_read_res(sc, &res, pos); 309 310 if (res.vr_id != VPD_RES_READ) { 311 printf("%s: bad VPD resource id: expected %x got %x\n", 312 sc->bge_dev.dv_xname, VPD_RES_READ, res.vr_id); 313 return; 314 } 315 316 pos += sizeof(res); 317 sc->bge_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 318 for (i = 0; i < res.vr_len + 1; i++) 319 sc->bge_vpd_readonly[i] = bge_vpd_readbyte(sc, i + pos); 320 } 321 322 /* 323 * Read a byte of data stored in the EEPROM at address 'addr.' The 324 * BCM570x supports both the traditional bitbang interface and an 325 * auto access interface for reading the EEPROM. We use the auto 326 * access method. 327 */ 328 u_int8_t 329 bge_eeprom_getbyte(sc, addr, dest) 330 struct bge_softc *sc; 331 int addr; 332 u_int8_t *dest; 333 { 334 int i; 335 u_int32_t byte = 0; 336 337 /* 338 * Enable use of auto EEPROM access so we can avoid 339 * having to use the bitbang method. 340 */ 341 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 342 343 /* Reset the EEPROM, load the clock period. */ 344 CSR_WRITE_4(sc, BGE_EE_ADDR, 345 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 346 DELAY(20); 347 348 /* Issue the read EEPROM command. */ 349 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 350 351 /* Wait for completion */ 352 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 353 DELAY(10); 354 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 355 break; 356 } 357 358 if (i == BGE_TIMEOUT) { 359 printf("%s: eeprom read timed out\n", sc->bge_dev.dv_xname); 360 return(0); 361 } 362 363 /* Get result. */ 364 byte = CSR_READ_4(sc, BGE_EE_DATA); 365 366 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 367 368 return(0); 369 } 370 371 /* 372 * Read a sequence of bytes from the EEPROM. 373 */ 374 int 375 bge_read_eeprom(sc, dest, off, cnt) 376 struct bge_softc *sc; 377 caddr_t dest; 378 int off; 379 int cnt; 380 { 381 int err = 0, i; 382 u_int8_t byte = 0; 383 384 for (i = 0; i < cnt; i++) { 385 err = bge_eeprom_getbyte(sc, off + i, &byte); 386 if (err) 387 break; 388 *(dest + i) = byte; 389 } 390 391 return(err ? 1 : 0); 392 } 393 394 int 395 bge_miibus_readreg(dev, phy, reg) 396 struct device *dev; 397 int phy, reg; 398 { 399 struct bge_softc *sc = (struct bge_softc *)dev; 400 struct ifnet *ifp; 401 u_int32_t val; 402 int i; 403 404 ifp = &sc->arpcom.ac_if; 405 406 if (ifp->if_flags & IFF_RUNNING) 407 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 408 409 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY| 410 BGE_MIPHY(phy)|BGE_MIREG(reg)); 411 412 for (i = 0; i < BGE_TIMEOUT; i++) { 413 val = CSR_READ_4(sc, BGE_MI_COMM); 414 if (!(val & BGE_MICOMM_BUSY)) 415 break; 416 } 417 418 if (i == BGE_TIMEOUT) { 419 printf("%s: PHY read timed out\n", sc->bge_dev.dv_xname); 420 return(0); 421 } 422 423 val = CSR_READ_4(sc, BGE_MI_COMM); 424 425 if (ifp->if_flags & IFF_RUNNING) 426 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 427 428 if (val & BGE_MICOMM_READFAIL) 429 return(0); 430 431 return(val & 0xFFFF); 432 } 433 434 void 435 bge_miibus_writereg(dev, phy, reg, val) 436 struct device *dev; 437 int phy, reg, val; 438 { 439 struct bge_softc *sc = (struct bge_softc *)dev; 440 int i; 441 442 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY| 443 BGE_MIPHY(phy)|BGE_MIREG(reg)|val); 444 445 for (i = 0; i < BGE_TIMEOUT; i++) { 446 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) 447 break; 448 } 449 450 if (i == BGE_TIMEOUT) { 451 printf("%s: PHY read timed out\n", sc->bge_dev.dv_xname); 452 } 453 } 454 455 void 456 bge_miibus_statchg(dev) 457 struct device *dev; 458 { 459 struct bge_softc *sc = (struct bge_softc *)dev; 460 struct mii_data *mii = &sc->bge_mii; 461 462 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 463 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_TX) { 464 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 465 } else { 466 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 467 } 468 469 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 470 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 471 } else { 472 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 473 } 474 475 bge_phy_hack(sc); 476 } 477 478 /* 479 * Handle events that have triggered interrupts. 480 */ 481 void 482 bge_handle_events(sc) 483 struct bge_softc *sc; 484 { 485 486 return; 487 } 488 489 /* 490 * Memory management for jumbo frames. 491 */ 492 493 int 494 bge_alloc_jumbo_mem(sc) 495 struct bge_softc *sc; 496 { 497 caddr_t ptr, kva; 498 bus_dma_segment_t seg; 499 int i, rseg; 500 struct bge_jpool_entry *entry; 501 502 /* Grab a big chunk o' storage. */ 503 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0, 504 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 505 printf("%s: can't alloc rx buffers\n", sc->bge_dev.dv_xname); 506 return (ENOBUFS); 507 } 508 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, &kva, 509 BUS_DMA_NOWAIT)) { 510 printf("%s: can't map dma buffers (%d bytes)\n", 511 sc->bge_dev.dv_xname, BGE_JMEM); 512 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 513 return (ENOBUFS); 514 } 515 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0, 516 BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) { 517 printf("%s: can't create dma map\n", sc->bge_dev.dv_xname); 518 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 519 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 520 return (ENOBUFS); 521 } 522 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 523 kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) { 524 printf("%s: can't load dma map\n", sc->bge_dev.dv_xname); 525 bus_dmamap_destroy(sc->bge_dmatag, 526 sc->bge_cdata.bge_rx_jumbo_map); 527 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 528 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 529 return (ENOBUFS); 530 } 531 sc->bge_cdata.bge_jumbo_buf = (caddr_t)kva; 532 DPRINTFN(1,("bge_jumbo_buf = 0x%08X\n", sc->bge_cdata.bge_jumbo_buf)); 533 534 LIST_INIT(&sc->bge_jfree_listhead); 535 LIST_INIT(&sc->bge_jinuse_listhead); 536 537 /* 538 * Now divide it up into 9K pieces and save the addresses 539 * in an array. 540 */ 541 ptr = sc->bge_cdata.bge_jumbo_buf; 542 for (i = 0; i < BGE_JSLOTS; i++) { 543 sc->bge_cdata.bge_jslots[i] = ptr; 544 ptr += BGE_JLEN; 545 entry = malloc(sizeof(struct bge_jpool_entry), 546 M_DEVBUF, M_NOWAIT); 547 if (entry == NULL) { 548 bus_dmamap_unload(sc->bge_dmatag, 549 sc->bge_cdata.bge_rx_jumbo_map); 550 bus_dmamap_destroy(sc->bge_dmatag, 551 sc->bge_cdata.bge_rx_jumbo_map); 552 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 553 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 554 sc->bge_cdata.bge_jumbo_buf = NULL; 555 printf("%s: no memory for jumbo buffer queue!\n", 556 sc->bge_dev.dv_xname); 557 return(ENOBUFS); 558 } 559 entry->slot = i; 560 LIST_INSERT_HEAD(&sc->bge_jfree_listhead, 561 entry, jpool_entries); 562 } 563 564 return(0); 565 } 566 567 /* 568 * Allocate a jumbo buffer. 569 */ 570 void * 571 bge_jalloc(sc) 572 struct bge_softc *sc; 573 { 574 struct bge_jpool_entry *entry; 575 576 entry = LIST_FIRST(&sc->bge_jfree_listhead); 577 578 if (entry == NULL) { 579 printf("%s: no free jumbo buffers\n", sc->bge_dev.dv_xname); 580 return(NULL); 581 } 582 583 LIST_REMOVE(entry, jpool_entries); 584 LIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 585 return(sc->bge_cdata.bge_jslots[entry->slot]); 586 } 587 588 /* 589 * Release a jumbo buffer. 590 */ 591 void 592 bge_jfree(buf, size, arg) 593 caddr_t buf; 594 u_int size; 595 void *arg; 596 { 597 struct bge_jpool_entry *entry; 598 struct bge_softc *sc; 599 int i; 600 601 /* Extract the softc struct pointer. */ 602 sc = (struct bge_softc *)arg; 603 604 if (sc == NULL) 605 panic("bge_jfree: can't find softc pointer!"); 606 607 /* calculate the slot this buffer belongs to */ 608 609 i = ((vm_offset_t)buf 610 - (vm_offset_t)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 611 612 if ((i < 0) || (i >= BGE_JSLOTS)) 613 panic("bge_jfree: asked to free buffer that we don't manage!"); 614 615 entry = LIST_FIRST(&sc->bge_jinuse_listhead); 616 if (entry == NULL) 617 panic("bge_jfree: buffer not in use!"); 618 entry->slot = i; 619 LIST_REMOVE(entry, jpool_entries); 620 LIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 621 } 622 623 624 /* 625 * Intialize a standard receive ring descriptor. 626 */ 627 int 628 bge_newbuf_std(sc, i, m) 629 struct bge_softc *sc; 630 int i; 631 struct mbuf *m; 632 { 633 struct mbuf *m_new = NULL; 634 struct bge_rx_bd *r; 635 bus_dmamap_t rxmap = sc->bge_cdata.bge_rx_std_map[i]; 636 637 if (m == NULL) { 638 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 639 if (m_new == NULL) { 640 printf("%s: mbuf allocation failed " 641 "-- packet dropped!\n", sc->bge_dev.dv_xname); 642 return(ENOBUFS); 643 } 644 645 MCLGET(m_new, M_DONTWAIT); 646 if (!(m_new->m_flags & M_EXT)) { 647 printf("%s: cluster allocation failed " 648 "-- packet dropped!\n", sc->bge_dev.dv_xname); 649 m_freem(m_new); 650 return(ENOBUFS); 651 } 652 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 653 } else { 654 m_new = m; 655 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 656 m_new->m_data = m_new->m_ext.ext_buf; 657 } 658 659 if (bus_dmamap_load_mbuf(sc->bge_dmatag, rxmap, m_new, BUS_DMA_NOWAIT)) 660 return(ENOBUFS); 661 662 m_adj(m_new, ETHER_ALIGN); 663 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 664 r = &sc->bge_rdata->bge_rx_std_ring[i]; 665 BGE_HOSTADDR(r->bge_addr) = rxmap->dm_segs[0].ds_addr + ETHER_ALIGN; 666 r->bge_flags = BGE_RXBDFLAG_END; 667 r->bge_len = m_new->m_len; 668 r->bge_idx = i; 669 670 return(0); 671 } 672 673 /* 674 * Initialize a jumbo receive ring descriptor. This allocates 675 * a jumbo buffer from the pool managed internally by the driver. 676 */ 677 int 678 bge_newbuf_jumbo(sc, i, m) 679 struct bge_softc *sc; 680 int i; 681 struct mbuf *m; 682 { 683 struct mbuf *m_new = NULL; 684 struct bge_rx_bd *r; 685 686 if (m == NULL) { 687 caddr_t *buf = NULL; 688 689 /* Allocate the mbuf. */ 690 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 691 if (m_new == NULL) { 692 printf("%s: mbuf allocation failed " 693 "-- packet dropped!\n", sc->bge_dev.dv_xname); 694 return(ENOBUFS); 695 } 696 697 /* Allocate the jumbo buffer */ 698 buf = bge_jalloc(sc); 699 if (buf == NULL) { 700 m_freem(m_new); 701 printf("%s: jumbo allocation failed " 702 "-- packet dropped!\n", sc->bge_dev.dv_xname); 703 return(ENOBUFS); 704 } 705 706 /* Attach the buffer to the mbuf. */ 707 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 708 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, 0, bge_jfree, sc); 709 } else { 710 m_new = m; 711 m_new->m_data = m_new->m_ext.ext_buf; 712 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 713 } 714 715 m_adj(m_new, ETHER_ALIGN); 716 /* Set up the descriptor. */ 717 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 718 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 719 BGE_HOSTADDR(r->bge_addr) = 720 BGE_JUMBO_DMA_ADDR(sc, m_new) + ETHER_ALIGN; 721 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 722 r->bge_len = m_new->m_len; 723 r->bge_idx = i; 724 725 return(0); 726 } 727 728 /* 729 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 730 * that's 1MB or memory, which is a lot. For now, we fill only the first 731 * 256 ring entries and hope that our CPU is fast enough to keep up with 732 * the NIC. 733 */ 734 int 735 bge_init_rx_ring_std(sc) 736 struct bge_softc *sc; 737 { 738 int i; 739 740 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 741 if (bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, MCLBYTES, 742 0, BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_std_map[i])) 743 return(ENOBUFS); 744 } 745 746 for (i = 0; i < BGE_SSLOTS; i++) { 747 if (bge_newbuf_std(sc, i, NULL) == ENOBUFS) 748 return(ENOBUFS); 749 } 750 751 sc->bge_std = i - 1; 752 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 753 754 return(0); 755 } 756 757 void 758 bge_free_rx_ring_std(sc) 759 struct bge_softc *sc; 760 { 761 int i; 762 763 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 764 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 765 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 766 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 767 bus_dmamap_unload(sc->bge_dmatag, 768 sc->bge_cdata.bge_rx_std_map[i]); 769 } 770 bzero((char *)&sc->bge_rdata->bge_rx_std_ring[i], 771 sizeof(struct bge_rx_bd)); 772 } 773 } 774 775 int 776 bge_init_rx_ring_jumbo(sc) 777 struct bge_softc *sc; 778 { 779 int i; 780 struct bge_rcb *rcb; 781 struct bge_rcb_opaque *rcbo; 782 783 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 784 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 785 return(ENOBUFS); 786 }; 787 788 sc->bge_jumbo = i - 1; 789 790 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 791 rcbo = (struct bge_rcb_opaque *)rcb; 792 rcb->bge_flags = 0; 793 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcbo->bge_reg2); 794 795 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 796 797 return(0); 798 } 799 800 void 801 bge_free_rx_ring_jumbo(sc) 802 struct bge_softc *sc; 803 { 804 int i; 805 806 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 807 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 808 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 809 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 810 } 811 bzero((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 812 sizeof(struct bge_rx_bd)); 813 } 814 } 815 816 void 817 bge_free_tx_ring(sc) 818 struct bge_softc *sc; 819 { 820 int i; 821 822 if (sc->bge_rdata->bge_tx_ring == NULL) 823 return; 824 825 for (i = 0; i < BGE_TX_RING_CNT; i++) { 826 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 827 m_freem(sc->bge_cdata.bge_tx_chain[i]); 828 sc->bge_cdata.bge_tx_chain[i] = NULL; 829 bus_dmamap_unload(sc->bge_dmatag, 830 sc->bge_cdata.bge_tx_map[i]); 831 } 832 bzero((char *)&sc->bge_rdata->bge_tx_ring[i], 833 sizeof(struct bge_tx_bd)); 834 } 835 } 836 837 int 838 bge_init_tx_ring(sc) 839 struct bge_softc *sc; 840 { 841 int i; 842 843 sc->bge_txcnt = 0; 844 sc->bge_tx_saved_considx = 0; 845 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 846 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 847 848 for (i = 0; i < BGE_TX_RING_CNT; i++) { 849 if (bus_dmamap_create(sc->bge_dmatag, MCLBYTES, BGE_NTXSEG, 850 MCLBYTES, 0, BUS_DMA_NOWAIT, &sc->bge_cdata.bge_tx_map[i])) 851 return(ENOBUFS); 852 } 853 854 return(0); 855 } 856 857 #define BGE_POLY 0xEDB88320 858 859 u_int32_t 860 bge_crc(sc, addr) 861 struct bge_softc *sc; 862 caddr_t addr; 863 { 864 u_int32_t idx, bit, data, crc; 865 866 /* Compute CRC for the address value. */ 867 crc = 0xFFFFFFFF; /* initial value */ 868 869 for (idx = 0; idx < 6; idx++) { 870 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 871 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? BGE_POLY : 0); 872 } 873 874 return(crc & 0x7F); 875 } 876 877 void 878 bge_setmulti(sc) 879 struct bge_softc *sc; 880 { 881 struct arpcom *ac = &sc->arpcom; 882 struct ifnet *ifp = &ac->ac_if; 883 struct ether_multi *enm; 884 struct ether_multistep step; 885 u_int32_t hashes[4] = { 0, 0, 0, 0 }; 886 u_int32_t h; 887 int i; 888 889 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 890 for (i = 0; i < 4; i++) 891 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF); 892 return; 893 } 894 895 /* First, zot all the existing filters. */ 896 for (i = 0; i < 4; i++) 897 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0); 898 899 /* Now program new ones. */ 900 ETHER_FIRST_MULTI(step, ac, enm); 901 while (enm != NULL) { 902 h = bge_crc(sc, LLADDR((struct sockaddr_dl *)enm->enm_addrlo)); 903 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 904 ETHER_NEXT_MULTI(step, enm); 905 } 906 907 for (i = 0; i < 4; i++) 908 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 909 } 910 911 /* 912 * Do endian, PCI and DMA initialization. Also check the on-board ROM 913 * self-test results. 914 */ 915 int 916 bge_chipinit(sc) 917 struct bge_softc *sc; 918 { 919 u_int32_t cachesize; 920 int i; 921 struct pci_attach_args *pa = &(sc->bge_pa); 922 923 #ifdef BGE_CHECKSUM 924 sc->arpcom.ac_if.if_capabilities = 925 IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 926 #endif 927 928 /* Set endianness before we access any non-PCI registers. */ 929 #if BYTE_ORDER == BIG_ENDIAN 930 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL, 931 BGE_BIGENDIAN_INIT); 932 #else 933 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL, 934 BGE_LITTLEENDIAN_INIT); 935 #endif 936 937 /* 938 * Check the 'ROM failed' bit on the RX CPU to see if 939 * self-tests passed. 940 */ 941 if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) { 942 printf("%s: RX CPU self-diagnostics failed!\n", 943 sc->bge_dev.dv_xname); 944 return(ENODEV); 945 } 946 947 /* Clear the MAC control register */ 948 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 949 950 /* 951 * Clear the MAC statistics block in the NIC's 952 * internal memory. 953 */ 954 for (i = BGE_STATS_BLOCK; 955 i < BGE_STATS_BLOCK_END + 1; i += sizeof(u_int32_t)) 956 BGE_MEMWIN_WRITE(pa->pa_pc, pa->pa_tag, i, 0); 957 958 for (i = BGE_STATUS_BLOCK; 959 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(u_int32_t)) 960 BGE_MEMWIN_WRITE(pa->pa_pc, pa->pa_tag, i, 0); 961 962 /* Set up the PCI DMA control register. */ 963 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 964 BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD|0x0F); 965 966 /* 967 * Set up general mode register. 968 */ 969 #ifndef BGE_CHECKSUM 970 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_WORDSWAP_NONFRAME| 971 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 972 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS| 973 BGE_MODECTL_NO_RX_CRC); 974 #else 975 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_WORDSWAP_NONFRAME| 976 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 977 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS| 978 BGE_MODECTL_NO_RX_CRC 979 /* |BGE_MODECTL_TX_NO_PHDR_CSUM| */ 980 /* BGE_MODECTL_RX_NO_PHDR_CSUM */ 981 ); 982 #endif 983 984 /* Get cache line size. */ 985 cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ); 986 987 /* 988 * Avoid violating PCI spec on certain chip revs. 989 */ 990 if (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD) & 991 PCIM_CMD_MWIEN) { 992 switch(cachesize) { 993 case 1: 994 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 995 BGE_PCI_WRITE_BNDRY_16BYTES); 996 break; 997 case 2: 998 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 999 BGE_PCI_WRITE_BNDRY_32BYTES); 1000 break; 1001 case 4: 1002 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1003 BGE_PCI_WRITE_BNDRY_64BYTES); 1004 break; 1005 case 8: 1006 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1007 BGE_PCI_WRITE_BNDRY_128BYTES); 1008 break; 1009 case 16: 1010 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1011 BGE_PCI_WRITE_BNDRY_256BYTES); 1012 break; 1013 case 32: 1014 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1015 BGE_PCI_WRITE_BNDRY_512BYTES); 1016 break; 1017 case 64: 1018 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1019 BGE_PCI_WRITE_BNDRY_1024BYTES); 1020 break; 1021 default: 1022 /* Disable PCI memory write and invalidate. */ 1023 #if 0 1024 if (bootverbose) 1025 printf("%s: cache line size %d not " 1026 "supported; disabling PCI MWI\n", 1027 sc->bge_dev.dv_xname, cachesize); 1028 #endif 1029 PCI_CLRBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD, 1030 PCIM_CMD_MWIEN); 1031 break; 1032 } 1033 } 1034 1035 #ifdef __brokenalpha__ 1036 /* 1037 * Must insure that we do not cross an 8K (bytes) boundary 1038 * for DMA reads. Our highest limit is 1K bytes. This is a 1039 * restriction on some ALPHA platforms with early revision 1040 * 21174 PCI chipsets, such as the AlphaPC 164lx 1041 */ 1042 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 1043 #endif 1044 1045 /* Set the timer prescaler (always 66Mhz) */ 1046 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); 1047 1048 return(0); 1049 } 1050 1051 int 1052 bge_blockinit(sc) 1053 struct bge_softc *sc; 1054 { 1055 struct bge_rcb *rcb; 1056 struct bge_rcb_opaque *rcbo; 1057 vm_offset_t rcb_addr; 1058 int i; 1059 1060 /* 1061 * Initialize the memory window pointer register so that 1062 * we can access the first 32K of internal NIC RAM. This will 1063 * allow us to set up the TX send ring RCBs and the RX return 1064 * ring RCBs, plus other things which live in NIC memory. 1065 */ 1066 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0); 1067 1068 /* Configure mbuf memory pool */ 1069 if (sc->bge_extram) { 1070 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_EXT_SSRAM); 1071 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1072 } else { 1073 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1); 1074 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1075 } 1076 1077 /* Configure DMA resource pool */ 1078 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, BGE_DMA_DESCRIPTORS); 1079 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1080 1081 /* Configure mbuf pool watermarks */ 1082 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 24); 1083 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 24); 1084 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 48); 1085 1086 /* Configure DMA resource watermarks */ 1087 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1088 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1089 1090 /* Enable buffer manager */ 1091 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1092 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN); 1093 1094 /* Poll for buffer manager start indication */ 1095 for (i = 0; i < BGE_TIMEOUT; i++) { 1096 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1097 break; 1098 DELAY(10); 1099 } 1100 1101 if (i == BGE_TIMEOUT) { 1102 printf("%s: buffer manager failed to start\n", 1103 sc->bge_dev.dv_xname); 1104 return(ENXIO); 1105 } 1106 1107 /* Enable flow-through queues */ 1108 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1109 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1110 1111 /* Wait until queue initialization is complete */ 1112 for (i = 0; i < BGE_TIMEOUT; i++) { 1113 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1114 break; 1115 DELAY(10); 1116 } 1117 1118 if (i == BGE_TIMEOUT) { 1119 printf("%s: flow-through queue init failed\n", 1120 sc->bge_dev.dv_xname); 1121 return(ENXIO); 1122 } 1123 1124 /* Initialize the standard RX ring control block */ 1125 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 1126 BGE_HOSTADDR(rcb->bge_hostaddr) = 1127 BGE_RING_DMA_ADDR(sc, bge_rx_std_ring); 1128 rcb->bge_max_len = BGE_MAX_FRAMELEN; 1129 if (sc->bge_extram) 1130 rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS; 1131 else 1132 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1133 rcb->bge_flags = 0; 1134 rcbo = (struct bge_rcb_opaque *)rcb; 1135 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcbo->bge_reg0); 1136 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcbo->bge_reg1); 1137 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcbo->bge_reg2); 1138 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcbo->bge_reg3); 1139 1140 /* 1141 * Initialize the jumbo RX ring control block 1142 * We set the 'ring disabled' bit in the flags 1143 * field until we're actually ready to start 1144 * using this ring (i.e. once we set the MTU 1145 * high enough to require it). 1146 */ 1147 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1148 BGE_HOSTADDR(rcb->bge_hostaddr) = 1149 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring); 1150 rcb->bge_max_len = BGE_MAX_FRAMELEN; 1151 if (sc->bge_extram) 1152 rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS; 1153 else 1154 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1155 rcb->bge_flags = BGE_RCB_FLAG_RING_DISABLED; 1156 1157 rcbo = (struct bge_rcb_opaque *)rcb; 1158 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, rcbo->bge_reg0); 1159 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, rcbo->bge_reg1); 1160 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcbo->bge_reg2); 1161 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcbo->bge_reg3); 1162 1163 /* Set up dummy disabled mini ring RCB */ 1164 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 1165 rcb->bge_flags = BGE_RCB_FLAG_RING_DISABLED; 1166 rcbo = (struct bge_rcb_opaque *)rcb; 1167 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, rcbo->bge_reg2); 1168 1169 /* 1170 * Set the BD ring replentish thresholds. The recommended 1171 * values are 1/8th the number of descriptors allocated to 1172 * each ring. 1173 */ 1174 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, BGE_STD_RX_RING_CNT/8); 1175 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8); 1176 1177 /* 1178 * Disable all unused send rings by setting the 'ring disabled' 1179 * bit in the flags field of all the TX send ring control blocks. 1180 * These are located in NIC memory. 1181 */ 1182 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1183 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 1184 RCB_WRITE_2(sc, rcb_addr, bge_flags, 1185 BGE_RCB_FLAG_RING_DISABLED); 1186 RCB_WRITE_2(sc, rcb_addr, bge_max_len, 0); 1187 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 1188 rcb_addr += sizeof(struct bge_rcb); 1189 } 1190 1191 /* Configure TX RCB 0 (we use only the first ring) */ 1192 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1193 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 1194 RCB_WRITE_4(sc, rcb_addr, BGE_HOSTADDR(bge_hostaddr), 1195 BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 1196 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 1197 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 1198 RCB_WRITE_2(sc, rcb_addr, bge_max_len, BGE_TX_RING_CNT); 1199 RCB_WRITE_2(sc, rcb_addr, bge_flags, 0); 1200 1201 /* Disable all unused RX return rings */ 1202 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1203 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 1204 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 1205 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 1206 RCB_WRITE_2(sc, rcb_addr, bge_flags, 1207 BGE_RCB_FLAG_RING_DISABLED); 1208 RCB_WRITE_2(sc, rcb_addr, bge_max_len, BGE_RETURN_RING_CNT); 1209 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 1210 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO + 1211 (i * (sizeof(u_int64_t))), 0); 1212 rcb_addr += sizeof(struct bge_rcb); 1213 } 1214 1215 /* Initialize RX ring indexes */ 1216 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1217 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1218 CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1219 1220 /* 1221 * Set up RX return ring 0 1222 * Note that the NIC address for RX return rings is 0x00000000. 1223 * The return rings live entirely within the host, so the 1224 * nicaddr field in the RCB isn't used. 1225 */ 1226 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1227 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 1228 RCB_WRITE_4(sc, rcb_addr, BGE_HOSTADDR(bge_hostaddr), 1229 BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 1230 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 1231 RCB_WRITE_2(sc, rcb_addr, bge_max_len, BGE_RETURN_RING_CNT); 1232 RCB_WRITE_2(sc, rcb_addr, bge_flags, 0); 1233 1234 /* Set random backoff seed for TX */ 1235 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1236 sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] + 1237 sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] + 1238 sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] + 1239 BGE_TX_BACKOFF_SEED_MASK); 1240 1241 /* Set inter-packet gap */ 1242 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 1243 1244 /* 1245 * Specify which ring to use for packets that don't match 1246 * any RX rules. 1247 */ 1248 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1249 1250 /* 1251 * Configure number of RX lists. One interrupt distribution 1252 * list, sixteen active lists, one bad frames class. 1253 */ 1254 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1255 1256 /* Inialize RX list placement stats mask. */ 1257 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1258 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1259 1260 /* Disable host coalescing until we get it set up */ 1261 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1262 1263 /* Poll to make sure it's shut down. */ 1264 for (i = 0; i < BGE_TIMEOUT; i++) { 1265 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 1266 break; 1267 DELAY(10); 1268 } 1269 1270 if (i == BGE_TIMEOUT) { 1271 printf("%s: host coalescing engine failed to idle\n", 1272 sc->bge_dev.dv_xname); 1273 return(ENXIO); 1274 } 1275 1276 /* Set up host coalescing defaults */ 1277 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 1278 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 1279 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 1280 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 1281 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 1282 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 1283 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 1284 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 1285 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 1286 1287 /* Set up address of statistics block */ 1288 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 1289 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 0); 1290 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, 1291 BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 1292 1293 /* Set up address of status block */ 1294 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 1295 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 0); 1296 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, 1297 BGE_RING_DMA_ADDR(sc, bge_status_block)); 1298 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 1299 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 1300 1301 /* Turn on host coalescing state machine */ 1302 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 1303 1304 /* Turn on RX BD completion state machine and enable attentions */ 1305 CSR_WRITE_4(sc, BGE_RBDC_MODE, 1306 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN); 1307 1308 /* Turn on RX list placement state machine */ 1309 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 1310 1311 /* Turn on RX list selector state machine. */ 1312 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 1313 1314 /* Turn on DMA, clear stats */ 1315 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB| 1316 BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR| 1317 BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB| 1318 BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB| 1319 (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII)); 1320 1321 /* Set misc. local control, enable interrupts on attentions */ 1322 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 1323 1324 #ifdef notdef 1325 /* Assert GPIO pins for PHY reset */ 1326 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 1327 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 1328 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 1329 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 1330 #endif 1331 1332 /* Turn on DMA completion state machine */ 1333 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 1334 1335 /* Turn on write DMA state machine */ 1336 CSR_WRITE_4(sc, BGE_WDMA_MODE, 1337 BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS); 1338 1339 /* Turn on read DMA state machine */ 1340 CSR_WRITE_4(sc, BGE_RDMA_MODE, 1341 BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS); 1342 1343 /* Turn on RX data completion state machine */ 1344 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 1345 1346 /* Turn on RX BD initiator state machine */ 1347 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 1348 1349 /* Turn on RX data and RX BD initiator state machine */ 1350 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 1351 1352 /* Turn on Mbuf cluster free state machine */ 1353 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 1354 1355 /* Turn on send BD completion state machine */ 1356 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 1357 1358 /* Turn on send data completion state machine */ 1359 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 1360 1361 /* Turn on send data initiator state machine */ 1362 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 1363 1364 /* Turn on send BD initiator state machine */ 1365 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 1366 1367 /* Turn on send BD selector state machine */ 1368 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 1369 1370 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 1371 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 1372 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER); 1373 1374 /* init LED register */ 1375 CSR_WRITE_4(sc, BGE_MAC_LED_CTL, 0x00000000); 1376 1377 /* ack/clear link change events */ 1378 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 1379 BGE_MACSTAT_CFG_CHANGED); 1380 CSR_WRITE_4(sc, BGE_MI_STS, 0); 1381 1382 /* Enable PHY auto polling (for MII/GMII only) */ 1383 if (sc->bge_tbi) { 1384 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 1385 } else 1386 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16); 1387 1388 /* Enable link state change attentions. */ 1389 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 1390 1391 return(0); 1392 } 1393 1394 /* 1395 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 1396 * against our list and return its name if we find a match. Note 1397 * that since the Broadcom controller contains VPD support, we 1398 * can get the device name string from the controller itself instead 1399 * of the compiled-in string. This is a little slow, but it guarantees 1400 * we'll always announce the right product name. 1401 */ 1402 int 1403 bge_probe(parent, match, aux) 1404 struct device *parent; 1405 void *match; 1406 void *aux; 1407 { 1408 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 1409 1410 /* 1411 * Various supported device vendors/types and their 1412 * names. Note: the spec seems to indicate that the hardware 1413 * still has Alteon's vendor ID burned into it, though it will 1414 * always be overriden by the vendor ID in the EEPROM. Just to 1415 * be safe, we cover all possibilities. 1416 */ 1417 1418 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ALTEON && 1419 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ALTEON_BCM5700 || 1420 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ALTEON_BCM5701)) 1421 return (1); 1422 1423 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 1424 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5700 || 1425 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5701)) 1426 return (1); 1427 1428 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SCHNEIDERKOCH && 1429 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SCHNEIDERKOCH_SK9D21) 1430 return (1); 1431 1432 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_3COM && 1433 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_3COM_3C996) 1434 return (1); 1435 1436 return (0); 1437 } 1438 1439 void 1440 bge_attach(parent, self, aux) 1441 struct device *parent, *self; 1442 void *aux; 1443 { 1444 struct bge_softc *sc = (struct bge_softc *)self; 1445 struct pci_attach_args *pa = aux; 1446 pci_chipset_tag_t pc = pa->pa_pc; 1447 pci_intr_handle_t ih; 1448 const char *intrstr = NULL; 1449 bus_addr_t iobase; 1450 bus_size_t iosize; 1451 bus_dma_segment_t seg; 1452 int s, rseg; 1453 u_int32_t command; 1454 struct ifnet *ifp; 1455 int unit, error = 0; 1456 caddr_t kva; 1457 1458 s = splimp(); 1459 1460 sc->bge_pa = *pa; 1461 1462 /* 1463 * Map control/status registers. 1464 */ 1465 DPRINTFN(5, ("Map control/status regs\n")); 1466 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1467 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 1468 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1469 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1470 1471 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 1472 printf("%s: failed to enable memory mapping!\n", 1473 sc->bge_dev.dv_xname); 1474 error = ENXIO; 1475 goto fail; 1476 } 1477 1478 DPRINTFN(5, ("pci_mem_find\n")); 1479 if (pci_mem_find(pc, pa->pa_tag, BGE_PCI_BAR0, &iobase, 1480 &iosize, NULL)) { 1481 printf(": can't find mem space\n"); 1482 goto fail; 1483 } 1484 1485 DPRINTFN(5, ("bus_space_map\n")); 1486 if (bus_space_map(pa->pa_memt, iobase, iosize, 0, &sc->bge_bhandle)) { 1487 printf(": can't map mem space\n"); 1488 goto fail; 1489 } 1490 1491 sc->bge_btag = pa->pa_memt; 1492 1493 DPRINTFN(5, ("pci_intr_map\n")); 1494 if (pci_intr_map(pa, &ih)) { 1495 printf(": couldn't map interrupt\n"); 1496 goto fail; 1497 } 1498 1499 DPRINTFN(5, ("pci_intr_string\n")); 1500 intrstr = pci_intr_string(pc, ih); 1501 1502 DPRINTFN(5, ("pci_intr_establish\n")); 1503 sc->bge_intrhand = pci_intr_establish(pc, ih, IPL_NET, bge_intr, sc, 1504 sc->bge_dev.dv_xname); 1505 1506 if (sc->bge_intrhand == NULL) { 1507 printf(": couldn't establish interrupt"); 1508 if (intrstr != NULL) 1509 printf(" at %s", intrstr); 1510 printf("\n"); 1511 goto fail; 1512 } 1513 printf(": %s", intrstr); 1514 1515 /* Try to reset the chip. */ 1516 DPRINTFN(5, ("bge_reset\n")); 1517 bge_reset(sc); 1518 1519 if (bge_chipinit(sc)) { 1520 printf("%s: chip initializatino failed\n", 1521 sc->bge_dev.dv_xname); 1522 bge_release_resources(sc); 1523 error = ENXIO; 1524 goto fail; 1525 } 1526 1527 /* 1528 * Get station address from the EEPROM. 1529 */ 1530 if (bge_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1531 BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 1532 printf("bge%d: failed to read station address\n", unit); 1533 bge_release_resources(sc); 1534 error = ENXIO; 1535 goto fail; 1536 } 1537 1538 /* 1539 * A Broadcom chip was detected. Inform the world. 1540 */ 1541 printf(": Ethernet address: %s\n", 1542 ether_sprintf(sc->arpcom.ac_enaddr)); 1543 1544 /* Allocate the general information block and ring buffers. */ 1545 sc->bge_dmatag = pa->pa_dmat; 1546 DPRINTFN(5, ("bus_dmamem_alloc\n")); 1547 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 1548 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1549 printf("%s: can't alloc rx buffers\n", sc->bge_dev.dv_xname); 1550 goto fail; 1551 } 1552 DPRINTFN(5, ("bus_dmamem_map\n")); 1553 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, 1554 sizeof(struct bge_ring_data), &kva, 1555 BUS_DMA_NOWAIT)) { 1556 printf("%s: can't map dma buffers (%d bytes)\n", 1557 sc->bge_dev.dv_xname, sizeof(struct bge_ring_data)); 1558 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 1559 goto fail; 1560 } 1561 DPRINTFN(5, ("bus_dmamem_create\n")); 1562 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 1563 sizeof(struct bge_ring_data), 0, 1564 BUS_DMA_NOWAIT, &sc->bge_ring_map)) { 1565 printf("%s: can't create dma map\n", sc->bge_dev.dv_xname); 1566 bus_dmamem_unmap(sc->bge_dmatag, kva, 1567 sizeof(struct bge_ring_data)); 1568 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 1569 goto fail; 1570 } 1571 DPRINTFN(5, ("bus_dmamem_load\n")); 1572 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 1573 sizeof(struct bge_ring_data), NULL, 1574 BUS_DMA_NOWAIT)) { 1575 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 1576 bus_dmamem_unmap(sc->bge_dmatag, kva, 1577 sizeof(struct bge_ring_data)); 1578 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 1579 goto fail; 1580 } 1581 1582 DPRINTFN(5, ("bzero\n")); 1583 sc->bge_rdata = (struct bge_ring_data *)kva; 1584 1585 bzero(sc->bge_rdata, sizeof(struct bge_ring_data)); 1586 1587 /* Try to allocate memory for jumbo buffers. */ 1588 if (bge_alloc_jumbo_mem(sc)) { 1589 printf("%s: jumbo buffer allocation failed\n", 1590 sc->bge_dev.dv_xname); 1591 error = ENXIO; 1592 goto fail; 1593 } 1594 1595 /* Set default tuneable values. */ 1596 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 1597 sc->bge_rx_coal_ticks = 150; 1598 sc->bge_tx_coal_ticks = 150; 1599 sc->bge_rx_max_coal_bds = 64; 1600 sc->bge_tx_max_coal_bds = 128; 1601 1602 /* Set up ifnet structure */ 1603 ifp = &sc->arpcom.ac_if; 1604 ifp->if_softc = sc; 1605 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1606 ifp->if_ioctl = bge_ioctl; 1607 ifp->if_output = ether_output; 1608 ifp->if_start = bge_start; 1609 ifp->if_watchdog = bge_watchdog; 1610 ifp->if_baudrate = 1000000000; 1611 ifp->if_mtu = ETHERMTU; 1612 ifp->if_snd.ifq_maxlen = BGE_TX_RING_CNT - 1; 1613 DPRINTFN(5, ("bcopy\n")); 1614 bcopy(sc->bge_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 1615 1616 /* 1617 * Do MII setup. 1618 */ 1619 DPRINTFN(5, ("mii setup\n")); 1620 sc->bge_mii.mii_ifp = ifp; 1621 sc->bge_mii.mii_readreg = bge_miibus_readreg; 1622 sc->bge_mii.mii_writereg = bge_miibus_writereg; 1623 sc->bge_mii.mii_statchg = bge_miibus_statchg; 1624 1625 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 1626 if ((pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_SUBSYS) >> 16) == 1627 SK_SUBSYSID_9D41) 1628 sc->bge_tbi = 1; 1629 1630 /* 1631 * Do transceiver setup. 1632 */ 1633 ifmedia_init(&sc->bge_mii.mii_media, 0, bge_ifmedia_upd, 1634 bge_ifmedia_sts); 1635 mii_attach(&sc->bge_dev, &sc->bge_mii, 0xffffffff, 1636 MII_PHY_ANY, MII_OFFSET_ANY, 0); 1637 1638 if (LIST_FIRST(&sc->bge_mii.mii_phys) == NULL) { 1639 printf("%s: no PHY found!\n", sc->bge_dev.dv_xname); 1640 ifmedia_add(&sc->bge_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1641 0, NULL); 1642 ifmedia_set(&sc->bge_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1643 } else 1644 ifmedia_set(&sc->bge_mii.mii_media, IFM_ETHER|IFM_AUTO); 1645 1646 /* 1647 * Call MI attach routine. 1648 */ 1649 DPRINTFN(5, ("if_attach\n")); 1650 if_attach(ifp); 1651 DPRINTFN(5, ("ether_ifattach\n")); 1652 ether_ifattach(ifp); 1653 DPRINTFN(5, ("timeout_set\n")); 1654 timeout_set(&sc->bge_timeout, bge_tick, sc); 1655 fail: 1656 splx(s); 1657 } 1658 1659 void 1660 bge_release_resources(sc) 1661 struct bge_softc *sc; 1662 { 1663 if (sc->bge_vpd_prodname != NULL) 1664 free(sc->bge_vpd_prodname, M_DEVBUF); 1665 1666 if (sc->bge_vpd_readonly != NULL) 1667 free(sc->bge_vpd_readonly, M_DEVBUF); 1668 1669 #ifdef fake 1670 if (sc->bge_intrhand != NULL) 1671 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand); 1672 1673 if (sc->bge_irq != NULL) 1674 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq); 1675 1676 if (sc->bge_res != NULL) 1677 bus_release_resource(dev, SYS_RES_MEMORY, 1678 BGE_PCI_BAR0, sc->bge_res); 1679 1680 if (sc->bge_rdata != NULL) 1681 contigfree(sc->bge_rdata, 1682 sizeof(struct bge_ring_data), M_DEVBUF); 1683 #endif 1684 } 1685 1686 void 1687 bge_reset(sc) 1688 struct bge_softc *sc; 1689 { 1690 struct pci_attach_args *pa = &sc->bge_pa; 1691 u_int32_t cachesize, command, pcistate; 1692 int i, val = 0; 1693 1694 /* Save some important PCI state. */ 1695 cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ); 1696 command = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD); 1697 pcistate = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE); 1698 1699 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL, 1700 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 1701 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW); 1702 1703 /* Issue global reset */ 1704 bge_writereg_ind(sc, BGE_MISC_CFG, 1705 BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1)); 1706 1707 DELAY(1000); 1708 1709 /* Reset some of the PCI state that got zapped by reset */ 1710 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL, 1711 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 1712 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW); 1713 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ, cachesize); 1714 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD, command); 1715 bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1)); 1716 1717 /* 1718 * Prevent PXE restart: write a magic number to the 1719 * general communications memory at 0xB50. 1720 */ 1721 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 1722 /* 1723 * Poll the value location we just wrote until 1724 * we see the 1's complement of the magic number. 1725 * This indicates that the firmware initialization 1726 * is complete. 1727 */ 1728 for (i = 0; i < BGE_TIMEOUT; i++) { 1729 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 1730 if (val == ~BGE_MAGIC_NUMBER) 1731 break; 1732 DELAY(10); 1733 } 1734 1735 if (i == BGE_TIMEOUT) { 1736 printf("%s: firmware handshake timed out\n", 1737 sc->bge_dev.dv_xname); 1738 return; 1739 } 1740 1741 /* 1742 * XXX Wait for the value of the PCISTATE register to 1743 * return to its original pre-reset state. This is a 1744 * fairly good indicator of reset completion. If we don't 1745 * wait for the reset to fully complete, trying to read 1746 * from the device's non-PCI registers may yield garbage 1747 * results. 1748 */ 1749 for (i = 0; i < BGE_TIMEOUT; i++) { 1750 if (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE) == 1751 pcistate) 1752 break; 1753 DELAY(10); 1754 } 1755 1756 /* Enable memory arbiter. */ 1757 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 1758 1759 /* Fix up byte swapping */ 1760 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_BYTESWAP_NONFRAME| 1761 BGE_MODECTL_BYTESWAP_DATA); 1762 1763 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1764 1765 DELAY(10000); 1766 } 1767 1768 /* 1769 * Frame reception handling. This is called if there's a frame 1770 * on the receive return list. 1771 * 1772 * Note: we have to be able to handle two possibilities here: 1773 * 1) the frame is from the jumbo recieve ring 1774 * 2) the frame is from the standard receive ring 1775 */ 1776 1777 void 1778 bge_rxeof(sc) 1779 struct bge_softc *sc; 1780 { 1781 struct ifnet *ifp; 1782 int stdcnt = 0, jumbocnt = 0; 1783 1784 ifp = &sc->arpcom.ac_if; 1785 1786 while(sc->bge_rx_saved_considx != 1787 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx) { 1788 struct bge_rx_bd *cur_rx; 1789 u_int32_t rxidx; 1790 struct mbuf *m = NULL; 1791 #if NVLAN > 0 1792 u_int16_t vlan_tag = 0; 1793 int have_tag = 0; 1794 #endif 1795 #ifdef BGE_CHECKSUM 1796 int sumflags = 0; 1797 #endif 1798 1799 cur_rx = &sc->bge_rdata-> 1800 bge_rx_return_ring[sc->bge_rx_saved_considx]; 1801 1802 rxidx = cur_rx->bge_idx; 1803 BGE_INC(sc->bge_rx_saved_considx, BGE_RETURN_RING_CNT); 1804 1805 #if NVLAN > 0 1806 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 1807 have_tag = 1; 1808 vlan_tag = cur_rx->bge_vlan_tag; 1809 } 1810 #endif 1811 1812 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 1813 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 1814 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 1815 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 1816 jumbocnt++; 1817 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 1818 ifp->if_ierrors++; 1819 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 1820 continue; 1821 } 1822 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 1823 NULL)== ENOBUFS) { 1824 ifp->if_ierrors++; 1825 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 1826 continue; 1827 } 1828 } else { 1829 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 1830 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 1831 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 1832 bus_dmamap_unload(sc->bge_dmatag, 1833 sc->bge_cdata.bge_rx_std_map[rxidx]); 1834 stdcnt++; 1835 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 1836 ifp->if_ierrors++; 1837 bge_newbuf_std(sc, sc->bge_std, m); 1838 continue; 1839 } 1840 if (bge_newbuf_std(sc, sc->bge_std, 1841 NULL) == ENOBUFS) { 1842 ifp->if_ierrors++; 1843 bge_newbuf_std(sc, sc->bge_std, m); 1844 continue; 1845 } 1846 } 1847 1848 ifp->if_ipackets++; 1849 m->m_pkthdr.len = m->m_len = cur_rx->bge_len; 1850 m->m_pkthdr.rcvif = ifp; 1851 1852 #if NBPFILTER > 0 1853 /* 1854 * Handle BPF listeners. Let the BPF user see the packet. 1855 */ 1856 if (ifp->if_bpf) 1857 bpf_mtap(ifp->if_bpf, m); 1858 #endif 1859 1860 #ifdef BGE_CHECKSUM 1861 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0) 1862 sumflags |= M_IPV4_CSUM_IN_OK; 1863 else 1864 sumflags |= M_IPV4_CSUM_IN_BAD; 1865 #if 0 1866 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 1867 m->m_pkthdr.csum_data = 1868 cur_rx->bge_tcp_udp_csum; 1869 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 1870 } 1871 #endif 1872 m->m_pkthdr.csum = sumflags; 1873 sumflags = 0; 1874 #endif 1875 1876 #if NVLAN > 0 1877 /* 1878 * If we received a packet with a vlan tag, pass it 1879 * to vlan_input() instead of ether_input(). 1880 */ 1881 if (have_tag) { 1882 vlan_input_tag(m, vlan_tag); 1883 have_tag = vlan_tag = 0; 1884 continue; 1885 } 1886 #endif 1887 ether_input_mbuf(ifp, m); 1888 } 1889 1890 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 1891 if (stdcnt) 1892 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1893 if (jumbocnt) 1894 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1895 } 1896 1897 void 1898 bge_txeof(sc) 1899 struct bge_softc *sc; 1900 { 1901 struct bge_tx_bd *cur_tx = NULL; 1902 struct ifnet *ifp; 1903 1904 ifp = &sc->arpcom.ac_if; 1905 1906 /* 1907 * Go through our tx ring and free mbufs for those 1908 * frames that have been sent. 1909 */ 1910 while (sc->bge_tx_saved_considx != 1911 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 1912 u_int32_t idx = 0; 1913 1914 idx = sc->bge_tx_saved_considx; 1915 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 1916 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 1917 ifp->if_opackets++; 1918 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) { 1919 m_freem(sc->bge_cdata.bge_tx_chain[idx]); 1920 sc->bge_cdata.bge_tx_chain[idx] = NULL; 1921 bus_dmamap_unload(sc->bge_dmatag, 1922 sc->bge_cdata.bge_tx_map[idx]); 1923 } 1924 sc->bge_txcnt--; 1925 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 1926 ifp->if_timer = 0; 1927 } 1928 1929 if (cur_tx != NULL) 1930 ifp->if_flags &= ~IFF_OACTIVE; 1931 } 1932 1933 int 1934 bge_intr(xsc) 1935 void *xsc; 1936 { 1937 struct bge_softc *sc; 1938 struct ifnet *ifp; 1939 1940 sc = xsc; 1941 ifp = &sc->arpcom.ac_if; 1942 1943 #ifdef notdef 1944 /* Avoid this for now -- checking this register is expensive. */ 1945 /* Make sure this is really our interrupt. */ 1946 if (!(CSR_READ_4(sc, BGE_MISC_LOCAL_CTL) & BGE_MLC_INTR_STATE)) 1947 return (0); 1948 #endif 1949 /* Ack interrupt and stop others from occuring. */ 1950 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 1951 1952 /* Process link state changes. */ 1953 if (sc->bge_rdata->bge_status_block.bge_status & 1954 BGE_STATFLAG_LINKSTATE_CHANGED) { 1955 sc->bge_link = 0; 1956 timeout_del(&sc->bge_timeout); 1957 bge_tick(sc); 1958 /* ack the event to clear/reset it */ 1959 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 1960 BGE_MACSTAT_CFG_CHANGED); 1961 CSR_WRITE_4(sc, BGE_MI_STS, 0); 1962 } 1963 1964 if (ifp->if_flags & IFF_RUNNING) { 1965 /* Check RX return ring producer/consumer */ 1966 bge_rxeof(sc); 1967 1968 /* Check TX ring producer/consumer */ 1969 bge_txeof(sc); 1970 } 1971 1972 bge_handle_events(sc); 1973 1974 /* Re-enable interrupts. */ 1975 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 1976 1977 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL) 1978 bge_start(ifp); 1979 1980 return (1); 1981 } 1982 1983 void 1984 bge_tick(xsc) 1985 void *xsc; 1986 { 1987 struct bge_softc *sc = xsc; 1988 struct mii_data *mii = &sc->bge_mii; 1989 struct ifmedia *ifm = NULL; 1990 struct ifnet *ifp = &sc->arpcom.ac_if; 1991 int s; 1992 1993 s = splimp(); 1994 1995 bge_stats_update(sc); 1996 timeout_add(&sc->bge_timeout, hz); 1997 if (sc->bge_link) { 1998 splx(s); 1999 return; 2000 } 2001 2002 if (sc->bge_tbi) { 2003 ifm = &sc->bge_ifmedia; 2004 if (CSR_READ_4(sc, BGE_MAC_STS) & 2005 BGE_MACSTAT_TBI_PCS_SYNCHED) { 2006 sc->bge_link++; 2007 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 2008 printf("%s: gigabit link up\n", sc->bge_dev.dv_xname); 2009 if (ifp->if_snd.ifq_head != NULL) 2010 bge_start(ifp); 2011 } 2012 splx(s); 2013 return; 2014 } 2015 2016 mii_tick(mii); 2017 2018 if (!sc->bge_link && mii->mii_media_status & IFM_ACTIVE && 2019 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2020 sc->bge_link++; 2021 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_TX || 2022 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 2023 printf("%s: gigabit link up\n", sc->bge_dev.dv_xname); 2024 if (ifp->if_snd.ifq_head != NULL) 2025 bge_start(ifp); 2026 } 2027 2028 splx(s); 2029 } 2030 2031 void 2032 bge_stats_update(sc) 2033 struct bge_softc *sc; 2034 { 2035 struct ifnet *ifp = &sc->arpcom.ac_if; 2036 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 2037 2038 #define READ_STAT(sc, stats, stat) \ 2039 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 2040 2041 ifp->if_collisions += 2042 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) + 2043 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) + 2044 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) + 2045 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)) - 2046 ifp->if_collisions; 2047 2048 #undef READ_STAT 2049 2050 #ifdef notdef 2051 ifp->if_collisions += 2052 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 2053 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 2054 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 2055 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 2056 ifp->if_collisions; 2057 #endif 2058 } 2059 2060 /* 2061 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2062 * pointers to descriptors. 2063 */ 2064 int 2065 bge_encap(sc, m_head, txidx) 2066 struct bge_softc *sc; 2067 struct mbuf *m_head; 2068 u_int32_t *txidx; 2069 { 2070 struct bge_tx_bd *f = NULL; 2071 struct mbuf *m; 2072 u_int32_t frag, cur, cnt = 0; 2073 u_int16_t csum_flags = 0; 2074 bus_dmamap_t txmap; 2075 int i = 0; 2076 #if NVLAN > 0 2077 struct ifvlan *ifv = NULL; 2078 2079 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 2080 m_head->m_pkthdr.rcvif != NULL) 2081 ifv = m_head->m_pkthdr.rcvif->if_softc; 2082 #endif 2083 2084 m = m_head; 2085 cur = frag = *txidx; 2086 2087 #ifdef BGE_CHECKSUM 2088 if (m_head->m_pkthdr.csum) { 2089 if (m_head->m_pkthdr.csum & M_IPV4_CSUM_OUT) 2090 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 2091 if (m_head->m_pkthdr.csum & (M_TCPV4_CSUM_OUT | 2092 M_UDPV4_CSUM_OUT)) 2093 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 2094 #ifdef fake 2095 if (m_head->m_flags & M_LASTFRAG) 2096 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END; 2097 else if (m_head->m_flags & M_FRAG) 2098 csum_flags |= BGE_TXBDFLAG_IP_FRAG; 2099 #endif 2100 } 2101 #endif 2102 2103 /* 2104 * Start packing the mbufs in this chain into 2105 * the fragment pointers. Stop when we run out 2106 * of fragments or hit the end of the mbuf chain. 2107 */ 2108 txmap = sc->bge_cdata.bge_tx_map[frag]; 2109 if (bus_dmamap_load_mbuf(sc->bge_dmatag, txmap, m, 2110 BUS_DMA_NOWAIT)) 2111 return(ENOBUFS); 2112 2113 for (m = m_head; m != NULL; m = m->m_next) { 2114 if (m->m_len != 0) { 2115 f = &sc->bge_rdata->bge_tx_ring[frag]; 2116 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 2117 break; 2118 BGE_HOSTADDR(f->bge_addr) = 2119 txmap->dm_segs[i++].ds_addr; 2120 f->bge_len = m->m_len; 2121 f->bge_flags = csum_flags; 2122 #if NVLAN > 0 2123 if (ifv != NULL) { 2124 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 2125 f->bge_vlan_tag = ifv->ifv_tag; 2126 } else { 2127 f->bge_vlan_tag = 0; 2128 } 2129 #endif 2130 /* 2131 * Sanity check: avoid coming within 16 descriptors 2132 * of the end of the ring. 2133 */ 2134 if ((BGE_TX_RING_CNT - (sc->bge_txcnt + cnt)) < 16) 2135 return(ENOBUFS); 2136 cur = frag; 2137 BGE_INC(frag, BGE_TX_RING_CNT); 2138 cnt++; 2139 } 2140 } 2141 2142 if (m != NULL) 2143 return(ENOBUFS); 2144 2145 if (frag == sc->bge_tx_saved_considx) 2146 return(ENOBUFS); 2147 2148 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 2149 sc->bge_cdata.bge_tx_chain[cur] = m_head; 2150 sc->bge_txcnt += cnt; 2151 2152 *txidx = frag; 2153 2154 return(0); 2155 } 2156 2157 /* 2158 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2159 * to the mbuf data regions directly in the transmit descriptors. 2160 */ 2161 void 2162 bge_start(ifp) 2163 struct ifnet *ifp; 2164 { 2165 struct bge_softc *sc; 2166 struct mbuf *m_head = NULL; 2167 u_int32_t prodidx = 0; 2168 2169 sc = ifp->if_softc; 2170 2171 if (!sc->bge_link && ifp->if_snd.ifq_len < 10) 2172 return; 2173 2174 prodidx = CSR_READ_4(sc, BGE_MBX_TX_HOST_PROD0_LO); 2175 2176 while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 2177 IF_DEQUEUE(&ifp->if_snd, m_head); 2178 if (m_head == NULL) 2179 break; 2180 2181 /* 2182 * XXX 2183 * safety overkill. If this is a fragmented packet chain 2184 * with delayed TCP/UDP checksums, then only encapsulate 2185 * it if we have enough descriptors to handle the entire 2186 * chain at once. 2187 * (paranoia -- may not actually be needed) 2188 */ 2189 #ifdef fake 2190 if (m_head->m_flags & M_FIRSTFRAG && 2191 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 2192 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 2193 m_head->m_pkthdr.csum_data + 16) { 2194 IF_PREPEND(&ifp->if_snd, m_head); 2195 ifp->if_flags |= IFF_OACTIVE; 2196 break; 2197 } 2198 } 2199 #endif 2200 2201 /* 2202 * Pack the data into the transmit ring. If we 2203 * don't have room, set the OACTIVE flag and wait 2204 * for the NIC to drain the ring. 2205 */ 2206 if (bge_encap(sc, m_head, &prodidx)) { 2207 IF_PREPEND(&ifp->if_snd, m_head); 2208 ifp->if_flags |= IFF_OACTIVE; 2209 break; 2210 } 2211 2212 /* 2213 * If there's a BPF listener, bounce a copy of this frame 2214 * to him. 2215 */ 2216 if (ifp->if_bpf) 2217 bpf_mtap(ifp->if_bpf, m_head); 2218 } 2219 2220 /* Transmit */ 2221 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 2222 2223 /* 2224 * Set a timeout in case the chip goes out to lunch. 2225 */ 2226 ifp->if_timer = 5; 2227 } 2228 2229 /* 2230 * If we have a BCM5400 or BCM5401 PHY, we need to properly 2231 * program its internal DSP. Failing to do this can result in 2232 * massive packet loss at 1Gb speeds. 2233 */ 2234 void 2235 bge_phy_hack(sc) 2236 struct bge_softc *sc; 2237 { 2238 struct bge_bcom_hack bhack[] = { 2239 { BRGPHY_MII_AUXCTL, 0x4C20 }, 2240 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 2241 { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 2242 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 2243 { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 2244 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 2245 { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 2246 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 2247 { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 2248 { BRGPHY_MII_DSP_ADDR_REG, 0x201F }, 2249 { BRGPHY_MII_DSP_RW_PORT, 0x0A20 }, 2250 { 0, 0 } }; 2251 u_int16_t vid, did; 2252 int i; 2253 2254 vid = bge_miibus_readreg(&sc->bge_dev, 1, MII_PHYIDR1); 2255 did = bge_miibus_readreg(&sc->bge_dev, 1, MII_PHYIDR2); 2256 2257 if (MII_OUI(vid, did) == MII_OUI_xxBROADCOM && 2258 (MII_MODEL(did) == MII_MODEL_xxBROADCOM_BCM5400 || 2259 MII_MODEL(did) == MII_MODEL_xxBROADCOM_BCM5401)) { 2260 i = 0; 2261 while (bhack[i].reg) { 2262 bge_miibus_writereg(&sc->bge_dev, 1, bhack[i].reg, 2263 bhack[i].val); 2264 i++; 2265 } 2266 } 2267 } 2268 2269 void 2270 bge_init(xsc) 2271 void *xsc; 2272 { 2273 struct bge_softc *sc = xsc; 2274 struct ifnet *ifp; 2275 u_int16_t *m; 2276 int s; 2277 2278 s = splimp(); 2279 2280 ifp = &sc->arpcom.ac_if; 2281 2282 if (ifp->if_flags & IFF_RUNNING) 2283 return; 2284 2285 /* Cancel pending I/O and flush buffers. */ 2286 bge_stop(sc); 2287 bge_reset(sc); 2288 bge_chipinit(sc); 2289 2290 /* 2291 * Init the various state machines, ring 2292 * control blocks and firmware. 2293 */ 2294 if (bge_blockinit(sc)) { 2295 printf("%s: initialization failure\n", sc->bge_dev.dv_xname); 2296 splx(s); 2297 return; 2298 } 2299 2300 ifp = &sc->arpcom.ac_if; 2301 2302 /* Specify MTU. */ 2303 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 2304 ETHER_HDR_LEN + ETHER_CRC_LEN); 2305 2306 /* Load our MAC address. */ 2307 m = (u_int16_t *)&sc->arpcom.ac_enaddr[0]; 2308 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 2309 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 2310 2311 /* Enable or disable promiscuous mode as needed. */ 2312 if (ifp->if_flags & IFF_PROMISC) { 2313 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 2314 } else { 2315 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 2316 } 2317 2318 /* Program multicast filter. */ 2319 bge_setmulti(sc); 2320 2321 /* Init RX ring. */ 2322 bge_init_rx_ring_std(sc); 2323 2324 /* Init jumbo RX ring. */ 2325 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2326 bge_init_rx_ring_jumbo(sc); 2327 2328 /* Init our RX return ring index */ 2329 sc->bge_rx_saved_considx = 0; 2330 2331 /* Init TX ring. */ 2332 bge_init_tx_ring(sc); 2333 2334 /* Turn on transmitter */ 2335 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 2336 2337 /* Turn on receiver */ 2338 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 2339 2340 /* Tell firmware we're alive. */ 2341 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2342 2343 /* Enable host interrupts. */ 2344 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 2345 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 2346 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 2347 2348 bge_ifmedia_upd(ifp); 2349 2350 ifp->if_flags |= IFF_RUNNING; 2351 ifp->if_flags &= ~IFF_OACTIVE; 2352 2353 splx(s); 2354 2355 timeout_add(&sc->bge_timeout, hz); 2356 } 2357 2358 /* 2359 * Set media options. 2360 */ 2361 int 2362 bge_ifmedia_upd(ifp) 2363 struct ifnet *ifp; 2364 { 2365 struct bge_softc *sc = ifp->if_softc; 2366 struct mii_data *mii = &sc->bge_mii; 2367 struct ifmedia *ifm = &sc->bge_ifmedia; 2368 2369 /* If this is a 1000baseX NIC, enable the TBI port. */ 2370 if (sc->bge_tbi) { 2371 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2372 return(EINVAL); 2373 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2374 case IFM_AUTO: 2375 break; 2376 case IFM_1000_SX: 2377 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2378 BGE_CLRBIT(sc, BGE_MAC_MODE, 2379 BGE_MACMODE_HALF_DUPLEX); 2380 } else { 2381 BGE_SETBIT(sc, BGE_MAC_MODE, 2382 BGE_MACMODE_HALF_DUPLEX); 2383 } 2384 break; 2385 default: 2386 return(EINVAL); 2387 } 2388 return(0); 2389 } 2390 2391 sc->bge_link = 0; 2392 if (mii->mii_instance) { 2393 struct mii_softc *miisc; 2394 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 2395 miisc = LIST_NEXT(miisc, mii_list)) 2396 mii_phy_reset(miisc); 2397 } 2398 bge_phy_hack(sc); 2399 mii_mediachg(mii); 2400 2401 return(0); 2402 } 2403 2404 /* 2405 * Report current media status. 2406 */ 2407 void 2408 bge_ifmedia_sts(ifp, ifmr) 2409 struct ifnet *ifp; 2410 struct ifmediareq *ifmr; 2411 { 2412 struct bge_softc *sc = ifp->if_softc; 2413 struct mii_data *mii = &sc->bge_mii; 2414 2415 if (sc->bge_tbi) { 2416 ifmr->ifm_status = IFM_AVALID; 2417 ifmr->ifm_active = IFM_ETHER; 2418 if (CSR_READ_4(sc, BGE_MAC_STS) & 2419 BGE_MACSTAT_TBI_PCS_SYNCHED) 2420 ifmr->ifm_status |= IFM_ACTIVE; 2421 ifmr->ifm_active |= IFM_1000_SX; 2422 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 2423 ifmr->ifm_active |= IFM_HDX; 2424 else 2425 ifmr->ifm_active |= IFM_FDX; 2426 return; 2427 } 2428 2429 mii_pollstat(mii); 2430 ifmr->ifm_active = mii->mii_media_active; 2431 ifmr->ifm_status = mii->mii_media_status; 2432 } 2433 2434 int 2435 bge_ioctl(ifp, command, data) 2436 struct ifnet *ifp; 2437 u_long command; 2438 caddr_t data; 2439 { 2440 struct bge_softc *sc = ifp->if_softc; 2441 struct ifreq *ifr = (struct ifreq *) data; 2442 struct ifaddr *ifa = (struct ifaddr *)data; 2443 int s, error = 0; 2444 struct mii_data *mii; 2445 2446 s = splimp(); 2447 2448 if ((error = ether_ioctl(ifp, &sc->arpcom, command, data)) > 0) { 2449 splx(s); 2450 return (error); 2451 } 2452 2453 switch(command) { 2454 case SIOCSIFADDR: 2455 ifp->if_flags |= IFF_UP; 2456 switch (ifa->ifa_addr->sa_family) { 2457 #ifdef INET 2458 case AF_INET: 2459 bge_init(sc); 2460 arp_ifinit(&sc->arpcom, ifa); 2461 break; 2462 #endif /* INET */ 2463 default: 2464 bge_init(sc); 2465 break; 2466 } 2467 break; 2468 case SIOCSIFMTU: 2469 if (ifr->ifr_mtu > BGE_JUMBO_MTU) 2470 error = EINVAL; 2471 else 2472 ifp->if_mtu = ifr->ifr_mtu; 2473 break; 2474 case SIOCSIFFLAGS: 2475 if (ifp->if_flags & IFF_UP) { 2476 /* 2477 * If only the state of the PROMISC flag changed, 2478 * then just use the 'set promisc mode' command 2479 * instead of reinitializing the entire NIC. Doing 2480 * a full re-init means reloading the firmware and 2481 * waiting for it to start up, which may take a 2482 * second or two. 2483 */ 2484 if (ifp->if_flags & IFF_RUNNING && 2485 ifp->if_flags & IFF_PROMISC && 2486 !(sc->bge_if_flags & IFF_PROMISC)) { 2487 BGE_SETBIT(sc, BGE_RX_MODE, 2488 BGE_RXMODE_RX_PROMISC); 2489 } else if (ifp->if_flags & IFF_RUNNING && 2490 !(ifp->if_flags & IFF_PROMISC) && 2491 sc->bge_if_flags & IFF_PROMISC) { 2492 BGE_CLRBIT(sc, BGE_RX_MODE, 2493 BGE_RXMODE_RX_PROMISC); 2494 } else 2495 bge_init(sc); 2496 } else { 2497 if (ifp->if_flags & IFF_RUNNING) { 2498 bge_stop(sc); 2499 } 2500 } 2501 sc->bge_if_flags = ifp->if_flags; 2502 error = 0; 2503 break; 2504 case SIOCADDMULTI: 2505 case SIOCDELMULTI: 2506 if (ifp->if_flags & IFF_RUNNING) { 2507 bge_setmulti(sc); 2508 error = 0; 2509 } 2510 break; 2511 case SIOCSIFMEDIA: 2512 case SIOCGIFMEDIA: 2513 if (sc->bge_tbi) { 2514 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 2515 command); 2516 } else { 2517 mii = &sc->bge_mii; 2518 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 2519 command); 2520 } 2521 error = 0; 2522 break; 2523 default: 2524 error = EINVAL; 2525 break; 2526 } 2527 2528 (void)splx(s); 2529 2530 return(error); 2531 } 2532 2533 void 2534 bge_watchdog(ifp) 2535 struct ifnet *ifp; 2536 { 2537 struct bge_softc *sc; 2538 2539 sc = ifp->if_softc; 2540 2541 printf("%s: watchdog timeout -- resetting\n", sc->bge_dev.dv_xname); 2542 2543 ifp->if_flags &= ~IFF_RUNNING; 2544 bge_init(sc); 2545 2546 ifp->if_oerrors++; 2547 } 2548 2549 /* 2550 * Stop the adapter and free any mbufs allocated to the 2551 * RX and TX lists. 2552 */ 2553 void 2554 bge_stop(sc) 2555 struct bge_softc *sc; 2556 { 2557 struct ifnet *ifp = &sc->arpcom.ac_if; 2558 struct ifmedia_entry *ifm; 2559 struct mii_data *mii; 2560 int mtmp, itmp; 2561 2562 timeout_del(&sc->bge_timeout); 2563 2564 /* 2565 * Disable all of the receiver blocks 2566 */ 2567 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 2568 BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 2569 BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2570 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2571 BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 2572 BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 2573 BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 2574 2575 /* 2576 * Disable all of the transmit blocks 2577 */ 2578 BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 2579 BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 2580 BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 2581 BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 2582 BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 2583 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2584 BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 2585 2586 /* 2587 * Shut down all of the memory managers and related 2588 * state machines. 2589 */ 2590 BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 2591 BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 2592 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 2593 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2594 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2595 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 2596 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 2597 2598 /* Disable host interrupts. */ 2599 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 2600 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 2601 2602 /* 2603 * Tell firmware we're shutting down. 2604 */ 2605 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2606 2607 /* Free the RX lists. */ 2608 bge_free_rx_ring_std(sc); 2609 2610 /* Free jumbo RX list. */ 2611 bge_free_rx_ring_jumbo(sc); 2612 2613 /* Free TX buffers. */ 2614 bge_free_tx_ring(sc); 2615 2616 /* 2617 * Isolate/power down the PHY, but leave the media selection 2618 * unchanged so that things will be put back to normal when 2619 * we bring the interface back up. 2620 */ 2621 if (!sc->bge_tbi) { 2622 mii = &sc->bge_mii; 2623 itmp = ifp->if_flags; 2624 ifp->if_flags |= IFF_UP; 2625 ifm = mii->mii_media.ifm_cur; 2626 mtmp = ifm->ifm_media; 2627 ifm->ifm_media = IFM_ETHER|IFM_NONE; 2628 mii_mediachg(mii); 2629 ifm->ifm_media = mtmp; 2630 ifp->if_flags = itmp; 2631 } 2632 2633 sc->bge_link = 0; 2634 2635 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 2636 2637 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2638 } 2639 2640 /* 2641 * Stop all chip I/O so that the kernel's probe routines don't 2642 * get confused by errant DMAs when rebooting. 2643 */ 2644 void 2645 bge_shutdown(xsc) 2646 void *xsc; 2647 { 2648 struct bge_softc *sc = (struct bge_softc *)xsc; 2649 2650 bge_stop(sc); 2651 bge_reset(sc); 2652 } 2653 2654 struct cfattach bge_ca = { 2655 sizeof(struct bge_softc), bge_probe, bge_attach 2656 }; 2657 2658 struct cfdriver bge_cd = { 2659 0, "bge", DV_IFNET 2660 }; 2661