1 /* $OpenBSD: if_aq_pci.c,v 1.22 2023/05/02 12:32:22 kettenis Exp $ */ 2 /* $NetBSD: if_aq.c,v 1.27 2021/06/16 00:21:18 riastradh Exp $ */ 3 4 /* 5 * Copyright (c) 2021 Jonathan Matthew <jonathan@d14n.org> 6 * Copyright (c) 2021 Mike Larkin <mlarkin@openbsd.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /** 22 * aQuantia Corporation Network Driver 23 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved 24 * 25 * Redistribution and use in source and binary forms, with or without 26 * modification, are permitted provided that the following conditions 27 * are met: 28 * 29 * (1) Redistributions of source code must retain the above 30 * copyright notice, this list of conditions and the following 31 * disclaimer. 32 * 33 * (2) Redistributions in binary form must reproduce the above 34 * copyright notice, this list of conditions and the following 35 * disclaimer in the documentation and/or other materials provided 36 * with the distribution. 37 * 38 * (3) The name of the author may not be used to endorse or promote 39 * products derived from this software without specific prior 40 * written permission. 41 * 42 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS 43 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 44 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 45 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 46 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 47 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 48 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 49 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 50 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 51 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 52 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 53 * 54 */ 55 56 /*- 57 * Copyright (c) 2020 Ryo Shimizu <ryo@nerv.org> 58 * All rights reserved. 59 * 60 * Redistribution and use in source and binary forms, with or without 61 * modification, are permitted provided that the following conditions 62 * are met: 63 * 1. Redistributions of source code must retain the above copyright 64 * notice, this list of conditions and the following disclaimer. 65 * 2. Redistributions in binary form must reproduce the above copyright 66 * notice, this list of conditions and the following disclaimer in the 67 * documentation and/or other materials provided with the distribution. 68 * 69 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 70 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 71 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 72 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 73 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 74 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 75 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 76 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 77 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 78 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 79 * POSSIBILITY OF SUCH DAMAGE. 80 */ 81 #include "bpfilter.h" 82 #include "vlan.h" 83 84 #include <sys/types.h> 85 #include <sys/device.h> 86 #include <sys/param.h> 87 #include <sys/kernel.h> 88 #include <sys/sockio.h> 89 #include <sys/systm.h> 90 #include <sys/intrmap.h> 91 92 #include <net/if.h> 93 #include <net/if_media.h> 94 #include <net/toeplitz.h> 95 96 #include <netinet/in.h> 97 #include <netinet/if_ether.h> 98 99 #ifdef __HAVE_FDT 100 #include <dev/ofw/openfirm.h> 101 #endif 102 103 #include <dev/pci/pcireg.h> 104 #include <dev/pci/pcivar.h> 105 #include <dev/pci/pcidevs.h> 106 107 #if NBPFILTER > 0 108 #include <net/bpf.h> 109 #endif 110 111 /* #define AQ_DEBUG 1 */ 112 #ifdef AQ_DEBUG 113 #define DPRINTF(x) printf x 114 #else 115 #define DPRINTF(x) 116 #endif /* AQ_DEBUG */ 117 118 #define DEVNAME(_s) ((_s)->sc_dev.dv_xname) 119 120 #define AQ_BAR0 0x10 121 #define AQ_MAXQ 8 122 #define AQ_RSS_KEYSIZE 40 123 #define AQ_RSS_REDIR_ENTRIES 12 124 125 #define AQ_TXD_NUM 2048 126 #define AQ_RXD_NUM 2048 127 128 #define AQ_TX_MAX_SEGMENTS 32 129 130 #define AQ_LINKSTAT_IRQ 31 131 132 #define RPF_ACTION_HOST 1 133 134 #define AQ_FW_SOFTRESET_REG 0x0000 135 #define AQ_FW_SOFTRESET_DIS (1 << 14) 136 #define AQ_FW_SOFTRESET_RESET (1 << 15) 137 #define AQ_FW_VERSION_REG 0x0018 138 #define AQ_HW_REVISION_REG 0x001c 139 #define AQ2_HW_FPGA_VERSION_REG 0x00f4 140 #define AQ_GLB_NVR_INTERFACE1_REG 0x0100 141 #define AQ_FW_MBOX_CMD_REG 0x0200 142 #define AQ_FW_MBOX_CMD_EXECUTE 0x00008000 143 #define AQ_FW_MBOX_CMD_BUSY 0x00000100 144 #define AQ_FW_MBOX_ADDR_REG 0x0208 145 #define AQ_FW_MBOX_VAL_REG 0x020C 146 #define AQ_FW_GLB_CPU_SEM_REG(i) (0x03a0 + (i) * 4) 147 #define AQ_FW_SEM_RAM_REG AQ_FW_GLB_CPU_SEM_REG(2) 148 #define AQ2_ART_SEM_REG AQ_FW_GLB_CPU_SEM_REG(3) 149 #define AQ_FW_GLB_CTL2_REG 0x0404 150 #define AQ_GLB_GENERAL_PROVISIONING9_REG 0x0520 151 #define AQ_GLB_NVR_PROVISIONING2_REG 0x0534 152 #define AQ_INTR_STATUS_REG 0x2000 /* intr status */ 153 #define AQ_INTR_STATUS_CLR_REG 0x2050 /* intr status clear */ 154 #define AQ_INTR_MASK_REG 0x2060 /* intr mask set */ 155 #define AQ_INTR_MASK_CLR_REG 0x2070 /* intr mask clear */ 156 #define AQ_INTR_AUTOMASK_REG 0x2090 157 158 /* AQ_INTR_IRQ_MAP_TXRX_REG 0x2100-0x2140 */ 159 #define AQ_INTR_IRQ_MAP_TXRX_REG(i) (0x2100 + ((i) / 2) * 4) 160 #define AQ_INTR_IRQ_MAP_TX_REG(i) AQ_INTR_IRQ_MAP_TXRX_REG(i) 161 #define AQ_INTR_IRQ_MAP_TX_IRQMAP(i) (0x1FU << (((i) & 1) ? 16 : 24)) 162 #define AQ_INTR_IRQ_MAP_TX_EN(i) (1U << (((i) & 1) ? 23 : 31)) 163 #define AQ_INTR_IRQ_MAP_RX_REG(i) AQ_INTR_IRQ_MAP_TXRX_REG(i) 164 #define AQ_INTR_IRQ_MAP_RX_IRQMAP(i) (0x1FU << (((i) & 1) ? 0 : 8)) 165 #define AQ_INTR_IRQ_MAP_RX_EN(i) (1U << (((i) & 1) ? 7 : 15)) 166 167 /* AQ_GEN_INTR_MAP_REG[AQ_RINGS_NUM] 0x2180-0x2200 */ 168 #define AQ_GEN_INTR_MAP_REG(i) (0x2180 + (i) * 4) 169 #define AQ_B0_ERR_INT 8U 170 171 #define AQ_INTR_CTRL_REG 0x2300 172 #define AQ_INTR_CTRL_IRQMODE ((1 << 0) | (1 << 1)) 173 #define AQ_INTR_CTRL_IRQMODE_LEGACY 0 174 #define AQ_INTR_CTRL_IRQMODE_MSI 1 175 #define AQ_INTR_CTRL_IRQMODE_MSIX 2 176 #define AQ_INTR_CTRL_MULTIVEC (1 << 2) 177 #define AQ_INTR_CTRL_RESET_DIS (1 << 29) 178 #define AQ_INTR_CTRL_RESET_IRQ (1 << 31) 179 #define AQ_MBOXIF_POWER_GATING_CONTROL_REG 0x32a8 180 181 #define FW_MPI_MBOX_ADDR_REG 0x0360 182 #define FW1X_MPI_INIT1_REG 0x0364 183 #define FW1X_MPI_INIT2_REG 0x0370 184 #define FW1X_MPI_EFUSEADDR_REG 0x0374 185 186 #define FW2X_MPI_EFUSEADDR_REG 0x0364 187 #define FW2X_MPI_CONTROL_REG 0x0368 /* 64bit */ 188 #define FW2X_MPI_STATE_REG 0x0370 /* 64bit */ 189 #define FW_BOOT_EXIT_CODE_REG 0x0388 190 191 #define FW_BOOT_EXIT_CODE_REG 0x0388 192 #define RBL_STATUS_DEAD 0x0000dead 193 #define RBL_STATUS_SUCCESS 0x0000abba 194 #define RBL_STATUS_FAILURE 0x00000bad 195 #define RBL_STATUS_HOST_BOOT 0x0000f1a7 196 #define FW_MPI_DAISY_CHAIN_STATUS_REG 0x0704 197 #define AQ_PCI_REG_CONTROL_6_REG 0x1014 198 199 #define FW_MPI_RESETCTRL_REG 0x4000 200 #define FW_MPI_RESETCTRL_RESET_DIS (1 << 29) 201 202 #define RX_SYSCONTROL_REG 0x5000 203 #define RX_SYSCONTROL_RESET_DIS (1 << 29) 204 205 #define RX_TCP_RSS_HASH_REG 0x5040 206 #define RX_TCP_RSS_HASH_RPF2 (0xf << 16) 207 #define RX_TCP_RSS_HASH_TYPE (0xffff) 208 209 #define RPF_L2BC_REG 0x5100 210 #define RPF_L2BC_EN (1 << 0) 211 #define RPF_L2BC_PROMISC (1 << 3) 212 #define RPF_L2BC_ACTION 0x7000 213 #define RPF_L2BC_THRESHOLD 0xFFFF0000 214 215 #define AQ_HW_MAC_OWN 0 216 217 /* RPF_L2UC_*_REG[34] (actual [38]?) */ 218 #define RPF_L2UC_LSW_REG(i) (0x5110 + (i) * 8) 219 #define RPF_L2UC_MSW_REG(i) (0x5114 + (i) * 8) 220 #define RPF_L2UC_MSW_MACADDR_HI 0xFFFF 221 #define RPF_L2UC_MSW_ACTION 0x70000 222 #define RPF_L2UC_MSW_TAG 0x03c00000 223 #define RPF_L2UC_MSW_EN (1 << 31) 224 #define AQ_HW_MAC_NUM 34 225 226 /* RPF_MCAST_FILTER_REG[8] 0x5250-0x5270 */ 227 #define RPF_MCAST_FILTER_REG(i) (0x5250 + (i) * 4) 228 #define RPF_MCAST_FILTER_EN (1 << 31) 229 #define RPF_MCAST_FILTER_MASK_REG 0x5270 230 #define RPF_MCAST_FILTER_MASK_ALLMULTI (1 << 14) 231 232 #define RPF_VLAN_MODE_REG 0x5280 233 #define RPF_VLAN_MODE_PROMISC (1 << 1) 234 #define RPF_VLAN_MODE_ACCEPT_UNTAGGED (1 << 2) 235 #define RPF_VLAN_MODE_UNTAGGED_ACTION 0x38 236 237 #define RPF_VLAN_TPID_REG 0x5284 238 #define RPF_VLAN_TPID_OUTER 0xFFFF0000 239 #define RPF_VLAN_TPID_INNER 0xFFFF 240 241 /* RPF_ETHERTYPE_FILTER_REG[AQ_RINGS_NUM] 0x5300-0x5380 */ 242 #define RPF_ETHERTYPE_FILTER_REG(i) (0x5300 + (i) * 4) 243 #define RPF_ETHERTYPE_FILTER_EN (1 << 31) 244 245 /* RPF_L3_FILTER_REG[8] 0x5380-0x53a0 */ 246 #define RPF_L3_FILTER_REG(i) (0x5380 + (i) * 4) 247 #define RPF_L3_FILTER_L4_EN (1 << 31) 248 249 #define RX_FLR_RSS_CONTROL1_REG 0x54c0 250 #define RX_FLR_RSS_CONTROL1_EN (1 << 31) 251 252 #define RPF_RPB_RX_TC_UPT_REG 0x54c4 253 #define RPF_RPB_RX_TC_UPT_MASK(i) (0x00000007 << ((i) * 4)) 254 255 #define RPF_RSS_KEY_ADDR_REG 0x54d0 256 #define RPF_RSS_KEY_ADDR 0x1f 257 #define RPF_RSS_KEY_WR_EN (1 << 5) 258 #define RPF_RSS_KEY_WR_DATA_REG 0x54d4 259 #define RPF_RSS_KEY_RD_DATA_REG 0x54d8 260 261 #define RPF_RSS_REDIR_ADDR_REG 0x54e0 262 #define RPF_RSS_REDIR_ADDR 0xf 263 #define RPF_RSS_REDIR_WR_EN (1 << 4) 264 265 #define RPF_RSS_REDIR_WR_DATA_REG 0x54e4 266 267 268 #define RPO_HWCSUM_REG 0x5580 269 #define RPO_HWCSUM_L4CSUM_EN (1 << 0) 270 #define RPO_HWCSUM_IP4CSUM_EN (1 << 1) 271 272 #define RPB_RPF_RX_REG 0x5700 273 #define RPB_RPF_RX_TC_MODE (1 << 8) 274 #define RPB_RPF_RX_FC_MODE 0x30 275 #define RPB_RPF_RX_BUF_EN (1 << 0) 276 277 /* RPB_RXB_BUFSIZE_REG[AQ_TRAFFICCLASS_NUM] 0x5710-0x5790 */ 278 #define RPB_RXB_BUFSIZE_REG(i) (0x5710 + (i) * 0x10) 279 #define RPB_RXB_BUFSIZE 0x1FF 280 #define RPB_RXB_XOFF_REG(i) (0x5714 + (i) * 0x10) 281 #define RPB_RXB_XOFF_EN (1 << 31) 282 #define RPB_RXB_XOFF_THRESH_HI 0x3FFF0000 283 #define RPB_RXB_XOFF_THRESH_LO 0x3FFF 284 285 #define RX_DMA_DESC_CACHE_INIT_REG 0x5a00 286 #define RX_DMA_DESC_CACHE_INIT (1 << 0) 287 288 #define RX_DMA_INT_DESC_WRWB_EN_REG 0x5a30 289 #define RX_DMA_INT_DESC_WRWB_EN (1 << 2) 290 #define RX_DMA_INT_DESC_MODERATE_EN (1 << 3) 291 292 #define RX_INTR_MODERATION_CTL_REG(i) (0x5a40 + (i) * 4) 293 #define RX_INTR_MODERATION_CTL_EN (1 << 1) 294 #define RX_INTR_MODERATION_CTL_MIN (0xFF << 8) 295 #define RX_INTR_MODERATION_CTL_MAX (0x1FF << 16) 296 297 #define RX_DMA_DESC_BASE_ADDRLSW_REG(i) (0x5b00 + (i) * 0x20) 298 #define RX_DMA_DESC_BASE_ADDRMSW_REG(i) (0x5b04 + (i) * 0x20) 299 #define RX_DMA_DESC_REG(i) (0x5b08 + (i) * 0x20) 300 #define RX_DMA_DESC_LEN (0x3FF << 3) 301 #define RX_DMA_DESC_RESET (1 << 25) 302 #define RX_DMA_DESC_HEADER_SPLIT (1 << 28) 303 #define RX_DMA_DESC_VLAN_STRIP (1 << 29) 304 #define RX_DMA_DESC_EN (1 << 31) 305 #define RX_DMA_DESC_HEAD_PTR_REG(i) (0x5b0c + (i) * 0x20) 306 #define RX_DMA_DESC_HEAD_PTR 0xFFF 307 #define RX_DMA_DESC_TAIL_PTR_REG(i) (0x5b10 + (i) * 0x20) 308 #define RX_DMA_DESC_BUFSIZE_REG(i) (0x5b18 + (i) * 0x20) 309 #define RX_DMA_DESC_BUFSIZE_DATA 0x000F 310 #define RX_DMA_DESC_BUFSIZE_HDR 0x0FF0 311 312 #define RX_DMA_DCAD_REG(i) (0x6100 + (i) * 4) 313 #define RX_DMA_DCAD_CPUID 0xFF 314 #define RX_DMA_DCAD_PAYLOAD_EN (1 << 29) 315 #define RX_DMA_DCAD_HEADER_EN (1 << 30) 316 #define RX_DMA_DCAD_DESC_EN (1 << 31) 317 318 #define RX_DMA_DCA_REG 0x6180 319 #define RX_DMA_DCA_EN (1 << 31) 320 #define RX_DMA_DCA_MODE 0xF 321 322 #define TX_SYSCONTROL_REG 0x7000 323 #define TX_SYSCONTROL_RESET_DIS (1 << 29) 324 325 #define TX_TPO2_REG 0x7040 326 #define TX_TPO2_EN (1 << 16) 327 328 #define TPS_DESC_VM_ARB_MODE_REG 0x7300 329 #define TPS_DESC_VM_ARB_MODE (1 << 0) 330 #define TPS_DESC_RATE_REG 0x7310 331 #define TPS_DESC_RATE_TA_RST (1 << 31) 332 #define TPS_DESC_RATE_LIM 0x7FF 333 #define TPS_DESC_TC_ARB_MODE_REG 0x7200 334 #define TPS_DESC_TC_ARB_MODE 0x3 335 #define TPS_DATA_TC_ARB_MODE_REG 0x7100 336 #define TPS_DATA_TC_ARB_MODE (1 << 0) 337 338 /* TPS_DATA_TCT_REG[AQ_TRAFFICCLASS_NUM] 0x7110-0x7130 */ 339 #define TPS_DATA_TCT_REG(i) (0x7110 + (i) * 4) 340 #define TPS_DATA_TCT_CREDIT_MAX 0xFFF0000 341 #define TPS_DATA_TCT_WEIGHT 0x1FF 342 /* TPS_DATA_TCT_REG[AQ_TRAFFICCLASS_NUM] 0x7210-0x7230 */ 343 #define TPS_DESC_TCT_REG(i) (0x7210 + (i) * 4) 344 #define TPS_DESC_TCT_CREDIT_MAX 0xFFF0000 345 #define TPS_DESC_TCT_WEIGHT 0x1FF 346 347 #define AQ_HW_TXBUF_MAX 160 348 #define AQ_HW_RXBUF_MAX 320 349 350 #define TPO_HWCSUM_REG 0x7800 351 #define TPO_HWCSUM_L4CSUM_EN (1 << 0) 352 #define TPO_HWCSUM_IP4CSUM_EN (1 << 1) 353 354 #define THM_LSO_TCP_FLAG1_REG 0x7820 355 #define THM_LSO_TCP_FLAG1_FIRST 0xFFF 356 #define THM_LSO_TCP_FLAG1_MID 0xFFF0000 357 #define THM_LSO_TCP_FLAG2_REG 0x7824 358 #define THM_LSO_TCP_FLAG2_LAST 0xFFF 359 360 #define TPB_TX_BUF_REG 0x7900 361 #define TPB_TX_BUF_EN (1 << 0) 362 #define TPB_TX_BUF_SCP_INS_EN (1 << 2) 363 #define TPB_TX_BUF_CLK_GATE_EN (1 << 5) 364 #define TPB_TX_BUF_TC_MODE_EN (1 << 8) 365 366 367 /* TPB_TXB_BUFSIZE_REG[AQ_TRAFFICCLASS_NUM] 0x7910-7990 */ 368 #define TPB_TXB_BUFSIZE_REG(i) (0x7910 + (i) * 0x10) 369 #define TPB_TXB_BUFSIZE (0xFF) 370 #define TPB_TXB_THRESH_REG(i) (0x7914 + (i) * 0x10) 371 #define TPB_TXB_THRESH_HI 0x1FFF0000 372 #define TPB_TXB_THRESH_LO 0x1FFF 373 374 #define AQ_HW_TX_DMA_TOTAL_REQ_LIMIT_REG 0x7b20 375 376 #define TX_DMA_INT_DESC_WRWB_EN_REG 0x7b40 377 #define TX_DMA_INT_DESC_WRWB_EN (1 << 1) 378 #define TX_DMA_INT_DESC_MODERATE_EN (1 << 4) 379 380 #define TX_DMA_DESC_BASE_ADDRLSW_REG(i) (0x7c00 + (i) * 0x40) 381 #define TX_DMA_DESC_BASE_ADDRMSW_REG(i) (0x7c04 + (i) * 0x40) 382 #define TX_DMA_DESC_REG(i) (0x7c08 + (i) * 0x40) 383 #define TX_DMA_DESC_LEN 0x00000FF8 384 #define TX_DMA_DESC_EN 0x80000000 385 #define TX_DMA_DESC_HEAD_PTR_REG(i) (0x7c0c + (i) * 0x40) 386 #define TX_DMA_DESC_HEAD_PTR 0x00000FFF 387 #define TX_DMA_DESC_TAIL_PTR_REG(i) (0x7c10 + (i) * 0x40) 388 #define TX_DMA_DESC_WRWB_THRESH_REG(i) (0x7c18 + (i) * 0x40) 389 #define TX_DMA_DESC_WRWB_THRESH 0x00003F00 390 391 #define TDM_DCAD_REG(i) (0x8400 + (i) * 4) 392 #define TDM_DCAD_CPUID 0x7F 393 #define TDM_DCAD_CPUID_EN 0x80000000 394 395 #define TDM_DCA_REG 0x8480 396 #define TDM_DCA_EN (1 << 31) 397 #define TDM_DCA_MODE 0xF 398 399 #define TX_INTR_MODERATION_CTL_REG(i) (0x8980 + (i) * 4) 400 #define TX_INTR_MODERATION_CTL_EN (1 << 1) 401 #define TX_INTR_MODERATION_CTL_MIN (0xFF << 8) 402 #define TX_INTR_MODERATION_CTL_MAX (0x1FF << 16) 403 404 /* AQ2 registers */ 405 406 #define AQ2_MIF_HOST_FINISHED_STATUS_WRITE_REG 0x0e00 407 #define AQ2_MIF_HOST_FINISHED_STATUS_READ_REG 0x0e04 408 #define AQ2_MIF_HOST_FINISHED_STATUS_ACK (1 << 0) 409 410 #define AQ2_MCP_HOST_REQ_INT_REG 0x0f00 411 #define AQ2_MCP_HOST_REQ_INT_READY (1 << 0) 412 #define AQ2_MCP_HOST_REQ_INT_SET_REG 0x0f04 413 #define AQ2_MCP_HOST_REQ_INT_CLR_REG 0x0f08 414 415 #define AQ2_MIF_BOOT_REG 0x3040 416 #define AQ2_MIF_BOOT_HOST_DATA_LOADED (1 << 16) 417 #define AQ2_MIF_BOOT_BOOT_STARTED (1 << 24) 418 #define AQ2_MIF_BOOT_CRASH_INIT (1 << 27) 419 #define AQ2_MIF_BOOT_BOOT_CODE_FAILED (1 << 28) 420 #define AQ2_MIF_BOOT_FW_INIT_FAILED (1 << 29) 421 #define AQ2_MIF_BOOT_FW_INIT_COMP_SUCCESS (1 << 31) 422 423 /* AQ2 action resolver table */ 424 #define AQ2_ART_ACTION_ACT_SHIFT 8 425 #define AQ2_ART_ACTION_RSS 0x0080 426 #define AQ2_ART_ACTION_INDEX_SHIFT 2 427 #define AQ2_ART_ACTION_ENABLE 0x0001 428 #define AQ2_ART_ACTION(act, rss, idx, en) \ 429 (((act) << AQ2_ART_ACTION_ACT_SHIFT) | \ 430 ((rss) ? AQ2_ART_ACTION_RSS : 0) | \ 431 ((idx) << AQ2_ART_ACTION_INDEX_SHIFT) | \ 432 ((en) ? AQ2_ART_ACTION_ENABLE : 0)) 433 #define AQ2_ART_ACTION_DROP AQ2_ART_ACTION(0, 0, 0, 1) 434 #define AQ2_ART_ACTION_DISABLE AQ2_ART_ACTION(0, 0, 0, 0) 435 #define AQ2_ART_ACTION_ASSIGN_QUEUE(q) AQ2_ART_ACTION(1, 0, (q), 1) 436 #define AQ2_ART_ACTION_ASSIGN_TC(tc) AQ2_ART_ACTION(1, 1, (tc), 1) 437 438 #define AQ2_RPF_TAG_PCP_MASK 0xe0000000 439 #define AQ2_RPF_TAG_PCP_SHIFT 29 440 #define AQ2_RPF_TAG_FLEX_MASK 0x18000000 441 #define AQ2_RPF_TAG_UNKNOWN_MASK 0x07000000 442 #define AQ2_RPF_TAG_L4_MASK 0x00e00000 443 #define AQ2_RPF_TAG_L3_V6_MASK 0x001c0000 444 #define AQ2_RPF_TAG_L3_V4_MASK 0x00038000 445 #define AQ2_RPF_TAG_UNTAG_MASK 0x00004000 446 #define AQ2_RPF_TAG_VLAN_MASK 0x00003c00 447 #define AQ2_RPF_TAG_ET_MASK 0x00000380 448 #define AQ2_RPF_TAG_ALLMC_MASK 0x00000040 449 #define AQ2_RPF_TAG_UC_MASK 0x0000002f 450 451 /* index of aq2_filter_art_set() */ 452 #define AQ2_RPF_INDEX_L2_PROMISC_OFF 0 453 #define AQ2_RPF_INDEX_VLAN_PROMISC_OFF 1 454 #define AQ2_RPF_INDEX_L3L4_USER 8 455 #define AQ2_RPF_INDEX_ET_PCP_USER 24 456 #define AQ2_RPF_INDEX_VLAN_USER 40 457 #define AQ2_RPF_INDEX_PCP_TO_TC 56 458 459 #define AQ2_RPF_L2BC_TAG_REG 0x50f0 460 #define AQ2_RPF_L2BC_TAG_MASK 0x0000003f 461 462 #define AQ2_RPF_NEW_CTRL_REG 0x5104 463 #define AQ2_RPF_NEW_CTRL_ENABLE (1 << 11) 464 465 #define AQ2_RPF_REDIR2_REG 0x54c8 466 #define AQ2_RPF_REDIR2_INDEX (1 << 12) 467 #define AQ2_RPF_REDIR2_HASHTYPE 0x00000100 468 #define AQ2_RPF_REDIR2_HASHTYPE_NONE 0 469 #define AQ2_RPF_REDIR2_HASHTYPE_IP (1 << 0) 470 #define AQ2_RPF_REDIR2_HASHTYPE_TCP4 (1 << 1) 471 #define AQ2_RPF_REDIR2_HASHTYPE_UDP4 (1 << 2) 472 #define AQ2_RPF_REDIR2_HASHTYPE_IP6 (1 << 3) 473 #define AQ2_RPF_REDIR2_HASHTYPE_TCP6 (1 << 4) 474 #define AQ2_RPF_REDIR2_HASHTYPE_UDP6 (1 << 5) 475 #define AQ2_RPF_REDIR2_HASHTYPE_IP6EX (1 << 6) 476 #define AQ2_RPF_REDIR2_HASHTYPE_TCP6EX (1 << 7) 477 #define AQ2_RPF_REDIR2_HASHTYPE_UDP6EX (1 << 8) 478 #define AQ2_RPF_REDIR2_HASHTYPE_ALL 0x00000100 479 480 #define AQ2_RPF_REC_TAB_ENABLE_REG 0x6ff0 481 #define AQ2_RPF_REC_TAB_ENABLE_MASK 0x0000ffff 482 483 #define AQ2_LAUNCHTIME_CTRL_REG 0x7a1c 484 #define AQ2_LAUNCHTIME_CTRL_RATIO 0x0000ff00 485 #define AQ2_LAUNCHTIME_CTRL_RATIO_SPEED_QUARTER 4 486 #define AQ2_LAUNCHTIME_CTRL_RATIO_SPEED_HALF 2 487 #define AQ2_LAUNCHTIME_CTRL_RATIO_SPEED_FULL 1 488 489 #define AQ2_TX_INTR_MODERATION_CTL_REG(i) (0x7c28 + (i) * 0x40) 490 #define AQ2_TX_INTR_MODERATION_CTL_EN (1 << 1) 491 #define AQ2_TX_INTR_MODERATION_CTL_MIN 0x0000ff00 492 #define AQ2_TX_INTR_MODERATION_CTL_MAX 0x01ff0000 493 494 #define AQ2_FW_INTERFACE_IN_MTU_REG 0x12000 495 #define AQ2_FW_INTERFACE_IN_MAC_ADDRESS_REG 0x12008 496 497 #define AQ2_FW_INTERFACE_IN_LINK_CONTROL_REG 0x12010 498 #define AQ2_FW_INTERFACE_IN_LINK_CONTROL_MODE 0x0000000f 499 #define AQ2_FW_INTERFACE_IN_LINK_CONTROL_MODE_INVALID 0 500 #define AQ2_FW_INTERFACE_IN_LINK_CONTROL_MODE_ACTIVE 1 501 #define AQ2_FW_INTERFACE_IN_LINK_CONTROL_MODE_SLEEP_PROXY 2 502 #define AQ2_FW_INTERFACE_IN_LINK_CONTROL_MODE_LOWPOWER 3 503 #define AQ2_FW_INTERFACE_IN_LINK_CONTROL_MODE_SHUTDOWN 4 504 505 #define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_REG 0x12018 506 #define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_DOWNSHIFT (1 << 27) 507 #define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_PAUSE_TX (1 << 25) 508 #define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_PAUSE_RX (1 << 24) 509 #define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_EEE_10G (1 << 20) 510 #define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_EEE_5G (1 << 19) 511 #define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_EEE_2G5 (1 << 18) 512 #define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_EEE_1G (1 << 17) 513 #define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_EEE_100M (1 << 16) 514 #define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_10G (1 << 15) 515 #define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_N5G (1 << 14) 516 #define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_5G (1 << 13) 517 #define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_N2G5 (1 << 12) 518 #define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_2G5 (1 << 11) 519 #define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_1G (1 << 10) 520 #define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_100M (1 << 9) 521 #define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_10M (1 << 8) 522 #define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_1G_HD (1 << 7) 523 #define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_100M_HD (1 << 6) 524 #define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_10M_HD (1 << 5) 525 #define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_EXTERNAL_LOOPBACK (1 << 4) 526 #define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_INTERNAL_LOOPBACK (1 << 3) 527 #define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_MINIMAL_LINK_SPEED (1 << 2) 528 #define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_LINK_RENEGOTIATE (1 << 1) 529 #define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_LINK_UP (1 << 0) 530 531 #define AQ2_FW_INTERFACE_IN_REQUEST_POLICY_REG 0x12a58 532 #define AQ2_FW_INTERFACE_IN_REQUEST_POLICY_MCAST_QUEUE_OR_TC 0x00800000 533 #define AQ2_FW_INTERFACE_IN_REQUEST_POLICY_MCAST_RX_QUEUE_TC_INDEX 0x007c0000 534 #define AQ2_FW_INTERFACE_IN_REQUEST_POLICY_MCAST_ACCEPT 0x00010000 535 #define AQ2_FW_INTERFACE_IN_REQUEST_POLICY_BCAST_QUEUE_OR_TC 0x00008000 536 #define AQ2_FW_INTERFACE_IN_REQUEST_POLICY_BCAST_RX_QUEUE_TC_INDEX 0x00007c00 537 #define AQ2_FW_INTERFACE_IN_REQUEST_POLICY_BCAST_ACCEPT 0x00000100 538 #define AQ2_FW_INTERFACE_IN_REQUEST_POLICY_PROMISC_QUEUE_OR_TC 0x00000080 539 #define AQ2_FW_INTERFACE_IN_REQUEST_POLICY_PROMISC_RX_QUEUE_TX_INDEX 0x0000007c 540 #define AQ2_FW_INTERFACE_IN_REQUEST_POLICY_PROMISC_MCAST 0x00000002 541 #define AQ2_FW_INTERFACE_IN_REQUEST_POLICY_PROMISC_ALL 0x00000001 542 543 #define AQ2_FW_INTERFACE_OUT_TRANSACTION_ID_REG 0x13000 544 #define AQ2_FW_INTERFACE_OUT_TRANSACTION_ID_B 0xffff0000 545 #define AQ2_FW_INTERFACE_OUT_TRANSACTION_ID_B_S 16 546 #define AQ2_FW_INTERFACE_OUT_TRANSACTION_ID_A 0x0000ffff 547 #define AQ2_FW_INTERFACE_OUT_TRANSACTION_ID_A_S 0 548 549 #define AQ2_FW_INTERFACE_OUT_VERSION_BUNDLE_REG 0x13004 550 #define AQ2_FW_INTERFACE_OUT_VERSION_MAC_REG 0x13008 551 552 #define AQ2_FW_INTERFACE_OUT_VERSION_PHY_REG 0x1300c 553 #define AQ2_FW_INTERFACE_OUT_VERSION_BUILD 0xffff0000 554 #define AQ2_FW_INTERFACE_OUT_VERSION_BUILD_S 16 555 #define AQ2_FW_INTERFACE_OUT_VERSION_MINOR 0x0000ff00 556 #define AQ2_FW_INTERFACE_OUT_VERSION_MINOR_S 8 557 #define AQ2_FW_INTERFACE_OUT_VERSION_MAJOR 0x000000ff 558 #define AQ2_FW_INTERFACE_OUT_VERSION_MAJOR_S 0 559 560 #define AQ2_FW_INTERFACE_OUT_VERSION_IFACE_REG 0x13010 561 #define AQ2_FW_INTERFACE_OUT_VERSION_IFACE_VER 0x0000000f 562 #define AQ2_FW_INTERFACE_OUT_VERSION_IFACE_VER_A0 0 563 #define AQ2_FW_INTERFACE_OUT_VERSION_IFACE_VER_B0 1 564 565 #define AQ2_FW_INTERFACE_OUT_LINK_STATUS_REG 0x13014 566 #define AQ2_FW_INTERFACE_OUT_LINK_STATUS_DUPLEX (1 << 11) 567 #define AQ2_FW_INTERFACE_OUT_LINK_STATUS_EEE (1 << 10) 568 #define AQ2_FW_INTERFACE_OUT_LINK_STATUS_PAUSE_RX (1 << 9) 569 #define AQ2_FW_INTERFACE_OUT_LINK_STATUS_PAUSE_TX (1 << 8) 570 #define AQ2_FW_INTERFACE_OUT_LINK_STATUS_RATE 0x000000f0 571 #define AQ2_FW_INTERFACE_OUT_LINK_STATUS_RATE_S 4 572 #define AQ2_FW_INTERFACE_OUT_LINK_STATUS_RATE_10G 6 573 #define AQ2_FW_INTERFACE_OUT_LINK_STATUS_RATE_5G 5 574 #define AQ2_FW_INTERFACE_OUT_LINK_STATUS_RATE_2G5 4 575 #define AQ2_FW_INTERFACE_OUT_LINK_STATUS_RATE_1G 3 576 #define AQ2_FW_INTERFACE_OUT_LINK_STATUS_RATE_100M 2 577 #define AQ2_FW_INTERFACE_OUT_LINK_STATUS_RATE_10M 1 578 #define AQ2_FW_INTERFACE_OUT_LINK_STATUS_RATE_INVALID 0 579 #define AQ2_FW_INTERFACE_OUT_LINK_STATUS_STATE 0x0000000f 580 581 #define AQ2_FW_INTERFACE_OUT_FILTER_CAPS_REG 0x13774 582 #define AQ2_FW_INTERFACE_OUT_FILTER_CAPS3_RESOLVER_BASE_INDEX 0x00ff0000 583 #define AQ2_FW_INTERFACE_OUT_FILTER_CAPS3_RESOLVER_BASE_INDEX_SHIFT 16 584 585 #define AQ2_RPF_ACT_ART_REQ_TAG_REG(i) (0x14000 + (i) * 0x10) 586 #define AQ2_RPF_ACT_ART_REQ_MASK_REG(i) (0x14004 + (i) * 0x10) 587 #define AQ2_RPF_ACT_ART_REQ_ACTION_REG(i) (0x14008 + (i) * 0x10) 588 589 #define __LOWEST_SET_BIT(__mask) (((((uint32_t)__mask) - 1) & ((uint32_t)__mask)) ^ ((uint32_t)__mask)) 590 #define __SHIFTIN(__x, __mask) ((__x) * __LOWEST_SET_BIT(__mask)) 591 592 #define AQ_READ_REG(sc, reg) \ 593 bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)) 594 #define AQ_READ_REGS(sc, reg, p, cnt) \ 595 bus_space_read_region_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (p), (cnt)); 596 597 #define AQ_WRITE_REG(sc, reg, val) \ 598 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 599 600 #define AQ_WRITE_REG_BIT(sc, reg, mask, val) \ 601 do { \ 602 uint32_t _v; \ 603 _v = AQ_READ_REG((sc), (reg)); \ 604 _v &= ~(mask); \ 605 if ((val) != 0) \ 606 _v |= __SHIFTIN((val), (mask)); \ 607 AQ_WRITE_REG((sc), (reg), _v); \ 608 } while (/* CONSTCOND */ 0) 609 610 #define AQ_READ64_REG(sc, reg) \ 611 ((uint64_t)AQ_READ_REG(sc, reg) | \ 612 (((uint64_t)AQ_READ_REG(sc, (reg) + 4)) << 32)) 613 614 #define AQ_WRITE64_REG(sc, reg, val) \ 615 do { \ 616 AQ_WRITE_REG(sc, reg, (uint32_t)val); \ 617 AQ_WRITE_REG(sc, reg + 4, (uint32_t)(val >> 32)); \ 618 } while (/* CONSTCOND */0) 619 620 #define WAIT_FOR(expr, us, n, errp) \ 621 do { \ 622 unsigned int _n; \ 623 for (_n = n; (!(expr)) && _n != 0; --_n) { \ 624 delay((us)); \ 625 } \ 626 if ((errp != NULL)) { \ 627 if (_n == 0) \ 628 *(errp) = ETIMEDOUT; \ 629 else \ 630 *(errp) = 0; \ 631 } \ 632 } while (/* CONSTCOND */ 0) 633 634 #define FW_VERSION_MAJOR(sc) (((sc)->sc_fw_version >> 24) & 0xff) 635 #define FW_VERSION_MINOR(sc) (((sc)->sc_fw_version >> 16) & 0xff) 636 #define FW_VERSION_BUILD(sc) ((sc)->sc_fw_version & 0xffff) 637 638 #define FEATURES_MIPS 0x00000001 639 #define FEATURES_TPO2 0x00000002 640 #define FEATURES_RPF2 0x00000004 641 #define FEATURES_MPI_AQ 0x00000008 642 #define FEATURES_AQ1_REV_A0 0x01000000 643 #define FEATURES_AQ1_REV_A (FEATURES_AQ1_REV_A0) 644 #define FEATURES_AQ1_REV_B0 0x02000000 645 #define FEATURES_AQ1_REV_B1 0x04000000 646 #define FEATURES_AQ1_REV_B (FEATURES_AQ1_REV_B0|FEATURES_AQ1_REV_B1) 647 #define FEATURES_AQ1 (FEATURES_AQ1_REV_A|FEATURES_AQ1_REV_B) 648 #define FEATURES_AQ2 0x10000000 649 #define FEATURES_AQ2_IFACE_A0 0x20000000 650 #define FEATURES_AQ2_IFACE_B0 0x40000000 651 #define HWTYPE_AQ1_P(sc) (((sc)->sc_features & FEATURES_AQ1) != 0) 652 #define HWTYPE_AQ2_P(sc) (((sc)->sc_features & FEATURES_AQ2) != 0) 653 654 /* lock for firmware interface */ 655 #define AQ_MPI_LOCK(sc) mtx_enter(&(sc)->sc_mpi_mutex); 656 #define AQ_MPI_UNLOCK(sc) mtx_leave(&(sc)->sc_mpi_mutex); 657 658 #define FW2X_CTRL_10BASET_HD (1 << 0) 659 #define FW2X_CTRL_10BASET_FD (1 << 1) 660 #define FW2X_CTRL_100BASETX_HD (1 << 2) 661 #define FW2X_CTRL_100BASET4_HD (1 << 3) 662 #define FW2X_CTRL_100BASET2_HD (1 << 4) 663 #define FW2X_CTRL_100BASETX_FD (1 << 5) 664 #define FW2X_CTRL_100BASET2_FD (1 << 6) 665 #define FW2X_CTRL_1000BASET_HD (1 << 7) 666 #define FW2X_CTRL_1000BASET_FD (1 << 8) 667 #define FW2X_CTRL_2P5GBASET_FD (1 << 9) 668 #define FW2X_CTRL_5GBASET_FD (1 << 10) 669 #define FW2X_CTRL_10GBASET_FD (1 << 11) 670 #define FW2X_CTRL_RESERVED1 (1ULL << 32) 671 #define FW2X_CTRL_10BASET_EEE (1ULL << 33) 672 #define FW2X_CTRL_RESERVED2 (1ULL << 34) 673 #define FW2X_CTRL_PAUSE (1ULL << 35) 674 #define FW2X_CTRL_ASYMMETRIC_PAUSE (1ULL << 36) 675 #define FW2X_CTRL_100BASETX_EEE (1ULL << 37) 676 #define FW2X_CTRL_RESERVED3 (1ULL << 38) 677 #define FW2X_CTRL_RESERVED4 (1ULL << 39) 678 #define FW2X_CTRL_1000BASET_FD_EEE (1ULL << 40) 679 #define FW2X_CTRL_2P5GBASET_FD_EEE (1ULL << 41) 680 #define FW2X_CTRL_5GBASET_FD_EEE (1ULL << 42) 681 #define FW2X_CTRL_10GBASET_FD_EEE (1ULL << 43) 682 #define FW2X_CTRL_RESERVED5 (1ULL << 44) 683 #define FW2X_CTRL_RESERVED6 (1ULL << 45) 684 #define FW2X_CTRL_RESERVED7 (1ULL << 46) 685 #define FW2X_CTRL_RESERVED8 (1ULL << 47) 686 #define FW2X_CTRL_RESERVED9 (1ULL << 48) 687 #define FW2X_CTRL_CABLE_DIAG (1ULL << 49) 688 #define FW2X_CTRL_TEMPERATURE (1ULL << 50) 689 #define FW2X_CTRL_DOWNSHIFT (1ULL << 51) 690 #define FW2X_CTRL_PTP_AVB_EN (1ULL << 52) 691 #define FW2X_CTRL_MEDIA_DETECT (1ULL << 53) 692 #define FW2X_CTRL_LINK_DROP (1ULL << 54) 693 #define FW2X_CTRL_SLEEP_PROXY (1ULL << 55) 694 #define FW2X_CTRL_WOL (1ULL << 56) 695 #define FW2X_CTRL_MAC_STOP (1ULL << 57) 696 #define FW2X_CTRL_EXT_LOOPBACK (1ULL << 58) 697 #define FW2X_CTRL_INT_LOOPBACK (1ULL << 59) 698 #define FW2X_CTRL_EFUSE_AGENT (1ULL << 60) 699 #define FW2X_CTRL_WOL_TIMER (1ULL << 61) 700 #define FW2X_CTRL_STATISTICS (1ULL << 62) 701 #define FW2X_CTRL_TRANSACTION_ID (1ULL << 63) 702 703 #define FW2X_CTRL_RATE_100M FW2X_CTRL_100BASETX_FD 704 #define FW2X_CTRL_RATE_1G FW2X_CTRL_1000BASET_FD 705 #define FW2X_CTRL_RATE_2G5 FW2X_CTRL_2P5GBASET_FD 706 #define FW2X_CTRL_RATE_5G FW2X_CTRL_5GBASET_FD 707 #define FW2X_CTRL_RATE_10G FW2X_CTRL_10GBASET_FD 708 #define FW2X_CTRL_RATE_MASK \ 709 (FW2X_CTRL_RATE_100M | \ 710 FW2X_CTRL_RATE_1G | \ 711 FW2X_CTRL_RATE_2G5 | \ 712 FW2X_CTRL_RATE_5G | \ 713 FW2X_CTRL_RATE_10G) 714 #define FW2X_CTRL_EEE_MASK \ 715 (FW2X_CTRL_10BASET_EEE | \ 716 FW2X_CTRL_100BASETX_EEE | \ 717 FW2X_CTRL_1000BASET_FD_EEE | \ 718 FW2X_CTRL_2P5GBASET_FD_EEE | \ 719 FW2X_CTRL_5GBASET_FD_EEE | \ 720 FW2X_CTRL_10GBASET_FD_EEE) 721 722 enum aq_hwtype { 723 HWTYPE_AQ1, 724 HWTYPE_AQ2 725 }; 726 727 enum aq_fw_bootloader_mode { 728 FW_BOOT_MODE_UNKNOWN = 0, 729 FW_BOOT_MODE_FLB, 730 FW_BOOT_MODE_RBL_FLASH, 731 FW_BOOT_MODE_RBL_HOST_BOOTLOAD 732 }; 733 734 enum aq_media_type { 735 AQ_MEDIA_TYPE_UNKNOWN = 0, 736 AQ_MEDIA_TYPE_FIBRE, 737 AQ_MEDIA_TYPE_TP 738 }; 739 740 enum aq_link_speed { 741 AQ_LINK_NONE = 0, 742 AQ_LINK_10M = (1 << 0), 743 AQ_LINK_100M = (1 << 1), 744 AQ_LINK_1G = (1 << 2), 745 AQ_LINK_2G5 = (1 << 3), 746 AQ_LINK_5G = (1 << 4), 747 AQ_LINK_10G = (1 << 5) 748 }; 749 750 #define AQ_LINK_ALL (AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5 | \ 751 AQ_LINK_5G | AQ_LINK_10G ) 752 #define AQ_LINK_AUTO AQ_LINK_ALL 753 754 enum aq_link_eee { 755 AQ_EEE_DISABLE = 0, 756 AQ_EEE_ENABLE = 1 757 }; 758 759 enum aq_hw_fw_mpi_state { 760 MPI_DEINIT = 0, 761 MPI_RESET = 1, 762 MPI_INIT = 2, 763 MPI_POWER = 4 764 }; 765 766 enum aq_link_fc { 767 AQ_FC_NONE = 0, 768 AQ_FC_RX = (1 << 0), 769 AQ_FC_TX = (1 << 1), 770 AQ_FC_ALL = (AQ_FC_RX | AQ_FC_TX) 771 }; 772 773 struct aq_dmamem { 774 bus_dmamap_t aqm_map; 775 bus_dma_segment_t aqm_seg; 776 int aqm_nsegs; 777 size_t aqm_size; 778 caddr_t aqm_kva; 779 }; 780 781 #define AQ_DMA_MAP(_aqm) ((_aqm)->aqm_map) 782 #define AQ_DMA_DVA(_aqm) ((_aqm)->aqm_map->dm_segs[0].ds_addr) 783 #define AQ_DMA_KVA(_aqm) ((void *)(_aqm)->aqm_kva) 784 #define AQ_DMA_LEN(_aqm) ((_aqm)->aqm_size) 785 786 787 struct aq_mailbox_header { 788 uint32_t version; 789 uint32_t transaction_id; 790 int32_t error; 791 } __packed __aligned(4); 792 793 struct aq_hw_stats_s { 794 uint32_t uprc; 795 uint32_t mprc; 796 uint32_t bprc; 797 uint32_t erpt; 798 uint32_t uptc; 799 uint32_t mptc; 800 uint32_t bptc; 801 uint32_t erpr; 802 uint32_t mbtc; 803 uint32_t bbtc; 804 uint32_t mbrc; 805 uint32_t bbrc; 806 uint32_t ubrc; 807 uint32_t ubtc; 808 uint32_t ptc; 809 uint32_t prc; 810 uint32_t dpc; /* not exists in fw2x_msm_statistics */ 811 uint32_t cprc; /* not exists in fw2x_msm_statistics */ 812 } __packed __aligned(4); 813 814 struct aq_fw2x_capabilities { 815 uint32_t caps_lo; 816 uint32_t caps_hi; 817 } __packed __aligned(4); 818 819 struct aq_fw2x_msm_statistics { 820 uint32_t uprc; 821 uint32_t mprc; 822 uint32_t bprc; 823 uint32_t erpt; 824 uint32_t uptc; 825 uint32_t mptc; 826 uint32_t bptc; 827 uint32_t erpr; 828 uint32_t mbtc; 829 uint32_t bbtc; 830 uint32_t mbrc; 831 uint32_t bbrc; 832 uint32_t ubrc; 833 uint32_t ubtc; 834 uint32_t ptc; 835 uint32_t prc; 836 } __packed __aligned(4); 837 838 struct aq_fw2x_phy_cable_diag_data { 839 uint32_t lane_data[4]; 840 } __packed __aligned(4); 841 842 struct aq_fw2x_mailbox { /* struct fwHostInterface */ 843 struct aq_mailbox_header header; 844 struct aq_fw2x_msm_statistics msm; /* msmStatistics_t msm; */ 845 846 uint32_t phy_info1; 847 #define PHYINFO1_FAULT_CODE __BITS(31,16) 848 #define PHYINFO1_PHY_H_BIT __BITS(0,15) 849 uint32_t phy_info2; 850 #define PHYINFO2_TEMPERATURE __BITS(15,0) 851 #define PHYINFO2_CABLE_LEN __BITS(23,16) 852 853 struct aq_fw2x_phy_cable_diag_data diag_data; 854 uint32_t reserved[8]; 855 856 struct aq_fw2x_capabilities caps; 857 858 /* ... */ 859 } __packed __aligned(4); 860 861 struct aq_rx_desc_read { 862 uint64_t buf_addr; 863 uint64_t hdr_addr; 864 } __packed; 865 866 struct aq_rx_desc_wb { 867 uint32_t type; 868 #define AQ_RXDESC_TYPE_RSSTYPE 0x000f 869 #define AQ_RXDESC_TYPE_ETHER 0x0030 870 #define AQ_RXDESC_TYPE_PROTO 0x01c0 871 #define AQ_RXDESC_TYPE_VLAN (1 << 9) 872 #define AQ_RXDESC_TYPE_VLAN2 (1 << 10) 873 #define AQ_RXDESC_TYPE_DMA_ERR (1 << 12) 874 #define AQ_RXDESC_TYPE_V4_SUM (1 << 19) 875 #define AQ_RXDESC_TYPE_L4_SUM (1 << 20) 876 uint32_t rss_hash; 877 uint16_t status; 878 #define AQ_RXDESC_STATUS_DD (1 << 0) 879 #define AQ_RXDESC_STATUS_EOP (1 << 1) 880 #define AQ_RXDESC_STATUS_MACERR (1 << 2) 881 #define AQ_RXDESC_STATUS_V4_SUM_NG (1 << 3) 882 #define AQ_RXDESC_STATUS_L4_SUM_ERR (1 << 4) 883 #define AQ_RXDESC_STATUS_L4_SUM_OK (1 << 5) 884 uint16_t pkt_len; 885 uint16_t next_desc_ptr; 886 uint16_t vlan; 887 } __packed; 888 889 struct aq_tx_desc { 890 uint64_t buf_addr; 891 uint32_t ctl1; 892 #define AQ_TXDESC_CTL1_TYPE_TXD 0x00000001 893 #define AQ_TXDESC_CTL1_TYPE_TXC 0x00000002 894 #define AQ_TXDESC_CTL1_BLEN_SHIFT 4 895 #define AQ_TXDESC_CTL1_VLAN_SHIFT 4 896 #define AQ_TXDESC_CTL1_DD (1 << 20) 897 #define AQ_TXDESC_CTL1_CMD_EOP (1 << 21) 898 #define AQ_TXDESC_CTL1_CMD_VLAN (1 << 22) 899 #define AQ_TXDESC_CTL1_CMD_FCS (1 << 23) 900 #define AQ_TXDESC_CTL1_CMD_IP4CSUM (1 << 24) 901 #define AQ_TXDESC_CTL1_CMD_L4CSUM (1 << 25) 902 #define AQ_TXDESC_CTL1_CMD_WB (1 << 27) 903 904 #define AQ_TXDESC_CTL1_VID_SHIFT 4 905 uint32_t ctl2; 906 #define AQ_TXDESC_CTL2_LEN_SHIFT 14 907 #define AQ_TXDESC_CTL2_CTX_EN (1 << 13) 908 } __packed; 909 910 struct aq_slot { 911 bus_dmamap_t as_map; 912 struct mbuf *as_m; 913 }; 914 915 struct aq_rxring { 916 struct ifiqueue *rx_ifiq; 917 struct aq_dmamem rx_mem; 918 struct aq_slot *rx_slots; 919 int rx_q; 920 int rx_irq; 921 922 struct timeout rx_refill; 923 struct if_rxring rx_rxr; 924 uint32_t rx_prod; 925 uint32_t rx_cons; 926 927 struct mbuf *rx_m_head; 928 struct mbuf **rx_m_tail; 929 int rx_m_error; 930 }; 931 932 struct aq_txring { 933 struct ifqueue *tx_ifq; 934 struct aq_dmamem tx_mem; 935 struct aq_slot *tx_slots; 936 int tx_q; 937 int tx_irq; 938 uint32_t tx_prod; 939 uint32_t tx_cons; 940 }; 941 942 struct aq_queues { 943 char q_name[16]; 944 void *q_ihc; 945 struct aq_softc *q_sc; 946 int q_index; 947 struct aq_rxring q_rx; 948 struct aq_txring q_tx; 949 }; 950 951 952 struct aq_softc; 953 struct aq_firmware_ops { 954 int (*reset)(struct aq_softc *); 955 int (*get_mac_addr)(struct aq_softc *); 956 int (*set_mode)(struct aq_softc *, enum aq_hw_fw_mpi_state, 957 enum aq_link_speed, enum aq_link_fc, enum aq_link_eee); 958 int (*get_mode)(struct aq_softc *, enum aq_hw_fw_mpi_state *, 959 enum aq_link_speed *, enum aq_link_fc *, enum aq_link_eee *); 960 int (*get_stats)(struct aq_softc *, struct aq_hw_stats_s *); 961 }; 962 963 struct aq_softc { 964 struct device sc_dev; 965 uint16_t sc_product; 966 uint16_t sc_revision; 967 bus_dma_tag_t sc_dmat; 968 pci_chipset_tag_t sc_pc; 969 pcitag_t sc_pcitag; 970 int sc_nqueues; 971 struct aq_queues sc_queues[AQ_MAXQ]; 972 struct intrmap *sc_intrmap; 973 void *sc_ih; 974 bus_space_handle_t sc_ioh; 975 bus_space_tag_t sc_iot; 976 977 uint32_t sc_mbox_addr; 978 int sc_rbl_enabled; 979 int sc_fast_start_enabled; 980 int sc_flash_present; 981 int sc_art_filter_base_index; 982 uint32_t sc_fw_version; 983 const struct aq_firmware_ops *sc_fw_ops; 984 uint64_t sc_fw_caps; 985 enum aq_media_type sc_media_type; 986 enum aq_link_speed sc_available_rates; 987 uint32_t sc_features; 988 int sc_linkstat_irq; 989 struct arpcom sc_arpcom; 990 struct ifmedia sc_media; 991 992 struct ether_addr sc_enaddr; 993 struct mutex sc_mpi_mutex; 994 }; 995 996 const struct pci_matchid aq_devices[] = { 997 { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC100 }, 998 { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC107 }, 999 { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC108 }, 1000 { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC109 }, 1001 { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC111 }, 1002 { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC112 }, 1003 { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC113 }, 1004 { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC113C }, 1005 { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC113CA }, 1006 { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC113CS }, 1007 { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC114CS }, 1008 { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC115C }, 1009 { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC116C }, 1010 { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC100S }, 1011 { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC107S }, 1012 { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC108S }, 1013 { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC109S }, 1014 { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC111S }, 1015 { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC112S }, 1016 { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_D100 }, 1017 { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_D107 }, 1018 { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_D108 }, 1019 { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_D109 }, 1020 }; 1021 1022 const struct aq_product { 1023 pci_vendor_id_t aq_vendor; 1024 pci_product_id_t aq_product; 1025 enum aq_hwtype aq_hwtype; 1026 enum aq_media_type aq_media_type; 1027 enum aq_link_speed aq_available_rates; 1028 } aq_products[] = { 1029 { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC100, HWTYPE_AQ1, 1030 AQ_MEDIA_TYPE_FIBRE, AQ_LINK_ALL 1031 }, 1032 { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC107, HWTYPE_AQ1, 1033 AQ_MEDIA_TYPE_TP, AQ_LINK_ALL 1034 }, 1035 { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC108, HWTYPE_AQ1, 1036 AQ_MEDIA_TYPE_TP, AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5 | AQ_LINK_5G 1037 }, 1038 { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC109, HWTYPE_AQ1, 1039 AQ_MEDIA_TYPE_TP, AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5 1040 }, 1041 { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC111, HWTYPE_AQ1, 1042 AQ_MEDIA_TYPE_TP, AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5 | AQ_LINK_5G 1043 }, 1044 { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC112, HWTYPE_AQ1, 1045 AQ_MEDIA_TYPE_TP, AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5 1046 }, 1047 { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC100S, HWTYPE_AQ1, 1048 AQ_MEDIA_TYPE_FIBRE, AQ_LINK_ALL 1049 }, 1050 { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC107S, HWTYPE_AQ1, 1051 AQ_MEDIA_TYPE_TP, AQ_LINK_ALL 1052 }, 1053 { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC108S, HWTYPE_AQ1, 1054 AQ_MEDIA_TYPE_TP, AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5 | AQ_LINK_5G 1055 }, 1056 { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC109S, HWTYPE_AQ1, 1057 AQ_MEDIA_TYPE_TP, AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5 1058 }, 1059 { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC111S, HWTYPE_AQ1, 1060 AQ_MEDIA_TYPE_TP, AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5 | AQ_LINK_5G 1061 }, 1062 { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC112S, HWTYPE_AQ1, 1063 AQ_MEDIA_TYPE_TP, AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5 1064 }, 1065 { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_D100, HWTYPE_AQ1, 1066 AQ_MEDIA_TYPE_FIBRE, AQ_LINK_ALL 1067 }, 1068 { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_D107, HWTYPE_AQ1, 1069 AQ_MEDIA_TYPE_TP, AQ_LINK_ALL 1070 }, 1071 { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_D108, HWTYPE_AQ1, 1072 AQ_MEDIA_TYPE_TP, AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5 | AQ_LINK_5G 1073 }, 1074 { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_D109, HWTYPE_AQ1, 1075 AQ_MEDIA_TYPE_TP, AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5 1076 }, 1077 1078 { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC113, HWTYPE_AQ2, 1079 AQ_MEDIA_TYPE_TP, AQ_LINK_ALL | AQ_LINK_10M 1080 }, 1081 { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC113C, HWTYPE_AQ2, 1082 AQ_MEDIA_TYPE_TP, AQ_LINK_ALL | AQ_LINK_10M 1083 }, 1084 { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC113CA, HWTYPE_AQ2, 1085 AQ_MEDIA_TYPE_TP, AQ_LINK_ALL | AQ_LINK_10M 1086 }, 1087 { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC113CS, HWTYPE_AQ2, 1088 AQ_MEDIA_TYPE_TP, AQ_LINK_ALL | AQ_LINK_10M 1089 }, 1090 { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC114CS, HWTYPE_AQ2, 1091 AQ_MEDIA_TYPE_TP, 1092 AQ_LINK_10M | AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5 | AQ_LINK_5G 1093 }, 1094 { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC115C, HWTYPE_AQ2, 1095 AQ_MEDIA_TYPE_TP, 1096 AQ_LINK_10M | AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5 1097 }, 1098 { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC116C, HWTYPE_AQ2, 1099 AQ_MEDIA_TYPE_TP, AQ_LINK_10M | AQ_LINK_100M | AQ_LINK_1G 1100 }, 1101 }; 1102 1103 int aq_match(struct device *, void *, void *); 1104 void aq_attach(struct device *, struct device *, void *); 1105 int aq_detach(struct device *, int); 1106 int aq_activate(struct device *, int); 1107 int aq_intr(void *); 1108 int aq_intr_link(void *); 1109 int aq_intr_queue(void *); 1110 int aq_init_rss(struct aq_softc *); 1111 int aq_hw_reset(struct aq_softc *); 1112 int aq_hw_init(struct aq_softc *, int, int); 1113 void aq_hw_qos_set(struct aq_softc *); 1114 void aq_l3_filter_set(struct aq_softc *); 1115 void aq_hw_init_tx_path(struct aq_softc *); 1116 void aq_hw_init_rx_path(struct aq_softc *); 1117 int aq_set_mac_addr(struct aq_softc *, int, uint8_t *); 1118 int aq_set_linkmode(struct aq_softc *, enum aq_link_speed, 1119 enum aq_link_fc, enum aq_link_eee); 1120 void aq_watchdog(struct ifnet *); 1121 void aq_enable_intr(struct aq_softc *, int, int); 1122 int aq_rxrinfo(struct aq_softc *, struct if_rxrinfo *); 1123 int aq_ioctl(struct ifnet *, u_long, caddr_t); 1124 int aq_up(struct aq_softc *); 1125 void aq_down(struct aq_softc *); 1126 void aq_iff(struct aq_softc *); 1127 void aq_start(struct ifqueue *); 1128 void aq_ifmedia_status(struct ifnet *, struct ifmediareq *); 1129 int aq_ifmedia_change(struct ifnet *); 1130 void aq_update_link_status(struct aq_softc *); 1131 1132 int aq1_fw_reboot(struct aq_softc *); 1133 int aq1_fw_read_version(struct aq_softc *); 1134 int aq1_fw_version_init(struct aq_softc *); 1135 int aq1_hw_init_ucp(struct aq_softc *); 1136 void aq1_global_software_reset(struct aq_softc *); 1137 int aq1_mac_soft_reset(struct aq_softc *, enum aq_fw_bootloader_mode *); 1138 int aq1_mac_soft_reset_rbl(struct aq_softc *, enum aq_fw_bootloader_mode *); 1139 int aq1_mac_soft_reset_flb(struct aq_softc *); 1140 int aq1_fw_downld_dwords(struct aq_softc *, uint32_t, uint32_t *, uint32_t); 1141 1142 int aq2_interface_buffer_read(struct aq_softc *, uint32_t, uint32_t *, 1143 uint32_t); 1144 int aq2_fw_reboot(struct aq_softc *); 1145 int aq2_filter_art_set(struct aq_softc *, uint32_t, uint32_t, uint32_t, 1146 uint32_t action); 1147 1148 void aq_refill(void *); 1149 int aq_rx_fill(struct aq_softc *, struct aq_rxring *); 1150 static inline unsigned int aq_rx_fill_slots(struct aq_softc *, 1151 struct aq_rxring *, uint); 1152 1153 int aq_dmamem_alloc(struct aq_softc *, struct aq_dmamem *, 1154 bus_size_t, u_int); 1155 void aq_dmamem_zero(struct aq_dmamem *); 1156 void aq_dmamem_free(struct aq_softc *, struct aq_dmamem *); 1157 1158 int aq1_get_mac_addr(struct aq_softc *); 1159 1160 int aq_fw1x_reset(struct aq_softc *); 1161 int aq_fw1x_get_mode(struct aq_softc *, enum aq_hw_fw_mpi_state *, 1162 enum aq_link_speed *, enum aq_link_fc *, enum aq_link_eee *); 1163 int aq_fw1x_set_mode(struct aq_softc *, enum aq_hw_fw_mpi_state, 1164 enum aq_link_speed, enum aq_link_fc, enum aq_link_eee); 1165 int aq_fw1x_get_stats(struct aq_softc *, struct aq_hw_stats_s *); 1166 1167 int aq_fw2x_reset(struct aq_softc *); 1168 int aq_fw2x_get_mode(struct aq_softc *, enum aq_hw_fw_mpi_state *, 1169 enum aq_link_speed *, enum aq_link_fc *, enum aq_link_eee *); 1170 int aq_fw2x_set_mode(struct aq_softc *, enum aq_hw_fw_mpi_state, 1171 enum aq_link_speed, enum aq_link_fc, enum aq_link_eee); 1172 int aq_fw2x_get_stats(struct aq_softc *, struct aq_hw_stats_s *); 1173 1174 int aq2_fw_reset(struct aq_softc *); 1175 int aq2_get_mac_addr(struct aq_softc *); 1176 int aq2_fw_get_mode(struct aq_softc *, enum aq_hw_fw_mpi_state *, 1177 enum aq_link_speed *, enum aq_link_fc *, enum aq_link_eee *); 1178 int aq2_fw_set_mode(struct aq_softc *, enum aq_hw_fw_mpi_state, 1179 enum aq_link_speed, enum aq_link_fc, enum aq_link_eee); 1180 int aq2_fw_get_stats(struct aq_softc *, struct aq_hw_stats_s *); 1181 1182 const struct aq_firmware_ops aq_fw1x_ops = { 1183 .reset = aq_fw1x_reset, 1184 .get_mac_addr = aq1_get_mac_addr, 1185 .set_mode = aq_fw1x_set_mode, 1186 .get_mode = aq_fw1x_get_mode, 1187 .get_stats = aq_fw1x_get_stats, 1188 }; 1189 1190 const struct aq_firmware_ops aq_fw2x_ops = { 1191 .reset = aq_fw2x_reset, 1192 .get_mac_addr = aq1_get_mac_addr, 1193 .set_mode = aq_fw2x_set_mode, 1194 .get_mode = aq_fw2x_get_mode, 1195 .get_stats = aq_fw2x_get_stats, 1196 }; 1197 1198 const struct aq_firmware_ops aq2_fw_ops = { 1199 .reset = aq2_fw_reset, 1200 .get_mac_addr = aq2_get_mac_addr, 1201 .set_mode = aq2_fw_set_mode, 1202 .get_mode = aq2_fw_get_mode, 1203 .get_stats = aq2_fw_get_stats 1204 }; 1205 1206 const struct cfattach aq_ca = { 1207 sizeof(struct aq_softc), aq_match, aq_attach, NULL, 1208 aq_activate 1209 }; 1210 1211 struct cfdriver aq_cd = { 1212 NULL, "aq", DV_IFNET 1213 }; 1214 1215 int 1216 aq_match(struct device *dev, void *match, void *aux) 1217 { 1218 return pci_matchbyid((struct pci_attach_args *)aux, aq_devices, 1219 sizeof(aq_devices) / sizeof(aq_devices[0])); 1220 } 1221 1222 const struct aq_product * 1223 aq_lookup(const struct pci_attach_args *pa) 1224 { 1225 unsigned int i; 1226 1227 for (i = 0; i < sizeof(aq_products) / sizeof(aq_products[0]); i++) { 1228 if (PCI_VENDOR(pa->pa_id) == aq_products[i].aq_vendor && 1229 PCI_PRODUCT(pa->pa_id) == aq_products[i].aq_product) { 1230 return &aq_products[i]; 1231 } 1232 } 1233 1234 return NULL; 1235 } 1236 1237 void 1238 aq_attach(struct device *parent, struct device *self, void *aux) 1239 { 1240 struct aq_softc *sc = (struct aq_softc *)self; 1241 struct pci_attach_args *pa = aux; 1242 const struct aq_product *aqp; 1243 pcireg_t bar, memtype; 1244 pci_chipset_tag_t pc; 1245 pci_intr_handle_t ih; 1246 int (*isr)(void *); 1247 const char *intrstr; 1248 pcitag_t tag; 1249 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1250 int txmin, txmax, rxmin, rxmax; 1251 int irqmode, irqnum; 1252 int i; 1253 1254 mtx_init(&sc->sc_mpi_mutex, IPL_NET); 1255 1256 sc->sc_dmat = pa->pa_dmat; 1257 sc->sc_pc = pc = pa->pa_pc; 1258 sc->sc_pcitag = tag = pa->pa_tag; 1259 1260 sc->sc_product = PCI_PRODUCT(pa->pa_id); 1261 sc->sc_revision = PCI_REVISION(pa->pa_class); 1262 1263 aqp = aq_lookup(pa); 1264 1265 bar = pci_conf_read(pc, tag, AQ_BAR0); 1266 if (PCI_MAPREG_TYPE(bar) != PCI_MAPREG_TYPE_MEM) { 1267 printf(": wrong BAR type\n"); 1268 return; 1269 } 1270 1271 memtype = pci_mapreg_type(pc, tag, AQ_BAR0); 1272 if (pci_mapreg_map(pa, AQ_BAR0, memtype, 0, &sc->sc_iot, &sc->sc_ioh, 1273 NULL, NULL, 0)) { 1274 printf(": failed to map BAR0\n"); 1275 return; 1276 } 1277 1278 sc->sc_nqueues = 1; 1279 sc->sc_linkstat_irq = AQ_LINKSTAT_IRQ; 1280 isr = aq_intr; 1281 irqnum = 0; 1282 1283 if (pci_intr_map_msix(pa, 0, &ih) == 0) { 1284 int nmsix = pci_intr_msix_count(pa); 1285 /* don't do rss on aq2 yet */ 1286 if (aqp->aq_hwtype == HWTYPE_AQ1 && nmsix > 1) { 1287 nmsix--; 1288 sc->sc_intrmap = intrmap_create(&sc->sc_dev, 1289 nmsix, AQ_MAXQ, INTRMAP_POWEROF2); 1290 sc->sc_nqueues = intrmap_count(sc->sc_intrmap); 1291 KASSERT(sc->sc_nqueues > 0); 1292 KASSERT(powerof2(sc->sc_nqueues)); 1293 1294 sc->sc_linkstat_irq = 0; 1295 isr = aq_intr_link; 1296 irqnum++; 1297 } 1298 irqmode = AQ_INTR_CTRL_IRQMODE_MSIX; 1299 } else if (pci_intr_map_msi(pa, &ih) == 0) { 1300 irqmode = AQ_INTR_CTRL_IRQMODE_MSI; 1301 } else if (pci_intr_map(pa, &ih) == 0) { 1302 irqmode = AQ_INTR_CTRL_IRQMODE_LEGACY; 1303 } else { 1304 printf(": failed to map interrupt\n"); 1305 return; 1306 } 1307 1308 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, 1309 IPL_NET | IPL_MPSAFE, isr, sc, self->dv_xname); 1310 intrstr = pci_intr_string(pa->pa_pc, ih); 1311 if (intrstr) 1312 printf(": %s", intrstr); 1313 1314 if (sc->sc_nqueues > 1) 1315 printf(", %d queues", sc->sc_nqueues); 1316 1317 switch (aqp->aq_hwtype) { 1318 case HWTYPE_AQ1: 1319 if (aq1_fw_reboot(sc)) 1320 return; 1321 break; 1322 case HWTYPE_AQ2: 1323 if (aq2_fw_reboot(sc)) 1324 return; 1325 break; 1326 default: 1327 return; 1328 } 1329 1330 if (aq_hw_reset(sc)) 1331 return; 1332 1333 if (sc->sc_fw_ops->get_mac_addr(sc)) 1334 return; 1335 printf(", address %s", ether_sprintf(sc->sc_enaddr.ether_addr_octet)); 1336 1337 if (aq_init_rss(sc)) 1338 return; 1339 1340 if (aq_hw_init(sc, irqmode, (sc->sc_nqueues > 1))) 1341 return; 1342 1343 sc->sc_media_type = aqp->aq_media_type; 1344 sc->sc_available_rates = aqp->aq_available_rates; 1345 1346 ifmedia_init(&sc->sc_media, IFM_IMASK, aq_ifmedia_change, 1347 aq_ifmedia_status); 1348 1349 bcopy(sc->sc_enaddr.ether_addr_octet, sc->sc_arpcom.ac_enaddr, 6); 1350 strlcpy(ifp->if_xname, self->dv_xname, IFNAMSIZ); 1351 ifp->if_softc = sc; 1352 ifp->if_flags = IFF_BROADCAST | IFF_MULTICAST | IFF_SIMPLEX; 1353 ifp->if_xflags = IFXF_MPSAFE; 1354 ifp->if_ioctl = aq_ioctl; 1355 ifp->if_qstart = aq_start; 1356 ifp->if_watchdog = aq_watchdog; 1357 ifp->if_hardmtu = 9000; 1358 ifp->if_capabilities = IFCAP_VLAN_MTU | IFCAP_CSUM_IPv4 | 1359 IFCAP_CSUM_UDPv4 | IFCAP_CSUM_UDPv6 | IFCAP_CSUM_TCPv4 | 1360 IFCAP_CSUM_TCPv6; 1361 #if NVLAN > 0 1362 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 1363 #endif 1364 ifq_set_maxlen(&ifp->if_snd, AQ_TXD_NUM); 1365 1366 ifmedia_init(&sc->sc_media, IFM_IMASK, aq_ifmedia_change, 1367 aq_ifmedia_status); 1368 if (sc->sc_available_rates & AQ_LINK_10M) { 1369 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_10_T, 0, NULL); 1370 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_10_T|IFM_FDX, 0, 1371 NULL); 1372 } 1373 1374 if (sc->sc_available_rates & AQ_LINK_100M) { 1375 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_100_TX, 0, NULL); 1376 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_100_TX|IFM_FDX, 0, 1377 NULL); 1378 } 1379 1380 if (sc->sc_available_rates & AQ_LINK_1G) { 1381 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_1000_T, 0, NULL); 1382 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_1000_T|IFM_FDX, 0, 1383 NULL); 1384 } 1385 1386 if (sc->sc_available_rates & AQ_LINK_2G5) { 1387 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_2500_T, 0, NULL); 1388 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_2500_T | IFM_FDX, 1389 0, NULL); 1390 } 1391 1392 if (sc->sc_available_rates & AQ_LINK_5G) { 1393 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_5000_T, 0, NULL); 1394 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_5000_T | IFM_FDX, 1395 0, NULL); 1396 } 1397 1398 if (sc->sc_available_rates & AQ_LINK_10G) { 1399 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_10G_T, 0, NULL); 1400 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_10G_T | IFM_FDX, 1401 0, NULL); 1402 } 1403 1404 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_AUTO, 0, NULL); 1405 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_AUTO | IFM_FDX, 0, NULL); 1406 ifmedia_set(&sc->sc_media, IFM_ETHER | IFM_AUTO); 1407 aq_set_linkmode(sc, AQ_LINK_AUTO, AQ_FC_NONE, AQ_EEE_DISABLE); 1408 1409 if_attach(ifp); 1410 ether_ifattach(ifp); 1411 1412 if_attach_iqueues(ifp, sc->sc_nqueues); 1413 if_attach_queues(ifp, sc->sc_nqueues); 1414 1415 /* 1416 * set interrupt moderation for up to 20k interrupts per second, 1417 * more rx than tx. these values are in units of 2us. 1418 */ 1419 txmin = 20; 1420 txmax = 200; 1421 rxmin = 6; 1422 rxmax = 60; 1423 1424 for (i = 0; i < sc->sc_nqueues; i++) { 1425 struct aq_queues *aq = &sc->sc_queues[i]; 1426 struct aq_rxring *rx = &aq->q_rx; 1427 struct aq_txring *tx = &aq->q_tx; 1428 pci_intr_handle_t ih; 1429 1430 aq->q_sc = sc; 1431 aq->q_index = i; 1432 rx->rx_q = i; 1433 rx->rx_ifiq = ifp->if_iqs[i]; 1434 rx->rx_m_head = NULL; 1435 rx->rx_m_tail = &rx->rx_m_head; 1436 rx->rx_m_error = 0; 1437 ifp->if_iqs[i]->ifiq_softc = aq; 1438 timeout_set(&rx->rx_refill, aq_refill, rx); 1439 1440 tx->tx_q = i; 1441 tx->tx_ifq = ifp->if_ifqs[i]; 1442 ifp->if_ifqs[i]->ifq_softc = aq; 1443 1444 snprintf(aq->q_name, sizeof(aq->q_name), "%s:%u", 1445 DEVNAME(sc), i); 1446 1447 if (sc->sc_nqueues > 1) { 1448 if (pci_intr_map_msix(pa, irqnum, &ih)) { 1449 printf(": unable to map msi-x vector %d\n", 1450 irqnum); 1451 return; 1452 } 1453 1454 aq->q_ihc = pci_intr_establish_cpu(sc->sc_pc, ih, 1455 IPL_NET | IPL_MPSAFE, intrmap_cpu(sc->sc_intrmap, i), 1456 aq_intr_queue, aq, aq->q_name); 1457 if (aq->q_ihc == NULL) { 1458 printf(": unable to establish interrupt %d\n", 1459 irqnum); 1460 return; 1461 } 1462 rx->rx_irq = irqnum; 1463 tx->tx_irq = irqnum; 1464 irqnum++; 1465 } else { 1466 rx->rx_irq = irqnum++; 1467 tx->tx_irq = irqnum++; 1468 } 1469 1470 if (HWTYPE_AQ2_P(sc)) { 1471 AQ_WRITE_REG_BIT(sc, AQ2_TX_INTR_MODERATION_CTL_REG(i), 1472 AQ2_TX_INTR_MODERATION_CTL_MIN, txmin); 1473 AQ_WRITE_REG_BIT(sc, AQ2_TX_INTR_MODERATION_CTL_REG(i), 1474 AQ2_TX_INTR_MODERATION_CTL_MAX, txmax); 1475 AQ_WRITE_REG_BIT(sc, AQ2_TX_INTR_MODERATION_CTL_REG(i), 1476 AQ2_TX_INTR_MODERATION_CTL_EN, 1); 1477 } else { 1478 AQ_WRITE_REG_BIT(sc, TX_INTR_MODERATION_CTL_REG(i), 1479 TX_INTR_MODERATION_CTL_MIN, txmin); 1480 AQ_WRITE_REG_BIT(sc, TX_INTR_MODERATION_CTL_REG(i), 1481 TX_INTR_MODERATION_CTL_MAX, txmax); 1482 AQ_WRITE_REG_BIT(sc, TX_INTR_MODERATION_CTL_REG(i), 1483 TX_INTR_MODERATION_CTL_EN, 1); 1484 } 1485 AQ_WRITE_REG_BIT(sc, RX_INTR_MODERATION_CTL_REG(i), 1486 RX_INTR_MODERATION_CTL_MIN, rxmin); 1487 AQ_WRITE_REG_BIT(sc, RX_INTR_MODERATION_CTL_REG(i), 1488 RX_INTR_MODERATION_CTL_MAX, rxmax); 1489 AQ_WRITE_REG_BIT(sc, RX_INTR_MODERATION_CTL_REG(i), 1490 RX_INTR_MODERATION_CTL_EN, 1); 1491 } 1492 1493 AQ_WRITE_REG_BIT(sc, TX_DMA_INT_DESC_WRWB_EN_REG, 1494 TX_DMA_INT_DESC_WRWB_EN, 0); 1495 AQ_WRITE_REG_BIT(sc, TX_DMA_INT_DESC_WRWB_EN_REG, 1496 TX_DMA_INT_DESC_MODERATE_EN, 1); 1497 AQ_WRITE_REG_BIT(sc, RX_DMA_INT_DESC_WRWB_EN_REG, 1498 RX_DMA_INT_DESC_WRWB_EN, 0); 1499 AQ_WRITE_REG_BIT(sc, RX_DMA_INT_DESC_WRWB_EN_REG, 1500 RX_DMA_INT_DESC_MODERATE_EN, 1); 1501 1502 aq_enable_intr(sc, 1, 0); 1503 printf("\n"); 1504 } 1505 1506 int 1507 aq1_fw_reboot(struct aq_softc *sc) 1508 { 1509 uint32_t ver, v, boot_exit_code; 1510 int i, error; 1511 enum aq_fw_bootloader_mode mode; 1512 1513 mode = FW_BOOT_MODE_UNKNOWN; 1514 1515 ver = AQ_READ_REG(sc, AQ_FW_VERSION_REG); 1516 1517 for (i = 1000; i > 0; i--) { 1518 v = AQ_READ_REG(sc, FW_MPI_DAISY_CHAIN_STATUS_REG); 1519 boot_exit_code = AQ_READ_REG(sc, FW_BOOT_EXIT_CODE_REG); 1520 if (v != 0x06000000 || boot_exit_code != 0) 1521 break; 1522 } 1523 1524 if (i <= 0) { 1525 printf(": F/W reset failed. Neither RBL nor FLB started"); 1526 return ETIMEDOUT; 1527 } 1528 1529 sc->sc_rbl_enabled = (boot_exit_code != 0); 1530 1531 /* 1532 * Having FW version 0 is an indicator that cold start 1533 * is in progress. This means two things: 1534 * 1) Driver have to wait for FW/HW to finish boot (500ms giveup) 1535 * 2) Driver may skip reset sequence and save time. 1536 */ 1537 if (sc->sc_fast_start_enabled && (ver != 0)) { 1538 if (aq1_fw_read_version(sc) == 0) 1539 goto faststart; 1540 } 1541 1542 error = aq1_mac_soft_reset(sc, &mode); 1543 if (error != 0) { 1544 printf("%s: MAC reset failed: %d\n", DEVNAME(sc), error); 1545 return error; 1546 } 1547 1548 switch (mode) { 1549 case FW_BOOT_MODE_FLB: 1550 DPRINTF(("%s: FLB> F/W successfully loaded from flash.", 1551 DEVNAME(sc))); 1552 sc->sc_flash_present = 1; 1553 break; 1554 case FW_BOOT_MODE_RBL_FLASH: 1555 DPRINTF(("%s: RBL> F/W loaded from flash. Host Bootload " 1556 "disabled.", DEVNAME(sc))); 1557 sc->sc_flash_present = 1; 1558 break; 1559 case FW_BOOT_MODE_UNKNOWN: 1560 printf("%s: F/W bootload error: unknown bootloader type", 1561 DEVNAME(sc)); 1562 return ENOTSUP; 1563 case FW_BOOT_MODE_RBL_HOST_BOOTLOAD: 1564 printf("%s: RBL> F/W Host Bootload not implemented", DEVNAME(sc)); 1565 return ENOTSUP; 1566 } 1567 1568 faststart: 1569 error = aq1_fw_read_version(sc); 1570 if (error != 0) 1571 return error; 1572 1573 error = aq1_fw_version_init(sc); 1574 if (error != 0) 1575 return error; 1576 1577 return aq1_hw_init_ucp(sc); 1578 } 1579 1580 int 1581 aq1_mac_soft_reset_rbl(struct aq_softc *sc, enum aq_fw_bootloader_mode *mode) 1582 { 1583 int timo; 1584 1585 DPRINTF(("%s: RBL> MAC reset STARTED!\n", DEVNAME(sc))); 1586 1587 AQ_WRITE_REG(sc, AQ_FW_GLB_CTL2_REG, 0x40e1); 1588 AQ_WRITE_REG(sc, AQ_FW_GLB_CPU_SEM_REG(0), 1); 1589 AQ_WRITE_REG(sc, AQ_MBOXIF_POWER_GATING_CONTROL_REG, 0); 1590 1591 /* MAC FW will reload PHY FW if 1E.1000.3 was cleaned - #undone */ 1592 AQ_WRITE_REG(sc, FW_BOOT_EXIT_CODE_REG, RBL_STATUS_DEAD); 1593 1594 aq1_global_software_reset(sc); 1595 1596 AQ_WRITE_REG(sc, AQ_FW_GLB_CTL2_REG, 0x40e0); 1597 1598 /* Wait for RBL to finish boot process. */ 1599 #define RBL_TIMEOUT_MS 10000 1600 uint16_t rbl_status; 1601 for (timo = RBL_TIMEOUT_MS; timo > 0; timo--) { 1602 rbl_status = AQ_READ_REG(sc, FW_BOOT_EXIT_CODE_REG) & 0xffff; 1603 if (rbl_status != 0 && rbl_status != RBL_STATUS_DEAD) 1604 break; 1605 delay(1000); 1606 } 1607 1608 if (timo <= 0) { 1609 printf("%s: RBL> RBL restart failed: timeout\n", DEVNAME(sc)); 1610 return EBUSY; 1611 } 1612 1613 switch (rbl_status) { 1614 case RBL_STATUS_SUCCESS: 1615 if (mode != NULL) 1616 *mode = FW_BOOT_MODE_RBL_FLASH; 1617 DPRINTF(("%s: RBL> reset complete! [Flash]\n", DEVNAME(sc))); 1618 break; 1619 case RBL_STATUS_HOST_BOOT: 1620 if (mode != NULL) 1621 *mode = FW_BOOT_MODE_RBL_HOST_BOOTLOAD; 1622 DPRINTF(("%s: RBL> reset complete! [Host Bootload]\n", 1623 DEVNAME(sc))); 1624 break; 1625 case RBL_STATUS_FAILURE: 1626 default: 1627 printf("%s: unknown RBL status 0x%x\n", DEVNAME(sc), 1628 rbl_status); 1629 return EBUSY; 1630 } 1631 1632 return 0; 1633 } 1634 1635 int 1636 aq1_mac_soft_reset_flb(struct aq_softc *sc) 1637 { 1638 uint32_t v; 1639 int timo; 1640 1641 AQ_WRITE_REG(sc, AQ_FW_GLB_CTL2_REG, 0x40e1); 1642 /* 1643 * Let Felicity hardware to complete SMBUS transaction before 1644 * Global software reset. 1645 */ 1646 delay(50000); 1647 1648 /* 1649 * If SPI burst transaction was interrupted(before running the script), 1650 * global software reset may not clear SPI interface. 1651 * Clean it up manually before global reset. 1652 */ 1653 AQ_WRITE_REG(sc, AQ_GLB_NVR_PROVISIONING2_REG, 0x00a0); 1654 AQ_WRITE_REG(sc, AQ_GLB_NVR_INTERFACE1_REG, 0x009f); 1655 AQ_WRITE_REG(sc, AQ_GLB_NVR_INTERFACE1_REG, 0x809f); 1656 delay(50000); 1657 1658 v = AQ_READ_REG(sc, AQ_FW_SOFTRESET_REG); 1659 v &= ~AQ_FW_SOFTRESET_DIS; 1660 v |= AQ_FW_SOFTRESET_RESET; 1661 AQ_WRITE_REG(sc, AQ_FW_SOFTRESET_REG, v); 1662 1663 /* Kickstart. */ 1664 AQ_WRITE_REG(sc, AQ_FW_GLB_CTL2_REG, 0x80e0); 1665 AQ_WRITE_REG(sc, AQ_MBOXIF_POWER_GATING_CONTROL_REG, 0); 1666 if (!sc->sc_fast_start_enabled) 1667 AQ_WRITE_REG(sc, AQ_GLB_GENERAL_PROVISIONING9_REG, 1); 1668 1669 /* 1670 * For the case SPI burst transaction was interrupted (by MCP reset 1671 * above), wait until it is completed by hardware. 1672 */ 1673 delay(50000); 1674 1675 /* MAC Kickstart */ 1676 if (!sc->sc_fast_start_enabled) { 1677 AQ_WRITE_REG(sc, AQ_FW_GLB_CTL2_REG, 0x180e0); 1678 1679 uint32_t flb_status; 1680 for (timo = 0; timo < 1000; timo++) { 1681 flb_status = AQ_READ_REG(sc, 1682 FW_MPI_DAISY_CHAIN_STATUS_REG) & 0x10; 1683 if (flb_status != 0) 1684 break; 1685 delay(1000); 1686 } 1687 if (flb_status == 0) { 1688 printf("%s: FLB> MAC kickstart failed: timed out\n", 1689 DEVNAME(sc)); 1690 return ETIMEDOUT; 1691 } 1692 DPRINTF(("%s: FLB> MAC kickstart done, %d ms\n", DEVNAME(sc), 1693 timo)); 1694 /* FW reset */ 1695 AQ_WRITE_REG(sc, AQ_FW_GLB_CTL2_REG, 0x80e0); 1696 /* 1697 * Let Felicity hardware complete SMBUS transaction before 1698 * Global software reset. 1699 */ 1700 delay(50000); 1701 sc->sc_fast_start_enabled = true; 1702 } 1703 AQ_WRITE_REG(sc, AQ_FW_GLB_CPU_SEM_REG(0), 1); 1704 1705 /* PHY Kickstart: #undone */ 1706 aq1_global_software_reset(sc); 1707 1708 for (timo = 0; timo < 1000; timo++) { 1709 if (AQ_READ_REG(sc, AQ_FW_VERSION_REG) != 0) 1710 break; 1711 delay(10000); 1712 } 1713 if (timo >= 1000) { 1714 printf("%s: FLB> Global Soft Reset failed\n", DEVNAME(sc)); 1715 return ETIMEDOUT; 1716 } 1717 DPRINTF(("%s: FLB> F/W restart: %d ms\n", DEVNAME(sc), timo * 10)); 1718 1719 return 0; 1720 1721 } 1722 1723 int 1724 aq1_mac_soft_reset(struct aq_softc *sc, enum aq_fw_bootloader_mode *mode) 1725 { 1726 if (sc->sc_rbl_enabled) 1727 return aq1_mac_soft_reset_rbl(sc, mode); 1728 1729 if (mode != NULL) 1730 *mode = FW_BOOT_MODE_FLB; 1731 return aq1_mac_soft_reset_flb(sc); 1732 } 1733 1734 void 1735 aq1_global_software_reset(struct aq_softc *sc) 1736 { 1737 uint32_t v; 1738 1739 AQ_WRITE_REG_BIT(sc, RX_SYSCONTROL_REG, RX_SYSCONTROL_RESET_DIS, 0); 1740 AQ_WRITE_REG_BIT(sc, TX_SYSCONTROL_REG, TX_SYSCONTROL_RESET_DIS, 0); 1741 AQ_WRITE_REG_BIT(sc, FW_MPI_RESETCTRL_REG, 1742 FW_MPI_RESETCTRL_RESET_DIS, 0); 1743 1744 v = AQ_READ_REG(sc, AQ_FW_SOFTRESET_REG); 1745 v &= ~AQ_FW_SOFTRESET_DIS; 1746 v |= AQ_FW_SOFTRESET_RESET; 1747 AQ_WRITE_REG(sc, AQ_FW_SOFTRESET_REG, v); 1748 } 1749 1750 int 1751 aq1_fw_read_version(struct aq_softc *sc) 1752 { 1753 int i, error = EBUSY; 1754 #define MAC_FW_START_TIMEOUT_MS 10000 1755 for (i = 0; i < MAC_FW_START_TIMEOUT_MS; i++) { 1756 sc->sc_fw_version = AQ_READ_REG(sc, AQ_FW_VERSION_REG); 1757 if (sc->sc_fw_version != 0) { 1758 error = 0; 1759 break; 1760 } 1761 delay(1000); 1762 } 1763 return error; 1764 } 1765 1766 int 1767 aq1_fw_version_init(struct aq_softc *sc) 1768 { 1769 int error = 0; 1770 char fw_vers[sizeof("F/W version xxxxx.xxxxx.xxxxx")]; 1771 1772 if (FW_VERSION_MAJOR(sc) == 1) { 1773 sc->sc_fw_ops = &aq_fw1x_ops; 1774 } else if ((FW_VERSION_MAJOR(sc) == 2) || (FW_VERSION_MAJOR(sc) == 3)) { 1775 sc->sc_fw_ops = &aq_fw2x_ops; 1776 } else { 1777 printf(": Unsupported F/W version %d.%d.%d\n", 1778 FW_VERSION_MAJOR(sc), FW_VERSION_MINOR(sc), 1779 FW_VERSION_BUILD(sc)); 1780 return ENOTSUP; 1781 } 1782 snprintf(fw_vers, sizeof(fw_vers), "F/W version %d.%d.%d", 1783 FW_VERSION_MAJOR(sc), FW_VERSION_MINOR(sc), FW_VERSION_BUILD(sc)); 1784 1785 /* detect revision */ 1786 uint32_t hwrev = AQ_READ_REG(sc, AQ_HW_REVISION_REG); 1787 switch (hwrev & 0x0000000f) { 1788 case 0x01: 1789 printf(", Atlantic A0, %s", fw_vers); 1790 sc->sc_features |= FEATURES_AQ1_REV_A0 | 1791 FEATURES_MPI_AQ | FEATURES_MIPS; 1792 break; 1793 case 0x02: 1794 printf(", Atlantic B0, %s", fw_vers); 1795 sc->sc_features |= FEATURES_AQ1_REV_B0 | 1796 FEATURES_MPI_AQ | FEATURES_MIPS | 1797 FEATURES_TPO2 | FEATURES_RPF2; 1798 break; 1799 case 0x0A: 1800 printf(", Atlantic B1, %s", fw_vers); 1801 sc->sc_features |= FEATURES_AQ1_REV_B1 | 1802 FEATURES_MPI_AQ | FEATURES_MIPS | 1803 FEATURES_TPO2 | FEATURES_RPF2; 1804 break; 1805 default: 1806 printf(": Unknown revision (0x%08x)\n", hwrev); 1807 error = ENOTSUP; 1808 break; 1809 } 1810 return error; 1811 } 1812 1813 int 1814 aq1_hw_init_ucp(struct aq_softc *sc) 1815 { 1816 int timo; 1817 1818 if (FW_VERSION_MAJOR(sc) == 1) { 1819 if (AQ_READ_REG(sc, FW1X_MPI_INIT2_REG) == 0) { 1820 uint32_t data; 1821 arc4random_buf(&data, sizeof(data)); 1822 data &= 0xfefefefe; 1823 data |= 0x02020202; 1824 AQ_WRITE_REG(sc, FW1X_MPI_INIT2_REG, data); 1825 } 1826 AQ_WRITE_REG(sc, FW1X_MPI_INIT1_REG, 0); 1827 } 1828 1829 for (timo = 100; timo > 0; timo--) { 1830 sc->sc_mbox_addr = AQ_READ_REG(sc, FW_MPI_MBOX_ADDR_REG); 1831 if (sc->sc_mbox_addr != 0) 1832 break; 1833 delay(1000); 1834 } 1835 1836 #define AQ_FW_MIN_VERSION 0x01050006 1837 #define AQ_FW_MIN_VERSION_STR "1.5.6" 1838 if (sc->sc_fw_version < AQ_FW_MIN_VERSION) { 1839 printf("%s: atlantic: wrong FW version: " AQ_FW_MIN_VERSION_STR 1840 " or later required, this is %d.%d.%d\n", 1841 DEVNAME(sc), 1842 FW_VERSION_MAJOR(sc), 1843 FW_VERSION_MINOR(sc), 1844 FW_VERSION_BUILD(sc)); 1845 return ENOTSUP; 1846 } 1847 1848 if (sc->sc_mbox_addr == 0) 1849 printf("%s: NULL MBOX!!\n", DEVNAME(sc)); 1850 1851 return 0; 1852 } 1853 1854 int 1855 aq2_interface_buffer_read(struct aq_softc *sc, uint32_t reg0, uint32_t *data0, 1856 uint32_t size0) 1857 { 1858 uint32_t tid0, tid1, reg, *data, size; 1859 int timo; 1860 1861 for (timo = 10000; timo > 0; timo--) { 1862 tid0 = AQ_READ_REG(sc, AQ2_FW_INTERFACE_OUT_TRANSACTION_ID_REG); 1863 if (((tid0 & AQ2_FW_INTERFACE_OUT_TRANSACTION_ID_A) 1864 >> AQ2_FW_INTERFACE_OUT_TRANSACTION_ID_A_S) != 1865 ((tid0 & AQ2_FW_INTERFACE_OUT_TRANSACTION_ID_B) 1866 >> AQ2_FW_INTERFACE_OUT_TRANSACTION_ID_B_S)) { 1867 delay(10); 1868 continue; 1869 } 1870 1871 for (reg = reg0, data = data0, size = size0; 1872 size >= 4; reg += 4, data++, size -= 4) { 1873 *data = AQ_READ_REG(sc, reg); 1874 } 1875 1876 tid1 = AQ_READ_REG(sc, AQ2_FW_INTERFACE_OUT_TRANSACTION_ID_REG); 1877 if (tid0 == tid1) 1878 break; 1879 } 1880 if (timo == 0) { 1881 printf("%s: interface buffer read timeout\n", DEVNAME(sc)); 1882 return ETIMEDOUT; 1883 } 1884 return 0; 1885 } 1886 1887 int 1888 aq2_fw_reboot(struct aq_softc *sc) 1889 { 1890 uint32_t v; 1891 int timo, err; 1892 char buf[32]; 1893 uint32_t filter_caps[3]; 1894 1895 sc->sc_fw_ops = &aq2_fw_ops; 1896 sc->sc_features = FEATURES_AQ2; 1897 1898 AQ_WRITE_REG(sc, AQ2_MCP_HOST_REQ_INT_CLR_REG, 1); 1899 AQ_WRITE_REG(sc, AQ2_MIF_BOOT_REG, 1); /* reboot request */ 1900 for (timo = 200000; timo > 0; timo--) { 1901 v = AQ_READ_REG(sc, AQ2_MIF_BOOT_REG); 1902 if ((v & AQ2_MIF_BOOT_BOOT_STARTED) && v != 0xffffffff) 1903 break; 1904 delay(10); 1905 } 1906 if (timo <= 0) { 1907 printf(": FW reboot timeout\n"); 1908 return ETIMEDOUT; 1909 } 1910 1911 for (timo = 2000000; timo > 0; timo--) { 1912 v = AQ_READ_REG(sc, AQ2_MIF_BOOT_REG); 1913 if ((v & AQ2_MIF_BOOT_FW_INIT_FAILED) || 1914 (v & AQ2_MIF_BOOT_FW_INIT_COMP_SUCCESS)) 1915 break; 1916 v = AQ_READ_REG(sc, AQ2_MCP_HOST_REQ_INT_REG); 1917 if (v & AQ2_MCP_HOST_REQ_INT_READY) 1918 break; 1919 delay(10); 1920 } 1921 if (timo <= 0) { 1922 printf(": FW restart timeout\n"); 1923 return ETIMEDOUT; 1924 } 1925 1926 v = AQ_READ_REG(sc, AQ2_MIF_BOOT_REG); 1927 if (v & AQ2_MIF_BOOT_FW_INIT_FAILED) { 1928 printf(": FW restart failed\n"); 1929 return ETIMEDOUT; 1930 } 1931 1932 v = AQ_READ_REG(sc, AQ2_MCP_HOST_REQ_INT_REG); 1933 if (v & AQ2_MCP_HOST_REQ_INT_READY) { 1934 printf(": firmware required\n"); 1935 return ENXIO; 1936 } 1937 1938 /* 1939 * Get aq2 firmware version. 1940 * Note that the bit layout and its meaning are different from aq1. 1941 */ 1942 err = aq2_interface_buffer_read(sc, AQ2_FW_INTERFACE_OUT_VERSION_BUNDLE_REG, 1943 (uint32_t *)&v, sizeof(v)); 1944 if (err != 0) 1945 return err; 1946 1947 sc->sc_fw_version = 1948 (((v & AQ2_FW_INTERFACE_OUT_VERSION_MAJOR) >> 1949 AQ2_FW_INTERFACE_OUT_VERSION_MAJOR_S) << 24) | 1950 (((v & AQ2_FW_INTERFACE_OUT_VERSION_MINOR) >> 1951 AQ2_FW_INTERFACE_OUT_VERSION_MINOR_S) << 16) | 1952 (((v & AQ2_FW_INTERFACE_OUT_VERSION_BUILD) >> 1953 AQ2_FW_INTERFACE_OUT_VERSION_BUILD_S)); 1954 1955 err = aq2_interface_buffer_read(sc, AQ2_FW_INTERFACE_OUT_VERSION_IFACE_REG, 1956 (uint32_t *)&v, sizeof(v)); 1957 if (err != 0) 1958 return err; 1959 1960 switch (v & AQ2_FW_INTERFACE_OUT_VERSION_IFACE_VER) { 1961 case AQ2_FW_INTERFACE_OUT_VERSION_IFACE_VER_A0: 1962 sc->sc_features |= FEATURES_AQ2_IFACE_A0; 1963 strncpy(buf, "A0", sizeof(buf)); 1964 break; 1965 case AQ2_FW_INTERFACE_OUT_VERSION_IFACE_VER_B0: 1966 sc->sc_features |= FEATURES_AQ2_IFACE_B0; 1967 strncpy(buf, "B0", sizeof(buf)); 1968 break; 1969 default: 1970 snprintf(buf, sizeof(buf), "(unknown 0x%08x)", v); 1971 break; 1972 } 1973 printf(", Atlantic2 %s, F/W version %d.%d.%d", buf, 1974 FW_VERSION_MAJOR(sc), FW_VERSION_MINOR(sc), FW_VERSION_BUILD(sc)); 1975 1976 aq2_interface_buffer_read(sc, AQ2_FW_INTERFACE_OUT_FILTER_CAPS_REG, 1977 filter_caps, sizeof(filter_caps)); 1978 sc->sc_art_filter_base_index = ((filter_caps[2] & 1979 AQ2_FW_INTERFACE_OUT_FILTER_CAPS3_RESOLVER_BASE_INDEX) >> 1980 AQ2_FW_INTERFACE_OUT_FILTER_CAPS3_RESOLVER_BASE_INDEX_SHIFT) * 8; 1981 1982 /* debug info */ 1983 v = AQ_READ_REG(sc, AQ_HW_REVISION_REG); 1984 DPRINTF(("%s: HW Rev: 0x%08x\n", DEVNAME(sc), v)); 1985 1986 return 0; 1987 } 1988 1989 int 1990 aq_hw_reset(struct aq_softc *sc) 1991 { 1992 int error; 1993 1994 /* disable irq */ 1995 AQ_WRITE_REG_BIT(sc, AQ_INTR_CTRL_REG, AQ_INTR_CTRL_RESET_DIS, 0); 1996 1997 /* apply */ 1998 AQ_WRITE_REG_BIT(sc, AQ_INTR_CTRL_REG, AQ_INTR_CTRL_RESET_IRQ, 1); 1999 2000 /* wait ack 10 times by 1ms */ 2001 WAIT_FOR( 2002 (AQ_READ_REG(sc, AQ_INTR_CTRL_REG) & AQ_INTR_CTRL_RESET_IRQ) == 0, 2003 1000, 10, &error); 2004 if (error != 0) { 2005 printf(": IRQ reset failed: %d\n", error); 2006 return error; 2007 } 2008 2009 return sc->sc_fw_ops->reset(sc); 2010 } 2011 2012 int 2013 aq1_get_mac_addr(struct aq_softc *sc) 2014 { 2015 uint32_t mac_addr[2]; 2016 uint32_t efuse_shadow_addr; 2017 int err; 2018 2019 efuse_shadow_addr = 0; 2020 if (FW_VERSION_MAJOR(sc) >= 2) 2021 efuse_shadow_addr = AQ_READ_REG(sc, FW2X_MPI_EFUSEADDR_REG); 2022 else 2023 efuse_shadow_addr = AQ_READ_REG(sc, FW1X_MPI_EFUSEADDR_REG); 2024 2025 if (efuse_shadow_addr == 0) { 2026 printf(": cannot get efuse addr\n"); 2027 return ENXIO; 2028 } 2029 2030 DPRINTF(("%s: efuse_shadow_addr = %x\n", DEVNAME(sc), efuse_shadow_addr)); 2031 2032 memset(mac_addr, 0, sizeof(mac_addr)); 2033 err = aq1_fw_downld_dwords(sc, efuse_shadow_addr + (40 * 4), 2034 mac_addr, 2); 2035 if (err < 0) 2036 return err; 2037 2038 if (mac_addr[0] == 0 && mac_addr[1] == 0) { 2039 printf(": mac address not found\n"); 2040 return ENXIO; 2041 } 2042 2043 DPRINTF(("%s: mac0 %x mac1 %x\n", DEVNAME(sc), mac_addr[0], 2044 mac_addr[1])); 2045 2046 mac_addr[0] = htobe32(mac_addr[0]); 2047 mac_addr[1] = htobe32(mac_addr[1]); 2048 2049 DPRINTF(("%s: mac0 %x mac1 %x\n", DEVNAME(sc), mac_addr[0], 2050 mac_addr[1])); 2051 2052 memcpy(sc->sc_enaddr.ether_addr_octet, 2053 (uint8_t *)mac_addr, ETHER_ADDR_LEN); 2054 2055 return 0; 2056 } 2057 2058 int 2059 aq_activate(struct device *self, int act) 2060 { 2061 return 0; 2062 } 2063 2064 int 2065 aq1_fw_downld_dwords(struct aq_softc *sc, uint32_t addr, uint32_t *p, 2066 uint32_t cnt) 2067 { 2068 uint32_t v; 2069 int error = 0; 2070 2071 WAIT_FOR(AQ_READ_REG(sc, AQ_FW_SEM_RAM_REG) == 1, 1, 10000, &error); 2072 if (error != 0) { 2073 AQ_WRITE_REG(sc, AQ_FW_SEM_RAM_REG, 1); 2074 v = AQ_READ_REG(sc, AQ_FW_SEM_RAM_REG); 2075 if (v == 0) { 2076 printf("%s: %s:%d: timeout\n", 2077 DEVNAME(sc), __func__, __LINE__); 2078 return ETIMEDOUT; 2079 } 2080 } 2081 2082 AQ_WRITE_REG(sc, AQ_FW_MBOX_ADDR_REG, addr); 2083 2084 error = 0; 2085 for (; cnt > 0 && error == 0; cnt--) { 2086 /* execute mailbox interface */ 2087 AQ_WRITE_REG_BIT(sc, AQ_FW_MBOX_CMD_REG, 2088 AQ_FW_MBOX_CMD_EXECUTE, 1); 2089 if (sc->sc_features & FEATURES_AQ1_REV_B1) { 2090 WAIT_FOR(AQ_READ_REG(sc, AQ_FW_MBOX_ADDR_REG) != addr, 2091 1, 1000, &error); 2092 } else { 2093 WAIT_FOR((AQ_READ_REG(sc, AQ_FW_MBOX_CMD_REG) & 2094 AQ_FW_MBOX_CMD_BUSY) == 0, 2095 1, 1000, &error); 2096 } 2097 *p++ = AQ_READ_REG(sc, AQ_FW_MBOX_VAL_REG); 2098 addr += sizeof(uint32_t); 2099 } 2100 AQ_WRITE_REG(sc, AQ_FW_SEM_RAM_REG, 1); 2101 2102 if (error != 0) 2103 printf("%s: %s:%d: timeout\n", 2104 DEVNAME(sc), __func__, __LINE__); 2105 2106 return error; 2107 } 2108 2109 int 2110 aq_fw2x_reset(struct aq_softc *sc) 2111 { 2112 struct aq_fw2x_capabilities caps = { 0 }; 2113 int error; 2114 2115 error = aq1_fw_downld_dwords(sc, 2116 sc->sc_mbox_addr + offsetof(struct aq_fw2x_mailbox, caps), 2117 (uint32_t *)&caps, sizeof caps / sizeof(uint32_t)); 2118 if (error != 0) { 2119 printf("%s: fw2x> can't get F/W capabilities mask, error %d\n", 2120 DEVNAME(sc), error); 2121 return error; 2122 } 2123 sc->sc_fw_caps = caps.caps_lo | ((uint64_t)caps.caps_hi << 32); 2124 2125 DPRINTF(("%s: fw2x> F/W capabilities=0x%llx\n", DEVNAME(sc), 2126 sc->sc_fw_caps)); 2127 2128 return 0; 2129 } 2130 2131 int 2132 aq_fw1x_reset(struct aq_softc *sc) 2133 { 2134 printf("%s: unimplemented %s\n", DEVNAME(sc), __func__); 2135 return 0; 2136 } 2137 2138 int 2139 aq_fw1x_set_mode(struct aq_softc *sc, enum aq_hw_fw_mpi_state w, 2140 enum aq_link_speed x, enum aq_link_fc y, enum aq_link_eee z) 2141 { 2142 return 0; 2143 } 2144 2145 int 2146 aq_fw1x_get_mode(struct aq_softc *sc, enum aq_hw_fw_mpi_state *w, 2147 enum aq_link_speed *x, enum aq_link_fc *y, enum aq_link_eee *z) 2148 { 2149 return 0; 2150 } 2151 2152 int 2153 aq_fw1x_get_stats(struct aq_softc *sc, struct aq_hw_stats_s *w) 2154 { 2155 return 0; 2156 } 2157 2158 2159 int 2160 aq_fw2x_get_mode(struct aq_softc *sc, enum aq_hw_fw_mpi_state *modep, 2161 enum aq_link_speed *speedp, enum aq_link_fc *fcp, enum aq_link_eee *eeep) 2162 { 2163 uint64_t mpi_state, mpi_ctrl; 2164 enum aq_link_speed speed; 2165 enum aq_link_fc fc; 2166 2167 AQ_MPI_LOCK(sc); 2168 2169 mpi_state = AQ_READ64_REG(sc, FW2X_MPI_STATE_REG); 2170 if (modep != NULL) { 2171 mpi_ctrl = AQ_READ64_REG(sc, FW2X_MPI_CONTROL_REG); 2172 if (mpi_ctrl & FW2X_CTRL_RATE_MASK) 2173 *modep = MPI_INIT; 2174 else 2175 *modep = MPI_DEINIT; 2176 } 2177 2178 AQ_MPI_UNLOCK(sc); 2179 2180 if (mpi_state & FW2X_CTRL_RATE_10G) 2181 speed = AQ_LINK_10G; 2182 else if (mpi_state & FW2X_CTRL_RATE_5G) 2183 speed = AQ_LINK_5G; 2184 else if (mpi_state & FW2X_CTRL_RATE_2G5) 2185 speed = AQ_LINK_2G5; 2186 else if (mpi_state & FW2X_CTRL_RATE_1G) 2187 speed = AQ_LINK_1G; 2188 else if (mpi_state & FW2X_CTRL_RATE_100M) 2189 speed = AQ_LINK_100M; 2190 else 2191 speed = AQ_LINK_NONE; 2192 if (speedp != NULL) 2193 *speedp = speed; 2194 2195 fc = AQ_FC_NONE; 2196 if (mpi_state & FW2X_CTRL_PAUSE) 2197 fc |= AQ_FC_RX; 2198 if (mpi_state & FW2X_CTRL_ASYMMETRIC_PAUSE) 2199 fc |= AQ_FC_TX; 2200 if (fcp != NULL) 2201 *fcp = fc; 2202 2203 if (eeep != NULL) 2204 *eeep = AQ_EEE_DISABLE; 2205 2206 return 0; 2207 } 2208 2209 int 2210 aq_fw2x_get_stats(struct aq_softc *sc, struct aq_hw_stats_s *w) 2211 { 2212 return 0; 2213 } 2214 2215 static int 2216 aq2_fw_wait_shared_ack(struct aq_softc *sc) 2217 { 2218 int error; 2219 2220 AQ_WRITE_REG(sc, AQ2_MIF_HOST_FINISHED_STATUS_WRITE_REG, 2221 AQ2_MIF_HOST_FINISHED_STATUS_ACK); 2222 WAIT_FOR((AQ_READ_REG(sc, AQ2_MIF_HOST_FINISHED_STATUS_READ_REG) & 2223 AQ2_MIF_HOST_FINISHED_STATUS_ACK) == 0, 100, 100000, &error); 2224 2225 return error; 2226 } 2227 2228 int 2229 aq2_fw_reset(struct aq_softc *sc) 2230 { 2231 uint32_t v; 2232 int error; 2233 2234 AQ_WRITE_REG_BIT(sc, AQ2_FW_INTERFACE_IN_LINK_CONTROL_REG, 2235 AQ2_FW_INTERFACE_IN_LINK_CONTROL_MODE, 2236 AQ2_FW_INTERFACE_IN_LINK_CONTROL_MODE_ACTIVE); 2237 2238 AQ_WRITE_REG(sc, AQ2_FW_INTERFACE_IN_MTU_REG, 2239 /*AQ2_JUMBO_MTU*/ MCLBYTES + sizeof(struct ether_header)); 2240 2241 v = AQ_READ_REG(sc, AQ2_FW_INTERFACE_IN_REQUEST_POLICY_REG); 2242 v |= AQ2_FW_INTERFACE_IN_REQUEST_POLICY_MCAST_QUEUE_OR_TC; 2243 v &= ~AQ2_FW_INTERFACE_IN_REQUEST_POLICY_MCAST_RX_QUEUE_TC_INDEX; 2244 v |= AQ2_FW_INTERFACE_IN_REQUEST_POLICY_MCAST_ACCEPT; 2245 v |= AQ2_FW_INTERFACE_IN_REQUEST_POLICY_BCAST_QUEUE_OR_TC; 2246 v &= AQ2_FW_INTERFACE_IN_REQUEST_POLICY_BCAST_RX_QUEUE_TC_INDEX; 2247 v |= AQ2_FW_INTERFACE_IN_REQUEST_POLICY_BCAST_ACCEPT; 2248 v |= AQ2_FW_INTERFACE_IN_REQUEST_POLICY_PROMISC_QUEUE_OR_TC; 2249 v &= ~AQ2_FW_INTERFACE_IN_REQUEST_POLICY_PROMISC_RX_QUEUE_TX_INDEX; 2250 AQ_WRITE_REG(sc, AQ2_FW_INTERFACE_IN_REQUEST_POLICY_REG, v); 2251 2252 error = aq2_fw_wait_shared_ack(sc); 2253 if (error != 0) 2254 printf(": reset timed out\n"); 2255 return error; 2256 } 2257 2258 int 2259 aq2_get_mac_addr(struct aq_softc *sc) 2260 { 2261 uint32_t mac_addr[2]; 2262 2263 memset(mac_addr, 0, sizeof(mac_addr)); 2264 AQ_READ_REGS(sc, AQ2_FW_INTERFACE_IN_MAC_ADDRESS_REG, 2265 mac_addr, nitems(mac_addr)); 2266 2267 #ifdef __HAVE_FDT 2268 if (mac_addr[0] == 0 && mac_addr[1] == 0 && 2269 PCITAG_NODE(sc->sc_pcitag)) { 2270 OF_getprop(PCITAG_NODE(sc->sc_pcitag), "local-mac-address", 2271 mac_addr, ETHER_ADDR_LEN); 2272 } 2273 #endif 2274 2275 if (mac_addr[0] == 0 && mac_addr[1] == 0) { 2276 printf(": mac address not found\n"); 2277 return ENXIO; 2278 } 2279 2280 mac_addr[0] = htole32(mac_addr[0]); 2281 mac_addr[1] = htole32(mac_addr[1]); 2282 2283 memcpy(sc->sc_enaddr.ether_addr_octet, 2284 (uint8_t *)mac_addr, ETHER_ADDR_LEN); 2285 return 0; 2286 } 2287 2288 int 2289 aq2_fw_set_mode(struct aq_softc *sc, enum aq_hw_fw_mpi_state w, 2290 enum aq_link_speed speed, enum aq_link_fc fc, enum aq_link_eee eee) 2291 { 2292 uint32_t v, ov; 2293 int error; 2294 2295 AQ_MPI_LOCK(sc); 2296 2297 v = AQ_READ_REG(sc, AQ2_FW_INTERFACE_IN_LINK_OPTIONS_REG); 2298 v &= ~( 2299 AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_10G | 2300 AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_N5G | 2301 AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_5G | 2302 AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_N2G5 | 2303 AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_2G5 | 2304 AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_1G | 2305 AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_100M | 2306 AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_10M | 2307 AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_1G_HD | 2308 AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_100M_HD | 2309 AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_10M_HD); 2310 2311 v &= ~AQ2_FW_INTERFACE_IN_LINK_OPTIONS_LINK_UP; 2312 ov = v; 2313 2314 if (speed & AQ_LINK_10G) 2315 v |= AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_10G; 2316 if (speed & AQ_LINK_5G) 2317 v |= AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_N5G | 2318 AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_5G; 2319 if (speed & AQ_LINK_2G5) 2320 v |= AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_N2G5 | 2321 AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_2G5; 2322 if (speed & AQ_LINK_1G) 2323 v |= AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_1G | 2324 AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_1G_HD; 2325 if (speed & AQ_LINK_100M) 2326 v |= AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_100M | 2327 AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_100M_HD; 2328 if (speed & AQ_LINK_10M) { 2329 v |= AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_10M | 2330 AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_10M_HD; 2331 } 2332 2333 /* flow control */ 2334 v &= ~(AQ2_FW_INTERFACE_IN_LINK_OPTIONS_PAUSE_TX | 2335 AQ2_FW_INTERFACE_IN_LINK_OPTIONS_PAUSE_RX); 2336 if (fc & AQ_FC_TX) 2337 v |= AQ2_FW_INTERFACE_IN_LINK_OPTIONS_PAUSE_TX; 2338 if (fc & AQ_FC_RX) 2339 v |= AQ2_FW_INTERFACE_IN_LINK_OPTIONS_PAUSE_RX; 2340 2341 if (speed == AQ_LINK_NONE) { 2342 AQ_WRITE_REG_BIT(sc, AQ2_FW_INTERFACE_IN_LINK_CONTROL_REG, 2343 AQ2_FW_INTERFACE_IN_LINK_CONTROL_MODE, 2344 AQ2_FW_INTERFACE_IN_LINK_CONTROL_MODE_SHUTDOWN); 2345 } else { 2346 AQ_WRITE_REG_BIT(sc, AQ2_FW_INTERFACE_IN_LINK_CONTROL_REG, 2347 AQ2_FW_INTERFACE_IN_LINK_CONTROL_MODE, 2348 AQ2_FW_INTERFACE_IN_LINK_CONTROL_MODE_ACTIVE); 2349 v |= AQ2_FW_INTERFACE_IN_LINK_OPTIONS_LINK_UP; 2350 } 2351 2352 AQ_WRITE_REG(sc, AQ2_FW_INTERFACE_IN_LINK_OPTIONS_REG, v); 2353 error = aq2_fw_wait_shared_ack(sc); 2354 2355 AQ_MPI_UNLOCK(sc); 2356 return error; 2357 } 2358 2359 int 2360 aq2_fw_get_mode(struct aq_softc *sc, enum aq_hw_fw_mpi_state *modep, 2361 enum aq_link_speed *speedp, enum aq_link_fc *fcp, enum aq_link_eee *eeep) 2362 { 2363 uint32_t v; 2364 enum aq_link_speed speed; 2365 enum aq_link_fc fc = 0; 2366 enum aq_link_eee eee; 2367 2368 if (modep != NULL) 2369 *modep = MPI_INIT; 2370 2371 v = AQ_READ_REG(sc, AQ2_FW_INTERFACE_OUT_LINK_STATUS_REG); 2372 switch ((v & AQ2_FW_INTERFACE_OUT_LINK_STATUS_RATE) >> 2373 AQ2_FW_INTERFACE_OUT_LINK_STATUS_RATE_S) { 2374 case AQ2_FW_INTERFACE_OUT_LINK_STATUS_RATE_10G: 2375 speed = AQ_LINK_10G; 2376 break; 2377 case AQ2_FW_INTERFACE_OUT_LINK_STATUS_RATE_5G: 2378 speed = AQ_LINK_5G; 2379 break; 2380 case AQ2_FW_INTERFACE_OUT_LINK_STATUS_RATE_2G5: 2381 speed = AQ_LINK_2G5; 2382 break; 2383 case AQ2_FW_INTERFACE_OUT_LINK_STATUS_RATE_1G: 2384 speed = AQ_LINK_1G; 2385 break; 2386 case AQ2_FW_INTERFACE_OUT_LINK_STATUS_RATE_100M: 2387 speed = AQ_LINK_100M; 2388 break; 2389 case AQ2_FW_INTERFACE_OUT_LINK_STATUS_RATE_10M: 2390 speed = AQ_LINK_10M; 2391 break; 2392 case AQ2_FW_INTERFACE_OUT_LINK_STATUS_RATE_INVALID: 2393 default: 2394 speed = AQ_LINK_NONE; 2395 break; 2396 } 2397 if (speedp != NULL) 2398 *speedp = speed; 2399 2400 if (v & AQ2_FW_INTERFACE_OUT_LINK_STATUS_PAUSE_TX) 2401 fc |= AQ_FC_TX; 2402 if (v & AQ2_FW_INTERFACE_OUT_LINK_STATUS_PAUSE_RX) 2403 fc |= AQ_FC_RX; 2404 if (fcp != NULL) 2405 *fcp = fc; 2406 2407 eee = (v & AQ2_FW_INTERFACE_OUT_LINK_STATUS_EEE) ? 2408 AQ_EEE_ENABLE : AQ_EEE_DISABLE; 2409 if (eeep != NULL) 2410 *eeep = eee; 2411 2412 return 0; 2413 } 2414 2415 int 2416 aq2_fw_get_stats(struct aq_softc *sc, struct aq_hw_stats_s *w) 2417 { 2418 return 0; 2419 } 2420 2421 void 2422 aq_hw_l3_filter_set(struct aq_softc *sc) 2423 { 2424 int i; 2425 2426 /* clear all filter */ 2427 for (i = 0; i < 8; i++) { 2428 AQ_WRITE_REG_BIT(sc, RPF_L3_FILTER_REG(i), 2429 RPF_L3_FILTER_L4_EN, 0); 2430 } 2431 } 2432 2433 int 2434 aq_hw_init(struct aq_softc *sc, int irqmode, int multivec) 2435 { 2436 uint32_t v; 2437 2438 if (HWTYPE_AQ1_P(sc)) { 2439 /* Force limit MRRS on RDM/TDM to 2K */ 2440 v = AQ_READ_REG(sc, AQ_PCI_REG_CONTROL_6_REG); 2441 AQ_WRITE_REG(sc, AQ_PCI_REG_CONTROL_6_REG, 2442 (v & ~0x0707) | 0x0404); 2443 2444 /* 2445 * TX DMA total request limit. B0 hardware is not capable to 2446 * handle more than (8K-MRRS) incoming DMA data. 2447 * Value 24 in 256byte units 2448 */ 2449 AQ_WRITE_REG(sc, AQ_HW_TX_DMA_TOTAL_REQ_LIMIT_REG, 24); 2450 } 2451 2452 if (HWTYPE_AQ2_P(sc)) { 2453 uint32_t fpgaver, speed; 2454 fpgaver = AQ_READ_REG(sc, AQ2_HW_FPGA_VERSION_REG); 2455 if (fpgaver < 0x01000000) 2456 speed = AQ2_LAUNCHTIME_CTRL_RATIO_SPEED_FULL; 2457 else if (fpgaver >= 0x01008502) 2458 speed = AQ2_LAUNCHTIME_CTRL_RATIO_SPEED_HALF; 2459 else 2460 speed = AQ2_LAUNCHTIME_CTRL_RATIO_SPEED_QUARTER; 2461 AQ_WRITE_REG_BIT(sc, AQ2_LAUNCHTIME_CTRL_REG, 2462 AQ2_LAUNCHTIME_CTRL_RATIO, speed); 2463 } 2464 2465 aq_hw_init_tx_path(sc); 2466 aq_hw_init_rx_path(sc); 2467 2468 if (aq_set_mac_addr(sc, AQ_HW_MAC_OWN, sc->sc_enaddr.ether_addr_octet)) 2469 return EINVAL; 2470 2471 aq_set_linkmode(sc, AQ_LINK_NONE, AQ_FC_NONE, AQ_EEE_DISABLE); 2472 2473 aq_hw_qos_set(sc); 2474 2475 if (HWTYPE_AQ2_P(sc)) { 2476 AQ_WRITE_REG_BIT(sc, AQ2_RPF_NEW_CTRL_REG, 2477 AQ2_RPF_NEW_CTRL_ENABLE, 1); 2478 } 2479 2480 /* Enable interrupt */ 2481 AQ_WRITE_REG(sc, AQ_INTR_CTRL_REG, AQ_INTR_CTRL_RESET_DIS); 2482 AQ_WRITE_REG_BIT(sc, AQ_INTR_CTRL_REG, AQ_INTR_CTRL_MULTIVEC, multivec); 2483 2484 AQ_WRITE_REG_BIT(sc, AQ_INTR_CTRL_REG, AQ_INTR_CTRL_IRQMODE, irqmode); 2485 2486 AQ_WRITE_REG(sc, AQ_INTR_AUTOMASK_REG, 0xffffffff); 2487 2488 AQ_WRITE_REG(sc, AQ_GEN_INTR_MAP_REG(0), 2489 ((AQ_B0_ERR_INT << 24) | (1U << 31)) | 2490 ((AQ_B0_ERR_INT << 16) | (1 << 23)) 2491 ); 2492 2493 /* link interrupt */ 2494 AQ_WRITE_REG(sc, AQ_GEN_INTR_MAP_REG(3), 2495 (1 << 7) | sc->sc_linkstat_irq); 2496 2497 return 0; 2498 } 2499 2500 void 2501 aq_hw_init_tx_path(struct aq_softc *sc) 2502 { 2503 /* Tx TC/RSS number config */ 2504 AQ_WRITE_REG_BIT(sc, TPB_TX_BUF_REG, TPB_TX_BUF_TC_MODE_EN, 1); 2505 2506 AQ_WRITE_REG_BIT(sc, THM_LSO_TCP_FLAG1_REG, 2507 THM_LSO_TCP_FLAG1_FIRST, 0x0ff6); 2508 AQ_WRITE_REG_BIT(sc, THM_LSO_TCP_FLAG1_REG, 2509 THM_LSO_TCP_FLAG1_MID, 0x0ff6); 2510 AQ_WRITE_REG_BIT(sc, THM_LSO_TCP_FLAG2_REG, 2511 THM_LSO_TCP_FLAG2_LAST, 0x0f7f); 2512 2513 /* misc */ 2514 AQ_WRITE_REG(sc, TX_TPO2_REG, 2515 (sc->sc_features & FEATURES_TPO2) ? TX_TPO2_EN : 0); 2516 AQ_WRITE_REG_BIT(sc, TDM_DCA_REG, TDM_DCA_EN, 0); 2517 AQ_WRITE_REG_BIT(sc, TDM_DCA_REG, TDM_DCA_MODE, 0); 2518 2519 AQ_WRITE_REG_BIT(sc, TPB_TX_BUF_REG, TPB_TX_BUF_SCP_INS_EN, 1); 2520 2521 if ((sc->sc_features & FEATURES_AQ1_REV_B) || HWTYPE_AQ2_P(sc)) { 2522 AQ_WRITE_REG_BIT(sc, TPB_TX_BUF_REG, TPB_TX_BUF_CLK_GATE_EN, 0); 2523 } 2524 } 2525 2526 void 2527 aq_hw_init_rx_path(struct aq_softc *sc) 2528 { 2529 int i; 2530 2531 /* clear setting */ 2532 AQ_WRITE_REG_BIT(sc, RPB_RPF_RX_REG, RPB_RPF_RX_TC_MODE, 0); 2533 AQ_WRITE_REG_BIT(sc, RPB_RPF_RX_REG, RPB_RPF_RX_FC_MODE, 0); 2534 2535 if (HWTYPE_AQ2_P(sc)) { 2536 AQ_WRITE_REG_BIT(sc, AQ2_RPF_REDIR2_REG, 2537 AQ2_RPF_REDIR2_HASHTYPE, AQ2_RPF_REDIR2_HASHTYPE_ALL); 2538 } 2539 2540 if (sc->sc_nqueues > 1) { 2541 uint32_t bits; 2542 2543 AQ_WRITE_REG_BIT(sc, RPB_RPF_RX_REG, RPB_RPF_RX_TC_MODE, 1); 2544 AQ_WRITE_REG_BIT(sc, RPB_RPF_RX_REG, RPB_RPF_RX_FC_MODE, 1); 2545 2546 switch (sc->sc_nqueues) { 2547 case 2: 2548 bits = 0x11111111; 2549 break; 2550 case 4: 2551 bits = 0x22222222; 2552 break; 2553 case 8: 2554 bits = 0x33333333; 2555 break; 2556 } 2557 2558 AQ_WRITE_REG(sc, RX_FLR_RSS_CONTROL1_REG, 2559 RX_FLR_RSS_CONTROL1_EN | bits); 2560 } else { 2561 AQ_WRITE_REG(sc, RX_FLR_RSS_CONTROL1_REG, 0); 2562 } 2563 2564 if (HWTYPE_AQ1_P(sc)) { 2565 for (i = 0; i < 32; i++) { 2566 AQ_WRITE_REG_BIT(sc, RPF_ETHERTYPE_FILTER_REG(i), 2567 RPF_ETHERTYPE_FILTER_EN, 0); 2568 } 2569 } 2570 2571 /* L2 and Multicast filters */ 2572 for (i = 0; i < AQ_HW_MAC_NUM; i++) { 2573 AQ_WRITE_REG_BIT(sc, RPF_L2UC_MSW_REG(i), RPF_L2UC_MSW_EN, 0); 2574 AQ_WRITE_REG_BIT(sc, RPF_L2UC_MSW_REG(i), RPF_L2UC_MSW_ACTION, 2575 RPF_ACTION_HOST); 2576 } 2577 AQ_WRITE_REG(sc, RPF_MCAST_FILTER_MASK_REG, 0); 2578 AQ_WRITE_REG(sc, RPF_MCAST_FILTER_REG(0), 0x00010fff); 2579 2580 /* Vlan filters */ 2581 AQ_WRITE_REG_BIT(sc, RPF_VLAN_TPID_REG, RPF_VLAN_TPID_OUTER, 2582 ETHERTYPE_QINQ); 2583 AQ_WRITE_REG_BIT(sc, RPF_VLAN_TPID_REG, RPF_VLAN_TPID_INNER, 2584 ETHERTYPE_VLAN); 2585 AQ_WRITE_REG_BIT(sc, RPF_VLAN_MODE_REG, RPF_VLAN_MODE_PROMISC, 1); 2586 2587 if ((sc->sc_features & FEATURES_AQ1_REV_B) || HWTYPE_AQ2_P(sc)) { 2588 AQ_WRITE_REG_BIT(sc, RPF_VLAN_MODE_REG, 2589 RPF_VLAN_MODE_ACCEPT_UNTAGGED, 1); 2590 AQ_WRITE_REG_BIT(sc, RPF_VLAN_MODE_REG, 2591 RPF_VLAN_MODE_UNTAGGED_ACTION, RPF_ACTION_HOST); 2592 } 2593 2594 if (HWTYPE_AQ2_P(sc)) { 2595 AQ_WRITE_REG_BIT(sc, AQ2_RPF_REC_TAB_ENABLE_REG, 2596 AQ2_RPF_REC_TAB_ENABLE_MASK, 0xffff); 2597 AQ_WRITE_REG_BIT(sc, RPF_L2UC_MSW_REG(0), 2598 RPF_L2UC_MSW_TAG, 1); 2599 AQ_WRITE_REG_BIT(sc, AQ2_RPF_L2BC_TAG_REG, 2600 AQ2_RPF_L2BC_TAG_MASK, 1); 2601 2602 aq2_filter_art_set(sc, AQ2_RPF_INDEX_L2_PROMISC_OFF, 2603 0, AQ2_RPF_TAG_UC_MASK | AQ2_RPF_TAG_ALLMC_MASK, 2604 AQ2_ART_ACTION_DROP); 2605 aq2_filter_art_set(sc, AQ2_RPF_INDEX_VLAN_PROMISC_OFF, 2606 0, AQ2_RPF_TAG_VLAN_MASK | AQ2_RPF_TAG_UNTAG_MASK, 2607 AQ2_ART_ACTION_DROP); 2608 2609 for (int i = 0; i < 8; i++) { 2610 aq2_filter_art_set(sc, AQ2_RPF_INDEX_PCP_TO_TC + i, 2611 (i << AQ2_RPF_TAG_PCP_SHIFT), AQ2_RPF_TAG_PCP_MASK, 2612 AQ2_ART_ACTION_ASSIGN_TC(i % sc->sc_nqueues)); 2613 } 2614 2615 } else if (HWTYPE_AQ1_P(sc)) { 2616 if (sc->sc_features & FEATURES_RPF2) 2617 AQ_WRITE_REG(sc, RX_TCP_RSS_HASH_REG, 2618 RX_TCP_RSS_HASH_RPF2); 2619 else 2620 AQ_WRITE_REG(sc, RX_TCP_RSS_HASH_REG, 0); 2621 2622 /* we might want to figure out what this magic number does */ 2623 AQ_WRITE_REG_BIT(sc, RX_TCP_RSS_HASH_REG, 2624 RX_TCP_RSS_HASH_TYPE, 0x001e); 2625 } 2626 2627 AQ_WRITE_REG_BIT(sc, RPF_L2BC_REG, RPF_L2BC_EN, 1); 2628 AQ_WRITE_REG_BIT(sc, RPF_L2BC_REG, RPF_L2BC_ACTION, RPF_ACTION_HOST); 2629 AQ_WRITE_REG_BIT(sc, RPF_L2BC_REG, RPF_L2BC_THRESHOLD, 0xffff); 2630 2631 AQ_WRITE_REG_BIT(sc, RX_DMA_DCA_REG, RX_DMA_DCA_EN, 0); 2632 AQ_WRITE_REG_BIT(sc, RX_DMA_DCA_REG, RX_DMA_DCA_MODE, 0); 2633 } 2634 2635 /* set multicast filter. index 0 for own address */ 2636 int 2637 aq_set_mac_addr(struct aq_softc *sc, int index, uint8_t *enaddr) 2638 { 2639 uint32_t h, l; 2640 2641 if (index >= AQ_HW_MAC_NUM) 2642 return EINVAL; 2643 2644 if (enaddr == NULL) { 2645 /* disable */ 2646 AQ_WRITE_REG_BIT(sc, 2647 RPF_L2UC_MSW_REG(index), RPF_L2UC_MSW_EN, 0); 2648 return 0; 2649 } 2650 2651 h = (enaddr[0] << 8) | (enaddr[1]); 2652 l = ((uint32_t)enaddr[2] << 24) | (enaddr[3] << 16) | 2653 (enaddr[4] << 8) | (enaddr[5]); 2654 2655 /* disable, set, and enable */ 2656 AQ_WRITE_REG_BIT(sc, RPF_L2UC_MSW_REG(index), RPF_L2UC_MSW_EN, 0); 2657 AQ_WRITE_REG(sc, RPF_L2UC_LSW_REG(index), l); 2658 AQ_WRITE_REG_BIT(sc, RPF_L2UC_MSW_REG(index), 2659 RPF_L2UC_MSW_MACADDR_HI, h); 2660 AQ_WRITE_REG_BIT(sc, RPF_L2UC_MSW_REG(index), 2661 RPF_L2UC_MSW_ACTION, RPF_ACTION_HOST); 2662 if (HWTYPE_AQ2_P(sc)) 2663 AQ_WRITE_REG_BIT(sc, RPF_L2UC_MSW_REG(index), 2664 RPF_L2UC_MSW_TAG, 1); 2665 AQ_WRITE_REG_BIT(sc, RPF_L2UC_MSW_REG(index), RPF_L2UC_MSW_EN, 1); 2666 2667 return 0; 2668 } 2669 2670 int 2671 aq_get_linkmode(struct aq_softc *sc, enum aq_link_speed *speed, 2672 enum aq_link_fc *fc, enum aq_link_eee *eee) 2673 { 2674 enum aq_hw_fw_mpi_state mode; 2675 int error; 2676 2677 error = sc->sc_fw_ops->get_mode(sc, &mode, speed, fc, eee); 2678 if (error != 0) 2679 return error; 2680 if (mode != MPI_INIT) 2681 return ENXIO; 2682 2683 return 0; 2684 } 2685 2686 int 2687 aq_set_linkmode(struct aq_softc *sc, enum aq_link_speed speed, 2688 enum aq_link_fc fc, enum aq_link_eee eee) 2689 { 2690 return sc->sc_fw_ops->set_mode(sc, MPI_INIT, speed, fc, eee); 2691 } 2692 2693 int 2694 aq_fw2x_set_mode(struct aq_softc *sc, enum aq_hw_fw_mpi_state mode, 2695 enum aq_link_speed speed, enum aq_link_fc fc, enum aq_link_eee eee) 2696 { 2697 uint64_t mpi_ctrl; 2698 int error = 0; 2699 2700 AQ_MPI_LOCK(sc); 2701 2702 mpi_ctrl = AQ_READ64_REG(sc, FW2X_MPI_CONTROL_REG); 2703 2704 switch (mode) { 2705 case MPI_INIT: 2706 mpi_ctrl &= ~FW2X_CTRL_RATE_MASK; 2707 if (speed & AQ_LINK_10G) 2708 mpi_ctrl |= FW2X_CTRL_RATE_10G; 2709 if (speed & AQ_LINK_5G) 2710 mpi_ctrl |= FW2X_CTRL_RATE_5G; 2711 if (speed & AQ_LINK_2G5) 2712 mpi_ctrl |= FW2X_CTRL_RATE_2G5; 2713 if (speed & AQ_LINK_1G) 2714 mpi_ctrl |= FW2X_CTRL_RATE_1G; 2715 if (speed & AQ_LINK_100M) 2716 mpi_ctrl |= FW2X_CTRL_RATE_100M; 2717 2718 mpi_ctrl &= ~FW2X_CTRL_LINK_DROP; 2719 2720 mpi_ctrl &= ~FW2X_CTRL_EEE_MASK; 2721 if (eee == AQ_EEE_ENABLE) 2722 mpi_ctrl |= FW2X_CTRL_EEE_MASK; 2723 2724 mpi_ctrl &= ~(FW2X_CTRL_PAUSE | FW2X_CTRL_ASYMMETRIC_PAUSE); 2725 if (fc & AQ_FC_RX) 2726 mpi_ctrl |= FW2X_CTRL_PAUSE; 2727 if (fc & AQ_FC_TX) 2728 mpi_ctrl |= FW2X_CTRL_ASYMMETRIC_PAUSE; 2729 break; 2730 case MPI_DEINIT: 2731 mpi_ctrl &= ~(FW2X_CTRL_RATE_MASK | FW2X_CTRL_EEE_MASK); 2732 mpi_ctrl &= ~(FW2X_CTRL_PAUSE | FW2X_CTRL_ASYMMETRIC_PAUSE); 2733 break; 2734 default: 2735 printf("%s: fw2x> unknown MPI state %d\n", DEVNAME(sc), mode); 2736 error = EINVAL; 2737 goto failure; 2738 } 2739 AQ_WRITE64_REG(sc, FW2X_MPI_CONTROL_REG, mpi_ctrl); 2740 2741 failure: 2742 AQ_MPI_UNLOCK(sc); 2743 return error; 2744 } 2745 2746 void 2747 aq_hw_qos_set(struct aq_softc *sc) 2748 { 2749 uint32_t tc = 0; 2750 uint32_t buff_size; 2751 2752 /* TPS Descriptor rate init */ 2753 AQ_WRITE_REG_BIT(sc, TPS_DESC_RATE_REG, TPS_DESC_RATE_TA_RST, 0); 2754 AQ_WRITE_REG_BIT(sc, TPS_DESC_RATE_REG, TPS_DESC_RATE_LIM, 0xa); 2755 2756 /* TPS VM init */ 2757 AQ_WRITE_REG_BIT(sc, TPS_DESC_VM_ARB_MODE_REG, TPS_DESC_VM_ARB_MODE, 0); 2758 2759 /* TPS TC credits init */ 2760 AQ_WRITE_REG_BIT(sc, TPS_DESC_TC_ARB_MODE_REG, TPS_DESC_TC_ARB_MODE, 0); 2761 AQ_WRITE_REG_BIT(sc, TPS_DATA_TC_ARB_MODE_REG, TPS_DATA_TC_ARB_MODE, 0); 2762 2763 AQ_WRITE_REG_BIT(sc, TPS_DATA_TCT_REG(tc), 2764 TPS_DATA_TCT_CREDIT_MAX, 0xfff); 2765 AQ_WRITE_REG_BIT(sc, TPS_DATA_TCT_REG(tc), 2766 TPS_DATA_TCT_WEIGHT, 0x64); 2767 AQ_WRITE_REG_BIT(sc, TPS_DESC_TCT_REG(tc), 2768 TPS_DESC_TCT_CREDIT_MAX, 0x50); 2769 AQ_WRITE_REG_BIT(sc, TPS_DESC_TCT_REG(tc), 2770 TPS_DESC_TCT_WEIGHT, 0x1e); 2771 2772 /* Tx buf size */ 2773 tc = 0; 2774 buff_size = AQ_HW_TXBUF_MAX; 2775 AQ_WRITE_REG_BIT(sc, TPB_TXB_BUFSIZE_REG(tc), TPB_TXB_BUFSIZE, 2776 buff_size); 2777 AQ_WRITE_REG_BIT(sc, TPB_TXB_THRESH_REG(tc), TPB_TXB_THRESH_HI, 2778 (buff_size * (1024 / 32) * 66) / 100); 2779 AQ_WRITE_REG_BIT(sc, TPB_TXB_THRESH_REG(tc), TPB_TXB_THRESH_LO, 2780 (buff_size * (1024 / 32) * 50) / 100); 2781 2782 /* QoS Rx buf size per TC */ 2783 tc = 0; 2784 buff_size = AQ_HW_RXBUF_MAX; 2785 AQ_WRITE_REG_BIT(sc, RPB_RXB_BUFSIZE_REG(tc), RPB_RXB_BUFSIZE, 2786 buff_size); 2787 AQ_WRITE_REG_BIT(sc, RPB_RXB_XOFF_REG(tc), RPB_RXB_XOFF_EN, 0); 2788 AQ_WRITE_REG_BIT(sc, RPB_RXB_XOFF_REG(tc), RPB_RXB_XOFF_THRESH_HI, 2789 (buff_size * (1024 / 32) * 66) / 100); 2790 AQ_WRITE_REG_BIT(sc, RPB_RXB_XOFF_REG(tc), RPB_RXB_XOFF_THRESH_LO, 2791 (buff_size * (1024 / 32) * 50) / 100); 2792 2793 /* QoS 802.1p priority -> TC mapping */ 2794 int i_priority; 2795 for (i_priority = 0; i_priority < 8; i_priority++) { 2796 AQ_WRITE_REG_BIT(sc, RPF_RPB_RX_TC_UPT_REG, 2797 RPF_RPB_RX_TC_UPT_MASK(i_priority), 0); 2798 } 2799 } 2800 2801 int 2802 aq_init_rss(struct aq_softc *sc) 2803 { 2804 uint32_t rss_key[AQ_RSS_KEYSIZE / sizeof(uint32_t)]; 2805 uint32_t redir; 2806 int bits, queue; 2807 int error; 2808 int i; 2809 2810 if (sc->sc_nqueues == 1) 2811 return 0; 2812 2813 /* rss key is composed of 32 bit registers */ 2814 stoeplitz_to_key(rss_key, sizeof(rss_key)); 2815 for (i = 0; i < nitems(rss_key); i++) { 2816 AQ_WRITE_REG(sc, RPF_RSS_KEY_WR_DATA_REG, htole32(rss_key[i])); 2817 AQ_WRITE_REG_BIT(sc, RPF_RSS_KEY_ADDR_REG, RPF_RSS_KEY_ADDR, 2818 nitems(rss_key) - 1 - i); 2819 AQ_WRITE_REG_BIT(sc, RPF_RSS_KEY_ADDR_REG, RPF_RSS_KEY_WR_EN, 2820 1); 2821 WAIT_FOR((AQ_READ_REG(sc, RPF_RSS_KEY_ADDR_REG) & 2822 RPF_RSS_KEY_WR_EN) == 0, 1000, 10, &error); 2823 if (error != 0) { 2824 printf(": timed out setting rss key\n"); 2825 return error; 2826 } 2827 } 2828 2829 /* 2830 * the redirection table has 64 entries, each entry is a 3 bit 2831 * queue number, packed into a 16 bit register, so there are 12 2832 * registers to program. 2833 */ 2834 bits = 0; 2835 redir = 0; 2836 queue = 0; 2837 for (i = 0; i < AQ_RSS_REDIR_ENTRIES; i++) { 2838 while (bits < 16) { 2839 redir |= (queue << bits); 2840 bits += 3; 2841 queue++; 2842 if (queue == sc->sc_nqueues) 2843 queue = 0; 2844 } 2845 2846 AQ_WRITE_REG(sc, RPF_RSS_REDIR_WR_DATA_REG, htole16(redir)); 2847 AQ_WRITE_REG_BIT(sc, RPF_RSS_REDIR_ADDR_REG, RPF_RSS_REDIR_ADDR, 2848 i); 2849 AQ_WRITE_REG_BIT(sc, RPF_RSS_REDIR_ADDR_REG, 2850 RPF_RSS_REDIR_WR_EN, 1); 2851 WAIT_FOR((AQ_READ_REG(sc, RPF_RSS_REDIR_ADDR_REG) & 2852 RPF_RSS_REDIR_WR_EN) == 0, 1000, 10, &error); 2853 if (error != 0) { 2854 printf(": timed out setting rss table\n"); 2855 return error; 2856 } 2857 redir >>= 16; 2858 bits -= 16; 2859 } 2860 2861 return 0; 2862 } 2863 2864 void 2865 aq_txring_reset(struct aq_softc *sc, struct aq_txring *tx, int start) 2866 { 2867 daddr_t paddr; 2868 2869 tx->tx_prod = 0; 2870 tx->tx_cons = 0; 2871 2872 /* empty slots? */ 2873 2874 AQ_WRITE_REG_BIT(sc, TX_DMA_DESC_REG(tx->tx_q), TX_DMA_DESC_EN, 0); 2875 2876 if (start == 0) 2877 return; 2878 2879 paddr = AQ_DMA_DVA(&tx->tx_mem); 2880 AQ_WRITE_REG(sc, TX_DMA_DESC_BASE_ADDRLSW_REG(tx->tx_q), paddr); 2881 AQ_WRITE_REG(sc, TX_DMA_DESC_BASE_ADDRMSW_REG(tx->tx_q), 2882 paddr >> 32); 2883 2884 AQ_WRITE_REG_BIT(sc, TX_DMA_DESC_REG(tx->tx_q), TX_DMA_DESC_LEN, 2885 AQ_TXD_NUM / 8); 2886 2887 tx->tx_prod = AQ_READ_REG(sc, TX_DMA_DESC_TAIL_PTR_REG(tx->tx_q)); 2888 tx->tx_cons = tx->tx_prod; 2889 AQ_WRITE_REG(sc, TX_DMA_DESC_WRWB_THRESH_REG(tx->tx_q), 0); 2890 2891 AQ_WRITE_REG_BIT(sc, AQ_INTR_IRQ_MAP_TX_REG(tx->tx_q), 2892 AQ_INTR_IRQ_MAP_TX_IRQMAP(tx->tx_q), tx->tx_irq); 2893 AQ_WRITE_REG_BIT(sc, AQ_INTR_IRQ_MAP_TX_REG(tx->tx_q), 2894 AQ_INTR_IRQ_MAP_TX_EN(tx->tx_q), 1); 2895 2896 AQ_WRITE_REG_BIT(sc, TX_DMA_DESC_REG(tx->tx_q), TX_DMA_DESC_EN, 1); 2897 2898 AQ_WRITE_REG_BIT(sc, TDM_DCAD_REG(tx->tx_q), TDM_DCAD_CPUID, 0); 2899 AQ_WRITE_REG_BIT(sc, TDM_DCAD_REG(tx->tx_q), TDM_DCAD_CPUID_EN, 0); 2900 } 2901 2902 void 2903 aq_rxring_reset(struct aq_softc *sc, struct aq_rxring *rx, int start) 2904 { 2905 daddr_t paddr; 2906 int strip; 2907 2908 AQ_WRITE_REG_BIT(sc, RX_DMA_DESC_REG(rx->rx_q), RX_DMA_DESC_EN, 0); 2909 /* drain */ 2910 2911 if (start == 0) 2912 return; 2913 2914 paddr = AQ_DMA_DVA(&rx->rx_mem); 2915 AQ_WRITE_REG(sc, RX_DMA_DESC_BASE_ADDRLSW_REG(rx->rx_q), paddr); 2916 AQ_WRITE_REG(sc, RX_DMA_DESC_BASE_ADDRMSW_REG(rx->rx_q), 2917 paddr >> 32); 2918 2919 AQ_WRITE_REG_BIT(sc, RX_DMA_DESC_REG(rx->rx_q), RX_DMA_DESC_LEN, 2920 AQ_RXD_NUM / 8); 2921 2922 AQ_WRITE_REG_BIT(sc, RX_DMA_DESC_BUFSIZE_REG(rx->rx_q), 2923 RX_DMA_DESC_BUFSIZE_DATA, MCLBYTES / 1024); 2924 AQ_WRITE_REG_BIT(sc, RX_DMA_DESC_BUFSIZE_REG(rx->rx_q), 2925 RX_DMA_DESC_BUFSIZE_HDR, 0); 2926 AQ_WRITE_REG_BIT(sc, RX_DMA_DESC_REG(rx->rx_q), 2927 RX_DMA_DESC_HEADER_SPLIT, 0); 2928 2929 #if NVLAN > 0 2930 strip = 1; 2931 #else 2932 strip = 0; 2933 #endif 2934 AQ_WRITE_REG_BIT(sc, RX_DMA_DESC_REG(rx->rx_q), 2935 RX_DMA_DESC_VLAN_STRIP, strip); 2936 2937 rx->rx_cons = AQ_READ_REG(sc, RX_DMA_DESC_HEAD_PTR_REG(rx->rx_q)) & 2938 RX_DMA_DESC_HEAD_PTR; 2939 AQ_WRITE_REG(sc, RX_DMA_DESC_TAIL_PTR_REG(rx->rx_q), rx->rx_cons); 2940 rx->rx_prod = rx->rx_cons; 2941 2942 AQ_WRITE_REG_BIT(sc, AQ_INTR_IRQ_MAP_RX_REG(rx->rx_q), 2943 AQ_INTR_IRQ_MAP_RX_IRQMAP(rx->rx_q), rx->rx_irq); 2944 AQ_WRITE_REG_BIT(sc, AQ_INTR_IRQ_MAP_RX_REG(rx->rx_q), 2945 AQ_INTR_IRQ_MAP_RX_EN(rx->rx_q), 1); 2946 2947 AQ_WRITE_REG_BIT(sc, RX_DMA_DCAD_REG(rx->rx_q), 2948 RX_DMA_DCAD_CPUID, 0); 2949 AQ_WRITE_REG_BIT(sc, RX_DMA_DCAD_REG(rx->rx_q), 2950 RX_DMA_DCAD_DESC_EN, 0); 2951 AQ_WRITE_REG_BIT(sc, RX_DMA_DCAD_REG(rx->rx_q), 2952 RX_DMA_DCAD_HEADER_EN, 0); 2953 AQ_WRITE_REG_BIT(sc, RX_DMA_DCAD_REG(rx->rx_q), 2954 RX_DMA_DCAD_PAYLOAD_EN, 0); 2955 2956 AQ_WRITE_REG_BIT(sc, RX_DMA_DESC_REG(rx->rx_q), RX_DMA_DESC_EN, 1); 2957 } 2958 2959 static inline unsigned int 2960 aq_rx_fill_slots(struct aq_softc *sc, struct aq_rxring *rx, uint nslots) 2961 { 2962 struct aq_rx_desc_read *ring, *rd; 2963 struct aq_slot *as; 2964 struct mbuf *m; 2965 uint p, fills; 2966 2967 ring = AQ_DMA_KVA(&rx->rx_mem); 2968 p = rx->rx_prod; 2969 2970 bus_dmamap_sync(sc->sc_dmat, AQ_DMA_MAP(&rx->rx_mem), 0, 2971 AQ_DMA_LEN(&rx->rx_mem), BUS_DMASYNC_POSTWRITE); 2972 2973 for (fills = 0; fills < nslots; fills++) { 2974 as = &rx->rx_slots[p]; 2975 rd = &ring[p]; 2976 2977 m = MCLGETL(NULL, M_DONTWAIT, MCLBYTES + ETHER_ALIGN); 2978 if (m == NULL) 2979 break; 2980 2981 m->m_data += (m->m_ext.ext_size - (MCLBYTES + ETHER_ALIGN)); 2982 m->m_data += ETHER_ALIGN; 2983 m->m_len = m->m_pkthdr.len = MCLBYTES; 2984 2985 if (bus_dmamap_load_mbuf(sc->sc_dmat, as->as_map, m, 2986 BUS_DMA_NOWAIT) != 0) { 2987 m_freem(m); 2988 break; 2989 } 2990 as->as_m = m; 2991 2992 bus_dmamap_sync(sc->sc_dmat, as->as_map, 0, 2993 as->as_map->dm_mapsize, BUS_DMASYNC_PREREAD); 2994 htolem64(&rd->buf_addr, as->as_map->dm_segs[0].ds_addr); 2995 rd->hdr_addr = 0; 2996 p++; 2997 if (p == AQ_RXD_NUM) 2998 p = 0; 2999 } 3000 3001 bus_dmamap_sync(sc->sc_dmat, AQ_DMA_MAP(&rx->rx_mem), 0, 3002 AQ_DMA_LEN(&rx->rx_mem), BUS_DMASYNC_PREWRITE); 3003 3004 rx->rx_prod = p; 3005 AQ_WRITE_REG(sc, RX_DMA_DESC_TAIL_PTR_REG(rx->rx_q), rx->rx_prod); 3006 return (nslots - fills); 3007 } 3008 3009 int 3010 aq_rx_fill(struct aq_softc *sc, struct aq_rxring *rx) 3011 { 3012 u_int slots; 3013 3014 slots = if_rxr_get(&rx->rx_rxr, AQ_RXD_NUM); 3015 if (slots == 0) 3016 return 1; 3017 3018 slots = aq_rx_fill_slots(sc, rx, slots); 3019 if_rxr_put(&rx->rx_rxr, slots); 3020 return 0; 3021 } 3022 3023 void 3024 aq_refill(void *xq) 3025 { 3026 struct aq_queues *q = xq; 3027 struct aq_softc *sc = q->q_sc; 3028 3029 aq_rx_fill(sc, &q->q_rx); 3030 3031 if (if_rxr_inuse(&q->q_rx.rx_rxr) == 0) 3032 timeout_add(&q->q_rx.rx_refill, 1); 3033 } 3034 3035 void 3036 aq_rxeof(struct aq_softc *sc, struct aq_rxring *rx) 3037 { 3038 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 3039 struct aq_rx_desc_wb *rxd; 3040 struct aq_rx_desc_wb *ring; 3041 struct aq_slot *as; 3042 uint32_t end, idx; 3043 uint16_t pktlen, status; 3044 uint32_t rxd_type; 3045 struct mbuf *m, *mb; 3046 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 3047 int rxfree; 3048 3049 if (!ISSET(ifp->if_flags, IFF_RUNNING)) 3050 return; 3051 3052 end = AQ_READ_REG(sc, RX_DMA_DESC_HEAD_PTR_REG(rx->rx_q)) & 3053 RX_DMA_DESC_HEAD_PTR; 3054 3055 bus_dmamap_sync(sc->sc_dmat, AQ_DMA_MAP(&rx->rx_mem), 0, 3056 AQ_DMA_LEN(&rx->rx_mem), BUS_DMASYNC_POSTREAD); 3057 3058 rxfree = 0; 3059 idx = rx->rx_cons; 3060 ring = AQ_DMA_KVA(&rx->rx_mem); 3061 while (idx != end) { 3062 rxd = &ring[idx]; 3063 as = &rx->rx_slots[idx]; 3064 3065 bus_dmamap_sync(sc->sc_dmat, as->as_map, 0, 3066 as->as_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 3067 bus_dmamap_unload(sc->sc_dmat, as->as_map); 3068 3069 status = lemtoh16(&rxd->status); 3070 if ((status & AQ_RXDESC_STATUS_DD) == 0) 3071 break; 3072 3073 rxfree++; 3074 mb = as->as_m; 3075 as->as_m = NULL; 3076 3077 pktlen = lemtoh16(&rxd->pkt_len); 3078 rxd_type = lemtoh32(&rxd->type); 3079 if ((rxd_type & AQ_RXDESC_TYPE_RSSTYPE) != 0) { 3080 mb->m_pkthdr.ph_flowid = lemtoh32(&rxd->rss_hash); 3081 mb->m_pkthdr.csum_flags |= M_FLOWID; 3082 } 3083 3084 mb->m_pkthdr.len = 0; 3085 mb->m_next = NULL; 3086 *rx->rx_m_tail = mb; 3087 rx->rx_m_tail = &mb->m_next; 3088 3089 m = rx->rx_m_head; 3090 3091 #if NVLAN > 0 3092 if (rxd_type & (AQ_RXDESC_TYPE_VLAN | AQ_RXDESC_TYPE_VLAN2)) { 3093 m->m_pkthdr.ether_vtag = lemtoh16(&rxd->vlan); 3094 m->m_flags |= M_VLANTAG; 3095 } 3096 #endif 3097 3098 if ((rxd_type & AQ_RXDESC_TYPE_V4_SUM) && 3099 ((status & AQ_RXDESC_STATUS_V4_SUM_NG) == 0)) 3100 m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK; 3101 3102 if ((rxd_type & AQ_RXDESC_TYPE_L4_SUM) && 3103 (status & AQ_RXDESC_STATUS_L4_SUM_OK)) 3104 m->m_pkthdr.csum_flags |= M_UDP_CSUM_IN_OK | 3105 M_TCP_CSUM_IN_OK; 3106 3107 if ((status & AQ_RXDESC_STATUS_MACERR) || 3108 (rxd_type & AQ_RXDESC_TYPE_DMA_ERR)) { 3109 printf("%s:rx: rx error (status %x type %x)\n", 3110 DEVNAME(sc), status, rxd_type); 3111 rx->rx_m_error = 1; 3112 } 3113 3114 if (status & AQ_RXDESC_STATUS_EOP) { 3115 mb->m_len = pktlen - m->m_pkthdr.len; 3116 m->m_pkthdr.len = pktlen; 3117 if (rx->rx_m_error != 0) { 3118 ifp->if_ierrors++; 3119 m_freem(m); 3120 } else { 3121 ml_enqueue(&ml, m); 3122 } 3123 3124 rx->rx_m_head = NULL; 3125 rx->rx_m_tail = &rx->rx_m_head; 3126 rx->rx_m_error = 0; 3127 } else { 3128 mb->m_len = MCLBYTES; 3129 m->m_pkthdr.len += mb->m_len; 3130 } 3131 3132 idx++; 3133 if (idx == AQ_RXD_NUM) 3134 idx = 0; 3135 } 3136 3137 bus_dmamap_sync(sc->sc_dmat, AQ_DMA_MAP(&rx->rx_mem), 0, 3138 AQ_DMA_LEN(&rx->rx_mem), BUS_DMASYNC_PREREAD); 3139 3140 rx->rx_cons = idx; 3141 3142 if (rxfree > 0) { 3143 if_rxr_put(&rx->rx_rxr, rxfree); 3144 if (ifiq_input(rx->rx_ifiq, &ml)) 3145 if_rxr_livelocked(&rx->rx_rxr); 3146 3147 aq_rx_fill(sc, rx); 3148 if (if_rxr_inuse(&rx->rx_rxr) == 0) 3149 timeout_add(&rx->rx_refill, 1); 3150 } 3151 } 3152 3153 void 3154 aq_txeof(struct aq_softc *sc, struct aq_txring *tx) 3155 { 3156 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 3157 struct aq_slot *as; 3158 uint32_t idx, end, free; 3159 3160 if (!ISSET(ifp->if_flags, IFF_RUNNING)) 3161 return; 3162 3163 idx = tx->tx_cons; 3164 end = AQ_READ_REG(sc, TX_DMA_DESC_HEAD_PTR_REG(tx->tx_q)) & 3165 TX_DMA_DESC_HEAD_PTR; 3166 free = 0; 3167 3168 bus_dmamap_sync(sc->sc_dmat, AQ_DMA_MAP(&tx->tx_mem), 0, 3169 AQ_DMA_LEN(&tx->tx_mem), BUS_DMASYNC_POSTREAD); 3170 3171 while (idx != end) { 3172 as = &tx->tx_slots[idx]; 3173 3174 if (as->as_m != NULL) { 3175 bus_dmamap_sync(sc->sc_dmat, as->as_map, 0, 3176 as->as_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 3177 bus_dmamap_unload(sc->sc_dmat, as->as_map); 3178 3179 m_freem(as->as_m); 3180 as->as_m = NULL; 3181 } 3182 3183 idx++; 3184 if (idx == AQ_TXD_NUM) 3185 idx = 0; 3186 free++; 3187 } 3188 3189 bus_dmamap_sync(sc->sc_dmat, AQ_DMA_MAP(&tx->tx_mem), 0, 3190 AQ_DMA_LEN(&tx->tx_mem), BUS_DMASYNC_PREREAD); 3191 3192 tx->tx_cons = idx; 3193 3194 if (free != 0) { 3195 if (ifq_is_oactive(tx->tx_ifq)) 3196 ifq_restart(tx->tx_ifq); 3197 } 3198 } 3199 3200 void 3201 aq_start(struct ifqueue *ifq) 3202 { 3203 struct aq_queues *aq = ifq->ifq_softc; 3204 struct aq_softc *sc = aq->q_sc; 3205 struct aq_txring *tx = &aq->q_tx; 3206 struct aq_tx_desc *ring, *txd; 3207 struct aq_slot *as; 3208 struct mbuf *m; 3209 uint32_t idx, free, used, ctl1, ctl2; 3210 int error, i; 3211 3212 idx = tx->tx_prod; 3213 free = tx->tx_cons + AQ_TXD_NUM - tx->tx_prod; 3214 used = 0; 3215 3216 bus_dmamap_sync(sc->sc_dmat, AQ_DMA_MAP(&tx->tx_mem), 0, 3217 AQ_DMA_LEN(&tx->tx_mem), BUS_DMASYNC_POSTWRITE); 3218 ring = (struct aq_tx_desc *)AQ_DMA_KVA(&tx->tx_mem); 3219 3220 for (;;) { 3221 if (used + AQ_TX_MAX_SEGMENTS + 1 >= free) { 3222 ifq_set_oactive(ifq); 3223 break; 3224 } 3225 3226 m = ifq_dequeue(ifq); 3227 if (m == NULL) 3228 break; 3229 3230 as = &tx->tx_slots[idx]; 3231 3232 error = bus_dmamap_load_mbuf(sc->sc_dmat, as->as_map, m, 3233 BUS_DMA_STREAMING | BUS_DMA_NOWAIT); 3234 if (error == EFBIG) { 3235 if (m_defrag(m, M_DONTWAIT)) { 3236 m_freem(m); 3237 break; 3238 } 3239 3240 error = bus_dmamap_load_mbuf(sc->sc_dmat, as->as_map, 3241 m, BUS_DMA_STREAMING | BUS_DMA_NOWAIT); 3242 } 3243 if (error != 0) { 3244 m_freem(m); 3245 break; 3246 } 3247 3248 as->as_m = m; 3249 3250 #if NBPFILTER > 0 3251 if (ifq->ifq_if->if_bpf) 3252 bpf_mtap_ether(ifq->ifq_if->if_bpf, m, BPF_DIRECTION_OUT); 3253 #endif 3254 bus_dmamap_sync(sc->sc_dmat, as->as_map, 0, 3255 as->as_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 3256 3257 ctl2 = m->m_pkthdr.len << AQ_TXDESC_CTL2_LEN_SHIFT; 3258 ctl1 = AQ_TXDESC_CTL1_TYPE_TXD | AQ_TXDESC_CTL1_CMD_FCS; 3259 #if NVLAN > 0 3260 if (m->m_flags & M_VLANTAG) { 3261 txd = ring + idx; 3262 txd->buf_addr = 0; 3263 txd->ctl1 = htole32(AQ_TXDESC_CTL1_TYPE_TXC | 3264 (m->m_pkthdr.ether_vtag << AQ_TXDESC_CTL1_VLAN_SHIFT)); 3265 txd->ctl2 = 0; 3266 3267 ctl1 |= AQ_TXDESC_CTL1_CMD_VLAN; 3268 ctl2 |= AQ_TXDESC_CTL2_CTX_EN; 3269 3270 idx++; 3271 if (idx == AQ_TXD_NUM) 3272 idx = 0; 3273 used++; 3274 } 3275 #endif 3276 3277 if (m->m_pkthdr.csum_flags & M_IPV4_CSUM_OUT) 3278 ctl1 |= AQ_TXDESC_CTL1_CMD_IP4CSUM; 3279 if (m->m_pkthdr.csum_flags & (M_TCP_CSUM_OUT | M_UDP_CSUM_OUT)) 3280 ctl1 |= AQ_TXDESC_CTL1_CMD_L4CSUM; 3281 3282 for (i = 0; i < as->as_map->dm_nsegs; i++) { 3283 3284 if (i == as->as_map->dm_nsegs - 1) 3285 ctl1 |= AQ_TXDESC_CTL1_CMD_EOP | 3286 AQ_TXDESC_CTL1_CMD_WB; 3287 3288 txd = ring + idx; 3289 txd->buf_addr = htole64(as->as_map->dm_segs[i].ds_addr); 3290 txd->ctl1 = htole32(ctl1 | 3291 (as->as_map->dm_segs[i].ds_len << 3292 AQ_TXDESC_CTL1_BLEN_SHIFT)); 3293 txd->ctl2 = htole32(ctl2); 3294 3295 idx++; 3296 if (idx == AQ_TXD_NUM) 3297 idx = 0; 3298 used++; 3299 } 3300 } 3301 3302 bus_dmamap_sync(sc->sc_dmat, AQ_DMA_MAP(&tx->tx_mem), 0, 3303 AQ_DMA_LEN(&tx->tx_mem), BUS_DMASYNC_PREWRITE); 3304 3305 if (used != 0) { 3306 tx->tx_prod = idx; 3307 AQ_WRITE_REG(sc, TX_DMA_DESC_TAIL_PTR_REG(tx->tx_q), 3308 tx->tx_prod); 3309 } 3310 } 3311 3312 int 3313 aq_intr_queue(void *arg) 3314 { 3315 struct aq_queues *aq = arg; 3316 struct aq_softc *sc = aq->q_sc; 3317 uint32_t status; 3318 uint32_t clear; 3319 3320 status = AQ_READ_REG(sc, AQ_INTR_STATUS_REG); 3321 clear = 0; 3322 if (status & (1 << aq->q_tx.tx_irq)) { 3323 clear |= (1 << aq->q_tx.tx_irq); 3324 aq_txeof(sc, &aq->q_tx); 3325 } 3326 3327 if (status & (1 << aq->q_rx.rx_irq)) { 3328 clear |= (1 << aq->q_rx.rx_irq); 3329 aq_rxeof(sc, &aq->q_rx); 3330 } 3331 3332 AQ_WRITE_REG(sc, AQ_INTR_STATUS_CLR_REG, clear); 3333 return (clear != 0); 3334 } 3335 3336 int 3337 aq_intr_link(void *arg) 3338 { 3339 struct aq_softc *sc = arg; 3340 uint32_t status; 3341 3342 status = AQ_READ_REG(sc, AQ_INTR_STATUS_REG); 3343 if (status & (1 << sc->sc_linkstat_irq)) { 3344 aq_update_link_status(sc); 3345 AQ_WRITE_REG(sc, AQ_INTR_STATUS_REG, (1 << sc->sc_linkstat_irq)); 3346 return 1; 3347 } 3348 3349 return 0; 3350 } 3351 3352 int 3353 aq_intr(void *arg) 3354 { 3355 struct aq_softc *sc = arg; 3356 struct aq_queues *aq = &sc->sc_queues[0]; 3357 uint32_t status; 3358 3359 status = AQ_READ_REG(sc, AQ_INTR_STATUS_REG); 3360 AQ_WRITE_REG(sc, AQ_INTR_STATUS_CLR_REG, 0xffffffff); 3361 3362 if (status & (1 << sc->sc_linkstat_irq)) 3363 aq_update_link_status(sc); 3364 3365 if (status & (1 << aq->q_tx.tx_irq)) { 3366 aq_txeof(sc, &aq->q_tx); 3367 AQ_WRITE_REG(sc, AQ_INTR_STATUS_CLR_REG, 3368 (1 << aq->q_tx.tx_irq)); 3369 } 3370 if (status & (1 << aq->q_rx.rx_irq)) { 3371 aq_rxeof(sc, &aq->q_rx); 3372 AQ_WRITE_REG(sc, AQ_INTR_STATUS_CLR_REG, 3373 (1 << aq->q_rx.rx_irq)); 3374 } 3375 3376 return 1; 3377 } 3378 3379 void 3380 aq_watchdog(struct ifnet *ifp) 3381 { 3382 3383 } 3384 3385 void 3386 aq_free_slots(struct aq_softc *sc, struct aq_slot *slots, int allocated, 3387 int total) 3388 { 3389 struct aq_slot *as; 3390 3391 int i = allocated; 3392 while (i-- > 0) { 3393 as = &slots[i]; 3394 bus_dmamap_destroy(sc->sc_dmat, as->as_map); 3395 if (as->as_m != NULL) 3396 m_freem(as->as_m); 3397 } 3398 free(slots, M_DEVBUF, total * sizeof(*as)); 3399 } 3400 3401 int 3402 aq_queue_up(struct aq_softc *sc, struct aq_queues *aq) 3403 { 3404 struct aq_rxring *rx; 3405 struct aq_txring *tx; 3406 struct aq_slot *as; 3407 int i, mtu; 3408 3409 rx = &aq->q_rx; 3410 rx->rx_slots = mallocarray(sizeof(*as), AQ_RXD_NUM, M_DEVBUF, 3411 M_WAITOK | M_ZERO); 3412 if (rx->rx_slots == NULL) { 3413 printf("%s: failed to allocate rx slots %d\n", DEVNAME(sc), 3414 aq->q_index); 3415 return ENOMEM; 3416 } 3417 3418 for (i = 0; i < AQ_RXD_NUM; i++) { 3419 as = &rx->rx_slots[i]; 3420 if (bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 3421 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW | BUS_DMA_64BIT, 3422 &as->as_map) != 0) { 3423 printf("%s: failed to allocate rx dma maps %d\n", 3424 DEVNAME(sc), aq->q_index); 3425 goto destroy_rx_slots; 3426 } 3427 } 3428 3429 if (aq_dmamem_alloc(sc, &rx->rx_mem, AQ_RXD_NUM * 3430 sizeof(struct aq_rx_desc_read), PAGE_SIZE) != 0) { 3431 printf("%s: unable to allocate rx ring %d\n", DEVNAME(sc), 3432 aq->q_index); 3433 goto destroy_rx_slots; 3434 } 3435 3436 tx = &aq->q_tx; 3437 tx->tx_slots = mallocarray(sizeof(*as), AQ_TXD_NUM, M_DEVBUF, 3438 M_WAITOK | M_ZERO); 3439 if (tx->tx_slots == NULL) { 3440 printf("%s: failed to allocate tx slots %d\n", DEVNAME(sc), 3441 aq->q_index); 3442 goto destroy_rx_ring; 3443 } 3444 3445 mtu = sc->sc_arpcom.ac_if.if_hardmtu; 3446 for (i = 0; i < AQ_TXD_NUM; i++) { 3447 as = &tx->tx_slots[i]; 3448 if (bus_dmamap_create(sc->sc_dmat, mtu, AQ_TX_MAX_SEGMENTS, 3449 MCLBYTES, 0, BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW | BUS_DMA_64BIT, 3450 &as->as_map) != 0) { 3451 printf("%s: failed to allocated tx dma maps %d\n", 3452 DEVNAME(sc), aq->q_index); 3453 goto destroy_tx_slots; 3454 } 3455 } 3456 3457 if (aq_dmamem_alloc(sc, &tx->tx_mem, AQ_TXD_NUM * 3458 sizeof(struct aq_tx_desc), PAGE_SIZE) != 0) { 3459 printf("%s: unable to allocate tx ring %d\n", DEVNAME(sc), 3460 aq->q_index); 3461 goto destroy_tx_slots; 3462 } 3463 3464 bus_dmamap_sync(sc->sc_dmat, AQ_DMA_MAP(&tx->tx_mem), 3465 0, AQ_DMA_LEN(&tx->tx_mem), 3466 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3467 3468 bus_dmamap_sync(sc->sc_dmat, AQ_DMA_MAP(&rx->rx_mem), 3469 0, AQ_DMA_LEN(&rx->rx_mem), 3470 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3471 3472 aq_txring_reset(sc, tx, 1); 3473 aq_rxring_reset(sc, rx, 1); 3474 return 0; 3475 3476 destroy_tx_slots: 3477 aq_free_slots(sc, tx->tx_slots, i, AQ_TXD_NUM); 3478 tx->tx_slots = NULL; 3479 i = AQ_RXD_NUM; 3480 3481 destroy_rx_ring: 3482 aq_dmamem_free(sc, &rx->rx_mem); 3483 destroy_rx_slots: 3484 aq_free_slots(sc, rx->rx_slots, i, AQ_RXD_NUM); 3485 rx->rx_slots = NULL; 3486 return ENOMEM; 3487 } 3488 3489 void 3490 aq_queue_down(struct aq_softc *sc, struct aq_queues *aq) 3491 { 3492 struct aq_txring *tx; 3493 struct aq_rxring *rx; 3494 3495 tx = &aq->q_tx; 3496 aq_txring_reset(sc, &aq->q_tx, 0); 3497 if (tx->tx_slots != NULL) { 3498 aq_free_slots(sc, tx->tx_slots, AQ_TXD_NUM, AQ_TXD_NUM); 3499 tx->tx_slots = NULL; 3500 } 3501 3502 bus_dmamap_sync(sc->sc_dmat, AQ_DMA_MAP(&tx->tx_mem), 3503 0, AQ_DMA_LEN(&tx->tx_mem), 3504 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3505 3506 aq_dmamem_free(sc, &tx->tx_mem); 3507 3508 rx = &aq->q_rx; 3509 m_freem(rx->rx_m_head); 3510 rx->rx_m_head = NULL; 3511 rx->rx_m_tail = &rx->rx_m_head; 3512 rx->rx_m_error = 0; 3513 aq_rxring_reset(sc, &aq->q_rx, 0); 3514 if (rx->rx_slots != NULL) { 3515 aq_free_slots(sc, rx->rx_slots, AQ_RXD_NUM, AQ_RXD_NUM); 3516 rx->rx_slots = NULL; 3517 } 3518 3519 bus_dmamap_sync(sc->sc_dmat, AQ_DMA_MAP(&rx->rx_mem), 3520 0, AQ_DMA_LEN(&rx->rx_mem), 3521 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3522 3523 aq_dmamem_free(sc, &rx->rx_mem); 3524 } 3525 3526 void 3527 aq_invalidate_rx_desc_cache(struct aq_softc *sc) 3528 { 3529 uint32_t cache; 3530 3531 cache = AQ_READ_REG(sc, RX_DMA_DESC_CACHE_INIT_REG); 3532 AQ_WRITE_REG_BIT(sc, RX_DMA_DESC_CACHE_INIT_REG, RX_DMA_DESC_CACHE_INIT, 3533 (cache & RX_DMA_DESC_CACHE_INIT) ^ RX_DMA_DESC_CACHE_INIT); 3534 } 3535 3536 int 3537 aq_up(struct aq_softc *sc) 3538 { 3539 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 3540 int i; 3541 3542 aq_invalidate_rx_desc_cache(sc); 3543 3544 for (i = 0; i < sc->sc_nqueues; i++) { 3545 if (aq_queue_up(sc, &sc->sc_queues[i]) != 0) 3546 goto downqueues; 3547 } 3548 3549 aq_set_mac_addr(sc, AQ_HW_MAC_OWN, sc->sc_arpcom.ac_enaddr); 3550 3551 AQ_WRITE_REG_BIT(sc, TPO_HWCSUM_REG, TPO_HWCSUM_IP4CSUM_EN, 1); 3552 AQ_WRITE_REG_BIT(sc, TPO_HWCSUM_REG, TPO_HWCSUM_L4CSUM_EN, 1); 3553 3554 AQ_WRITE_REG_BIT(sc, RPO_HWCSUM_REG, RPO_HWCSUM_IP4CSUM_EN, 1); 3555 AQ_WRITE_REG_BIT(sc, RPO_HWCSUM_REG, RPO_HWCSUM_L4CSUM_EN, 1); 3556 3557 SET(ifp->if_flags, IFF_RUNNING); 3558 aq_enable_intr(sc, 1, 1); 3559 AQ_WRITE_REG_BIT(sc, TPB_TX_BUF_REG, TPB_TX_BUF_EN, 1); 3560 AQ_WRITE_REG_BIT(sc, RPB_RPF_RX_REG, RPB_RPF_RX_BUF_EN, 1); 3561 3562 for (i = 0; i < sc->sc_nqueues; i++) { 3563 struct aq_queues *aq = &sc->sc_queues[i]; 3564 3565 if_rxr_init(&aq->q_rx.rx_rxr, howmany(ifp->if_hardmtu, MCLBYTES), 3566 AQ_RXD_NUM - 1); 3567 aq_rx_fill(sc, &aq->q_rx); 3568 3569 ifq_clr_oactive(aq->q_tx.tx_ifq); 3570 } 3571 3572 return ENETRESET; 3573 3574 downqueues: 3575 for (i = 0; i < sc->sc_nqueues; i++) 3576 aq_queue_down(sc, &sc->sc_queues[i]); 3577 return ENOMEM; 3578 } 3579 3580 void 3581 aq_down(struct aq_softc *sc) 3582 { 3583 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 3584 int i; 3585 3586 CLR(ifp->if_flags, IFF_RUNNING); 3587 3588 aq_enable_intr(sc, 1, 0); 3589 intr_barrier(sc->sc_ih); 3590 3591 AQ_WRITE_REG_BIT(sc, RPB_RPF_RX_REG, RPB_RPF_RX_BUF_EN, 0); 3592 for (i = 0; i < sc->sc_nqueues; i++) { 3593 /* queue intr barrier? */ 3594 aq_queue_down(sc, &sc->sc_queues[i]); 3595 } 3596 3597 aq_invalidate_rx_desc_cache(sc); 3598 } 3599 3600 void 3601 aq_enable_intr(struct aq_softc *sc, int link, int txrx) 3602 { 3603 uint32_t imask = 0; 3604 int i; 3605 3606 if (txrx) { 3607 for (i = 0; i < sc->sc_nqueues; i++) { 3608 imask |= (1 << sc->sc_queues[i].q_tx.tx_irq); 3609 imask |= (1 << sc->sc_queues[i].q_rx.rx_irq); 3610 } 3611 } 3612 3613 if (link) 3614 imask |= (1 << sc->sc_linkstat_irq); 3615 3616 AQ_WRITE_REG(sc, AQ_INTR_MASK_REG, imask); 3617 AQ_WRITE_REG(sc, AQ_INTR_STATUS_CLR_REG, 0xffffffff); 3618 } 3619 3620 void 3621 aq_ifmedia_status(struct ifnet *ifp, struct ifmediareq *ifmr) 3622 { 3623 struct aq_softc *aq = ifp->if_softc; 3624 enum aq_link_speed speed; 3625 enum aq_link_fc fc; 3626 int media; 3627 int flow; 3628 3629 if (aq_get_linkmode(aq, &speed, &fc, NULL) != 0) 3630 return; 3631 3632 switch (speed) { 3633 case AQ_LINK_10G: 3634 media = IFM_10G_T; 3635 break; 3636 case AQ_LINK_5G: 3637 media = IFM_5000_T; 3638 break; 3639 case AQ_LINK_2G5: 3640 media = IFM_2500_T; 3641 break; 3642 case AQ_LINK_1G: 3643 media = IFM_1000_T; 3644 break; 3645 case AQ_LINK_100M: 3646 media = IFM_100_TX; 3647 break; 3648 case AQ_LINK_10M: 3649 media = IFM_10_T; 3650 break; 3651 case AQ_LINK_NONE: 3652 media = 0; 3653 break; 3654 } 3655 3656 flow = 0; 3657 if (fc & AQ_FC_RX) 3658 flow |= IFM_ETH_RXPAUSE; 3659 if (fc & AQ_FC_TX) 3660 flow |= IFM_ETH_TXPAUSE; 3661 3662 ifmr->ifm_status = IFM_AVALID; 3663 if (speed != AQ_LINK_NONE) { 3664 ifmr->ifm_status |= IFM_ACTIVE; 3665 ifmr->ifm_active = IFM_ETHER | IFM_AUTO | media | flow; 3666 } 3667 } 3668 3669 int 3670 aq_ifmedia_change(struct ifnet *ifp) 3671 { 3672 struct aq_softc *sc = ifp->if_softc; 3673 enum aq_link_speed rate = AQ_LINK_NONE; 3674 enum aq_link_fc fc = AQ_FC_NONE; 3675 3676 if (IFM_TYPE(sc->sc_media.ifm_media) != IFM_ETHER) 3677 return EINVAL; 3678 3679 switch (IFM_SUBTYPE(sc->sc_media.ifm_media)) { 3680 case IFM_AUTO: 3681 rate = AQ_LINK_AUTO; 3682 break; 3683 case IFM_NONE: 3684 rate = AQ_LINK_NONE; 3685 break; 3686 case IFM_10_T: 3687 rate = AQ_LINK_10M; 3688 break; 3689 case IFM_100_TX: 3690 rate = AQ_LINK_100M; 3691 break; 3692 case IFM_1000_T: 3693 rate = AQ_LINK_1G; 3694 break; 3695 case IFM_2500_T: 3696 rate = AQ_LINK_2G5; 3697 break; 3698 case IFM_5000_T: 3699 rate = AQ_LINK_5G; 3700 break; 3701 case IFM_10G_T: 3702 rate = AQ_LINK_10G; 3703 break; 3704 default: 3705 return ENODEV; 3706 } 3707 3708 if (sc->sc_media.ifm_media & IFM_FLOW) 3709 fc = AQ_FC_ALL; 3710 3711 return aq_set_linkmode(sc, rate, fc, AQ_EEE_DISABLE); 3712 } 3713 3714 void 3715 aq_update_link_status(struct aq_softc *sc) 3716 { 3717 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 3718 enum aq_link_speed speed; 3719 enum aq_link_fc fc; 3720 3721 if (aq_get_linkmode(sc, &speed, &fc, NULL) != 0) 3722 return; 3723 3724 if (speed == AQ_LINK_NONE) { 3725 if (ifp->if_link_state != LINK_STATE_DOWN) { 3726 ifp->if_link_state = LINK_STATE_DOWN; 3727 if_link_state_change(ifp); 3728 } 3729 } else { 3730 if (ifp->if_link_state != LINK_STATE_FULL_DUPLEX) { 3731 ifp->if_link_state = LINK_STATE_FULL_DUPLEX; 3732 if_link_state_change(ifp); 3733 } 3734 } 3735 } 3736 3737 int 3738 aq_rxrinfo(struct aq_softc *sc, struct if_rxrinfo *ifri) 3739 { 3740 struct if_rxring_info *ifr; 3741 int i; 3742 int error; 3743 3744 ifr = mallocarray(sc->sc_nqueues, sizeof(*ifr), M_TEMP, 3745 M_WAITOK | M_ZERO | M_CANFAIL); 3746 if (ifr == NULL) 3747 return (ENOMEM); 3748 3749 for (i = 0; i < sc->sc_nqueues; i++) { 3750 ifr[i].ifr_size = MCLBYTES; 3751 ifr[i].ifr_info = sc->sc_queues[i].q_rx.rx_rxr; 3752 } 3753 3754 error = if_rxr_info_ioctl(ifri, sc->sc_nqueues, ifr); 3755 free(ifr, M_TEMP, sc->sc_nqueues * sizeof(*ifr)); 3756 3757 return (error); 3758 } 3759 3760 int 3761 aq_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 3762 { 3763 struct aq_softc *sc = ifp->if_softc; 3764 struct ifreq *ifr = (struct ifreq *)data; 3765 int error = 0, s; 3766 3767 s = splnet(); 3768 3769 switch (cmd) { 3770 case SIOCSIFADDR: 3771 ifp->if_flags |= IFF_UP; 3772 if ((ifp->if_flags & IFF_RUNNING) == 0) 3773 error = aq_up(sc); 3774 break; 3775 case SIOCSIFFLAGS: 3776 if (ifp->if_flags & IFF_UP) { 3777 if (ifp->if_flags & IFF_RUNNING) 3778 error = ENETRESET; 3779 else 3780 error = aq_up(sc); 3781 } else { 3782 if (ifp->if_flags & IFF_RUNNING) 3783 aq_down(sc); 3784 } 3785 break; 3786 case SIOCSIFMEDIA: 3787 case SIOCGIFMEDIA: 3788 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 3789 break; 3790 3791 case SIOCGIFRXR: 3792 error = aq_rxrinfo(sc, (struct if_rxrinfo *)ifr->ifr_data); 3793 break; 3794 3795 default: 3796 error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data); 3797 } 3798 3799 if (error == ENETRESET) { 3800 if (ifp->if_flags & IFF_RUNNING) 3801 aq_iff(sc); 3802 error = 0; 3803 } 3804 3805 splx(s); 3806 return error; 3807 } 3808 3809 int 3810 aq2_filter_art_set(struct aq_softc *sc, uint32_t idx, 3811 uint32_t tag, uint32_t mask, uint32_t action) 3812 { 3813 int error; 3814 3815 AQ_MPI_LOCK(sc); 3816 3817 WAIT_FOR(AQ_READ_REG(sc, AQ2_ART_SEM_REG) == 1, 10, 1000, &error); 3818 if (error != 0) { 3819 printf("%s: AQ2_ART_SEM_REG timeout\n", DEVNAME(sc)); 3820 goto out; 3821 } 3822 3823 idx += sc->sc_art_filter_base_index; 3824 AQ_WRITE_REG(sc, AQ2_RPF_ACT_ART_REQ_TAG_REG(idx), tag); 3825 AQ_WRITE_REG(sc, AQ2_RPF_ACT_ART_REQ_MASK_REG(idx), mask); 3826 AQ_WRITE_REG(sc, AQ2_RPF_ACT_ART_REQ_ACTION_REG(idx), action); 3827 3828 AQ_WRITE_REG(sc, AQ2_ART_SEM_REG, 1); 3829 3830 out: 3831 AQ_MPI_UNLOCK(sc); 3832 return error; 3833 } 3834 3835 void 3836 aq_iff(struct aq_softc *sc) 3837 { 3838 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 3839 struct arpcom *ac = &sc->sc_arpcom; 3840 struct ether_multi *enm; 3841 struct ether_multistep step; 3842 uint32_t action; 3843 int idx; 3844 3845 if (HWTYPE_AQ2_P(sc)) { 3846 action = (ifp->if_flags & IFF_PROMISC) ? 3847 AQ2_ART_ACTION_DISABLE : AQ2_ART_ACTION_DROP; 3848 aq2_filter_art_set(sc, AQ2_RPF_INDEX_L2_PROMISC_OFF, 0, 3849 AQ2_RPF_TAG_UC_MASK | AQ2_RPF_TAG_ALLMC_MASK, action); 3850 aq2_filter_art_set(sc, AQ2_RPF_INDEX_VLAN_PROMISC_OFF, 0, 3851 AQ2_RPF_TAG_VLAN_MASK | AQ2_RPF_TAG_UNTAG_MASK, action); 3852 } 3853 3854 if (ifp->if_flags & IFF_PROMISC) { 3855 ifp->if_flags |= IFF_ALLMULTI; 3856 AQ_WRITE_REG_BIT(sc, RPF_L2BC_REG, RPF_L2BC_PROMISC, 1); 3857 } else if (ac->ac_multirangecnt > 0 || 3858 ac->ac_multicnt >= AQ_HW_MAC_NUM) { 3859 ifp->if_flags |= IFF_ALLMULTI; 3860 AQ_WRITE_REG_BIT(sc, RPF_L2BC_REG, RPF_L2BC_PROMISC, 0); 3861 AQ_WRITE_REG_BIT(sc, RPF_MCAST_FILTER_MASK_REG, 3862 RPF_MCAST_FILTER_MASK_ALLMULTI, 1); 3863 AQ_WRITE_REG_BIT(sc, RPF_MCAST_FILTER_REG(0), 3864 RPF_MCAST_FILTER_EN, 1); 3865 } else { 3866 ifp->if_flags &= ~IFF_ALLMULTI; 3867 idx = AQ_HW_MAC_OWN + 1; 3868 3869 AQ_WRITE_REG_BIT(sc, RPF_L2BC_REG, RPF_L2BC_PROMISC, 0); 3870 3871 ETHER_FIRST_MULTI(step, ac, enm); 3872 while (enm != NULL) { 3873 aq_set_mac_addr(sc, idx++, enm->enm_addrlo); 3874 ETHER_NEXT_MULTI(step, enm); 3875 } 3876 3877 for (; idx < AQ_HW_MAC_NUM; idx++) 3878 aq_set_mac_addr(sc, idx, NULL); 3879 3880 AQ_WRITE_REG_BIT(sc, RPF_MCAST_FILTER_MASK_REG, 3881 RPF_MCAST_FILTER_MASK_ALLMULTI, 0); 3882 AQ_WRITE_REG_BIT(sc, RPF_MCAST_FILTER_REG(0), 3883 RPF_MCAST_FILTER_EN, 0); 3884 } 3885 } 3886 3887 int 3888 aq_dmamem_alloc(struct aq_softc *sc, struct aq_dmamem *aqm, 3889 bus_size_t size, u_int align) 3890 { 3891 aqm->aqm_size = size; 3892 3893 if (bus_dmamap_create(sc->sc_dmat, aqm->aqm_size, 1, 3894 aqm->aqm_size, 0, 3895 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW | BUS_DMA_64BIT, 3896 &aqm->aqm_map) != 0) 3897 return (1); 3898 if (bus_dmamem_alloc(sc->sc_dmat, aqm->aqm_size, 3899 align, 0, &aqm->aqm_seg, 1, &aqm->aqm_nsegs, 3900 BUS_DMA_WAITOK | BUS_DMA_ZERO) != 0) 3901 goto destroy; 3902 if (bus_dmamem_map(sc->sc_dmat, &aqm->aqm_seg, aqm->aqm_nsegs, 3903 aqm->aqm_size, &aqm->aqm_kva, 3904 BUS_DMA_WAITOK | BUS_DMA_COHERENT) != 0) 3905 goto free; 3906 if (bus_dmamap_load(sc->sc_dmat, aqm->aqm_map, aqm->aqm_kva, 3907 aqm->aqm_size, NULL, BUS_DMA_WAITOK) != 0) 3908 goto unmap; 3909 3910 return (0); 3911 unmap: 3912 bus_dmamem_unmap(sc->sc_dmat, aqm->aqm_kva, aqm->aqm_size); 3913 free: 3914 bus_dmamem_free(sc->sc_dmat, &aqm->aqm_seg, 1); 3915 destroy: 3916 bus_dmamap_destroy(sc->sc_dmat, aqm->aqm_map); 3917 return (1); 3918 } 3919 3920 void 3921 aq_dmamem_free(struct aq_softc *sc, struct aq_dmamem *aqm) 3922 { 3923 bus_dmamap_unload(sc->sc_dmat, aqm->aqm_map); 3924 bus_dmamem_unmap(sc->sc_dmat, aqm->aqm_kva, aqm->aqm_size); 3925 bus_dmamem_free(sc->sc_dmat, &aqm->aqm_seg, 1); 3926 bus_dmamap_destroy(sc->sc_dmat, aqm->aqm_map); 3927 } 3928