1 /* $OpenBSD: if_ale.c,v 1.20 2011/09/13 08:15:35 kevlo Exp $ */ 2 /*- 3 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: src/sys/dev/ale/if_ale.c,v 1.3 2008/12/03 09:01:12 yongari Exp $ 29 */ 30 31 /* Driver for Atheros AR8121/AR8113/AR8114 PCIe Ethernet. */ 32 33 #include "bpfilter.h" 34 #include "vlan.h" 35 36 #include <sys/param.h> 37 #include <sys/endian.h> 38 #include <sys/systm.h> 39 #include <sys/types.h> 40 #include <sys/sockio.h> 41 #include <sys/mbuf.h> 42 #include <sys/queue.h> 43 #include <sys/kernel.h> 44 #include <sys/device.h> 45 #include <sys/timeout.h> 46 #include <sys/socket.h> 47 48 #include <machine/bus.h> 49 50 #include <net/if.h> 51 #include <net/if_dl.h> 52 #include <net/if_llc.h> 53 #include <net/if_media.h> 54 55 #ifdef INET 56 #include <netinet/in.h> 57 #include <netinet/in_systm.h> 58 #include <netinet/in_var.h> 59 #include <netinet/ip.h> 60 #include <netinet/if_ether.h> 61 #endif 62 63 #include <net/if_types.h> 64 #include <net/if_vlan_var.h> 65 66 #if NBPFILTER > 0 67 #include <net/bpf.h> 68 #endif 69 70 #include <dev/rndvar.h> 71 72 #include <dev/mii/mii.h> 73 #include <dev/mii/miivar.h> 74 75 #include <dev/pci/pcireg.h> 76 #include <dev/pci/pcivar.h> 77 #include <dev/pci/pcidevs.h> 78 79 #include <dev/pci/if_alereg.h> 80 81 int ale_match(struct device *, void *, void *); 82 void ale_attach(struct device *, struct device *, void *); 83 int ale_detach(struct device *, int); 84 int ale_activate(struct device *, int); 85 86 int ale_miibus_readreg(struct device *, int, int); 87 void ale_miibus_writereg(struct device *, int, int, int); 88 void ale_miibus_statchg(struct device *); 89 90 int ale_init(struct ifnet *); 91 void ale_start(struct ifnet *); 92 int ale_ioctl(struct ifnet *, u_long, caddr_t); 93 void ale_watchdog(struct ifnet *); 94 int ale_mediachange(struct ifnet *); 95 void ale_mediastatus(struct ifnet *, struct ifmediareq *); 96 97 int ale_intr(void *); 98 int ale_rxeof(struct ale_softc *sc); 99 void ale_rx_update_page(struct ale_softc *, struct ale_rx_page **, 100 uint32_t, uint32_t *); 101 void ale_rxcsum(struct ale_softc *, struct mbuf *, uint32_t); 102 void ale_txeof(struct ale_softc *); 103 104 int ale_dma_alloc(struct ale_softc *); 105 void ale_dma_free(struct ale_softc *); 106 int ale_encap(struct ale_softc *, struct mbuf **); 107 void ale_init_rx_pages(struct ale_softc *); 108 void ale_init_tx_ring(struct ale_softc *); 109 110 void ale_stop(struct ale_softc *); 111 void ale_tick(void *); 112 void ale_get_macaddr(struct ale_softc *); 113 void ale_mac_config(struct ale_softc *); 114 void ale_phy_reset(struct ale_softc *); 115 void ale_reset(struct ale_softc *); 116 void ale_iff(struct ale_softc *); 117 void ale_rxvlan(struct ale_softc *); 118 void ale_stats_clear(struct ale_softc *); 119 void ale_stats_update(struct ale_softc *); 120 void ale_stop_mac(struct ale_softc *); 121 122 const struct pci_matchid ale_devices[] = { 123 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L1E } 124 }; 125 126 struct cfattach ale_ca = { 127 sizeof (struct ale_softc), ale_match, ale_attach, NULL, 128 ale_activate 129 }; 130 131 struct cfdriver ale_cd = { 132 NULL, "ale", DV_IFNET 133 }; 134 135 int aledebug = 0; 136 #define DPRINTF(x) do { if (aledebug) printf x; } while (0) 137 138 #define ALE_CSUM_FEATURES (M_TCP_CSUM_OUT | M_UDP_CSUM_OUT) 139 140 int 141 ale_miibus_readreg(struct device *dev, int phy, int reg) 142 { 143 struct ale_softc *sc = (struct ale_softc *)dev; 144 uint32_t v; 145 int i; 146 147 if (phy != sc->ale_phyaddr) 148 return (0); 149 150 if ((sc->ale_flags & ALE_FLAG_FASTETHER) != 0 && 151 reg == MII_EXTSR) 152 return (0); 153 154 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 155 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 156 for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 157 DELAY(5); 158 v = CSR_READ_4(sc, ALE_MDIO); 159 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 160 break; 161 } 162 163 if (i == 0) { 164 printf("%s: phy read timeout: phy %d, reg %d\n", 165 sc->sc_dev.dv_xname, phy, reg); 166 return (0); 167 } 168 169 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 170 } 171 172 void 173 ale_miibus_writereg(struct device *dev, int phy, int reg, int val) 174 { 175 struct ale_softc *sc = (struct ale_softc *)dev; 176 uint32_t v; 177 int i; 178 179 if (phy != sc->ale_phyaddr) 180 return; 181 182 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 183 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 184 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 185 for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 186 DELAY(5); 187 v = CSR_READ_4(sc, ALE_MDIO); 188 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 189 break; 190 } 191 192 if (i == 0) 193 printf("%s: phy write timeout: phy %d, reg %d\n", 194 sc->sc_dev.dv_xname, phy, reg); 195 } 196 197 void 198 ale_miibus_statchg(struct device *dev) 199 { 200 struct ale_softc *sc = (struct ale_softc *)dev; 201 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 202 struct mii_data *mii = &sc->sc_miibus; 203 uint32_t reg; 204 205 if ((ifp->if_flags & IFF_RUNNING) == 0) 206 return; 207 208 sc->ale_flags &= ~ALE_FLAG_LINK; 209 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 210 (IFM_ACTIVE | IFM_AVALID)) { 211 switch (IFM_SUBTYPE(mii->mii_media_active)) { 212 case IFM_10_T: 213 case IFM_100_TX: 214 sc->ale_flags |= ALE_FLAG_LINK; 215 break; 216 217 case IFM_1000_T: 218 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0) 219 sc->ale_flags |= ALE_FLAG_LINK; 220 break; 221 222 default: 223 break; 224 } 225 } 226 227 /* Stop Rx/Tx MACs. */ 228 ale_stop_mac(sc); 229 230 /* Program MACs with resolved speed/duplex/flow-control. */ 231 if ((sc->ale_flags & ALE_FLAG_LINK) != 0) { 232 ale_mac_config(sc); 233 /* Reenable Tx/Rx MACs. */ 234 reg = CSR_READ_4(sc, ALE_MAC_CFG); 235 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 236 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 237 } 238 } 239 240 void 241 ale_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 242 { 243 struct ale_softc *sc = ifp->if_softc; 244 struct mii_data *mii = &sc->sc_miibus; 245 246 mii_pollstat(mii); 247 ifmr->ifm_status = mii->mii_media_status; 248 ifmr->ifm_active = mii->mii_media_active; 249 } 250 251 int 252 ale_mediachange(struct ifnet *ifp) 253 { 254 struct ale_softc *sc = ifp->if_softc; 255 struct mii_data *mii = &sc->sc_miibus; 256 int error; 257 258 if (mii->mii_instance != 0) { 259 struct mii_softc *miisc; 260 261 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 262 mii_phy_reset(miisc); 263 } 264 error = mii_mediachg(mii); 265 266 return (error); 267 } 268 269 int 270 ale_match(struct device *dev, void *match, void *aux) 271 { 272 return pci_matchbyid((struct pci_attach_args *)aux, ale_devices, 273 sizeof (ale_devices) / sizeof (ale_devices[0])); 274 } 275 276 void 277 ale_get_macaddr(struct ale_softc *sc) 278 { 279 uint32_t ea[2], reg; 280 int i, vpdc; 281 282 reg = CSR_READ_4(sc, ALE_SPI_CTRL); 283 if ((reg & SPI_VPD_ENB) != 0) { 284 reg &= ~SPI_VPD_ENB; 285 CSR_WRITE_4(sc, ALE_SPI_CTRL, reg); 286 } 287 288 if (pci_get_capability(sc->sc_pct, sc->sc_pcitag, PCI_CAP_VPD, 289 &vpdc, NULL)) { 290 /* 291 * PCI VPD capability found, let TWSI reload EEPROM. 292 * This will set ethernet address of controller. 293 */ 294 CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) | 295 TWSI_CTRL_SW_LD_START); 296 for (i = 100; i > 0; i--) { 297 DELAY(1000); 298 reg = CSR_READ_4(sc, ALE_TWSI_CTRL); 299 if ((reg & TWSI_CTRL_SW_LD_START) == 0) 300 break; 301 } 302 if (i == 0) 303 printf("%s: reloading EEPROM timeout!\n", 304 sc->sc_dev.dv_xname); 305 } else { 306 if (aledebug) 307 printf("%s: PCI VPD capability not found!\n", 308 sc->sc_dev.dv_xname); 309 } 310 311 ea[0] = CSR_READ_4(sc, ALE_PAR0); 312 ea[1] = CSR_READ_4(sc, ALE_PAR1); 313 sc->ale_eaddr[0] = (ea[1] >> 8) & 0xFF; 314 sc->ale_eaddr[1] = (ea[1] >> 0) & 0xFF; 315 sc->ale_eaddr[2] = (ea[0] >> 24) & 0xFF; 316 sc->ale_eaddr[3] = (ea[0] >> 16) & 0xFF; 317 sc->ale_eaddr[4] = (ea[0] >> 8) & 0xFF; 318 sc->ale_eaddr[5] = (ea[0] >> 0) & 0xFF; 319 } 320 321 void 322 ale_phy_reset(struct ale_softc *sc) 323 { 324 /* Reset magic from Linux. */ 325 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 326 GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET | 327 GPHY_CTRL_PHY_PLL_ON); 328 DELAY(1000); 329 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 330 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | 331 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_PLL_ON); 332 DELAY(1000); 333 334 #define ATPHY_DBG_ADDR 0x1D 335 #define ATPHY_DBG_DATA 0x1E 336 337 /* Enable hibernation mode. */ 338 ale_miibus_writereg(&sc->sc_dev, sc->ale_phyaddr, 339 ATPHY_DBG_ADDR, 0x0B); 340 ale_miibus_writereg(&sc->sc_dev, sc->ale_phyaddr, 341 ATPHY_DBG_DATA, 0xBC00); 342 /* Set Class A/B for all modes. */ 343 ale_miibus_writereg(&sc->sc_dev, sc->ale_phyaddr, 344 ATPHY_DBG_ADDR, 0x00); 345 ale_miibus_writereg(&sc->sc_dev, sc->ale_phyaddr, 346 ATPHY_DBG_DATA, 0x02EF); 347 /* Enable 10BT power saving. */ 348 ale_miibus_writereg(&sc->sc_dev, sc->ale_phyaddr, 349 ATPHY_DBG_ADDR, 0x12); 350 ale_miibus_writereg(&sc->sc_dev, sc->ale_phyaddr, 351 ATPHY_DBG_DATA, 0x4C04); 352 /* Adjust 1000T power. */ 353 ale_miibus_writereg(&sc->sc_dev, sc->ale_phyaddr, 354 ATPHY_DBG_ADDR, 0x04); 355 ale_miibus_writereg(&sc->sc_dev, sc->ale_phyaddr, 356 ATPHY_DBG_ADDR, 0x8BBB); 357 /* 10BT center tap voltage. */ 358 ale_miibus_writereg(&sc->sc_dev, sc->ale_phyaddr, 359 ATPHY_DBG_ADDR, 0x05); 360 ale_miibus_writereg(&sc->sc_dev, sc->ale_phyaddr, 361 ATPHY_DBG_ADDR, 0x2C46); 362 363 #undef ATPHY_DBG_ADDR 364 #undef ATPHY_DBG_DATA 365 DELAY(1000); 366 } 367 368 void 369 ale_attach(struct device *parent, struct device *self, void *aux) 370 { 371 struct ale_softc *sc = (struct ale_softc *)self; 372 struct pci_attach_args *pa = aux; 373 pci_chipset_tag_t pc = pa->pa_pc; 374 pci_intr_handle_t ih; 375 const char *intrstr; 376 struct ifnet *ifp; 377 pcireg_t memtype; 378 int mii_flags, error = 0; 379 uint32_t rxf_len, txf_len; 380 const char *chipname; 381 382 /* 383 * Allocate IO memory 384 */ 385 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, ALE_PCIR_BAR); 386 if (pci_mapreg_map(pa, ALE_PCIR_BAR, memtype, 0, &sc->sc_mem_bt, 387 &sc->sc_mem_bh, NULL, &sc->sc_mem_size, 0)) { 388 printf(": can't map mem space\n"); 389 return; 390 } 391 392 if (pci_intr_map_msi(pa, &ih) != 0 && pci_intr_map(pa, &ih) != 0) { 393 printf(": can't map interrupt\n"); 394 goto fail; 395 } 396 397 /* 398 * Allocate IRQ 399 */ 400 intrstr = pci_intr_string(pc, ih); 401 sc->sc_irq_handle = pci_intr_establish(pc, ih, IPL_NET, ale_intr, sc, 402 sc->sc_dev.dv_xname); 403 if (sc->sc_irq_handle == NULL) { 404 printf(": could not establish interrupt"); 405 if (intrstr != NULL) 406 printf(" at %s", intrstr); 407 printf("\n"); 408 goto fail; 409 } 410 411 sc->sc_dmat = pa->pa_dmat; 412 sc->sc_pct = pa->pa_pc; 413 sc->sc_pcitag = pa->pa_tag; 414 415 /* Set PHY address. */ 416 sc->ale_phyaddr = ALE_PHY_ADDR; 417 418 /* Reset PHY. */ 419 ale_phy_reset(sc); 420 421 /* Reset the ethernet controller. */ 422 ale_reset(sc); 423 424 /* Get PCI and chip id/revision. */ 425 sc->ale_rev = PCI_REVISION(pa->pa_class); 426 if (sc->ale_rev >= 0xF0) { 427 /* L2E Rev. B. AR8114 */ 428 sc->ale_flags |= ALE_FLAG_FASTETHER; 429 chipname = "AR8114"; 430 } else { 431 if ((CSR_READ_4(sc, ALE_PHY_STATUS) & PHY_STATUS_100M) != 0) { 432 /* L1E AR8121 */ 433 sc->ale_flags |= ALE_FLAG_JUMBO; 434 chipname = "AR8121"; 435 } else { 436 /* L2E Rev. A. AR8113 */ 437 sc->ale_flags |= ALE_FLAG_FASTETHER; 438 chipname = "AR8113"; 439 } 440 } 441 442 printf(": %s, %s", chipname, intrstr); 443 444 /* 445 * All known controllers seems to require 4 bytes alignment 446 * of Tx buffers to make Tx checksum offload with custom 447 * checksum generation method work. 448 */ 449 sc->ale_flags |= ALE_FLAG_TXCSUM_BUG; 450 451 /* 452 * All known controllers seems to have issues on Rx checksum 453 * offload for fragmented IP datagrams. 454 */ 455 sc->ale_flags |= ALE_FLAG_RXCSUM_BUG; 456 457 /* 458 * Don't use Tx CMB. It is known to cause RRS update failure 459 * under certain circumstances. Typical phenomenon of the 460 * issue would be unexpected sequence number encountered in 461 * Rx handler. 462 */ 463 sc->ale_flags |= ALE_FLAG_TXCMB_BUG; 464 sc->ale_chip_rev = CSR_READ_4(sc, ALE_MASTER_CFG) >> 465 MASTER_CHIP_REV_SHIFT; 466 if (aledebug) { 467 printf("%s: PCI device revision : 0x%04x\n", 468 sc->sc_dev.dv_xname, sc->ale_rev); 469 printf("%s: Chip id/revision : 0x%04x\n", 470 sc->sc_dev.dv_xname, sc->ale_chip_rev); 471 } 472 473 /* 474 * Uninitialized hardware returns an invalid chip id/revision 475 * as well as 0xFFFFFFFF for Tx/Rx fifo length. 476 */ 477 txf_len = CSR_READ_4(sc, ALE_SRAM_TX_FIFO_LEN); 478 rxf_len = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 479 if (sc->ale_chip_rev == 0xFFFF || txf_len == 0xFFFFFFFF || 480 rxf_len == 0xFFFFFFF) { 481 printf("%s: chip revision : 0x%04x, %u Tx FIFO " 482 "%u Rx FIFO -- not initialized?\n", sc->sc_dev.dv_xname, 483 sc->ale_chip_rev, txf_len, rxf_len); 484 goto fail; 485 } 486 487 if (aledebug) { 488 printf("%s: %u Tx FIFO, %u Rx FIFO\n", sc->sc_dev.dv_xname, 489 txf_len, rxf_len); 490 } 491 492 /* Set max allowable DMA size. */ 493 sc->ale_dma_rd_burst = DMA_CFG_RD_BURST_128; 494 sc->ale_dma_wr_burst = DMA_CFG_WR_BURST_128; 495 496 error = ale_dma_alloc(sc); 497 if (error) 498 goto fail; 499 500 /* Load station address. */ 501 ale_get_macaddr(sc); 502 503 ifp = &sc->sc_arpcom.ac_if; 504 ifp->if_softc = sc; 505 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 506 ifp->if_ioctl = ale_ioctl; 507 ifp->if_start = ale_start; 508 ifp->if_watchdog = ale_watchdog; 509 ifp->if_baudrate = IF_Gbps(1); 510 IFQ_SET_MAXLEN(&ifp->if_snd, ALE_TX_RING_CNT - 1); 511 IFQ_SET_READY(&ifp->if_snd); 512 bcopy(sc->ale_eaddr, sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN); 513 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 514 515 ifp->if_capabilities = IFCAP_VLAN_MTU; 516 517 #ifdef ALE_CHECKSUM 518 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 519 IFCAP_CSUM_UDPv4; 520 #endif 521 522 #if NVLAN > 0 523 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 524 #endif 525 526 printf(", address %s\n", ether_sprintf(sc->sc_arpcom.ac_enaddr)); 527 528 /* Set up MII bus. */ 529 sc->sc_miibus.mii_ifp = ifp; 530 sc->sc_miibus.mii_readreg = ale_miibus_readreg; 531 sc->sc_miibus.mii_writereg = ale_miibus_writereg; 532 sc->sc_miibus.mii_statchg = ale_miibus_statchg; 533 534 ifmedia_init(&sc->sc_miibus.mii_media, 0, ale_mediachange, 535 ale_mediastatus); 536 mii_flags = 0; 537 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) 538 mii_flags |= MIIF_DOPAUSE; 539 mii_attach(self, &sc->sc_miibus, 0xffffffff, MII_PHY_ANY, 540 MII_OFFSET_ANY, mii_flags); 541 542 if (LIST_FIRST(&sc->sc_miibus.mii_phys) == NULL) { 543 printf("%s: no PHY found!\n", sc->sc_dev.dv_xname); 544 ifmedia_add(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL, 545 0, NULL); 546 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL); 547 } else 548 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_AUTO); 549 550 if_attach(ifp); 551 ether_ifattach(ifp); 552 553 timeout_set(&sc->ale_tick_ch, ale_tick, sc); 554 555 return; 556 fail: 557 ale_dma_free(sc); 558 if (sc->sc_irq_handle != NULL) 559 pci_intr_disestablish(pc, sc->sc_irq_handle); 560 if (sc->sc_mem_size) 561 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 562 } 563 564 int 565 ale_detach(struct device *self, int flags) 566 { 567 struct ale_softc *sc = (struct ale_softc *)self; 568 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 569 int s; 570 571 s = splnet(); 572 ale_stop(sc); 573 splx(s); 574 575 mii_detach(&sc->sc_miibus, MII_PHY_ANY, MII_OFFSET_ANY); 576 577 /* Delete all remaining media. */ 578 ifmedia_delete_instance(&sc->sc_miibus.mii_media, IFM_INST_ANY); 579 580 ether_ifdetach(ifp); 581 if_detach(ifp); 582 ale_dma_free(sc); 583 584 if (sc->sc_irq_handle != NULL) { 585 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 586 sc->sc_irq_handle = NULL; 587 } 588 589 return (0); 590 } 591 592 int 593 ale_activate(struct device *self, int act) 594 { 595 struct ale_softc *sc = (struct ale_softc *)self; 596 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 597 int rv = 0; 598 599 switch (act) { 600 case DVACT_QUIESCE: 601 rv = config_activate_children(self, act); 602 break; 603 case DVACT_SUSPEND: 604 if (ifp->if_flags & IFF_RUNNING) 605 ale_stop(sc); 606 rv = config_activate_children(self, act); 607 break; 608 case DVACT_RESUME: 609 rv = config_activate_children(self, act); 610 if (ifp->if_flags & IFF_UP) 611 ale_init(ifp); 612 break; 613 } 614 return (rv); 615 } 616 617 int 618 ale_dma_alloc(struct ale_softc *sc) 619 { 620 struct ale_txdesc *txd; 621 int nsegs, error, guard_size, i; 622 623 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) 624 guard_size = ALE_JUMBO_FRAMELEN; 625 else 626 guard_size = ALE_MAX_FRAMELEN; 627 sc->ale_pagesize = roundup(guard_size + ALE_RX_PAGE_SZ, 628 ALE_RX_PAGE_ALIGN); 629 630 /* 631 * Create DMA stuffs for TX ring 632 */ 633 error = bus_dmamap_create(sc->sc_dmat, ALE_TX_RING_SZ, 1, 634 ALE_TX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->ale_cdata.ale_tx_ring_map); 635 if (error) 636 return (ENOBUFS); 637 638 /* Allocate DMA'able memory for TX ring */ 639 error = bus_dmamem_alloc(sc->sc_dmat, ALE_TX_RING_SZ, 640 ETHER_ALIGN, 0, &sc->ale_cdata.ale_tx_ring_seg, 1, 641 &nsegs, BUS_DMA_WAITOK | BUS_DMA_ZERO); 642 if (error) { 643 printf("%s: could not allocate DMA'able memory for Tx ring.\n", 644 sc->sc_dev.dv_xname); 645 return error; 646 } 647 648 error = bus_dmamem_map(sc->sc_dmat, &sc->ale_cdata.ale_tx_ring_seg, 649 nsegs, ALE_TX_RING_SZ, (caddr_t *)&sc->ale_cdata.ale_tx_ring, 650 BUS_DMA_NOWAIT); 651 if (error) 652 return (ENOBUFS); 653 654 /* Load the DMA map for Tx ring. */ 655 error = bus_dmamap_load(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map, 656 sc->ale_cdata.ale_tx_ring, ALE_TX_RING_SZ, NULL, BUS_DMA_WAITOK); 657 if (error) { 658 printf("%s: could not load DMA'able memory for Tx ring.\n", 659 sc->sc_dev.dv_xname); 660 bus_dmamem_free(sc->sc_dmat, 661 (bus_dma_segment_t *)&sc->ale_cdata.ale_tx_ring, 1); 662 return error; 663 } 664 sc->ale_cdata.ale_tx_ring_paddr = 665 sc->ale_cdata.ale_tx_ring_map->dm_segs[0].ds_addr; 666 667 for (i = 0; i < ALE_RX_PAGES; i++) { 668 /* 669 * Create DMA stuffs for RX pages 670 */ 671 error = bus_dmamap_create(sc->sc_dmat, sc->ale_pagesize, 1, 672 sc->ale_pagesize, 0, BUS_DMA_NOWAIT, 673 &sc->ale_cdata.ale_rx_page[i].page_map); 674 if (error) 675 return (ENOBUFS); 676 677 /* Allocate DMA'able memory for RX pages */ 678 error = bus_dmamem_alloc(sc->sc_dmat, sc->ale_pagesize, 679 ETHER_ALIGN, 0, &sc->ale_cdata.ale_rx_page[i].page_seg, 680 1, &nsegs, BUS_DMA_WAITOK | BUS_DMA_ZERO); 681 if (error) { 682 printf("%s: could not allocate DMA'able memory for " 683 "Rx ring.\n", sc->sc_dev.dv_xname); 684 return error; 685 } 686 error = bus_dmamem_map(sc->sc_dmat, 687 &sc->ale_cdata.ale_rx_page[i].page_seg, nsegs, 688 sc->ale_pagesize, 689 (caddr_t *)&sc->ale_cdata.ale_rx_page[i].page_addr, 690 BUS_DMA_NOWAIT); 691 if (error) 692 return (ENOBUFS); 693 694 /* Load the DMA map for Rx pages. */ 695 error = bus_dmamap_load(sc->sc_dmat, 696 sc->ale_cdata.ale_rx_page[i].page_map, 697 sc->ale_cdata.ale_rx_page[i].page_addr, 698 sc->ale_pagesize, NULL, BUS_DMA_WAITOK); 699 if (error) { 700 printf("%s: could not load DMA'able memory for " 701 "Rx pages.\n", sc->sc_dev.dv_xname); 702 bus_dmamem_free(sc->sc_dmat, 703 (bus_dma_segment_t *)sc->ale_cdata.ale_rx_page[i].page_addr, 1); 704 return error; 705 } 706 sc->ale_cdata.ale_rx_page[i].page_paddr = 707 sc->ale_cdata.ale_rx_page[i].page_map->dm_segs[0].ds_addr; 708 } 709 710 /* 711 * Create DMA stuffs for Tx CMB. 712 */ 713 error = bus_dmamap_create(sc->sc_dmat, ALE_TX_CMB_SZ, 1, 714 ALE_TX_CMB_SZ, 0, BUS_DMA_NOWAIT, &sc->ale_cdata.ale_tx_cmb_map); 715 if (error) 716 return (ENOBUFS); 717 718 /* Allocate DMA'able memory for Tx CMB. */ 719 error = bus_dmamem_alloc(sc->sc_dmat, ALE_TX_CMB_SZ, ETHER_ALIGN, 0, 720 &sc->ale_cdata.ale_tx_cmb_seg, 1, &nsegs, 721 BUS_DMA_WAITOK |BUS_DMA_ZERO); 722 723 if (error) { 724 printf("%s: could not allocate DMA'able memory for Tx CMB.\n", 725 sc->sc_dev.dv_xname); 726 return error; 727 } 728 729 error = bus_dmamem_map(sc->sc_dmat, &sc->ale_cdata.ale_tx_cmb_seg, 730 nsegs, ALE_TX_CMB_SZ, (caddr_t *)&sc->ale_cdata.ale_tx_cmb, 731 BUS_DMA_NOWAIT); 732 if (error) 733 return (ENOBUFS); 734 735 /* Load the DMA map for Tx CMB. */ 736 error = bus_dmamap_load(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map, 737 sc->ale_cdata.ale_tx_cmb, ALE_TX_CMB_SZ, NULL, BUS_DMA_WAITOK); 738 if (error) { 739 printf("%s: could not load DMA'able memory for Tx CMB.\n", 740 sc->sc_dev.dv_xname); 741 bus_dmamem_free(sc->sc_dmat, 742 (bus_dma_segment_t *)&sc->ale_cdata.ale_tx_cmb, 1); 743 return error; 744 } 745 746 sc->ale_cdata.ale_tx_cmb_paddr = 747 sc->ale_cdata.ale_tx_cmb_map->dm_segs[0].ds_addr; 748 749 for (i = 0; i < ALE_RX_PAGES; i++) { 750 /* 751 * Create DMA stuffs for Rx CMB. 752 */ 753 error = bus_dmamap_create(sc->sc_dmat, ALE_RX_CMB_SZ, 1, 754 ALE_RX_CMB_SZ, 0, BUS_DMA_NOWAIT, 755 &sc->ale_cdata.ale_rx_page[i].cmb_map); 756 if (error) 757 return (ENOBUFS); 758 759 /* Allocate DMA'able memory for Rx CMB */ 760 error = bus_dmamem_alloc(sc->sc_dmat, ALE_RX_CMB_SZ, 761 ETHER_ALIGN, 0, &sc->ale_cdata.ale_rx_page[i].cmb_seg, 1, 762 &nsegs, BUS_DMA_WAITOK | BUS_DMA_ZERO); 763 if (error) { 764 printf("%s: could not allocate DMA'able memory for " 765 "Rx CMB\n", sc->sc_dev.dv_xname); 766 return error; 767 } 768 error = bus_dmamem_map(sc->sc_dmat, 769 &sc->ale_cdata.ale_rx_page[i].cmb_seg, nsegs, 770 ALE_RX_CMB_SZ, 771 (caddr_t *)&sc->ale_cdata.ale_rx_page[i].cmb_addr, 772 BUS_DMA_NOWAIT); 773 if (error) 774 return (ENOBUFS); 775 776 /* Load the DMA map for Rx CMB */ 777 error = bus_dmamap_load(sc->sc_dmat, 778 sc->ale_cdata.ale_rx_page[i].cmb_map, 779 sc->ale_cdata.ale_rx_page[i].cmb_addr, 780 ALE_RX_CMB_SZ, NULL, BUS_DMA_WAITOK); 781 if (error) { 782 printf("%s: could not load DMA'able memory for Rx CMB" 783 "\n", sc->sc_dev.dv_xname); 784 bus_dmamem_free(sc->sc_dmat, 785 (bus_dma_segment_t *)&sc->ale_cdata.ale_rx_page[i].cmb_addr, 1); 786 return error; 787 } 788 sc->ale_cdata.ale_rx_page[i].cmb_paddr = 789 sc->ale_cdata.ale_rx_page[i].cmb_map->dm_segs[0].ds_addr; 790 } 791 792 793 /* Create DMA maps for Tx buffers. */ 794 for (i = 0; i < ALE_TX_RING_CNT; i++) { 795 txd = &sc->ale_cdata.ale_txdesc[i]; 796 txd->tx_m = NULL; 797 txd->tx_dmamap = NULL; 798 error = bus_dmamap_create(sc->sc_dmat, ALE_TSO_MAXSIZE, 799 ALE_MAXTXSEGS, ALE_TSO_MAXSEGSIZE, 0, BUS_DMA_NOWAIT, 800 &txd->tx_dmamap); 801 if (error) { 802 printf("%s: could not create Tx dmamap.\n", 803 sc->sc_dev.dv_xname); 804 return error; 805 } 806 } 807 808 return (0); 809 } 810 811 void 812 ale_dma_free(struct ale_softc *sc) 813 { 814 struct ale_txdesc *txd; 815 int i; 816 817 /* Tx buffers. */ 818 for (i = 0; i < ALE_TX_RING_CNT; i++) { 819 txd = &sc->ale_cdata.ale_txdesc[i]; 820 if (txd->tx_dmamap != NULL) { 821 bus_dmamap_destroy(sc->sc_dmat, txd->tx_dmamap); 822 txd->tx_dmamap = NULL; 823 } 824 } 825 826 /* Tx descriptor ring. */ 827 if (sc->ale_cdata.ale_tx_ring_map != NULL) 828 bus_dmamap_unload(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map); 829 if (sc->ale_cdata.ale_tx_ring_map != NULL && 830 sc->ale_cdata.ale_tx_ring != NULL) 831 bus_dmamem_free(sc->sc_dmat, 832 (bus_dma_segment_t *)sc->ale_cdata.ale_tx_ring, 1); 833 sc->ale_cdata.ale_tx_ring = NULL; 834 sc->ale_cdata.ale_tx_ring_map = NULL; 835 836 /* Rx page block. */ 837 for (i = 0; i < ALE_RX_PAGES; i++) { 838 if (sc->ale_cdata.ale_rx_page[i].page_map != NULL) 839 bus_dmamap_unload(sc->sc_dmat, 840 sc->ale_cdata.ale_rx_page[i].page_map); 841 if (sc->ale_cdata.ale_rx_page[i].page_map != NULL && 842 sc->ale_cdata.ale_rx_page[i].page_addr != NULL) 843 bus_dmamem_free(sc->sc_dmat, 844 (bus_dma_segment_t *)sc->ale_cdata.ale_rx_page[i].page_addr, 1); 845 sc->ale_cdata.ale_rx_page[i].page_addr = NULL; 846 sc->ale_cdata.ale_rx_page[i].page_map = NULL; 847 } 848 849 /* Rx CMB. */ 850 for (i = 0; i < ALE_RX_PAGES; i++) { 851 if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL) 852 bus_dmamap_unload(sc->sc_dmat, 853 sc->ale_cdata.ale_rx_page[i].cmb_map); 854 if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL && 855 sc->ale_cdata.ale_rx_page[i].cmb_addr != NULL) 856 bus_dmamem_free(sc->sc_dmat, 857 (bus_dma_segment_t *)sc->ale_cdata.ale_rx_page[i].cmb_addr, 1); 858 sc->ale_cdata.ale_rx_page[i].cmb_addr = NULL; 859 sc->ale_cdata.ale_rx_page[i].cmb_map = NULL; 860 } 861 862 /* Tx CMB. */ 863 if (sc->ale_cdata.ale_tx_cmb_map != NULL) 864 bus_dmamap_unload(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map); 865 if (sc->ale_cdata.ale_tx_cmb_map != NULL && 866 sc->ale_cdata.ale_tx_cmb != NULL) 867 bus_dmamem_free(sc->sc_dmat, 868 (bus_dma_segment_t *)sc->ale_cdata.ale_tx_cmb, 1); 869 sc->ale_cdata.ale_tx_cmb = NULL; 870 sc->ale_cdata.ale_tx_cmb_map = NULL; 871 872 } 873 874 int 875 ale_encap(struct ale_softc *sc, struct mbuf **m_head) 876 { 877 struct ale_txdesc *txd, *txd_last; 878 struct tx_desc *desc; 879 struct mbuf *m; 880 bus_dmamap_t map; 881 uint32_t cflags, poff, vtag; 882 int error, i, prod; 883 884 m = *m_head; 885 cflags = vtag = 0; 886 poff = 0; 887 888 prod = sc->ale_cdata.ale_tx_prod; 889 txd = &sc->ale_cdata.ale_txdesc[prod]; 890 txd_last = txd; 891 map = txd->tx_dmamap; 892 893 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, BUS_DMA_NOWAIT); 894 if (error != 0 && error != EFBIG) 895 goto drop; 896 if (error != 0) { 897 if (m_defrag(*m_head, M_DONTWAIT)) { 898 error = ENOBUFS; 899 goto drop; 900 } 901 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, 902 BUS_DMA_NOWAIT); 903 if (error != 0) 904 goto drop; 905 } 906 907 /* Check descriptor overrun. */ 908 if (sc->ale_cdata.ale_tx_cnt + map->dm_nsegs >= ALE_TX_RING_CNT - 2) { 909 bus_dmamap_unload(sc->sc_dmat, map); 910 return (ENOBUFS); 911 } 912 913 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 914 BUS_DMASYNC_PREWRITE); 915 916 m = *m_head; 917 /* Configure Tx checksum offload. */ 918 if ((m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0) { 919 /* 920 * AR81xx supports Tx custom checksum offload feature 921 * that offloads single 16bit checksum computation. 922 * So you can choose one among IP, TCP and UDP. 923 * Normally driver sets checksum start/insertion 924 * position from the information of TCP/UDP frame as 925 * TCP/UDP checksum takes more time than that of IP. 926 * However it seems that custom checksum offload 927 * requires 4 bytes aligned Tx buffers due to hardware 928 * bug. 929 * AR81xx also supports explicit Tx checksum computation 930 * if it is told that the size of IP header and TCP 931 * header(for UDP, the header size does not matter 932 * because it's fixed length). However with this scheme 933 * TSO does not work so you have to choose one either 934 * TSO or explicit Tx checksum offload. I chosen TSO 935 * plus custom checksum offload with work-around which 936 * will cover most common usage for this consumer 937 * ethernet controller. The work-around takes a lot of 938 * CPU cycles if Tx buffer is not aligned on 4 bytes 939 * boundary, though. 940 */ 941 cflags |= ALE_TD_CXSUM; 942 /* Set checksum start offset. */ 943 cflags |= (poff << ALE_TD_CSUM_PLOADOFFSET_SHIFT); 944 } 945 946 #if NVLAN > 0 947 /* Configure VLAN hardware tag insertion. */ 948 if (m->m_flags & M_VLANTAG) { 949 vtag = ALE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag); 950 vtag = ((vtag << ALE_TD_VLAN_SHIFT) & ALE_TD_VLAN_MASK); 951 cflags |= ALE_TD_INSERT_VLAN_TAG; 952 } 953 #endif 954 955 desc = NULL; 956 for (i = 0; i < map->dm_nsegs; i++) { 957 desc = &sc->ale_cdata.ale_tx_ring[prod]; 958 desc->addr = htole64(map->dm_segs[i].ds_addr); 959 desc->len = 960 htole32(ALE_TX_BYTES(map->dm_segs[i].ds_len) | vtag); 961 desc->flags = htole32(cflags); 962 sc->ale_cdata.ale_tx_cnt++; 963 ALE_DESC_INC(prod, ALE_TX_RING_CNT); 964 } 965 966 /* Update producer index. */ 967 sc->ale_cdata.ale_tx_prod = prod; 968 969 /* Finally set EOP on the last descriptor. */ 970 prod = (prod + ALE_TX_RING_CNT - 1) % ALE_TX_RING_CNT; 971 desc = &sc->ale_cdata.ale_tx_ring[prod]; 972 desc->flags |= htole32(ALE_TD_EOP); 973 974 /* Swap dmamap of the first and the last. */ 975 txd = &sc->ale_cdata.ale_txdesc[prod]; 976 map = txd_last->tx_dmamap; 977 txd_last->tx_dmamap = txd->tx_dmamap; 978 txd->tx_dmamap = map; 979 txd->tx_m = m; 980 981 /* Sync descriptors. */ 982 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map, 0, 983 sc->ale_cdata.ale_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 984 985 return (0); 986 987 drop: 988 m_freem(*m_head); 989 *m_head = NULL; 990 return (error); 991 } 992 993 void 994 ale_start(struct ifnet *ifp) 995 { 996 struct ale_softc *sc = ifp->if_softc; 997 struct mbuf *m_head; 998 int enq; 999 1000 /* Reclaim transmitted frames. */ 1001 if (sc->ale_cdata.ale_tx_cnt >= ALE_TX_DESC_HIWAT) 1002 ale_txeof(sc); 1003 1004 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1005 return; 1006 if ((sc->ale_flags & ALE_FLAG_LINK) == 0) 1007 return; 1008 if (IFQ_IS_EMPTY(&ifp->if_snd)) 1009 return; 1010 1011 enq = 0; 1012 for (;;) { 1013 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1014 if (m_head == NULL) 1015 break; 1016 1017 /* 1018 * Pack the data into the transmit ring. If we 1019 * don't have room, set the OACTIVE flag and wait 1020 * for the NIC to drain the ring. 1021 */ 1022 if (ale_encap(sc, &m_head)) { 1023 if (m_head == NULL) { 1024 ifp->if_oerrors++; 1025 break; 1026 } 1027 IF_PREPEND(&ifp->if_snd, m_head); 1028 ifp->if_flags |= IFF_OACTIVE; 1029 break; 1030 } 1031 1032 enq = 1; 1033 1034 #if NBPFILTER > 0 1035 /* 1036 * If there's a BPF listener, bounce a copy of this frame 1037 * to him. 1038 */ 1039 if (ifp->if_bpf != NULL) 1040 bpf_mtap_ether(ifp->if_bpf, m_head, BPF_DIRECTION_OUT); 1041 #endif 1042 } 1043 1044 if (enq) { 1045 /* Kick. */ 1046 CSR_WRITE_4(sc, ALE_MBOX_TPD_PROD_IDX, 1047 sc->ale_cdata.ale_tx_prod); 1048 1049 /* Set a timeout in case the chip goes out to lunch. */ 1050 ifp->if_timer = ALE_TX_TIMEOUT; 1051 } 1052 } 1053 1054 void 1055 ale_watchdog(struct ifnet *ifp) 1056 { 1057 struct ale_softc *sc = ifp->if_softc; 1058 1059 if ((sc->ale_flags & ALE_FLAG_LINK) == 0) { 1060 printf("%s: watchdog timeout (missed link)\n", 1061 sc->sc_dev.dv_xname); 1062 ifp->if_oerrors++; 1063 ale_init(ifp); 1064 return; 1065 } 1066 1067 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 1068 ifp->if_oerrors++; 1069 ale_init(ifp); 1070 ale_start(ifp); 1071 } 1072 1073 int 1074 ale_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1075 { 1076 struct ale_softc *sc = ifp->if_softc; 1077 struct mii_data *mii = &sc->sc_miibus; 1078 struct ifaddr *ifa = (struct ifaddr *)data; 1079 struct ifreq *ifr = (struct ifreq *)data; 1080 int s, error = 0; 1081 1082 s = splnet(); 1083 1084 switch (cmd) { 1085 case SIOCSIFADDR: 1086 ifp->if_flags |= IFF_UP; 1087 if (!(ifp->if_flags & IFF_RUNNING)) 1088 ale_init(ifp); 1089 #ifdef INET 1090 if (ifa->ifa_addr->sa_family == AF_INET) 1091 arp_ifinit(&sc->sc_arpcom, ifa); 1092 #endif 1093 break; 1094 1095 case SIOCSIFFLAGS: 1096 if (ifp->if_flags & IFF_UP) { 1097 if (ifp->if_flags & IFF_RUNNING) 1098 error = ENETRESET; 1099 else 1100 ale_init(ifp); 1101 } else { 1102 if (ifp->if_flags & IFF_RUNNING) 1103 ale_stop(sc); 1104 } 1105 break; 1106 1107 case SIOCSIFMEDIA: 1108 case SIOCGIFMEDIA: 1109 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1110 break; 1111 1112 default: 1113 error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data); 1114 break; 1115 } 1116 1117 if (error == ENETRESET) { 1118 if (ifp->if_flags & IFF_RUNNING) 1119 ale_iff(sc); 1120 error = 0; 1121 } 1122 1123 splx(s); 1124 return (error); 1125 } 1126 1127 void 1128 ale_mac_config(struct ale_softc *sc) 1129 { 1130 struct mii_data *mii; 1131 uint32_t reg; 1132 1133 mii = &sc->sc_miibus; 1134 reg = CSR_READ_4(sc, ALE_MAC_CFG); 1135 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 1136 MAC_CFG_SPEED_MASK); 1137 /* Reprogram MAC with resolved speed/duplex. */ 1138 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1139 case IFM_10_T: 1140 case IFM_100_TX: 1141 reg |= MAC_CFG_SPEED_10_100; 1142 break; 1143 case IFM_1000_T: 1144 reg |= MAC_CFG_SPEED_1000; 1145 break; 1146 } 1147 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1148 reg |= MAC_CFG_FULL_DUPLEX; 1149 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1150 reg |= MAC_CFG_TX_FC; 1151 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1152 reg |= MAC_CFG_RX_FC; 1153 } 1154 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1155 } 1156 1157 void 1158 ale_stats_clear(struct ale_softc *sc) 1159 { 1160 struct smb sb; 1161 uint32_t *reg; 1162 int i; 1163 1164 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 1165 CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 1166 i += sizeof(uint32_t); 1167 } 1168 /* Read Tx statistics. */ 1169 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 1170 CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 1171 i += sizeof(uint32_t); 1172 } 1173 } 1174 1175 void 1176 ale_stats_update(struct ale_softc *sc) 1177 { 1178 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1179 struct ale_hw_stats *stat; 1180 struct smb sb, *smb; 1181 uint32_t *reg; 1182 int i; 1183 1184 stat = &sc->ale_stats; 1185 smb = &sb; 1186 1187 /* Read Rx statistics. */ 1188 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 1189 *reg = CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 1190 i += sizeof(uint32_t); 1191 } 1192 /* Read Tx statistics. */ 1193 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 1194 *reg = CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 1195 i += sizeof(uint32_t); 1196 } 1197 1198 /* Rx stats. */ 1199 stat->rx_frames += smb->rx_frames; 1200 stat->rx_bcast_frames += smb->rx_bcast_frames; 1201 stat->rx_mcast_frames += smb->rx_mcast_frames; 1202 stat->rx_pause_frames += smb->rx_pause_frames; 1203 stat->rx_control_frames += smb->rx_control_frames; 1204 stat->rx_crcerrs += smb->rx_crcerrs; 1205 stat->rx_lenerrs += smb->rx_lenerrs; 1206 stat->rx_bytes += smb->rx_bytes; 1207 stat->rx_runts += smb->rx_runts; 1208 stat->rx_fragments += smb->rx_fragments; 1209 stat->rx_pkts_64 += smb->rx_pkts_64; 1210 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 1211 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 1212 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 1213 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 1214 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 1215 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 1216 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 1217 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 1218 stat->rx_rrs_errs += smb->rx_rrs_errs; 1219 stat->rx_alignerrs += smb->rx_alignerrs; 1220 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 1221 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 1222 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 1223 1224 /* Tx stats. */ 1225 stat->tx_frames += smb->tx_frames; 1226 stat->tx_bcast_frames += smb->tx_bcast_frames; 1227 stat->tx_mcast_frames += smb->tx_mcast_frames; 1228 stat->tx_pause_frames += smb->tx_pause_frames; 1229 stat->tx_excess_defer += smb->tx_excess_defer; 1230 stat->tx_control_frames += smb->tx_control_frames; 1231 stat->tx_deferred += smb->tx_deferred; 1232 stat->tx_bytes += smb->tx_bytes; 1233 stat->tx_pkts_64 += smb->tx_pkts_64; 1234 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 1235 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 1236 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 1237 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 1238 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 1239 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 1240 stat->tx_single_colls += smb->tx_single_colls; 1241 stat->tx_multi_colls += smb->tx_multi_colls; 1242 stat->tx_late_colls += smb->tx_late_colls; 1243 stat->tx_excess_colls += smb->tx_excess_colls; 1244 stat->tx_abort += smb->tx_abort; 1245 stat->tx_underrun += smb->tx_underrun; 1246 stat->tx_desc_underrun += smb->tx_desc_underrun; 1247 stat->tx_lenerrs += smb->tx_lenerrs; 1248 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 1249 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 1250 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 1251 1252 /* Update counters in ifnet. */ 1253 ifp->if_opackets += smb->tx_frames; 1254 1255 ifp->if_collisions += smb->tx_single_colls + 1256 smb->tx_multi_colls * 2 + smb->tx_late_colls + 1257 smb->tx_abort * HDPX_CFG_RETRY_DEFAULT; 1258 1259 /* 1260 * XXX 1261 * tx_pkts_truncated counter looks suspicious. It constantly 1262 * increments with no sign of Tx errors. This may indicate 1263 * the counter name is not correct one so I've removed the 1264 * counter in output errors. 1265 */ 1266 ifp->if_oerrors += smb->tx_abort + smb->tx_late_colls + 1267 smb->tx_underrun; 1268 1269 ifp->if_ipackets += smb->rx_frames; 1270 1271 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 1272 smb->rx_runts + smb->rx_pkts_truncated + 1273 smb->rx_fifo_oflows + smb->rx_rrs_errs + 1274 smb->rx_alignerrs; 1275 } 1276 1277 int 1278 ale_intr(void *xsc) 1279 { 1280 struct ale_softc *sc = xsc; 1281 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1282 uint32_t status; 1283 1284 status = CSR_READ_4(sc, ALE_INTR_STATUS); 1285 if ((status & ALE_INTRS) == 0) 1286 return (0); 1287 1288 /* Acknowledge and disable interrupts. */ 1289 CSR_WRITE_4(sc, ALE_INTR_STATUS, status | INTR_DIS_INT); 1290 1291 if (ifp->if_flags & IFF_RUNNING) { 1292 int error; 1293 1294 error = ale_rxeof(sc); 1295 if (error) { 1296 sc->ale_stats.reset_brk_seq++; 1297 ale_init(ifp); 1298 return (0); 1299 } 1300 1301 if (status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) { 1302 if (status & INTR_DMA_RD_TO_RST) 1303 printf("%s: DMA read error! -- resetting\n", 1304 sc->sc_dev.dv_xname); 1305 if (status & INTR_DMA_WR_TO_RST) 1306 printf("%s: DMA write error! -- resetting\n", 1307 sc->sc_dev.dv_xname); 1308 ale_init(ifp); 1309 return (0); 1310 } 1311 1312 ale_txeof(sc); 1313 ale_start(ifp); 1314 } 1315 1316 /* Re-enable interrupts. */ 1317 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0x7FFFFFFF); 1318 return (1); 1319 } 1320 1321 void 1322 ale_txeof(struct ale_softc *sc) 1323 { 1324 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1325 struct ale_txdesc *txd; 1326 uint32_t cons, prod; 1327 int prog; 1328 1329 if (sc->ale_cdata.ale_tx_cnt == 0) 1330 return; 1331 1332 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map, 0, 1333 sc->ale_cdata.ale_tx_ring_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1334 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) { 1335 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map, 0, 1336 sc->ale_cdata.ale_tx_cmb_map->dm_mapsize, 1337 BUS_DMASYNC_POSTREAD); 1338 prod = *sc->ale_cdata.ale_tx_cmb & TPD_CNT_MASK; 1339 } else 1340 prod = CSR_READ_2(sc, ALE_TPD_CONS_IDX); 1341 cons = sc->ale_cdata.ale_tx_cons; 1342 /* 1343 * Go through our Tx list and free mbufs for those 1344 * frames which have been transmitted. 1345 */ 1346 for (prog = 0; cons != prod; prog++, 1347 ALE_DESC_INC(cons, ALE_TX_RING_CNT)) { 1348 if (sc->ale_cdata.ale_tx_cnt <= 0) 1349 break; 1350 prog++; 1351 ifp->if_flags &= ~IFF_OACTIVE; 1352 sc->ale_cdata.ale_tx_cnt--; 1353 txd = &sc->ale_cdata.ale_txdesc[cons]; 1354 if (txd->tx_m != NULL) { 1355 /* Reclaim transmitted mbufs. */ 1356 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1357 m_freem(txd->tx_m); 1358 txd->tx_m = NULL; 1359 } 1360 } 1361 1362 if (prog > 0) { 1363 sc->ale_cdata.ale_tx_cons = cons; 1364 /* 1365 * Unarm watchdog timer only when there is no pending 1366 * Tx descriptors in queue. 1367 */ 1368 if (sc->ale_cdata.ale_tx_cnt == 0) 1369 ifp->if_timer = 0; 1370 } 1371 } 1372 1373 void 1374 ale_rx_update_page(struct ale_softc *sc, struct ale_rx_page **page, 1375 uint32_t length, uint32_t *prod) 1376 { 1377 struct ale_rx_page *rx_page; 1378 1379 rx_page = *page; 1380 /* Update consumer position. */ 1381 rx_page->cons += roundup(length + sizeof(struct rx_rs), 1382 ALE_RX_PAGE_ALIGN); 1383 if (rx_page->cons >= ALE_RX_PAGE_SZ) { 1384 /* 1385 * End of Rx page reached, let hardware reuse 1386 * this page. 1387 */ 1388 rx_page->cons = 0; 1389 *rx_page->cmb_addr = 0; 1390 bus_dmamap_sync(sc->sc_dmat, rx_page->cmb_map, 0, 1391 rx_page->cmb_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1392 CSR_WRITE_1(sc, ALE_RXF0_PAGE0 + sc->ale_cdata.ale_rx_curp, 1393 RXF_VALID); 1394 /* Switch to alternate Rx page. */ 1395 sc->ale_cdata.ale_rx_curp ^= 1; 1396 rx_page = *page = 1397 &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 1398 /* Page flipped, sync CMB and Rx page. */ 1399 bus_dmamap_sync(sc->sc_dmat, rx_page->page_map, 0, 1400 rx_page->page_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1401 bus_dmamap_sync(sc->sc_dmat, rx_page->cmb_map, 0, 1402 rx_page->cmb_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1403 /* Sync completed, cache updated producer index. */ 1404 *prod = *rx_page->cmb_addr; 1405 } 1406 } 1407 1408 1409 /* 1410 * It seems that AR81xx controller can compute partial checksum. 1411 * The partial checksum value can be used to accelerate checksum 1412 * computation for fragmented TCP/UDP packets. Upper network stack 1413 * already takes advantage of the partial checksum value in IP 1414 * reassembly stage. But I'm not sure the correctness of the 1415 * partial hardware checksum assistance due to lack of data sheet. 1416 * In addition, the Rx feature of controller that requires copying 1417 * for every frames effectively nullifies one of most nice offload 1418 * capability of controller. 1419 */ 1420 void 1421 ale_rxcsum(struct ale_softc *sc, struct mbuf *m, uint32_t status) 1422 { 1423 struct ip *ip; 1424 char *p; 1425 1426 if ((status & ALE_RD_IPCSUM_NOK) == 0) 1427 m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK; 1428 1429 if ((sc->ale_flags & ALE_FLAG_RXCSUM_BUG) == 0) { 1430 if (((status & ALE_RD_IPV4_FRAG) == 0) && 1431 ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0) && 1432 ((status & ALE_RD_TCP_UDPCSUM_NOK) == 0)) { 1433 m->m_pkthdr.csum_flags |= 1434 M_TCP_CSUM_IN_OK | M_UDP_CSUM_IN_OK; 1435 } 1436 } else { 1437 if ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0 && 1438 (status & ALE_RD_TCP_UDPCSUM_NOK) == 0) { 1439 p = mtod(m, char *); 1440 p += ETHER_HDR_LEN; 1441 if ((status & ALE_RD_802_3) != 0) 1442 p += LLC_SNAPFRAMELEN; 1443 #if NVLAN > 0 1444 if (status & ALE_RD_VLAN) 1445 p += EVL_ENCAPLEN; 1446 #endif 1447 ip = (struct ip *)p; 1448 if (ip->ip_off != 0 && (status & ALE_RD_IPV4_DF) == 0) 1449 return; 1450 m->m_pkthdr.csum_flags |= 1451 M_TCP_CSUM_IN_OK | M_UDP_CSUM_IN_OK; 1452 } 1453 } 1454 /* 1455 * Don't mark bad checksum for TCP/UDP frames 1456 * as fragmented frames may always have set 1457 * bad checksummed bit of frame status. 1458 */ 1459 } 1460 1461 /* Process received frames. */ 1462 int 1463 ale_rxeof(struct ale_softc *sc) 1464 { 1465 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1466 struct ale_rx_page *rx_page; 1467 struct rx_rs *rs; 1468 struct mbuf *m; 1469 uint32_t length, prod, seqno, status; 1470 int prog; 1471 1472 rx_page = &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 1473 bus_dmamap_sync(sc->sc_dmat, rx_page->cmb_map, 0, 1474 rx_page->cmb_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1475 bus_dmamap_sync(sc->sc_dmat, rx_page->page_map, 0, 1476 rx_page->page_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1477 /* 1478 * Don't directly access producer index as hardware may 1479 * update it while Rx handler is in progress. It would 1480 * be even better if there is a way to let hardware 1481 * know how far driver processed its received frames. 1482 * Alternatively, hardware could provide a way to disable 1483 * CMB updates until driver acknowledges the end of CMB 1484 * access. 1485 */ 1486 prod = *rx_page->cmb_addr; 1487 for (prog = 0; ; prog++) { 1488 if (rx_page->cons >= prod) 1489 break; 1490 rs = (struct rx_rs *)(rx_page->page_addr + rx_page->cons); 1491 seqno = ALE_RX_SEQNO(letoh32(rs->seqno)); 1492 if (sc->ale_cdata.ale_rx_seqno != seqno) { 1493 /* 1494 * Normally I believe this should not happen unless 1495 * severe driver bug or corrupted memory. However 1496 * it seems to happen under certain conditions which 1497 * is triggered by abrupt Rx events such as initiation 1498 * of bulk transfer of remote host. It's not easy to 1499 * reproduce this and I doubt it could be related 1500 * with FIFO overflow of hardware or activity of Tx 1501 * CMB updates. I also remember similar behaviour 1502 * seen on RealTek 8139 which uses resembling Rx 1503 * scheme. 1504 */ 1505 if (aledebug) 1506 printf("%s: garbled seq: %u, expected: %u -- " 1507 "resetting!\n", sc->sc_dev.dv_xname, 1508 seqno, sc->ale_cdata.ale_rx_seqno); 1509 return (EIO); 1510 } 1511 /* Frame received. */ 1512 sc->ale_cdata.ale_rx_seqno++; 1513 length = ALE_RX_BYTES(letoh32(rs->length)); 1514 status = letoh32(rs->flags); 1515 if (status & ALE_RD_ERROR) { 1516 /* 1517 * We want to pass the following frames to upper 1518 * layer regardless of error status of Rx return 1519 * status. 1520 * 1521 * o IP/TCP/UDP checksum is bad. 1522 * o frame length and protocol specific length 1523 * does not match. 1524 */ 1525 if (status & (ALE_RD_CRC | ALE_RD_CODE | 1526 ALE_RD_DRIBBLE | ALE_RD_RUNT | ALE_RD_OFLOW | 1527 ALE_RD_TRUNC)) { 1528 ale_rx_update_page(sc, &rx_page, length, &prod); 1529 continue; 1530 } 1531 } 1532 /* 1533 * m_devget(9) is major bottle-neck of ale(4)(It comes 1534 * from hardware limitation). For jumbo frames we could 1535 * get a slightly better performance if driver use 1536 * m_getjcl(9) with proper buffer size argument. However 1537 * that would make code more complicated and I don't 1538 * think users would expect good Rx performance numbers 1539 * on these low-end consumer ethernet controller. 1540 */ 1541 m = m_devget((char *)(rs + 1), length - ETHER_CRC_LEN, 1542 ETHER_ALIGN, ifp, NULL); 1543 if (m == NULL) { 1544 ifp->if_iqdrops++; 1545 ale_rx_update_page(sc, &rx_page, length, &prod); 1546 continue; 1547 } 1548 if (status & ALE_RD_IPV4) 1549 ale_rxcsum(sc, m, status); 1550 #if NVLAN > 0 1551 if (status & ALE_RD_VLAN) { 1552 uint32_t vtags = ALE_RX_VLAN(letoh32(rs->vtags)); 1553 m->m_pkthdr.ether_vtag = ALE_RX_VLAN_TAG(vtags); 1554 m->m_flags |= M_VLANTAG; 1555 } 1556 #endif 1557 1558 1559 #if NBPFILTER > 0 1560 if (ifp->if_bpf) 1561 bpf_mtap_ether(ifp->if_bpf, m, BPF_DIRECTION_IN); 1562 #endif 1563 1564 /* Pass it to upper layer. */ 1565 ether_input_mbuf(ifp, m); 1566 1567 ale_rx_update_page(sc, &rx_page, length, &prod); 1568 } 1569 1570 return 0; 1571 } 1572 1573 void 1574 ale_tick(void *xsc) 1575 { 1576 struct ale_softc *sc = xsc; 1577 struct mii_data *mii = &sc->sc_miibus; 1578 int s; 1579 1580 s = splnet(); 1581 mii_tick(mii); 1582 ale_stats_update(sc); 1583 1584 timeout_add_sec(&sc->ale_tick_ch, 1); 1585 splx(s); 1586 } 1587 1588 void 1589 ale_reset(struct ale_softc *sc) 1590 { 1591 uint32_t reg; 1592 int i; 1593 1594 /* Initialize PCIe module. From Linux. */ 1595 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 1596 1597 CSR_WRITE_4(sc, ALE_MASTER_CFG, MASTER_RESET); 1598 for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 1599 DELAY(10); 1600 if ((CSR_READ_4(sc, ALE_MASTER_CFG) & MASTER_RESET) == 0) 1601 break; 1602 } 1603 if (i == 0) 1604 printf("%s: master reset timeout!\n", sc->sc_dev.dv_xname); 1605 1606 for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 1607 if ((reg = CSR_READ_4(sc, ALE_IDLE_STATUS)) == 0) 1608 break; 1609 DELAY(10); 1610 } 1611 1612 if (i == 0) 1613 printf("%s: reset timeout(0x%08x)!\n", sc->sc_dev.dv_xname, 1614 reg); 1615 } 1616 1617 int 1618 ale_init(struct ifnet *ifp) 1619 { 1620 struct ale_softc *sc = ifp->if_softc; 1621 struct mii_data *mii; 1622 uint8_t eaddr[ETHER_ADDR_LEN]; 1623 bus_addr_t paddr; 1624 uint32_t reg, rxf_hi, rxf_lo; 1625 1626 /* 1627 * Cancel any pending I/O. 1628 */ 1629 ale_stop(sc); 1630 1631 /* 1632 * Reset the chip to a known state. 1633 */ 1634 ale_reset(sc); 1635 1636 /* Initialize Tx descriptors, DMA memory blocks. */ 1637 ale_init_rx_pages(sc); 1638 ale_init_tx_ring(sc); 1639 1640 /* Reprogram the station address. */ 1641 bcopy(LLADDR(ifp->if_sadl), eaddr, ETHER_ADDR_LEN); 1642 CSR_WRITE_4(sc, ALE_PAR0, 1643 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 1644 CSR_WRITE_4(sc, ALE_PAR1, eaddr[0] << 8 | eaddr[1]); 1645 1646 /* 1647 * Clear WOL status and disable all WOL feature as WOL 1648 * would interfere Rx operation under normal environments. 1649 */ 1650 CSR_READ_4(sc, ALE_WOL_CFG); 1651 CSR_WRITE_4(sc, ALE_WOL_CFG, 0); 1652 1653 /* 1654 * Set Tx descriptor/RXF0/CMB base addresses. They share 1655 * the same high address part of DMAable region. 1656 */ 1657 paddr = sc->ale_cdata.ale_tx_ring_paddr; 1658 CSR_WRITE_4(sc, ALE_TPD_ADDR_HI, ALE_ADDR_HI(paddr)); 1659 CSR_WRITE_4(sc, ALE_TPD_ADDR_LO, ALE_ADDR_LO(paddr)); 1660 CSR_WRITE_4(sc, ALE_TPD_CNT, 1661 (ALE_TX_RING_CNT << TPD_CNT_SHIFT) & TPD_CNT_MASK); 1662 1663 /* Set Rx page base address, note we use single queue. */ 1664 paddr = sc->ale_cdata.ale_rx_page[0].page_paddr; 1665 CSR_WRITE_4(sc, ALE_RXF0_PAGE0_ADDR_LO, ALE_ADDR_LO(paddr)); 1666 paddr = sc->ale_cdata.ale_rx_page[1].page_paddr; 1667 CSR_WRITE_4(sc, ALE_RXF0_PAGE1_ADDR_LO, ALE_ADDR_LO(paddr)); 1668 1669 /* Set Tx/Rx CMB addresses. */ 1670 paddr = sc->ale_cdata.ale_tx_cmb_paddr; 1671 CSR_WRITE_4(sc, ALE_TX_CMB_ADDR_LO, ALE_ADDR_LO(paddr)); 1672 paddr = sc->ale_cdata.ale_rx_page[0].cmb_paddr; 1673 CSR_WRITE_4(sc, ALE_RXF0_CMB0_ADDR_LO, ALE_ADDR_LO(paddr)); 1674 paddr = sc->ale_cdata.ale_rx_page[1].cmb_paddr; 1675 CSR_WRITE_4(sc, ALE_RXF0_CMB1_ADDR_LO, ALE_ADDR_LO(paddr)); 1676 1677 /* Mark RXF0 is valid. */ 1678 CSR_WRITE_1(sc, ALE_RXF0_PAGE0, RXF_VALID); 1679 CSR_WRITE_1(sc, ALE_RXF0_PAGE1, RXF_VALID); 1680 /* 1681 * No need to initialize RFX1/RXF2/RXF3. We don't use 1682 * multi-queue yet. 1683 */ 1684 1685 /* Set Rx page size, excluding guard frame size. */ 1686 CSR_WRITE_4(sc, ALE_RXF_PAGE_SIZE, ALE_RX_PAGE_SZ); 1687 1688 /* Tell hardware that we're ready to load DMA blocks. */ 1689 CSR_WRITE_4(sc, ALE_DMA_BLOCK, DMA_BLOCK_LOAD); 1690 1691 /* Set Rx/Tx interrupt trigger threshold. */ 1692 CSR_WRITE_4(sc, ALE_INT_TRIG_THRESH, (1 << INT_TRIG_RX_THRESH_SHIFT) | 1693 (4 << INT_TRIG_TX_THRESH_SHIFT)); 1694 /* 1695 * XXX 1696 * Set interrupt trigger timer, its purpose and relation 1697 * with interrupt moderation mechanism is not clear yet. 1698 */ 1699 CSR_WRITE_4(sc, ALE_INT_TRIG_TIMER, 1700 ((ALE_USECS(10) << INT_TRIG_RX_TIMER_SHIFT) | 1701 (ALE_USECS(1000) << INT_TRIG_TX_TIMER_SHIFT))); 1702 1703 /* Configure interrupt moderation timer. */ 1704 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT; 1705 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT; 1706 reg = ALE_USECS(sc->ale_int_rx_mod) << IM_TIMER_RX_SHIFT; 1707 reg |= ALE_USECS(sc->ale_int_tx_mod) << IM_TIMER_TX_SHIFT; 1708 CSR_WRITE_4(sc, ALE_IM_TIMER, reg); 1709 reg = CSR_READ_4(sc, ALE_MASTER_CFG); 1710 reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK); 1711 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); 1712 if (ALE_USECS(sc->ale_int_rx_mod) != 0) 1713 reg |= MASTER_IM_RX_TIMER_ENB; 1714 if (ALE_USECS(sc->ale_int_tx_mod) != 0) 1715 reg |= MASTER_IM_TX_TIMER_ENB; 1716 CSR_WRITE_4(sc, ALE_MASTER_CFG, reg); 1717 CSR_WRITE_2(sc, ALE_INTR_CLR_TIMER, ALE_USECS(1000)); 1718 1719 /* Set Maximum frame size of controller. */ 1720 if (ifp->if_mtu < ETHERMTU) 1721 sc->ale_max_frame_size = ETHERMTU; 1722 else 1723 sc->ale_max_frame_size = ifp->if_mtu; 1724 sc->ale_max_frame_size += ETHER_HDR_LEN + EVL_ENCAPLEN + ETHER_CRC_LEN; 1725 CSR_WRITE_4(sc, ALE_FRAME_SIZE, sc->ale_max_frame_size); 1726 1727 /* Configure IPG/IFG parameters. */ 1728 CSR_WRITE_4(sc, ALE_IPG_IFG_CFG, 1729 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) | 1730 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 1731 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 1732 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK)); 1733 1734 /* Set parameters for half-duplex media. */ 1735 CSR_WRITE_4(sc, ALE_HDPX_CFG, 1736 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 1737 HDPX_CFG_LCOL_MASK) | 1738 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 1739 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 1740 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 1741 HDPX_CFG_ABEBT_MASK) | 1742 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 1743 HDPX_CFG_JAMIPG_MASK)); 1744 1745 /* Configure Tx jumbo frame parameters. */ 1746 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 1747 if (ifp->if_mtu < ETHERMTU) 1748 reg = sc->ale_max_frame_size; 1749 else if (ifp->if_mtu < 6 * 1024) 1750 reg = (sc->ale_max_frame_size * 2) / 3; 1751 else 1752 reg = sc->ale_max_frame_size / 2; 1753 CSR_WRITE_4(sc, ALE_TX_JUMBO_THRESH, 1754 roundup(reg, TX_JUMBO_THRESH_UNIT) >> 1755 TX_JUMBO_THRESH_UNIT_SHIFT); 1756 } 1757 1758 /* Configure TxQ. */ 1759 reg = (128 << (sc->ale_dma_rd_burst >> DMA_CFG_RD_BURST_SHIFT)) 1760 << TXQ_CFG_TX_FIFO_BURST_SHIFT; 1761 reg |= (TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 1762 TXQ_CFG_TPD_BURST_MASK; 1763 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE | TXQ_CFG_ENB); 1764 1765 /* Configure Rx jumbo frame & flow control parameters. */ 1766 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 1767 reg = roundup(sc->ale_max_frame_size, RX_JUMBO_THRESH_UNIT); 1768 CSR_WRITE_4(sc, ALE_RX_JUMBO_THRESH, 1769 (((reg >> RX_JUMBO_THRESH_UNIT_SHIFT) << 1770 RX_JUMBO_THRESH_MASK_SHIFT) & RX_JUMBO_THRESH_MASK) | 1771 ((RX_JUMBO_LKAH_DEFAULT << RX_JUMBO_LKAH_SHIFT) & 1772 RX_JUMBO_LKAH_MASK)); 1773 reg = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 1774 rxf_hi = (reg * 7) / 10; 1775 rxf_lo = (reg * 3)/ 10; 1776 CSR_WRITE_4(sc, ALE_RX_FIFO_PAUSE_THRESH, 1777 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 1778 RX_FIFO_PAUSE_THRESH_LO_MASK) | 1779 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 1780 RX_FIFO_PAUSE_THRESH_HI_MASK)); 1781 } 1782 1783 /* Disable RSS. */ 1784 CSR_WRITE_4(sc, ALE_RSS_IDT_TABLE0, 0); 1785 CSR_WRITE_4(sc, ALE_RSS_CPU, 0); 1786 1787 /* Configure RxQ. */ 1788 CSR_WRITE_4(sc, ALE_RXQ_CFG, 1789 RXQ_CFG_ALIGN_32 | RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 1790 1791 /* Configure DMA parameters. */ 1792 reg = 0; 1793 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) 1794 reg |= DMA_CFG_TXCMB_ENB; 1795 CSR_WRITE_4(sc, ALE_DMA_CFG, 1796 DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI | DMA_CFG_RCB_64 | 1797 sc->ale_dma_rd_burst | reg | 1798 sc->ale_dma_wr_burst | DMA_CFG_RXCMB_ENB | 1799 ((DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 1800 DMA_CFG_RD_DELAY_CNT_MASK) | 1801 ((DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 1802 DMA_CFG_WR_DELAY_CNT_MASK)); 1803 1804 /* 1805 * Hardware can be configured to issue SMB interrupt based 1806 * on programmed interval. Since there is a callout that is 1807 * invoked for every hz in driver we use that instead of 1808 * relying on periodic SMB interrupt. 1809 */ 1810 CSR_WRITE_4(sc, ALE_SMB_STAT_TIMER, ALE_USECS(0)); 1811 1812 /* Clear MAC statistics. */ 1813 ale_stats_clear(sc); 1814 1815 /* 1816 * Configure Tx/Rx MACs. 1817 * - Auto-padding for short frames. 1818 * - Enable CRC generation. 1819 * Actual reconfiguration of MAC for resolved speed/duplex 1820 * is followed after detection of link establishment. 1821 * AR81xx always does checksum computation regardless of 1822 * MAC_CFG_RXCSUM_ENB bit. In fact, setting the bit will 1823 * cause Rx handling issue for fragmented IP datagrams due 1824 * to silicon bug. 1825 */ 1826 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 1827 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 1828 MAC_CFG_PREAMBLE_MASK); 1829 if ((sc->ale_flags & ALE_FLAG_FASTETHER) != 0) 1830 reg |= MAC_CFG_SPEED_10_100; 1831 else 1832 reg |= MAC_CFG_SPEED_1000; 1833 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1834 1835 /* Set up the receive filter. */ 1836 ale_iff(sc); 1837 1838 ale_rxvlan(sc); 1839 1840 /* Acknowledge all pending interrupts and clear it. */ 1841 CSR_WRITE_4(sc, ALE_INTR_MASK, ALE_INTRS); 1842 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 1843 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0); 1844 1845 sc->ale_flags &= ~ALE_FLAG_LINK; 1846 1847 /* Switch to the current media. */ 1848 mii = &sc->sc_miibus; 1849 mii_mediachg(mii); 1850 1851 timeout_add_sec(&sc->ale_tick_ch, 1); 1852 1853 ifp->if_flags |= IFF_RUNNING; 1854 ifp->if_flags &= ~IFF_OACTIVE; 1855 1856 return 0; 1857 } 1858 1859 void 1860 ale_stop(struct ale_softc *sc) 1861 { 1862 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1863 struct ale_txdesc *txd; 1864 uint32_t reg; 1865 int i; 1866 1867 /* 1868 * Mark the interface down and cancel the watchdog timer. 1869 */ 1870 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1871 ifp->if_timer = 0; 1872 1873 timeout_del(&sc->ale_tick_ch); 1874 sc->ale_flags &= ~ALE_FLAG_LINK; 1875 1876 ale_stats_update(sc); 1877 1878 /* Disable interrupts. */ 1879 CSR_WRITE_4(sc, ALE_INTR_MASK, 0); 1880 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 1881 1882 /* Disable queue processing and DMA. */ 1883 reg = CSR_READ_4(sc, ALE_TXQ_CFG); 1884 reg &= ~TXQ_CFG_ENB; 1885 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg); 1886 reg = CSR_READ_4(sc, ALE_RXQ_CFG); 1887 reg &= ~RXQ_CFG_ENB; 1888 CSR_WRITE_4(sc, ALE_RXQ_CFG, reg); 1889 reg = CSR_READ_4(sc, ALE_DMA_CFG); 1890 reg &= ~(DMA_CFG_TXCMB_ENB | DMA_CFG_RXCMB_ENB); 1891 CSR_WRITE_4(sc, ALE_DMA_CFG, reg); 1892 DELAY(1000); 1893 1894 /* Stop Rx/Tx MACs. */ 1895 ale_stop_mac(sc); 1896 1897 /* Disable interrupts again? XXX */ 1898 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 1899 1900 /* 1901 * Free TX mbufs still in the queues. 1902 */ 1903 for (i = 0; i < ALE_TX_RING_CNT; i++) { 1904 txd = &sc->ale_cdata.ale_txdesc[i]; 1905 if (txd->tx_m != NULL) { 1906 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1907 m_freem(txd->tx_m); 1908 txd->tx_m = NULL; 1909 } 1910 } 1911 } 1912 1913 void 1914 ale_stop_mac(struct ale_softc *sc) 1915 { 1916 uint32_t reg; 1917 int i; 1918 1919 reg = CSR_READ_4(sc, ALE_MAC_CFG); 1920 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 1921 reg &= ~MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 1922 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1923 } 1924 1925 for (i = ALE_TIMEOUT; i > 0; i--) { 1926 reg = CSR_READ_4(sc, ALE_IDLE_STATUS); 1927 if (reg == 0) 1928 break; 1929 DELAY(10); 1930 } 1931 if (i == 0) 1932 printf("%s: could not disable Tx/Rx MAC(0x%08x)!\n", 1933 sc->sc_dev.dv_xname, reg); 1934 } 1935 1936 void 1937 ale_init_tx_ring(struct ale_softc *sc) 1938 { 1939 struct ale_txdesc *txd; 1940 int i; 1941 1942 sc->ale_cdata.ale_tx_prod = 0; 1943 sc->ale_cdata.ale_tx_cons = 0; 1944 sc->ale_cdata.ale_tx_cnt = 0; 1945 1946 bzero(sc->ale_cdata.ale_tx_ring, ALE_TX_RING_SZ); 1947 bzero(sc->ale_cdata.ale_tx_cmb, ALE_TX_CMB_SZ); 1948 for (i = 0; i < ALE_TX_RING_CNT; i++) { 1949 txd = &sc->ale_cdata.ale_txdesc[i]; 1950 txd->tx_m = NULL; 1951 } 1952 *sc->ale_cdata.ale_tx_cmb = 0; 1953 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map, 0, 1954 sc->ale_cdata.ale_tx_cmb_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1955 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map, 0, 1956 sc->ale_cdata.ale_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1957 } 1958 1959 void 1960 ale_init_rx_pages(struct ale_softc *sc) 1961 { 1962 struct ale_rx_page *rx_page; 1963 int i; 1964 1965 sc->ale_cdata.ale_rx_seqno = 0; 1966 sc->ale_cdata.ale_rx_curp = 0; 1967 1968 for (i = 0; i < ALE_RX_PAGES; i++) { 1969 rx_page = &sc->ale_cdata.ale_rx_page[i]; 1970 bzero(rx_page->page_addr, sc->ale_pagesize); 1971 bzero(rx_page->cmb_addr, ALE_RX_CMB_SZ); 1972 rx_page->cons = 0; 1973 *rx_page->cmb_addr = 0; 1974 bus_dmamap_sync(sc->sc_dmat, rx_page->page_map, 0, 1975 rx_page->page_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1976 bus_dmamap_sync(sc->sc_dmat, rx_page->cmb_map, 0, 1977 rx_page->cmb_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1978 } 1979 } 1980 1981 void 1982 ale_rxvlan(struct ale_softc *sc) 1983 { 1984 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1985 uint32_t reg; 1986 1987 reg = CSR_READ_4(sc, ALE_MAC_CFG); 1988 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 1989 if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) 1990 reg |= MAC_CFG_VLAN_TAG_STRIP; 1991 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1992 } 1993 1994 void 1995 ale_iff(struct ale_softc *sc) 1996 { 1997 struct arpcom *ac = &sc->sc_arpcom; 1998 struct ifnet *ifp = &ac->ac_if; 1999 struct ether_multi *enm; 2000 struct ether_multistep step; 2001 uint32_t crc; 2002 uint32_t mchash[2]; 2003 uint32_t rxcfg; 2004 2005 rxcfg = CSR_READ_4(sc, ALE_MAC_CFG); 2006 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 2007 ifp->if_flags &= ~IFF_ALLMULTI; 2008 2009 /* 2010 * Always accept broadcast frames. 2011 */ 2012 rxcfg |= MAC_CFG_BCAST; 2013 2014 if (ifp->if_flags & IFF_PROMISC || ac->ac_multirangecnt > 0) { 2015 ifp->if_flags |= IFF_ALLMULTI; 2016 if (ifp->if_flags & IFF_PROMISC) 2017 rxcfg |= MAC_CFG_PROMISC; 2018 else 2019 rxcfg |= MAC_CFG_ALLMULTI; 2020 mchash[0] = mchash[1] = 0xFFFFFFFF; 2021 } else { 2022 /* Program new filter. */ 2023 bzero(mchash, sizeof(mchash)); 2024 2025 ETHER_FIRST_MULTI(step, ac, enm); 2026 while (enm != NULL) { 2027 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2028 2029 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 2030 2031 ETHER_NEXT_MULTI(step, enm); 2032 } 2033 } 2034 2035 CSR_WRITE_4(sc, ALE_MAR0, mchash[0]); 2036 CSR_WRITE_4(sc, ALE_MAR1, mchash[1]); 2037 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg); 2038 } 2039