1 /* $OpenBSD: if_ale.c,v 1.4 2009/03/29 21:53:52 sthen Exp $ */ 2 /*- 3 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: src/sys/dev/ale/if_ale.c,v 1.3 2008/12/03 09:01:12 yongari Exp $ 29 */ 30 31 /* Driver for Atheros AR8121/AR8113/AR8114 PCIe Ethernet. */ 32 33 #include "bpfilter.h" 34 #include "vlan.h" 35 36 #include <sys/param.h> 37 #include <sys/proc.h> 38 #include <sys/endian.h> 39 #include <sys/systm.h> 40 #include <sys/types.h> 41 #include <sys/sockio.h> 42 #include <sys/mbuf.h> 43 #include <sys/queue.h> 44 #include <sys/kernel.h> 45 #include <sys/device.h> 46 #include <sys/timeout.h> 47 #include <sys/socket.h> 48 49 #include <machine/bus.h> 50 51 #include <net/if.h> 52 #include <net/if_dl.h> 53 #include <net/if_llc.h> 54 #include <net/if_media.h> 55 56 #ifdef INET 57 #include <netinet/in.h> 58 #include <netinet/in_systm.h> 59 #include <netinet/in_var.h> 60 #include <netinet/ip.h> 61 #include <netinet/if_ether.h> 62 #endif 63 64 #include <net/if_types.h> 65 #include <net/if_vlan_var.h> 66 67 #if NBPFILTER > 0 68 #include <net/bpf.h> 69 #endif 70 71 #include <dev/rndvar.h> 72 73 #include <dev/mii/mii.h> 74 #include <dev/mii/miivar.h> 75 76 #include <dev/pci/pcireg.h> 77 #include <dev/pci/pcivar.h> 78 #include <dev/pci/pcidevs.h> 79 80 #include <dev/pci/if_alereg.h> 81 82 int ale_match(struct device *, void *, void *); 83 void ale_attach(struct device *, struct device *, void *); 84 int ale_detach(struct device *, int); 85 86 int ale_miibus_readreg(struct device *, int, int); 87 void ale_miibus_writereg(struct device *, int, int, int); 88 void ale_miibus_statchg(struct device *); 89 90 int ale_init(struct ifnet *); 91 void ale_start(struct ifnet *); 92 int ale_ioctl(struct ifnet *, u_long, caddr_t); 93 void ale_watchdog(struct ifnet *); 94 int ale_mediachange(struct ifnet *); 95 void ale_mediastatus(struct ifnet *, struct ifmediareq *); 96 97 int ale_intr(void *); 98 int ale_rxeof(struct ale_softc *sc); 99 void ale_rx_update_page(struct ale_softc *, struct ale_rx_page **, 100 uint32_t, uint32_t *); 101 void ale_rxcsum(struct ale_softc *, struct mbuf *, uint32_t); 102 void ale_txeof(struct ale_softc *); 103 104 int ale_dma_alloc(struct ale_softc *); 105 void ale_dma_free(struct ale_softc *); 106 int ale_encap(struct ale_softc *, struct mbuf **); 107 void ale_init_rx_pages(struct ale_softc *); 108 void ale_init_tx_ring(struct ale_softc *); 109 110 void ale_stop(struct ale_softc *); 111 void ale_tick(void *); 112 void ale_get_macaddr(struct ale_softc *); 113 void ale_mac_config(struct ale_softc *); 114 void ale_phy_reset(struct ale_softc *); 115 void ale_reset(struct ale_softc *); 116 void ale_rxfilter(struct ale_softc *); 117 void ale_rxvlan(struct ale_softc *); 118 void ale_stats_clear(struct ale_softc *); 119 void ale_stats_update(struct ale_softc *); 120 void ale_stop_mac(struct ale_softc *); 121 122 const struct pci_matchid ale_devices[] = { 123 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L1E } 124 }; 125 126 struct cfattach ale_ca = { 127 sizeof (struct ale_softc), ale_match, ale_attach 128 }; 129 130 struct cfdriver ale_cd = { 131 NULL, "ale", DV_IFNET 132 }; 133 134 int aledebug = 0; 135 #define DPRINTF(x) do { if (aledebug) printf x; } while (0) 136 137 #define ALE_CSUM_FEATURES (M_TCPV4_CSUM_OUT | M_UDPV4_CSUM_OUT) 138 139 int 140 ale_miibus_readreg(struct device *dev, int phy, int reg) 141 { 142 struct ale_softc *sc = (struct ale_softc *)dev; 143 uint32_t v; 144 int i; 145 146 if (phy != sc->ale_phyaddr) 147 return (0); 148 149 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 150 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 151 for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 152 DELAY(5); 153 v = CSR_READ_4(sc, ALE_MDIO); 154 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 155 break; 156 } 157 158 if (i == 0) { 159 printf("%s: phy read timeout: phy %d, reg %d\n", 160 sc->sc_dev.dv_xname, phy, reg); 161 return (0); 162 } 163 164 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 165 } 166 167 void 168 ale_miibus_writereg(struct device *dev, int phy, int reg, int val) 169 { 170 struct ale_softc *sc = (struct ale_softc *)dev; 171 uint32_t v; 172 int i; 173 174 if (phy != sc->ale_phyaddr) 175 return; 176 177 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 178 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 179 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 180 for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 181 DELAY(5); 182 v = CSR_READ_4(sc, ALE_MDIO); 183 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 184 break; 185 } 186 187 if (i == 0) 188 printf("%s: phy write timeout: phy %d, reg %d\n", 189 sc->sc_dev.dv_xname, phy, reg); 190 } 191 192 void 193 ale_miibus_statchg(struct device *dev) 194 { 195 struct ale_softc *sc = (struct ale_softc *)dev; 196 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 197 struct mii_data *mii; 198 uint32_t reg; 199 200 if ((ifp->if_flags & IFF_RUNNING) == 0) 201 return; 202 203 mii = &sc->sc_miibus; 204 205 sc->ale_flags &= ~ALE_FLAG_LINK; 206 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 207 (IFM_ACTIVE | IFM_AVALID)) { 208 switch (IFM_SUBTYPE(mii->mii_media_active)) { 209 case IFM_10_T: 210 case IFM_100_TX: 211 sc->ale_flags |= ALE_FLAG_LINK; 212 break; 213 214 case IFM_1000_T: 215 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0) 216 sc->ale_flags |= ALE_FLAG_LINK; 217 break; 218 219 default: 220 break; 221 } 222 } 223 224 /* Stop Rx/Tx MACs. */ 225 ale_stop_mac(sc); 226 227 /* Program MACs with resolved speed/duplex/flow-control. */ 228 if ((sc->ale_flags & ALE_FLAG_LINK) != 0) { 229 ale_mac_config(sc); 230 /* Reenable Tx/Rx MACs. */ 231 reg = CSR_READ_4(sc, ALE_MAC_CFG); 232 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 233 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 234 } 235 } 236 237 void 238 ale_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 239 { 240 struct ale_softc *sc = ifp->if_softc; 241 struct mii_data *mii = &sc->sc_miibus; 242 243 mii_pollstat(mii); 244 ifmr->ifm_status = mii->mii_media_status; 245 ifmr->ifm_active = mii->mii_media_active; 246 } 247 248 int 249 ale_mediachange(struct ifnet *ifp) 250 { 251 struct ale_softc *sc = ifp->if_softc; 252 struct mii_data *mii = &sc->sc_miibus; 253 int error; 254 255 if (mii->mii_instance != 0) { 256 struct mii_softc *miisc; 257 258 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 259 mii_phy_reset(miisc); 260 } 261 error = mii_mediachg(mii); 262 263 return (error); 264 } 265 266 int 267 ale_match(struct device *dev, void *match, void *aux) 268 { 269 return pci_matchbyid((struct pci_attach_args *)aux, ale_devices, 270 sizeof (ale_devices) / sizeof (ale_devices[0])); 271 } 272 273 void 274 ale_get_macaddr(struct ale_softc *sc) 275 { 276 uint32_t ea[2], reg; 277 int i, vpdc; 278 279 reg = CSR_READ_4(sc, ALE_SPI_CTRL); 280 if ((reg & SPI_VPD_ENB) != 0) { 281 reg &= ~SPI_VPD_ENB; 282 CSR_WRITE_4(sc, ALE_SPI_CTRL, reg); 283 } 284 285 if (pci_get_capability(sc->sc_pct, sc->sc_pcitag, PCI_CAP_VPD, 286 &vpdc, NULL)) { 287 /* 288 * PCI VPD capability found, let TWSI reload EEPROM. 289 * This will set ethernet address of controller. 290 */ 291 CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) | 292 TWSI_CTRL_SW_LD_START); 293 for (i = 100; i > 0; i--) { 294 DELAY(1000); 295 reg = CSR_READ_4(sc, ALE_TWSI_CTRL); 296 if ((reg & TWSI_CTRL_SW_LD_START) == 0) 297 break; 298 } 299 if (i == 0) 300 printf("%s: reloading EEPROM timeout!\n", 301 sc->sc_dev.dv_xname); 302 } else { 303 if (aledebug) 304 printf("%s: PCI VPD capability not found!\n", 305 sc->sc_dev.dv_xname); 306 } 307 308 ea[0] = CSR_READ_4(sc, ALE_PAR0); 309 ea[1] = CSR_READ_4(sc, ALE_PAR1); 310 sc->ale_eaddr[0] = (ea[1] >> 8) & 0xFF; 311 sc->ale_eaddr[1] = (ea[1] >> 0) & 0xFF; 312 sc->ale_eaddr[2] = (ea[0] >> 24) & 0xFF; 313 sc->ale_eaddr[3] = (ea[0] >> 16) & 0xFF; 314 sc->ale_eaddr[4] = (ea[0] >> 8) & 0xFF; 315 sc->ale_eaddr[5] = (ea[0] >> 0) & 0xFF; 316 } 317 318 void 319 ale_phy_reset(struct ale_softc *sc) 320 { 321 /* Reset magic from Linux. */ 322 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 323 GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET | 324 GPHY_CTRL_PHY_PLL_ON); 325 DELAY(1000); 326 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 327 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | 328 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_PLL_ON); 329 DELAY(1000); 330 331 #define ATPHY_DBG_ADDR 0x1D 332 #define ATPHY_DBG_DATA 0x1E 333 334 /* Enable hibernation mode. */ 335 ale_miibus_writereg(&sc->sc_dev, sc->ale_phyaddr, 336 ATPHY_DBG_ADDR, 0x0B); 337 ale_miibus_writereg(&sc->sc_dev, sc->ale_phyaddr, 338 ATPHY_DBG_DATA, 0xBC00); 339 /* Set Class A/B for all modes. */ 340 ale_miibus_writereg(&sc->sc_dev, sc->ale_phyaddr, 341 ATPHY_DBG_ADDR, 0x00); 342 ale_miibus_writereg(&sc->sc_dev, sc->ale_phyaddr, 343 ATPHY_DBG_DATA, 0x02EF); 344 /* Enable 10BT power saving. */ 345 ale_miibus_writereg(&sc->sc_dev, sc->ale_phyaddr, 346 ATPHY_DBG_ADDR, 0x12); 347 ale_miibus_writereg(&sc->sc_dev, sc->ale_phyaddr, 348 ATPHY_DBG_DATA, 0x4C04); 349 /* Adjust 1000T power. */ 350 ale_miibus_writereg(&sc->sc_dev, sc->ale_phyaddr, 351 ATPHY_DBG_ADDR, 0x04); 352 ale_miibus_writereg(&sc->sc_dev, sc->ale_phyaddr, 353 ATPHY_DBG_ADDR, 0x8BBB); 354 /* 10BT center tap voltage. */ 355 ale_miibus_writereg(&sc->sc_dev, sc->ale_phyaddr, 356 ATPHY_DBG_ADDR, 0x05); 357 ale_miibus_writereg(&sc->sc_dev, sc->ale_phyaddr, 358 ATPHY_DBG_ADDR, 0x2C46); 359 360 #undef ATPHY_DBG_ADDR 361 #undef ATPHY_DBG_DATA 362 DELAY(1000); 363 } 364 365 void 366 ale_attach(struct device *parent, struct device *self, void *aux) 367 { 368 struct ale_softc *sc = (struct ale_softc *)self; 369 struct pci_attach_args *pa = aux; 370 pci_chipset_tag_t pc = pa->pa_pc; 371 pci_intr_handle_t ih; 372 const char *intrstr; 373 struct ifnet *ifp; 374 pcireg_t memtype; 375 int error = 0; 376 uint32_t rxf_len, txf_len; 377 378 /* 379 * Allocate IO memory 380 */ 381 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, ALE_PCIR_BAR); 382 if (pci_mapreg_map(pa, ALE_PCIR_BAR, memtype, 0, &sc->sc_mem_bt, 383 &sc->sc_mem_bh, NULL, &sc->sc_mem_size, 0)) { 384 printf(": can't map mem space\n"); 385 return; 386 } 387 388 if (pci_intr_map(pa, &ih) != 0) { 389 printf(": can't map interrupt\n"); 390 goto fail; 391 } 392 393 /* 394 * Allocate IRQ 395 */ 396 intrstr = pci_intr_string(pc, ih); 397 sc->sc_irq_handle = pci_intr_establish(pc, ih, IPL_NET, ale_intr, sc, 398 sc->sc_dev.dv_xname); 399 if (sc->sc_irq_handle == NULL) { 400 printf(": could not establish interrupt"); 401 if (intrstr != NULL) 402 printf(" at %s", intrstr); 403 printf("\n"); 404 goto fail; 405 } 406 printf(": %s", intrstr); 407 408 sc->sc_dmat = pa->pa_dmat; 409 sc->sc_pct = pa->pa_pc; 410 sc->sc_pcitag = pa->pa_tag; 411 412 /* Set PHY address. */ 413 sc->ale_phyaddr = ALE_PHY_ADDR; 414 415 /* Reset PHY. */ 416 ale_phy_reset(sc); 417 418 /* Reset the ethernet controller. */ 419 ale_reset(sc); 420 421 /* Get PCI and chip id/revision. */ 422 sc->ale_rev = PCI_REVISION(pa->pa_class); 423 if (sc->ale_rev >= 0xF0) { 424 /* L2E Rev. B. AR8114 */ 425 sc->ale_flags |= ALE_FLAG_FASTETHER; 426 } else { 427 if ((CSR_READ_4(sc, ALE_PHY_STATUS) & PHY_STATUS_100M) != 0) { 428 /* L1E AR8121 */ 429 sc->ale_flags |= ALE_FLAG_JUMBO; 430 } else { 431 /* L2E Rev. A. AR8113 */ 432 sc->ale_flags |= ALE_FLAG_FASTETHER; 433 } 434 } 435 436 /* 437 * All known controllers seems to require 4 bytes alignment 438 * of Tx buffers to make Tx checksum offload with custom 439 * checksum generation method work. 440 */ 441 sc->ale_flags |= ALE_FLAG_TXCSUM_BUG; 442 443 /* 444 * All known controllers seems to have issues on Rx checksum 445 * offload for fragmented IP datagrams. 446 */ 447 sc->ale_flags |= ALE_FLAG_RXCSUM_BUG; 448 449 /* 450 * Don't use Tx CMB. It is known to cause RRS update failure 451 * under certain circumstances. Typical phenomenon of the 452 * issue would be unexpected sequence number encountered in 453 * Rx handler. 454 */ 455 sc->ale_flags |= ALE_FLAG_TXCMB_BUG; 456 sc->ale_chip_rev = CSR_READ_4(sc, ALE_MASTER_CFG) >> 457 MASTER_CHIP_REV_SHIFT; 458 if (aledebug) { 459 printf("%s: PCI device revision : 0x%04x\n", 460 sc->sc_dev.dv_xname, sc->ale_rev); 461 printf("%s: Chip id/revision : 0x%04x\n", 462 sc->sc_dev.dv_xname, sc->ale_chip_rev); 463 } 464 465 /* 466 * Uninitialized hardware returns an invalid chip id/revision 467 * as well as 0xFFFFFFFF for Tx/Rx fifo length. 468 */ 469 txf_len = CSR_READ_4(sc, ALE_SRAM_TX_FIFO_LEN); 470 rxf_len = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 471 if (sc->ale_chip_rev == 0xFFFF || txf_len == 0xFFFFFFFF || 472 rxf_len == 0xFFFFFFF) { 473 printf("%s: chip revision : 0x%04x, %u Tx FIFO " 474 "%u Rx FIFO -- not initialized?\n", sc->sc_dev.dv_xname, 475 sc->ale_chip_rev, txf_len, rxf_len); 476 goto fail; 477 } 478 479 if (aledebug) { 480 printf("%s: %u Tx FIFO, %u Rx FIFO\n", sc->sc_dev.dv_xname, 481 txf_len, rxf_len); 482 } 483 484 /* Set max allowable DMA size. */ 485 sc->ale_dma_rd_burst = DMA_CFG_RD_BURST_128; 486 sc->ale_dma_wr_burst = DMA_CFG_WR_BURST_128; 487 488 error = ale_dma_alloc(sc); 489 if (error) 490 goto fail; 491 492 /* Load station address. */ 493 ale_get_macaddr(sc); 494 495 ifp = &sc->sc_arpcom.ac_if; 496 ifp->if_softc = sc; 497 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 498 ifp->if_init = ale_init; 499 ifp->if_ioctl = ale_ioctl; 500 ifp->if_start = ale_start; 501 ifp->if_watchdog = ale_watchdog; 502 ifp->if_baudrate = IF_Gbps(1); 503 IFQ_SET_MAXLEN(&ifp->if_snd, ALE_TX_RING_CNT - 1); 504 IFQ_SET_READY(&ifp->if_snd); 505 bcopy(sc->ale_eaddr, sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN); 506 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 507 508 ifp->if_capabilities = IFCAP_VLAN_MTU; 509 510 #ifdef ALE_CHECKSUM 511 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 512 IFCAP_CSUM_UDPv4; 513 #endif 514 515 #if NVLAN > 0 516 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 517 #endif 518 519 printf(", address %s\n", ether_sprintf(sc->sc_arpcom.ac_enaddr)); 520 521 /* Set up MII bus. */ 522 sc->sc_miibus.mii_ifp = ifp; 523 sc->sc_miibus.mii_readreg = ale_miibus_readreg; 524 sc->sc_miibus.mii_writereg = ale_miibus_writereg; 525 sc->sc_miibus.mii_statchg = ale_miibus_statchg; 526 527 ifmedia_init(&sc->sc_miibus.mii_media, 0, ale_mediachange, 528 ale_mediastatus); 529 mii_attach(self, &sc->sc_miibus, 0xffffffff, MII_PHY_ANY, 530 MII_OFFSET_ANY, 0); 531 532 if (LIST_FIRST(&sc->sc_miibus.mii_phys) == NULL) { 533 printf("%s: no PHY found!\n", sc->sc_dev.dv_xname); 534 ifmedia_add(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL, 535 0, NULL); 536 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL); 537 } else 538 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_AUTO); 539 540 if_attach(ifp); 541 ether_ifattach(ifp); 542 543 timeout_set(&sc->ale_tick_ch, ale_tick, sc); 544 545 return; 546 fail: 547 ale_dma_free(sc); 548 if (sc->sc_irq_handle != NULL) 549 pci_intr_disestablish(pc, sc->sc_irq_handle); 550 if (sc->sc_mem_size) 551 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 552 } 553 554 int 555 ale_detach(struct device *self, int flags) 556 { 557 struct ale_softc *sc = (struct ale_softc *)self; 558 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 559 int s; 560 561 s = splnet(); 562 ale_stop(sc); 563 splx(s); 564 565 mii_detach(&sc->sc_miibus, MII_PHY_ANY, MII_OFFSET_ANY); 566 567 /* Delete all remaining media. */ 568 ifmedia_delete_instance(&sc->sc_miibus.mii_media, IFM_INST_ANY); 569 570 ether_ifdetach(ifp); 571 if_detach(ifp); 572 ale_dma_free(sc); 573 574 if (sc->sc_irq_handle != NULL) { 575 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 576 sc->sc_irq_handle = NULL; 577 } 578 579 return (0); 580 } 581 582 583 int 584 ale_dma_alloc(struct ale_softc *sc) 585 { 586 struct ale_txdesc *txd; 587 int nsegs, error, guard_size, i; 588 589 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) 590 guard_size = ALE_JUMBO_FRAMELEN; 591 else 592 guard_size = ALE_MAX_FRAMELEN; 593 sc->ale_pagesize = roundup(guard_size + ALE_RX_PAGE_SZ, 594 ALE_RX_PAGE_ALIGN); 595 596 /* 597 * Create DMA stuffs for TX ring 598 */ 599 error = bus_dmamap_create(sc->sc_dmat, ALE_TX_RING_SZ, 1, 600 ALE_TX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->ale_cdata.ale_tx_ring_map); 601 if (error) 602 return (ENOBUFS); 603 604 /* Allocate DMA'able memory for TX ring */ 605 error = bus_dmamem_alloc(sc->sc_dmat, ALE_TX_RING_SZ, 606 ETHER_ALIGN, 0, &sc->ale_cdata.ale_tx_ring_seg, 1, 607 &nsegs, BUS_DMA_WAITOK); 608 if (error) { 609 printf("%s: could not allocate DMA'able memory for Tx ring.\n", 610 sc->sc_dev.dv_xname); 611 return error; 612 } 613 614 error = bus_dmamem_map(sc->sc_dmat, &sc->ale_cdata.ale_tx_ring_seg, 615 nsegs, ALE_TX_RING_SZ, (caddr_t *)&sc->ale_cdata.ale_tx_ring, 616 BUS_DMA_NOWAIT); 617 if (error) 618 return (ENOBUFS); 619 620 bzero(sc->ale_cdata.ale_tx_ring, ALE_TX_RING_SZ); 621 622 /* Load the DMA map for Tx ring. */ 623 error = bus_dmamap_load(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map, 624 sc->ale_cdata.ale_tx_ring, ALE_TX_RING_SZ, NULL, BUS_DMA_WAITOK); 625 if (error) { 626 printf("%s: could not load DMA'able memory for Tx ring.\n", 627 sc->sc_dev.dv_xname); 628 bus_dmamem_free(sc->sc_dmat, 629 (bus_dma_segment_t *)&sc->ale_cdata.ale_tx_ring, 1); 630 return error; 631 } 632 sc->ale_cdata.ale_tx_ring_paddr = 633 sc->ale_cdata.ale_tx_ring_map->dm_segs[0].ds_addr; 634 635 for (i = 0; i < ALE_RX_PAGES; i++) { 636 /* 637 * Create DMA stuffs for RX pages 638 */ 639 error = bus_dmamap_create(sc->sc_dmat, sc->ale_pagesize, 1, 640 sc->ale_pagesize, 0, BUS_DMA_NOWAIT, 641 &sc->ale_cdata.ale_rx_page[i].page_map); 642 if (error) 643 return (ENOBUFS); 644 645 /* Allocate DMA'able memory for RX pages */ 646 error = bus_dmamem_alloc(sc->sc_dmat, sc->ale_pagesize, 647 ETHER_ALIGN, 0, &sc->ale_cdata.ale_rx_page[i].page_seg, 648 1, &nsegs, BUS_DMA_WAITOK); 649 if (error) { 650 printf("%s: could not allocate DMA'able memory for " 651 "Rx ring.\n", sc->sc_dev.dv_xname); 652 return error; 653 } 654 error = bus_dmamem_map(sc->sc_dmat, 655 &sc->ale_cdata.ale_rx_page[i].page_seg, nsegs, 656 sc->ale_pagesize, 657 (caddr_t *)&sc->ale_cdata.ale_rx_page[i].page_addr, 658 BUS_DMA_NOWAIT); 659 if (error) 660 return (ENOBUFS); 661 662 bzero(sc->ale_cdata.ale_rx_page[i].page_addr, sc->ale_pagesize); 663 664 /* Load the DMA map for Rx pages. */ 665 error = bus_dmamap_load(sc->sc_dmat, 666 sc->ale_cdata.ale_rx_page[i].page_map, 667 sc->ale_cdata.ale_rx_page[i].page_addr, 668 sc->ale_pagesize, NULL, BUS_DMA_WAITOK); 669 if (error) { 670 printf("%s: could not load DMA'able memory for " 671 "Rx pages.\n", sc->sc_dev.dv_xname); 672 bus_dmamem_free(sc->sc_dmat, 673 (bus_dma_segment_t *)sc->ale_cdata.ale_rx_page[i].page_addr, 1); 674 return error; 675 } 676 sc->ale_cdata.ale_rx_page[i].page_paddr = 677 sc->ale_cdata.ale_rx_page[i].page_map->dm_segs[0].ds_addr; 678 } 679 680 /* 681 * Create DMA stuffs for Tx CMB. 682 */ 683 error = bus_dmamap_create(sc->sc_dmat, ALE_TX_CMB_SZ, 1, 684 ALE_TX_CMB_SZ, 0, BUS_DMA_NOWAIT, &sc->ale_cdata.ale_tx_cmb_map); 685 if (error) 686 return (ENOBUFS); 687 688 /* Allocate DMA'able memory for Tx CMB. */ 689 error = bus_dmamem_alloc(sc->sc_dmat, ALE_TX_CMB_SZ, ETHER_ALIGN, 0, 690 &sc->ale_cdata.ale_tx_cmb_seg, 1, &nsegs, BUS_DMA_WAITOK); 691 692 if (error) { 693 printf("%s: could not allocate DMA'able memory for Tx CMB.\n", 694 sc->sc_dev.dv_xname); 695 return error; 696 } 697 698 error = bus_dmamem_map(sc->sc_dmat, &sc->ale_cdata.ale_tx_cmb_seg, 699 nsegs, ALE_TX_CMB_SZ, (caddr_t *)&sc->ale_cdata.ale_tx_cmb, 700 BUS_DMA_NOWAIT); 701 if (error) 702 return (ENOBUFS); 703 704 bzero(sc->ale_cdata.ale_tx_cmb, ALE_TX_CMB_SZ); 705 706 /* Load the DMA map for Tx CMB. */ 707 error = bus_dmamap_load(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map, 708 sc->ale_cdata.ale_tx_cmb, ALE_TX_CMB_SZ, NULL, BUS_DMA_WAITOK); 709 if (error) { 710 printf("%s: could not load DMA'able memory for Tx CMB.\n", 711 sc->sc_dev.dv_xname); 712 bus_dmamem_free(sc->sc_dmat, 713 (bus_dma_segment_t *)&sc->ale_cdata.ale_tx_cmb, 1); 714 return error; 715 } 716 717 sc->ale_cdata.ale_tx_cmb_paddr = 718 sc->ale_cdata.ale_tx_cmb_map->dm_segs[0].ds_addr; 719 720 for (i = 0; i < ALE_RX_PAGES; i++) { 721 /* 722 * Create DMA stuffs for Rx CMB. 723 */ 724 error = bus_dmamap_create(sc->sc_dmat, ALE_RX_CMB_SZ, 1, 725 ALE_RX_CMB_SZ, 0, BUS_DMA_NOWAIT, 726 &sc->ale_cdata.ale_rx_page[i].cmb_map); 727 if (error) 728 return (ENOBUFS); 729 730 /* Allocate DMA'able memory for Rx CMB */ 731 error = bus_dmamem_alloc(sc->sc_dmat, ALE_RX_CMB_SZ, 732 ETHER_ALIGN, 0, &sc->ale_cdata.ale_rx_page[i].cmb_seg, 1, 733 &nsegs, BUS_DMA_WAITOK); 734 if (error) { 735 printf("%s: could not allocate DMA'able memory for " 736 "Rx CMB\n", sc->sc_dev.dv_xname); 737 return error; 738 } 739 error = bus_dmamem_map(sc->sc_dmat, 740 &sc->ale_cdata.ale_rx_page[i].cmb_seg, nsegs, 741 ALE_RX_CMB_SZ, 742 (caddr_t *)&sc->ale_cdata.ale_rx_page[i].cmb_addr, 743 BUS_DMA_NOWAIT); 744 if (error) 745 return (ENOBUFS); 746 747 bzero(sc->ale_cdata.ale_rx_page[i].cmb_addr, ALE_RX_CMB_SZ); 748 749 /* Load the DMA map for Rx CMB */ 750 error = bus_dmamap_load(sc->sc_dmat, 751 sc->ale_cdata.ale_rx_page[i].cmb_map, 752 sc->ale_cdata.ale_rx_page[i].cmb_addr, 753 ALE_RX_CMB_SZ, NULL, BUS_DMA_WAITOK); 754 if (error) { 755 printf("%s: could not load DMA'able memory for Rx CMB" 756 "\n", sc->sc_dev.dv_xname); 757 bus_dmamem_free(sc->sc_dmat, 758 (bus_dma_segment_t *)&sc->ale_cdata.ale_rx_page[i].cmb_addr, 1); 759 return error; 760 } 761 sc->ale_cdata.ale_rx_page[i].cmb_paddr = 762 sc->ale_cdata.ale_rx_page[i].cmb_map->dm_segs[0].ds_addr; 763 } 764 765 766 /* Create DMA maps for Tx buffers. */ 767 for (i = 0; i < ALE_TX_RING_CNT; i++) { 768 txd = &sc->ale_cdata.ale_txdesc[i]; 769 txd->tx_m = NULL; 770 txd->tx_dmamap = NULL; 771 error = bus_dmamap_create(sc->sc_dmat, ALE_TSO_MAXSIZE, 772 ALE_MAXTXSEGS, ALE_TSO_MAXSEGSIZE, 0, BUS_DMA_NOWAIT, 773 &txd->tx_dmamap); 774 if (error) { 775 printf("%s: could not create Tx dmamap.\n", 776 sc->sc_dev.dv_xname); 777 return error; 778 } 779 } 780 781 return (0); 782 } 783 784 void 785 ale_dma_free(struct ale_softc *sc) 786 { 787 struct ale_txdesc *txd; 788 int i; 789 790 /* Tx buffers. */ 791 for (i = 0; i < ALE_TX_RING_CNT; i++) { 792 txd = &sc->ale_cdata.ale_txdesc[i]; 793 if (txd->tx_dmamap != NULL) { 794 bus_dmamap_destroy(sc->sc_dmat, txd->tx_dmamap); 795 txd->tx_dmamap = NULL; 796 } 797 } 798 799 /* Tx descriptor ring. */ 800 if (sc->ale_cdata.ale_tx_ring_map != NULL) 801 bus_dmamap_unload(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map); 802 if (sc->ale_cdata.ale_tx_ring_map != NULL && 803 sc->ale_cdata.ale_tx_ring != NULL) 804 bus_dmamem_free(sc->sc_dmat, 805 (bus_dma_segment_t *)sc->ale_cdata.ale_tx_ring, 1); 806 sc->ale_cdata.ale_tx_ring = NULL; 807 sc->ale_cdata.ale_tx_ring_map = NULL; 808 809 /* Rx page block. */ 810 for (i = 0; i < ALE_RX_PAGES; i++) { 811 if (sc->ale_cdata.ale_rx_page[i].page_map != NULL) 812 bus_dmamap_unload(sc->sc_dmat, 813 sc->ale_cdata.ale_rx_page[i].page_map); 814 if (sc->ale_cdata.ale_rx_page[i].page_map != NULL && 815 sc->ale_cdata.ale_rx_page[i].page_addr != NULL) 816 bus_dmamem_free(sc->sc_dmat, 817 (bus_dma_segment_t *)sc->ale_cdata.ale_rx_page[i].page_addr, 1); 818 sc->ale_cdata.ale_rx_page[i].page_addr = NULL; 819 sc->ale_cdata.ale_rx_page[i].page_map = NULL; 820 } 821 822 /* Rx CMB. */ 823 for (i = 0; i < ALE_RX_PAGES; i++) { 824 if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL) 825 bus_dmamap_unload(sc->sc_dmat, 826 sc->ale_cdata.ale_rx_page[i].cmb_map); 827 if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL && 828 sc->ale_cdata.ale_rx_page[i].cmb_addr != NULL) 829 bus_dmamem_free(sc->sc_dmat, 830 (bus_dma_segment_t *)sc->ale_cdata.ale_rx_page[i].cmb_addr, 1); 831 sc->ale_cdata.ale_rx_page[i].cmb_addr = NULL; 832 sc->ale_cdata.ale_rx_page[i].cmb_map = NULL; 833 } 834 835 /* Tx CMB. */ 836 if (sc->ale_cdata.ale_tx_cmb_map != NULL) 837 bus_dmamap_unload(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map); 838 if (sc->ale_cdata.ale_tx_cmb_map != NULL && 839 sc->ale_cdata.ale_tx_cmb != NULL) 840 bus_dmamem_free(sc->sc_dmat, 841 (bus_dma_segment_t *)sc->ale_cdata.ale_tx_cmb, 1); 842 sc->ale_cdata.ale_tx_cmb = NULL; 843 sc->ale_cdata.ale_tx_cmb_map = NULL; 844 845 } 846 847 int 848 ale_encap(struct ale_softc *sc, struct mbuf **m_head) 849 { 850 struct ale_txdesc *txd, *txd_last; 851 struct tx_desc *desc; 852 struct mbuf *m; 853 bus_dmamap_t map; 854 uint32_t cflags, poff, vtag; 855 int error, i, nsegs, prod; 856 857 m = *m_head; 858 cflags = vtag = 0; 859 poff = 0; 860 861 prod = sc->ale_cdata.ale_tx_prod; 862 txd = &sc->ale_cdata.ale_txdesc[prod]; 863 txd_last = txd; 864 map = txd->tx_dmamap; 865 866 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, BUS_DMA_NOWAIT); 867 868 if (error != 0) { 869 bus_dmamap_unload(sc->sc_dmat, map); 870 error = EFBIG; 871 } 872 if (error == EFBIG) { 873 error = 0; 874 875 MGETHDR(m, M_DONTWAIT, MT_DATA); 876 if (m == NULL) { 877 printf("%s: can't defrag TX mbuf\n", 878 sc->sc_dev.dv_xname); 879 m_freem(*m_head); 880 *m_head = NULL; 881 return (ENOBUFS); 882 } 883 884 M_DUP_PKTHDR(m, *m_head); 885 if ((*m_head)->m_pkthdr.len > MHLEN) { 886 MCLGET(m, M_DONTWAIT); 887 if (!(m->m_flags & M_EXT)) { 888 m_freem(*m_head); 889 m_freem(m); 890 *m_head = NULL; 891 return (ENOBUFS); 892 } 893 } 894 m_copydata(*m_head, 0, (*m_head)->m_pkthdr.len, 895 mtod(m, caddr_t)); 896 m_freem(*m_head); 897 m->m_len = m->m_pkthdr.len; 898 *m_head = m; 899 900 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, 901 BUS_DMA_NOWAIT); 902 903 if (error != 0) { 904 printf("%s: could not load defragged TX mbuf\n", 905 sc->sc_dev.dv_xname); 906 if (!error) { 907 bus_dmamap_unload(sc->sc_dmat, map); 908 error = EFBIG; 909 } 910 m_freem(*m_head); 911 *m_head = NULL; 912 return (error); 913 } 914 } else if (error) { 915 printf("%s: could not load TX mbuf\n", sc->sc_dev.dv_xname); 916 return (error); 917 } 918 919 nsegs = map->dm_nsegs; 920 921 if (nsegs == 0) { 922 m_freem(*m_head); 923 *m_head = NULL; 924 return (EIO); 925 } 926 927 /* Check descriptor overrun. */ 928 if (sc->ale_cdata.ale_tx_cnt + nsegs >= ALE_TX_RING_CNT - 2) { 929 bus_dmamap_unload(sc->sc_dmat, map); 930 return (ENOBUFS); 931 } 932 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 933 BUS_DMASYNC_PREWRITE); 934 935 m = *m_head; 936 /* Configure Tx checksum offload. */ 937 if ((m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0) { 938 /* 939 * AR81xx supports Tx custom checksum offload feature 940 * that offloads single 16bit checksum computation. 941 * So you can choose one among IP, TCP and UDP. 942 * Normally driver sets checksum start/insertion 943 * position from the information of TCP/UDP frame as 944 * TCP/UDP checksum takes more time than that of IP. 945 * However it seems that custom checksum offload 946 * requires 4 bytes aligned Tx buffers due to hardware 947 * bug. 948 * AR81xx also supports explicit Tx checksum computation 949 * if it is told that the size of IP header and TCP 950 * header(for UDP, the header size does not matter 951 * because it's fixed length). However with this scheme 952 * TSO does not work so you have to choose one either 953 * TSO or explicit Tx checksum offload. I chosen TSO 954 * plus custom checksum offload with work-around which 955 * will cover most common usage for this consumer 956 * ethernet controller. The work-around takes a lot of 957 * CPU cycles if Tx buffer is not aligned on 4 bytes 958 * boundary, though. 959 */ 960 cflags |= ALE_TD_CXSUM; 961 /* Set checksum start offset. */ 962 cflags |= (poff << ALE_TD_CSUM_PLOADOFFSET_SHIFT); 963 } 964 965 #if NVLAN > 0 966 /* Configure VLAN hardware tag insertion. */ 967 if (m->m_flags & M_VLANTAG) { 968 vtag = ALE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag); 969 vtag = ((vtag << ALE_TD_VLAN_SHIFT) & ALE_TD_VLAN_MASK); 970 cflags |= ALE_TD_INSERT_VLAN_TAG; 971 } 972 #endif 973 974 desc = NULL; 975 for (i = 0; i < nsegs; i++) { 976 desc = &sc->ale_cdata.ale_tx_ring[prod]; 977 desc->addr = htole64(map->dm_segs[i].ds_addr); 978 desc->len = 979 htole32(ALE_TX_BYTES(map->dm_segs[i].ds_len) | vtag); 980 desc->flags = htole32(cflags); 981 sc->ale_cdata.ale_tx_cnt++; 982 ALE_DESC_INC(prod, ALE_TX_RING_CNT); 983 } 984 /* Update producer index. */ 985 sc->ale_cdata.ale_tx_prod = prod; 986 987 /* Finally set EOP on the last descriptor. */ 988 prod = (prod + ALE_TX_RING_CNT - 1) % ALE_TX_RING_CNT; 989 desc = &sc->ale_cdata.ale_tx_ring[prod]; 990 desc->flags |= htole32(ALE_TD_EOP); 991 992 /* Swap dmamap of the first and the last. */ 993 txd = &sc->ale_cdata.ale_txdesc[prod]; 994 map = txd_last->tx_dmamap; 995 txd_last->tx_dmamap = txd->tx_dmamap; 996 txd->tx_dmamap = map; 997 txd->tx_m = m; 998 999 /* Sync descriptors. */ 1000 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map, 0, 1001 sc->ale_cdata.ale_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1002 1003 return (0); 1004 } 1005 1006 void 1007 ale_start(struct ifnet *ifp) 1008 { 1009 struct ale_softc *sc = ifp->if_softc; 1010 struct mbuf *m_head; 1011 int enq; 1012 1013 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1014 return; 1015 1016 /* Reclaim transmitted frames. */ 1017 if (sc->ale_cdata.ale_tx_cnt >= ALE_TX_DESC_HIWAT) 1018 ale_txeof(sc); 1019 1020 enq = 0; 1021 for (;;) { 1022 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1023 if (m_head == NULL) 1024 break; 1025 1026 /* 1027 * Pack the data into the transmit ring. If we 1028 * don't have room, set the OACTIVE flag and wait 1029 * for the NIC to drain the ring. 1030 */ 1031 if (ale_encap(sc, &m_head)) { 1032 if (m_head == NULL) 1033 break; 1034 ifp->if_flags |= IFF_OACTIVE; 1035 break; 1036 } 1037 enq = 1; 1038 1039 #if NBPFILTER > 0 1040 /* 1041 * If there's a BPF listener, bounce a copy of this frame 1042 * to him. 1043 */ 1044 if (ifp->if_bpf != NULL) 1045 bpf_mtap_ether(ifp->if_bpf, m_head, BPF_DIRECTION_OUT); 1046 #endif 1047 } 1048 1049 if (enq) { 1050 /* Kick. */ 1051 CSR_WRITE_4(sc, ALE_MBOX_TPD_PROD_IDX, 1052 sc->ale_cdata.ale_tx_prod); 1053 1054 /* Set a timeout in case the chip goes out to lunch. */ 1055 ifp->if_timer = ALE_TX_TIMEOUT; 1056 } 1057 } 1058 1059 void 1060 ale_watchdog(struct ifnet *ifp) 1061 { 1062 struct ale_softc *sc = ifp->if_softc; 1063 1064 if ((sc->ale_flags & ALE_FLAG_LINK) == 0) { 1065 printf("%s: watchdog timeout (missed link)\n", 1066 sc->sc_dev.dv_xname); 1067 ifp->if_oerrors++; 1068 ale_init(ifp); 1069 return; 1070 } 1071 1072 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 1073 ifp->if_oerrors++; 1074 ale_init(ifp); 1075 1076 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1077 ale_start(ifp); 1078 } 1079 1080 int 1081 ale_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1082 { 1083 struct ale_softc *sc = ifp->if_softc; 1084 struct mii_data *mii = &sc->sc_miibus; 1085 struct ifaddr *ifa = (struct ifaddr *)data; 1086 struct ifreq *ifr = (struct ifreq *)data; 1087 int s, error = 0; 1088 1089 s = splnet(); 1090 1091 switch (cmd) { 1092 case SIOCSIFADDR: 1093 ifp->if_flags |= IFF_UP; 1094 if (!(ifp->if_flags & IFF_RUNNING)) 1095 ale_init(ifp); 1096 #ifdef INET 1097 if (ifa->ifa_addr->sa_family == AF_INET) 1098 arp_ifinit(&sc->sc_arpcom, ifa); 1099 #endif 1100 break; 1101 1102 case SIOCSIFFLAGS: 1103 if (ifp->if_flags & IFF_UP) { 1104 if (ifp->if_flags & IFF_RUNNING) 1105 error = ENETRESET; 1106 else 1107 ale_init(ifp); 1108 } else { 1109 if (ifp->if_flags & IFF_RUNNING) 1110 ale_stop(sc); 1111 } 1112 break; 1113 1114 case SIOCSIFMEDIA: 1115 case SIOCGIFMEDIA: 1116 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1117 break; 1118 1119 default: 1120 error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data); 1121 break; 1122 } 1123 1124 if (error == ENETRESET) { 1125 if (ifp->if_flags & IFF_RUNNING) 1126 ale_rxfilter(sc); 1127 error = 0; 1128 } 1129 1130 splx(s); 1131 return (error); 1132 } 1133 1134 void 1135 ale_mac_config(struct ale_softc *sc) 1136 { 1137 struct mii_data *mii; 1138 uint32_t reg; 1139 1140 mii = &sc->sc_miibus; 1141 reg = CSR_READ_4(sc, ALE_MAC_CFG); 1142 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 1143 MAC_CFG_SPEED_MASK); 1144 /* Reprogram MAC with resolved speed/duplex. */ 1145 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1146 case IFM_10_T: 1147 case IFM_100_TX: 1148 reg |= MAC_CFG_SPEED_10_100; 1149 break; 1150 case IFM_1000_T: 1151 reg |= MAC_CFG_SPEED_1000; 1152 break; 1153 } 1154 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1155 reg |= MAC_CFG_FULL_DUPLEX; 1156 #ifdef notyet 1157 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1158 reg |= MAC_CFG_TX_FC; 1159 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1160 reg |= MAC_CFG_RX_FC; 1161 #endif 1162 } 1163 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1164 } 1165 1166 void 1167 ale_stats_clear(struct ale_softc *sc) 1168 { 1169 struct smb sb; 1170 uint32_t *reg; 1171 int i; 1172 1173 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 1174 CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 1175 i += sizeof(uint32_t); 1176 } 1177 /* Read Tx statistics. */ 1178 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 1179 CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 1180 i += sizeof(uint32_t); 1181 } 1182 } 1183 1184 void 1185 ale_stats_update(struct ale_softc *sc) 1186 { 1187 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1188 struct ale_hw_stats *stat; 1189 struct smb sb, *smb; 1190 uint32_t *reg; 1191 int i; 1192 1193 stat = &sc->ale_stats; 1194 smb = &sb; 1195 1196 /* Read Rx statistics. */ 1197 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 1198 *reg = CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 1199 i += sizeof(uint32_t); 1200 } 1201 /* Read Tx statistics. */ 1202 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 1203 *reg = CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 1204 i += sizeof(uint32_t); 1205 } 1206 1207 /* Rx stats. */ 1208 stat->rx_frames += smb->rx_frames; 1209 stat->rx_bcast_frames += smb->rx_bcast_frames; 1210 stat->rx_mcast_frames += smb->rx_mcast_frames; 1211 stat->rx_pause_frames += smb->rx_pause_frames; 1212 stat->rx_control_frames += smb->rx_control_frames; 1213 stat->rx_crcerrs += smb->rx_crcerrs; 1214 stat->rx_lenerrs += smb->rx_lenerrs; 1215 stat->rx_bytes += smb->rx_bytes; 1216 stat->rx_runts += smb->rx_runts; 1217 stat->rx_fragments += smb->rx_fragments; 1218 stat->rx_pkts_64 += smb->rx_pkts_64; 1219 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 1220 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 1221 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 1222 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 1223 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 1224 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 1225 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 1226 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 1227 stat->rx_rrs_errs += smb->rx_rrs_errs; 1228 stat->rx_alignerrs += smb->rx_alignerrs; 1229 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 1230 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 1231 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 1232 1233 /* Tx stats. */ 1234 stat->tx_frames += smb->tx_frames; 1235 stat->tx_bcast_frames += smb->tx_bcast_frames; 1236 stat->tx_mcast_frames += smb->tx_mcast_frames; 1237 stat->tx_pause_frames += smb->tx_pause_frames; 1238 stat->tx_excess_defer += smb->tx_excess_defer; 1239 stat->tx_control_frames += smb->tx_control_frames; 1240 stat->tx_deferred += smb->tx_deferred; 1241 stat->tx_bytes += smb->tx_bytes; 1242 stat->tx_pkts_64 += smb->tx_pkts_64; 1243 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 1244 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 1245 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 1246 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 1247 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 1248 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 1249 stat->tx_single_colls += smb->tx_single_colls; 1250 stat->tx_multi_colls += smb->tx_multi_colls; 1251 stat->tx_late_colls += smb->tx_late_colls; 1252 stat->tx_excess_colls += smb->tx_excess_colls; 1253 stat->tx_abort += smb->tx_abort; 1254 stat->tx_underrun += smb->tx_underrun; 1255 stat->tx_desc_underrun += smb->tx_desc_underrun; 1256 stat->tx_lenerrs += smb->tx_lenerrs; 1257 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 1258 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 1259 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 1260 1261 /* Update counters in ifnet. */ 1262 ifp->if_opackets += smb->tx_frames; 1263 1264 ifp->if_collisions += smb->tx_single_colls + 1265 smb->tx_multi_colls * 2 + smb->tx_late_colls + 1266 smb->tx_abort * HDPX_CFG_RETRY_DEFAULT; 1267 1268 /* 1269 * XXX 1270 * tx_pkts_truncated counter looks suspicious. It constantly 1271 * increments with no sign of Tx errors. This may indicate 1272 * the counter name is not correct one so I've removed the 1273 * counter in output errors. 1274 */ 1275 ifp->if_oerrors += smb->tx_abort + smb->tx_late_colls + 1276 smb->tx_underrun; 1277 1278 ifp->if_ipackets += smb->rx_frames; 1279 1280 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 1281 smb->rx_runts + smb->rx_pkts_truncated + 1282 smb->rx_fifo_oflows + smb->rx_rrs_errs + 1283 smb->rx_alignerrs; 1284 } 1285 1286 int 1287 ale_intr(void *xsc) 1288 { 1289 struct ale_softc *sc = xsc; 1290 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1291 uint32_t status; 1292 1293 status = CSR_READ_4(sc, ALE_INTR_STATUS); 1294 if ((status & ALE_INTRS) == 0) 1295 return (0); 1296 1297 /* Acknowledge and disable interrupts. */ 1298 CSR_WRITE_4(sc, ALE_INTR_STATUS, status | INTR_DIS_INT); 1299 1300 if (ifp->if_flags & IFF_RUNNING) { 1301 int error; 1302 1303 error = ale_rxeof(sc); 1304 if (error) { 1305 sc->ale_stats.reset_brk_seq++; 1306 ale_init(ifp); 1307 return (0); 1308 } 1309 1310 if (status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) { 1311 if (status & INTR_DMA_RD_TO_RST) 1312 printf("%s: DMA read error! -- resetting\n", 1313 sc->sc_dev.dv_xname); 1314 if (status & INTR_DMA_WR_TO_RST) 1315 printf("%s: DMA write error! -- resetting\n", 1316 sc->sc_dev.dv_xname); 1317 ale_init(ifp); 1318 return (0); 1319 } 1320 1321 ale_txeof(sc); 1322 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1323 ale_start(ifp); 1324 } 1325 1326 /* Re-enable interrupts. */ 1327 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0x7FFFFFFF); 1328 return (1); 1329 } 1330 1331 void 1332 ale_txeof(struct ale_softc *sc) 1333 { 1334 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1335 struct ale_txdesc *txd; 1336 uint32_t cons, prod; 1337 int prog; 1338 1339 if (sc->ale_cdata.ale_tx_cnt == 0) 1340 return; 1341 1342 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map, 0, 1343 sc->ale_cdata.ale_tx_ring_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1344 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) { 1345 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map, 0, 1346 sc->ale_cdata.ale_tx_cmb_map->dm_mapsize, 1347 BUS_DMASYNC_POSTREAD); 1348 prod = *sc->ale_cdata.ale_tx_cmb & TPD_CNT_MASK; 1349 } else 1350 prod = CSR_READ_2(sc, ALE_TPD_CONS_IDX); 1351 cons = sc->ale_cdata.ale_tx_cons; 1352 /* 1353 * Go through our Tx list and free mbufs for those 1354 * frames which have been transmitted. 1355 */ 1356 for (prog = 0; cons != prod; prog++, 1357 ALE_DESC_INC(cons, ALE_TX_RING_CNT)) { 1358 if (sc->ale_cdata.ale_tx_cnt <= 0) 1359 break; 1360 prog++; 1361 ifp->if_flags &= ~IFF_OACTIVE; 1362 sc->ale_cdata.ale_tx_cnt--; 1363 txd = &sc->ale_cdata.ale_txdesc[cons]; 1364 if (txd->tx_m != NULL) { 1365 /* Reclaim transmitted mbufs. */ 1366 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1367 m_freem(txd->tx_m); 1368 txd->tx_m = NULL; 1369 } 1370 } 1371 1372 if (prog > 0) { 1373 sc->ale_cdata.ale_tx_cons = cons; 1374 /* 1375 * Unarm watchdog timer only when there is no pending 1376 * Tx descriptors in queue. 1377 */ 1378 if (sc->ale_cdata.ale_tx_cnt == 0) 1379 ifp->if_timer = 0; 1380 } 1381 } 1382 1383 void 1384 ale_rx_update_page(struct ale_softc *sc, struct ale_rx_page **page, 1385 uint32_t length, uint32_t *prod) 1386 { 1387 struct ale_rx_page *rx_page; 1388 1389 rx_page = *page; 1390 /* Update consumer position. */ 1391 rx_page->cons += roundup(length + sizeof(struct rx_rs), 1392 ALE_RX_PAGE_ALIGN); 1393 if (rx_page->cons >= ALE_RX_PAGE_SZ) { 1394 /* 1395 * End of Rx page reached, let hardware reuse 1396 * this page. 1397 */ 1398 rx_page->cons = 0; 1399 *rx_page->cmb_addr = 0; 1400 bus_dmamap_sync(sc->sc_dmat, rx_page->cmb_map, 0, 1401 rx_page->cmb_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1402 CSR_WRITE_1(sc, ALE_RXF0_PAGE0 + sc->ale_cdata.ale_rx_curp, 1403 RXF_VALID); 1404 /* Switch to alternate Rx page. */ 1405 sc->ale_cdata.ale_rx_curp ^= 1; 1406 rx_page = *page = 1407 &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 1408 /* Page flipped, sync CMB and Rx page. */ 1409 bus_dmamap_sync(sc->sc_dmat, rx_page->page_map, 0, 1410 rx_page->page_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1411 bus_dmamap_sync(sc->sc_dmat, rx_page->cmb_map, 0, 1412 rx_page->cmb_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1413 /* Sync completed, cache updated producer index. */ 1414 *prod = *rx_page->cmb_addr; 1415 } 1416 } 1417 1418 1419 /* 1420 * It seems that AR81xx controller can compute partial checksum. 1421 * The partial checksum value can be used to accelerate checksum 1422 * computation for fragmented TCP/UDP packets. Upper network stack 1423 * already takes advantage of the partial checksum value in IP 1424 * reassembly stage. But I'm not sure the correctness of the 1425 * partial hardware checksum assistance due to lack of data sheet. 1426 * In addition, the Rx feature of controller that requires copying 1427 * for every frames effectively nullifies one of most nice offload 1428 * capability of controller. 1429 */ 1430 void 1431 ale_rxcsum(struct ale_softc *sc, struct mbuf *m, uint32_t status) 1432 { 1433 struct ip *ip; 1434 char *p; 1435 1436 if ((status & ALE_RD_IPCSUM_NOK) == 0) 1437 m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK; 1438 1439 if ((sc->ale_flags & ALE_FLAG_RXCSUM_BUG) == 0) { 1440 if (((status & ALE_RD_IPV4_FRAG) == 0) && 1441 ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0) && 1442 ((status & ALE_RD_TCP_UDPCSUM_NOK) == 0)) { 1443 m->m_pkthdr.csum_flags |= 1444 M_TCP_CSUM_IN_OK | M_UDP_CSUM_IN_OK; 1445 } 1446 } else { 1447 if ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0 && 1448 (status & ALE_RD_TCP_UDPCSUM_NOK) == 0) { 1449 p = mtod(m, char *); 1450 p += ETHER_HDR_LEN; 1451 if ((status & ALE_RD_802_3) != 0) 1452 p += LLC_SNAPFRAMELEN; 1453 #if NVLAN > 0 1454 if (status & ALE_RD_VLAN) 1455 p += EVL_ENCAPLEN; 1456 #endif 1457 ip = (struct ip *)p; 1458 if (ip->ip_off != 0 && (status & ALE_RD_IPV4_DF) == 0) 1459 return; 1460 m->m_pkthdr.csum_flags |= 1461 M_TCP_CSUM_IN_OK | M_UDP_CSUM_IN_OK; 1462 } 1463 } 1464 /* 1465 * Don't mark bad checksum for TCP/UDP frames 1466 * as fragmented frames may always have set 1467 * bad checksummed bit of frame status. 1468 */ 1469 } 1470 1471 /* Process received frames. */ 1472 int 1473 ale_rxeof(struct ale_softc *sc) 1474 { 1475 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1476 struct ale_rx_page *rx_page; 1477 struct rx_rs *rs; 1478 struct mbuf *m; 1479 uint32_t length, prod, seqno, status; 1480 int prog; 1481 1482 rx_page = &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 1483 bus_dmamap_sync(sc->sc_dmat, rx_page->cmb_map, 0, 1484 rx_page->cmb_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1485 bus_dmamap_sync(sc->sc_dmat, rx_page->page_map, 0, 1486 rx_page->page_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1487 /* 1488 * Don't directly access producer index as hardware may 1489 * update it while Rx handler is in progress. It would 1490 * be even better if there is a way to let hardware 1491 * know how far driver processed its received frames. 1492 * Alternatively, hardware could provide a way to disable 1493 * CMB updates until driver acknowledges the end of CMB 1494 * access. 1495 */ 1496 prod = *rx_page->cmb_addr; 1497 for (prog = 0; ; prog++) { 1498 if (rx_page->cons >= prod) 1499 break; 1500 rs = (struct rx_rs *)(rx_page->page_addr + rx_page->cons); 1501 seqno = ALE_RX_SEQNO(letoh32(rs->seqno)); 1502 if (sc->ale_cdata.ale_rx_seqno != seqno) { 1503 /* 1504 * Normally I believe this should not happen unless 1505 * severe driver bug or corrupted memory. However 1506 * it seems to happen under certain conditions which 1507 * is triggered by abrupt Rx events such as initiation 1508 * of bulk transfer of remote host. It's not easy to 1509 * reproduce this and I doubt it could be related 1510 * with FIFO overflow of hardware or activity of Tx 1511 * CMB updates. I also remember similar behaviour 1512 * seen on RealTek 8139 which uses resembling Rx 1513 * scheme. 1514 */ 1515 if (aledebug) 1516 printf("%s: garbled seq: %u, expected: %u -- " 1517 "resetting!\n", sc->sc_dev.dv_xname, 1518 seqno, sc->ale_cdata.ale_rx_seqno); 1519 return (EIO); 1520 } 1521 /* Frame received. */ 1522 sc->ale_cdata.ale_rx_seqno++; 1523 length = ALE_RX_BYTES(letoh32(rs->length)); 1524 status = letoh32(rs->flags); 1525 if (status & ALE_RD_ERROR) { 1526 /* 1527 * We want to pass the following frames to upper 1528 * layer regardless of error status of Rx return 1529 * status. 1530 * 1531 * o IP/TCP/UDP checksum is bad. 1532 * o frame length and protocol specific length 1533 * does not match. 1534 */ 1535 if (status & (ALE_RD_CRC | ALE_RD_CODE | 1536 ALE_RD_DRIBBLE | ALE_RD_RUNT | ALE_RD_OFLOW | 1537 ALE_RD_TRUNC)) { 1538 ale_rx_update_page(sc, &rx_page, length, &prod); 1539 continue; 1540 } 1541 } 1542 /* 1543 * m_devget(9) is major bottle-neck of ale(4)(It comes 1544 * from hardware limitation). For jumbo frames we could 1545 * get a slightly better performance if driver use 1546 * m_getjcl(9) with proper buffer size argument. However 1547 * that would make code more complicated and I don't 1548 * think users would expect good Rx performance numbers 1549 * on these low-end consumer ethernet controller. 1550 */ 1551 m = m_devget((char *)(rs + 1), length - ETHER_CRC_LEN, 1552 ETHER_ALIGN, ifp, NULL); 1553 if (m == NULL) { 1554 ifp->if_iqdrops++; 1555 ale_rx_update_page(sc, &rx_page, length, &prod); 1556 continue; 1557 } 1558 if (status & ALE_RD_IPV4) 1559 ale_rxcsum(sc, m, status); 1560 #if NVLAN > 0 1561 if (status & ALE_RD_VLAN) { 1562 uint32_t vtags = ALE_RX_VLAN(letoh32(rs->vtags)); 1563 m->m_pkthdr.ether_vtag = ALE_RX_VLAN_TAG(vtags); 1564 m->m_flags |= M_VLANTAG; 1565 } 1566 #endif 1567 1568 1569 #if NBPFILTER > 0 1570 if (ifp->if_bpf) 1571 bpf_mtap_ether(ifp->if_bpf, m, BPF_DIRECTION_IN); 1572 #endif 1573 1574 /* Pass it to upper layer. */ 1575 ether_input_mbuf(ifp, m); 1576 1577 ale_rx_update_page(sc, &rx_page, length, &prod); 1578 } 1579 1580 return 0; 1581 } 1582 1583 void 1584 ale_tick(void *xsc) 1585 { 1586 struct ale_softc *sc = xsc; 1587 struct mii_data *mii = &sc->sc_miibus; 1588 int s; 1589 1590 s = splnet(); 1591 mii_tick(mii); 1592 ale_stats_update(sc); 1593 1594 timeout_add_sec(&sc->ale_tick_ch, 1); 1595 splx(s); 1596 } 1597 1598 void 1599 ale_reset(struct ale_softc *sc) 1600 { 1601 uint32_t reg; 1602 int i; 1603 1604 /* Initialize PCIe module. From Linux. */ 1605 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 1606 1607 CSR_WRITE_4(sc, ALE_MASTER_CFG, MASTER_RESET); 1608 for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 1609 DELAY(10); 1610 if ((CSR_READ_4(sc, ALE_MASTER_CFG) & MASTER_RESET) == 0) 1611 break; 1612 } 1613 if (i == 0) 1614 printf("%s: master reset timeout!\n", sc->sc_dev.dv_xname); 1615 1616 for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 1617 if ((reg = CSR_READ_4(sc, ALE_IDLE_STATUS)) == 0) 1618 break; 1619 DELAY(10); 1620 } 1621 1622 if (i == 0) 1623 printf("%s: reset timeout(0x%08x)!\n", sc->sc_dev.dv_xname, 1624 reg); 1625 } 1626 1627 int 1628 ale_init(struct ifnet *ifp) 1629 { 1630 struct ale_softc *sc = ifp->if_softc; 1631 struct mii_data *mii; 1632 uint8_t eaddr[ETHER_ADDR_LEN]; 1633 bus_addr_t paddr; 1634 uint32_t reg, rxf_hi, rxf_lo; 1635 1636 /* 1637 * Cancel any pending I/O. 1638 */ 1639 ale_stop(sc); 1640 1641 /* 1642 * Reset the chip to a known state. 1643 */ 1644 ale_reset(sc); 1645 1646 /* Initialize Tx descriptors, DMA memory blocks. */ 1647 ale_init_rx_pages(sc); 1648 ale_init_tx_ring(sc); 1649 1650 /* Reprogram the station address. */ 1651 bcopy(LLADDR(ifp->if_sadl), eaddr, ETHER_ADDR_LEN); 1652 CSR_WRITE_4(sc, ALE_PAR0, 1653 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 1654 CSR_WRITE_4(sc, ALE_PAR1, eaddr[0] << 8 | eaddr[1]); 1655 1656 /* 1657 * Clear WOL status and disable all WOL feature as WOL 1658 * would interfere Rx operation under normal environments. 1659 */ 1660 CSR_READ_4(sc, ALE_WOL_CFG); 1661 CSR_WRITE_4(sc, ALE_WOL_CFG, 0); 1662 1663 /* 1664 * Set Tx descriptor/RXF0/CMB base addresses. They share 1665 * the same high address part of DMAable region. 1666 */ 1667 paddr = sc->ale_cdata.ale_tx_ring_paddr; 1668 CSR_WRITE_4(sc, ALE_TPD_ADDR_HI, ALE_ADDR_HI(paddr)); 1669 CSR_WRITE_4(sc, ALE_TPD_ADDR_LO, ALE_ADDR_LO(paddr)); 1670 CSR_WRITE_4(sc, ALE_TPD_CNT, 1671 (ALE_TX_RING_CNT << TPD_CNT_SHIFT) & TPD_CNT_MASK); 1672 1673 /* Set Rx page base address, note we use single queue. */ 1674 paddr = sc->ale_cdata.ale_rx_page[0].page_paddr; 1675 CSR_WRITE_4(sc, ALE_RXF0_PAGE0_ADDR_LO, ALE_ADDR_LO(paddr)); 1676 paddr = sc->ale_cdata.ale_rx_page[1].page_paddr; 1677 CSR_WRITE_4(sc, ALE_RXF0_PAGE1_ADDR_LO, ALE_ADDR_LO(paddr)); 1678 1679 /* Set Tx/Rx CMB addresses. */ 1680 paddr = sc->ale_cdata.ale_tx_cmb_paddr; 1681 CSR_WRITE_4(sc, ALE_TX_CMB_ADDR_LO, ALE_ADDR_LO(paddr)); 1682 paddr = sc->ale_cdata.ale_rx_page[0].cmb_paddr; 1683 CSR_WRITE_4(sc, ALE_RXF0_CMB0_ADDR_LO, ALE_ADDR_LO(paddr)); 1684 paddr = sc->ale_cdata.ale_rx_page[1].cmb_paddr; 1685 CSR_WRITE_4(sc, ALE_RXF0_CMB1_ADDR_LO, ALE_ADDR_LO(paddr)); 1686 1687 /* Mark RXF0 is valid. */ 1688 CSR_WRITE_1(sc, ALE_RXF0_PAGE0, RXF_VALID); 1689 CSR_WRITE_1(sc, ALE_RXF0_PAGE1, RXF_VALID); 1690 /* 1691 * No need to initialize RFX1/RXF2/RXF3. We don't use 1692 * multi-queue yet. 1693 */ 1694 1695 /* Set Rx page size, excluding guard frame size. */ 1696 CSR_WRITE_4(sc, ALE_RXF_PAGE_SIZE, ALE_RX_PAGE_SZ); 1697 1698 /* Tell hardware that we're ready to load DMA blocks. */ 1699 CSR_WRITE_4(sc, ALE_DMA_BLOCK, DMA_BLOCK_LOAD); 1700 1701 /* Set Rx/Tx interrupt trigger threshold. */ 1702 CSR_WRITE_4(sc, ALE_INT_TRIG_THRESH, (1 << INT_TRIG_RX_THRESH_SHIFT) | 1703 (4 << INT_TRIG_TX_THRESH_SHIFT)); 1704 /* 1705 * XXX 1706 * Set interrupt trigger timer, its purpose and relation 1707 * with interrupt moderation mechanism is not clear yet. 1708 */ 1709 CSR_WRITE_4(sc, ALE_INT_TRIG_TIMER, 1710 ((ALE_USECS(10) << INT_TRIG_RX_TIMER_SHIFT) | 1711 (ALE_USECS(1000) << INT_TRIG_TX_TIMER_SHIFT))); 1712 1713 /* Configure interrupt moderation timer. */ 1714 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT; 1715 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT; 1716 reg = ALE_USECS(sc->ale_int_rx_mod) << IM_TIMER_RX_SHIFT; 1717 reg |= ALE_USECS(sc->ale_int_tx_mod) << IM_TIMER_TX_SHIFT; 1718 CSR_WRITE_4(sc, ALE_IM_TIMER, reg); 1719 reg = CSR_READ_4(sc, ALE_MASTER_CFG); 1720 reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK); 1721 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); 1722 if (ALE_USECS(sc->ale_int_rx_mod) != 0) 1723 reg |= MASTER_IM_RX_TIMER_ENB; 1724 if (ALE_USECS(sc->ale_int_tx_mod) != 0) 1725 reg |= MASTER_IM_TX_TIMER_ENB; 1726 CSR_WRITE_4(sc, ALE_MASTER_CFG, reg); 1727 CSR_WRITE_2(sc, ALE_INTR_CLR_TIMER, ALE_USECS(1000)); 1728 1729 /* Set Maximum frame size of controller. */ 1730 if (ifp->if_mtu < ETHERMTU) 1731 sc->ale_max_frame_size = ETHERMTU; 1732 else 1733 sc->ale_max_frame_size = ifp->if_mtu; 1734 sc->ale_max_frame_size += ETHER_HDR_LEN + EVL_ENCAPLEN + ETHER_CRC_LEN; 1735 CSR_WRITE_4(sc, ALE_FRAME_SIZE, sc->ale_max_frame_size); 1736 1737 /* Configure IPG/IFG parameters. */ 1738 CSR_WRITE_4(sc, ALE_IPG_IFG_CFG, 1739 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) | 1740 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 1741 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 1742 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK)); 1743 1744 /* Set parameters for half-duplex media. */ 1745 CSR_WRITE_4(sc, ALE_HDPX_CFG, 1746 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 1747 HDPX_CFG_LCOL_MASK) | 1748 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 1749 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 1750 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 1751 HDPX_CFG_ABEBT_MASK) | 1752 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 1753 HDPX_CFG_JAMIPG_MASK)); 1754 1755 /* Configure Tx jumbo frame parameters. */ 1756 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 1757 if (ifp->if_mtu < ETHERMTU) 1758 reg = sc->ale_max_frame_size; 1759 else if (ifp->if_mtu < 6 * 1024) 1760 reg = (sc->ale_max_frame_size * 2) / 3; 1761 else 1762 reg = sc->ale_max_frame_size / 2; 1763 CSR_WRITE_4(sc, ALE_TX_JUMBO_THRESH, 1764 roundup(reg, TX_JUMBO_THRESH_UNIT) >> 1765 TX_JUMBO_THRESH_UNIT_SHIFT); 1766 } 1767 1768 /* Configure TxQ. */ 1769 reg = (128 << (sc->ale_dma_rd_burst >> DMA_CFG_RD_BURST_SHIFT)) 1770 << TXQ_CFG_TX_FIFO_BURST_SHIFT; 1771 reg |= (TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 1772 TXQ_CFG_TPD_BURST_MASK; 1773 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE | TXQ_CFG_ENB); 1774 1775 /* Configure Rx jumbo frame & flow control parameters. */ 1776 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 1777 reg = roundup(sc->ale_max_frame_size, RX_JUMBO_THRESH_UNIT); 1778 CSR_WRITE_4(sc, ALE_RX_JUMBO_THRESH, 1779 (((reg >> RX_JUMBO_THRESH_UNIT_SHIFT) << 1780 RX_JUMBO_THRESH_MASK_SHIFT) & RX_JUMBO_THRESH_MASK) | 1781 ((RX_JUMBO_LKAH_DEFAULT << RX_JUMBO_LKAH_SHIFT) & 1782 RX_JUMBO_LKAH_MASK)); 1783 reg = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 1784 rxf_hi = (reg * 7) / 10; 1785 rxf_lo = (reg * 3)/ 10; 1786 CSR_WRITE_4(sc, ALE_RX_FIFO_PAUSE_THRESH, 1787 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 1788 RX_FIFO_PAUSE_THRESH_LO_MASK) | 1789 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 1790 RX_FIFO_PAUSE_THRESH_HI_MASK)); 1791 } 1792 1793 /* Disable RSS. */ 1794 CSR_WRITE_4(sc, ALE_RSS_IDT_TABLE0, 0); 1795 CSR_WRITE_4(sc, ALE_RSS_CPU, 0); 1796 1797 /* Configure RxQ. */ 1798 CSR_WRITE_4(sc, ALE_RXQ_CFG, 1799 RXQ_CFG_ALIGN_32 | RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 1800 1801 /* Configure DMA parameters. */ 1802 reg = 0; 1803 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) 1804 reg |= DMA_CFG_TXCMB_ENB; 1805 CSR_WRITE_4(sc, ALE_DMA_CFG, 1806 DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI | DMA_CFG_RCB_64 | 1807 sc->ale_dma_rd_burst | reg | 1808 sc->ale_dma_wr_burst | DMA_CFG_RXCMB_ENB | 1809 ((DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 1810 DMA_CFG_RD_DELAY_CNT_MASK) | 1811 ((DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 1812 DMA_CFG_WR_DELAY_CNT_MASK)); 1813 1814 /* 1815 * Hardware can be configured to issue SMB interrupt based 1816 * on programmed interval. Since there is a callout that is 1817 * invoked for every hz in driver we use that instead of 1818 * relying on periodic SMB interrupt. 1819 */ 1820 CSR_WRITE_4(sc, ALE_SMB_STAT_TIMER, ALE_USECS(0)); 1821 1822 /* Clear MAC statistics. */ 1823 ale_stats_clear(sc); 1824 1825 /* 1826 * Configure Tx/Rx MACs. 1827 * - Auto-padding for short frames. 1828 * - Enable CRC generation. 1829 * Actual reconfiguration of MAC for resolved speed/duplex 1830 * is followed after detection of link establishment. 1831 * AR81xx always does checksum computation regardless of 1832 * MAC_CFG_RXCSUM_ENB bit. In fact, setting the bit will 1833 * cause Rx handling issue for fragmented IP datagrams due 1834 * to silicon bug. 1835 */ 1836 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 1837 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 1838 MAC_CFG_PREAMBLE_MASK); 1839 if ((sc->ale_flags & ALE_FLAG_FASTETHER) != 0) 1840 reg |= MAC_CFG_SPEED_10_100; 1841 else 1842 reg |= MAC_CFG_SPEED_1000; 1843 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1844 1845 /* Set up the receive filter. */ 1846 ale_rxfilter(sc); 1847 ale_rxvlan(sc); 1848 1849 /* Acknowledge all pending interrupts and clear it. */ 1850 CSR_WRITE_4(sc, ALE_INTR_MASK, ALE_INTRS); 1851 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 1852 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0); 1853 1854 sc->ale_flags &= ~ALE_FLAG_LINK; 1855 1856 /* Switch to the current media. */ 1857 mii = &sc->sc_miibus; 1858 mii_mediachg(mii); 1859 1860 timeout_add_sec(&sc->ale_tick_ch, 1); 1861 1862 ifp->if_flags |= IFF_RUNNING; 1863 ifp->if_flags &= ~IFF_OACTIVE; 1864 1865 return 0; 1866 } 1867 1868 void 1869 ale_stop(struct ale_softc *sc) 1870 { 1871 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1872 struct ale_txdesc *txd; 1873 uint32_t reg; 1874 int i; 1875 1876 /* 1877 * Mark the interface down and cancel the watchdog timer. 1878 */ 1879 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1880 ifp->if_timer = 0; 1881 1882 timeout_del(&sc->ale_tick_ch); 1883 sc->ale_flags &= ~ALE_FLAG_LINK; 1884 1885 ale_stats_update(sc); 1886 1887 /* Disable interrupts. */ 1888 CSR_WRITE_4(sc, ALE_INTR_MASK, 0); 1889 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 1890 1891 /* Disable queue processing and DMA. */ 1892 reg = CSR_READ_4(sc, ALE_TXQ_CFG); 1893 reg &= ~TXQ_CFG_ENB; 1894 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg); 1895 reg = CSR_READ_4(sc, ALE_RXQ_CFG); 1896 reg &= ~RXQ_CFG_ENB; 1897 CSR_WRITE_4(sc, ALE_RXQ_CFG, reg); 1898 reg = CSR_READ_4(sc, ALE_DMA_CFG); 1899 reg &= ~(DMA_CFG_TXCMB_ENB | DMA_CFG_RXCMB_ENB); 1900 CSR_WRITE_4(sc, ALE_DMA_CFG, reg); 1901 DELAY(1000); 1902 1903 /* Stop Rx/Tx MACs. */ 1904 ale_stop_mac(sc); 1905 1906 /* Disable interrupts again? XXX */ 1907 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 1908 1909 /* 1910 * Free TX mbufs still in the queues. 1911 */ 1912 for (i = 0; i < ALE_TX_RING_CNT; i++) { 1913 txd = &sc->ale_cdata.ale_txdesc[i]; 1914 if (txd->tx_m != NULL) { 1915 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1916 m_freem(txd->tx_m); 1917 txd->tx_m = NULL; 1918 } 1919 } 1920 } 1921 1922 void 1923 ale_stop_mac(struct ale_softc *sc) 1924 { 1925 uint32_t reg; 1926 int i; 1927 1928 reg = CSR_READ_4(sc, ALE_MAC_CFG); 1929 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 1930 reg &= ~MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 1931 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1932 } 1933 1934 for (i = ALE_TIMEOUT; i > 0; i--) { 1935 reg = CSR_READ_4(sc, ALE_IDLE_STATUS); 1936 if (reg == 0) 1937 break; 1938 DELAY(10); 1939 } 1940 if (i == 0) 1941 printf("%s: could not disable Tx/Rx MAC(0x%08x)!\n", 1942 sc->sc_dev.dv_xname, reg); 1943 } 1944 1945 void 1946 ale_init_tx_ring(struct ale_softc *sc) 1947 { 1948 struct ale_txdesc *txd; 1949 int i; 1950 1951 sc->ale_cdata.ale_tx_prod = 0; 1952 sc->ale_cdata.ale_tx_cons = 0; 1953 sc->ale_cdata.ale_tx_cnt = 0; 1954 1955 bzero(sc->ale_cdata.ale_tx_ring, ALE_TX_RING_SZ); 1956 bzero(sc->ale_cdata.ale_tx_cmb, ALE_TX_CMB_SZ); 1957 for (i = 0; i < ALE_TX_RING_CNT; i++) { 1958 txd = &sc->ale_cdata.ale_txdesc[i]; 1959 txd->tx_m = NULL; 1960 } 1961 *sc->ale_cdata.ale_tx_cmb = 0; 1962 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map, 0, 1963 sc->ale_cdata.ale_tx_cmb_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1964 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map, 0, 1965 sc->ale_cdata.ale_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1966 } 1967 1968 void 1969 ale_init_rx_pages(struct ale_softc *sc) 1970 { 1971 struct ale_rx_page *rx_page; 1972 int i; 1973 1974 sc->ale_cdata.ale_rx_seqno = 0; 1975 sc->ale_cdata.ale_rx_curp = 0; 1976 1977 for (i = 0; i < ALE_RX_PAGES; i++) { 1978 rx_page = &sc->ale_cdata.ale_rx_page[i]; 1979 bzero(rx_page->page_addr, sc->ale_pagesize); 1980 bzero(rx_page->cmb_addr, ALE_RX_CMB_SZ); 1981 rx_page->cons = 0; 1982 *rx_page->cmb_addr = 0; 1983 bus_dmamap_sync(sc->sc_dmat, rx_page->page_map, 0, 1984 rx_page->page_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1985 bus_dmamap_sync(sc->sc_dmat, rx_page->cmb_map, 0, 1986 rx_page->cmb_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1987 } 1988 } 1989 1990 void 1991 ale_rxvlan(struct ale_softc *sc) 1992 { 1993 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1994 uint32_t reg; 1995 1996 reg = CSR_READ_4(sc, ALE_MAC_CFG); 1997 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 1998 if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) 1999 reg |= MAC_CFG_VLAN_TAG_STRIP; 2000 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2001 } 2002 2003 void 2004 ale_rxfilter(struct ale_softc *sc) 2005 { 2006 struct arpcom *ac = &sc->sc_arpcom; 2007 struct ifnet *ifp = &ac->ac_if; 2008 struct ether_multi *enm; 2009 struct ether_multistep step; 2010 uint32_t crc; 2011 uint32_t mchash[2]; 2012 uint32_t rxcfg; 2013 2014 rxcfg = CSR_READ_4(sc, ALE_MAC_CFG); 2015 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 2016 2017 /* 2018 * Always accept broadcast frames. 2019 */ 2020 rxcfg |= MAC_CFG_BCAST; 2021 2022 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC || 2023 ac->ac_multirangecnt > 0) { 2024 allmulti: 2025 if (ifp->if_flags & IFF_PROMISC) 2026 rxcfg |= MAC_CFG_PROMISC; 2027 else 2028 rxcfg |= MAC_CFG_ALLMULTI; 2029 mchash[0] = mchash[1] = 0xFFFFFFFF; 2030 } else { 2031 /* Program new filter. */ 2032 bzero(mchash, sizeof(mchash)); 2033 2034 ETHER_FIRST_MULTI(step, ac, enm); 2035 while (enm != NULL) { 2036 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 2037 ETHER_ADDR_LEN)) { 2038 ifp->if_flags |= IFF_ALLMULTI; 2039 goto allmulti; 2040 } 2041 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 2042 2043 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 2044 ETHER_NEXT_MULTI(step, enm); 2045 } 2046 } 2047 2048 CSR_WRITE_4(sc, ALE_MAR0, mchash[0]); 2049 CSR_WRITE_4(sc, ALE_MAR1, mchash[1]); 2050 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg); 2051 } 2052