1 /* $OpenBSD: if_alc.c,v 1.27 2014/07/22 13:12:11 mpi Exp $ */ 2 /*- 3 * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* Driver for Atheros AR8131/AR8132 PCIe Ethernet. */ 30 31 #include "bpfilter.h" 32 #include "vlan.h" 33 34 #include <sys/param.h> 35 #include <sys/endian.h> 36 #include <sys/systm.h> 37 #include <sys/types.h> 38 #include <sys/sockio.h> 39 #include <sys/mbuf.h> 40 #include <sys/queue.h> 41 #include <sys/kernel.h> 42 #include <sys/device.h> 43 #include <sys/timeout.h> 44 #include <sys/socket.h> 45 46 #include <machine/bus.h> 47 48 #include <net/if.h> 49 #include <net/if_dl.h> 50 #include <net/if_media.h> 51 52 #ifdef INET 53 #include <netinet/in.h> 54 #include <netinet/if_ether.h> 55 #endif 56 57 #include <net/if_types.h> 58 #include <net/if_vlan_var.h> 59 60 #if NBPFILTER > 0 61 #include <net/bpf.h> 62 #endif 63 64 #include <dev/rndvar.h> 65 66 #include <dev/mii/mii.h> 67 #include <dev/mii/miivar.h> 68 69 #include <dev/pci/pcireg.h> 70 #include <dev/pci/pcivar.h> 71 #include <dev/pci/pcidevs.h> 72 73 #include <dev/pci/if_alcreg.h> 74 75 int alc_match(struct device *, void *, void *); 76 void alc_attach(struct device *, struct device *, void *); 77 int alc_detach(struct device *, int); 78 int alc_activate(struct device *, int); 79 80 int alc_init(struct ifnet *); 81 void alc_start(struct ifnet *); 82 int alc_ioctl(struct ifnet *, u_long, caddr_t); 83 void alc_watchdog(struct ifnet *); 84 int alc_mediachange(struct ifnet *); 85 void alc_mediastatus(struct ifnet *, struct ifmediareq *); 86 87 void alc_aspm(struct alc_softc *, int); 88 void alc_disable_l0s_l1(struct alc_softc *); 89 int alc_dma_alloc(struct alc_softc *); 90 void alc_dma_free(struct alc_softc *); 91 int alc_encap(struct alc_softc *, struct mbuf **); 92 void alc_get_macaddr(struct alc_softc *); 93 void alc_init_cmb(struct alc_softc *); 94 void alc_init_rr_ring(struct alc_softc *); 95 int alc_init_rx_ring(struct alc_softc *); 96 void alc_init_smb(struct alc_softc *); 97 void alc_init_tx_ring(struct alc_softc *); 98 int alc_intr(void *); 99 void alc_mac_config(struct alc_softc *); 100 int alc_miibus_readreg(struct device *, int, int); 101 void alc_miibus_statchg(struct device *); 102 void alc_miibus_writereg(struct device *, int, int, int); 103 int alc_newbuf(struct alc_softc *, struct alc_rxdesc *); 104 void alc_phy_down(struct alc_softc *); 105 void alc_phy_reset(struct alc_softc *); 106 void alc_reset(struct alc_softc *); 107 void alc_rxeof(struct alc_softc *, struct rx_rdesc *); 108 void alc_rxintr(struct alc_softc *); 109 void alc_iff(struct alc_softc *); 110 void alc_rxvlan(struct alc_softc *); 111 void alc_start_queue(struct alc_softc *); 112 void alc_stats_clear(struct alc_softc *); 113 void alc_stats_update(struct alc_softc *); 114 void alc_stop(struct alc_softc *); 115 void alc_stop_mac(struct alc_softc *); 116 void alc_stop_queue(struct alc_softc *); 117 void alc_tick(void *); 118 void alc_txeof(struct alc_softc *); 119 120 uint32_t alc_dma_burst[] = { 128, 256, 512, 1024, 2048, 4096, 0 }; 121 122 const struct pci_matchid alc_devices[] = { 123 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L1C }, 124 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L2C }, 125 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L1D }, 126 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L1D_1 }, 127 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L2C_1 }, 128 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L2C_2 } 129 }; 130 131 struct cfattach alc_ca = { 132 sizeof (struct alc_softc), alc_match, alc_attach, NULL, 133 alc_activate 134 }; 135 136 struct cfdriver alc_cd = { 137 NULL, "alc", DV_IFNET 138 }; 139 140 int alcdebug = 0; 141 #define DPRINTF(x) do { if (alcdebug) printf x; } while (0) 142 143 #define ALC_CSUM_FEATURES (M_TCP_CSUM_OUT | M_UDP_CSUM_OUT) 144 145 int 146 alc_miibus_readreg(struct device *dev, int phy, int reg) 147 { 148 struct alc_softc *sc = (struct alc_softc *)dev; 149 uint32_t v; 150 int i; 151 152 if (phy != sc->alc_phyaddr) 153 return (0); 154 155 /* 156 * For AR8132 fast ethernet controller, do not report 1000baseT 157 * capability to mii(4). Even though AR8132 uses the same 158 * model/revision number of F1 gigabit PHY, the PHY has no 159 * ability to establish 1000baseT link. 160 */ 161 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0 && 162 reg == MII_EXTSR) 163 return (0); 164 165 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 166 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 167 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 168 DELAY(5); 169 v = CSR_READ_4(sc, ALC_MDIO); 170 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 171 break; 172 } 173 174 if (i == 0) { 175 printf("%s: phy read timeout: phy %d, reg %d\n", 176 sc->sc_dev.dv_xname, phy, reg); 177 return (0); 178 } 179 180 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 181 } 182 183 void 184 alc_miibus_writereg(struct device *dev, int phy, int reg, int val) 185 { 186 struct alc_softc *sc = (struct alc_softc *)dev; 187 uint32_t v; 188 int i; 189 190 if (phy != sc->alc_phyaddr) 191 return; 192 193 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 194 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 195 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 196 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 197 DELAY(5); 198 v = CSR_READ_4(sc, ALC_MDIO); 199 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 200 break; 201 } 202 203 if (i == 0) 204 printf("%s: phy write timeout: phy %d, reg %d\n", 205 sc->sc_dev.dv_xname, phy, reg); 206 } 207 208 void 209 alc_miibus_statchg(struct device *dev) 210 { 211 struct alc_softc *sc = (struct alc_softc *)dev; 212 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 213 struct mii_data *mii = &sc->sc_miibus; 214 uint32_t reg; 215 216 if ((ifp->if_flags & IFF_RUNNING) == 0) 217 return; 218 219 sc->alc_flags &= ~ALC_FLAG_LINK; 220 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 221 (IFM_ACTIVE | IFM_AVALID)) { 222 switch (IFM_SUBTYPE(mii->mii_media_active)) { 223 case IFM_10_T: 224 case IFM_100_TX: 225 sc->alc_flags |= ALC_FLAG_LINK; 226 break; 227 case IFM_1000_T: 228 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 229 sc->alc_flags |= ALC_FLAG_LINK; 230 break; 231 default: 232 break; 233 } 234 } 235 alc_stop_queue(sc); 236 /* Stop Rx/Tx MACs. */ 237 alc_stop_mac(sc); 238 239 /* Program MACs with resolved speed/duplex/flow-control. */ 240 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 241 alc_start_queue(sc); 242 alc_mac_config(sc); 243 /* Re-enable Tx/Rx MACs. */ 244 reg = CSR_READ_4(sc, ALC_MAC_CFG); 245 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 246 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 247 alc_aspm(sc, IFM_SUBTYPE(mii->mii_media_active)); 248 } 249 } 250 251 void 252 alc_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 253 { 254 struct alc_softc *sc = ifp->if_softc; 255 struct mii_data *mii = &sc->sc_miibus; 256 257 if ((ifp->if_flags & IFF_UP) == 0) 258 return; 259 260 mii_pollstat(mii); 261 ifmr->ifm_status = mii->mii_media_status; 262 ifmr->ifm_active = mii->mii_media_active; 263 } 264 265 int 266 alc_mediachange(struct ifnet *ifp) 267 { 268 struct alc_softc *sc = ifp->if_softc; 269 struct mii_data *mii = &sc->sc_miibus; 270 int error; 271 272 if (mii->mii_instance != 0) { 273 struct mii_softc *miisc; 274 275 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 276 mii_phy_reset(miisc); 277 } 278 error = mii_mediachg(mii); 279 280 return (error); 281 } 282 283 int 284 alc_match(struct device *dev, void *match, void *aux) 285 { 286 return pci_matchbyid((struct pci_attach_args *)aux, alc_devices, 287 nitems(alc_devices)); 288 } 289 290 void 291 alc_get_macaddr(struct alc_softc *sc) 292 { 293 uint32_t ea[2], opt; 294 uint16_t val; 295 int eeprom, i; 296 297 eeprom = 0; 298 opt = CSR_READ_4(sc, ALC_OPT_CFG); 299 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 && 300 (CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) { 301 /* 302 * EEPROM found, let TWSI reload EEPROM configuration. 303 * This will set ethernet address of controller. 304 */ 305 eeprom++; 306 switch (sc->sc_product) { 307 case PCI_PRODUCT_ATTANSIC_L1C: 308 case PCI_PRODUCT_ATTANSIC_L2C: 309 if ((opt & OPT_CFG_CLK_ENB) == 0) { 310 opt |= OPT_CFG_CLK_ENB; 311 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 312 CSR_READ_4(sc, ALC_OPT_CFG); 313 DELAY(1000); 314 } 315 break; 316 case PCI_PRODUCT_ATTANSIC_L1D: 317 case PCI_PRODUCT_ATTANSIC_L1D_1: 318 case PCI_PRODUCT_ATTANSIC_L2C_1: 319 case PCI_PRODUCT_ATTANSIC_L2C_2: 320 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 321 ALC_MII_DBG_ADDR, 0x00); 322 val = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr, 323 ALC_MII_DBG_DATA); 324 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 325 ALC_MII_DBG_DATA, val & 0xFF7F); 326 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 327 ALC_MII_DBG_ADDR, 0x3B); 328 val = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr, 329 ALC_MII_DBG_DATA); 330 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 331 ALC_MII_DBG_DATA, val | 0x0008); 332 DELAY(20); 333 break; 334 } 335 336 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 337 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 338 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 339 CSR_READ_4(sc, ALC_WOL_CFG); 340 341 CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) | 342 TWSI_CFG_SW_LD_START); 343 for (i = 100; i > 0; i--) { 344 DELAY(1000); 345 if ((CSR_READ_4(sc, ALC_TWSI_CFG) & 346 TWSI_CFG_SW_LD_START) == 0) 347 break; 348 } 349 if (i == 0) 350 printf("%s: reloading EEPROM timeout!\n", 351 sc->sc_dev.dv_xname); 352 } else { 353 if (alcdebug) 354 printf("%s: EEPROM not found!\n", sc->sc_dev.dv_xname); 355 } 356 if (eeprom != 0) { 357 switch (sc->sc_product) { 358 case PCI_PRODUCT_ATTANSIC_L1C: 359 case PCI_PRODUCT_ATTANSIC_L2C: 360 if ((opt & OPT_CFG_CLK_ENB) != 0) { 361 opt &= ~OPT_CFG_CLK_ENB; 362 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 363 CSR_READ_4(sc, ALC_OPT_CFG); 364 DELAY(1000); 365 } 366 break; 367 case PCI_PRODUCT_ATTANSIC_L1D: 368 case PCI_PRODUCT_ATTANSIC_L1D_1: 369 case PCI_PRODUCT_ATTANSIC_L2C_1: 370 case PCI_PRODUCT_ATTANSIC_L2C_2: 371 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 372 ALC_MII_DBG_ADDR, 0x00); 373 val = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr, 374 ALC_MII_DBG_DATA); 375 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 376 ALC_MII_DBG_DATA, val | 0x0080); 377 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 378 ALC_MII_DBG_ADDR, 0x3B); 379 val = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr, 380 ALC_MII_DBG_DATA); 381 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 382 ALC_MII_DBG_DATA, val & 0xFFF7); 383 DELAY(20); 384 break; 385 } 386 } 387 388 ea[0] = CSR_READ_4(sc, ALC_PAR0); 389 ea[1] = CSR_READ_4(sc, ALC_PAR1); 390 sc->alc_eaddr[0] = (ea[1] >> 8) & 0xFF; 391 sc->alc_eaddr[1] = (ea[1] >> 0) & 0xFF; 392 sc->alc_eaddr[2] = (ea[0] >> 24) & 0xFF; 393 sc->alc_eaddr[3] = (ea[0] >> 16) & 0xFF; 394 sc->alc_eaddr[4] = (ea[0] >> 8) & 0xFF; 395 sc->alc_eaddr[5] = (ea[0] >> 0) & 0xFF; 396 } 397 398 void 399 alc_disable_l0s_l1(struct alc_softc *sc) 400 { 401 uint32_t pmcfg; 402 403 /* Another magic from vendor. */ 404 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 405 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_CLK_SWH_L1 | 406 PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | PM_CFG_MAC_ASPM_CHK | 407 PM_CFG_SERDES_PD_EX_L1); 408 pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB | 409 PM_CFG_SERDES_L1_ENB; 410 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 411 } 412 413 void 414 alc_phy_reset(struct alc_softc *sc) 415 { 416 uint16_t data; 417 418 /* Reset magic from Linux. */ 419 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_SEL_ANA_RESET); 420 CSR_READ_2(sc, ALC_GPHY_CFG); 421 DELAY(10 * 1000); 422 423 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | 424 GPHY_CFG_SEL_ANA_RESET); 425 CSR_READ_2(sc, ALC_GPHY_CFG); 426 DELAY(10 * 1000); 427 428 /* DSP fixup, Vendor magic. */ 429 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1) { 430 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 431 ALC_MII_DBG_ADDR, 0x000A); 432 data = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr, 433 ALC_MII_DBG_DATA); 434 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 435 ALC_MII_DBG_DATA, data & 0xDFFF); 436 } 437 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D || 438 sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D_1 || 439 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1 || 440 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_2) { 441 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 442 ALC_MII_DBG_ADDR, 0x003B); 443 data = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr, 444 ALC_MII_DBG_DATA); 445 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 446 ALC_MII_DBG_DATA, data & 0xFFF7); 447 DELAY(20 * 1000); 448 } 449 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D) { 450 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 451 ALC_MII_DBG_ADDR, 0x0029); 452 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 453 ALC_MII_DBG_DATA, 0x929D); 454 } 455 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1C || 456 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C || 457 sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D_1 || 458 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_2) { 459 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 460 ALC_MII_DBG_ADDR, 0x0029); 461 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 462 ALC_MII_DBG_DATA, 0xB6DD); 463 } 464 465 /* Load DSP codes, vendor magic. */ 466 data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE | 467 ((1 << ANA_INTERVAL_SEL_TIMER_SHIFT) & ANA_INTERVAL_SEL_TIMER_MASK); 468 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 469 ALC_MII_DBG_ADDR, MII_ANA_CFG18); 470 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 471 ALC_MII_DBG_DATA, data); 472 473 data = ((2 << ANA_SERDES_CDR_BW_SHIFT) & ANA_SERDES_CDR_BW_MASK) | 474 ANA_SERDES_EN_DEEM | ANA_SERDES_SEL_HSP | ANA_SERDES_EN_PLL | 475 ANA_SERDES_EN_LCKDT; 476 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 477 ALC_MII_DBG_ADDR, MII_ANA_CFG5); 478 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 479 ALC_MII_DBG_DATA, data); 480 481 data = ((44 << ANA_LONG_CABLE_TH_100_SHIFT) & 482 ANA_LONG_CABLE_TH_100_MASK) | 483 ((33 << ANA_SHORT_CABLE_TH_100_SHIFT) & 484 ANA_SHORT_CABLE_TH_100_SHIFT) | 485 ANA_BP_BAD_LINK_ACCUM | ANA_BP_SMALL_BW; 486 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 487 ALC_MII_DBG_ADDR, MII_ANA_CFG54); 488 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 489 ALC_MII_DBG_DATA, data); 490 491 data = ((11 << ANA_IECHO_ADJ_3_SHIFT) & ANA_IECHO_ADJ_3_MASK) | 492 ((11 << ANA_IECHO_ADJ_2_SHIFT) & ANA_IECHO_ADJ_2_MASK) | 493 ((8 << ANA_IECHO_ADJ_1_SHIFT) & ANA_IECHO_ADJ_1_MASK) | 494 ((8 << ANA_IECHO_ADJ_0_SHIFT) & ANA_IECHO_ADJ_0_MASK); 495 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 496 ALC_MII_DBG_ADDR, MII_ANA_CFG4); 497 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 498 ALC_MII_DBG_DATA, data); 499 500 data = ((7 & ANA_MANUL_SWICH_ON_SHIFT) & ANA_MANUL_SWICH_ON_MASK) | 501 ANA_RESTART_CAL | ANA_MAN_ENABLE | ANA_SEL_HSP | ANA_EN_HB | 502 ANA_OEN_125M; 503 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 504 ALC_MII_DBG_ADDR, MII_ANA_CFG0); 505 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 506 ALC_MII_DBG_DATA, data); 507 DELAY(1000); 508 509 /* Disable hibernation. */ 510 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 511 0x0029); 512 data = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr, 513 ALC_MII_DBG_DATA); 514 data &= ~0x8000; 515 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 516 data); 517 518 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 519 0x000B); 520 data = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr, 521 ALC_MII_DBG_DATA); 522 data &= ~0x8000; 523 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 524 data); 525 } 526 527 void 528 alc_phy_down(struct alc_softc *sc) 529 { 530 switch (sc->sc_product) { 531 case PCI_PRODUCT_ATTANSIC_L1D: 532 case PCI_PRODUCT_ATTANSIC_L1D_1: 533 /* 534 * GPHY power down caused more problems on AR8151 v2.0. 535 * When driver is reloaded after GPHY power down, 536 * accesses to PHY/MAC registers hung the system. Only 537 * cold boot recovered from it. I'm not sure whether 538 * AR8151 v1.0 also requires this one though. I don't 539 * have AR8151 v1.0 controller in hand. 540 * The only option left is to isolate the PHY and 541 * initiates power down the PHY which in turn saves 542 * more power when driver is unloaded. 543 */ 544 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 545 MII_BMCR, BMCR_ISO | BMCR_PDOWN); 546 break; 547 default: 548 /* Force PHY down. */ 549 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | 550 GPHY_CFG_SEL_ANA_RESET | GPHY_CFG_PHY_IDDQ | 551 GPHY_CFG_PWDOWN_HW); 552 DELAY(1000); 553 break; 554 } 555 } 556 557 void 558 alc_aspm(struct alc_softc *sc, int media) 559 { 560 uint32_t pmcfg; 561 uint16_t linkcfg; 562 563 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 564 if ((sc->alc_flags & (ALC_FLAG_APS | ALC_FLAG_PCIE)) == 565 (ALC_FLAG_APS | ALC_FLAG_PCIE)) 566 linkcfg = CSR_READ_2(sc, sc->alc_expcap + 567 PCI_PCIE_LCSR); 568 else 569 linkcfg = 0; 570 pmcfg &= ~PM_CFG_SERDES_PD_EX_L1; 571 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_LCKDET_TIMER_MASK); 572 pmcfg |= PM_CFG_MAC_ASPM_CHK; 573 pmcfg |= (PM_CFG_LCKDET_TIMER_DEFAULT << PM_CFG_LCKDET_TIMER_SHIFT); 574 pmcfg &= ~(PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 575 576 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 577 /* Disable extended sync except AR8152 B v1.0 */ 578 linkcfg &= ~0x80; 579 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1 && 580 sc->alc_rev == ATHEROS_AR8152_B_V10) 581 linkcfg |= 0x80; 582 CSR_WRITE_2(sc, sc->alc_expcap + PCI_PCIE_LCSR, 583 linkcfg); 584 pmcfg &= ~(PM_CFG_EN_BUFS_RX_L0S | PM_CFG_SA_DLY_ENB | 585 PM_CFG_HOTRST); 586 pmcfg |= (PM_CFG_L1_ENTRY_TIMER_DEFAULT << 587 PM_CFG_L1_ENTRY_TIMER_SHIFT); 588 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 589 pmcfg |= (PM_CFG_PM_REQ_TIMER_DEFAULT << 590 PM_CFG_PM_REQ_TIMER_SHIFT); 591 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_PCIE_RECV; 592 } 593 594 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 595 if ((sc->alc_flags & ALC_FLAG_L0S) != 0) 596 pmcfg |= PM_CFG_ASPM_L0S_ENB; 597 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 598 pmcfg |= PM_CFG_ASPM_L1_ENB; 599 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 600 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1) 601 pmcfg &= ~PM_CFG_ASPM_L0S_ENB; 602 pmcfg &= ~(PM_CFG_SERDES_L1_ENB | 603 PM_CFG_SERDES_PLL_L1_ENB | 604 PM_CFG_SERDES_BUDS_RX_L1_ENB); 605 pmcfg |= PM_CFG_CLK_SWH_L1; 606 if (media == IFM_100_TX || media == IFM_1000_T) { 607 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK; 608 switch (sc->sc_product) { 609 case PCI_PRODUCT_ATTANSIC_L2C_1: 610 pmcfg |= (7 << 611 PM_CFG_L1_ENTRY_TIMER_SHIFT); 612 break; 613 case PCI_PRODUCT_ATTANSIC_L1D_1: 614 case PCI_PRODUCT_ATTANSIC_L2C_2: 615 pmcfg |= (4 << 616 PM_CFG_L1_ENTRY_TIMER_SHIFT); 617 break; 618 default: 619 pmcfg |= (15 << 620 PM_CFG_L1_ENTRY_TIMER_SHIFT); 621 break; 622 } 623 } 624 } else { 625 pmcfg |= PM_CFG_SERDES_L1_ENB | 626 PM_CFG_SERDES_PLL_L1_ENB | 627 PM_CFG_SERDES_BUDS_RX_L1_ENB; 628 pmcfg &= ~(PM_CFG_CLK_SWH_L1 | 629 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 630 } 631 } else { 632 pmcfg &= ~(PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_L1_ENB | 633 PM_CFG_SERDES_PLL_L1_ENB); 634 pmcfg |= PM_CFG_CLK_SWH_L1; 635 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 636 pmcfg |= PM_CFG_ASPM_L1_ENB; 637 } 638 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 639 } 640 641 void 642 alc_attach(struct device *parent, struct device *self, void *aux) 643 { 644 645 struct alc_softc *sc = (struct alc_softc *)self; 646 struct pci_attach_args *pa = aux; 647 pci_chipset_tag_t pc = pa->pa_pc; 648 pci_intr_handle_t ih; 649 const char *intrstr; 650 struct ifnet *ifp; 651 pcireg_t memtype; 652 char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/L1" }; 653 uint16_t burst; 654 int base, state, error = 0; 655 uint32_t cap, ctl, val; 656 657 /* 658 * Allocate IO memory 659 */ 660 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, ALC_PCIR_BAR); 661 if (pci_mapreg_map(pa, ALC_PCIR_BAR, memtype, 0, &sc->sc_mem_bt, 662 &sc->sc_mem_bh, NULL, &sc->sc_mem_size, 0)) { 663 printf(": can't map mem space\n"); 664 return; 665 } 666 667 if (pci_intr_map_msi(pa, &ih) != 0 && pci_intr_map(pa, &ih) != 0) { 668 printf(": can't map interrupt\n"); 669 goto fail; 670 } 671 672 /* 673 * Allocate IRQ 674 */ 675 intrstr = pci_intr_string(pc, ih); 676 sc->sc_irq_handle = pci_intr_establish(pc, ih, IPL_NET, alc_intr, sc, 677 sc->sc_dev.dv_xname); 678 if (sc->sc_irq_handle == NULL) { 679 printf(": could not establish interrupt"); 680 if (intrstr != NULL) 681 printf(" at %s", intrstr); 682 printf("\n"); 683 goto fail; 684 } 685 printf(": %s", intrstr); 686 687 sc->sc_dmat = pa->pa_dmat; 688 sc->sc_pct = pa->pa_pc; 689 sc->sc_pcitag = pa->pa_tag; 690 691 /* Set PHY address. */ 692 sc->alc_phyaddr = ALC_PHY_ADDR; 693 694 /* Get PCI and chip id/revision. */ 695 sc->sc_product = PCI_PRODUCT(pa->pa_id); 696 sc->alc_rev = PCI_REVISION(pa->pa_class); 697 698 /* Initialize DMA parameters. */ 699 sc->alc_dma_rd_burst = 0; 700 sc->alc_dma_wr_burst = 0; 701 sc->alc_rcb = DMA_CFG_RCB_64; 702 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PCIEXPRESS, 703 &base, NULL)) { 704 sc->alc_flags |= ALC_FLAG_PCIE; 705 sc->alc_expcap = base; 706 burst = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 707 base + PCI_PCIE_DCSR) >> 16; 708 sc->alc_dma_rd_burst = (burst & 0x7000) >> 12; 709 sc->alc_dma_wr_burst = (burst & 0x00e0) >> 5; 710 if (alcdebug) { 711 printf("%s: Read request size : %u bytes.\n", 712 sc->sc_dev.dv_xname, 713 alc_dma_burst[sc->alc_dma_rd_burst]); 714 printf("%s: TLP payload size : %u bytes.\n", 715 sc->sc_dev.dv_xname, 716 alc_dma_burst[sc->alc_dma_wr_burst]); 717 } 718 if (alc_dma_burst[sc->alc_dma_rd_burst] > 1024) 719 sc->alc_dma_rd_burst = 3; 720 if (alc_dma_burst[sc->alc_dma_wr_burst] > 1024) 721 sc->alc_dma_wr_burst = 3; 722 /* Clear data link and flow-control protocol error. */ 723 val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV); 724 val &= ~(PEX_UNC_ERR_SEV_DLP | PEX_UNC_ERR_SEV_FCP); 725 CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val); 726 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 727 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 728 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, 729 CSR_READ_4(sc, ALC_PCIE_PHYMISC) | 730 PCIE_PHYMISC_FORCE_RCV_DET); 731 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1 && 732 sc->alc_rev == ATHEROS_AR8152_B_V10) { 733 val = CSR_READ_4(sc, ALC_PCIE_PHYMISC2); 734 val &= ~(PCIE_PHYMISC2_SERDES_CDR_MASK | 735 PCIE_PHYMISC2_SERDES_TH_MASK); 736 val |= 3 << PCIE_PHYMISC2_SERDES_CDR_SHIFT; 737 val |= 3 << PCIE_PHYMISC2_SERDES_TH_SHIFT; 738 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC2, val); 739 } 740 /* Disable ASPM L0S and L1. */ 741 cap = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 742 base + PCI_PCIE_LCAP) >> 16; 743 if ((cap & 0x00000c00) != 0) { 744 ctl = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 745 base + PCI_PCIE_LCSR) >> 16; 746 if ((ctl & 0x08) != 0) 747 sc->alc_rcb = DMA_CFG_RCB_128; 748 if (alcdebug) 749 printf("%s: RCB %u bytes\n", 750 sc->sc_dev.dv_xname, 751 sc->alc_rcb == DMA_CFG_RCB_64 ? 64 : 128); 752 state = ctl & 0x03; 753 if (state & 0x01) 754 sc->alc_flags |= ALC_FLAG_L0S; 755 if (state & 0x02) 756 sc->alc_flags |= ALC_FLAG_L1S; 757 if (alcdebug) 758 printf("%s: ASPM %s %s\n", 759 sc->sc_dev.dv_xname, 760 aspm_state[state], 761 state == 0 ? "disabled" : "enabled"); 762 alc_disable_l0s_l1(sc); 763 } 764 } 765 766 /* Reset PHY. */ 767 alc_phy_reset(sc); 768 769 /* Reset the ethernet controller. */ 770 alc_reset(sc); 771 772 /* 773 * One odd thing is AR8132 uses the same PHY hardware(F1 774 * gigabit PHY) of AR8131. So atphy(4) of AR8132 reports 775 * the PHY supports 1000Mbps but that's not true. The PHY 776 * used in AR8132 can't establish gigabit link even if it 777 * shows the same PHY model/revision number of AR8131. 778 */ 779 switch (sc->sc_product) { 780 case PCI_PRODUCT_ATTANSIC_L2C_1: 781 case PCI_PRODUCT_ATTANSIC_L2C_2: 782 sc->alc_flags |= ALC_FLAG_APS; 783 /* FALLTHROUGH */ 784 case PCI_PRODUCT_ATTANSIC_L2C: 785 sc->alc_flags |= ALC_FLAG_FASTETHER; 786 break; 787 case PCI_PRODUCT_ATTANSIC_L1D: 788 case PCI_PRODUCT_ATTANSIC_L1D_1: 789 sc->alc_flags |= ALC_FLAG_APS; 790 /* FALLTHROUGH */ 791 default: 792 break; 793 } 794 sc->alc_flags |= ALC_FLAG_ASPM_MON | ALC_FLAG_JUMBO; 795 796 switch (sc->sc_product) { 797 case PCI_PRODUCT_ATTANSIC_L1C: 798 case PCI_PRODUCT_ATTANSIC_L2C: 799 sc->alc_max_framelen = 9 * 1024; 800 break; 801 case PCI_PRODUCT_ATTANSIC_L1D: 802 case PCI_PRODUCT_ATTANSIC_L1D_1: 803 case PCI_PRODUCT_ATTANSIC_L2C_1: 804 case PCI_PRODUCT_ATTANSIC_L2C_2: 805 sc->alc_max_framelen = 6 * 1024; 806 break; 807 } 808 809 /* 810 * It seems that AR813x/AR815x has silicon bug for SMB. In 811 * addition, Atheros said that enabling SMB wouldn't improve 812 * performance. However I think it's bad to access lots of 813 * registers to extract MAC statistics. 814 */ 815 sc->alc_flags |= ALC_FLAG_SMB_BUG; 816 /* 817 * Don't use Tx CMB. It is known to have silicon bug. 818 */ 819 sc->alc_flags |= ALC_FLAG_CMB_BUG; 820 821 sc->alc_chip_rev = CSR_READ_4(sc, ALC_MASTER_CFG) >> 822 MASTER_CHIP_REV_SHIFT; 823 if (alcdebug) { 824 printf("%s: PCI device revision : 0x%04x\n", 825 sc->sc_dev.dv_xname, sc->alc_rev); 826 printf("%s: Chip id/revision : 0x%04x\n", 827 sc->sc_dev.dv_xname, sc->alc_chip_rev); 828 printf("%s: %u Tx FIFO, %u Rx FIFO\n", sc->sc_dev.dv_xname, 829 CSR_READ_4(sc, ALC_SRAM_TX_FIFO_LEN) * 8, 830 CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN) * 8); 831 } 832 833 error = alc_dma_alloc(sc); 834 if (error) 835 goto fail; 836 837 /* Load station address. */ 838 alc_get_macaddr(sc); 839 840 ifp = &sc->sc_arpcom.ac_if; 841 ifp->if_softc = sc; 842 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 843 ifp->if_ioctl = alc_ioctl; 844 ifp->if_start = alc_start; 845 ifp->if_watchdog = alc_watchdog; 846 IFQ_SET_MAXLEN(&ifp->if_snd, ALC_TX_RING_CNT - 1); 847 IFQ_SET_READY(&ifp->if_snd); 848 bcopy(sc->alc_eaddr, sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN); 849 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 850 851 ifp->if_capabilities = IFCAP_VLAN_MTU; 852 853 #ifdef ALC_CHECKSUM 854 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 855 IFCAP_CSUM_UDPv4; 856 #endif 857 858 #if NVLAN > 0 859 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 860 #endif 861 862 printf(", address %s\n", ether_sprintf(sc->sc_arpcom.ac_enaddr)); 863 864 /* Set up MII bus. */ 865 sc->sc_miibus.mii_ifp = ifp; 866 sc->sc_miibus.mii_readreg = alc_miibus_readreg; 867 sc->sc_miibus.mii_writereg = alc_miibus_writereg; 868 sc->sc_miibus.mii_statchg = alc_miibus_statchg; 869 870 ifmedia_init(&sc->sc_miibus.mii_media, 0, alc_mediachange, 871 alc_mediastatus); 872 mii_attach(self, &sc->sc_miibus, 0xffffffff, MII_PHY_ANY, 873 MII_OFFSET_ANY, MIIF_DOPAUSE); 874 875 if (LIST_FIRST(&sc->sc_miibus.mii_phys) == NULL) { 876 printf("%s: no PHY found!\n", sc->sc_dev.dv_xname); 877 ifmedia_add(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL, 878 0, NULL); 879 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL); 880 } else 881 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_AUTO); 882 883 if_attach(ifp); 884 ether_ifattach(ifp); 885 886 timeout_set(&sc->alc_tick_ch, alc_tick, sc); 887 888 return; 889 fail: 890 alc_dma_free(sc); 891 if (sc->sc_irq_handle != NULL) 892 pci_intr_disestablish(pc, sc->sc_irq_handle); 893 if (sc->sc_mem_size) 894 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 895 } 896 897 int 898 alc_detach(struct device *self, int flags) 899 { 900 struct alc_softc *sc = (struct alc_softc *)self; 901 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 902 int s; 903 904 s = splnet(); 905 alc_stop(sc); 906 splx(s); 907 908 mii_detach(&sc->sc_miibus, MII_PHY_ANY, MII_OFFSET_ANY); 909 910 /* Delete all remaining media. */ 911 ifmedia_delete_instance(&sc->sc_miibus.mii_media, IFM_INST_ANY); 912 913 ether_ifdetach(ifp); 914 if_detach(ifp); 915 alc_dma_free(sc); 916 917 alc_phy_down(sc); 918 if (sc->sc_irq_handle != NULL) { 919 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 920 sc->sc_irq_handle = NULL; 921 } 922 923 return (0); 924 } 925 926 int 927 alc_activate(struct device *self, int act) 928 { 929 struct alc_softc *sc = (struct alc_softc *)self; 930 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 931 int rv = 0; 932 933 switch (act) { 934 case DVACT_SUSPEND: 935 if (ifp->if_flags & IFF_RUNNING) 936 alc_stop(sc); 937 rv = config_activate_children(self, act); 938 break; 939 case DVACT_RESUME: 940 if (ifp->if_flags & IFF_UP) 941 alc_init(ifp); 942 break; 943 default: 944 rv = config_activate_children(self, act); 945 break; 946 } 947 return (rv); 948 } 949 950 int 951 alc_dma_alloc(struct alc_softc *sc) 952 { 953 struct alc_txdesc *txd; 954 struct alc_rxdesc *rxd; 955 int nsegs, error, i; 956 957 /* 958 * Create DMA stuffs for TX ring 959 */ 960 error = bus_dmamap_create(sc->sc_dmat, ALC_TX_RING_SZ, 1, 961 ALC_TX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->alc_cdata.alc_tx_ring_map); 962 if (error) 963 return (ENOBUFS); 964 965 /* Allocate DMA'able memory for TX ring */ 966 error = bus_dmamem_alloc(sc->sc_dmat, ALC_TX_RING_SZ, 967 ETHER_ALIGN, 0, &sc->alc_rdata.alc_tx_ring_seg, 1, 968 &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 969 if (error) { 970 printf("%s: could not allocate DMA'able memory for Tx ring.\n", 971 sc->sc_dev.dv_xname); 972 return error; 973 } 974 975 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_tx_ring_seg, 976 nsegs, ALC_TX_RING_SZ, (caddr_t *)&sc->alc_rdata.alc_tx_ring, 977 BUS_DMA_NOWAIT); 978 if (error) 979 return (ENOBUFS); 980 981 /* Load the DMA map for Tx ring. */ 982 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 983 sc->alc_rdata.alc_tx_ring, ALC_TX_RING_SZ, NULL, BUS_DMA_WAITOK); 984 if (error) { 985 printf("%s: could not load DMA'able memory for Tx ring.\n", 986 sc->sc_dev.dv_xname); 987 bus_dmamem_free(sc->sc_dmat, 988 (bus_dma_segment_t *)&sc->alc_rdata.alc_tx_ring, 1); 989 return error; 990 } 991 992 sc->alc_rdata.alc_tx_ring_paddr = 993 sc->alc_cdata.alc_tx_ring_map->dm_segs[0].ds_addr; 994 995 /* 996 * Create DMA stuffs for RX ring 997 */ 998 error = bus_dmamap_create(sc->sc_dmat, ALC_RX_RING_SZ, 1, 999 ALC_RX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->alc_cdata.alc_rx_ring_map); 1000 if (error) 1001 return (ENOBUFS); 1002 1003 /* Allocate DMA'able memory for RX ring */ 1004 error = bus_dmamem_alloc(sc->sc_dmat, ALC_RX_RING_SZ, 1005 ETHER_ALIGN, 0, &sc->alc_rdata.alc_rx_ring_seg, 1, 1006 &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 1007 if (error) { 1008 printf("%s: could not allocate DMA'able memory for Rx ring.\n", 1009 sc->sc_dev.dv_xname); 1010 return error; 1011 } 1012 1013 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_rx_ring_seg, 1014 nsegs, ALC_RX_RING_SZ, (caddr_t *)&sc->alc_rdata.alc_rx_ring, 1015 BUS_DMA_NOWAIT); 1016 if (error) 1017 return (ENOBUFS); 1018 1019 /* Load the DMA map for Rx ring. */ 1020 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 1021 sc->alc_rdata.alc_rx_ring, ALC_RX_RING_SZ, NULL, BUS_DMA_WAITOK); 1022 if (error) { 1023 printf("%s: could not load DMA'able memory for Rx ring.\n", 1024 sc->sc_dev.dv_xname); 1025 bus_dmamem_free(sc->sc_dmat, 1026 (bus_dma_segment_t *)sc->alc_rdata.alc_rx_ring, 1); 1027 return error; 1028 } 1029 1030 sc->alc_rdata.alc_rx_ring_paddr = 1031 sc->alc_cdata.alc_rx_ring_map->dm_segs[0].ds_addr; 1032 1033 /* 1034 * Create DMA stuffs for RX return ring 1035 */ 1036 error = bus_dmamap_create(sc->sc_dmat, ALC_RR_RING_SZ, 1, 1037 ALC_RR_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->alc_cdata.alc_rr_ring_map); 1038 if (error) 1039 return (ENOBUFS); 1040 1041 /* Allocate DMA'able memory for RX return ring */ 1042 error = bus_dmamem_alloc(sc->sc_dmat, ALC_RR_RING_SZ, 1043 ETHER_ALIGN, 0, &sc->alc_rdata.alc_rr_ring_seg, 1, 1044 &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 1045 if (error) { 1046 printf("%s: could not allocate DMA'able memory for Rx " 1047 "return ring.\n", sc->sc_dev.dv_xname); 1048 return error; 1049 } 1050 1051 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_rr_ring_seg, 1052 nsegs, ALC_RR_RING_SZ, (caddr_t *)&sc->alc_rdata.alc_rr_ring, 1053 BUS_DMA_NOWAIT); 1054 if (error) 1055 return (ENOBUFS); 1056 1057 /* Load the DMA map for Rx return ring. */ 1058 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 1059 sc->alc_rdata.alc_rr_ring, ALC_RR_RING_SZ, NULL, BUS_DMA_WAITOK); 1060 if (error) { 1061 printf("%s: could not load DMA'able memory for Rx return ring." 1062 "\n", sc->sc_dev.dv_xname); 1063 bus_dmamem_free(sc->sc_dmat, 1064 (bus_dma_segment_t *)&sc->alc_rdata.alc_rr_ring, 1); 1065 return error; 1066 } 1067 1068 sc->alc_rdata.alc_rr_ring_paddr = 1069 sc->alc_cdata.alc_rr_ring_map->dm_segs[0].ds_addr; 1070 1071 /* 1072 * Create DMA stuffs for CMB block 1073 */ 1074 error = bus_dmamap_create(sc->sc_dmat, ALC_CMB_SZ, 1, 1075 ALC_CMB_SZ, 0, BUS_DMA_NOWAIT, 1076 &sc->alc_cdata.alc_cmb_map); 1077 if (error) 1078 return (ENOBUFS); 1079 1080 /* Allocate DMA'able memory for CMB block */ 1081 error = bus_dmamem_alloc(sc->sc_dmat, ALC_CMB_SZ, 1082 ETHER_ALIGN, 0, &sc->alc_rdata.alc_cmb_seg, 1, 1083 &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 1084 if (error) { 1085 printf("%s: could not allocate DMA'able memory for " 1086 "CMB block\n", sc->sc_dev.dv_xname); 1087 return error; 1088 } 1089 1090 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_cmb_seg, 1091 nsegs, ALC_CMB_SZ, (caddr_t *)&sc->alc_rdata.alc_cmb, 1092 BUS_DMA_NOWAIT); 1093 if (error) 1094 return (ENOBUFS); 1095 1096 /* Load the DMA map for CMB block. */ 1097 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 1098 sc->alc_rdata.alc_cmb, ALC_CMB_SZ, NULL, 1099 BUS_DMA_WAITOK); 1100 if (error) { 1101 printf("%s: could not load DMA'able memory for CMB block\n", 1102 sc->sc_dev.dv_xname); 1103 bus_dmamem_free(sc->sc_dmat, 1104 (bus_dma_segment_t *)&sc->alc_rdata.alc_cmb, 1); 1105 return error; 1106 } 1107 1108 sc->alc_rdata.alc_cmb_paddr = 1109 sc->alc_cdata.alc_cmb_map->dm_segs[0].ds_addr; 1110 1111 /* 1112 * Create DMA stuffs for SMB block 1113 */ 1114 error = bus_dmamap_create(sc->sc_dmat, ALC_SMB_SZ, 1, 1115 ALC_SMB_SZ, 0, BUS_DMA_NOWAIT, 1116 &sc->alc_cdata.alc_smb_map); 1117 if (error) 1118 return (ENOBUFS); 1119 1120 /* Allocate DMA'able memory for SMB block */ 1121 error = bus_dmamem_alloc(sc->sc_dmat, ALC_SMB_SZ, 1122 ETHER_ALIGN, 0, &sc->alc_rdata.alc_smb_seg, 1, 1123 &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 1124 if (error) { 1125 printf("%s: could not allocate DMA'able memory for " 1126 "SMB block\n", sc->sc_dev.dv_xname); 1127 return error; 1128 } 1129 1130 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_smb_seg, 1131 nsegs, ALC_SMB_SZ, (caddr_t *)&sc->alc_rdata.alc_smb, 1132 BUS_DMA_NOWAIT); 1133 if (error) 1134 return (ENOBUFS); 1135 1136 /* Load the DMA map for SMB block */ 1137 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 1138 sc->alc_rdata.alc_smb, ALC_SMB_SZ, NULL, 1139 BUS_DMA_WAITOK); 1140 if (error) { 1141 printf("%s: could not load DMA'able memory for SMB block\n", 1142 sc->sc_dev.dv_xname); 1143 bus_dmamem_free(sc->sc_dmat, 1144 (bus_dma_segment_t *)&sc->alc_rdata.alc_smb, 1); 1145 return error; 1146 } 1147 1148 sc->alc_rdata.alc_smb_paddr = 1149 sc->alc_cdata.alc_smb_map->dm_segs[0].ds_addr; 1150 1151 1152 /* Create DMA maps for Tx buffers. */ 1153 for (i = 0; i < ALC_TX_RING_CNT; i++) { 1154 txd = &sc->alc_cdata.alc_txdesc[i]; 1155 txd->tx_m = NULL; 1156 txd->tx_dmamap = NULL; 1157 error = bus_dmamap_create(sc->sc_dmat, ALC_TSO_MAXSIZE, 1158 ALC_MAXTXSEGS, ALC_TSO_MAXSEGSIZE, 0, BUS_DMA_NOWAIT, 1159 &txd->tx_dmamap); 1160 if (error) { 1161 printf("%s: could not create Tx dmamap.\n", 1162 sc->sc_dev.dv_xname); 1163 return error; 1164 } 1165 } 1166 1167 /* Create DMA maps for Rx buffers. */ 1168 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 1169 BUS_DMA_NOWAIT, &sc->alc_cdata.alc_rx_sparemap); 1170 if (error) { 1171 printf("%s: could not create spare Rx dmamap.\n", 1172 sc->sc_dev.dv_xname); 1173 return error; 1174 } 1175 1176 for (i = 0; i < ALC_RX_RING_CNT; i++) { 1177 rxd = &sc->alc_cdata.alc_rxdesc[i]; 1178 rxd->rx_m = NULL; 1179 rxd->rx_dmamap = NULL; 1180 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1181 MCLBYTES, 0, BUS_DMA_NOWAIT, &rxd->rx_dmamap); 1182 if (error) { 1183 printf("%s: could not create Rx dmamap.\n", 1184 sc->sc_dev.dv_xname); 1185 return error; 1186 } 1187 } 1188 1189 return (0); 1190 } 1191 1192 1193 void 1194 alc_dma_free(struct alc_softc *sc) 1195 { 1196 struct alc_txdesc *txd; 1197 struct alc_rxdesc *rxd; 1198 int i; 1199 1200 /* Tx buffers */ 1201 for (i = 0; i < ALC_TX_RING_CNT; i++) { 1202 txd = &sc->alc_cdata.alc_txdesc[i]; 1203 if (txd->tx_dmamap != NULL) { 1204 bus_dmamap_destroy(sc->sc_dmat, txd->tx_dmamap); 1205 txd->tx_dmamap = NULL; 1206 } 1207 } 1208 /* Rx buffers */ 1209 for (i = 0; i < ALC_RX_RING_CNT; i++) { 1210 rxd = &sc->alc_cdata.alc_rxdesc[i]; 1211 if (rxd->rx_dmamap != NULL) { 1212 bus_dmamap_destroy(sc->sc_dmat, rxd->rx_dmamap); 1213 rxd->rx_dmamap = NULL; 1214 } 1215 } 1216 if (sc->alc_cdata.alc_rx_sparemap != NULL) { 1217 bus_dmamap_destroy(sc->sc_dmat, sc->alc_cdata.alc_rx_sparemap); 1218 sc->alc_cdata.alc_rx_sparemap = NULL; 1219 } 1220 1221 /* Tx ring. */ 1222 if (sc->alc_cdata.alc_tx_ring_map != NULL) 1223 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map); 1224 if (sc->alc_cdata.alc_tx_ring_map != NULL && 1225 sc->alc_rdata.alc_tx_ring != NULL) 1226 bus_dmamem_free(sc->sc_dmat, 1227 (bus_dma_segment_t *)sc->alc_rdata.alc_tx_ring, 1); 1228 sc->alc_rdata.alc_tx_ring = NULL; 1229 sc->alc_cdata.alc_tx_ring_map = NULL; 1230 1231 /* Rx ring. */ 1232 if (sc->alc_cdata.alc_rx_ring_map != NULL) 1233 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map); 1234 if (sc->alc_cdata.alc_rx_ring_map != NULL && 1235 sc->alc_rdata.alc_rx_ring != NULL) 1236 bus_dmamem_free(sc->sc_dmat, 1237 (bus_dma_segment_t *)sc->alc_rdata.alc_rx_ring, 1); 1238 sc->alc_rdata.alc_rx_ring = NULL; 1239 sc->alc_cdata.alc_rx_ring_map = NULL; 1240 1241 /* Rx return ring. */ 1242 if (sc->alc_cdata.alc_rr_ring_map != NULL) 1243 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map); 1244 if (sc->alc_cdata.alc_rr_ring_map != NULL && 1245 sc->alc_rdata.alc_rr_ring != NULL) 1246 bus_dmamem_free(sc->sc_dmat, 1247 (bus_dma_segment_t *)sc->alc_rdata.alc_rr_ring, 1); 1248 sc->alc_rdata.alc_rr_ring = NULL; 1249 sc->alc_cdata.alc_rr_ring_map = NULL; 1250 1251 /* CMB block */ 1252 if (sc->alc_cdata.alc_cmb_map != NULL) 1253 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_cmb_map); 1254 if (sc->alc_cdata.alc_cmb_map != NULL && 1255 sc->alc_rdata.alc_cmb != NULL) 1256 bus_dmamem_free(sc->sc_dmat, 1257 (bus_dma_segment_t *)sc->alc_rdata.alc_cmb, 1); 1258 sc->alc_rdata.alc_cmb = NULL; 1259 sc->alc_cdata.alc_cmb_map = NULL; 1260 1261 /* SMB block */ 1262 if (sc->alc_cdata.alc_smb_map != NULL) 1263 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_smb_map); 1264 if (sc->alc_cdata.alc_smb_map != NULL && 1265 sc->alc_rdata.alc_smb != NULL) 1266 bus_dmamem_free(sc->sc_dmat, 1267 (bus_dma_segment_t *)sc->alc_rdata.alc_smb, 1); 1268 sc->alc_rdata.alc_smb = NULL; 1269 sc->alc_cdata.alc_smb_map = NULL; 1270 } 1271 1272 int 1273 alc_encap(struct alc_softc *sc, struct mbuf **m_head) 1274 { 1275 struct alc_txdesc *txd, *txd_last; 1276 struct tx_desc *desc; 1277 struct mbuf *m; 1278 bus_dmamap_t map; 1279 uint32_t cflags, poff, vtag; 1280 int error, idx, prod; 1281 1282 m = *m_head; 1283 cflags = vtag = 0; 1284 poff = 0; 1285 1286 prod = sc->alc_cdata.alc_tx_prod; 1287 txd = &sc->alc_cdata.alc_txdesc[prod]; 1288 txd_last = txd; 1289 map = txd->tx_dmamap; 1290 1291 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, BUS_DMA_NOWAIT); 1292 if (error != 0 && error != EFBIG) 1293 goto drop; 1294 if (error != 0) { 1295 if (m_defrag(*m_head, M_DONTWAIT)) { 1296 error = ENOBUFS; 1297 goto drop; 1298 } 1299 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, 1300 BUS_DMA_NOWAIT); 1301 if (error != 0) 1302 goto drop; 1303 } 1304 1305 /* Check descriptor overrun. */ 1306 if (sc->alc_cdata.alc_tx_cnt + map->dm_nsegs >= ALC_TX_RING_CNT - 3) { 1307 bus_dmamap_unload(sc->sc_dmat, map); 1308 return (ENOBUFS); 1309 } 1310 1311 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1312 BUS_DMASYNC_PREWRITE); 1313 1314 m = *m_head; 1315 desc = NULL; 1316 idx = 0; 1317 #if NVLAN > 0 1318 /* Configure VLAN hardware tag insertion. */ 1319 if (m->m_flags & M_VLANTAG) { 1320 vtag = htons(m->m_pkthdr.ether_vtag); 1321 vtag = (vtag << TD_VLAN_SHIFT) & TD_VLAN_MASK; 1322 cflags |= TD_INS_VLAN_TAG; 1323 } 1324 #endif 1325 /* Configure Tx checksum offload. */ 1326 if ((m->m_pkthdr.csum_flags & ALC_CSUM_FEATURES) != 0) { 1327 cflags |= TD_CUSTOM_CSUM; 1328 /* Set checksum start offset. */ 1329 cflags |= ((poff >> 1) << TD_PLOAD_OFFSET_SHIFT) & 1330 TD_PLOAD_OFFSET_MASK; 1331 } 1332 1333 for (; idx < map->dm_nsegs; idx++) { 1334 desc = &sc->alc_rdata.alc_tx_ring[prod]; 1335 desc->len = 1336 htole32(TX_BYTES(map->dm_segs[idx].ds_len) | vtag); 1337 desc->flags = htole32(cflags); 1338 desc->addr = htole64(map->dm_segs[idx].ds_addr); 1339 sc->alc_cdata.alc_tx_cnt++; 1340 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 1341 } 1342 1343 /* Update producer index. */ 1344 sc->alc_cdata.alc_tx_prod = prod; 1345 1346 /* Finally set EOP on the last descriptor. */ 1347 prod = (prod + ALC_TX_RING_CNT - 1) % ALC_TX_RING_CNT; 1348 desc = &sc->alc_rdata.alc_tx_ring[prod]; 1349 desc->flags |= htole32(TD_EOP); 1350 1351 /* Swap dmamap of the first and the last. */ 1352 txd = &sc->alc_cdata.alc_txdesc[prod]; 1353 map = txd_last->tx_dmamap; 1354 txd_last->tx_dmamap = txd->tx_dmamap; 1355 txd->tx_dmamap = map; 1356 txd->tx_m = m; 1357 1358 return (0); 1359 1360 drop: 1361 m_freem(*m_head); 1362 *m_head = NULL; 1363 return (error); 1364 } 1365 1366 void 1367 alc_start(struct ifnet *ifp) 1368 { 1369 struct alc_softc *sc = ifp->if_softc; 1370 struct mbuf *m_head; 1371 int enq = 0; 1372 1373 /* Reclaim transmitted frames. */ 1374 if (sc->alc_cdata.alc_tx_cnt >= ALC_TX_DESC_HIWAT) 1375 alc_txeof(sc); 1376 1377 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1378 return; 1379 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) 1380 return; 1381 if (IFQ_IS_EMPTY(&ifp->if_snd)) 1382 return; 1383 1384 for (;;) { 1385 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1386 if (m_head == NULL) 1387 break; 1388 1389 /* 1390 * Pack the data into the transmit ring. If we 1391 * don't have room, set the OACTIVE flag and wait 1392 * for the NIC to drain the ring. 1393 */ 1394 if (alc_encap(sc, &m_head)) { 1395 if (m_head == NULL) 1396 ifp->if_oerrors++; 1397 else { 1398 IF_PREPEND(&ifp->if_snd, m_head); 1399 ifp->if_flags |= IFF_OACTIVE; 1400 } 1401 break; 1402 } 1403 enq++; 1404 1405 #if NBPFILTER > 0 1406 /* 1407 * If there's a BPF listener, bounce a copy of this frame 1408 * to him. 1409 */ 1410 if (ifp->if_bpf != NULL) 1411 bpf_mtap_ether(ifp->if_bpf, m_head, BPF_DIRECTION_OUT); 1412 #endif 1413 } 1414 1415 if (enq > 0) { 1416 /* Sync descriptors. */ 1417 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0, 1418 sc->alc_cdata.alc_tx_ring_map->dm_mapsize, 1419 BUS_DMASYNC_PREWRITE); 1420 /* Kick. Assume we're using normal Tx priority queue. */ 1421 CSR_WRITE_4(sc, ALC_MBOX_TD_PROD_IDX, 1422 (sc->alc_cdata.alc_tx_prod << 1423 MBOX_TD_PROD_LO_IDX_SHIFT) & 1424 MBOX_TD_PROD_LO_IDX_MASK); 1425 /* Set a timeout in case the chip goes out to lunch. */ 1426 ifp->if_timer = ALC_TX_TIMEOUT; 1427 } 1428 } 1429 1430 void 1431 alc_watchdog(struct ifnet *ifp) 1432 { 1433 struct alc_softc *sc = ifp->if_softc; 1434 1435 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) { 1436 printf("%s: watchdog timeout (missed link)\n", 1437 sc->sc_dev.dv_xname); 1438 ifp->if_oerrors++; 1439 alc_init(ifp); 1440 return; 1441 } 1442 1443 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 1444 ifp->if_oerrors++; 1445 alc_init(ifp); 1446 alc_start(ifp); 1447 } 1448 1449 int 1450 alc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1451 { 1452 struct alc_softc *sc = ifp->if_softc; 1453 struct mii_data *mii = &sc->sc_miibus; 1454 struct ifaddr *ifa = (struct ifaddr *)data; 1455 struct ifreq *ifr = (struct ifreq *)data; 1456 int s, error = 0; 1457 1458 s = splnet(); 1459 1460 switch (cmd) { 1461 case SIOCSIFADDR: 1462 ifp->if_flags |= IFF_UP; 1463 if (!(ifp->if_flags & IFF_RUNNING)) 1464 alc_init(ifp); 1465 #ifdef INET 1466 if (ifa->ifa_addr->sa_family == AF_INET) 1467 arp_ifinit(&sc->sc_arpcom, ifa); 1468 #endif 1469 break; 1470 1471 case SIOCSIFFLAGS: 1472 if (ifp->if_flags & IFF_UP) { 1473 if (ifp->if_flags & IFF_RUNNING) 1474 error = ENETRESET; 1475 else 1476 alc_init(ifp); 1477 } else { 1478 if (ifp->if_flags & IFF_RUNNING) 1479 alc_stop(sc); 1480 } 1481 break; 1482 1483 case SIOCSIFMEDIA: 1484 case SIOCGIFMEDIA: 1485 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1486 break; 1487 1488 default: 1489 error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data); 1490 break; 1491 } 1492 1493 if (error == ENETRESET) { 1494 if (ifp->if_flags & IFF_RUNNING) 1495 alc_iff(sc); 1496 error = 0; 1497 } 1498 1499 splx(s); 1500 return (error); 1501 } 1502 1503 void 1504 alc_mac_config(struct alc_softc *sc) 1505 { 1506 struct mii_data *mii; 1507 uint32_t reg; 1508 1509 mii = &sc->sc_miibus; 1510 reg = CSR_READ_4(sc, ALC_MAC_CFG); 1511 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 1512 MAC_CFG_SPEED_MASK); 1513 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D || 1514 sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D_1 || 1515 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_2) 1516 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 1517 /* Reprogram MAC with resolved speed/duplex. */ 1518 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1519 case IFM_10_T: 1520 case IFM_100_TX: 1521 reg |= MAC_CFG_SPEED_10_100; 1522 break; 1523 case IFM_1000_T: 1524 reg |= MAC_CFG_SPEED_1000; 1525 break; 1526 } 1527 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1528 reg |= MAC_CFG_FULL_DUPLEX; 1529 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1530 reg |= MAC_CFG_TX_FC; 1531 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1532 reg |= MAC_CFG_RX_FC; 1533 } 1534 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 1535 } 1536 1537 void 1538 alc_stats_clear(struct alc_softc *sc) 1539 { 1540 struct smb sb, *smb; 1541 uint32_t *reg; 1542 int i; 1543 1544 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 1545 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 1546 sc->alc_cdata.alc_smb_map->dm_mapsize, 1547 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1548 smb = sc->alc_rdata.alc_smb; 1549 /* Update done, clear. */ 1550 smb->updated = 0; 1551 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 1552 sc->alc_cdata.alc_smb_map->dm_mapsize, 1553 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1554 } else { 1555 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 1556 reg++) { 1557 CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 1558 i += sizeof(uint32_t); 1559 } 1560 /* Read Tx statistics. */ 1561 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 1562 reg++) { 1563 CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 1564 i += sizeof(uint32_t); 1565 } 1566 } 1567 } 1568 1569 void 1570 alc_stats_update(struct alc_softc *sc) 1571 { 1572 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1573 struct alc_hw_stats *stat; 1574 struct smb sb, *smb; 1575 uint32_t *reg; 1576 int i; 1577 1578 stat = &sc->alc_stats; 1579 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 1580 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 1581 sc->alc_cdata.alc_smb_map->dm_mapsize, 1582 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1583 smb = sc->alc_rdata.alc_smb; 1584 if (smb->updated == 0) 1585 return; 1586 } else { 1587 smb = &sb; 1588 /* Read Rx statistics. */ 1589 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 1590 reg++) { 1591 *reg = CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 1592 i += sizeof(uint32_t); 1593 } 1594 /* Read Tx statistics. */ 1595 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 1596 reg++) { 1597 *reg = CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 1598 i += sizeof(uint32_t); 1599 } 1600 } 1601 1602 /* Rx stats. */ 1603 stat->rx_frames += smb->rx_frames; 1604 stat->rx_bcast_frames += smb->rx_bcast_frames; 1605 stat->rx_mcast_frames += smb->rx_mcast_frames; 1606 stat->rx_pause_frames += smb->rx_pause_frames; 1607 stat->rx_control_frames += smb->rx_control_frames; 1608 stat->rx_crcerrs += smb->rx_crcerrs; 1609 stat->rx_lenerrs += smb->rx_lenerrs; 1610 stat->rx_bytes += smb->rx_bytes; 1611 stat->rx_runts += smb->rx_runts; 1612 stat->rx_fragments += smb->rx_fragments; 1613 stat->rx_pkts_64 += smb->rx_pkts_64; 1614 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 1615 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 1616 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 1617 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 1618 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 1619 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 1620 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 1621 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 1622 stat->rx_rrs_errs += smb->rx_rrs_errs; 1623 stat->rx_alignerrs += smb->rx_alignerrs; 1624 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 1625 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 1626 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 1627 1628 /* Tx stats. */ 1629 stat->tx_frames += smb->tx_frames; 1630 stat->tx_bcast_frames += smb->tx_bcast_frames; 1631 stat->tx_mcast_frames += smb->tx_mcast_frames; 1632 stat->tx_pause_frames += smb->tx_pause_frames; 1633 stat->tx_excess_defer += smb->tx_excess_defer; 1634 stat->tx_control_frames += smb->tx_control_frames; 1635 stat->tx_deferred += smb->tx_deferred; 1636 stat->tx_bytes += smb->tx_bytes; 1637 stat->tx_pkts_64 += smb->tx_pkts_64; 1638 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 1639 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 1640 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 1641 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 1642 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 1643 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 1644 stat->tx_single_colls += smb->tx_single_colls; 1645 stat->tx_multi_colls += smb->tx_multi_colls; 1646 stat->tx_late_colls += smb->tx_late_colls; 1647 stat->tx_excess_colls += smb->tx_excess_colls; 1648 stat->tx_abort += smb->tx_abort; 1649 stat->tx_underrun += smb->tx_underrun; 1650 stat->tx_desc_underrun += smb->tx_desc_underrun; 1651 stat->tx_lenerrs += smb->tx_lenerrs; 1652 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 1653 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 1654 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 1655 1656 /* Update counters in ifnet. */ 1657 ifp->if_opackets += smb->tx_frames; 1658 1659 ifp->if_collisions += smb->tx_single_colls + 1660 smb->tx_multi_colls * 2 + smb->tx_late_colls + 1661 smb->tx_abort * HDPX_CFG_RETRY_DEFAULT; 1662 1663 /* 1664 * XXX 1665 * tx_pkts_truncated counter looks suspicious. It constantly 1666 * increments with no sign of Tx errors. This may indicate 1667 * the counter name is not correct one so I've removed the 1668 * counter in output errors. 1669 */ 1670 ifp->if_oerrors += smb->tx_abort + smb->tx_late_colls + 1671 smb->tx_underrun; 1672 1673 ifp->if_ipackets += smb->rx_frames; 1674 1675 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 1676 smb->rx_runts + smb->rx_pkts_truncated + 1677 smb->rx_fifo_oflows + smb->rx_rrs_errs + 1678 smb->rx_alignerrs; 1679 1680 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 1681 /* Update done, clear. */ 1682 smb->updated = 0; 1683 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 1684 sc->alc_cdata.alc_smb_map->dm_mapsize, 1685 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1686 } 1687 } 1688 1689 int 1690 alc_intr(void *arg) 1691 { 1692 struct alc_softc *sc = arg; 1693 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1694 uint32_t status; 1695 int claimed = 0; 1696 1697 status = CSR_READ_4(sc, ALC_INTR_STATUS); 1698 if ((status & ALC_INTRS) == 0) 1699 return (0); 1700 1701 /* Disable interrupts. */ 1702 CSR_WRITE_4(sc, ALC_INTR_STATUS, INTR_DIS_INT); 1703 1704 status = CSR_READ_4(sc, ALC_INTR_STATUS); 1705 if ((status & ALC_INTRS) == 0) 1706 goto back; 1707 1708 /* Acknowledge and disable interrupts. */ 1709 CSR_WRITE_4(sc, ALC_INTR_STATUS, status | INTR_DIS_INT); 1710 1711 if (ifp->if_flags & IFF_RUNNING) { 1712 if (status & INTR_RX_PKT) 1713 alc_rxintr(sc); 1714 1715 if (status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | 1716 INTR_TXQ_TO_RST)) { 1717 if (status & INTR_DMA_RD_TO_RST) 1718 printf("%s: DMA read error! -- resetting\n", 1719 sc->sc_dev.dv_xname); 1720 if (status & INTR_DMA_WR_TO_RST) 1721 printf("%s: DMA write error! -- resetting\n", 1722 sc->sc_dev.dv_xname); 1723 if (status & INTR_TXQ_TO_RST) 1724 printf("%s: TxQ reset! -- resetting\n", 1725 sc->sc_dev.dv_xname); 1726 alc_init(ifp); 1727 return (0); 1728 } 1729 1730 if (status & INTR_TX_PKT) 1731 alc_txeof(sc); 1732 1733 alc_start(ifp); 1734 } 1735 1736 claimed = 1; 1737 back: 1738 /* Re-enable interrupts. */ 1739 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0x7FFFFFFF); 1740 return (claimed); 1741 } 1742 1743 void 1744 alc_txeof(struct alc_softc *sc) 1745 { 1746 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1747 struct alc_txdesc *txd; 1748 uint32_t cons, prod; 1749 int prog; 1750 1751 if (sc->alc_cdata.alc_tx_cnt == 0) 1752 return; 1753 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0, 1754 sc->alc_cdata.alc_tx_ring_map->dm_mapsize, 1755 BUS_DMASYNC_POSTWRITE); 1756 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 1757 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0, 1758 sc->alc_cdata.alc_cmb_map->dm_mapsize, 1759 BUS_DMASYNC_POSTREAD); 1760 prod = sc->alc_rdata.alc_cmb->cons; 1761 } else 1762 prod = CSR_READ_4(sc, ALC_MBOX_TD_CONS_IDX); 1763 /* Assume we're using normal Tx priority queue. */ 1764 prod = (prod & MBOX_TD_CONS_LO_IDX_MASK) >> 1765 MBOX_TD_CONS_LO_IDX_SHIFT; 1766 cons = sc->alc_cdata.alc_tx_cons; 1767 /* 1768 * Go through our Tx list and free mbufs for those 1769 * frames which have been transmitted. 1770 */ 1771 for (prog = 0; cons != prod; prog++, 1772 ALC_DESC_INC(cons, ALC_TX_RING_CNT)) { 1773 if (sc->alc_cdata.alc_tx_cnt <= 0) 1774 break; 1775 prog++; 1776 ifp->if_flags &= ~IFF_OACTIVE; 1777 sc->alc_cdata.alc_tx_cnt--; 1778 txd = &sc->alc_cdata.alc_txdesc[cons]; 1779 if (txd->tx_m != NULL) { 1780 /* Reclaim transmitted mbufs. */ 1781 bus_dmamap_sync(sc->sc_dmat, txd->tx_dmamap, 0, 1782 txd->tx_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1783 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1784 m_freem(txd->tx_m); 1785 txd->tx_m = NULL; 1786 } 1787 } 1788 1789 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 1790 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0, 1791 sc->alc_cdata.alc_cmb_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1792 sc->alc_cdata.alc_tx_cons = cons; 1793 /* 1794 * Unarm watchdog timer only when there is no pending 1795 * frames in Tx queue. 1796 */ 1797 if (sc->alc_cdata.alc_tx_cnt == 0) 1798 ifp->if_timer = 0; 1799 } 1800 1801 int 1802 alc_newbuf(struct alc_softc *sc, struct alc_rxdesc *rxd) 1803 { 1804 struct mbuf *m; 1805 bus_dmamap_t map; 1806 int error; 1807 1808 MGETHDR(m, M_DONTWAIT, MT_DATA); 1809 if (m == NULL) 1810 return (ENOBUFS); 1811 MCLGET(m, M_DONTWAIT); 1812 if (!(m->m_flags & M_EXT)) { 1813 m_freem(m); 1814 return (ENOBUFS); 1815 } 1816 1817 m->m_len = m->m_pkthdr.len = RX_BUF_SIZE_MAX; 1818 1819 error = bus_dmamap_load_mbuf(sc->sc_dmat, 1820 sc->alc_cdata.alc_rx_sparemap, m, BUS_DMA_NOWAIT); 1821 1822 if (error != 0) { 1823 m_freem(m); 1824 printf("%s: can't load RX mbuf\n", sc->sc_dev.dv_xname); 1825 return (error); 1826 } 1827 1828 if (rxd->rx_m != NULL) { 1829 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0, 1830 rxd->rx_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1831 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 1832 } 1833 map = rxd->rx_dmamap; 1834 rxd->rx_dmamap = sc->alc_cdata.alc_rx_sparemap; 1835 sc->alc_cdata.alc_rx_sparemap = map; 1836 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0, rxd->rx_dmamap->dm_mapsize, 1837 BUS_DMASYNC_PREREAD); 1838 rxd->rx_m = m; 1839 rxd->rx_desc->addr = htole64(rxd->rx_dmamap->dm_segs[0].ds_addr); 1840 return (0); 1841 } 1842 1843 void 1844 alc_rxintr(struct alc_softc *sc) 1845 { 1846 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1847 struct rx_rdesc *rrd; 1848 uint32_t nsegs, status; 1849 int rr_cons, prog; 1850 1851 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 0, 1852 sc->alc_cdata.alc_rr_ring_map->dm_mapsize, 1853 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1854 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 0, 1855 sc->alc_cdata.alc_rx_ring_map->dm_mapsize, 1856 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1857 rr_cons = sc->alc_cdata.alc_rr_cons; 1858 for (prog = 0; (ifp->if_flags & IFF_RUNNING) != 0;) { 1859 rrd = &sc->alc_rdata.alc_rr_ring[rr_cons]; 1860 status = letoh32(rrd->status); 1861 if ((status & RRD_VALID) == 0) 1862 break; 1863 nsegs = RRD_RD_CNT(letoh32(rrd->rdinfo)); 1864 if (nsegs == 0) { 1865 /* This should not happen! */ 1866 if (alcdebug) 1867 printf("%s: unexpected segment count -- " 1868 "resetting\n", sc->sc_dev.dv_xname); 1869 break; 1870 } 1871 alc_rxeof(sc, rrd); 1872 /* Clear Rx return status. */ 1873 rrd->status = 0; 1874 ALC_DESC_INC(rr_cons, ALC_RR_RING_CNT); 1875 sc->alc_cdata.alc_rx_cons += nsegs; 1876 sc->alc_cdata.alc_rx_cons %= ALC_RR_RING_CNT; 1877 prog += nsegs; 1878 } 1879 1880 if (prog > 0) { 1881 /* Update the consumer index. */ 1882 sc->alc_cdata.alc_rr_cons = rr_cons; 1883 /* Sync Rx return descriptors. */ 1884 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 0, 1885 sc->alc_cdata.alc_rr_ring_map->dm_mapsize, 1886 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1887 /* 1888 * Sync updated Rx descriptors such that controller see 1889 * modified buffer addresses. 1890 */ 1891 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 0, 1892 sc->alc_cdata.alc_rx_ring_map->dm_mapsize, 1893 BUS_DMASYNC_PREWRITE); 1894 /* 1895 * Let controller know availability of new Rx buffers. 1896 * Since alc(4) use RXQ_CFG_RD_BURST_DEFAULT descriptors 1897 * it may be possible to update ALC_MBOX_RD0_PROD_IDX 1898 * only when Rx buffer pre-fetching is required. In 1899 * addition we already set ALC_RX_RD_FREE_THRESH to 1900 * RX_RD_FREE_THRESH_LO_DEFAULT descriptors. However 1901 * it still seems that pre-fetching needs more 1902 * experimentation. 1903 */ 1904 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 1905 sc->alc_cdata.alc_rx_cons); 1906 } 1907 } 1908 1909 /* Receive a frame. */ 1910 void 1911 alc_rxeof(struct alc_softc *sc, struct rx_rdesc *rrd) 1912 { 1913 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1914 struct alc_rxdesc *rxd; 1915 struct mbuf *mp, *m; 1916 uint32_t rdinfo, status; 1917 int count, nsegs, rx_cons; 1918 1919 status = letoh32(rrd->status); 1920 rdinfo = letoh32(rrd->rdinfo); 1921 rx_cons = RRD_RD_IDX(rdinfo); 1922 nsegs = RRD_RD_CNT(rdinfo); 1923 1924 sc->alc_cdata.alc_rxlen = RRD_BYTES(status); 1925 if (status & (RRD_ERR_SUM | RRD_ERR_LENGTH)) { 1926 /* 1927 * We want to pass the following frames to upper 1928 * layer regardless of error status of Rx return 1929 * ring. 1930 * 1931 * o IP/TCP/UDP checksum is bad. 1932 * o frame length and protocol specific length 1933 * does not match. 1934 * 1935 * Force network stack compute checksum for 1936 * errored frames. 1937 */ 1938 if ((status & (RRD_ERR_CRC | RRD_ERR_ALIGN | 1939 RRD_ERR_TRUNC | RRD_ERR_RUNT)) != 0) 1940 return; 1941 } 1942 1943 for (count = 0; count < nsegs; count++, 1944 ALC_DESC_INC(rx_cons, ALC_RX_RING_CNT)) { 1945 rxd = &sc->alc_cdata.alc_rxdesc[rx_cons]; 1946 mp = rxd->rx_m; 1947 /* Add a new receive buffer to the ring. */ 1948 if (alc_newbuf(sc, rxd) != 0) { 1949 ifp->if_iqdrops++; 1950 /* Reuse Rx buffers. */ 1951 if (sc->alc_cdata.alc_rxhead != NULL) 1952 m_freem(sc->alc_cdata.alc_rxhead); 1953 break; 1954 } 1955 1956 /* 1957 * Assume we've received a full sized frame. 1958 * Actual size is fixed when we encounter the end of 1959 * multi-segmented frame. 1960 */ 1961 mp->m_len = sc->alc_buf_size; 1962 1963 /* Chain received mbufs. */ 1964 if (sc->alc_cdata.alc_rxhead == NULL) { 1965 sc->alc_cdata.alc_rxhead = mp; 1966 sc->alc_cdata.alc_rxtail = mp; 1967 } else { 1968 mp->m_flags &= ~M_PKTHDR; 1969 sc->alc_cdata.alc_rxprev_tail = 1970 sc->alc_cdata.alc_rxtail; 1971 sc->alc_cdata.alc_rxtail->m_next = mp; 1972 sc->alc_cdata.alc_rxtail = mp; 1973 } 1974 1975 if (count == nsegs - 1) { 1976 /* Last desc. for this frame. */ 1977 m = sc->alc_cdata.alc_rxhead; 1978 m->m_flags |= M_PKTHDR; 1979 /* 1980 * It seems that L1C/L2C controller has no way 1981 * to tell hardware to strip CRC bytes. 1982 */ 1983 m->m_pkthdr.len = 1984 sc->alc_cdata.alc_rxlen - ETHER_CRC_LEN; 1985 if (nsegs > 1) { 1986 /* Set last mbuf size. */ 1987 mp->m_len = sc->alc_cdata.alc_rxlen - 1988 (nsegs - 1) * sc->alc_buf_size; 1989 /* Remove the CRC bytes in chained mbufs. */ 1990 if (mp->m_len <= ETHER_CRC_LEN) { 1991 sc->alc_cdata.alc_rxtail = 1992 sc->alc_cdata.alc_rxprev_tail; 1993 sc->alc_cdata.alc_rxtail->m_len -= 1994 (ETHER_CRC_LEN - mp->m_len); 1995 sc->alc_cdata.alc_rxtail->m_next = NULL; 1996 m_freem(mp); 1997 } else { 1998 mp->m_len -= ETHER_CRC_LEN; 1999 } 2000 } else 2001 m->m_len = m->m_pkthdr.len; 2002 m->m_pkthdr.rcvif = ifp; 2003 /* 2004 * Due to hardware bugs, Rx checksum offloading 2005 * was intentionally disabled. 2006 */ 2007 #if NVLAN > 0 2008 if (status & RRD_VLAN_TAG) { 2009 u_int32_t vtag = RRD_VLAN(letoh32(rrd->vtag)); 2010 m->m_pkthdr.ether_vtag = ntohs(vtag); 2011 m->m_flags |= M_VLANTAG; 2012 } 2013 #endif 2014 2015 #if NBPFILTER > 0 2016 if (ifp->if_bpf) 2017 bpf_mtap_ether(ifp->if_bpf, m, 2018 BPF_DIRECTION_IN); 2019 #endif 2020 2021 { 2022 /* Pass it on. */ 2023 ether_input_mbuf(ifp, m); 2024 } 2025 } 2026 } 2027 /* Reset mbuf chains. */ 2028 ALC_RXCHAIN_RESET(sc); 2029 } 2030 2031 void 2032 alc_tick(void *xsc) 2033 { 2034 struct alc_softc *sc = xsc; 2035 struct mii_data *mii = &sc->sc_miibus; 2036 int s; 2037 2038 s = splnet(); 2039 mii_tick(mii); 2040 alc_stats_update(sc); 2041 2042 timeout_add_sec(&sc->alc_tick_ch, 1); 2043 splx(s); 2044 } 2045 2046 void 2047 alc_reset(struct alc_softc *sc) 2048 { 2049 uint32_t reg; 2050 int i; 2051 2052 reg = CSR_READ_4(sc, ALC_MASTER_CFG) & 0xFFFF; 2053 reg |= MASTER_OOB_DIS_OFF | MASTER_RESET; 2054 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 2055 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 2056 DELAY(10); 2057 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0) 2058 break; 2059 } 2060 if (i == 0) 2061 printf("%s: master reset timeout!\n", sc->sc_dev.dv_xname); 2062 2063 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 2064 if ((reg = CSR_READ_4(sc, ALC_IDLE_STATUS)) == 0) 2065 break; 2066 DELAY(10); 2067 } 2068 2069 if (i == 0) 2070 printf("%s: reset timeout(0x%08x)!\n", sc->sc_dev.dv_xname, 2071 reg); 2072 } 2073 2074 int 2075 alc_init(struct ifnet *ifp) 2076 { 2077 struct alc_softc *sc = ifp->if_softc; 2078 struct mii_data *mii; 2079 uint8_t eaddr[ETHER_ADDR_LEN]; 2080 bus_addr_t paddr; 2081 uint32_t reg, rxf_hi, rxf_lo; 2082 int error; 2083 2084 /* 2085 * Cancel any pending I/O. 2086 */ 2087 alc_stop(sc); 2088 /* 2089 * Reset the chip to a known state. 2090 */ 2091 alc_reset(sc); 2092 2093 /* Initialize Rx descriptors. */ 2094 error = alc_init_rx_ring(sc); 2095 if (error != 0) { 2096 printf("%s: no memory for Rx buffers.\n", sc->sc_dev.dv_xname); 2097 alc_stop(sc); 2098 return (error); 2099 } 2100 alc_init_rr_ring(sc); 2101 alc_init_tx_ring(sc); 2102 alc_init_cmb(sc); 2103 alc_init_smb(sc); 2104 2105 /* Enable all clocks. */ 2106 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, 0); 2107 2108 /* Reprogram the station address. */ 2109 bcopy(LLADDR(ifp->if_sadl), eaddr, ETHER_ADDR_LEN); 2110 CSR_WRITE_4(sc, ALC_PAR0, 2111 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 2112 CSR_WRITE_4(sc, ALC_PAR1, eaddr[0] << 8 | eaddr[1]); 2113 /* 2114 * Clear WOL status and disable all WOL feature as WOL 2115 * would interfere Rx operation under normal environments. 2116 */ 2117 CSR_READ_4(sc, ALC_WOL_CFG); 2118 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 2119 /* Set Tx descriptor base addresses. */ 2120 paddr = sc->alc_rdata.alc_tx_ring_paddr; 2121 CSR_WRITE_4(sc, ALC_TX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 2122 CSR_WRITE_4(sc, ALC_TDL_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 2123 /* We don't use high priority ring. */ 2124 CSR_WRITE_4(sc, ALC_TDH_HEAD_ADDR_LO, 0); 2125 /* Set Tx descriptor counter. */ 2126 CSR_WRITE_4(sc, ALC_TD_RING_CNT, 2127 (ALC_TX_RING_CNT << TD_RING_CNT_SHIFT) & TD_RING_CNT_MASK); 2128 /* Set Rx descriptor base addresses. */ 2129 paddr = sc->alc_rdata.alc_rx_ring_paddr; 2130 CSR_WRITE_4(sc, ALC_RX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 2131 CSR_WRITE_4(sc, ALC_RD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 2132 /* We use one Rx ring. */ 2133 CSR_WRITE_4(sc, ALC_RD1_HEAD_ADDR_LO, 0); 2134 CSR_WRITE_4(sc, ALC_RD2_HEAD_ADDR_LO, 0); 2135 CSR_WRITE_4(sc, ALC_RD3_HEAD_ADDR_LO, 0); 2136 /* Set Rx descriptor counter. */ 2137 CSR_WRITE_4(sc, ALC_RD_RING_CNT, 2138 (ALC_RX_RING_CNT << RD_RING_CNT_SHIFT) & RD_RING_CNT_MASK); 2139 2140 /* 2141 * Let hardware split jumbo frames into alc_max_buf_sized chunks. 2142 * if it do not fit the buffer size. Rx return descriptor holds 2143 * a counter that indicates how many fragments were made by the 2144 * hardware. The buffer size should be multiple of 8 bytes. 2145 * Since hardware has limit on the size of buffer size, always 2146 * use the maximum value. 2147 * For strict-alignment architectures make sure to reduce buffer 2148 * size by 8 bytes to make room for alignment fixup. 2149 */ 2150 sc->alc_buf_size = RX_BUF_SIZE_MAX; 2151 CSR_WRITE_4(sc, ALC_RX_BUF_SIZE, sc->alc_buf_size); 2152 2153 paddr = sc->alc_rdata.alc_rr_ring_paddr; 2154 /* Set Rx return descriptor base addresses. */ 2155 CSR_WRITE_4(sc, ALC_RRD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 2156 /* We use one Rx return ring. */ 2157 CSR_WRITE_4(sc, ALC_RRD1_HEAD_ADDR_LO, 0); 2158 CSR_WRITE_4(sc, ALC_RRD2_HEAD_ADDR_LO, 0); 2159 CSR_WRITE_4(sc, ALC_RRD3_HEAD_ADDR_LO, 0); 2160 /* Set Rx return descriptor counter. */ 2161 CSR_WRITE_4(sc, ALC_RRD_RING_CNT, 2162 (ALC_RR_RING_CNT << RRD_RING_CNT_SHIFT) & RRD_RING_CNT_MASK); 2163 paddr = sc->alc_rdata.alc_cmb_paddr; 2164 CSR_WRITE_4(sc, ALC_CMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 2165 paddr = sc->alc_rdata.alc_smb_paddr; 2166 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 2167 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 2168 2169 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1) { 2170 /* Reconfigure SRAM - Vendor magic. */ 2171 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_LEN, 0x000002A0); 2172 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_LEN, 0x00000100); 2173 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_ADDR, 0x029F0000); 2174 CSR_WRITE_4(sc, ALC_SRAM_RD0_ADDR, 0x02BF02A0); 2175 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_ADDR, 0x03BF02C0); 2176 CSR_WRITE_4(sc, ALC_SRAM_TD_ADDR, 0x03DF03C0); 2177 CSR_WRITE_4(sc, ALC_TXF_WATER_MARK, 0x00000000); 2178 CSR_WRITE_4(sc, ALC_RD_DMA_CFG, 0x00000000); 2179 } 2180 2181 /* Tell hardware that we're ready to load DMA blocks. */ 2182 CSR_WRITE_4(sc, ALC_DMA_BLOCK, DMA_BLOCK_LOAD); 2183 2184 /* Configure interrupt moderation timer. */ 2185 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 2186 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 2187 reg = ALC_USECS(sc->alc_int_rx_mod) << IM_TIMER_RX_SHIFT; 2188 reg |= ALC_USECS(sc->alc_int_tx_mod) << IM_TIMER_TX_SHIFT; 2189 CSR_WRITE_4(sc, ALC_IM_TIMER, reg); 2190 /* 2191 * We don't want to automatic interrupt clear as task queue 2192 * for the interrupt should know interrupt status. 2193 */ 2194 reg = MASTER_SA_TIMER_ENB; 2195 if (ALC_USECS(sc->alc_int_rx_mod) != 0) 2196 reg |= MASTER_IM_RX_TIMER_ENB; 2197 if (ALC_USECS(sc->alc_int_tx_mod) != 0) 2198 reg |= MASTER_IM_TX_TIMER_ENB; 2199 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 2200 /* 2201 * Disable interrupt re-trigger timer. We don't want automatic 2202 * re-triggering of un-ACKed interrupts. 2203 */ 2204 CSR_WRITE_4(sc, ALC_INTR_RETRIG_TIMER, ALC_USECS(0)); 2205 /* Configure CMB. */ 2206 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 2207 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, 4); 2208 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(5000)); 2209 } else 2210 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(0)); 2211 /* 2212 * Hardware can be configured to issue SMB interrupt based 2213 * on programmed interval. Since there is a callout that is 2214 * invoked for every hz in driver we use that instead of 2215 * relying on periodic SMB interrupt. 2216 */ 2217 CSR_WRITE_4(sc, ALC_SMB_STAT_TIMER, ALC_USECS(0)); 2218 /* Clear MAC statistics. */ 2219 alc_stats_clear(sc); 2220 2221 /* 2222 * Always use maximum frame size that controller can support. 2223 * Otherwise received frames that has larger frame length 2224 * than alc(4) MTU would be silently dropped in hardware. This 2225 * would make path-MTU discovery hard as sender wouldn't get 2226 * any responses from receiver. alc(4) supports 2227 * multi-fragmented frames on Rx path so it has no issue on 2228 * assembling fragmented frames. Using maximum frame size also 2229 * removes the need to reinitialize hardware when interface 2230 * MTU configuration was changed. 2231 * 2232 * Be conservative in what you do, be liberal in what you 2233 * accept from others - RFC 793. 2234 */ 2235 CSR_WRITE_4(sc, ALC_FRAME_SIZE, sc->alc_max_framelen); 2236 2237 /* Disable header split(?) */ 2238 CSR_WRITE_4(sc, ALC_HDS_CFG, 0); 2239 2240 /* Configure IPG/IFG parameters. */ 2241 CSR_WRITE_4(sc, ALC_IPG_IFG_CFG, 2242 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) | 2243 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 2244 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 2245 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK)); 2246 /* Set parameters for half-duplex media. */ 2247 CSR_WRITE_4(sc, ALC_HDPX_CFG, 2248 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 2249 HDPX_CFG_LCOL_MASK) | 2250 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 2251 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 2252 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 2253 HDPX_CFG_ABEBT_MASK) | 2254 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 2255 HDPX_CFG_JAMIPG_MASK)); 2256 /* 2257 * Set TSO/checksum offload threshold. For frames that is 2258 * larger than this threshold, hardware wouldn't do 2259 * TSO/checksum offloading. 2260 */ 2261 CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH, 2262 (sc->alc_max_framelen >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) & 2263 TSO_OFFLOAD_THRESH_MASK); 2264 /* Configure TxQ. */ 2265 reg = (alc_dma_burst[sc->alc_dma_rd_burst] << 2266 TXQ_CFG_TX_FIFO_BURST_SHIFT) & TXQ_CFG_TX_FIFO_BURST_MASK; 2267 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1 || 2268 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_2) 2269 reg >>= 1; 2270 reg |= (TXQ_CFG_TD_BURST_DEFAULT << TXQ_CFG_TD_BURST_SHIFT) & 2271 TXQ_CFG_TD_BURST_MASK; 2272 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE); 2273 2274 /* Configure Rx free descriptor pre-fetching. */ 2275 CSR_WRITE_4(sc, ALC_RX_RD_FREE_THRESH, 2276 ((RX_RD_FREE_THRESH_HI_DEFAULT << RX_RD_FREE_THRESH_HI_SHIFT) & 2277 RX_RD_FREE_THRESH_HI_MASK) | 2278 ((RX_RD_FREE_THRESH_LO_DEFAULT << RX_RD_FREE_THRESH_LO_SHIFT) & 2279 RX_RD_FREE_THRESH_LO_MASK)); 2280 2281 /* 2282 * Configure flow control parameters. 2283 * XON : 80% of Rx FIFO 2284 * XOFF : 30% of Rx FIFO 2285 */ 2286 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1C || 2287 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C) { 2288 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 2289 rxf_hi = (reg * 8) / 10; 2290 rxf_lo = (reg * 3) / 10; 2291 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 2292 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 2293 RX_FIFO_PAUSE_THRESH_LO_MASK) | 2294 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 2295 RX_FIFO_PAUSE_THRESH_HI_MASK)); 2296 } 2297 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D_1 || 2298 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1) 2299 CSR_WRITE_4(sc, ALC_SERDES_LOCK, 2300 CSR_READ_4(sc, ALC_SERDES_LOCK) | SERDES_MAC_CLK_SLOWDOWN | 2301 SERDES_PHY_CLK_SLOWDOWN); 2302 2303 /* Disable RSS until I understand L1C/L2C's RSS logic. */ 2304 CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0); 2305 CSR_WRITE_4(sc, ALC_RSS_CPU, 0); 2306 2307 /* Configure RxQ. */ 2308 reg = (RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 2309 RXQ_CFG_RD_BURST_MASK; 2310 reg |= RXQ_CFG_RSS_MODE_DIS; 2311 if ((sc->alc_flags & ALC_FLAG_ASPM_MON) != 0) 2312 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_1M; 2313 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 2314 2315 /* Configure DMA parameters. */ 2316 reg = DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI; 2317 reg |= sc->alc_rcb; 2318 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 2319 reg |= DMA_CFG_CMB_ENB; 2320 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) 2321 reg |= DMA_CFG_SMB_ENB; 2322 else 2323 reg |= DMA_CFG_SMB_DIS; 2324 reg |= (sc->alc_dma_rd_burst & DMA_CFG_RD_BURST_MASK) << 2325 DMA_CFG_RD_BURST_SHIFT; 2326 reg |= (sc->alc_dma_wr_burst & DMA_CFG_WR_BURST_MASK) << 2327 DMA_CFG_WR_BURST_SHIFT; 2328 reg |= (DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 2329 DMA_CFG_RD_DELAY_CNT_MASK; 2330 reg |= (DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 2331 DMA_CFG_WR_DELAY_CNT_MASK; 2332 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 2333 2334 /* 2335 * Configure Tx/Rx MACs. 2336 * - Auto-padding for short frames. 2337 * - Enable CRC generation. 2338 * Actual reconfiguration of MAC for resolved speed/duplex 2339 * is followed after detection of link establishment. 2340 * AR813x/AR815x always does checksum computation regardless 2341 * of MAC_CFG_RXCSUM_ENB bit. Also the controller is known to 2342 * have bug in protocol field in Rx return structure so 2343 * these controllers can't handle fragmented frames. Disable 2344 * Rx checksum offloading until there is a newer controller 2345 * that has sane implementation. 2346 */ 2347 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 2348 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 2349 MAC_CFG_PREAMBLE_MASK); 2350 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D || 2351 sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D_1 || 2352 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_2) 2353 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 2354 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0) 2355 reg |= MAC_CFG_SPEED_10_100; 2356 else 2357 reg |= MAC_CFG_SPEED_1000; 2358 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 2359 2360 /* Set up the receive filter. */ 2361 alc_iff(sc); 2362 2363 alc_rxvlan(sc); 2364 2365 /* Acknowledge all pending interrupts and clear it. */ 2366 CSR_WRITE_4(sc, ALC_INTR_MASK, ALC_INTRS); 2367 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 2368 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0); 2369 2370 sc->alc_flags &= ~ALC_FLAG_LINK; 2371 /* Switch to the current media. */ 2372 mii = &sc->sc_miibus; 2373 mii_mediachg(mii); 2374 2375 timeout_add_sec(&sc->alc_tick_ch, 1); 2376 2377 ifp->if_flags |= IFF_RUNNING; 2378 ifp->if_flags &= ~IFF_OACTIVE; 2379 2380 return (0); 2381 } 2382 2383 void 2384 alc_stop(struct alc_softc *sc) 2385 { 2386 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 2387 struct alc_txdesc *txd; 2388 struct alc_rxdesc *rxd; 2389 uint32_t reg; 2390 int i; 2391 2392 /* 2393 * Mark the interface down and cancel the watchdog timer. 2394 */ 2395 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2396 ifp->if_timer = 0; 2397 2398 timeout_del(&sc->alc_tick_ch); 2399 sc->alc_flags &= ~ALC_FLAG_LINK; 2400 2401 alc_stats_update(sc); 2402 2403 /* Disable interrupts. */ 2404 CSR_WRITE_4(sc, ALC_INTR_MASK, 0); 2405 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 2406 alc_stop_queue(sc); 2407 2408 /* Disable DMA. */ 2409 reg = CSR_READ_4(sc, ALC_DMA_CFG); 2410 reg &= ~(DMA_CFG_CMB_ENB | DMA_CFG_SMB_ENB); 2411 reg |= DMA_CFG_SMB_DIS; 2412 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 2413 DELAY(1000); 2414 2415 /* Stop Rx/Tx MACs. */ 2416 alc_stop_mac(sc); 2417 2418 /* Disable interrupts which might be touched in taskq handler. */ 2419 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 2420 2421 /* Reclaim Rx buffers that have been processed. */ 2422 if (sc->alc_cdata.alc_rxhead != NULL) 2423 m_freem(sc->alc_cdata.alc_rxhead); 2424 ALC_RXCHAIN_RESET(sc); 2425 /* 2426 * Free Tx/Rx mbufs still in the queues. 2427 */ 2428 for (i = 0; i < ALC_RX_RING_CNT; i++) { 2429 rxd = &sc->alc_cdata.alc_rxdesc[i]; 2430 if (rxd->rx_m != NULL) { 2431 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0, 2432 rxd->rx_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2433 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 2434 m_freem(rxd->rx_m); 2435 rxd->rx_m = NULL; 2436 } 2437 } 2438 for (i = 0; i < ALC_TX_RING_CNT; i++) { 2439 txd = &sc->alc_cdata.alc_txdesc[i]; 2440 if (txd->tx_m != NULL) { 2441 bus_dmamap_sync(sc->sc_dmat, txd->tx_dmamap, 0, 2442 txd->tx_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2443 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 2444 m_freem(txd->tx_m); 2445 txd->tx_m = NULL; 2446 } 2447 } 2448 } 2449 2450 void 2451 alc_stop_mac(struct alc_softc *sc) 2452 { 2453 uint32_t reg; 2454 int i; 2455 2456 /* Disable Rx/Tx MAC. */ 2457 reg = CSR_READ_4(sc, ALC_MAC_CFG); 2458 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 2459 reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 2460 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 2461 } 2462 for (i = ALC_TIMEOUT; i > 0; i--) { 2463 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 2464 if (reg == 0) 2465 break; 2466 DELAY(10); 2467 } 2468 if (i == 0) 2469 printf("%s: could not disable Rx/Tx MAC(0x%08x)!\n", 2470 sc->sc_dev.dv_xname, reg); 2471 } 2472 2473 void 2474 alc_start_queue(struct alc_softc *sc) 2475 { 2476 uint32_t qcfg[] = { 2477 0, 2478 RXQ_CFG_QUEUE0_ENB, 2479 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB, 2480 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | RXQ_CFG_QUEUE2_ENB, 2481 RXQ_CFG_ENB 2482 }; 2483 uint32_t cfg; 2484 2485 /* Enable RxQ. */ 2486 cfg = CSR_READ_4(sc, ALC_RXQ_CFG); 2487 cfg &= ~RXQ_CFG_ENB; 2488 cfg |= qcfg[1]; 2489 CSR_WRITE_4(sc, ALC_RXQ_CFG, cfg); 2490 /* Enable TxQ. */ 2491 cfg = CSR_READ_4(sc, ALC_TXQ_CFG); 2492 cfg |= TXQ_CFG_ENB; 2493 CSR_WRITE_4(sc, ALC_TXQ_CFG, cfg); 2494 } 2495 2496 void 2497 alc_stop_queue(struct alc_softc *sc) 2498 { 2499 uint32_t reg; 2500 int i; 2501 2502 /* Disable RxQ. */ 2503 reg = CSR_READ_4(sc, ALC_RXQ_CFG); 2504 if ((reg & RXQ_CFG_ENB) != 0) { 2505 reg &= ~RXQ_CFG_ENB; 2506 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 2507 } 2508 /* Disable TxQ. */ 2509 reg = CSR_READ_4(sc, ALC_TXQ_CFG); 2510 if ((reg & TXQ_CFG_ENB) != 0) { 2511 reg &= ~TXQ_CFG_ENB; 2512 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg); 2513 } 2514 for (i = ALC_TIMEOUT; i > 0; i--) { 2515 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 2516 if ((reg & (IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 2517 break; 2518 DELAY(10); 2519 } 2520 if (i == 0) 2521 printf("%s: could not disable RxQ/TxQ (0x%08x)!\n", 2522 sc->sc_dev.dv_xname, reg); 2523 } 2524 2525 void 2526 alc_init_tx_ring(struct alc_softc *sc) 2527 { 2528 struct alc_ring_data *rd; 2529 struct alc_txdesc *txd; 2530 int i; 2531 2532 sc->alc_cdata.alc_tx_prod = 0; 2533 sc->alc_cdata.alc_tx_cons = 0; 2534 sc->alc_cdata.alc_tx_cnt = 0; 2535 2536 rd = &sc->alc_rdata; 2537 bzero(rd->alc_tx_ring, ALC_TX_RING_SZ); 2538 for (i = 0; i < ALC_TX_RING_CNT; i++) { 2539 txd = &sc->alc_cdata.alc_txdesc[i]; 2540 txd->tx_m = NULL; 2541 } 2542 2543 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0, 2544 sc->alc_cdata.alc_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2545 } 2546 2547 int 2548 alc_init_rx_ring(struct alc_softc *sc) 2549 { 2550 struct alc_ring_data *rd; 2551 struct alc_rxdesc *rxd; 2552 int i; 2553 2554 sc->alc_cdata.alc_rx_cons = ALC_RX_RING_CNT - 1; 2555 rd = &sc->alc_rdata; 2556 bzero(rd->alc_rx_ring, ALC_RX_RING_SZ); 2557 for (i = 0; i < ALC_RX_RING_CNT; i++) { 2558 rxd = &sc->alc_cdata.alc_rxdesc[i]; 2559 rxd->rx_m = NULL; 2560 rxd->rx_desc = &rd->alc_rx_ring[i]; 2561 if (alc_newbuf(sc, rxd) != 0) 2562 return (ENOBUFS); 2563 } 2564 2565 /* 2566 * Since controller does not update Rx descriptors, driver 2567 * does have to read Rx descriptors back so BUS_DMASYNC_PREWRITE 2568 * is enough to ensure coherence. 2569 */ 2570 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 0, 2571 sc->alc_cdata.alc_rx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2572 /* Let controller know availability of new Rx buffers. */ 2573 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, sc->alc_cdata.alc_rx_cons); 2574 2575 return (0); 2576 } 2577 2578 void 2579 alc_init_rr_ring(struct alc_softc *sc) 2580 { 2581 struct alc_ring_data *rd; 2582 2583 sc->alc_cdata.alc_rr_cons = 0; 2584 ALC_RXCHAIN_RESET(sc); 2585 2586 rd = &sc->alc_rdata; 2587 bzero(rd->alc_rr_ring, ALC_RR_RING_SZ); 2588 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 0, 2589 sc->alc_cdata.alc_rr_ring_map->dm_mapsize, 2590 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2591 } 2592 2593 void 2594 alc_init_cmb(struct alc_softc *sc) 2595 { 2596 struct alc_ring_data *rd; 2597 2598 rd = &sc->alc_rdata; 2599 bzero(rd->alc_cmb, ALC_CMB_SZ); 2600 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0, 2601 sc->alc_cdata.alc_cmb_map->dm_mapsize, 2602 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2603 } 2604 2605 void 2606 alc_init_smb(struct alc_softc *sc) 2607 { 2608 struct alc_ring_data *rd; 2609 2610 rd = &sc->alc_rdata; 2611 bzero(rd->alc_smb, ALC_SMB_SZ); 2612 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 2613 sc->alc_cdata.alc_smb_map->dm_mapsize, 2614 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2615 } 2616 2617 void 2618 alc_rxvlan(struct alc_softc *sc) 2619 { 2620 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 2621 uint32_t reg; 2622 2623 reg = CSR_READ_4(sc, ALC_MAC_CFG); 2624 if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) 2625 reg |= MAC_CFG_VLAN_TAG_STRIP; 2626 else 2627 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 2628 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 2629 } 2630 2631 void 2632 alc_iff(struct alc_softc *sc) 2633 { 2634 struct arpcom *ac = &sc->sc_arpcom; 2635 struct ifnet *ifp = &ac->ac_if; 2636 struct ether_multi *enm; 2637 struct ether_multistep step; 2638 uint32_t crc; 2639 uint32_t mchash[2]; 2640 uint32_t rxcfg; 2641 2642 rxcfg = CSR_READ_4(sc, ALC_MAC_CFG); 2643 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 2644 ifp->if_flags &= ~IFF_ALLMULTI; 2645 2646 /* 2647 * Always accept broadcast frames. 2648 */ 2649 rxcfg |= MAC_CFG_BCAST; 2650 2651 if (ifp->if_flags & IFF_PROMISC || ac->ac_multirangecnt > 0) { 2652 ifp->if_flags |= IFF_ALLMULTI; 2653 if (ifp->if_flags & IFF_PROMISC) 2654 rxcfg |= MAC_CFG_PROMISC; 2655 else 2656 rxcfg |= MAC_CFG_ALLMULTI; 2657 mchash[0] = mchash[1] = 0xFFFFFFFF; 2658 } else { 2659 /* Program new filter. */ 2660 bzero(mchash, sizeof(mchash)); 2661 2662 ETHER_FIRST_MULTI(step, ac, enm); 2663 while (enm != NULL) { 2664 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2665 2666 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 2667 2668 ETHER_NEXT_MULTI(step, enm); 2669 } 2670 } 2671 2672 CSR_WRITE_4(sc, ALC_MAR0, mchash[0]); 2673 CSR_WRITE_4(sc, ALC_MAR1, mchash[1]); 2674 CSR_WRITE_4(sc, ALC_MAC_CFG, rxcfg); 2675 } 2676