1 /* $OpenBSD: if_alc.c,v 1.26 2013/12/28 03:34:53 deraadt Exp $ */ 2 /*- 3 * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* Driver for Atheros AR8131/AR8132 PCIe Ethernet. */ 30 31 #include "bpfilter.h" 32 #include "vlan.h" 33 34 #include <sys/param.h> 35 #include <sys/endian.h> 36 #include <sys/systm.h> 37 #include <sys/types.h> 38 #include <sys/sockio.h> 39 #include <sys/mbuf.h> 40 #include <sys/queue.h> 41 #include <sys/kernel.h> 42 #include <sys/device.h> 43 #include <sys/timeout.h> 44 #include <sys/socket.h> 45 46 #include <machine/bus.h> 47 48 #include <net/if.h> 49 #include <net/if_dl.h> 50 #include <net/if_media.h> 51 52 #ifdef INET 53 #include <netinet/in.h> 54 #include <netinet/in_systm.h> 55 #include <netinet/ip.h> 56 #include <netinet/if_ether.h> 57 #endif 58 59 #include <net/if_types.h> 60 #include <net/if_vlan_var.h> 61 62 #if NBPFILTER > 0 63 #include <net/bpf.h> 64 #endif 65 66 #include <dev/rndvar.h> 67 68 #include <dev/mii/mii.h> 69 #include <dev/mii/miivar.h> 70 71 #include <dev/pci/pcireg.h> 72 #include <dev/pci/pcivar.h> 73 #include <dev/pci/pcidevs.h> 74 75 #include <dev/pci/if_alcreg.h> 76 77 int alc_match(struct device *, void *, void *); 78 void alc_attach(struct device *, struct device *, void *); 79 int alc_detach(struct device *, int); 80 int alc_activate(struct device *, int); 81 82 int alc_init(struct ifnet *); 83 void alc_start(struct ifnet *); 84 int alc_ioctl(struct ifnet *, u_long, caddr_t); 85 void alc_watchdog(struct ifnet *); 86 int alc_mediachange(struct ifnet *); 87 void alc_mediastatus(struct ifnet *, struct ifmediareq *); 88 89 void alc_aspm(struct alc_softc *, int); 90 void alc_disable_l0s_l1(struct alc_softc *); 91 int alc_dma_alloc(struct alc_softc *); 92 void alc_dma_free(struct alc_softc *); 93 int alc_encap(struct alc_softc *, struct mbuf **); 94 void alc_get_macaddr(struct alc_softc *); 95 void alc_init_cmb(struct alc_softc *); 96 void alc_init_rr_ring(struct alc_softc *); 97 int alc_init_rx_ring(struct alc_softc *); 98 void alc_init_smb(struct alc_softc *); 99 void alc_init_tx_ring(struct alc_softc *); 100 int alc_intr(void *); 101 void alc_mac_config(struct alc_softc *); 102 int alc_miibus_readreg(struct device *, int, int); 103 void alc_miibus_statchg(struct device *); 104 void alc_miibus_writereg(struct device *, int, int, int); 105 int alc_newbuf(struct alc_softc *, struct alc_rxdesc *); 106 void alc_phy_down(struct alc_softc *); 107 void alc_phy_reset(struct alc_softc *); 108 void alc_reset(struct alc_softc *); 109 void alc_rxeof(struct alc_softc *, struct rx_rdesc *); 110 void alc_rxintr(struct alc_softc *); 111 void alc_iff(struct alc_softc *); 112 void alc_rxvlan(struct alc_softc *); 113 void alc_start_queue(struct alc_softc *); 114 void alc_stats_clear(struct alc_softc *); 115 void alc_stats_update(struct alc_softc *); 116 void alc_stop(struct alc_softc *); 117 void alc_stop_mac(struct alc_softc *); 118 void alc_stop_queue(struct alc_softc *); 119 void alc_tick(void *); 120 void alc_txeof(struct alc_softc *); 121 122 uint32_t alc_dma_burst[] = { 128, 256, 512, 1024, 2048, 4096, 0 }; 123 124 const struct pci_matchid alc_devices[] = { 125 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L1C }, 126 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L2C }, 127 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L1D }, 128 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L1D_1 }, 129 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L2C_1 }, 130 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L2C_2 } 131 }; 132 133 struct cfattach alc_ca = { 134 sizeof (struct alc_softc), alc_match, alc_attach, NULL, 135 alc_activate 136 }; 137 138 struct cfdriver alc_cd = { 139 NULL, "alc", DV_IFNET 140 }; 141 142 int alcdebug = 0; 143 #define DPRINTF(x) do { if (alcdebug) printf x; } while (0) 144 145 #define ALC_CSUM_FEATURES (M_TCP_CSUM_OUT | M_UDP_CSUM_OUT) 146 147 int 148 alc_miibus_readreg(struct device *dev, int phy, int reg) 149 { 150 struct alc_softc *sc = (struct alc_softc *)dev; 151 uint32_t v; 152 int i; 153 154 if (phy != sc->alc_phyaddr) 155 return (0); 156 157 /* 158 * For AR8132 fast ethernet controller, do not report 1000baseT 159 * capability to mii(4). Even though AR8132 uses the same 160 * model/revision number of F1 gigabit PHY, the PHY has no 161 * ability to establish 1000baseT link. 162 */ 163 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0 && 164 reg == MII_EXTSR) 165 return (0); 166 167 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 168 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 169 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 170 DELAY(5); 171 v = CSR_READ_4(sc, ALC_MDIO); 172 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 173 break; 174 } 175 176 if (i == 0) { 177 printf("%s: phy read timeout: phy %d, reg %d\n", 178 sc->sc_dev.dv_xname, phy, reg); 179 return (0); 180 } 181 182 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 183 } 184 185 void 186 alc_miibus_writereg(struct device *dev, int phy, int reg, int val) 187 { 188 struct alc_softc *sc = (struct alc_softc *)dev; 189 uint32_t v; 190 int i; 191 192 if (phy != sc->alc_phyaddr) 193 return; 194 195 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 196 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 197 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 198 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 199 DELAY(5); 200 v = CSR_READ_4(sc, ALC_MDIO); 201 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 202 break; 203 } 204 205 if (i == 0) 206 printf("%s: phy write timeout: phy %d, reg %d\n", 207 sc->sc_dev.dv_xname, phy, reg); 208 } 209 210 void 211 alc_miibus_statchg(struct device *dev) 212 { 213 struct alc_softc *sc = (struct alc_softc *)dev; 214 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 215 struct mii_data *mii = &sc->sc_miibus; 216 uint32_t reg; 217 218 if ((ifp->if_flags & IFF_RUNNING) == 0) 219 return; 220 221 sc->alc_flags &= ~ALC_FLAG_LINK; 222 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 223 (IFM_ACTIVE | IFM_AVALID)) { 224 switch (IFM_SUBTYPE(mii->mii_media_active)) { 225 case IFM_10_T: 226 case IFM_100_TX: 227 sc->alc_flags |= ALC_FLAG_LINK; 228 break; 229 case IFM_1000_T: 230 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 231 sc->alc_flags |= ALC_FLAG_LINK; 232 break; 233 default: 234 break; 235 } 236 } 237 alc_stop_queue(sc); 238 /* Stop Rx/Tx MACs. */ 239 alc_stop_mac(sc); 240 241 /* Program MACs with resolved speed/duplex/flow-control. */ 242 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 243 alc_start_queue(sc); 244 alc_mac_config(sc); 245 /* Re-enable Tx/Rx MACs. */ 246 reg = CSR_READ_4(sc, ALC_MAC_CFG); 247 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 248 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 249 alc_aspm(sc, IFM_SUBTYPE(mii->mii_media_active)); 250 } 251 } 252 253 void 254 alc_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 255 { 256 struct alc_softc *sc = ifp->if_softc; 257 struct mii_data *mii = &sc->sc_miibus; 258 259 if ((ifp->if_flags & IFF_UP) == 0) 260 return; 261 262 mii_pollstat(mii); 263 ifmr->ifm_status = mii->mii_media_status; 264 ifmr->ifm_active = mii->mii_media_active; 265 } 266 267 int 268 alc_mediachange(struct ifnet *ifp) 269 { 270 struct alc_softc *sc = ifp->if_softc; 271 struct mii_data *mii = &sc->sc_miibus; 272 int error; 273 274 if (mii->mii_instance != 0) { 275 struct mii_softc *miisc; 276 277 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 278 mii_phy_reset(miisc); 279 } 280 error = mii_mediachg(mii); 281 282 return (error); 283 } 284 285 int 286 alc_match(struct device *dev, void *match, void *aux) 287 { 288 return pci_matchbyid((struct pci_attach_args *)aux, alc_devices, 289 nitems(alc_devices)); 290 } 291 292 void 293 alc_get_macaddr(struct alc_softc *sc) 294 { 295 uint32_t ea[2], opt; 296 uint16_t val; 297 int eeprom, i; 298 299 eeprom = 0; 300 opt = CSR_READ_4(sc, ALC_OPT_CFG); 301 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 && 302 (CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) { 303 /* 304 * EEPROM found, let TWSI reload EEPROM configuration. 305 * This will set ethernet address of controller. 306 */ 307 eeprom++; 308 switch (sc->sc_product) { 309 case PCI_PRODUCT_ATTANSIC_L1C: 310 case PCI_PRODUCT_ATTANSIC_L2C: 311 if ((opt & OPT_CFG_CLK_ENB) == 0) { 312 opt |= OPT_CFG_CLK_ENB; 313 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 314 CSR_READ_4(sc, ALC_OPT_CFG); 315 DELAY(1000); 316 } 317 break; 318 case PCI_PRODUCT_ATTANSIC_L1D: 319 case PCI_PRODUCT_ATTANSIC_L1D_1: 320 case PCI_PRODUCT_ATTANSIC_L2C_1: 321 case PCI_PRODUCT_ATTANSIC_L2C_2: 322 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 323 ALC_MII_DBG_ADDR, 0x00); 324 val = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr, 325 ALC_MII_DBG_DATA); 326 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 327 ALC_MII_DBG_DATA, val & 0xFF7F); 328 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 329 ALC_MII_DBG_ADDR, 0x3B); 330 val = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr, 331 ALC_MII_DBG_DATA); 332 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 333 ALC_MII_DBG_DATA, val | 0x0008); 334 DELAY(20); 335 break; 336 } 337 338 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 339 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 340 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 341 CSR_READ_4(sc, ALC_WOL_CFG); 342 343 CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) | 344 TWSI_CFG_SW_LD_START); 345 for (i = 100; i > 0; i--) { 346 DELAY(1000); 347 if ((CSR_READ_4(sc, ALC_TWSI_CFG) & 348 TWSI_CFG_SW_LD_START) == 0) 349 break; 350 } 351 if (i == 0) 352 printf("%s: reloading EEPROM timeout!\n", 353 sc->sc_dev.dv_xname); 354 } else { 355 if (alcdebug) 356 printf("%s: EEPROM not found!\n", sc->sc_dev.dv_xname); 357 } 358 if (eeprom != 0) { 359 switch (sc->sc_product) { 360 case PCI_PRODUCT_ATTANSIC_L1C: 361 case PCI_PRODUCT_ATTANSIC_L2C: 362 if ((opt & OPT_CFG_CLK_ENB) != 0) { 363 opt &= ~OPT_CFG_CLK_ENB; 364 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 365 CSR_READ_4(sc, ALC_OPT_CFG); 366 DELAY(1000); 367 } 368 break; 369 case PCI_PRODUCT_ATTANSIC_L1D: 370 case PCI_PRODUCT_ATTANSIC_L1D_1: 371 case PCI_PRODUCT_ATTANSIC_L2C_1: 372 case PCI_PRODUCT_ATTANSIC_L2C_2: 373 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 374 ALC_MII_DBG_ADDR, 0x00); 375 val = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr, 376 ALC_MII_DBG_DATA); 377 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 378 ALC_MII_DBG_DATA, val | 0x0080); 379 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 380 ALC_MII_DBG_ADDR, 0x3B); 381 val = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr, 382 ALC_MII_DBG_DATA); 383 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 384 ALC_MII_DBG_DATA, val & 0xFFF7); 385 DELAY(20); 386 break; 387 } 388 } 389 390 ea[0] = CSR_READ_4(sc, ALC_PAR0); 391 ea[1] = CSR_READ_4(sc, ALC_PAR1); 392 sc->alc_eaddr[0] = (ea[1] >> 8) & 0xFF; 393 sc->alc_eaddr[1] = (ea[1] >> 0) & 0xFF; 394 sc->alc_eaddr[2] = (ea[0] >> 24) & 0xFF; 395 sc->alc_eaddr[3] = (ea[0] >> 16) & 0xFF; 396 sc->alc_eaddr[4] = (ea[0] >> 8) & 0xFF; 397 sc->alc_eaddr[5] = (ea[0] >> 0) & 0xFF; 398 } 399 400 void 401 alc_disable_l0s_l1(struct alc_softc *sc) 402 { 403 uint32_t pmcfg; 404 405 /* Another magic from vendor. */ 406 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 407 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_CLK_SWH_L1 | 408 PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | PM_CFG_MAC_ASPM_CHK | 409 PM_CFG_SERDES_PD_EX_L1); 410 pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB | 411 PM_CFG_SERDES_L1_ENB; 412 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 413 } 414 415 void 416 alc_phy_reset(struct alc_softc *sc) 417 { 418 uint16_t data; 419 420 /* Reset magic from Linux. */ 421 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_SEL_ANA_RESET); 422 CSR_READ_2(sc, ALC_GPHY_CFG); 423 DELAY(10 * 1000); 424 425 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | 426 GPHY_CFG_SEL_ANA_RESET); 427 CSR_READ_2(sc, ALC_GPHY_CFG); 428 DELAY(10 * 1000); 429 430 /* DSP fixup, Vendor magic. */ 431 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1) { 432 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 433 ALC_MII_DBG_ADDR, 0x000A); 434 data = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr, 435 ALC_MII_DBG_DATA); 436 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 437 ALC_MII_DBG_DATA, data & 0xDFFF); 438 } 439 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D || 440 sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D_1 || 441 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1 || 442 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_2) { 443 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 444 ALC_MII_DBG_ADDR, 0x003B); 445 data = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr, 446 ALC_MII_DBG_DATA); 447 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 448 ALC_MII_DBG_DATA, data & 0xFFF7); 449 DELAY(20 * 1000); 450 } 451 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D) { 452 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 453 ALC_MII_DBG_ADDR, 0x0029); 454 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 455 ALC_MII_DBG_DATA, 0x929D); 456 } 457 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1C || 458 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C || 459 sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D_1 || 460 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_2) { 461 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 462 ALC_MII_DBG_ADDR, 0x0029); 463 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 464 ALC_MII_DBG_DATA, 0xB6DD); 465 } 466 467 /* Load DSP codes, vendor magic. */ 468 data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE | 469 ((1 << ANA_INTERVAL_SEL_TIMER_SHIFT) & ANA_INTERVAL_SEL_TIMER_MASK); 470 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 471 ALC_MII_DBG_ADDR, MII_ANA_CFG18); 472 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 473 ALC_MII_DBG_DATA, data); 474 475 data = ((2 << ANA_SERDES_CDR_BW_SHIFT) & ANA_SERDES_CDR_BW_MASK) | 476 ANA_SERDES_EN_DEEM | ANA_SERDES_SEL_HSP | ANA_SERDES_EN_PLL | 477 ANA_SERDES_EN_LCKDT; 478 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 479 ALC_MII_DBG_ADDR, MII_ANA_CFG5); 480 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 481 ALC_MII_DBG_DATA, data); 482 483 data = ((44 << ANA_LONG_CABLE_TH_100_SHIFT) & 484 ANA_LONG_CABLE_TH_100_MASK) | 485 ((33 << ANA_SHORT_CABLE_TH_100_SHIFT) & 486 ANA_SHORT_CABLE_TH_100_SHIFT) | 487 ANA_BP_BAD_LINK_ACCUM | ANA_BP_SMALL_BW; 488 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 489 ALC_MII_DBG_ADDR, MII_ANA_CFG54); 490 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 491 ALC_MII_DBG_DATA, data); 492 493 data = ((11 << ANA_IECHO_ADJ_3_SHIFT) & ANA_IECHO_ADJ_3_MASK) | 494 ((11 << ANA_IECHO_ADJ_2_SHIFT) & ANA_IECHO_ADJ_2_MASK) | 495 ((8 << ANA_IECHO_ADJ_1_SHIFT) & ANA_IECHO_ADJ_1_MASK) | 496 ((8 << ANA_IECHO_ADJ_0_SHIFT) & ANA_IECHO_ADJ_0_MASK); 497 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 498 ALC_MII_DBG_ADDR, MII_ANA_CFG4); 499 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 500 ALC_MII_DBG_DATA, data); 501 502 data = ((7 & ANA_MANUL_SWICH_ON_SHIFT) & ANA_MANUL_SWICH_ON_MASK) | 503 ANA_RESTART_CAL | ANA_MAN_ENABLE | ANA_SEL_HSP | ANA_EN_HB | 504 ANA_OEN_125M; 505 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 506 ALC_MII_DBG_ADDR, MII_ANA_CFG0); 507 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 508 ALC_MII_DBG_DATA, data); 509 DELAY(1000); 510 511 /* Disable hibernation. */ 512 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 513 0x0029); 514 data = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr, 515 ALC_MII_DBG_DATA); 516 data &= ~0x8000; 517 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 518 data); 519 520 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 521 0x000B); 522 data = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr, 523 ALC_MII_DBG_DATA); 524 data &= ~0x8000; 525 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 526 data); 527 } 528 529 void 530 alc_phy_down(struct alc_softc *sc) 531 { 532 switch (sc->sc_product) { 533 case PCI_PRODUCT_ATTANSIC_L1D: 534 case PCI_PRODUCT_ATTANSIC_L1D_1: 535 /* 536 * GPHY power down caused more problems on AR8151 v2.0. 537 * When driver is reloaded after GPHY power down, 538 * accesses to PHY/MAC registers hung the system. Only 539 * cold boot recovered from it. I'm not sure whether 540 * AR8151 v1.0 also requires this one though. I don't 541 * have AR8151 v1.0 controller in hand. 542 * The only option left is to isolate the PHY and 543 * initiates power down the PHY which in turn saves 544 * more power when driver is unloaded. 545 */ 546 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 547 MII_BMCR, BMCR_ISO | BMCR_PDOWN); 548 break; 549 default: 550 /* Force PHY down. */ 551 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | 552 GPHY_CFG_SEL_ANA_RESET | GPHY_CFG_PHY_IDDQ | 553 GPHY_CFG_PWDOWN_HW); 554 DELAY(1000); 555 break; 556 } 557 } 558 559 void 560 alc_aspm(struct alc_softc *sc, int media) 561 { 562 uint32_t pmcfg; 563 uint16_t linkcfg; 564 565 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 566 if ((sc->alc_flags & (ALC_FLAG_APS | ALC_FLAG_PCIE)) == 567 (ALC_FLAG_APS | ALC_FLAG_PCIE)) 568 linkcfg = CSR_READ_2(sc, sc->alc_expcap + 569 PCI_PCIE_LCSR); 570 else 571 linkcfg = 0; 572 pmcfg &= ~PM_CFG_SERDES_PD_EX_L1; 573 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_LCKDET_TIMER_MASK); 574 pmcfg |= PM_CFG_MAC_ASPM_CHK; 575 pmcfg |= (PM_CFG_LCKDET_TIMER_DEFAULT << PM_CFG_LCKDET_TIMER_SHIFT); 576 pmcfg &= ~(PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 577 578 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 579 /* Disable extended sync except AR8152 B v1.0 */ 580 linkcfg &= ~0x80; 581 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1 && 582 sc->alc_rev == ATHEROS_AR8152_B_V10) 583 linkcfg |= 0x80; 584 CSR_WRITE_2(sc, sc->alc_expcap + PCI_PCIE_LCSR, 585 linkcfg); 586 pmcfg &= ~(PM_CFG_EN_BUFS_RX_L0S | PM_CFG_SA_DLY_ENB | 587 PM_CFG_HOTRST); 588 pmcfg |= (PM_CFG_L1_ENTRY_TIMER_DEFAULT << 589 PM_CFG_L1_ENTRY_TIMER_SHIFT); 590 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 591 pmcfg |= (PM_CFG_PM_REQ_TIMER_DEFAULT << 592 PM_CFG_PM_REQ_TIMER_SHIFT); 593 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_PCIE_RECV; 594 } 595 596 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 597 if ((sc->alc_flags & ALC_FLAG_L0S) != 0) 598 pmcfg |= PM_CFG_ASPM_L0S_ENB; 599 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 600 pmcfg |= PM_CFG_ASPM_L1_ENB; 601 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 602 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1) 603 pmcfg &= ~PM_CFG_ASPM_L0S_ENB; 604 pmcfg &= ~(PM_CFG_SERDES_L1_ENB | 605 PM_CFG_SERDES_PLL_L1_ENB | 606 PM_CFG_SERDES_BUDS_RX_L1_ENB); 607 pmcfg |= PM_CFG_CLK_SWH_L1; 608 if (media == IFM_100_TX || media == IFM_1000_T) { 609 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK; 610 switch (sc->sc_product) { 611 case PCI_PRODUCT_ATTANSIC_L2C_1: 612 pmcfg |= (7 << 613 PM_CFG_L1_ENTRY_TIMER_SHIFT); 614 break; 615 case PCI_PRODUCT_ATTANSIC_L1D_1: 616 case PCI_PRODUCT_ATTANSIC_L2C_2: 617 pmcfg |= (4 << 618 PM_CFG_L1_ENTRY_TIMER_SHIFT); 619 break; 620 default: 621 pmcfg |= (15 << 622 PM_CFG_L1_ENTRY_TIMER_SHIFT); 623 break; 624 } 625 } 626 } else { 627 pmcfg |= PM_CFG_SERDES_L1_ENB | 628 PM_CFG_SERDES_PLL_L1_ENB | 629 PM_CFG_SERDES_BUDS_RX_L1_ENB; 630 pmcfg &= ~(PM_CFG_CLK_SWH_L1 | 631 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 632 } 633 } else { 634 pmcfg &= ~(PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_L1_ENB | 635 PM_CFG_SERDES_PLL_L1_ENB); 636 pmcfg |= PM_CFG_CLK_SWH_L1; 637 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 638 pmcfg |= PM_CFG_ASPM_L1_ENB; 639 } 640 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 641 } 642 643 void 644 alc_attach(struct device *parent, struct device *self, void *aux) 645 { 646 647 struct alc_softc *sc = (struct alc_softc *)self; 648 struct pci_attach_args *pa = aux; 649 pci_chipset_tag_t pc = pa->pa_pc; 650 pci_intr_handle_t ih; 651 const char *intrstr; 652 struct ifnet *ifp; 653 pcireg_t memtype; 654 char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/L1" }; 655 uint16_t burst; 656 int base, state, error = 0; 657 uint32_t cap, ctl, val; 658 659 /* 660 * Allocate IO memory 661 */ 662 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, ALC_PCIR_BAR); 663 if (pci_mapreg_map(pa, ALC_PCIR_BAR, memtype, 0, &sc->sc_mem_bt, 664 &sc->sc_mem_bh, NULL, &sc->sc_mem_size, 0)) { 665 printf(": can't map mem space\n"); 666 return; 667 } 668 669 if (pci_intr_map_msi(pa, &ih) != 0 && pci_intr_map(pa, &ih) != 0) { 670 printf(": can't map interrupt\n"); 671 goto fail; 672 } 673 674 /* 675 * Allocate IRQ 676 */ 677 intrstr = pci_intr_string(pc, ih); 678 sc->sc_irq_handle = pci_intr_establish(pc, ih, IPL_NET, alc_intr, sc, 679 sc->sc_dev.dv_xname); 680 if (sc->sc_irq_handle == NULL) { 681 printf(": could not establish interrupt"); 682 if (intrstr != NULL) 683 printf(" at %s", intrstr); 684 printf("\n"); 685 goto fail; 686 } 687 printf(": %s", intrstr); 688 689 sc->sc_dmat = pa->pa_dmat; 690 sc->sc_pct = pa->pa_pc; 691 sc->sc_pcitag = pa->pa_tag; 692 693 /* Set PHY address. */ 694 sc->alc_phyaddr = ALC_PHY_ADDR; 695 696 /* Get PCI and chip id/revision. */ 697 sc->sc_product = PCI_PRODUCT(pa->pa_id); 698 sc->alc_rev = PCI_REVISION(pa->pa_class); 699 700 /* Initialize DMA parameters. */ 701 sc->alc_dma_rd_burst = 0; 702 sc->alc_dma_wr_burst = 0; 703 sc->alc_rcb = DMA_CFG_RCB_64; 704 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PCIEXPRESS, 705 &base, NULL)) { 706 sc->alc_flags |= ALC_FLAG_PCIE; 707 sc->alc_expcap = base; 708 burst = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 709 base + PCI_PCIE_DCSR) >> 16; 710 sc->alc_dma_rd_burst = (burst & 0x7000) >> 12; 711 sc->alc_dma_wr_burst = (burst & 0x00e0) >> 5; 712 if (alcdebug) { 713 printf("%s: Read request size : %u bytes.\n", 714 sc->sc_dev.dv_xname, 715 alc_dma_burst[sc->alc_dma_rd_burst]); 716 printf("%s: TLP payload size : %u bytes.\n", 717 sc->sc_dev.dv_xname, 718 alc_dma_burst[sc->alc_dma_wr_burst]); 719 } 720 if (alc_dma_burst[sc->alc_dma_rd_burst] > 1024) 721 sc->alc_dma_rd_burst = 3; 722 if (alc_dma_burst[sc->alc_dma_wr_burst] > 1024) 723 sc->alc_dma_wr_burst = 3; 724 /* Clear data link and flow-control protocol error. */ 725 val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV); 726 val &= ~(PEX_UNC_ERR_SEV_DLP | PEX_UNC_ERR_SEV_FCP); 727 CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val); 728 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 729 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 730 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, 731 CSR_READ_4(sc, ALC_PCIE_PHYMISC) | 732 PCIE_PHYMISC_FORCE_RCV_DET); 733 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1 && 734 sc->alc_rev == ATHEROS_AR8152_B_V10) { 735 val = CSR_READ_4(sc, ALC_PCIE_PHYMISC2); 736 val &= ~(PCIE_PHYMISC2_SERDES_CDR_MASK | 737 PCIE_PHYMISC2_SERDES_TH_MASK); 738 val |= 3 << PCIE_PHYMISC2_SERDES_CDR_SHIFT; 739 val |= 3 << PCIE_PHYMISC2_SERDES_TH_SHIFT; 740 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC2, val); 741 } 742 /* Disable ASPM L0S and L1. */ 743 cap = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 744 base + PCI_PCIE_LCAP) >> 16; 745 if ((cap & 0x00000c00) != 0) { 746 ctl = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 747 base + PCI_PCIE_LCSR) >> 16; 748 if ((ctl & 0x08) != 0) 749 sc->alc_rcb = DMA_CFG_RCB_128; 750 if (alcdebug) 751 printf("%s: RCB %u bytes\n", 752 sc->sc_dev.dv_xname, 753 sc->alc_rcb == DMA_CFG_RCB_64 ? 64 : 128); 754 state = ctl & 0x03; 755 if (state & 0x01) 756 sc->alc_flags |= ALC_FLAG_L0S; 757 if (state & 0x02) 758 sc->alc_flags |= ALC_FLAG_L1S; 759 if (alcdebug) 760 printf("%s: ASPM %s %s\n", 761 sc->sc_dev.dv_xname, 762 aspm_state[state], 763 state == 0 ? "disabled" : "enabled"); 764 alc_disable_l0s_l1(sc); 765 } 766 } 767 768 /* Reset PHY. */ 769 alc_phy_reset(sc); 770 771 /* Reset the ethernet controller. */ 772 alc_reset(sc); 773 774 /* 775 * One odd thing is AR8132 uses the same PHY hardware(F1 776 * gigabit PHY) of AR8131. So atphy(4) of AR8132 reports 777 * the PHY supports 1000Mbps but that's not true. The PHY 778 * used in AR8132 can't establish gigabit link even if it 779 * shows the same PHY model/revision number of AR8131. 780 */ 781 switch (sc->sc_product) { 782 case PCI_PRODUCT_ATTANSIC_L2C_1: 783 case PCI_PRODUCT_ATTANSIC_L2C_2: 784 sc->alc_flags |= ALC_FLAG_APS; 785 /* FALLTHROUGH */ 786 case PCI_PRODUCT_ATTANSIC_L2C: 787 sc->alc_flags |= ALC_FLAG_FASTETHER; 788 break; 789 case PCI_PRODUCT_ATTANSIC_L1D: 790 case PCI_PRODUCT_ATTANSIC_L1D_1: 791 sc->alc_flags |= ALC_FLAG_APS; 792 /* FALLTHROUGH */ 793 default: 794 break; 795 } 796 sc->alc_flags |= ALC_FLAG_ASPM_MON | ALC_FLAG_JUMBO; 797 798 switch (sc->sc_product) { 799 case PCI_PRODUCT_ATTANSIC_L1C: 800 case PCI_PRODUCT_ATTANSIC_L2C: 801 sc->alc_max_framelen = 9 * 1024; 802 break; 803 case PCI_PRODUCT_ATTANSIC_L1D: 804 case PCI_PRODUCT_ATTANSIC_L1D_1: 805 case PCI_PRODUCT_ATTANSIC_L2C_1: 806 case PCI_PRODUCT_ATTANSIC_L2C_2: 807 sc->alc_max_framelen = 6 * 1024; 808 break; 809 } 810 811 /* 812 * It seems that AR813x/AR815x has silicon bug for SMB. In 813 * addition, Atheros said that enabling SMB wouldn't improve 814 * performance. However I think it's bad to access lots of 815 * registers to extract MAC statistics. 816 */ 817 sc->alc_flags |= ALC_FLAG_SMB_BUG; 818 /* 819 * Don't use Tx CMB. It is known to have silicon bug. 820 */ 821 sc->alc_flags |= ALC_FLAG_CMB_BUG; 822 823 sc->alc_chip_rev = CSR_READ_4(sc, ALC_MASTER_CFG) >> 824 MASTER_CHIP_REV_SHIFT; 825 if (alcdebug) { 826 printf("%s: PCI device revision : 0x%04x\n", 827 sc->sc_dev.dv_xname, sc->alc_rev); 828 printf("%s: Chip id/revision : 0x%04x\n", 829 sc->sc_dev.dv_xname, sc->alc_chip_rev); 830 printf("%s: %u Tx FIFO, %u Rx FIFO\n", sc->sc_dev.dv_xname, 831 CSR_READ_4(sc, ALC_SRAM_TX_FIFO_LEN) * 8, 832 CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN) * 8); 833 } 834 835 error = alc_dma_alloc(sc); 836 if (error) 837 goto fail; 838 839 /* Load station address. */ 840 alc_get_macaddr(sc); 841 842 ifp = &sc->sc_arpcom.ac_if; 843 ifp->if_softc = sc; 844 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 845 ifp->if_ioctl = alc_ioctl; 846 ifp->if_start = alc_start; 847 ifp->if_watchdog = alc_watchdog; 848 IFQ_SET_MAXLEN(&ifp->if_snd, ALC_TX_RING_CNT - 1); 849 IFQ_SET_READY(&ifp->if_snd); 850 bcopy(sc->alc_eaddr, sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN); 851 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 852 853 ifp->if_capabilities = IFCAP_VLAN_MTU; 854 855 #ifdef ALC_CHECKSUM 856 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 857 IFCAP_CSUM_UDPv4; 858 #endif 859 860 #if NVLAN > 0 861 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 862 #endif 863 864 printf(", address %s\n", ether_sprintf(sc->sc_arpcom.ac_enaddr)); 865 866 /* Set up MII bus. */ 867 sc->sc_miibus.mii_ifp = ifp; 868 sc->sc_miibus.mii_readreg = alc_miibus_readreg; 869 sc->sc_miibus.mii_writereg = alc_miibus_writereg; 870 sc->sc_miibus.mii_statchg = alc_miibus_statchg; 871 872 ifmedia_init(&sc->sc_miibus.mii_media, 0, alc_mediachange, 873 alc_mediastatus); 874 mii_attach(self, &sc->sc_miibus, 0xffffffff, MII_PHY_ANY, 875 MII_OFFSET_ANY, MIIF_DOPAUSE); 876 877 if (LIST_FIRST(&sc->sc_miibus.mii_phys) == NULL) { 878 printf("%s: no PHY found!\n", sc->sc_dev.dv_xname); 879 ifmedia_add(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL, 880 0, NULL); 881 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL); 882 } else 883 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_AUTO); 884 885 if_attach(ifp); 886 ether_ifattach(ifp); 887 888 timeout_set(&sc->alc_tick_ch, alc_tick, sc); 889 890 return; 891 fail: 892 alc_dma_free(sc); 893 if (sc->sc_irq_handle != NULL) 894 pci_intr_disestablish(pc, sc->sc_irq_handle); 895 if (sc->sc_mem_size) 896 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 897 } 898 899 int 900 alc_detach(struct device *self, int flags) 901 { 902 struct alc_softc *sc = (struct alc_softc *)self; 903 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 904 int s; 905 906 s = splnet(); 907 alc_stop(sc); 908 splx(s); 909 910 mii_detach(&sc->sc_miibus, MII_PHY_ANY, MII_OFFSET_ANY); 911 912 /* Delete all remaining media. */ 913 ifmedia_delete_instance(&sc->sc_miibus.mii_media, IFM_INST_ANY); 914 915 ether_ifdetach(ifp); 916 if_detach(ifp); 917 alc_dma_free(sc); 918 919 alc_phy_down(sc); 920 if (sc->sc_irq_handle != NULL) { 921 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 922 sc->sc_irq_handle = NULL; 923 } 924 925 return (0); 926 } 927 928 int 929 alc_activate(struct device *self, int act) 930 { 931 struct alc_softc *sc = (struct alc_softc *)self; 932 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 933 int rv = 0; 934 935 switch (act) { 936 case DVACT_SUSPEND: 937 if (ifp->if_flags & IFF_RUNNING) 938 alc_stop(sc); 939 rv = config_activate_children(self, act); 940 break; 941 case DVACT_RESUME: 942 if (ifp->if_flags & IFF_UP) 943 alc_init(ifp); 944 break; 945 default: 946 rv = config_activate_children(self, act); 947 break; 948 } 949 return (rv); 950 } 951 952 int 953 alc_dma_alloc(struct alc_softc *sc) 954 { 955 struct alc_txdesc *txd; 956 struct alc_rxdesc *rxd; 957 int nsegs, error, i; 958 959 /* 960 * Create DMA stuffs for TX ring 961 */ 962 error = bus_dmamap_create(sc->sc_dmat, ALC_TX_RING_SZ, 1, 963 ALC_TX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->alc_cdata.alc_tx_ring_map); 964 if (error) 965 return (ENOBUFS); 966 967 /* Allocate DMA'able memory for TX ring */ 968 error = bus_dmamem_alloc(sc->sc_dmat, ALC_TX_RING_SZ, 969 ETHER_ALIGN, 0, &sc->alc_rdata.alc_tx_ring_seg, 1, 970 &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 971 if (error) { 972 printf("%s: could not allocate DMA'able memory for Tx ring.\n", 973 sc->sc_dev.dv_xname); 974 return error; 975 } 976 977 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_tx_ring_seg, 978 nsegs, ALC_TX_RING_SZ, (caddr_t *)&sc->alc_rdata.alc_tx_ring, 979 BUS_DMA_NOWAIT); 980 if (error) 981 return (ENOBUFS); 982 983 /* Load the DMA map for Tx ring. */ 984 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 985 sc->alc_rdata.alc_tx_ring, ALC_TX_RING_SZ, NULL, BUS_DMA_WAITOK); 986 if (error) { 987 printf("%s: could not load DMA'able memory for Tx ring.\n", 988 sc->sc_dev.dv_xname); 989 bus_dmamem_free(sc->sc_dmat, 990 (bus_dma_segment_t *)&sc->alc_rdata.alc_tx_ring, 1); 991 return error; 992 } 993 994 sc->alc_rdata.alc_tx_ring_paddr = 995 sc->alc_cdata.alc_tx_ring_map->dm_segs[0].ds_addr; 996 997 /* 998 * Create DMA stuffs for RX ring 999 */ 1000 error = bus_dmamap_create(sc->sc_dmat, ALC_RX_RING_SZ, 1, 1001 ALC_RX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->alc_cdata.alc_rx_ring_map); 1002 if (error) 1003 return (ENOBUFS); 1004 1005 /* Allocate DMA'able memory for RX ring */ 1006 error = bus_dmamem_alloc(sc->sc_dmat, ALC_RX_RING_SZ, 1007 ETHER_ALIGN, 0, &sc->alc_rdata.alc_rx_ring_seg, 1, 1008 &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 1009 if (error) { 1010 printf("%s: could not allocate DMA'able memory for Rx ring.\n", 1011 sc->sc_dev.dv_xname); 1012 return error; 1013 } 1014 1015 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_rx_ring_seg, 1016 nsegs, ALC_RX_RING_SZ, (caddr_t *)&sc->alc_rdata.alc_rx_ring, 1017 BUS_DMA_NOWAIT); 1018 if (error) 1019 return (ENOBUFS); 1020 1021 /* Load the DMA map for Rx ring. */ 1022 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 1023 sc->alc_rdata.alc_rx_ring, ALC_RX_RING_SZ, NULL, BUS_DMA_WAITOK); 1024 if (error) { 1025 printf("%s: could not load DMA'able memory for Rx ring.\n", 1026 sc->sc_dev.dv_xname); 1027 bus_dmamem_free(sc->sc_dmat, 1028 (bus_dma_segment_t *)sc->alc_rdata.alc_rx_ring, 1); 1029 return error; 1030 } 1031 1032 sc->alc_rdata.alc_rx_ring_paddr = 1033 sc->alc_cdata.alc_rx_ring_map->dm_segs[0].ds_addr; 1034 1035 /* 1036 * Create DMA stuffs for RX return ring 1037 */ 1038 error = bus_dmamap_create(sc->sc_dmat, ALC_RR_RING_SZ, 1, 1039 ALC_RR_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->alc_cdata.alc_rr_ring_map); 1040 if (error) 1041 return (ENOBUFS); 1042 1043 /* Allocate DMA'able memory for RX return ring */ 1044 error = bus_dmamem_alloc(sc->sc_dmat, ALC_RR_RING_SZ, 1045 ETHER_ALIGN, 0, &sc->alc_rdata.alc_rr_ring_seg, 1, 1046 &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 1047 if (error) { 1048 printf("%s: could not allocate DMA'able memory for Rx " 1049 "return ring.\n", sc->sc_dev.dv_xname); 1050 return error; 1051 } 1052 1053 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_rr_ring_seg, 1054 nsegs, ALC_RR_RING_SZ, (caddr_t *)&sc->alc_rdata.alc_rr_ring, 1055 BUS_DMA_NOWAIT); 1056 if (error) 1057 return (ENOBUFS); 1058 1059 /* Load the DMA map for Rx return ring. */ 1060 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 1061 sc->alc_rdata.alc_rr_ring, ALC_RR_RING_SZ, NULL, BUS_DMA_WAITOK); 1062 if (error) { 1063 printf("%s: could not load DMA'able memory for Rx return ring." 1064 "\n", sc->sc_dev.dv_xname); 1065 bus_dmamem_free(sc->sc_dmat, 1066 (bus_dma_segment_t *)&sc->alc_rdata.alc_rr_ring, 1); 1067 return error; 1068 } 1069 1070 sc->alc_rdata.alc_rr_ring_paddr = 1071 sc->alc_cdata.alc_rr_ring_map->dm_segs[0].ds_addr; 1072 1073 /* 1074 * Create DMA stuffs for CMB block 1075 */ 1076 error = bus_dmamap_create(sc->sc_dmat, ALC_CMB_SZ, 1, 1077 ALC_CMB_SZ, 0, BUS_DMA_NOWAIT, 1078 &sc->alc_cdata.alc_cmb_map); 1079 if (error) 1080 return (ENOBUFS); 1081 1082 /* Allocate DMA'able memory for CMB block */ 1083 error = bus_dmamem_alloc(sc->sc_dmat, ALC_CMB_SZ, 1084 ETHER_ALIGN, 0, &sc->alc_rdata.alc_cmb_seg, 1, 1085 &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 1086 if (error) { 1087 printf("%s: could not allocate DMA'able memory for " 1088 "CMB block\n", sc->sc_dev.dv_xname); 1089 return error; 1090 } 1091 1092 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_cmb_seg, 1093 nsegs, ALC_CMB_SZ, (caddr_t *)&sc->alc_rdata.alc_cmb, 1094 BUS_DMA_NOWAIT); 1095 if (error) 1096 return (ENOBUFS); 1097 1098 /* Load the DMA map for CMB block. */ 1099 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 1100 sc->alc_rdata.alc_cmb, ALC_CMB_SZ, NULL, 1101 BUS_DMA_WAITOK); 1102 if (error) { 1103 printf("%s: could not load DMA'able memory for CMB block\n", 1104 sc->sc_dev.dv_xname); 1105 bus_dmamem_free(sc->sc_dmat, 1106 (bus_dma_segment_t *)&sc->alc_rdata.alc_cmb, 1); 1107 return error; 1108 } 1109 1110 sc->alc_rdata.alc_cmb_paddr = 1111 sc->alc_cdata.alc_cmb_map->dm_segs[0].ds_addr; 1112 1113 /* 1114 * Create DMA stuffs for SMB block 1115 */ 1116 error = bus_dmamap_create(sc->sc_dmat, ALC_SMB_SZ, 1, 1117 ALC_SMB_SZ, 0, BUS_DMA_NOWAIT, 1118 &sc->alc_cdata.alc_smb_map); 1119 if (error) 1120 return (ENOBUFS); 1121 1122 /* Allocate DMA'able memory for SMB block */ 1123 error = bus_dmamem_alloc(sc->sc_dmat, ALC_SMB_SZ, 1124 ETHER_ALIGN, 0, &sc->alc_rdata.alc_smb_seg, 1, 1125 &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 1126 if (error) { 1127 printf("%s: could not allocate DMA'able memory for " 1128 "SMB block\n", sc->sc_dev.dv_xname); 1129 return error; 1130 } 1131 1132 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_smb_seg, 1133 nsegs, ALC_SMB_SZ, (caddr_t *)&sc->alc_rdata.alc_smb, 1134 BUS_DMA_NOWAIT); 1135 if (error) 1136 return (ENOBUFS); 1137 1138 /* Load the DMA map for SMB block */ 1139 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 1140 sc->alc_rdata.alc_smb, ALC_SMB_SZ, NULL, 1141 BUS_DMA_WAITOK); 1142 if (error) { 1143 printf("%s: could not load DMA'able memory for SMB block\n", 1144 sc->sc_dev.dv_xname); 1145 bus_dmamem_free(sc->sc_dmat, 1146 (bus_dma_segment_t *)&sc->alc_rdata.alc_smb, 1); 1147 return error; 1148 } 1149 1150 sc->alc_rdata.alc_smb_paddr = 1151 sc->alc_cdata.alc_smb_map->dm_segs[0].ds_addr; 1152 1153 1154 /* Create DMA maps for Tx buffers. */ 1155 for (i = 0; i < ALC_TX_RING_CNT; i++) { 1156 txd = &sc->alc_cdata.alc_txdesc[i]; 1157 txd->tx_m = NULL; 1158 txd->tx_dmamap = NULL; 1159 error = bus_dmamap_create(sc->sc_dmat, ALC_TSO_MAXSIZE, 1160 ALC_MAXTXSEGS, ALC_TSO_MAXSEGSIZE, 0, BUS_DMA_NOWAIT, 1161 &txd->tx_dmamap); 1162 if (error) { 1163 printf("%s: could not create Tx dmamap.\n", 1164 sc->sc_dev.dv_xname); 1165 return error; 1166 } 1167 } 1168 1169 /* Create DMA maps for Rx buffers. */ 1170 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 1171 BUS_DMA_NOWAIT, &sc->alc_cdata.alc_rx_sparemap); 1172 if (error) { 1173 printf("%s: could not create spare Rx dmamap.\n", 1174 sc->sc_dev.dv_xname); 1175 return error; 1176 } 1177 1178 for (i = 0; i < ALC_RX_RING_CNT; i++) { 1179 rxd = &sc->alc_cdata.alc_rxdesc[i]; 1180 rxd->rx_m = NULL; 1181 rxd->rx_dmamap = NULL; 1182 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1183 MCLBYTES, 0, BUS_DMA_NOWAIT, &rxd->rx_dmamap); 1184 if (error) { 1185 printf("%s: could not create Rx dmamap.\n", 1186 sc->sc_dev.dv_xname); 1187 return error; 1188 } 1189 } 1190 1191 return (0); 1192 } 1193 1194 1195 void 1196 alc_dma_free(struct alc_softc *sc) 1197 { 1198 struct alc_txdesc *txd; 1199 struct alc_rxdesc *rxd; 1200 int i; 1201 1202 /* Tx buffers */ 1203 for (i = 0; i < ALC_TX_RING_CNT; i++) { 1204 txd = &sc->alc_cdata.alc_txdesc[i]; 1205 if (txd->tx_dmamap != NULL) { 1206 bus_dmamap_destroy(sc->sc_dmat, txd->tx_dmamap); 1207 txd->tx_dmamap = NULL; 1208 } 1209 } 1210 /* Rx buffers */ 1211 for (i = 0; i < ALC_RX_RING_CNT; i++) { 1212 rxd = &sc->alc_cdata.alc_rxdesc[i]; 1213 if (rxd->rx_dmamap != NULL) { 1214 bus_dmamap_destroy(sc->sc_dmat, rxd->rx_dmamap); 1215 rxd->rx_dmamap = NULL; 1216 } 1217 } 1218 if (sc->alc_cdata.alc_rx_sparemap != NULL) { 1219 bus_dmamap_destroy(sc->sc_dmat, sc->alc_cdata.alc_rx_sparemap); 1220 sc->alc_cdata.alc_rx_sparemap = NULL; 1221 } 1222 1223 /* Tx ring. */ 1224 if (sc->alc_cdata.alc_tx_ring_map != NULL) 1225 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map); 1226 if (sc->alc_cdata.alc_tx_ring_map != NULL && 1227 sc->alc_rdata.alc_tx_ring != NULL) 1228 bus_dmamem_free(sc->sc_dmat, 1229 (bus_dma_segment_t *)sc->alc_rdata.alc_tx_ring, 1); 1230 sc->alc_rdata.alc_tx_ring = NULL; 1231 sc->alc_cdata.alc_tx_ring_map = NULL; 1232 1233 /* Rx ring. */ 1234 if (sc->alc_cdata.alc_rx_ring_map != NULL) 1235 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map); 1236 if (sc->alc_cdata.alc_rx_ring_map != NULL && 1237 sc->alc_rdata.alc_rx_ring != NULL) 1238 bus_dmamem_free(sc->sc_dmat, 1239 (bus_dma_segment_t *)sc->alc_rdata.alc_rx_ring, 1); 1240 sc->alc_rdata.alc_rx_ring = NULL; 1241 sc->alc_cdata.alc_rx_ring_map = NULL; 1242 1243 /* Rx return ring. */ 1244 if (sc->alc_cdata.alc_rr_ring_map != NULL) 1245 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map); 1246 if (sc->alc_cdata.alc_rr_ring_map != NULL && 1247 sc->alc_rdata.alc_rr_ring != NULL) 1248 bus_dmamem_free(sc->sc_dmat, 1249 (bus_dma_segment_t *)sc->alc_rdata.alc_rr_ring, 1); 1250 sc->alc_rdata.alc_rr_ring = NULL; 1251 sc->alc_cdata.alc_rr_ring_map = NULL; 1252 1253 /* CMB block */ 1254 if (sc->alc_cdata.alc_cmb_map != NULL) 1255 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_cmb_map); 1256 if (sc->alc_cdata.alc_cmb_map != NULL && 1257 sc->alc_rdata.alc_cmb != NULL) 1258 bus_dmamem_free(sc->sc_dmat, 1259 (bus_dma_segment_t *)sc->alc_rdata.alc_cmb, 1); 1260 sc->alc_rdata.alc_cmb = NULL; 1261 sc->alc_cdata.alc_cmb_map = NULL; 1262 1263 /* SMB block */ 1264 if (sc->alc_cdata.alc_smb_map != NULL) 1265 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_smb_map); 1266 if (sc->alc_cdata.alc_smb_map != NULL && 1267 sc->alc_rdata.alc_smb != NULL) 1268 bus_dmamem_free(sc->sc_dmat, 1269 (bus_dma_segment_t *)sc->alc_rdata.alc_smb, 1); 1270 sc->alc_rdata.alc_smb = NULL; 1271 sc->alc_cdata.alc_smb_map = NULL; 1272 } 1273 1274 int 1275 alc_encap(struct alc_softc *sc, struct mbuf **m_head) 1276 { 1277 struct alc_txdesc *txd, *txd_last; 1278 struct tx_desc *desc; 1279 struct mbuf *m; 1280 bus_dmamap_t map; 1281 uint32_t cflags, poff, vtag; 1282 int error, idx, prod; 1283 1284 m = *m_head; 1285 cflags = vtag = 0; 1286 poff = 0; 1287 1288 prod = sc->alc_cdata.alc_tx_prod; 1289 txd = &sc->alc_cdata.alc_txdesc[prod]; 1290 txd_last = txd; 1291 map = txd->tx_dmamap; 1292 1293 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, BUS_DMA_NOWAIT); 1294 if (error != 0 && error != EFBIG) 1295 goto drop; 1296 if (error != 0) { 1297 if (m_defrag(*m_head, M_DONTWAIT)) { 1298 error = ENOBUFS; 1299 goto drop; 1300 } 1301 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, 1302 BUS_DMA_NOWAIT); 1303 if (error != 0) 1304 goto drop; 1305 } 1306 1307 /* Check descriptor overrun. */ 1308 if (sc->alc_cdata.alc_tx_cnt + map->dm_nsegs >= ALC_TX_RING_CNT - 3) { 1309 bus_dmamap_unload(sc->sc_dmat, map); 1310 return (ENOBUFS); 1311 } 1312 1313 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1314 BUS_DMASYNC_PREWRITE); 1315 1316 m = *m_head; 1317 desc = NULL; 1318 idx = 0; 1319 #if NVLAN > 0 1320 /* Configure VLAN hardware tag insertion. */ 1321 if (m->m_flags & M_VLANTAG) { 1322 vtag = htons(m->m_pkthdr.ether_vtag); 1323 vtag = (vtag << TD_VLAN_SHIFT) & TD_VLAN_MASK; 1324 cflags |= TD_INS_VLAN_TAG; 1325 } 1326 #endif 1327 /* Configure Tx checksum offload. */ 1328 if ((m->m_pkthdr.csum_flags & ALC_CSUM_FEATURES) != 0) { 1329 cflags |= TD_CUSTOM_CSUM; 1330 /* Set checksum start offset. */ 1331 cflags |= ((poff >> 1) << TD_PLOAD_OFFSET_SHIFT) & 1332 TD_PLOAD_OFFSET_MASK; 1333 } 1334 1335 for (; idx < map->dm_nsegs; idx++) { 1336 desc = &sc->alc_rdata.alc_tx_ring[prod]; 1337 desc->len = 1338 htole32(TX_BYTES(map->dm_segs[idx].ds_len) | vtag); 1339 desc->flags = htole32(cflags); 1340 desc->addr = htole64(map->dm_segs[idx].ds_addr); 1341 sc->alc_cdata.alc_tx_cnt++; 1342 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 1343 } 1344 1345 /* Update producer index. */ 1346 sc->alc_cdata.alc_tx_prod = prod; 1347 1348 /* Finally set EOP on the last descriptor. */ 1349 prod = (prod + ALC_TX_RING_CNT - 1) % ALC_TX_RING_CNT; 1350 desc = &sc->alc_rdata.alc_tx_ring[prod]; 1351 desc->flags |= htole32(TD_EOP); 1352 1353 /* Swap dmamap of the first and the last. */ 1354 txd = &sc->alc_cdata.alc_txdesc[prod]; 1355 map = txd_last->tx_dmamap; 1356 txd_last->tx_dmamap = txd->tx_dmamap; 1357 txd->tx_dmamap = map; 1358 txd->tx_m = m; 1359 1360 return (0); 1361 1362 drop: 1363 m_freem(*m_head); 1364 *m_head = NULL; 1365 return (error); 1366 } 1367 1368 void 1369 alc_start(struct ifnet *ifp) 1370 { 1371 struct alc_softc *sc = ifp->if_softc; 1372 struct mbuf *m_head; 1373 int enq = 0; 1374 1375 /* Reclaim transmitted frames. */ 1376 if (sc->alc_cdata.alc_tx_cnt >= ALC_TX_DESC_HIWAT) 1377 alc_txeof(sc); 1378 1379 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1380 return; 1381 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) 1382 return; 1383 if (IFQ_IS_EMPTY(&ifp->if_snd)) 1384 return; 1385 1386 for (;;) { 1387 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1388 if (m_head == NULL) 1389 break; 1390 1391 /* 1392 * Pack the data into the transmit ring. If we 1393 * don't have room, set the OACTIVE flag and wait 1394 * for the NIC to drain the ring. 1395 */ 1396 if (alc_encap(sc, &m_head)) { 1397 if (m_head == NULL) 1398 ifp->if_oerrors++; 1399 else { 1400 IF_PREPEND(&ifp->if_snd, m_head); 1401 ifp->if_flags |= IFF_OACTIVE; 1402 } 1403 break; 1404 } 1405 enq++; 1406 1407 #if NBPFILTER > 0 1408 /* 1409 * If there's a BPF listener, bounce a copy of this frame 1410 * to him. 1411 */ 1412 if (ifp->if_bpf != NULL) 1413 bpf_mtap_ether(ifp->if_bpf, m_head, BPF_DIRECTION_OUT); 1414 #endif 1415 } 1416 1417 if (enq > 0) { 1418 /* Sync descriptors. */ 1419 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0, 1420 sc->alc_cdata.alc_tx_ring_map->dm_mapsize, 1421 BUS_DMASYNC_PREWRITE); 1422 /* Kick. Assume we're using normal Tx priority queue. */ 1423 CSR_WRITE_4(sc, ALC_MBOX_TD_PROD_IDX, 1424 (sc->alc_cdata.alc_tx_prod << 1425 MBOX_TD_PROD_LO_IDX_SHIFT) & 1426 MBOX_TD_PROD_LO_IDX_MASK); 1427 /* Set a timeout in case the chip goes out to lunch. */ 1428 ifp->if_timer = ALC_TX_TIMEOUT; 1429 } 1430 } 1431 1432 void 1433 alc_watchdog(struct ifnet *ifp) 1434 { 1435 struct alc_softc *sc = ifp->if_softc; 1436 1437 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) { 1438 printf("%s: watchdog timeout (missed link)\n", 1439 sc->sc_dev.dv_xname); 1440 ifp->if_oerrors++; 1441 alc_init(ifp); 1442 return; 1443 } 1444 1445 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 1446 ifp->if_oerrors++; 1447 alc_init(ifp); 1448 alc_start(ifp); 1449 } 1450 1451 int 1452 alc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1453 { 1454 struct alc_softc *sc = ifp->if_softc; 1455 struct mii_data *mii = &sc->sc_miibus; 1456 struct ifaddr *ifa = (struct ifaddr *)data; 1457 struct ifreq *ifr = (struct ifreq *)data; 1458 int s, error = 0; 1459 1460 s = splnet(); 1461 1462 switch (cmd) { 1463 case SIOCSIFADDR: 1464 ifp->if_flags |= IFF_UP; 1465 if (!(ifp->if_flags & IFF_RUNNING)) 1466 alc_init(ifp); 1467 #ifdef INET 1468 if (ifa->ifa_addr->sa_family == AF_INET) 1469 arp_ifinit(&sc->sc_arpcom, ifa); 1470 #endif 1471 break; 1472 1473 case SIOCSIFFLAGS: 1474 if (ifp->if_flags & IFF_UP) { 1475 if (ifp->if_flags & IFF_RUNNING) 1476 error = ENETRESET; 1477 else 1478 alc_init(ifp); 1479 } else { 1480 if (ifp->if_flags & IFF_RUNNING) 1481 alc_stop(sc); 1482 } 1483 break; 1484 1485 case SIOCSIFMEDIA: 1486 case SIOCGIFMEDIA: 1487 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1488 break; 1489 1490 default: 1491 error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data); 1492 break; 1493 } 1494 1495 if (error == ENETRESET) { 1496 if (ifp->if_flags & IFF_RUNNING) 1497 alc_iff(sc); 1498 error = 0; 1499 } 1500 1501 splx(s); 1502 return (error); 1503 } 1504 1505 void 1506 alc_mac_config(struct alc_softc *sc) 1507 { 1508 struct mii_data *mii; 1509 uint32_t reg; 1510 1511 mii = &sc->sc_miibus; 1512 reg = CSR_READ_4(sc, ALC_MAC_CFG); 1513 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 1514 MAC_CFG_SPEED_MASK); 1515 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D || 1516 sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D_1 || 1517 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_2) 1518 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 1519 /* Reprogram MAC with resolved speed/duplex. */ 1520 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1521 case IFM_10_T: 1522 case IFM_100_TX: 1523 reg |= MAC_CFG_SPEED_10_100; 1524 break; 1525 case IFM_1000_T: 1526 reg |= MAC_CFG_SPEED_1000; 1527 break; 1528 } 1529 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1530 reg |= MAC_CFG_FULL_DUPLEX; 1531 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1532 reg |= MAC_CFG_TX_FC; 1533 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1534 reg |= MAC_CFG_RX_FC; 1535 } 1536 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 1537 } 1538 1539 void 1540 alc_stats_clear(struct alc_softc *sc) 1541 { 1542 struct smb sb, *smb; 1543 uint32_t *reg; 1544 int i; 1545 1546 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 1547 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 1548 sc->alc_cdata.alc_smb_map->dm_mapsize, 1549 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1550 smb = sc->alc_rdata.alc_smb; 1551 /* Update done, clear. */ 1552 smb->updated = 0; 1553 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 1554 sc->alc_cdata.alc_smb_map->dm_mapsize, 1555 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1556 } else { 1557 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 1558 reg++) { 1559 CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 1560 i += sizeof(uint32_t); 1561 } 1562 /* Read Tx statistics. */ 1563 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 1564 reg++) { 1565 CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 1566 i += sizeof(uint32_t); 1567 } 1568 } 1569 } 1570 1571 void 1572 alc_stats_update(struct alc_softc *sc) 1573 { 1574 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1575 struct alc_hw_stats *stat; 1576 struct smb sb, *smb; 1577 uint32_t *reg; 1578 int i; 1579 1580 stat = &sc->alc_stats; 1581 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 1582 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 1583 sc->alc_cdata.alc_smb_map->dm_mapsize, 1584 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1585 smb = sc->alc_rdata.alc_smb; 1586 if (smb->updated == 0) 1587 return; 1588 } else { 1589 smb = &sb; 1590 /* Read Rx statistics. */ 1591 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 1592 reg++) { 1593 *reg = CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 1594 i += sizeof(uint32_t); 1595 } 1596 /* Read Tx statistics. */ 1597 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 1598 reg++) { 1599 *reg = CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 1600 i += sizeof(uint32_t); 1601 } 1602 } 1603 1604 /* Rx stats. */ 1605 stat->rx_frames += smb->rx_frames; 1606 stat->rx_bcast_frames += smb->rx_bcast_frames; 1607 stat->rx_mcast_frames += smb->rx_mcast_frames; 1608 stat->rx_pause_frames += smb->rx_pause_frames; 1609 stat->rx_control_frames += smb->rx_control_frames; 1610 stat->rx_crcerrs += smb->rx_crcerrs; 1611 stat->rx_lenerrs += smb->rx_lenerrs; 1612 stat->rx_bytes += smb->rx_bytes; 1613 stat->rx_runts += smb->rx_runts; 1614 stat->rx_fragments += smb->rx_fragments; 1615 stat->rx_pkts_64 += smb->rx_pkts_64; 1616 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 1617 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 1618 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 1619 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 1620 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 1621 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 1622 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 1623 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 1624 stat->rx_rrs_errs += smb->rx_rrs_errs; 1625 stat->rx_alignerrs += smb->rx_alignerrs; 1626 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 1627 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 1628 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 1629 1630 /* Tx stats. */ 1631 stat->tx_frames += smb->tx_frames; 1632 stat->tx_bcast_frames += smb->tx_bcast_frames; 1633 stat->tx_mcast_frames += smb->tx_mcast_frames; 1634 stat->tx_pause_frames += smb->tx_pause_frames; 1635 stat->tx_excess_defer += smb->tx_excess_defer; 1636 stat->tx_control_frames += smb->tx_control_frames; 1637 stat->tx_deferred += smb->tx_deferred; 1638 stat->tx_bytes += smb->tx_bytes; 1639 stat->tx_pkts_64 += smb->tx_pkts_64; 1640 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 1641 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 1642 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 1643 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 1644 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 1645 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 1646 stat->tx_single_colls += smb->tx_single_colls; 1647 stat->tx_multi_colls += smb->tx_multi_colls; 1648 stat->tx_late_colls += smb->tx_late_colls; 1649 stat->tx_excess_colls += smb->tx_excess_colls; 1650 stat->tx_abort += smb->tx_abort; 1651 stat->tx_underrun += smb->tx_underrun; 1652 stat->tx_desc_underrun += smb->tx_desc_underrun; 1653 stat->tx_lenerrs += smb->tx_lenerrs; 1654 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 1655 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 1656 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 1657 1658 /* Update counters in ifnet. */ 1659 ifp->if_opackets += smb->tx_frames; 1660 1661 ifp->if_collisions += smb->tx_single_colls + 1662 smb->tx_multi_colls * 2 + smb->tx_late_colls + 1663 smb->tx_abort * HDPX_CFG_RETRY_DEFAULT; 1664 1665 /* 1666 * XXX 1667 * tx_pkts_truncated counter looks suspicious. It constantly 1668 * increments with no sign of Tx errors. This may indicate 1669 * the counter name is not correct one so I've removed the 1670 * counter in output errors. 1671 */ 1672 ifp->if_oerrors += smb->tx_abort + smb->tx_late_colls + 1673 smb->tx_underrun; 1674 1675 ifp->if_ipackets += smb->rx_frames; 1676 1677 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 1678 smb->rx_runts + smb->rx_pkts_truncated + 1679 smb->rx_fifo_oflows + smb->rx_rrs_errs + 1680 smb->rx_alignerrs; 1681 1682 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 1683 /* Update done, clear. */ 1684 smb->updated = 0; 1685 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 1686 sc->alc_cdata.alc_smb_map->dm_mapsize, 1687 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1688 } 1689 } 1690 1691 int 1692 alc_intr(void *arg) 1693 { 1694 struct alc_softc *sc = arg; 1695 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1696 uint32_t status; 1697 int claimed = 0; 1698 1699 status = CSR_READ_4(sc, ALC_INTR_STATUS); 1700 if ((status & ALC_INTRS) == 0) 1701 return (0); 1702 1703 /* Disable interrupts. */ 1704 CSR_WRITE_4(sc, ALC_INTR_STATUS, INTR_DIS_INT); 1705 1706 status = CSR_READ_4(sc, ALC_INTR_STATUS); 1707 if ((status & ALC_INTRS) == 0) 1708 goto back; 1709 1710 /* Acknowledge and disable interrupts. */ 1711 CSR_WRITE_4(sc, ALC_INTR_STATUS, status | INTR_DIS_INT); 1712 1713 if (ifp->if_flags & IFF_RUNNING) { 1714 if (status & INTR_RX_PKT) 1715 alc_rxintr(sc); 1716 1717 if (status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | 1718 INTR_TXQ_TO_RST)) { 1719 if (status & INTR_DMA_RD_TO_RST) 1720 printf("%s: DMA read error! -- resetting\n", 1721 sc->sc_dev.dv_xname); 1722 if (status & INTR_DMA_WR_TO_RST) 1723 printf("%s: DMA write error! -- resetting\n", 1724 sc->sc_dev.dv_xname); 1725 if (status & INTR_TXQ_TO_RST) 1726 printf("%s: TxQ reset! -- resetting\n", 1727 sc->sc_dev.dv_xname); 1728 alc_init(ifp); 1729 return (0); 1730 } 1731 1732 if (status & INTR_TX_PKT) 1733 alc_txeof(sc); 1734 1735 alc_start(ifp); 1736 } 1737 1738 claimed = 1; 1739 back: 1740 /* Re-enable interrupts. */ 1741 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0x7FFFFFFF); 1742 return (claimed); 1743 } 1744 1745 void 1746 alc_txeof(struct alc_softc *sc) 1747 { 1748 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1749 struct alc_txdesc *txd; 1750 uint32_t cons, prod; 1751 int prog; 1752 1753 if (sc->alc_cdata.alc_tx_cnt == 0) 1754 return; 1755 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0, 1756 sc->alc_cdata.alc_tx_ring_map->dm_mapsize, 1757 BUS_DMASYNC_POSTWRITE); 1758 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 1759 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0, 1760 sc->alc_cdata.alc_cmb_map->dm_mapsize, 1761 BUS_DMASYNC_POSTREAD); 1762 prod = sc->alc_rdata.alc_cmb->cons; 1763 } else 1764 prod = CSR_READ_4(sc, ALC_MBOX_TD_CONS_IDX); 1765 /* Assume we're using normal Tx priority queue. */ 1766 prod = (prod & MBOX_TD_CONS_LO_IDX_MASK) >> 1767 MBOX_TD_CONS_LO_IDX_SHIFT; 1768 cons = sc->alc_cdata.alc_tx_cons; 1769 /* 1770 * Go through our Tx list and free mbufs for those 1771 * frames which have been transmitted. 1772 */ 1773 for (prog = 0; cons != prod; prog++, 1774 ALC_DESC_INC(cons, ALC_TX_RING_CNT)) { 1775 if (sc->alc_cdata.alc_tx_cnt <= 0) 1776 break; 1777 prog++; 1778 ifp->if_flags &= ~IFF_OACTIVE; 1779 sc->alc_cdata.alc_tx_cnt--; 1780 txd = &sc->alc_cdata.alc_txdesc[cons]; 1781 if (txd->tx_m != NULL) { 1782 /* Reclaim transmitted mbufs. */ 1783 bus_dmamap_sync(sc->sc_dmat, txd->tx_dmamap, 0, 1784 txd->tx_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1785 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1786 m_freem(txd->tx_m); 1787 txd->tx_m = NULL; 1788 } 1789 } 1790 1791 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 1792 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0, 1793 sc->alc_cdata.alc_cmb_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1794 sc->alc_cdata.alc_tx_cons = cons; 1795 /* 1796 * Unarm watchdog timer only when there is no pending 1797 * frames in Tx queue. 1798 */ 1799 if (sc->alc_cdata.alc_tx_cnt == 0) 1800 ifp->if_timer = 0; 1801 } 1802 1803 int 1804 alc_newbuf(struct alc_softc *sc, struct alc_rxdesc *rxd) 1805 { 1806 struct mbuf *m; 1807 bus_dmamap_t map; 1808 int error; 1809 1810 MGETHDR(m, M_DONTWAIT, MT_DATA); 1811 if (m == NULL) 1812 return (ENOBUFS); 1813 MCLGET(m, M_DONTWAIT); 1814 if (!(m->m_flags & M_EXT)) { 1815 m_freem(m); 1816 return (ENOBUFS); 1817 } 1818 1819 m->m_len = m->m_pkthdr.len = RX_BUF_SIZE_MAX; 1820 1821 error = bus_dmamap_load_mbuf(sc->sc_dmat, 1822 sc->alc_cdata.alc_rx_sparemap, m, BUS_DMA_NOWAIT); 1823 1824 if (error != 0) { 1825 m_freem(m); 1826 printf("%s: can't load RX mbuf\n", sc->sc_dev.dv_xname); 1827 return (error); 1828 } 1829 1830 if (rxd->rx_m != NULL) { 1831 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0, 1832 rxd->rx_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1833 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 1834 } 1835 map = rxd->rx_dmamap; 1836 rxd->rx_dmamap = sc->alc_cdata.alc_rx_sparemap; 1837 sc->alc_cdata.alc_rx_sparemap = map; 1838 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0, rxd->rx_dmamap->dm_mapsize, 1839 BUS_DMASYNC_PREREAD); 1840 rxd->rx_m = m; 1841 rxd->rx_desc->addr = htole64(rxd->rx_dmamap->dm_segs[0].ds_addr); 1842 return (0); 1843 } 1844 1845 void 1846 alc_rxintr(struct alc_softc *sc) 1847 { 1848 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1849 struct rx_rdesc *rrd; 1850 uint32_t nsegs, status; 1851 int rr_cons, prog; 1852 1853 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 0, 1854 sc->alc_cdata.alc_rr_ring_map->dm_mapsize, 1855 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1856 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 0, 1857 sc->alc_cdata.alc_rx_ring_map->dm_mapsize, 1858 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1859 rr_cons = sc->alc_cdata.alc_rr_cons; 1860 for (prog = 0; (ifp->if_flags & IFF_RUNNING) != 0;) { 1861 rrd = &sc->alc_rdata.alc_rr_ring[rr_cons]; 1862 status = letoh32(rrd->status); 1863 if ((status & RRD_VALID) == 0) 1864 break; 1865 nsegs = RRD_RD_CNT(letoh32(rrd->rdinfo)); 1866 if (nsegs == 0) { 1867 /* This should not happen! */ 1868 if (alcdebug) 1869 printf("%s: unexpected segment count -- " 1870 "resetting\n", sc->sc_dev.dv_xname); 1871 break; 1872 } 1873 alc_rxeof(sc, rrd); 1874 /* Clear Rx return status. */ 1875 rrd->status = 0; 1876 ALC_DESC_INC(rr_cons, ALC_RR_RING_CNT); 1877 sc->alc_cdata.alc_rx_cons += nsegs; 1878 sc->alc_cdata.alc_rx_cons %= ALC_RR_RING_CNT; 1879 prog += nsegs; 1880 } 1881 1882 if (prog > 0) { 1883 /* Update the consumer index. */ 1884 sc->alc_cdata.alc_rr_cons = rr_cons; 1885 /* Sync Rx return descriptors. */ 1886 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 0, 1887 sc->alc_cdata.alc_rr_ring_map->dm_mapsize, 1888 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1889 /* 1890 * Sync updated Rx descriptors such that controller see 1891 * modified buffer addresses. 1892 */ 1893 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 0, 1894 sc->alc_cdata.alc_rx_ring_map->dm_mapsize, 1895 BUS_DMASYNC_PREWRITE); 1896 /* 1897 * Let controller know availability of new Rx buffers. 1898 * Since alc(4) use RXQ_CFG_RD_BURST_DEFAULT descriptors 1899 * it may be possible to update ALC_MBOX_RD0_PROD_IDX 1900 * only when Rx buffer pre-fetching is required. In 1901 * addition we already set ALC_RX_RD_FREE_THRESH to 1902 * RX_RD_FREE_THRESH_LO_DEFAULT descriptors. However 1903 * it still seems that pre-fetching needs more 1904 * experimentation. 1905 */ 1906 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 1907 sc->alc_cdata.alc_rx_cons); 1908 } 1909 } 1910 1911 /* Receive a frame. */ 1912 void 1913 alc_rxeof(struct alc_softc *sc, struct rx_rdesc *rrd) 1914 { 1915 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1916 struct alc_rxdesc *rxd; 1917 struct mbuf *mp, *m; 1918 uint32_t rdinfo, status; 1919 int count, nsegs, rx_cons; 1920 1921 status = letoh32(rrd->status); 1922 rdinfo = letoh32(rrd->rdinfo); 1923 rx_cons = RRD_RD_IDX(rdinfo); 1924 nsegs = RRD_RD_CNT(rdinfo); 1925 1926 sc->alc_cdata.alc_rxlen = RRD_BYTES(status); 1927 if (status & (RRD_ERR_SUM | RRD_ERR_LENGTH)) { 1928 /* 1929 * We want to pass the following frames to upper 1930 * layer regardless of error status of Rx return 1931 * ring. 1932 * 1933 * o IP/TCP/UDP checksum is bad. 1934 * o frame length and protocol specific length 1935 * does not match. 1936 * 1937 * Force network stack compute checksum for 1938 * errored frames. 1939 */ 1940 if ((status & (RRD_ERR_CRC | RRD_ERR_ALIGN | 1941 RRD_ERR_TRUNC | RRD_ERR_RUNT)) != 0) 1942 return; 1943 } 1944 1945 for (count = 0; count < nsegs; count++, 1946 ALC_DESC_INC(rx_cons, ALC_RX_RING_CNT)) { 1947 rxd = &sc->alc_cdata.alc_rxdesc[rx_cons]; 1948 mp = rxd->rx_m; 1949 /* Add a new receive buffer to the ring. */ 1950 if (alc_newbuf(sc, rxd) != 0) { 1951 ifp->if_iqdrops++; 1952 /* Reuse Rx buffers. */ 1953 if (sc->alc_cdata.alc_rxhead != NULL) 1954 m_freem(sc->alc_cdata.alc_rxhead); 1955 break; 1956 } 1957 1958 /* 1959 * Assume we've received a full sized frame. 1960 * Actual size is fixed when we encounter the end of 1961 * multi-segmented frame. 1962 */ 1963 mp->m_len = sc->alc_buf_size; 1964 1965 /* Chain received mbufs. */ 1966 if (sc->alc_cdata.alc_rxhead == NULL) { 1967 sc->alc_cdata.alc_rxhead = mp; 1968 sc->alc_cdata.alc_rxtail = mp; 1969 } else { 1970 mp->m_flags &= ~M_PKTHDR; 1971 sc->alc_cdata.alc_rxprev_tail = 1972 sc->alc_cdata.alc_rxtail; 1973 sc->alc_cdata.alc_rxtail->m_next = mp; 1974 sc->alc_cdata.alc_rxtail = mp; 1975 } 1976 1977 if (count == nsegs - 1) { 1978 /* Last desc. for this frame. */ 1979 m = sc->alc_cdata.alc_rxhead; 1980 m->m_flags |= M_PKTHDR; 1981 /* 1982 * It seems that L1C/L2C controller has no way 1983 * to tell hardware to strip CRC bytes. 1984 */ 1985 m->m_pkthdr.len = 1986 sc->alc_cdata.alc_rxlen - ETHER_CRC_LEN; 1987 if (nsegs > 1) { 1988 /* Set last mbuf size. */ 1989 mp->m_len = sc->alc_cdata.alc_rxlen - 1990 (nsegs - 1) * sc->alc_buf_size; 1991 /* Remove the CRC bytes in chained mbufs. */ 1992 if (mp->m_len <= ETHER_CRC_LEN) { 1993 sc->alc_cdata.alc_rxtail = 1994 sc->alc_cdata.alc_rxprev_tail; 1995 sc->alc_cdata.alc_rxtail->m_len -= 1996 (ETHER_CRC_LEN - mp->m_len); 1997 sc->alc_cdata.alc_rxtail->m_next = NULL; 1998 m_freem(mp); 1999 } else { 2000 mp->m_len -= ETHER_CRC_LEN; 2001 } 2002 } else 2003 m->m_len = m->m_pkthdr.len; 2004 m->m_pkthdr.rcvif = ifp; 2005 /* 2006 * Due to hardware bugs, Rx checksum offloading 2007 * was intentionally disabled. 2008 */ 2009 #if NVLAN > 0 2010 if (status & RRD_VLAN_TAG) { 2011 u_int32_t vtag = RRD_VLAN(letoh32(rrd->vtag)); 2012 m->m_pkthdr.ether_vtag = ntohs(vtag); 2013 m->m_flags |= M_VLANTAG; 2014 } 2015 #endif 2016 2017 #if NBPFILTER > 0 2018 if (ifp->if_bpf) 2019 bpf_mtap_ether(ifp->if_bpf, m, 2020 BPF_DIRECTION_IN); 2021 #endif 2022 2023 { 2024 /* Pass it on. */ 2025 ether_input_mbuf(ifp, m); 2026 } 2027 } 2028 } 2029 /* Reset mbuf chains. */ 2030 ALC_RXCHAIN_RESET(sc); 2031 } 2032 2033 void 2034 alc_tick(void *xsc) 2035 { 2036 struct alc_softc *sc = xsc; 2037 struct mii_data *mii = &sc->sc_miibus; 2038 int s; 2039 2040 s = splnet(); 2041 mii_tick(mii); 2042 alc_stats_update(sc); 2043 2044 timeout_add_sec(&sc->alc_tick_ch, 1); 2045 splx(s); 2046 } 2047 2048 void 2049 alc_reset(struct alc_softc *sc) 2050 { 2051 uint32_t reg; 2052 int i; 2053 2054 reg = CSR_READ_4(sc, ALC_MASTER_CFG) & 0xFFFF; 2055 reg |= MASTER_OOB_DIS_OFF | MASTER_RESET; 2056 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 2057 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 2058 DELAY(10); 2059 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0) 2060 break; 2061 } 2062 if (i == 0) 2063 printf("%s: master reset timeout!\n", sc->sc_dev.dv_xname); 2064 2065 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 2066 if ((reg = CSR_READ_4(sc, ALC_IDLE_STATUS)) == 0) 2067 break; 2068 DELAY(10); 2069 } 2070 2071 if (i == 0) 2072 printf("%s: reset timeout(0x%08x)!\n", sc->sc_dev.dv_xname, 2073 reg); 2074 } 2075 2076 int 2077 alc_init(struct ifnet *ifp) 2078 { 2079 struct alc_softc *sc = ifp->if_softc; 2080 struct mii_data *mii; 2081 uint8_t eaddr[ETHER_ADDR_LEN]; 2082 bus_addr_t paddr; 2083 uint32_t reg, rxf_hi, rxf_lo; 2084 int error; 2085 2086 /* 2087 * Cancel any pending I/O. 2088 */ 2089 alc_stop(sc); 2090 /* 2091 * Reset the chip to a known state. 2092 */ 2093 alc_reset(sc); 2094 2095 /* Initialize Rx descriptors. */ 2096 error = alc_init_rx_ring(sc); 2097 if (error != 0) { 2098 printf("%s: no memory for Rx buffers.\n", sc->sc_dev.dv_xname); 2099 alc_stop(sc); 2100 return (error); 2101 } 2102 alc_init_rr_ring(sc); 2103 alc_init_tx_ring(sc); 2104 alc_init_cmb(sc); 2105 alc_init_smb(sc); 2106 2107 /* Enable all clocks. */ 2108 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, 0); 2109 2110 /* Reprogram the station address. */ 2111 bcopy(LLADDR(ifp->if_sadl), eaddr, ETHER_ADDR_LEN); 2112 CSR_WRITE_4(sc, ALC_PAR0, 2113 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 2114 CSR_WRITE_4(sc, ALC_PAR1, eaddr[0] << 8 | eaddr[1]); 2115 /* 2116 * Clear WOL status and disable all WOL feature as WOL 2117 * would interfere Rx operation under normal environments. 2118 */ 2119 CSR_READ_4(sc, ALC_WOL_CFG); 2120 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 2121 /* Set Tx descriptor base addresses. */ 2122 paddr = sc->alc_rdata.alc_tx_ring_paddr; 2123 CSR_WRITE_4(sc, ALC_TX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 2124 CSR_WRITE_4(sc, ALC_TDL_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 2125 /* We don't use high priority ring. */ 2126 CSR_WRITE_4(sc, ALC_TDH_HEAD_ADDR_LO, 0); 2127 /* Set Tx descriptor counter. */ 2128 CSR_WRITE_4(sc, ALC_TD_RING_CNT, 2129 (ALC_TX_RING_CNT << TD_RING_CNT_SHIFT) & TD_RING_CNT_MASK); 2130 /* Set Rx descriptor base addresses. */ 2131 paddr = sc->alc_rdata.alc_rx_ring_paddr; 2132 CSR_WRITE_4(sc, ALC_RX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 2133 CSR_WRITE_4(sc, ALC_RD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 2134 /* We use one Rx ring. */ 2135 CSR_WRITE_4(sc, ALC_RD1_HEAD_ADDR_LO, 0); 2136 CSR_WRITE_4(sc, ALC_RD2_HEAD_ADDR_LO, 0); 2137 CSR_WRITE_4(sc, ALC_RD3_HEAD_ADDR_LO, 0); 2138 /* Set Rx descriptor counter. */ 2139 CSR_WRITE_4(sc, ALC_RD_RING_CNT, 2140 (ALC_RX_RING_CNT << RD_RING_CNT_SHIFT) & RD_RING_CNT_MASK); 2141 2142 /* 2143 * Let hardware split jumbo frames into alc_max_buf_sized chunks. 2144 * if it do not fit the buffer size. Rx return descriptor holds 2145 * a counter that indicates how many fragments were made by the 2146 * hardware. The buffer size should be multiple of 8 bytes. 2147 * Since hardware has limit on the size of buffer size, always 2148 * use the maximum value. 2149 * For strict-alignment architectures make sure to reduce buffer 2150 * size by 8 bytes to make room for alignment fixup. 2151 */ 2152 sc->alc_buf_size = RX_BUF_SIZE_MAX; 2153 CSR_WRITE_4(sc, ALC_RX_BUF_SIZE, sc->alc_buf_size); 2154 2155 paddr = sc->alc_rdata.alc_rr_ring_paddr; 2156 /* Set Rx return descriptor base addresses. */ 2157 CSR_WRITE_4(sc, ALC_RRD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 2158 /* We use one Rx return ring. */ 2159 CSR_WRITE_4(sc, ALC_RRD1_HEAD_ADDR_LO, 0); 2160 CSR_WRITE_4(sc, ALC_RRD2_HEAD_ADDR_LO, 0); 2161 CSR_WRITE_4(sc, ALC_RRD3_HEAD_ADDR_LO, 0); 2162 /* Set Rx return descriptor counter. */ 2163 CSR_WRITE_4(sc, ALC_RRD_RING_CNT, 2164 (ALC_RR_RING_CNT << RRD_RING_CNT_SHIFT) & RRD_RING_CNT_MASK); 2165 paddr = sc->alc_rdata.alc_cmb_paddr; 2166 CSR_WRITE_4(sc, ALC_CMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 2167 paddr = sc->alc_rdata.alc_smb_paddr; 2168 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 2169 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 2170 2171 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1) { 2172 /* Reconfigure SRAM - Vendor magic. */ 2173 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_LEN, 0x000002A0); 2174 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_LEN, 0x00000100); 2175 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_ADDR, 0x029F0000); 2176 CSR_WRITE_4(sc, ALC_SRAM_RD0_ADDR, 0x02BF02A0); 2177 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_ADDR, 0x03BF02C0); 2178 CSR_WRITE_4(sc, ALC_SRAM_TD_ADDR, 0x03DF03C0); 2179 CSR_WRITE_4(sc, ALC_TXF_WATER_MARK, 0x00000000); 2180 CSR_WRITE_4(sc, ALC_RD_DMA_CFG, 0x00000000); 2181 } 2182 2183 /* Tell hardware that we're ready to load DMA blocks. */ 2184 CSR_WRITE_4(sc, ALC_DMA_BLOCK, DMA_BLOCK_LOAD); 2185 2186 /* Configure interrupt moderation timer. */ 2187 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 2188 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 2189 reg = ALC_USECS(sc->alc_int_rx_mod) << IM_TIMER_RX_SHIFT; 2190 reg |= ALC_USECS(sc->alc_int_tx_mod) << IM_TIMER_TX_SHIFT; 2191 CSR_WRITE_4(sc, ALC_IM_TIMER, reg); 2192 /* 2193 * We don't want to automatic interrupt clear as task queue 2194 * for the interrupt should know interrupt status. 2195 */ 2196 reg = MASTER_SA_TIMER_ENB; 2197 if (ALC_USECS(sc->alc_int_rx_mod) != 0) 2198 reg |= MASTER_IM_RX_TIMER_ENB; 2199 if (ALC_USECS(sc->alc_int_tx_mod) != 0) 2200 reg |= MASTER_IM_TX_TIMER_ENB; 2201 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 2202 /* 2203 * Disable interrupt re-trigger timer. We don't want automatic 2204 * re-triggering of un-ACKed interrupts. 2205 */ 2206 CSR_WRITE_4(sc, ALC_INTR_RETRIG_TIMER, ALC_USECS(0)); 2207 /* Configure CMB. */ 2208 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 2209 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, 4); 2210 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(5000)); 2211 } else 2212 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(0)); 2213 /* 2214 * Hardware can be configured to issue SMB interrupt based 2215 * on programmed interval. Since there is a callout that is 2216 * invoked for every hz in driver we use that instead of 2217 * relying on periodic SMB interrupt. 2218 */ 2219 CSR_WRITE_4(sc, ALC_SMB_STAT_TIMER, ALC_USECS(0)); 2220 /* Clear MAC statistics. */ 2221 alc_stats_clear(sc); 2222 2223 /* 2224 * Always use maximum frame size that controller can support. 2225 * Otherwise received frames that has larger frame length 2226 * than alc(4) MTU would be silently dropped in hardware. This 2227 * would make path-MTU discovery hard as sender wouldn't get 2228 * any responses from receiver. alc(4) supports 2229 * multi-fragmented frames on Rx path so it has no issue on 2230 * assembling fragmented frames. Using maximum frame size also 2231 * removes the need to reinitialize hardware when interface 2232 * MTU configuration was changed. 2233 * 2234 * Be conservative in what you do, be liberal in what you 2235 * accept from others - RFC 793. 2236 */ 2237 CSR_WRITE_4(sc, ALC_FRAME_SIZE, sc->alc_max_framelen); 2238 2239 /* Disable header split(?) */ 2240 CSR_WRITE_4(sc, ALC_HDS_CFG, 0); 2241 2242 /* Configure IPG/IFG parameters. */ 2243 CSR_WRITE_4(sc, ALC_IPG_IFG_CFG, 2244 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) | 2245 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 2246 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 2247 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK)); 2248 /* Set parameters for half-duplex media. */ 2249 CSR_WRITE_4(sc, ALC_HDPX_CFG, 2250 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 2251 HDPX_CFG_LCOL_MASK) | 2252 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 2253 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 2254 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 2255 HDPX_CFG_ABEBT_MASK) | 2256 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 2257 HDPX_CFG_JAMIPG_MASK)); 2258 /* 2259 * Set TSO/checksum offload threshold. For frames that is 2260 * larger than this threshold, hardware wouldn't do 2261 * TSO/checksum offloading. 2262 */ 2263 CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH, 2264 (sc->alc_max_framelen >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) & 2265 TSO_OFFLOAD_THRESH_MASK); 2266 /* Configure TxQ. */ 2267 reg = (alc_dma_burst[sc->alc_dma_rd_burst] << 2268 TXQ_CFG_TX_FIFO_BURST_SHIFT) & TXQ_CFG_TX_FIFO_BURST_MASK; 2269 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1 || 2270 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_2) 2271 reg >>= 1; 2272 reg |= (TXQ_CFG_TD_BURST_DEFAULT << TXQ_CFG_TD_BURST_SHIFT) & 2273 TXQ_CFG_TD_BURST_MASK; 2274 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE); 2275 2276 /* Configure Rx free descriptor pre-fetching. */ 2277 CSR_WRITE_4(sc, ALC_RX_RD_FREE_THRESH, 2278 ((RX_RD_FREE_THRESH_HI_DEFAULT << RX_RD_FREE_THRESH_HI_SHIFT) & 2279 RX_RD_FREE_THRESH_HI_MASK) | 2280 ((RX_RD_FREE_THRESH_LO_DEFAULT << RX_RD_FREE_THRESH_LO_SHIFT) & 2281 RX_RD_FREE_THRESH_LO_MASK)); 2282 2283 /* 2284 * Configure flow control parameters. 2285 * XON : 80% of Rx FIFO 2286 * XOFF : 30% of Rx FIFO 2287 */ 2288 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1C || 2289 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C) { 2290 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 2291 rxf_hi = (reg * 8) / 10; 2292 rxf_lo = (reg * 3) / 10; 2293 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 2294 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 2295 RX_FIFO_PAUSE_THRESH_LO_MASK) | 2296 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 2297 RX_FIFO_PAUSE_THRESH_HI_MASK)); 2298 } 2299 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D_1 || 2300 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1) 2301 CSR_WRITE_4(sc, ALC_SERDES_LOCK, 2302 CSR_READ_4(sc, ALC_SERDES_LOCK) | SERDES_MAC_CLK_SLOWDOWN | 2303 SERDES_PHY_CLK_SLOWDOWN); 2304 2305 /* Disable RSS until I understand L1C/L2C's RSS logic. */ 2306 CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0); 2307 CSR_WRITE_4(sc, ALC_RSS_CPU, 0); 2308 2309 /* Configure RxQ. */ 2310 reg = (RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 2311 RXQ_CFG_RD_BURST_MASK; 2312 reg |= RXQ_CFG_RSS_MODE_DIS; 2313 if ((sc->alc_flags & ALC_FLAG_ASPM_MON) != 0) 2314 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_1M; 2315 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 2316 2317 /* Configure DMA parameters. */ 2318 reg = DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI; 2319 reg |= sc->alc_rcb; 2320 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 2321 reg |= DMA_CFG_CMB_ENB; 2322 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) 2323 reg |= DMA_CFG_SMB_ENB; 2324 else 2325 reg |= DMA_CFG_SMB_DIS; 2326 reg |= (sc->alc_dma_rd_burst & DMA_CFG_RD_BURST_MASK) << 2327 DMA_CFG_RD_BURST_SHIFT; 2328 reg |= (sc->alc_dma_wr_burst & DMA_CFG_WR_BURST_MASK) << 2329 DMA_CFG_WR_BURST_SHIFT; 2330 reg |= (DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 2331 DMA_CFG_RD_DELAY_CNT_MASK; 2332 reg |= (DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 2333 DMA_CFG_WR_DELAY_CNT_MASK; 2334 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 2335 2336 /* 2337 * Configure Tx/Rx MACs. 2338 * - Auto-padding for short frames. 2339 * - Enable CRC generation. 2340 * Actual reconfiguration of MAC for resolved speed/duplex 2341 * is followed after detection of link establishment. 2342 * AR813x/AR815x always does checksum computation regardless 2343 * of MAC_CFG_RXCSUM_ENB bit. Also the controller is known to 2344 * have bug in protocol field in Rx return structure so 2345 * these controllers can't handle fragmented frames. Disable 2346 * Rx checksum offloading until there is a newer controller 2347 * that has sane implementation. 2348 */ 2349 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 2350 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 2351 MAC_CFG_PREAMBLE_MASK); 2352 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D || 2353 sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D_1 || 2354 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_2) 2355 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 2356 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0) 2357 reg |= MAC_CFG_SPEED_10_100; 2358 else 2359 reg |= MAC_CFG_SPEED_1000; 2360 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 2361 2362 /* Set up the receive filter. */ 2363 alc_iff(sc); 2364 2365 alc_rxvlan(sc); 2366 2367 /* Acknowledge all pending interrupts and clear it. */ 2368 CSR_WRITE_4(sc, ALC_INTR_MASK, ALC_INTRS); 2369 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 2370 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0); 2371 2372 sc->alc_flags &= ~ALC_FLAG_LINK; 2373 /* Switch to the current media. */ 2374 mii = &sc->sc_miibus; 2375 mii_mediachg(mii); 2376 2377 timeout_add_sec(&sc->alc_tick_ch, 1); 2378 2379 ifp->if_flags |= IFF_RUNNING; 2380 ifp->if_flags &= ~IFF_OACTIVE; 2381 2382 return (0); 2383 } 2384 2385 void 2386 alc_stop(struct alc_softc *sc) 2387 { 2388 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 2389 struct alc_txdesc *txd; 2390 struct alc_rxdesc *rxd; 2391 uint32_t reg; 2392 int i; 2393 2394 /* 2395 * Mark the interface down and cancel the watchdog timer. 2396 */ 2397 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2398 ifp->if_timer = 0; 2399 2400 timeout_del(&sc->alc_tick_ch); 2401 sc->alc_flags &= ~ALC_FLAG_LINK; 2402 2403 alc_stats_update(sc); 2404 2405 /* Disable interrupts. */ 2406 CSR_WRITE_4(sc, ALC_INTR_MASK, 0); 2407 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 2408 alc_stop_queue(sc); 2409 2410 /* Disable DMA. */ 2411 reg = CSR_READ_4(sc, ALC_DMA_CFG); 2412 reg &= ~(DMA_CFG_CMB_ENB | DMA_CFG_SMB_ENB); 2413 reg |= DMA_CFG_SMB_DIS; 2414 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 2415 DELAY(1000); 2416 2417 /* Stop Rx/Tx MACs. */ 2418 alc_stop_mac(sc); 2419 2420 /* Disable interrupts which might be touched in taskq handler. */ 2421 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 2422 2423 /* Reclaim Rx buffers that have been processed. */ 2424 if (sc->alc_cdata.alc_rxhead != NULL) 2425 m_freem(sc->alc_cdata.alc_rxhead); 2426 ALC_RXCHAIN_RESET(sc); 2427 /* 2428 * Free Tx/Rx mbufs still in the queues. 2429 */ 2430 for (i = 0; i < ALC_RX_RING_CNT; i++) { 2431 rxd = &sc->alc_cdata.alc_rxdesc[i]; 2432 if (rxd->rx_m != NULL) { 2433 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0, 2434 rxd->rx_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2435 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 2436 m_freem(rxd->rx_m); 2437 rxd->rx_m = NULL; 2438 } 2439 } 2440 for (i = 0; i < ALC_TX_RING_CNT; i++) { 2441 txd = &sc->alc_cdata.alc_txdesc[i]; 2442 if (txd->tx_m != NULL) { 2443 bus_dmamap_sync(sc->sc_dmat, txd->tx_dmamap, 0, 2444 txd->tx_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2445 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 2446 m_freem(txd->tx_m); 2447 txd->tx_m = NULL; 2448 } 2449 } 2450 } 2451 2452 void 2453 alc_stop_mac(struct alc_softc *sc) 2454 { 2455 uint32_t reg; 2456 int i; 2457 2458 /* Disable Rx/Tx MAC. */ 2459 reg = CSR_READ_4(sc, ALC_MAC_CFG); 2460 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 2461 reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 2462 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 2463 } 2464 for (i = ALC_TIMEOUT; i > 0; i--) { 2465 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 2466 if (reg == 0) 2467 break; 2468 DELAY(10); 2469 } 2470 if (i == 0) 2471 printf("%s: could not disable Rx/Tx MAC(0x%08x)!\n", 2472 sc->sc_dev.dv_xname, reg); 2473 } 2474 2475 void 2476 alc_start_queue(struct alc_softc *sc) 2477 { 2478 uint32_t qcfg[] = { 2479 0, 2480 RXQ_CFG_QUEUE0_ENB, 2481 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB, 2482 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | RXQ_CFG_QUEUE2_ENB, 2483 RXQ_CFG_ENB 2484 }; 2485 uint32_t cfg; 2486 2487 /* Enable RxQ. */ 2488 cfg = CSR_READ_4(sc, ALC_RXQ_CFG); 2489 cfg &= ~RXQ_CFG_ENB; 2490 cfg |= qcfg[1]; 2491 CSR_WRITE_4(sc, ALC_RXQ_CFG, cfg); 2492 /* Enable TxQ. */ 2493 cfg = CSR_READ_4(sc, ALC_TXQ_CFG); 2494 cfg |= TXQ_CFG_ENB; 2495 CSR_WRITE_4(sc, ALC_TXQ_CFG, cfg); 2496 } 2497 2498 void 2499 alc_stop_queue(struct alc_softc *sc) 2500 { 2501 uint32_t reg; 2502 int i; 2503 2504 /* Disable RxQ. */ 2505 reg = CSR_READ_4(sc, ALC_RXQ_CFG); 2506 if ((reg & RXQ_CFG_ENB) != 0) { 2507 reg &= ~RXQ_CFG_ENB; 2508 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 2509 } 2510 /* Disable TxQ. */ 2511 reg = CSR_READ_4(sc, ALC_TXQ_CFG); 2512 if ((reg & TXQ_CFG_ENB) != 0) { 2513 reg &= ~TXQ_CFG_ENB; 2514 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg); 2515 } 2516 for (i = ALC_TIMEOUT; i > 0; i--) { 2517 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 2518 if ((reg & (IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 2519 break; 2520 DELAY(10); 2521 } 2522 if (i == 0) 2523 printf("%s: could not disable RxQ/TxQ (0x%08x)!\n", 2524 sc->sc_dev.dv_xname, reg); 2525 } 2526 2527 void 2528 alc_init_tx_ring(struct alc_softc *sc) 2529 { 2530 struct alc_ring_data *rd; 2531 struct alc_txdesc *txd; 2532 int i; 2533 2534 sc->alc_cdata.alc_tx_prod = 0; 2535 sc->alc_cdata.alc_tx_cons = 0; 2536 sc->alc_cdata.alc_tx_cnt = 0; 2537 2538 rd = &sc->alc_rdata; 2539 bzero(rd->alc_tx_ring, ALC_TX_RING_SZ); 2540 for (i = 0; i < ALC_TX_RING_CNT; i++) { 2541 txd = &sc->alc_cdata.alc_txdesc[i]; 2542 txd->tx_m = NULL; 2543 } 2544 2545 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0, 2546 sc->alc_cdata.alc_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2547 } 2548 2549 int 2550 alc_init_rx_ring(struct alc_softc *sc) 2551 { 2552 struct alc_ring_data *rd; 2553 struct alc_rxdesc *rxd; 2554 int i; 2555 2556 sc->alc_cdata.alc_rx_cons = ALC_RX_RING_CNT - 1; 2557 rd = &sc->alc_rdata; 2558 bzero(rd->alc_rx_ring, ALC_RX_RING_SZ); 2559 for (i = 0; i < ALC_RX_RING_CNT; i++) { 2560 rxd = &sc->alc_cdata.alc_rxdesc[i]; 2561 rxd->rx_m = NULL; 2562 rxd->rx_desc = &rd->alc_rx_ring[i]; 2563 if (alc_newbuf(sc, rxd) != 0) 2564 return (ENOBUFS); 2565 } 2566 2567 /* 2568 * Since controller does not update Rx descriptors, driver 2569 * does have to read Rx descriptors back so BUS_DMASYNC_PREWRITE 2570 * is enough to ensure coherence. 2571 */ 2572 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 0, 2573 sc->alc_cdata.alc_rx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2574 /* Let controller know availability of new Rx buffers. */ 2575 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, sc->alc_cdata.alc_rx_cons); 2576 2577 return (0); 2578 } 2579 2580 void 2581 alc_init_rr_ring(struct alc_softc *sc) 2582 { 2583 struct alc_ring_data *rd; 2584 2585 sc->alc_cdata.alc_rr_cons = 0; 2586 ALC_RXCHAIN_RESET(sc); 2587 2588 rd = &sc->alc_rdata; 2589 bzero(rd->alc_rr_ring, ALC_RR_RING_SZ); 2590 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 0, 2591 sc->alc_cdata.alc_rr_ring_map->dm_mapsize, 2592 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2593 } 2594 2595 void 2596 alc_init_cmb(struct alc_softc *sc) 2597 { 2598 struct alc_ring_data *rd; 2599 2600 rd = &sc->alc_rdata; 2601 bzero(rd->alc_cmb, ALC_CMB_SZ); 2602 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0, 2603 sc->alc_cdata.alc_cmb_map->dm_mapsize, 2604 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2605 } 2606 2607 void 2608 alc_init_smb(struct alc_softc *sc) 2609 { 2610 struct alc_ring_data *rd; 2611 2612 rd = &sc->alc_rdata; 2613 bzero(rd->alc_smb, ALC_SMB_SZ); 2614 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 2615 sc->alc_cdata.alc_smb_map->dm_mapsize, 2616 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2617 } 2618 2619 void 2620 alc_rxvlan(struct alc_softc *sc) 2621 { 2622 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 2623 uint32_t reg; 2624 2625 reg = CSR_READ_4(sc, ALC_MAC_CFG); 2626 if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) 2627 reg |= MAC_CFG_VLAN_TAG_STRIP; 2628 else 2629 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 2630 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 2631 } 2632 2633 void 2634 alc_iff(struct alc_softc *sc) 2635 { 2636 struct arpcom *ac = &sc->sc_arpcom; 2637 struct ifnet *ifp = &ac->ac_if; 2638 struct ether_multi *enm; 2639 struct ether_multistep step; 2640 uint32_t crc; 2641 uint32_t mchash[2]; 2642 uint32_t rxcfg; 2643 2644 rxcfg = CSR_READ_4(sc, ALC_MAC_CFG); 2645 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 2646 ifp->if_flags &= ~IFF_ALLMULTI; 2647 2648 /* 2649 * Always accept broadcast frames. 2650 */ 2651 rxcfg |= MAC_CFG_BCAST; 2652 2653 if (ifp->if_flags & IFF_PROMISC || ac->ac_multirangecnt > 0) { 2654 ifp->if_flags |= IFF_ALLMULTI; 2655 if (ifp->if_flags & IFF_PROMISC) 2656 rxcfg |= MAC_CFG_PROMISC; 2657 else 2658 rxcfg |= MAC_CFG_ALLMULTI; 2659 mchash[0] = mchash[1] = 0xFFFFFFFF; 2660 } else { 2661 /* Program new filter. */ 2662 bzero(mchash, sizeof(mchash)); 2663 2664 ETHER_FIRST_MULTI(step, ac, enm); 2665 while (enm != NULL) { 2666 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2667 2668 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 2669 2670 ETHER_NEXT_MULTI(step, enm); 2671 } 2672 } 2673 2674 CSR_WRITE_4(sc, ALC_MAR0, mchash[0]); 2675 CSR_WRITE_4(sc, ALC_MAR1, mchash[1]); 2676 CSR_WRITE_4(sc, ALC_MAC_CFG, rxcfg); 2677 } 2678