1 /* $OpenBSD: if_alc.c,v 1.50 2019/06/03 01:52:53 kevlo Exp $ */ 2 /*- 3 * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* Driver for Atheros AR813x/AR815x/AR816x/AR817x PCIe Ethernet. */ 30 31 #include "bpfilter.h" 32 #include "vlan.h" 33 34 #include <sys/param.h> 35 #include <sys/endian.h> 36 #include <sys/systm.h> 37 #include <sys/sockio.h> 38 #include <sys/mbuf.h> 39 #include <sys/queue.h> 40 #include <sys/kernel.h> 41 #include <sys/device.h> 42 #include <sys/timeout.h> 43 #include <sys/socket.h> 44 45 #include <machine/bus.h> 46 47 #include <net/if.h> 48 #include <net/if_dl.h> 49 #include <net/if_media.h> 50 51 #include <netinet/in.h> 52 #include <netinet/if_ether.h> 53 54 #if NBPFILTER > 0 55 #include <net/bpf.h> 56 #endif 57 58 #include <dev/mii/mii.h> 59 #include <dev/mii/miivar.h> 60 61 #include <dev/pci/pcireg.h> 62 #include <dev/pci/pcivar.h> 63 #include <dev/pci/pcidevs.h> 64 65 #include <dev/pci/if_alcreg.h> 66 67 int alc_match(struct device *, void *, void *); 68 void alc_attach(struct device *, struct device *, void *); 69 int alc_detach(struct device *, int); 70 int alc_activate(struct device *, int); 71 72 int alc_init(struct ifnet *); 73 void alc_start(struct ifnet *); 74 int alc_ioctl(struct ifnet *, u_long, caddr_t); 75 void alc_watchdog(struct ifnet *); 76 int alc_mediachange(struct ifnet *); 77 void alc_mediastatus(struct ifnet *, struct ifmediareq *); 78 79 void alc_aspm(struct alc_softc *, int, uint64_t); 80 void alc_aspm_813x(struct alc_softc *, uint64_t); 81 void alc_aspm_816x(struct alc_softc *, int); 82 void alc_disable_l0s_l1(struct alc_softc *); 83 int alc_dma_alloc(struct alc_softc *); 84 void alc_dma_free(struct alc_softc *); 85 int alc_encap(struct alc_softc *, struct mbuf *); 86 void alc_get_macaddr(struct alc_softc *); 87 void alc_get_macaddr_813x(struct alc_softc *); 88 void alc_get_macaddr_816x(struct alc_softc *); 89 void alc_get_macaddr_par(struct alc_softc *); 90 void alc_init_cmb(struct alc_softc *); 91 void alc_init_rr_ring(struct alc_softc *); 92 int alc_init_rx_ring(struct alc_softc *); 93 void alc_init_smb(struct alc_softc *); 94 void alc_init_tx_ring(struct alc_softc *); 95 int alc_intr(void *); 96 void alc_mac_config(struct alc_softc *); 97 int alc_mii_readreg_813x(struct device *, int, int); 98 int alc_mii_readreg_816x(struct device *, int, int); 99 void alc_mii_writereg_813x(struct device *, int, int, int); 100 void alc_mii_writereg_816x(struct device *, int, int, int); 101 void alc_dsp_fixup(struct alc_softc *, int); 102 int alc_miibus_readreg(struct device *, int, int); 103 void alc_miibus_statchg(struct device *); 104 void alc_miibus_writereg(struct device *, int, int, int); 105 int alc_miidbg_readreg(struct alc_softc *, int); 106 void alc_miidbg_writereg(struct alc_softc *, int, int); 107 int alc_miiext_readreg(struct alc_softc *, int, int); 108 void alc_miiext_writereg(struct alc_softc *, int, int, int); 109 void alc_phy_reset_813x(struct alc_softc *); 110 void alc_phy_reset_816x(struct alc_softc *); 111 int alc_newbuf(struct alc_softc *, struct alc_rxdesc *); 112 void alc_phy_down(struct alc_softc *); 113 void alc_phy_reset(struct alc_softc *); 114 void alc_reset(struct alc_softc *); 115 void alc_rxeof(struct alc_softc *, struct rx_rdesc *); 116 int alc_rxintr(struct alc_softc *); 117 void alc_iff(struct alc_softc *); 118 void alc_rxvlan(struct alc_softc *); 119 void alc_start_queue(struct alc_softc *); 120 void alc_stats_clear(struct alc_softc *); 121 void alc_stats_update(struct alc_softc *); 122 void alc_stop(struct alc_softc *); 123 void alc_stop_mac(struct alc_softc *); 124 void alc_stop_queue(struct alc_softc *); 125 void alc_tick(void *); 126 void alc_txeof(struct alc_softc *); 127 void alc_init_pcie(struct alc_softc *, int); 128 void alc_config_msi(struct alc_softc *); 129 int alc_dma_alloc(struct alc_softc *); 130 void alc_dma_free(struct alc_softc *); 131 int alc_encap(struct alc_softc *, struct mbuf *); 132 void alc_osc_reset(struct alc_softc *); 133 134 uint32_t alc_dma_burst[] = { 128, 256, 512, 1024, 2048, 4096, 0, 0 }; 135 136 const struct pci_matchid alc_devices[] = { 137 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L1C }, 138 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L2C }, 139 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L1D }, 140 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L1D_1 }, 141 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L2C_1 }, 142 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L2C_2 }, 143 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8161 }, 144 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8162 }, 145 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8171 }, 146 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8172 }, 147 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_E2200 }, 148 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_E2400 }, 149 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_E2500 } 150 }; 151 152 struct cfattach alc_ca = { 153 sizeof (struct alc_softc), alc_match, alc_attach, alc_detach, 154 alc_activate 155 }; 156 157 struct cfdriver alc_cd = { 158 NULL, "alc", DV_IFNET 159 }; 160 161 int alcdebug = 0; 162 #define DPRINTF(x) do { if (alcdebug) printf x; } while (0) 163 164 #define ALC_CSUM_FEATURES (M_TCP_CSUM_OUT | M_UDP_CSUM_OUT) 165 166 int 167 alc_miibus_readreg(struct device *dev, int phy, int reg) 168 { 169 struct alc_softc *sc = (struct alc_softc *)dev; 170 uint32_t v; 171 172 if (phy != sc->alc_phyaddr) 173 return (0); 174 175 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 176 v = alc_mii_readreg_816x(dev, phy, reg); 177 else 178 v = alc_mii_readreg_813x(dev, phy, reg); 179 180 return (v); 181 } 182 183 int 184 alc_mii_readreg_813x(struct device *dev, int phy, int reg) 185 { 186 struct alc_softc *sc = (struct alc_softc *)dev; 187 uint32_t v; 188 int i; 189 190 /* 191 * For AR8132 fast ethernet controller, do not report 1000baseT 192 * capability to mii(4). Even though AR8132 uses the same 193 * model/revision number of F1 gigabit PHY, the PHY has no 194 * ability to establish 1000baseT link. 195 */ 196 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0 && 197 reg == MII_EXTSR) 198 return (0); 199 200 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 201 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 202 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 203 DELAY(5); 204 v = CSR_READ_4(sc, ALC_MDIO); 205 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 206 break; 207 } 208 209 if (i == 0) { 210 printf("%s: phy read timeout: phy %d, reg %d\n", 211 sc->sc_dev.dv_xname, phy, reg); 212 return (0); 213 } 214 215 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 216 } 217 218 int 219 alc_mii_readreg_816x(struct device *dev, int phy, int reg) 220 { 221 struct alc_softc *sc = (struct alc_softc *)dev; 222 uint32_t clk, v; 223 int i; 224 225 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 226 clk = MDIO_CLK_25_128; 227 else 228 clk = MDIO_CLK_25_4; 229 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 230 MDIO_SUP_PREAMBLE | clk | MDIO_REG_ADDR(reg)); 231 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 232 DELAY(5); 233 v = CSR_READ_4(sc, ALC_MDIO); 234 if ((v & MDIO_OP_BUSY) == 0) 235 break; 236 } 237 238 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 239 } 240 241 void 242 alc_miibus_writereg(struct device *dev, int phy, int reg, int val) 243 { 244 struct alc_softc *sc = (struct alc_softc *)dev; 245 246 if (phy != sc->alc_phyaddr) 247 return; 248 249 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 250 alc_mii_writereg_816x(dev, phy, reg, val); 251 else 252 alc_mii_writereg_813x(dev, phy, reg, val); 253 } 254 255 void 256 alc_mii_writereg_813x(struct device *dev, int phy, int reg, int val) 257 { 258 struct alc_softc *sc = (struct alc_softc *)dev; 259 uint32_t v; 260 int i; 261 262 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 263 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 264 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 265 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 266 DELAY(5); 267 v = CSR_READ_4(sc, ALC_MDIO); 268 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 269 break; 270 } 271 272 if (i == 0) 273 printf("%s: phy write timeout: phy %d, reg %d\n", 274 sc->sc_dev.dv_xname, phy, reg); 275 } 276 277 void 278 alc_mii_writereg_816x(struct device *dev, int phy, int reg, int val) 279 { 280 struct alc_softc *sc = (struct alc_softc *)dev; 281 uint32_t clk, v; 282 int i; 283 284 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 285 clk = MDIO_CLK_25_128; 286 else 287 clk = MDIO_CLK_25_4; 288 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 289 ((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) | MDIO_REG_ADDR(reg) | 290 MDIO_SUP_PREAMBLE | clk); 291 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 292 DELAY(5); 293 v = CSR_READ_4(sc, ALC_MDIO); 294 if ((v & MDIO_OP_BUSY) == 0) 295 break; 296 } 297 298 if (i == 0) 299 printf("%s: phy write timeout: phy %d, reg %d\n", 300 sc->sc_dev.dv_xname, phy, reg); 301 } 302 303 void 304 alc_miibus_statchg(struct device *dev) 305 { 306 struct alc_softc *sc = (struct alc_softc *)dev; 307 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 308 struct mii_data *mii = &sc->sc_miibus; 309 uint32_t reg; 310 311 if ((ifp->if_flags & IFF_RUNNING) == 0) 312 return; 313 314 sc->alc_flags &= ~ALC_FLAG_LINK; 315 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 316 (IFM_ACTIVE | IFM_AVALID)) { 317 switch (IFM_SUBTYPE(mii->mii_media_active)) { 318 case IFM_10_T: 319 case IFM_100_TX: 320 sc->alc_flags |= ALC_FLAG_LINK; 321 break; 322 case IFM_1000_T: 323 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 324 sc->alc_flags |= ALC_FLAG_LINK; 325 break; 326 default: 327 break; 328 } 329 } 330 /* Stop Rx/Tx MACs. */ 331 alc_stop_mac(sc); 332 333 /* Program MACs with resolved speed/duplex/flow-control. */ 334 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 335 alc_start_queue(sc); 336 alc_mac_config(sc); 337 /* Re-enable Tx/Rx MACs. */ 338 reg = CSR_READ_4(sc, ALC_MAC_CFG); 339 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 340 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 341 } 342 alc_aspm(sc, 0, IFM_SUBTYPE(mii->mii_media_active)); 343 alc_dsp_fixup(sc, IFM_SUBTYPE(mii->mii_media_active)); 344 } 345 346 int 347 alc_miidbg_readreg(struct alc_softc *sc, int reg) 348 { 349 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 350 reg); 351 return (alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr, 352 ALC_MII_DBG_DATA)); 353 } 354 355 356 void 357 alc_miidbg_writereg(struct alc_softc *sc, int reg, int val) 358 { 359 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 360 reg); 361 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 362 val); 363 } 364 365 int 366 alc_miiext_readreg(struct alc_softc *sc, int devaddr, int reg) 367 { 368 uint32_t clk, v; 369 int i; 370 371 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | 372 EXT_MDIO_DEVADDR(devaddr)); 373 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 374 clk = MDIO_CLK_25_128; 375 else 376 clk = MDIO_CLK_25_4; 377 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 378 MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT); 379 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 380 DELAY(5); 381 v = CSR_READ_4(sc, ALC_MDIO); 382 if ((v & MDIO_OP_BUSY) == 0) 383 break; 384 } 385 386 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 387 } 388 389 void 390 alc_miiext_writereg(struct alc_softc *sc, int devaddr, int reg, int val) 391 { 392 uint32_t clk, v; 393 int i; 394 395 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | 396 EXT_MDIO_DEVADDR(devaddr)); 397 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 398 clk = MDIO_CLK_25_128; 399 else 400 clk = MDIO_CLK_25_4; 401 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 402 ((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) | 403 MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT); 404 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 405 DELAY(5); 406 v = CSR_READ_4(sc, ALC_MDIO); 407 if ((v & MDIO_OP_BUSY) == 0) 408 break; 409 } 410 } 411 412 void 413 alc_dsp_fixup(struct alc_softc *sc, int media) 414 { 415 uint16_t agc, len, val; 416 417 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 418 return; 419 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_C0) 420 return; 421 422 /* 423 * Vendor PHY magic. 424 * 1000BT/AZ, wrong cable length 425 */ 426 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 427 len = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL6); 428 len = (len >> EXT_CLDCTL6_CAB_LEN_SHIFT) & 429 EXT_CLDCTL6_CAB_LEN_MASK; 430 agc = alc_miidbg_readreg(sc, MII_DBG_AGC); 431 agc = (agc >> DBG_AGC_2_VGA_SHIFT) & DBG_AGC_2_VGA_MASK; 432 if ((media == IFM_1000_T && len > EXT_CLDCTL6_CAB_LEN_SHORT1G && 433 agc > DBG_AGC_LONG1G_LIMT) || 434 (media == IFM_100_TX && len > DBG_AGC_LONG100M_LIMT && 435 agc > DBG_AGC_LONG1G_LIMT)) { 436 alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT, 437 DBG_AZ_ANADECT_LONG); 438 val = alc_miiext_readreg(sc, MII_EXT_ANEG, 439 MII_EXT_ANEG_AFE); 440 val |= ANEG_AFEE_10BT_100M_TH; 441 alc_miiext_writereg(sc, MII_EXT_ANEG, 442 MII_EXT_ANEG_AFE, val); 443 } else { 444 alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT, 445 DBG_AZ_ANADECT_DEFAULT); 446 val = alc_miiext_readreg(sc, MII_EXT_ANEG, 447 MII_EXT_ANEG_AFE); 448 val &= ~ANEG_AFEE_10BT_100M_TH; 449 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, 450 val); 451 } 452 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 && 453 AR816X_REV(sc->alc_rev) == AR816X_REV_B0) { 454 if (media == IFM_1000_T) { 455 /* 456 * Giga link threshold, raise the tolerance of 457 * noise 50%. 458 */ 459 val = alc_miidbg_readreg(sc, MII_DBG_MSE20DB); 460 val &= ~DBG_MSE20DB_TH_MASK; 461 val |= (DBG_MSE20DB_TH_HI << 462 DBG_MSE20DB_TH_SHIFT); 463 alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val); 464 } else if (media == IFM_100_TX) 465 alc_miidbg_writereg(sc, MII_DBG_MSE16DB, 466 DBG_MSE16DB_UP); 467 } 468 } else { 469 val = alc_miiext_readreg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE); 470 val &= ~ANEG_AFEE_10BT_100M_TH; 471 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, val); 472 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 && 473 AR816X_REV(sc->alc_rev) == AR816X_REV_B0) { 474 alc_miidbg_writereg(sc, MII_DBG_MSE16DB, 475 DBG_MSE16DB_DOWN); 476 val = alc_miidbg_readreg(sc, MII_DBG_MSE20DB); 477 val &= ~DBG_MSE20DB_TH_MASK; 478 val |= (DBG_MSE20DB_TH_DEFAULT << DBG_MSE20DB_TH_SHIFT); 479 alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val); 480 } 481 } 482 } 483 484 void 485 alc_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 486 { 487 struct alc_softc *sc = ifp->if_softc; 488 struct mii_data *mii = &sc->sc_miibus; 489 490 if ((ifp->if_flags & IFF_UP) == 0) 491 return; 492 493 mii_pollstat(mii); 494 ifmr->ifm_status = mii->mii_media_status; 495 ifmr->ifm_active = mii->mii_media_active; 496 } 497 498 int 499 alc_mediachange(struct ifnet *ifp) 500 { 501 struct alc_softc *sc = ifp->if_softc; 502 struct mii_data *mii = &sc->sc_miibus; 503 int error; 504 505 if (mii->mii_instance != 0) { 506 struct mii_softc *miisc; 507 508 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 509 mii_phy_reset(miisc); 510 } 511 error = mii_mediachg(mii); 512 513 return (error); 514 } 515 516 int 517 alc_match(struct device *dev, void *match, void *aux) 518 { 519 return pci_matchbyid((struct pci_attach_args *)aux, alc_devices, 520 nitems(alc_devices)); 521 } 522 523 void 524 alc_get_macaddr(struct alc_softc *sc) 525 { 526 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 527 alc_get_macaddr_816x(sc); 528 else 529 alc_get_macaddr_813x(sc); 530 } 531 532 void 533 alc_get_macaddr_813x(struct alc_softc *sc) 534 { 535 uint32_t opt; 536 uint16_t val; 537 int eeprom, i; 538 539 eeprom = 0; 540 opt = CSR_READ_4(sc, ALC_OPT_CFG); 541 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 && 542 (CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) { 543 /* 544 * EEPROM found, let TWSI reload EEPROM configuration. 545 * This will set ethernet address of controller. 546 */ 547 eeprom++; 548 switch (sc->sc_product) { 549 case PCI_PRODUCT_ATTANSIC_L1C: 550 case PCI_PRODUCT_ATTANSIC_L2C: 551 if ((opt & OPT_CFG_CLK_ENB) == 0) { 552 opt |= OPT_CFG_CLK_ENB; 553 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 554 CSR_READ_4(sc, ALC_OPT_CFG); 555 DELAY(1000); 556 } 557 break; 558 case PCI_PRODUCT_ATTANSIC_L1D: 559 case PCI_PRODUCT_ATTANSIC_L1D_1: 560 case PCI_PRODUCT_ATTANSIC_L2C_1: 561 case PCI_PRODUCT_ATTANSIC_L2C_2: 562 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 563 ALC_MII_DBG_ADDR, 0x00); 564 val = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr, 565 ALC_MII_DBG_DATA); 566 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 567 ALC_MII_DBG_DATA, val & 0xFF7F); 568 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 569 ALC_MII_DBG_ADDR, 0x3B); 570 val = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr, 571 ALC_MII_DBG_DATA); 572 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 573 ALC_MII_DBG_DATA, val | 0x0008); 574 DELAY(20); 575 break; 576 } 577 578 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 579 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 580 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 581 CSR_READ_4(sc, ALC_WOL_CFG); 582 583 CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) | 584 TWSI_CFG_SW_LD_START); 585 for (i = 100; i > 0; i--) { 586 DELAY(1000); 587 if ((CSR_READ_4(sc, ALC_TWSI_CFG) & 588 TWSI_CFG_SW_LD_START) == 0) 589 break; 590 } 591 if (i == 0) 592 printf("%s: reloading EEPROM timeout!\n", 593 sc->sc_dev.dv_xname); 594 } else { 595 if (alcdebug) 596 printf("%s: EEPROM not found!\n", sc->sc_dev.dv_xname); 597 } 598 if (eeprom != 0) { 599 switch (sc->sc_product) { 600 case PCI_PRODUCT_ATTANSIC_L1C: 601 case PCI_PRODUCT_ATTANSIC_L2C: 602 if ((opt & OPT_CFG_CLK_ENB) != 0) { 603 opt &= ~OPT_CFG_CLK_ENB; 604 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 605 CSR_READ_4(sc, ALC_OPT_CFG); 606 DELAY(1000); 607 } 608 break; 609 case PCI_PRODUCT_ATTANSIC_L1D: 610 case PCI_PRODUCT_ATTANSIC_L1D_1: 611 case PCI_PRODUCT_ATTANSIC_L2C_1: 612 case PCI_PRODUCT_ATTANSIC_L2C_2: 613 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 614 ALC_MII_DBG_ADDR, 0x00); 615 val = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr, 616 ALC_MII_DBG_DATA); 617 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 618 ALC_MII_DBG_DATA, val | 0x0080); 619 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 620 ALC_MII_DBG_ADDR, 0x3B); 621 val = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr, 622 ALC_MII_DBG_DATA); 623 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 624 ALC_MII_DBG_DATA, val & 0xFFF7); 625 DELAY(20); 626 break; 627 } 628 } 629 630 alc_get_macaddr_par(sc); 631 } 632 633 void 634 alc_get_macaddr_816x(struct alc_softc *sc) 635 { 636 uint32_t reg; 637 int i, reloaded; 638 639 reloaded = 0; 640 /* Try to reload station address via TWSI. */ 641 for (i = 100; i > 0; i--) { 642 reg = CSR_READ_4(sc, ALC_SLD); 643 if ((reg & (SLD_PROGRESS | SLD_START)) == 0) 644 break; 645 DELAY(1000); 646 } 647 if (i != 0) { 648 CSR_WRITE_4(sc, ALC_SLD, reg | SLD_START); 649 for (i = 100; i > 0; i--) { 650 DELAY(1000); 651 reg = CSR_READ_4(sc, ALC_SLD); 652 if ((reg & SLD_START) == 0) 653 break; 654 } 655 } 656 657 /* Try to reload station address from EEPROM or FLASH. */ 658 if (reloaded == 0) { 659 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 660 if ((reg & (EEPROM_LD_EEPROM_EXIST | 661 EEPROM_LD_FLASH_EXIST)) != 0) { 662 for (i = 100; i > 0; i--) { 663 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 664 if ((reg & (EEPROM_LD_PROGRESS | 665 EEPROM_LD_START)) == 0) 666 break; 667 DELAY(1000); 668 } 669 if (i != 0) { 670 CSR_WRITE_4(sc, ALC_EEPROM_LD, reg | 671 EEPROM_LD_START); 672 for (i = 100; i > 0; i--) { 673 DELAY(1000); 674 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 675 if ((reg & EEPROM_LD_START) == 0) 676 break; 677 } 678 } 679 } 680 } 681 682 alc_get_macaddr_par(sc); 683 } 684 685 void 686 alc_get_macaddr_par(struct alc_softc *sc) 687 { 688 uint32_t ea[2]; 689 690 ea[0] = CSR_READ_4(sc, ALC_PAR0); 691 ea[1] = CSR_READ_4(sc, ALC_PAR1); 692 sc->alc_eaddr[0] = (ea[1] >> 8) & 0xFF; 693 sc->alc_eaddr[1] = (ea[1] >> 0) & 0xFF; 694 sc->alc_eaddr[2] = (ea[0] >> 24) & 0xFF; 695 sc->alc_eaddr[3] = (ea[0] >> 16) & 0xFF; 696 sc->alc_eaddr[4] = (ea[0] >> 8) & 0xFF; 697 sc->alc_eaddr[5] = (ea[0] >> 0) & 0xFF; 698 } 699 700 void 701 alc_disable_l0s_l1(struct alc_softc *sc) 702 { 703 uint32_t pmcfg; 704 705 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 706 /* Another magic from vendor. */ 707 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 708 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_CLK_SWH_L1 | 709 PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 710 PM_CFG_MAC_ASPM_CHK | PM_CFG_SERDES_PD_EX_L1); 711 pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB | 712 PM_CFG_SERDES_PLL_L1_ENB | PM_CFG_SERDES_L1_ENB; 713 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 714 } 715 } 716 717 void 718 alc_phy_reset(struct alc_softc *sc) 719 { 720 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 721 alc_phy_reset_816x(sc); 722 else 723 alc_phy_reset_813x(sc); 724 } 725 726 void 727 alc_phy_reset_813x(struct alc_softc *sc) 728 { 729 uint16_t data; 730 731 /* Reset magic from Linux. */ 732 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_SEL_ANA_RESET); 733 CSR_READ_2(sc, ALC_GPHY_CFG); 734 DELAY(10 * 1000); 735 736 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | 737 GPHY_CFG_SEL_ANA_RESET); 738 CSR_READ_2(sc, ALC_GPHY_CFG); 739 DELAY(10 * 1000); 740 741 /* DSP fixup, Vendor magic. */ 742 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1) { 743 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 744 ALC_MII_DBG_ADDR, 0x000A); 745 data = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr, 746 ALC_MII_DBG_DATA); 747 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 748 ALC_MII_DBG_DATA, data & 0xDFFF); 749 } 750 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D || 751 sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D_1 || 752 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1 || 753 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_2) { 754 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 755 ALC_MII_DBG_ADDR, 0x003B); 756 data = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr, 757 ALC_MII_DBG_DATA); 758 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 759 ALC_MII_DBG_DATA, data & 0xFFF7); 760 DELAY(20 * 1000); 761 } 762 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D) { 763 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 764 ALC_MII_DBG_ADDR, 0x0029); 765 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 766 ALC_MII_DBG_DATA, 0x929D); 767 } 768 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1C || 769 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C || 770 sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D_1 || 771 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_2) { 772 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 773 ALC_MII_DBG_ADDR, 0x0029); 774 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 775 ALC_MII_DBG_DATA, 0xB6DD); 776 } 777 778 /* Load DSP codes, vendor magic. */ 779 data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE | 780 ((1 << ANA_INTERVAL_SEL_TIMER_SHIFT) & ANA_INTERVAL_SEL_TIMER_MASK); 781 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 782 ALC_MII_DBG_ADDR, MII_ANA_CFG18); 783 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 784 ALC_MII_DBG_DATA, data); 785 786 data = ((2 << ANA_SERDES_CDR_BW_SHIFT) & ANA_SERDES_CDR_BW_MASK) | 787 ANA_SERDES_EN_DEEM | ANA_SERDES_SEL_HSP | ANA_SERDES_EN_PLL | 788 ANA_SERDES_EN_LCKDT; 789 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 790 ALC_MII_DBG_ADDR, MII_ANA_CFG5); 791 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 792 ALC_MII_DBG_DATA, data); 793 794 data = ((44 << ANA_LONG_CABLE_TH_100_SHIFT) & 795 ANA_LONG_CABLE_TH_100_MASK) | 796 ((33 << ANA_SHORT_CABLE_TH_100_SHIFT) & 797 ANA_SHORT_CABLE_TH_100_SHIFT) | 798 ANA_BP_BAD_LINK_ACCUM | ANA_BP_SMALL_BW; 799 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 800 ALC_MII_DBG_ADDR, MII_ANA_CFG54); 801 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 802 ALC_MII_DBG_DATA, data); 803 804 data = ((11 << ANA_IECHO_ADJ_3_SHIFT) & ANA_IECHO_ADJ_3_MASK) | 805 ((11 << ANA_IECHO_ADJ_2_SHIFT) & ANA_IECHO_ADJ_2_MASK) | 806 ((8 << ANA_IECHO_ADJ_1_SHIFT) & ANA_IECHO_ADJ_1_MASK) | 807 ((8 << ANA_IECHO_ADJ_0_SHIFT) & ANA_IECHO_ADJ_0_MASK); 808 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 809 ALC_MII_DBG_ADDR, MII_ANA_CFG4); 810 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 811 ALC_MII_DBG_DATA, data); 812 813 data = ((7 & ANA_MANUL_SWICH_ON_SHIFT) & ANA_MANUL_SWICH_ON_MASK) | 814 ANA_RESTART_CAL | ANA_MAN_ENABLE | ANA_SEL_HSP | ANA_EN_HB | 815 ANA_OEN_125M; 816 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 817 ALC_MII_DBG_ADDR, MII_ANA_CFG0); 818 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 819 ALC_MII_DBG_DATA, data); 820 DELAY(1000); 821 822 /* Disable hibernation. */ 823 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 824 0x0029); 825 data = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr, 826 ALC_MII_DBG_DATA); 827 data &= ~0x8000; 828 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 829 data); 830 831 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 832 0x000B); 833 data = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr, 834 ALC_MII_DBG_DATA); 835 data &= ~0x8000; 836 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 837 data); 838 } 839 840 void 841 alc_phy_reset_816x(struct alc_softc *sc) 842 { 843 uint32_t val; 844 845 val = CSR_READ_4(sc, ALC_GPHY_CFG); 846 val &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | 847 GPHY_CFG_GATE_25M_ENB | GPHY_CFG_PHY_IDDQ | GPHY_CFG_PHY_PLL_ON | 848 GPHY_CFG_PWDOWN_HW | GPHY_CFG_100AB_ENB); 849 val |= GPHY_CFG_SEL_ANA_RESET; 850 /* Disable PHY hibernation. */ 851 val &= ~(GPHY_CFG_HIB_PULSE | GPHY_CFG_HIB_EN); 852 CSR_WRITE_4(sc, ALC_GPHY_CFG, val); 853 DELAY(10); 854 CSR_WRITE_4(sc, ALC_GPHY_CFG, val | GPHY_CFG_EXT_RESET); 855 DELAY(800); 856 /* Vendor PHY magic. */ 857 /* Disable PHY hibernation. */ 858 alc_miidbg_writereg(sc, MII_DBG_LEGCYPS, 859 DBG_LEGCYPS_DEFAULT & ~DBG_LEGCYPS_ENB); 860 alc_miidbg_writereg(sc, MII_DBG_HIBNEG, DBG_HIBNEG_DEFAULT & 861 ~(DBG_HIBNEG_PSHIB_EN | DBG_HIBNEG_HIB_PULSE)); 862 alc_miidbg_writereg(sc, MII_DBG_GREENCFG, DBG_GREENCFG_DEFAULT); 863 /* XXX Disable EEE. */ 864 val = CSR_READ_4(sc, ALC_LPI_CTL); 865 val &= ~LPI_CTL_ENB; 866 CSR_WRITE_4(sc, ALC_LPI_CTL, val); 867 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_LOCAL_EEEADV, 0); 868 /* PHY power saving. */ 869 alc_miidbg_writereg(sc, MII_DBG_TST10BTCFG, DBG_TST10BTCFG_DEFAULT); 870 alc_miidbg_writereg(sc, MII_DBG_SRDSYSMOD, DBG_SRDSYSMOD_DEFAULT); 871 alc_miidbg_writereg(sc, MII_DBG_TST100BTCFG, DBG_TST100BTCFG_DEFAULT); 872 alc_miidbg_writereg(sc, MII_DBG_ANACTL, DBG_ANACTL_DEFAULT); 873 val = alc_miidbg_readreg(sc, MII_DBG_GREENCFG2); 874 val &= ~DBG_GREENCFG2_GATE_DFSE_EN; 875 alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, val); 876 /* RTL8139C, 120m issue. */ 877 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_NLP78, 878 ANEG_NLP78_120M_DEFAULT); 879 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_S3DIG10, 880 ANEG_S3DIG10_DEFAULT); 881 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0) { 882 /* Turn off half amplitude. */ 883 val = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3); 884 val |= EXT_CLDCTL3_BP_CABLE1TH_DET_GT; 885 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3, val); 886 /* Turn off Green feature. */ 887 val = alc_miidbg_readreg(sc, MII_DBG_GREENCFG2); 888 val |= DBG_GREENCFG2_BP_GREEN; 889 alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, val); 890 /* Turn off half bias. */ 891 val = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5); 892 val |= EXT_CLDCTL5_BP_VD_HLFBIAS; 893 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5, val); 894 } 895 } 896 897 void 898 alc_phy_down(struct alc_softc *sc) 899 { 900 uint32_t gphy; 901 902 switch (sc->sc_product) { 903 case PCI_PRODUCT_ATTANSIC_AR8161: 904 case PCI_PRODUCT_ATTANSIC_E2200: 905 case PCI_PRODUCT_ATTANSIC_E2400: 906 case PCI_PRODUCT_ATTANSIC_E2500: 907 case PCI_PRODUCT_ATTANSIC_AR8162: 908 case PCI_PRODUCT_ATTANSIC_AR8171: 909 case PCI_PRODUCT_ATTANSIC_AR8172: 910 gphy = CSR_READ_4(sc, ALC_GPHY_CFG); 911 gphy &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | 912 GPHY_CFG_100AB_ENB | GPHY_CFG_PHY_PLL_ON); 913 gphy |= GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | 914 GPHY_CFG_SEL_ANA_RESET; 915 gphy |= GPHY_CFG_PHY_IDDQ | GPHY_CFG_PWDOWN_HW; 916 CSR_WRITE_4(sc, ALC_GPHY_CFG, gphy); 917 break; 918 case PCI_PRODUCT_ATTANSIC_L1D: 919 case PCI_PRODUCT_ATTANSIC_L1D_1: 920 case PCI_PRODUCT_ATTANSIC_L2C_1: 921 case PCI_PRODUCT_ATTANSIC_L2C_2: 922 /* 923 * GPHY power down caused more problems on AR8151 v2.0. 924 * When driver is reloaded after GPHY power down, 925 * accesses to PHY/MAC registers hung the system. Only 926 * cold boot recovered from it. I'm not sure whether 927 * AR8151 v1.0 also requires this one though. I don't 928 * have AR8151 v1.0 controller in hand. 929 * The only option left is to isolate the PHY and 930 * initiates power down the PHY which in turn saves 931 * more power when driver is unloaded. 932 */ 933 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 934 MII_BMCR, BMCR_ISO | BMCR_PDOWN); 935 break; 936 default: 937 /* Force PHY down. */ 938 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | 939 GPHY_CFG_SEL_ANA_RESET | GPHY_CFG_PHY_IDDQ | 940 GPHY_CFG_PWDOWN_HW); 941 DELAY(1000); 942 break; 943 } 944 } 945 946 void 947 alc_aspm(struct alc_softc *sc, int init, uint64_t media) 948 { 949 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 950 alc_aspm_816x(sc, init); 951 else 952 alc_aspm_813x(sc, media); 953 } 954 955 void 956 alc_aspm_813x(struct alc_softc *sc, uint64_t media) 957 { 958 uint32_t pmcfg; 959 uint16_t linkcfg; 960 961 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 962 if ((sc->alc_flags & (ALC_FLAG_APS | ALC_FLAG_PCIE)) == 963 (ALC_FLAG_APS | ALC_FLAG_PCIE)) 964 linkcfg = CSR_READ_2(sc, sc->alc_expcap + PCI_PCIE_LCSR); 965 else 966 linkcfg = 0; 967 pmcfg &= ~PM_CFG_SERDES_PD_EX_L1; 968 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_LCKDET_TIMER_MASK); 969 pmcfg |= PM_CFG_MAC_ASPM_CHK; 970 pmcfg |= (PM_CFG_LCKDET_TIMER_DEFAULT << PM_CFG_LCKDET_TIMER_SHIFT); 971 pmcfg &= ~(PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 972 973 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 974 /* Disable extended sync except AR8152 B v1.0 */ 975 linkcfg &= ~0x80; 976 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1 && 977 sc->alc_rev == ATHEROS_AR8152_B_V10) 978 linkcfg |= 0x80; 979 CSR_WRITE_2(sc, sc->alc_expcap + PCI_PCIE_LCSR, linkcfg); 980 pmcfg &= ~(PM_CFG_EN_BUFS_RX_L0S | PM_CFG_SA_DLY_ENB | 981 PM_CFG_HOTRST); 982 pmcfg |= (PM_CFG_L1_ENTRY_TIMER_DEFAULT << 983 PM_CFG_L1_ENTRY_TIMER_SHIFT); 984 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 985 pmcfg |= (PM_CFG_PM_REQ_TIMER_DEFAULT << 986 PM_CFG_PM_REQ_TIMER_SHIFT); 987 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_PCIE_RECV; 988 } 989 990 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 991 if ((sc->alc_flags & ALC_FLAG_L0S) != 0) 992 pmcfg |= PM_CFG_ASPM_L0S_ENB; 993 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 994 pmcfg |= PM_CFG_ASPM_L1_ENB; 995 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 996 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1) 997 pmcfg &= ~PM_CFG_ASPM_L0S_ENB; 998 pmcfg &= ~(PM_CFG_SERDES_L1_ENB | 999 PM_CFG_SERDES_PLL_L1_ENB | 1000 PM_CFG_SERDES_BUDS_RX_L1_ENB); 1001 pmcfg |= PM_CFG_CLK_SWH_L1; 1002 if (media == IFM_100_TX || media == IFM_1000_T) { 1003 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK; 1004 switch (sc->sc_product) { 1005 case PCI_PRODUCT_ATTANSIC_L2C_1: 1006 pmcfg |= (7 << 1007 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1008 break; 1009 case PCI_PRODUCT_ATTANSIC_L1D_1: 1010 case PCI_PRODUCT_ATTANSIC_L2C_2: 1011 pmcfg |= (4 << 1012 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1013 break; 1014 default: 1015 pmcfg |= (15 << 1016 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1017 break; 1018 } 1019 } 1020 } else { 1021 pmcfg |= PM_CFG_SERDES_L1_ENB | 1022 PM_CFG_SERDES_PLL_L1_ENB | 1023 PM_CFG_SERDES_BUDS_RX_L1_ENB; 1024 pmcfg &= ~(PM_CFG_CLK_SWH_L1 | 1025 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 1026 } 1027 } else { 1028 pmcfg &= ~(PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_L1_ENB | 1029 PM_CFG_SERDES_PLL_L1_ENB); 1030 pmcfg |= PM_CFG_CLK_SWH_L1; 1031 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 1032 pmcfg |= PM_CFG_ASPM_L1_ENB; 1033 } 1034 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 1035 } 1036 1037 void 1038 alc_aspm_816x(struct alc_softc *sc, int init) 1039 { 1040 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1041 uint32_t pmcfg; 1042 1043 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 1044 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_816X_MASK; 1045 pmcfg |= PM_CFG_L1_ENTRY_TIMER_816X_DEFAULT; 1046 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 1047 pmcfg |= PM_CFG_PM_REQ_TIMER_816X_DEFAULT; 1048 pmcfg &= ~PM_CFG_LCKDET_TIMER_MASK; 1049 pmcfg |= PM_CFG_LCKDET_TIMER_DEFAULT; 1050 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_CLK_SWH_L1 | PM_CFG_PCIE_RECV; 1051 pmcfg &= ~(PM_CFG_RX_L1_AFTER_L0S | PM_CFG_TX_L1_AFTER_L0S | 1052 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB | 1053 PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB | 1054 PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SA_DLY_ENB | 1055 PM_CFG_MAC_ASPM_CHK | PM_CFG_HOTRST); 1056 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 1057 (sc->alc_rev & 0x01) != 0) 1058 pmcfg |= PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB; 1059 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 1060 /* Link up, enable both L0s, L1s. */ 1061 pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 1062 PM_CFG_MAC_ASPM_CHK; 1063 } else { 1064 if (init != 0) 1065 pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 1066 PM_CFG_MAC_ASPM_CHK; 1067 else if ((ifp->if_flags & IFF_RUNNING) != 0) 1068 pmcfg |= PM_CFG_ASPM_L1_ENB | PM_CFG_MAC_ASPM_CHK; 1069 } 1070 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 1071 } 1072 1073 void 1074 alc_init_pcie(struct alc_softc *sc, int base) 1075 { 1076 const char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/L1" }; 1077 uint32_t cap, ctl, val; 1078 int state; 1079 1080 /* Clear data link and flow-control protocol error. */ 1081 val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV); 1082 val &= ~(PEX_UNC_ERR_SEV_DLP | PEX_UNC_ERR_SEV_FCP); 1083 CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val); 1084 1085 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 1086 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 1087 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 1088 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, 1089 CSR_READ_4(sc, ALC_PCIE_PHYMISC) | 1090 PCIE_PHYMISC_FORCE_RCV_DET); 1091 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1 && 1092 sc->alc_rev == ATHEROS_AR8152_B_V10) { 1093 val = CSR_READ_4(sc, ALC_PCIE_PHYMISC2); 1094 val &= ~(PCIE_PHYMISC2_SERDES_CDR_MASK | 1095 PCIE_PHYMISC2_SERDES_TH_MASK); 1096 val |= 3 << PCIE_PHYMISC2_SERDES_CDR_SHIFT; 1097 val |= 3 << PCIE_PHYMISC2_SERDES_TH_SHIFT; 1098 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC2, val); 1099 } 1100 /* Disable ASPM L0S and L1. */ 1101 cap = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 1102 base + PCI_PCIE_LCAP) >> 16; 1103 if ((cap & 0x00000c00) != 0) { 1104 ctl = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 1105 base + PCI_PCIE_LCSR) >> 16; 1106 if ((ctl & 0x08) != 0) 1107 sc->alc_rcb = DMA_CFG_RCB_128; 1108 if (alcdebug) 1109 printf("%s: RCB %u bytes\n", 1110 sc->sc_dev.dv_xname, 1111 sc->alc_rcb == DMA_CFG_RCB_64 ? 64 : 128); 1112 state = ctl & 0x03; 1113 if (state & 0x01) 1114 sc->alc_flags |= ALC_FLAG_L0S; 1115 if (state & 0x02) 1116 sc->alc_flags |= ALC_FLAG_L1S; 1117 if (alcdebug) 1118 printf("%s: ASPM %s %s\n", 1119 sc->sc_dev.dv_xname, 1120 aspm_state[state], 1121 state == 0 ? "disabled" : "enabled"); 1122 alc_disable_l0s_l1(sc); 1123 } 1124 } else { 1125 val = CSR_READ_4(sc, ALC_PDLL_TRNS1); 1126 val &= ~PDLL_TRNS1_D3PLLOFF_ENB; 1127 CSR_WRITE_4(sc, ALC_PDLL_TRNS1, val); 1128 val = CSR_READ_4(sc, ALC_MASTER_CFG); 1129 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 1130 (sc->alc_rev & 0x01) != 0) { 1131 if ((val & MASTER_WAKEN_25M) == 0 || 1132 (val & MASTER_CLK_SEL_DIS) == 0) { 1133 val |= MASTER_WAKEN_25M | MASTER_CLK_SEL_DIS; 1134 CSR_WRITE_4(sc, ALC_MASTER_CFG, val); 1135 } 1136 } else { 1137 if ((val & MASTER_WAKEN_25M) == 0 || 1138 (val & MASTER_CLK_SEL_DIS) != 0) { 1139 val |= MASTER_WAKEN_25M; 1140 val &= ~MASTER_CLK_SEL_DIS; 1141 CSR_WRITE_4(sc, ALC_MASTER_CFG, val); 1142 } 1143 } 1144 } 1145 } 1146 1147 void 1148 alc_config_msi(struct alc_softc *sc) 1149 { 1150 uint32_t ctl, mod; 1151 1152 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 1153 /* 1154 * It seems interrupt moderation is controlled by 1155 * ALC_MSI_RETRANS_TIMER register if MSI/MSIX is active. 1156 * Driver uses RX interrupt moderation parameter to 1157 * program ALC_MSI_RETRANS_TIMER register. 1158 */ 1159 ctl = CSR_READ_4(sc, ALC_MSI_RETRANS_TIMER); 1160 ctl &= ~MSI_RETRANS_TIMER_MASK; 1161 ctl &= ~MSI_RETRANS_MASK_SEL_LINE; 1162 mod = ALC_USECS(sc->alc_int_rx_mod); 1163 if (mod == 0) 1164 mod = 1; 1165 ctl |= mod; 1166 if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1167 CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, ctl | 1168 MSI_RETRANS_MASK_SEL_LINE); 1169 else 1170 CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, 0); 1171 } 1172 } 1173 1174 void 1175 alc_attach(struct device *parent, struct device *self, void *aux) 1176 { 1177 struct alc_softc *sc = (struct alc_softc *)self; 1178 struct pci_attach_args *pa = aux; 1179 pci_chipset_tag_t pc = pa->pa_pc; 1180 pci_intr_handle_t ih; 1181 const char *intrstr; 1182 struct ifnet *ifp; 1183 pcireg_t memtype; 1184 uint16_t burst; 1185 int base, error = 0; 1186 1187 /* Set PHY address. */ 1188 sc->alc_phyaddr = ALC_PHY_ADDR; 1189 1190 /* Get PCI and chip id/revision. */ 1191 sc->sc_product = PCI_PRODUCT(pa->pa_id); 1192 sc->alc_rev = PCI_REVISION(pa->pa_class); 1193 1194 /* 1195 * One odd thing is AR8132 uses the same PHY hardware(F1 1196 * gigabit PHY) of AR8131. So atphy(4) of AR8132 reports 1197 * the PHY supports 1000Mbps but that's not true. The PHY 1198 * used in AR8132 can't establish gigabit link even if it 1199 * shows the same PHY model/revision number of AR8131. 1200 */ 1201 switch (sc->sc_product) { 1202 case PCI_PRODUCT_ATTANSIC_E2200: 1203 case PCI_PRODUCT_ATTANSIC_E2400: 1204 case PCI_PRODUCT_ATTANSIC_E2500: 1205 sc->alc_flags |= ALC_FLAG_E2X00; 1206 /* FALLTHROUGH */ 1207 case PCI_PRODUCT_ATTANSIC_AR8161: 1208 if (AR816X_REV(sc->alc_rev) == 0) 1209 sc->alc_flags |= ALC_FLAG_LINK_WAR; 1210 /* FALLTHROUGH */ 1211 case PCI_PRODUCT_ATTANSIC_AR8171: 1212 sc->alc_flags |= ALC_FLAG_AR816X_FAMILY; 1213 break; 1214 case PCI_PRODUCT_ATTANSIC_AR8162: 1215 case PCI_PRODUCT_ATTANSIC_AR8172: 1216 sc->alc_flags |= ALC_FLAG_FASTETHER | ALC_FLAG_AR816X_FAMILY; 1217 break; 1218 case PCI_PRODUCT_ATTANSIC_L2C_1: 1219 case PCI_PRODUCT_ATTANSIC_L2C_2: 1220 sc->alc_flags |= ALC_FLAG_APS; 1221 /* FALLTHROUGH */ 1222 case PCI_PRODUCT_ATTANSIC_L2C: 1223 sc->alc_flags |= ALC_FLAG_FASTETHER; 1224 break; 1225 case PCI_PRODUCT_ATTANSIC_L1D: 1226 case PCI_PRODUCT_ATTANSIC_L1D_1: 1227 sc->alc_flags |= ALC_FLAG_APS; 1228 /* FALLTHROUGH */ 1229 default: 1230 break; 1231 } 1232 sc->alc_flags |= ALC_FLAG_JUMBO; 1233 1234 /* 1235 * Allocate IO memory 1236 */ 1237 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, ALC_PCIR_BAR); 1238 if (pci_mapreg_map(pa, ALC_PCIR_BAR, memtype, 0, &sc->sc_mem_bt, 1239 &sc->sc_mem_bh, NULL, &sc->sc_mem_size, 0)) { 1240 printf(": can't map mem space\n"); 1241 return; 1242 } 1243 1244 sc->alc_flags |= ALC_FLAG_MSI; 1245 if (pci_intr_map_msi(pa, &ih) != 0) { 1246 if (pci_intr_map(pa, &ih) != 0) { 1247 printf(": can't map interrupt\n"); 1248 goto fail; 1249 } 1250 sc->alc_flags &= ~ALC_FLAG_MSI; 1251 } 1252 1253 /* 1254 * Allocate IRQ 1255 */ 1256 intrstr = pci_intr_string(pc, ih); 1257 sc->sc_irq_handle = pci_intr_establish(pc, ih, IPL_NET, alc_intr, sc, 1258 sc->sc_dev.dv_xname); 1259 if (sc->sc_irq_handle == NULL) { 1260 printf(": could not establish interrupt"); 1261 if (intrstr != NULL) 1262 printf(" at %s", intrstr); 1263 printf("\n"); 1264 goto fail; 1265 } 1266 printf(": %s", intrstr); 1267 1268 alc_config_msi(sc); 1269 1270 sc->sc_dmat = pa->pa_dmat; 1271 sc->sc_pct = pa->pa_pc; 1272 sc->sc_pcitag = pa->pa_tag; 1273 1274 switch (sc->sc_product) { 1275 case PCI_PRODUCT_ATTANSIC_L1D: 1276 case PCI_PRODUCT_ATTANSIC_L1D_1: 1277 case PCI_PRODUCT_ATTANSIC_L2C_1: 1278 case PCI_PRODUCT_ATTANSIC_L2C_2: 1279 sc->alc_max_framelen = 6 * 1024; 1280 break; 1281 default: 1282 sc->alc_max_framelen = 9 * 1024; 1283 break; 1284 } 1285 1286 /* 1287 * It seems that AR813x/AR815x has silicon bug for SMB. In 1288 * addition, Atheros said that enabling SMB wouldn't improve 1289 * performance. However I think it's bad to access lots of 1290 * registers to extract MAC statistics. 1291 */ 1292 sc->alc_flags |= ALC_FLAG_SMB_BUG; 1293 /* 1294 * Don't use Tx CMB. It is known to have silicon bug. 1295 */ 1296 sc->alc_flags |= ALC_FLAG_CMB_BUG; 1297 sc->alc_chip_rev = CSR_READ_4(sc, ALC_MASTER_CFG) >> 1298 MASTER_CHIP_REV_SHIFT; 1299 if (alcdebug) { 1300 printf("%s: PCI device revision : 0x%04x\n", 1301 sc->sc_dev.dv_xname, sc->alc_rev); 1302 printf("%s: Chip id/revision : 0x%04x\n", 1303 sc->sc_dev.dv_xname, sc->alc_chip_rev); 1304 printf("%s: %u Tx FIFO, %u Rx FIFO\n", sc->sc_dev.dv_xname, 1305 CSR_READ_4(sc, ALC_SRAM_TX_FIFO_LEN) * 8, 1306 CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN) * 8); 1307 } 1308 1309 /* Initialize DMA parameters. */ 1310 sc->alc_dma_rd_burst = 0; 1311 sc->alc_dma_wr_burst = 0; 1312 sc->alc_rcb = DMA_CFG_RCB_64; 1313 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PCIEXPRESS, 1314 &base, NULL)) { 1315 sc->alc_flags |= ALC_FLAG_PCIE; 1316 sc->alc_expcap = base; 1317 burst = CSR_READ_2(sc, base + PCI_PCIE_DCSR); 1318 sc->alc_dma_rd_burst = (burst & 0x7000) >> 12; 1319 sc->alc_dma_wr_burst = (burst & 0x00e0) >> 5; 1320 if (alcdebug) { 1321 printf("%s: Read request size : %u bytes.\n", 1322 sc->sc_dev.dv_xname, 1323 alc_dma_burst[sc->alc_dma_rd_burst]); 1324 printf("%s: TLP payload size : %u bytes.\n", 1325 sc->sc_dev.dv_xname, 1326 alc_dma_burst[sc->alc_dma_wr_burst]); 1327 } 1328 if (alc_dma_burst[sc->alc_dma_rd_burst] > 1024) 1329 sc->alc_dma_rd_burst = 3; 1330 if (alc_dma_burst[sc->alc_dma_wr_burst] > 1024) 1331 sc->alc_dma_wr_burst = 3; 1332 /* 1333 * Force maximum payload size to 128 bytes for 1334 * E2200/E2400/E2500. 1335 * Otherwise it triggers DMA write error. 1336 */ 1337 if ((sc->alc_flags & ALC_FLAG_E2X00) != 0) 1338 sc->alc_dma_wr_burst = 0; 1339 alc_init_pcie(sc, base); 1340 } 1341 1342 /* Reset PHY. */ 1343 alc_phy_reset(sc); 1344 1345 /* Reset the ethernet controller. */ 1346 alc_stop_mac(sc); 1347 alc_reset(sc); 1348 1349 error = alc_dma_alloc(sc); 1350 if (error) 1351 goto fail; 1352 1353 /* Load station address. */ 1354 alc_get_macaddr(sc); 1355 1356 ifp = &sc->sc_arpcom.ac_if; 1357 ifp->if_softc = sc; 1358 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1359 ifp->if_ioctl = alc_ioctl; 1360 ifp->if_start = alc_start; 1361 ifp->if_watchdog = alc_watchdog; 1362 IFQ_SET_MAXLEN(&ifp->if_snd, ALC_TX_RING_CNT - 1); 1363 bcopy(sc->alc_eaddr, sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN); 1364 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 1365 1366 ifp->if_capabilities = IFCAP_VLAN_MTU; 1367 1368 #ifdef ALC_CHECKSUM 1369 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 1370 IFCAP_CSUM_UDPv4; 1371 #endif 1372 1373 #if NVLAN > 0 1374 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 1375 #endif 1376 1377 printf(", address %s\n", ether_sprintf(sc->sc_arpcom.ac_enaddr)); 1378 1379 /* Set up MII bus. */ 1380 sc->sc_miibus.mii_ifp = ifp; 1381 sc->sc_miibus.mii_readreg = alc_miibus_readreg; 1382 sc->sc_miibus.mii_writereg = alc_miibus_writereg; 1383 sc->sc_miibus.mii_statchg = alc_miibus_statchg; 1384 1385 ifmedia_init(&sc->sc_miibus.mii_media, 0, alc_mediachange, 1386 alc_mediastatus); 1387 mii_attach(self, &sc->sc_miibus, 0xffffffff, MII_PHY_ANY, 1388 MII_OFFSET_ANY, MIIF_DOPAUSE); 1389 1390 if (LIST_FIRST(&sc->sc_miibus.mii_phys) == NULL) { 1391 printf("%s: no PHY found!\n", sc->sc_dev.dv_xname); 1392 ifmedia_add(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL, 1393 0, NULL); 1394 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL); 1395 } else 1396 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_AUTO); 1397 1398 if_attach(ifp); 1399 ether_ifattach(ifp); 1400 1401 timeout_set(&sc->alc_tick_ch, alc_tick, sc); 1402 1403 return; 1404 fail: 1405 alc_dma_free(sc); 1406 if (sc->sc_irq_handle != NULL) 1407 pci_intr_disestablish(pc, sc->sc_irq_handle); 1408 if (sc->sc_mem_size) 1409 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 1410 } 1411 1412 int 1413 alc_detach(struct device *self, int flags) 1414 { 1415 struct alc_softc *sc = (struct alc_softc *)self; 1416 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1417 int s; 1418 1419 s = splnet(); 1420 alc_stop(sc); 1421 splx(s); 1422 1423 mii_detach(&sc->sc_miibus, MII_PHY_ANY, MII_OFFSET_ANY); 1424 1425 /* Delete all remaining media. */ 1426 ifmedia_delete_instance(&sc->sc_miibus.mii_media, IFM_INST_ANY); 1427 1428 ether_ifdetach(ifp); 1429 if_detach(ifp); 1430 alc_dma_free(sc); 1431 1432 alc_phy_down(sc); 1433 if (sc->sc_irq_handle != NULL) { 1434 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 1435 sc->sc_irq_handle = NULL; 1436 } 1437 1438 return (0); 1439 } 1440 1441 int 1442 alc_activate(struct device *self, int act) 1443 { 1444 struct alc_softc *sc = (struct alc_softc *)self; 1445 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1446 int rv = 0; 1447 1448 switch (act) { 1449 case DVACT_SUSPEND: 1450 if (ifp->if_flags & IFF_RUNNING) 1451 alc_stop(sc); 1452 rv = config_activate_children(self, act); 1453 break; 1454 case DVACT_RESUME: 1455 if (ifp->if_flags & IFF_UP) 1456 alc_init(ifp); 1457 break; 1458 default: 1459 rv = config_activate_children(self, act); 1460 break; 1461 } 1462 return (rv); 1463 } 1464 1465 int 1466 alc_dma_alloc(struct alc_softc *sc) 1467 { 1468 struct alc_txdesc *txd; 1469 struct alc_rxdesc *rxd; 1470 int nsegs, error, i; 1471 1472 /* 1473 * Create DMA stuffs for TX ring 1474 */ 1475 error = bus_dmamap_create(sc->sc_dmat, ALC_TX_RING_SZ, 1, 1476 ALC_TX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->alc_cdata.alc_tx_ring_map); 1477 if (error) 1478 return (ENOBUFS); 1479 1480 /* Allocate DMA'able memory for TX ring */ 1481 error = bus_dmamem_alloc(sc->sc_dmat, ALC_TX_RING_SZ, 1482 ETHER_ALIGN, 0, &sc->alc_rdata.alc_tx_ring_seg, 1, 1483 &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 1484 if (error) { 1485 printf("%s: could not allocate DMA'able memory for Tx ring.\n", 1486 sc->sc_dev.dv_xname); 1487 return (error); 1488 } 1489 1490 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_tx_ring_seg, 1491 nsegs, ALC_TX_RING_SZ, (caddr_t *)&sc->alc_rdata.alc_tx_ring, 1492 BUS_DMA_NOWAIT); 1493 if (error) 1494 return (ENOBUFS); 1495 1496 /* Load the DMA map for Tx ring. */ 1497 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 1498 sc->alc_rdata.alc_tx_ring, ALC_TX_RING_SZ, NULL, BUS_DMA_WAITOK); 1499 if (error) { 1500 printf("%s: could not load DMA'able memory for Tx ring.\n", 1501 sc->sc_dev.dv_xname); 1502 bus_dmamem_free(sc->sc_dmat, 1503 (bus_dma_segment_t *)&sc->alc_rdata.alc_tx_ring, 1); 1504 return (error); 1505 } 1506 1507 sc->alc_rdata.alc_tx_ring_paddr = 1508 sc->alc_cdata.alc_tx_ring_map->dm_segs[0].ds_addr; 1509 1510 /* 1511 * Create DMA stuffs for RX ring 1512 */ 1513 error = bus_dmamap_create(sc->sc_dmat, ALC_RX_RING_SZ, 1, 1514 ALC_RX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->alc_cdata.alc_rx_ring_map); 1515 if (error) 1516 return (ENOBUFS); 1517 1518 /* Allocate DMA'able memory for RX ring */ 1519 error = bus_dmamem_alloc(sc->sc_dmat, ALC_RX_RING_SZ, 1520 ETHER_ALIGN, 0, &sc->alc_rdata.alc_rx_ring_seg, 1, 1521 &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 1522 if (error) { 1523 printf("%s: could not allocate DMA'able memory for Rx ring.\n", 1524 sc->sc_dev.dv_xname); 1525 return (error); 1526 } 1527 1528 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_rx_ring_seg, 1529 nsegs, ALC_RX_RING_SZ, (caddr_t *)&sc->alc_rdata.alc_rx_ring, 1530 BUS_DMA_NOWAIT); 1531 if (error) 1532 return (ENOBUFS); 1533 1534 /* Load the DMA map for Rx ring. */ 1535 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 1536 sc->alc_rdata.alc_rx_ring, ALC_RX_RING_SZ, NULL, BUS_DMA_WAITOK); 1537 if (error) { 1538 printf("%s: could not load DMA'able memory for Rx ring.\n", 1539 sc->sc_dev.dv_xname); 1540 bus_dmamem_free(sc->sc_dmat, 1541 (bus_dma_segment_t *)sc->alc_rdata.alc_rx_ring, 1); 1542 return (error); 1543 } 1544 1545 sc->alc_rdata.alc_rx_ring_paddr = 1546 sc->alc_cdata.alc_rx_ring_map->dm_segs[0].ds_addr; 1547 1548 /* 1549 * Create DMA stuffs for RX return ring 1550 */ 1551 error = bus_dmamap_create(sc->sc_dmat, ALC_RR_RING_SZ, 1, 1552 ALC_RR_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->alc_cdata.alc_rr_ring_map); 1553 if (error) 1554 return (ENOBUFS); 1555 1556 /* Allocate DMA'able memory for RX return ring */ 1557 error = bus_dmamem_alloc(sc->sc_dmat, ALC_RR_RING_SZ, 1558 ETHER_ALIGN, 0, &sc->alc_rdata.alc_rr_ring_seg, 1, 1559 &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 1560 if (error) { 1561 printf("%s: could not allocate DMA'able memory for Rx " 1562 "return ring.\n", sc->sc_dev.dv_xname); 1563 return (error); 1564 } 1565 1566 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_rr_ring_seg, 1567 nsegs, ALC_RR_RING_SZ, (caddr_t *)&sc->alc_rdata.alc_rr_ring, 1568 BUS_DMA_NOWAIT); 1569 if (error) 1570 return (ENOBUFS); 1571 1572 /* Load the DMA map for Rx return ring. */ 1573 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 1574 sc->alc_rdata.alc_rr_ring, ALC_RR_RING_SZ, NULL, BUS_DMA_WAITOK); 1575 if (error) { 1576 printf("%s: could not load DMA'able memory for Rx return ring." 1577 "\n", sc->sc_dev.dv_xname); 1578 bus_dmamem_free(sc->sc_dmat, 1579 (bus_dma_segment_t *)&sc->alc_rdata.alc_rr_ring, 1); 1580 return (error); 1581 } 1582 1583 sc->alc_rdata.alc_rr_ring_paddr = 1584 sc->alc_cdata.alc_rr_ring_map->dm_segs[0].ds_addr; 1585 1586 /* 1587 * Create DMA stuffs for CMB block 1588 */ 1589 error = bus_dmamap_create(sc->sc_dmat, ALC_CMB_SZ, 1, 1590 ALC_CMB_SZ, 0, BUS_DMA_NOWAIT, 1591 &sc->alc_cdata.alc_cmb_map); 1592 if (error) 1593 return (ENOBUFS); 1594 1595 /* Allocate DMA'able memory for CMB block */ 1596 error = bus_dmamem_alloc(sc->sc_dmat, ALC_CMB_SZ, 1597 ETHER_ALIGN, 0, &sc->alc_rdata.alc_cmb_seg, 1, 1598 &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 1599 if (error) { 1600 printf("%s: could not allocate DMA'able memory for " 1601 "CMB block\n", sc->sc_dev.dv_xname); 1602 return (error); 1603 } 1604 1605 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_cmb_seg, 1606 nsegs, ALC_CMB_SZ, (caddr_t *)&sc->alc_rdata.alc_cmb, 1607 BUS_DMA_NOWAIT); 1608 if (error) 1609 return (ENOBUFS); 1610 1611 /* Load the DMA map for CMB block. */ 1612 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 1613 sc->alc_rdata.alc_cmb, ALC_CMB_SZ, NULL, 1614 BUS_DMA_WAITOK); 1615 if (error) { 1616 printf("%s: could not load DMA'able memory for CMB block\n", 1617 sc->sc_dev.dv_xname); 1618 bus_dmamem_free(sc->sc_dmat, 1619 (bus_dma_segment_t *)&sc->alc_rdata.alc_cmb, 1); 1620 return (error); 1621 } 1622 1623 sc->alc_rdata.alc_cmb_paddr = 1624 sc->alc_cdata.alc_cmb_map->dm_segs[0].ds_addr; 1625 1626 /* 1627 * Create DMA stuffs for SMB block 1628 */ 1629 error = bus_dmamap_create(sc->sc_dmat, ALC_SMB_SZ, 1, 1630 ALC_SMB_SZ, 0, BUS_DMA_NOWAIT, 1631 &sc->alc_cdata.alc_smb_map); 1632 if (error) 1633 return (ENOBUFS); 1634 1635 /* Allocate DMA'able memory for SMB block */ 1636 error = bus_dmamem_alloc(sc->sc_dmat, ALC_SMB_SZ, 1637 ETHER_ALIGN, 0, &sc->alc_rdata.alc_smb_seg, 1, 1638 &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 1639 if (error) { 1640 printf("%s: could not allocate DMA'able memory for " 1641 "SMB block\n", sc->sc_dev.dv_xname); 1642 return (error); 1643 } 1644 1645 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_smb_seg, 1646 nsegs, ALC_SMB_SZ, (caddr_t *)&sc->alc_rdata.alc_smb, 1647 BUS_DMA_NOWAIT); 1648 if (error) 1649 return (ENOBUFS); 1650 1651 /* Load the DMA map for SMB block */ 1652 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 1653 sc->alc_rdata.alc_smb, ALC_SMB_SZ, NULL, 1654 BUS_DMA_WAITOK); 1655 if (error) { 1656 printf("%s: could not load DMA'able memory for SMB block\n", 1657 sc->sc_dev.dv_xname); 1658 bus_dmamem_free(sc->sc_dmat, 1659 (bus_dma_segment_t *)&sc->alc_rdata.alc_smb, 1); 1660 return (error); 1661 } 1662 1663 sc->alc_rdata.alc_smb_paddr = 1664 sc->alc_cdata.alc_smb_map->dm_segs[0].ds_addr; 1665 1666 1667 /* Create DMA maps for Tx buffers. */ 1668 for (i = 0; i < ALC_TX_RING_CNT; i++) { 1669 txd = &sc->alc_cdata.alc_txdesc[i]; 1670 txd->tx_m = NULL; 1671 txd->tx_dmamap = NULL; 1672 error = bus_dmamap_create(sc->sc_dmat, ALC_TSO_MAXSIZE, 1673 ALC_MAXTXSEGS, ALC_TSO_MAXSEGSIZE, 0, BUS_DMA_NOWAIT, 1674 &txd->tx_dmamap); 1675 if (error) { 1676 printf("%s: could not create Tx dmamap.\n", 1677 sc->sc_dev.dv_xname); 1678 return (error); 1679 } 1680 } 1681 1682 /* Create DMA maps for Rx buffers. */ 1683 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 1684 BUS_DMA_NOWAIT, &sc->alc_cdata.alc_rx_sparemap); 1685 if (error) { 1686 printf("%s: could not create spare Rx dmamap.\n", 1687 sc->sc_dev.dv_xname); 1688 return (error); 1689 } 1690 1691 for (i = 0; i < ALC_RX_RING_CNT; i++) { 1692 rxd = &sc->alc_cdata.alc_rxdesc[i]; 1693 rxd->rx_m = NULL; 1694 rxd->rx_dmamap = NULL; 1695 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1696 MCLBYTES, 0, BUS_DMA_NOWAIT, &rxd->rx_dmamap); 1697 if (error) { 1698 printf("%s: could not create Rx dmamap.\n", 1699 sc->sc_dev.dv_xname); 1700 return (error); 1701 } 1702 } 1703 1704 return (0); 1705 } 1706 1707 void 1708 alc_dma_free(struct alc_softc *sc) 1709 { 1710 struct alc_txdesc *txd; 1711 struct alc_rxdesc *rxd; 1712 int i; 1713 1714 /* Tx buffers */ 1715 for (i = 0; i < ALC_TX_RING_CNT; i++) { 1716 txd = &sc->alc_cdata.alc_txdesc[i]; 1717 if (txd->tx_dmamap != NULL) { 1718 bus_dmamap_destroy(sc->sc_dmat, txd->tx_dmamap); 1719 txd->tx_dmamap = NULL; 1720 } 1721 } 1722 /* Rx buffers */ 1723 for (i = 0; i < ALC_RX_RING_CNT; i++) { 1724 rxd = &sc->alc_cdata.alc_rxdesc[i]; 1725 if (rxd->rx_dmamap != NULL) { 1726 bus_dmamap_destroy(sc->sc_dmat, rxd->rx_dmamap); 1727 rxd->rx_dmamap = NULL; 1728 } 1729 } 1730 if (sc->alc_cdata.alc_rx_sparemap != NULL) { 1731 bus_dmamap_destroy(sc->sc_dmat, sc->alc_cdata.alc_rx_sparemap); 1732 sc->alc_cdata.alc_rx_sparemap = NULL; 1733 } 1734 1735 /* Tx ring. */ 1736 if (sc->alc_cdata.alc_tx_ring_map != NULL) 1737 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map); 1738 if (sc->alc_cdata.alc_tx_ring_map != NULL && 1739 sc->alc_rdata.alc_tx_ring != NULL) 1740 bus_dmamem_free(sc->sc_dmat, 1741 (bus_dma_segment_t *)sc->alc_rdata.alc_tx_ring, 1); 1742 sc->alc_rdata.alc_tx_ring = NULL; 1743 sc->alc_cdata.alc_tx_ring_map = NULL; 1744 1745 /* Rx ring. */ 1746 if (sc->alc_cdata.alc_rx_ring_map != NULL) 1747 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map); 1748 if (sc->alc_cdata.alc_rx_ring_map != NULL && 1749 sc->alc_rdata.alc_rx_ring != NULL) 1750 bus_dmamem_free(sc->sc_dmat, 1751 (bus_dma_segment_t *)sc->alc_rdata.alc_rx_ring, 1); 1752 sc->alc_rdata.alc_rx_ring = NULL; 1753 sc->alc_cdata.alc_rx_ring_map = NULL; 1754 1755 /* Rx return ring. */ 1756 if (sc->alc_cdata.alc_rr_ring_map != NULL) 1757 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map); 1758 if (sc->alc_cdata.alc_rr_ring_map != NULL && 1759 sc->alc_rdata.alc_rr_ring != NULL) 1760 bus_dmamem_free(sc->sc_dmat, 1761 (bus_dma_segment_t *)sc->alc_rdata.alc_rr_ring, 1); 1762 sc->alc_rdata.alc_rr_ring = NULL; 1763 sc->alc_cdata.alc_rr_ring_map = NULL; 1764 1765 /* CMB block */ 1766 if (sc->alc_cdata.alc_cmb_map != NULL) 1767 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_cmb_map); 1768 if (sc->alc_cdata.alc_cmb_map != NULL && 1769 sc->alc_rdata.alc_cmb != NULL) 1770 bus_dmamem_free(sc->sc_dmat, 1771 (bus_dma_segment_t *)sc->alc_rdata.alc_cmb, 1); 1772 sc->alc_rdata.alc_cmb = NULL; 1773 sc->alc_cdata.alc_cmb_map = NULL; 1774 1775 /* SMB block */ 1776 if (sc->alc_cdata.alc_smb_map != NULL) 1777 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_smb_map); 1778 if (sc->alc_cdata.alc_smb_map != NULL && 1779 sc->alc_rdata.alc_smb != NULL) 1780 bus_dmamem_free(sc->sc_dmat, 1781 (bus_dma_segment_t *)sc->alc_rdata.alc_smb, 1); 1782 sc->alc_rdata.alc_smb = NULL; 1783 sc->alc_cdata.alc_smb_map = NULL; 1784 } 1785 1786 int 1787 alc_encap(struct alc_softc *sc, struct mbuf *m) 1788 { 1789 struct alc_txdesc *txd, *txd_last; 1790 struct tx_desc *desc; 1791 bus_dmamap_t map; 1792 uint32_t cflags, poff, vtag; 1793 int error, idx, prod; 1794 1795 cflags = vtag = 0; 1796 poff = 0; 1797 1798 prod = sc->alc_cdata.alc_tx_prod; 1799 txd = &sc->alc_cdata.alc_txdesc[prod]; 1800 txd_last = txd; 1801 map = txd->tx_dmamap; 1802 1803 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, BUS_DMA_NOWAIT); 1804 if (error != 0 && error != EFBIG) 1805 goto drop; 1806 if (error != 0) { 1807 if (m_defrag(m, M_DONTWAIT)) { 1808 error = ENOBUFS; 1809 goto drop; 1810 } 1811 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1812 BUS_DMA_NOWAIT); 1813 if (error != 0) 1814 goto drop; 1815 } 1816 1817 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1818 BUS_DMASYNC_PREWRITE); 1819 1820 desc = NULL; 1821 idx = 0; 1822 #if NVLAN > 0 1823 /* Configure VLAN hardware tag insertion. */ 1824 if (m->m_flags & M_VLANTAG) { 1825 vtag = htons(m->m_pkthdr.ether_vtag); 1826 vtag = (vtag << TD_VLAN_SHIFT) & TD_VLAN_MASK; 1827 cflags |= TD_INS_VLAN_TAG; 1828 } 1829 #endif 1830 /* Configure Tx checksum offload. */ 1831 if ((m->m_pkthdr.csum_flags & ALC_CSUM_FEATURES) != 0) { 1832 cflags |= TD_CUSTOM_CSUM; 1833 /* Set checksum start offset. */ 1834 cflags |= ((poff >> 1) << TD_PLOAD_OFFSET_SHIFT) & 1835 TD_PLOAD_OFFSET_MASK; 1836 } 1837 1838 for (; idx < map->dm_nsegs; idx++) { 1839 desc = &sc->alc_rdata.alc_tx_ring[prod]; 1840 desc->len = 1841 htole32(TX_BYTES(map->dm_segs[idx].ds_len) | vtag); 1842 desc->flags = htole32(cflags); 1843 desc->addr = htole64(map->dm_segs[idx].ds_addr); 1844 sc->alc_cdata.alc_tx_cnt++; 1845 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 1846 } 1847 1848 /* Update producer index. */ 1849 sc->alc_cdata.alc_tx_prod = prod; 1850 1851 /* Finally set EOP on the last descriptor. */ 1852 prod = (prod + ALC_TX_RING_CNT - 1) % ALC_TX_RING_CNT; 1853 desc = &sc->alc_rdata.alc_tx_ring[prod]; 1854 desc->flags |= htole32(TD_EOP); 1855 1856 /* Swap dmamap of the first and the last. */ 1857 txd = &sc->alc_cdata.alc_txdesc[prod]; 1858 map = txd_last->tx_dmamap; 1859 txd_last->tx_dmamap = txd->tx_dmamap; 1860 txd->tx_dmamap = map; 1861 txd->tx_m = m; 1862 1863 return (0); 1864 1865 drop: 1866 m_freem(m); 1867 return (error); 1868 } 1869 1870 void 1871 alc_start(struct ifnet *ifp) 1872 { 1873 struct alc_softc *sc = ifp->if_softc; 1874 struct mbuf *m; 1875 int enq = 0; 1876 1877 /* Reclaim transmitted frames. */ 1878 if (sc->alc_cdata.alc_tx_cnt >= ALC_TX_DESC_HIWAT) 1879 alc_txeof(sc); 1880 1881 if (!(ifp->if_flags & IFF_RUNNING) || ifq_is_oactive(&ifp->if_snd)) 1882 return; 1883 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) 1884 return; 1885 if (IFQ_IS_EMPTY(&ifp->if_snd)) 1886 return; 1887 1888 for (;;) { 1889 if (sc->alc_cdata.alc_tx_cnt + ALC_MAXTXSEGS >= 1890 ALC_TX_RING_CNT - 3) { 1891 ifq_set_oactive(&ifp->if_snd); 1892 break; 1893 } 1894 1895 IFQ_DEQUEUE(&ifp->if_snd, m); 1896 if (m == NULL) 1897 break; 1898 1899 if (alc_encap(sc, m) != 0) { 1900 ifp->if_oerrors++; 1901 continue; 1902 } 1903 enq++; 1904 1905 #if NBPFILTER > 0 1906 /* 1907 * If there's a BPF listener, bounce a copy of this frame 1908 * to him. 1909 */ 1910 if (ifp->if_bpf != NULL) 1911 bpf_mtap_ether(ifp->if_bpf, m, BPF_DIRECTION_OUT); 1912 #endif 1913 } 1914 1915 if (enq > 0) { 1916 /* Sync descriptors. */ 1917 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0, 1918 sc->alc_cdata.alc_tx_ring_map->dm_mapsize, 1919 BUS_DMASYNC_PREWRITE); 1920 /* Kick. Assume we're using normal Tx priority queue. */ 1921 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 1922 CSR_WRITE_2(sc, ALC_MBOX_TD_PRI0_PROD_IDX, 1923 (uint16_t)sc->alc_cdata.alc_tx_prod); 1924 else 1925 CSR_WRITE_4(sc, ALC_MBOX_TD_PROD_IDX, 1926 (sc->alc_cdata.alc_tx_prod << 1927 MBOX_TD_PROD_LO_IDX_SHIFT) & 1928 MBOX_TD_PROD_LO_IDX_MASK); 1929 /* Set a timeout in case the chip goes out to lunch. */ 1930 ifp->if_timer = ALC_TX_TIMEOUT; 1931 } 1932 } 1933 1934 void 1935 alc_watchdog(struct ifnet *ifp) 1936 { 1937 struct alc_softc *sc = ifp->if_softc; 1938 1939 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) { 1940 printf("%s: watchdog timeout (missed link)\n", 1941 sc->sc_dev.dv_xname); 1942 ifp->if_oerrors++; 1943 alc_init(ifp); 1944 return; 1945 } 1946 1947 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 1948 ifp->if_oerrors++; 1949 alc_init(ifp); 1950 alc_start(ifp); 1951 } 1952 1953 int 1954 alc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1955 { 1956 struct alc_softc *sc = ifp->if_softc; 1957 struct mii_data *mii = &sc->sc_miibus; 1958 struct ifreq *ifr = (struct ifreq *)data; 1959 int s, error = 0; 1960 1961 s = splnet(); 1962 1963 switch (cmd) { 1964 case SIOCSIFADDR: 1965 ifp->if_flags |= IFF_UP; 1966 if (!(ifp->if_flags & IFF_RUNNING)) 1967 alc_init(ifp); 1968 break; 1969 1970 case SIOCSIFFLAGS: 1971 if (ifp->if_flags & IFF_UP) { 1972 if (ifp->if_flags & IFF_RUNNING) 1973 error = ENETRESET; 1974 else 1975 alc_init(ifp); 1976 } else { 1977 if (ifp->if_flags & IFF_RUNNING) 1978 alc_stop(sc); 1979 } 1980 break; 1981 1982 case SIOCSIFMEDIA: 1983 case SIOCGIFMEDIA: 1984 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1985 break; 1986 1987 default: 1988 error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data); 1989 break; 1990 } 1991 1992 if (error == ENETRESET) { 1993 if (ifp->if_flags & IFF_RUNNING) 1994 alc_iff(sc); 1995 error = 0; 1996 } 1997 1998 splx(s); 1999 return (error); 2000 } 2001 2002 void 2003 alc_mac_config(struct alc_softc *sc) 2004 { 2005 struct mii_data *mii; 2006 uint32_t reg; 2007 2008 mii = &sc->sc_miibus; 2009 reg = CSR_READ_4(sc, ALC_MAC_CFG); 2010 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 2011 MAC_CFG_SPEED_MASK); 2012 if ((sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D || 2013 sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D_1 || 2014 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_2 || 2015 sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 2016 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 2017 /* Reprogram MAC with resolved speed/duplex. */ 2018 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2019 case IFM_10_T: 2020 case IFM_100_TX: 2021 reg |= MAC_CFG_SPEED_10_100; 2022 break; 2023 case IFM_1000_T: 2024 reg |= MAC_CFG_SPEED_1000; 2025 break; 2026 } 2027 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 2028 reg |= MAC_CFG_FULL_DUPLEX; 2029 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 2030 reg |= MAC_CFG_TX_FC; 2031 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 2032 reg |= MAC_CFG_RX_FC; 2033 } 2034 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 2035 } 2036 2037 void 2038 alc_stats_clear(struct alc_softc *sc) 2039 { 2040 struct smb sb, *smb; 2041 uint32_t *reg; 2042 int i; 2043 2044 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2045 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 2046 sc->alc_cdata.alc_smb_map->dm_mapsize, 2047 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2048 smb = sc->alc_rdata.alc_smb; 2049 /* Update done, clear. */ 2050 smb->updated = 0; 2051 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 2052 sc->alc_cdata.alc_smb_map->dm_mapsize, 2053 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2054 } else { 2055 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 2056 reg++) { 2057 CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 2058 i += sizeof(uint32_t); 2059 } 2060 /* Read Tx statistics. */ 2061 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 2062 reg++) { 2063 CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 2064 i += sizeof(uint32_t); 2065 } 2066 } 2067 } 2068 2069 void 2070 alc_stats_update(struct alc_softc *sc) 2071 { 2072 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 2073 struct alc_hw_stats *stat; 2074 struct smb sb, *smb; 2075 uint32_t *reg; 2076 int i; 2077 2078 stat = &sc->alc_stats; 2079 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2080 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 2081 sc->alc_cdata.alc_smb_map->dm_mapsize, 2082 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2083 smb = sc->alc_rdata.alc_smb; 2084 if (smb->updated == 0) 2085 return; 2086 } else { 2087 smb = &sb; 2088 /* Read Rx statistics. */ 2089 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 2090 reg++) { 2091 *reg = CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 2092 i += sizeof(uint32_t); 2093 } 2094 /* Read Tx statistics. */ 2095 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 2096 reg++) { 2097 *reg = CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 2098 i += sizeof(uint32_t); 2099 } 2100 } 2101 2102 /* Rx stats. */ 2103 stat->rx_frames += smb->rx_frames; 2104 stat->rx_bcast_frames += smb->rx_bcast_frames; 2105 stat->rx_mcast_frames += smb->rx_mcast_frames; 2106 stat->rx_pause_frames += smb->rx_pause_frames; 2107 stat->rx_control_frames += smb->rx_control_frames; 2108 stat->rx_crcerrs += smb->rx_crcerrs; 2109 stat->rx_lenerrs += smb->rx_lenerrs; 2110 stat->rx_bytes += smb->rx_bytes; 2111 stat->rx_runts += smb->rx_runts; 2112 stat->rx_fragments += smb->rx_fragments; 2113 stat->rx_pkts_64 += smb->rx_pkts_64; 2114 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 2115 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 2116 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2117 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2118 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2119 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2120 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2121 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2122 stat->rx_rrs_errs += smb->rx_rrs_errs; 2123 stat->rx_alignerrs += smb->rx_alignerrs; 2124 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2125 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2126 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2127 2128 /* Tx stats. */ 2129 stat->tx_frames += smb->tx_frames; 2130 stat->tx_bcast_frames += smb->tx_bcast_frames; 2131 stat->tx_mcast_frames += smb->tx_mcast_frames; 2132 stat->tx_pause_frames += smb->tx_pause_frames; 2133 stat->tx_excess_defer += smb->tx_excess_defer; 2134 stat->tx_control_frames += smb->tx_control_frames; 2135 stat->tx_deferred += smb->tx_deferred; 2136 stat->tx_bytes += smb->tx_bytes; 2137 stat->tx_pkts_64 += smb->tx_pkts_64; 2138 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2139 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2140 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2141 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2142 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2143 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2144 stat->tx_single_colls += smb->tx_single_colls; 2145 stat->tx_multi_colls += smb->tx_multi_colls; 2146 stat->tx_late_colls += smb->tx_late_colls; 2147 stat->tx_excess_colls += smb->tx_excess_colls; 2148 stat->tx_underrun += smb->tx_underrun; 2149 stat->tx_desc_underrun += smb->tx_desc_underrun; 2150 stat->tx_lenerrs += smb->tx_lenerrs; 2151 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2152 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2153 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2154 2155 ifp->if_collisions += smb->tx_single_colls + 2156 smb->tx_multi_colls * 2 + smb->tx_late_colls + 2157 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT; 2158 2159 ifp->if_oerrors += smb->tx_late_colls + smb->tx_excess_colls + 2160 smb->tx_underrun + smb->tx_pkts_truncated; 2161 2162 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 2163 smb->rx_runts + smb->rx_pkts_truncated + 2164 smb->rx_fifo_oflows + smb->rx_rrs_errs + 2165 smb->rx_alignerrs; 2166 2167 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2168 /* Update done, clear. */ 2169 smb->updated = 0; 2170 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 2171 sc->alc_cdata.alc_smb_map->dm_mapsize, 2172 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2173 } 2174 } 2175 2176 int 2177 alc_intr(void *arg) 2178 { 2179 struct alc_softc *sc = arg; 2180 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 2181 uint32_t status; 2182 int claimed = 0; 2183 2184 status = CSR_READ_4(sc, ALC_INTR_STATUS); 2185 if ((status & ALC_INTRS) == 0) 2186 return (0); 2187 2188 /* Disable interrupts. */ 2189 CSR_WRITE_4(sc, ALC_INTR_STATUS, INTR_DIS_INT); 2190 2191 status = CSR_READ_4(sc, ALC_INTR_STATUS); 2192 if ((status & ALC_INTRS) == 0) 2193 goto back; 2194 2195 /* Acknowledge and disable interrupts. */ 2196 CSR_WRITE_4(sc, ALC_INTR_STATUS, status | INTR_DIS_INT); 2197 2198 if (ifp->if_flags & IFF_RUNNING) { 2199 int error = 0; 2200 2201 if (status & INTR_RX_PKT) { 2202 error = alc_rxintr(sc); 2203 if (error) { 2204 alc_init(ifp); 2205 return (0); 2206 } 2207 } 2208 if (status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | 2209 INTR_TXQ_TO_RST)) { 2210 if (status & INTR_DMA_RD_TO_RST) 2211 printf("%s: DMA read error! -- resetting\n", 2212 sc->sc_dev.dv_xname); 2213 if (status & INTR_DMA_WR_TO_RST) 2214 printf("%s: DMA write error! -- resetting\n", 2215 sc->sc_dev.dv_xname); 2216 if (status & INTR_TXQ_TO_RST) 2217 printf("%s: TxQ reset! -- resetting\n", 2218 sc->sc_dev.dv_xname); 2219 alc_init(ifp); 2220 return (0); 2221 } 2222 2223 alc_txeof(sc); 2224 alc_start(ifp); 2225 } 2226 2227 claimed = 1; 2228 back: 2229 /* Re-enable interrupts. */ 2230 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0x7FFFFFFF); 2231 return (claimed); 2232 } 2233 2234 void 2235 alc_txeof(struct alc_softc *sc) 2236 { 2237 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 2238 struct alc_txdesc *txd; 2239 uint32_t cons, prod; 2240 int prog; 2241 2242 if (sc->alc_cdata.alc_tx_cnt == 0) 2243 return; 2244 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0, 2245 sc->alc_cdata.alc_tx_ring_map->dm_mapsize, 2246 BUS_DMASYNC_POSTWRITE); 2247 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 2248 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0, 2249 sc->alc_cdata.alc_cmb_map->dm_mapsize, 2250 BUS_DMASYNC_POSTREAD); 2251 prod = sc->alc_rdata.alc_cmb->cons; 2252 } else { 2253 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 2254 prod = CSR_READ_2(sc, ALC_MBOX_TD_PRI0_CONS_IDX); 2255 else { 2256 prod = CSR_READ_4(sc, ALC_MBOX_TD_CONS_IDX); 2257 /* Assume we're using normal Tx priority queue. */ 2258 prod = (prod & MBOX_TD_CONS_LO_IDX_MASK) >> 2259 MBOX_TD_CONS_LO_IDX_SHIFT; 2260 } 2261 } 2262 cons = sc->alc_cdata.alc_tx_cons; 2263 /* 2264 * Go through our Tx list and free mbufs for those 2265 * frames which have been transmitted. 2266 */ 2267 for (prog = 0; cons != prod; prog++, 2268 ALC_DESC_INC(cons, ALC_TX_RING_CNT)) { 2269 if (sc->alc_cdata.alc_tx_cnt <= 0) 2270 break; 2271 prog++; 2272 ifq_clr_oactive(&ifp->if_snd); 2273 sc->alc_cdata.alc_tx_cnt--; 2274 txd = &sc->alc_cdata.alc_txdesc[cons]; 2275 if (txd->tx_m != NULL) { 2276 /* Reclaim transmitted mbufs. */ 2277 bus_dmamap_sync(sc->sc_dmat, txd->tx_dmamap, 0, 2278 txd->tx_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2279 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 2280 m_freem(txd->tx_m); 2281 txd->tx_m = NULL; 2282 } 2283 } 2284 2285 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 2286 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0, 2287 sc->alc_cdata.alc_cmb_map->dm_mapsize, BUS_DMASYNC_PREREAD); 2288 sc->alc_cdata.alc_tx_cons = cons; 2289 /* 2290 * Unarm watchdog timer only when there is no pending 2291 * frames in Tx queue. 2292 */ 2293 if (sc->alc_cdata.alc_tx_cnt == 0) 2294 ifp->if_timer = 0; 2295 } 2296 2297 int 2298 alc_newbuf(struct alc_softc *sc, struct alc_rxdesc *rxd) 2299 { 2300 struct mbuf *m; 2301 bus_dmamap_t map; 2302 int error; 2303 2304 MGETHDR(m, M_DONTWAIT, MT_DATA); 2305 if (m == NULL) 2306 return (ENOBUFS); 2307 MCLGET(m, M_DONTWAIT); 2308 if (!(m->m_flags & M_EXT)) { 2309 m_freem(m); 2310 return (ENOBUFS); 2311 } 2312 2313 m->m_len = m->m_pkthdr.len = RX_BUF_SIZE_MAX; 2314 2315 error = bus_dmamap_load_mbuf(sc->sc_dmat, 2316 sc->alc_cdata.alc_rx_sparemap, m, BUS_DMA_NOWAIT); 2317 2318 if (error != 0) { 2319 m_freem(m); 2320 printf("%s: can't load RX mbuf\n", sc->sc_dev.dv_xname); 2321 return (error); 2322 } 2323 2324 if (rxd->rx_m != NULL) { 2325 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0, 2326 rxd->rx_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2327 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 2328 } 2329 map = rxd->rx_dmamap; 2330 rxd->rx_dmamap = sc->alc_cdata.alc_rx_sparemap; 2331 sc->alc_cdata.alc_rx_sparemap = map; 2332 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0, rxd->rx_dmamap->dm_mapsize, 2333 BUS_DMASYNC_PREREAD); 2334 rxd->rx_m = m; 2335 rxd->rx_desc->addr = htole64(rxd->rx_dmamap->dm_segs[0].ds_addr); 2336 return (0); 2337 } 2338 2339 int 2340 alc_rxintr(struct alc_softc *sc) 2341 { 2342 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 2343 struct rx_rdesc *rrd; 2344 uint32_t nsegs, status; 2345 int rr_cons, prog; 2346 2347 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 0, 2348 sc->alc_cdata.alc_rr_ring_map->dm_mapsize, 2349 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2350 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 0, 2351 sc->alc_cdata.alc_rx_ring_map->dm_mapsize, 2352 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2353 rr_cons = sc->alc_cdata.alc_rr_cons; 2354 for (prog = 0; (ifp->if_flags & IFF_RUNNING) != 0;) { 2355 rrd = &sc->alc_rdata.alc_rr_ring[rr_cons]; 2356 status = letoh32(rrd->status); 2357 if ((status & RRD_VALID) == 0) 2358 break; 2359 nsegs = RRD_RD_CNT(letoh32(rrd->rdinfo)); 2360 if (nsegs == 0) { 2361 /* This should not happen! */ 2362 if (alcdebug) 2363 printf("%s: unexpected segment count -- " 2364 "resetting\n", sc->sc_dev.dv_xname); 2365 return (EIO); 2366 } 2367 alc_rxeof(sc, rrd); 2368 /* Clear Rx return status. */ 2369 rrd->status = 0; 2370 ALC_DESC_INC(rr_cons, ALC_RR_RING_CNT); 2371 sc->alc_cdata.alc_rx_cons += nsegs; 2372 sc->alc_cdata.alc_rx_cons %= ALC_RR_RING_CNT; 2373 prog += nsegs; 2374 } 2375 2376 if (prog > 0) { 2377 /* Update the consumer index. */ 2378 sc->alc_cdata.alc_rr_cons = rr_cons; 2379 /* Sync Rx return descriptors. */ 2380 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 0, 2381 sc->alc_cdata.alc_rr_ring_map->dm_mapsize, 2382 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2383 /* 2384 * Sync updated Rx descriptors such that controller see 2385 * modified buffer addresses. 2386 */ 2387 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 0, 2388 sc->alc_cdata.alc_rx_ring_map->dm_mapsize, 2389 BUS_DMASYNC_PREWRITE); 2390 /* 2391 * Let controller know availability of new Rx buffers. 2392 * Since alc(4) use RXQ_CFG_RD_BURST_DEFAULT descriptors 2393 * it may be possible to update ALC_MBOX_RD0_PROD_IDX 2394 * only when Rx buffer pre-fetching is required. In 2395 * addition we already set ALC_RX_RD_FREE_THRESH to 2396 * RX_RD_FREE_THRESH_LO_DEFAULT descriptors. However 2397 * it still seems that pre-fetching needs more 2398 * experimentation. 2399 */ 2400 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 2401 CSR_WRITE_2(sc, ALC_MBOX_RD0_PROD_IDX, 2402 (uint16_t)sc->alc_cdata.alc_rx_cons); 2403 else 2404 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 2405 sc->alc_cdata.alc_rx_cons); 2406 } 2407 2408 return (0); 2409 } 2410 2411 /* Receive a frame. */ 2412 void 2413 alc_rxeof(struct alc_softc *sc, struct rx_rdesc *rrd) 2414 { 2415 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 2416 struct alc_rxdesc *rxd; 2417 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 2418 struct mbuf *mp, *m; 2419 uint32_t rdinfo, status; 2420 int count, nsegs, rx_cons; 2421 2422 status = letoh32(rrd->status); 2423 rdinfo = letoh32(rrd->rdinfo); 2424 rx_cons = RRD_RD_IDX(rdinfo); 2425 nsegs = RRD_RD_CNT(rdinfo); 2426 2427 sc->alc_cdata.alc_rxlen = RRD_BYTES(status); 2428 if (status & (RRD_ERR_SUM | RRD_ERR_LENGTH)) { 2429 /* 2430 * We want to pass the following frames to upper 2431 * layer regardless of error status of Rx return 2432 * ring. 2433 * 2434 * o IP/TCP/UDP checksum is bad. 2435 * o frame length and protocol specific length 2436 * does not match. 2437 * 2438 * Force network stack compute checksum for 2439 * errored frames. 2440 */ 2441 if ((status & (RRD_ERR_CRC | RRD_ERR_ALIGN | 2442 RRD_ERR_TRUNC | RRD_ERR_RUNT)) != 0) 2443 return; 2444 } 2445 2446 for (count = 0; count < nsegs; count++, 2447 ALC_DESC_INC(rx_cons, ALC_RX_RING_CNT)) { 2448 rxd = &sc->alc_cdata.alc_rxdesc[rx_cons]; 2449 mp = rxd->rx_m; 2450 /* Add a new receive buffer to the ring. */ 2451 if (alc_newbuf(sc, rxd) != 0) { 2452 ifp->if_iqdrops++; 2453 /* Reuse Rx buffers. */ 2454 m_freem(sc->alc_cdata.alc_rxhead); 2455 break; 2456 } 2457 2458 /* 2459 * Assume we've received a full sized frame. 2460 * Actual size is fixed when we encounter the end of 2461 * multi-segmented frame. 2462 */ 2463 mp->m_len = sc->alc_buf_size; 2464 2465 /* Chain received mbufs. */ 2466 if (sc->alc_cdata.alc_rxhead == NULL) { 2467 sc->alc_cdata.alc_rxhead = mp; 2468 sc->alc_cdata.alc_rxtail = mp; 2469 } else { 2470 mp->m_flags &= ~M_PKTHDR; 2471 sc->alc_cdata.alc_rxprev_tail = 2472 sc->alc_cdata.alc_rxtail; 2473 sc->alc_cdata.alc_rxtail->m_next = mp; 2474 sc->alc_cdata.alc_rxtail = mp; 2475 } 2476 2477 if (count == nsegs - 1) { 2478 /* Last desc. for this frame. */ 2479 m = sc->alc_cdata.alc_rxhead; 2480 m->m_flags |= M_PKTHDR; 2481 /* 2482 * It seems that L1C/L2C controller has no way 2483 * to tell hardware to strip CRC bytes. 2484 */ 2485 m->m_pkthdr.len = 2486 sc->alc_cdata.alc_rxlen - ETHER_CRC_LEN; 2487 if (nsegs > 1) { 2488 /* Set last mbuf size. */ 2489 mp->m_len = sc->alc_cdata.alc_rxlen - 2490 (nsegs - 1) * sc->alc_buf_size; 2491 /* Remove the CRC bytes in chained mbufs. */ 2492 if (mp->m_len <= ETHER_CRC_LEN) { 2493 sc->alc_cdata.alc_rxtail = 2494 sc->alc_cdata.alc_rxprev_tail; 2495 sc->alc_cdata.alc_rxtail->m_len -= 2496 (ETHER_CRC_LEN - mp->m_len); 2497 sc->alc_cdata.alc_rxtail->m_next = NULL; 2498 m_freem(mp); 2499 } else { 2500 mp->m_len -= ETHER_CRC_LEN; 2501 } 2502 } else 2503 m->m_len = m->m_pkthdr.len; 2504 /* 2505 * Due to hardware bugs, Rx checksum offloading 2506 * was intentionally disabled. 2507 */ 2508 #if NVLAN > 0 2509 if (status & RRD_VLAN_TAG) { 2510 u_int32_t vtag = RRD_VLAN(letoh32(rrd->vtag)); 2511 m->m_pkthdr.ether_vtag = ntohs(vtag); 2512 m->m_flags |= M_VLANTAG; 2513 } 2514 #endif 2515 2516 2517 ml_enqueue(&ml, m); 2518 } 2519 } 2520 if_input(ifp, &ml); 2521 2522 /* Reset mbuf chains. */ 2523 ALC_RXCHAIN_RESET(sc); 2524 } 2525 2526 void 2527 alc_tick(void *xsc) 2528 { 2529 struct alc_softc *sc = xsc; 2530 struct mii_data *mii = &sc->sc_miibus; 2531 int s; 2532 2533 s = splnet(); 2534 mii_tick(mii); 2535 alc_stats_update(sc); 2536 2537 timeout_add_sec(&sc->alc_tick_ch, 1); 2538 splx(s); 2539 } 2540 2541 void 2542 alc_osc_reset(struct alc_softc *sc) 2543 { 2544 uint32_t reg; 2545 2546 reg = CSR_READ_4(sc, ALC_MISC3); 2547 reg &= ~MISC3_25M_BY_SW; 2548 reg |= MISC3_25M_NOTO_INTNL; 2549 CSR_WRITE_4(sc, ALC_MISC3, reg); 2550 reg = CSR_READ_4(sc, ALC_MISC); 2551 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0) { 2552 /* 2553 * Restore over-current protection default value. 2554 * This value could be reset by MAC reset. 2555 */ 2556 reg &= ~MISC_PSW_OCP_MASK; 2557 reg |= (MISC_PSW_OCP_DEFAULT << MISC_PSW_OCP_SHIFT); 2558 reg &= ~MISC_INTNLOSC_OPEN; 2559 CSR_WRITE_4(sc, ALC_MISC, reg); 2560 CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN); 2561 reg = CSR_READ_4(sc, ALC_MISC2); 2562 reg &= ~MISC2_CALB_START; 2563 CSR_WRITE_4(sc, ALC_MISC2, reg); 2564 CSR_WRITE_4(sc, ALC_MISC2, reg | MISC2_CALB_START); 2565 } else { 2566 reg &= ~MISC_INTNLOSC_OPEN; 2567 /* Disable isolate for revision A devices. */ 2568 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1) 2569 reg &= ~MISC_ISO_ENB; 2570 CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN); 2571 CSR_WRITE_4(sc, ALC_MISC, reg); 2572 } 2573 DELAY(20); 2574 } 2575 2576 void 2577 alc_reset(struct alc_softc *sc) 2578 { 2579 uint32_t reg, pmcfg = 0; 2580 int i; 2581 2582 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2583 /* Reset workaround. */ 2584 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 1); 2585 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 2586 (sc->alc_rev & 0x01) != 0) { 2587 /* Disable L0s/L1s before reset. */ 2588 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 2589 if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | 2590 PM_CFG_ASPM_L1_ENB))!= 0) { 2591 pmcfg &= ~(PM_CFG_ASPM_L0S_ENB | 2592 PM_CFG_ASPM_L1_ENB); 2593 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 2594 } 2595 } 2596 } 2597 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 2598 reg |= MASTER_OOB_DIS_OFF | MASTER_RESET; 2599 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 2600 2601 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2602 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 2603 DELAY(10); 2604 if (CSR_READ_4(sc, ALC_MBOX_RD0_PROD_IDX) == 0) 2605 break; 2606 } 2607 if (i == 0) 2608 printf("MAC reset timeout!\n"); 2609 } 2610 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 2611 DELAY(10); 2612 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0) 2613 break; 2614 } 2615 if (i == 0) 2616 printf("%s: master reset timeout!\n", sc->sc_dev.dv_xname); 2617 2618 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 2619 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 2620 if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC | 2621 IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 2622 break; 2623 DELAY(10); 2624 } 2625 2626 if (i == 0) 2627 printf("%s: reset timeout(0x%08x)!\n", sc->sc_dev.dv_xname, 2628 reg); 2629 2630 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2631 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 2632 (sc->alc_rev & 0x01) != 0) { 2633 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 2634 reg |= MASTER_CLK_SEL_DIS; 2635 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 2636 /* Restore L0s/L1s config. */ 2637 if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | 2638 PM_CFG_ASPM_L1_ENB)) != 0) 2639 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 2640 } 2641 alc_osc_reset(sc); 2642 reg = CSR_READ_4(sc, ALC_MISC3); 2643 reg &= ~MISC3_25M_BY_SW; 2644 reg |= MISC3_25M_NOTO_INTNL; 2645 CSR_WRITE_4(sc, ALC_MISC3, reg); 2646 reg = CSR_READ_4(sc, ALC_MISC); 2647 reg &= ~MISC_INTNLOSC_OPEN; 2648 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1) 2649 reg &= ~MISC_ISO_ENB; 2650 CSR_WRITE_4(sc, ALC_MISC, reg); 2651 DELAY(20); 2652 } 2653 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 2654 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1 || 2655 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_2) 2656 CSR_WRITE_4(sc, ALC_SERDES_LOCK, 2657 CSR_READ_4(sc, ALC_SERDES_LOCK) | 2658 SERDES_MAC_CLK_SLOWDOWN | SERDES_PHY_CLK_SLOWDOWN); 2659 } 2660 2661 int 2662 alc_init(struct ifnet *ifp) 2663 { 2664 struct alc_softc *sc = ifp->if_softc; 2665 uint8_t eaddr[ETHER_ADDR_LEN]; 2666 bus_addr_t paddr; 2667 uint32_t reg, rxf_hi, rxf_lo; 2668 int error; 2669 2670 /* 2671 * Cancel any pending I/O. 2672 */ 2673 alc_stop(sc); 2674 /* 2675 * Reset the chip to a known state. 2676 */ 2677 alc_reset(sc); 2678 2679 /* Initialize Rx descriptors. */ 2680 error = alc_init_rx_ring(sc); 2681 if (error != 0) { 2682 printf("%s: no memory for Rx buffers.\n", sc->sc_dev.dv_xname); 2683 alc_stop(sc); 2684 return (error); 2685 } 2686 alc_init_rr_ring(sc); 2687 alc_init_tx_ring(sc); 2688 alc_init_cmb(sc); 2689 alc_init_smb(sc); 2690 2691 /* Enable all clocks. */ 2692 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2693 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, CLK_GATING_DMAW_ENB | 2694 CLK_GATING_DMAR_ENB | CLK_GATING_TXQ_ENB | 2695 CLK_GATING_RXQ_ENB | CLK_GATING_TXMAC_ENB | 2696 CLK_GATING_RXMAC_ENB); 2697 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0) 2698 CSR_WRITE_4(sc, ALC_IDLE_DECISN_TIMER, 2699 IDLE_DECISN_TIMER_DEFAULT_1MS); 2700 } else 2701 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, 0); 2702 2703 /* Reprogram the station address. */ 2704 bcopy(LLADDR(ifp->if_sadl), eaddr, ETHER_ADDR_LEN); 2705 CSR_WRITE_4(sc, ALC_PAR0, 2706 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 2707 CSR_WRITE_4(sc, ALC_PAR1, eaddr[0] << 8 | eaddr[1]); 2708 /* 2709 * Clear WOL status and disable all WOL feature as WOL 2710 * would interfere Rx operation under normal environments. 2711 */ 2712 CSR_READ_4(sc, ALC_WOL_CFG); 2713 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 2714 /* Set Tx descriptor base addresses. */ 2715 paddr = sc->alc_rdata.alc_tx_ring_paddr; 2716 CSR_WRITE_4(sc, ALC_TX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 2717 CSR_WRITE_4(sc, ALC_TDL_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 2718 /* We don't use high priority ring. */ 2719 CSR_WRITE_4(sc, ALC_TDH_HEAD_ADDR_LO, 0); 2720 /* Set Tx descriptor counter. */ 2721 CSR_WRITE_4(sc, ALC_TD_RING_CNT, 2722 (ALC_TX_RING_CNT << TD_RING_CNT_SHIFT) & TD_RING_CNT_MASK); 2723 /* Set Rx descriptor base addresses. */ 2724 paddr = sc->alc_rdata.alc_rx_ring_paddr; 2725 CSR_WRITE_4(sc, ALC_RX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 2726 CSR_WRITE_4(sc, ALC_RD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 2727 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 2728 /* We use one Rx ring. */ 2729 CSR_WRITE_4(sc, ALC_RD1_HEAD_ADDR_LO, 0); 2730 CSR_WRITE_4(sc, ALC_RD2_HEAD_ADDR_LO, 0); 2731 CSR_WRITE_4(sc, ALC_RD3_HEAD_ADDR_LO, 0); 2732 } 2733 /* Set Rx descriptor counter. */ 2734 CSR_WRITE_4(sc, ALC_RD_RING_CNT, 2735 (ALC_RX_RING_CNT << RD_RING_CNT_SHIFT) & RD_RING_CNT_MASK); 2736 2737 /* 2738 * Let hardware split jumbo frames into alc_max_buf_sized chunks. 2739 * if it do not fit the buffer size. Rx return descriptor holds 2740 * a counter that indicates how many fragments were made by the 2741 * hardware. The buffer size should be multiple of 8 bytes. 2742 * Since hardware has limit on the size of buffer size, always 2743 * use the maximum value. 2744 * For strict-alignment architectures make sure to reduce buffer 2745 * size by 8 bytes to make room for alignment fixup. 2746 */ 2747 sc->alc_buf_size = RX_BUF_SIZE_MAX; 2748 CSR_WRITE_4(sc, ALC_RX_BUF_SIZE, sc->alc_buf_size); 2749 2750 paddr = sc->alc_rdata.alc_rr_ring_paddr; 2751 /* Set Rx return descriptor base addresses. */ 2752 CSR_WRITE_4(sc, ALC_RRD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 2753 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 2754 /* We use one Rx return ring. */ 2755 CSR_WRITE_4(sc, ALC_RRD1_HEAD_ADDR_LO, 0); 2756 CSR_WRITE_4(sc, ALC_RRD2_HEAD_ADDR_LO, 0); 2757 CSR_WRITE_4(sc, ALC_RRD3_HEAD_ADDR_LO, 0); 2758 } 2759 /* Set Rx return descriptor counter. */ 2760 CSR_WRITE_4(sc, ALC_RRD_RING_CNT, 2761 (ALC_RR_RING_CNT << RRD_RING_CNT_SHIFT) & RRD_RING_CNT_MASK); 2762 paddr = sc->alc_rdata.alc_cmb_paddr; 2763 CSR_WRITE_4(sc, ALC_CMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 2764 paddr = sc->alc_rdata.alc_smb_paddr; 2765 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 2766 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 2767 2768 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1) { 2769 /* Reconfigure SRAM - Vendor magic. */ 2770 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_LEN, 0x000002A0); 2771 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_LEN, 0x00000100); 2772 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_ADDR, 0x029F0000); 2773 CSR_WRITE_4(sc, ALC_SRAM_RD0_ADDR, 0x02BF02A0); 2774 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_ADDR, 0x03BF02C0); 2775 CSR_WRITE_4(sc, ALC_SRAM_TD_ADDR, 0x03DF03C0); 2776 CSR_WRITE_4(sc, ALC_TXF_WATER_MARK, 0x00000000); 2777 CSR_WRITE_4(sc, ALC_RD_DMA_CFG, 0x00000000); 2778 } 2779 2780 /* Tell hardware that we're ready to load DMA blocks. */ 2781 CSR_WRITE_4(sc, ALC_DMA_BLOCK, DMA_BLOCK_LOAD); 2782 2783 /* Configure interrupt moderation timer. */ 2784 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 2785 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 2786 reg = ALC_USECS(sc->alc_int_rx_mod) << IM_TIMER_RX_SHIFT; 2787 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) 2788 reg |= ALC_USECS(sc->alc_int_tx_mod) << IM_TIMER_TX_SHIFT; 2789 CSR_WRITE_4(sc, ALC_IM_TIMER, reg); 2790 /* 2791 * We don't want to automatic interrupt clear as task queue 2792 * for the interrupt should know interrupt status. 2793 */ 2794 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 2795 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); 2796 reg |= MASTER_SA_TIMER_ENB; 2797 if (ALC_USECS(sc->alc_int_rx_mod) != 0) 2798 reg |= MASTER_IM_RX_TIMER_ENB; 2799 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0 && 2800 ALC_USECS(sc->alc_int_tx_mod) != 0) 2801 reg |= MASTER_IM_TX_TIMER_ENB; 2802 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 2803 /* 2804 * Disable interrupt re-trigger timer. We don't want automatic 2805 * re-triggering of un-ACKed interrupts. 2806 */ 2807 CSR_WRITE_4(sc, ALC_INTR_RETRIG_TIMER, ALC_USECS(0)); 2808 /* Configure CMB. */ 2809 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2810 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, ALC_TX_RING_CNT / 3); 2811 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, 2812 ALC_USECS(sc->alc_int_tx_mod)); 2813 } else { 2814 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 2815 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, 4); 2816 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(5000)); 2817 } else 2818 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(0)); 2819 } 2820 /* 2821 * Hardware can be configured to issue SMB interrupt based 2822 * on programmed interval. Since there is a callout that is 2823 * invoked for every hz in driver we use that instead of 2824 * relying on periodic SMB interrupt. 2825 */ 2826 CSR_WRITE_4(sc, ALC_SMB_STAT_TIMER, ALC_USECS(0)); 2827 /* Clear MAC statistics. */ 2828 alc_stats_clear(sc); 2829 2830 /* 2831 * Always use maximum frame size that controller can support. 2832 * Otherwise received frames that has larger frame length 2833 * than alc(4) MTU would be silently dropped in hardware. This 2834 * would make path-MTU discovery hard as sender wouldn't get 2835 * any responses from receiver. alc(4) supports 2836 * multi-fragmented frames on Rx path so it has no issue on 2837 * assembling fragmented frames. Using maximum frame size also 2838 * removes the need to reinitialize hardware when interface 2839 * MTU configuration was changed. 2840 * 2841 * Be conservative in what you do, be liberal in what you 2842 * accept from others - RFC 793. 2843 */ 2844 CSR_WRITE_4(sc, ALC_FRAME_SIZE, sc->alc_max_framelen); 2845 2846 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 2847 /* Disable header split(?) */ 2848 CSR_WRITE_4(sc, ALC_HDS_CFG, 0); 2849 /* Configure IPG/IFG parameters. */ 2850 CSR_WRITE_4(sc, ALC_IPG_IFG_CFG, 2851 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & 2852 IPG_IFG_IPGT_MASK) | 2853 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & 2854 IPG_IFG_MIFG_MASK) | 2855 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & 2856 IPG_IFG_IPG1_MASK) | 2857 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & 2858 IPG_IFG_IPG2_MASK)); 2859 /* Set parameters for half-duplex media. */ 2860 CSR_WRITE_4(sc, ALC_HDPX_CFG, 2861 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 2862 HDPX_CFG_LCOL_MASK) | 2863 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 2864 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 2865 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 2866 HDPX_CFG_ABEBT_MASK) | 2867 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 2868 HDPX_CFG_JAMIPG_MASK)); 2869 } 2870 2871 /* 2872 * Set TSO/checksum offload threshold. For frames that is 2873 * larger than this threshold, hardware wouldn't do 2874 * TSO/checksum offloading. 2875 */ 2876 reg = (sc->alc_max_framelen >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) & 2877 TSO_OFFLOAD_THRESH_MASK; 2878 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 2879 reg |= TSO_OFFLOAD_ERRLGPKT_DROP_ENB; 2880 CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH, reg); 2881 /* Configure TxQ. */ 2882 reg = (alc_dma_burst[sc->alc_dma_rd_burst] << 2883 TXQ_CFG_TX_FIFO_BURST_SHIFT) & TXQ_CFG_TX_FIFO_BURST_MASK; 2884 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1 || 2885 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_2) 2886 reg >>= 1; 2887 reg |= (TXQ_CFG_TD_BURST_DEFAULT << TXQ_CFG_TD_BURST_SHIFT) & 2888 TXQ_CFG_TD_BURST_MASK; 2889 reg |= TXQ_CFG_IP_OPTION_ENB | TXQ_CFG_8023_ENB; 2890 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE); 2891 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2892 reg = (TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q1_BURST_SHIFT | 2893 TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q2_BURST_SHIFT | 2894 TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q3_BURST_SHIFT | 2895 HQTD_CFG_BURST_ENB); 2896 CSR_WRITE_4(sc, ALC_HQTD_CFG, reg); 2897 reg = WRR_PRI_RESTRICT_NONE; 2898 reg |= (WRR_PRI_DEFAULT << WRR_PRI0_SHIFT | 2899 WRR_PRI_DEFAULT << WRR_PRI1_SHIFT | 2900 WRR_PRI_DEFAULT << WRR_PRI2_SHIFT | 2901 WRR_PRI_DEFAULT << WRR_PRI3_SHIFT); 2902 CSR_WRITE_4(sc, ALC_WRR, reg); 2903 } else { 2904 /* Configure Rx free descriptor pre-fetching. */ 2905 CSR_WRITE_4(sc, ALC_RX_RD_FREE_THRESH, 2906 ((RX_RD_FREE_THRESH_HI_DEFAULT << 2907 RX_RD_FREE_THRESH_HI_SHIFT) & RX_RD_FREE_THRESH_HI_MASK) | 2908 ((RX_RD_FREE_THRESH_LO_DEFAULT << 2909 RX_RD_FREE_THRESH_LO_SHIFT) & RX_RD_FREE_THRESH_LO_MASK)); 2910 } 2911 2912 /* 2913 * Configure flow control parameters. 2914 * XON : 80% of Rx FIFO 2915 * XOFF : 30% of Rx FIFO 2916 */ 2917 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2918 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 2919 reg &= SRAM_RX_FIFO_LEN_MASK; 2920 reg *= 8; 2921 if (reg > 8 * 1024) 2922 reg -= RX_FIFO_PAUSE_816X_RSVD; 2923 else 2924 reg -= RX_BUF_SIZE_MAX; 2925 reg /= 8; 2926 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 2927 ((reg << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 2928 RX_FIFO_PAUSE_THRESH_LO_MASK) | 2929 (((RX_FIFO_PAUSE_816X_RSVD / 8) << 2930 RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 2931 RX_FIFO_PAUSE_THRESH_HI_MASK)); 2932 } else if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1C|| 2933 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C) { 2934 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 2935 rxf_hi = (reg * 8) / 10; 2936 rxf_lo = (reg * 3) / 10; 2937 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 2938 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 2939 RX_FIFO_PAUSE_THRESH_LO_MASK) | 2940 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 2941 RX_FIFO_PAUSE_THRESH_HI_MASK)); 2942 } 2943 2944 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 2945 /* Disable RSS until I understand L1C/L2C's RSS logic. */ 2946 CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0); 2947 CSR_WRITE_4(sc, ALC_RSS_CPU, 0); 2948 } 2949 2950 /* Configure RxQ. */ 2951 reg = (RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 2952 RXQ_CFG_RD_BURST_MASK; 2953 reg |= RXQ_CFG_RSS_MODE_DIS; 2954 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2955 reg |= (RXQ_CFG_816X_IDT_TBL_SIZE_DEFAULT << 2956 RXQ_CFG_816X_IDT_TBL_SIZE_SHIFT) & 2957 RXQ_CFG_816X_IDT_TBL_SIZE_MASK; 2958 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 2959 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M; 2960 } else { 2961 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0 && 2962 sc->sc_product != PCI_PRODUCT_ATTANSIC_L1D_1) 2963 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M; 2964 } 2965 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 2966 2967 /* Configure DMA parameters. */ 2968 reg = DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI; 2969 reg |= sc->alc_rcb; 2970 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 2971 reg |= DMA_CFG_CMB_ENB; 2972 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) 2973 reg |= DMA_CFG_SMB_ENB; 2974 else 2975 reg |= DMA_CFG_SMB_DIS; 2976 reg |= (sc->alc_dma_rd_burst & DMA_CFG_RD_BURST_MASK) << 2977 DMA_CFG_RD_BURST_SHIFT; 2978 reg |= (sc->alc_dma_wr_burst & DMA_CFG_WR_BURST_MASK) << 2979 DMA_CFG_WR_BURST_SHIFT; 2980 reg |= (DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 2981 DMA_CFG_RD_DELAY_CNT_MASK; 2982 reg |= (DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 2983 DMA_CFG_WR_DELAY_CNT_MASK; 2984 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2985 switch (AR816X_REV(sc->alc_rev)) { 2986 case AR816X_REV_A0: 2987 case AR816X_REV_A1: 2988 reg |= DMA_CFG_RD_CHNL_SEL_2; 2989 break; 2990 case AR816X_REV_B0: 2991 /* FALLTHROUGH */ 2992 default: 2993 reg |= DMA_CFG_RD_CHNL_SEL_4; 2994 break; 2995 } 2996 } 2997 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 2998 2999 /* 3000 * Configure Tx/Rx MACs. 3001 * - Auto-padding for short frames. 3002 * - Enable CRC generation. 3003 * Actual reconfiguration of MAC for resolved speed/duplex 3004 * is followed after detection of link establishment. 3005 * AR813x/AR815x always does checksum computation regardless 3006 * of MAC_CFG_RXCSUM_ENB bit. Also the controller is known to 3007 * have bug in protocol field in Rx return structure so 3008 * these controllers can't handle fragmented frames. Disable 3009 * Rx checksum offloading until there is a newer controller 3010 * that has sane implementation. 3011 */ 3012 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 3013 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 3014 MAC_CFG_PREAMBLE_MASK); 3015 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 3016 sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D || 3017 sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D_1 || 3018 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_2) 3019 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 3020 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0) 3021 reg |= MAC_CFG_SPEED_10_100; 3022 else 3023 reg |= MAC_CFG_SPEED_1000; 3024 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3025 3026 /* Set up the receive filter. */ 3027 alc_iff(sc); 3028 3029 alc_rxvlan(sc); 3030 3031 /* Acknowledge all pending interrupts and clear it. */ 3032 CSR_WRITE_4(sc, ALC_INTR_MASK, ALC_INTRS); 3033 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3034 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0); 3035 3036 ifp->if_flags |= IFF_RUNNING; 3037 ifq_clr_oactive(&ifp->if_snd); 3038 3039 sc->alc_flags &= ~ALC_FLAG_LINK; 3040 /* Switch to the current media. */ 3041 alc_mediachange(ifp); 3042 3043 timeout_add_sec(&sc->alc_tick_ch, 1); 3044 3045 return (0); 3046 } 3047 3048 void 3049 alc_stop(struct alc_softc *sc) 3050 { 3051 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 3052 struct alc_txdesc *txd; 3053 struct alc_rxdesc *rxd; 3054 uint32_t reg; 3055 int i; 3056 3057 /* 3058 * Mark the interface down and cancel the watchdog timer. 3059 */ 3060 ifp->if_flags &= ~IFF_RUNNING; 3061 ifq_clr_oactive(&ifp->if_snd); 3062 ifp->if_timer = 0; 3063 3064 timeout_del(&sc->alc_tick_ch); 3065 sc->alc_flags &= ~ALC_FLAG_LINK; 3066 3067 alc_stats_update(sc); 3068 3069 /* Disable interrupts. */ 3070 CSR_WRITE_4(sc, ALC_INTR_MASK, 0); 3071 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3072 3073 /* Disable DMA. */ 3074 reg = CSR_READ_4(sc, ALC_DMA_CFG); 3075 reg &= ~(DMA_CFG_CMB_ENB | DMA_CFG_SMB_ENB); 3076 reg |= DMA_CFG_SMB_DIS; 3077 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 3078 DELAY(1000); 3079 3080 /* Stop Rx/Tx MACs. */ 3081 alc_stop_mac(sc); 3082 3083 /* Disable interrupts which might be touched in taskq handler. */ 3084 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3085 3086 /* Disable L0s/L1s */ 3087 reg = CSR_READ_4(sc, ALC_PM_CFG); 3088 if ((reg & (PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB))!= 0) { 3089 reg &= ~(PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB); 3090 CSR_WRITE_4(sc, ALC_PM_CFG, reg); 3091 } 3092 3093 /* Reclaim Rx buffers that have been processed. */ 3094 m_freem(sc->alc_cdata.alc_rxhead); 3095 ALC_RXCHAIN_RESET(sc); 3096 /* 3097 * Free Tx/Rx mbufs still in the queues. 3098 */ 3099 for (i = 0; i < ALC_RX_RING_CNT; i++) { 3100 rxd = &sc->alc_cdata.alc_rxdesc[i]; 3101 if (rxd->rx_m != NULL) { 3102 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0, 3103 rxd->rx_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 3104 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 3105 m_freem(rxd->rx_m); 3106 rxd->rx_m = NULL; 3107 } 3108 } 3109 for (i = 0; i < ALC_TX_RING_CNT; i++) { 3110 txd = &sc->alc_cdata.alc_txdesc[i]; 3111 if (txd->tx_m != NULL) { 3112 bus_dmamap_sync(sc->sc_dmat, txd->tx_dmamap, 0, 3113 txd->tx_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 3114 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 3115 m_freem(txd->tx_m); 3116 txd->tx_m = NULL; 3117 } 3118 } 3119 } 3120 3121 void 3122 alc_stop_mac(struct alc_softc *sc) 3123 { 3124 uint32_t reg; 3125 int i; 3126 3127 alc_stop_queue(sc); 3128 /* Disable Rx/Tx MAC. */ 3129 reg = CSR_READ_4(sc, ALC_MAC_CFG); 3130 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 3131 reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 3132 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3133 } 3134 for (i = ALC_TIMEOUT; i > 0; i--) { 3135 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 3136 if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC)) == 0) 3137 break; 3138 DELAY(10); 3139 } 3140 if (i == 0) 3141 printf("%s: could not disable Rx/Tx MAC(0x%08x)!\n", 3142 sc->sc_dev.dv_xname, reg); 3143 } 3144 3145 void 3146 alc_start_queue(struct alc_softc *sc) 3147 { 3148 uint32_t qcfg[] = { 3149 0, 3150 RXQ_CFG_QUEUE0_ENB, 3151 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB, 3152 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | RXQ_CFG_QUEUE2_ENB, 3153 RXQ_CFG_ENB 3154 }; 3155 uint32_t cfg; 3156 3157 /* Enable RxQ. */ 3158 cfg = CSR_READ_4(sc, ALC_RXQ_CFG); 3159 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 3160 cfg &= ~RXQ_CFG_ENB; 3161 cfg |= qcfg[1]; 3162 } else 3163 cfg |= RXQ_CFG_QUEUE0_ENB; 3164 3165 CSR_WRITE_4(sc, ALC_RXQ_CFG, cfg); 3166 /* Enable TxQ. */ 3167 cfg = CSR_READ_4(sc, ALC_TXQ_CFG); 3168 cfg |= TXQ_CFG_ENB; 3169 CSR_WRITE_4(sc, ALC_TXQ_CFG, cfg); 3170 } 3171 3172 void 3173 alc_stop_queue(struct alc_softc *sc) 3174 { 3175 uint32_t reg; 3176 int i; 3177 3178 /* Disable RxQ. */ 3179 reg = CSR_READ_4(sc, ALC_RXQ_CFG); 3180 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 3181 if ((reg & RXQ_CFG_ENB) != 0) { 3182 reg &= ~RXQ_CFG_ENB; 3183 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 3184 } 3185 } else { 3186 if ((reg & RXQ_CFG_QUEUE0_ENB) != 0) { 3187 reg &= ~RXQ_CFG_QUEUE0_ENB; 3188 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 3189 } 3190 } 3191 /* Disable TxQ. */ 3192 reg = CSR_READ_4(sc, ALC_TXQ_CFG); 3193 if ((reg & TXQ_CFG_ENB) != 0) { 3194 reg &= ~TXQ_CFG_ENB; 3195 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg); 3196 } 3197 DELAY(40); 3198 for (i = ALC_TIMEOUT; i > 0; i--) { 3199 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 3200 if ((reg & (IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 3201 break; 3202 DELAY(10); 3203 } 3204 if (i == 0) 3205 printf("%s: could not disable RxQ/TxQ (0x%08x)!\n", 3206 sc->sc_dev.dv_xname, reg); 3207 } 3208 3209 void 3210 alc_init_tx_ring(struct alc_softc *sc) 3211 { 3212 struct alc_ring_data *rd; 3213 struct alc_txdesc *txd; 3214 int i; 3215 3216 sc->alc_cdata.alc_tx_prod = 0; 3217 sc->alc_cdata.alc_tx_cons = 0; 3218 sc->alc_cdata.alc_tx_cnt = 0; 3219 3220 rd = &sc->alc_rdata; 3221 bzero(rd->alc_tx_ring, ALC_TX_RING_SZ); 3222 for (i = 0; i < ALC_TX_RING_CNT; i++) { 3223 txd = &sc->alc_cdata.alc_txdesc[i]; 3224 txd->tx_m = NULL; 3225 } 3226 3227 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0, 3228 sc->alc_cdata.alc_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 3229 } 3230 3231 int 3232 alc_init_rx_ring(struct alc_softc *sc) 3233 { 3234 struct alc_ring_data *rd; 3235 struct alc_rxdesc *rxd; 3236 int i; 3237 3238 sc->alc_cdata.alc_rx_cons = ALC_RX_RING_CNT - 1; 3239 rd = &sc->alc_rdata; 3240 bzero(rd->alc_rx_ring, ALC_RX_RING_SZ); 3241 for (i = 0; i < ALC_RX_RING_CNT; i++) { 3242 rxd = &sc->alc_cdata.alc_rxdesc[i]; 3243 rxd->rx_m = NULL; 3244 rxd->rx_desc = &rd->alc_rx_ring[i]; 3245 if (alc_newbuf(sc, rxd) != 0) 3246 return (ENOBUFS); 3247 } 3248 3249 /* 3250 * Since controller does not update Rx descriptors, driver 3251 * does have to read Rx descriptors back so BUS_DMASYNC_PREWRITE 3252 * is enough to ensure coherence. 3253 */ 3254 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 0, 3255 sc->alc_cdata.alc_rx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 3256 /* Let controller know availability of new Rx buffers. */ 3257 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, sc->alc_cdata.alc_rx_cons); 3258 3259 return (0); 3260 } 3261 3262 void 3263 alc_init_rr_ring(struct alc_softc *sc) 3264 { 3265 struct alc_ring_data *rd; 3266 3267 sc->alc_cdata.alc_rr_cons = 0; 3268 ALC_RXCHAIN_RESET(sc); 3269 3270 rd = &sc->alc_rdata; 3271 bzero(rd->alc_rr_ring, ALC_RR_RING_SZ); 3272 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 0, 3273 sc->alc_cdata.alc_rr_ring_map->dm_mapsize, 3274 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3275 } 3276 3277 void 3278 alc_init_cmb(struct alc_softc *sc) 3279 { 3280 struct alc_ring_data *rd; 3281 3282 rd = &sc->alc_rdata; 3283 bzero(rd->alc_cmb, ALC_CMB_SZ); 3284 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0, 3285 sc->alc_cdata.alc_cmb_map->dm_mapsize, 3286 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3287 } 3288 3289 void 3290 alc_init_smb(struct alc_softc *sc) 3291 { 3292 struct alc_ring_data *rd; 3293 3294 rd = &sc->alc_rdata; 3295 bzero(rd->alc_smb, ALC_SMB_SZ); 3296 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 3297 sc->alc_cdata.alc_smb_map->dm_mapsize, 3298 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3299 } 3300 3301 void 3302 alc_rxvlan(struct alc_softc *sc) 3303 { 3304 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 3305 uint32_t reg; 3306 3307 reg = CSR_READ_4(sc, ALC_MAC_CFG); 3308 if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) 3309 reg |= MAC_CFG_VLAN_TAG_STRIP; 3310 else 3311 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 3312 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3313 } 3314 3315 void 3316 alc_iff(struct alc_softc *sc) 3317 { 3318 struct arpcom *ac = &sc->sc_arpcom; 3319 struct ifnet *ifp = &ac->ac_if; 3320 struct ether_multi *enm; 3321 struct ether_multistep step; 3322 uint32_t crc; 3323 uint32_t mchash[2]; 3324 uint32_t rxcfg; 3325 3326 rxcfg = CSR_READ_4(sc, ALC_MAC_CFG); 3327 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 3328 ifp->if_flags &= ~IFF_ALLMULTI; 3329 3330 /* 3331 * Always accept broadcast frames. 3332 */ 3333 rxcfg |= MAC_CFG_BCAST; 3334 3335 if (ifp->if_flags & IFF_PROMISC || ac->ac_multirangecnt > 0) { 3336 ifp->if_flags |= IFF_ALLMULTI; 3337 if (ifp->if_flags & IFF_PROMISC) 3338 rxcfg |= MAC_CFG_PROMISC; 3339 else 3340 rxcfg |= MAC_CFG_ALLMULTI; 3341 mchash[0] = mchash[1] = 0xFFFFFFFF; 3342 } else { 3343 /* Program new filter. */ 3344 bzero(mchash, sizeof(mchash)); 3345 3346 ETHER_FIRST_MULTI(step, ac, enm); 3347 while (enm != NULL) { 3348 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3349 3350 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 3351 3352 ETHER_NEXT_MULTI(step, enm); 3353 } 3354 } 3355 3356 CSR_WRITE_4(sc, ALC_MAR0, mchash[0]); 3357 CSR_WRITE_4(sc, ALC_MAR1, mchash[1]); 3358 CSR_WRITE_4(sc, ALC_MAC_CFG, rxcfg); 3359 } 3360