1 /* $OpenBSD: if_alc.c,v 1.21 2011/10/19 05:23:44 kevlo Exp $ */ 2 /*- 3 * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* Driver for Atheros AR8131/AR8132 PCIe Ethernet. */ 30 31 #include "bpfilter.h" 32 #include "vlan.h" 33 34 #include <sys/param.h> 35 #include <sys/endian.h> 36 #include <sys/systm.h> 37 #include <sys/types.h> 38 #include <sys/sockio.h> 39 #include <sys/mbuf.h> 40 #include <sys/queue.h> 41 #include <sys/kernel.h> 42 #include <sys/device.h> 43 #include <sys/timeout.h> 44 #include <sys/socket.h> 45 46 #include <machine/bus.h> 47 48 #include <net/if.h> 49 #include <net/if_dl.h> 50 #include <net/if_llc.h> 51 #include <net/if_media.h> 52 53 #ifdef INET 54 #include <netinet/in.h> 55 #include <netinet/in_systm.h> 56 #include <netinet/in_var.h> 57 #include <netinet/ip.h> 58 #include <netinet/if_ether.h> 59 #endif 60 61 #include <net/if_types.h> 62 #include <net/if_vlan_var.h> 63 64 #if NBPFILTER > 0 65 #include <net/bpf.h> 66 #endif 67 68 #include <dev/rndvar.h> 69 70 #include <dev/mii/mii.h> 71 #include <dev/mii/miivar.h> 72 73 #include <dev/pci/pcireg.h> 74 #include <dev/pci/pcivar.h> 75 #include <dev/pci/pcidevs.h> 76 77 #include <dev/pci/if_alcreg.h> 78 79 int alc_match(struct device *, void *, void *); 80 void alc_attach(struct device *, struct device *, void *); 81 int alc_detach(struct device *, int); 82 int alc_activate(struct device *, int); 83 84 int alc_init(struct ifnet *); 85 void alc_start(struct ifnet *); 86 int alc_ioctl(struct ifnet *, u_long, caddr_t); 87 void alc_watchdog(struct ifnet *); 88 int alc_mediachange(struct ifnet *); 89 void alc_mediastatus(struct ifnet *, struct ifmediareq *); 90 91 void alc_aspm(struct alc_softc *, int); 92 void alc_disable_l0s_l1(struct alc_softc *); 93 int alc_dma_alloc(struct alc_softc *); 94 void alc_dma_free(struct alc_softc *); 95 int alc_encap(struct alc_softc *, struct mbuf **); 96 void alc_get_macaddr(struct alc_softc *); 97 void alc_init_cmb(struct alc_softc *); 98 void alc_init_rr_ring(struct alc_softc *); 99 int alc_init_rx_ring(struct alc_softc *); 100 void alc_init_smb(struct alc_softc *); 101 void alc_init_tx_ring(struct alc_softc *); 102 int alc_intr(void *); 103 void alc_mac_config(struct alc_softc *); 104 int alc_miibus_readreg(struct device *, int, int); 105 void alc_miibus_statchg(struct device *); 106 void alc_miibus_writereg(struct device *, int, int, int); 107 int alc_newbuf(struct alc_softc *, struct alc_rxdesc *); 108 void alc_phy_down(struct alc_softc *); 109 void alc_phy_reset(struct alc_softc *); 110 void alc_reset(struct alc_softc *); 111 void alc_rxeof(struct alc_softc *, struct rx_rdesc *); 112 void alc_rxintr(struct alc_softc *); 113 void alc_iff(struct alc_softc *); 114 void alc_rxvlan(struct alc_softc *); 115 void alc_start_queue(struct alc_softc *); 116 void alc_stats_clear(struct alc_softc *); 117 void alc_stats_update(struct alc_softc *); 118 void alc_stop(struct alc_softc *); 119 void alc_stop_mac(struct alc_softc *); 120 void alc_stop_queue(struct alc_softc *); 121 void alc_tick(void *); 122 void alc_txeof(struct alc_softc *); 123 124 uint32_t alc_dma_burst[] = { 128, 256, 512, 1024, 2048, 4096, 0 }; 125 126 const struct pci_matchid alc_devices[] = { 127 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L1C }, 128 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L2C }, 129 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L1D }, 130 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L1D_1 }, 131 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L2C_1 }, 132 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L2C_2 } 133 }; 134 135 struct cfattach alc_ca = { 136 sizeof (struct alc_softc), alc_match, alc_attach, NULL, 137 alc_activate 138 }; 139 140 struct cfdriver alc_cd = { 141 NULL, "alc", DV_IFNET 142 }; 143 144 int alcdebug = 0; 145 #define DPRINTF(x) do { if (alcdebug) printf x; } while (0) 146 147 #define ALC_CSUM_FEATURES (M_TCP_CSUM_OUT | M_UDP_CSUM_OUT) 148 149 int 150 alc_miibus_readreg(struct device *dev, int phy, int reg) 151 { 152 struct alc_softc *sc = (struct alc_softc *)dev; 153 uint32_t v; 154 int i; 155 156 if (phy != sc->alc_phyaddr) 157 return (0); 158 159 /* 160 * For AR8132 fast ethernet controller, do not report 1000baseT 161 * capability to mii(4). Even though AR8132 uses the same 162 * model/revision number of F1 gigabit PHY, the PHY has no 163 * ability to establish 1000baseT link. 164 */ 165 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0 && 166 reg == MII_EXTSR) 167 return (0); 168 169 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 170 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 171 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 172 DELAY(5); 173 v = CSR_READ_4(sc, ALC_MDIO); 174 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 175 break; 176 } 177 178 if (i == 0) { 179 printf("%s: phy read timeout: phy %d, reg %d\n", 180 sc->sc_dev.dv_xname, phy, reg); 181 return (0); 182 } 183 184 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 185 } 186 187 void 188 alc_miibus_writereg(struct device *dev, int phy, int reg, int val) 189 { 190 struct alc_softc *sc = (struct alc_softc *)dev; 191 uint32_t v; 192 int i; 193 194 if (phy != sc->alc_phyaddr) 195 return; 196 197 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 198 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 199 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 200 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 201 DELAY(5); 202 v = CSR_READ_4(sc, ALC_MDIO); 203 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 204 break; 205 } 206 207 if (i == 0) 208 printf("%s: phy write timeout: phy %d, reg %d\n", 209 sc->sc_dev.dv_xname, phy, reg); 210 } 211 212 void 213 alc_miibus_statchg(struct device *dev) 214 { 215 struct alc_softc *sc = (struct alc_softc *)dev; 216 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 217 struct mii_data *mii = &sc->sc_miibus; 218 uint32_t reg; 219 220 if ((ifp->if_flags & IFF_RUNNING) == 0) 221 return; 222 223 sc->alc_flags &= ~ALC_FLAG_LINK; 224 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 225 (IFM_ACTIVE | IFM_AVALID)) { 226 switch (IFM_SUBTYPE(mii->mii_media_active)) { 227 case IFM_10_T: 228 case IFM_100_TX: 229 sc->alc_flags |= ALC_FLAG_LINK; 230 break; 231 case IFM_1000_T: 232 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 233 sc->alc_flags |= ALC_FLAG_LINK; 234 break; 235 default: 236 break; 237 } 238 } 239 alc_stop_queue(sc); 240 /* Stop Rx/Tx MACs. */ 241 alc_stop_mac(sc); 242 243 /* Program MACs with resolved speed/duplex/flow-control. */ 244 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 245 alc_start_queue(sc); 246 alc_mac_config(sc); 247 /* Re-enable Tx/Rx MACs. */ 248 reg = CSR_READ_4(sc, ALC_MAC_CFG); 249 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 250 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 251 alc_aspm(sc, IFM_SUBTYPE(mii->mii_media_active)); 252 } 253 } 254 255 void 256 alc_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 257 { 258 struct alc_softc *sc = ifp->if_softc; 259 struct mii_data *mii = &sc->sc_miibus; 260 261 if ((ifp->if_flags & IFF_UP) == 0) 262 return; 263 264 mii_pollstat(mii); 265 ifmr->ifm_status = mii->mii_media_status; 266 ifmr->ifm_active = mii->mii_media_active; 267 } 268 269 int 270 alc_mediachange(struct ifnet *ifp) 271 { 272 struct alc_softc *sc = ifp->if_softc; 273 struct mii_data *mii = &sc->sc_miibus; 274 int error; 275 276 if (mii->mii_instance != 0) { 277 struct mii_softc *miisc; 278 279 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 280 mii_phy_reset(miisc); 281 } 282 error = mii_mediachg(mii); 283 284 return (error); 285 } 286 287 int 288 alc_match(struct device *dev, void *match, void *aux) 289 { 290 return pci_matchbyid((struct pci_attach_args *)aux, alc_devices, 291 nitems(alc_devices)); 292 } 293 294 void 295 alc_get_macaddr(struct alc_softc *sc) 296 { 297 uint32_t ea[2], opt; 298 uint16_t val; 299 int eeprom, i; 300 301 eeprom = 0; 302 opt = CSR_READ_4(sc, ALC_OPT_CFG); 303 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 && 304 (CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) { 305 /* 306 * EEPROM found, let TWSI reload EEPROM configuration. 307 * This will set ethernet address of controller. 308 */ 309 eeprom++; 310 switch (sc->sc_product) { 311 case PCI_PRODUCT_ATTANSIC_L1C: 312 case PCI_PRODUCT_ATTANSIC_L2C: 313 if ((opt & OPT_CFG_CLK_ENB) == 0) { 314 opt |= OPT_CFG_CLK_ENB; 315 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 316 CSR_READ_4(sc, ALC_OPT_CFG); 317 DELAY(1000); 318 } 319 break; 320 case PCI_PRODUCT_ATTANSIC_L1D: 321 case PCI_PRODUCT_ATTANSIC_L1D_1: 322 case PCI_PRODUCT_ATTANSIC_L2C_1: 323 case PCI_PRODUCT_ATTANSIC_L2C_2: 324 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 325 ALC_MII_DBG_ADDR, 0x00); 326 val = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr, 327 ALC_MII_DBG_DATA); 328 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 329 ALC_MII_DBG_DATA, val & 0xFF7F); 330 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 331 ALC_MII_DBG_ADDR, 0x3B); 332 val = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr, 333 ALC_MII_DBG_DATA); 334 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 335 ALC_MII_DBG_DATA, val | 0x0008); 336 DELAY(20); 337 break; 338 } 339 340 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 341 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 342 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 343 CSR_READ_4(sc, ALC_WOL_CFG); 344 345 CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) | 346 TWSI_CFG_SW_LD_START); 347 for (i = 100; i > 0; i--) { 348 DELAY(1000); 349 if ((CSR_READ_4(sc, ALC_TWSI_CFG) & 350 TWSI_CFG_SW_LD_START) == 0) 351 break; 352 } 353 if (i == 0) 354 printf("%s: reloading EEPROM timeout!\n", 355 sc->sc_dev.dv_xname); 356 } else { 357 if (alcdebug) 358 printf("%s: EEPROM not found!\n", sc->sc_dev.dv_xname); 359 } 360 if (eeprom != 0) { 361 switch (sc->sc_product) { 362 case PCI_PRODUCT_ATTANSIC_L1C: 363 case PCI_PRODUCT_ATTANSIC_L2C: 364 if ((opt & OPT_CFG_CLK_ENB) != 0) { 365 opt &= ~OPT_CFG_CLK_ENB; 366 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 367 CSR_READ_4(sc, ALC_OPT_CFG); 368 DELAY(1000); 369 } 370 break; 371 case PCI_PRODUCT_ATTANSIC_L1D: 372 case PCI_PRODUCT_ATTANSIC_L1D_1: 373 case PCI_PRODUCT_ATTANSIC_L2C_1: 374 case PCI_PRODUCT_ATTANSIC_L2C_2: 375 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 376 ALC_MII_DBG_ADDR, 0x00); 377 val = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr, 378 ALC_MII_DBG_DATA); 379 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 380 ALC_MII_DBG_DATA, val | 0x0080); 381 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 382 ALC_MII_DBG_ADDR, 0x3B); 383 val = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr, 384 ALC_MII_DBG_DATA); 385 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 386 ALC_MII_DBG_DATA, val & 0xFFF7); 387 DELAY(20); 388 break; 389 } 390 } 391 392 ea[0] = CSR_READ_4(sc, ALC_PAR0); 393 ea[1] = CSR_READ_4(sc, ALC_PAR1); 394 sc->alc_eaddr[0] = (ea[1] >> 8) & 0xFF; 395 sc->alc_eaddr[1] = (ea[1] >> 0) & 0xFF; 396 sc->alc_eaddr[2] = (ea[0] >> 24) & 0xFF; 397 sc->alc_eaddr[3] = (ea[0] >> 16) & 0xFF; 398 sc->alc_eaddr[4] = (ea[0] >> 8) & 0xFF; 399 sc->alc_eaddr[5] = (ea[0] >> 0) & 0xFF; 400 } 401 402 void 403 alc_disable_l0s_l1(struct alc_softc *sc) 404 { 405 uint32_t pmcfg; 406 407 /* Another magic from vendor. */ 408 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 409 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_CLK_SWH_L1 | 410 PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | PM_CFG_MAC_ASPM_CHK | 411 PM_CFG_SERDES_PD_EX_L1); 412 pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB | 413 PM_CFG_SERDES_L1_ENB; 414 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 415 } 416 417 void 418 alc_phy_reset(struct alc_softc *sc) 419 { 420 uint16_t data; 421 422 /* Reset magic from Linux. */ 423 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_SEL_ANA_RESET); 424 CSR_READ_2(sc, ALC_GPHY_CFG); 425 DELAY(10 * 1000); 426 427 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | 428 GPHY_CFG_SEL_ANA_RESET); 429 CSR_READ_2(sc, ALC_GPHY_CFG); 430 DELAY(10 * 1000); 431 432 /* DSP fixup, Vendor magic. */ 433 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1) { 434 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 435 ALC_MII_DBG_ADDR, 0x000A); 436 data = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr, 437 ALC_MII_DBG_DATA); 438 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 439 ALC_MII_DBG_DATA, data & 0xDFFF); 440 } 441 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D || 442 sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D_1 || 443 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1 || 444 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_2) { 445 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 446 ALC_MII_DBG_ADDR, 0x003B); 447 data = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr, 448 ALC_MII_DBG_DATA); 449 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 450 ALC_MII_DBG_DATA, data & 0xFFF7); 451 DELAY(20 * 1000); 452 } 453 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D) { 454 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 455 ALC_MII_DBG_ADDR, 0x0029); 456 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 457 ALC_MII_DBG_DATA, 0x929D); 458 } 459 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1C || 460 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C || 461 sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D_1 || 462 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_2) { 463 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 464 ALC_MII_DBG_ADDR, 0x0029); 465 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 466 ALC_MII_DBG_DATA, 0xB6DD); 467 } 468 469 /* Load DSP codes, vendor magic. */ 470 data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE | 471 ((1 << ANA_INTERVAL_SEL_TIMER_SHIFT) & ANA_INTERVAL_SEL_TIMER_MASK); 472 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 473 ALC_MII_DBG_ADDR, MII_ANA_CFG18); 474 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 475 ALC_MII_DBG_DATA, data); 476 477 data = ((2 << ANA_SERDES_CDR_BW_SHIFT) & ANA_SERDES_CDR_BW_MASK) | 478 ANA_SERDES_EN_DEEM | ANA_SERDES_SEL_HSP | ANA_SERDES_EN_PLL | 479 ANA_SERDES_EN_LCKDT; 480 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 481 ALC_MII_DBG_ADDR, MII_ANA_CFG5); 482 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 483 ALC_MII_DBG_DATA, data); 484 485 data = ((44 << ANA_LONG_CABLE_TH_100_SHIFT) & 486 ANA_LONG_CABLE_TH_100_MASK) | 487 ((33 << ANA_SHORT_CABLE_TH_100_SHIFT) & 488 ANA_SHORT_CABLE_TH_100_SHIFT) | 489 ANA_BP_BAD_LINK_ACCUM | ANA_BP_SMALL_BW; 490 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 491 ALC_MII_DBG_ADDR, MII_ANA_CFG54); 492 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 493 ALC_MII_DBG_DATA, data); 494 495 data = ((11 << ANA_IECHO_ADJ_3_SHIFT) & ANA_IECHO_ADJ_3_MASK) | 496 ((11 << ANA_IECHO_ADJ_2_SHIFT) & ANA_IECHO_ADJ_2_MASK) | 497 ((8 << ANA_IECHO_ADJ_1_SHIFT) & ANA_IECHO_ADJ_1_MASK) | 498 ((8 << ANA_IECHO_ADJ_0_SHIFT) & ANA_IECHO_ADJ_0_MASK); 499 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 500 ALC_MII_DBG_ADDR, MII_ANA_CFG4); 501 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 502 ALC_MII_DBG_DATA, data); 503 504 data = ((7 & ANA_MANUL_SWICH_ON_SHIFT) & ANA_MANUL_SWICH_ON_MASK) | 505 ANA_RESTART_CAL | ANA_MAN_ENABLE | ANA_SEL_HSP | ANA_EN_HB | 506 ANA_OEN_125M; 507 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 508 ALC_MII_DBG_ADDR, MII_ANA_CFG0); 509 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 510 ALC_MII_DBG_DATA, data); 511 DELAY(1000); 512 513 /* Disable hibernation. */ 514 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 515 0x0029); 516 data = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr, 517 ALC_MII_DBG_DATA); 518 data &= ~0x8000; 519 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 520 data); 521 522 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 523 0x000B); 524 data = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr, 525 ALC_MII_DBG_DATA); 526 data &= ~0x8000; 527 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 528 data); 529 } 530 531 void 532 alc_phy_down(struct alc_softc *sc) 533 { 534 switch (sc->sc_product) { 535 case PCI_PRODUCT_ATTANSIC_L1D: 536 case PCI_PRODUCT_ATTANSIC_L1D_1: 537 /* 538 * GPHY power down caused more problems on AR8151 v2.0. 539 * When driver is reloaded after GPHY power down, 540 * accesses to PHY/MAC registers hung the system. Only 541 * cold boot recovered from it. I'm not sure whether 542 * AR8151 v1.0 also requires this one though. I don't 543 * have AR8151 v1.0 controller in hand. 544 * The only option left is to isolate the PHY and 545 * initiates power down the PHY which in turn saves 546 * more power when driver is unloaded. 547 */ 548 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 549 MII_BMCR, BMCR_ISO | BMCR_PDOWN); 550 break; 551 default: 552 /* Force PHY down. */ 553 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | 554 GPHY_CFG_SEL_ANA_RESET | GPHY_CFG_PHY_IDDQ | 555 GPHY_CFG_PWDOWN_HW); 556 DELAY(1000); 557 break; 558 } 559 } 560 561 void 562 alc_aspm(struct alc_softc *sc, int media) 563 { 564 uint32_t pmcfg; 565 uint16_t linkcfg; 566 567 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 568 if ((sc->alc_flags & (ALC_FLAG_APS | ALC_FLAG_PCIE)) == 569 (ALC_FLAG_APS | ALC_FLAG_PCIE)) 570 linkcfg = CSR_READ_2(sc, sc->alc_expcap + 571 PCI_PCIE_LCSR); 572 else 573 linkcfg = 0; 574 pmcfg &= ~PM_CFG_SERDES_PD_EX_L1; 575 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_LCKDET_TIMER_MASK); 576 pmcfg |= PM_CFG_MAC_ASPM_CHK; 577 pmcfg |= (PM_CFG_LCKDET_TIMER_DEFAULT << PM_CFG_LCKDET_TIMER_SHIFT); 578 pmcfg &= ~(PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 579 580 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 581 /* Disable extended sync except AR8152 B v1.0 */ 582 linkcfg &= ~0x80; 583 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1 && 584 sc->alc_rev == ATHEROS_AR8152_B_V10) 585 linkcfg |= 0x80; 586 CSR_WRITE_2(sc, sc->alc_expcap + PCI_PCIE_LCSR, 587 linkcfg); 588 pmcfg &= ~(PM_CFG_EN_BUFS_RX_L0S | PM_CFG_SA_DLY_ENB | 589 PM_CFG_HOTRST); 590 pmcfg |= (PM_CFG_L1_ENTRY_TIMER_DEFAULT << 591 PM_CFG_L1_ENTRY_TIMER_SHIFT); 592 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 593 pmcfg |= (PM_CFG_PM_REQ_TIMER_DEFAULT << 594 PM_CFG_PM_REQ_TIMER_SHIFT); 595 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_PCIE_RECV; 596 } 597 598 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 599 if ((sc->alc_flags & ALC_FLAG_L0S) != 0) 600 pmcfg |= PM_CFG_ASPM_L0S_ENB; 601 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 602 pmcfg |= PM_CFG_ASPM_L1_ENB; 603 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 604 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1) 605 pmcfg &= ~PM_CFG_ASPM_L0S_ENB; 606 pmcfg &= ~(PM_CFG_SERDES_L1_ENB | 607 PM_CFG_SERDES_PLL_L1_ENB | 608 PM_CFG_SERDES_BUDS_RX_L1_ENB); 609 pmcfg |= PM_CFG_CLK_SWH_L1; 610 if (media == IFM_100_TX || media == IFM_1000_T) { 611 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK; 612 switch (sc->sc_product) { 613 case PCI_PRODUCT_ATTANSIC_L2C_1: 614 pmcfg |= (7 << 615 PM_CFG_L1_ENTRY_TIMER_SHIFT); 616 break; 617 case PCI_PRODUCT_ATTANSIC_L1D_1: 618 case PCI_PRODUCT_ATTANSIC_L2C_2: 619 pmcfg |= (4 << 620 PM_CFG_L1_ENTRY_TIMER_SHIFT); 621 break; 622 default: 623 pmcfg |= (15 << 624 PM_CFG_L1_ENTRY_TIMER_SHIFT); 625 break; 626 } 627 } 628 } else { 629 pmcfg |= PM_CFG_SERDES_L1_ENB | 630 PM_CFG_SERDES_PLL_L1_ENB | 631 PM_CFG_SERDES_BUDS_RX_L1_ENB; 632 pmcfg &= ~(PM_CFG_CLK_SWH_L1 | 633 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 634 } 635 } else { 636 pmcfg &= ~(PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_L1_ENB | 637 PM_CFG_SERDES_PLL_L1_ENB); 638 pmcfg |= PM_CFG_CLK_SWH_L1; 639 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 640 pmcfg |= PM_CFG_ASPM_L1_ENB; 641 } 642 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 643 } 644 645 void 646 alc_attach(struct device *parent, struct device *self, void *aux) 647 { 648 649 struct alc_softc *sc = (struct alc_softc *)self; 650 struct pci_attach_args *pa = aux; 651 pci_chipset_tag_t pc = pa->pa_pc; 652 pci_intr_handle_t ih; 653 const char *intrstr; 654 struct ifnet *ifp; 655 pcireg_t memtype; 656 char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/L1" }; 657 uint16_t burst; 658 int base, state, error = 0; 659 uint32_t cap, ctl, val; 660 661 /* 662 * Allocate IO memory 663 */ 664 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, ALC_PCIR_BAR); 665 if (pci_mapreg_map(pa, ALC_PCIR_BAR, memtype, 0, &sc->sc_mem_bt, 666 &sc->sc_mem_bh, NULL, &sc->sc_mem_size, 0)) { 667 printf(": can't map mem space\n"); 668 return; 669 } 670 671 if (pci_intr_map_msi(pa, &ih) != 0 && pci_intr_map(pa, &ih) != 0) { 672 printf(": can't map interrupt\n"); 673 goto fail; 674 } 675 676 /* 677 * Allocate IRQ 678 */ 679 intrstr = pci_intr_string(pc, ih); 680 sc->sc_irq_handle = pci_intr_establish(pc, ih, IPL_NET, alc_intr, sc, 681 sc->sc_dev.dv_xname); 682 if (sc->sc_irq_handle == NULL) { 683 printf(": could not establish interrupt"); 684 if (intrstr != NULL) 685 printf(" at %s", intrstr); 686 printf("\n"); 687 goto fail; 688 } 689 printf(": %s", intrstr); 690 691 sc->sc_dmat = pa->pa_dmat; 692 sc->sc_pct = pa->pa_pc; 693 sc->sc_pcitag = pa->pa_tag; 694 695 /* Set PHY address. */ 696 sc->alc_phyaddr = ALC_PHY_ADDR; 697 698 /* Get PCI and chip id/revision. */ 699 sc->sc_product = PCI_PRODUCT(pa->pa_id); 700 sc->alc_rev = PCI_REVISION(pa->pa_class); 701 702 /* Initialize DMA parameters. */ 703 sc->alc_dma_rd_burst = 0; 704 sc->alc_dma_wr_burst = 0; 705 sc->alc_rcb = DMA_CFG_RCB_64; 706 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PCIEXPRESS, 707 &base, NULL)) { 708 sc->alc_flags |= ALC_FLAG_PCIE; 709 sc->alc_expcap = base; 710 burst = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 711 base + PCI_PCIE_DCSR) >> 16; 712 sc->alc_dma_rd_burst = (burst & 0x7000) >> 12; 713 sc->alc_dma_wr_burst = (burst & 0x00e0) >> 5; 714 if (alcdebug) { 715 printf("%s: Read request size : %u bytes.\n", 716 sc->sc_dev.dv_xname, 717 alc_dma_burst[sc->alc_dma_rd_burst]); 718 printf("%s: TLP payload size : %u bytes.\n", 719 sc->sc_dev.dv_xname, 720 alc_dma_burst[sc->alc_dma_wr_burst]); 721 } 722 if (alc_dma_burst[sc->alc_dma_rd_burst] > 1024) 723 sc->alc_dma_rd_burst = 3; 724 if (alc_dma_burst[sc->alc_dma_wr_burst] > 1024) 725 sc->alc_dma_wr_burst = 3; 726 /* Clear data link and flow-control protocol error. */ 727 val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV); 728 val &= ~(PEX_UNC_ERR_SEV_DLP | PEX_UNC_ERR_SEV_FCP); 729 CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val); 730 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 731 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 732 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, 733 CSR_READ_4(sc, ALC_PCIE_PHYMISC) | 734 PCIE_PHYMISC_FORCE_RCV_DET); 735 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1 && 736 sc->alc_rev == ATHEROS_AR8152_B_V10) { 737 val = CSR_READ_4(sc, ALC_PCIE_PHYMISC2); 738 val &= ~(PCIE_PHYMISC2_SERDES_CDR_MASK | 739 PCIE_PHYMISC2_SERDES_TH_MASK); 740 val |= 3 << PCIE_PHYMISC2_SERDES_CDR_SHIFT; 741 val |= 3 << PCIE_PHYMISC2_SERDES_TH_SHIFT; 742 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC2, val); 743 } 744 /* Disable ASPM L0S and L1. */ 745 cap = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 746 base + PCI_PCIE_LCAP) >> 16; 747 if ((cap & 0x00000c00) != 0) { 748 ctl = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 749 base + PCI_PCIE_LCSR) >> 16; 750 if ((ctl & 0x08) != 0) 751 sc->alc_rcb = DMA_CFG_RCB_128; 752 if (alcdebug) 753 printf("%s: RCB %u bytes\n", 754 sc->sc_dev.dv_xname, 755 sc->alc_rcb == DMA_CFG_RCB_64 ? 64 : 128); 756 state = ctl & 0x03; 757 if (state & 0x01) 758 sc->alc_flags |= ALC_FLAG_L0S; 759 if (state & 0x02) 760 sc->alc_flags |= ALC_FLAG_L1S; 761 if (alcdebug) 762 printf("%s: ASPM %s %s\n", 763 sc->sc_dev.dv_xname, 764 aspm_state[state], 765 state == 0 ? "disabled" : "enabled"); 766 alc_disable_l0s_l1(sc); 767 } 768 } 769 770 /* Reset PHY. */ 771 alc_phy_reset(sc); 772 773 /* Reset the ethernet controller. */ 774 alc_reset(sc); 775 776 /* 777 * One odd thing is AR8132 uses the same PHY hardware(F1 778 * gigabit PHY) of AR8131. So atphy(4) of AR8132 reports 779 * the PHY supports 1000Mbps but that's not true. The PHY 780 * used in AR8132 can't establish gigabit link even if it 781 * shows the same PHY model/revision number of AR8131. 782 */ 783 switch (sc->sc_product) { 784 case PCI_PRODUCT_ATTANSIC_L2C_1: 785 case PCI_PRODUCT_ATTANSIC_L2C_2: 786 sc->alc_flags |= ALC_FLAG_APS; 787 /* FALLTHROUGH */ 788 case PCI_PRODUCT_ATTANSIC_L2C: 789 sc->alc_flags |= ALC_FLAG_FASTETHER; 790 break; 791 case PCI_PRODUCT_ATTANSIC_L1D: 792 case PCI_PRODUCT_ATTANSIC_L1D_1: 793 sc->alc_flags |= ALC_FLAG_APS; 794 /* FALLTHROUGH */ 795 default: 796 break; 797 } 798 sc->alc_flags |= ALC_FLAG_ASPM_MON | ALC_FLAG_JUMBO; 799 800 switch (sc->sc_product) { 801 case PCI_PRODUCT_ATTANSIC_L1C: 802 case PCI_PRODUCT_ATTANSIC_L2C: 803 sc->alc_max_framelen = 9 * 1024; 804 break; 805 case PCI_PRODUCT_ATTANSIC_L1D: 806 case PCI_PRODUCT_ATTANSIC_L1D_1: 807 case PCI_PRODUCT_ATTANSIC_L2C_1: 808 case PCI_PRODUCT_ATTANSIC_L2C_2: 809 sc->alc_max_framelen = 6 * 1024; 810 break; 811 } 812 813 /* 814 * It seems that AR813x/AR815x has silicon bug for SMB. In 815 * addition, Atheros said that enabling SMB wouldn't improve 816 * performance. However I think it's bad to access lots of 817 * registers to extract MAC statistics. 818 */ 819 sc->alc_flags |= ALC_FLAG_SMB_BUG; 820 /* 821 * Don't use Tx CMB. It is known to have silicon bug. 822 */ 823 sc->alc_flags |= ALC_FLAG_CMB_BUG; 824 825 sc->alc_chip_rev = CSR_READ_4(sc, ALC_MASTER_CFG) >> 826 MASTER_CHIP_REV_SHIFT; 827 if (alcdebug) { 828 printf("%s: PCI device revision : 0x%04x\n", 829 sc->sc_dev.dv_xname, sc->alc_rev); 830 printf("%s: Chip id/revision : 0x%04x\n", 831 sc->sc_dev.dv_xname, sc->alc_chip_rev); 832 printf("%s: %u Tx FIFO, %u Rx FIFO\n", sc->sc_dev.dv_xname, 833 CSR_READ_4(sc, ALC_SRAM_TX_FIFO_LEN) * 8, 834 CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN) * 8); 835 } 836 837 error = alc_dma_alloc(sc); 838 if (error) 839 goto fail; 840 841 /* Load station address. */ 842 alc_get_macaddr(sc); 843 844 ifp = &sc->sc_arpcom.ac_if; 845 ifp->if_softc = sc; 846 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 847 ifp->if_ioctl = alc_ioctl; 848 ifp->if_start = alc_start; 849 ifp->if_watchdog = alc_watchdog; 850 ifp->if_baudrate = IF_Gbps(1); 851 IFQ_SET_MAXLEN(&ifp->if_snd, ALC_TX_RING_CNT - 1); 852 IFQ_SET_READY(&ifp->if_snd); 853 bcopy(sc->alc_eaddr, sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN); 854 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 855 856 ifp->if_capabilities = IFCAP_VLAN_MTU; 857 858 #ifdef ALC_CHECKSUM 859 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 860 IFCAP_CSUM_UDPv4; 861 #endif 862 863 #if NVLAN > 0 864 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 865 #endif 866 867 printf(", address %s\n", ether_sprintf(sc->sc_arpcom.ac_enaddr)); 868 869 /* Set up MII bus. */ 870 sc->sc_miibus.mii_ifp = ifp; 871 sc->sc_miibus.mii_readreg = alc_miibus_readreg; 872 sc->sc_miibus.mii_writereg = alc_miibus_writereg; 873 sc->sc_miibus.mii_statchg = alc_miibus_statchg; 874 875 ifmedia_init(&sc->sc_miibus.mii_media, 0, alc_mediachange, 876 alc_mediastatus); 877 mii_attach(self, &sc->sc_miibus, 0xffffffff, MII_PHY_ANY, 878 MII_OFFSET_ANY, MIIF_DOPAUSE); 879 880 if (LIST_FIRST(&sc->sc_miibus.mii_phys) == NULL) { 881 printf("%s: no PHY found!\n", sc->sc_dev.dv_xname); 882 ifmedia_add(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL, 883 0, NULL); 884 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL); 885 } else 886 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_AUTO); 887 888 if_attach(ifp); 889 ether_ifattach(ifp); 890 891 timeout_set(&sc->alc_tick_ch, alc_tick, sc); 892 893 return; 894 fail: 895 alc_dma_free(sc); 896 if (sc->sc_irq_handle != NULL) 897 pci_intr_disestablish(pc, sc->sc_irq_handle); 898 if (sc->sc_mem_size) 899 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 900 } 901 902 int 903 alc_detach(struct device *self, int flags) 904 { 905 struct alc_softc *sc = (struct alc_softc *)self; 906 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 907 int s; 908 909 s = splnet(); 910 alc_stop(sc); 911 splx(s); 912 913 mii_detach(&sc->sc_miibus, MII_PHY_ANY, MII_OFFSET_ANY); 914 915 /* Delete all remaining media. */ 916 ifmedia_delete_instance(&sc->sc_miibus.mii_media, IFM_INST_ANY); 917 918 ether_ifdetach(ifp); 919 if_detach(ifp); 920 alc_dma_free(sc); 921 922 alc_phy_down(sc); 923 if (sc->sc_irq_handle != NULL) { 924 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 925 sc->sc_irq_handle = NULL; 926 } 927 928 return (0); 929 } 930 931 int 932 alc_activate(struct device *self, int act) 933 { 934 struct alc_softc *sc = (struct alc_softc *)self; 935 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 936 int rv = 0; 937 938 switch (act) { 939 case DVACT_QUIESCE: 940 rv = config_activate_children(self, act); 941 break; 942 case DVACT_SUSPEND: 943 if (ifp->if_flags & IFF_RUNNING) 944 alc_stop(sc); 945 rv = config_activate_children(self, act); 946 break; 947 case DVACT_RESUME: 948 rv = config_activate_children(self, act); 949 if (ifp->if_flags & IFF_UP) 950 alc_init(ifp); 951 break; 952 } 953 return (rv); 954 } 955 956 int 957 alc_dma_alloc(struct alc_softc *sc) 958 { 959 struct alc_txdesc *txd; 960 struct alc_rxdesc *rxd; 961 int nsegs, error, i; 962 963 /* 964 * Create DMA stuffs for TX ring 965 */ 966 error = bus_dmamap_create(sc->sc_dmat, ALC_TX_RING_SZ, 1, 967 ALC_TX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->alc_cdata.alc_tx_ring_map); 968 if (error) 969 return (ENOBUFS); 970 971 /* Allocate DMA'able memory for TX ring */ 972 error = bus_dmamem_alloc(sc->sc_dmat, ALC_TX_RING_SZ, 973 ETHER_ALIGN, 0, &sc->alc_rdata.alc_tx_ring_seg, 1, 974 &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 975 if (error) { 976 printf("%s: could not allocate DMA'able memory for Tx ring.\n", 977 sc->sc_dev.dv_xname); 978 return error; 979 } 980 981 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_tx_ring_seg, 982 nsegs, ALC_TX_RING_SZ, (caddr_t *)&sc->alc_rdata.alc_tx_ring, 983 BUS_DMA_NOWAIT); 984 if (error) 985 return (ENOBUFS); 986 987 /* Load the DMA map for Tx ring. */ 988 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 989 sc->alc_rdata.alc_tx_ring, ALC_TX_RING_SZ, NULL, BUS_DMA_WAITOK); 990 if (error) { 991 printf("%s: could not load DMA'able memory for Tx ring.\n", 992 sc->sc_dev.dv_xname); 993 bus_dmamem_free(sc->sc_dmat, 994 (bus_dma_segment_t *)&sc->alc_rdata.alc_tx_ring, 1); 995 return error; 996 } 997 998 sc->alc_rdata.alc_tx_ring_paddr = 999 sc->alc_cdata.alc_tx_ring_map->dm_segs[0].ds_addr; 1000 1001 /* 1002 * Create DMA stuffs for RX ring 1003 */ 1004 error = bus_dmamap_create(sc->sc_dmat, ALC_RX_RING_SZ, 1, 1005 ALC_RX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->alc_cdata.alc_rx_ring_map); 1006 if (error) 1007 return (ENOBUFS); 1008 1009 /* Allocate DMA'able memory for RX ring */ 1010 error = bus_dmamem_alloc(sc->sc_dmat, ALC_RX_RING_SZ, 1011 ETHER_ALIGN, 0, &sc->alc_rdata.alc_rx_ring_seg, 1, 1012 &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 1013 if (error) { 1014 printf("%s: could not allocate DMA'able memory for Rx ring.\n", 1015 sc->sc_dev.dv_xname); 1016 return error; 1017 } 1018 1019 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_rx_ring_seg, 1020 nsegs, ALC_RX_RING_SZ, (caddr_t *)&sc->alc_rdata.alc_rx_ring, 1021 BUS_DMA_NOWAIT); 1022 if (error) 1023 return (ENOBUFS); 1024 1025 /* Load the DMA map for Rx ring. */ 1026 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 1027 sc->alc_rdata.alc_rx_ring, ALC_RX_RING_SZ, NULL, BUS_DMA_WAITOK); 1028 if (error) { 1029 printf("%s: could not load DMA'able memory for Rx ring.\n", 1030 sc->sc_dev.dv_xname); 1031 bus_dmamem_free(sc->sc_dmat, 1032 (bus_dma_segment_t *)sc->alc_rdata.alc_rx_ring, 1); 1033 return error; 1034 } 1035 1036 sc->alc_rdata.alc_rx_ring_paddr = 1037 sc->alc_cdata.alc_rx_ring_map->dm_segs[0].ds_addr; 1038 1039 /* 1040 * Create DMA stuffs for RX return ring 1041 */ 1042 error = bus_dmamap_create(sc->sc_dmat, ALC_RR_RING_SZ, 1, 1043 ALC_RR_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->alc_cdata.alc_rr_ring_map); 1044 if (error) 1045 return (ENOBUFS); 1046 1047 /* Allocate DMA'able memory for RX return ring */ 1048 error = bus_dmamem_alloc(sc->sc_dmat, ALC_RR_RING_SZ, 1049 ETHER_ALIGN, 0, &sc->alc_rdata.alc_rr_ring_seg, 1, 1050 &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 1051 if (error) { 1052 printf("%s: could not allocate DMA'able memory for Rx " 1053 "return ring.\n", sc->sc_dev.dv_xname); 1054 return error; 1055 } 1056 1057 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_rr_ring_seg, 1058 nsegs, ALC_RR_RING_SZ, (caddr_t *)&sc->alc_rdata.alc_rr_ring, 1059 BUS_DMA_NOWAIT); 1060 if (error) 1061 return (ENOBUFS); 1062 1063 /* Load the DMA map for Rx return ring. */ 1064 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 1065 sc->alc_rdata.alc_rr_ring, ALC_RR_RING_SZ, NULL, BUS_DMA_WAITOK); 1066 if (error) { 1067 printf("%s: could not load DMA'able memory for Rx return ring." 1068 "\n", sc->sc_dev.dv_xname); 1069 bus_dmamem_free(sc->sc_dmat, 1070 (bus_dma_segment_t *)&sc->alc_rdata.alc_rr_ring, 1); 1071 return error; 1072 } 1073 1074 sc->alc_rdata.alc_rr_ring_paddr = 1075 sc->alc_cdata.alc_rr_ring_map->dm_segs[0].ds_addr; 1076 1077 /* 1078 * Create DMA stuffs for CMB block 1079 */ 1080 error = bus_dmamap_create(sc->sc_dmat, ALC_CMB_SZ, 1, 1081 ALC_CMB_SZ, 0, BUS_DMA_NOWAIT, 1082 &sc->alc_cdata.alc_cmb_map); 1083 if (error) 1084 return (ENOBUFS); 1085 1086 /* Allocate DMA'able memory for CMB block */ 1087 error = bus_dmamem_alloc(sc->sc_dmat, ALC_CMB_SZ, 1088 ETHER_ALIGN, 0, &sc->alc_rdata.alc_cmb_seg, 1, 1089 &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 1090 if (error) { 1091 printf("%s: could not allocate DMA'able memory for " 1092 "CMB block\n", sc->sc_dev.dv_xname); 1093 return error; 1094 } 1095 1096 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_cmb_seg, 1097 nsegs, ALC_CMB_SZ, (caddr_t *)&sc->alc_rdata.alc_cmb, 1098 BUS_DMA_NOWAIT); 1099 if (error) 1100 return (ENOBUFS); 1101 1102 /* Load the DMA map for CMB block. */ 1103 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 1104 sc->alc_rdata.alc_cmb, ALC_CMB_SZ, NULL, 1105 BUS_DMA_WAITOK); 1106 if (error) { 1107 printf("%s: could not load DMA'able memory for CMB block\n", 1108 sc->sc_dev.dv_xname); 1109 bus_dmamem_free(sc->sc_dmat, 1110 (bus_dma_segment_t *)&sc->alc_rdata.alc_cmb, 1); 1111 return error; 1112 } 1113 1114 sc->alc_rdata.alc_cmb_paddr = 1115 sc->alc_cdata.alc_cmb_map->dm_segs[0].ds_addr; 1116 1117 /* 1118 * Create DMA stuffs for SMB block 1119 */ 1120 error = bus_dmamap_create(sc->sc_dmat, ALC_SMB_SZ, 1, 1121 ALC_SMB_SZ, 0, BUS_DMA_NOWAIT, 1122 &sc->alc_cdata.alc_smb_map); 1123 if (error) 1124 return (ENOBUFS); 1125 1126 /* Allocate DMA'able memory for SMB block */ 1127 error = bus_dmamem_alloc(sc->sc_dmat, ALC_SMB_SZ, 1128 ETHER_ALIGN, 0, &sc->alc_rdata.alc_smb_seg, 1, 1129 &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 1130 if (error) { 1131 printf("%s: could not allocate DMA'able memory for " 1132 "SMB block\n", sc->sc_dev.dv_xname); 1133 return error; 1134 } 1135 1136 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_smb_seg, 1137 nsegs, ALC_SMB_SZ, (caddr_t *)&sc->alc_rdata.alc_smb, 1138 BUS_DMA_NOWAIT); 1139 if (error) 1140 return (ENOBUFS); 1141 1142 /* Load the DMA map for SMB block */ 1143 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 1144 sc->alc_rdata.alc_smb, ALC_SMB_SZ, NULL, 1145 BUS_DMA_WAITOK); 1146 if (error) { 1147 printf("%s: could not load DMA'able memory for SMB block\n", 1148 sc->sc_dev.dv_xname); 1149 bus_dmamem_free(sc->sc_dmat, 1150 (bus_dma_segment_t *)&sc->alc_rdata.alc_smb, 1); 1151 return error; 1152 } 1153 1154 sc->alc_rdata.alc_smb_paddr = 1155 sc->alc_cdata.alc_smb_map->dm_segs[0].ds_addr; 1156 1157 1158 /* Create DMA maps for Tx buffers. */ 1159 for (i = 0; i < ALC_TX_RING_CNT; i++) { 1160 txd = &sc->alc_cdata.alc_txdesc[i]; 1161 txd->tx_m = NULL; 1162 txd->tx_dmamap = NULL; 1163 error = bus_dmamap_create(sc->sc_dmat, ALC_TSO_MAXSIZE, 1164 ALC_MAXTXSEGS, ALC_TSO_MAXSEGSIZE, 0, BUS_DMA_NOWAIT, 1165 &txd->tx_dmamap); 1166 if (error) { 1167 printf("%s: could not create Tx dmamap.\n", 1168 sc->sc_dev.dv_xname); 1169 return error; 1170 } 1171 } 1172 1173 /* Create DMA maps for Rx buffers. */ 1174 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 1175 BUS_DMA_NOWAIT, &sc->alc_cdata.alc_rx_sparemap); 1176 if (error) { 1177 printf("%s: could not create spare Rx dmamap.\n", 1178 sc->sc_dev.dv_xname); 1179 return error; 1180 } 1181 1182 for (i = 0; i < ALC_RX_RING_CNT; i++) { 1183 rxd = &sc->alc_cdata.alc_rxdesc[i]; 1184 rxd->rx_m = NULL; 1185 rxd->rx_dmamap = NULL; 1186 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1187 MCLBYTES, 0, BUS_DMA_NOWAIT, &rxd->rx_dmamap); 1188 if (error) { 1189 printf("%s: could not create Rx dmamap.\n", 1190 sc->sc_dev.dv_xname); 1191 return error; 1192 } 1193 } 1194 1195 return (0); 1196 } 1197 1198 1199 void 1200 alc_dma_free(struct alc_softc *sc) 1201 { 1202 struct alc_txdesc *txd; 1203 struct alc_rxdesc *rxd; 1204 int i; 1205 1206 /* Tx buffers */ 1207 for (i = 0; i < ALC_TX_RING_CNT; i++) { 1208 txd = &sc->alc_cdata.alc_txdesc[i]; 1209 if (txd->tx_dmamap != NULL) { 1210 bus_dmamap_destroy(sc->sc_dmat, txd->tx_dmamap); 1211 txd->tx_dmamap = NULL; 1212 } 1213 } 1214 /* Rx buffers */ 1215 for (i = 0; i < ALC_RX_RING_CNT; i++) { 1216 rxd = &sc->alc_cdata.alc_rxdesc[i]; 1217 if (rxd->rx_dmamap != NULL) { 1218 bus_dmamap_destroy(sc->sc_dmat, rxd->rx_dmamap); 1219 rxd->rx_dmamap = NULL; 1220 } 1221 } 1222 if (sc->alc_cdata.alc_rx_sparemap != NULL) { 1223 bus_dmamap_destroy(sc->sc_dmat, sc->alc_cdata.alc_rx_sparemap); 1224 sc->alc_cdata.alc_rx_sparemap = NULL; 1225 } 1226 1227 /* Tx ring. */ 1228 if (sc->alc_cdata.alc_tx_ring_map != NULL) 1229 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map); 1230 if (sc->alc_cdata.alc_tx_ring_map != NULL && 1231 sc->alc_rdata.alc_tx_ring != NULL) 1232 bus_dmamem_free(sc->sc_dmat, 1233 (bus_dma_segment_t *)sc->alc_rdata.alc_tx_ring, 1); 1234 sc->alc_rdata.alc_tx_ring = NULL; 1235 sc->alc_cdata.alc_tx_ring_map = NULL; 1236 1237 /* Rx ring. */ 1238 if (sc->alc_cdata.alc_rx_ring_map != NULL) 1239 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map); 1240 if (sc->alc_cdata.alc_rx_ring_map != NULL && 1241 sc->alc_rdata.alc_rx_ring != NULL) 1242 bus_dmamem_free(sc->sc_dmat, 1243 (bus_dma_segment_t *)sc->alc_rdata.alc_rx_ring, 1); 1244 sc->alc_rdata.alc_rx_ring = NULL; 1245 sc->alc_cdata.alc_rx_ring_map = NULL; 1246 1247 /* Rx return ring. */ 1248 if (sc->alc_cdata.alc_rr_ring_map != NULL) 1249 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map); 1250 if (sc->alc_cdata.alc_rr_ring_map != NULL && 1251 sc->alc_rdata.alc_rr_ring != NULL) 1252 bus_dmamem_free(sc->sc_dmat, 1253 (bus_dma_segment_t *)sc->alc_rdata.alc_rr_ring, 1); 1254 sc->alc_rdata.alc_rr_ring = NULL; 1255 sc->alc_cdata.alc_rr_ring_map = NULL; 1256 1257 /* CMB block */ 1258 if (sc->alc_cdata.alc_cmb_map != NULL) 1259 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_cmb_map); 1260 if (sc->alc_cdata.alc_cmb_map != NULL && 1261 sc->alc_rdata.alc_cmb != NULL) 1262 bus_dmamem_free(sc->sc_dmat, 1263 (bus_dma_segment_t *)sc->alc_rdata.alc_cmb, 1); 1264 sc->alc_rdata.alc_cmb = NULL; 1265 sc->alc_cdata.alc_cmb_map = NULL; 1266 1267 /* SMB block */ 1268 if (sc->alc_cdata.alc_smb_map != NULL) 1269 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_smb_map); 1270 if (sc->alc_cdata.alc_smb_map != NULL && 1271 sc->alc_rdata.alc_smb != NULL) 1272 bus_dmamem_free(sc->sc_dmat, 1273 (bus_dma_segment_t *)sc->alc_rdata.alc_smb, 1); 1274 sc->alc_rdata.alc_smb = NULL; 1275 sc->alc_cdata.alc_smb_map = NULL; 1276 } 1277 1278 int 1279 alc_encap(struct alc_softc *sc, struct mbuf **m_head) 1280 { 1281 struct alc_txdesc *txd, *txd_last; 1282 struct tx_desc *desc; 1283 struct mbuf *m; 1284 bus_dmamap_t map; 1285 uint32_t cflags, poff, vtag; 1286 int error, idx, prod; 1287 1288 m = *m_head; 1289 cflags = vtag = 0; 1290 poff = 0; 1291 1292 prod = sc->alc_cdata.alc_tx_prod; 1293 txd = &sc->alc_cdata.alc_txdesc[prod]; 1294 txd_last = txd; 1295 map = txd->tx_dmamap; 1296 1297 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, BUS_DMA_NOWAIT); 1298 if (error != 0 && error != EFBIG) 1299 goto drop; 1300 if (error != 0) { 1301 if (m_defrag(*m_head, M_DONTWAIT)) { 1302 error = ENOBUFS; 1303 goto drop; 1304 } 1305 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, 1306 BUS_DMA_NOWAIT); 1307 if (error != 0) 1308 goto drop; 1309 } 1310 1311 /* Check descriptor overrun. */ 1312 if (sc->alc_cdata.alc_tx_cnt + map->dm_nsegs >= ALC_TX_RING_CNT - 3) { 1313 bus_dmamap_unload(sc->sc_dmat, map); 1314 return (ENOBUFS); 1315 } 1316 1317 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1318 BUS_DMASYNC_PREWRITE); 1319 1320 m = *m_head; 1321 desc = NULL; 1322 idx = 0; 1323 #if NVLAN > 0 1324 /* Configure VLAN hardware tag insertion. */ 1325 if (m->m_flags & M_VLANTAG) { 1326 vtag = htons(m->m_pkthdr.ether_vtag); 1327 vtag = (vtag << TD_VLAN_SHIFT) & TD_VLAN_MASK; 1328 cflags |= TD_INS_VLAN_TAG; 1329 } 1330 #endif 1331 /* Configure Tx checksum offload. */ 1332 if ((m->m_pkthdr.csum_flags & ALC_CSUM_FEATURES) != 0) { 1333 cflags |= TD_CUSTOM_CSUM; 1334 /* Set checksum start offset. */ 1335 cflags |= ((poff >> 1) << TD_PLOAD_OFFSET_SHIFT) & 1336 TD_PLOAD_OFFSET_MASK; 1337 } 1338 1339 for (; idx < map->dm_nsegs; idx++) { 1340 desc = &sc->alc_rdata.alc_tx_ring[prod]; 1341 desc->len = 1342 htole32(TX_BYTES(map->dm_segs[idx].ds_len) | vtag); 1343 desc->flags = htole32(cflags); 1344 desc->addr = htole64(map->dm_segs[idx].ds_addr); 1345 sc->alc_cdata.alc_tx_cnt++; 1346 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 1347 } 1348 1349 /* Update producer index. */ 1350 sc->alc_cdata.alc_tx_prod = prod; 1351 1352 /* Finally set EOP on the last descriptor. */ 1353 prod = (prod + ALC_TX_RING_CNT - 1) % ALC_TX_RING_CNT; 1354 desc = &sc->alc_rdata.alc_tx_ring[prod]; 1355 desc->flags |= htole32(TD_EOP); 1356 1357 /* Swap dmamap of the first and the last. */ 1358 txd = &sc->alc_cdata.alc_txdesc[prod]; 1359 map = txd_last->tx_dmamap; 1360 txd_last->tx_dmamap = txd->tx_dmamap; 1361 txd->tx_dmamap = map; 1362 txd->tx_m = m; 1363 1364 return (0); 1365 1366 drop: 1367 m_freem(*m_head); 1368 *m_head = NULL; 1369 return (error); 1370 } 1371 1372 void 1373 alc_start(struct ifnet *ifp) 1374 { 1375 struct alc_softc *sc = ifp->if_softc; 1376 struct mbuf *m_head; 1377 int enq = 0; 1378 1379 /* Reclaim transmitted frames. */ 1380 if (sc->alc_cdata.alc_tx_cnt >= ALC_TX_DESC_HIWAT) 1381 alc_txeof(sc); 1382 1383 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1384 return; 1385 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) 1386 return; 1387 if (IFQ_IS_EMPTY(&ifp->if_snd)) 1388 return; 1389 1390 for (;;) { 1391 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1392 if (m_head == NULL) 1393 break; 1394 1395 /* 1396 * Pack the data into the transmit ring. If we 1397 * don't have room, set the OACTIVE flag and wait 1398 * for the NIC to drain the ring. 1399 */ 1400 if (alc_encap(sc, &m_head)) { 1401 if (m_head == NULL) 1402 ifp->if_oerrors++; 1403 else { 1404 IF_PREPEND(&ifp->if_snd, m_head); 1405 ifp->if_flags |= IFF_OACTIVE; 1406 } 1407 break; 1408 } 1409 enq++; 1410 1411 #if NBPFILTER > 0 1412 /* 1413 * If there's a BPF listener, bounce a copy of this frame 1414 * to him. 1415 */ 1416 if (ifp->if_bpf != NULL) 1417 bpf_mtap_ether(ifp->if_bpf, m_head, BPF_DIRECTION_OUT); 1418 #endif 1419 } 1420 1421 if (enq > 0) { 1422 /* Sync descriptors. */ 1423 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0, 1424 sc->alc_cdata.alc_tx_ring_map->dm_mapsize, 1425 BUS_DMASYNC_PREWRITE); 1426 /* Kick. Assume we're using normal Tx priority queue. */ 1427 CSR_WRITE_4(sc, ALC_MBOX_TD_PROD_IDX, 1428 (sc->alc_cdata.alc_tx_prod << 1429 MBOX_TD_PROD_LO_IDX_SHIFT) & 1430 MBOX_TD_PROD_LO_IDX_MASK); 1431 /* Set a timeout in case the chip goes out to lunch. */ 1432 ifp->if_timer = ALC_TX_TIMEOUT; 1433 } 1434 } 1435 1436 void 1437 alc_watchdog(struct ifnet *ifp) 1438 { 1439 struct alc_softc *sc = ifp->if_softc; 1440 1441 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) { 1442 printf("%s: watchdog timeout (missed link)\n", 1443 sc->sc_dev.dv_xname); 1444 ifp->if_oerrors++; 1445 alc_init(ifp); 1446 return; 1447 } 1448 1449 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 1450 ifp->if_oerrors++; 1451 alc_init(ifp); 1452 alc_start(ifp); 1453 } 1454 1455 int 1456 alc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1457 { 1458 struct alc_softc *sc = ifp->if_softc; 1459 struct mii_data *mii = &sc->sc_miibus; 1460 struct ifaddr *ifa = (struct ifaddr *)data; 1461 struct ifreq *ifr = (struct ifreq *)data; 1462 int s, error = 0; 1463 1464 s = splnet(); 1465 1466 switch (cmd) { 1467 case SIOCSIFADDR: 1468 ifp->if_flags |= IFF_UP; 1469 if (!(ifp->if_flags & IFF_RUNNING)) 1470 alc_init(ifp); 1471 #ifdef INET 1472 if (ifa->ifa_addr->sa_family == AF_INET) 1473 arp_ifinit(&sc->sc_arpcom, ifa); 1474 #endif 1475 break; 1476 1477 case SIOCSIFFLAGS: 1478 if (ifp->if_flags & IFF_UP) { 1479 if (ifp->if_flags & IFF_RUNNING) 1480 error = ENETRESET; 1481 else 1482 alc_init(ifp); 1483 } else { 1484 if (ifp->if_flags & IFF_RUNNING) 1485 alc_stop(sc); 1486 } 1487 break; 1488 1489 case SIOCSIFMEDIA: 1490 case SIOCGIFMEDIA: 1491 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1492 break; 1493 1494 default: 1495 error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data); 1496 break; 1497 } 1498 1499 if (error == ENETRESET) { 1500 if (ifp->if_flags & IFF_RUNNING) 1501 alc_iff(sc); 1502 error = 0; 1503 } 1504 1505 splx(s); 1506 return (error); 1507 } 1508 1509 void 1510 alc_mac_config(struct alc_softc *sc) 1511 { 1512 struct mii_data *mii; 1513 uint32_t reg; 1514 1515 mii = &sc->sc_miibus; 1516 reg = CSR_READ_4(sc, ALC_MAC_CFG); 1517 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 1518 MAC_CFG_SPEED_MASK); 1519 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D || 1520 sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D_1 || 1521 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_2) 1522 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 1523 /* Reprogram MAC with resolved speed/duplex. */ 1524 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1525 case IFM_10_T: 1526 case IFM_100_TX: 1527 reg |= MAC_CFG_SPEED_10_100; 1528 break; 1529 case IFM_1000_T: 1530 reg |= MAC_CFG_SPEED_1000; 1531 break; 1532 } 1533 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1534 reg |= MAC_CFG_FULL_DUPLEX; 1535 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1536 reg |= MAC_CFG_TX_FC; 1537 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1538 reg |= MAC_CFG_RX_FC; 1539 } 1540 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 1541 } 1542 1543 void 1544 alc_stats_clear(struct alc_softc *sc) 1545 { 1546 struct smb sb, *smb; 1547 uint32_t *reg; 1548 int i; 1549 1550 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 1551 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 1552 sc->alc_cdata.alc_smb_map->dm_mapsize, 1553 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1554 smb = sc->alc_rdata.alc_smb; 1555 /* Update done, clear. */ 1556 smb->updated = 0; 1557 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 1558 sc->alc_cdata.alc_smb_map->dm_mapsize, 1559 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1560 } else { 1561 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 1562 reg++) { 1563 CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 1564 i += sizeof(uint32_t); 1565 } 1566 /* Read Tx statistics. */ 1567 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 1568 reg++) { 1569 CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 1570 i += sizeof(uint32_t); 1571 } 1572 } 1573 } 1574 1575 void 1576 alc_stats_update(struct alc_softc *sc) 1577 { 1578 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1579 struct alc_hw_stats *stat; 1580 struct smb sb, *smb; 1581 uint32_t *reg; 1582 int i; 1583 1584 stat = &sc->alc_stats; 1585 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 1586 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 1587 sc->alc_cdata.alc_smb_map->dm_mapsize, 1588 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1589 smb = sc->alc_rdata.alc_smb; 1590 if (smb->updated == 0) 1591 return; 1592 } else { 1593 smb = &sb; 1594 /* Read Rx statistics. */ 1595 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 1596 reg++) { 1597 *reg = CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 1598 i += sizeof(uint32_t); 1599 } 1600 /* Read Tx statistics. */ 1601 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 1602 reg++) { 1603 *reg = CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 1604 i += sizeof(uint32_t); 1605 } 1606 } 1607 1608 /* Rx stats. */ 1609 stat->rx_frames += smb->rx_frames; 1610 stat->rx_bcast_frames += smb->rx_bcast_frames; 1611 stat->rx_mcast_frames += smb->rx_mcast_frames; 1612 stat->rx_pause_frames += smb->rx_pause_frames; 1613 stat->rx_control_frames += smb->rx_control_frames; 1614 stat->rx_crcerrs += smb->rx_crcerrs; 1615 stat->rx_lenerrs += smb->rx_lenerrs; 1616 stat->rx_bytes += smb->rx_bytes; 1617 stat->rx_runts += smb->rx_runts; 1618 stat->rx_fragments += smb->rx_fragments; 1619 stat->rx_pkts_64 += smb->rx_pkts_64; 1620 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 1621 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 1622 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 1623 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 1624 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 1625 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 1626 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 1627 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 1628 stat->rx_rrs_errs += smb->rx_rrs_errs; 1629 stat->rx_alignerrs += smb->rx_alignerrs; 1630 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 1631 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 1632 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 1633 1634 /* Tx stats. */ 1635 stat->tx_frames += smb->tx_frames; 1636 stat->tx_bcast_frames += smb->tx_bcast_frames; 1637 stat->tx_mcast_frames += smb->tx_mcast_frames; 1638 stat->tx_pause_frames += smb->tx_pause_frames; 1639 stat->tx_excess_defer += smb->tx_excess_defer; 1640 stat->tx_control_frames += smb->tx_control_frames; 1641 stat->tx_deferred += smb->tx_deferred; 1642 stat->tx_bytes += smb->tx_bytes; 1643 stat->tx_pkts_64 += smb->tx_pkts_64; 1644 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 1645 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 1646 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 1647 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 1648 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 1649 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 1650 stat->tx_single_colls += smb->tx_single_colls; 1651 stat->tx_multi_colls += smb->tx_multi_colls; 1652 stat->tx_late_colls += smb->tx_late_colls; 1653 stat->tx_excess_colls += smb->tx_excess_colls; 1654 stat->tx_abort += smb->tx_abort; 1655 stat->tx_underrun += smb->tx_underrun; 1656 stat->tx_desc_underrun += smb->tx_desc_underrun; 1657 stat->tx_lenerrs += smb->tx_lenerrs; 1658 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 1659 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 1660 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 1661 1662 /* Update counters in ifnet. */ 1663 ifp->if_opackets += smb->tx_frames; 1664 1665 ifp->if_collisions += smb->tx_single_colls + 1666 smb->tx_multi_colls * 2 + smb->tx_late_colls + 1667 smb->tx_abort * HDPX_CFG_RETRY_DEFAULT; 1668 1669 /* 1670 * XXX 1671 * tx_pkts_truncated counter looks suspicious. It constantly 1672 * increments with no sign of Tx errors. This may indicate 1673 * the counter name is not correct one so I've removed the 1674 * counter in output errors. 1675 */ 1676 ifp->if_oerrors += smb->tx_abort + smb->tx_late_colls + 1677 smb->tx_underrun; 1678 1679 ifp->if_ipackets += smb->rx_frames; 1680 1681 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 1682 smb->rx_runts + smb->rx_pkts_truncated + 1683 smb->rx_fifo_oflows + smb->rx_rrs_errs + 1684 smb->rx_alignerrs; 1685 1686 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 1687 /* Update done, clear. */ 1688 smb->updated = 0; 1689 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 1690 sc->alc_cdata.alc_smb_map->dm_mapsize, 1691 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1692 } 1693 } 1694 1695 int 1696 alc_intr(void *arg) 1697 { 1698 struct alc_softc *sc = arg; 1699 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1700 uint32_t status; 1701 int claimed = 0; 1702 1703 status = CSR_READ_4(sc, ALC_INTR_STATUS); 1704 if ((status & ALC_INTRS) == 0) 1705 return (0); 1706 1707 /* Disable interrupts. */ 1708 CSR_WRITE_4(sc, ALC_INTR_STATUS, INTR_DIS_INT); 1709 1710 status = CSR_READ_4(sc, ALC_INTR_STATUS); 1711 if ((status & ALC_INTRS) == 0) 1712 goto back; 1713 1714 /* Acknowledge and disable interrupts. */ 1715 CSR_WRITE_4(sc, ALC_INTR_STATUS, status | INTR_DIS_INT); 1716 1717 if (ifp->if_flags & IFF_RUNNING) { 1718 if (status & INTR_RX_PKT) 1719 alc_rxintr(sc); 1720 1721 if (status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | 1722 INTR_TXQ_TO_RST)) { 1723 if (status & INTR_DMA_RD_TO_RST) 1724 printf("%s: DMA read error! -- resetting\n", 1725 sc->sc_dev.dv_xname); 1726 if (status & INTR_DMA_WR_TO_RST) 1727 printf("%s: DMA write error! -- resetting\n", 1728 sc->sc_dev.dv_xname); 1729 if (status & INTR_TXQ_TO_RST) 1730 printf("%s: TxQ reset! -- resetting\n", 1731 sc->sc_dev.dv_xname); 1732 alc_init(ifp); 1733 return (0); 1734 } 1735 1736 if (status & INTR_TX_PKT) 1737 alc_txeof(sc); 1738 1739 alc_start(ifp); 1740 } 1741 1742 claimed = 1; 1743 back: 1744 /* Re-enable interrupts. */ 1745 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0x7FFFFFFF); 1746 return (claimed); 1747 } 1748 1749 void 1750 alc_txeof(struct alc_softc *sc) 1751 { 1752 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1753 struct alc_txdesc *txd; 1754 uint32_t cons, prod; 1755 int prog; 1756 1757 if (sc->alc_cdata.alc_tx_cnt == 0) 1758 return; 1759 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0, 1760 sc->alc_cdata.alc_tx_ring_map->dm_mapsize, 1761 BUS_DMASYNC_POSTWRITE); 1762 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 1763 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0, 1764 sc->alc_cdata.alc_cmb_map->dm_mapsize, 1765 BUS_DMASYNC_POSTREAD); 1766 prod = sc->alc_rdata.alc_cmb->cons; 1767 } else 1768 prod = CSR_READ_4(sc, ALC_MBOX_TD_CONS_IDX); 1769 /* Assume we're using normal Tx priority queue. */ 1770 prod = (prod & MBOX_TD_CONS_LO_IDX_MASK) >> 1771 MBOX_TD_CONS_LO_IDX_SHIFT; 1772 cons = sc->alc_cdata.alc_tx_cons; 1773 /* 1774 * Go through our Tx list and free mbufs for those 1775 * frames which have been transmitted. 1776 */ 1777 for (prog = 0; cons != prod; prog++, 1778 ALC_DESC_INC(cons, ALC_TX_RING_CNT)) { 1779 if (sc->alc_cdata.alc_tx_cnt <= 0) 1780 break; 1781 prog++; 1782 ifp->if_flags &= ~IFF_OACTIVE; 1783 sc->alc_cdata.alc_tx_cnt--; 1784 txd = &sc->alc_cdata.alc_txdesc[cons]; 1785 if (txd->tx_m != NULL) { 1786 /* Reclaim transmitted mbufs. */ 1787 bus_dmamap_sync(sc->sc_dmat, txd->tx_dmamap, 0, 1788 txd->tx_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1789 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1790 m_freem(txd->tx_m); 1791 txd->tx_m = NULL; 1792 } 1793 } 1794 1795 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 1796 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0, 1797 sc->alc_cdata.alc_cmb_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1798 sc->alc_cdata.alc_tx_cons = cons; 1799 /* 1800 * Unarm watchdog timer only when there is no pending 1801 * frames in Tx queue. 1802 */ 1803 if (sc->alc_cdata.alc_tx_cnt == 0) 1804 ifp->if_timer = 0; 1805 } 1806 1807 int 1808 alc_newbuf(struct alc_softc *sc, struct alc_rxdesc *rxd) 1809 { 1810 struct mbuf *m; 1811 bus_dmamap_t map; 1812 int error; 1813 1814 MGETHDR(m, M_DONTWAIT, MT_DATA); 1815 if (m == NULL) 1816 return (ENOBUFS); 1817 MCLGET(m, M_DONTWAIT); 1818 if (!(m->m_flags & M_EXT)) { 1819 m_freem(m); 1820 return (ENOBUFS); 1821 } 1822 1823 m->m_len = m->m_pkthdr.len = RX_BUF_SIZE_MAX; 1824 1825 error = bus_dmamap_load_mbuf(sc->sc_dmat, 1826 sc->alc_cdata.alc_rx_sparemap, m, BUS_DMA_NOWAIT); 1827 1828 if (error != 0) { 1829 m_freem(m); 1830 printf("%s: can't load RX mbuf\n", sc->sc_dev.dv_xname); 1831 return (error); 1832 } 1833 1834 if (rxd->rx_m != NULL) { 1835 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0, 1836 rxd->rx_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1837 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 1838 } 1839 map = rxd->rx_dmamap; 1840 rxd->rx_dmamap = sc->alc_cdata.alc_rx_sparemap; 1841 sc->alc_cdata.alc_rx_sparemap = map; 1842 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0, rxd->rx_dmamap->dm_mapsize, 1843 BUS_DMASYNC_PREREAD); 1844 rxd->rx_m = m; 1845 rxd->rx_desc->addr = htole64(rxd->rx_dmamap->dm_segs[0].ds_addr); 1846 return (0); 1847 } 1848 1849 void 1850 alc_rxintr(struct alc_softc *sc) 1851 { 1852 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1853 struct rx_rdesc *rrd; 1854 uint32_t nsegs, status; 1855 int rr_cons, prog; 1856 1857 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 0, 1858 sc->alc_cdata.alc_rr_ring_map->dm_mapsize, 1859 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1860 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 0, 1861 sc->alc_cdata.alc_rx_ring_map->dm_mapsize, 1862 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1863 rr_cons = sc->alc_cdata.alc_rr_cons; 1864 for (prog = 0; (ifp->if_flags & IFF_RUNNING) != 0;) { 1865 rrd = &sc->alc_rdata.alc_rr_ring[rr_cons]; 1866 status = letoh32(rrd->status); 1867 if ((status & RRD_VALID) == 0) 1868 break; 1869 nsegs = RRD_RD_CNT(letoh32(rrd->rdinfo)); 1870 if (nsegs == 0) { 1871 /* This should not happen! */ 1872 if (alcdebug) 1873 printf("%s: unexpected segment count -- " 1874 "resetting\n", sc->sc_dev.dv_xname); 1875 break; 1876 } 1877 alc_rxeof(sc, rrd); 1878 /* Clear Rx return status. */ 1879 rrd->status = 0; 1880 ALC_DESC_INC(rr_cons, ALC_RR_RING_CNT); 1881 sc->alc_cdata.alc_rx_cons += nsegs; 1882 sc->alc_cdata.alc_rx_cons %= ALC_RR_RING_CNT; 1883 prog += nsegs; 1884 } 1885 1886 if (prog > 0) { 1887 /* Update the consumer index. */ 1888 sc->alc_cdata.alc_rr_cons = rr_cons; 1889 /* Sync Rx return descriptors. */ 1890 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 0, 1891 sc->alc_cdata.alc_rr_ring_map->dm_mapsize, 1892 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1893 /* 1894 * Sync updated Rx descriptors such that controller see 1895 * modified buffer addresses. 1896 */ 1897 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 0, 1898 sc->alc_cdata.alc_rx_ring_map->dm_mapsize, 1899 BUS_DMASYNC_PREWRITE); 1900 /* 1901 * Let controller know availability of new Rx buffers. 1902 * Since alc(4) use RXQ_CFG_RD_BURST_DEFAULT descriptors 1903 * it may be possible to update ALC_MBOX_RD0_PROD_IDX 1904 * only when Rx buffer pre-fetching is required. In 1905 * addition we already set ALC_RX_RD_FREE_THRESH to 1906 * RX_RD_FREE_THRESH_LO_DEFAULT descriptors. However 1907 * it still seems that pre-fetching needs more 1908 * experimentation. 1909 */ 1910 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 1911 sc->alc_cdata.alc_rx_cons); 1912 } 1913 } 1914 1915 /* Receive a frame. */ 1916 void 1917 alc_rxeof(struct alc_softc *sc, struct rx_rdesc *rrd) 1918 { 1919 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1920 struct alc_rxdesc *rxd; 1921 struct mbuf *mp, *m; 1922 uint32_t rdinfo, status; 1923 int count, nsegs, rx_cons; 1924 1925 status = letoh32(rrd->status); 1926 rdinfo = letoh32(rrd->rdinfo); 1927 rx_cons = RRD_RD_IDX(rdinfo); 1928 nsegs = RRD_RD_CNT(rdinfo); 1929 1930 sc->alc_cdata.alc_rxlen = RRD_BYTES(status); 1931 if (status & (RRD_ERR_SUM | RRD_ERR_LENGTH)) { 1932 /* 1933 * We want to pass the following frames to upper 1934 * layer regardless of error status of Rx return 1935 * ring. 1936 * 1937 * o IP/TCP/UDP checksum is bad. 1938 * o frame length and protocol specific length 1939 * does not match. 1940 * 1941 * Force network stack compute checksum for 1942 * errored frames. 1943 */ 1944 if ((status & (RRD_ERR_CRC | RRD_ERR_ALIGN | 1945 RRD_ERR_TRUNC | RRD_ERR_RUNT)) != 0) 1946 return; 1947 } 1948 1949 for (count = 0; count < nsegs; count++, 1950 ALC_DESC_INC(rx_cons, ALC_RX_RING_CNT)) { 1951 rxd = &sc->alc_cdata.alc_rxdesc[rx_cons]; 1952 mp = rxd->rx_m; 1953 /* Add a new receive buffer to the ring. */ 1954 if (alc_newbuf(sc, rxd) != 0) { 1955 ifp->if_iqdrops++; 1956 /* Reuse Rx buffers. */ 1957 if (sc->alc_cdata.alc_rxhead != NULL) 1958 m_freem(sc->alc_cdata.alc_rxhead); 1959 break; 1960 } 1961 1962 /* 1963 * Assume we've received a full sized frame. 1964 * Actual size is fixed when we encounter the end of 1965 * multi-segmented frame. 1966 */ 1967 mp->m_len = sc->alc_buf_size; 1968 1969 /* Chain received mbufs. */ 1970 if (sc->alc_cdata.alc_rxhead == NULL) { 1971 sc->alc_cdata.alc_rxhead = mp; 1972 sc->alc_cdata.alc_rxtail = mp; 1973 } else { 1974 mp->m_flags &= ~M_PKTHDR; 1975 sc->alc_cdata.alc_rxprev_tail = 1976 sc->alc_cdata.alc_rxtail; 1977 sc->alc_cdata.alc_rxtail->m_next = mp; 1978 sc->alc_cdata.alc_rxtail = mp; 1979 } 1980 1981 if (count == nsegs - 1) { 1982 /* Last desc. for this frame. */ 1983 m = sc->alc_cdata.alc_rxhead; 1984 m->m_flags |= M_PKTHDR; 1985 /* 1986 * It seems that L1C/L2C controller has no way 1987 * to tell hardware to strip CRC bytes. 1988 */ 1989 m->m_pkthdr.len = 1990 sc->alc_cdata.alc_rxlen - ETHER_CRC_LEN; 1991 if (nsegs > 1) { 1992 /* Set last mbuf size. */ 1993 mp->m_len = sc->alc_cdata.alc_rxlen - 1994 (nsegs - 1) * sc->alc_buf_size; 1995 /* Remove the CRC bytes in chained mbufs. */ 1996 if (mp->m_len <= ETHER_CRC_LEN) { 1997 sc->alc_cdata.alc_rxtail = 1998 sc->alc_cdata.alc_rxprev_tail; 1999 sc->alc_cdata.alc_rxtail->m_len -= 2000 (ETHER_CRC_LEN - mp->m_len); 2001 sc->alc_cdata.alc_rxtail->m_next = NULL; 2002 m_freem(mp); 2003 } else { 2004 mp->m_len -= ETHER_CRC_LEN; 2005 } 2006 } else 2007 m->m_len = m->m_pkthdr.len; 2008 m->m_pkthdr.rcvif = ifp; 2009 /* 2010 * Due to hardware bugs, Rx checksum offloading 2011 * was intentionally disabled. 2012 */ 2013 #if NVLAN > 0 2014 if (status & RRD_VLAN_TAG) { 2015 u_int32_t vtag = RRD_VLAN(letoh32(rrd->vtag)); 2016 m->m_pkthdr.ether_vtag = ntohs(vtag); 2017 m->m_flags |= M_VLANTAG; 2018 } 2019 #endif 2020 2021 #if NBPFILTER > 0 2022 if (ifp->if_bpf) 2023 bpf_mtap_ether(ifp->if_bpf, m, 2024 BPF_DIRECTION_IN); 2025 #endif 2026 2027 { 2028 /* Pass it on. */ 2029 ether_input_mbuf(ifp, m); 2030 } 2031 } 2032 } 2033 /* Reset mbuf chains. */ 2034 ALC_RXCHAIN_RESET(sc); 2035 } 2036 2037 void 2038 alc_tick(void *xsc) 2039 { 2040 struct alc_softc *sc = xsc; 2041 struct mii_data *mii = &sc->sc_miibus; 2042 int s; 2043 2044 s = splnet(); 2045 mii_tick(mii); 2046 alc_stats_update(sc); 2047 2048 timeout_add_sec(&sc->alc_tick_ch, 1); 2049 splx(s); 2050 } 2051 2052 void 2053 alc_reset(struct alc_softc *sc) 2054 { 2055 uint32_t reg; 2056 int i; 2057 2058 reg = CSR_READ_4(sc, ALC_MASTER_CFG) & 0xFFFF; 2059 reg |= MASTER_OOB_DIS_OFF | MASTER_RESET; 2060 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 2061 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 2062 DELAY(10); 2063 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0) 2064 break; 2065 } 2066 if (i == 0) 2067 printf("%s: master reset timeout!\n", sc->sc_dev.dv_xname); 2068 2069 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 2070 if ((reg = CSR_READ_4(sc, ALC_IDLE_STATUS)) == 0) 2071 break; 2072 DELAY(10); 2073 } 2074 2075 if (i == 0) 2076 printf("%s: reset timeout(0x%08x)!\n", sc->sc_dev.dv_xname, 2077 reg); 2078 } 2079 2080 int 2081 alc_init(struct ifnet *ifp) 2082 { 2083 struct alc_softc *sc = ifp->if_softc; 2084 struct mii_data *mii; 2085 uint8_t eaddr[ETHER_ADDR_LEN]; 2086 bus_addr_t paddr; 2087 uint32_t reg, rxf_hi, rxf_lo; 2088 int error; 2089 2090 /* 2091 * Cancel any pending I/O. 2092 */ 2093 alc_stop(sc); 2094 /* 2095 * Reset the chip to a known state. 2096 */ 2097 alc_reset(sc); 2098 2099 /* Initialize Rx descriptors. */ 2100 error = alc_init_rx_ring(sc); 2101 if (error != 0) { 2102 printf("%s: no memory for Rx buffers.\n", sc->sc_dev.dv_xname); 2103 alc_stop(sc); 2104 return (error); 2105 } 2106 alc_init_rr_ring(sc); 2107 alc_init_tx_ring(sc); 2108 alc_init_cmb(sc); 2109 alc_init_smb(sc); 2110 2111 /* Enable all clocks. */ 2112 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, 0); 2113 2114 /* Reprogram the station address. */ 2115 bcopy(LLADDR(ifp->if_sadl), eaddr, ETHER_ADDR_LEN); 2116 CSR_WRITE_4(sc, ALC_PAR0, 2117 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 2118 CSR_WRITE_4(sc, ALC_PAR1, eaddr[0] << 8 | eaddr[1]); 2119 /* 2120 * Clear WOL status and disable all WOL feature as WOL 2121 * would interfere Rx operation under normal environments. 2122 */ 2123 CSR_READ_4(sc, ALC_WOL_CFG); 2124 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 2125 /* Set Tx descriptor base addresses. */ 2126 paddr = sc->alc_rdata.alc_tx_ring_paddr; 2127 CSR_WRITE_4(sc, ALC_TX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 2128 CSR_WRITE_4(sc, ALC_TDL_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 2129 /* We don't use high priority ring. */ 2130 CSR_WRITE_4(sc, ALC_TDH_HEAD_ADDR_LO, 0); 2131 /* Set Tx descriptor counter. */ 2132 CSR_WRITE_4(sc, ALC_TD_RING_CNT, 2133 (ALC_TX_RING_CNT << TD_RING_CNT_SHIFT) & TD_RING_CNT_MASK); 2134 /* Set Rx descriptor base addresses. */ 2135 paddr = sc->alc_rdata.alc_rx_ring_paddr; 2136 CSR_WRITE_4(sc, ALC_RX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 2137 CSR_WRITE_4(sc, ALC_RD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 2138 /* We use one Rx ring. */ 2139 CSR_WRITE_4(sc, ALC_RD1_HEAD_ADDR_LO, 0); 2140 CSR_WRITE_4(sc, ALC_RD2_HEAD_ADDR_LO, 0); 2141 CSR_WRITE_4(sc, ALC_RD3_HEAD_ADDR_LO, 0); 2142 /* Set Rx descriptor counter. */ 2143 CSR_WRITE_4(sc, ALC_RD_RING_CNT, 2144 (ALC_RX_RING_CNT << RD_RING_CNT_SHIFT) & RD_RING_CNT_MASK); 2145 2146 /* 2147 * Let hardware split jumbo frames into alc_max_buf_sized chunks. 2148 * if it do not fit the buffer size. Rx return descriptor holds 2149 * a counter that indicates how many fragments were made by the 2150 * hardware. The buffer size should be multiple of 8 bytes. 2151 * Since hardware has limit on the size of buffer size, always 2152 * use the maximum value. 2153 * For strict-alignment architectures make sure to reduce buffer 2154 * size by 8 bytes to make room for alignment fixup. 2155 */ 2156 sc->alc_buf_size = RX_BUF_SIZE_MAX; 2157 CSR_WRITE_4(sc, ALC_RX_BUF_SIZE, sc->alc_buf_size); 2158 2159 paddr = sc->alc_rdata.alc_rr_ring_paddr; 2160 /* Set Rx return descriptor base addresses. */ 2161 CSR_WRITE_4(sc, ALC_RRD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 2162 /* We use one Rx return ring. */ 2163 CSR_WRITE_4(sc, ALC_RRD1_HEAD_ADDR_LO, 0); 2164 CSR_WRITE_4(sc, ALC_RRD2_HEAD_ADDR_LO, 0); 2165 CSR_WRITE_4(sc, ALC_RRD3_HEAD_ADDR_LO, 0); 2166 /* Set Rx return descriptor counter. */ 2167 CSR_WRITE_4(sc, ALC_RRD_RING_CNT, 2168 (ALC_RR_RING_CNT << RRD_RING_CNT_SHIFT) & RRD_RING_CNT_MASK); 2169 paddr = sc->alc_rdata.alc_cmb_paddr; 2170 CSR_WRITE_4(sc, ALC_CMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 2171 paddr = sc->alc_rdata.alc_smb_paddr; 2172 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 2173 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 2174 2175 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1) { 2176 /* Reconfigure SRAM - Vendor magic. */ 2177 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_LEN, 0x000002A0); 2178 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_LEN, 0x00000100); 2179 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_ADDR, 0x029F0000); 2180 CSR_WRITE_4(sc, ALC_SRAM_RD0_ADDR, 0x02BF02A0); 2181 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_ADDR, 0x03BF02C0); 2182 CSR_WRITE_4(sc, ALC_SRAM_TD_ADDR, 0x03DF03C0); 2183 CSR_WRITE_4(sc, ALC_TXF_WATER_MARK, 0x00000000); 2184 CSR_WRITE_4(sc, ALC_RD_DMA_CFG, 0x00000000); 2185 } 2186 2187 /* Tell hardware that we're ready to load DMA blocks. */ 2188 CSR_WRITE_4(sc, ALC_DMA_BLOCK, DMA_BLOCK_LOAD); 2189 2190 /* Configure interrupt moderation timer. */ 2191 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 2192 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 2193 reg = ALC_USECS(sc->alc_int_rx_mod) << IM_TIMER_RX_SHIFT; 2194 reg |= ALC_USECS(sc->alc_int_tx_mod) << IM_TIMER_TX_SHIFT; 2195 CSR_WRITE_4(sc, ALC_IM_TIMER, reg); 2196 /* 2197 * We don't want to automatic interrupt clear as task queue 2198 * for the interrupt should know interrupt status. 2199 */ 2200 reg = MASTER_SA_TIMER_ENB; 2201 if (ALC_USECS(sc->alc_int_rx_mod) != 0) 2202 reg |= MASTER_IM_RX_TIMER_ENB; 2203 if (ALC_USECS(sc->alc_int_tx_mod) != 0) 2204 reg |= MASTER_IM_TX_TIMER_ENB; 2205 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 2206 /* 2207 * Disable interrupt re-trigger timer. We don't want automatic 2208 * re-triggering of un-ACKed interrupts. 2209 */ 2210 CSR_WRITE_4(sc, ALC_INTR_RETRIG_TIMER, ALC_USECS(0)); 2211 /* Configure CMB. */ 2212 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 2213 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, 4); 2214 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(5000)); 2215 } else 2216 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(0)); 2217 /* 2218 * Hardware can be configured to issue SMB interrupt based 2219 * on programmed interval. Since there is a callout that is 2220 * invoked for every hz in driver we use that instead of 2221 * relying on periodic SMB interrupt. 2222 */ 2223 CSR_WRITE_4(sc, ALC_SMB_STAT_TIMER, ALC_USECS(0)); 2224 /* Clear MAC statistics. */ 2225 alc_stats_clear(sc); 2226 2227 /* 2228 * Always use maximum frame size that controller can support. 2229 * Otherwise received frames that has larger frame length 2230 * than alc(4) MTU would be silently dropped in hardware. This 2231 * would make path-MTU discovery hard as sender wouldn't get 2232 * any responses from receiver. alc(4) supports 2233 * multi-fragmented frames on Rx path so it has no issue on 2234 * assembling fragmented frames. Using maximum frame size also 2235 * removes the need to reinitialize hardware when interface 2236 * MTU configuration was changed. 2237 * 2238 * Be conservative in what you do, be liberal in what you 2239 * accept from others - RFC 793. 2240 */ 2241 CSR_WRITE_4(sc, ALC_FRAME_SIZE, sc->alc_max_framelen); 2242 2243 /* Disable header split(?) */ 2244 CSR_WRITE_4(sc, ALC_HDS_CFG, 0); 2245 2246 /* Configure IPG/IFG parameters. */ 2247 CSR_WRITE_4(sc, ALC_IPG_IFG_CFG, 2248 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) | 2249 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 2250 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 2251 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK)); 2252 /* Set parameters for half-duplex media. */ 2253 CSR_WRITE_4(sc, ALC_HDPX_CFG, 2254 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 2255 HDPX_CFG_LCOL_MASK) | 2256 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 2257 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 2258 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 2259 HDPX_CFG_ABEBT_MASK) | 2260 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 2261 HDPX_CFG_JAMIPG_MASK)); 2262 /* 2263 * Set TSO/checksum offload threshold. For frames that is 2264 * larger than this threshold, hardware wouldn't do 2265 * TSO/checksum offloading. 2266 */ 2267 CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH, 2268 (sc->alc_max_framelen >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) & 2269 TSO_OFFLOAD_THRESH_MASK); 2270 /* Configure TxQ. */ 2271 reg = (alc_dma_burst[sc->alc_dma_rd_burst] << 2272 TXQ_CFG_TX_FIFO_BURST_SHIFT) & TXQ_CFG_TX_FIFO_BURST_MASK; 2273 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1 || 2274 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_2) 2275 reg >>= 1; 2276 reg |= (TXQ_CFG_TD_BURST_DEFAULT << TXQ_CFG_TD_BURST_SHIFT) & 2277 TXQ_CFG_TD_BURST_MASK; 2278 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE); 2279 2280 /* Configure Rx free descriptor pre-fetching. */ 2281 CSR_WRITE_4(sc, ALC_RX_RD_FREE_THRESH, 2282 ((RX_RD_FREE_THRESH_HI_DEFAULT << RX_RD_FREE_THRESH_HI_SHIFT) & 2283 RX_RD_FREE_THRESH_HI_MASK) | 2284 ((RX_RD_FREE_THRESH_LO_DEFAULT << RX_RD_FREE_THRESH_LO_SHIFT) & 2285 RX_RD_FREE_THRESH_LO_MASK)); 2286 2287 /* 2288 * Configure flow control parameters. 2289 * XON : 80% of Rx FIFO 2290 * XOFF : 30% of Rx FIFO 2291 */ 2292 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1C || 2293 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C) { 2294 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 2295 rxf_hi = (reg * 8) / 10; 2296 rxf_lo = (reg * 3) / 10; 2297 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 2298 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 2299 RX_FIFO_PAUSE_THRESH_LO_MASK) | 2300 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 2301 RX_FIFO_PAUSE_THRESH_HI_MASK)); 2302 } 2303 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D_1 || 2304 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1) 2305 CSR_WRITE_4(sc, ALC_SERDES_LOCK, 2306 CSR_READ_4(sc, ALC_SERDES_LOCK) | SERDES_MAC_CLK_SLOWDOWN | 2307 SERDES_PHY_CLK_SLOWDOWN); 2308 2309 /* Disable RSS until I understand L1C/L2C's RSS logic. */ 2310 CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0); 2311 CSR_WRITE_4(sc, ALC_RSS_CPU, 0); 2312 2313 /* Configure RxQ. */ 2314 reg = (RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 2315 RXQ_CFG_RD_BURST_MASK; 2316 reg |= RXQ_CFG_RSS_MODE_DIS; 2317 if ((sc->alc_flags & ALC_FLAG_ASPM_MON) != 0) 2318 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_1M; 2319 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 2320 2321 /* Configure DMA parameters. */ 2322 reg = DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI; 2323 reg |= sc->alc_rcb; 2324 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 2325 reg |= DMA_CFG_CMB_ENB; 2326 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) 2327 reg |= DMA_CFG_SMB_ENB; 2328 else 2329 reg |= DMA_CFG_SMB_DIS; 2330 reg |= (sc->alc_dma_rd_burst & DMA_CFG_RD_BURST_MASK) << 2331 DMA_CFG_RD_BURST_SHIFT; 2332 reg |= (sc->alc_dma_wr_burst & DMA_CFG_WR_BURST_MASK) << 2333 DMA_CFG_WR_BURST_SHIFT; 2334 reg |= (DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 2335 DMA_CFG_RD_DELAY_CNT_MASK; 2336 reg |= (DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 2337 DMA_CFG_WR_DELAY_CNT_MASK; 2338 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 2339 2340 /* 2341 * Configure Tx/Rx MACs. 2342 * - Auto-padding for short frames. 2343 * - Enable CRC generation. 2344 * Actual reconfiguration of MAC for resolved speed/duplex 2345 * is followed after detection of link establishment. 2346 * AR813x/AR815x always does checksum computation regardless 2347 * of MAC_CFG_RXCSUM_ENB bit. Also the controller is known to 2348 * have bug in protocol field in Rx return structure so 2349 * these controllers can't handle fragmented frames. Disable 2350 * Rx checksum offloading until there is a newer controller 2351 * that has sane implementation. 2352 */ 2353 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 2354 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 2355 MAC_CFG_PREAMBLE_MASK); 2356 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D || 2357 sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D_1 || 2358 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_2) 2359 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 2360 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0) 2361 reg |= MAC_CFG_SPEED_10_100; 2362 else 2363 reg |= MAC_CFG_SPEED_1000; 2364 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 2365 2366 /* Set up the receive filter. */ 2367 alc_iff(sc); 2368 2369 alc_rxvlan(sc); 2370 2371 /* Acknowledge all pending interrupts and clear it. */ 2372 CSR_WRITE_4(sc, ALC_INTR_MASK, ALC_INTRS); 2373 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 2374 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0); 2375 2376 sc->alc_flags &= ~ALC_FLAG_LINK; 2377 /* Switch to the current media. */ 2378 mii = &sc->sc_miibus; 2379 mii_mediachg(mii); 2380 2381 timeout_add_sec(&sc->alc_tick_ch, 1); 2382 2383 ifp->if_flags |= IFF_RUNNING; 2384 ifp->if_flags &= ~IFF_OACTIVE; 2385 2386 return (0); 2387 } 2388 2389 void 2390 alc_stop(struct alc_softc *sc) 2391 { 2392 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 2393 struct alc_txdesc *txd; 2394 struct alc_rxdesc *rxd; 2395 uint32_t reg; 2396 int i; 2397 2398 /* 2399 * Mark the interface down and cancel the watchdog timer. 2400 */ 2401 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2402 ifp->if_timer = 0; 2403 2404 timeout_del(&sc->alc_tick_ch); 2405 sc->alc_flags &= ~ALC_FLAG_LINK; 2406 2407 alc_stats_update(sc); 2408 2409 /* Disable interrupts. */ 2410 CSR_WRITE_4(sc, ALC_INTR_MASK, 0); 2411 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 2412 alc_stop_queue(sc); 2413 2414 /* Disable DMA. */ 2415 reg = CSR_READ_4(sc, ALC_DMA_CFG); 2416 reg &= ~(DMA_CFG_CMB_ENB | DMA_CFG_SMB_ENB); 2417 reg |= DMA_CFG_SMB_DIS; 2418 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 2419 DELAY(1000); 2420 2421 /* Stop Rx/Tx MACs. */ 2422 alc_stop_mac(sc); 2423 2424 /* Disable interrupts which might be touched in taskq handler. */ 2425 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 2426 2427 /* Reclaim Rx buffers that have been processed. */ 2428 if (sc->alc_cdata.alc_rxhead != NULL) 2429 m_freem(sc->alc_cdata.alc_rxhead); 2430 ALC_RXCHAIN_RESET(sc); 2431 /* 2432 * Free Tx/Rx mbufs still in the queues. 2433 */ 2434 for (i = 0; i < ALC_RX_RING_CNT; i++) { 2435 rxd = &sc->alc_cdata.alc_rxdesc[i]; 2436 if (rxd->rx_m != NULL) { 2437 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0, 2438 rxd->rx_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2439 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 2440 m_freem(rxd->rx_m); 2441 rxd->rx_m = NULL; 2442 } 2443 } 2444 for (i = 0; i < ALC_TX_RING_CNT; i++) { 2445 txd = &sc->alc_cdata.alc_txdesc[i]; 2446 if (txd->tx_m != NULL) { 2447 bus_dmamap_sync(sc->sc_dmat, txd->tx_dmamap, 0, 2448 txd->tx_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2449 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 2450 m_freem(txd->tx_m); 2451 txd->tx_m = NULL; 2452 } 2453 } 2454 } 2455 2456 void 2457 alc_stop_mac(struct alc_softc *sc) 2458 { 2459 uint32_t reg; 2460 int i; 2461 2462 /* Disable Rx/Tx MAC. */ 2463 reg = CSR_READ_4(sc, ALC_MAC_CFG); 2464 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 2465 reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 2466 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 2467 } 2468 for (i = ALC_TIMEOUT; i > 0; i--) { 2469 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 2470 if (reg == 0) 2471 break; 2472 DELAY(10); 2473 } 2474 if (i == 0) 2475 printf("%s: could not disable Rx/Tx MAC(0x%08x)!\n", 2476 sc->sc_dev.dv_xname, reg); 2477 } 2478 2479 void 2480 alc_start_queue(struct alc_softc *sc) 2481 { 2482 uint32_t qcfg[] = { 2483 0, 2484 RXQ_CFG_QUEUE0_ENB, 2485 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB, 2486 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | RXQ_CFG_QUEUE2_ENB, 2487 RXQ_CFG_ENB 2488 }; 2489 uint32_t cfg; 2490 2491 /* Enable RxQ. */ 2492 cfg = CSR_READ_4(sc, ALC_RXQ_CFG); 2493 cfg &= ~RXQ_CFG_ENB; 2494 cfg |= qcfg[1]; 2495 CSR_WRITE_4(sc, ALC_RXQ_CFG, cfg); 2496 /* Enable TxQ. */ 2497 cfg = CSR_READ_4(sc, ALC_TXQ_CFG); 2498 cfg |= TXQ_CFG_ENB; 2499 CSR_WRITE_4(sc, ALC_TXQ_CFG, cfg); 2500 } 2501 2502 void 2503 alc_stop_queue(struct alc_softc *sc) 2504 { 2505 uint32_t reg; 2506 int i; 2507 2508 /* Disable RxQ. */ 2509 reg = CSR_READ_4(sc, ALC_RXQ_CFG); 2510 if ((reg & RXQ_CFG_ENB) != 0) { 2511 reg &= ~RXQ_CFG_ENB; 2512 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 2513 } 2514 /* Disable TxQ. */ 2515 reg = CSR_READ_4(sc, ALC_TXQ_CFG); 2516 if ((reg & TXQ_CFG_ENB) != 0) { 2517 reg &= ~TXQ_CFG_ENB; 2518 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg); 2519 } 2520 for (i = ALC_TIMEOUT; i > 0; i--) { 2521 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 2522 if ((reg & (IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 2523 break; 2524 DELAY(10); 2525 } 2526 if (i == 0) 2527 printf("%s: could not disable RxQ/TxQ (0x%08x)!\n", 2528 sc->sc_dev.dv_xname, reg); 2529 } 2530 2531 void 2532 alc_init_tx_ring(struct alc_softc *sc) 2533 { 2534 struct alc_ring_data *rd; 2535 struct alc_txdesc *txd; 2536 int i; 2537 2538 sc->alc_cdata.alc_tx_prod = 0; 2539 sc->alc_cdata.alc_tx_cons = 0; 2540 sc->alc_cdata.alc_tx_cnt = 0; 2541 2542 rd = &sc->alc_rdata; 2543 bzero(rd->alc_tx_ring, ALC_TX_RING_SZ); 2544 for (i = 0; i < ALC_TX_RING_CNT; i++) { 2545 txd = &sc->alc_cdata.alc_txdesc[i]; 2546 txd->tx_m = NULL; 2547 } 2548 2549 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0, 2550 sc->alc_cdata.alc_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2551 } 2552 2553 int 2554 alc_init_rx_ring(struct alc_softc *sc) 2555 { 2556 struct alc_ring_data *rd; 2557 struct alc_rxdesc *rxd; 2558 int i; 2559 2560 sc->alc_cdata.alc_rx_cons = ALC_RX_RING_CNT - 1; 2561 rd = &sc->alc_rdata; 2562 bzero(rd->alc_rx_ring, ALC_RX_RING_SZ); 2563 for (i = 0; i < ALC_RX_RING_CNT; i++) { 2564 rxd = &sc->alc_cdata.alc_rxdesc[i]; 2565 rxd->rx_m = NULL; 2566 rxd->rx_desc = &rd->alc_rx_ring[i]; 2567 if (alc_newbuf(sc, rxd) != 0) 2568 return (ENOBUFS); 2569 } 2570 2571 /* 2572 * Since controller does not update Rx descriptors, driver 2573 * does have to read Rx descriptors back so BUS_DMASYNC_PREWRITE 2574 * is enough to ensure coherence. 2575 */ 2576 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 0, 2577 sc->alc_cdata.alc_rx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2578 /* Let controller know availability of new Rx buffers. */ 2579 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, sc->alc_cdata.alc_rx_cons); 2580 2581 return (0); 2582 } 2583 2584 void 2585 alc_init_rr_ring(struct alc_softc *sc) 2586 { 2587 struct alc_ring_data *rd; 2588 2589 sc->alc_cdata.alc_rr_cons = 0; 2590 ALC_RXCHAIN_RESET(sc); 2591 2592 rd = &sc->alc_rdata; 2593 bzero(rd->alc_rr_ring, ALC_RR_RING_SZ); 2594 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 0, 2595 sc->alc_cdata.alc_rr_ring_map->dm_mapsize, 2596 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2597 } 2598 2599 void 2600 alc_init_cmb(struct alc_softc *sc) 2601 { 2602 struct alc_ring_data *rd; 2603 2604 rd = &sc->alc_rdata; 2605 bzero(rd->alc_cmb, ALC_CMB_SZ); 2606 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0, 2607 sc->alc_cdata.alc_cmb_map->dm_mapsize, 2608 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2609 } 2610 2611 void 2612 alc_init_smb(struct alc_softc *sc) 2613 { 2614 struct alc_ring_data *rd; 2615 2616 rd = &sc->alc_rdata; 2617 bzero(rd->alc_smb, ALC_SMB_SZ); 2618 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 2619 sc->alc_cdata.alc_smb_map->dm_mapsize, 2620 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2621 } 2622 2623 void 2624 alc_rxvlan(struct alc_softc *sc) 2625 { 2626 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 2627 uint32_t reg; 2628 2629 reg = CSR_READ_4(sc, ALC_MAC_CFG); 2630 if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) 2631 reg |= MAC_CFG_VLAN_TAG_STRIP; 2632 else 2633 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 2634 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 2635 } 2636 2637 void 2638 alc_iff(struct alc_softc *sc) 2639 { 2640 struct arpcom *ac = &sc->sc_arpcom; 2641 struct ifnet *ifp = &ac->ac_if; 2642 struct ether_multi *enm; 2643 struct ether_multistep step; 2644 uint32_t crc; 2645 uint32_t mchash[2]; 2646 uint32_t rxcfg; 2647 2648 rxcfg = CSR_READ_4(sc, ALC_MAC_CFG); 2649 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 2650 ifp->if_flags &= ~IFF_ALLMULTI; 2651 2652 /* 2653 * Always accept broadcast frames. 2654 */ 2655 rxcfg |= MAC_CFG_BCAST; 2656 2657 if (ifp->if_flags & IFF_PROMISC || ac->ac_multirangecnt > 0) { 2658 ifp->if_flags |= IFF_ALLMULTI; 2659 if (ifp->if_flags & IFF_PROMISC) 2660 rxcfg |= MAC_CFG_PROMISC; 2661 else 2662 rxcfg |= MAC_CFG_ALLMULTI; 2663 mchash[0] = mchash[1] = 0xFFFFFFFF; 2664 } else { 2665 /* Program new filter. */ 2666 bzero(mchash, sizeof(mchash)); 2667 2668 ETHER_FIRST_MULTI(step, ac, enm); 2669 while (enm != NULL) { 2670 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2671 2672 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 2673 2674 ETHER_NEXT_MULTI(step, enm); 2675 } 2676 } 2677 2678 CSR_WRITE_4(sc, ALC_MAR0, mchash[0]); 2679 CSR_WRITE_4(sc, ALC_MAR1, mchash[1]); 2680 CSR_WRITE_4(sc, ALC_MAC_CFG, rxcfg); 2681 } 2682