1 /* $OpenBSD: if_alc.c,v 1.2 2009/09/13 14:42:52 krw Exp $ */ 2 /*- 3 * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* Driver for Atheros AR8131/AR8132 PCIe Ethernet. */ 30 31 #include "bpfilter.h" 32 #include "vlan.h" 33 34 #include <sys/param.h> 35 #include <sys/proc.h> 36 #include <sys/endian.h> 37 #include <sys/systm.h> 38 #include <sys/types.h> 39 #include <sys/sockio.h> 40 #include <sys/mbuf.h> 41 #include <sys/queue.h> 42 #include <sys/kernel.h> 43 #include <sys/device.h> 44 #include <sys/timeout.h> 45 #include <sys/socket.h> 46 47 #include <machine/bus.h> 48 49 #include <net/if.h> 50 #include <net/if_dl.h> 51 #include <net/if_llc.h> 52 #include <net/if_media.h> 53 54 #ifdef INET 55 #include <netinet/in.h> 56 #include <netinet/in_systm.h> 57 #include <netinet/in_var.h> 58 #include <netinet/ip.h> 59 #include <netinet/if_ether.h> 60 #endif 61 62 #include <net/if_types.h> 63 #include <net/if_vlan_var.h> 64 65 #if NBPFILTER > 0 66 #include <net/bpf.h> 67 #endif 68 69 #include <dev/rndvar.h> 70 71 #include <dev/mii/mii.h> 72 #include <dev/mii/miivar.h> 73 74 #include <dev/pci/pcireg.h> 75 #include <dev/pci/pcivar.h> 76 #include <dev/pci/pcidevs.h> 77 78 #include <dev/pci/if_alcreg.h> 79 80 int alc_match(struct device *, void *, void *); 81 void alc_attach(struct device *, struct device *, void *); 82 int alc_detach(struct device *, int); 83 84 int alc_init(struct ifnet *); 85 void alc_start(struct ifnet *); 86 int alc_ioctl(struct ifnet *, u_long, caddr_t); 87 void alc_watchdog(struct ifnet *); 88 int alc_mediachange(struct ifnet *); 89 void alc_mediastatus(struct ifnet *, struct ifmediareq *); 90 91 void alc_aspm(struct alc_softc *); 92 void alc_disable_l0s_l1(struct alc_softc *); 93 int alc_dma_alloc(struct alc_softc *); 94 void alc_dma_free(struct alc_softc *); 95 int alc_encap(struct alc_softc *, struct mbuf **); 96 void alc_get_macaddr(struct alc_softc *); 97 void alc_init_cmb(struct alc_softc *); 98 void alc_init_rr_ring(struct alc_softc *); 99 int alc_init_rx_ring(struct alc_softc *); 100 void alc_init_smb(struct alc_softc *); 101 void alc_init_tx_ring(struct alc_softc *); 102 int alc_intr(void *); 103 void alc_mac_config(struct alc_softc *); 104 int alc_miibus_readreg(struct device *, int, int); 105 void alc_miibus_statchg(struct device *); 106 void alc_miibus_writereg(struct device *, int, int, int); 107 int alc_newbuf(struct alc_softc *, struct alc_rxdesc *, int); 108 void alc_phy_down(struct alc_softc *); 109 void alc_phy_reset(struct alc_softc *); 110 void alc_reset(struct alc_softc *); 111 void alc_rxeof(struct alc_softc *, struct rx_rdesc *); 112 int alc_rxintr(struct alc_softc *); 113 void alc_rxfilter(struct alc_softc *); 114 void alc_rxvlan(struct alc_softc *); 115 void alc_start_queue(struct alc_softc *); 116 void alc_stats_clear(struct alc_softc *); 117 void alc_stats_update(struct alc_softc *); 118 void alc_stop(struct alc_softc *); 119 void alc_stop_mac(struct alc_softc *); 120 void alc_stop_queue(struct alc_softc *); 121 void alc_tick(void *); 122 void alc_txeof(struct alc_softc *); 123 124 uint32_t alc_dma_burst[] = { 128, 256, 512, 1024, 2048, 4096, 0 }; 125 126 const struct pci_matchid alc_devices[] = { 127 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L1C }, 128 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L2C } 129 }; 130 131 struct cfattach alc_ca = { 132 sizeof (struct alc_softc), alc_match, alc_attach 133 }; 134 135 struct cfdriver alc_cd = { 136 NULL, "alc", DV_IFNET 137 }; 138 139 int alcdebug = 0; 140 #define DPRINTF(x) do { if (alcdebug) printf x; } while (0) 141 142 #define ALC_CSUM_FEATURES (M_TCPV4_CSUM_OUT | M_UDPV4_CSUM_OUT) 143 144 int 145 alc_miibus_readreg(struct device *dev, int phy, int reg) 146 { 147 struct alc_softc *sc = (struct alc_softc *)dev; 148 uint32_t v; 149 int i; 150 151 if (phy != sc->alc_phyaddr) 152 return (0); 153 154 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 155 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 156 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 157 DELAY(5); 158 v = CSR_READ_4(sc, ALC_MDIO); 159 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 160 break; 161 } 162 163 if (i == 0) { 164 printf("%s: phy read timeout: phy %d, reg %d\n", 165 sc->sc_dev.dv_xname, phy, reg); 166 return (0); 167 } 168 169 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 170 } 171 172 void 173 alc_miibus_writereg(struct device *dev, int phy, int reg, int val) 174 { 175 struct alc_softc *sc = (struct alc_softc *)dev; 176 uint32_t v; 177 int i; 178 179 if (phy != sc->alc_phyaddr) 180 return; 181 182 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 183 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 184 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 185 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 186 DELAY(5); 187 v = CSR_READ_4(sc, ALC_MDIO); 188 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 189 break; 190 } 191 192 if (i == 0) 193 printf("%s: phy write timeout: phy %d, reg %d\n", 194 sc->sc_dev.dv_xname, phy, reg); 195 } 196 197 void 198 alc_miibus_statchg(struct device *dev) 199 { 200 struct alc_softc *sc = (struct alc_softc *)dev; 201 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 202 struct mii_data *mii; 203 uint32_t reg; 204 205 if ((ifp->if_flags & IFF_RUNNING) == 0) 206 return; 207 208 mii = &sc->sc_miibus; 209 210 sc->alc_flags &= ~ALC_FLAG_LINK; 211 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 212 (IFM_ACTIVE | IFM_AVALID)) { 213 switch (IFM_SUBTYPE(mii->mii_media_active)) { 214 case IFM_10_T: 215 case IFM_100_TX: 216 sc->alc_flags |= ALC_FLAG_LINK; 217 break; 218 case IFM_1000_T: 219 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 220 sc->alc_flags |= ALC_FLAG_LINK; 221 break; 222 default: 223 break; 224 } 225 } 226 alc_stop_queue(sc); 227 /* Stop Rx/Tx MACs. */ 228 alc_stop_mac(sc); 229 230 /* Program MACs with resolved speed/duplex/flow-control. */ 231 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 232 alc_start_queue(sc); 233 alc_mac_config(sc); 234 /* Re-enable Tx/Rx MACs. */ 235 reg = CSR_READ_4(sc, ALC_MAC_CFG); 236 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 237 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 238 } 239 alc_aspm(sc); 240 } 241 242 void 243 alc_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 244 { 245 struct alc_softc *sc = ifp->if_softc; 246 struct mii_data *mii = &sc->sc_miibus; 247 248 mii_pollstat(mii); 249 ifmr->ifm_status = mii->mii_media_status; 250 ifmr->ifm_active = mii->mii_media_active; 251 } 252 253 int 254 alc_mediachange(struct ifnet *ifp) 255 { 256 struct alc_softc *sc = ifp->if_softc; 257 struct mii_data *mii = &sc->sc_miibus; 258 int error; 259 260 if (mii->mii_instance != 0) { 261 struct mii_softc *miisc; 262 263 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 264 mii_phy_reset(miisc); 265 } 266 error = mii_mediachg(mii); 267 268 return (error); 269 } 270 271 int 272 alc_match(struct device *dev, void *match, void *aux) 273 { 274 return pci_matchbyid((struct pci_attach_args *)aux, alc_devices, 275 nitems(alc_devices)); 276 } 277 278 void 279 alc_get_macaddr(struct alc_softc *sc) 280 { 281 uint32_t ea[2], opt; 282 int i; 283 284 opt = CSR_READ_4(sc, ALC_OPT_CFG); 285 if ((CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) { 286 /* 287 * EEPROM found, let TWSI reload EEPROM configuration. 288 * This will set ethernet address of controller. 289 */ 290 if ((opt & OPT_CFG_CLK_ENB) == 0) { 291 opt |= OPT_CFG_CLK_ENB; 292 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 293 CSR_READ_4(sc, ALC_OPT_CFG); 294 DELAY(1000); 295 } 296 CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) | 297 TWSI_CFG_SW_LD_START); 298 for (i = 100; i > 0; i--) { 299 DELAY(1000); 300 if ((CSR_READ_4(sc, ALC_TWSI_CFG) & 301 TWSI_CFG_SW_LD_START) == 0) 302 break; 303 } 304 if (i == 0) 305 printf("%s: reloading EEPROM timeout!\n", 306 sc->sc_dev.dv_xname); 307 } else { 308 if (alcdebug) 309 printf("%s: EEPROM not found!\n", sc->sc_dev.dv_xname); 310 } 311 if ((opt & OPT_CFG_CLK_ENB) != 0) { 312 opt &= ~OPT_CFG_CLK_ENB; 313 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 314 CSR_READ_4(sc, ALC_OPT_CFG); 315 DELAY(1000); 316 } 317 318 ea[0] = CSR_READ_4(sc, ALC_PAR0); 319 ea[1] = CSR_READ_4(sc, ALC_PAR1); 320 sc->alc_eaddr[0] = (ea[1] >> 8) & 0xFF; 321 sc->alc_eaddr[1] = (ea[1] >> 0) & 0xFF; 322 sc->alc_eaddr[2] = (ea[0] >> 24) & 0xFF; 323 sc->alc_eaddr[3] = (ea[0] >> 16) & 0xFF; 324 sc->alc_eaddr[4] = (ea[0] >> 8) & 0xFF; 325 sc->alc_eaddr[5] = (ea[0] >> 0) & 0xFF; 326 } 327 328 void 329 alc_disable_l0s_l1(struct alc_softc *sc) 330 { 331 uint32_t pmcfg; 332 333 /* Another magic from vendor. */ 334 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 335 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_CLK_SWH_L1 | 336 PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | PM_CFG_MAC_ASPM_CHK | 337 PM_CFG_SERDES_PD_EX_L1); 338 pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB | 339 PM_CFG_SERDES_L1_ENB; 340 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 341 } 342 343 void 344 alc_phy_reset(struct alc_softc *sc) 345 { 346 uint16_t data; 347 348 /* Reset magic from Linux. */ 349 CSR_WRITE_2(sc, ALC_GPHY_CFG, 350 GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | GPHY_CFG_SEL_ANA_RESET); 351 CSR_READ_2(sc, ALC_GPHY_CFG); 352 DELAY(10 * 1000); 353 354 CSR_WRITE_2(sc, ALC_GPHY_CFG, 355 GPHY_CFG_EXT_RESET | GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | 356 GPHY_CFG_SEL_ANA_RESET); 357 CSR_READ_2(sc, ALC_GPHY_CFG); 358 DELAY(10 * 1000); 359 360 /* Load DSP codes, vendor magic. */ 361 data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE | 362 ((1 << ANA_INTERVAL_SEL_TIMER_SHIFT) & ANA_INTERVAL_SEL_TIMER_MASK); 363 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 364 ALC_MII_DBG_ADDR, MII_ANA_CFG18); 365 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 366 ALC_MII_DBG_DATA, data); 367 368 data = ((2 << ANA_SERDES_CDR_BW_SHIFT) & ANA_SERDES_CDR_BW_MASK) | 369 ANA_SERDES_EN_DEEM | ANA_SERDES_SEL_HSP | ANA_SERDES_EN_PLL | 370 ANA_SERDES_EN_LCKDT; 371 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 372 ALC_MII_DBG_ADDR, MII_ANA_CFG5); 373 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 374 ALC_MII_DBG_DATA, data); 375 376 data = ((44 << ANA_LONG_CABLE_TH_100_SHIFT) & 377 ANA_LONG_CABLE_TH_100_MASK) | 378 ((33 << ANA_SHORT_CABLE_TH_100_SHIFT) & 379 ANA_SHORT_CABLE_TH_100_SHIFT) | 380 ANA_BP_BAD_LINK_ACCUM | ANA_BP_SMALL_BW; 381 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 382 ALC_MII_DBG_ADDR, MII_ANA_CFG54); 383 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 384 ALC_MII_DBG_DATA, data); 385 386 data = ((11 << ANA_IECHO_ADJ_3_SHIFT) & ANA_IECHO_ADJ_3_MASK) | 387 ((11 << ANA_IECHO_ADJ_2_SHIFT) & ANA_IECHO_ADJ_2_MASK) | 388 ((8 << ANA_IECHO_ADJ_1_SHIFT) & ANA_IECHO_ADJ_1_MASK) | 389 ((8 << ANA_IECHO_ADJ_0_SHIFT) & ANA_IECHO_ADJ_0_MASK); 390 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 391 ALC_MII_DBG_ADDR, MII_ANA_CFG4); 392 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 393 ALC_MII_DBG_DATA, data); 394 395 data = ((7 & ANA_MANUL_SWICH_ON_SHIFT) & ANA_MANUL_SWICH_ON_MASK) | 396 ANA_RESTART_CAL | ANA_MAN_ENABLE | ANA_SEL_HSP | ANA_EN_HB | 397 ANA_OEN_125M; 398 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 399 ALC_MII_DBG_ADDR, MII_ANA_CFG0); 400 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 401 ALC_MII_DBG_DATA, data); 402 DELAY(1000); 403 } 404 405 void 406 alc_phy_down(struct alc_softc *sc) 407 { 408 409 /* Force PHY down. */ 410 CSR_WRITE_2(sc, ALC_GPHY_CFG, 411 GPHY_CFG_EXT_RESET | GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | 412 GPHY_CFG_SEL_ANA_RESET | GPHY_CFG_PHY_IDDQ | GPHY_CFG_PWDOWN_HW); 413 DELAY(1000); 414 } 415 416 void 417 alc_aspm(struct alc_softc *sc) 418 { 419 uint32_t pmcfg; 420 421 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 422 pmcfg &= ~PM_CFG_SERDES_PD_EX_L1; 423 pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB; 424 pmcfg |= PM_CFG_SERDES_L1_ENB; 425 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK; 426 pmcfg |= PM_CFG_MAC_ASPM_CHK; 427 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 428 pmcfg |= PM_CFG_SERDES_PLL_L1_ENB; 429 pmcfg &= ~PM_CFG_CLK_SWH_L1; 430 pmcfg &= ~PM_CFG_ASPM_L1_ENB; 431 pmcfg &= ~PM_CFG_ASPM_L0S_ENB; 432 } else { 433 pmcfg &= ~PM_CFG_SERDES_PLL_L1_ENB; 434 pmcfg |= PM_CFG_CLK_SWH_L1; 435 pmcfg &= ~PM_CFG_ASPM_L1_ENB; 436 pmcfg &= ~PM_CFG_ASPM_L0S_ENB; 437 } 438 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 439 } 440 441 void 442 alc_attach(struct device *parent, struct device *self, void *aux) 443 { 444 445 struct alc_softc *sc = (struct alc_softc *)self; 446 struct pci_attach_args *pa = aux; 447 pci_chipset_tag_t pc = pa->pa_pc; 448 pci_intr_handle_t ih; 449 const char *intrstr; 450 struct ifnet *ifp; 451 pcireg_t memtype; 452 char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/l1" }; 453 uint16_t burst; 454 int base, mii_flags, state, error = 0; 455 uint32_t cap, ctl, val; 456 457 /* 458 * Allocate IO memory 459 */ 460 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, ALC_PCIR_BAR); 461 if (pci_mapreg_map(pa, ALC_PCIR_BAR, memtype, 0, &sc->sc_mem_bt, 462 &sc->sc_mem_bh, NULL, &sc->sc_mem_size, 0)) { 463 printf(": can't map mem space\n"); 464 return; 465 } 466 467 if (pci_intr_map(pa, &ih) != 0) { 468 printf(": can't map interrupt\n"); 469 goto fail; 470 } 471 472 /* 473 * Allocate IRQ 474 */ 475 intrstr = pci_intr_string(pc, ih); 476 sc->sc_irq_handle = pci_intr_establish(pc, ih, IPL_NET, alc_intr, sc, 477 sc->sc_dev.dv_xname); 478 if (sc->sc_irq_handle == NULL) { 479 printf(": could not establish interrupt"); 480 if (intrstr != NULL) 481 printf(" at %s", intrstr); 482 printf("\n"); 483 goto fail; 484 } 485 printf(": %s", intrstr); 486 487 sc->sc_dmat = pa->pa_dmat; 488 sc->sc_pct = pa->pa_pc; 489 sc->sc_pcitag = pa->pa_tag; 490 491 /* Set PHY address. */ 492 sc->alc_phyaddr = ALC_PHY_ADDR; 493 494 /* Initialize DMA parameters. */ 495 sc->alc_dma_rd_burst = 0; 496 sc->alc_dma_wr_burst = 0; 497 sc->alc_rcb = DMA_CFG_RCB_64; 498 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PCIEXPRESS, 499 &base, NULL)) { 500 sc->alc_flags |= ALC_FLAG_PCIE; 501 burst = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 502 base + PCI_PCIE_DCSR) >> 16; 503 sc->alc_dma_rd_burst = (burst & 0x7000) >> 12; 504 sc->alc_dma_wr_burst = (burst & 0x00e0) >> 5; 505 if (alcdebug) { 506 printf("%s: Read request size : %u bytes.\n", 507 sc->sc_dev.dv_xname, 508 alc_dma_burst[sc->alc_dma_rd_burst]); 509 printf("%s: TLP payload size : %u bytes.\n", 510 sc->sc_dev.dv_xname, 511 alc_dma_burst[sc->alc_dma_wr_burst]); 512 } 513 /* Clear data link and flow-control protocol error. */ 514 val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV); 515 val &= ~(PEX_UNC_ERR_SEV_DLP | PEX_UNC_ERR_SEV_FCP); 516 CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val); 517 /* Disable ASPM L0S and L1. */ 518 cap = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 519 base + PCI_PCIE_LCAP) >> 16; 520 if ((cap & 0x00000c00) != 0) { 521 ctl = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 522 base + PCI_PCIE_LCSR) >> 16; 523 if ((ctl & 0x08) != 0) 524 sc->alc_rcb = DMA_CFG_RCB_128; 525 if (alcdebug) 526 printf("%s: RCB %u bytes\n", 527 sc->sc_dev.dv_xname, 528 sc->alc_rcb == DMA_CFG_RCB_64 ? 64 : 128); 529 state = ctl & 0x03; 530 if (alcdebug) 531 printf("%s: ASPM %s %s\n", 532 sc->sc_dev.dv_xname, 533 aspm_state[state], 534 state == 0 ? "disabled" : "enabled"); 535 if (state != 0) 536 alc_disable_l0s_l1(sc); 537 } 538 } 539 540 /* Reset PHY. */ 541 alc_phy_reset(sc); 542 543 /* Reset the ethernet controller. */ 544 alc_reset(sc); 545 546 /* 547 * One odd thing is AR8132 uses the same PHY hardware(F1 548 * gigabit PHY) of AR8131. So atphy(4) of AR8132 reports 549 * the PHY supports 1000Mbps but that's not true. The PHY 550 * used in AR8132 can't establish gigabit link even if it 551 * shows the same PHY model/revision number of AR8131. 552 */ 553 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATTANSIC_L2C) 554 sc->alc_flags |= ALC_FLAG_FASTETHER | ALC_FLAG_JUMBO; 555 else 556 sc->alc_flags |= ALC_FLAG_JUMBO | ALC_FLAG_ASPM_MON; 557 /* 558 * It seems that AR8131/AR8132 has silicon bug for SMB. In 559 * addition, Atheros said that enabling SMB wouldn't improve 560 * performance. However I think it's bad to access lots of 561 * registers to extract MAC statistics. 562 */ 563 sc->alc_flags |= ALC_FLAG_SMB_BUG; 564 /* 565 * Don't use Tx CMB. It is known to have silicon bug. 566 */ 567 sc->alc_flags |= ALC_FLAG_CMB_BUG; 568 sc->alc_rev = PCI_REVISION(pa->pa_class); 569 sc->alc_chip_rev = CSR_READ_4(sc, ALC_MASTER_CFG) >> 570 MASTER_CHIP_REV_SHIFT; 571 if (alcdebug) { 572 printf("%s: PCI device revision : 0x%04x\n", 573 sc->sc_dev.dv_xname, sc->alc_rev); 574 printf("%s: Chip id/revision : 0x%04x\n", 575 sc->sc_dev.dv_xname, sc->alc_chip_rev); 576 printf("%s: %u Tx FIFO, %u Rx FIFO\n", sc->sc_dev.dv_xname, 577 CSR_READ_4(sc, ALC_SRAM_TX_FIFO_LEN) * 8, 578 CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN) * 8); 579 } 580 581 error = alc_dma_alloc(sc); 582 if (error) 583 goto fail; 584 585 /* Load station address. */ 586 alc_get_macaddr(sc); 587 588 ifp = &sc->sc_arpcom.ac_if; 589 ifp->if_softc = sc; 590 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 591 ifp->if_init = alc_init; 592 ifp->if_ioctl = alc_ioctl; 593 ifp->if_start = alc_start; 594 ifp->if_watchdog = alc_watchdog; 595 ifp->if_baudrate = IF_Gbps(1); 596 IFQ_SET_MAXLEN(&ifp->if_snd, ALC_TX_RING_CNT - 1); 597 IFQ_SET_READY(&ifp->if_snd); 598 bcopy(sc->alc_eaddr, sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN); 599 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 600 601 ifp->if_capabilities = IFCAP_VLAN_MTU; 602 603 #ifdef ALC_CHECKSUM 604 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 605 IFCAP_CSUM_UDPv4; 606 #endif 607 608 #if NVLAN > 0 609 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 610 #endif 611 612 printf(", address %s\n", ether_sprintf(sc->sc_arpcom.ac_enaddr)); 613 614 /* Set up MII bus. */ 615 sc->sc_miibus.mii_ifp = ifp; 616 sc->sc_miibus.mii_readreg = alc_miibus_readreg; 617 sc->sc_miibus.mii_writereg = alc_miibus_writereg; 618 sc->sc_miibus.mii_statchg = alc_miibus_statchg; 619 620 ifmedia_init(&sc->sc_miibus.mii_media, 0, alc_mediachange, 621 alc_mediastatus); 622 mii_flags = 0; 623 if ((sc->alc_flags & ALC_FLAG_JUMBO) != 0) 624 mii_flags |= MIIF_DOPAUSE; 625 mii_attach(self, &sc->sc_miibus, 0xffffffff, MII_PHY_ANY, 626 MII_OFFSET_ANY, mii_flags); 627 628 if (LIST_FIRST(&sc->sc_miibus.mii_phys) == NULL) { 629 printf("%s: no PHY found!\n", sc->sc_dev.dv_xname); 630 ifmedia_add(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL, 631 0, NULL); 632 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL); 633 } else 634 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_AUTO); 635 636 if_attach(ifp); 637 ether_ifattach(ifp); 638 639 timeout_set(&sc->alc_tick_ch, alc_tick, sc); 640 641 return; 642 fail: 643 alc_dma_free(sc); 644 if (sc->sc_irq_handle != NULL) 645 pci_intr_disestablish(pc, sc->sc_irq_handle); 646 if (sc->sc_mem_size) 647 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 648 } 649 650 int 651 alc_detach(struct device *self, int flags) 652 { 653 struct alc_softc *sc = (struct alc_softc *)self; 654 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 655 int s; 656 657 s = splnet(); 658 alc_stop(sc); 659 splx(s); 660 661 mii_detach(&sc->sc_miibus, MII_PHY_ANY, MII_OFFSET_ANY); 662 663 /* Delete all remaining media. */ 664 ifmedia_delete_instance(&sc->sc_miibus.mii_media, IFM_INST_ANY); 665 666 ether_ifdetach(ifp); 667 if_detach(ifp); 668 alc_dma_free(sc); 669 670 alc_phy_down(sc); 671 if (sc->sc_irq_handle != NULL) { 672 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 673 sc->sc_irq_handle = NULL; 674 } 675 676 return (0); 677 } 678 679 int 680 alc_dma_alloc(struct alc_softc *sc) 681 { 682 struct alc_txdesc *txd; 683 struct alc_rxdesc *rxd; 684 int nsegs, error, i; 685 686 /* 687 * Create DMA stuffs for TX ring 688 */ 689 error = bus_dmamap_create(sc->sc_dmat, ALC_TX_RING_SZ, 1, 690 ALC_TX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->alc_cdata.alc_tx_ring_map); 691 if (error) 692 return (ENOBUFS); 693 694 /* Allocate DMA'able memory for TX ring */ 695 error = bus_dmamem_alloc(sc->sc_dmat, ALC_TX_RING_SZ, 696 ETHER_ALIGN, 0, &sc->alc_rdata.alc_tx_ring_seg, 1, 697 &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 698 if (error) { 699 printf("%s: could not allocate DMA'able memory for Tx ring.\n", 700 sc->sc_dev.dv_xname); 701 return error; 702 } 703 704 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_tx_ring_seg, 705 nsegs, ALC_TX_RING_SZ, (caddr_t *)&sc->alc_rdata.alc_tx_ring, 706 BUS_DMA_NOWAIT); 707 if (error) 708 return (ENOBUFS); 709 710 /* Load the DMA map for Tx ring. */ 711 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 712 sc->alc_rdata.alc_tx_ring, ALC_TX_RING_SZ, NULL, BUS_DMA_WAITOK); 713 if (error) { 714 printf("%s: could not load DMA'able memory for Tx ring.\n", 715 sc->sc_dev.dv_xname); 716 bus_dmamem_free(sc->sc_dmat, 717 (bus_dma_segment_t *)&sc->alc_rdata.alc_tx_ring, 1); 718 return error; 719 } 720 721 sc->alc_rdata.alc_tx_ring_paddr = 722 sc->alc_cdata.alc_tx_ring_map->dm_segs[0].ds_addr; 723 724 /* 725 * Create DMA stuffs for RX ring 726 */ 727 error = bus_dmamap_create(sc->sc_dmat, ALC_RX_RING_SZ, 1, 728 ALC_RX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->alc_cdata.alc_rx_ring_map); 729 if (error) 730 return (ENOBUFS); 731 732 /* Allocate DMA'able memory for RX ring */ 733 error = bus_dmamem_alloc(sc->sc_dmat, ALC_RX_RING_SZ, 734 ETHER_ALIGN, 0, &sc->alc_rdata.alc_rx_ring_seg, 1, 735 &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 736 if (error) { 737 printf("%s: could not allocate DMA'able memory for Rx ring.\n", 738 sc->sc_dev.dv_xname); 739 return error; 740 } 741 742 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_rx_ring_seg, 743 nsegs, ALC_RX_RING_SZ, (caddr_t *)&sc->alc_rdata.alc_rx_ring, 744 BUS_DMA_NOWAIT); 745 if (error) 746 return (ENOBUFS); 747 748 /* Load the DMA map for Rx ring. */ 749 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 750 sc->alc_rdata.alc_rx_ring, ALC_RX_RING_SZ, NULL, BUS_DMA_WAITOK); 751 if (error) { 752 printf("%s: could not load DMA'able memory for Rx ring.\n", 753 sc->sc_dev.dv_xname); 754 bus_dmamem_free(sc->sc_dmat, 755 (bus_dma_segment_t *)sc->alc_rdata.alc_rx_ring, 1); 756 return error; 757 } 758 759 sc->alc_rdata.alc_rx_ring_paddr = 760 sc->alc_cdata.alc_rx_ring_map->dm_segs[0].ds_addr; 761 762 /* 763 * Create DMA stuffs for RX return ring 764 */ 765 error = bus_dmamap_create(sc->sc_dmat, ALC_RR_RING_SZ, 1, 766 ALC_RR_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->alc_cdata.alc_rr_ring_map); 767 if (error) 768 return (ENOBUFS); 769 770 /* Allocate DMA'able memory for RX return ring */ 771 error = bus_dmamem_alloc(sc->sc_dmat, ALC_RR_RING_SZ, 772 ETHER_ALIGN, 0, &sc->alc_rdata.alc_rr_ring_seg, 1, 773 &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 774 if (error) { 775 printf("%s: could not allocate DMA'able memory for Rx " 776 "return ring.\n", sc->sc_dev.dv_xname); 777 return error; 778 } 779 780 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_rr_ring_seg, 781 nsegs, ALC_RR_RING_SZ, (caddr_t *)&sc->alc_rdata.alc_rr_ring, 782 BUS_DMA_NOWAIT); 783 if (error) 784 return (ENOBUFS); 785 786 /* Load the DMA map for Rx return ring. */ 787 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 788 sc->alc_rdata.alc_rr_ring, ALC_RR_RING_SZ, NULL, BUS_DMA_WAITOK); 789 if (error) { 790 printf("%s: could not load DMA'able memory for Rx return ring." 791 "\n", sc->sc_dev.dv_xname); 792 bus_dmamem_free(sc->sc_dmat, 793 (bus_dma_segment_t *)&sc->alc_rdata.alc_rr_ring, 1); 794 return error; 795 } 796 797 sc->alc_rdata.alc_rr_ring_paddr = 798 sc->alc_cdata.alc_rr_ring_map->dm_segs[0].ds_addr; 799 800 /* 801 * Create DMA stuffs for CMB block 802 */ 803 error = bus_dmamap_create(sc->sc_dmat, ALC_CMB_SZ, 1, 804 ALC_CMB_SZ, 0, BUS_DMA_NOWAIT, 805 &sc->alc_cdata.alc_cmb_map); 806 if (error) 807 return (ENOBUFS); 808 809 /* Allocate DMA'able memory for CMB block */ 810 error = bus_dmamem_alloc(sc->sc_dmat, ALC_CMB_SZ, 811 ETHER_ALIGN, 0, &sc->alc_rdata.alc_cmb_seg, 1, 812 &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 813 if (error) { 814 printf("%s: could not allocate DMA'able memory for " 815 "CMB block\n", sc->sc_dev.dv_xname); 816 return error; 817 } 818 819 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_cmb_seg, 820 nsegs, ALC_CMB_SZ, (caddr_t *)&sc->alc_rdata.alc_cmb, 821 BUS_DMA_NOWAIT); 822 if (error) 823 return (ENOBUFS); 824 825 /* Load the DMA map for CMB block. */ 826 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 827 sc->alc_rdata.alc_cmb, ALC_CMB_SZ, NULL, 828 BUS_DMA_WAITOK); 829 if (error) { 830 printf("%s: could not load DMA'able memory for CMB block\n", 831 sc->sc_dev.dv_xname); 832 bus_dmamem_free(sc->sc_dmat, 833 (bus_dma_segment_t *)&sc->alc_rdata.alc_cmb, 1); 834 return error; 835 } 836 837 sc->alc_rdata.alc_cmb_paddr = 838 sc->alc_cdata.alc_cmb_map->dm_segs[0].ds_addr; 839 840 /* 841 * Create DMA stuffs for SMB block 842 */ 843 error = bus_dmamap_create(sc->sc_dmat, ALC_SMB_SZ, 1, 844 ALC_SMB_SZ, 0, BUS_DMA_NOWAIT, 845 &sc->alc_cdata.alc_smb_map); 846 if (error) 847 return (ENOBUFS); 848 849 /* Allocate DMA'able memory for SMB block */ 850 error = bus_dmamem_alloc(sc->sc_dmat, ALC_SMB_SZ, 851 ETHER_ALIGN, 0, &sc->alc_rdata.alc_smb_seg, 1, 852 &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 853 if (error) { 854 printf("%s: could not allocate DMA'able memory for " 855 "SMB block\n", sc->sc_dev.dv_xname); 856 return error; 857 } 858 859 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_smb_seg, 860 nsegs, ALC_SMB_SZ, (caddr_t *)&sc->alc_rdata.alc_smb, 861 BUS_DMA_NOWAIT); 862 if (error) 863 return (ENOBUFS); 864 865 /* Load the DMA map for SMB block */ 866 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 867 sc->alc_rdata.alc_smb, ALC_SMB_SZ, NULL, 868 BUS_DMA_WAITOK); 869 if (error) { 870 printf("%s: could not load DMA'able memory for SMB block\n", 871 sc->sc_dev.dv_xname); 872 bus_dmamem_free(sc->sc_dmat, 873 (bus_dma_segment_t *)&sc->alc_rdata.alc_smb, 1); 874 return error; 875 } 876 877 sc->alc_rdata.alc_smb_paddr = 878 sc->alc_cdata.alc_smb_map->dm_segs[0].ds_addr; 879 880 881 /* Create DMA maps for Tx buffers. */ 882 for (i = 0; i < ALC_TX_RING_CNT; i++) { 883 txd = &sc->alc_cdata.alc_txdesc[i]; 884 txd->tx_m = NULL; 885 txd->tx_dmamap = NULL; 886 error = bus_dmamap_create(sc->sc_dmat, ALC_TSO_MAXSIZE, 887 ALC_MAXTXSEGS, ALC_TSO_MAXSEGSIZE, 0, BUS_DMA_NOWAIT, 888 &txd->tx_dmamap); 889 if (error) { 890 printf("%s: could not create Tx dmamap.\n", 891 sc->sc_dev.dv_xname); 892 return error; 893 } 894 } 895 896 /* Create DMA maps for Rx buffers. */ 897 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 898 BUS_DMA_NOWAIT, &sc->alc_cdata.alc_rx_sparemap); 899 if (error) { 900 printf("%s: could not create spare Rx dmamap.\n", 901 sc->sc_dev.dv_xname); 902 return error; 903 } 904 905 for (i = 0; i < ALC_RX_RING_CNT; i++) { 906 rxd = &sc->alc_cdata.alc_rxdesc[i]; 907 rxd->rx_m = NULL; 908 rxd->rx_dmamap = NULL; 909 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 910 MCLBYTES, 0, BUS_DMA_NOWAIT, &rxd->rx_dmamap); 911 if (error) { 912 printf("%s: could not create Rx dmamap.\n", 913 sc->sc_dev.dv_xname); 914 return error; 915 } 916 } 917 918 return (0); 919 } 920 921 922 void 923 alc_dma_free(struct alc_softc *sc) 924 { 925 struct alc_txdesc *txd; 926 struct alc_rxdesc *rxd; 927 int i; 928 929 /* Tx buffers */ 930 for (i = 0; i < ALC_TX_RING_CNT; i++) { 931 txd = &sc->alc_cdata.alc_txdesc[i]; 932 if (txd->tx_dmamap != NULL) { 933 bus_dmamap_destroy(sc->sc_dmat, txd->tx_dmamap); 934 txd->tx_dmamap = NULL; 935 } 936 } 937 /* Rx buffers */ 938 for (i = 0; i < ALC_RX_RING_CNT; i++) { 939 rxd = &sc->alc_cdata.alc_rxdesc[i]; 940 if (rxd->rx_dmamap != NULL) { 941 bus_dmamap_destroy(sc->sc_dmat, rxd->rx_dmamap); 942 rxd->rx_dmamap = NULL; 943 } 944 } 945 if (sc->alc_cdata.alc_rx_sparemap != NULL) { 946 bus_dmamap_destroy(sc->sc_dmat, sc->alc_cdata.alc_rx_sparemap); 947 sc->alc_cdata.alc_rx_sparemap = NULL; 948 } 949 950 /* Tx ring. */ 951 if (sc->alc_cdata.alc_tx_ring_map != NULL) 952 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map); 953 if (sc->alc_cdata.alc_tx_ring_map != NULL && 954 sc->alc_rdata.alc_tx_ring != NULL) 955 bus_dmamem_free(sc->sc_dmat, 956 (bus_dma_segment_t *)sc->alc_rdata.alc_tx_ring, 1); 957 sc->alc_rdata.alc_tx_ring = NULL; 958 sc->alc_cdata.alc_tx_ring_map = NULL; 959 960 /* Rx ring. */ 961 if (sc->alc_cdata.alc_rx_ring_map != NULL) 962 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map); 963 if (sc->alc_cdata.alc_rx_ring_map != NULL && 964 sc->alc_rdata.alc_rx_ring != NULL) 965 bus_dmamem_free(sc->sc_dmat, 966 (bus_dma_segment_t *)sc->alc_rdata.alc_rx_ring, 1); 967 sc->alc_rdata.alc_rx_ring = NULL; 968 sc->alc_cdata.alc_rx_ring_map = NULL; 969 970 /* Rx return ring. */ 971 if (sc->alc_cdata.alc_rr_ring_map != NULL) 972 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map); 973 if (sc->alc_cdata.alc_rr_ring_map != NULL && 974 sc->alc_rdata.alc_rr_ring != NULL) 975 bus_dmamem_free(sc->sc_dmat, 976 (bus_dma_segment_t *)sc->alc_rdata.alc_rr_ring, 1); 977 sc->alc_rdata.alc_rr_ring = NULL; 978 sc->alc_cdata.alc_rr_ring_map = NULL; 979 980 /* CMB block */ 981 if (sc->alc_cdata.alc_cmb_map != NULL) 982 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_cmb_map); 983 if (sc->alc_cdata.alc_cmb_map != NULL && 984 sc->alc_rdata.alc_cmb != NULL) 985 bus_dmamem_free(sc->sc_dmat, 986 (bus_dma_segment_t *)sc->alc_rdata.alc_cmb, 1); 987 sc->alc_rdata.alc_cmb = NULL; 988 sc->alc_cdata.alc_cmb_map = NULL; 989 990 /* SMB block */ 991 if (sc->alc_cdata.alc_smb_map != NULL) 992 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_smb_map); 993 if (sc->alc_cdata.alc_smb_map != NULL && 994 sc->alc_rdata.alc_smb != NULL) 995 bus_dmamem_free(sc->sc_dmat, 996 (bus_dma_segment_t *)sc->alc_rdata.alc_smb, 1); 997 sc->alc_rdata.alc_smb = NULL; 998 sc->alc_cdata.alc_smb_map = NULL; 999 } 1000 1001 int 1002 alc_encap(struct alc_softc *sc, struct mbuf **m_head) 1003 { 1004 struct alc_txdesc *txd, *txd_last; 1005 struct tx_desc *desc; 1006 struct mbuf *m; 1007 bus_dmamap_t map; 1008 uint32_t cflags, poff, vtag; 1009 int error, idx, nsegs, prod; 1010 1011 m = *m_head; 1012 cflags = vtag = 0; 1013 poff = 0; 1014 1015 prod = sc->alc_cdata.alc_tx_prod; 1016 txd = &sc->alc_cdata.alc_txdesc[prod]; 1017 txd_last = txd; 1018 map = txd->tx_dmamap; 1019 1020 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, BUS_DMA_NOWAIT); 1021 1022 if (error != 0) { 1023 bus_dmamap_unload(sc->sc_dmat, map); 1024 error = EFBIG; 1025 } 1026 if (error == EFBIG) { 1027 if (m_defrag(*m_head, M_DONTWAIT)) { 1028 printf("%s: can't defrag TX mbuf\n", 1029 sc->sc_dev.dv_xname); 1030 m_freem(*m_head); 1031 *m_head = NULL; 1032 return (ENOBUFS); 1033 } 1034 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, 1035 BUS_DMA_NOWAIT); 1036 if (error != 0) { 1037 printf("%s: could not load defragged TX mbuf\n", 1038 sc->sc_dev.dv_xname); 1039 m_freem(*m_head); 1040 *m_head = NULL; 1041 return (error); 1042 } 1043 } else if (error) { 1044 printf("%s: could not load TX mbuf\n", sc->sc_dev.dv_xname); 1045 return (error); 1046 } 1047 1048 nsegs = map->dm_nsegs; 1049 1050 if (nsegs == 0) { 1051 m_freem(*m_head); 1052 *m_head = NULL; 1053 return (EIO); 1054 } 1055 1056 /* Check descriptor overrun. */ 1057 if (sc->alc_cdata.alc_tx_cnt + nsegs >= ALC_TX_RING_CNT - 3) { 1058 bus_dmamap_unload(sc->sc_dmat, map); 1059 return (ENOBUFS); 1060 } 1061 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1062 BUS_DMASYNC_PREWRITE); 1063 1064 m = *m_head; 1065 desc = NULL; 1066 idx = 0; 1067 #if NVLAN > 0 1068 /* Configure VLAN hardware tag insertion. */ 1069 if (m->m_flags & M_VLANTAG) { 1070 vtag = htons(m->m_pkthdr.ether_vtag); 1071 vtag = (vtag << TD_VLAN_SHIFT) & TD_VLAN_MASK; 1072 cflags |= TD_INS_VLAN_TAG; 1073 } 1074 #endif 1075 /* Configure Tx checksum offload. */ 1076 if ((m->m_pkthdr.csum_flags & ALC_CSUM_FEATURES) != 0) { 1077 cflags |= TD_CUSTOM_CSUM; 1078 /* Set checksum start offset. */ 1079 cflags |= ((poff >> 1) << TD_PLOAD_OFFSET_SHIFT) & 1080 TD_PLOAD_OFFSET_MASK; 1081 } 1082 for (; idx < nsegs; idx++) { 1083 desc = &sc->alc_rdata.alc_tx_ring[prod]; 1084 desc->len = 1085 htole32(TX_BYTES(map->dm_segs[idx].ds_len) | vtag); 1086 desc->flags = htole32(cflags); 1087 desc->addr = htole64(map->dm_segs[idx].ds_addr); 1088 sc->alc_cdata.alc_tx_cnt++; 1089 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 1090 } 1091 /* Update producer index. */ 1092 sc->alc_cdata.alc_tx_prod = prod; 1093 1094 /* Finally set EOP on the last descriptor. */ 1095 prod = (prod + ALC_TX_RING_CNT - 1) % ALC_TX_RING_CNT; 1096 desc = &sc->alc_rdata.alc_tx_ring[prod]; 1097 desc->flags |= htole32(TD_EOP); 1098 1099 /* Swap dmamap of the first and the last. */ 1100 txd = &sc->alc_cdata.alc_txdesc[prod]; 1101 map = txd_last->tx_dmamap; 1102 txd_last->tx_dmamap = txd->tx_dmamap; 1103 txd->tx_dmamap = map; 1104 txd->tx_m = m; 1105 1106 return (0); 1107 } 1108 1109 void 1110 alc_start(struct ifnet *ifp) 1111 { 1112 struct alc_softc *sc = ifp->if_softc; 1113 struct mbuf *m_head; 1114 int enq; 1115 1116 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1117 return; 1118 1119 /* Reclaim transmitted frames. */ 1120 if (sc->alc_cdata.alc_tx_cnt >= ALC_TX_DESC_HIWAT) 1121 alc_txeof(sc); 1122 1123 enq = 0; 1124 for (;;) { 1125 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1126 if (m_head == NULL) 1127 break; 1128 1129 /* 1130 * Pack the data into the transmit ring. If we 1131 * don't have room, set the OACTIVE flag and wait 1132 * for the NIC to drain the ring. 1133 */ 1134 if (alc_encap(sc, &m_head)) { 1135 if (m_head == NULL) 1136 break; 1137 ifp->if_flags |= IFF_OACTIVE; 1138 break; 1139 } 1140 enq = 1; 1141 1142 #if NBPFILTER > 0 1143 /* 1144 * If there's a BPF listener, bounce a copy of this frame 1145 * to him. 1146 */ 1147 if (ifp->if_bpf != NULL) 1148 bpf_mtap_ether(ifp->if_bpf, m_head, BPF_DIRECTION_OUT); 1149 #endif 1150 } 1151 1152 if (enq) { 1153 /* Sync descriptors. */ 1154 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0, 1155 sc->alc_cdata.alc_tx_ring_map->dm_mapsize, 1156 BUS_DMASYNC_PREWRITE); 1157 /* Kick. Assume we're using normal Tx priority queue. */ 1158 CSR_WRITE_4(sc, ALC_MBOX_TD_PROD_IDX, 1159 (sc->alc_cdata.alc_tx_prod << 1160 MBOX_TD_PROD_LO_IDX_SHIFT) & 1161 MBOX_TD_PROD_LO_IDX_MASK); 1162 /* Set a timeout in case the chip goes out to lunch. */ 1163 ifp->if_timer = ALC_TX_TIMEOUT; 1164 } 1165 } 1166 1167 void 1168 alc_watchdog(struct ifnet *ifp) 1169 { 1170 struct alc_softc *sc = ifp->if_softc; 1171 1172 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) { 1173 printf("%s: watchdog timeout (missed link)\n", 1174 sc->sc_dev.dv_xname); 1175 ifp->if_oerrors++; 1176 alc_init(ifp); 1177 return; 1178 } 1179 1180 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 1181 ifp->if_oerrors++; 1182 alc_init(ifp); 1183 1184 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1185 alc_start(ifp); 1186 } 1187 1188 int 1189 alc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1190 { 1191 struct alc_softc *sc = ifp->if_softc; 1192 struct mii_data *mii = &sc->sc_miibus; 1193 struct ifaddr *ifa = (struct ifaddr *)data; 1194 struct ifreq *ifr = (struct ifreq *)data; 1195 int s, error = 0; 1196 1197 s = splnet(); 1198 1199 switch (cmd) { 1200 case SIOCSIFADDR: 1201 ifp->if_flags |= IFF_UP; 1202 if (!(ifp->if_flags & IFF_RUNNING)) 1203 alc_init(ifp); 1204 #ifdef INET 1205 if (ifa->ifa_addr->sa_family == AF_INET) 1206 arp_ifinit(&sc->sc_arpcom, ifa); 1207 #endif 1208 break; 1209 1210 case SIOCSIFFLAGS: 1211 if (ifp->if_flags & IFF_UP) { 1212 if (ifp->if_flags & IFF_RUNNING) 1213 error = ENETRESET; 1214 else 1215 alc_init(ifp); 1216 } else { 1217 if (ifp->if_flags & IFF_RUNNING) 1218 alc_stop(sc); 1219 } 1220 break; 1221 1222 case SIOCSIFMEDIA: 1223 case SIOCGIFMEDIA: 1224 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1225 break; 1226 1227 default: 1228 error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data); 1229 break; 1230 } 1231 1232 if (error == ENETRESET) { 1233 if (ifp->if_flags & IFF_RUNNING) 1234 alc_rxfilter(sc); 1235 error = 0; 1236 } 1237 1238 splx(s); 1239 return (error); 1240 } 1241 1242 void 1243 alc_mac_config(struct alc_softc *sc) 1244 { 1245 struct mii_data *mii; 1246 uint32_t reg; 1247 1248 mii = &sc->sc_miibus; 1249 reg = CSR_READ_4(sc, ALC_MAC_CFG); 1250 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 1251 MAC_CFG_SPEED_MASK); 1252 /* Reprogram MAC with resolved speed/duplex. */ 1253 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1254 case IFM_10_T: 1255 case IFM_100_TX: 1256 reg |= MAC_CFG_SPEED_10_100; 1257 break; 1258 case IFM_1000_T: 1259 reg |= MAC_CFG_SPEED_1000; 1260 break; 1261 } 1262 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1263 reg |= MAC_CFG_FULL_DUPLEX; 1264 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1265 reg |= MAC_CFG_TX_FC; 1266 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1267 reg |= MAC_CFG_RX_FC; 1268 } 1269 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 1270 } 1271 1272 void 1273 alc_stats_clear(struct alc_softc *sc) 1274 { 1275 struct smb sb, *smb; 1276 uint32_t *reg; 1277 int i; 1278 1279 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 1280 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 1281 sc->alc_cdata.alc_smb_map->dm_mapsize, 1282 BUS_DMASYNC_POSTREAD); 1283 smb = sc->alc_rdata.alc_smb; 1284 /* Update done, clear. */ 1285 smb->updated = 0; 1286 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 1287 sc->alc_cdata.alc_smb_map->dm_mapsize, 1288 BUS_DMASYNC_PREWRITE); 1289 } else { 1290 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 1291 reg++) { 1292 CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 1293 i += sizeof(uint32_t); 1294 } 1295 /* Read Tx statistics. */ 1296 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 1297 reg++) { 1298 CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 1299 i += sizeof(uint32_t); 1300 } 1301 } 1302 } 1303 1304 void 1305 alc_stats_update(struct alc_softc *sc) 1306 { 1307 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1308 struct alc_hw_stats *stat; 1309 struct smb sb, *smb; 1310 uint32_t *reg; 1311 int i; 1312 1313 stat = &sc->alc_stats; 1314 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 1315 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 1316 sc->alc_cdata.alc_smb_map->dm_mapsize, 1317 BUS_DMASYNC_POSTREAD); 1318 smb = sc->alc_rdata.alc_smb; 1319 if (smb->updated == 0) 1320 return; 1321 } else { 1322 smb = &sb; 1323 /* Read Rx statistics. */ 1324 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 1325 reg++) { 1326 *reg = CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 1327 i += sizeof(uint32_t); 1328 } 1329 /* Read Tx statistics. */ 1330 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 1331 reg++) { 1332 *reg = CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 1333 i += sizeof(uint32_t); 1334 } 1335 } 1336 1337 /* Rx stats. */ 1338 stat->rx_frames += smb->rx_frames; 1339 stat->rx_bcast_frames += smb->rx_bcast_frames; 1340 stat->rx_mcast_frames += smb->rx_mcast_frames; 1341 stat->rx_pause_frames += smb->rx_pause_frames; 1342 stat->rx_control_frames += smb->rx_control_frames; 1343 stat->rx_crcerrs += smb->rx_crcerrs; 1344 stat->rx_lenerrs += smb->rx_lenerrs; 1345 stat->rx_bytes += smb->rx_bytes; 1346 stat->rx_runts += smb->rx_runts; 1347 stat->rx_fragments += smb->rx_fragments; 1348 stat->rx_pkts_64 += smb->rx_pkts_64; 1349 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 1350 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 1351 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 1352 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 1353 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 1354 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 1355 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 1356 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 1357 stat->rx_rrs_errs += smb->rx_rrs_errs; 1358 stat->rx_alignerrs += smb->rx_alignerrs; 1359 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 1360 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 1361 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 1362 1363 /* Tx stats. */ 1364 stat->tx_frames += smb->tx_frames; 1365 stat->tx_bcast_frames += smb->tx_bcast_frames; 1366 stat->tx_mcast_frames += smb->tx_mcast_frames; 1367 stat->tx_pause_frames += smb->tx_pause_frames; 1368 stat->tx_excess_defer += smb->tx_excess_defer; 1369 stat->tx_control_frames += smb->tx_control_frames; 1370 stat->tx_deferred += smb->tx_deferred; 1371 stat->tx_bytes += smb->tx_bytes; 1372 stat->tx_pkts_64 += smb->tx_pkts_64; 1373 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 1374 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 1375 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 1376 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 1377 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 1378 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 1379 stat->tx_single_colls += smb->tx_single_colls; 1380 stat->tx_multi_colls += smb->tx_multi_colls; 1381 stat->tx_late_colls += smb->tx_late_colls; 1382 stat->tx_excess_colls += smb->tx_excess_colls; 1383 stat->tx_abort += smb->tx_abort; 1384 stat->tx_underrun += smb->tx_underrun; 1385 stat->tx_desc_underrun += smb->tx_desc_underrun; 1386 stat->tx_lenerrs += smb->tx_lenerrs; 1387 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 1388 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 1389 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 1390 1391 /* Update counters in ifnet. */ 1392 ifp->if_opackets += smb->tx_frames; 1393 1394 ifp->if_collisions += smb->tx_single_colls + 1395 smb->tx_multi_colls * 2 + smb->tx_late_colls + 1396 smb->tx_abort * HDPX_CFG_RETRY_DEFAULT; 1397 1398 /* 1399 * XXX 1400 * tx_pkts_truncated counter looks suspicious. It constantly 1401 * increments with no sign of Tx errors. This may indicate 1402 * the counter name is not correct one so I've removed the 1403 * counter in output errors. 1404 */ 1405 ifp->if_oerrors += smb->tx_abort + smb->tx_late_colls + 1406 smb->tx_underrun; 1407 1408 ifp->if_ipackets += smb->rx_frames; 1409 1410 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 1411 smb->rx_runts + smb->rx_pkts_truncated + 1412 smb->rx_fifo_oflows + smb->rx_rrs_errs + 1413 smb->rx_alignerrs; 1414 1415 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 1416 /* Update done, clear. */ 1417 smb->updated = 0; 1418 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 1419 sc->alc_cdata.alc_smb_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1420 } 1421 } 1422 1423 int 1424 alc_intr(void *arg) 1425 { 1426 struct alc_softc *sc = arg; 1427 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1428 uint32_t status; 1429 1430 status = CSR_READ_4(sc, ALC_INTR_STATUS); 1431 if ((status & ALC_INTRS) == 0) 1432 return (0); 1433 1434 /* Acknowledge and disable interrupts. */ 1435 CSR_WRITE_4(sc, ALC_INTR_STATUS, status | INTR_DIS_INT); 1436 1437 if (ifp->if_flags & IFF_RUNNING) { 1438 if (status & INTR_RX_PKT) { 1439 int error; 1440 1441 error = alc_rxintr(sc); 1442 if (error) { 1443 alc_init(ifp); 1444 return (0); 1445 } 1446 } 1447 1448 if (status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | 1449 INTR_TXQ_TO_RST)) { 1450 if (status & INTR_DMA_RD_TO_RST) 1451 printf("%s: DMA read error! -- resetting\n", 1452 sc->sc_dev.dv_xname); 1453 if (status & INTR_DMA_WR_TO_RST) 1454 printf("%s: DMA write error! -- resetting\n", 1455 sc->sc_dev.dv_xname); 1456 if (status & INTR_TXQ_TO_RST) 1457 printf("%s: TxQ reset! -- resetting\n", 1458 sc->sc_dev.dv_xname); 1459 alc_init(ifp); 1460 return (0); 1461 } 1462 1463 alc_txeof(sc); 1464 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1465 alc_start(ifp); 1466 } 1467 1468 /* Re-enable interrupts. */ 1469 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0x7FFFFFFF); 1470 return (1); 1471 } 1472 1473 void 1474 alc_txeof(struct alc_softc *sc) 1475 { 1476 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1477 struct alc_txdesc *txd; 1478 uint32_t cons, prod; 1479 int prog; 1480 1481 if (sc->alc_cdata.alc_tx_cnt == 0) 1482 return; 1483 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0, 1484 sc->alc_cdata.alc_tx_ring_map->dm_mapsize, 1485 BUS_DMASYNC_POSTREAD); 1486 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 1487 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0, 1488 sc->alc_cdata.alc_cmb_map->dm_mapsize, 1489 BUS_DMASYNC_POSTREAD); 1490 prod = sc->alc_rdata.alc_cmb->cons; 1491 } else 1492 prod = CSR_READ_4(sc, ALC_MBOX_TD_CONS_IDX); 1493 /* Assume we're using normal Tx priority queue. */ 1494 prod = (prod & MBOX_TD_CONS_LO_IDX_MASK) >> 1495 MBOX_TD_CONS_LO_IDX_SHIFT; 1496 cons = sc->alc_cdata.alc_tx_cons; 1497 /* 1498 * Go through our Tx list and free mbufs for those 1499 * frames which have been transmitted. 1500 */ 1501 for (prog = 0; cons != prod; prog++, 1502 ALC_DESC_INC(cons, ALC_TX_RING_CNT)) { 1503 if (sc->alc_cdata.alc_tx_cnt <= 0) 1504 break; 1505 prog++; 1506 ifp->if_flags &= ~IFF_OACTIVE; 1507 sc->alc_cdata.alc_tx_cnt--; 1508 txd = &sc->alc_cdata.alc_txdesc[cons]; 1509 if (txd->tx_m != NULL) { 1510 /* Reclaim transmitted mbufs. */ 1511 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1512 m_freem(txd->tx_m); 1513 txd->tx_m = NULL; 1514 } 1515 } 1516 1517 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 1518 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0, 1519 sc->alc_cdata.alc_cmb_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1520 sc->alc_cdata.alc_tx_cons = cons; 1521 /* 1522 * Unarm watchdog timer only when there is no pending 1523 * frames in Tx queue. 1524 */ 1525 if (sc->alc_cdata.alc_tx_cnt == 0) 1526 ifp->if_timer = 0; 1527 } 1528 1529 int 1530 alc_newbuf(struct alc_softc *sc, struct alc_rxdesc *rxd, int init) 1531 { 1532 struct mbuf *m; 1533 bus_dmamap_t map; 1534 int error; 1535 1536 MGETHDR(m, init ? M_WAITOK : M_DONTWAIT, MT_DATA); 1537 if (m == NULL) 1538 return (ENOBUFS); 1539 MCLGET(m, init ? M_WAITOK : M_DONTWAIT); 1540 if (!(m->m_flags & M_EXT)) { 1541 m_freem(m); 1542 return (ENOBUFS); 1543 } 1544 1545 m->m_len = m->m_pkthdr.len = RX_BUF_SIZE_MAX; 1546 1547 error = bus_dmamap_load_mbuf(sc->sc_dmat, 1548 sc->alc_cdata.alc_rx_sparemap, m, BUS_DMA_NOWAIT); 1549 1550 if (error != 0) { 1551 if (!error) { 1552 bus_dmamap_unload(sc->sc_dmat, 1553 sc->alc_cdata.alc_rx_sparemap); 1554 error = EFBIG; 1555 printf("%s: too many segments?!\n", 1556 sc->sc_dev.dv_xname); 1557 } 1558 m_freem(m); 1559 1560 if (init) 1561 printf("%s: can't load RX mbuf\n", sc->sc_dev.dv_xname); 1562 1563 return (error); 1564 } 1565 1566 if (rxd->rx_m != NULL) { 1567 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0, 1568 rxd->rx_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1569 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 1570 } 1571 map = rxd->rx_dmamap; 1572 rxd->rx_dmamap = sc->alc_cdata.alc_rx_sparemap; 1573 sc->alc_cdata.alc_rx_sparemap = map; 1574 rxd->rx_m = m; 1575 rxd->rx_desc->addr = htole64(rxd->rx_dmamap->dm_segs[0].ds_addr); 1576 return (0); 1577 } 1578 1579 int 1580 alc_rxintr(struct alc_softc *sc) 1581 { 1582 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1583 struct rx_rdesc *rrd; 1584 uint32_t nsegs, status; 1585 int rr_cons, prog; 1586 1587 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 0, 1588 sc->alc_cdata.alc_rr_ring_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1589 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 0, 1590 sc->alc_cdata.alc_rx_ring_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1591 rr_cons = sc->alc_cdata.alc_rr_cons; 1592 for (prog = 0; (ifp->if_flags & IFF_RUNNING) != 0;) { 1593 rrd = &sc->alc_rdata.alc_rr_ring[rr_cons]; 1594 status = letoh32(rrd->status); 1595 if ((status & RRD_VALID) == 0) 1596 break; 1597 nsegs = RRD_RD_CNT(letoh32(rrd->rdinfo)); 1598 if (nsegs == 0) { 1599 /* This should not happen! */ 1600 if (alcdebug) 1601 printf("%s: unexpected segment count -- " 1602 "resetting\n", sc->sc_dev.dv_xname); 1603 return (EIO); 1604 } 1605 alc_rxeof(sc, rrd); 1606 /* Clear Rx return status. */ 1607 rrd->status = 0; 1608 ALC_DESC_INC(rr_cons, ALC_RR_RING_CNT); 1609 sc->alc_cdata.alc_rx_cons += nsegs; 1610 sc->alc_cdata.alc_rx_cons %= ALC_RR_RING_CNT; 1611 prog += nsegs; 1612 } 1613 1614 if (prog > 0) { 1615 /* Update the consumer index. */ 1616 sc->alc_cdata.alc_rr_cons = rr_cons; 1617 /* Sync Rx return descriptors. */ 1618 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 0, 1619 sc->alc_cdata.alc_rr_ring_map->dm_mapsize, 1620 BUS_DMASYNC_PREWRITE); 1621 /* 1622 * Sync updated Rx descriptors such that controller see 1623 * modified buffer addresses. 1624 */ 1625 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 0, 1626 sc->alc_cdata.alc_rx_ring_map->dm_mapsize, 1627 BUS_DMASYNC_PREWRITE); 1628 /* 1629 * Let controller know availability of new Rx buffers. 1630 * Since alc(4) use RXQ_CFG_RD_BURST_DEFAULT descriptors 1631 * it may be possible to update ALC_MBOX_RD0_PROD_IDX 1632 * only when Rx buffer pre-fetching is required. In 1633 * addition we already set ALC_RX_RD_FREE_THRESH to 1634 * RX_RD_FREE_THRESH_LO_DEFAULT descriptors. However 1635 * it still seems that pre-fetching needs more 1636 * experimentation. 1637 */ 1638 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 1639 sc->alc_cdata.alc_rx_cons); 1640 } 1641 1642 return (0); 1643 } 1644 1645 /* Receive a frame. */ 1646 void 1647 alc_rxeof(struct alc_softc *sc, struct rx_rdesc *rrd) 1648 { 1649 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1650 struct alc_rxdesc *rxd; 1651 struct mbuf *mp, *m; 1652 uint32_t rdinfo, status; 1653 int count, nsegs, rx_cons; 1654 1655 status = letoh32(rrd->status); 1656 rdinfo = letoh32(rrd->rdinfo); 1657 rx_cons = RRD_RD_IDX(rdinfo); 1658 nsegs = RRD_RD_CNT(rdinfo); 1659 1660 sc->alc_cdata.alc_rxlen = RRD_BYTES(status); 1661 if (status & (RRD_ERR_SUM | RRD_ERR_LENGTH)) { 1662 /* 1663 * We want to pass the following frames to upper 1664 * layer regardless of error status of Rx return 1665 * ring. 1666 * 1667 * o IP/TCP/UDP checksum is bad. 1668 * o frame length and protocol specific length 1669 * does not match. 1670 * 1671 * Force network stack compute checksum for 1672 * errored frames. 1673 */ 1674 status |= RRD_TCP_UDPCSUM_NOK | RRD_IPCSUM_NOK; 1675 if ((RRD_ERR_CRC | RRD_ERR_ALIGN | RRD_ERR_TRUNC | 1676 RRD_ERR_RUNT) != 0) 1677 return; 1678 } 1679 1680 for (count = 0; count < nsegs; count++, 1681 ALC_DESC_INC(rx_cons, ALC_RX_RING_CNT)) { 1682 rxd = &sc->alc_cdata.alc_rxdesc[rx_cons]; 1683 mp = rxd->rx_m; 1684 /* Add a new receive buffer to the ring. */ 1685 if (alc_newbuf(sc, rxd, 0) != 0) { 1686 ifp->if_iqdrops++; 1687 /* Reuse Rx buffers. */ 1688 if (sc->alc_cdata.alc_rxhead != NULL) 1689 m_freem(sc->alc_cdata.alc_rxhead); 1690 break; 1691 } 1692 1693 /* 1694 * Assume we've received a full sized frame. 1695 * Actual size is fixed when we encounter the end of 1696 * multi-segmented frame. 1697 */ 1698 mp->m_len = sc->alc_buf_size; 1699 1700 /* Chain received mbufs. */ 1701 if (sc->alc_cdata.alc_rxhead == NULL) { 1702 sc->alc_cdata.alc_rxhead = mp; 1703 sc->alc_cdata.alc_rxtail = mp; 1704 } else { 1705 mp->m_flags &= ~M_PKTHDR; 1706 sc->alc_cdata.alc_rxprev_tail = 1707 sc->alc_cdata.alc_rxtail; 1708 sc->alc_cdata.alc_rxtail->m_next = mp; 1709 sc->alc_cdata.alc_rxtail = mp; 1710 } 1711 1712 if (count == nsegs - 1) { 1713 /* Last desc. for this frame. */ 1714 m = sc->alc_cdata.alc_rxhead; 1715 m->m_flags |= M_PKTHDR; 1716 /* 1717 * It seems that L1C/L2C controller has no way 1718 * to tell hardware to strip CRC bytes. 1719 */ 1720 m->m_pkthdr.len = 1721 sc->alc_cdata.alc_rxlen - ETHER_CRC_LEN; 1722 if (nsegs > 1) { 1723 /* Set last mbuf size. */ 1724 mp->m_len = sc->alc_cdata.alc_rxlen - 1725 (nsegs - 1) * sc->alc_buf_size; 1726 /* Remove the CRC bytes in chained mbufs. */ 1727 if (mp->m_len <= ETHER_CRC_LEN) { 1728 sc->alc_cdata.alc_rxtail = 1729 sc->alc_cdata.alc_rxprev_tail; 1730 sc->alc_cdata.alc_rxtail->m_len -= 1731 (ETHER_CRC_LEN - mp->m_len); 1732 sc->alc_cdata.alc_rxtail->m_next = NULL; 1733 m_freem(mp); 1734 } else { 1735 mp->m_len -= ETHER_CRC_LEN; 1736 } 1737 } else 1738 m->m_len = m->m_pkthdr.len; 1739 m->m_pkthdr.rcvif = ifp; 1740 #if NVLAN > 0 1741 /* 1742 * Due to hardware bugs, Rx checksum offloading 1743 * was intentionally disabled. 1744 */ 1745 if (status & RRD_VLAN_TAG) { 1746 u_int32_t vtag = RRD_VLAN(letoh32(rrd->vtag)); 1747 m->m_pkthdr.ether_vtag = ntohs(vtag); 1748 m->m_flags |= M_VLANTAG; 1749 } 1750 #endif 1751 1752 #if NBPFILTER > 0 1753 if (ifp->if_bpf) 1754 bpf_mtap_ether(ifp->if_bpf, m, 1755 BPF_DIRECTION_IN); 1756 #endif 1757 1758 { 1759 /* Pass it on. */ 1760 ether_input_mbuf(ifp, m); 1761 } 1762 } 1763 } 1764 /* Reset mbuf chains. */ 1765 ALC_RXCHAIN_RESET(sc); 1766 } 1767 1768 void 1769 alc_tick(void *xsc) 1770 { 1771 struct alc_softc *sc = xsc; 1772 struct mii_data *mii = &sc->sc_miibus; 1773 int s; 1774 1775 s = splnet(); 1776 mii_tick(mii); 1777 alc_stats_update(sc); 1778 1779 timeout_add_sec(&sc->alc_tick_ch, 1); 1780 splx(s); 1781 } 1782 1783 void 1784 alc_reset(struct alc_softc *sc) 1785 { 1786 uint32_t reg; 1787 int i; 1788 1789 CSR_WRITE_4(sc, ALC_MASTER_CFG, MASTER_RESET); 1790 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 1791 DELAY(10); 1792 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0) 1793 break; 1794 } 1795 if (i == 0) 1796 printf("%s: master reset timeout!\n", sc->sc_dev.dv_xname); 1797 1798 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 1799 if ((reg = CSR_READ_4(sc, ALC_IDLE_STATUS)) == 0) 1800 break; 1801 DELAY(10); 1802 } 1803 1804 if (i == 0) 1805 printf("%s: reset timeout(0x%08x)!\n", sc->sc_dev.dv_xname, 1806 reg); 1807 } 1808 1809 int 1810 alc_init(struct ifnet *ifp) 1811 { 1812 struct alc_softc *sc = ifp->if_softc; 1813 struct mii_data *mii; 1814 uint8_t eaddr[ETHER_ADDR_LEN]; 1815 bus_addr_t paddr; 1816 uint32_t reg, rxf_hi, rxf_lo; 1817 int error; 1818 1819 /* 1820 * Cancel any pending I/O. 1821 */ 1822 alc_stop(sc); 1823 /* 1824 * Reset the chip to a known state. 1825 */ 1826 alc_reset(sc); 1827 1828 /* Initialize Rx descriptors. */ 1829 error = alc_init_rx_ring(sc); 1830 if (error != 0) { 1831 printf("%s: no memory for Rx buffers.\n", sc->sc_dev.dv_xname); 1832 alc_stop(sc); 1833 return (error); 1834 } 1835 alc_init_rr_ring(sc); 1836 alc_init_tx_ring(sc); 1837 alc_init_cmb(sc); 1838 alc_init_smb(sc); 1839 1840 /* Reprogram the station address. */ 1841 bcopy(LLADDR(ifp->if_sadl), eaddr, ETHER_ADDR_LEN); 1842 CSR_WRITE_4(sc, ALC_PAR0, 1843 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 1844 CSR_WRITE_4(sc, ALC_PAR1, eaddr[0] << 8 | eaddr[1]); 1845 /* 1846 * Clear WOL status and disable all WOL feature as WOL 1847 * would interfere Rx operation under normal environments. 1848 */ 1849 CSR_READ_4(sc, ALC_WOL_CFG); 1850 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 1851 /* Set Tx descriptor base addresses. */ 1852 paddr = sc->alc_rdata.alc_tx_ring_paddr; 1853 CSR_WRITE_4(sc, ALC_TX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 1854 CSR_WRITE_4(sc, ALC_TDL_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 1855 /* We don't use high priority ring. */ 1856 CSR_WRITE_4(sc, ALC_TDH_HEAD_ADDR_LO, 0); 1857 /* Set Tx descriptor counter. */ 1858 CSR_WRITE_4(sc, ALC_TD_RING_CNT, 1859 (ALC_TX_RING_CNT << TD_RING_CNT_SHIFT) & TD_RING_CNT_MASK); 1860 /* Set Rx descriptor base addresses. */ 1861 paddr = sc->alc_rdata.alc_rx_ring_paddr; 1862 CSR_WRITE_4(sc, ALC_RX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 1863 CSR_WRITE_4(sc, ALC_RD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 1864 /* We use one Rx ring. */ 1865 CSR_WRITE_4(sc, ALC_RD1_HEAD_ADDR_LO, 0); 1866 CSR_WRITE_4(sc, ALC_RD2_HEAD_ADDR_LO, 0); 1867 CSR_WRITE_4(sc, ALC_RD3_HEAD_ADDR_LO, 0); 1868 /* Set Rx descriptor counter. */ 1869 CSR_WRITE_4(sc, ALC_RD_RING_CNT, 1870 (ALC_RX_RING_CNT << RD_RING_CNT_SHIFT) & RD_RING_CNT_MASK); 1871 1872 /* 1873 * Let hardware split jumbo frames into alc_max_buf_sized chunks. 1874 * if it do not fit the buffer size. Rx return descriptor holds 1875 * a counter that indicates how many fragments were made by the 1876 * hardware. The buffer size should be multiple of 8 bytes. 1877 * Since hardware has limit on the size of buffer size, always 1878 * use the maximum value. 1879 * For strict-alignment architectures make sure to reduce buffer 1880 * size by 8 bytes to make room for alignment fixup. 1881 */ 1882 sc->alc_buf_size = RX_BUF_SIZE_MAX; 1883 CSR_WRITE_4(sc, ALC_RX_BUF_SIZE, sc->alc_buf_size); 1884 1885 paddr = sc->alc_rdata.alc_rr_ring_paddr; 1886 /* Set Rx return descriptor base addresses. */ 1887 CSR_WRITE_4(sc, ALC_RRD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 1888 /* We use one Rx return ring. */ 1889 CSR_WRITE_4(sc, ALC_RRD1_HEAD_ADDR_LO, 0); 1890 CSR_WRITE_4(sc, ALC_RRD2_HEAD_ADDR_LO, 0); 1891 CSR_WRITE_4(sc, ALC_RRD3_HEAD_ADDR_LO, 0); 1892 /* Set Rx return descriptor counter. */ 1893 CSR_WRITE_4(sc, ALC_RRD_RING_CNT, 1894 (ALC_RR_RING_CNT << RRD_RING_CNT_SHIFT) & RRD_RING_CNT_MASK); 1895 paddr = sc->alc_rdata.alc_cmb_paddr; 1896 CSR_WRITE_4(sc, ALC_CMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 1897 paddr = sc->alc_rdata.alc_smb_paddr; 1898 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 1899 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 1900 1901 /* Tell hardware that we're ready to load DMA blocks. */ 1902 CSR_WRITE_4(sc, ALC_DMA_BLOCK, DMA_BLOCK_LOAD); 1903 1904 /* Configure interrupt moderation timer. */ 1905 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 1906 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 1907 reg = ALC_USECS(sc->alc_int_rx_mod) << IM_TIMER_RX_SHIFT; 1908 reg |= ALC_USECS(sc->alc_int_tx_mod) << IM_TIMER_TX_SHIFT; 1909 CSR_WRITE_4(sc, ALC_IM_TIMER, reg); 1910 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 1911 reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK); 1912 /* 1913 * We don't want to automatic interrupt clear as task queue 1914 * for the interrupt should know interrupt status. 1915 */ 1916 reg &= ~MASTER_INTR_RD_CLR; 1917 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); 1918 if (ALC_USECS(sc->alc_int_rx_mod) != 0) 1919 reg |= MASTER_IM_RX_TIMER_ENB; 1920 if (ALC_USECS(sc->alc_int_tx_mod) != 0) 1921 reg |= MASTER_IM_TX_TIMER_ENB; 1922 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 1923 /* 1924 * Disable interrupt re-trigger timer. We don't want automatic 1925 * re-triggering of un-ACKed interrupts. 1926 */ 1927 CSR_WRITE_4(sc, ALC_INTR_RETRIG_TIMER, ALC_USECS(0)); 1928 /* Configure CMB. */ 1929 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, 4); 1930 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 1931 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(5000)); 1932 else 1933 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(0)); 1934 /* 1935 * Hardware can be configured to issue SMB interrupt based 1936 * on programmed interval. Since there is a callout that is 1937 * invoked for every hz in driver we use that instead of 1938 * relying on periodic SMB interrupt. 1939 */ 1940 CSR_WRITE_4(sc, ALC_SMB_STAT_TIMER, ALC_USECS(0)); 1941 /* Clear MAC statistics. */ 1942 alc_stats_clear(sc); 1943 1944 /* 1945 * Always use maximum frame size that controller can support. 1946 * Otherwise received frames that has larger frame length 1947 * than alc(4) MTU would be silently dropped in hardware. This 1948 * would make path-MTU discovery hard as sender wouldn't get 1949 * any responses from receiver. alc(4) supports 1950 * multi-fragmented frames on Rx path so it has no issue on 1951 * assembling fragmented frames. Using maximum frame size also 1952 * removes the need to reinitialize hardware when interface 1953 * MTU configuration was changed. 1954 * 1955 * Be conservative in what you do, be liberal in what you 1956 * accept from others - RFC 793. 1957 */ 1958 CSR_WRITE_4(sc, ALC_FRAME_SIZE, ALC_JUMBO_FRAMELEN); 1959 1960 /* Disable header split(?) */ 1961 CSR_WRITE_4(sc, ALC_HDS_CFG, 0); 1962 1963 /* Configure IPG/IFG parameters. */ 1964 CSR_WRITE_4(sc, ALC_IPG_IFG_CFG, 1965 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) | 1966 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 1967 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 1968 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK)); 1969 /* Set parameters for half-duplex media. */ 1970 CSR_WRITE_4(sc, ALC_HDPX_CFG, 1971 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 1972 HDPX_CFG_LCOL_MASK) | 1973 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 1974 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 1975 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 1976 HDPX_CFG_ABEBT_MASK) | 1977 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 1978 HDPX_CFG_JAMIPG_MASK)); 1979 /* 1980 * Set TSO/checksum offload threshold. For frames that is 1981 * larger than this threshold, hardware wouldn't do 1982 * TSO/checksum offloading. 1983 */ 1984 CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH, 1985 (ALC_JUMBO_FRAMELEN >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) & 1986 TSO_OFFLOAD_THRESH_MASK); 1987 /* Configure TxQ. */ 1988 reg = (alc_dma_burst[sc->alc_dma_rd_burst] << 1989 TXQ_CFG_TX_FIFO_BURST_SHIFT) & TXQ_CFG_TX_FIFO_BURST_MASK; 1990 reg |= (TXQ_CFG_TD_BURST_DEFAULT << TXQ_CFG_TD_BURST_SHIFT) & 1991 TXQ_CFG_TD_BURST_MASK; 1992 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE); 1993 1994 /* Configure Rx free descriptor pre-fetching. */ 1995 CSR_WRITE_4(sc, ALC_RX_RD_FREE_THRESH, 1996 ((RX_RD_FREE_THRESH_HI_DEFAULT << RX_RD_FREE_THRESH_HI_SHIFT) & 1997 RX_RD_FREE_THRESH_HI_MASK) | 1998 ((RX_RD_FREE_THRESH_LO_DEFAULT << RX_RD_FREE_THRESH_LO_SHIFT) & 1999 RX_RD_FREE_THRESH_LO_MASK)); 2000 2001 /* 2002 * Configure flow control parameters. 2003 * XON : 80% of Rx FIFO 2004 * XOFF : 30% of Rx FIFO 2005 */ 2006 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 2007 rxf_hi = (reg * 8) / 10; 2008 rxf_lo = (reg * 3)/ 10; 2009 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 2010 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 2011 RX_FIFO_PAUSE_THRESH_LO_MASK) | 2012 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 2013 RX_FIFO_PAUSE_THRESH_HI_MASK)); 2014 2015 /* Disable RSS until I understand L1C/L2C's RSS logic. */ 2016 CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0); 2017 CSR_WRITE_4(sc, ALC_RSS_CPU, 0); 2018 2019 /* Configure RxQ. */ 2020 reg = (RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 2021 RXQ_CFG_RD_BURST_MASK; 2022 reg |= RXQ_CFG_RSS_MODE_DIS; 2023 if ((sc->alc_flags & ALC_FLAG_ASPM_MON) != 0) 2024 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M; 2025 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 2026 2027 /* Configure Rx DMAW request thresold. */ 2028 CSR_WRITE_4(sc, ALC_RD_DMA_CFG, 2029 ((RD_DMA_CFG_THRESH_DEFAULT << RD_DMA_CFG_THRESH_SHIFT) & 2030 RD_DMA_CFG_THRESH_MASK) | 2031 ((ALC_RD_DMA_CFG_USECS(0) << RD_DMA_CFG_TIMER_SHIFT) & 2032 RD_DMA_CFG_TIMER_MASK)); 2033 /* Configure DMA parameters. */ 2034 reg = DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI; 2035 reg |= sc->alc_rcb; 2036 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 2037 reg |= DMA_CFG_CMB_ENB; 2038 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) 2039 reg |= DMA_CFG_SMB_ENB; 2040 else 2041 reg |= DMA_CFG_SMB_DIS; 2042 reg |= (sc->alc_dma_rd_burst & DMA_CFG_RD_BURST_MASK) << 2043 DMA_CFG_RD_BURST_SHIFT; 2044 reg |= (sc->alc_dma_wr_burst & DMA_CFG_WR_BURST_MASK) << 2045 DMA_CFG_WR_BURST_SHIFT; 2046 reg |= (DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 2047 DMA_CFG_RD_DELAY_CNT_MASK; 2048 reg |= (DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 2049 DMA_CFG_WR_DELAY_CNT_MASK; 2050 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 2051 2052 /* 2053 * Configure Tx/Rx MACs. 2054 * - Auto-padding for short frames. 2055 * - Enable CRC generation. 2056 * Actual reconfiguration of MAC for resolved speed/duplex 2057 * is followed after detection of link establishment. 2058 * AR8131/AR8132 always does checksum computation regardless 2059 * of MAC_CFG_RXCSUM_ENB bit. Also the controller is known to 2060 * have bug in protocol field in Rx return structure so 2061 * these controllers can't handle fragmented frames. Disable 2062 * Rx checksum offloading until there is a newer controller 2063 * that has sane implementation. 2064 */ 2065 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 2066 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 2067 MAC_CFG_PREAMBLE_MASK); 2068 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0) 2069 reg |= MAC_CFG_SPEED_10_100; 2070 else 2071 reg |= MAC_CFG_SPEED_1000; 2072 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 2073 2074 /* Set up the receive filter. */ 2075 alc_rxfilter(sc); 2076 alc_rxvlan(sc); 2077 2078 /* Acknowledge all pending interrupts and clear it. */ 2079 CSR_WRITE_4(sc, ALC_INTR_MASK, ALC_INTRS); 2080 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 2081 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0); 2082 2083 sc->alc_flags &= ~ALC_FLAG_LINK; 2084 /* Switch to the current media. */ 2085 mii = &sc->sc_miibus; 2086 mii_mediachg(mii); 2087 2088 timeout_add_sec(&sc->alc_tick_ch, 1); 2089 2090 ifp->if_flags |= IFF_RUNNING; 2091 ifp->if_flags &= ~IFF_OACTIVE; 2092 2093 return (0); 2094 } 2095 2096 void 2097 alc_stop(struct alc_softc *sc) 2098 { 2099 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 2100 struct alc_txdesc *txd; 2101 struct alc_rxdesc *rxd; 2102 uint32_t reg; 2103 int i; 2104 2105 /* 2106 * Mark the interface down and cancel the watchdog timer. 2107 */ 2108 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2109 ifp->if_timer = 0; 2110 2111 timeout_del(&sc->alc_tick_ch); 2112 sc->alc_flags &= ~ALC_FLAG_LINK; 2113 2114 alc_stats_update(sc); 2115 2116 /* Disable interrupts. */ 2117 CSR_WRITE_4(sc, ALC_INTR_MASK, 0); 2118 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 2119 alc_stop_queue(sc); 2120 2121 /* Disable DMA. */ 2122 reg = CSR_READ_4(sc, ALC_DMA_CFG); 2123 reg &= ~(DMA_CFG_CMB_ENB | DMA_CFG_SMB_ENB); 2124 reg |= DMA_CFG_SMB_DIS; 2125 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 2126 DELAY(1000); 2127 2128 /* Stop Rx/Tx MACs. */ 2129 alc_stop_mac(sc); 2130 2131 /* Disable interrupts which might be touched in taskq handler. */ 2132 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 2133 2134 /* Reclaim Rx buffers that have been processed. */ 2135 if (sc->alc_cdata.alc_rxhead != NULL) 2136 m_freem(sc->alc_cdata.alc_rxhead); 2137 ALC_RXCHAIN_RESET(sc); 2138 /* 2139 * Free Tx/Rx mbufs still in the queues. 2140 */ 2141 for (i = 0; i < ALC_RX_RING_CNT; i++) { 2142 rxd = &sc->alc_cdata.alc_rxdesc[i]; 2143 if (rxd->rx_m != NULL) { 2144 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 2145 m_freem(rxd->rx_m); 2146 rxd->rx_m = NULL; 2147 } 2148 } 2149 for (i = 0; i < ALC_TX_RING_CNT; i++) { 2150 txd = &sc->alc_cdata.alc_txdesc[i]; 2151 if (txd->tx_m != NULL) { 2152 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 2153 m_freem(txd->tx_m); 2154 txd->tx_m = NULL; 2155 } 2156 } 2157 } 2158 2159 void 2160 alc_stop_mac(struct alc_softc *sc) 2161 { 2162 uint32_t reg; 2163 int i; 2164 2165 /* Disable Rx/Tx MAC. */ 2166 reg = CSR_READ_4(sc, ALC_MAC_CFG); 2167 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 2168 reg &= ~MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 2169 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 2170 } 2171 for (i = ALC_TIMEOUT; i > 0; i--) { 2172 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 2173 if (reg == 0) 2174 break; 2175 DELAY(10); 2176 } 2177 if (i == 0) 2178 printf("%s: could not disable Rx/Tx MAC(0x%08x)!\n", 2179 sc->sc_dev.dv_xname, reg); 2180 } 2181 2182 void 2183 alc_start_queue(struct alc_softc *sc) 2184 { 2185 uint32_t qcfg[] = { 2186 0, 2187 RXQ_CFG_QUEUE0_ENB, 2188 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB, 2189 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | RXQ_CFG_QUEUE2_ENB, 2190 RXQ_CFG_ENB 2191 }; 2192 uint32_t cfg; 2193 2194 /* Enable RxQ. */ 2195 cfg = CSR_READ_4(sc, ALC_RXQ_CFG); 2196 cfg &= ~RXQ_CFG_ENB; 2197 cfg |= qcfg[1]; 2198 CSR_WRITE_4(sc, ALC_RXQ_CFG, cfg); 2199 /* Enable TxQ. */ 2200 cfg = CSR_READ_4(sc, ALC_TXQ_CFG); 2201 cfg |= TXQ_CFG_ENB; 2202 CSR_WRITE_4(sc, ALC_TXQ_CFG, cfg); 2203 } 2204 2205 void 2206 alc_stop_queue(struct alc_softc *sc) 2207 { 2208 uint32_t reg; 2209 int i; 2210 2211 /* Disable RxQ. */ 2212 reg = CSR_READ_4(sc, ALC_RXQ_CFG); 2213 if ((reg & RXQ_CFG_ENB) != 0) { 2214 reg &= ~RXQ_CFG_ENB; 2215 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 2216 } 2217 /* Disable TxQ. */ 2218 reg = CSR_READ_4(sc, ALC_TXQ_CFG); 2219 if ((reg & TXQ_CFG_ENB) == 0) { 2220 reg &= ~TXQ_CFG_ENB; 2221 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg); 2222 } 2223 for (i = ALC_TIMEOUT; i > 0; i--) { 2224 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 2225 if ((reg & (IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 2226 break; 2227 DELAY(10); 2228 } 2229 if (i == 0) 2230 printf("%s: could not disable RxQ/TxQ (0x%08x)!\n", 2231 sc->sc_dev.dv_xname, reg); 2232 } 2233 2234 void 2235 alc_init_tx_ring(struct alc_softc *sc) 2236 { 2237 struct alc_ring_data *rd; 2238 struct alc_txdesc *txd; 2239 int i; 2240 2241 sc->alc_cdata.alc_tx_prod = 0; 2242 sc->alc_cdata.alc_tx_cons = 0; 2243 sc->alc_cdata.alc_tx_cnt = 0; 2244 2245 rd = &sc->alc_rdata; 2246 bzero(rd->alc_tx_ring, ALC_TX_RING_SZ); 2247 for (i = 0; i < ALC_TX_RING_CNT; i++) { 2248 txd = &sc->alc_cdata.alc_txdesc[i]; 2249 txd->tx_m = NULL; 2250 } 2251 2252 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0, 2253 sc->alc_cdata.alc_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2254 } 2255 2256 int 2257 alc_init_rx_ring(struct alc_softc *sc) 2258 { 2259 struct alc_ring_data *rd; 2260 struct alc_rxdesc *rxd; 2261 int i; 2262 2263 sc->alc_cdata.alc_rx_cons = ALC_RX_RING_CNT - 1; 2264 rd = &sc->alc_rdata; 2265 bzero(rd->alc_rx_ring, ALC_RX_RING_SZ); 2266 for (i = 0; i < ALC_RX_RING_CNT; i++) { 2267 rxd = &sc->alc_cdata.alc_rxdesc[i]; 2268 rxd->rx_m = NULL; 2269 rxd->rx_desc = &rd->alc_rx_ring[i]; 2270 if (alc_newbuf(sc, rxd, 1) != 0) 2271 return (ENOBUFS); 2272 } 2273 2274 /* 2275 * Since controller does not update Rx descriptors, driver 2276 * does have to read Rx descriptors back so BUS_DMASYNC_PREWRITE 2277 * is enough to ensure coherence. 2278 */ 2279 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 0, 2280 sc->alc_cdata.alc_rx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2281 /* Let controller know availability of new Rx buffers. */ 2282 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, sc->alc_cdata.alc_rx_cons); 2283 2284 return (0); 2285 } 2286 2287 void 2288 alc_init_rr_ring(struct alc_softc *sc) 2289 { 2290 struct alc_ring_data *rd; 2291 2292 sc->alc_cdata.alc_rr_cons = 0; 2293 ALC_RXCHAIN_RESET(sc); 2294 2295 rd = &sc->alc_rdata; 2296 bzero(rd->alc_rr_ring, ALC_RR_RING_SZ); 2297 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 0, 2298 sc->alc_cdata.alc_rr_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2299 } 2300 2301 void 2302 alc_init_cmb(struct alc_softc *sc) 2303 { 2304 struct alc_ring_data *rd; 2305 2306 rd = &sc->alc_rdata; 2307 bzero(rd->alc_cmb, ALC_CMB_SZ); 2308 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0, 2309 sc->alc_cdata.alc_cmb_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2310 } 2311 2312 void 2313 alc_init_smb(struct alc_softc *sc) 2314 { 2315 struct alc_ring_data *rd; 2316 2317 rd = &sc->alc_rdata; 2318 bzero(rd->alc_smb, ALC_SMB_SZ); 2319 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 2320 sc->alc_cdata.alc_smb_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2321 } 2322 2323 void 2324 alc_rxvlan(struct alc_softc *sc) 2325 { 2326 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 2327 uint32_t reg; 2328 2329 reg = CSR_READ_4(sc, ALC_MAC_CFG); 2330 if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) 2331 reg |= MAC_CFG_VLAN_TAG_STRIP; 2332 else 2333 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 2334 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 2335 } 2336 2337 void 2338 alc_rxfilter(struct alc_softc *sc) 2339 { 2340 struct arpcom *ac = &sc->sc_arpcom; 2341 struct ifnet *ifp = &ac->ac_if; 2342 struct ether_multi *enm; 2343 struct ether_multistep step; 2344 uint32_t crc; 2345 uint32_t mchash[2]; 2346 uint32_t rxcfg; 2347 2348 rxcfg = CSR_READ_4(sc, ALC_MAC_CFG); 2349 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 2350 ifp->if_flags &= ~IFF_ALLMULTI; 2351 2352 /* 2353 * Always accept broadcast frames. 2354 */ 2355 rxcfg |= MAC_CFG_BCAST; 2356 2357 if (ifp->if_flags & IFF_PROMISC || ac->ac_multirangecnt > 0) { 2358 ifp->if_flags |= IFF_ALLMULTI; 2359 if (ifp->if_flags & IFF_PROMISC) 2360 rxcfg |= MAC_CFG_PROMISC; 2361 else 2362 rxcfg |= MAC_CFG_ALLMULTI; 2363 mchash[0] = mchash[1] = 0xFFFFFFFF; 2364 } else { 2365 /* Program new filter. */ 2366 bzero(mchash, sizeof(mchash)); 2367 2368 ETHER_FIRST_MULTI(step, ac, enm); 2369 while (enm != NULL) { 2370 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 2371 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 2372 ETHER_NEXT_MULTI(step, enm); 2373 } 2374 } 2375 2376 CSR_WRITE_4(sc, ALC_MAR0, mchash[0]); 2377 CSR_WRITE_4(sc, ALC_MAR1, mchash[1]); 2378 CSR_WRITE_4(sc, ALC_MAC_CFG, rxcfg); 2379 } 2380