1 /* $OpenBSD: if_alc.c,v 1.57 2023/11/10 15:51:20 bluhm Exp $ */ 2 /*- 3 * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* Driver for Atheros AR813x/AR815x/AR816x/AR817x PCIe Ethernet. */ 30 31 #include "bpfilter.h" 32 #include "vlan.h" 33 34 #include <sys/param.h> 35 #include <sys/endian.h> 36 #include <sys/systm.h> 37 #include <sys/sockio.h> 38 #include <sys/mbuf.h> 39 #include <sys/queue.h> 40 #include <sys/kernel.h> 41 #include <sys/device.h> 42 #include <sys/timeout.h> 43 #include <sys/socket.h> 44 45 #include <machine/bus.h> 46 47 #include <net/if.h> 48 #include <net/if_dl.h> 49 #include <net/if_media.h> 50 51 #include <netinet/in.h> 52 #include <netinet/if_ether.h> 53 54 #if NBPFILTER > 0 55 #include <net/bpf.h> 56 #endif 57 58 #include <dev/mii/mii.h> 59 #include <dev/mii/miivar.h> 60 61 #include <dev/pci/pcireg.h> 62 #include <dev/pci/pcivar.h> 63 #include <dev/pci/pcidevs.h> 64 65 #include <dev/pci/if_alcreg.h> 66 67 int alc_match(struct device *, void *, void *); 68 void alc_attach(struct device *, struct device *, void *); 69 int alc_detach(struct device *, int); 70 int alc_activate(struct device *, int); 71 72 int alc_init(struct ifnet *); 73 void alc_start(struct ifnet *); 74 int alc_ioctl(struct ifnet *, u_long, caddr_t); 75 void alc_watchdog(struct ifnet *); 76 int alc_mediachange(struct ifnet *); 77 void alc_mediastatus(struct ifnet *, struct ifmediareq *); 78 79 void alc_aspm(struct alc_softc *, int, uint64_t); 80 void alc_aspm_813x(struct alc_softc *, uint64_t); 81 void alc_aspm_816x(struct alc_softc *, int); 82 void alc_disable_l0s_l1(struct alc_softc *); 83 int alc_dma_alloc(struct alc_softc *); 84 void alc_dma_free(struct alc_softc *); 85 int alc_encap(struct alc_softc *, struct mbuf *); 86 void alc_get_macaddr(struct alc_softc *); 87 void alc_get_macaddr_813x(struct alc_softc *); 88 void alc_get_macaddr_816x(struct alc_softc *); 89 void alc_get_macaddr_par(struct alc_softc *); 90 void alc_init_cmb(struct alc_softc *); 91 void alc_init_rr_ring(struct alc_softc *); 92 int alc_init_rx_ring(struct alc_softc *); 93 void alc_init_smb(struct alc_softc *); 94 void alc_init_tx_ring(struct alc_softc *); 95 int alc_intr(void *); 96 void alc_mac_config(struct alc_softc *); 97 int alc_mii_readreg_813x(struct device *, int, int); 98 int alc_mii_readreg_816x(struct device *, int, int); 99 void alc_mii_writereg_813x(struct device *, int, int, int); 100 void alc_mii_writereg_816x(struct device *, int, int, int); 101 void alc_dsp_fixup(struct alc_softc *, int); 102 int alc_miibus_readreg(struct device *, int, int); 103 void alc_miibus_statchg(struct device *); 104 void alc_miibus_writereg(struct device *, int, int, int); 105 int alc_miidbg_readreg(struct alc_softc *, int); 106 void alc_miidbg_writereg(struct alc_softc *, int, int); 107 int alc_miiext_readreg(struct alc_softc *, int, int); 108 void alc_miiext_writereg(struct alc_softc *, int, int, int); 109 void alc_phy_reset_813x(struct alc_softc *); 110 void alc_phy_reset_816x(struct alc_softc *); 111 int alc_newbuf(struct alc_softc *, struct alc_rxdesc *); 112 void alc_phy_down(struct alc_softc *); 113 void alc_phy_reset(struct alc_softc *); 114 void alc_reset(struct alc_softc *); 115 void alc_rxeof(struct alc_softc *, struct rx_rdesc *); 116 int alc_rxintr(struct alc_softc *); 117 void alc_iff(struct alc_softc *); 118 void alc_rxvlan(struct alc_softc *); 119 void alc_start_queue(struct alc_softc *); 120 void alc_stats_clear(struct alc_softc *); 121 void alc_stats_update(struct alc_softc *); 122 void alc_stop(struct alc_softc *); 123 void alc_stop_mac(struct alc_softc *); 124 void alc_stop_queue(struct alc_softc *); 125 void alc_tick(void *); 126 void alc_txeof(struct alc_softc *); 127 void alc_init_pcie(struct alc_softc *, int); 128 void alc_config_msi(struct alc_softc *); 129 int alc_dma_alloc(struct alc_softc *); 130 void alc_dma_free(struct alc_softc *); 131 int alc_encap(struct alc_softc *, struct mbuf *); 132 void alc_osc_reset(struct alc_softc *); 133 134 uint32_t alc_dma_burst[] = { 128, 256, 512, 1024, 2048, 4096, 0, 0 }; 135 136 const struct pci_matchid alc_devices[] = { 137 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L1C }, 138 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L2C }, 139 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L1D }, 140 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L1D_1 }, 141 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L2C_1 }, 142 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L2C_2 }, 143 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8161 }, 144 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8162 }, 145 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8171 }, 146 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8172 }, 147 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_E2200 }, 148 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_E2400 }, 149 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_E2500 } 150 }; 151 152 const struct cfattach alc_ca = { 153 sizeof (struct alc_softc), alc_match, alc_attach, alc_detach, 154 alc_activate 155 }; 156 157 struct cfdriver alc_cd = { 158 NULL, "alc", DV_IFNET 159 }; 160 161 int alcdebug = 0; 162 #define DPRINTF(x) do { if (alcdebug) printf x; } while (0) 163 164 #define ALC_CSUM_FEATURES (M_TCP_CSUM_OUT | M_UDP_CSUM_OUT) 165 166 int 167 alc_miibus_readreg(struct device *dev, int phy, int reg) 168 { 169 struct alc_softc *sc = (struct alc_softc *)dev; 170 uint32_t v; 171 172 if (phy != sc->alc_phyaddr) 173 return (0); 174 175 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 176 v = alc_mii_readreg_816x(dev, phy, reg); 177 else 178 v = alc_mii_readreg_813x(dev, phy, reg); 179 180 return (v); 181 } 182 183 int 184 alc_mii_readreg_813x(struct device *dev, int phy, int reg) 185 { 186 struct alc_softc *sc = (struct alc_softc *)dev; 187 uint32_t v; 188 int i; 189 190 /* 191 * For AR8132 fast ethernet controller, do not report 1000baseT 192 * capability to mii(4). Even though AR8132 uses the same 193 * model/revision number of F1 gigabit PHY, the PHY has no 194 * ability to establish 1000baseT link. 195 */ 196 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0 && 197 reg == MII_EXTSR) 198 return (0); 199 200 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 201 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 202 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 203 DELAY(5); 204 v = CSR_READ_4(sc, ALC_MDIO); 205 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 206 break; 207 } 208 209 if (i == 0) { 210 printf("%s: phy read timeout: phy %d, reg %d\n", 211 sc->sc_dev.dv_xname, phy, reg); 212 return (0); 213 } 214 215 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 216 } 217 218 int 219 alc_mii_readreg_816x(struct device *dev, int phy, int reg) 220 { 221 struct alc_softc *sc = (struct alc_softc *)dev; 222 uint32_t clk, v; 223 int i; 224 225 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 226 clk = MDIO_CLK_25_128; 227 else 228 clk = MDIO_CLK_25_4; 229 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 230 MDIO_SUP_PREAMBLE | clk | MDIO_REG_ADDR(reg)); 231 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 232 DELAY(5); 233 v = CSR_READ_4(sc, ALC_MDIO); 234 if ((v & MDIO_OP_BUSY) == 0) 235 break; 236 } 237 238 if (i == 0) { 239 printf("%s: phy read timeout: phy %d, reg %d\n", 240 sc->sc_dev.dv_xname, phy, reg); 241 return (0); 242 } 243 244 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 245 } 246 247 void 248 alc_miibus_writereg(struct device *dev, int phy, int reg, int val) 249 { 250 struct alc_softc *sc = (struct alc_softc *)dev; 251 252 if (phy != sc->alc_phyaddr) 253 return; 254 255 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 256 alc_mii_writereg_816x(dev, phy, reg, val); 257 else 258 alc_mii_writereg_813x(dev, phy, reg, val); 259 } 260 261 void 262 alc_mii_writereg_813x(struct device *dev, int phy, int reg, int val) 263 { 264 struct alc_softc *sc = (struct alc_softc *)dev; 265 uint32_t v; 266 int i; 267 268 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 269 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 270 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 271 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 272 DELAY(5); 273 v = CSR_READ_4(sc, ALC_MDIO); 274 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 275 break; 276 } 277 278 if (i == 0) 279 printf("%s: phy write timeout: phy %d, reg %d\n", 280 sc->sc_dev.dv_xname, phy, reg); 281 } 282 283 void 284 alc_mii_writereg_816x(struct device *dev, int phy, int reg, int val) 285 { 286 struct alc_softc *sc = (struct alc_softc *)dev; 287 uint32_t clk, v; 288 int i; 289 290 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 291 clk = MDIO_CLK_25_128; 292 else 293 clk = MDIO_CLK_25_4; 294 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 295 ((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) | MDIO_REG_ADDR(reg) | 296 MDIO_SUP_PREAMBLE | clk); 297 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 298 DELAY(5); 299 v = CSR_READ_4(sc, ALC_MDIO); 300 if ((v & MDIO_OP_BUSY) == 0) 301 break; 302 } 303 304 if (i == 0) 305 printf("%s: phy write timeout: phy %d, reg %d\n", 306 sc->sc_dev.dv_xname, phy, reg); 307 } 308 309 void 310 alc_miibus_statchg(struct device *dev) 311 { 312 struct alc_softc *sc = (struct alc_softc *)dev; 313 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 314 struct mii_data *mii = &sc->sc_miibus; 315 uint32_t reg; 316 317 if ((ifp->if_flags & IFF_RUNNING) == 0) 318 return; 319 320 sc->alc_flags &= ~ALC_FLAG_LINK; 321 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 322 (IFM_ACTIVE | IFM_AVALID)) { 323 switch (IFM_SUBTYPE(mii->mii_media_active)) { 324 case IFM_10_T: 325 case IFM_100_TX: 326 sc->alc_flags |= ALC_FLAG_LINK; 327 break; 328 case IFM_1000_T: 329 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 330 sc->alc_flags |= ALC_FLAG_LINK; 331 break; 332 default: 333 break; 334 } 335 } 336 /* Stop Rx/Tx MACs. */ 337 alc_stop_mac(sc); 338 339 /* Program MACs with resolved speed/duplex/flow-control. */ 340 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 341 alc_start_queue(sc); 342 alc_mac_config(sc); 343 /* Re-enable Tx/Rx MACs. */ 344 reg = CSR_READ_4(sc, ALC_MAC_CFG); 345 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 346 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 347 } 348 alc_aspm(sc, 0, IFM_SUBTYPE(mii->mii_media_active)); 349 alc_dsp_fixup(sc, IFM_SUBTYPE(mii->mii_media_active)); 350 } 351 352 int 353 alc_miidbg_readreg(struct alc_softc *sc, int reg) 354 { 355 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 356 reg); 357 return (alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr, 358 ALC_MII_DBG_DATA)); 359 } 360 361 362 void 363 alc_miidbg_writereg(struct alc_softc *sc, int reg, int val) 364 { 365 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 366 reg); 367 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 368 val); 369 } 370 371 int 372 alc_miiext_readreg(struct alc_softc *sc, int devaddr, int reg) 373 { 374 uint32_t clk, v; 375 int i; 376 377 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | 378 EXT_MDIO_DEVADDR(devaddr)); 379 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 380 clk = MDIO_CLK_25_128; 381 else 382 clk = MDIO_CLK_25_4; 383 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 384 MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT); 385 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 386 DELAY(5); 387 v = CSR_READ_4(sc, ALC_MDIO); 388 if ((v & MDIO_OP_BUSY) == 0) 389 break; 390 } 391 392 if (i == 0) { 393 printf("%s: phy ext read timeout: phy %d, reg %d\n", 394 sc->sc_dev.dv_xname, devaddr, reg); 395 return (0); 396 } 397 398 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 399 } 400 401 void 402 alc_miiext_writereg(struct alc_softc *sc, int devaddr, int reg, int val) 403 { 404 uint32_t clk, v; 405 int i; 406 407 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | 408 EXT_MDIO_DEVADDR(devaddr)); 409 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 410 clk = MDIO_CLK_25_128; 411 else 412 clk = MDIO_CLK_25_4; 413 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 414 ((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) | 415 MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT); 416 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 417 DELAY(5); 418 v = CSR_READ_4(sc, ALC_MDIO); 419 if ((v & MDIO_OP_BUSY) == 0) 420 break; 421 } 422 423 if (i == 0) 424 printf("%s: phy ext write timeout: phy %d, reg %d\n", 425 sc->sc_dev.dv_xname, devaddr, reg); 426 } 427 428 void 429 alc_dsp_fixup(struct alc_softc *sc, int media) 430 { 431 uint16_t agc, len, val; 432 433 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 434 return; 435 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_C0) 436 return; 437 438 /* 439 * Vendor PHY magic. 440 * 1000BT/AZ, wrong cable length 441 */ 442 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 443 len = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL6); 444 len = (len >> EXT_CLDCTL6_CAB_LEN_SHIFT) & 445 EXT_CLDCTL6_CAB_LEN_MASK; 446 agc = alc_miidbg_readreg(sc, MII_DBG_AGC); 447 agc = (agc >> DBG_AGC_2_VGA_SHIFT) & DBG_AGC_2_VGA_MASK; 448 if ((media == IFM_1000_T && len > EXT_CLDCTL6_CAB_LEN_SHORT1G && 449 agc > DBG_AGC_LONG1G_LIMT) || 450 (media == IFM_100_TX && len > DBG_AGC_LONG100M_LIMT && 451 agc > DBG_AGC_LONG1G_LIMT)) { 452 alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT, 453 DBG_AZ_ANADECT_LONG); 454 val = alc_miiext_readreg(sc, MII_EXT_ANEG, 455 MII_EXT_ANEG_AFE); 456 val |= ANEG_AFEE_10BT_100M_TH; 457 alc_miiext_writereg(sc, MII_EXT_ANEG, 458 MII_EXT_ANEG_AFE, val); 459 } else { 460 alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT, 461 DBG_AZ_ANADECT_DEFAULT); 462 val = alc_miiext_readreg(sc, MII_EXT_ANEG, 463 MII_EXT_ANEG_AFE); 464 val &= ~ANEG_AFEE_10BT_100M_TH; 465 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, 466 val); 467 } 468 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 && 469 AR816X_REV(sc->alc_rev) == AR816X_REV_B0) { 470 if (media == IFM_1000_T) { 471 /* 472 * Giga link threshold, raise the tolerance of 473 * noise 50%. 474 */ 475 val = alc_miidbg_readreg(sc, MII_DBG_MSE20DB); 476 val &= ~DBG_MSE20DB_TH_MASK; 477 val |= (DBG_MSE20DB_TH_HI << 478 DBG_MSE20DB_TH_SHIFT); 479 alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val); 480 } else if (media == IFM_100_TX) 481 alc_miidbg_writereg(sc, MII_DBG_MSE16DB, 482 DBG_MSE16DB_UP); 483 } 484 } else { 485 val = alc_miiext_readreg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE); 486 val &= ~ANEG_AFEE_10BT_100M_TH; 487 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, val); 488 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 && 489 AR816X_REV(sc->alc_rev) == AR816X_REV_B0) { 490 alc_miidbg_writereg(sc, MII_DBG_MSE16DB, 491 DBG_MSE16DB_DOWN); 492 val = alc_miidbg_readreg(sc, MII_DBG_MSE20DB); 493 val &= ~DBG_MSE20DB_TH_MASK; 494 val |= (DBG_MSE20DB_TH_DEFAULT << DBG_MSE20DB_TH_SHIFT); 495 alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val); 496 } 497 } 498 } 499 500 void 501 alc_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 502 { 503 struct alc_softc *sc = ifp->if_softc; 504 struct mii_data *mii = &sc->sc_miibus; 505 506 if ((ifp->if_flags & IFF_UP) == 0) 507 return; 508 509 mii_pollstat(mii); 510 ifmr->ifm_status = mii->mii_media_status; 511 ifmr->ifm_active = mii->mii_media_active; 512 } 513 514 int 515 alc_mediachange(struct ifnet *ifp) 516 { 517 struct alc_softc *sc = ifp->if_softc; 518 struct mii_data *mii = &sc->sc_miibus; 519 int error; 520 521 if (mii->mii_instance != 0) { 522 struct mii_softc *miisc; 523 524 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 525 mii_phy_reset(miisc); 526 } 527 error = mii_mediachg(mii); 528 529 return (error); 530 } 531 532 int 533 alc_match(struct device *dev, void *match, void *aux) 534 { 535 return pci_matchbyid((struct pci_attach_args *)aux, alc_devices, 536 nitems(alc_devices)); 537 } 538 539 void 540 alc_get_macaddr(struct alc_softc *sc) 541 { 542 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 543 alc_get_macaddr_816x(sc); 544 else 545 alc_get_macaddr_813x(sc); 546 } 547 548 void 549 alc_get_macaddr_813x(struct alc_softc *sc) 550 { 551 uint32_t opt; 552 uint16_t val; 553 int eeprom, i; 554 555 eeprom = 0; 556 opt = CSR_READ_4(sc, ALC_OPT_CFG); 557 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 && 558 (CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) { 559 /* 560 * EEPROM found, let TWSI reload EEPROM configuration. 561 * This will set ethernet address of controller. 562 */ 563 eeprom++; 564 switch (sc->sc_product) { 565 case PCI_PRODUCT_ATTANSIC_L1C: 566 case PCI_PRODUCT_ATTANSIC_L2C: 567 if ((opt & OPT_CFG_CLK_ENB) == 0) { 568 opt |= OPT_CFG_CLK_ENB; 569 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 570 CSR_READ_4(sc, ALC_OPT_CFG); 571 DELAY(1000); 572 } 573 break; 574 case PCI_PRODUCT_ATTANSIC_L1D: 575 case PCI_PRODUCT_ATTANSIC_L1D_1: 576 case PCI_PRODUCT_ATTANSIC_L2C_1: 577 case PCI_PRODUCT_ATTANSIC_L2C_2: 578 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 579 ALC_MII_DBG_ADDR, 0x00); 580 val = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr, 581 ALC_MII_DBG_DATA); 582 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 583 ALC_MII_DBG_DATA, val & 0xFF7F); 584 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 585 ALC_MII_DBG_ADDR, 0x3B); 586 val = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr, 587 ALC_MII_DBG_DATA); 588 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 589 ALC_MII_DBG_DATA, val | 0x0008); 590 DELAY(20); 591 break; 592 } 593 594 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 595 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 596 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 597 CSR_READ_4(sc, ALC_WOL_CFG); 598 599 CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) | 600 TWSI_CFG_SW_LD_START); 601 for (i = 100; i > 0; i--) { 602 DELAY(1000); 603 if ((CSR_READ_4(sc, ALC_TWSI_CFG) & 604 TWSI_CFG_SW_LD_START) == 0) 605 break; 606 } 607 if (i == 0) 608 printf("%s: reloading EEPROM timeout!\n", 609 sc->sc_dev.dv_xname); 610 } else { 611 if (alcdebug) 612 printf("%s: EEPROM not found!\n", sc->sc_dev.dv_xname); 613 } 614 if (eeprom != 0) { 615 switch (sc->sc_product) { 616 case PCI_PRODUCT_ATTANSIC_L1C: 617 case PCI_PRODUCT_ATTANSIC_L2C: 618 if ((opt & OPT_CFG_CLK_ENB) != 0) { 619 opt &= ~OPT_CFG_CLK_ENB; 620 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 621 CSR_READ_4(sc, ALC_OPT_CFG); 622 DELAY(1000); 623 } 624 break; 625 case PCI_PRODUCT_ATTANSIC_L1D: 626 case PCI_PRODUCT_ATTANSIC_L1D_1: 627 case PCI_PRODUCT_ATTANSIC_L2C_1: 628 case PCI_PRODUCT_ATTANSIC_L2C_2: 629 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 630 ALC_MII_DBG_ADDR, 0x00); 631 val = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr, 632 ALC_MII_DBG_DATA); 633 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 634 ALC_MII_DBG_DATA, val | 0x0080); 635 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 636 ALC_MII_DBG_ADDR, 0x3B); 637 val = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr, 638 ALC_MII_DBG_DATA); 639 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 640 ALC_MII_DBG_DATA, val & 0xFFF7); 641 DELAY(20); 642 break; 643 } 644 } 645 646 alc_get_macaddr_par(sc); 647 } 648 649 void 650 alc_get_macaddr_816x(struct alc_softc *sc) 651 { 652 uint32_t reg; 653 int i, reloaded; 654 655 reloaded = 0; 656 /* Try to reload station address via TWSI. */ 657 for (i = 100; i > 0; i--) { 658 reg = CSR_READ_4(sc, ALC_SLD); 659 if ((reg & (SLD_PROGRESS | SLD_START)) == 0) 660 break; 661 DELAY(1000); 662 } 663 if (i != 0) { 664 CSR_WRITE_4(sc, ALC_SLD, reg | SLD_START); 665 for (i = 100; i > 0; i--) { 666 DELAY(1000); 667 reg = CSR_READ_4(sc, ALC_SLD); 668 if ((reg & SLD_START) == 0) 669 break; 670 } 671 if (i != 0) 672 reloaded++; 673 else if (alcdebug) 674 printf("%s: reloading station address via TWSI timed" 675 "out!\n", sc->sc_dev.dv_xname); 676 } 677 678 /* Try to reload station address from EEPROM or FLASH. */ 679 if (reloaded == 0) { 680 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 681 if ((reg & (EEPROM_LD_EEPROM_EXIST | 682 EEPROM_LD_FLASH_EXIST)) != 0) { 683 for (i = 100; i > 0; i--) { 684 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 685 if ((reg & (EEPROM_LD_PROGRESS | 686 EEPROM_LD_START)) == 0) 687 break; 688 DELAY(1000); 689 } 690 if (i != 0) { 691 CSR_WRITE_4(sc, ALC_EEPROM_LD, reg | 692 EEPROM_LD_START); 693 for (i = 100; i > 0; i--) { 694 DELAY(1000); 695 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 696 if ((reg & EEPROM_LD_START) == 0) 697 break; 698 } 699 } else if (alcdebug) 700 printf("%s: reloading EEPROM/FLASH timed out!\n", 701 sc->sc_dev.dv_xname); 702 } 703 } 704 705 alc_get_macaddr_par(sc); 706 } 707 708 void 709 alc_get_macaddr_par(struct alc_softc *sc) 710 { 711 uint32_t ea[2]; 712 713 ea[0] = CSR_READ_4(sc, ALC_PAR0); 714 ea[1] = CSR_READ_4(sc, ALC_PAR1); 715 sc->alc_eaddr[0] = (ea[1] >> 8) & 0xFF; 716 sc->alc_eaddr[1] = (ea[1] >> 0) & 0xFF; 717 sc->alc_eaddr[2] = (ea[0] >> 24) & 0xFF; 718 sc->alc_eaddr[3] = (ea[0] >> 16) & 0xFF; 719 sc->alc_eaddr[4] = (ea[0] >> 8) & 0xFF; 720 sc->alc_eaddr[5] = (ea[0] >> 0) & 0xFF; 721 } 722 723 void 724 alc_disable_l0s_l1(struct alc_softc *sc) 725 { 726 uint32_t pmcfg; 727 728 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 729 /* Another magic from vendor. */ 730 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 731 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_CLK_SWH_L1 | 732 PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 733 PM_CFG_MAC_ASPM_CHK | PM_CFG_SERDES_PD_EX_L1); 734 pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB | 735 PM_CFG_SERDES_PLL_L1_ENB | PM_CFG_SERDES_L1_ENB; 736 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 737 } 738 } 739 740 void 741 alc_phy_reset(struct alc_softc *sc) 742 { 743 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 744 alc_phy_reset_816x(sc); 745 else 746 alc_phy_reset_813x(sc); 747 } 748 749 void 750 alc_phy_reset_813x(struct alc_softc *sc) 751 { 752 uint16_t data; 753 754 /* Reset magic from Linux. */ 755 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_SEL_ANA_RESET); 756 CSR_READ_2(sc, ALC_GPHY_CFG); 757 DELAY(10 * 1000); 758 759 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | 760 GPHY_CFG_SEL_ANA_RESET); 761 CSR_READ_2(sc, ALC_GPHY_CFG); 762 DELAY(10 * 1000); 763 764 /* DSP fixup, Vendor magic. */ 765 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1) { 766 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 767 ALC_MII_DBG_ADDR, 0x000A); 768 data = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr, 769 ALC_MII_DBG_DATA); 770 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 771 ALC_MII_DBG_DATA, data & 0xDFFF); 772 } 773 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D || 774 sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D_1 || 775 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1 || 776 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_2) { 777 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 778 ALC_MII_DBG_ADDR, 0x003B); 779 data = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr, 780 ALC_MII_DBG_DATA); 781 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 782 ALC_MII_DBG_DATA, data & 0xFFF7); 783 DELAY(20 * 1000); 784 } 785 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D) { 786 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 787 ALC_MII_DBG_ADDR, 0x0029); 788 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 789 ALC_MII_DBG_DATA, 0x929D); 790 } 791 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1C || 792 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C || 793 sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D_1 || 794 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_2) { 795 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 796 ALC_MII_DBG_ADDR, 0x0029); 797 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 798 ALC_MII_DBG_DATA, 0xB6DD); 799 } 800 801 /* Load DSP codes, vendor magic. */ 802 data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE | 803 ((1 << ANA_INTERVAL_SEL_TIMER_SHIFT) & ANA_INTERVAL_SEL_TIMER_MASK); 804 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 805 ALC_MII_DBG_ADDR, MII_ANA_CFG18); 806 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 807 ALC_MII_DBG_DATA, data); 808 809 data = ((2 << ANA_SERDES_CDR_BW_SHIFT) & ANA_SERDES_CDR_BW_MASK) | 810 ANA_SERDES_EN_DEEM | ANA_SERDES_SEL_HSP | ANA_SERDES_EN_PLL | 811 ANA_SERDES_EN_LCKDT; 812 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 813 ALC_MII_DBG_ADDR, MII_ANA_CFG5); 814 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 815 ALC_MII_DBG_DATA, data); 816 817 data = ((44 << ANA_LONG_CABLE_TH_100_SHIFT) & 818 ANA_LONG_CABLE_TH_100_MASK) | 819 ((33 << ANA_SHORT_CABLE_TH_100_SHIFT) & 820 ANA_SHORT_CABLE_TH_100_SHIFT) | 821 ANA_BP_BAD_LINK_ACCUM | ANA_BP_SMALL_BW; 822 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 823 ALC_MII_DBG_ADDR, MII_ANA_CFG54); 824 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 825 ALC_MII_DBG_DATA, data); 826 827 data = ((11 << ANA_IECHO_ADJ_3_SHIFT) & ANA_IECHO_ADJ_3_MASK) | 828 ((11 << ANA_IECHO_ADJ_2_SHIFT) & ANA_IECHO_ADJ_2_MASK) | 829 ((8 << ANA_IECHO_ADJ_1_SHIFT) & ANA_IECHO_ADJ_1_MASK) | 830 ((8 << ANA_IECHO_ADJ_0_SHIFT) & ANA_IECHO_ADJ_0_MASK); 831 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 832 ALC_MII_DBG_ADDR, MII_ANA_CFG4); 833 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 834 ALC_MII_DBG_DATA, data); 835 836 data = ((7 & ANA_MANUL_SWICH_ON_SHIFT) & ANA_MANUL_SWICH_ON_MASK) | 837 ANA_RESTART_CAL | ANA_MAN_ENABLE | ANA_SEL_HSP | ANA_EN_HB | 838 ANA_OEN_125M; 839 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 840 ALC_MII_DBG_ADDR, MII_ANA_CFG0); 841 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 842 ALC_MII_DBG_DATA, data); 843 DELAY(1000); 844 845 /* Disable hibernation. */ 846 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 847 0x0029); 848 data = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr, 849 ALC_MII_DBG_DATA); 850 data &= ~0x8000; 851 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 852 data); 853 854 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 855 0x000B); 856 data = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr, 857 ALC_MII_DBG_DATA); 858 data &= ~0x8000; 859 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 860 data); 861 } 862 863 void 864 alc_phy_reset_816x(struct alc_softc *sc) 865 { 866 uint32_t val; 867 868 val = CSR_READ_4(sc, ALC_GPHY_CFG); 869 val &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | 870 GPHY_CFG_GATE_25M_ENB | GPHY_CFG_PHY_IDDQ | GPHY_CFG_PHY_PLL_ON | 871 GPHY_CFG_PWDOWN_HW | GPHY_CFG_100AB_ENB); 872 val |= GPHY_CFG_SEL_ANA_RESET; 873 /* Disable PHY hibernation. */ 874 val &= ~(GPHY_CFG_HIB_PULSE | GPHY_CFG_HIB_EN); 875 CSR_WRITE_4(sc, ALC_GPHY_CFG, val); 876 DELAY(10); 877 CSR_WRITE_4(sc, ALC_GPHY_CFG, val | GPHY_CFG_EXT_RESET); 878 DELAY(800); 879 /* Vendor PHY magic. */ 880 /* Disable PHY hibernation. */ 881 alc_miidbg_writereg(sc, MII_DBG_LEGCYPS, 882 DBG_LEGCYPS_DEFAULT & ~DBG_LEGCYPS_ENB); 883 alc_miidbg_writereg(sc, MII_DBG_HIBNEG, DBG_HIBNEG_DEFAULT & 884 ~(DBG_HIBNEG_PSHIB_EN | DBG_HIBNEG_HIB_PULSE)); 885 alc_miidbg_writereg(sc, MII_DBG_GREENCFG, DBG_GREENCFG_DEFAULT); 886 /* XXX Disable EEE. */ 887 val = CSR_READ_4(sc, ALC_LPI_CTL); 888 val &= ~LPI_CTL_ENB; 889 CSR_WRITE_4(sc, ALC_LPI_CTL, val); 890 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_LOCAL_EEEADV, 0); 891 /* PHY power saving. */ 892 alc_miidbg_writereg(sc, MII_DBG_TST10BTCFG, DBG_TST10BTCFG_DEFAULT); 893 alc_miidbg_writereg(sc, MII_DBG_SRDSYSMOD, DBG_SRDSYSMOD_DEFAULT); 894 alc_miidbg_writereg(sc, MII_DBG_TST100BTCFG, DBG_TST100BTCFG_DEFAULT); 895 alc_miidbg_writereg(sc, MII_DBG_ANACTL, DBG_ANACTL_DEFAULT); 896 val = alc_miidbg_readreg(sc, MII_DBG_GREENCFG2); 897 val &= ~DBG_GREENCFG2_GATE_DFSE_EN; 898 alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, val); 899 /* RTL8139C, 120m issue. */ 900 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_NLP78, 901 ANEG_NLP78_120M_DEFAULT); 902 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_S3DIG10, 903 ANEG_S3DIG10_DEFAULT); 904 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0) { 905 /* Turn off half amplitude. */ 906 val = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3); 907 val |= EXT_CLDCTL3_BP_CABLE1TH_DET_GT; 908 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3, val); 909 /* Turn off Green feature. */ 910 val = alc_miidbg_readreg(sc, MII_DBG_GREENCFG2); 911 val |= DBG_GREENCFG2_BP_GREEN; 912 alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, val); 913 /* Turn off half bias. */ 914 val = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5); 915 val |= EXT_CLDCTL5_BP_VD_HLFBIAS; 916 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5, val); 917 } 918 } 919 920 void 921 alc_phy_down(struct alc_softc *sc) 922 { 923 uint32_t gphy; 924 925 switch (sc->sc_product) { 926 case PCI_PRODUCT_ATTANSIC_AR8161: 927 case PCI_PRODUCT_ATTANSIC_E2200: 928 case PCI_PRODUCT_ATTANSIC_E2400: 929 case PCI_PRODUCT_ATTANSIC_E2500: 930 case PCI_PRODUCT_ATTANSIC_AR8162: 931 case PCI_PRODUCT_ATTANSIC_AR8171: 932 case PCI_PRODUCT_ATTANSIC_AR8172: 933 gphy = CSR_READ_4(sc, ALC_GPHY_CFG); 934 gphy &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | 935 GPHY_CFG_100AB_ENB | GPHY_CFG_PHY_PLL_ON); 936 gphy |= GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | 937 GPHY_CFG_SEL_ANA_RESET; 938 gphy |= GPHY_CFG_PHY_IDDQ | GPHY_CFG_PWDOWN_HW; 939 CSR_WRITE_4(sc, ALC_GPHY_CFG, gphy); 940 break; 941 case PCI_PRODUCT_ATTANSIC_L1D: 942 case PCI_PRODUCT_ATTANSIC_L1D_1: 943 case PCI_PRODUCT_ATTANSIC_L2C_1: 944 case PCI_PRODUCT_ATTANSIC_L2C_2: 945 /* 946 * GPHY power down caused more problems on AR8151 v2.0. 947 * When driver is reloaded after GPHY power down, 948 * accesses to PHY/MAC registers hung the system. Only 949 * cold boot recovered from it. I'm not sure whether 950 * AR8151 v1.0 also requires this one though. I don't 951 * have AR8151 v1.0 controller in hand. 952 * The only option left is to isolate the PHY and 953 * initiates power down the PHY which in turn saves 954 * more power when driver is unloaded. 955 */ 956 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 957 MII_BMCR, BMCR_ISO | BMCR_PDOWN); 958 break; 959 default: 960 /* Force PHY down. */ 961 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | 962 GPHY_CFG_SEL_ANA_RESET | GPHY_CFG_PHY_IDDQ | 963 GPHY_CFG_PWDOWN_HW); 964 DELAY(1000); 965 break; 966 } 967 } 968 969 void 970 alc_aspm(struct alc_softc *sc, int init, uint64_t media) 971 { 972 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 973 alc_aspm_816x(sc, init); 974 else 975 alc_aspm_813x(sc, media); 976 } 977 978 void 979 alc_aspm_813x(struct alc_softc *sc, uint64_t media) 980 { 981 uint32_t pmcfg; 982 uint16_t linkcfg; 983 984 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 985 if ((sc->alc_flags & (ALC_FLAG_APS | ALC_FLAG_PCIE)) == 986 (ALC_FLAG_APS | ALC_FLAG_PCIE)) 987 linkcfg = CSR_READ_2(sc, sc->alc_expcap + PCI_PCIE_LCSR); 988 else 989 linkcfg = 0; 990 pmcfg &= ~PM_CFG_SERDES_PD_EX_L1; 991 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_LCKDET_TIMER_MASK); 992 pmcfg |= PM_CFG_MAC_ASPM_CHK; 993 pmcfg |= (PM_CFG_LCKDET_TIMER_DEFAULT << PM_CFG_LCKDET_TIMER_SHIFT); 994 pmcfg &= ~(PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 995 996 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 997 /* Disable extended sync except AR8152 B v1.0 */ 998 linkcfg &= ~0x80; 999 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1 && 1000 sc->alc_rev == ATHEROS_AR8152_B_V10) 1001 linkcfg |= 0x80; 1002 CSR_WRITE_2(sc, sc->alc_expcap + PCI_PCIE_LCSR, linkcfg); 1003 pmcfg &= ~(PM_CFG_EN_BUFS_RX_L0S | PM_CFG_SA_DLY_ENB | 1004 PM_CFG_HOTRST); 1005 pmcfg |= (PM_CFG_L1_ENTRY_TIMER_DEFAULT << 1006 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1007 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 1008 pmcfg |= (PM_CFG_PM_REQ_TIMER_DEFAULT << 1009 PM_CFG_PM_REQ_TIMER_SHIFT); 1010 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_PCIE_RECV; 1011 } 1012 1013 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 1014 if ((sc->alc_flags & ALC_FLAG_L0S) != 0) 1015 pmcfg |= PM_CFG_ASPM_L0S_ENB; 1016 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 1017 pmcfg |= PM_CFG_ASPM_L1_ENB; 1018 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 1019 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1) 1020 pmcfg &= ~PM_CFG_ASPM_L0S_ENB; 1021 pmcfg &= ~(PM_CFG_SERDES_L1_ENB | 1022 PM_CFG_SERDES_PLL_L1_ENB | 1023 PM_CFG_SERDES_BUDS_RX_L1_ENB); 1024 pmcfg |= PM_CFG_CLK_SWH_L1; 1025 if (media == IFM_100_TX || media == IFM_1000_T) { 1026 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK; 1027 switch (sc->sc_product) { 1028 case PCI_PRODUCT_ATTANSIC_L2C_1: 1029 pmcfg |= (7 << 1030 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1031 break; 1032 case PCI_PRODUCT_ATTANSIC_L1D_1: 1033 case PCI_PRODUCT_ATTANSIC_L2C_2: 1034 pmcfg |= (4 << 1035 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1036 break; 1037 default: 1038 pmcfg |= (15 << 1039 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1040 break; 1041 } 1042 } 1043 } else { 1044 pmcfg |= PM_CFG_SERDES_L1_ENB | 1045 PM_CFG_SERDES_PLL_L1_ENB | 1046 PM_CFG_SERDES_BUDS_RX_L1_ENB; 1047 pmcfg &= ~(PM_CFG_CLK_SWH_L1 | 1048 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 1049 } 1050 } else { 1051 pmcfg &= ~(PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_L1_ENB | 1052 PM_CFG_SERDES_PLL_L1_ENB); 1053 pmcfg |= PM_CFG_CLK_SWH_L1; 1054 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 1055 pmcfg |= PM_CFG_ASPM_L1_ENB; 1056 } 1057 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 1058 } 1059 1060 void 1061 alc_aspm_816x(struct alc_softc *sc, int init) 1062 { 1063 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1064 uint32_t pmcfg; 1065 1066 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 1067 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_816X_MASK; 1068 pmcfg |= PM_CFG_L1_ENTRY_TIMER_816X_DEFAULT; 1069 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 1070 pmcfg |= PM_CFG_PM_REQ_TIMER_816X_DEFAULT; 1071 pmcfg &= ~PM_CFG_LCKDET_TIMER_MASK; 1072 pmcfg |= PM_CFG_LCKDET_TIMER_DEFAULT; 1073 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_CLK_SWH_L1 | PM_CFG_PCIE_RECV; 1074 pmcfg &= ~(PM_CFG_RX_L1_AFTER_L0S | PM_CFG_TX_L1_AFTER_L0S | 1075 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB | 1076 PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB | 1077 PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SA_DLY_ENB | 1078 PM_CFG_MAC_ASPM_CHK | PM_CFG_HOTRST); 1079 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 1080 (sc->alc_rev & 0x01) != 0) 1081 pmcfg |= PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB; 1082 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 1083 /* Link up, enable both L0s, L1s. */ 1084 pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 1085 PM_CFG_MAC_ASPM_CHK; 1086 } else { 1087 if (init != 0) 1088 pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 1089 PM_CFG_MAC_ASPM_CHK; 1090 else if ((ifp->if_flags & IFF_RUNNING) != 0) 1091 pmcfg |= PM_CFG_ASPM_L1_ENB | PM_CFG_MAC_ASPM_CHK; 1092 } 1093 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 1094 } 1095 1096 void 1097 alc_init_pcie(struct alc_softc *sc, int base) 1098 { 1099 const char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/L1" }; 1100 uint32_t cap, ctl, val; 1101 int state; 1102 1103 /* Clear data link and flow-control protocol error. */ 1104 val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV); 1105 val &= ~(PEX_UNC_ERR_SEV_DLP | PEX_UNC_ERR_SEV_FCP); 1106 CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val); 1107 1108 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 1109 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 1110 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 1111 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, 1112 CSR_READ_4(sc, ALC_PCIE_PHYMISC) | 1113 PCIE_PHYMISC_FORCE_RCV_DET); 1114 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1 && 1115 sc->alc_rev == ATHEROS_AR8152_B_V10) { 1116 val = CSR_READ_4(sc, ALC_PCIE_PHYMISC2); 1117 val &= ~(PCIE_PHYMISC2_SERDES_CDR_MASK | 1118 PCIE_PHYMISC2_SERDES_TH_MASK); 1119 val |= 3 << PCIE_PHYMISC2_SERDES_CDR_SHIFT; 1120 val |= 3 << PCIE_PHYMISC2_SERDES_TH_SHIFT; 1121 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC2, val); 1122 } 1123 /* Disable ASPM L0S and L1. */ 1124 cap = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 1125 base + PCI_PCIE_LCAP) >> 16; 1126 if ((cap & 0x00000c00) != 0) { 1127 ctl = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 1128 base + PCI_PCIE_LCSR) >> 16; 1129 if ((ctl & 0x08) != 0) 1130 sc->alc_rcb = DMA_CFG_RCB_128; 1131 if (alcdebug) 1132 printf("%s: RCB %u bytes\n", 1133 sc->sc_dev.dv_xname, 1134 sc->alc_rcb == DMA_CFG_RCB_64 ? 64 : 128); 1135 state = ctl & 0x03; 1136 if (state & 0x01) 1137 sc->alc_flags |= ALC_FLAG_L0S; 1138 if (state & 0x02) 1139 sc->alc_flags |= ALC_FLAG_L1S; 1140 if (alcdebug) 1141 printf("%s: ASPM %s %s\n", 1142 sc->sc_dev.dv_xname, 1143 aspm_state[state], 1144 state == 0 ? "disabled" : "enabled"); 1145 alc_disable_l0s_l1(sc); 1146 } 1147 } else { 1148 val = CSR_READ_4(sc, ALC_PDLL_TRNS1); 1149 val &= ~PDLL_TRNS1_D3PLLOFF_ENB; 1150 CSR_WRITE_4(sc, ALC_PDLL_TRNS1, val); 1151 val = CSR_READ_4(sc, ALC_MASTER_CFG); 1152 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 1153 (sc->alc_rev & 0x01) != 0) { 1154 if ((val & MASTER_WAKEN_25M) == 0 || 1155 (val & MASTER_CLK_SEL_DIS) == 0) { 1156 val |= MASTER_WAKEN_25M | MASTER_CLK_SEL_DIS; 1157 CSR_WRITE_4(sc, ALC_MASTER_CFG, val); 1158 } 1159 } else { 1160 if ((val & MASTER_WAKEN_25M) == 0 || 1161 (val & MASTER_CLK_SEL_DIS) != 0) { 1162 val |= MASTER_WAKEN_25M; 1163 val &= ~MASTER_CLK_SEL_DIS; 1164 CSR_WRITE_4(sc, ALC_MASTER_CFG, val); 1165 } 1166 } 1167 } 1168 } 1169 1170 void 1171 alc_config_msi(struct alc_softc *sc) 1172 { 1173 uint32_t ctl, mod; 1174 1175 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 1176 /* 1177 * It seems interrupt moderation is controlled by 1178 * ALC_MSI_RETRANS_TIMER register if MSI/MSIX is active. 1179 * Driver uses RX interrupt moderation parameter to 1180 * program ALC_MSI_RETRANS_TIMER register. 1181 */ 1182 ctl = CSR_READ_4(sc, ALC_MSI_RETRANS_TIMER); 1183 ctl &= ~MSI_RETRANS_TIMER_MASK; 1184 ctl &= ~MSI_RETRANS_MASK_SEL_LINE; 1185 mod = ALC_USECS(sc->alc_int_rx_mod); 1186 if (mod == 0) 1187 mod = 1; 1188 ctl |= mod; 1189 if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1190 CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, ctl | 1191 MSI_RETRANS_MASK_SEL_LINE); 1192 else 1193 CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, 0); 1194 } 1195 } 1196 1197 void 1198 alc_attach(struct device *parent, struct device *self, void *aux) 1199 { 1200 struct alc_softc *sc = (struct alc_softc *)self; 1201 struct pci_attach_args *pa = aux; 1202 pci_chipset_tag_t pc = pa->pa_pc; 1203 pci_intr_handle_t ih; 1204 const char *intrstr; 1205 struct ifnet *ifp; 1206 pcireg_t memtype; 1207 uint16_t burst; 1208 int base, error = 0; 1209 1210 /* Set PHY address. */ 1211 sc->alc_phyaddr = ALC_PHY_ADDR; 1212 1213 /* Get PCI and chip id/revision. */ 1214 sc->sc_product = PCI_PRODUCT(pa->pa_id); 1215 sc->alc_rev = PCI_REVISION(pa->pa_class); 1216 1217 /* 1218 * One odd thing is AR8132 uses the same PHY hardware(F1 1219 * gigabit PHY) of AR8131. So atphy(4) of AR8132 reports 1220 * the PHY supports 1000Mbps but that's not true. The PHY 1221 * used in AR8132 can't establish gigabit link even if it 1222 * shows the same PHY model/revision number of AR8131. 1223 */ 1224 switch (sc->sc_product) { 1225 case PCI_PRODUCT_ATTANSIC_E2200: 1226 case PCI_PRODUCT_ATTANSIC_E2400: 1227 case PCI_PRODUCT_ATTANSIC_E2500: 1228 sc->alc_flags |= ALC_FLAG_E2X00; 1229 /* FALLTHROUGH */ 1230 case PCI_PRODUCT_ATTANSIC_AR8161: 1231 if (AR816X_REV(sc->alc_rev) == 0) 1232 sc->alc_flags |= ALC_FLAG_LINK_WAR; 1233 /* FALLTHROUGH */ 1234 case PCI_PRODUCT_ATTANSIC_AR8171: 1235 sc->alc_flags |= ALC_FLAG_AR816X_FAMILY; 1236 break; 1237 case PCI_PRODUCT_ATTANSIC_AR8162: 1238 case PCI_PRODUCT_ATTANSIC_AR8172: 1239 sc->alc_flags |= ALC_FLAG_FASTETHER | ALC_FLAG_AR816X_FAMILY; 1240 break; 1241 case PCI_PRODUCT_ATTANSIC_L2C_1: 1242 case PCI_PRODUCT_ATTANSIC_L2C_2: 1243 sc->alc_flags |= ALC_FLAG_APS; 1244 /* FALLTHROUGH */ 1245 case PCI_PRODUCT_ATTANSIC_L2C: 1246 sc->alc_flags |= ALC_FLAG_FASTETHER; 1247 break; 1248 case PCI_PRODUCT_ATTANSIC_L1D: 1249 case PCI_PRODUCT_ATTANSIC_L1D_1: 1250 sc->alc_flags |= ALC_FLAG_APS; 1251 /* FALLTHROUGH */ 1252 default: 1253 break; 1254 } 1255 sc->alc_flags |= ALC_FLAG_JUMBO; 1256 1257 /* 1258 * Allocate IO memory 1259 */ 1260 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, ALC_PCIR_BAR); 1261 if (pci_mapreg_map(pa, ALC_PCIR_BAR, memtype, 0, &sc->sc_mem_bt, 1262 &sc->sc_mem_bh, NULL, &sc->sc_mem_size, 0)) { 1263 printf(": can't map mem space\n"); 1264 return; 1265 } 1266 1267 sc->alc_flags |= ALC_FLAG_MSI; 1268 if (pci_intr_map_msi(pa, &ih) != 0) { 1269 if (pci_intr_map(pa, &ih) != 0) { 1270 printf(": can't map interrupt\n"); 1271 goto fail; 1272 } 1273 sc->alc_flags &= ~ALC_FLAG_MSI; 1274 } 1275 1276 /* 1277 * Allocate IRQ 1278 */ 1279 intrstr = pci_intr_string(pc, ih); 1280 sc->sc_irq_handle = pci_intr_establish(pc, ih, IPL_NET, alc_intr, sc, 1281 sc->sc_dev.dv_xname); 1282 if (sc->sc_irq_handle == NULL) { 1283 printf(": could not establish interrupt"); 1284 if (intrstr != NULL) 1285 printf(" at %s", intrstr); 1286 printf("\n"); 1287 goto fail; 1288 } 1289 printf(": %s", intrstr); 1290 1291 alc_config_msi(sc); 1292 1293 sc->sc_dmat = pa->pa_dmat; 1294 sc->sc_pct = pa->pa_pc; 1295 sc->sc_pcitag = pa->pa_tag; 1296 1297 switch (sc->sc_product) { 1298 case PCI_PRODUCT_ATTANSIC_L1D: 1299 case PCI_PRODUCT_ATTANSIC_L1D_1: 1300 case PCI_PRODUCT_ATTANSIC_L2C_1: 1301 case PCI_PRODUCT_ATTANSIC_L2C_2: 1302 sc->alc_max_framelen = 6 * 1024; 1303 break; 1304 default: 1305 sc->alc_max_framelen = 9 * 1024; 1306 break; 1307 } 1308 1309 /* 1310 * It seems that AR813x/AR815x has silicon bug for SMB. In 1311 * addition, Atheros said that enabling SMB wouldn't improve 1312 * performance. However I think it's bad to access lots of 1313 * registers to extract MAC statistics. 1314 */ 1315 sc->alc_flags |= ALC_FLAG_SMB_BUG; 1316 /* 1317 * Don't use Tx CMB. It is known to have silicon bug. 1318 */ 1319 sc->alc_flags |= ALC_FLAG_CMB_BUG; 1320 sc->alc_chip_rev = CSR_READ_4(sc, ALC_MASTER_CFG) >> 1321 MASTER_CHIP_REV_SHIFT; 1322 if (alcdebug) { 1323 printf("%s: PCI device revision : 0x%04x\n", 1324 sc->sc_dev.dv_xname, sc->alc_rev); 1325 printf("%s: Chip id/revision : 0x%04x\n", 1326 sc->sc_dev.dv_xname, sc->alc_chip_rev); 1327 printf("%s: %u Tx FIFO, %u Rx FIFO\n", sc->sc_dev.dv_xname, 1328 CSR_READ_4(sc, ALC_SRAM_TX_FIFO_LEN) * 8, 1329 CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN) * 8); 1330 } 1331 1332 /* Initialize DMA parameters. */ 1333 sc->alc_dma_rd_burst = 0; 1334 sc->alc_dma_wr_burst = 0; 1335 sc->alc_rcb = DMA_CFG_RCB_64; 1336 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PCIEXPRESS, 1337 &base, NULL)) { 1338 sc->alc_flags |= ALC_FLAG_PCIE; 1339 sc->alc_expcap = base; 1340 burst = CSR_READ_2(sc, base + PCI_PCIE_DCSR); 1341 sc->alc_dma_rd_burst = (burst & 0x7000) >> 12; 1342 sc->alc_dma_wr_burst = (burst & 0x00e0) >> 5; 1343 if (alcdebug) { 1344 printf("%s: Read request size : %u bytes.\n", 1345 sc->sc_dev.dv_xname, 1346 alc_dma_burst[sc->alc_dma_rd_burst]); 1347 printf("%s: TLP payload size : %u bytes.\n", 1348 sc->sc_dev.dv_xname, 1349 alc_dma_burst[sc->alc_dma_wr_burst]); 1350 } 1351 if (alc_dma_burst[sc->alc_dma_rd_burst] > 1024) 1352 sc->alc_dma_rd_burst = 3; 1353 if (alc_dma_burst[sc->alc_dma_wr_burst] > 1024) 1354 sc->alc_dma_wr_burst = 3; 1355 /* 1356 * Force maximum payload size to 128 bytes for 1357 * E2200/E2400/E2500/AR8162/AR8171/AR8172. 1358 * Otherwise it triggers DMA write error. 1359 */ 1360 if ((sc->alc_flags & 1361 (ALC_FLAG_E2X00 | ALC_FLAG_AR816X_FAMILY)) != 0) 1362 sc->alc_dma_wr_burst = 0; 1363 alc_init_pcie(sc, base); 1364 } 1365 1366 /* Reset PHY. */ 1367 alc_phy_reset(sc); 1368 1369 /* Reset the ethernet controller. */ 1370 alc_stop_mac(sc); 1371 alc_reset(sc); 1372 1373 error = alc_dma_alloc(sc); 1374 if (error) 1375 goto fail; 1376 1377 /* Load station address. */ 1378 alc_get_macaddr(sc); 1379 1380 ifp = &sc->sc_arpcom.ac_if; 1381 ifp->if_softc = sc; 1382 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1383 ifp->if_ioctl = alc_ioctl; 1384 ifp->if_start = alc_start; 1385 ifp->if_watchdog = alc_watchdog; 1386 ifq_init_maxlen(&ifp->if_snd, ALC_TX_RING_CNT - 1); 1387 bcopy(sc->alc_eaddr, sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN); 1388 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 1389 1390 ifp->if_capabilities = IFCAP_VLAN_MTU; 1391 1392 #ifdef ALC_CHECKSUM 1393 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 1394 IFCAP_CSUM_UDPv4; 1395 #endif 1396 1397 #if NVLAN > 0 1398 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 1399 #endif 1400 1401 printf(", address %s\n", ether_sprintf(sc->sc_arpcom.ac_enaddr)); 1402 1403 /* Set up MII bus. */ 1404 sc->sc_miibus.mii_ifp = ifp; 1405 sc->sc_miibus.mii_readreg = alc_miibus_readreg; 1406 sc->sc_miibus.mii_writereg = alc_miibus_writereg; 1407 sc->sc_miibus.mii_statchg = alc_miibus_statchg; 1408 1409 ifmedia_init(&sc->sc_miibus.mii_media, 0, alc_mediachange, 1410 alc_mediastatus); 1411 mii_attach(self, &sc->sc_miibus, 0xffffffff, MII_PHY_ANY, 1412 MII_OFFSET_ANY, MIIF_DOPAUSE); 1413 1414 if (LIST_FIRST(&sc->sc_miibus.mii_phys) == NULL) { 1415 printf("%s: no PHY found!\n", sc->sc_dev.dv_xname); 1416 ifmedia_add(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL, 1417 0, NULL); 1418 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL); 1419 } else 1420 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_AUTO); 1421 1422 if_attach(ifp); 1423 ether_ifattach(ifp); 1424 1425 timeout_set(&sc->alc_tick_ch, alc_tick, sc); 1426 1427 return; 1428 fail: 1429 alc_dma_free(sc); 1430 if (sc->sc_irq_handle != NULL) 1431 pci_intr_disestablish(pc, sc->sc_irq_handle); 1432 if (sc->sc_mem_size) 1433 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 1434 } 1435 1436 int 1437 alc_detach(struct device *self, int flags) 1438 { 1439 struct alc_softc *sc = (struct alc_softc *)self; 1440 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1441 int s; 1442 1443 s = splnet(); 1444 alc_stop(sc); 1445 splx(s); 1446 1447 mii_detach(&sc->sc_miibus, MII_PHY_ANY, MII_OFFSET_ANY); 1448 1449 /* Delete all remaining media. */ 1450 ifmedia_delete_instance(&sc->sc_miibus.mii_media, IFM_INST_ANY); 1451 1452 ether_ifdetach(ifp); 1453 if_detach(ifp); 1454 alc_dma_free(sc); 1455 1456 alc_phy_down(sc); 1457 if (sc->sc_irq_handle != NULL) { 1458 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 1459 sc->sc_irq_handle = NULL; 1460 } 1461 1462 return (0); 1463 } 1464 1465 int 1466 alc_activate(struct device *self, int act) 1467 { 1468 struct alc_softc *sc = (struct alc_softc *)self; 1469 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1470 int rv = 0; 1471 1472 switch (act) { 1473 case DVACT_SUSPEND: 1474 if (ifp->if_flags & IFF_RUNNING) 1475 alc_stop(sc); 1476 rv = config_activate_children(self, act); 1477 break; 1478 case DVACT_RESUME: 1479 if (ifp->if_flags & IFF_UP) 1480 alc_init(ifp); 1481 break; 1482 default: 1483 rv = config_activate_children(self, act); 1484 break; 1485 } 1486 return (rv); 1487 } 1488 1489 int 1490 alc_dma_alloc(struct alc_softc *sc) 1491 { 1492 struct alc_txdesc *txd; 1493 struct alc_rxdesc *rxd; 1494 int nsegs, error, i; 1495 1496 /* 1497 * Create DMA stuffs for TX ring 1498 */ 1499 error = bus_dmamap_create(sc->sc_dmat, ALC_TX_RING_SZ, 1, 1500 ALC_TX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->alc_cdata.alc_tx_ring_map); 1501 if (error) 1502 return (ENOBUFS); 1503 1504 /* Allocate DMA'able memory for TX ring */ 1505 error = bus_dmamem_alloc(sc->sc_dmat, ALC_TX_RING_SZ, 1506 ETHER_ALIGN, 0, &sc->alc_rdata.alc_tx_ring_seg, 1, 1507 &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 1508 if (error) { 1509 printf("%s: could not allocate DMA'able memory for Tx ring.\n", 1510 sc->sc_dev.dv_xname); 1511 return (error); 1512 } 1513 1514 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_tx_ring_seg, 1515 nsegs, ALC_TX_RING_SZ, (caddr_t *)&sc->alc_rdata.alc_tx_ring, 1516 BUS_DMA_NOWAIT); 1517 if (error) 1518 return (ENOBUFS); 1519 1520 /* Load the DMA map for Tx ring. */ 1521 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 1522 sc->alc_rdata.alc_tx_ring, ALC_TX_RING_SZ, NULL, BUS_DMA_WAITOK); 1523 if (error) { 1524 printf("%s: could not load DMA'able memory for Tx ring.\n", 1525 sc->sc_dev.dv_xname); 1526 bus_dmamem_free(sc->sc_dmat, 1527 (bus_dma_segment_t *)&sc->alc_rdata.alc_tx_ring, 1); 1528 return (error); 1529 } 1530 1531 sc->alc_rdata.alc_tx_ring_paddr = 1532 sc->alc_cdata.alc_tx_ring_map->dm_segs[0].ds_addr; 1533 1534 /* 1535 * Create DMA stuffs for RX ring 1536 */ 1537 error = bus_dmamap_create(sc->sc_dmat, ALC_RX_RING_SZ, 1, 1538 ALC_RX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->alc_cdata.alc_rx_ring_map); 1539 if (error) 1540 return (ENOBUFS); 1541 1542 /* Allocate DMA'able memory for RX ring */ 1543 error = bus_dmamem_alloc(sc->sc_dmat, ALC_RX_RING_SZ, 1544 ETHER_ALIGN, 0, &sc->alc_rdata.alc_rx_ring_seg, 1, 1545 &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 1546 if (error) { 1547 printf("%s: could not allocate DMA'able memory for Rx ring.\n", 1548 sc->sc_dev.dv_xname); 1549 return (error); 1550 } 1551 1552 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_rx_ring_seg, 1553 nsegs, ALC_RX_RING_SZ, (caddr_t *)&sc->alc_rdata.alc_rx_ring, 1554 BUS_DMA_NOWAIT); 1555 if (error) 1556 return (ENOBUFS); 1557 1558 /* Load the DMA map for Rx ring. */ 1559 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 1560 sc->alc_rdata.alc_rx_ring, ALC_RX_RING_SZ, NULL, BUS_DMA_WAITOK); 1561 if (error) { 1562 printf("%s: could not load DMA'able memory for Rx ring.\n", 1563 sc->sc_dev.dv_xname); 1564 bus_dmamem_free(sc->sc_dmat, 1565 (bus_dma_segment_t *)sc->alc_rdata.alc_rx_ring, 1); 1566 return (error); 1567 } 1568 1569 sc->alc_rdata.alc_rx_ring_paddr = 1570 sc->alc_cdata.alc_rx_ring_map->dm_segs[0].ds_addr; 1571 1572 /* 1573 * Create DMA stuffs for RX return ring 1574 */ 1575 error = bus_dmamap_create(sc->sc_dmat, ALC_RR_RING_SZ, 1, 1576 ALC_RR_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->alc_cdata.alc_rr_ring_map); 1577 if (error) 1578 return (ENOBUFS); 1579 1580 /* Allocate DMA'able memory for RX return ring */ 1581 error = bus_dmamem_alloc(sc->sc_dmat, ALC_RR_RING_SZ, 1582 ETHER_ALIGN, 0, &sc->alc_rdata.alc_rr_ring_seg, 1, 1583 &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 1584 if (error) { 1585 printf("%s: could not allocate DMA'able memory for Rx " 1586 "return ring.\n", sc->sc_dev.dv_xname); 1587 return (error); 1588 } 1589 1590 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_rr_ring_seg, 1591 nsegs, ALC_RR_RING_SZ, (caddr_t *)&sc->alc_rdata.alc_rr_ring, 1592 BUS_DMA_NOWAIT); 1593 if (error) 1594 return (ENOBUFS); 1595 1596 /* Load the DMA map for Rx return ring. */ 1597 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 1598 sc->alc_rdata.alc_rr_ring, ALC_RR_RING_SZ, NULL, BUS_DMA_WAITOK); 1599 if (error) { 1600 printf("%s: could not load DMA'able memory for Rx return ring." 1601 "\n", sc->sc_dev.dv_xname); 1602 bus_dmamem_free(sc->sc_dmat, 1603 (bus_dma_segment_t *)&sc->alc_rdata.alc_rr_ring, 1); 1604 return (error); 1605 } 1606 1607 sc->alc_rdata.alc_rr_ring_paddr = 1608 sc->alc_cdata.alc_rr_ring_map->dm_segs[0].ds_addr; 1609 1610 /* 1611 * Create DMA stuffs for CMB block 1612 */ 1613 error = bus_dmamap_create(sc->sc_dmat, ALC_CMB_SZ, 1, 1614 ALC_CMB_SZ, 0, BUS_DMA_NOWAIT, 1615 &sc->alc_cdata.alc_cmb_map); 1616 if (error) 1617 return (ENOBUFS); 1618 1619 /* Allocate DMA'able memory for CMB block */ 1620 error = bus_dmamem_alloc(sc->sc_dmat, ALC_CMB_SZ, 1621 ETHER_ALIGN, 0, &sc->alc_rdata.alc_cmb_seg, 1, 1622 &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 1623 if (error) { 1624 printf("%s: could not allocate DMA'able memory for " 1625 "CMB block\n", sc->sc_dev.dv_xname); 1626 return (error); 1627 } 1628 1629 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_cmb_seg, 1630 nsegs, ALC_CMB_SZ, (caddr_t *)&sc->alc_rdata.alc_cmb, 1631 BUS_DMA_NOWAIT); 1632 if (error) 1633 return (ENOBUFS); 1634 1635 /* Load the DMA map for CMB block. */ 1636 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 1637 sc->alc_rdata.alc_cmb, ALC_CMB_SZ, NULL, 1638 BUS_DMA_WAITOK); 1639 if (error) { 1640 printf("%s: could not load DMA'able memory for CMB block\n", 1641 sc->sc_dev.dv_xname); 1642 bus_dmamem_free(sc->sc_dmat, 1643 (bus_dma_segment_t *)&sc->alc_rdata.alc_cmb, 1); 1644 return (error); 1645 } 1646 1647 sc->alc_rdata.alc_cmb_paddr = 1648 sc->alc_cdata.alc_cmb_map->dm_segs[0].ds_addr; 1649 1650 /* 1651 * Create DMA stuffs for SMB block 1652 */ 1653 error = bus_dmamap_create(sc->sc_dmat, ALC_SMB_SZ, 1, 1654 ALC_SMB_SZ, 0, BUS_DMA_NOWAIT, 1655 &sc->alc_cdata.alc_smb_map); 1656 if (error) 1657 return (ENOBUFS); 1658 1659 /* Allocate DMA'able memory for SMB block */ 1660 error = bus_dmamem_alloc(sc->sc_dmat, ALC_SMB_SZ, 1661 ETHER_ALIGN, 0, &sc->alc_rdata.alc_smb_seg, 1, 1662 &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 1663 if (error) { 1664 printf("%s: could not allocate DMA'able memory for " 1665 "SMB block\n", sc->sc_dev.dv_xname); 1666 return (error); 1667 } 1668 1669 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_smb_seg, 1670 nsegs, ALC_SMB_SZ, (caddr_t *)&sc->alc_rdata.alc_smb, 1671 BUS_DMA_NOWAIT); 1672 if (error) 1673 return (ENOBUFS); 1674 1675 /* Load the DMA map for SMB block */ 1676 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 1677 sc->alc_rdata.alc_smb, ALC_SMB_SZ, NULL, 1678 BUS_DMA_WAITOK); 1679 if (error) { 1680 printf("%s: could not load DMA'able memory for SMB block\n", 1681 sc->sc_dev.dv_xname); 1682 bus_dmamem_free(sc->sc_dmat, 1683 (bus_dma_segment_t *)&sc->alc_rdata.alc_smb, 1); 1684 return (error); 1685 } 1686 1687 sc->alc_rdata.alc_smb_paddr = 1688 sc->alc_cdata.alc_smb_map->dm_segs[0].ds_addr; 1689 1690 1691 /* Create DMA maps for Tx buffers. */ 1692 for (i = 0; i < ALC_TX_RING_CNT; i++) { 1693 txd = &sc->alc_cdata.alc_txdesc[i]; 1694 txd->tx_m = NULL; 1695 txd->tx_dmamap = NULL; 1696 error = bus_dmamap_create(sc->sc_dmat, ALC_TSO_MAXSIZE, 1697 ALC_MAXTXSEGS, ALC_TSO_MAXSEGSIZE, 0, BUS_DMA_NOWAIT, 1698 &txd->tx_dmamap); 1699 if (error) { 1700 printf("%s: could not create Tx dmamap.\n", 1701 sc->sc_dev.dv_xname); 1702 return (error); 1703 } 1704 } 1705 1706 /* Create DMA maps for Rx buffers. */ 1707 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 1708 BUS_DMA_NOWAIT, &sc->alc_cdata.alc_rx_sparemap); 1709 if (error) { 1710 printf("%s: could not create spare Rx dmamap.\n", 1711 sc->sc_dev.dv_xname); 1712 return (error); 1713 } 1714 1715 for (i = 0; i < ALC_RX_RING_CNT; i++) { 1716 rxd = &sc->alc_cdata.alc_rxdesc[i]; 1717 rxd->rx_m = NULL; 1718 rxd->rx_dmamap = NULL; 1719 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1720 MCLBYTES, 0, BUS_DMA_NOWAIT, &rxd->rx_dmamap); 1721 if (error) { 1722 printf("%s: could not create Rx dmamap.\n", 1723 sc->sc_dev.dv_xname); 1724 return (error); 1725 } 1726 } 1727 1728 return (0); 1729 } 1730 1731 void 1732 alc_dma_free(struct alc_softc *sc) 1733 { 1734 struct alc_txdesc *txd; 1735 struct alc_rxdesc *rxd; 1736 int i; 1737 1738 /* Tx buffers */ 1739 for (i = 0; i < ALC_TX_RING_CNT; i++) { 1740 txd = &sc->alc_cdata.alc_txdesc[i]; 1741 if (txd->tx_dmamap != NULL) { 1742 bus_dmamap_destroy(sc->sc_dmat, txd->tx_dmamap); 1743 txd->tx_dmamap = NULL; 1744 } 1745 } 1746 /* Rx buffers */ 1747 for (i = 0; i < ALC_RX_RING_CNT; i++) { 1748 rxd = &sc->alc_cdata.alc_rxdesc[i]; 1749 if (rxd->rx_dmamap != NULL) { 1750 bus_dmamap_destroy(sc->sc_dmat, rxd->rx_dmamap); 1751 rxd->rx_dmamap = NULL; 1752 } 1753 } 1754 if (sc->alc_cdata.alc_rx_sparemap != NULL) { 1755 bus_dmamap_destroy(sc->sc_dmat, sc->alc_cdata.alc_rx_sparemap); 1756 sc->alc_cdata.alc_rx_sparemap = NULL; 1757 } 1758 1759 /* Tx ring. */ 1760 if (sc->alc_cdata.alc_tx_ring_map != NULL) 1761 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map); 1762 if (sc->alc_cdata.alc_tx_ring_map != NULL && 1763 sc->alc_rdata.alc_tx_ring != NULL) 1764 bus_dmamem_free(sc->sc_dmat, 1765 (bus_dma_segment_t *)sc->alc_rdata.alc_tx_ring, 1); 1766 sc->alc_rdata.alc_tx_ring = NULL; 1767 sc->alc_cdata.alc_tx_ring_map = NULL; 1768 1769 /* Rx ring. */ 1770 if (sc->alc_cdata.alc_rx_ring_map != NULL) 1771 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map); 1772 if (sc->alc_cdata.alc_rx_ring_map != NULL && 1773 sc->alc_rdata.alc_rx_ring != NULL) 1774 bus_dmamem_free(sc->sc_dmat, 1775 (bus_dma_segment_t *)sc->alc_rdata.alc_rx_ring, 1); 1776 sc->alc_rdata.alc_rx_ring = NULL; 1777 sc->alc_cdata.alc_rx_ring_map = NULL; 1778 1779 /* Rx return ring. */ 1780 if (sc->alc_cdata.alc_rr_ring_map != NULL) 1781 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map); 1782 if (sc->alc_cdata.alc_rr_ring_map != NULL && 1783 sc->alc_rdata.alc_rr_ring != NULL) 1784 bus_dmamem_free(sc->sc_dmat, 1785 (bus_dma_segment_t *)sc->alc_rdata.alc_rr_ring, 1); 1786 sc->alc_rdata.alc_rr_ring = NULL; 1787 sc->alc_cdata.alc_rr_ring_map = NULL; 1788 1789 /* CMB block */ 1790 if (sc->alc_cdata.alc_cmb_map != NULL) 1791 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_cmb_map); 1792 if (sc->alc_cdata.alc_cmb_map != NULL && 1793 sc->alc_rdata.alc_cmb != NULL) 1794 bus_dmamem_free(sc->sc_dmat, 1795 (bus_dma_segment_t *)sc->alc_rdata.alc_cmb, 1); 1796 sc->alc_rdata.alc_cmb = NULL; 1797 sc->alc_cdata.alc_cmb_map = NULL; 1798 1799 /* SMB block */ 1800 if (sc->alc_cdata.alc_smb_map != NULL) 1801 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_smb_map); 1802 if (sc->alc_cdata.alc_smb_map != NULL && 1803 sc->alc_rdata.alc_smb != NULL) 1804 bus_dmamem_free(sc->sc_dmat, 1805 (bus_dma_segment_t *)sc->alc_rdata.alc_smb, 1); 1806 sc->alc_rdata.alc_smb = NULL; 1807 sc->alc_cdata.alc_smb_map = NULL; 1808 } 1809 1810 int 1811 alc_encap(struct alc_softc *sc, struct mbuf *m) 1812 { 1813 struct alc_txdesc *txd, *txd_last; 1814 struct tx_desc *desc; 1815 bus_dmamap_t map; 1816 uint32_t cflags, poff, vtag; 1817 int error, idx, prod; 1818 1819 cflags = vtag = 0; 1820 poff = 0; 1821 1822 prod = sc->alc_cdata.alc_tx_prod; 1823 txd = &sc->alc_cdata.alc_txdesc[prod]; 1824 txd_last = txd; 1825 map = txd->tx_dmamap; 1826 1827 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, BUS_DMA_NOWAIT); 1828 if (error != 0 && error != EFBIG) 1829 goto drop; 1830 if (error != 0) { 1831 if (m_defrag(m, M_DONTWAIT)) { 1832 error = ENOBUFS; 1833 goto drop; 1834 } 1835 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1836 BUS_DMA_NOWAIT); 1837 if (error != 0) 1838 goto drop; 1839 } 1840 1841 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1842 BUS_DMASYNC_PREWRITE); 1843 1844 desc = NULL; 1845 idx = 0; 1846 #if NVLAN > 0 1847 /* Configure VLAN hardware tag insertion. */ 1848 if (m->m_flags & M_VLANTAG) { 1849 vtag = htons(m->m_pkthdr.ether_vtag); 1850 vtag = (vtag << TD_VLAN_SHIFT) & TD_VLAN_MASK; 1851 cflags |= TD_INS_VLAN_TAG; 1852 } 1853 #endif 1854 /* Configure Tx checksum offload. */ 1855 if ((m->m_pkthdr.csum_flags & ALC_CSUM_FEATURES) != 0) { 1856 cflags |= TD_CUSTOM_CSUM; 1857 /* Set checksum start offset. */ 1858 cflags |= ((poff >> 1) << TD_PLOAD_OFFSET_SHIFT) & 1859 TD_PLOAD_OFFSET_MASK; 1860 } 1861 1862 for (; idx < map->dm_nsegs; idx++) { 1863 desc = &sc->alc_rdata.alc_tx_ring[prod]; 1864 desc->len = 1865 htole32(TX_BYTES(map->dm_segs[idx].ds_len) | vtag); 1866 desc->flags = htole32(cflags); 1867 desc->addr = htole64(map->dm_segs[idx].ds_addr); 1868 sc->alc_cdata.alc_tx_cnt++; 1869 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 1870 } 1871 1872 /* Update producer index. */ 1873 sc->alc_cdata.alc_tx_prod = prod; 1874 1875 /* Finally set EOP on the last descriptor. */ 1876 prod = (prod + ALC_TX_RING_CNT - 1) % ALC_TX_RING_CNT; 1877 desc = &sc->alc_rdata.alc_tx_ring[prod]; 1878 desc->flags |= htole32(TD_EOP); 1879 1880 /* Swap dmamap of the first and the last. */ 1881 txd = &sc->alc_cdata.alc_txdesc[prod]; 1882 map = txd_last->tx_dmamap; 1883 txd_last->tx_dmamap = txd->tx_dmamap; 1884 txd->tx_dmamap = map; 1885 txd->tx_m = m; 1886 1887 return (0); 1888 1889 drop: 1890 m_freem(m); 1891 return (error); 1892 } 1893 1894 void 1895 alc_start(struct ifnet *ifp) 1896 { 1897 struct alc_softc *sc = ifp->if_softc; 1898 struct mbuf *m; 1899 int enq = 0; 1900 1901 /* Reclaim transmitted frames. */ 1902 if (sc->alc_cdata.alc_tx_cnt >= ALC_TX_DESC_HIWAT) 1903 alc_txeof(sc); 1904 1905 if (!(ifp->if_flags & IFF_RUNNING) || ifq_is_oactive(&ifp->if_snd)) 1906 return; 1907 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) 1908 return; 1909 if (ifq_empty(&ifp->if_snd)) 1910 return; 1911 1912 for (;;) { 1913 if (sc->alc_cdata.alc_tx_cnt + ALC_MAXTXSEGS >= 1914 ALC_TX_RING_CNT - 3) { 1915 ifq_set_oactive(&ifp->if_snd); 1916 break; 1917 } 1918 1919 m = ifq_dequeue(&ifp->if_snd); 1920 if (m == NULL) 1921 break; 1922 1923 if (alc_encap(sc, m) != 0) { 1924 ifp->if_oerrors++; 1925 continue; 1926 } 1927 enq++; 1928 1929 #if NBPFILTER > 0 1930 /* 1931 * If there's a BPF listener, bounce a copy of this frame 1932 * to him. 1933 */ 1934 if (ifp->if_bpf != NULL) 1935 bpf_mtap_ether(ifp->if_bpf, m, BPF_DIRECTION_OUT); 1936 #endif 1937 } 1938 1939 if (enq > 0) { 1940 /* Sync descriptors. */ 1941 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0, 1942 sc->alc_cdata.alc_tx_ring_map->dm_mapsize, 1943 BUS_DMASYNC_PREWRITE); 1944 /* Kick. Assume we're using normal Tx priority queue. */ 1945 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 1946 CSR_WRITE_2(sc, ALC_MBOX_TD_PRI0_PROD_IDX, 1947 (uint16_t)sc->alc_cdata.alc_tx_prod); 1948 else 1949 CSR_WRITE_4(sc, ALC_MBOX_TD_PROD_IDX, 1950 (sc->alc_cdata.alc_tx_prod << 1951 MBOX_TD_PROD_LO_IDX_SHIFT) & 1952 MBOX_TD_PROD_LO_IDX_MASK); 1953 /* Set a timeout in case the chip goes out to lunch. */ 1954 ifp->if_timer = ALC_TX_TIMEOUT; 1955 } 1956 } 1957 1958 void 1959 alc_watchdog(struct ifnet *ifp) 1960 { 1961 struct alc_softc *sc = ifp->if_softc; 1962 1963 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) { 1964 printf("%s: watchdog timeout (missed link)\n", 1965 sc->sc_dev.dv_xname); 1966 ifp->if_oerrors++; 1967 alc_init(ifp); 1968 return; 1969 } 1970 1971 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 1972 ifp->if_oerrors++; 1973 alc_init(ifp); 1974 alc_start(ifp); 1975 } 1976 1977 int 1978 alc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1979 { 1980 struct alc_softc *sc = ifp->if_softc; 1981 struct mii_data *mii = &sc->sc_miibus; 1982 struct ifreq *ifr = (struct ifreq *)data; 1983 int s, error = 0; 1984 1985 s = splnet(); 1986 1987 switch (cmd) { 1988 case SIOCSIFADDR: 1989 ifp->if_flags |= IFF_UP; 1990 if (!(ifp->if_flags & IFF_RUNNING)) 1991 alc_init(ifp); 1992 break; 1993 1994 case SIOCSIFFLAGS: 1995 if (ifp->if_flags & IFF_UP) { 1996 if (ifp->if_flags & IFF_RUNNING) 1997 error = ENETRESET; 1998 else 1999 alc_init(ifp); 2000 } else { 2001 if (ifp->if_flags & IFF_RUNNING) 2002 alc_stop(sc); 2003 } 2004 break; 2005 2006 case SIOCSIFMEDIA: 2007 case SIOCGIFMEDIA: 2008 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 2009 break; 2010 2011 default: 2012 error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data); 2013 break; 2014 } 2015 2016 if (error == ENETRESET) { 2017 if (ifp->if_flags & IFF_RUNNING) 2018 alc_iff(sc); 2019 error = 0; 2020 } 2021 2022 splx(s); 2023 return (error); 2024 } 2025 2026 void 2027 alc_mac_config(struct alc_softc *sc) 2028 { 2029 struct mii_data *mii; 2030 uint32_t reg; 2031 2032 mii = &sc->sc_miibus; 2033 reg = CSR_READ_4(sc, ALC_MAC_CFG); 2034 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 2035 MAC_CFG_SPEED_MASK); 2036 if ((sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D || 2037 sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D_1 || 2038 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_2 || 2039 sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 2040 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 2041 /* Reprogram MAC with resolved speed/duplex. */ 2042 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2043 case IFM_10_T: 2044 case IFM_100_TX: 2045 reg |= MAC_CFG_SPEED_10_100; 2046 break; 2047 case IFM_1000_T: 2048 reg |= MAC_CFG_SPEED_1000; 2049 break; 2050 } 2051 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 2052 reg |= MAC_CFG_FULL_DUPLEX; 2053 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 2054 reg |= MAC_CFG_TX_FC; 2055 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 2056 reg |= MAC_CFG_RX_FC; 2057 } 2058 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 2059 } 2060 2061 void 2062 alc_stats_clear(struct alc_softc *sc) 2063 { 2064 struct smb sb, *smb; 2065 uint32_t *reg; 2066 int i; 2067 2068 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2069 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 2070 sc->alc_cdata.alc_smb_map->dm_mapsize, 2071 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2072 smb = sc->alc_rdata.alc_smb; 2073 /* Update done, clear. */ 2074 smb->updated = 0; 2075 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 2076 sc->alc_cdata.alc_smb_map->dm_mapsize, 2077 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2078 } else { 2079 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 2080 reg++) { 2081 CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 2082 i += sizeof(uint32_t); 2083 } 2084 /* Read Tx statistics. */ 2085 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 2086 reg++) { 2087 CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 2088 i += sizeof(uint32_t); 2089 } 2090 } 2091 } 2092 2093 void 2094 alc_stats_update(struct alc_softc *sc) 2095 { 2096 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 2097 struct alc_hw_stats *stat; 2098 struct smb sb, *smb; 2099 uint32_t *reg; 2100 int i; 2101 2102 stat = &sc->alc_stats; 2103 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2104 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 2105 sc->alc_cdata.alc_smb_map->dm_mapsize, 2106 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2107 smb = sc->alc_rdata.alc_smb; 2108 if (smb->updated == 0) 2109 return; 2110 } else { 2111 smb = &sb; 2112 /* Read Rx statistics. */ 2113 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 2114 reg++) { 2115 *reg = CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 2116 i += sizeof(uint32_t); 2117 } 2118 /* Read Tx statistics. */ 2119 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 2120 reg++) { 2121 *reg = CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 2122 i += sizeof(uint32_t); 2123 } 2124 } 2125 2126 /* Rx stats. */ 2127 stat->rx_frames += smb->rx_frames; 2128 stat->rx_bcast_frames += smb->rx_bcast_frames; 2129 stat->rx_mcast_frames += smb->rx_mcast_frames; 2130 stat->rx_pause_frames += smb->rx_pause_frames; 2131 stat->rx_control_frames += smb->rx_control_frames; 2132 stat->rx_crcerrs += smb->rx_crcerrs; 2133 stat->rx_lenerrs += smb->rx_lenerrs; 2134 stat->rx_bytes += smb->rx_bytes; 2135 stat->rx_runts += smb->rx_runts; 2136 stat->rx_fragments += smb->rx_fragments; 2137 stat->rx_pkts_64 += smb->rx_pkts_64; 2138 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 2139 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 2140 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2141 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2142 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2143 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2144 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2145 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2146 stat->rx_rrs_errs += smb->rx_rrs_errs; 2147 stat->rx_alignerrs += smb->rx_alignerrs; 2148 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2149 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2150 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2151 2152 /* Tx stats. */ 2153 stat->tx_frames += smb->tx_frames; 2154 stat->tx_bcast_frames += smb->tx_bcast_frames; 2155 stat->tx_mcast_frames += smb->tx_mcast_frames; 2156 stat->tx_pause_frames += smb->tx_pause_frames; 2157 stat->tx_excess_defer += smb->tx_excess_defer; 2158 stat->tx_control_frames += smb->tx_control_frames; 2159 stat->tx_deferred += smb->tx_deferred; 2160 stat->tx_bytes += smb->tx_bytes; 2161 stat->tx_pkts_64 += smb->tx_pkts_64; 2162 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2163 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2164 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2165 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2166 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2167 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2168 stat->tx_single_colls += smb->tx_single_colls; 2169 stat->tx_multi_colls += smb->tx_multi_colls; 2170 stat->tx_late_colls += smb->tx_late_colls; 2171 stat->tx_excess_colls += smb->tx_excess_colls; 2172 stat->tx_underrun += smb->tx_underrun; 2173 stat->tx_desc_underrun += smb->tx_desc_underrun; 2174 stat->tx_lenerrs += smb->tx_lenerrs; 2175 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2176 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2177 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2178 2179 ifp->if_collisions += smb->tx_single_colls + 2180 smb->tx_multi_colls * 2 + smb->tx_late_colls + 2181 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT; 2182 2183 ifp->if_oerrors += smb->tx_late_colls + smb->tx_excess_colls + 2184 smb->tx_underrun + smb->tx_pkts_truncated; 2185 2186 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 2187 smb->rx_runts + smb->rx_pkts_truncated + 2188 smb->rx_fifo_oflows + smb->rx_rrs_errs + 2189 smb->rx_alignerrs; 2190 2191 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2192 /* Update done, clear. */ 2193 smb->updated = 0; 2194 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 2195 sc->alc_cdata.alc_smb_map->dm_mapsize, 2196 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2197 } 2198 } 2199 2200 int 2201 alc_intr(void *arg) 2202 { 2203 struct alc_softc *sc = arg; 2204 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 2205 uint32_t status; 2206 int claimed = 0; 2207 2208 status = CSR_READ_4(sc, ALC_INTR_STATUS); 2209 if ((status & ALC_INTRS) == 0) 2210 return (0); 2211 2212 /* Disable interrupts. */ 2213 CSR_WRITE_4(sc, ALC_INTR_STATUS, INTR_DIS_INT); 2214 2215 status = CSR_READ_4(sc, ALC_INTR_STATUS); 2216 if ((status & ALC_INTRS) == 0) 2217 goto back; 2218 2219 /* Acknowledge and disable interrupts. */ 2220 CSR_WRITE_4(sc, ALC_INTR_STATUS, status | INTR_DIS_INT); 2221 2222 if (ifp->if_flags & IFF_RUNNING) { 2223 int error = 0; 2224 2225 if (status & INTR_RX_PKT) { 2226 error = alc_rxintr(sc); 2227 if (error) { 2228 alc_init(ifp); 2229 return (0); 2230 } 2231 } 2232 if (status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | 2233 INTR_TXQ_TO_RST)) { 2234 if (status & INTR_DMA_RD_TO_RST) 2235 printf("%s: DMA read error! -- resetting\n", 2236 sc->sc_dev.dv_xname); 2237 if (status & INTR_DMA_WR_TO_RST) 2238 printf("%s: DMA write error! -- resetting\n", 2239 sc->sc_dev.dv_xname); 2240 if (status & INTR_TXQ_TO_RST) 2241 printf("%s: TxQ reset! -- resetting\n", 2242 sc->sc_dev.dv_xname); 2243 alc_init(ifp); 2244 return (0); 2245 } 2246 2247 alc_txeof(sc); 2248 alc_start(ifp); 2249 } 2250 2251 claimed = 1; 2252 back: 2253 /* Re-enable interrupts. */ 2254 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0x7FFFFFFF); 2255 return (claimed); 2256 } 2257 2258 void 2259 alc_txeof(struct alc_softc *sc) 2260 { 2261 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 2262 struct alc_txdesc *txd; 2263 uint32_t cons, prod; 2264 int prog; 2265 2266 if (sc->alc_cdata.alc_tx_cnt == 0) 2267 return; 2268 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0, 2269 sc->alc_cdata.alc_tx_ring_map->dm_mapsize, 2270 BUS_DMASYNC_POSTWRITE); 2271 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 2272 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0, 2273 sc->alc_cdata.alc_cmb_map->dm_mapsize, 2274 BUS_DMASYNC_POSTREAD); 2275 prod = sc->alc_rdata.alc_cmb->cons; 2276 } else { 2277 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 2278 prod = CSR_READ_2(sc, ALC_MBOX_TD_PRI0_CONS_IDX); 2279 else { 2280 prod = CSR_READ_4(sc, ALC_MBOX_TD_CONS_IDX); 2281 /* Assume we're using normal Tx priority queue. */ 2282 prod = (prod & MBOX_TD_CONS_LO_IDX_MASK) >> 2283 MBOX_TD_CONS_LO_IDX_SHIFT; 2284 } 2285 } 2286 cons = sc->alc_cdata.alc_tx_cons; 2287 /* 2288 * Go through our Tx list and free mbufs for those 2289 * frames which have been transmitted. 2290 */ 2291 for (prog = 0; cons != prod; prog++, 2292 ALC_DESC_INC(cons, ALC_TX_RING_CNT)) { 2293 if (sc->alc_cdata.alc_tx_cnt <= 0) 2294 break; 2295 prog++; 2296 ifq_clr_oactive(&ifp->if_snd); 2297 sc->alc_cdata.alc_tx_cnt--; 2298 txd = &sc->alc_cdata.alc_txdesc[cons]; 2299 if (txd->tx_m != NULL) { 2300 /* Reclaim transmitted mbufs. */ 2301 bus_dmamap_sync(sc->sc_dmat, txd->tx_dmamap, 0, 2302 txd->tx_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2303 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 2304 m_freem(txd->tx_m); 2305 txd->tx_m = NULL; 2306 } 2307 } 2308 2309 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 2310 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0, 2311 sc->alc_cdata.alc_cmb_map->dm_mapsize, BUS_DMASYNC_PREREAD); 2312 sc->alc_cdata.alc_tx_cons = cons; 2313 /* 2314 * Unarm watchdog timer only when there is no pending 2315 * frames in Tx queue. 2316 */ 2317 if (sc->alc_cdata.alc_tx_cnt == 0) 2318 ifp->if_timer = 0; 2319 } 2320 2321 int 2322 alc_newbuf(struct alc_softc *sc, struct alc_rxdesc *rxd) 2323 { 2324 struct mbuf *m; 2325 bus_dmamap_t map; 2326 int error; 2327 2328 MGETHDR(m, M_DONTWAIT, MT_DATA); 2329 if (m == NULL) 2330 return (ENOBUFS); 2331 MCLGET(m, M_DONTWAIT); 2332 if (!(m->m_flags & M_EXT)) { 2333 m_freem(m); 2334 return (ENOBUFS); 2335 } 2336 2337 m->m_len = m->m_pkthdr.len = RX_BUF_SIZE_MAX; 2338 2339 error = bus_dmamap_load_mbuf(sc->sc_dmat, 2340 sc->alc_cdata.alc_rx_sparemap, m, BUS_DMA_NOWAIT); 2341 2342 if (error != 0) { 2343 m_freem(m); 2344 printf("%s: can't load RX mbuf\n", sc->sc_dev.dv_xname); 2345 return (error); 2346 } 2347 2348 if (rxd->rx_m != NULL) { 2349 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0, 2350 rxd->rx_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2351 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 2352 } 2353 map = rxd->rx_dmamap; 2354 rxd->rx_dmamap = sc->alc_cdata.alc_rx_sparemap; 2355 sc->alc_cdata.alc_rx_sparemap = map; 2356 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0, rxd->rx_dmamap->dm_mapsize, 2357 BUS_DMASYNC_PREREAD); 2358 rxd->rx_m = m; 2359 rxd->rx_desc->addr = htole64(rxd->rx_dmamap->dm_segs[0].ds_addr); 2360 return (0); 2361 } 2362 2363 int 2364 alc_rxintr(struct alc_softc *sc) 2365 { 2366 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 2367 struct rx_rdesc *rrd; 2368 uint32_t nsegs, status; 2369 int rr_cons, prog; 2370 2371 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 0, 2372 sc->alc_cdata.alc_rr_ring_map->dm_mapsize, 2373 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2374 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 0, 2375 sc->alc_cdata.alc_rx_ring_map->dm_mapsize, 2376 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2377 rr_cons = sc->alc_cdata.alc_rr_cons; 2378 for (prog = 0; (ifp->if_flags & IFF_RUNNING) != 0;) { 2379 rrd = &sc->alc_rdata.alc_rr_ring[rr_cons]; 2380 status = letoh32(rrd->status); 2381 if ((status & RRD_VALID) == 0) 2382 break; 2383 nsegs = RRD_RD_CNT(letoh32(rrd->rdinfo)); 2384 if (nsegs == 0) { 2385 /* This should not happen! */ 2386 if (alcdebug) 2387 printf("%s: unexpected segment count -- " 2388 "resetting\n", sc->sc_dev.dv_xname); 2389 return (EIO); 2390 } 2391 alc_rxeof(sc, rrd); 2392 /* Clear Rx return status. */ 2393 rrd->status = 0; 2394 ALC_DESC_INC(rr_cons, ALC_RR_RING_CNT); 2395 sc->alc_cdata.alc_rx_cons += nsegs; 2396 sc->alc_cdata.alc_rx_cons %= ALC_RR_RING_CNT; 2397 prog += nsegs; 2398 } 2399 2400 if (prog > 0) { 2401 /* Update the consumer index. */ 2402 sc->alc_cdata.alc_rr_cons = rr_cons; 2403 /* Sync Rx return descriptors. */ 2404 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 0, 2405 sc->alc_cdata.alc_rr_ring_map->dm_mapsize, 2406 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2407 /* 2408 * Sync updated Rx descriptors such that controller see 2409 * modified buffer addresses. 2410 */ 2411 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 0, 2412 sc->alc_cdata.alc_rx_ring_map->dm_mapsize, 2413 BUS_DMASYNC_PREWRITE); 2414 /* 2415 * Let controller know availability of new Rx buffers. 2416 * Since alc(4) use RXQ_CFG_RD_BURST_DEFAULT descriptors 2417 * it may be possible to update ALC_MBOX_RD0_PROD_IDX 2418 * only when Rx buffer pre-fetching is required. In 2419 * addition we already set ALC_RX_RD_FREE_THRESH to 2420 * RX_RD_FREE_THRESH_LO_DEFAULT descriptors. However 2421 * it still seems that pre-fetching needs more 2422 * experimentation. 2423 */ 2424 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 2425 CSR_WRITE_2(sc, ALC_MBOX_RD0_PROD_IDX, 2426 (uint16_t)sc->alc_cdata.alc_rx_cons); 2427 else 2428 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 2429 sc->alc_cdata.alc_rx_cons); 2430 } 2431 2432 return (0); 2433 } 2434 2435 /* Receive a frame. */ 2436 void 2437 alc_rxeof(struct alc_softc *sc, struct rx_rdesc *rrd) 2438 { 2439 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 2440 struct alc_rxdesc *rxd; 2441 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 2442 struct mbuf *mp, *m; 2443 uint32_t rdinfo, status; 2444 int count, nsegs, rx_cons; 2445 2446 status = letoh32(rrd->status); 2447 rdinfo = letoh32(rrd->rdinfo); 2448 rx_cons = RRD_RD_IDX(rdinfo); 2449 nsegs = RRD_RD_CNT(rdinfo); 2450 2451 sc->alc_cdata.alc_rxlen = RRD_BYTES(status); 2452 if (status & (RRD_ERR_SUM | RRD_ERR_LENGTH)) { 2453 /* 2454 * We want to pass the following frames to upper 2455 * layer regardless of error status of Rx return 2456 * ring. 2457 * 2458 * o IP/TCP/UDP checksum is bad. 2459 * o frame length and protocol specific length 2460 * does not match. 2461 * 2462 * Force network stack compute checksum for 2463 * errored frames. 2464 */ 2465 if ((status & (RRD_ERR_CRC | RRD_ERR_ALIGN | 2466 RRD_ERR_TRUNC | RRD_ERR_RUNT)) != 0) 2467 return; 2468 } 2469 2470 for (count = 0; count < nsegs; count++, 2471 ALC_DESC_INC(rx_cons, ALC_RX_RING_CNT)) { 2472 rxd = &sc->alc_cdata.alc_rxdesc[rx_cons]; 2473 mp = rxd->rx_m; 2474 /* Add a new receive buffer to the ring. */ 2475 if (alc_newbuf(sc, rxd) != 0) { 2476 ifp->if_iqdrops++; 2477 /* Reuse Rx buffers. */ 2478 m_freem(sc->alc_cdata.alc_rxhead); 2479 break; 2480 } 2481 2482 /* 2483 * Assume we've received a full sized frame. 2484 * Actual size is fixed when we encounter the end of 2485 * multi-segmented frame. 2486 */ 2487 mp->m_len = sc->alc_buf_size; 2488 2489 /* Chain received mbufs. */ 2490 if (sc->alc_cdata.alc_rxhead == NULL) { 2491 sc->alc_cdata.alc_rxhead = mp; 2492 sc->alc_cdata.alc_rxtail = mp; 2493 } else { 2494 mp->m_flags &= ~M_PKTHDR; 2495 sc->alc_cdata.alc_rxprev_tail = 2496 sc->alc_cdata.alc_rxtail; 2497 sc->alc_cdata.alc_rxtail->m_next = mp; 2498 sc->alc_cdata.alc_rxtail = mp; 2499 } 2500 2501 if (count == nsegs - 1) { 2502 /* Last desc. for this frame. */ 2503 m = sc->alc_cdata.alc_rxhead; 2504 m->m_flags |= M_PKTHDR; 2505 /* 2506 * It seems that L1C/L2C controller has no way 2507 * to tell hardware to strip CRC bytes. 2508 */ 2509 m->m_pkthdr.len = 2510 sc->alc_cdata.alc_rxlen - ETHER_CRC_LEN; 2511 if (nsegs > 1) { 2512 /* Set last mbuf size. */ 2513 mp->m_len = sc->alc_cdata.alc_rxlen - 2514 (nsegs - 1) * sc->alc_buf_size; 2515 /* Remove the CRC bytes in chained mbufs. */ 2516 if (mp->m_len <= ETHER_CRC_LEN) { 2517 sc->alc_cdata.alc_rxtail = 2518 sc->alc_cdata.alc_rxprev_tail; 2519 sc->alc_cdata.alc_rxtail->m_len -= 2520 (ETHER_CRC_LEN - mp->m_len); 2521 sc->alc_cdata.alc_rxtail->m_next = NULL; 2522 m_freem(mp); 2523 } else { 2524 mp->m_len -= ETHER_CRC_LEN; 2525 } 2526 } else 2527 m->m_len = m->m_pkthdr.len; 2528 /* 2529 * Due to hardware bugs, Rx checksum offloading 2530 * was intentionally disabled. 2531 */ 2532 #if NVLAN > 0 2533 if (status & RRD_VLAN_TAG) { 2534 u_int32_t vtag = RRD_VLAN(letoh32(rrd->vtag)); 2535 m->m_pkthdr.ether_vtag = ntohs(vtag); 2536 m->m_flags |= M_VLANTAG; 2537 } 2538 #endif 2539 2540 2541 ml_enqueue(&ml, m); 2542 } 2543 } 2544 if_input(ifp, &ml); 2545 2546 /* Reset mbuf chains. */ 2547 ALC_RXCHAIN_RESET(sc); 2548 } 2549 2550 void 2551 alc_tick(void *xsc) 2552 { 2553 struct alc_softc *sc = xsc; 2554 struct mii_data *mii = &sc->sc_miibus; 2555 int s; 2556 2557 s = splnet(); 2558 mii_tick(mii); 2559 alc_stats_update(sc); 2560 2561 timeout_add_sec(&sc->alc_tick_ch, 1); 2562 splx(s); 2563 } 2564 2565 void 2566 alc_osc_reset(struct alc_softc *sc) 2567 { 2568 uint32_t reg; 2569 2570 reg = CSR_READ_4(sc, ALC_MISC3); 2571 reg &= ~MISC3_25M_BY_SW; 2572 reg |= MISC3_25M_NOTO_INTNL; 2573 CSR_WRITE_4(sc, ALC_MISC3, reg); 2574 reg = CSR_READ_4(sc, ALC_MISC); 2575 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0) { 2576 /* 2577 * Restore over-current protection default value. 2578 * This value could be reset by MAC reset. 2579 */ 2580 reg &= ~MISC_PSW_OCP_MASK; 2581 reg |= (MISC_PSW_OCP_DEFAULT << MISC_PSW_OCP_SHIFT); 2582 reg &= ~MISC_INTNLOSC_OPEN; 2583 CSR_WRITE_4(sc, ALC_MISC, reg); 2584 CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN); 2585 reg = CSR_READ_4(sc, ALC_MISC2); 2586 reg &= ~MISC2_CALB_START; 2587 CSR_WRITE_4(sc, ALC_MISC2, reg); 2588 CSR_WRITE_4(sc, ALC_MISC2, reg | MISC2_CALB_START); 2589 } else { 2590 reg &= ~MISC_INTNLOSC_OPEN; 2591 /* Disable isolate for revision A devices. */ 2592 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1) 2593 reg &= ~MISC_ISO_ENB; 2594 CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN); 2595 CSR_WRITE_4(sc, ALC_MISC, reg); 2596 } 2597 DELAY(20); 2598 } 2599 2600 void 2601 alc_reset(struct alc_softc *sc) 2602 { 2603 uint32_t reg, pmcfg = 0; 2604 int i; 2605 2606 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2607 /* Reset workaround. */ 2608 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 1); 2609 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 2610 (sc->alc_rev & 0x01) != 0) { 2611 /* Disable L0s/L1s before reset. */ 2612 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 2613 if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | 2614 PM_CFG_ASPM_L1_ENB))!= 0) { 2615 pmcfg &= ~(PM_CFG_ASPM_L0S_ENB | 2616 PM_CFG_ASPM_L1_ENB); 2617 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 2618 } 2619 } 2620 } 2621 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 2622 reg |= MASTER_OOB_DIS_OFF | MASTER_RESET; 2623 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 2624 2625 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2626 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 2627 DELAY(10); 2628 if (CSR_READ_4(sc, ALC_MBOX_RD0_PROD_IDX) == 0) 2629 break; 2630 } 2631 if (i == 0) 2632 printf("MAC reset timeout!\n"); 2633 } 2634 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 2635 DELAY(10); 2636 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0) 2637 break; 2638 } 2639 if (i == 0) 2640 printf("%s: master reset timeout!\n", sc->sc_dev.dv_xname); 2641 2642 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 2643 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 2644 if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC | 2645 IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 2646 break; 2647 DELAY(10); 2648 } 2649 2650 if (i == 0) 2651 printf("%s: reset timeout(0x%08x)!\n", sc->sc_dev.dv_xname, 2652 reg); 2653 2654 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2655 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 2656 (sc->alc_rev & 0x01) != 0) { 2657 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 2658 reg |= MASTER_CLK_SEL_DIS; 2659 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 2660 /* Restore L0s/L1s config. */ 2661 if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | 2662 PM_CFG_ASPM_L1_ENB)) != 0) 2663 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 2664 } 2665 alc_osc_reset(sc); 2666 reg = CSR_READ_4(sc, ALC_MISC3); 2667 reg &= ~MISC3_25M_BY_SW; 2668 reg |= MISC3_25M_NOTO_INTNL; 2669 CSR_WRITE_4(sc, ALC_MISC3, reg); 2670 reg = CSR_READ_4(sc, ALC_MISC); 2671 reg &= ~MISC_INTNLOSC_OPEN; 2672 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1) 2673 reg &= ~MISC_ISO_ENB; 2674 CSR_WRITE_4(sc, ALC_MISC, reg); 2675 DELAY(20); 2676 } 2677 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 2678 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1 || 2679 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_2) 2680 CSR_WRITE_4(sc, ALC_SERDES_LOCK, 2681 CSR_READ_4(sc, ALC_SERDES_LOCK) | 2682 SERDES_MAC_CLK_SLOWDOWN | SERDES_PHY_CLK_SLOWDOWN); 2683 } 2684 2685 int 2686 alc_init(struct ifnet *ifp) 2687 { 2688 struct alc_softc *sc = ifp->if_softc; 2689 uint8_t eaddr[ETHER_ADDR_LEN]; 2690 bus_addr_t paddr; 2691 uint32_t reg, rxf_hi, rxf_lo; 2692 int error; 2693 2694 /* 2695 * Cancel any pending I/O. 2696 */ 2697 alc_stop(sc); 2698 /* 2699 * Reset the chip to a known state. 2700 */ 2701 alc_reset(sc); 2702 2703 /* Initialize Rx descriptors. */ 2704 error = alc_init_rx_ring(sc); 2705 if (error != 0) { 2706 printf("%s: no memory for Rx buffers.\n", sc->sc_dev.dv_xname); 2707 alc_stop(sc); 2708 return (error); 2709 } 2710 alc_init_rr_ring(sc); 2711 alc_init_tx_ring(sc); 2712 alc_init_cmb(sc); 2713 alc_init_smb(sc); 2714 2715 /* Enable all clocks. */ 2716 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2717 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, CLK_GATING_DMAW_ENB | 2718 CLK_GATING_DMAR_ENB | CLK_GATING_TXQ_ENB | 2719 CLK_GATING_RXQ_ENB | CLK_GATING_TXMAC_ENB | 2720 CLK_GATING_RXMAC_ENB); 2721 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0) 2722 CSR_WRITE_4(sc, ALC_IDLE_DECISN_TIMER, 2723 IDLE_DECISN_TIMER_DEFAULT_1MS); 2724 } else 2725 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, 0); 2726 2727 /* Reprogram the station address. */ 2728 bcopy(LLADDR(ifp->if_sadl), eaddr, ETHER_ADDR_LEN); 2729 CSR_WRITE_4(sc, ALC_PAR0, 2730 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 2731 CSR_WRITE_4(sc, ALC_PAR1, eaddr[0] << 8 | eaddr[1]); 2732 /* 2733 * Clear WOL status and disable all WOL feature as WOL 2734 * would interfere Rx operation under normal environments. 2735 */ 2736 CSR_READ_4(sc, ALC_WOL_CFG); 2737 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 2738 /* Set Tx descriptor base addresses. */ 2739 paddr = sc->alc_rdata.alc_tx_ring_paddr; 2740 CSR_WRITE_4(sc, ALC_TX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 2741 CSR_WRITE_4(sc, ALC_TDL_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 2742 /* We don't use high priority ring. */ 2743 CSR_WRITE_4(sc, ALC_TDH_HEAD_ADDR_LO, 0); 2744 /* Set Tx descriptor counter. */ 2745 CSR_WRITE_4(sc, ALC_TD_RING_CNT, 2746 (ALC_TX_RING_CNT << TD_RING_CNT_SHIFT) & TD_RING_CNT_MASK); 2747 /* Set Rx descriptor base addresses. */ 2748 paddr = sc->alc_rdata.alc_rx_ring_paddr; 2749 CSR_WRITE_4(sc, ALC_RX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 2750 CSR_WRITE_4(sc, ALC_RD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 2751 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 2752 /* We use one Rx ring. */ 2753 CSR_WRITE_4(sc, ALC_RD1_HEAD_ADDR_LO, 0); 2754 CSR_WRITE_4(sc, ALC_RD2_HEAD_ADDR_LO, 0); 2755 CSR_WRITE_4(sc, ALC_RD3_HEAD_ADDR_LO, 0); 2756 } 2757 /* Set Rx descriptor counter. */ 2758 CSR_WRITE_4(sc, ALC_RD_RING_CNT, 2759 (ALC_RX_RING_CNT << RD_RING_CNT_SHIFT) & RD_RING_CNT_MASK); 2760 2761 /* 2762 * Let hardware split jumbo frames into alc_max_buf_sized chunks. 2763 * if it do not fit the buffer size. Rx return descriptor holds 2764 * a counter that indicates how many fragments were made by the 2765 * hardware. The buffer size should be multiple of 8 bytes. 2766 * Since hardware has limit on the size of buffer size, always 2767 * use the maximum value. 2768 * For strict-alignment architectures make sure to reduce buffer 2769 * size by 8 bytes to make room for alignment fixup. 2770 */ 2771 sc->alc_buf_size = RX_BUF_SIZE_MAX; 2772 CSR_WRITE_4(sc, ALC_RX_BUF_SIZE, sc->alc_buf_size); 2773 2774 paddr = sc->alc_rdata.alc_rr_ring_paddr; 2775 /* Set Rx return descriptor base addresses. */ 2776 CSR_WRITE_4(sc, ALC_RRD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 2777 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 2778 /* We use one Rx return ring. */ 2779 CSR_WRITE_4(sc, ALC_RRD1_HEAD_ADDR_LO, 0); 2780 CSR_WRITE_4(sc, ALC_RRD2_HEAD_ADDR_LO, 0); 2781 CSR_WRITE_4(sc, ALC_RRD3_HEAD_ADDR_LO, 0); 2782 } 2783 /* Set Rx return descriptor counter. */ 2784 CSR_WRITE_4(sc, ALC_RRD_RING_CNT, 2785 (ALC_RR_RING_CNT << RRD_RING_CNT_SHIFT) & RRD_RING_CNT_MASK); 2786 paddr = sc->alc_rdata.alc_cmb_paddr; 2787 CSR_WRITE_4(sc, ALC_CMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 2788 paddr = sc->alc_rdata.alc_smb_paddr; 2789 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 2790 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 2791 2792 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1) { 2793 /* Reconfigure SRAM - Vendor magic. */ 2794 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_LEN, 0x000002A0); 2795 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_LEN, 0x00000100); 2796 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_ADDR, 0x029F0000); 2797 CSR_WRITE_4(sc, ALC_SRAM_RD0_ADDR, 0x02BF02A0); 2798 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_ADDR, 0x03BF02C0); 2799 CSR_WRITE_4(sc, ALC_SRAM_TD_ADDR, 0x03DF03C0); 2800 CSR_WRITE_4(sc, ALC_TXF_WATER_MARK, 0x00000000); 2801 CSR_WRITE_4(sc, ALC_RD_DMA_CFG, 0x00000000); 2802 } 2803 2804 /* Tell hardware that we're ready to load DMA blocks. */ 2805 CSR_WRITE_4(sc, ALC_DMA_BLOCK, DMA_BLOCK_LOAD); 2806 2807 /* Configure interrupt moderation timer. */ 2808 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 2809 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 2810 reg = ALC_USECS(sc->alc_int_rx_mod) << IM_TIMER_RX_SHIFT; 2811 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) 2812 reg |= ALC_USECS(sc->alc_int_tx_mod) << IM_TIMER_TX_SHIFT; 2813 CSR_WRITE_4(sc, ALC_IM_TIMER, reg); 2814 /* 2815 * We don't want to automatic interrupt clear as task queue 2816 * for the interrupt should know interrupt status. 2817 */ 2818 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 2819 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); 2820 reg |= MASTER_SA_TIMER_ENB; 2821 if (ALC_USECS(sc->alc_int_rx_mod) != 0) 2822 reg |= MASTER_IM_RX_TIMER_ENB; 2823 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0 && 2824 ALC_USECS(sc->alc_int_tx_mod) != 0) 2825 reg |= MASTER_IM_TX_TIMER_ENB; 2826 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 2827 /* 2828 * Disable interrupt re-trigger timer. We don't want automatic 2829 * re-triggering of un-ACKed interrupts. 2830 */ 2831 CSR_WRITE_4(sc, ALC_INTR_RETRIG_TIMER, ALC_USECS(0)); 2832 /* Configure CMB. */ 2833 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2834 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, ALC_TX_RING_CNT / 3); 2835 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, 2836 ALC_USECS(sc->alc_int_tx_mod)); 2837 } else { 2838 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 2839 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, 4); 2840 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(5000)); 2841 } else 2842 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(0)); 2843 } 2844 /* 2845 * Hardware can be configured to issue SMB interrupt based 2846 * on programmed interval. Since there is a callout that is 2847 * invoked for every hz in driver we use that instead of 2848 * relying on periodic SMB interrupt. 2849 */ 2850 CSR_WRITE_4(sc, ALC_SMB_STAT_TIMER, ALC_USECS(0)); 2851 /* Clear MAC statistics. */ 2852 alc_stats_clear(sc); 2853 2854 /* 2855 * Always use maximum frame size that controller can support. 2856 * Otherwise received frames that has larger frame length 2857 * than alc(4) MTU would be silently dropped in hardware. This 2858 * would make path-MTU discovery hard as sender wouldn't get 2859 * any responses from receiver. alc(4) supports 2860 * multi-fragmented frames on Rx path so it has no issue on 2861 * assembling fragmented frames. Using maximum frame size also 2862 * removes the need to reinitialize hardware when interface 2863 * MTU configuration was changed. 2864 * 2865 * Be conservative in what you do, be liberal in what you 2866 * accept from others - RFC 793. 2867 */ 2868 CSR_WRITE_4(sc, ALC_FRAME_SIZE, sc->alc_max_framelen); 2869 2870 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 2871 /* Disable header split(?) */ 2872 CSR_WRITE_4(sc, ALC_HDS_CFG, 0); 2873 /* Configure IPG/IFG parameters. */ 2874 CSR_WRITE_4(sc, ALC_IPG_IFG_CFG, 2875 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & 2876 IPG_IFG_IPGT_MASK) | 2877 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & 2878 IPG_IFG_MIFG_MASK) | 2879 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & 2880 IPG_IFG_IPG1_MASK) | 2881 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & 2882 IPG_IFG_IPG2_MASK)); 2883 /* Set parameters for half-duplex media. */ 2884 CSR_WRITE_4(sc, ALC_HDPX_CFG, 2885 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 2886 HDPX_CFG_LCOL_MASK) | 2887 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 2888 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 2889 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 2890 HDPX_CFG_ABEBT_MASK) | 2891 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 2892 HDPX_CFG_JAMIPG_MASK)); 2893 } 2894 2895 /* 2896 * Set TSO/checksum offload threshold. For frames that is 2897 * larger than this threshold, hardware wouldn't do 2898 * TSO/checksum offloading. 2899 */ 2900 reg = (sc->alc_max_framelen >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) & 2901 TSO_OFFLOAD_THRESH_MASK; 2902 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 2903 reg |= TSO_OFFLOAD_ERRLGPKT_DROP_ENB; 2904 CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH, reg); 2905 /* Configure TxQ. */ 2906 reg = (alc_dma_burst[sc->alc_dma_rd_burst] << 2907 TXQ_CFG_TX_FIFO_BURST_SHIFT) & TXQ_CFG_TX_FIFO_BURST_MASK; 2908 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1 || 2909 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_2) 2910 reg >>= 1; 2911 reg |= (TXQ_CFG_TD_BURST_DEFAULT << TXQ_CFG_TD_BURST_SHIFT) & 2912 TXQ_CFG_TD_BURST_MASK; 2913 reg |= TXQ_CFG_IP_OPTION_ENB | TXQ_CFG_8023_ENB; 2914 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE); 2915 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2916 reg = (TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q1_BURST_SHIFT | 2917 TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q2_BURST_SHIFT | 2918 TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q3_BURST_SHIFT | 2919 HQTD_CFG_BURST_ENB); 2920 CSR_WRITE_4(sc, ALC_HQTD_CFG, reg); 2921 reg = WRR_PRI_RESTRICT_NONE; 2922 reg |= (WRR_PRI_DEFAULT << WRR_PRI0_SHIFT | 2923 WRR_PRI_DEFAULT << WRR_PRI1_SHIFT | 2924 WRR_PRI_DEFAULT << WRR_PRI2_SHIFT | 2925 WRR_PRI_DEFAULT << WRR_PRI3_SHIFT); 2926 CSR_WRITE_4(sc, ALC_WRR, reg); 2927 } else { 2928 /* Configure Rx free descriptor pre-fetching. */ 2929 CSR_WRITE_4(sc, ALC_RX_RD_FREE_THRESH, 2930 ((RX_RD_FREE_THRESH_HI_DEFAULT << 2931 RX_RD_FREE_THRESH_HI_SHIFT) & RX_RD_FREE_THRESH_HI_MASK) | 2932 ((RX_RD_FREE_THRESH_LO_DEFAULT << 2933 RX_RD_FREE_THRESH_LO_SHIFT) & RX_RD_FREE_THRESH_LO_MASK)); 2934 } 2935 2936 /* 2937 * Configure flow control parameters. 2938 * XON : 80% of Rx FIFO 2939 * XOFF : 30% of Rx FIFO 2940 */ 2941 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2942 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 2943 reg &= SRAM_RX_FIFO_LEN_MASK; 2944 reg *= 8; 2945 if (reg > 8 * 1024) 2946 reg -= RX_FIFO_PAUSE_816X_RSVD; 2947 else 2948 reg -= RX_BUF_SIZE_MAX; 2949 reg /= 8; 2950 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 2951 ((reg << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 2952 RX_FIFO_PAUSE_THRESH_LO_MASK) | 2953 (((RX_FIFO_PAUSE_816X_RSVD / 8) << 2954 RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 2955 RX_FIFO_PAUSE_THRESH_HI_MASK)); 2956 } else if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1C|| 2957 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C) { 2958 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 2959 rxf_hi = (reg * 8) / 10; 2960 rxf_lo = (reg * 3) / 10; 2961 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 2962 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 2963 RX_FIFO_PAUSE_THRESH_LO_MASK) | 2964 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 2965 RX_FIFO_PAUSE_THRESH_HI_MASK)); 2966 } 2967 2968 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 2969 /* Disable RSS until I understand L1C/L2C's RSS logic. */ 2970 CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0); 2971 CSR_WRITE_4(sc, ALC_RSS_CPU, 0); 2972 } 2973 2974 /* Configure RxQ. */ 2975 reg = (RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 2976 RXQ_CFG_RD_BURST_MASK; 2977 reg |= RXQ_CFG_RSS_MODE_DIS; 2978 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2979 reg |= (RXQ_CFG_816X_IDT_TBL_SIZE_DEFAULT << 2980 RXQ_CFG_816X_IDT_TBL_SIZE_SHIFT) & 2981 RXQ_CFG_816X_IDT_TBL_SIZE_MASK; 2982 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 2983 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M; 2984 } else { 2985 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0 && 2986 sc->sc_product != PCI_PRODUCT_ATTANSIC_L1D_1) 2987 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M; 2988 } 2989 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 2990 2991 /* Configure DMA parameters. */ 2992 reg = DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI; 2993 reg |= sc->alc_rcb; 2994 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 2995 reg |= DMA_CFG_CMB_ENB; 2996 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) 2997 reg |= DMA_CFG_SMB_ENB; 2998 else 2999 reg |= DMA_CFG_SMB_DIS; 3000 reg |= (sc->alc_dma_rd_burst & DMA_CFG_RD_BURST_MASK) << 3001 DMA_CFG_RD_BURST_SHIFT; 3002 reg |= (sc->alc_dma_wr_burst & DMA_CFG_WR_BURST_MASK) << 3003 DMA_CFG_WR_BURST_SHIFT; 3004 reg |= (DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 3005 DMA_CFG_RD_DELAY_CNT_MASK; 3006 reg |= (DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 3007 DMA_CFG_WR_DELAY_CNT_MASK; 3008 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3009 switch (AR816X_REV(sc->alc_rev)) { 3010 case AR816X_REV_A0: 3011 case AR816X_REV_A1: 3012 reg |= DMA_CFG_RD_CHNL_SEL_2; 3013 break; 3014 case AR816X_REV_B0: 3015 /* FALLTHROUGH */ 3016 default: 3017 reg |= DMA_CFG_RD_CHNL_SEL_4; 3018 break; 3019 } 3020 } 3021 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 3022 3023 /* 3024 * Configure Tx/Rx MACs. 3025 * - Auto-padding for short frames. 3026 * - Enable CRC generation. 3027 * Actual reconfiguration of MAC for resolved speed/duplex 3028 * is followed after detection of link establishment. 3029 * AR813x/AR815x always does checksum computation regardless 3030 * of MAC_CFG_RXCSUM_ENB bit. Also the controller is known to 3031 * have bug in protocol field in Rx return structure so 3032 * these controllers can't handle fragmented frames. Disable 3033 * Rx checksum offloading until there is a newer controller 3034 * that has sane implementation. 3035 */ 3036 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 3037 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 3038 MAC_CFG_PREAMBLE_MASK); 3039 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 3040 sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D || 3041 sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D_1 || 3042 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_2) 3043 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 3044 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0) 3045 reg |= MAC_CFG_SPEED_10_100; 3046 else 3047 reg |= MAC_CFG_SPEED_1000; 3048 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3049 3050 /* Set up the receive filter. */ 3051 alc_iff(sc); 3052 3053 alc_rxvlan(sc); 3054 3055 /* Acknowledge all pending interrupts and clear it. */ 3056 CSR_WRITE_4(sc, ALC_INTR_MASK, ALC_INTRS); 3057 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3058 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0); 3059 3060 ifp->if_flags |= IFF_RUNNING; 3061 ifq_clr_oactive(&ifp->if_snd); 3062 3063 sc->alc_flags &= ~ALC_FLAG_LINK; 3064 /* Switch to the current media. */ 3065 alc_mediachange(ifp); 3066 3067 timeout_add_sec(&sc->alc_tick_ch, 1); 3068 3069 return (0); 3070 } 3071 3072 void 3073 alc_stop(struct alc_softc *sc) 3074 { 3075 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 3076 struct alc_txdesc *txd; 3077 struct alc_rxdesc *rxd; 3078 uint32_t reg; 3079 int i; 3080 3081 /* 3082 * Mark the interface down and cancel the watchdog timer. 3083 */ 3084 ifp->if_flags &= ~IFF_RUNNING; 3085 ifq_clr_oactive(&ifp->if_snd); 3086 ifp->if_timer = 0; 3087 3088 timeout_del(&sc->alc_tick_ch); 3089 sc->alc_flags &= ~ALC_FLAG_LINK; 3090 3091 alc_stats_update(sc); 3092 3093 /* Disable interrupts. */ 3094 CSR_WRITE_4(sc, ALC_INTR_MASK, 0); 3095 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3096 3097 /* Disable DMA. */ 3098 reg = CSR_READ_4(sc, ALC_DMA_CFG); 3099 reg &= ~(DMA_CFG_CMB_ENB | DMA_CFG_SMB_ENB); 3100 reg |= DMA_CFG_SMB_DIS; 3101 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 3102 DELAY(1000); 3103 3104 /* Stop Rx/Tx MACs. */ 3105 alc_stop_mac(sc); 3106 3107 /* Disable interrupts which might be touched in taskq handler. */ 3108 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3109 3110 /* Disable L0s/L1s */ 3111 reg = CSR_READ_4(sc, ALC_PM_CFG); 3112 if ((reg & (PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB))!= 0) { 3113 reg &= ~(PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB); 3114 CSR_WRITE_4(sc, ALC_PM_CFG, reg); 3115 } 3116 3117 /* Reclaim Rx buffers that have been processed. */ 3118 m_freem(sc->alc_cdata.alc_rxhead); 3119 ALC_RXCHAIN_RESET(sc); 3120 /* 3121 * Free Tx/Rx mbufs still in the queues. 3122 */ 3123 for (i = 0; i < ALC_RX_RING_CNT; i++) { 3124 rxd = &sc->alc_cdata.alc_rxdesc[i]; 3125 if (rxd->rx_m != NULL) { 3126 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0, 3127 rxd->rx_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 3128 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 3129 m_freem(rxd->rx_m); 3130 rxd->rx_m = NULL; 3131 } 3132 } 3133 for (i = 0; i < ALC_TX_RING_CNT; i++) { 3134 txd = &sc->alc_cdata.alc_txdesc[i]; 3135 if (txd->tx_m != NULL) { 3136 bus_dmamap_sync(sc->sc_dmat, txd->tx_dmamap, 0, 3137 txd->tx_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 3138 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 3139 m_freem(txd->tx_m); 3140 txd->tx_m = NULL; 3141 } 3142 } 3143 } 3144 3145 void 3146 alc_stop_mac(struct alc_softc *sc) 3147 { 3148 uint32_t reg; 3149 int i; 3150 3151 alc_stop_queue(sc); 3152 /* Disable Rx/Tx MAC. */ 3153 reg = CSR_READ_4(sc, ALC_MAC_CFG); 3154 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 3155 reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 3156 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3157 } 3158 for (i = ALC_TIMEOUT; i > 0; i--) { 3159 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 3160 if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC)) == 0) 3161 break; 3162 DELAY(10); 3163 } 3164 if (i == 0) 3165 printf("%s: could not disable Rx/Tx MAC(0x%08x)!\n", 3166 sc->sc_dev.dv_xname, reg); 3167 } 3168 3169 void 3170 alc_start_queue(struct alc_softc *sc) 3171 { 3172 uint32_t qcfg[] = { 3173 0, 3174 RXQ_CFG_QUEUE0_ENB, 3175 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB, 3176 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | RXQ_CFG_QUEUE2_ENB, 3177 RXQ_CFG_ENB 3178 }; 3179 uint32_t cfg; 3180 3181 /* Enable RxQ. */ 3182 cfg = CSR_READ_4(sc, ALC_RXQ_CFG); 3183 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 3184 cfg &= ~RXQ_CFG_ENB; 3185 cfg |= qcfg[1]; 3186 } else 3187 cfg |= RXQ_CFG_QUEUE0_ENB; 3188 3189 CSR_WRITE_4(sc, ALC_RXQ_CFG, cfg); 3190 /* Enable TxQ. */ 3191 cfg = CSR_READ_4(sc, ALC_TXQ_CFG); 3192 cfg |= TXQ_CFG_ENB; 3193 CSR_WRITE_4(sc, ALC_TXQ_CFG, cfg); 3194 } 3195 3196 void 3197 alc_stop_queue(struct alc_softc *sc) 3198 { 3199 uint32_t reg; 3200 int i; 3201 3202 /* Disable RxQ. */ 3203 reg = CSR_READ_4(sc, ALC_RXQ_CFG); 3204 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 3205 if ((reg & RXQ_CFG_ENB) != 0) { 3206 reg &= ~RXQ_CFG_ENB; 3207 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 3208 } 3209 } else { 3210 if ((reg & RXQ_CFG_QUEUE0_ENB) != 0) { 3211 reg &= ~RXQ_CFG_QUEUE0_ENB; 3212 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 3213 } 3214 } 3215 /* Disable TxQ. */ 3216 reg = CSR_READ_4(sc, ALC_TXQ_CFG); 3217 if ((reg & TXQ_CFG_ENB) != 0) { 3218 reg &= ~TXQ_CFG_ENB; 3219 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg); 3220 } 3221 DELAY(40); 3222 for (i = ALC_TIMEOUT; i > 0; i--) { 3223 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 3224 if ((reg & (IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 3225 break; 3226 DELAY(10); 3227 } 3228 if (i == 0) 3229 printf("%s: could not disable RxQ/TxQ (0x%08x)!\n", 3230 sc->sc_dev.dv_xname, reg); 3231 } 3232 3233 void 3234 alc_init_tx_ring(struct alc_softc *sc) 3235 { 3236 struct alc_ring_data *rd; 3237 struct alc_txdesc *txd; 3238 int i; 3239 3240 sc->alc_cdata.alc_tx_prod = 0; 3241 sc->alc_cdata.alc_tx_cons = 0; 3242 sc->alc_cdata.alc_tx_cnt = 0; 3243 3244 rd = &sc->alc_rdata; 3245 bzero(rd->alc_tx_ring, ALC_TX_RING_SZ); 3246 for (i = 0; i < ALC_TX_RING_CNT; i++) { 3247 txd = &sc->alc_cdata.alc_txdesc[i]; 3248 txd->tx_m = NULL; 3249 } 3250 3251 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0, 3252 sc->alc_cdata.alc_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 3253 } 3254 3255 int 3256 alc_init_rx_ring(struct alc_softc *sc) 3257 { 3258 struct alc_ring_data *rd; 3259 struct alc_rxdesc *rxd; 3260 int i; 3261 3262 sc->alc_cdata.alc_rx_cons = ALC_RX_RING_CNT - 1; 3263 rd = &sc->alc_rdata; 3264 bzero(rd->alc_rx_ring, ALC_RX_RING_SZ); 3265 for (i = 0; i < ALC_RX_RING_CNT; i++) { 3266 rxd = &sc->alc_cdata.alc_rxdesc[i]; 3267 rxd->rx_m = NULL; 3268 rxd->rx_desc = &rd->alc_rx_ring[i]; 3269 if (alc_newbuf(sc, rxd) != 0) 3270 return (ENOBUFS); 3271 } 3272 3273 /* 3274 * Since controller does not update Rx descriptors, driver 3275 * does have to read Rx descriptors back so BUS_DMASYNC_PREWRITE 3276 * is enough to ensure coherence. 3277 */ 3278 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 0, 3279 sc->alc_cdata.alc_rx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 3280 /* Let controller know availability of new Rx buffers. */ 3281 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, sc->alc_cdata.alc_rx_cons); 3282 3283 return (0); 3284 } 3285 3286 void 3287 alc_init_rr_ring(struct alc_softc *sc) 3288 { 3289 struct alc_ring_data *rd; 3290 3291 sc->alc_cdata.alc_rr_cons = 0; 3292 ALC_RXCHAIN_RESET(sc); 3293 3294 rd = &sc->alc_rdata; 3295 bzero(rd->alc_rr_ring, ALC_RR_RING_SZ); 3296 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 0, 3297 sc->alc_cdata.alc_rr_ring_map->dm_mapsize, 3298 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3299 } 3300 3301 void 3302 alc_init_cmb(struct alc_softc *sc) 3303 { 3304 struct alc_ring_data *rd; 3305 3306 rd = &sc->alc_rdata; 3307 bzero(rd->alc_cmb, ALC_CMB_SZ); 3308 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0, 3309 sc->alc_cdata.alc_cmb_map->dm_mapsize, 3310 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3311 } 3312 3313 void 3314 alc_init_smb(struct alc_softc *sc) 3315 { 3316 struct alc_ring_data *rd; 3317 3318 rd = &sc->alc_rdata; 3319 bzero(rd->alc_smb, ALC_SMB_SZ); 3320 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 3321 sc->alc_cdata.alc_smb_map->dm_mapsize, 3322 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3323 } 3324 3325 void 3326 alc_rxvlan(struct alc_softc *sc) 3327 { 3328 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 3329 uint32_t reg; 3330 3331 reg = CSR_READ_4(sc, ALC_MAC_CFG); 3332 if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) 3333 reg |= MAC_CFG_VLAN_TAG_STRIP; 3334 else 3335 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 3336 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3337 } 3338 3339 void 3340 alc_iff(struct alc_softc *sc) 3341 { 3342 struct arpcom *ac = &sc->sc_arpcom; 3343 struct ifnet *ifp = &ac->ac_if; 3344 struct ether_multi *enm; 3345 struct ether_multistep step; 3346 uint32_t crc; 3347 uint32_t mchash[2]; 3348 uint32_t rxcfg; 3349 3350 rxcfg = CSR_READ_4(sc, ALC_MAC_CFG); 3351 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 3352 ifp->if_flags &= ~IFF_ALLMULTI; 3353 3354 /* 3355 * Always accept broadcast frames. 3356 */ 3357 rxcfg |= MAC_CFG_BCAST; 3358 3359 if (ifp->if_flags & IFF_PROMISC || ac->ac_multirangecnt > 0) { 3360 ifp->if_flags |= IFF_ALLMULTI; 3361 if (ifp->if_flags & IFF_PROMISC) 3362 rxcfg |= MAC_CFG_PROMISC; 3363 else 3364 rxcfg |= MAC_CFG_ALLMULTI; 3365 mchash[0] = mchash[1] = 0xFFFFFFFF; 3366 } else { 3367 /* Program new filter. */ 3368 bzero(mchash, sizeof(mchash)); 3369 3370 ETHER_FIRST_MULTI(step, ac, enm); 3371 while (enm != NULL) { 3372 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3373 3374 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 3375 3376 ETHER_NEXT_MULTI(step, enm); 3377 } 3378 } 3379 3380 CSR_WRITE_4(sc, ALC_MAR0, mchash[0]); 3381 CSR_WRITE_4(sc, ALC_MAR1, mchash[1]); 3382 CSR_WRITE_4(sc, ALC_MAC_CFG, rxcfg); 3383 } 3384