1 /* $OpenBSD: if_alc.c,v 1.41 2017/01/22 10:17:38 dlg Exp $ */ 2 /*- 3 * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* Driver for Atheros AR8131/AR8132 PCIe Ethernet. */ 30 31 #include "bpfilter.h" 32 #include "vlan.h" 33 34 #include <sys/param.h> 35 #include <sys/endian.h> 36 #include <sys/systm.h> 37 #include <sys/types.h> 38 #include <sys/sockio.h> 39 #include <sys/mbuf.h> 40 #include <sys/queue.h> 41 #include <sys/kernel.h> 42 #include <sys/device.h> 43 #include <sys/timeout.h> 44 #include <sys/socket.h> 45 46 #include <machine/bus.h> 47 48 #include <net/if.h> 49 #include <net/if_dl.h> 50 #include <net/if_media.h> 51 52 #include <netinet/in.h> 53 #include <netinet/if_ether.h> 54 55 #if NBPFILTER > 0 56 #include <net/bpf.h> 57 #endif 58 59 #include <dev/mii/mii.h> 60 #include <dev/mii/miivar.h> 61 62 #include <dev/pci/pcireg.h> 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pcidevs.h> 65 66 #include <dev/pci/if_alcreg.h> 67 68 int alc_match(struct device *, void *, void *); 69 void alc_attach(struct device *, struct device *, void *); 70 int alc_detach(struct device *, int); 71 int alc_activate(struct device *, int); 72 73 int alc_init(struct ifnet *); 74 void alc_start(struct ifnet *); 75 int alc_ioctl(struct ifnet *, u_long, caddr_t); 76 void alc_watchdog(struct ifnet *); 77 int alc_mediachange(struct ifnet *); 78 void alc_mediastatus(struct ifnet *, struct ifmediareq *); 79 80 void alc_aspm(struct alc_softc *, uint64_t); 81 void alc_disable_l0s_l1(struct alc_softc *); 82 int alc_dma_alloc(struct alc_softc *); 83 void alc_dma_free(struct alc_softc *); 84 int alc_encap(struct alc_softc *, struct mbuf *); 85 void alc_get_macaddr(struct alc_softc *); 86 void alc_init_cmb(struct alc_softc *); 87 void alc_init_rr_ring(struct alc_softc *); 88 int alc_init_rx_ring(struct alc_softc *); 89 void alc_init_smb(struct alc_softc *); 90 void alc_init_tx_ring(struct alc_softc *); 91 int alc_intr(void *); 92 void alc_mac_config(struct alc_softc *); 93 int alc_miibus_readreg(struct device *, int, int); 94 void alc_miibus_statchg(struct device *); 95 void alc_miibus_writereg(struct device *, int, int, int); 96 int alc_newbuf(struct alc_softc *, struct alc_rxdesc *); 97 void alc_phy_down(struct alc_softc *); 98 void alc_phy_reset(struct alc_softc *); 99 void alc_reset(struct alc_softc *); 100 void alc_rxeof(struct alc_softc *, struct rx_rdesc *); 101 void alc_rxintr(struct alc_softc *); 102 void alc_iff(struct alc_softc *); 103 void alc_rxvlan(struct alc_softc *); 104 void alc_start_queue(struct alc_softc *); 105 void alc_stats_clear(struct alc_softc *); 106 void alc_stats_update(struct alc_softc *); 107 void alc_stop(struct alc_softc *); 108 void alc_stop_mac(struct alc_softc *); 109 void alc_stop_queue(struct alc_softc *); 110 void alc_tick(void *); 111 void alc_txeof(struct alc_softc *); 112 113 uint32_t alc_dma_burst[] = { 128, 256, 512, 1024, 2048, 4096, 0 }; 114 115 const struct pci_matchid alc_devices[] = { 116 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L1C }, 117 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L2C }, 118 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L1D }, 119 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L1D_1 }, 120 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L2C_1 }, 121 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L2C_2 } 122 }; 123 124 struct cfattach alc_ca = { 125 sizeof (struct alc_softc), alc_match, alc_attach, NULL, 126 alc_activate 127 }; 128 129 struct cfdriver alc_cd = { 130 NULL, "alc", DV_IFNET 131 }; 132 133 int alcdebug = 0; 134 #define DPRINTF(x) do { if (alcdebug) printf x; } while (0) 135 136 #define ALC_CSUM_FEATURES (M_TCP_CSUM_OUT | M_UDP_CSUM_OUT) 137 138 int 139 alc_miibus_readreg(struct device *dev, int phy, int reg) 140 { 141 struct alc_softc *sc = (struct alc_softc *)dev; 142 uint32_t v; 143 int i; 144 145 if (phy != sc->alc_phyaddr) 146 return (0); 147 148 /* 149 * For AR8132 fast ethernet controller, do not report 1000baseT 150 * capability to mii(4). Even though AR8132 uses the same 151 * model/revision number of F1 gigabit PHY, the PHY has no 152 * ability to establish 1000baseT link. 153 */ 154 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0 && 155 reg == MII_EXTSR) 156 return (0); 157 158 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 159 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 160 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 161 DELAY(5); 162 v = CSR_READ_4(sc, ALC_MDIO); 163 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 164 break; 165 } 166 167 if (i == 0) { 168 printf("%s: phy read timeout: phy %d, reg %d\n", 169 sc->sc_dev.dv_xname, phy, reg); 170 return (0); 171 } 172 173 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 174 } 175 176 void 177 alc_miibus_writereg(struct device *dev, int phy, int reg, int val) 178 { 179 struct alc_softc *sc = (struct alc_softc *)dev; 180 uint32_t v; 181 int i; 182 183 if (phy != sc->alc_phyaddr) 184 return; 185 186 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 187 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 188 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 189 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 190 DELAY(5); 191 v = CSR_READ_4(sc, ALC_MDIO); 192 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 193 break; 194 } 195 196 if (i == 0) 197 printf("%s: phy write timeout: phy %d, reg %d\n", 198 sc->sc_dev.dv_xname, phy, reg); 199 } 200 201 void 202 alc_miibus_statchg(struct device *dev) 203 { 204 struct alc_softc *sc = (struct alc_softc *)dev; 205 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 206 struct mii_data *mii = &sc->sc_miibus; 207 uint32_t reg; 208 209 if ((ifp->if_flags & IFF_RUNNING) == 0) 210 return; 211 212 sc->alc_flags &= ~ALC_FLAG_LINK; 213 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 214 (IFM_ACTIVE | IFM_AVALID)) { 215 switch (IFM_SUBTYPE(mii->mii_media_active)) { 216 case IFM_10_T: 217 case IFM_100_TX: 218 sc->alc_flags |= ALC_FLAG_LINK; 219 break; 220 case IFM_1000_T: 221 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 222 sc->alc_flags |= ALC_FLAG_LINK; 223 break; 224 default: 225 break; 226 } 227 } 228 alc_stop_queue(sc); 229 /* Stop Rx/Tx MACs. */ 230 alc_stop_mac(sc); 231 232 /* Program MACs with resolved speed/duplex/flow-control. */ 233 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 234 alc_start_queue(sc); 235 alc_mac_config(sc); 236 /* Re-enable Tx/Rx MACs. */ 237 reg = CSR_READ_4(sc, ALC_MAC_CFG); 238 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 239 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 240 alc_aspm(sc, IFM_SUBTYPE(mii->mii_media_active)); 241 } 242 } 243 244 void 245 alc_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 246 { 247 struct alc_softc *sc = ifp->if_softc; 248 struct mii_data *mii = &sc->sc_miibus; 249 250 if ((ifp->if_flags & IFF_UP) == 0) 251 return; 252 253 mii_pollstat(mii); 254 ifmr->ifm_status = mii->mii_media_status; 255 ifmr->ifm_active = mii->mii_media_active; 256 } 257 258 int 259 alc_mediachange(struct ifnet *ifp) 260 { 261 struct alc_softc *sc = ifp->if_softc; 262 struct mii_data *mii = &sc->sc_miibus; 263 int error; 264 265 if (mii->mii_instance != 0) { 266 struct mii_softc *miisc; 267 268 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 269 mii_phy_reset(miisc); 270 } 271 error = mii_mediachg(mii); 272 273 return (error); 274 } 275 276 int 277 alc_match(struct device *dev, void *match, void *aux) 278 { 279 return pci_matchbyid((struct pci_attach_args *)aux, alc_devices, 280 nitems(alc_devices)); 281 } 282 283 void 284 alc_get_macaddr(struct alc_softc *sc) 285 { 286 uint32_t ea[2], opt; 287 uint16_t val; 288 int eeprom, i; 289 290 eeprom = 0; 291 opt = CSR_READ_4(sc, ALC_OPT_CFG); 292 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 && 293 (CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) { 294 /* 295 * EEPROM found, let TWSI reload EEPROM configuration. 296 * This will set ethernet address of controller. 297 */ 298 eeprom++; 299 switch (sc->sc_product) { 300 case PCI_PRODUCT_ATTANSIC_L1C: 301 case PCI_PRODUCT_ATTANSIC_L2C: 302 if ((opt & OPT_CFG_CLK_ENB) == 0) { 303 opt |= OPT_CFG_CLK_ENB; 304 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 305 CSR_READ_4(sc, ALC_OPT_CFG); 306 DELAY(1000); 307 } 308 break; 309 case PCI_PRODUCT_ATTANSIC_L1D: 310 case PCI_PRODUCT_ATTANSIC_L1D_1: 311 case PCI_PRODUCT_ATTANSIC_L2C_1: 312 case PCI_PRODUCT_ATTANSIC_L2C_2: 313 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 314 ALC_MII_DBG_ADDR, 0x00); 315 val = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr, 316 ALC_MII_DBG_DATA); 317 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 318 ALC_MII_DBG_DATA, val & 0xFF7F); 319 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 320 ALC_MII_DBG_ADDR, 0x3B); 321 val = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr, 322 ALC_MII_DBG_DATA); 323 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 324 ALC_MII_DBG_DATA, val | 0x0008); 325 DELAY(20); 326 break; 327 } 328 329 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 330 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 331 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 332 CSR_READ_4(sc, ALC_WOL_CFG); 333 334 CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) | 335 TWSI_CFG_SW_LD_START); 336 for (i = 100; i > 0; i--) { 337 DELAY(1000); 338 if ((CSR_READ_4(sc, ALC_TWSI_CFG) & 339 TWSI_CFG_SW_LD_START) == 0) 340 break; 341 } 342 if (i == 0) 343 printf("%s: reloading EEPROM timeout!\n", 344 sc->sc_dev.dv_xname); 345 } else { 346 if (alcdebug) 347 printf("%s: EEPROM not found!\n", sc->sc_dev.dv_xname); 348 } 349 if (eeprom != 0) { 350 switch (sc->sc_product) { 351 case PCI_PRODUCT_ATTANSIC_L1C: 352 case PCI_PRODUCT_ATTANSIC_L2C: 353 if ((opt & OPT_CFG_CLK_ENB) != 0) { 354 opt &= ~OPT_CFG_CLK_ENB; 355 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 356 CSR_READ_4(sc, ALC_OPT_CFG); 357 DELAY(1000); 358 } 359 break; 360 case PCI_PRODUCT_ATTANSIC_L1D: 361 case PCI_PRODUCT_ATTANSIC_L1D_1: 362 case PCI_PRODUCT_ATTANSIC_L2C_1: 363 case PCI_PRODUCT_ATTANSIC_L2C_2: 364 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 365 ALC_MII_DBG_ADDR, 0x00); 366 val = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr, 367 ALC_MII_DBG_DATA); 368 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 369 ALC_MII_DBG_DATA, val | 0x0080); 370 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 371 ALC_MII_DBG_ADDR, 0x3B); 372 val = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr, 373 ALC_MII_DBG_DATA); 374 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 375 ALC_MII_DBG_DATA, val & 0xFFF7); 376 DELAY(20); 377 break; 378 } 379 } 380 381 ea[0] = CSR_READ_4(sc, ALC_PAR0); 382 ea[1] = CSR_READ_4(sc, ALC_PAR1); 383 sc->alc_eaddr[0] = (ea[1] >> 8) & 0xFF; 384 sc->alc_eaddr[1] = (ea[1] >> 0) & 0xFF; 385 sc->alc_eaddr[2] = (ea[0] >> 24) & 0xFF; 386 sc->alc_eaddr[3] = (ea[0] >> 16) & 0xFF; 387 sc->alc_eaddr[4] = (ea[0] >> 8) & 0xFF; 388 sc->alc_eaddr[5] = (ea[0] >> 0) & 0xFF; 389 } 390 391 void 392 alc_disable_l0s_l1(struct alc_softc *sc) 393 { 394 uint32_t pmcfg; 395 396 /* Another magic from vendor. */ 397 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 398 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_CLK_SWH_L1 | 399 PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | PM_CFG_MAC_ASPM_CHK | 400 PM_CFG_SERDES_PD_EX_L1); 401 pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB | 402 PM_CFG_SERDES_L1_ENB; 403 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 404 } 405 406 void 407 alc_phy_reset(struct alc_softc *sc) 408 { 409 uint16_t data; 410 411 /* Reset magic from Linux. */ 412 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_SEL_ANA_RESET); 413 CSR_READ_2(sc, ALC_GPHY_CFG); 414 DELAY(10 * 1000); 415 416 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | 417 GPHY_CFG_SEL_ANA_RESET); 418 CSR_READ_2(sc, ALC_GPHY_CFG); 419 DELAY(10 * 1000); 420 421 /* DSP fixup, Vendor magic. */ 422 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1) { 423 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 424 ALC_MII_DBG_ADDR, 0x000A); 425 data = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr, 426 ALC_MII_DBG_DATA); 427 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 428 ALC_MII_DBG_DATA, data & 0xDFFF); 429 } 430 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D || 431 sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D_1 || 432 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1 || 433 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_2) { 434 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 435 ALC_MII_DBG_ADDR, 0x003B); 436 data = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr, 437 ALC_MII_DBG_DATA); 438 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 439 ALC_MII_DBG_DATA, data & 0xFFF7); 440 DELAY(20 * 1000); 441 } 442 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D) { 443 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 444 ALC_MII_DBG_ADDR, 0x0029); 445 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 446 ALC_MII_DBG_DATA, 0x929D); 447 } 448 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1C || 449 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C || 450 sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D_1 || 451 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_2) { 452 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 453 ALC_MII_DBG_ADDR, 0x0029); 454 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 455 ALC_MII_DBG_DATA, 0xB6DD); 456 } 457 458 /* Load DSP codes, vendor magic. */ 459 data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE | 460 ((1 << ANA_INTERVAL_SEL_TIMER_SHIFT) & ANA_INTERVAL_SEL_TIMER_MASK); 461 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 462 ALC_MII_DBG_ADDR, MII_ANA_CFG18); 463 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 464 ALC_MII_DBG_DATA, data); 465 466 data = ((2 << ANA_SERDES_CDR_BW_SHIFT) & ANA_SERDES_CDR_BW_MASK) | 467 ANA_SERDES_EN_DEEM | ANA_SERDES_SEL_HSP | ANA_SERDES_EN_PLL | 468 ANA_SERDES_EN_LCKDT; 469 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 470 ALC_MII_DBG_ADDR, MII_ANA_CFG5); 471 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 472 ALC_MII_DBG_DATA, data); 473 474 data = ((44 << ANA_LONG_CABLE_TH_100_SHIFT) & 475 ANA_LONG_CABLE_TH_100_MASK) | 476 ((33 << ANA_SHORT_CABLE_TH_100_SHIFT) & 477 ANA_SHORT_CABLE_TH_100_SHIFT) | 478 ANA_BP_BAD_LINK_ACCUM | ANA_BP_SMALL_BW; 479 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 480 ALC_MII_DBG_ADDR, MII_ANA_CFG54); 481 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 482 ALC_MII_DBG_DATA, data); 483 484 data = ((11 << ANA_IECHO_ADJ_3_SHIFT) & ANA_IECHO_ADJ_3_MASK) | 485 ((11 << ANA_IECHO_ADJ_2_SHIFT) & ANA_IECHO_ADJ_2_MASK) | 486 ((8 << ANA_IECHO_ADJ_1_SHIFT) & ANA_IECHO_ADJ_1_MASK) | 487 ((8 << ANA_IECHO_ADJ_0_SHIFT) & ANA_IECHO_ADJ_0_MASK); 488 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 489 ALC_MII_DBG_ADDR, MII_ANA_CFG4); 490 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 491 ALC_MII_DBG_DATA, data); 492 493 data = ((7 & ANA_MANUL_SWICH_ON_SHIFT) & ANA_MANUL_SWICH_ON_MASK) | 494 ANA_RESTART_CAL | ANA_MAN_ENABLE | ANA_SEL_HSP | ANA_EN_HB | 495 ANA_OEN_125M; 496 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 497 ALC_MII_DBG_ADDR, MII_ANA_CFG0); 498 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 499 ALC_MII_DBG_DATA, data); 500 DELAY(1000); 501 502 /* Disable hibernation. */ 503 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 504 0x0029); 505 data = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr, 506 ALC_MII_DBG_DATA); 507 data &= ~0x8000; 508 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 509 data); 510 511 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 512 0x000B); 513 data = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr, 514 ALC_MII_DBG_DATA); 515 data &= ~0x8000; 516 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 517 data); 518 } 519 520 void 521 alc_phy_down(struct alc_softc *sc) 522 { 523 switch (sc->sc_product) { 524 case PCI_PRODUCT_ATTANSIC_L1D: 525 case PCI_PRODUCT_ATTANSIC_L1D_1: 526 /* 527 * GPHY power down caused more problems on AR8151 v2.0. 528 * When driver is reloaded after GPHY power down, 529 * accesses to PHY/MAC registers hung the system. Only 530 * cold boot recovered from it. I'm not sure whether 531 * AR8151 v1.0 also requires this one though. I don't 532 * have AR8151 v1.0 controller in hand. 533 * The only option left is to isolate the PHY and 534 * initiates power down the PHY which in turn saves 535 * more power when driver is unloaded. 536 */ 537 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, 538 MII_BMCR, BMCR_ISO | BMCR_PDOWN); 539 break; 540 default: 541 /* Force PHY down. */ 542 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | 543 GPHY_CFG_SEL_ANA_RESET | GPHY_CFG_PHY_IDDQ | 544 GPHY_CFG_PWDOWN_HW); 545 DELAY(1000); 546 break; 547 } 548 } 549 550 void 551 alc_aspm(struct alc_softc *sc, uint64_t media) 552 { 553 uint32_t pmcfg; 554 uint16_t linkcfg; 555 556 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 557 if ((sc->alc_flags & (ALC_FLAG_APS | ALC_FLAG_PCIE)) == 558 (ALC_FLAG_APS | ALC_FLAG_PCIE)) 559 linkcfg = CSR_READ_2(sc, sc->alc_expcap + 560 PCI_PCIE_LCSR); 561 else 562 linkcfg = 0; 563 pmcfg &= ~PM_CFG_SERDES_PD_EX_L1; 564 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_LCKDET_TIMER_MASK); 565 pmcfg |= PM_CFG_MAC_ASPM_CHK; 566 pmcfg |= (PM_CFG_LCKDET_TIMER_DEFAULT << PM_CFG_LCKDET_TIMER_SHIFT); 567 pmcfg &= ~(PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 568 569 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 570 /* Disable extended sync except AR8152 B v1.0 */ 571 linkcfg &= ~0x80; 572 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1 && 573 sc->alc_rev == ATHEROS_AR8152_B_V10) 574 linkcfg |= 0x80; 575 CSR_WRITE_2(sc, sc->alc_expcap + PCI_PCIE_LCSR, 576 linkcfg); 577 pmcfg &= ~(PM_CFG_EN_BUFS_RX_L0S | PM_CFG_SA_DLY_ENB | 578 PM_CFG_HOTRST); 579 pmcfg |= (PM_CFG_L1_ENTRY_TIMER_DEFAULT << 580 PM_CFG_L1_ENTRY_TIMER_SHIFT); 581 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 582 pmcfg |= (PM_CFG_PM_REQ_TIMER_DEFAULT << 583 PM_CFG_PM_REQ_TIMER_SHIFT); 584 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_PCIE_RECV; 585 } 586 587 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 588 if ((sc->alc_flags & ALC_FLAG_L0S) != 0) 589 pmcfg |= PM_CFG_ASPM_L0S_ENB; 590 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 591 pmcfg |= PM_CFG_ASPM_L1_ENB; 592 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 593 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1) 594 pmcfg &= ~PM_CFG_ASPM_L0S_ENB; 595 pmcfg &= ~(PM_CFG_SERDES_L1_ENB | 596 PM_CFG_SERDES_PLL_L1_ENB | 597 PM_CFG_SERDES_BUDS_RX_L1_ENB); 598 pmcfg |= PM_CFG_CLK_SWH_L1; 599 if (media == IFM_100_TX || media == IFM_1000_T) { 600 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK; 601 switch (sc->sc_product) { 602 case PCI_PRODUCT_ATTANSIC_L2C_1: 603 pmcfg |= (7 << 604 PM_CFG_L1_ENTRY_TIMER_SHIFT); 605 break; 606 case PCI_PRODUCT_ATTANSIC_L1D_1: 607 case PCI_PRODUCT_ATTANSIC_L2C_2: 608 pmcfg |= (4 << 609 PM_CFG_L1_ENTRY_TIMER_SHIFT); 610 break; 611 default: 612 pmcfg |= (15 << 613 PM_CFG_L1_ENTRY_TIMER_SHIFT); 614 break; 615 } 616 } 617 } else { 618 pmcfg |= PM_CFG_SERDES_L1_ENB | 619 PM_CFG_SERDES_PLL_L1_ENB | 620 PM_CFG_SERDES_BUDS_RX_L1_ENB; 621 pmcfg &= ~(PM_CFG_CLK_SWH_L1 | 622 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 623 } 624 } else { 625 pmcfg &= ~(PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_L1_ENB | 626 PM_CFG_SERDES_PLL_L1_ENB); 627 pmcfg |= PM_CFG_CLK_SWH_L1; 628 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 629 pmcfg |= PM_CFG_ASPM_L1_ENB; 630 } 631 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 632 } 633 634 void 635 alc_attach(struct device *parent, struct device *self, void *aux) 636 { 637 638 struct alc_softc *sc = (struct alc_softc *)self; 639 struct pci_attach_args *pa = aux; 640 pci_chipset_tag_t pc = pa->pa_pc; 641 pci_intr_handle_t ih; 642 const char *intrstr; 643 struct ifnet *ifp; 644 pcireg_t memtype; 645 char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/L1" }; 646 uint16_t burst; 647 int base, state, error = 0; 648 uint32_t cap, ctl, val; 649 650 /* 651 * Allocate IO memory 652 */ 653 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, ALC_PCIR_BAR); 654 if (pci_mapreg_map(pa, ALC_PCIR_BAR, memtype, 0, &sc->sc_mem_bt, 655 &sc->sc_mem_bh, NULL, &sc->sc_mem_size, 0)) { 656 printf(": can't map mem space\n"); 657 return; 658 } 659 660 if (pci_intr_map_msi(pa, &ih) != 0 && pci_intr_map(pa, &ih) != 0) { 661 printf(": can't map interrupt\n"); 662 goto fail; 663 } 664 665 /* 666 * Allocate IRQ 667 */ 668 intrstr = pci_intr_string(pc, ih); 669 sc->sc_irq_handle = pci_intr_establish(pc, ih, IPL_NET, alc_intr, sc, 670 sc->sc_dev.dv_xname); 671 if (sc->sc_irq_handle == NULL) { 672 printf(": could not establish interrupt"); 673 if (intrstr != NULL) 674 printf(" at %s", intrstr); 675 printf("\n"); 676 goto fail; 677 } 678 printf(": %s", intrstr); 679 680 sc->sc_dmat = pa->pa_dmat; 681 sc->sc_pct = pa->pa_pc; 682 sc->sc_pcitag = pa->pa_tag; 683 684 /* Set PHY address. */ 685 sc->alc_phyaddr = ALC_PHY_ADDR; 686 687 /* Get PCI and chip id/revision. */ 688 sc->sc_product = PCI_PRODUCT(pa->pa_id); 689 sc->alc_rev = PCI_REVISION(pa->pa_class); 690 691 /* Initialize DMA parameters. */ 692 sc->alc_dma_rd_burst = 0; 693 sc->alc_dma_wr_burst = 0; 694 sc->alc_rcb = DMA_CFG_RCB_64; 695 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PCIEXPRESS, 696 &base, NULL)) { 697 sc->alc_flags |= ALC_FLAG_PCIE; 698 sc->alc_expcap = base; 699 burst = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 700 base + PCI_PCIE_DCSR) >> 16; 701 sc->alc_dma_rd_burst = (burst & 0x7000) >> 12; 702 sc->alc_dma_wr_burst = (burst & 0x00e0) >> 5; 703 if (alcdebug) { 704 printf("%s: Read request size : %u bytes.\n", 705 sc->sc_dev.dv_xname, 706 alc_dma_burst[sc->alc_dma_rd_burst]); 707 printf("%s: TLP payload size : %u bytes.\n", 708 sc->sc_dev.dv_xname, 709 alc_dma_burst[sc->alc_dma_wr_burst]); 710 } 711 if (alc_dma_burst[sc->alc_dma_rd_burst] > 1024) 712 sc->alc_dma_rd_burst = 3; 713 if (alc_dma_burst[sc->alc_dma_wr_burst] > 1024) 714 sc->alc_dma_wr_burst = 3; 715 /* Clear data link and flow-control protocol error. */ 716 val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV); 717 val &= ~(PEX_UNC_ERR_SEV_DLP | PEX_UNC_ERR_SEV_FCP); 718 CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val); 719 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 720 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 721 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, 722 CSR_READ_4(sc, ALC_PCIE_PHYMISC) | 723 PCIE_PHYMISC_FORCE_RCV_DET); 724 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1 && 725 sc->alc_rev == ATHEROS_AR8152_B_V10) { 726 val = CSR_READ_4(sc, ALC_PCIE_PHYMISC2); 727 val &= ~(PCIE_PHYMISC2_SERDES_CDR_MASK | 728 PCIE_PHYMISC2_SERDES_TH_MASK); 729 val |= 3 << PCIE_PHYMISC2_SERDES_CDR_SHIFT; 730 val |= 3 << PCIE_PHYMISC2_SERDES_TH_SHIFT; 731 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC2, val); 732 } 733 /* Disable ASPM L0S and L1. */ 734 cap = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 735 base + PCI_PCIE_LCAP) >> 16; 736 if ((cap & 0x00000c00) != 0) { 737 ctl = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 738 base + PCI_PCIE_LCSR) >> 16; 739 if ((ctl & 0x08) != 0) 740 sc->alc_rcb = DMA_CFG_RCB_128; 741 if (alcdebug) 742 printf("%s: RCB %u bytes\n", 743 sc->sc_dev.dv_xname, 744 sc->alc_rcb == DMA_CFG_RCB_64 ? 64 : 128); 745 state = ctl & 0x03; 746 if (state & 0x01) 747 sc->alc_flags |= ALC_FLAG_L0S; 748 if (state & 0x02) 749 sc->alc_flags |= ALC_FLAG_L1S; 750 if (alcdebug) 751 printf("%s: ASPM %s %s\n", 752 sc->sc_dev.dv_xname, 753 aspm_state[state], 754 state == 0 ? "disabled" : "enabled"); 755 alc_disable_l0s_l1(sc); 756 } 757 } 758 759 /* Reset PHY. */ 760 alc_phy_reset(sc); 761 762 /* Reset the ethernet controller. */ 763 alc_reset(sc); 764 765 /* 766 * One odd thing is AR8132 uses the same PHY hardware(F1 767 * gigabit PHY) of AR8131. So atphy(4) of AR8132 reports 768 * the PHY supports 1000Mbps but that's not true. The PHY 769 * used in AR8132 can't establish gigabit link even if it 770 * shows the same PHY model/revision number of AR8131. 771 */ 772 switch (sc->sc_product) { 773 case PCI_PRODUCT_ATTANSIC_L2C_1: 774 case PCI_PRODUCT_ATTANSIC_L2C_2: 775 sc->alc_flags |= ALC_FLAG_APS; 776 /* FALLTHROUGH */ 777 case PCI_PRODUCT_ATTANSIC_L2C: 778 sc->alc_flags |= ALC_FLAG_FASTETHER; 779 break; 780 case PCI_PRODUCT_ATTANSIC_L1D: 781 case PCI_PRODUCT_ATTANSIC_L1D_1: 782 sc->alc_flags |= ALC_FLAG_APS; 783 /* FALLTHROUGH */ 784 default: 785 break; 786 } 787 sc->alc_flags |= ALC_FLAG_ASPM_MON | ALC_FLAG_JUMBO; 788 789 switch (sc->sc_product) { 790 case PCI_PRODUCT_ATTANSIC_L1C: 791 case PCI_PRODUCT_ATTANSIC_L2C: 792 sc->alc_max_framelen = 9 * 1024; 793 break; 794 case PCI_PRODUCT_ATTANSIC_L1D: 795 case PCI_PRODUCT_ATTANSIC_L1D_1: 796 case PCI_PRODUCT_ATTANSIC_L2C_1: 797 case PCI_PRODUCT_ATTANSIC_L2C_2: 798 sc->alc_max_framelen = 6 * 1024; 799 break; 800 } 801 802 /* 803 * It seems that AR813x/AR815x has silicon bug for SMB. In 804 * addition, Atheros said that enabling SMB wouldn't improve 805 * performance. However I think it's bad to access lots of 806 * registers to extract MAC statistics. 807 */ 808 sc->alc_flags |= ALC_FLAG_SMB_BUG; 809 /* 810 * Don't use Tx CMB. It is known to have silicon bug. 811 */ 812 sc->alc_flags |= ALC_FLAG_CMB_BUG; 813 814 sc->alc_chip_rev = CSR_READ_4(sc, ALC_MASTER_CFG) >> 815 MASTER_CHIP_REV_SHIFT; 816 if (alcdebug) { 817 printf("%s: PCI device revision : 0x%04x\n", 818 sc->sc_dev.dv_xname, sc->alc_rev); 819 printf("%s: Chip id/revision : 0x%04x\n", 820 sc->sc_dev.dv_xname, sc->alc_chip_rev); 821 printf("%s: %u Tx FIFO, %u Rx FIFO\n", sc->sc_dev.dv_xname, 822 CSR_READ_4(sc, ALC_SRAM_TX_FIFO_LEN) * 8, 823 CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN) * 8); 824 } 825 826 error = alc_dma_alloc(sc); 827 if (error) 828 goto fail; 829 830 /* Load station address. */ 831 alc_get_macaddr(sc); 832 833 ifp = &sc->sc_arpcom.ac_if; 834 ifp->if_softc = sc; 835 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 836 ifp->if_ioctl = alc_ioctl; 837 ifp->if_start = alc_start; 838 ifp->if_watchdog = alc_watchdog; 839 IFQ_SET_MAXLEN(&ifp->if_snd, ALC_TX_RING_CNT - 1); 840 bcopy(sc->alc_eaddr, sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN); 841 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 842 843 ifp->if_capabilities = IFCAP_VLAN_MTU; 844 845 #ifdef ALC_CHECKSUM 846 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 847 IFCAP_CSUM_UDPv4; 848 #endif 849 850 #if NVLAN > 0 851 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 852 #endif 853 854 printf(", address %s\n", ether_sprintf(sc->sc_arpcom.ac_enaddr)); 855 856 /* Set up MII bus. */ 857 sc->sc_miibus.mii_ifp = ifp; 858 sc->sc_miibus.mii_readreg = alc_miibus_readreg; 859 sc->sc_miibus.mii_writereg = alc_miibus_writereg; 860 sc->sc_miibus.mii_statchg = alc_miibus_statchg; 861 862 ifmedia_init(&sc->sc_miibus.mii_media, 0, alc_mediachange, 863 alc_mediastatus); 864 mii_attach(self, &sc->sc_miibus, 0xffffffff, MII_PHY_ANY, 865 MII_OFFSET_ANY, MIIF_DOPAUSE); 866 867 if (LIST_FIRST(&sc->sc_miibus.mii_phys) == NULL) { 868 printf("%s: no PHY found!\n", sc->sc_dev.dv_xname); 869 ifmedia_add(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL, 870 0, NULL); 871 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL); 872 } else 873 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_AUTO); 874 875 if_attach(ifp); 876 ether_ifattach(ifp); 877 878 timeout_set(&sc->alc_tick_ch, alc_tick, sc); 879 880 return; 881 fail: 882 alc_dma_free(sc); 883 if (sc->sc_irq_handle != NULL) 884 pci_intr_disestablish(pc, sc->sc_irq_handle); 885 if (sc->sc_mem_size) 886 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 887 } 888 889 int 890 alc_detach(struct device *self, int flags) 891 { 892 struct alc_softc *sc = (struct alc_softc *)self; 893 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 894 int s; 895 896 s = splnet(); 897 alc_stop(sc); 898 splx(s); 899 900 mii_detach(&sc->sc_miibus, MII_PHY_ANY, MII_OFFSET_ANY); 901 902 /* Delete all remaining media. */ 903 ifmedia_delete_instance(&sc->sc_miibus.mii_media, IFM_INST_ANY); 904 905 ether_ifdetach(ifp); 906 if_detach(ifp); 907 alc_dma_free(sc); 908 909 alc_phy_down(sc); 910 if (sc->sc_irq_handle != NULL) { 911 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 912 sc->sc_irq_handle = NULL; 913 } 914 915 return (0); 916 } 917 918 int 919 alc_activate(struct device *self, int act) 920 { 921 struct alc_softc *sc = (struct alc_softc *)self; 922 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 923 int rv = 0; 924 925 switch (act) { 926 case DVACT_SUSPEND: 927 if (ifp->if_flags & IFF_RUNNING) 928 alc_stop(sc); 929 rv = config_activate_children(self, act); 930 break; 931 case DVACT_RESUME: 932 if (ifp->if_flags & IFF_UP) 933 alc_init(ifp); 934 break; 935 default: 936 rv = config_activate_children(self, act); 937 break; 938 } 939 return (rv); 940 } 941 942 int 943 alc_dma_alloc(struct alc_softc *sc) 944 { 945 struct alc_txdesc *txd; 946 struct alc_rxdesc *rxd; 947 int nsegs, error, i; 948 949 /* 950 * Create DMA stuffs for TX ring 951 */ 952 error = bus_dmamap_create(sc->sc_dmat, ALC_TX_RING_SZ, 1, 953 ALC_TX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->alc_cdata.alc_tx_ring_map); 954 if (error) 955 return (ENOBUFS); 956 957 /* Allocate DMA'able memory for TX ring */ 958 error = bus_dmamem_alloc(sc->sc_dmat, ALC_TX_RING_SZ, 959 ETHER_ALIGN, 0, &sc->alc_rdata.alc_tx_ring_seg, 1, 960 &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 961 if (error) { 962 printf("%s: could not allocate DMA'able memory for Tx ring.\n", 963 sc->sc_dev.dv_xname); 964 return error; 965 } 966 967 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_tx_ring_seg, 968 nsegs, ALC_TX_RING_SZ, (caddr_t *)&sc->alc_rdata.alc_tx_ring, 969 BUS_DMA_NOWAIT); 970 if (error) 971 return (ENOBUFS); 972 973 /* Load the DMA map for Tx ring. */ 974 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 975 sc->alc_rdata.alc_tx_ring, ALC_TX_RING_SZ, NULL, BUS_DMA_WAITOK); 976 if (error) { 977 printf("%s: could not load DMA'able memory for Tx ring.\n", 978 sc->sc_dev.dv_xname); 979 bus_dmamem_free(sc->sc_dmat, 980 (bus_dma_segment_t *)&sc->alc_rdata.alc_tx_ring, 1); 981 return error; 982 } 983 984 sc->alc_rdata.alc_tx_ring_paddr = 985 sc->alc_cdata.alc_tx_ring_map->dm_segs[0].ds_addr; 986 987 /* 988 * Create DMA stuffs for RX ring 989 */ 990 error = bus_dmamap_create(sc->sc_dmat, ALC_RX_RING_SZ, 1, 991 ALC_RX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->alc_cdata.alc_rx_ring_map); 992 if (error) 993 return (ENOBUFS); 994 995 /* Allocate DMA'able memory for RX ring */ 996 error = bus_dmamem_alloc(sc->sc_dmat, ALC_RX_RING_SZ, 997 ETHER_ALIGN, 0, &sc->alc_rdata.alc_rx_ring_seg, 1, 998 &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 999 if (error) { 1000 printf("%s: could not allocate DMA'able memory for Rx ring.\n", 1001 sc->sc_dev.dv_xname); 1002 return error; 1003 } 1004 1005 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_rx_ring_seg, 1006 nsegs, ALC_RX_RING_SZ, (caddr_t *)&sc->alc_rdata.alc_rx_ring, 1007 BUS_DMA_NOWAIT); 1008 if (error) 1009 return (ENOBUFS); 1010 1011 /* Load the DMA map for Rx ring. */ 1012 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 1013 sc->alc_rdata.alc_rx_ring, ALC_RX_RING_SZ, NULL, BUS_DMA_WAITOK); 1014 if (error) { 1015 printf("%s: could not load DMA'able memory for Rx ring.\n", 1016 sc->sc_dev.dv_xname); 1017 bus_dmamem_free(sc->sc_dmat, 1018 (bus_dma_segment_t *)sc->alc_rdata.alc_rx_ring, 1); 1019 return error; 1020 } 1021 1022 sc->alc_rdata.alc_rx_ring_paddr = 1023 sc->alc_cdata.alc_rx_ring_map->dm_segs[0].ds_addr; 1024 1025 /* 1026 * Create DMA stuffs for RX return ring 1027 */ 1028 error = bus_dmamap_create(sc->sc_dmat, ALC_RR_RING_SZ, 1, 1029 ALC_RR_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->alc_cdata.alc_rr_ring_map); 1030 if (error) 1031 return (ENOBUFS); 1032 1033 /* Allocate DMA'able memory for RX return ring */ 1034 error = bus_dmamem_alloc(sc->sc_dmat, ALC_RR_RING_SZ, 1035 ETHER_ALIGN, 0, &sc->alc_rdata.alc_rr_ring_seg, 1, 1036 &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 1037 if (error) { 1038 printf("%s: could not allocate DMA'able memory for Rx " 1039 "return ring.\n", sc->sc_dev.dv_xname); 1040 return error; 1041 } 1042 1043 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_rr_ring_seg, 1044 nsegs, ALC_RR_RING_SZ, (caddr_t *)&sc->alc_rdata.alc_rr_ring, 1045 BUS_DMA_NOWAIT); 1046 if (error) 1047 return (ENOBUFS); 1048 1049 /* Load the DMA map for Rx return ring. */ 1050 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 1051 sc->alc_rdata.alc_rr_ring, ALC_RR_RING_SZ, NULL, BUS_DMA_WAITOK); 1052 if (error) { 1053 printf("%s: could not load DMA'able memory for Rx return ring." 1054 "\n", sc->sc_dev.dv_xname); 1055 bus_dmamem_free(sc->sc_dmat, 1056 (bus_dma_segment_t *)&sc->alc_rdata.alc_rr_ring, 1); 1057 return error; 1058 } 1059 1060 sc->alc_rdata.alc_rr_ring_paddr = 1061 sc->alc_cdata.alc_rr_ring_map->dm_segs[0].ds_addr; 1062 1063 /* 1064 * Create DMA stuffs for CMB block 1065 */ 1066 error = bus_dmamap_create(sc->sc_dmat, ALC_CMB_SZ, 1, 1067 ALC_CMB_SZ, 0, BUS_DMA_NOWAIT, 1068 &sc->alc_cdata.alc_cmb_map); 1069 if (error) 1070 return (ENOBUFS); 1071 1072 /* Allocate DMA'able memory for CMB block */ 1073 error = bus_dmamem_alloc(sc->sc_dmat, ALC_CMB_SZ, 1074 ETHER_ALIGN, 0, &sc->alc_rdata.alc_cmb_seg, 1, 1075 &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 1076 if (error) { 1077 printf("%s: could not allocate DMA'able memory for " 1078 "CMB block\n", sc->sc_dev.dv_xname); 1079 return error; 1080 } 1081 1082 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_cmb_seg, 1083 nsegs, ALC_CMB_SZ, (caddr_t *)&sc->alc_rdata.alc_cmb, 1084 BUS_DMA_NOWAIT); 1085 if (error) 1086 return (ENOBUFS); 1087 1088 /* Load the DMA map for CMB block. */ 1089 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 1090 sc->alc_rdata.alc_cmb, ALC_CMB_SZ, NULL, 1091 BUS_DMA_WAITOK); 1092 if (error) { 1093 printf("%s: could not load DMA'able memory for CMB block\n", 1094 sc->sc_dev.dv_xname); 1095 bus_dmamem_free(sc->sc_dmat, 1096 (bus_dma_segment_t *)&sc->alc_rdata.alc_cmb, 1); 1097 return error; 1098 } 1099 1100 sc->alc_rdata.alc_cmb_paddr = 1101 sc->alc_cdata.alc_cmb_map->dm_segs[0].ds_addr; 1102 1103 /* 1104 * Create DMA stuffs for SMB block 1105 */ 1106 error = bus_dmamap_create(sc->sc_dmat, ALC_SMB_SZ, 1, 1107 ALC_SMB_SZ, 0, BUS_DMA_NOWAIT, 1108 &sc->alc_cdata.alc_smb_map); 1109 if (error) 1110 return (ENOBUFS); 1111 1112 /* Allocate DMA'able memory for SMB block */ 1113 error = bus_dmamem_alloc(sc->sc_dmat, ALC_SMB_SZ, 1114 ETHER_ALIGN, 0, &sc->alc_rdata.alc_smb_seg, 1, 1115 &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 1116 if (error) { 1117 printf("%s: could not allocate DMA'able memory for " 1118 "SMB block\n", sc->sc_dev.dv_xname); 1119 return error; 1120 } 1121 1122 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_smb_seg, 1123 nsegs, ALC_SMB_SZ, (caddr_t *)&sc->alc_rdata.alc_smb, 1124 BUS_DMA_NOWAIT); 1125 if (error) 1126 return (ENOBUFS); 1127 1128 /* Load the DMA map for SMB block */ 1129 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 1130 sc->alc_rdata.alc_smb, ALC_SMB_SZ, NULL, 1131 BUS_DMA_WAITOK); 1132 if (error) { 1133 printf("%s: could not load DMA'able memory for SMB block\n", 1134 sc->sc_dev.dv_xname); 1135 bus_dmamem_free(sc->sc_dmat, 1136 (bus_dma_segment_t *)&sc->alc_rdata.alc_smb, 1); 1137 return error; 1138 } 1139 1140 sc->alc_rdata.alc_smb_paddr = 1141 sc->alc_cdata.alc_smb_map->dm_segs[0].ds_addr; 1142 1143 1144 /* Create DMA maps for Tx buffers. */ 1145 for (i = 0; i < ALC_TX_RING_CNT; i++) { 1146 txd = &sc->alc_cdata.alc_txdesc[i]; 1147 txd->tx_m = NULL; 1148 txd->tx_dmamap = NULL; 1149 error = bus_dmamap_create(sc->sc_dmat, ALC_TSO_MAXSIZE, 1150 ALC_MAXTXSEGS, ALC_TSO_MAXSEGSIZE, 0, BUS_DMA_NOWAIT, 1151 &txd->tx_dmamap); 1152 if (error) { 1153 printf("%s: could not create Tx dmamap.\n", 1154 sc->sc_dev.dv_xname); 1155 return error; 1156 } 1157 } 1158 1159 /* Create DMA maps for Rx buffers. */ 1160 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 1161 BUS_DMA_NOWAIT, &sc->alc_cdata.alc_rx_sparemap); 1162 if (error) { 1163 printf("%s: could not create spare Rx dmamap.\n", 1164 sc->sc_dev.dv_xname); 1165 return error; 1166 } 1167 1168 for (i = 0; i < ALC_RX_RING_CNT; i++) { 1169 rxd = &sc->alc_cdata.alc_rxdesc[i]; 1170 rxd->rx_m = NULL; 1171 rxd->rx_dmamap = NULL; 1172 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1173 MCLBYTES, 0, BUS_DMA_NOWAIT, &rxd->rx_dmamap); 1174 if (error) { 1175 printf("%s: could not create Rx dmamap.\n", 1176 sc->sc_dev.dv_xname); 1177 return error; 1178 } 1179 } 1180 1181 return (0); 1182 } 1183 1184 1185 void 1186 alc_dma_free(struct alc_softc *sc) 1187 { 1188 struct alc_txdesc *txd; 1189 struct alc_rxdesc *rxd; 1190 int i; 1191 1192 /* Tx buffers */ 1193 for (i = 0; i < ALC_TX_RING_CNT; i++) { 1194 txd = &sc->alc_cdata.alc_txdesc[i]; 1195 if (txd->tx_dmamap != NULL) { 1196 bus_dmamap_destroy(sc->sc_dmat, txd->tx_dmamap); 1197 txd->tx_dmamap = NULL; 1198 } 1199 } 1200 /* Rx buffers */ 1201 for (i = 0; i < ALC_RX_RING_CNT; i++) { 1202 rxd = &sc->alc_cdata.alc_rxdesc[i]; 1203 if (rxd->rx_dmamap != NULL) { 1204 bus_dmamap_destroy(sc->sc_dmat, rxd->rx_dmamap); 1205 rxd->rx_dmamap = NULL; 1206 } 1207 } 1208 if (sc->alc_cdata.alc_rx_sparemap != NULL) { 1209 bus_dmamap_destroy(sc->sc_dmat, sc->alc_cdata.alc_rx_sparemap); 1210 sc->alc_cdata.alc_rx_sparemap = NULL; 1211 } 1212 1213 /* Tx ring. */ 1214 if (sc->alc_cdata.alc_tx_ring_map != NULL) 1215 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map); 1216 if (sc->alc_cdata.alc_tx_ring_map != NULL && 1217 sc->alc_rdata.alc_tx_ring != NULL) 1218 bus_dmamem_free(sc->sc_dmat, 1219 (bus_dma_segment_t *)sc->alc_rdata.alc_tx_ring, 1); 1220 sc->alc_rdata.alc_tx_ring = NULL; 1221 sc->alc_cdata.alc_tx_ring_map = NULL; 1222 1223 /* Rx ring. */ 1224 if (sc->alc_cdata.alc_rx_ring_map != NULL) 1225 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map); 1226 if (sc->alc_cdata.alc_rx_ring_map != NULL && 1227 sc->alc_rdata.alc_rx_ring != NULL) 1228 bus_dmamem_free(sc->sc_dmat, 1229 (bus_dma_segment_t *)sc->alc_rdata.alc_rx_ring, 1); 1230 sc->alc_rdata.alc_rx_ring = NULL; 1231 sc->alc_cdata.alc_rx_ring_map = NULL; 1232 1233 /* Rx return ring. */ 1234 if (sc->alc_cdata.alc_rr_ring_map != NULL) 1235 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map); 1236 if (sc->alc_cdata.alc_rr_ring_map != NULL && 1237 sc->alc_rdata.alc_rr_ring != NULL) 1238 bus_dmamem_free(sc->sc_dmat, 1239 (bus_dma_segment_t *)sc->alc_rdata.alc_rr_ring, 1); 1240 sc->alc_rdata.alc_rr_ring = NULL; 1241 sc->alc_cdata.alc_rr_ring_map = NULL; 1242 1243 /* CMB block */ 1244 if (sc->alc_cdata.alc_cmb_map != NULL) 1245 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_cmb_map); 1246 if (sc->alc_cdata.alc_cmb_map != NULL && 1247 sc->alc_rdata.alc_cmb != NULL) 1248 bus_dmamem_free(sc->sc_dmat, 1249 (bus_dma_segment_t *)sc->alc_rdata.alc_cmb, 1); 1250 sc->alc_rdata.alc_cmb = NULL; 1251 sc->alc_cdata.alc_cmb_map = NULL; 1252 1253 /* SMB block */ 1254 if (sc->alc_cdata.alc_smb_map != NULL) 1255 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_smb_map); 1256 if (sc->alc_cdata.alc_smb_map != NULL && 1257 sc->alc_rdata.alc_smb != NULL) 1258 bus_dmamem_free(sc->sc_dmat, 1259 (bus_dma_segment_t *)sc->alc_rdata.alc_smb, 1); 1260 sc->alc_rdata.alc_smb = NULL; 1261 sc->alc_cdata.alc_smb_map = NULL; 1262 } 1263 1264 int 1265 alc_encap(struct alc_softc *sc, struct mbuf *m) 1266 { 1267 struct alc_txdesc *txd, *txd_last; 1268 struct tx_desc *desc; 1269 bus_dmamap_t map; 1270 uint32_t cflags, poff, vtag; 1271 int error, idx, prod; 1272 1273 cflags = vtag = 0; 1274 poff = 0; 1275 1276 prod = sc->alc_cdata.alc_tx_prod; 1277 txd = &sc->alc_cdata.alc_txdesc[prod]; 1278 txd_last = txd; 1279 map = txd->tx_dmamap; 1280 1281 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, BUS_DMA_NOWAIT); 1282 if (error != 0 && error != EFBIG) 1283 goto drop; 1284 if (error != 0) { 1285 if (m_defrag(m, M_DONTWAIT)) { 1286 error = ENOBUFS; 1287 goto drop; 1288 } 1289 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1290 BUS_DMA_NOWAIT); 1291 if (error != 0) 1292 goto drop; 1293 } 1294 1295 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1296 BUS_DMASYNC_PREWRITE); 1297 1298 desc = NULL; 1299 idx = 0; 1300 #if NVLAN > 0 1301 /* Configure VLAN hardware tag insertion. */ 1302 if (m->m_flags & M_VLANTAG) { 1303 vtag = htons(m->m_pkthdr.ether_vtag); 1304 vtag = (vtag << TD_VLAN_SHIFT) & TD_VLAN_MASK; 1305 cflags |= TD_INS_VLAN_TAG; 1306 } 1307 #endif 1308 /* Configure Tx checksum offload. */ 1309 if ((m->m_pkthdr.csum_flags & ALC_CSUM_FEATURES) != 0) { 1310 cflags |= TD_CUSTOM_CSUM; 1311 /* Set checksum start offset. */ 1312 cflags |= ((poff >> 1) << TD_PLOAD_OFFSET_SHIFT) & 1313 TD_PLOAD_OFFSET_MASK; 1314 } 1315 1316 for (; idx < map->dm_nsegs; idx++) { 1317 desc = &sc->alc_rdata.alc_tx_ring[prod]; 1318 desc->len = 1319 htole32(TX_BYTES(map->dm_segs[idx].ds_len) | vtag); 1320 desc->flags = htole32(cflags); 1321 desc->addr = htole64(map->dm_segs[idx].ds_addr); 1322 sc->alc_cdata.alc_tx_cnt++; 1323 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 1324 } 1325 1326 /* Update producer index. */ 1327 sc->alc_cdata.alc_tx_prod = prod; 1328 1329 /* Finally set EOP on the last descriptor. */ 1330 prod = (prod + ALC_TX_RING_CNT - 1) % ALC_TX_RING_CNT; 1331 desc = &sc->alc_rdata.alc_tx_ring[prod]; 1332 desc->flags |= htole32(TD_EOP); 1333 1334 /* Swap dmamap of the first and the last. */ 1335 txd = &sc->alc_cdata.alc_txdesc[prod]; 1336 map = txd_last->tx_dmamap; 1337 txd_last->tx_dmamap = txd->tx_dmamap; 1338 txd->tx_dmamap = map; 1339 txd->tx_m = m; 1340 1341 return (0); 1342 1343 drop: 1344 m_freem(m); 1345 return (error); 1346 } 1347 1348 void 1349 alc_start(struct ifnet *ifp) 1350 { 1351 struct alc_softc *sc = ifp->if_softc; 1352 struct mbuf *m; 1353 int enq = 0; 1354 1355 /* Reclaim transmitted frames. */ 1356 if (sc->alc_cdata.alc_tx_cnt >= ALC_TX_DESC_HIWAT) 1357 alc_txeof(sc); 1358 1359 if (!(ifp->if_flags & IFF_RUNNING) || ifq_is_oactive(&ifp->if_snd)) 1360 return; 1361 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) 1362 return; 1363 if (IFQ_IS_EMPTY(&ifp->if_snd)) 1364 return; 1365 1366 for (;;) { 1367 if (sc->alc_cdata.alc_tx_cnt + ALC_MAXTXSEGS >= 1368 ALC_TX_RING_CNT - 3) { 1369 ifq_set_oactive(&ifp->if_snd); 1370 break; 1371 } 1372 1373 IFQ_DEQUEUE(&ifp->if_snd, m); 1374 if (m == NULL) 1375 break; 1376 1377 if (alc_encap(sc, m) != 0) { 1378 ifp->if_oerrors++; 1379 continue; 1380 } 1381 enq++; 1382 1383 #if NBPFILTER > 0 1384 /* 1385 * If there's a BPF listener, bounce a copy of this frame 1386 * to him. 1387 */ 1388 if (ifp->if_bpf != NULL) 1389 bpf_mtap_ether(ifp->if_bpf, m, BPF_DIRECTION_OUT); 1390 #endif 1391 } 1392 1393 if (enq > 0) { 1394 /* Sync descriptors. */ 1395 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0, 1396 sc->alc_cdata.alc_tx_ring_map->dm_mapsize, 1397 BUS_DMASYNC_PREWRITE); 1398 /* Kick. Assume we're using normal Tx priority queue. */ 1399 CSR_WRITE_4(sc, ALC_MBOX_TD_PROD_IDX, 1400 (sc->alc_cdata.alc_tx_prod << 1401 MBOX_TD_PROD_LO_IDX_SHIFT) & 1402 MBOX_TD_PROD_LO_IDX_MASK); 1403 /* Set a timeout in case the chip goes out to lunch. */ 1404 ifp->if_timer = ALC_TX_TIMEOUT; 1405 } 1406 } 1407 1408 void 1409 alc_watchdog(struct ifnet *ifp) 1410 { 1411 struct alc_softc *sc = ifp->if_softc; 1412 1413 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) { 1414 printf("%s: watchdog timeout (missed link)\n", 1415 sc->sc_dev.dv_xname); 1416 ifp->if_oerrors++; 1417 alc_init(ifp); 1418 return; 1419 } 1420 1421 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 1422 ifp->if_oerrors++; 1423 alc_init(ifp); 1424 alc_start(ifp); 1425 } 1426 1427 int 1428 alc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1429 { 1430 struct alc_softc *sc = ifp->if_softc; 1431 struct mii_data *mii = &sc->sc_miibus; 1432 struct ifreq *ifr = (struct ifreq *)data; 1433 int s, error = 0; 1434 1435 s = splnet(); 1436 1437 switch (cmd) { 1438 case SIOCSIFADDR: 1439 ifp->if_flags |= IFF_UP; 1440 if (!(ifp->if_flags & IFF_RUNNING)) 1441 alc_init(ifp); 1442 break; 1443 1444 case SIOCSIFFLAGS: 1445 if (ifp->if_flags & IFF_UP) { 1446 if (ifp->if_flags & IFF_RUNNING) 1447 error = ENETRESET; 1448 else 1449 alc_init(ifp); 1450 } else { 1451 if (ifp->if_flags & IFF_RUNNING) 1452 alc_stop(sc); 1453 } 1454 break; 1455 1456 case SIOCSIFMEDIA: 1457 case SIOCGIFMEDIA: 1458 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1459 break; 1460 1461 default: 1462 error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data); 1463 break; 1464 } 1465 1466 if (error == ENETRESET) { 1467 if (ifp->if_flags & IFF_RUNNING) 1468 alc_iff(sc); 1469 error = 0; 1470 } 1471 1472 splx(s); 1473 return (error); 1474 } 1475 1476 void 1477 alc_mac_config(struct alc_softc *sc) 1478 { 1479 struct mii_data *mii; 1480 uint32_t reg; 1481 1482 mii = &sc->sc_miibus; 1483 reg = CSR_READ_4(sc, ALC_MAC_CFG); 1484 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 1485 MAC_CFG_SPEED_MASK); 1486 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D || 1487 sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D_1 || 1488 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_2) 1489 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 1490 /* Reprogram MAC with resolved speed/duplex. */ 1491 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1492 case IFM_10_T: 1493 case IFM_100_TX: 1494 reg |= MAC_CFG_SPEED_10_100; 1495 break; 1496 case IFM_1000_T: 1497 reg |= MAC_CFG_SPEED_1000; 1498 break; 1499 } 1500 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1501 reg |= MAC_CFG_FULL_DUPLEX; 1502 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1503 reg |= MAC_CFG_TX_FC; 1504 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1505 reg |= MAC_CFG_RX_FC; 1506 } 1507 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 1508 } 1509 1510 void 1511 alc_stats_clear(struct alc_softc *sc) 1512 { 1513 struct smb sb, *smb; 1514 uint32_t *reg; 1515 int i; 1516 1517 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 1518 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 1519 sc->alc_cdata.alc_smb_map->dm_mapsize, 1520 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1521 smb = sc->alc_rdata.alc_smb; 1522 /* Update done, clear. */ 1523 smb->updated = 0; 1524 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 1525 sc->alc_cdata.alc_smb_map->dm_mapsize, 1526 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1527 } else { 1528 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 1529 reg++) { 1530 CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 1531 i += sizeof(uint32_t); 1532 } 1533 /* Read Tx statistics. */ 1534 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 1535 reg++) { 1536 CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 1537 i += sizeof(uint32_t); 1538 } 1539 } 1540 } 1541 1542 void 1543 alc_stats_update(struct alc_softc *sc) 1544 { 1545 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1546 struct alc_hw_stats *stat; 1547 struct smb sb, *smb; 1548 uint32_t *reg; 1549 int i; 1550 1551 stat = &sc->alc_stats; 1552 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 1553 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 1554 sc->alc_cdata.alc_smb_map->dm_mapsize, 1555 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1556 smb = sc->alc_rdata.alc_smb; 1557 if (smb->updated == 0) 1558 return; 1559 } else { 1560 smb = &sb; 1561 /* Read Rx statistics. */ 1562 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 1563 reg++) { 1564 *reg = CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 1565 i += sizeof(uint32_t); 1566 } 1567 /* Read Tx statistics. */ 1568 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 1569 reg++) { 1570 *reg = CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 1571 i += sizeof(uint32_t); 1572 } 1573 } 1574 1575 /* Rx stats. */ 1576 stat->rx_frames += smb->rx_frames; 1577 stat->rx_bcast_frames += smb->rx_bcast_frames; 1578 stat->rx_mcast_frames += smb->rx_mcast_frames; 1579 stat->rx_pause_frames += smb->rx_pause_frames; 1580 stat->rx_control_frames += smb->rx_control_frames; 1581 stat->rx_crcerrs += smb->rx_crcerrs; 1582 stat->rx_lenerrs += smb->rx_lenerrs; 1583 stat->rx_bytes += smb->rx_bytes; 1584 stat->rx_runts += smb->rx_runts; 1585 stat->rx_fragments += smb->rx_fragments; 1586 stat->rx_pkts_64 += smb->rx_pkts_64; 1587 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 1588 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 1589 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 1590 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 1591 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 1592 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 1593 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 1594 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 1595 stat->rx_rrs_errs += smb->rx_rrs_errs; 1596 stat->rx_alignerrs += smb->rx_alignerrs; 1597 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 1598 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 1599 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 1600 1601 /* Tx stats. */ 1602 stat->tx_frames += smb->tx_frames; 1603 stat->tx_bcast_frames += smb->tx_bcast_frames; 1604 stat->tx_mcast_frames += smb->tx_mcast_frames; 1605 stat->tx_pause_frames += smb->tx_pause_frames; 1606 stat->tx_excess_defer += smb->tx_excess_defer; 1607 stat->tx_control_frames += smb->tx_control_frames; 1608 stat->tx_deferred += smb->tx_deferred; 1609 stat->tx_bytes += smb->tx_bytes; 1610 stat->tx_pkts_64 += smb->tx_pkts_64; 1611 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 1612 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 1613 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 1614 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 1615 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 1616 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 1617 stat->tx_single_colls += smb->tx_single_colls; 1618 stat->tx_multi_colls += smb->tx_multi_colls; 1619 stat->tx_late_colls += smb->tx_late_colls; 1620 stat->tx_excess_colls += smb->tx_excess_colls; 1621 stat->tx_underrun += smb->tx_underrun; 1622 stat->tx_desc_underrun += smb->tx_desc_underrun; 1623 stat->tx_lenerrs += smb->tx_lenerrs; 1624 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 1625 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 1626 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 1627 1628 ifp->if_collisions += smb->tx_single_colls + 1629 smb->tx_multi_colls * 2 + smb->tx_late_colls + 1630 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT; 1631 1632 ifp->if_oerrors += smb->tx_late_colls + smb->tx_excess_colls + 1633 smb->tx_underrun + smb->tx_pkts_truncated; 1634 1635 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 1636 smb->rx_runts + smb->rx_pkts_truncated + 1637 smb->rx_fifo_oflows + smb->rx_rrs_errs + 1638 smb->rx_alignerrs; 1639 1640 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 1641 /* Update done, clear. */ 1642 smb->updated = 0; 1643 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 1644 sc->alc_cdata.alc_smb_map->dm_mapsize, 1645 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1646 } 1647 } 1648 1649 int 1650 alc_intr(void *arg) 1651 { 1652 struct alc_softc *sc = arg; 1653 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1654 uint32_t status; 1655 int claimed = 0; 1656 1657 status = CSR_READ_4(sc, ALC_INTR_STATUS); 1658 if ((status & ALC_INTRS) == 0) 1659 return (0); 1660 1661 /* Disable interrupts. */ 1662 CSR_WRITE_4(sc, ALC_INTR_STATUS, INTR_DIS_INT); 1663 1664 status = CSR_READ_4(sc, ALC_INTR_STATUS); 1665 if ((status & ALC_INTRS) == 0) 1666 goto back; 1667 1668 /* Acknowledge and disable interrupts. */ 1669 CSR_WRITE_4(sc, ALC_INTR_STATUS, status | INTR_DIS_INT); 1670 1671 if (ifp->if_flags & IFF_RUNNING) { 1672 if (status & INTR_RX_PKT) 1673 alc_rxintr(sc); 1674 1675 if (status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | 1676 INTR_TXQ_TO_RST)) { 1677 if (status & INTR_DMA_RD_TO_RST) 1678 printf("%s: DMA read error! -- resetting\n", 1679 sc->sc_dev.dv_xname); 1680 if (status & INTR_DMA_WR_TO_RST) 1681 printf("%s: DMA write error! -- resetting\n", 1682 sc->sc_dev.dv_xname); 1683 if (status & INTR_TXQ_TO_RST) 1684 printf("%s: TxQ reset! -- resetting\n", 1685 sc->sc_dev.dv_xname); 1686 alc_init(ifp); 1687 return (0); 1688 } 1689 1690 if (status & INTR_TX_PKT) 1691 alc_txeof(sc); 1692 1693 alc_start(ifp); 1694 } 1695 1696 claimed = 1; 1697 back: 1698 /* Re-enable interrupts. */ 1699 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0x7FFFFFFF); 1700 return (claimed); 1701 } 1702 1703 void 1704 alc_txeof(struct alc_softc *sc) 1705 { 1706 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1707 struct alc_txdesc *txd; 1708 uint32_t cons, prod; 1709 int prog; 1710 1711 if (sc->alc_cdata.alc_tx_cnt == 0) 1712 return; 1713 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0, 1714 sc->alc_cdata.alc_tx_ring_map->dm_mapsize, 1715 BUS_DMASYNC_POSTWRITE); 1716 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 1717 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0, 1718 sc->alc_cdata.alc_cmb_map->dm_mapsize, 1719 BUS_DMASYNC_POSTREAD); 1720 prod = sc->alc_rdata.alc_cmb->cons; 1721 } else 1722 prod = CSR_READ_4(sc, ALC_MBOX_TD_CONS_IDX); 1723 /* Assume we're using normal Tx priority queue. */ 1724 prod = (prod & MBOX_TD_CONS_LO_IDX_MASK) >> 1725 MBOX_TD_CONS_LO_IDX_SHIFT; 1726 cons = sc->alc_cdata.alc_tx_cons; 1727 /* 1728 * Go through our Tx list and free mbufs for those 1729 * frames which have been transmitted. 1730 */ 1731 for (prog = 0; cons != prod; prog++, 1732 ALC_DESC_INC(cons, ALC_TX_RING_CNT)) { 1733 if (sc->alc_cdata.alc_tx_cnt <= 0) 1734 break; 1735 prog++; 1736 ifq_clr_oactive(&ifp->if_snd); 1737 sc->alc_cdata.alc_tx_cnt--; 1738 txd = &sc->alc_cdata.alc_txdesc[cons]; 1739 if (txd->tx_m != NULL) { 1740 /* Reclaim transmitted mbufs. */ 1741 bus_dmamap_sync(sc->sc_dmat, txd->tx_dmamap, 0, 1742 txd->tx_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1743 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1744 m_freem(txd->tx_m); 1745 txd->tx_m = NULL; 1746 } 1747 } 1748 1749 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 1750 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0, 1751 sc->alc_cdata.alc_cmb_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1752 sc->alc_cdata.alc_tx_cons = cons; 1753 /* 1754 * Unarm watchdog timer only when there is no pending 1755 * frames in Tx queue. 1756 */ 1757 if (sc->alc_cdata.alc_tx_cnt == 0) 1758 ifp->if_timer = 0; 1759 } 1760 1761 int 1762 alc_newbuf(struct alc_softc *sc, struct alc_rxdesc *rxd) 1763 { 1764 struct mbuf *m; 1765 bus_dmamap_t map; 1766 int error; 1767 1768 MGETHDR(m, M_DONTWAIT, MT_DATA); 1769 if (m == NULL) 1770 return (ENOBUFS); 1771 MCLGET(m, M_DONTWAIT); 1772 if (!(m->m_flags & M_EXT)) { 1773 m_freem(m); 1774 return (ENOBUFS); 1775 } 1776 1777 m->m_len = m->m_pkthdr.len = RX_BUF_SIZE_MAX; 1778 1779 error = bus_dmamap_load_mbuf(sc->sc_dmat, 1780 sc->alc_cdata.alc_rx_sparemap, m, BUS_DMA_NOWAIT); 1781 1782 if (error != 0) { 1783 m_freem(m); 1784 printf("%s: can't load RX mbuf\n", sc->sc_dev.dv_xname); 1785 return (error); 1786 } 1787 1788 if (rxd->rx_m != NULL) { 1789 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0, 1790 rxd->rx_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1791 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 1792 } 1793 map = rxd->rx_dmamap; 1794 rxd->rx_dmamap = sc->alc_cdata.alc_rx_sparemap; 1795 sc->alc_cdata.alc_rx_sparemap = map; 1796 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0, rxd->rx_dmamap->dm_mapsize, 1797 BUS_DMASYNC_PREREAD); 1798 rxd->rx_m = m; 1799 rxd->rx_desc->addr = htole64(rxd->rx_dmamap->dm_segs[0].ds_addr); 1800 return (0); 1801 } 1802 1803 void 1804 alc_rxintr(struct alc_softc *sc) 1805 { 1806 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1807 struct rx_rdesc *rrd; 1808 uint32_t nsegs, status; 1809 int rr_cons, prog; 1810 1811 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 0, 1812 sc->alc_cdata.alc_rr_ring_map->dm_mapsize, 1813 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1814 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 0, 1815 sc->alc_cdata.alc_rx_ring_map->dm_mapsize, 1816 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1817 rr_cons = sc->alc_cdata.alc_rr_cons; 1818 for (prog = 0; (ifp->if_flags & IFF_RUNNING) != 0;) { 1819 rrd = &sc->alc_rdata.alc_rr_ring[rr_cons]; 1820 status = letoh32(rrd->status); 1821 if ((status & RRD_VALID) == 0) 1822 break; 1823 nsegs = RRD_RD_CNT(letoh32(rrd->rdinfo)); 1824 if (nsegs == 0) { 1825 /* This should not happen! */ 1826 if (alcdebug) 1827 printf("%s: unexpected segment count -- " 1828 "resetting\n", sc->sc_dev.dv_xname); 1829 break; 1830 } 1831 alc_rxeof(sc, rrd); 1832 /* Clear Rx return status. */ 1833 rrd->status = 0; 1834 ALC_DESC_INC(rr_cons, ALC_RR_RING_CNT); 1835 sc->alc_cdata.alc_rx_cons += nsegs; 1836 sc->alc_cdata.alc_rx_cons %= ALC_RR_RING_CNT; 1837 prog += nsegs; 1838 } 1839 1840 if (prog > 0) { 1841 /* Update the consumer index. */ 1842 sc->alc_cdata.alc_rr_cons = rr_cons; 1843 /* Sync Rx return descriptors. */ 1844 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 0, 1845 sc->alc_cdata.alc_rr_ring_map->dm_mapsize, 1846 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1847 /* 1848 * Sync updated Rx descriptors such that controller see 1849 * modified buffer addresses. 1850 */ 1851 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 0, 1852 sc->alc_cdata.alc_rx_ring_map->dm_mapsize, 1853 BUS_DMASYNC_PREWRITE); 1854 /* 1855 * Let controller know availability of new Rx buffers. 1856 * Since alc(4) use RXQ_CFG_RD_BURST_DEFAULT descriptors 1857 * it may be possible to update ALC_MBOX_RD0_PROD_IDX 1858 * only when Rx buffer pre-fetching is required. In 1859 * addition we already set ALC_RX_RD_FREE_THRESH to 1860 * RX_RD_FREE_THRESH_LO_DEFAULT descriptors. However 1861 * it still seems that pre-fetching needs more 1862 * experimentation. 1863 */ 1864 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 1865 sc->alc_cdata.alc_rx_cons); 1866 } 1867 } 1868 1869 /* Receive a frame. */ 1870 void 1871 alc_rxeof(struct alc_softc *sc, struct rx_rdesc *rrd) 1872 { 1873 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1874 struct alc_rxdesc *rxd; 1875 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 1876 struct mbuf *mp, *m; 1877 uint32_t rdinfo, status; 1878 int count, nsegs, rx_cons; 1879 1880 status = letoh32(rrd->status); 1881 rdinfo = letoh32(rrd->rdinfo); 1882 rx_cons = RRD_RD_IDX(rdinfo); 1883 nsegs = RRD_RD_CNT(rdinfo); 1884 1885 sc->alc_cdata.alc_rxlen = RRD_BYTES(status); 1886 if (status & (RRD_ERR_SUM | RRD_ERR_LENGTH)) { 1887 /* 1888 * We want to pass the following frames to upper 1889 * layer regardless of error status of Rx return 1890 * ring. 1891 * 1892 * o IP/TCP/UDP checksum is bad. 1893 * o frame length and protocol specific length 1894 * does not match. 1895 * 1896 * Force network stack compute checksum for 1897 * errored frames. 1898 */ 1899 if ((status & (RRD_ERR_CRC | RRD_ERR_ALIGN | 1900 RRD_ERR_TRUNC | RRD_ERR_RUNT)) != 0) 1901 return; 1902 } 1903 1904 for (count = 0; count < nsegs; count++, 1905 ALC_DESC_INC(rx_cons, ALC_RX_RING_CNT)) { 1906 rxd = &sc->alc_cdata.alc_rxdesc[rx_cons]; 1907 mp = rxd->rx_m; 1908 /* Add a new receive buffer to the ring. */ 1909 if (alc_newbuf(sc, rxd) != 0) { 1910 ifp->if_iqdrops++; 1911 /* Reuse Rx buffers. */ 1912 m_freem(sc->alc_cdata.alc_rxhead); 1913 break; 1914 } 1915 1916 /* 1917 * Assume we've received a full sized frame. 1918 * Actual size is fixed when we encounter the end of 1919 * multi-segmented frame. 1920 */ 1921 mp->m_len = sc->alc_buf_size; 1922 1923 /* Chain received mbufs. */ 1924 if (sc->alc_cdata.alc_rxhead == NULL) { 1925 sc->alc_cdata.alc_rxhead = mp; 1926 sc->alc_cdata.alc_rxtail = mp; 1927 } else { 1928 mp->m_flags &= ~M_PKTHDR; 1929 sc->alc_cdata.alc_rxprev_tail = 1930 sc->alc_cdata.alc_rxtail; 1931 sc->alc_cdata.alc_rxtail->m_next = mp; 1932 sc->alc_cdata.alc_rxtail = mp; 1933 } 1934 1935 if (count == nsegs - 1) { 1936 /* Last desc. for this frame. */ 1937 m = sc->alc_cdata.alc_rxhead; 1938 m->m_flags |= M_PKTHDR; 1939 /* 1940 * It seems that L1C/L2C controller has no way 1941 * to tell hardware to strip CRC bytes. 1942 */ 1943 m->m_pkthdr.len = 1944 sc->alc_cdata.alc_rxlen - ETHER_CRC_LEN; 1945 if (nsegs > 1) { 1946 /* Set last mbuf size. */ 1947 mp->m_len = sc->alc_cdata.alc_rxlen - 1948 (nsegs - 1) * sc->alc_buf_size; 1949 /* Remove the CRC bytes in chained mbufs. */ 1950 if (mp->m_len <= ETHER_CRC_LEN) { 1951 sc->alc_cdata.alc_rxtail = 1952 sc->alc_cdata.alc_rxprev_tail; 1953 sc->alc_cdata.alc_rxtail->m_len -= 1954 (ETHER_CRC_LEN - mp->m_len); 1955 sc->alc_cdata.alc_rxtail->m_next = NULL; 1956 m_freem(mp); 1957 } else { 1958 mp->m_len -= ETHER_CRC_LEN; 1959 } 1960 } else 1961 m->m_len = m->m_pkthdr.len; 1962 /* 1963 * Due to hardware bugs, Rx checksum offloading 1964 * was intentionally disabled. 1965 */ 1966 #if NVLAN > 0 1967 if (status & RRD_VLAN_TAG) { 1968 u_int32_t vtag = RRD_VLAN(letoh32(rrd->vtag)); 1969 m->m_pkthdr.ether_vtag = ntohs(vtag); 1970 m->m_flags |= M_VLANTAG; 1971 } 1972 #endif 1973 1974 1975 ml_enqueue(&ml, m); 1976 } 1977 } 1978 if_input(ifp, &ml); 1979 1980 /* Reset mbuf chains. */ 1981 ALC_RXCHAIN_RESET(sc); 1982 } 1983 1984 void 1985 alc_tick(void *xsc) 1986 { 1987 struct alc_softc *sc = xsc; 1988 struct mii_data *mii = &sc->sc_miibus; 1989 int s; 1990 1991 s = splnet(); 1992 mii_tick(mii); 1993 alc_stats_update(sc); 1994 1995 timeout_add_sec(&sc->alc_tick_ch, 1); 1996 splx(s); 1997 } 1998 1999 void 2000 alc_reset(struct alc_softc *sc) 2001 { 2002 uint32_t reg; 2003 int i; 2004 2005 reg = CSR_READ_4(sc, ALC_MASTER_CFG) & 0xFFFF; 2006 reg |= MASTER_OOB_DIS_OFF | MASTER_RESET; 2007 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 2008 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 2009 DELAY(10); 2010 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0) 2011 break; 2012 } 2013 if (i == 0) 2014 printf("%s: master reset timeout!\n", sc->sc_dev.dv_xname); 2015 2016 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 2017 if ((reg = CSR_READ_4(sc, ALC_IDLE_STATUS)) == 0) 2018 break; 2019 DELAY(10); 2020 } 2021 2022 if (i == 0) 2023 printf("%s: reset timeout(0x%08x)!\n", sc->sc_dev.dv_xname, 2024 reg); 2025 } 2026 2027 int 2028 alc_init(struct ifnet *ifp) 2029 { 2030 struct alc_softc *sc = ifp->if_softc; 2031 struct mii_data *mii; 2032 uint8_t eaddr[ETHER_ADDR_LEN]; 2033 bus_addr_t paddr; 2034 uint32_t reg, rxf_hi, rxf_lo; 2035 int error; 2036 2037 /* 2038 * Cancel any pending I/O. 2039 */ 2040 alc_stop(sc); 2041 /* 2042 * Reset the chip to a known state. 2043 */ 2044 alc_reset(sc); 2045 2046 /* Initialize Rx descriptors. */ 2047 error = alc_init_rx_ring(sc); 2048 if (error != 0) { 2049 printf("%s: no memory for Rx buffers.\n", sc->sc_dev.dv_xname); 2050 alc_stop(sc); 2051 return (error); 2052 } 2053 alc_init_rr_ring(sc); 2054 alc_init_tx_ring(sc); 2055 alc_init_cmb(sc); 2056 alc_init_smb(sc); 2057 2058 /* Enable all clocks. */ 2059 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, 0); 2060 2061 /* Reprogram the station address. */ 2062 bcopy(LLADDR(ifp->if_sadl), eaddr, ETHER_ADDR_LEN); 2063 CSR_WRITE_4(sc, ALC_PAR0, 2064 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 2065 CSR_WRITE_4(sc, ALC_PAR1, eaddr[0] << 8 | eaddr[1]); 2066 /* 2067 * Clear WOL status and disable all WOL feature as WOL 2068 * would interfere Rx operation under normal environments. 2069 */ 2070 CSR_READ_4(sc, ALC_WOL_CFG); 2071 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 2072 /* Set Tx descriptor base addresses. */ 2073 paddr = sc->alc_rdata.alc_tx_ring_paddr; 2074 CSR_WRITE_4(sc, ALC_TX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 2075 CSR_WRITE_4(sc, ALC_TDL_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 2076 /* We don't use high priority ring. */ 2077 CSR_WRITE_4(sc, ALC_TDH_HEAD_ADDR_LO, 0); 2078 /* Set Tx descriptor counter. */ 2079 CSR_WRITE_4(sc, ALC_TD_RING_CNT, 2080 (ALC_TX_RING_CNT << TD_RING_CNT_SHIFT) & TD_RING_CNT_MASK); 2081 /* Set Rx descriptor base addresses. */ 2082 paddr = sc->alc_rdata.alc_rx_ring_paddr; 2083 CSR_WRITE_4(sc, ALC_RX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 2084 CSR_WRITE_4(sc, ALC_RD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 2085 /* We use one Rx ring. */ 2086 CSR_WRITE_4(sc, ALC_RD1_HEAD_ADDR_LO, 0); 2087 CSR_WRITE_4(sc, ALC_RD2_HEAD_ADDR_LO, 0); 2088 CSR_WRITE_4(sc, ALC_RD3_HEAD_ADDR_LO, 0); 2089 /* Set Rx descriptor counter. */ 2090 CSR_WRITE_4(sc, ALC_RD_RING_CNT, 2091 (ALC_RX_RING_CNT << RD_RING_CNT_SHIFT) & RD_RING_CNT_MASK); 2092 2093 /* 2094 * Let hardware split jumbo frames into alc_max_buf_sized chunks. 2095 * if it do not fit the buffer size. Rx return descriptor holds 2096 * a counter that indicates how many fragments were made by the 2097 * hardware. The buffer size should be multiple of 8 bytes. 2098 * Since hardware has limit on the size of buffer size, always 2099 * use the maximum value. 2100 * For strict-alignment architectures make sure to reduce buffer 2101 * size by 8 bytes to make room for alignment fixup. 2102 */ 2103 sc->alc_buf_size = RX_BUF_SIZE_MAX; 2104 CSR_WRITE_4(sc, ALC_RX_BUF_SIZE, sc->alc_buf_size); 2105 2106 paddr = sc->alc_rdata.alc_rr_ring_paddr; 2107 /* Set Rx return descriptor base addresses. */ 2108 CSR_WRITE_4(sc, ALC_RRD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 2109 /* We use one Rx return ring. */ 2110 CSR_WRITE_4(sc, ALC_RRD1_HEAD_ADDR_LO, 0); 2111 CSR_WRITE_4(sc, ALC_RRD2_HEAD_ADDR_LO, 0); 2112 CSR_WRITE_4(sc, ALC_RRD3_HEAD_ADDR_LO, 0); 2113 /* Set Rx return descriptor counter. */ 2114 CSR_WRITE_4(sc, ALC_RRD_RING_CNT, 2115 (ALC_RR_RING_CNT << RRD_RING_CNT_SHIFT) & RRD_RING_CNT_MASK); 2116 paddr = sc->alc_rdata.alc_cmb_paddr; 2117 CSR_WRITE_4(sc, ALC_CMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 2118 paddr = sc->alc_rdata.alc_smb_paddr; 2119 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 2120 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 2121 2122 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1) { 2123 /* Reconfigure SRAM - Vendor magic. */ 2124 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_LEN, 0x000002A0); 2125 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_LEN, 0x00000100); 2126 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_ADDR, 0x029F0000); 2127 CSR_WRITE_4(sc, ALC_SRAM_RD0_ADDR, 0x02BF02A0); 2128 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_ADDR, 0x03BF02C0); 2129 CSR_WRITE_4(sc, ALC_SRAM_TD_ADDR, 0x03DF03C0); 2130 CSR_WRITE_4(sc, ALC_TXF_WATER_MARK, 0x00000000); 2131 CSR_WRITE_4(sc, ALC_RD_DMA_CFG, 0x00000000); 2132 } 2133 2134 /* Tell hardware that we're ready to load DMA blocks. */ 2135 CSR_WRITE_4(sc, ALC_DMA_BLOCK, DMA_BLOCK_LOAD); 2136 2137 /* Configure interrupt moderation timer. */ 2138 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 2139 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 2140 reg = ALC_USECS(sc->alc_int_rx_mod) << IM_TIMER_RX_SHIFT; 2141 reg |= ALC_USECS(sc->alc_int_tx_mod) << IM_TIMER_TX_SHIFT; 2142 CSR_WRITE_4(sc, ALC_IM_TIMER, reg); 2143 /* 2144 * We don't want to automatic interrupt clear as task queue 2145 * for the interrupt should know interrupt status. 2146 */ 2147 reg = MASTER_SA_TIMER_ENB; 2148 if (ALC_USECS(sc->alc_int_rx_mod) != 0) 2149 reg |= MASTER_IM_RX_TIMER_ENB; 2150 if (ALC_USECS(sc->alc_int_tx_mod) != 0) 2151 reg |= MASTER_IM_TX_TIMER_ENB; 2152 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 2153 /* 2154 * Disable interrupt re-trigger timer. We don't want automatic 2155 * re-triggering of un-ACKed interrupts. 2156 */ 2157 CSR_WRITE_4(sc, ALC_INTR_RETRIG_TIMER, ALC_USECS(0)); 2158 /* Configure CMB. */ 2159 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 2160 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, 4); 2161 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(5000)); 2162 } else 2163 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(0)); 2164 /* 2165 * Hardware can be configured to issue SMB interrupt based 2166 * on programmed interval. Since there is a callout that is 2167 * invoked for every hz in driver we use that instead of 2168 * relying on periodic SMB interrupt. 2169 */ 2170 CSR_WRITE_4(sc, ALC_SMB_STAT_TIMER, ALC_USECS(0)); 2171 /* Clear MAC statistics. */ 2172 alc_stats_clear(sc); 2173 2174 /* 2175 * Always use maximum frame size that controller can support. 2176 * Otherwise received frames that has larger frame length 2177 * than alc(4) MTU would be silently dropped in hardware. This 2178 * would make path-MTU discovery hard as sender wouldn't get 2179 * any responses from receiver. alc(4) supports 2180 * multi-fragmented frames on Rx path so it has no issue on 2181 * assembling fragmented frames. Using maximum frame size also 2182 * removes the need to reinitialize hardware when interface 2183 * MTU configuration was changed. 2184 * 2185 * Be conservative in what you do, be liberal in what you 2186 * accept from others - RFC 793. 2187 */ 2188 CSR_WRITE_4(sc, ALC_FRAME_SIZE, sc->alc_max_framelen); 2189 2190 /* Disable header split(?) */ 2191 CSR_WRITE_4(sc, ALC_HDS_CFG, 0); 2192 2193 /* Configure IPG/IFG parameters. */ 2194 CSR_WRITE_4(sc, ALC_IPG_IFG_CFG, 2195 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) | 2196 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 2197 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 2198 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK)); 2199 /* Set parameters for half-duplex media. */ 2200 CSR_WRITE_4(sc, ALC_HDPX_CFG, 2201 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 2202 HDPX_CFG_LCOL_MASK) | 2203 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 2204 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 2205 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 2206 HDPX_CFG_ABEBT_MASK) | 2207 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 2208 HDPX_CFG_JAMIPG_MASK)); 2209 /* 2210 * Set TSO/checksum offload threshold. For frames that is 2211 * larger than this threshold, hardware wouldn't do 2212 * TSO/checksum offloading. 2213 */ 2214 CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH, 2215 (sc->alc_max_framelen >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) & 2216 TSO_OFFLOAD_THRESH_MASK); 2217 /* Configure TxQ. */ 2218 reg = (alc_dma_burst[sc->alc_dma_rd_burst] << 2219 TXQ_CFG_TX_FIFO_BURST_SHIFT) & TXQ_CFG_TX_FIFO_BURST_MASK; 2220 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1 || 2221 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_2) 2222 reg >>= 1; 2223 reg |= (TXQ_CFG_TD_BURST_DEFAULT << TXQ_CFG_TD_BURST_SHIFT) & 2224 TXQ_CFG_TD_BURST_MASK; 2225 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE); 2226 2227 /* Configure Rx free descriptor pre-fetching. */ 2228 CSR_WRITE_4(sc, ALC_RX_RD_FREE_THRESH, 2229 ((RX_RD_FREE_THRESH_HI_DEFAULT << RX_RD_FREE_THRESH_HI_SHIFT) & 2230 RX_RD_FREE_THRESH_HI_MASK) | 2231 ((RX_RD_FREE_THRESH_LO_DEFAULT << RX_RD_FREE_THRESH_LO_SHIFT) & 2232 RX_RD_FREE_THRESH_LO_MASK)); 2233 2234 /* 2235 * Configure flow control parameters. 2236 * XON : 80% of Rx FIFO 2237 * XOFF : 30% of Rx FIFO 2238 */ 2239 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1C || 2240 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C) { 2241 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 2242 rxf_hi = (reg * 8) / 10; 2243 rxf_lo = (reg * 3) / 10; 2244 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 2245 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 2246 RX_FIFO_PAUSE_THRESH_LO_MASK) | 2247 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 2248 RX_FIFO_PAUSE_THRESH_HI_MASK)); 2249 } 2250 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D_1 || 2251 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1) 2252 CSR_WRITE_4(sc, ALC_SERDES_LOCK, 2253 CSR_READ_4(sc, ALC_SERDES_LOCK) | SERDES_MAC_CLK_SLOWDOWN | 2254 SERDES_PHY_CLK_SLOWDOWN); 2255 2256 /* Disable RSS until I understand L1C/L2C's RSS logic. */ 2257 CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0); 2258 CSR_WRITE_4(sc, ALC_RSS_CPU, 0); 2259 2260 /* Configure RxQ. */ 2261 reg = (RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 2262 RXQ_CFG_RD_BURST_MASK; 2263 reg |= RXQ_CFG_RSS_MODE_DIS; 2264 if ((sc->alc_flags & ALC_FLAG_ASPM_MON) != 0) 2265 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_1M; 2266 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 2267 2268 /* Configure DMA parameters. */ 2269 reg = DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI; 2270 reg |= sc->alc_rcb; 2271 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 2272 reg |= DMA_CFG_CMB_ENB; 2273 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) 2274 reg |= DMA_CFG_SMB_ENB; 2275 else 2276 reg |= DMA_CFG_SMB_DIS; 2277 reg |= (sc->alc_dma_rd_burst & DMA_CFG_RD_BURST_MASK) << 2278 DMA_CFG_RD_BURST_SHIFT; 2279 reg |= (sc->alc_dma_wr_burst & DMA_CFG_WR_BURST_MASK) << 2280 DMA_CFG_WR_BURST_SHIFT; 2281 reg |= (DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 2282 DMA_CFG_RD_DELAY_CNT_MASK; 2283 reg |= (DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 2284 DMA_CFG_WR_DELAY_CNT_MASK; 2285 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 2286 2287 /* 2288 * Configure Tx/Rx MACs. 2289 * - Auto-padding for short frames. 2290 * - Enable CRC generation. 2291 * Actual reconfiguration of MAC for resolved speed/duplex 2292 * is followed after detection of link establishment. 2293 * AR813x/AR815x always does checksum computation regardless 2294 * of MAC_CFG_RXCSUM_ENB bit. Also the controller is known to 2295 * have bug in protocol field in Rx return structure so 2296 * these controllers can't handle fragmented frames. Disable 2297 * Rx checksum offloading until there is a newer controller 2298 * that has sane implementation. 2299 */ 2300 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 2301 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 2302 MAC_CFG_PREAMBLE_MASK); 2303 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D || 2304 sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D_1 || 2305 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_2) 2306 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 2307 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0) 2308 reg |= MAC_CFG_SPEED_10_100; 2309 else 2310 reg |= MAC_CFG_SPEED_1000; 2311 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 2312 2313 /* Set up the receive filter. */ 2314 alc_iff(sc); 2315 2316 alc_rxvlan(sc); 2317 2318 /* Acknowledge all pending interrupts and clear it. */ 2319 CSR_WRITE_4(sc, ALC_INTR_MASK, ALC_INTRS); 2320 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 2321 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0); 2322 2323 sc->alc_flags &= ~ALC_FLAG_LINK; 2324 /* Switch to the current media. */ 2325 mii = &sc->sc_miibus; 2326 mii_mediachg(mii); 2327 2328 timeout_add_sec(&sc->alc_tick_ch, 1); 2329 2330 ifp->if_flags |= IFF_RUNNING; 2331 ifq_clr_oactive(&ifp->if_snd); 2332 2333 return (0); 2334 } 2335 2336 void 2337 alc_stop(struct alc_softc *sc) 2338 { 2339 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 2340 struct alc_txdesc *txd; 2341 struct alc_rxdesc *rxd; 2342 uint32_t reg; 2343 int i; 2344 2345 /* 2346 * Mark the interface down and cancel the watchdog timer. 2347 */ 2348 ifp->if_flags &= ~IFF_RUNNING; 2349 ifq_clr_oactive(&ifp->if_snd); 2350 ifp->if_timer = 0; 2351 2352 timeout_del(&sc->alc_tick_ch); 2353 sc->alc_flags &= ~ALC_FLAG_LINK; 2354 2355 alc_stats_update(sc); 2356 2357 /* Disable interrupts. */ 2358 CSR_WRITE_4(sc, ALC_INTR_MASK, 0); 2359 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 2360 alc_stop_queue(sc); 2361 2362 /* Disable DMA. */ 2363 reg = CSR_READ_4(sc, ALC_DMA_CFG); 2364 reg &= ~(DMA_CFG_CMB_ENB | DMA_CFG_SMB_ENB); 2365 reg |= DMA_CFG_SMB_DIS; 2366 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 2367 DELAY(1000); 2368 2369 /* Stop Rx/Tx MACs. */ 2370 alc_stop_mac(sc); 2371 2372 /* Disable interrupts which might be touched in taskq handler. */ 2373 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 2374 2375 /* Reclaim Rx buffers that have been processed. */ 2376 m_freem(sc->alc_cdata.alc_rxhead); 2377 ALC_RXCHAIN_RESET(sc); 2378 /* 2379 * Free Tx/Rx mbufs still in the queues. 2380 */ 2381 for (i = 0; i < ALC_RX_RING_CNT; i++) { 2382 rxd = &sc->alc_cdata.alc_rxdesc[i]; 2383 if (rxd->rx_m != NULL) { 2384 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0, 2385 rxd->rx_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2386 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 2387 m_freem(rxd->rx_m); 2388 rxd->rx_m = NULL; 2389 } 2390 } 2391 for (i = 0; i < ALC_TX_RING_CNT; i++) { 2392 txd = &sc->alc_cdata.alc_txdesc[i]; 2393 if (txd->tx_m != NULL) { 2394 bus_dmamap_sync(sc->sc_dmat, txd->tx_dmamap, 0, 2395 txd->tx_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2396 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 2397 m_freem(txd->tx_m); 2398 txd->tx_m = NULL; 2399 } 2400 } 2401 } 2402 2403 void 2404 alc_stop_mac(struct alc_softc *sc) 2405 { 2406 uint32_t reg; 2407 int i; 2408 2409 /* Disable Rx/Tx MAC. */ 2410 reg = CSR_READ_4(sc, ALC_MAC_CFG); 2411 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 2412 reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 2413 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 2414 } 2415 for (i = ALC_TIMEOUT; i > 0; i--) { 2416 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 2417 if (reg == 0) 2418 break; 2419 DELAY(10); 2420 } 2421 if (i == 0) 2422 printf("%s: could not disable Rx/Tx MAC(0x%08x)!\n", 2423 sc->sc_dev.dv_xname, reg); 2424 } 2425 2426 void 2427 alc_start_queue(struct alc_softc *sc) 2428 { 2429 uint32_t qcfg[] = { 2430 0, 2431 RXQ_CFG_QUEUE0_ENB, 2432 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB, 2433 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | RXQ_CFG_QUEUE2_ENB, 2434 RXQ_CFG_ENB 2435 }; 2436 uint32_t cfg; 2437 2438 /* Enable RxQ. */ 2439 cfg = CSR_READ_4(sc, ALC_RXQ_CFG); 2440 cfg &= ~RXQ_CFG_ENB; 2441 cfg |= qcfg[1]; 2442 CSR_WRITE_4(sc, ALC_RXQ_CFG, cfg); 2443 /* Enable TxQ. */ 2444 cfg = CSR_READ_4(sc, ALC_TXQ_CFG); 2445 cfg |= TXQ_CFG_ENB; 2446 CSR_WRITE_4(sc, ALC_TXQ_CFG, cfg); 2447 } 2448 2449 void 2450 alc_stop_queue(struct alc_softc *sc) 2451 { 2452 uint32_t reg; 2453 int i; 2454 2455 /* Disable RxQ. */ 2456 reg = CSR_READ_4(sc, ALC_RXQ_CFG); 2457 if ((reg & RXQ_CFG_ENB) != 0) { 2458 reg &= ~RXQ_CFG_ENB; 2459 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 2460 } 2461 /* Disable TxQ. */ 2462 reg = CSR_READ_4(sc, ALC_TXQ_CFG); 2463 if ((reg & TXQ_CFG_ENB) != 0) { 2464 reg &= ~TXQ_CFG_ENB; 2465 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg); 2466 } 2467 for (i = ALC_TIMEOUT; i > 0; i--) { 2468 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 2469 if ((reg & (IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 2470 break; 2471 DELAY(10); 2472 } 2473 if (i == 0) 2474 printf("%s: could not disable RxQ/TxQ (0x%08x)!\n", 2475 sc->sc_dev.dv_xname, reg); 2476 } 2477 2478 void 2479 alc_init_tx_ring(struct alc_softc *sc) 2480 { 2481 struct alc_ring_data *rd; 2482 struct alc_txdesc *txd; 2483 int i; 2484 2485 sc->alc_cdata.alc_tx_prod = 0; 2486 sc->alc_cdata.alc_tx_cons = 0; 2487 sc->alc_cdata.alc_tx_cnt = 0; 2488 2489 rd = &sc->alc_rdata; 2490 bzero(rd->alc_tx_ring, ALC_TX_RING_SZ); 2491 for (i = 0; i < ALC_TX_RING_CNT; i++) { 2492 txd = &sc->alc_cdata.alc_txdesc[i]; 2493 txd->tx_m = NULL; 2494 } 2495 2496 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0, 2497 sc->alc_cdata.alc_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2498 } 2499 2500 int 2501 alc_init_rx_ring(struct alc_softc *sc) 2502 { 2503 struct alc_ring_data *rd; 2504 struct alc_rxdesc *rxd; 2505 int i; 2506 2507 sc->alc_cdata.alc_rx_cons = ALC_RX_RING_CNT - 1; 2508 rd = &sc->alc_rdata; 2509 bzero(rd->alc_rx_ring, ALC_RX_RING_SZ); 2510 for (i = 0; i < ALC_RX_RING_CNT; i++) { 2511 rxd = &sc->alc_cdata.alc_rxdesc[i]; 2512 rxd->rx_m = NULL; 2513 rxd->rx_desc = &rd->alc_rx_ring[i]; 2514 if (alc_newbuf(sc, rxd) != 0) 2515 return (ENOBUFS); 2516 } 2517 2518 /* 2519 * Since controller does not update Rx descriptors, driver 2520 * does have to read Rx descriptors back so BUS_DMASYNC_PREWRITE 2521 * is enough to ensure coherence. 2522 */ 2523 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 0, 2524 sc->alc_cdata.alc_rx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2525 /* Let controller know availability of new Rx buffers. */ 2526 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, sc->alc_cdata.alc_rx_cons); 2527 2528 return (0); 2529 } 2530 2531 void 2532 alc_init_rr_ring(struct alc_softc *sc) 2533 { 2534 struct alc_ring_data *rd; 2535 2536 sc->alc_cdata.alc_rr_cons = 0; 2537 ALC_RXCHAIN_RESET(sc); 2538 2539 rd = &sc->alc_rdata; 2540 bzero(rd->alc_rr_ring, ALC_RR_RING_SZ); 2541 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 0, 2542 sc->alc_cdata.alc_rr_ring_map->dm_mapsize, 2543 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2544 } 2545 2546 void 2547 alc_init_cmb(struct alc_softc *sc) 2548 { 2549 struct alc_ring_data *rd; 2550 2551 rd = &sc->alc_rdata; 2552 bzero(rd->alc_cmb, ALC_CMB_SZ); 2553 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0, 2554 sc->alc_cdata.alc_cmb_map->dm_mapsize, 2555 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2556 } 2557 2558 void 2559 alc_init_smb(struct alc_softc *sc) 2560 { 2561 struct alc_ring_data *rd; 2562 2563 rd = &sc->alc_rdata; 2564 bzero(rd->alc_smb, ALC_SMB_SZ); 2565 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 2566 sc->alc_cdata.alc_smb_map->dm_mapsize, 2567 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2568 } 2569 2570 void 2571 alc_rxvlan(struct alc_softc *sc) 2572 { 2573 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 2574 uint32_t reg; 2575 2576 reg = CSR_READ_4(sc, ALC_MAC_CFG); 2577 if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) 2578 reg |= MAC_CFG_VLAN_TAG_STRIP; 2579 else 2580 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 2581 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 2582 } 2583 2584 void 2585 alc_iff(struct alc_softc *sc) 2586 { 2587 struct arpcom *ac = &sc->sc_arpcom; 2588 struct ifnet *ifp = &ac->ac_if; 2589 struct ether_multi *enm; 2590 struct ether_multistep step; 2591 uint32_t crc; 2592 uint32_t mchash[2]; 2593 uint32_t rxcfg; 2594 2595 rxcfg = CSR_READ_4(sc, ALC_MAC_CFG); 2596 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 2597 ifp->if_flags &= ~IFF_ALLMULTI; 2598 2599 /* 2600 * Always accept broadcast frames. 2601 */ 2602 rxcfg |= MAC_CFG_BCAST; 2603 2604 if (ifp->if_flags & IFF_PROMISC || ac->ac_multirangecnt > 0) { 2605 ifp->if_flags |= IFF_ALLMULTI; 2606 if (ifp->if_flags & IFF_PROMISC) 2607 rxcfg |= MAC_CFG_PROMISC; 2608 else 2609 rxcfg |= MAC_CFG_ALLMULTI; 2610 mchash[0] = mchash[1] = 0xFFFFFFFF; 2611 } else { 2612 /* Program new filter. */ 2613 bzero(mchash, sizeof(mchash)); 2614 2615 ETHER_FIRST_MULTI(step, ac, enm); 2616 while (enm != NULL) { 2617 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2618 2619 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 2620 2621 ETHER_NEXT_MULTI(step, enm); 2622 } 2623 } 2624 2625 CSR_WRITE_4(sc, ALC_MAR0, mchash[0]); 2626 CSR_WRITE_4(sc, ALC_MAR1, mchash[1]); 2627 CSR_WRITE_4(sc, ALC_MAC_CFG, rxcfg); 2628 } 2629