1 /* $OpenBSD: if_agereg.h,v 1.2 2009/02/23 01:38:37 kevlo Exp $ */ 2 3 /*- 4 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD: src/sys/dev/age/if_agereg.h,v 1.1 2008/05/19 01:39:59 yongari Exp $ 30 */ 31 32 #ifndef _IF_AGEREG_H 33 #define _IF_AGEREG_H 34 35 #define AGE_PCIR_BAR 0x10 36 37 /* 38 * Attansic Technology Corp. PCI vendor ID 39 */ 40 #define VENDORID_ATTANSIC 0x1969 41 42 /* 43 * Attansic L1 device ID 44 */ 45 #define DEVICEID_ATTANSIC_L1 0x1048 46 47 #define AGE_VPD_REG_CONF_START 0x0100 48 #define AGE_VPD_REG_CONF_END 0x01FF 49 #define AGE_VPD_REG_CONF_SIG 0x5A 50 51 #define AGE_SPI_CTRL 0x200 52 #define SPI_STAT_NOT_READY 0x00000001 53 #define SPI_STAT_WR_ENB 0x00000002 54 #define SPI_STAT_WRP_ENB 0x00000080 55 #define SPI_INST_MASK 0x000000FF 56 #define SPI_START 0x00000100 57 #define SPI_INST_START 0x00000800 58 #define SPI_VPD_ENB 0x00002000 59 #define SPI_LOADER_START 0x00008000 60 #define SPI_CS_HI_MASK 0x00030000 61 #define SPI_CS_HOLD_MASK 0x000C0000 62 #define SPI_CLK_LO_MASK 0x00300000 63 #define SPI_CLK_HI_MASK 0x00C00000 64 #define SPI_CS_SETUP_MASK 0x03000000 65 #define SPI_EPROM_PG_MASK 0x0C000000 66 #define SPI_INST_SHIFT 8 67 #define SPI_CS_HI_SHIFT 16 68 #define SPI_CS_HOLD_SHIFT 18 69 #define SPI_CLK_LO_SHIFT 20 70 #define SPI_CLK_HI_SHIFT 22 71 #define SPI_CS_SETUP_SHIFT 24 72 #define SPI_EPROM_PG_SHIFT 26 73 #define SPI_WAIT_READY 0x10000000 74 75 #define AGE_SPI_ADDR 0x204 /* 16bits */ 76 77 #define AGE_SPI_DATA 0x208 78 79 #define AGE_SPI_CONFIG 0x20C 80 81 #define AGE_SPI_OP_PROGRAM 0x210 /* 8bits */ 82 83 #define AGE_SPI_OP_SC_ERASE 0x211 /* 8bits */ 84 85 #define AGE_SPI_OP_CHIP_ERASE 0x212 /* 8bits */ 86 87 #define AGE_SPI_OP_RDID 0x213 /* 8bits */ 88 89 #define AGE_SPI_OP_WREN 0x214 /* 8bits */ 90 91 #define AGE_SPI_OP_RDSR 0x215 /* 8bits */ 92 93 #define AGE_SPI_OP_WRSR 0x216 /* 8bits */ 94 95 #define AGE_SPI_OP_READ 0x217 /* 8bits */ 96 97 #define AGE_TWSI_CTRL 0x218 98 99 #define AGE_DEV_MISC_CTRL 0x21C 100 101 #define AGE_MASTER_CFG 0x1400 102 #define MASTER_RESET 0x00000001 103 #define MASTER_MTIMER_ENB 0x00000002 104 #define MASTER_ITIMER_ENB 0x00000004 105 #define MASTER_MANUAL_INT_ENB 0x00000008 106 #define MASTER_CHIP_REV_MASK 0x00FF0000 107 #define MASTER_CHIP_ID_MASK 0xFF000000 108 #define MASTER_CHIP_REV_SHIFT 16 109 #define MASTER_CHIP_ID_SHIFT 24 110 111 /* Number of ticks per usec for L1. */ 112 #define AGE_TICK_USECS 2 113 #define AGE_USECS(x) ((x) / AGE_TICK_USECS) 114 115 #define AGE_MANUAL_TIMER 0x1404 116 117 #define AGE_IM_TIMER 0x1408 /* 16bits */ 118 #define AGE_IM_TIMER_MIN 0 119 #define AGE_IM_TIMER_MAX 130000 /* 130ms */ 120 #define AGE_IM_TIMER_DEFAULT 100 121 122 #define AGE_GPHY_CTRL 0x140C /* 16bits */ 123 #define GPHY_CTRL_RST 0x0000 124 #define GPHY_CTRL_CLR 0x0001 125 126 #define AGE_INTR_CLR_TIMER 0x140E /* 16bits */ 127 128 #define AGE_IDLE_STATUS 0x1410 129 #define IDLE_STATUS_RXMAC 0x00000001 130 #define IDLE_STATUS_TXMAC 0x00000002 131 #define IDLE_STATUS_RXQ 0x00000004 132 #define IDLE_STATUS_TXQ 0x00000008 133 #define IDLE_STATUS_DMARD 0x00000010 134 #define IDLE_STATUS_DMAWR 0x00000020 135 #define IDLE_STATUS_SMB 0x00000040 136 #define IDLE_STATUS_CMB 0x00000080 137 138 #define AGE_MDIO 0x1414 139 #define MDIO_DATA_MASK 0x0000FFFF 140 #define MDIO_REG_ADDR_MASK 0x001F0000 141 #define MDIO_OP_READ 0x00200000 142 #define MDIO_OP_WRITE 0x00000000 143 #define MDIO_SUP_PREAMBLE 0x00400000 144 #define MDIO_OP_EXECUTE 0x00800000 145 #define MDIO_CLK_25_4 0x00000000 146 #define MDIO_CLK_25_6 0x02000000 147 #define MDIO_CLK_25_8 0x03000000 148 #define MDIO_CLK_25_10 0x04000000 149 #define MDIO_CLK_25_14 0x05000000 150 #define MDIO_CLK_25_20 0x06000000 151 #define MDIO_CLK_25_28 0x07000000 152 #define MDIO_OP_BUSY 0x08000000 153 #define MDIO_DATA_SHIFT 0 154 #define MDIO_REG_ADDR_SHIFT 16 155 156 #define MDIO_REG_ADDR(x) \ 157 (((x) << MDIO_REG_ADDR_SHIFT) & MDIO_REG_ADDR_MASK) 158 /* Default PHY address. */ 159 #define AGE_PHY_ADDR 0 160 161 #define AGE_PHY_STATUS 0x1418 162 163 #define AGE_BIST0 0x141C 164 #define BIST0_ENB 0x00000001 165 #define BIST0_SRAM_FAIL 0x00000002 166 #define BIST0_FUSE_FLAG 0x00000004 167 168 #define AGE_BIST1 0x1420 169 #define BIST1_ENB 0x00000001 170 #define BIST1_SRAM_FAIL 0x00000002 171 #define BIST1_FUSE_FLAG 0x00000004 172 173 #define AGE_MAC_CFG 0x1480 174 #define MAC_CFG_TX_ENB 0x00000001 175 #define MAC_CFG_RX_ENB 0x00000002 176 #define MAC_CFG_TX_FC 0x00000004 177 #define MAC_CFG_RX_FC 0x00000008 178 #define MAC_CFG_LOOP 0x00000010 179 #define MAC_CFG_FULL_DUPLEX 0x00000020 180 #define MAC_CFG_TX_CRC_ENB 0x00000040 181 #define MAC_CFG_TX_AUTO_PAD 0x00000080 182 #define MAC_CFG_TX_LENCHK 0x00000100 183 #define MAC_CFG_RX_JUMBO_ENB 0x00000200 184 #define MAC_CFG_PREAMBLE_MASK 0x00003C00 185 #define MAC_CFG_VLAN_TAG_STRIP 0x00004000 186 #define MAC_CFG_PROMISC 0x00008000 187 #define MAC_CFG_TX_PAUSE 0x00010000 188 #define MAC_CFG_SCNT 0x00020000 189 #define MAC_CFG_SYNC_RST_TX 0x00040000 190 #define MAC_CFG_SPEED_MASK 0x00300000 191 #define MAC_CFG_SPEED_10_100 0x00100000 192 #define MAC_CFG_SPEED_1000 0x00200000 193 #define MAC_CFG_DBG_TX_BACKOFF 0x00400000 194 #define MAC_CFG_TX_JUMBO_ENB 0x00800000 195 #define MAC_CFG_RXCSUM_ENB 0x01000000 196 #define MAC_CFG_ALLMULTI 0x02000000 197 #define MAC_CFG_BCAST 0x04000000 198 #define MAC_CFG_DBG 0x08000000 199 #define MAC_CFG_PREAMBLE_SHIFT 10 200 #define MAC_CFG_PREAMBLE_DEFAULT 7 201 202 #define AGE_IPG_IFG_CFG 0x1484 203 #define IPG_IFG_IPGT_MASK 0x0000007F 204 #define IPG_IFG_MIFG_MASK 0x0000FF00 205 #define IPG_IFG_IPG1_MASK 0x007F0000 206 #define IPG_IFG_IPG2_MASK 0x7F000000 207 #define IPG_IFG_IPGT_SHIFT 0 208 #define IPG_IFG_IPGT_DEFAULT 0x60 209 #define IPG_IFG_MIFG_SHIFT 8 210 #define IPG_IFG_MIFG_DEFAULT 0x50 211 #define IPG_IFG_IPG1_SHIFT 16 212 #define IPG_IFG_IPG1_DEFAULT 0x40 213 #define IPG_IFG_IPG2_SHIFT 24 214 #define IPG_IFG_IPG2_DEFAULT 0x60 215 216 /* station address */ 217 #define AGE_PAR0 0x1488 218 #define AGE_PAR1 0x148C 219 220 /* 64bit multicast hash register. */ 221 #define AGE_MAR0 0x1490 222 #define AGE_MAR1 0x1494 223 224 /* half-duplex parameter configuration. */ 225 #define AGE_HDPX_CFG 0x1498 226 #define HDPX_CFG_LCOL_MASK 0x000003FF 227 #define HDPX_CFG_RETRY_MASK 0x0000F000 228 #define HDPX_CFG_EXC_DEF_EN 0x00010000 229 #define HDPX_CFG_NO_BACK_C 0x00020000 230 #define HDPX_CFG_NO_BACK_P 0x00040000 231 #define HDPX_CFG_ABEBE 0x00080000 232 #define HDPX_CFG_ABEBT_MASK 0x00F00000 233 #define HDPX_CFG_JAMIPG_MASK 0x0F000000 234 #define HDPX_CFG_LCOL_SHIFT 0 235 #define HDPX_CFG_LCOL_DEFAULT 0x37 236 #define HDPX_CFG_RETRY_SHIFT 12 237 #define HDPX_CFG_RETRY_DEFAULT 0x0F 238 #define HDPX_CFG_ABEBT_SHIFT 20 239 #define HDPX_CFG_ABEBT_DEFAULT 0x0A 240 #define HDPX_CFG_JAMIPG_SHIFT 24 241 #define HDPX_CFG_JAMIPG_DEFAULT 0x07 242 243 #define AGE_FRAME_SIZE 0x149C 244 245 #define AGE_WOL_CFG 0x14A0 246 #define WOL_CFG_PATTERN 0x00000001 247 #define WOL_CFG_PATTERN_ENB 0x00000002 248 #define WOL_CFG_MAGIC 0x00000004 249 #define WOL_CFG_MAGIC_ENB 0x00000008 250 #define WOL_CFG_LINK_CHG 0x00000010 251 #define WOL_CFG_LINK_CHG_ENB 0x00000020 252 #define WOL_CFG_PATTERN_DET 0x00000100 253 #define WOL_CFG_MAGIC_DET 0x00000200 254 #define WOL_CFG_LINK_CHG_DET 0x00000400 255 #define WOL_CFG_CLK_SWITCH_ENB 0x00008000 256 #define WOL_CFG_PATTERN0 0x00010000 257 #define WOL_CFG_PATTERN1 0x00020000 258 #define WOL_CFG_PATTERN2 0x00040000 259 #define WOL_CFG_PATTERN3 0x00080000 260 #define WOL_CFG_PATTERN4 0x00100000 261 #define WOL_CFG_PATTERN5 0x00200000 262 #define WOL_CFG_PATTERN6 0x00400000 263 264 /* WOL pattern length. */ 265 #define AGE_PATTERN_CFG0 0x14A4 266 #define PATTERN_CFG_0_LEN_MASK 0x0000007F 267 #define PATTERN_CFG_1_LEN_MASK 0x00007F00 268 #define PATTERN_CFG_2_LEN_MASK 0x007F0000 269 #define PATTERN_CFG_3_LEN_MASK 0x7F000000 270 271 #define AGE_PATTERN_CFG1 0x14A8 272 #define PATTERN_CFG_4_LEN_MASK 0x0000007F 273 #define PATTERN_CFG_5_LEN_MASK 0x00007F00 274 #define PATTERN_CFG_6_LEN_MASK 0x007F0000 275 276 #define AGE_SRAM_RD_ADDR 0x1500 277 278 #define AGE_SRAM_RD_LEN 0x1504 279 280 #define AGE_SRAM_RRD_ADDR 0x1508 281 282 #define AGE_SRAM_RRD_LEN 0x150C 283 284 #define AGE_SRAM_TPD_ADDR 0x1510 285 286 #define AGE_SRAM_TPD_LEN 0x1514 287 288 #define AGE_SRAM_TRD_ADDR 0x1518 289 290 #define AGE_SRAM_TRD_LEN 0x151C 291 292 #define AGE_SRAM_RX_FIFO_ADDR 0x1520 293 294 #define AGE_SRAM_RX_FIFO_LEN 0x1524 295 296 #define AGE_SRAM_TX_FIFO_ADDR 0x1528 297 298 #define AGE_SRAM_TX_FIFO_LEN 0x152C 299 300 #define AGE_SRAM_TCPH_ADDR 0x1530 301 #define SRAM_TCPH_ADDR_MASK 0x00000FFF 302 #define SRAM_PATH_ADDR_MASK 0x0FFF0000 303 #define SRAM_TCPH_ADDR_SHIFT 0 304 #define SRAM_PATH_ADDR_SHIFT 16 305 306 #define AGE_DMA_BLOCK 0x1534 307 #define DMA_BLOCK_LOAD 0x00000001 308 309 /* 310 * All descriptors and CMB/SMB share the same high address. 311 */ 312 #define AGE_DESC_ADDR_HI 0x1540 313 314 #define AGE_DESC_RD_ADDR_LO 0x1544 315 316 #define AGE_DESC_RRD_ADDR_LO 0x1548 317 318 #define AGE_DESC_TPD_ADDR_LO 0x154C 319 320 #define AGE_DESC_CMB_ADDR_LO 0x1550 321 322 #define AGE_DESC_SMB_ADDR_LO 0x1554 323 324 #define AGE_DESC_RRD_RD_CNT 0x1558 325 #define DESC_RD_CNT_MASK 0x000007FF 326 #define DESC_RRD_CNT_MASK 0x07FF0000 327 #define DESC_RD_CNT_SHIFT 0 328 #define DESC_RRD_CNT_SHIFT 16 329 330 #define AGE_DESC_TPD_CNT 0x155C 331 #define DESC_TPD_CNT_MASK 0x00003FF 332 #define DESC_TPD_CNT_SHIFT 0 333 334 #define AGE_TXQ_CFG 0x1580 335 #define TXQ_CFG_TPD_BURST_MASK 0x0000001F 336 #define TXQ_CFG_ENB 0x00000020 337 #define TXQ_CFG_ENHANCED_MODE 0x00000040 338 #define TXQ_CFG_TPD_FETCH_THRESH_MASK 0x00003F00 339 #define TXQ_CFG_TX_FIFO_BURST_MASK 0xFFFF0000 340 #define TXQ_CFG_TPD_BURST_SHIFT 0 341 #define TXQ_CFG_TPD_BURST_DEFAULT 4 342 #define TXQ_CFG_TPD_FETCH_THRESH_SHIFT 8 343 #define TXQ_CFG_TPD_FETCH_DEFAULT 16 344 #define TXQ_CFG_TX_FIFO_BURST_SHIFT 16 345 #define TXQ_CFG_TX_FIFO_BURST_DEFAULT 256 346 347 #define AGE_TX_JUMBO_TPD_TH_IPG 0x1584 348 #define TX_JUMBO_TPD_TH_MASK 0x000007FF 349 #define TX_JUMBO_TPD_IPG_MASK 0x001F0000 350 #define TX_JUMBO_TPD_TH_SHIFT 0 351 #define TX_JUMBO_TPD_IPG_SHIFT 16 352 #define TX_JUMBO_TPD_IPG_DEFAULT 1 353 354 #define AGE_RXQ_CFG 0x15A0 355 #define RXQ_CFG_RD_BURST_MASK 0x000000FF 356 #define RXQ_CFG_RRD_BURST_THRESH_MASK 0x0000FF00 357 #define RXQ_CFG_RD_PREF_MIN_IPG_MASK 0x001F0000 358 #define RXQ_CFG_CUT_THROUGH_ENB 0x40000000 359 #define RXQ_CFG_ENB 0x80000000 360 #define RXQ_CFG_RD_BURST_SHIFT 0 361 #define RXQ_CFG_RD_BURST_DEFAULT 8 362 #define RXQ_CFG_RRD_BURST_THRESH_SHIFT 8 363 #define RXQ_CFG_RRD_BURST_THRESH_DEFAULT 8 364 #define RXQ_CFG_RD_PREF_MIN_IPG_SHIFT 16 365 #define RXQ_CFG_RD_PREF_MIN_IPG_DEFAULT 1 366 367 #define AGE_RXQ_JUMBO_CFG 0x15A4 368 #define RXQ_JUMBO_CFG_SZ_THRESH_MASK 0x000007FF 369 #define RXQ_JUMBO_CFG_LKAH_MASK 0x00007800 370 #define RXQ_JUMBO_CFG_RRD_TIMER_MASK 0xFFFF0000 371 #define RXQ_JUMBO_CFG_SZ_THRESH_SHIFT 0 372 #define RXQ_JUMBO_CFG_LKAH_SHIFT 11 373 #define RXQ_JUMBO_CFG_LKAH_DEFAULT 0x01 374 #define RXQ_JUMBO_CFG_RRD_TIMER_SHIFT 16 375 376 #define AGE_RXQ_FIFO_PAUSE_THRESH 0x15A8 377 #define RXQ_FIFO_PAUSE_THRESH_LO_MASK 0x00000FFF 378 #define RXQ_FIFO_PAUSE_THRESH_HI_MASK 0x0FFF000 379 #define RXQ_FIFO_PAUSE_THRESH_LO_SHIFT 0 380 #define RXQ_FIFO_PAUSE_THRESH_HI_SHIFT 16 381 382 #define AGE_RXQ_RRD_PAUSE_THRESH 0x15AC 383 #define RXQ_RRD_PAUSE_THRESH_HI_MASK 0x00000FFF 384 #define RXQ_RRD_PAUSE_THRESH_LO_MASK 0x0FFF0000 385 #define RXQ_RRD_PAUSE_THRESH_HI_SHIFT 0 386 #define RXQ_RRD_PAUSE_THRESH_LO_SHIFT 16 387 388 #define AGE_DMA_CFG 0x15C0 389 #define DMA_CFG_IN_ORDER 0x00000001 390 #define DMA_CFG_ENH_ORDER 0x00000002 391 #define DMA_CFG_OUT_ORDER 0x00000004 392 #define DMA_CFG_RCB_64 0x00000000 393 #define DMA_CFG_RCB_128 0x00000008 394 #define DMA_CFG_RD_BURST_128 0x00000000 395 #define DMA_CFG_RD_BURST_256 0x00000010 396 #define DMA_CFG_RD_BURST_512 0x00000020 397 #define DMA_CFG_RD_BURST_1024 0x00000030 398 #define DMA_CFG_RD_BURST_2048 0x00000040 399 #define DMA_CFG_RD_BURST_4096 0x00000050 400 #define DMA_CFG_WR_BURST_128 0x00000000 401 #define DMA_CFG_WR_BURST_256 0x00000080 402 #define DMA_CFG_WR_BURST_512 0x00000100 403 #define DMA_CFG_WR_BURST_1024 0x00000180 404 #define DMA_CFG_WR_BURST_2048 0x00000200 405 #define DMA_CFG_WR_BURST_4096 0x00000280 406 #define DMA_CFG_RD_ENB 0x00000400 407 #define DMA_CFG_WR_ENB 0x00000800 408 #define DMA_CFG_RD_BURST_MASK 0x07 409 #define DMA_CFG_RD_BURST_SHIFT 4 410 #define DMA_CFG_WR_BURST_MASK 0x07 411 #define DMA_CFG_WR_BURST_SHIFT 7 412 413 #define AGE_CSMB_CTRL 0x15D0 414 #define CSMB_CTRL_CMB_KICK 0x00000001 415 #define CSMB_CTRL_SMB_KICK 0x00000002 416 #define CSMB_CTRL_CMB_ENB 0x00000004 417 #define CSMB_CTRL_SMB_ENB 0x00000008 418 419 /* CMB DMA Write Threshold Register */ 420 #define AGE_CMB_WR_THRESH 0x15D4 421 #define CMB_WR_THRESH_RRD_MASK 0x000007FF 422 #define CMB_WR_THRESH_TPD_MASK 0x07FF0000 423 #define CMB_WR_THRESH_RRD_SHIFT 0 424 #define CMB_WR_THRESH_RRD_DEFAULT 4 425 #define CMB_WR_THRESH_TPD_SHIFT 16 426 #define CMB_WR_THRESH_TPD_DEFAULT 4 427 428 /* RX/TX count-down timer to trigger CMB-write. */ 429 #define AGE_CMB_WR_TIMER 0x15D8 430 #define CMB_WR_TIMER_RX_MASK 0x0000FFFF 431 #define CMB_WR_TIMER_TX_MASK 0xFFFF0000 432 #define CMB_WR_TIMER_RX_SHIFT 0 433 #define CMB_WR_TIMER_TX_SHIFT 16 434 435 /* Number of packet received since last CMB write */ 436 #define AGE_CMB_RX_PKT_CNT 0x15DC 437 438 /* Number of packet transmitted since last CMB write */ 439 #define AGE_CMB_TX_PKT_CNT 0x15E0 440 441 /* SMB auto DMA timer register */ 442 #define AGE_SMB_TIMER 0x15E4 443 444 #define AGE_MBOX 0x15F0 445 #define MBOX_RD_PROD_IDX_MASK 0x000007FF 446 #define MBOX_RRD_CONS_IDX_MASK 0x003FF800 447 #define MBOX_TD_PROD_IDX_MASK 0xFFC00000 448 #define MBOX_RD_PROD_IDX_SHIFT 0 449 #define MBOX_RRD_CONS_IDX_SHIFT 11 450 #define MBOX_TD_PROD_IDX_SHIFT 22 451 452 #define AGE_INTR_STATUS 0x1600 453 #define INTR_SMB 0x00000001 454 #define INTR_MOD_TIMER 0x00000002 455 #define INTR_MANUAL_TIMER 0x00000004 456 #define INTR_RX_FIFO_OFLOW 0x00000008 457 #define INTR_RD_UNDERRUN 0x00000010 458 #define INTR_RRD_OFLOW 0x00000020 459 #define INTR_TX_FIFO_UNDERRUN 0x00000040 460 #define INTR_LINK_CHG 0x00000080 461 #define INTR_HOST_RD_UNDERRUN 0x00000100 462 #define INTR_HOST_RRD_OFLOW 0x00000200 463 #define INTR_DMA_RD_TO_RST 0x00000400 464 #define INTR_DMA_WR_TO_RST 0x00000800 465 #define INTR_GPHY 0x00001000 466 #define INTR_RX_PKT 0x00010000 467 #define INTR_TX_PKT 0x00020000 468 #define INTR_TX_DMA 0x00040000 469 #define INTR_RX_DMA 0x00080000 470 #define INTR_CMB_RX 0x00100000 471 #define INTR_CMB_TX 0x00200000 472 #define INTR_MAC_RX 0x00400000 473 #define INTR_MAC_TX 0x00800000 474 #define INTR_UNDERRUN 0x01000000 475 #define INTR_FRAME_ERROR 0x02000000 476 #define INTR_FRAME_OK 0x04000000 477 #define INTR_CSUM_ERROR 0x08000000 478 #define INTR_PHY_LINK_DOWN 0x10000000 479 #define INTR_DIS_SMB 0x20000000 480 #define INTR_DIS_DMA 0x40000000 481 #define INTR_DIS_INT 0x80000000 482 483 /* Interrupt Mask Register */ 484 #define AGE_INTR_MASK 0x1604 485 486 #define AGE_INTRS \ 487 (INTR_SMB | INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | \ 488 INTR_CMB_TX | INTR_CMB_RX) 489 490 /* Statistics counters collected by the MAC. */ 491 struct smb { 492 /* Rx stats. */ 493 uint32_t rx_frames; 494 uint32_t rx_bcast_frames; 495 uint32_t rx_mcast_frames; 496 uint32_t rx_pause_frames; 497 uint32_t rx_control_frames; 498 uint32_t rx_crcerrs; 499 uint32_t rx_lenerrs; 500 uint32_t rx_bytes; 501 uint32_t rx_runts; 502 uint32_t rx_fragments; 503 uint32_t rx_pkts_64; 504 uint32_t rx_pkts_65_127; 505 uint32_t rx_pkts_128_255; 506 uint32_t rx_pkts_256_511; 507 uint32_t rx_pkts_512_1023; 508 uint32_t rx_pkts_1024_1518; 509 uint32_t rx_pkts_1519_max; 510 uint32_t rx_pkts_truncated; 511 uint32_t rx_fifo_oflows; 512 uint32_t rx_desc_oflows; 513 uint32_t rx_alignerrs; 514 uint32_t rx_bcast_bytes; 515 uint32_t rx_mcast_bytes; 516 uint32_t rx_pkts_filtered; 517 /* Tx stats. */ 518 uint32_t tx_frames; 519 uint32_t tx_bcast_frames; 520 uint32_t tx_mcast_frames; 521 uint32_t tx_pause_frames; 522 uint32_t tx_excess_defer; 523 uint32_t tx_control_frames; 524 uint32_t tx_deferred; 525 uint32_t tx_bytes; 526 uint32_t tx_pkts_64; 527 uint32_t tx_pkts_65_127; 528 uint32_t tx_pkts_128_255; 529 uint32_t tx_pkts_256_511; 530 uint32_t tx_pkts_512_1023; 531 uint32_t tx_pkts_1024_1518; 532 uint32_t tx_pkts_1519_max; 533 uint32_t tx_single_colls; 534 uint32_t tx_multi_colls; 535 uint32_t tx_late_colls; 536 uint32_t tx_excess_colls; 537 uint32_t tx_underrun; 538 uint32_t tx_desc_underrun; 539 uint32_t tx_lenerrs; 540 uint32_t tx_pkts_truncated; 541 uint32_t tx_bcast_bytes; 542 uint32_t tx_mcast_bytes; 543 uint32_t updated; 544 } __packed; 545 546 /* Coalescing message block */ 547 struct cmb { 548 uint32_t intr_status; 549 uint32_t rprod_cons; 550 #define RRD_PROD_MASK 0x0000FFFF 551 #define RD_CONS_MASK 0xFFFF0000 552 #define RRD_PROD_SHIFT 0 553 #define RD_CONS_SHIFT 16 554 uint32_t tpd_cons; 555 #define CMB_UPDATED 0x00000001 556 #define TPD_CONS_MASK 0xFFFF0000 557 #define TPD_CONS_SHIFT 16 558 } __packed; 559 560 /* Rx return descriptor */ 561 struct rx_rdesc { 562 uint32_t index; 563 #define AGE_RRD_NSEGS_MASK 0x000000FF 564 #define AGE_RRD_CONS_MASK 0xFFFF0000 565 #define AGE_RRD_NSEGS_SHIFT 0 566 #define AGE_RRD_CONS_SHIFT 16 567 uint32_t len; 568 #define AGE_RRD_CSUM_MASK 0x0000FFFF 569 #define AGE_RRD_LEN_MASK 0xFFFF0000 570 #define AGE_RRD_CSUM_SHIFT 0 571 #define AGE_RRD_LEN_SHIFT 16 572 uint32_t flags; 573 #define AGE_RRD_ETHERNET 0x00000080 574 #define AGE_RRD_VLAN 0x00000100 575 #define AGE_RRD_ERROR 0x00000200 576 #define AGE_RRD_IPV4 0x00000400 577 #define AGE_RRD_UDP 0x00000800 578 #define AGE_RRD_TCP 0x00001000 579 #define AGE_RRD_BCAST 0x00002000 580 #define AGE_RRD_MCAST 0x00004000 581 #define AGE_RRD_PAUSE 0x00008000 582 #define AGE_RRD_CRC 0x00010000 583 #define AGE_RRD_CODE 0x00020000 584 #define AGE_RRD_DRIBBLE 0x00040000 585 #define AGE_RRD_RUNT 0x00080000 586 #define AGE_RRD_OFLOW 0x00100000 587 #define AGE_RRD_TRUNC 0x00200000 588 #define AGE_RRD_IPCSUM_NOK 0x00400000 589 #define AGE_RRD_TCP_UDPCSUM_NOK 0x00800000 590 #define AGE_RRD_LENGTH_NOK 0x01000000 591 #define AGE_RRD_DES_ADDR_FILTERED 0x02000000 592 uint32_t vtags; 593 #define AGE_RRD_VLAN_MASK 0xFFFF0000 594 #define AGE_RRD_VLAN_SHIFT 16 595 } __packed; 596 597 #define AGE_RX_NSEGS(x) \ 598 (((x) & AGE_RRD_NSEGS_MASK) >> AGE_RRD_NSEGS_SHIFT) 599 #define AGE_RX_CONS(x) \ 600 (((x) & AGE_RRD_CONS_MASK) >> AGE_RRD_CONS_SHIFT) 601 #define AGE_RX_CSUM(x) \ 602 (((x) & AGE_RRD_CSUM_MASK) >> AGE_RRD_CSUM_SHIFT) 603 #define AGE_RX_BYTES(x) \ 604 (((x) & AGE_RRD_LEN_MASK) >> AGE_RRD_LEN_SHIFT) 605 #define AGE_RX_VLAN(x) \ 606 (((x) & AGE_RRD_VLAN_MASK) >> AGE_RRD_VLAN_SHIFT) 607 #define AGE_RX_VLAN_TAG(x) \ 608 (((x) >> 4) | (((x) & 7) << 13) | (((x) & 8) << 9)) 609 610 /* Rx descriptor. */ 611 struct rx_desc { 612 uint64_t addr; 613 uint32_t len; 614 #define AGE_RD_LEN_MASK 0x0000FFFF 615 #define AGE_CONS_UPD_REQ_MASK 0xFFFF0000 616 #define AGE_RD_LEN_SHIFT 0 617 #define AGE_CONS_UPD_REQ_SHIFT 16 618 } __packed; 619 620 /* Tx descriptor. */ 621 struct tx_desc { 622 uint64_t addr; 623 uint32_t len; 624 #define AGE_TD_VLAN_MASK 0xFFFF0000 625 #define AGE_TD_PKT_INT 0x00008000 626 #define AGE_TD_DMA_INT 0x00004000 627 #define AGE_TD_BUFLEN_MASK 0x00003FFF 628 #define AGE_TD_VLAN_SHIFT 16 629 #define AGE_TX_VLAN_TAG(x) \ 630 (((x) << 4) | ((x) >> 13) | (((x) >> 9) & 8)) 631 #define AGE_TD_BUFLEN_SHIFT 0 632 #define AGE_TX_BYTES(x) \ 633 (((x) << AGE_TD_BUFLEN_SHIFT) & AGE_TD_BUFLEN_MASK) 634 uint32_t flags; 635 #define AGE_TD_TSO_MSS 0xFFF80000 636 #define AGE_TD_TSO_HDR 0x00040000 637 #define AGE_TD_TSO_TCPHDR_LEN 0x0003C000 638 #define AGE_TD_IPHDR_LEN 0x00003C00 639 #define AGE_TD_LLC_SNAP 0x00000200 640 #define AGE_TD_VLAN_TAGGED 0x00000100 641 #define AGE_TD_UDPCSUM 0x00000080 642 #define AGE_TD_TCPCSUM 0x00000040 643 #define AGE_TD_IPCSUM 0x00000020 644 #define AGE_TD_TSO_IPV4 0x00000010 645 #define AGE_TD_TSO_IPV6 0x00000012 646 #define AGE_TD_CSUM 0x00000008 647 #define AGE_TD_INSERT_VLAN_TAG 0x00000004 648 #define AGE_TD_COALESCE 0x00000002 649 #define AGE_TD_EOP 0x00000001 650 651 #define AGE_TD_CSUM_PLOADOFFSET 0x00FF0000 652 #define AGE_TD_CSUM_XSUMOFFSET 0xFF000000 653 #define AGE_TD_CSUM_XSUMOFFSET_SHIFT 24 654 #define AGE_TD_CSUM_PLOADOFFSET_SHIFT 16 655 #define AGE_TD_TSO_MSS_SHIFT 19 656 #define AGE_TD_TSO_TCPHDR_LEN_SHIFT 14 657 #define AGE_TD_IPHDR_LEN_SHIFT 10 658 } __packed; 659 660 #define AGE_TX_RING_CNT 256 661 #define AGE_RX_RING_CNT 256 662 #define AGE_RR_RING_CNT (AGE_TX_RING_CNT + AGE_RX_RING_CNT) 663 /* The following ring alignments are just guessing. */ 664 #define AGE_TX_RING_ALIGN 16 665 #define AGE_RX_RING_ALIGN 16 666 #define AGE_RR_RING_ALIGN 16 667 #define AGE_CMB_ALIGN 16 668 #define AGE_SMB_ALIGN 16 669 670 #define AGE_TSO_MAXSEGSIZE 4096 671 #define AGE_TSO_MAXSIZE (65535 + sizeof(struct ether_vlan_header)) 672 #define AGE_MAXTXSEGS 32 673 674 #define AGE_ADDR_LO(x) ((uint64_t) (x) & 0xFFFFFFFF) 675 #define AGE_ADDR_HI(x) ((uint64_t) (x) >> 32) 676 677 #define AGE_MSI_MESSAGES 1 678 #define AGE_MSIX_MESSAGES 1 679 680 #define AGE_JUMBO_FRAMELEN 10240 681 #define AGE_JUMBO_MTU \ 682 (AGE_JUMBO_FRAMELEN - EVL_ENCAPLEN - \ 683 ETHER_HDR_LEN - ETHER_CRC_LEN) 684 685 #define AGE_DESC_INC(x, y) ((x) = ((x) + 1) % (y)) 686 687 #define AGE_PROC_MIN 30 688 #define AGE_PROC_MAX (AGE_RX_RING_CNT - 1) 689 #define AGE_PROC_DEFAULT (AGE_RX_RING_CNT / 2) 690 691 struct age_txdesc { 692 struct mbuf *tx_m; 693 bus_dmamap_t tx_dmamap; 694 struct tx_desc *tx_desc; 695 }; 696 697 struct age_rxdesc { 698 struct mbuf *rx_m; 699 bus_dmamap_t rx_dmamap; 700 struct rx_desc *rx_desc; 701 }; 702 703 struct age_chain_data{ 704 struct age_txdesc age_txdesc[AGE_TX_RING_CNT]; 705 struct age_rxdesc age_rxdesc[AGE_RX_RING_CNT]; 706 bus_dmamap_t age_tx_ring_map; 707 bus_dma_segment_t age_tx_ring_seg; 708 bus_dmamap_t age_rx_ring_map; 709 bus_dma_segment_t age_rx_ring_seg; 710 bus_dmamap_t age_rx_sparemap; 711 bus_dmamap_t age_rr_ring_map; 712 bus_dma_segment_t age_rr_ring_seg; 713 bus_dmamap_t age_cmb_block_map; 714 bus_dma_segment_t age_cmb_block_seg; 715 bus_dmamap_t age_smb_block_map; 716 bus_dma_segment_t age_smb_block_seg; 717 718 int age_tx_prod; 719 int age_tx_cons; 720 int age_tx_cnt; 721 int age_rx_cons; 722 int age_rr_cons; 723 int age_rxlen; 724 725 struct mbuf *age_rxhead; 726 struct mbuf *age_rxtail; 727 struct mbuf *age_rxprev_tail; 728 }; 729 730 struct age_ring_data { 731 struct tx_desc *age_tx_ring; 732 bus_dma_segment_t age_tx_ring_seg; 733 bus_addr_t age_tx_ring_paddr; 734 struct rx_desc *age_rx_ring; 735 bus_dma_segment_t age_rx_ring_seg; 736 bus_addr_t age_rx_ring_paddr; 737 struct rx_rdesc *age_rr_ring; 738 bus_dma_segment_t age_rr_ring_seg; 739 bus_addr_t age_rr_ring_paddr; 740 struct cmb *age_cmb_block; 741 bus_dma_segment_t age_cmb_block_seg; 742 bus_addr_t age_cmb_block_paddr; 743 struct smb *age_smb_block; 744 bus_dma_segment_t age_smb_block_seg; 745 bus_addr_t age_smb_block_paddr; 746 }; 747 748 #define AGE_TX_RING_SZ \ 749 (sizeof(struct tx_desc) * AGE_TX_RING_CNT) 750 #define AGE_RX_RING_SZ \ 751 (sizeof(struct rx_desc) * AGE_RX_RING_CNT) 752 #define AGE_RR_RING_SZ \ 753 (sizeof(struct rx_rdesc) * AGE_RR_RING_CNT) 754 #define AGE_CMB_BLOCK_SZ sizeof(struct cmb) 755 #define AGE_SMB_BLOCK_SZ sizeof(struct smb) 756 757 struct age_stats { 758 /* Rx stats. */ 759 uint64_t rx_frames; 760 uint64_t rx_bcast_frames; 761 uint64_t rx_mcast_frames; 762 uint32_t rx_pause_frames; 763 uint32_t rx_control_frames; 764 uint32_t rx_crcerrs; 765 uint32_t rx_lenerrs; 766 uint64_t rx_bytes; 767 uint32_t rx_runts; 768 uint64_t rx_fragments; 769 uint64_t rx_pkts_64; 770 uint64_t rx_pkts_65_127; 771 uint64_t rx_pkts_128_255; 772 uint64_t rx_pkts_256_511; 773 uint64_t rx_pkts_512_1023; 774 uint64_t rx_pkts_1024_1518; 775 uint64_t rx_pkts_1519_max; 776 uint64_t rx_pkts_truncated; 777 uint32_t rx_fifo_oflows; 778 uint32_t rx_desc_oflows; 779 uint32_t rx_alignerrs; 780 uint64_t rx_bcast_bytes; 781 uint64_t rx_mcast_bytes; 782 uint64_t rx_pkts_filtered; 783 /* Tx stats. */ 784 uint64_t tx_frames; 785 uint64_t tx_bcast_frames; 786 uint64_t tx_mcast_frames; 787 uint32_t tx_pause_frames; 788 uint32_t tx_excess_defer; 789 uint32_t tx_control_frames; 790 uint32_t tx_deferred; 791 uint64_t tx_bytes; 792 uint64_t tx_pkts_64; 793 uint64_t tx_pkts_65_127; 794 uint64_t tx_pkts_128_255; 795 uint64_t tx_pkts_256_511; 796 uint64_t tx_pkts_512_1023; 797 uint64_t tx_pkts_1024_1518; 798 uint64_t tx_pkts_1519_max; 799 uint32_t tx_single_colls; 800 uint32_t tx_multi_colls; 801 uint32_t tx_late_colls; 802 uint32_t tx_excess_colls; 803 uint32_t tx_underrun; 804 uint32_t tx_desc_underrun; 805 uint32_t tx_lenerrs; 806 uint32_t tx_pkts_truncated; 807 uint64_t tx_bcast_bytes; 808 uint64_t tx_mcast_bytes; 809 }; 810 811 /* 812 * Software state per device. 813 */ 814 struct age_softc { 815 struct device sc_dev; 816 struct arpcom sc_arpcom; 817 818 bus_space_tag_t sc_mem_bt; 819 bus_space_handle_t sc_mem_bh; 820 bus_size_t sc_mem_size; 821 bus_dma_tag_t sc_dmat; 822 pci_chipset_tag_t sc_pct; 823 pcitag_t sc_pcitag; 824 825 void *sc_irq_handle; 826 827 struct mii_data sc_miibus; 828 int age_rev; 829 int age_chip_rev; 830 int age_phyaddr; 831 832 uint8_t age_eaddr[ETHER_ADDR_LEN]; 833 uint32_t age_dma_rd_burst; 834 uint32_t age_dma_wr_burst; 835 836 uint32_t age_flags; 837 #define AGE_FLAG_PCIE 0x0001 838 #define AGE_FLAG_PCIX 0x0002 839 #define AGE_FLAG_MSI 0x0004 840 #define AGE_FLAG_MSIX 0x0008 841 #define AGE_FLAG_PMCAP 0x0010 842 #define AGE_FLAG_DETACH 0x4000 843 #define AGE_FLAG_LINK 0x8000 844 845 struct timeout age_tick_ch; 846 struct age_stats age_stat; 847 struct age_chain_data age_cdata; 848 struct age_ring_data age_rdata; 849 int age_process_limit; 850 int age_int_mod; 851 int age_max_frame_size; 852 int age_morework; 853 int age_rr_prod; 854 int age_tpd_cons; 855 856 int age_txd_spare; 857 }; 858 859 /* Register access macros. */ 860 #define CSR_WRITE_4(sc, reg, val) \ 861 bus_space_write_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val)) 862 #define CSR_WRITE_2(sc, reg, val) \ 863 bus_space_write_2((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val)) 864 #define CSR_READ_2(sc, reg) \ 865 bus_space_read_2((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg)) 866 #define CSR_READ_4(sc, reg) \ 867 bus_space_read_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg)) 868 869 870 #define AGE_COMMIT_MBOX(_sc) \ 871 do { \ 872 CSR_WRITE_4(_sc, AGE_MBOX, \ 873 (((_sc)->age_cdata.age_rx_cons << MBOX_RD_PROD_IDX_SHIFT) & \ 874 MBOX_RD_PROD_IDX_MASK) | \ 875 (((_sc)->age_cdata.age_rr_cons << \ 876 MBOX_RRD_CONS_IDX_SHIFT) & MBOX_RRD_CONS_IDX_MASK) | \ 877 (((_sc)->age_cdata.age_tx_prod << MBOX_TD_PROD_IDX_SHIFT) & \ 878 MBOX_TD_PROD_IDX_MASK)); \ 879 } while (0) 880 881 #define AGE_RXCHAIN_RESET(_sc) \ 882 do { \ 883 (_sc)->age_cdata.age_rxhead = NULL; \ 884 (_sc)->age_cdata.age_rxtail = NULL; \ 885 (_sc)->age_cdata.age_rxprev_tail = NULL; \ 886 (_sc)->age_cdata.age_rxlen = 0; \ 887 } while (0) 888 889 #define AGE_TX_TIMEOUT 5 890 #define AGE_RESET_TIMEOUT 100 891 #define AGE_TIMEOUT 1000 892 #define AGE_PHY_TIMEOUT 1000 893 894 #endif /* _IF_AGEREG_H */ 895