1 /* $OpenBSD: if_age.c,v 1.16 2011/08/26 07:52:22 kevlo Exp $ */ 2 3 /*- 4 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* Driver for Attansic Technology Corp. L1 Gigabit Ethernet. */ 31 32 #include "bpfilter.h" 33 #include "vlan.h" 34 35 #include <sys/param.h> 36 #include <sys/endian.h> 37 #include <sys/systm.h> 38 #include <sys/types.h> 39 #include <sys/sockio.h> 40 #include <sys/mbuf.h> 41 #include <sys/queue.h> 42 #include <sys/kernel.h> 43 #include <sys/device.h> 44 #include <sys/timeout.h> 45 #include <sys/socket.h> 46 47 #include <machine/bus.h> 48 49 #include <net/if.h> 50 #include <net/if_dl.h> 51 #include <net/if_media.h> 52 53 #ifdef INET 54 #include <netinet/in.h> 55 #include <netinet/in_systm.h> 56 #include <netinet/in_var.h> 57 #include <netinet/ip.h> 58 #include <netinet/if_ether.h> 59 #endif 60 61 #include <net/if_types.h> 62 #include <net/if_vlan_var.h> 63 64 #if NBPFILTER > 0 65 #include <net/bpf.h> 66 #endif 67 68 #include <dev/rndvar.h> 69 70 #include <dev/mii/mii.h> 71 #include <dev/mii/miivar.h> 72 73 #include <dev/pci/pcireg.h> 74 #include <dev/pci/pcivar.h> 75 #include <dev/pci/pcidevs.h> 76 77 #include <dev/pci/if_agereg.h> 78 79 int age_match(struct device *, void *, void *); 80 void age_attach(struct device *, struct device *, void *); 81 int age_detach(struct device *, int); 82 83 int age_miibus_readreg(struct device *, int, int); 84 void age_miibus_writereg(struct device *, int, int, int); 85 void age_miibus_statchg(struct device *); 86 87 int age_init(struct ifnet *); 88 int age_ioctl(struct ifnet *, u_long, caddr_t); 89 void age_start(struct ifnet *); 90 void age_watchdog(struct ifnet *); 91 void age_mediastatus(struct ifnet *, struct ifmediareq *); 92 int age_mediachange(struct ifnet *); 93 94 int age_intr(void *); 95 int age_dma_alloc(struct age_softc *); 96 void age_dma_free(struct age_softc *); 97 void age_get_macaddr(struct age_softc *); 98 void age_phy_reset(struct age_softc *); 99 100 int age_encap(struct age_softc *, struct mbuf **); 101 void age_init_tx_ring(struct age_softc *); 102 int age_init_rx_ring(struct age_softc *); 103 void age_init_rr_ring(struct age_softc *); 104 void age_init_cmb_block(struct age_softc *); 105 void age_init_smb_block(struct age_softc *); 106 int age_newbuf(struct age_softc *, struct age_rxdesc *); 107 void age_mac_config(struct age_softc *); 108 void age_txintr(struct age_softc *, int); 109 void age_rxeof(struct age_softc *sc, struct rx_rdesc *); 110 void age_rxintr(struct age_softc *, int); 111 void age_tick(void *); 112 void age_reset(struct age_softc *); 113 void age_stop(struct age_softc *); 114 void age_stats_update(struct age_softc *); 115 void age_stop_txmac(struct age_softc *); 116 void age_stop_rxmac(struct age_softc *); 117 void age_rxvlan(struct age_softc *sc); 118 void age_iff(struct age_softc *); 119 120 const struct pci_matchid age_devices[] = { 121 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L1 } 122 }; 123 124 struct cfattach age_ca = { 125 sizeof (struct age_softc), age_match, age_attach 126 }; 127 128 struct cfdriver age_cd = { 129 NULL, "age", DV_IFNET 130 }; 131 132 int agedebug = 0; 133 #define DPRINTF(x) do { if (agedebug) printf x; } while (0) 134 135 #define AGE_CSUM_FEATURES (M_TCP_CSUM_OUT | M_UDP_CSUM_OUT) 136 137 int 138 age_match(struct device *dev, void *match, void *aux) 139 { 140 return pci_matchbyid((struct pci_attach_args *)aux, age_devices, 141 sizeof (age_devices) / sizeof (age_devices[0])); 142 } 143 144 void 145 age_attach(struct device *parent, struct device *self, void *aux) 146 { 147 struct age_softc *sc = (struct age_softc *)self; 148 struct pci_attach_args *pa = aux; 149 pci_chipset_tag_t pc = pa->pa_pc; 150 pci_intr_handle_t ih; 151 const char *intrstr; 152 struct ifnet *ifp; 153 pcireg_t memtype; 154 int error = 0; 155 156 /* 157 * Allocate IO memory 158 */ 159 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, AGE_PCIR_BAR); 160 if (pci_mapreg_map(pa, AGE_PCIR_BAR, memtype, 0, &sc->sc_mem_bt, 161 &sc->sc_mem_bh, NULL, &sc->sc_mem_size, 0)) { 162 printf(": can't map mem space\n"); 163 return; 164 } 165 166 if (pci_intr_map_msi(pa, &ih) != 0 && pci_intr_map(pa, &ih) != 0) { 167 printf(": can't map interrupt\n"); 168 goto fail; 169 } 170 171 /* 172 * Allocate IRQ 173 */ 174 intrstr = pci_intr_string(pc, ih); 175 sc->sc_irq_handle = pci_intr_establish(pc, ih, IPL_NET, age_intr, sc, 176 sc->sc_dev.dv_xname); 177 if (sc->sc_irq_handle == NULL) { 178 printf(": could not establish interrupt"); 179 if (intrstr != NULL) 180 printf(" at %s", intrstr); 181 printf("\n"); 182 goto fail; 183 } 184 printf(": %s", intrstr); 185 186 sc->sc_dmat = pa->pa_dmat; 187 sc->sc_pct = pa->pa_pc; 188 sc->sc_pcitag = pa->pa_tag; 189 190 /* Set PHY address. */ 191 sc->age_phyaddr = AGE_PHY_ADDR; 192 193 /* Reset PHY. */ 194 age_phy_reset(sc); 195 196 /* Reset the ethernet controller. */ 197 age_reset(sc); 198 199 /* Get PCI and chip id/revision. */ 200 sc->age_rev = PCI_REVISION(pa->pa_class); 201 sc->age_chip_rev = CSR_READ_4(sc, AGE_MASTER_CFG) >> 202 MASTER_CHIP_REV_SHIFT; 203 if (agedebug) { 204 printf("%s: PCI device revision : 0x%04x\n", 205 sc->sc_dev.dv_xname, sc->age_rev); 206 printf("%s: Chip id/revision : 0x%04x\n", 207 sc->sc_dev.dv_xname, sc->age_chip_rev); 208 } 209 210 if (agedebug) { 211 printf("%s: %d Tx FIFO, %d Rx FIFO\n", sc->sc_dev.dv_xname, 212 CSR_READ_4(sc, AGE_SRAM_TX_FIFO_LEN), 213 CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN)); 214 } 215 216 /* Set max allowable DMA size. */ 217 sc->age_dma_rd_burst = DMA_CFG_RD_BURST_128; 218 sc->age_dma_wr_burst = DMA_CFG_WR_BURST_128; 219 220 /* Allocate DMA stuffs */ 221 error = age_dma_alloc(sc); 222 if (error) 223 goto fail; 224 225 /* Load station address. */ 226 age_get_macaddr(sc); 227 228 ifp = &sc->sc_arpcom.ac_if; 229 ifp->if_softc = sc; 230 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 231 ifp->if_ioctl = age_ioctl; 232 ifp->if_start = age_start; 233 ifp->if_watchdog = age_watchdog; 234 ifp->if_baudrate = IF_Gbps(1); 235 IFQ_SET_MAXLEN(&ifp->if_snd, AGE_TX_RING_CNT - 1); 236 IFQ_SET_READY(&ifp->if_snd); 237 bcopy(sc->age_eaddr, sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN); 238 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 239 240 ifp->if_capabilities = IFCAP_VLAN_MTU; 241 242 #ifdef AGE_CHECKSUM 243 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 244 IFCAP_CSUM_UDPv4; 245 #endif 246 247 #if NVLAN > 0 248 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 249 #endif 250 251 printf(", address %s\n", ether_sprintf(sc->sc_arpcom.ac_enaddr)); 252 253 /* Set up MII bus. */ 254 sc->sc_miibus.mii_ifp = ifp; 255 sc->sc_miibus.mii_readreg = age_miibus_readreg; 256 sc->sc_miibus.mii_writereg = age_miibus_writereg; 257 sc->sc_miibus.mii_statchg = age_miibus_statchg; 258 259 ifmedia_init(&sc->sc_miibus.mii_media, 0, age_mediachange, 260 age_mediastatus); 261 mii_attach(self, &sc->sc_miibus, 0xffffffff, MII_PHY_ANY, 262 MII_OFFSET_ANY, MIIF_DOPAUSE); 263 264 if (LIST_FIRST(&sc->sc_miibus.mii_phys) == NULL) { 265 printf("%s: no PHY found!\n", sc->sc_dev.dv_xname); 266 ifmedia_add(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL, 267 0, NULL); 268 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL); 269 } else 270 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_AUTO); 271 272 if_attach(ifp); 273 ether_ifattach(ifp); 274 275 timeout_set(&sc->age_tick_ch, age_tick, sc); 276 277 return; 278 fail: 279 age_dma_free(sc); 280 if (sc->sc_irq_handle != NULL) 281 pci_intr_disestablish(pc, sc->sc_irq_handle); 282 if (sc->sc_mem_size) 283 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 284 } 285 286 int 287 age_detach(struct device *self, int flags) 288 { 289 struct age_softc *sc = (struct age_softc *)self; 290 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 291 int s; 292 293 s = splnet(); 294 age_stop(sc); 295 splx(s); 296 297 mii_detach(&sc->sc_miibus, MII_PHY_ANY, MII_OFFSET_ANY); 298 299 /* Delete all remaining media. */ 300 ifmedia_delete_instance(&sc->sc_miibus.mii_media, IFM_INST_ANY); 301 302 ether_ifdetach(ifp); 303 if_detach(ifp); 304 age_dma_free(sc); 305 306 if (sc->sc_irq_handle != NULL) { 307 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 308 sc->sc_irq_handle = NULL; 309 } 310 311 return (0); 312 } 313 314 /* 315 * Read a PHY register on the MII of the L1. 316 */ 317 int 318 age_miibus_readreg(struct device *dev, int phy, int reg) 319 { 320 struct age_softc *sc = (struct age_softc *)dev; 321 uint32_t v; 322 int i; 323 324 if (phy != sc->age_phyaddr) 325 return (0); 326 327 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 328 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 329 for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 330 DELAY(1); 331 v = CSR_READ_4(sc, AGE_MDIO); 332 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 333 break; 334 } 335 336 if (i == 0) { 337 printf("%s: phy read timeout: phy %d, reg %d\n", 338 sc->sc_dev.dv_xname, phy, reg); 339 return (0); 340 } 341 342 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 343 } 344 345 /* 346 * Write a PHY register on the MII of the L1. 347 */ 348 void 349 age_miibus_writereg(struct device *dev, int phy, int reg, int val) 350 { 351 struct age_softc *sc = (struct age_softc *)dev; 352 uint32_t v; 353 int i; 354 355 if (phy != sc->age_phyaddr) 356 return; 357 358 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 359 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 360 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 361 362 for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 363 DELAY(1); 364 v = CSR_READ_4(sc, AGE_MDIO); 365 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 366 break; 367 } 368 369 if (i == 0) { 370 printf("%s: phy write timeout: phy %d, reg %d\n", 371 sc->sc_dev.dv_xname, phy, reg); 372 } 373 } 374 375 /* 376 * Callback from MII layer when media changes. 377 */ 378 void 379 age_miibus_statchg(struct device *dev) 380 { 381 struct age_softc *sc = (struct age_softc *)dev; 382 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 383 struct mii_data *mii = &sc->sc_miibus; 384 385 if ((ifp->if_flags & IFF_RUNNING) == 0) 386 return; 387 388 sc->age_flags &= ~AGE_FLAG_LINK; 389 if ((mii->mii_media_status & IFM_AVALID) != 0) { 390 switch (IFM_SUBTYPE(mii->mii_media_active)) { 391 case IFM_10_T: 392 case IFM_100_TX: 393 case IFM_1000_T: 394 sc->age_flags |= AGE_FLAG_LINK; 395 break; 396 default: 397 break; 398 } 399 } 400 401 /* Stop Rx/Tx MACs. */ 402 age_stop_rxmac(sc); 403 age_stop_txmac(sc); 404 405 /* Program MACs with resolved speed/duplex/flow-control. */ 406 if ((sc->age_flags & AGE_FLAG_LINK) != 0) { 407 uint32_t reg; 408 409 age_mac_config(sc); 410 reg = CSR_READ_4(sc, AGE_MAC_CFG); 411 /* Restart DMA engine and Tx/Rx MAC. */ 412 CSR_WRITE_4(sc, AGE_DMA_CFG, CSR_READ_4(sc, AGE_DMA_CFG) | 413 DMA_CFG_RD_ENB | DMA_CFG_WR_ENB); 414 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 415 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 416 } 417 } 418 419 /* 420 * Get the current interface media status. 421 */ 422 void 423 age_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 424 { 425 struct age_softc *sc = ifp->if_softc; 426 struct mii_data *mii = &sc->sc_miibus; 427 428 mii_pollstat(mii); 429 ifmr->ifm_status = mii->mii_media_status; 430 ifmr->ifm_active = mii->mii_media_active; 431 } 432 433 /* 434 * Set hardware to newly-selected media. 435 */ 436 int 437 age_mediachange(struct ifnet *ifp) 438 { 439 struct age_softc *sc = ifp->if_softc; 440 struct mii_data *mii = &sc->sc_miibus; 441 int error; 442 443 if (mii->mii_instance != 0) { 444 struct mii_softc *miisc; 445 446 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 447 mii_phy_reset(miisc); 448 } 449 error = mii_mediachg(mii); 450 451 return (error); 452 } 453 454 int 455 age_intr(void *arg) 456 { 457 struct age_softc *sc = arg; 458 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 459 struct cmb *cmb; 460 uint32_t status; 461 462 status = CSR_READ_4(sc, AGE_INTR_STATUS); 463 if (status == 0 || (status & AGE_INTRS) == 0) 464 return (0); 465 466 /* Disable interrupts. */ 467 CSR_WRITE_4(sc, AGE_INTR_STATUS, status | INTR_DIS_INT); 468 469 cmb = sc->age_rdata.age_cmb_block; 470 471 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 472 sc->age_cdata.age_cmb_block_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 473 status = letoh32(cmb->intr_status); 474 if ((status & AGE_INTRS) == 0) 475 goto back; 476 477 sc->age_tpd_cons = (letoh32(cmb->tpd_cons) & TPD_CONS_MASK) >> 478 TPD_CONS_SHIFT; 479 sc->age_rr_prod = (letoh32(cmb->rprod_cons) & RRD_PROD_MASK) >> 480 RRD_PROD_SHIFT; 481 482 /* Let hardware know CMB was served. */ 483 cmb->intr_status = 0; 484 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 485 sc->age_cdata.age_cmb_block_map->dm_mapsize, 486 BUS_DMASYNC_PREWRITE); 487 488 if (ifp->if_flags & IFF_RUNNING) { 489 if (status & INTR_CMB_RX) 490 age_rxintr(sc, sc->age_rr_prod); 491 492 if (status & INTR_CMB_TX) 493 age_txintr(sc, sc->age_tpd_cons); 494 495 if (status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) { 496 if (status & INTR_DMA_RD_TO_RST) 497 printf("%s: DMA read error! -- resetting\n", 498 sc->sc_dev.dv_xname); 499 if (status & INTR_DMA_WR_TO_RST) 500 printf("%s: DMA write error! -- resetting\n", 501 sc->sc_dev.dv_xname); 502 age_init(ifp); 503 } 504 505 age_start(ifp); 506 507 if (status & INTR_SMB) 508 age_stats_update(sc); 509 } 510 511 /* Check whether CMB was updated while serving Tx/Rx/SMB handler. */ 512 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 513 sc->age_cdata.age_cmb_block_map->dm_mapsize, 514 BUS_DMASYNC_POSTREAD); 515 516 back: 517 /* Re-enable interrupts. */ 518 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); 519 520 return (1); 521 } 522 523 void 524 age_get_macaddr(struct age_softc *sc) 525 { 526 uint32_t ea[2], reg; 527 int i, vpdc; 528 529 reg = CSR_READ_4(sc, AGE_SPI_CTRL); 530 if ((reg & SPI_VPD_ENB) != 0) { 531 /* Get VPD stored in TWSI EEPROM. */ 532 reg &= ~SPI_VPD_ENB; 533 CSR_WRITE_4(sc, AGE_SPI_CTRL, reg); 534 } 535 536 if (pci_get_capability(sc->sc_pct, sc->sc_pcitag, 537 PCI_CAP_VPD, &vpdc, NULL)) { 538 /* 539 * PCI VPD capability found, let TWSI reload EEPROM. 540 * This will set Ethernet address of controller. 541 */ 542 CSR_WRITE_4(sc, AGE_TWSI_CTRL, CSR_READ_4(sc, AGE_TWSI_CTRL) | 543 TWSI_CTRL_SW_LD_START); 544 for (i = 100; i > 0; i--) { 545 DELAY(1000); 546 reg = CSR_READ_4(sc, AGE_TWSI_CTRL); 547 if ((reg & TWSI_CTRL_SW_LD_START) == 0) 548 break; 549 } 550 if (i == 0) 551 printf("%s: reloading EEPROM timeout!\n", 552 sc->sc_dev.dv_xname); 553 } else { 554 if (agedebug) 555 printf("%s: PCI VPD capability not found!\n", 556 sc->sc_dev.dv_xname); 557 } 558 559 ea[0] = CSR_READ_4(sc, AGE_PAR0); 560 ea[1] = CSR_READ_4(sc, AGE_PAR1); 561 sc->age_eaddr[0] = (ea[1] >> 8) & 0xFF; 562 sc->age_eaddr[1] = (ea[1] >> 0) & 0xFF; 563 sc->age_eaddr[2] = (ea[0] >> 24) & 0xFF; 564 sc->age_eaddr[3] = (ea[0] >> 16) & 0xFF; 565 sc->age_eaddr[4] = (ea[0] >> 8) & 0xFF; 566 sc->age_eaddr[5] = (ea[0] >> 0) & 0xFF; 567 } 568 569 void 570 age_phy_reset(struct age_softc *sc) 571 { 572 uint16_t reg, pn; 573 int i, linkup; 574 575 /* Reset PHY. */ 576 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_RST); 577 DELAY(2000); 578 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_CLR); 579 DELAY(2000); 580 581 #define ATPHY_DBG_ADDR 0x1D 582 #define ATPHY_DBG_DATA 0x1E 583 #define ATPHY_CDTC 0x16 584 #define PHY_CDTC_ENB 0x0001 585 #define PHY_CDTC_POFF 8 586 #define ATPHY_CDTS 0x1C 587 #define PHY_CDTS_STAT_OK 0x0000 588 #define PHY_CDTS_STAT_SHORT 0x0100 589 #define PHY_CDTS_STAT_OPEN 0x0200 590 #define PHY_CDTS_STAT_INVAL 0x0300 591 #define PHY_CDTS_STAT_MASK 0x0300 592 593 /* Check power saving mode. Magic from Linux. */ 594 age_miibus_writereg(&sc->sc_dev, sc->age_phyaddr, MII_BMCR, BMCR_RESET); 595 for (linkup = 0, pn = 0; pn < 4; pn++) { 596 age_miibus_writereg(&sc->sc_dev, sc->age_phyaddr, ATPHY_CDTC, 597 (pn << PHY_CDTC_POFF) | PHY_CDTC_ENB); 598 for (i = 200; i > 0; i--) { 599 DELAY(1000); 600 reg = age_miibus_readreg(&sc->sc_dev, sc->age_phyaddr, 601 ATPHY_CDTC); 602 if ((reg & PHY_CDTC_ENB) == 0) 603 break; 604 } 605 DELAY(1000); 606 reg = age_miibus_readreg(&sc->sc_dev, sc->age_phyaddr, 607 ATPHY_CDTS); 608 if ((reg & PHY_CDTS_STAT_MASK) != PHY_CDTS_STAT_OPEN) { 609 linkup++; 610 break; 611 } 612 } 613 age_miibus_writereg(&sc->sc_dev, sc->age_phyaddr, MII_BMCR, 614 BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 615 if (linkup == 0) { 616 age_miibus_writereg(&sc->sc_dev, sc->age_phyaddr, 617 ATPHY_DBG_ADDR, 0); 618 age_miibus_writereg(&sc->sc_dev, sc->age_phyaddr, 619 ATPHY_DBG_DATA, 0x124E); 620 age_miibus_writereg(&sc->sc_dev, sc->age_phyaddr, 621 ATPHY_DBG_ADDR, 1); 622 reg = age_miibus_readreg(&sc->sc_dev, sc->age_phyaddr, 623 ATPHY_DBG_DATA); 624 age_miibus_writereg(&sc->sc_dev, sc->age_phyaddr, 625 ATPHY_DBG_DATA, reg | 0x03); 626 /* XXX */ 627 DELAY(1500 * 1000); 628 age_miibus_writereg(&sc->sc_dev, sc->age_phyaddr, 629 ATPHY_DBG_ADDR, 0); 630 age_miibus_writereg(&sc->sc_dev, sc->age_phyaddr, 631 ATPHY_DBG_DATA, 0x024E); 632 } 633 634 #undef ATPHY_DBG_ADDR 635 #undef ATPHY_DBG_DATA 636 #undef ATPHY_CDTC 637 #undef PHY_CDTC_ENB 638 #undef PHY_CDTC_POFF 639 #undef ATPHY_CDTS 640 #undef PHY_CDTS_STAT_OK 641 #undef PHY_CDTS_STAT_SHORT 642 #undef PHY_CDTS_STAT_OPEN 643 #undef PHY_CDTS_STAT_INVAL 644 #undef PHY_CDTS_STAT_MASK 645 } 646 647 int 648 age_dma_alloc(struct age_softc *sc) 649 { 650 struct age_txdesc *txd; 651 struct age_rxdesc *rxd; 652 int nsegs, error, i; 653 654 /* 655 * Create DMA stuffs for TX ring 656 */ 657 error = bus_dmamap_create(sc->sc_dmat, AGE_TX_RING_SZ, 1, 658 AGE_TX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->age_cdata.age_tx_ring_map); 659 if (error) 660 return (ENOBUFS); 661 662 /* Allocate DMA'able memory for TX ring */ 663 error = bus_dmamem_alloc(sc->sc_dmat, AGE_TX_RING_SZ, 664 ETHER_ALIGN, 0, &sc->age_rdata.age_tx_ring_seg, 1, 665 &nsegs, BUS_DMA_WAITOK | BUS_DMA_ZERO); 666 if (error) { 667 printf("%s: could not allocate DMA'able memory for Tx ring.\n", 668 sc->sc_dev.dv_xname); 669 return error; 670 } 671 672 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_tx_ring_seg, 673 nsegs, AGE_TX_RING_SZ, (caddr_t *)&sc->age_rdata.age_tx_ring, 674 BUS_DMA_NOWAIT); 675 if (error) 676 return (ENOBUFS); 677 678 /* Load the DMA map for Tx ring. */ 679 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 680 sc->age_rdata.age_tx_ring, AGE_TX_RING_SZ, NULL, BUS_DMA_WAITOK); 681 if (error) { 682 printf("%s: could not load DMA'able memory for Tx ring.\n", 683 sc->sc_dev.dv_xname); 684 bus_dmamem_free(sc->sc_dmat, 685 (bus_dma_segment_t *)&sc->age_rdata.age_tx_ring, 1); 686 return error; 687 } 688 689 sc->age_rdata.age_tx_ring_paddr = 690 sc->age_cdata.age_tx_ring_map->dm_segs[0].ds_addr; 691 692 /* 693 * Create DMA stuffs for RX ring 694 */ 695 error = bus_dmamap_create(sc->sc_dmat, AGE_RX_RING_SZ, 1, 696 AGE_RX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->age_cdata.age_rx_ring_map); 697 if (error) 698 return (ENOBUFS); 699 700 /* Allocate DMA'able memory for RX ring */ 701 error = bus_dmamem_alloc(sc->sc_dmat, AGE_RX_RING_SZ, 702 ETHER_ALIGN, 0, &sc->age_rdata.age_rx_ring_seg, 1, 703 &nsegs, BUS_DMA_WAITOK | BUS_DMA_ZERO); 704 if (error) { 705 printf("%s: could not allocate DMA'able memory for Rx ring.\n", 706 sc->sc_dev.dv_xname); 707 return error; 708 } 709 710 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_rx_ring_seg, 711 nsegs, AGE_RX_RING_SZ, (caddr_t *)&sc->age_rdata.age_rx_ring, 712 BUS_DMA_NOWAIT); 713 if (error) 714 return (ENOBUFS); 715 716 /* Load the DMA map for Rx ring. */ 717 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_rx_ring_map, 718 sc->age_rdata.age_rx_ring, AGE_RX_RING_SZ, NULL, BUS_DMA_WAITOK); 719 if (error) { 720 printf("%s: could not load DMA'able memory for Rx ring.\n", 721 sc->sc_dev.dv_xname); 722 bus_dmamem_free(sc->sc_dmat, 723 (bus_dma_segment_t *)sc->age_rdata.age_rx_ring, 1); 724 return error; 725 } 726 727 sc->age_rdata.age_rx_ring_paddr = 728 sc->age_cdata.age_rx_ring_map->dm_segs[0].ds_addr; 729 730 /* 731 * Create DMA stuffs for RX return ring 732 */ 733 error = bus_dmamap_create(sc->sc_dmat, AGE_RR_RING_SZ, 1, 734 AGE_RR_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->age_cdata.age_rr_ring_map); 735 if (error) 736 return (ENOBUFS); 737 738 /* Allocate DMA'able memory for RX return ring */ 739 error = bus_dmamem_alloc(sc->sc_dmat, AGE_RR_RING_SZ, 740 ETHER_ALIGN, 0, &sc->age_rdata.age_rr_ring_seg, 1, 741 &nsegs, BUS_DMA_WAITOK | BUS_DMA_ZERO); 742 if (error) { 743 printf("%s: could not allocate DMA'able memory for Rx " 744 "return ring.\n", sc->sc_dev.dv_xname); 745 return error; 746 } 747 748 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_rr_ring_seg, 749 nsegs, AGE_RR_RING_SZ, (caddr_t *)&sc->age_rdata.age_rr_ring, 750 BUS_DMA_NOWAIT); 751 if (error) 752 return (ENOBUFS); 753 754 /* Load the DMA map for Rx return ring. */ 755 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 756 sc->age_rdata.age_rr_ring, AGE_RR_RING_SZ, NULL, BUS_DMA_WAITOK); 757 if (error) { 758 printf("%s: could not load DMA'able memory for Rx return ring." 759 "\n", sc->sc_dev.dv_xname); 760 bus_dmamem_free(sc->sc_dmat, 761 (bus_dma_segment_t *)&sc->age_rdata.age_rr_ring, 1); 762 return error; 763 } 764 765 sc->age_rdata.age_rr_ring_paddr = 766 sc->age_cdata.age_rr_ring_map->dm_segs[0].ds_addr; 767 768 /* 769 * Create DMA stuffs for CMB block 770 */ 771 error = bus_dmamap_create(sc->sc_dmat, AGE_CMB_BLOCK_SZ, 1, 772 AGE_CMB_BLOCK_SZ, 0, BUS_DMA_NOWAIT, 773 &sc->age_cdata.age_cmb_block_map); 774 if (error) 775 return (ENOBUFS); 776 777 /* Allocate DMA'able memory for CMB block */ 778 error = bus_dmamem_alloc(sc->sc_dmat, AGE_CMB_BLOCK_SZ, 779 ETHER_ALIGN, 0, &sc->age_rdata.age_cmb_block_seg, 1, 780 &nsegs, BUS_DMA_WAITOK | BUS_DMA_ZERO); 781 if (error) { 782 printf("%s: could not allocate DMA'able memory for " 783 "CMB block\n", sc->sc_dev.dv_xname); 784 return error; 785 } 786 787 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_cmb_block_seg, 788 nsegs, AGE_CMB_BLOCK_SZ, (caddr_t *)&sc->age_rdata.age_cmb_block, 789 BUS_DMA_NOWAIT); 790 if (error) 791 return (ENOBUFS); 792 793 /* Load the DMA map for CMB block. */ 794 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 795 sc->age_rdata.age_cmb_block, AGE_CMB_BLOCK_SZ, NULL, 796 BUS_DMA_WAITOK); 797 if (error) { 798 printf("%s: could not load DMA'able memory for CMB block\n", 799 sc->sc_dev.dv_xname); 800 bus_dmamem_free(sc->sc_dmat, 801 (bus_dma_segment_t *)&sc->age_rdata.age_cmb_block, 1); 802 return error; 803 } 804 805 sc->age_rdata.age_cmb_block_paddr = 806 sc->age_cdata.age_cmb_block_map->dm_segs[0].ds_addr; 807 808 /* 809 * Create DMA stuffs for SMB block 810 */ 811 error = bus_dmamap_create(sc->sc_dmat, AGE_SMB_BLOCK_SZ, 1, 812 AGE_SMB_BLOCK_SZ, 0, BUS_DMA_NOWAIT, 813 &sc->age_cdata.age_smb_block_map); 814 if (error) 815 return (ENOBUFS); 816 817 /* Allocate DMA'able memory for SMB block */ 818 error = bus_dmamem_alloc(sc->sc_dmat, AGE_SMB_BLOCK_SZ, 819 ETHER_ALIGN, 0, &sc->age_rdata.age_smb_block_seg, 1, 820 &nsegs, BUS_DMA_WAITOK | BUS_DMA_ZERO); 821 if (error) { 822 printf("%s: could not allocate DMA'able memory for " 823 "SMB block\n", sc->sc_dev.dv_xname); 824 return error; 825 } 826 827 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_smb_block_seg, 828 nsegs, AGE_SMB_BLOCK_SZ, (caddr_t *)&sc->age_rdata.age_smb_block, 829 BUS_DMA_NOWAIT); 830 if (error) 831 return (ENOBUFS); 832 833 /* Load the DMA map for SMB block */ 834 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 835 sc->age_rdata.age_smb_block, AGE_SMB_BLOCK_SZ, NULL, 836 BUS_DMA_WAITOK); 837 if (error) { 838 printf("%s: could not load DMA'able memory for SMB block\n", 839 sc->sc_dev.dv_xname); 840 bus_dmamem_free(sc->sc_dmat, 841 (bus_dma_segment_t *)&sc->age_rdata.age_smb_block, 1); 842 return error; 843 } 844 845 sc->age_rdata.age_smb_block_paddr = 846 sc->age_cdata.age_smb_block_map->dm_segs[0].ds_addr; 847 848 /* Create DMA maps for Tx buffers. */ 849 for (i = 0; i < AGE_TX_RING_CNT; i++) { 850 txd = &sc->age_cdata.age_txdesc[i]; 851 txd->tx_m = NULL; 852 txd->tx_dmamap = NULL; 853 error = bus_dmamap_create(sc->sc_dmat, AGE_TSO_MAXSIZE, 854 AGE_MAXTXSEGS, AGE_TSO_MAXSEGSIZE, 0, BUS_DMA_NOWAIT, 855 &txd->tx_dmamap); 856 if (error) { 857 printf("%s: could not create Tx dmamap.\n", 858 sc->sc_dev.dv_xname); 859 return error; 860 } 861 } 862 863 /* Create DMA maps for Rx buffers. */ 864 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 865 BUS_DMA_NOWAIT, &sc->age_cdata.age_rx_sparemap); 866 if (error) { 867 printf("%s: could not create spare Rx dmamap.\n", 868 sc->sc_dev.dv_xname); 869 return error; 870 } 871 for (i = 0; i < AGE_RX_RING_CNT; i++) { 872 rxd = &sc->age_cdata.age_rxdesc[i]; 873 rxd->rx_m = NULL; 874 rxd->rx_dmamap = NULL; 875 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 876 MCLBYTES, 0, BUS_DMA_NOWAIT, &rxd->rx_dmamap); 877 if (error) { 878 printf("%s: could not create Rx dmamap.\n", 879 sc->sc_dev.dv_xname); 880 return error; 881 } 882 } 883 884 return (0); 885 } 886 887 void 888 age_dma_free(struct age_softc *sc) 889 { 890 struct age_txdesc *txd; 891 struct age_rxdesc *rxd; 892 int i; 893 894 /* Tx buffers */ 895 for (i = 0; i < AGE_TX_RING_CNT; i++) { 896 txd = &sc->age_cdata.age_txdesc[i]; 897 if (txd->tx_dmamap != NULL) { 898 bus_dmamap_destroy(sc->sc_dmat, txd->tx_dmamap); 899 txd->tx_dmamap = NULL; 900 } 901 } 902 /* Rx buffers */ 903 for (i = 0; i < AGE_RX_RING_CNT; i++) { 904 rxd = &sc->age_cdata.age_rxdesc[i]; 905 if (rxd->rx_dmamap != NULL) { 906 bus_dmamap_destroy(sc->sc_dmat, rxd->rx_dmamap); 907 rxd->rx_dmamap = NULL; 908 } 909 } 910 if (sc->age_cdata.age_rx_sparemap != NULL) { 911 bus_dmamap_destroy(sc->sc_dmat, sc->age_cdata.age_rx_sparemap); 912 sc->age_cdata.age_rx_sparemap = NULL; 913 } 914 915 /* Tx ring. */ 916 if (sc->age_cdata.age_tx_ring_map != NULL) 917 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_tx_ring_map); 918 if (sc->age_cdata.age_tx_ring_map != NULL && 919 sc->age_rdata.age_tx_ring != NULL) 920 bus_dmamem_free(sc->sc_dmat, 921 (bus_dma_segment_t *)sc->age_rdata.age_tx_ring, 1); 922 sc->age_rdata.age_tx_ring = NULL; 923 sc->age_cdata.age_tx_ring_map = NULL; 924 925 /* Rx ring. */ 926 if (sc->age_cdata.age_rx_ring_map != NULL) 927 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_rx_ring_map); 928 if (sc->age_cdata.age_rx_ring_map != NULL && 929 sc->age_rdata.age_rx_ring != NULL) 930 bus_dmamem_free(sc->sc_dmat, 931 (bus_dma_segment_t *)sc->age_rdata.age_rx_ring, 1); 932 sc->age_rdata.age_rx_ring = NULL; 933 sc->age_cdata.age_rx_ring_map = NULL; 934 935 /* Rx return ring. */ 936 if (sc->age_cdata.age_rr_ring_map != NULL) 937 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_rr_ring_map); 938 if (sc->age_cdata.age_rr_ring_map != NULL && 939 sc->age_rdata.age_rr_ring != NULL) 940 bus_dmamem_free(sc->sc_dmat, 941 (bus_dma_segment_t *)sc->age_rdata.age_rr_ring, 1); 942 sc->age_rdata.age_rr_ring = NULL; 943 sc->age_cdata.age_rr_ring_map = NULL; 944 945 /* CMB block */ 946 if (sc->age_cdata.age_cmb_block_map != NULL) 947 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_cmb_block_map); 948 if (sc->age_cdata.age_cmb_block_map != NULL && 949 sc->age_rdata.age_cmb_block != NULL) 950 bus_dmamem_free(sc->sc_dmat, 951 (bus_dma_segment_t *)sc->age_rdata.age_cmb_block, 1); 952 sc->age_rdata.age_cmb_block = NULL; 953 sc->age_cdata.age_cmb_block_map = NULL; 954 955 /* SMB block */ 956 if (sc->age_cdata.age_smb_block_map != NULL) 957 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_smb_block_map); 958 if (sc->age_cdata.age_smb_block_map != NULL && 959 sc->age_rdata.age_smb_block != NULL) 960 bus_dmamem_free(sc->sc_dmat, 961 (bus_dma_segment_t *)sc->age_rdata.age_smb_block, 1); 962 sc->age_rdata.age_smb_block = NULL; 963 sc->age_cdata.age_smb_block_map = NULL; 964 } 965 966 void 967 age_start(struct ifnet *ifp) 968 { 969 struct age_softc *sc = ifp->if_softc; 970 struct mbuf *m_head; 971 int enq; 972 973 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 974 return; 975 if ((sc->age_flags & AGE_FLAG_LINK) == 0) 976 return; 977 if (IFQ_IS_EMPTY(&ifp->if_snd)) 978 return; 979 980 enq = 0; 981 for (;;) { 982 IFQ_DEQUEUE(&ifp->if_snd, m_head); 983 if (m_head == NULL) 984 break; 985 986 /* 987 * Pack the data into the transmit ring. If we 988 * don't have room, set the OACTIVE flag and wait 989 * for the NIC to drain the ring. 990 */ 991 if (age_encap(sc, &m_head)) { 992 if (m_head == NULL) 993 break; 994 ifp->if_flags |= IFF_OACTIVE; 995 break; 996 } 997 enq = 1; 998 999 #if NBPFILTER > 0 1000 /* 1001 * If there's a BPF listener, bounce a copy of this frame 1002 * to him. 1003 */ 1004 if (ifp->if_bpf != NULL) 1005 bpf_mtap_ether(ifp->if_bpf, m_head, BPF_DIRECTION_OUT); 1006 #endif 1007 } 1008 1009 if (enq) { 1010 /* Update mbox. */ 1011 AGE_COMMIT_MBOX(sc); 1012 /* Set a timeout in case the chip goes out to lunch. */ 1013 ifp->if_timer = AGE_TX_TIMEOUT; 1014 } 1015 } 1016 1017 void 1018 age_watchdog(struct ifnet *ifp) 1019 { 1020 struct age_softc *sc = ifp->if_softc; 1021 1022 if ((sc->age_flags & AGE_FLAG_LINK) == 0) { 1023 printf("%s: watchdog timeout (missed link)\n", 1024 sc->sc_dev.dv_xname); 1025 ifp->if_oerrors++; 1026 age_init(ifp); 1027 return; 1028 } 1029 1030 if (sc->age_cdata.age_tx_cnt == 0) { 1031 printf("%s: watchdog timeout (missed Tx interrupts) " 1032 "-- recovering\n", sc->sc_dev.dv_xname); 1033 age_start(ifp); 1034 return; 1035 } 1036 1037 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 1038 ifp->if_oerrors++; 1039 age_init(ifp); 1040 age_start(ifp); 1041 } 1042 1043 int 1044 age_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1045 { 1046 struct age_softc *sc = ifp->if_softc; 1047 struct mii_data *mii = &sc->sc_miibus; 1048 struct ifaddr *ifa = (struct ifaddr *)data; 1049 struct ifreq *ifr = (struct ifreq *)data; 1050 int s, error = 0; 1051 1052 s = splnet(); 1053 1054 switch (cmd) { 1055 case SIOCSIFADDR: 1056 ifp->if_flags |= IFF_UP; 1057 if (!(ifp->if_flags & IFF_RUNNING)) 1058 age_init(ifp); 1059 #ifdef INET 1060 if (ifa->ifa_addr->sa_family == AF_INET) 1061 arp_ifinit(&sc->sc_arpcom, ifa); 1062 #endif 1063 break; 1064 1065 case SIOCSIFFLAGS: 1066 if (ifp->if_flags & IFF_UP) { 1067 if (ifp->if_flags & IFF_RUNNING) 1068 error = ENETRESET; 1069 else 1070 age_init(ifp); 1071 } else { 1072 if (ifp->if_flags & IFF_RUNNING) 1073 age_stop(sc); 1074 } 1075 break; 1076 1077 case SIOCSIFMEDIA: 1078 case SIOCGIFMEDIA: 1079 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1080 break; 1081 1082 default: 1083 error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data); 1084 break; 1085 } 1086 1087 if (error == ENETRESET) { 1088 if (ifp->if_flags & IFF_RUNNING) 1089 age_iff(sc); 1090 error = 0; 1091 } 1092 1093 splx(s); 1094 return (error); 1095 } 1096 1097 void 1098 age_mac_config(struct age_softc *sc) 1099 { 1100 struct mii_data *mii = &sc->sc_miibus; 1101 uint32_t reg; 1102 1103 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1104 reg &= ~MAC_CFG_FULL_DUPLEX; 1105 reg &= ~(MAC_CFG_TX_FC | MAC_CFG_RX_FC); 1106 reg &= ~MAC_CFG_SPEED_MASK; 1107 1108 /* Reprogram MAC with resolved speed/duplex. */ 1109 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1110 case IFM_10_T: 1111 case IFM_100_TX: 1112 reg |= MAC_CFG_SPEED_10_100; 1113 break; 1114 case IFM_1000_T: 1115 reg |= MAC_CFG_SPEED_1000; 1116 break; 1117 } 1118 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1119 reg |= MAC_CFG_FULL_DUPLEX; 1120 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1121 reg |= MAC_CFG_TX_FC; 1122 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1123 reg |= MAC_CFG_RX_FC; 1124 } 1125 1126 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1127 } 1128 1129 int 1130 age_encap(struct age_softc *sc, struct mbuf **m_head) 1131 { 1132 struct age_txdesc *txd, *txd_last; 1133 struct tx_desc *desc; 1134 struct mbuf *m; 1135 bus_dmamap_t map; 1136 uint32_t cflags, poff, vtag; 1137 int error, i, nsegs, prod; 1138 1139 m = *m_head; 1140 cflags = vtag = 0; 1141 poff = 0; 1142 1143 prod = sc->age_cdata.age_tx_prod; 1144 txd = &sc->age_cdata.age_txdesc[prod]; 1145 txd_last = txd; 1146 map = txd->tx_dmamap; 1147 1148 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, BUS_DMA_NOWAIT); 1149 1150 if (error != 0) { 1151 bus_dmamap_unload(sc->sc_dmat, map); 1152 error = EFBIG; 1153 } 1154 if (error == EFBIG) { 1155 if (m_defrag(*m_head, M_DONTWAIT)) { 1156 printf("%s: can't defrag TX mbuf\n", 1157 sc->sc_dev.dv_xname); 1158 m_freem(*m_head); 1159 *m_head = NULL; 1160 return (ENOBUFS); 1161 } 1162 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, 1163 BUS_DMA_NOWAIT); 1164 if (error != 0) { 1165 printf("%s: could not load defragged TX mbuf\n", 1166 sc->sc_dev.dv_xname); 1167 m_freem(*m_head); 1168 *m_head = NULL; 1169 return (error); 1170 } 1171 } else if (error) { 1172 printf("%s: could not load TX mbuf\n", sc->sc_dev.dv_xname); 1173 return (error); 1174 } 1175 1176 nsegs = map->dm_nsegs; 1177 1178 if (nsegs == 0) { 1179 m_freem(*m_head); 1180 *m_head = NULL; 1181 return (EIO); 1182 } 1183 1184 /* Check descriptor overrun. */ 1185 if (sc->age_cdata.age_tx_cnt + nsegs >= AGE_TX_RING_CNT - 2) { 1186 bus_dmamap_unload(sc->sc_dmat, map); 1187 return (ENOBUFS); 1188 } 1189 1190 m = *m_head; 1191 /* Configure Tx IP/TCP/UDP checksum offload. */ 1192 if ((m->m_pkthdr.csum_flags & AGE_CSUM_FEATURES) != 0) { 1193 cflags |= AGE_TD_CSUM; 1194 if ((m->m_pkthdr.csum_flags & M_TCP_CSUM_OUT) != 0) 1195 cflags |= AGE_TD_TCPCSUM; 1196 if ((m->m_pkthdr.csum_flags & M_UDP_CSUM_OUT) != 0) 1197 cflags |= AGE_TD_UDPCSUM; 1198 /* Set checksum start offset. */ 1199 cflags |= (poff << AGE_TD_CSUM_PLOADOFFSET_SHIFT); 1200 } 1201 1202 #if NVLAN > 0 1203 /* Configure VLAN hardware tag insertion. */ 1204 if (m->m_flags & M_VLANTAG) { 1205 vtag = AGE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag); 1206 vtag = ((vtag << AGE_TD_VLAN_SHIFT) & AGE_TD_VLAN_MASK); 1207 cflags |= AGE_TD_INSERT_VLAN_TAG; 1208 } 1209 #endif 1210 1211 desc = NULL; 1212 for (i = 0; i < nsegs; i++) { 1213 desc = &sc->age_rdata.age_tx_ring[prod]; 1214 desc->addr = htole64(map->dm_segs[i].ds_addr); 1215 desc->len = 1216 htole32(AGE_TX_BYTES(map->dm_segs[i].ds_len) | vtag); 1217 desc->flags = htole32(cflags); 1218 sc->age_cdata.age_tx_cnt++; 1219 AGE_DESC_INC(prod, AGE_TX_RING_CNT); 1220 } 1221 1222 /* Update producer index. */ 1223 sc->age_cdata.age_tx_prod = prod; 1224 1225 /* Set EOP on the last descriptor. */ 1226 prod = (prod + AGE_TX_RING_CNT - 1) % AGE_TX_RING_CNT; 1227 desc = &sc->age_rdata.age_tx_ring[prod]; 1228 desc->flags |= htole32(AGE_TD_EOP); 1229 1230 /* Swap dmamap of the first and the last. */ 1231 txd = &sc->age_cdata.age_txdesc[prod]; 1232 map = txd_last->tx_dmamap; 1233 txd_last->tx_dmamap = txd->tx_dmamap; 1234 txd->tx_dmamap = map; 1235 txd->tx_m = m; 1236 1237 /* Sync descriptors. */ 1238 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1239 BUS_DMASYNC_PREWRITE); 1240 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 0, 1241 sc->age_cdata.age_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1242 1243 return (0); 1244 } 1245 1246 void 1247 age_txintr(struct age_softc *sc, int tpd_cons) 1248 { 1249 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1250 struct age_txdesc *txd; 1251 int cons, prog; 1252 1253 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 0, 1254 sc->age_cdata.age_tx_ring_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1255 1256 /* 1257 * Go through our Tx list and free mbufs for those 1258 * frames which have been transmitted. 1259 */ 1260 cons = sc->age_cdata.age_tx_cons; 1261 for (prog = 0; cons != tpd_cons; AGE_DESC_INC(cons, AGE_TX_RING_CNT)) { 1262 if (sc->age_cdata.age_tx_cnt <= 0) 1263 break; 1264 prog++; 1265 ifp->if_flags &= ~IFF_OACTIVE; 1266 sc->age_cdata.age_tx_cnt--; 1267 txd = &sc->age_cdata.age_txdesc[cons]; 1268 /* 1269 * Clear Tx descriptors, it's not required but would 1270 * help debugging in case of Tx issues. 1271 */ 1272 txd->tx_desc->addr = 0; 1273 txd->tx_desc->len = 0; 1274 txd->tx_desc->flags = 0; 1275 1276 if (txd->tx_m == NULL) 1277 continue; 1278 /* Reclaim transmitted mbufs. */ 1279 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1280 m_freem(txd->tx_m); 1281 txd->tx_m = NULL; 1282 } 1283 1284 if (prog > 0) { 1285 sc->age_cdata.age_tx_cons = cons; 1286 1287 /* 1288 * Unarm watchdog timer only when there are no pending 1289 * Tx descriptors in queue. 1290 */ 1291 if (sc->age_cdata.age_tx_cnt == 0) 1292 ifp->if_timer = 0; 1293 1294 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 0, 1295 sc->age_cdata.age_tx_ring_map->dm_mapsize, 1296 BUS_DMASYNC_PREWRITE); 1297 } 1298 } 1299 1300 /* Receive a frame. */ 1301 void 1302 age_rxeof(struct age_softc *sc, struct rx_rdesc *rxrd) 1303 { 1304 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1305 struct age_rxdesc *rxd; 1306 struct rx_desc *desc; 1307 struct mbuf *mp, *m; 1308 uint32_t status, index; 1309 int count, nsegs, pktlen; 1310 int rx_cons; 1311 1312 status = letoh32(rxrd->flags); 1313 index = letoh32(rxrd->index); 1314 rx_cons = AGE_RX_CONS(index); 1315 nsegs = AGE_RX_NSEGS(index); 1316 1317 sc->age_cdata.age_rxlen = AGE_RX_BYTES(letoh32(rxrd->len)); 1318 if ((status & AGE_RRD_ERROR) != 0 && 1319 (status & (AGE_RRD_CRC | AGE_RRD_CODE | AGE_RRD_DRIBBLE | 1320 AGE_RRD_RUNT | AGE_RRD_OFLOW | AGE_RRD_TRUNC)) != 0) { 1321 /* 1322 * We want to pass the following frames to upper 1323 * layer regardless of error status of Rx return 1324 * ring. 1325 * 1326 * o IP/TCP/UDP checksum is bad. 1327 * o frame length and protocol specific length 1328 * does not match. 1329 */ 1330 sc->age_cdata.age_rx_cons += nsegs; 1331 sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT; 1332 return; 1333 } 1334 1335 pktlen = 0; 1336 for (count = 0; count < nsegs; count++, 1337 AGE_DESC_INC(rx_cons, AGE_RX_RING_CNT)) { 1338 rxd = &sc->age_cdata.age_rxdesc[rx_cons]; 1339 mp = rxd->rx_m; 1340 desc = rxd->rx_desc; 1341 /* Add a new receive buffer to the ring. */ 1342 if (age_newbuf(sc, rxd) != 0) { 1343 ifp->if_iqdrops++; 1344 /* Reuse Rx buffers. */ 1345 if (sc->age_cdata.age_rxhead != NULL) { 1346 m_freem(sc->age_cdata.age_rxhead); 1347 AGE_RXCHAIN_RESET(sc); 1348 } 1349 break; 1350 } 1351 1352 /* The length of the first mbuf is computed last. */ 1353 if (count != 0) { 1354 mp->m_len = AGE_RX_BYTES(letoh32(desc->len)); 1355 pktlen += mp->m_len; 1356 } 1357 1358 /* Chain received mbufs. */ 1359 if (sc->age_cdata.age_rxhead == NULL) { 1360 sc->age_cdata.age_rxhead = mp; 1361 sc->age_cdata.age_rxtail = mp; 1362 } else { 1363 mp->m_flags &= ~M_PKTHDR; 1364 sc->age_cdata.age_rxprev_tail = 1365 sc->age_cdata.age_rxtail; 1366 sc->age_cdata.age_rxtail->m_next = mp; 1367 sc->age_cdata.age_rxtail = mp; 1368 } 1369 1370 if (count == nsegs - 1) { 1371 /* 1372 * It seems that L1 controller has no way 1373 * to tell hardware to strip CRC bytes. 1374 */ 1375 sc->age_cdata.age_rxlen -= ETHER_CRC_LEN; 1376 if (nsegs > 1) { 1377 /* Remove the CRC bytes in chained mbufs. */ 1378 pktlen -= ETHER_CRC_LEN; 1379 if (mp->m_len <= ETHER_CRC_LEN) { 1380 sc->age_cdata.age_rxtail = 1381 sc->age_cdata.age_rxprev_tail; 1382 sc->age_cdata.age_rxtail->m_len -= 1383 (ETHER_CRC_LEN - mp->m_len); 1384 sc->age_cdata.age_rxtail->m_next = NULL; 1385 m_freem(mp); 1386 } else { 1387 mp->m_len -= ETHER_CRC_LEN; 1388 } 1389 } 1390 1391 m = sc->age_cdata.age_rxhead; 1392 m->m_flags |= M_PKTHDR; 1393 m->m_pkthdr.rcvif = ifp; 1394 m->m_pkthdr.len = sc->age_cdata.age_rxlen; 1395 /* Set the first mbuf length. */ 1396 m->m_len = sc->age_cdata.age_rxlen - pktlen; 1397 1398 /* 1399 * Set checksum information. 1400 * It seems that L1 controller can compute partial 1401 * checksum. The partial checksum value can be used 1402 * to accelerate checksum computation for fragmented 1403 * TCP/UDP packets. Upper network stack already 1404 * takes advantage of the partial checksum value in 1405 * IP reassembly stage. But I'm not sure the 1406 * correctness of the partial hardware checksum 1407 * assistance due to lack of data sheet. If it is 1408 * proven to work on L1 I'll enable it. 1409 */ 1410 if (status & AGE_RRD_IPV4) { 1411 if ((status & AGE_RRD_IPCSUM_NOK) == 0) 1412 m->m_pkthdr.csum_flags |= 1413 M_IPV4_CSUM_IN_OK; 1414 if ((status & (AGE_RRD_TCP | AGE_RRD_UDP)) && 1415 (status & AGE_RRD_TCP_UDPCSUM_NOK) == 0) { 1416 m->m_pkthdr.csum_flags |= 1417 M_TCP_CSUM_IN_OK | M_UDP_CSUM_IN_OK; 1418 } 1419 /* 1420 * Don't mark bad checksum for TCP/UDP frames 1421 * as fragmented frames may always have set 1422 * bad checksummed bit of descriptor status. 1423 */ 1424 } 1425 #if NVLAN > 0 1426 /* Check for VLAN tagged frames. */ 1427 if (status & AGE_RRD_VLAN) { 1428 u_int32_t vtag = AGE_RX_VLAN(letoh32(rxrd->vtags)); 1429 m->m_pkthdr.ether_vtag = 1430 AGE_RX_VLAN_TAG(vtag); 1431 m->m_flags |= M_VLANTAG; 1432 } 1433 #endif 1434 1435 #if NBPFILTER > 0 1436 if (ifp->if_bpf) 1437 bpf_mtap_ether(ifp->if_bpf, m, 1438 BPF_DIRECTION_IN); 1439 #endif 1440 /* Pass it on. */ 1441 ether_input_mbuf(ifp, m); 1442 1443 /* Reset mbuf chains. */ 1444 AGE_RXCHAIN_RESET(sc); 1445 } 1446 } 1447 1448 if (count != nsegs) { 1449 sc->age_cdata.age_rx_cons += nsegs; 1450 sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT; 1451 } else 1452 sc->age_cdata.age_rx_cons = rx_cons; 1453 } 1454 1455 void 1456 age_rxintr(struct age_softc *sc, int rr_prod) 1457 { 1458 struct rx_rdesc *rxrd; 1459 int rr_cons, nsegs, pktlen, prog; 1460 1461 rr_cons = sc->age_cdata.age_rr_cons; 1462 if (rr_cons == rr_prod) 1463 return; 1464 1465 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 0, 1466 sc->age_cdata.age_rr_ring_map->dm_mapsize, 1467 BUS_DMASYNC_POSTREAD); 1468 1469 for (prog = 0; rr_cons != rr_prod; prog++) { 1470 rxrd = &sc->age_rdata.age_rr_ring[rr_cons]; 1471 nsegs = AGE_RX_NSEGS(letoh32(rxrd->index)); 1472 if (nsegs == 0) 1473 break; 1474 /* 1475 * Check number of segments against received bytes 1476 * Non-matching value would indicate that hardware 1477 * is still trying to update Rx return descriptors. 1478 * I'm not sure whether this check is really needed. 1479 */ 1480 pktlen = AGE_RX_BYTES(letoh32(rxrd->len)); 1481 if (nsegs != ((pktlen + (MCLBYTES - ETHER_ALIGN - 1)) / 1482 (MCLBYTES - ETHER_ALIGN))) 1483 break; 1484 1485 /* Received a frame. */ 1486 age_rxeof(sc, rxrd); 1487 1488 /* Clear return ring. */ 1489 rxrd->index = 0; 1490 AGE_DESC_INC(rr_cons, AGE_RR_RING_CNT); 1491 } 1492 1493 if (prog > 0) { 1494 /* Update the consumer index. */ 1495 sc->age_cdata.age_rr_cons = rr_cons; 1496 1497 /* Sync descriptors. */ 1498 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 0, 1499 sc->age_cdata.age_rr_ring_map->dm_mapsize, 1500 BUS_DMASYNC_PREWRITE); 1501 1502 /* Notify hardware availability of new Rx buffers. */ 1503 AGE_COMMIT_MBOX(sc); 1504 } 1505 } 1506 1507 void 1508 age_tick(void *xsc) 1509 { 1510 struct age_softc *sc = xsc; 1511 struct mii_data *mii = &sc->sc_miibus; 1512 int s; 1513 1514 s = splnet(); 1515 mii_tick(mii); 1516 timeout_add_sec(&sc->age_tick_ch, 1); 1517 splx(s); 1518 } 1519 1520 void 1521 age_reset(struct age_softc *sc) 1522 { 1523 uint32_t reg; 1524 int i; 1525 1526 CSR_WRITE_4(sc, AGE_MASTER_CFG, MASTER_RESET); 1527 CSR_READ_4(sc, AGE_MASTER_CFG); 1528 DELAY(1000); 1529 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 1530 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 1531 break; 1532 DELAY(10); 1533 } 1534 1535 if (i == 0) 1536 printf("%s: reset timeout(0x%08x)!\n", sc->sc_dev.dv_xname, 1537 reg); 1538 1539 /* Initialize PCIe module. From Linux. */ 1540 CSR_WRITE_4(sc, 0x12FC, 0x6500); 1541 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 1542 } 1543 1544 int 1545 age_init(struct ifnet *ifp) 1546 { 1547 struct age_softc *sc = ifp->if_softc; 1548 struct mii_data *mii = &sc->sc_miibus; 1549 uint8_t eaddr[ETHER_ADDR_LEN]; 1550 bus_addr_t paddr; 1551 uint32_t reg, fsize; 1552 uint32_t rxf_hi, rxf_lo, rrd_hi, rrd_lo; 1553 int error; 1554 1555 /* 1556 * Cancel any pending I/O. 1557 */ 1558 age_stop(sc); 1559 1560 /* 1561 * Reset the chip to a known state. 1562 */ 1563 age_reset(sc); 1564 1565 /* Initialize descriptors. */ 1566 error = age_init_rx_ring(sc); 1567 if (error != 0) { 1568 printf("%s: no memory for Rx buffers.\n", sc->sc_dev.dv_xname); 1569 age_stop(sc); 1570 return (error); 1571 } 1572 age_init_rr_ring(sc); 1573 age_init_tx_ring(sc); 1574 age_init_cmb_block(sc); 1575 age_init_smb_block(sc); 1576 1577 /* Reprogram the station address. */ 1578 bcopy(LLADDR(ifp->if_sadl), eaddr, ETHER_ADDR_LEN); 1579 CSR_WRITE_4(sc, AGE_PAR0, 1580 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 1581 CSR_WRITE_4(sc, AGE_PAR1, eaddr[0] << 8 | eaddr[1]); 1582 1583 /* Set descriptor base addresses. */ 1584 paddr = sc->age_rdata.age_tx_ring_paddr; 1585 CSR_WRITE_4(sc, AGE_DESC_ADDR_HI, AGE_ADDR_HI(paddr)); 1586 paddr = sc->age_rdata.age_rx_ring_paddr; 1587 CSR_WRITE_4(sc, AGE_DESC_RD_ADDR_LO, AGE_ADDR_LO(paddr)); 1588 paddr = sc->age_rdata.age_rr_ring_paddr; 1589 CSR_WRITE_4(sc, AGE_DESC_RRD_ADDR_LO, AGE_ADDR_LO(paddr)); 1590 paddr = sc->age_rdata.age_tx_ring_paddr; 1591 CSR_WRITE_4(sc, AGE_DESC_TPD_ADDR_LO, AGE_ADDR_LO(paddr)); 1592 paddr = sc->age_rdata.age_cmb_block_paddr; 1593 CSR_WRITE_4(sc, AGE_DESC_CMB_ADDR_LO, AGE_ADDR_LO(paddr)); 1594 paddr = sc->age_rdata.age_smb_block_paddr; 1595 CSR_WRITE_4(sc, AGE_DESC_SMB_ADDR_LO, AGE_ADDR_LO(paddr)); 1596 1597 /* Set Rx/Rx return descriptor counter. */ 1598 CSR_WRITE_4(sc, AGE_DESC_RRD_RD_CNT, 1599 ((AGE_RR_RING_CNT << DESC_RRD_CNT_SHIFT) & 1600 DESC_RRD_CNT_MASK) | 1601 ((AGE_RX_RING_CNT << DESC_RD_CNT_SHIFT) & DESC_RD_CNT_MASK)); 1602 1603 /* Set Tx descriptor counter. */ 1604 CSR_WRITE_4(sc, AGE_DESC_TPD_CNT, 1605 (AGE_TX_RING_CNT << DESC_TPD_CNT_SHIFT) & DESC_TPD_CNT_MASK); 1606 1607 /* Tell hardware that we're ready to load descriptors. */ 1608 CSR_WRITE_4(sc, AGE_DMA_BLOCK, DMA_BLOCK_LOAD); 1609 1610 /* 1611 * Initialize mailbox register. 1612 * Updated producer/consumer index information is exchanged 1613 * through this mailbox register. However Tx producer and 1614 * Rx return consumer/Rx producer are all shared such that 1615 * it's hard to separate code path between Tx and Rx without 1616 * locking. If L1 hardware have a separate mail box register 1617 * for Tx and Rx consumer/producer management we could have 1618 * indepent Tx/Rx handler which in turn Rx handler could have 1619 * been run without any locking. 1620 */ 1621 AGE_COMMIT_MBOX(sc); 1622 1623 /* Configure IPG/IFG parameters. */ 1624 CSR_WRITE_4(sc, AGE_IPG_IFG_CFG, 1625 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK) | 1626 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 1627 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 1628 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK)); 1629 1630 /* Set parameters for half-duplex media. */ 1631 CSR_WRITE_4(sc, AGE_HDPX_CFG, 1632 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 1633 HDPX_CFG_LCOL_MASK) | 1634 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 1635 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 1636 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 1637 HDPX_CFG_ABEBT_MASK) | 1638 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 1639 HDPX_CFG_JAMIPG_MASK)); 1640 1641 /* Configure interrupt moderation timer. */ 1642 sc->age_int_mod = AGE_IM_TIMER_DEFAULT; 1643 CSR_WRITE_2(sc, AGE_IM_TIMER, AGE_USECS(sc->age_int_mod)); 1644 reg = CSR_READ_4(sc, AGE_MASTER_CFG); 1645 reg &= ~MASTER_MTIMER_ENB; 1646 if (AGE_USECS(sc->age_int_mod) == 0) 1647 reg &= ~MASTER_ITIMER_ENB; 1648 else 1649 reg |= MASTER_ITIMER_ENB; 1650 CSR_WRITE_4(sc, AGE_MASTER_CFG, reg); 1651 if (agedebug) 1652 printf("%s: interrupt moderation is %d us.\n", 1653 sc->sc_dev.dv_xname, sc->age_int_mod); 1654 CSR_WRITE_2(sc, AGE_INTR_CLR_TIMER, AGE_USECS(1000)); 1655 1656 /* Set Maximum frame size but don't let MTU be lass than ETHER_MTU. */ 1657 if (ifp->if_mtu < ETHERMTU) 1658 sc->age_max_frame_size = ETHERMTU; 1659 else 1660 sc->age_max_frame_size = ifp->if_mtu; 1661 sc->age_max_frame_size += ETHER_HDR_LEN + 1662 sizeof(struct ether_vlan_header) + ETHER_CRC_LEN; 1663 CSR_WRITE_4(sc, AGE_FRAME_SIZE, sc->age_max_frame_size); 1664 1665 /* Configure jumbo frame. */ 1666 fsize = roundup(sc->age_max_frame_size, sizeof(uint64_t)); 1667 CSR_WRITE_4(sc, AGE_RXQ_JUMBO_CFG, 1668 (((fsize / sizeof(uint64_t)) << 1669 RXQ_JUMBO_CFG_SZ_THRESH_SHIFT) & RXQ_JUMBO_CFG_SZ_THRESH_MASK) | 1670 ((RXQ_JUMBO_CFG_LKAH_DEFAULT << 1671 RXQ_JUMBO_CFG_LKAH_SHIFT) & RXQ_JUMBO_CFG_LKAH_MASK) | 1672 ((AGE_USECS(8) << RXQ_JUMBO_CFG_RRD_TIMER_SHIFT) & 1673 RXQ_JUMBO_CFG_RRD_TIMER_MASK)); 1674 1675 /* Configure flow-control parameters. From Linux. */ 1676 if ((sc->age_flags & AGE_FLAG_PCIE) != 0) { 1677 /* 1678 * Magic workaround for old-L1. 1679 * Don't know which hw revision requires this magic. 1680 */ 1681 CSR_WRITE_4(sc, 0x12FC, 0x6500); 1682 /* 1683 * Another magic workaround for flow-control mode 1684 * change. From Linux. 1685 */ 1686 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 1687 } 1688 /* 1689 * TODO 1690 * Should understand pause parameter relationships between FIFO 1691 * size and number of Rx descriptors and Rx return descriptors. 1692 * 1693 * Magic parameters came from Linux. 1694 */ 1695 switch (sc->age_chip_rev) { 1696 case 0x8001: 1697 case 0x9001: 1698 case 0x9002: 1699 case 0x9003: 1700 rxf_hi = AGE_RX_RING_CNT / 16; 1701 rxf_lo = (AGE_RX_RING_CNT * 7) / 8; 1702 rrd_hi = (AGE_RR_RING_CNT * 7) / 8; 1703 rrd_lo = AGE_RR_RING_CNT / 16; 1704 break; 1705 default: 1706 reg = CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN); 1707 rxf_lo = reg / 16; 1708 if (rxf_lo < 192) 1709 rxf_lo = 192; 1710 rxf_hi = (reg * 7) / 8; 1711 if (rxf_hi < rxf_lo) 1712 rxf_hi = rxf_lo + 16; 1713 reg = CSR_READ_4(sc, AGE_SRAM_RRD_LEN); 1714 rrd_lo = reg / 8; 1715 rrd_hi = (reg * 7) / 8; 1716 if (rrd_lo < 2) 1717 rrd_lo = 2; 1718 if (rrd_hi < rrd_lo) 1719 rrd_hi = rrd_lo + 3; 1720 break; 1721 } 1722 CSR_WRITE_4(sc, AGE_RXQ_FIFO_PAUSE_THRESH, 1723 ((rxf_lo << RXQ_FIFO_PAUSE_THRESH_LO_SHIFT) & 1724 RXQ_FIFO_PAUSE_THRESH_LO_MASK) | 1725 ((rxf_hi << RXQ_FIFO_PAUSE_THRESH_HI_SHIFT) & 1726 RXQ_FIFO_PAUSE_THRESH_HI_MASK)); 1727 CSR_WRITE_4(sc, AGE_RXQ_RRD_PAUSE_THRESH, 1728 ((rrd_lo << RXQ_RRD_PAUSE_THRESH_LO_SHIFT) & 1729 RXQ_RRD_PAUSE_THRESH_LO_MASK) | 1730 ((rrd_hi << RXQ_RRD_PAUSE_THRESH_HI_SHIFT) & 1731 RXQ_RRD_PAUSE_THRESH_HI_MASK)); 1732 1733 /* Configure RxQ. */ 1734 CSR_WRITE_4(sc, AGE_RXQ_CFG, 1735 ((RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 1736 RXQ_CFG_RD_BURST_MASK) | 1737 ((RXQ_CFG_RRD_BURST_THRESH_DEFAULT << 1738 RXQ_CFG_RRD_BURST_THRESH_SHIFT) & RXQ_CFG_RRD_BURST_THRESH_MASK) | 1739 ((RXQ_CFG_RD_PREF_MIN_IPG_DEFAULT << 1740 RXQ_CFG_RD_PREF_MIN_IPG_SHIFT) & RXQ_CFG_RD_PREF_MIN_IPG_MASK) | 1741 RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 1742 1743 /* Configure TxQ. */ 1744 CSR_WRITE_4(sc, AGE_TXQ_CFG, 1745 ((TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 1746 TXQ_CFG_TPD_BURST_MASK) | 1747 ((TXQ_CFG_TX_FIFO_BURST_DEFAULT << TXQ_CFG_TX_FIFO_BURST_SHIFT) & 1748 TXQ_CFG_TX_FIFO_BURST_MASK) | 1749 ((TXQ_CFG_TPD_FETCH_DEFAULT << 1750 TXQ_CFG_TPD_FETCH_THRESH_SHIFT) & TXQ_CFG_TPD_FETCH_THRESH_MASK) | 1751 TXQ_CFG_ENB); 1752 1753 /* Configure DMA parameters. */ 1754 CSR_WRITE_4(sc, AGE_DMA_CFG, 1755 DMA_CFG_ENH_ORDER | DMA_CFG_RCB_64 | 1756 sc->age_dma_rd_burst | DMA_CFG_RD_ENB | 1757 sc->age_dma_wr_burst | DMA_CFG_WR_ENB); 1758 1759 /* Configure CMB DMA write threshold. */ 1760 CSR_WRITE_4(sc, AGE_CMB_WR_THRESH, 1761 ((CMB_WR_THRESH_RRD_DEFAULT << CMB_WR_THRESH_RRD_SHIFT) & 1762 CMB_WR_THRESH_RRD_MASK) | 1763 ((CMB_WR_THRESH_TPD_DEFAULT << CMB_WR_THRESH_TPD_SHIFT) & 1764 CMB_WR_THRESH_TPD_MASK)); 1765 1766 /* Set CMB/SMB timer and enable them. */ 1767 CSR_WRITE_4(sc, AGE_CMB_WR_TIMER, 1768 ((AGE_USECS(2) << CMB_WR_TIMER_TX_SHIFT) & CMB_WR_TIMER_TX_MASK) | 1769 ((AGE_USECS(2) << CMB_WR_TIMER_RX_SHIFT) & CMB_WR_TIMER_RX_MASK)); 1770 1771 /* Request SMB updates for every seconds. */ 1772 CSR_WRITE_4(sc, AGE_SMB_TIMER, AGE_USECS(1000 * 1000)); 1773 CSR_WRITE_4(sc, AGE_CSMB_CTRL, CSMB_CTRL_SMB_ENB | CSMB_CTRL_CMB_ENB); 1774 1775 /* 1776 * Disable all WOL bits as WOL can interfere normal Rx 1777 * operation. 1778 */ 1779 CSR_WRITE_4(sc, AGE_WOL_CFG, 0); 1780 1781 /* 1782 * Configure Tx/Rx MACs. 1783 * - Auto-padding for short frames. 1784 * - Enable CRC generation. 1785 * Start with full-duplex/1000Mbps media. Actual reconfiguration 1786 * of MAC is followed after link establishment. 1787 */ 1788 CSR_WRITE_4(sc, AGE_MAC_CFG, 1789 MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | 1790 MAC_CFG_FULL_DUPLEX | MAC_CFG_SPEED_1000 | 1791 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 1792 MAC_CFG_PREAMBLE_MASK)); 1793 1794 /* Set up the receive filter. */ 1795 age_iff(sc); 1796 1797 age_rxvlan(sc); 1798 1799 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1800 reg |= MAC_CFG_RXCSUM_ENB; 1801 1802 /* Ack all pending interrupts and clear it. */ 1803 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); 1804 CSR_WRITE_4(sc, AGE_INTR_MASK, AGE_INTRS); 1805 1806 /* Finally enable Tx/Rx MAC. */ 1807 CSR_WRITE_4(sc, AGE_MAC_CFG, reg | MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 1808 1809 sc->age_flags &= ~AGE_FLAG_LINK; 1810 1811 /* Switch to the current media. */ 1812 mii_mediachg(mii); 1813 1814 timeout_add_sec(&sc->age_tick_ch, 1); 1815 1816 ifp->if_flags |= IFF_RUNNING; 1817 ifp->if_flags &= ~IFF_OACTIVE; 1818 1819 return (0); 1820 } 1821 1822 void 1823 age_stop(struct age_softc *sc) 1824 { 1825 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1826 struct age_txdesc *txd; 1827 struct age_rxdesc *rxd; 1828 uint32_t reg; 1829 int i; 1830 1831 /* 1832 * Mark the interface down and cancel the watchdog timer. 1833 */ 1834 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1835 ifp->if_timer = 0; 1836 1837 sc->age_flags &= ~AGE_FLAG_LINK; 1838 timeout_del(&sc->age_tick_ch); 1839 1840 /* 1841 * Disable interrupts. 1842 */ 1843 CSR_WRITE_4(sc, AGE_INTR_MASK, 0); 1844 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0xFFFFFFFF); 1845 1846 /* Stop CMB/SMB updates. */ 1847 CSR_WRITE_4(sc, AGE_CSMB_CTRL, 0); 1848 1849 /* Stop Rx/Tx MAC. */ 1850 age_stop_rxmac(sc); 1851 age_stop_txmac(sc); 1852 1853 /* Stop DMA. */ 1854 CSR_WRITE_4(sc, AGE_DMA_CFG, 1855 CSR_READ_4(sc, AGE_DMA_CFG) & ~(DMA_CFG_RD_ENB | DMA_CFG_WR_ENB)); 1856 1857 /* Stop TxQ/RxQ. */ 1858 CSR_WRITE_4(sc, AGE_TXQ_CFG, 1859 CSR_READ_4(sc, AGE_TXQ_CFG) & ~TXQ_CFG_ENB); 1860 CSR_WRITE_4(sc, AGE_RXQ_CFG, 1861 CSR_READ_4(sc, AGE_RXQ_CFG) & ~RXQ_CFG_ENB); 1862 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 1863 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 1864 break; 1865 DELAY(10); 1866 } 1867 if (i == 0) 1868 printf("%s: stopping Rx/Tx MACs timed out(0x%08x)!\n", 1869 sc->sc_dev.dv_xname, reg); 1870 1871 /* Reclaim Rx buffers that have been processed. */ 1872 if (sc->age_cdata.age_rxhead != NULL) 1873 m_freem(sc->age_cdata.age_rxhead); 1874 AGE_RXCHAIN_RESET(sc); 1875 1876 /* 1877 * Free RX and TX mbufs still in the queues. 1878 */ 1879 for (i = 0; i < AGE_RX_RING_CNT; i++) { 1880 rxd = &sc->age_cdata.age_rxdesc[i]; 1881 if (rxd->rx_m != NULL) { 1882 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 1883 m_freem(rxd->rx_m); 1884 rxd->rx_m = NULL; 1885 } 1886 } 1887 for (i = 0; i < AGE_TX_RING_CNT; i++) { 1888 txd = &sc->age_cdata.age_txdesc[i]; 1889 if (txd->tx_m != NULL) { 1890 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1891 m_freem(txd->tx_m); 1892 txd->tx_m = NULL; 1893 } 1894 } 1895 } 1896 1897 void 1898 age_stats_update(struct age_softc *sc) 1899 { 1900 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1901 struct age_stats *stat; 1902 struct smb *smb; 1903 1904 stat = &sc->age_stat; 1905 1906 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 0, 1907 sc->age_cdata.age_smb_block_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1908 1909 smb = sc->age_rdata.age_smb_block; 1910 if (smb->updated == 0) 1911 return; 1912 1913 /* Rx stats. */ 1914 stat->rx_frames += smb->rx_frames; 1915 stat->rx_bcast_frames += smb->rx_bcast_frames; 1916 stat->rx_mcast_frames += smb->rx_mcast_frames; 1917 stat->rx_pause_frames += smb->rx_pause_frames; 1918 stat->rx_control_frames += smb->rx_control_frames; 1919 stat->rx_crcerrs += smb->rx_crcerrs; 1920 stat->rx_lenerrs += smb->rx_lenerrs; 1921 stat->rx_bytes += smb->rx_bytes; 1922 stat->rx_runts += smb->rx_runts; 1923 stat->rx_fragments += smb->rx_fragments; 1924 stat->rx_pkts_64 += smb->rx_pkts_64; 1925 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 1926 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 1927 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 1928 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 1929 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 1930 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 1931 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 1932 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 1933 stat->rx_desc_oflows += smb->rx_desc_oflows; 1934 stat->rx_alignerrs += smb->rx_alignerrs; 1935 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 1936 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 1937 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 1938 1939 /* Tx stats. */ 1940 stat->tx_frames += smb->tx_frames; 1941 stat->tx_bcast_frames += smb->tx_bcast_frames; 1942 stat->tx_mcast_frames += smb->tx_mcast_frames; 1943 stat->tx_pause_frames += smb->tx_pause_frames; 1944 stat->tx_excess_defer += smb->tx_excess_defer; 1945 stat->tx_control_frames += smb->tx_control_frames; 1946 stat->tx_deferred += smb->tx_deferred; 1947 stat->tx_bytes += smb->tx_bytes; 1948 stat->tx_pkts_64 += smb->tx_pkts_64; 1949 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 1950 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 1951 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 1952 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 1953 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 1954 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 1955 stat->tx_single_colls += smb->tx_single_colls; 1956 stat->tx_multi_colls += smb->tx_multi_colls; 1957 stat->tx_late_colls += smb->tx_late_colls; 1958 stat->tx_excess_colls += smb->tx_excess_colls; 1959 stat->tx_underrun += smb->tx_underrun; 1960 stat->tx_desc_underrun += smb->tx_desc_underrun; 1961 stat->tx_lenerrs += smb->tx_lenerrs; 1962 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 1963 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 1964 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 1965 1966 /* Update counters in ifnet. */ 1967 ifp->if_opackets += smb->tx_frames; 1968 1969 ifp->if_collisions += smb->tx_single_colls + 1970 smb->tx_multi_colls + smb->tx_late_colls + 1971 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT; 1972 1973 ifp->if_oerrors += smb->tx_excess_colls + 1974 smb->tx_late_colls + smb->tx_underrun + 1975 smb->tx_pkts_truncated; 1976 1977 ifp->if_ipackets += smb->rx_frames; 1978 1979 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 1980 smb->rx_runts + smb->rx_pkts_truncated + 1981 smb->rx_fifo_oflows + smb->rx_desc_oflows + 1982 smb->rx_alignerrs; 1983 1984 /* Update done, clear. */ 1985 smb->updated = 0; 1986 1987 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 0, 1988 sc->age_cdata.age_smb_block_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1989 } 1990 1991 void 1992 age_stop_txmac(struct age_softc *sc) 1993 { 1994 uint32_t reg; 1995 int i; 1996 1997 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1998 if ((reg & MAC_CFG_TX_ENB) != 0) { 1999 reg &= ~MAC_CFG_TX_ENB; 2000 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2001 } 2002 /* Stop Tx DMA engine. */ 2003 reg = CSR_READ_4(sc, AGE_DMA_CFG); 2004 if ((reg & DMA_CFG_RD_ENB) != 0) { 2005 reg &= ~DMA_CFG_RD_ENB; 2006 CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 2007 } 2008 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2009 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 2010 (IDLE_STATUS_TXMAC | IDLE_STATUS_DMARD)) == 0) 2011 break; 2012 DELAY(10); 2013 } 2014 if (i == 0) 2015 printf("%s: stopping TxMAC timeout!\n", sc->sc_dev.dv_xname); 2016 } 2017 2018 void 2019 age_stop_rxmac(struct age_softc *sc) 2020 { 2021 uint32_t reg; 2022 int i; 2023 2024 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2025 if ((reg & MAC_CFG_RX_ENB) != 0) { 2026 reg &= ~MAC_CFG_RX_ENB; 2027 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2028 } 2029 /* Stop Rx DMA engine. */ 2030 reg = CSR_READ_4(sc, AGE_DMA_CFG); 2031 if ((reg & DMA_CFG_WR_ENB) != 0) { 2032 reg &= ~DMA_CFG_WR_ENB; 2033 CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 2034 } 2035 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2036 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 2037 (IDLE_STATUS_RXMAC | IDLE_STATUS_DMAWR)) == 0) 2038 break; 2039 DELAY(10); 2040 } 2041 if (i == 0) 2042 printf("%s: stopping RxMAC timeout!\n", sc->sc_dev.dv_xname); 2043 } 2044 2045 void 2046 age_init_tx_ring(struct age_softc *sc) 2047 { 2048 struct age_ring_data *rd; 2049 struct age_txdesc *txd; 2050 int i; 2051 2052 sc->age_cdata.age_tx_prod = 0; 2053 sc->age_cdata.age_tx_cons = 0; 2054 sc->age_cdata.age_tx_cnt = 0; 2055 2056 rd = &sc->age_rdata; 2057 bzero(rd->age_tx_ring, AGE_TX_RING_SZ); 2058 for (i = 0; i < AGE_TX_RING_CNT; i++) { 2059 txd = &sc->age_cdata.age_txdesc[i]; 2060 txd->tx_desc = &rd->age_tx_ring[i]; 2061 txd->tx_m = NULL; 2062 } 2063 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 0, 2064 sc->age_cdata.age_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2065 } 2066 2067 int 2068 age_init_rx_ring(struct age_softc *sc) 2069 { 2070 struct age_ring_data *rd; 2071 struct age_rxdesc *rxd; 2072 int i; 2073 2074 sc->age_cdata.age_rx_cons = AGE_RX_RING_CNT - 1; 2075 rd = &sc->age_rdata; 2076 bzero(rd->age_rx_ring, AGE_RX_RING_SZ); 2077 for (i = 0; i < AGE_RX_RING_CNT; i++) { 2078 rxd = &sc->age_cdata.age_rxdesc[i]; 2079 rxd->rx_m = NULL; 2080 rxd->rx_desc = &rd->age_rx_ring[i]; 2081 if (age_newbuf(sc, rxd) != 0) 2082 return (ENOBUFS); 2083 } 2084 2085 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rx_ring_map, 0, 2086 sc->age_cdata.age_rx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2087 2088 return (0); 2089 } 2090 2091 void 2092 age_init_rr_ring(struct age_softc *sc) 2093 { 2094 struct age_ring_data *rd; 2095 2096 sc->age_cdata.age_rr_cons = 0; 2097 AGE_RXCHAIN_RESET(sc); 2098 2099 rd = &sc->age_rdata; 2100 bzero(rd->age_rr_ring, AGE_RR_RING_SZ); 2101 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 0, 2102 sc->age_cdata.age_rr_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2103 } 2104 2105 void 2106 age_init_cmb_block(struct age_softc *sc) 2107 { 2108 struct age_ring_data *rd; 2109 2110 rd = &sc->age_rdata; 2111 bzero(rd->age_cmb_block, AGE_CMB_BLOCK_SZ); 2112 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 2113 sc->age_cdata.age_cmb_block_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2114 } 2115 2116 void 2117 age_init_smb_block(struct age_softc *sc) 2118 { 2119 struct age_ring_data *rd; 2120 2121 rd = &sc->age_rdata; 2122 bzero(rd->age_smb_block, AGE_SMB_BLOCK_SZ); 2123 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 0, 2124 sc->age_cdata.age_smb_block_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2125 } 2126 2127 int 2128 age_newbuf(struct age_softc *sc, struct age_rxdesc *rxd) 2129 { 2130 struct rx_desc *desc; 2131 struct mbuf *m; 2132 bus_dmamap_t map; 2133 int error; 2134 2135 MGETHDR(m, M_DONTWAIT, MT_DATA); 2136 if (m == NULL) 2137 return (ENOBUFS); 2138 MCLGET(m, M_DONTWAIT); 2139 if (!(m->m_flags & M_EXT)) { 2140 m_freem(m); 2141 return (ENOBUFS); 2142 } 2143 2144 m->m_len = m->m_pkthdr.len = MCLBYTES; 2145 m_adj(m, ETHER_ALIGN); 2146 2147 error = bus_dmamap_load_mbuf(sc->sc_dmat, 2148 sc->age_cdata.age_rx_sparemap, m, BUS_DMA_NOWAIT); 2149 2150 if (error != 0) { 2151 m_freem(m); 2152 printf("%s: can't load RX mbuf\n", sc->sc_dev.dv_xname); 2153 return (error); 2154 } 2155 2156 if (rxd->rx_m != NULL) { 2157 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0, 2158 rxd->rx_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2159 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 2160 } 2161 map = rxd->rx_dmamap; 2162 rxd->rx_dmamap = sc->age_cdata.age_rx_sparemap; 2163 sc->age_cdata.age_rx_sparemap = map; 2164 rxd->rx_m = m; 2165 2166 desc = rxd->rx_desc; 2167 desc->addr = htole64(rxd->rx_dmamap->dm_segs[0].ds_addr); 2168 desc->len = 2169 htole32((rxd->rx_dmamap->dm_segs[0].ds_len & AGE_RD_LEN_MASK) << 2170 AGE_RD_LEN_SHIFT); 2171 2172 return (0); 2173 } 2174 2175 void 2176 age_rxvlan(struct age_softc *sc) 2177 { 2178 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 2179 uint32_t reg; 2180 2181 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2182 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 2183 if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) 2184 reg |= MAC_CFG_VLAN_TAG_STRIP; 2185 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2186 } 2187 2188 void 2189 age_iff(struct age_softc *sc) 2190 { 2191 struct arpcom *ac = &sc->sc_arpcom; 2192 struct ifnet *ifp = &ac->ac_if; 2193 struct ether_multi *enm; 2194 struct ether_multistep step; 2195 uint32_t crc; 2196 uint32_t mchash[2]; 2197 uint32_t rxcfg; 2198 2199 rxcfg = CSR_READ_4(sc, AGE_MAC_CFG); 2200 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 2201 ifp->if_flags &= ~IFF_ALLMULTI; 2202 2203 /* 2204 * Always accept broadcast frames. 2205 */ 2206 rxcfg |= MAC_CFG_BCAST; 2207 2208 if (ifp->if_flags & IFF_PROMISC || ac->ac_multirangecnt > 0) { 2209 ifp->if_flags |= IFF_ALLMULTI; 2210 if (ifp->if_flags & IFF_PROMISC) 2211 rxcfg |= MAC_CFG_PROMISC; 2212 else 2213 rxcfg |= MAC_CFG_ALLMULTI; 2214 mchash[0] = mchash[1] = 0xFFFFFFFF; 2215 } else { 2216 /* Program new filter. */ 2217 bzero(mchash, sizeof(mchash)); 2218 2219 ETHER_FIRST_MULTI(step, ac, enm); 2220 while (enm != NULL) { 2221 crc = ether_crc32_be(enm->enm_addrlo, 2222 ETHER_ADDR_LEN); 2223 2224 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 2225 2226 ETHER_NEXT_MULTI(step, enm); 2227 } 2228 } 2229 2230 CSR_WRITE_4(sc, AGE_MAR0, mchash[0]); 2231 CSR_WRITE_4(sc, AGE_MAR1, mchash[1]); 2232 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg); 2233 } 2234