1 /* $OpenBSD: if_age.c,v 1.17 2011/09/15 01:51:40 kevlo Exp $ */ 2 3 /*- 4 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* Driver for Attansic Technology Corp. L1 Gigabit Ethernet. */ 31 32 #include "bpfilter.h" 33 #include "vlan.h" 34 35 #include <sys/param.h> 36 #include <sys/endian.h> 37 #include <sys/systm.h> 38 #include <sys/types.h> 39 #include <sys/sockio.h> 40 #include <sys/mbuf.h> 41 #include <sys/queue.h> 42 #include <sys/kernel.h> 43 #include <sys/device.h> 44 #include <sys/timeout.h> 45 #include <sys/socket.h> 46 47 #include <machine/bus.h> 48 49 #include <net/if.h> 50 #include <net/if_dl.h> 51 #include <net/if_media.h> 52 53 #ifdef INET 54 #include <netinet/in.h> 55 #include <netinet/in_systm.h> 56 #include <netinet/in_var.h> 57 #include <netinet/ip.h> 58 #include <netinet/if_ether.h> 59 #endif 60 61 #include <net/if_types.h> 62 #include <net/if_vlan_var.h> 63 64 #if NBPFILTER > 0 65 #include <net/bpf.h> 66 #endif 67 68 #include <dev/rndvar.h> 69 70 #include <dev/mii/mii.h> 71 #include <dev/mii/miivar.h> 72 73 #include <dev/pci/pcireg.h> 74 #include <dev/pci/pcivar.h> 75 #include <dev/pci/pcidevs.h> 76 77 #include <dev/pci/if_agereg.h> 78 79 int age_match(struct device *, void *, void *); 80 void age_attach(struct device *, struct device *, void *); 81 int age_detach(struct device *, int); 82 83 int age_miibus_readreg(struct device *, int, int); 84 void age_miibus_writereg(struct device *, int, int, int); 85 void age_miibus_statchg(struct device *); 86 87 int age_init(struct ifnet *); 88 int age_ioctl(struct ifnet *, u_long, caddr_t); 89 void age_start(struct ifnet *); 90 void age_watchdog(struct ifnet *); 91 void age_mediastatus(struct ifnet *, struct ifmediareq *); 92 int age_mediachange(struct ifnet *); 93 94 int age_intr(void *); 95 int age_dma_alloc(struct age_softc *); 96 void age_dma_free(struct age_softc *); 97 void age_get_macaddr(struct age_softc *); 98 void age_phy_reset(struct age_softc *); 99 100 int age_encap(struct age_softc *, struct mbuf **); 101 void age_init_tx_ring(struct age_softc *); 102 int age_init_rx_ring(struct age_softc *); 103 void age_init_rr_ring(struct age_softc *); 104 void age_init_cmb_block(struct age_softc *); 105 void age_init_smb_block(struct age_softc *); 106 int age_newbuf(struct age_softc *, struct age_rxdesc *); 107 void age_mac_config(struct age_softc *); 108 void age_txintr(struct age_softc *, int); 109 void age_rxeof(struct age_softc *sc, struct rx_rdesc *); 110 void age_rxintr(struct age_softc *, int); 111 void age_tick(void *); 112 void age_reset(struct age_softc *); 113 void age_stop(struct age_softc *); 114 void age_stats_update(struct age_softc *); 115 void age_stop_txmac(struct age_softc *); 116 void age_stop_rxmac(struct age_softc *); 117 void age_rxvlan(struct age_softc *sc); 118 void age_iff(struct age_softc *); 119 120 const struct pci_matchid age_devices[] = { 121 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L1 } 122 }; 123 124 struct cfattach age_ca = { 125 sizeof (struct age_softc), age_match, age_attach 126 }; 127 128 struct cfdriver age_cd = { 129 NULL, "age", DV_IFNET 130 }; 131 132 int agedebug = 0; 133 #define DPRINTF(x) do { if (agedebug) printf x; } while (0) 134 135 #define AGE_CSUM_FEATURES (M_TCP_CSUM_OUT | M_UDP_CSUM_OUT) 136 137 int 138 age_match(struct device *dev, void *match, void *aux) 139 { 140 return pci_matchbyid((struct pci_attach_args *)aux, age_devices, 141 sizeof (age_devices) / sizeof (age_devices[0])); 142 } 143 144 void 145 age_attach(struct device *parent, struct device *self, void *aux) 146 { 147 struct age_softc *sc = (struct age_softc *)self; 148 struct pci_attach_args *pa = aux; 149 pci_chipset_tag_t pc = pa->pa_pc; 150 pci_intr_handle_t ih; 151 const char *intrstr; 152 struct ifnet *ifp; 153 pcireg_t memtype; 154 int error = 0; 155 156 /* 157 * Allocate IO memory 158 */ 159 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, AGE_PCIR_BAR); 160 if (pci_mapreg_map(pa, AGE_PCIR_BAR, memtype, 0, &sc->sc_mem_bt, 161 &sc->sc_mem_bh, NULL, &sc->sc_mem_size, 0)) { 162 printf(": can't map mem space\n"); 163 return; 164 } 165 166 if (pci_intr_map_msi(pa, &ih) != 0 && pci_intr_map(pa, &ih) != 0) { 167 printf(": can't map interrupt\n"); 168 goto fail; 169 } 170 171 /* 172 * Allocate IRQ 173 */ 174 intrstr = pci_intr_string(pc, ih); 175 sc->sc_irq_handle = pci_intr_establish(pc, ih, IPL_NET, age_intr, sc, 176 sc->sc_dev.dv_xname); 177 if (sc->sc_irq_handle == NULL) { 178 printf(": could not establish interrupt"); 179 if (intrstr != NULL) 180 printf(" at %s", intrstr); 181 printf("\n"); 182 goto fail; 183 } 184 printf(": %s", intrstr); 185 186 sc->sc_dmat = pa->pa_dmat; 187 sc->sc_pct = pa->pa_pc; 188 sc->sc_pcitag = pa->pa_tag; 189 190 /* Set PHY address. */ 191 sc->age_phyaddr = AGE_PHY_ADDR; 192 193 /* Reset PHY. */ 194 age_phy_reset(sc); 195 196 /* Reset the ethernet controller. */ 197 age_reset(sc); 198 199 /* Get PCI and chip id/revision. */ 200 sc->age_rev = PCI_REVISION(pa->pa_class); 201 sc->age_chip_rev = CSR_READ_4(sc, AGE_MASTER_CFG) >> 202 MASTER_CHIP_REV_SHIFT; 203 if (agedebug) { 204 printf("%s: PCI device revision : 0x%04x\n", 205 sc->sc_dev.dv_xname, sc->age_rev); 206 printf("%s: Chip id/revision : 0x%04x\n", 207 sc->sc_dev.dv_xname, sc->age_chip_rev); 208 } 209 210 if (agedebug) { 211 printf("%s: %d Tx FIFO, %d Rx FIFO\n", sc->sc_dev.dv_xname, 212 CSR_READ_4(sc, AGE_SRAM_TX_FIFO_LEN), 213 CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN)); 214 } 215 216 /* Set max allowable DMA size. */ 217 sc->age_dma_rd_burst = DMA_CFG_RD_BURST_128; 218 sc->age_dma_wr_burst = DMA_CFG_WR_BURST_128; 219 220 /* Allocate DMA stuffs */ 221 error = age_dma_alloc(sc); 222 if (error) 223 goto fail; 224 225 /* Load station address. */ 226 age_get_macaddr(sc); 227 228 ifp = &sc->sc_arpcom.ac_if; 229 ifp->if_softc = sc; 230 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 231 ifp->if_ioctl = age_ioctl; 232 ifp->if_start = age_start; 233 ifp->if_watchdog = age_watchdog; 234 ifp->if_baudrate = IF_Gbps(1); 235 IFQ_SET_MAXLEN(&ifp->if_snd, AGE_TX_RING_CNT - 1); 236 IFQ_SET_READY(&ifp->if_snd); 237 bcopy(sc->age_eaddr, sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN); 238 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 239 240 ifp->if_capabilities = IFCAP_VLAN_MTU; 241 242 #ifdef AGE_CHECKSUM 243 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 244 IFCAP_CSUM_UDPv4; 245 #endif 246 247 #if NVLAN > 0 248 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 249 #endif 250 251 printf(", address %s\n", ether_sprintf(sc->sc_arpcom.ac_enaddr)); 252 253 /* Set up MII bus. */ 254 sc->sc_miibus.mii_ifp = ifp; 255 sc->sc_miibus.mii_readreg = age_miibus_readreg; 256 sc->sc_miibus.mii_writereg = age_miibus_writereg; 257 sc->sc_miibus.mii_statchg = age_miibus_statchg; 258 259 ifmedia_init(&sc->sc_miibus.mii_media, 0, age_mediachange, 260 age_mediastatus); 261 mii_attach(self, &sc->sc_miibus, 0xffffffff, MII_PHY_ANY, 262 MII_OFFSET_ANY, MIIF_DOPAUSE); 263 264 if (LIST_FIRST(&sc->sc_miibus.mii_phys) == NULL) { 265 printf("%s: no PHY found!\n", sc->sc_dev.dv_xname); 266 ifmedia_add(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL, 267 0, NULL); 268 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL); 269 } else 270 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_AUTO); 271 272 if_attach(ifp); 273 ether_ifattach(ifp); 274 275 timeout_set(&sc->age_tick_ch, age_tick, sc); 276 277 return; 278 fail: 279 age_dma_free(sc); 280 if (sc->sc_irq_handle != NULL) 281 pci_intr_disestablish(pc, sc->sc_irq_handle); 282 if (sc->sc_mem_size) 283 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 284 } 285 286 int 287 age_detach(struct device *self, int flags) 288 { 289 struct age_softc *sc = (struct age_softc *)self; 290 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 291 int s; 292 293 s = splnet(); 294 age_stop(sc); 295 splx(s); 296 297 mii_detach(&sc->sc_miibus, MII_PHY_ANY, MII_OFFSET_ANY); 298 299 /* Delete all remaining media. */ 300 ifmedia_delete_instance(&sc->sc_miibus.mii_media, IFM_INST_ANY); 301 302 ether_ifdetach(ifp); 303 if_detach(ifp); 304 age_dma_free(sc); 305 306 if (sc->sc_irq_handle != NULL) { 307 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 308 sc->sc_irq_handle = NULL; 309 } 310 311 return (0); 312 } 313 314 /* 315 * Read a PHY register on the MII of the L1. 316 */ 317 int 318 age_miibus_readreg(struct device *dev, int phy, int reg) 319 { 320 struct age_softc *sc = (struct age_softc *)dev; 321 uint32_t v; 322 int i; 323 324 if (phy != sc->age_phyaddr) 325 return (0); 326 327 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 328 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 329 for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 330 DELAY(1); 331 v = CSR_READ_4(sc, AGE_MDIO); 332 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 333 break; 334 } 335 336 if (i == 0) { 337 printf("%s: phy read timeout: phy %d, reg %d\n", 338 sc->sc_dev.dv_xname, phy, reg); 339 return (0); 340 } 341 342 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 343 } 344 345 /* 346 * Write a PHY register on the MII of the L1. 347 */ 348 void 349 age_miibus_writereg(struct device *dev, int phy, int reg, int val) 350 { 351 struct age_softc *sc = (struct age_softc *)dev; 352 uint32_t v; 353 int i; 354 355 if (phy != sc->age_phyaddr) 356 return; 357 358 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 359 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 360 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 361 362 for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 363 DELAY(1); 364 v = CSR_READ_4(sc, AGE_MDIO); 365 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 366 break; 367 } 368 369 if (i == 0) { 370 printf("%s: phy write timeout: phy %d, reg %d\n", 371 sc->sc_dev.dv_xname, phy, reg); 372 } 373 } 374 375 /* 376 * Callback from MII layer when media changes. 377 */ 378 void 379 age_miibus_statchg(struct device *dev) 380 { 381 struct age_softc *sc = (struct age_softc *)dev; 382 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 383 struct mii_data *mii = &sc->sc_miibus; 384 385 if ((ifp->if_flags & IFF_RUNNING) == 0) 386 return; 387 388 sc->age_flags &= ~AGE_FLAG_LINK; 389 if ((mii->mii_media_status & IFM_AVALID) != 0) { 390 switch (IFM_SUBTYPE(mii->mii_media_active)) { 391 case IFM_10_T: 392 case IFM_100_TX: 393 case IFM_1000_T: 394 sc->age_flags |= AGE_FLAG_LINK; 395 break; 396 default: 397 break; 398 } 399 } 400 401 /* Stop Rx/Tx MACs. */ 402 age_stop_rxmac(sc); 403 age_stop_txmac(sc); 404 405 /* Program MACs with resolved speed/duplex/flow-control. */ 406 if ((sc->age_flags & AGE_FLAG_LINK) != 0) { 407 uint32_t reg; 408 409 age_mac_config(sc); 410 reg = CSR_READ_4(sc, AGE_MAC_CFG); 411 /* Restart DMA engine and Tx/Rx MAC. */ 412 CSR_WRITE_4(sc, AGE_DMA_CFG, CSR_READ_4(sc, AGE_DMA_CFG) | 413 DMA_CFG_RD_ENB | DMA_CFG_WR_ENB); 414 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 415 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 416 } 417 } 418 419 /* 420 * Get the current interface media status. 421 */ 422 void 423 age_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 424 { 425 struct age_softc *sc = ifp->if_softc; 426 struct mii_data *mii = &sc->sc_miibus; 427 428 mii_pollstat(mii); 429 ifmr->ifm_status = mii->mii_media_status; 430 ifmr->ifm_active = mii->mii_media_active; 431 } 432 433 /* 434 * Set hardware to newly-selected media. 435 */ 436 int 437 age_mediachange(struct ifnet *ifp) 438 { 439 struct age_softc *sc = ifp->if_softc; 440 struct mii_data *mii = &sc->sc_miibus; 441 int error; 442 443 if (mii->mii_instance != 0) { 444 struct mii_softc *miisc; 445 446 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 447 mii_phy_reset(miisc); 448 } 449 error = mii_mediachg(mii); 450 451 return (error); 452 } 453 454 int 455 age_intr(void *arg) 456 { 457 struct age_softc *sc = arg; 458 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 459 struct cmb *cmb; 460 uint32_t status; 461 462 status = CSR_READ_4(sc, AGE_INTR_STATUS); 463 if (status == 0 || (status & AGE_INTRS) == 0) 464 return (0); 465 466 /* Disable interrupts. */ 467 CSR_WRITE_4(sc, AGE_INTR_STATUS, status | INTR_DIS_INT); 468 469 cmb = sc->age_rdata.age_cmb_block; 470 471 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 472 sc->age_cdata.age_cmb_block_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 473 status = letoh32(cmb->intr_status); 474 if ((status & AGE_INTRS) == 0) 475 goto back; 476 477 sc->age_tpd_cons = (letoh32(cmb->tpd_cons) & TPD_CONS_MASK) >> 478 TPD_CONS_SHIFT; 479 sc->age_rr_prod = (letoh32(cmb->rprod_cons) & RRD_PROD_MASK) >> 480 RRD_PROD_SHIFT; 481 482 /* Let hardware know CMB was served. */ 483 cmb->intr_status = 0; 484 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 485 sc->age_cdata.age_cmb_block_map->dm_mapsize, 486 BUS_DMASYNC_PREWRITE); 487 488 if (ifp->if_flags & IFF_RUNNING) { 489 if (status & INTR_CMB_RX) 490 age_rxintr(sc, sc->age_rr_prod); 491 492 if (status & INTR_CMB_TX) 493 age_txintr(sc, sc->age_tpd_cons); 494 495 if (status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) { 496 if (status & INTR_DMA_RD_TO_RST) 497 printf("%s: DMA read error! -- resetting\n", 498 sc->sc_dev.dv_xname); 499 if (status & INTR_DMA_WR_TO_RST) 500 printf("%s: DMA write error! -- resetting\n", 501 sc->sc_dev.dv_xname); 502 age_init(ifp); 503 } 504 505 age_start(ifp); 506 507 if (status & INTR_SMB) 508 age_stats_update(sc); 509 } 510 511 /* Check whether CMB was updated while serving Tx/Rx/SMB handler. */ 512 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 513 sc->age_cdata.age_cmb_block_map->dm_mapsize, 514 BUS_DMASYNC_POSTREAD); 515 516 back: 517 /* Re-enable interrupts. */ 518 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); 519 520 return (1); 521 } 522 523 void 524 age_get_macaddr(struct age_softc *sc) 525 { 526 uint32_t ea[2], reg; 527 int i, vpdc; 528 529 reg = CSR_READ_4(sc, AGE_SPI_CTRL); 530 if ((reg & SPI_VPD_ENB) != 0) { 531 /* Get VPD stored in TWSI EEPROM. */ 532 reg &= ~SPI_VPD_ENB; 533 CSR_WRITE_4(sc, AGE_SPI_CTRL, reg); 534 } 535 536 if (pci_get_capability(sc->sc_pct, sc->sc_pcitag, 537 PCI_CAP_VPD, &vpdc, NULL)) { 538 /* 539 * PCI VPD capability found, let TWSI reload EEPROM. 540 * This will set Ethernet address of controller. 541 */ 542 CSR_WRITE_4(sc, AGE_TWSI_CTRL, CSR_READ_4(sc, AGE_TWSI_CTRL) | 543 TWSI_CTRL_SW_LD_START); 544 for (i = 100; i > 0; i--) { 545 DELAY(1000); 546 reg = CSR_READ_4(sc, AGE_TWSI_CTRL); 547 if ((reg & TWSI_CTRL_SW_LD_START) == 0) 548 break; 549 } 550 if (i == 0) 551 printf("%s: reloading EEPROM timeout!\n", 552 sc->sc_dev.dv_xname); 553 } else { 554 if (agedebug) 555 printf("%s: PCI VPD capability not found!\n", 556 sc->sc_dev.dv_xname); 557 } 558 559 ea[0] = CSR_READ_4(sc, AGE_PAR0); 560 ea[1] = CSR_READ_4(sc, AGE_PAR1); 561 sc->age_eaddr[0] = (ea[1] >> 8) & 0xFF; 562 sc->age_eaddr[1] = (ea[1] >> 0) & 0xFF; 563 sc->age_eaddr[2] = (ea[0] >> 24) & 0xFF; 564 sc->age_eaddr[3] = (ea[0] >> 16) & 0xFF; 565 sc->age_eaddr[4] = (ea[0] >> 8) & 0xFF; 566 sc->age_eaddr[5] = (ea[0] >> 0) & 0xFF; 567 } 568 569 void 570 age_phy_reset(struct age_softc *sc) 571 { 572 uint16_t reg, pn; 573 int i, linkup; 574 575 /* Reset PHY. */ 576 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_RST); 577 DELAY(2000); 578 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_CLR); 579 DELAY(2000); 580 581 #define ATPHY_DBG_ADDR 0x1D 582 #define ATPHY_DBG_DATA 0x1E 583 #define ATPHY_CDTC 0x16 584 #define PHY_CDTC_ENB 0x0001 585 #define PHY_CDTC_POFF 8 586 #define ATPHY_CDTS 0x1C 587 #define PHY_CDTS_STAT_OK 0x0000 588 #define PHY_CDTS_STAT_SHORT 0x0100 589 #define PHY_CDTS_STAT_OPEN 0x0200 590 #define PHY_CDTS_STAT_INVAL 0x0300 591 #define PHY_CDTS_STAT_MASK 0x0300 592 593 /* Check power saving mode. Magic from Linux. */ 594 age_miibus_writereg(&sc->sc_dev, sc->age_phyaddr, MII_BMCR, BMCR_RESET); 595 for (linkup = 0, pn = 0; pn < 4; pn++) { 596 age_miibus_writereg(&sc->sc_dev, sc->age_phyaddr, ATPHY_CDTC, 597 (pn << PHY_CDTC_POFF) | PHY_CDTC_ENB); 598 for (i = 200; i > 0; i--) { 599 DELAY(1000); 600 reg = age_miibus_readreg(&sc->sc_dev, sc->age_phyaddr, 601 ATPHY_CDTC); 602 if ((reg & PHY_CDTC_ENB) == 0) 603 break; 604 } 605 DELAY(1000); 606 reg = age_miibus_readreg(&sc->sc_dev, sc->age_phyaddr, 607 ATPHY_CDTS); 608 if ((reg & PHY_CDTS_STAT_MASK) != PHY_CDTS_STAT_OPEN) { 609 linkup++; 610 break; 611 } 612 } 613 age_miibus_writereg(&sc->sc_dev, sc->age_phyaddr, MII_BMCR, 614 BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 615 if (linkup == 0) { 616 age_miibus_writereg(&sc->sc_dev, sc->age_phyaddr, 617 ATPHY_DBG_ADDR, 0); 618 age_miibus_writereg(&sc->sc_dev, sc->age_phyaddr, 619 ATPHY_DBG_DATA, 0x124E); 620 age_miibus_writereg(&sc->sc_dev, sc->age_phyaddr, 621 ATPHY_DBG_ADDR, 1); 622 reg = age_miibus_readreg(&sc->sc_dev, sc->age_phyaddr, 623 ATPHY_DBG_DATA); 624 age_miibus_writereg(&sc->sc_dev, sc->age_phyaddr, 625 ATPHY_DBG_DATA, reg | 0x03); 626 /* XXX */ 627 DELAY(1500 * 1000); 628 age_miibus_writereg(&sc->sc_dev, sc->age_phyaddr, 629 ATPHY_DBG_ADDR, 0); 630 age_miibus_writereg(&sc->sc_dev, sc->age_phyaddr, 631 ATPHY_DBG_DATA, 0x024E); 632 } 633 634 #undef ATPHY_DBG_ADDR 635 #undef ATPHY_DBG_DATA 636 #undef ATPHY_CDTC 637 #undef PHY_CDTC_ENB 638 #undef PHY_CDTC_POFF 639 #undef ATPHY_CDTS 640 #undef PHY_CDTS_STAT_OK 641 #undef PHY_CDTS_STAT_SHORT 642 #undef PHY_CDTS_STAT_OPEN 643 #undef PHY_CDTS_STAT_INVAL 644 #undef PHY_CDTS_STAT_MASK 645 } 646 647 int 648 age_dma_alloc(struct age_softc *sc) 649 { 650 struct age_txdesc *txd; 651 struct age_rxdesc *rxd; 652 int nsegs, error, i; 653 654 /* 655 * Create DMA stuffs for TX ring 656 */ 657 error = bus_dmamap_create(sc->sc_dmat, AGE_TX_RING_SZ, 1, 658 AGE_TX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->age_cdata.age_tx_ring_map); 659 if (error) 660 return (ENOBUFS); 661 662 /* Allocate DMA'able memory for TX ring */ 663 error = bus_dmamem_alloc(sc->sc_dmat, AGE_TX_RING_SZ, 664 ETHER_ALIGN, 0, &sc->age_rdata.age_tx_ring_seg, 1, 665 &nsegs, BUS_DMA_WAITOK | BUS_DMA_ZERO); 666 if (error) { 667 printf("%s: could not allocate DMA'able memory for Tx ring.\n", 668 sc->sc_dev.dv_xname); 669 return error; 670 } 671 672 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_tx_ring_seg, 673 nsegs, AGE_TX_RING_SZ, (caddr_t *)&sc->age_rdata.age_tx_ring, 674 BUS_DMA_NOWAIT); 675 if (error) 676 return (ENOBUFS); 677 678 /* Load the DMA map for Tx ring. */ 679 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 680 sc->age_rdata.age_tx_ring, AGE_TX_RING_SZ, NULL, BUS_DMA_WAITOK); 681 if (error) { 682 printf("%s: could not load DMA'able memory for Tx ring.\n", 683 sc->sc_dev.dv_xname); 684 bus_dmamem_free(sc->sc_dmat, 685 (bus_dma_segment_t *)&sc->age_rdata.age_tx_ring, 1); 686 return error; 687 } 688 689 sc->age_rdata.age_tx_ring_paddr = 690 sc->age_cdata.age_tx_ring_map->dm_segs[0].ds_addr; 691 692 /* 693 * Create DMA stuffs for RX ring 694 */ 695 error = bus_dmamap_create(sc->sc_dmat, AGE_RX_RING_SZ, 1, 696 AGE_RX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->age_cdata.age_rx_ring_map); 697 if (error) 698 return (ENOBUFS); 699 700 /* Allocate DMA'able memory for RX ring */ 701 error = bus_dmamem_alloc(sc->sc_dmat, AGE_RX_RING_SZ, 702 ETHER_ALIGN, 0, &sc->age_rdata.age_rx_ring_seg, 1, 703 &nsegs, BUS_DMA_WAITOK | BUS_DMA_ZERO); 704 if (error) { 705 printf("%s: could not allocate DMA'able memory for Rx ring.\n", 706 sc->sc_dev.dv_xname); 707 return error; 708 } 709 710 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_rx_ring_seg, 711 nsegs, AGE_RX_RING_SZ, (caddr_t *)&sc->age_rdata.age_rx_ring, 712 BUS_DMA_NOWAIT); 713 if (error) 714 return (ENOBUFS); 715 716 /* Load the DMA map for Rx ring. */ 717 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_rx_ring_map, 718 sc->age_rdata.age_rx_ring, AGE_RX_RING_SZ, NULL, BUS_DMA_WAITOK); 719 if (error) { 720 printf("%s: could not load DMA'able memory for Rx ring.\n", 721 sc->sc_dev.dv_xname); 722 bus_dmamem_free(sc->sc_dmat, 723 (bus_dma_segment_t *)sc->age_rdata.age_rx_ring, 1); 724 return error; 725 } 726 727 sc->age_rdata.age_rx_ring_paddr = 728 sc->age_cdata.age_rx_ring_map->dm_segs[0].ds_addr; 729 730 /* 731 * Create DMA stuffs for RX return ring 732 */ 733 error = bus_dmamap_create(sc->sc_dmat, AGE_RR_RING_SZ, 1, 734 AGE_RR_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->age_cdata.age_rr_ring_map); 735 if (error) 736 return (ENOBUFS); 737 738 /* Allocate DMA'able memory for RX return ring */ 739 error = bus_dmamem_alloc(sc->sc_dmat, AGE_RR_RING_SZ, 740 ETHER_ALIGN, 0, &sc->age_rdata.age_rr_ring_seg, 1, 741 &nsegs, BUS_DMA_WAITOK | BUS_DMA_ZERO); 742 if (error) { 743 printf("%s: could not allocate DMA'able memory for Rx " 744 "return ring.\n", sc->sc_dev.dv_xname); 745 return error; 746 } 747 748 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_rr_ring_seg, 749 nsegs, AGE_RR_RING_SZ, (caddr_t *)&sc->age_rdata.age_rr_ring, 750 BUS_DMA_NOWAIT); 751 if (error) 752 return (ENOBUFS); 753 754 /* Load the DMA map for Rx return ring. */ 755 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 756 sc->age_rdata.age_rr_ring, AGE_RR_RING_SZ, NULL, BUS_DMA_WAITOK); 757 if (error) { 758 printf("%s: could not load DMA'able memory for Rx return ring." 759 "\n", sc->sc_dev.dv_xname); 760 bus_dmamem_free(sc->sc_dmat, 761 (bus_dma_segment_t *)&sc->age_rdata.age_rr_ring, 1); 762 return error; 763 } 764 765 sc->age_rdata.age_rr_ring_paddr = 766 sc->age_cdata.age_rr_ring_map->dm_segs[0].ds_addr; 767 768 /* 769 * Create DMA stuffs for CMB block 770 */ 771 error = bus_dmamap_create(sc->sc_dmat, AGE_CMB_BLOCK_SZ, 1, 772 AGE_CMB_BLOCK_SZ, 0, BUS_DMA_NOWAIT, 773 &sc->age_cdata.age_cmb_block_map); 774 if (error) 775 return (ENOBUFS); 776 777 /* Allocate DMA'able memory for CMB block */ 778 error = bus_dmamem_alloc(sc->sc_dmat, AGE_CMB_BLOCK_SZ, 779 ETHER_ALIGN, 0, &sc->age_rdata.age_cmb_block_seg, 1, 780 &nsegs, BUS_DMA_WAITOK | BUS_DMA_ZERO); 781 if (error) { 782 printf("%s: could not allocate DMA'able memory for " 783 "CMB block\n", sc->sc_dev.dv_xname); 784 return error; 785 } 786 787 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_cmb_block_seg, 788 nsegs, AGE_CMB_BLOCK_SZ, (caddr_t *)&sc->age_rdata.age_cmb_block, 789 BUS_DMA_NOWAIT); 790 if (error) 791 return (ENOBUFS); 792 793 /* Load the DMA map for CMB block. */ 794 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 795 sc->age_rdata.age_cmb_block, AGE_CMB_BLOCK_SZ, NULL, 796 BUS_DMA_WAITOK); 797 if (error) { 798 printf("%s: could not load DMA'able memory for CMB block\n", 799 sc->sc_dev.dv_xname); 800 bus_dmamem_free(sc->sc_dmat, 801 (bus_dma_segment_t *)&sc->age_rdata.age_cmb_block, 1); 802 return error; 803 } 804 805 sc->age_rdata.age_cmb_block_paddr = 806 sc->age_cdata.age_cmb_block_map->dm_segs[0].ds_addr; 807 808 /* 809 * Create DMA stuffs for SMB block 810 */ 811 error = bus_dmamap_create(sc->sc_dmat, AGE_SMB_BLOCK_SZ, 1, 812 AGE_SMB_BLOCK_SZ, 0, BUS_DMA_NOWAIT, 813 &sc->age_cdata.age_smb_block_map); 814 if (error) 815 return (ENOBUFS); 816 817 /* Allocate DMA'able memory for SMB block */ 818 error = bus_dmamem_alloc(sc->sc_dmat, AGE_SMB_BLOCK_SZ, 819 ETHER_ALIGN, 0, &sc->age_rdata.age_smb_block_seg, 1, 820 &nsegs, BUS_DMA_WAITOK | BUS_DMA_ZERO); 821 if (error) { 822 printf("%s: could not allocate DMA'able memory for " 823 "SMB block\n", sc->sc_dev.dv_xname); 824 return error; 825 } 826 827 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_smb_block_seg, 828 nsegs, AGE_SMB_BLOCK_SZ, (caddr_t *)&sc->age_rdata.age_smb_block, 829 BUS_DMA_NOWAIT); 830 if (error) 831 return (ENOBUFS); 832 833 /* Load the DMA map for SMB block */ 834 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 835 sc->age_rdata.age_smb_block, AGE_SMB_BLOCK_SZ, NULL, 836 BUS_DMA_WAITOK); 837 if (error) { 838 printf("%s: could not load DMA'able memory for SMB block\n", 839 sc->sc_dev.dv_xname); 840 bus_dmamem_free(sc->sc_dmat, 841 (bus_dma_segment_t *)&sc->age_rdata.age_smb_block, 1); 842 return error; 843 } 844 845 sc->age_rdata.age_smb_block_paddr = 846 sc->age_cdata.age_smb_block_map->dm_segs[0].ds_addr; 847 848 /* Create DMA maps for Tx buffers. */ 849 for (i = 0; i < AGE_TX_RING_CNT; i++) { 850 txd = &sc->age_cdata.age_txdesc[i]; 851 txd->tx_m = NULL; 852 txd->tx_dmamap = NULL; 853 error = bus_dmamap_create(sc->sc_dmat, AGE_TSO_MAXSIZE, 854 AGE_MAXTXSEGS, AGE_TSO_MAXSEGSIZE, 0, BUS_DMA_NOWAIT, 855 &txd->tx_dmamap); 856 if (error) { 857 printf("%s: could not create Tx dmamap.\n", 858 sc->sc_dev.dv_xname); 859 return error; 860 } 861 } 862 863 /* Create DMA maps for Rx buffers. */ 864 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 865 BUS_DMA_NOWAIT, &sc->age_cdata.age_rx_sparemap); 866 if (error) { 867 printf("%s: could not create spare Rx dmamap.\n", 868 sc->sc_dev.dv_xname); 869 return error; 870 } 871 for (i = 0; i < AGE_RX_RING_CNT; i++) { 872 rxd = &sc->age_cdata.age_rxdesc[i]; 873 rxd->rx_m = NULL; 874 rxd->rx_dmamap = NULL; 875 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 876 MCLBYTES, 0, BUS_DMA_NOWAIT, &rxd->rx_dmamap); 877 if (error) { 878 printf("%s: could not create Rx dmamap.\n", 879 sc->sc_dev.dv_xname); 880 return error; 881 } 882 } 883 884 return (0); 885 } 886 887 void 888 age_dma_free(struct age_softc *sc) 889 { 890 struct age_txdesc *txd; 891 struct age_rxdesc *rxd; 892 int i; 893 894 /* Tx buffers */ 895 for (i = 0; i < AGE_TX_RING_CNT; i++) { 896 txd = &sc->age_cdata.age_txdesc[i]; 897 if (txd->tx_dmamap != NULL) { 898 bus_dmamap_destroy(sc->sc_dmat, txd->tx_dmamap); 899 txd->tx_dmamap = NULL; 900 } 901 } 902 /* Rx buffers */ 903 for (i = 0; i < AGE_RX_RING_CNT; i++) { 904 rxd = &sc->age_cdata.age_rxdesc[i]; 905 if (rxd->rx_dmamap != NULL) { 906 bus_dmamap_destroy(sc->sc_dmat, rxd->rx_dmamap); 907 rxd->rx_dmamap = NULL; 908 } 909 } 910 if (sc->age_cdata.age_rx_sparemap != NULL) { 911 bus_dmamap_destroy(sc->sc_dmat, sc->age_cdata.age_rx_sparemap); 912 sc->age_cdata.age_rx_sparemap = NULL; 913 } 914 915 /* Tx ring. */ 916 if (sc->age_cdata.age_tx_ring_map != NULL) 917 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_tx_ring_map); 918 if (sc->age_cdata.age_tx_ring_map != NULL && 919 sc->age_rdata.age_tx_ring != NULL) 920 bus_dmamem_free(sc->sc_dmat, 921 (bus_dma_segment_t *)sc->age_rdata.age_tx_ring, 1); 922 sc->age_rdata.age_tx_ring = NULL; 923 sc->age_cdata.age_tx_ring_map = NULL; 924 925 /* Rx ring. */ 926 if (sc->age_cdata.age_rx_ring_map != NULL) 927 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_rx_ring_map); 928 if (sc->age_cdata.age_rx_ring_map != NULL && 929 sc->age_rdata.age_rx_ring != NULL) 930 bus_dmamem_free(sc->sc_dmat, 931 (bus_dma_segment_t *)sc->age_rdata.age_rx_ring, 1); 932 sc->age_rdata.age_rx_ring = NULL; 933 sc->age_cdata.age_rx_ring_map = NULL; 934 935 /* Rx return ring. */ 936 if (sc->age_cdata.age_rr_ring_map != NULL) 937 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_rr_ring_map); 938 if (sc->age_cdata.age_rr_ring_map != NULL && 939 sc->age_rdata.age_rr_ring != NULL) 940 bus_dmamem_free(sc->sc_dmat, 941 (bus_dma_segment_t *)sc->age_rdata.age_rr_ring, 1); 942 sc->age_rdata.age_rr_ring = NULL; 943 sc->age_cdata.age_rr_ring_map = NULL; 944 945 /* CMB block */ 946 if (sc->age_cdata.age_cmb_block_map != NULL) 947 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_cmb_block_map); 948 if (sc->age_cdata.age_cmb_block_map != NULL && 949 sc->age_rdata.age_cmb_block != NULL) 950 bus_dmamem_free(sc->sc_dmat, 951 (bus_dma_segment_t *)sc->age_rdata.age_cmb_block, 1); 952 sc->age_rdata.age_cmb_block = NULL; 953 sc->age_cdata.age_cmb_block_map = NULL; 954 955 /* SMB block */ 956 if (sc->age_cdata.age_smb_block_map != NULL) 957 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_smb_block_map); 958 if (sc->age_cdata.age_smb_block_map != NULL && 959 sc->age_rdata.age_smb_block != NULL) 960 bus_dmamem_free(sc->sc_dmat, 961 (bus_dma_segment_t *)sc->age_rdata.age_smb_block, 1); 962 sc->age_rdata.age_smb_block = NULL; 963 sc->age_cdata.age_smb_block_map = NULL; 964 } 965 966 void 967 age_start(struct ifnet *ifp) 968 { 969 struct age_softc *sc = ifp->if_softc; 970 struct mbuf *m_head; 971 int enq; 972 973 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 974 return; 975 if ((sc->age_flags & AGE_FLAG_LINK) == 0) 976 return; 977 if (IFQ_IS_EMPTY(&ifp->if_snd)) 978 return; 979 980 enq = 0; 981 for (;;) { 982 IFQ_DEQUEUE(&ifp->if_snd, m_head); 983 if (m_head == NULL) 984 break; 985 986 /* 987 * Pack the data into the transmit ring. If we 988 * don't have room, set the OACTIVE flag and wait 989 * for the NIC to drain the ring. 990 */ 991 if (age_encap(sc, &m_head)) { 992 if (m_head == NULL) { 993 ifp->if_oerrors++; 994 break; 995 } 996 IF_PREPEND(&ifp->if_snd, m_head); 997 ifp->if_flags |= IFF_OACTIVE; 998 break; 999 } 1000 enq = 1; 1001 1002 #if NBPFILTER > 0 1003 /* 1004 * If there's a BPF listener, bounce a copy of this frame 1005 * to him. 1006 */ 1007 if (ifp->if_bpf != NULL) 1008 bpf_mtap_ether(ifp->if_bpf, m_head, BPF_DIRECTION_OUT); 1009 #endif 1010 } 1011 1012 if (enq) { 1013 /* Update mbox. */ 1014 AGE_COMMIT_MBOX(sc); 1015 /* Set a timeout in case the chip goes out to lunch. */ 1016 ifp->if_timer = AGE_TX_TIMEOUT; 1017 } 1018 } 1019 1020 void 1021 age_watchdog(struct ifnet *ifp) 1022 { 1023 struct age_softc *sc = ifp->if_softc; 1024 1025 if ((sc->age_flags & AGE_FLAG_LINK) == 0) { 1026 printf("%s: watchdog timeout (missed link)\n", 1027 sc->sc_dev.dv_xname); 1028 ifp->if_oerrors++; 1029 age_init(ifp); 1030 return; 1031 } 1032 1033 if (sc->age_cdata.age_tx_cnt == 0) { 1034 printf("%s: watchdog timeout (missed Tx interrupts) " 1035 "-- recovering\n", sc->sc_dev.dv_xname); 1036 age_start(ifp); 1037 return; 1038 } 1039 1040 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 1041 ifp->if_oerrors++; 1042 age_init(ifp); 1043 age_start(ifp); 1044 } 1045 1046 int 1047 age_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1048 { 1049 struct age_softc *sc = ifp->if_softc; 1050 struct mii_data *mii = &sc->sc_miibus; 1051 struct ifaddr *ifa = (struct ifaddr *)data; 1052 struct ifreq *ifr = (struct ifreq *)data; 1053 int s, error = 0; 1054 1055 s = splnet(); 1056 1057 switch (cmd) { 1058 case SIOCSIFADDR: 1059 ifp->if_flags |= IFF_UP; 1060 if (!(ifp->if_flags & IFF_RUNNING)) 1061 age_init(ifp); 1062 #ifdef INET 1063 if (ifa->ifa_addr->sa_family == AF_INET) 1064 arp_ifinit(&sc->sc_arpcom, ifa); 1065 #endif 1066 break; 1067 1068 case SIOCSIFFLAGS: 1069 if (ifp->if_flags & IFF_UP) { 1070 if (ifp->if_flags & IFF_RUNNING) 1071 error = ENETRESET; 1072 else 1073 age_init(ifp); 1074 } else { 1075 if (ifp->if_flags & IFF_RUNNING) 1076 age_stop(sc); 1077 } 1078 break; 1079 1080 case SIOCSIFMEDIA: 1081 case SIOCGIFMEDIA: 1082 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1083 break; 1084 1085 default: 1086 error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data); 1087 break; 1088 } 1089 1090 if (error == ENETRESET) { 1091 if (ifp->if_flags & IFF_RUNNING) 1092 age_iff(sc); 1093 error = 0; 1094 } 1095 1096 splx(s); 1097 return (error); 1098 } 1099 1100 void 1101 age_mac_config(struct age_softc *sc) 1102 { 1103 struct mii_data *mii = &sc->sc_miibus; 1104 uint32_t reg; 1105 1106 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1107 reg &= ~MAC_CFG_FULL_DUPLEX; 1108 reg &= ~(MAC_CFG_TX_FC | MAC_CFG_RX_FC); 1109 reg &= ~MAC_CFG_SPEED_MASK; 1110 1111 /* Reprogram MAC with resolved speed/duplex. */ 1112 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1113 case IFM_10_T: 1114 case IFM_100_TX: 1115 reg |= MAC_CFG_SPEED_10_100; 1116 break; 1117 case IFM_1000_T: 1118 reg |= MAC_CFG_SPEED_1000; 1119 break; 1120 } 1121 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1122 reg |= MAC_CFG_FULL_DUPLEX; 1123 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1124 reg |= MAC_CFG_TX_FC; 1125 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1126 reg |= MAC_CFG_RX_FC; 1127 } 1128 1129 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1130 } 1131 1132 int 1133 age_encap(struct age_softc *sc, struct mbuf **m_head) 1134 { 1135 struct age_txdesc *txd, *txd_last; 1136 struct tx_desc *desc; 1137 struct mbuf *m; 1138 bus_dmamap_t map; 1139 uint32_t cflags, poff, vtag; 1140 int error, i, prod; 1141 1142 m = *m_head; 1143 cflags = vtag = 0; 1144 poff = 0; 1145 1146 prod = sc->age_cdata.age_tx_prod; 1147 txd = &sc->age_cdata.age_txdesc[prod]; 1148 txd_last = txd; 1149 map = txd->tx_dmamap; 1150 1151 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, BUS_DMA_NOWAIT); 1152 if (error != 0 && error != EFBIG) 1153 goto drop; 1154 if (error != 0) { 1155 if (m_defrag(*m_head, M_DONTWAIT)) { 1156 error = ENOBUFS; 1157 goto drop; 1158 } 1159 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, 1160 BUS_DMA_NOWAIT); 1161 if (error != 0) 1162 goto drop; 1163 } 1164 1165 /* Check descriptor overrun. */ 1166 if (sc->age_cdata.age_tx_cnt + map->dm_nsegs >= AGE_TX_RING_CNT - 2) { 1167 bus_dmamap_unload(sc->sc_dmat, map); 1168 return (ENOBUFS); 1169 } 1170 1171 m = *m_head; 1172 /* Configure Tx IP/TCP/UDP checksum offload. */ 1173 if ((m->m_pkthdr.csum_flags & AGE_CSUM_FEATURES) != 0) { 1174 cflags |= AGE_TD_CSUM; 1175 if ((m->m_pkthdr.csum_flags & M_TCP_CSUM_OUT) != 0) 1176 cflags |= AGE_TD_TCPCSUM; 1177 if ((m->m_pkthdr.csum_flags & M_UDP_CSUM_OUT) != 0) 1178 cflags |= AGE_TD_UDPCSUM; 1179 /* Set checksum start offset. */ 1180 cflags |= (poff << AGE_TD_CSUM_PLOADOFFSET_SHIFT); 1181 } 1182 1183 #if NVLAN > 0 1184 /* Configure VLAN hardware tag insertion. */ 1185 if (m->m_flags & M_VLANTAG) { 1186 vtag = AGE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag); 1187 vtag = ((vtag << AGE_TD_VLAN_SHIFT) & AGE_TD_VLAN_MASK); 1188 cflags |= AGE_TD_INSERT_VLAN_TAG; 1189 } 1190 #endif 1191 1192 desc = NULL; 1193 for (i = 0; i < map->dm_nsegs; i++) { 1194 desc = &sc->age_rdata.age_tx_ring[prod]; 1195 desc->addr = htole64(map->dm_segs[i].ds_addr); 1196 desc->len = 1197 htole32(AGE_TX_BYTES(map->dm_segs[i].ds_len) | vtag); 1198 desc->flags = htole32(cflags); 1199 sc->age_cdata.age_tx_cnt++; 1200 AGE_DESC_INC(prod, AGE_TX_RING_CNT); 1201 } 1202 1203 /* Update producer index. */ 1204 sc->age_cdata.age_tx_prod = prod; 1205 1206 /* Set EOP on the last descriptor. */ 1207 prod = (prod + AGE_TX_RING_CNT - 1) % AGE_TX_RING_CNT; 1208 desc = &sc->age_rdata.age_tx_ring[prod]; 1209 desc->flags |= htole32(AGE_TD_EOP); 1210 1211 /* Swap dmamap of the first and the last. */ 1212 txd = &sc->age_cdata.age_txdesc[prod]; 1213 map = txd_last->tx_dmamap; 1214 txd_last->tx_dmamap = txd->tx_dmamap; 1215 txd->tx_dmamap = map; 1216 txd->tx_m = m; 1217 1218 /* Sync descriptors. */ 1219 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1220 BUS_DMASYNC_PREWRITE); 1221 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 0, 1222 sc->age_cdata.age_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1223 1224 return (0); 1225 1226 drop: 1227 m_freem(*m_head); 1228 *m_head = NULL; 1229 return (error); 1230 } 1231 1232 void 1233 age_txintr(struct age_softc *sc, int tpd_cons) 1234 { 1235 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1236 struct age_txdesc *txd; 1237 int cons, prog; 1238 1239 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 0, 1240 sc->age_cdata.age_tx_ring_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1241 1242 /* 1243 * Go through our Tx list and free mbufs for those 1244 * frames which have been transmitted. 1245 */ 1246 cons = sc->age_cdata.age_tx_cons; 1247 for (prog = 0; cons != tpd_cons; AGE_DESC_INC(cons, AGE_TX_RING_CNT)) { 1248 if (sc->age_cdata.age_tx_cnt <= 0) 1249 break; 1250 prog++; 1251 ifp->if_flags &= ~IFF_OACTIVE; 1252 sc->age_cdata.age_tx_cnt--; 1253 txd = &sc->age_cdata.age_txdesc[cons]; 1254 /* 1255 * Clear Tx descriptors, it's not required but would 1256 * help debugging in case of Tx issues. 1257 */ 1258 txd->tx_desc->addr = 0; 1259 txd->tx_desc->len = 0; 1260 txd->tx_desc->flags = 0; 1261 1262 if (txd->tx_m == NULL) 1263 continue; 1264 /* Reclaim transmitted mbufs. */ 1265 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1266 m_freem(txd->tx_m); 1267 txd->tx_m = NULL; 1268 } 1269 1270 if (prog > 0) { 1271 sc->age_cdata.age_tx_cons = cons; 1272 1273 /* 1274 * Unarm watchdog timer only when there are no pending 1275 * Tx descriptors in queue. 1276 */ 1277 if (sc->age_cdata.age_tx_cnt == 0) 1278 ifp->if_timer = 0; 1279 1280 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 0, 1281 sc->age_cdata.age_tx_ring_map->dm_mapsize, 1282 BUS_DMASYNC_PREWRITE); 1283 } 1284 } 1285 1286 /* Receive a frame. */ 1287 void 1288 age_rxeof(struct age_softc *sc, struct rx_rdesc *rxrd) 1289 { 1290 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1291 struct age_rxdesc *rxd; 1292 struct rx_desc *desc; 1293 struct mbuf *mp, *m; 1294 uint32_t status, index; 1295 int count, nsegs, pktlen; 1296 int rx_cons; 1297 1298 status = letoh32(rxrd->flags); 1299 index = letoh32(rxrd->index); 1300 rx_cons = AGE_RX_CONS(index); 1301 nsegs = AGE_RX_NSEGS(index); 1302 1303 sc->age_cdata.age_rxlen = AGE_RX_BYTES(letoh32(rxrd->len)); 1304 if ((status & AGE_RRD_ERROR) != 0 && 1305 (status & (AGE_RRD_CRC | AGE_RRD_CODE | AGE_RRD_DRIBBLE | 1306 AGE_RRD_RUNT | AGE_RRD_OFLOW | AGE_RRD_TRUNC)) != 0) { 1307 /* 1308 * We want to pass the following frames to upper 1309 * layer regardless of error status of Rx return 1310 * ring. 1311 * 1312 * o IP/TCP/UDP checksum is bad. 1313 * o frame length and protocol specific length 1314 * does not match. 1315 */ 1316 sc->age_cdata.age_rx_cons += nsegs; 1317 sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT; 1318 return; 1319 } 1320 1321 pktlen = 0; 1322 for (count = 0; count < nsegs; count++, 1323 AGE_DESC_INC(rx_cons, AGE_RX_RING_CNT)) { 1324 rxd = &sc->age_cdata.age_rxdesc[rx_cons]; 1325 mp = rxd->rx_m; 1326 desc = rxd->rx_desc; 1327 /* Add a new receive buffer to the ring. */ 1328 if (age_newbuf(sc, rxd) != 0) { 1329 ifp->if_iqdrops++; 1330 /* Reuse Rx buffers. */ 1331 if (sc->age_cdata.age_rxhead != NULL) { 1332 m_freem(sc->age_cdata.age_rxhead); 1333 AGE_RXCHAIN_RESET(sc); 1334 } 1335 break; 1336 } 1337 1338 /* The length of the first mbuf is computed last. */ 1339 if (count != 0) { 1340 mp->m_len = AGE_RX_BYTES(letoh32(desc->len)); 1341 pktlen += mp->m_len; 1342 } 1343 1344 /* Chain received mbufs. */ 1345 if (sc->age_cdata.age_rxhead == NULL) { 1346 sc->age_cdata.age_rxhead = mp; 1347 sc->age_cdata.age_rxtail = mp; 1348 } else { 1349 mp->m_flags &= ~M_PKTHDR; 1350 sc->age_cdata.age_rxprev_tail = 1351 sc->age_cdata.age_rxtail; 1352 sc->age_cdata.age_rxtail->m_next = mp; 1353 sc->age_cdata.age_rxtail = mp; 1354 } 1355 1356 if (count == nsegs - 1) { 1357 /* 1358 * It seems that L1 controller has no way 1359 * to tell hardware to strip CRC bytes. 1360 */ 1361 sc->age_cdata.age_rxlen -= ETHER_CRC_LEN; 1362 if (nsegs > 1) { 1363 /* Remove the CRC bytes in chained mbufs. */ 1364 pktlen -= ETHER_CRC_LEN; 1365 if (mp->m_len <= ETHER_CRC_LEN) { 1366 sc->age_cdata.age_rxtail = 1367 sc->age_cdata.age_rxprev_tail; 1368 sc->age_cdata.age_rxtail->m_len -= 1369 (ETHER_CRC_LEN - mp->m_len); 1370 sc->age_cdata.age_rxtail->m_next = NULL; 1371 m_freem(mp); 1372 } else { 1373 mp->m_len -= ETHER_CRC_LEN; 1374 } 1375 } 1376 1377 m = sc->age_cdata.age_rxhead; 1378 m->m_flags |= M_PKTHDR; 1379 m->m_pkthdr.rcvif = ifp; 1380 m->m_pkthdr.len = sc->age_cdata.age_rxlen; 1381 /* Set the first mbuf length. */ 1382 m->m_len = sc->age_cdata.age_rxlen - pktlen; 1383 1384 /* 1385 * Set checksum information. 1386 * It seems that L1 controller can compute partial 1387 * checksum. The partial checksum value can be used 1388 * to accelerate checksum computation for fragmented 1389 * TCP/UDP packets. Upper network stack already 1390 * takes advantage of the partial checksum value in 1391 * IP reassembly stage. But I'm not sure the 1392 * correctness of the partial hardware checksum 1393 * assistance due to lack of data sheet. If it is 1394 * proven to work on L1 I'll enable it. 1395 */ 1396 if (status & AGE_RRD_IPV4) { 1397 if ((status & AGE_RRD_IPCSUM_NOK) == 0) 1398 m->m_pkthdr.csum_flags |= 1399 M_IPV4_CSUM_IN_OK; 1400 if ((status & (AGE_RRD_TCP | AGE_RRD_UDP)) && 1401 (status & AGE_RRD_TCP_UDPCSUM_NOK) == 0) { 1402 m->m_pkthdr.csum_flags |= 1403 M_TCP_CSUM_IN_OK | M_UDP_CSUM_IN_OK; 1404 } 1405 /* 1406 * Don't mark bad checksum for TCP/UDP frames 1407 * as fragmented frames may always have set 1408 * bad checksummed bit of descriptor status. 1409 */ 1410 } 1411 #if NVLAN > 0 1412 /* Check for VLAN tagged frames. */ 1413 if (status & AGE_RRD_VLAN) { 1414 u_int32_t vtag = AGE_RX_VLAN(letoh32(rxrd->vtags)); 1415 m->m_pkthdr.ether_vtag = 1416 AGE_RX_VLAN_TAG(vtag); 1417 m->m_flags |= M_VLANTAG; 1418 } 1419 #endif 1420 1421 #if NBPFILTER > 0 1422 if (ifp->if_bpf) 1423 bpf_mtap_ether(ifp->if_bpf, m, 1424 BPF_DIRECTION_IN); 1425 #endif 1426 /* Pass it on. */ 1427 ether_input_mbuf(ifp, m); 1428 1429 /* Reset mbuf chains. */ 1430 AGE_RXCHAIN_RESET(sc); 1431 } 1432 } 1433 1434 if (count != nsegs) { 1435 sc->age_cdata.age_rx_cons += nsegs; 1436 sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT; 1437 } else 1438 sc->age_cdata.age_rx_cons = rx_cons; 1439 } 1440 1441 void 1442 age_rxintr(struct age_softc *sc, int rr_prod) 1443 { 1444 struct rx_rdesc *rxrd; 1445 int rr_cons, nsegs, pktlen, prog; 1446 1447 rr_cons = sc->age_cdata.age_rr_cons; 1448 if (rr_cons == rr_prod) 1449 return; 1450 1451 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 0, 1452 sc->age_cdata.age_rr_ring_map->dm_mapsize, 1453 BUS_DMASYNC_POSTREAD); 1454 1455 for (prog = 0; rr_cons != rr_prod; prog++) { 1456 rxrd = &sc->age_rdata.age_rr_ring[rr_cons]; 1457 nsegs = AGE_RX_NSEGS(letoh32(rxrd->index)); 1458 if (nsegs == 0) 1459 break; 1460 /* 1461 * Check number of segments against received bytes 1462 * Non-matching value would indicate that hardware 1463 * is still trying to update Rx return descriptors. 1464 * I'm not sure whether this check is really needed. 1465 */ 1466 pktlen = AGE_RX_BYTES(letoh32(rxrd->len)); 1467 if (nsegs != ((pktlen + (MCLBYTES - ETHER_ALIGN - 1)) / 1468 (MCLBYTES - ETHER_ALIGN))) 1469 break; 1470 1471 /* Received a frame. */ 1472 age_rxeof(sc, rxrd); 1473 1474 /* Clear return ring. */ 1475 rxrd->index = 0; 1476 AGE_DESC_INC(rr_cons, AGE_RR_RING_CNT); 1477 } 1478 1479 if (prog > 0) { 1480 /* Update the consumer index. */ 1481 sc->age_cdata.age_rr_cons = rr_cons; 1482 1483 /* Sync descriptors. */ 1484 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 0, 1485 sc->age_cdata.age_rr_ring_map->dm_mapsize, 1486 BUS_DMASYNC_PREWRITE); 1487 1488 /* Notify hardware availability of new Rx buffers. */ 1489 AGE_COMMIT_MBOX(sc); 1490 } 1491 } 1492 1493 void 1494 age_tick(void *xsc) 1495 { 1496 struct age_softc *sc = xsc; 1497 struct mii_data *mii = &sc->sc_miibus; 1498 int s; 1499 1500 s = splnet(); 1501 mii_tick(mii); 1502 timeout_add_sec(&sc->age_tick_ch, 1); 1503 splx(s); 1504 } 1505 1506 void 1507 age_reset(struct age_softc *sc) 1508 { 1509 uint32_t reg; 1510 int i; 1511 1512 CSR_WRITE_4(sc, AGE_MASTER_CFG, MASTER_RESET); 1513 CSR_READ_4(sc, AGE_MASTER_CFG); 1514 DELAY(1000); 1515 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 1516 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 1517 break; 1518 DELAY(10); 1519 } 1520 1521 if (i == 0) 1522 printf("%s: reset timeout(0x%08x)!\n", sc->sc_dev.dv_xname, 1523 reg); 1524 1525 /* Initialize PCIe module. From Linux. */ 1526 CSR_WRITE_4(sc, 0x12FC, 0x6500); 1527 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 1528 } 1529 1530 int 1531 age_init(struct ifnet *ifp) 1532 { 1533 struct age_softc *sc = ifp->if_softc; 1534 struct mii_data *mii = &sc->sc_miibus; 1535 uint8_t eaddr[ETHER_ADDR_LEN]; 1536 bus_addr_t paddr; 1537 uint32_t reg, fsize; 1538 uint32_t rxf_hi, rxf_lo, rrd_hi, rrd_lo; 1539 int error; 1540 1541 /* 1542 * Cancel any pending I/O. 1543 */ 1544 age_stop(sc); 1545 1546 /* 1547 * Reset the chip to a known state. 1548 */ 1549 age_reset(sc); 1550 1551 /* Initialize descriptors. */ 1552 error = age_init_rx_ring(sc); 1553 if (error != 0) { 1554 printf("%s: no memory for Rx buffers.\n", sc->sc_dev.dv_xname); 1555 age_stop(sc); 1556 return (error); 1557 } 1558 age_init_rr_ring(sc); 1559 age_init_tx_ring(sc); 1560 age_init_cmb_block(sc); 1561 age_init_smb_block(sc); 1562 1563 /* Reprogram the station address. */ 1564 bcopy(LLADDR(ifp->if_sadl), eaddr, ETHER_ADDR_LEN); 1565 CSR_WRITE_4(sc, AGE_PAR0, 1566 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 1567 CSR_WRITE_4(sc, AGE_PAR1, eaddr[0] << 8 | eaddr[1]); 1568 1569 /* Set descriptor base addresses. */ 1570 paddr = sc->age_rdata.age_tx_ring_paddr; 1571 CSR_WRITE_4(sc, AGE_DESC_ADDR_HI, AGE_ADDR_HI(paddr)); 1572 paddr = sc->age_rdata.age_rx_ring_paddr; 1573 CSR_WRITE_4(sc, AGE_DESC_RD_ADDR_LO, AGE_ADDR_LO(paddr)); 1574 paddr = sc->age_rdata.age_rr_ring_paddr; 1575 CSR_WRITE_4(sc, AGE_DESC_RRD_ADDR_LO, AGE_ADDR_LO(paddr)); 1576 paddr = sc->age_rdata.age_tx_ring_paddr; 1577 CSR_WRITE_4(sc, AGE_DESC_TPD_ADDR_LO, AGE_ADDR_LO(paddr)); 1578 paddr = sc->age_rdata.age_cmb_block_paddr; 1579 CSR_WRITE_4(sc, AGE_DESC_CMB_ADDR_LO, AGE_ADDR_LO(paddr)); 1580 paddr = sc->age_rdata.age_smb_block_paddr; 1581 CSR_WRITE_4(sc, AGE_DESC_SMB_ADDR_LO, AGE_ADDR_LO(paddr)); 1582 1583 /* Set Rx/Rx return descriptor counter. */ 1584 CSR_WRITE_4(sc, AGE_DESC_RRD_RD_CNT, 1585 ((AGE_RR_RING_CNT << DESC_RRD_CNT_SHIFT) & 1586 DESC_RRD_CNT_MASK) | 1587 ((AGE_RX_RING_CNT << DESC_RD_CNT_SHIFT) & DESC_RD_CNT_MASK)); 1588 1589 /* Set Tx descriptor counter. */ 1590 CSR_WRITE_4(sc, AGE_DESC_TPD_CNT, 1591 (AGE_TX_RING_CNT << DESC_TPD_CNT_SHIFT) & DESC_TPD_CNT_MASK); 1592 1593 /* Tell hardware that we're ready to load descriptors. */ 1594 CSR_WRITE_4(sc, AGE_DMA_BLOCK, DMA_BLOCK_LOAD); 1595 1596 /* 1597 * Initialize mailbox register. 1598 * Updated producer/consumer index information is exchanged 1599 * through this mailbox register. However Tx producer and 1600 * Rx return consumer/Rx producer are all shared such that 1601 * it's hard to separate code path between Tx and Rx without 1602 * locking. If L1 hardware have a separate mail box register 1603 * for Tx and Rx consumer/producer management we could have 1604 * indepent Tx/Rx handler which in turn Rx handler could have 1605 * been run without any locking. 1606 */ 1607 AGE_COMMIT_MBOX(sc); 1608 1609 /* Configure IPG/IFG parameters. */ 1610 CSR_WRITE_4(sc, AGE_IPG_IFG_CFG, 1611 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK) | 1612 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 1613 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 1614 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK)); 1615 1616 /* Set parameters for half-duplex media. */ 1617 CSR_WRITE_4(sc, AGE_HDPX_CFG, 1618 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 1619 HDPX_CFG_LCOL_MASK) | 1620 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 1621 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 1622 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 1623 HDPX_CFG_ABEBT_MASK) | 1624 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 1625 HDPX_CFG_JAMIPG_MASK)); 1626 1627 /* Configure interrupt moderation timer. */ 1628 sc->age_int_mod = AGE_IM_TIMER_DEFAULT; 1629 CSR_WRITE_2(sc, AGE_IM_TIMER, AGE_USECS(sc->age_int_mod)); 1630 reg = CSR_READ_4(sc, AGE_MASTER_CFG); 1631 reg &= ~MASTER_MTIMER_ENB; 1632 if (AGE_USECS(sc->age_int_mod) == 0) 1633 reg &= ~MASTER_ITIMER_ENB; 1634 else 1635 reg |= MASTER_ITIMER_ENB; 1636 CSR_WRITE_4(sc, AGE_MASTER_CFG, reg); 1637 if (agedebug) 1638 printf("%s: interrupt moderation is %d us.\n", 1639 sc->sc_dev.dv_xname, sc->age_int_mod); 1640 CSR_WRITE_2(sc, AGE_INTR_CLR_TIMER, AGE_USECS(1000)); 1641 1642 /* Set Maximum frame size but don't let MTU be lass than ETHER_MTU. */ 1643 if (ifp->if_mtu < ETHERMTU) 1644 sc->age_max_frame_size = ETHERMTU; 1645 else 1646 sc->age_max_frame_size = ifp->if_mtu; 1647 sc->age_max_frame_size += ETHER_HDR_LEN + 1648 sizeof(struct ether_vlan_header) + ETHER_CRC_LEN; 1649 CSR_WRITE_4(sc, AGE_FRAME_SIZE, sc->age_max_frame_size); 1650 1651 /* Configure jumbo frame. */ 1652 fsize = roundup(sc->age_max_frame_size, sizeof(uint64_t)); 1653 CSR_WRITE_4(sc, AGE_RXQ_JUMBO_CFG, 1654 (((fsize / sizeof(uint64_t)) << 1655 RXQ_JUMBO_CFG_SZ_THRESH_SHIFT) & RXQ_JUMBO_CFG_SZ_THRESH_MASK) | 1656 ((RXQ_JUMBO_CFG_LKAH_DEFAULT << 1657 RXQ_JUMBO_CFG_LKAH_SHIFT) & RXQ_JUMBO_CFG_LKAH_MASK) | 1658 ((AGE_USECS(8) << RXQ_JUMBO_CFG_RRD_TIMER_SHIFT) & 1659 RXQ_JUMBO_CFG_RRD_TIMER_MASK)); 1660 1661 /* Configure flow-control parameters. From Linux. */ 1662 if ((sc->age_flags & AGE_FLAG_PCIE) != 0) { 1663 /* 1664 * Magic workaround for old-L1. 1665 * Don't know which hw revision requires this magic. 1666 */ 1667 CSR_WRITE_4(sc, 0x12FC, 0x6500); 1668 /* 1669 * Another magic workaround for flow-control mode 1670 * change. From Linux. 1671 */ 1672 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 1673 } 1674 /* 1675 * TODO 1676 * Should understand pause parameter relationships between FIFO 1677 * size and number of Rx descriptors and Rx return descriptors. 1678 * 1679 * Magic parameters came from Linux. 1680 */ 1681 switch (sc->age_chip_rev) { 1682 case 0x8001: 1683 case 0x9001: 1684 case 0x9002: 1685 case 0x9003: 1686 rxf_hi = AGE_RX_RING_CNT / 16; 1687 rxf_lo = (AGE_RX_RING_CNT * 7) / 8; 1688 rrd_hi = (AGE_RR_RING_CNT * 7) / 8; 1689 rrd_lo = AGE_RR_RING_CNT / 16; 1690 break; 1691 default: 1692 reg = CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN); 1693 rxf_lo = reg / 16; 1694 if (rxf_lo < 192) 1695 rxf_lo = 192; 1696 rxf_hi = (reg * 7) / 8; 1697 if (rxf_hi < rxf_lo) 1698 rxf_hi = rxf_lo + 16; 1699 reg = CSR_READ_4(sc, AGE_SRAM_RRD_LEN); 1700 rrd_lo = reg / 8; 1701 rrd_hi = (reg * 7) / 8; 1702 if (rrd_lo < 2) 1703 rrd_lo = 2; 1704 if (rrd_hi < rrd_lo) 1705 rrd_hi = rrd_lo + 3; 1706 break; 1707 } 1708 CSR_WRITE_4(sc, AGE_RXQ_FIFO_PAUSE_THRESH, 1709 ((rxf_lo << RXQ_FIFO_PAUSE_THRESH_LO_SHIFT) & 1710 RXQ_FIFO_PAUSE_THRESH_LO_MASK) | 1711 ((rxf_hi << RXQ_FIFO_PAUSE_THRESH_HI_SHIFT) & 1712 RXQ_FIFO_PAUSE_THRESH_HI_MASK)); 1713 CSR_WRITE_4(sc, AGE_RXQ_RRD_PAUSE_THRESH, 1714 ((rrd_lo << RXQ_RRD_PAUSE_THRESH_LO_SHIFT) & 1715 RXQ_RRD_PAUSE_THRESH_LO_MASK) | 1716 ((rrd_hi << RXQ_RRD_PAUSE_THRESH_HI_SHIFT) & 1717 RXQ_RRD_PAUSE_THRESH_HI_MASK)); 1718 1719 /* Configure RxQ. */ 1720 CSR_WRITE_4(sc, AGE_RXQ_CFG, 1721 ((RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 1722 RXQ_CFG_RD_BURST_MASK) | 1723 ((RXQ_CFG_RRD_BURST_THRESH_DEFAULT << 1724 RXQ_CFG_RRD_BURST_THRESH_SHIFT) & RXQ_CFG_RRD_BURST_THRESH_MASK) | 1725 ((RXQ_CFG_RD_PREF_MIN_IPG_DEFAULT << 1726 RXQ_CFG_RD_PREF_MIN_IPG_SHIFT) & RXQ_CFG_RD_PREF_MIN_IPG_MASK) | 1727 RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 1728 1729 /* Configure TxQ. */ 1730 CSR_WRITE_4(sc, AGE_TXQ_CFG, 1731 ((TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 1732 TXQ_CFG_TPD_BURST_MASK) | 1733 ((TXQ_CFG_TX_FIFO_BURST_DEFAULT << TXQ_CFG_TX_FIFO_BURST_SHIFT) & 1734 TXQ_CFG_TX_FIFO_BURST_MASK) | 1735 ((TXQ_CFG_TPD_FETCH_DEFAULT << 1736 TXQ_CFG_TPD_FETCH_THRESH_SHIFT) & TXQ_CFG_TPD_FETCH_THRESH_MASK) | 1737 TXQ_CFG_ENB); 1738 1739 /* Configure DMA parameters. */ 1740 CSR_WRITE_4(sc, AGE_DMA_CFG, 1741 DMA_CFG_ENH_ORDER | DMA_CFG_RCB_64 | 1742 sc->age_dma_rd_burst | DMA_CFG_RD_ENB | 1743 sc->age_dma_wr_burst | DMA_CFG_WR_ENB); 1744 1745 /* Configure CMB DMA write threshold. */ 1746 CSR_WRITE_4(sc, AGE_CMB_WR_THRESH, 1747 ((CMB_WR_THRESH_RRD_DEFAULT << CMB_WR_THRESH_RRD_SHIFT) & 1748 CMB_WR_THRESH_RRD_MASK) | 1749 ((CMB_WR_THRESH_TPD_DEFAULT << CMB_WR_THRESH_TPD_SHIFT) & 1750 CMB_WR_THRESH_TPD_MASK)); 1751 1752 /* Set CMB/SMB timer and enable them. */ 1753 CSR_WRITE_4(sc, AGE_CMB_WR_TIMER, 1754 ((AGE_USECS(2) << CMB_WR_TIMER_TX_SHIFT) & CMB_WR_TIMER_TX_MASK) | 1755 ((AGE_USECS(2) << CMB_WR_TIMER_RX_SHIFT) & CMB_WR_TIMER_RX_MASK)); 1756 1757 /* Request SMB updates for every seconds. */ 1758 CSR_WRITE_4(sc, AGE_SMB_TIMER, AGE_USECS(1000 * 1000)); 1759 CSR_WRITE_4(sc, AGE_CSMB_CTRL, CSMB_CTRL_SMB_ENB | CSMB_CTRL_CMB_ENB); 1760 1761 /* 1762 * Disable all WOL bits as WOL can interfere normal Rx 1763 * operation. 1764 */ 1765 CSR_WRITE_4(sc, AGE_WOL_CFG, 0); 1766 1767 /* 1768 * Configure Tx/Rx MACs. 1769 * - Auto-padding for short frames. 1770 * - Enable CRC generation. 1771 * Start with full-duplex/1000Mbps media. Actual reconfiguration 1772 * of MAC is followed after link establishment. 1773 */ 1774 CSR_WRITE_4(sc, AGE_MAC_CFG, 1775 MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | 1776 MAC_CFG_FULL_DUPLEX | MAC_CFG_SPEED_1000 | 1777 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 1778 MAC_CFG_PREAMBLE_MASK)); 1779 1780 /* Set up the receive filter. */ 1781 age_iff(sc); 1782 1783 age_rxvlan(sc); 1784 1785 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1786 reg |= MAC_CFG_RXCSUM_ENB; 1787 1788 /* Ack all pending interrupts and clear it. */ 1789 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); 1790 CSR_WRITE_4(sc, AGE_INTR_MASK, AGE_INTRS); 1791 1792 /* Finally enable Tx/Rx MAC. */ 1793 CSR_WRITE_4(sc, AGE_MAC_CFG, reg | MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 1794 1795 sc->age_flags &= ~AGE_FLAG_LINK; 1796 1797 /* Switch to the current media. */ 1798 mii_mediachg(mii); 1799 1800 timeout_add_sec(&sc->age_tick_ch, 1); 1801 1802 ifp->if_flags |= IFF_RUNNING; 1803 ifp->if_flags &= ~IFF_OACTIVE; 1804 1805 return (0); 1806 } 1807 1808 void 1809 age_stop(struct age_softc *sc) 1810 { 1811 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1812 struct age_txdesc *txd; 1813 struct age_rxdesc *rxd; 1814 uint32_t reg; 1815 int i; 1816 1817 /* 1818 * Mark the interface down and cancel the watchdog timer. 1819 */ 1820 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1821 ifp->if_timer = 0; 1822 1823 sc->age_flags &= ~AGE_FLAG_LINK; 1824 timeout_del(&sc->age_tick_ch); 1825 1826 /* 1827 * Disable interrupts. 1828 */ 1829 CSR_WRITE_4(sc, AGE_INTR_MASK, 0); 1830 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0xFFFFFFFF); 1831 1832 /* Stop CMB/SMB updates. */ 1833 CSR_WRITE_4(sc, AGE_CSMB_CTRL, 0); 1834 1835 /* Stop Rx/Tx MAC. */ 1836 age_stop_rxmac(sc); 1837 age_stop_txmac(sc); 1838 1839 /* Stop DMA. */ 1840 CSR_WRITE_4(sc, AGE_DMA_CFG, 1841 CSR_READ_4(sc, AGE_DMA_CFG) & ~(DMA_CFG_RD_ENB | DMA_CFG_WR_ENB)); 1842 1843 /* Stop TxQ/RxQ. */ 1844 CSR_WRITE_4(sc, AGE_TXQ_CFG, 1845 CSR_READ_4(sc, AGE_TXQ_CFG) & ~TXQ_CFG_ENB); 1846 CSR_WRITE_4(sc, AGE_RXQ_CFG, 1847 CSR_READ_4(sc, AGE_RXQ_CFG) & ~RXQ_CFG_ENB); 1848 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 1849 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 1850 break; 1851 DELAY(10); 1852 } 1853 if (i == 0) 1854 printf("%s: stopping Rx/Tx MACs timed out(0x%08x)!\n", 1855 sc->sc_dev.dv_xname, reg); 1856 1857 /* Reclaim Rx buffers that have been processed. */ 1858 if (sc->age_cdata.age_rxhead != NULL) 1859 m_freem(sc->age_cdata.age_rxhead); 1860 AGE_RXCHAIN_RESET(sc); 1861 1862 /* 1863 * Free RX and TX mbufs still in the queues. 1864 */ 1865 for (i = 0; i < AGE_RX_RING_CNT; i++) { 1866 rxd = &sc->age_cdata.age_rxdesc[i]; 1867 if (rxd->rx_m != NULL) { 1868 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 1869 m_freem(rxd->rx_m); 1870 rxd->rx_m = NULL; 1871 } 1872 } 1873 for (i = 0; i < AGE_TX_RING_CNT; i++) { 1874 txd = &sc->age_cdata.age_txdesc[i]; 1875 if (txd->tx_m != NULL) { 1876 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1877 m_freem(txd->tx_m); 1878 txd->tx_m = NULL; 1879 } 1880 } 1881 } 1882 1883 void 1884 age_stats_update(struct age_softc *sc) 1885 { 1886 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1887 struct age_stats *stat; 1888 struct smb *smb; 1889 1890 stat = &sc->age_stat; 1891 1892 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 0, 1893 sc->age_cdata.age_smb_block_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1894 1895 smb = sc->age_rdata.age_smb_block; 1896 if (smb->updated == 0) 1897 return; 1898 1899 /* Rx stats. */ 1900 stat->rx_frames += smb->rx_frames; 1901 stat->rx_bcast_frames += smb->rx_bcast_frames; 1902 stat->rx_mcast_frames += smb->rx_mcast_frames; 1903 stat->rx_pause_frames += smb->rx_pause_frames; 1904 stat->rx_control_frames += smb->rx_control_frames; 1905 stat->rx_crcerrs += smb->rx_crcerrs; 1906 stat->rx_lenerrs += smb->rx_lenerrs; 1907 stat->rx_bytes += smb->rx_bytes; 1908 stat->rx_runts += smb->rx_runts; 1909 stat->rx_fragments += smb->rx_fragments; 1910 stat->rx_pkts_64 += smb->rx_pkts_64; 1911 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 1912 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 1913 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 1914 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 1915 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 1916 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 1917 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 1918 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 1919 stat->rx_desc_oflows += smb->rx_desc_oflows; 1920 stat->rx_alignerrs += smb->rx_alignerrs; 1921 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 1922 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 1923 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 1924 1925 /* Tx stats. */ 1926 stat->tx_frames += smb->tx_frames; 1927 stat->tx_bcast_frames += smb->tx_bcast_frames; 1928 stat->tx_mcast_frames += smb->tx_mcast_frames; 1929 stat->tx_pause_frames += smb->tx_pause_frames; 1930 stat->tx_excess_defer += smb->tx_excess_defer; 1931 stat->tx_control_frames += smb->tx_control_frames; 1932 stat->tx_deferred += smb->tx_deferred; 1933 stat->tx_bytes += smb->tx_bytes; 1934 stat->tx_pkts_64 += smb->tx_pkts_64; 1935 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 1936 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 1937 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 1938 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 1939 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 1940 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 1941 stat->tx_single_colls += smb->tx_single_colls; 1942 stat->tx_multi_colls += smb->tx_multi_colls; 1943 stat->tx_late_colls += smb->tx_late_colls; 1944 stat->tx_excess_colls += smb->tx_excess_colls; 1945 stat->tx_underrun += smb->tx_underrun; 1946 stat->tx_desc_underrun += smb->tx_desc_underrun; 1947 stat->tx_lenerrs += smb->tx_lenerrs; 1948 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 1949 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 1950 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 1951 1952 /* Update counters in ifnet. */ 1953 ifp->if_opackets += smb->tx_frames; 1954 1955 ifp->if_collisions += smb->tx_single_colls + 1956 smb->tx_multi_colls + smb->tx_late_colls + 1957 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT; 1958 1959 ifp->if_oerrors += smb->tx_excess_colls + 1960 smb->tx_late_colls + smb->tx_underrun + 1961 smb->tx_pkts_truncated; 1962 1963 ifp->if_ipackets += smb->rx_frames; 1964 1965 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 1966 smb->rx_runts + smb->rx_pkts_truncated + 1967 smb->rx_fifo_oflows + smb->rx_desc_oflows + 1968 smb->rx_alignerrs; 1969 1970 /* Update done, clear. */ 1971 smb->updated = 0; 1972 1973 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 0, 1974 sc->age_cdata.age_smb_block_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1975 } 1976 1977 void 1978 age_stop_txmac(struct age_softc *sc) 1979 { 1980 uint32_t reg; 1981 int i; 1982 1983 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1984 if ((reg & MAC_CFG_TX_ENB) != 0) { 1985 reg &= ~MAC_CFG_TX_ENB; 1986 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1987 } 1988 /* Stop Tx DMA engine. */ 1989 reg = CSR_READ_4(sc, AGE_DMA_CFG); 1990 if ((reg & DMA_CFG_RD_ENB) != 0) { 1991 reg &= ~DMA_CFG_RD_ENB; 1992 CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 1993 } 1994 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 1995 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 1996 (IDLE_STATUS_TXMAC | IDLE_STATUS_DMARD)) == 0) 1997 break; 1998 DELAY(10); 1999 } 2000 if (i == 0) 2001 printf("%s: stopping TxMAC timeout!\n", sc->sc_dev.dv_xname); 2002 } 2003 2004 void 2005 age_stop_rxmac(struct age_softc *sc) 2006 { 2007 uint32_t reg; 2008 int i; 2009 2010 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2011 if ((reg & MAC_CFG_RX_ENB) != 0) { 2012 reg &= ~MAC_CFG_RX_ENB; 2013 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2014 } 2015 /* Stop Rx DMA engine. */ 2016 reg = CSR_READ_4(sc, AGE_DMA_CFG); 2017 if ((reg & DMA_CFG_WR_ENB) != 0) { 2018 reg &= ~DMA_CFG_WR_ENB; 2019 CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 2020 } 2021 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2022 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 2023 (IDLE_STATUS_RXMAC | IDLE_STATUS_DMAWR)) == 0) 2024 break; 2025 DELAY(10); 2026 } 2027 if (i == 0) 2028 printf("%s: stopping RxMAC timeout!\n", sc->sc_dev.dv_xname); 2029 } 2030 2031 void 2032 age_init_tx_ring(struct age_softc *sc) 2033 { 2034 struct age_ring_data *rd; 2035 struct age_txdesc *txd; 2036 int i; 2037 2038 sc->age_cdata.age_tx_prod = 0; 2039 sc->age_cdata.age_tx_cons = 0; 2040 sc->age_cdata.age_tx_cnt = 0; 2041 2042 rd = &sc->age_rdata; 2043 bzero(rd->age_tx_ring, AGE_TX_RING_SZ); 2044 for (i = 0; i < AGE_TX_RING_CNT; i++) { 2045 txd = &sc->age_cdata.age_txdesc[i]; 2046 txd->tx_desc = &rd->age_tx_ring[i]; 2047 txd->tx_m = NULL; 2048 } 2049 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 0, 2050 sc->age_cdata.age_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2051 } 2052 2053 int 2054 age_init_rx_ring(struct age_softc *sc) 2055 { 2056 struct age_ring_data *rd; 2057 struct age_rxdesc *rxd; 2058 int i; 2059 2060 sc->age_cdata.age_rx_cons = AGE_RX_RING_CNT - 1; 2061 rd = &sc->age_rdata; 2062 bzero(rd->age_rx_ring, AGE_RX_RING_SZ); 2063 for (i = 0; i < AGE_RX_RING_CNT; i++) { 2064 rxd = &sc->age_cdata.age_rxdesc[i]; 2065 rxd->rx_m = NULL; 2066 rxd->rx_desc = &rd->age_rx_ring[i]; 2067 if (age_newbuf(sc, rxd) != 0) 2068 return (ENOBUFS); 2069 } 2070 2071 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rx_ring_map, 0, 2072 sc->age_cdata.age_rx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2073 2074 return (0); 2075 } 2076 2077 void 2078 age_init_rr_ring(struct age_softc *sc) 2079 { 2080 struct age_ring_data *rd; 2081 2082 sc->age_cdata.age_rr_cons = 0; 2083 AGE_RXCHAIN_RESET(sc); 2084 2085 rd = &sc->age_rdata; 2086 bzero(rd->age_rr_ring, AGE_RR_RING_SZ); 2087 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 0, 2088 sc->age_cdata.age_rr_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2089 } 2090 2091 void 2092 age_init_cmb_block(struct age_softc *sc) 2093 { 2094 struct age_ring_data *rd; 2095 2096 rd = &sc->age_rdata; 2097 bzero(rd->age_cmb_block, AGE_CMB_BLOCK_SZ); 2098 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 2099 sc->age_cdata.age_cmb_block_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2100 } 2101 2102 void 2103 age_init_smb_block(struct age_softc *sc) 2104 { 2105 struct age_ring_data *rd; 2106 2107 rd = &sc->age_rdata; 2108 bzero(rd->age_smb_block, AGE_SMB_BLOCK_SZ); 2109 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 0, 2110 sc->age_cdata.age_smb_block_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2111 } 2112 2113 int 2114 age_newbuf(struct age_softc *sc, struct age_rxdesc *rxd) 2115 { 2116 struct rx_desc *desc; 2117 struct mbuf *m; 2118 bus_dmamap_t map; 2119 int error; 2120 2121 MGETHDR(m, M_DONTWAIT, MT_DATA); 2122 if (m == NULL) 2123 return (ENOBUFS); 2124 MCLGET(m, M_DONTWAIT); 2125 if (!(m->m_flags & M_EXT)) { 2126 m_freem(m); 2127 return (ENOBUFS); 2128 } 2129 2130 m->m_len = m->m_pkthdr.len = MCLBYTES; 2131 m_adj(m, ETHER_ALIGN); 2132 2133 error = bus_dmamap_load_mbuf(sc->sc_dmat, 2134 sc->age_cdata.age_rx_sparemap, m, BUS_DMA_NOWAIT); 2135 2136 if (error != 0) { 2137 m_freem(m); 2138 printf("%s: can't load RX mbuf\n", sc->sc_dev.dv_xname); 2139 return (error); 2140 } 2141 2142 if (rxd->rx_m != NULL) { 2143 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0, 2144 rxd->rx_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2145 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 2146 } 2147 map = rxd->rx_dmamap; 2148 rxd->rx_dmamap = sc->age_cdata.age_rx_sparemap; 2149 sc->age_cdata.age_rx_sparemap = map; 2150 rxd->rx_m = m; 2151 2152 desc = rxd->rx_desc; 2153 desc->addr = htole64(rxd->rx_dmamap->dm_segs[0].ds_addr); 2154 desc->len = 2155 htole32((rxd->rx_dmamap->dm_segs[0].ds_len & AGE_RD_LEN_MASK) << 2156 AGE_RD_LEN_SHIFT); 2157 2158 return (0); 2159 } 2160 2161 void 2162 age_rxvlan(struct age_softc *sc) 2163 { 2164 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 2165 uint32_t reg; 2166 2167 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2168 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 2169 if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) 2170 reg |= MAC_CFG_VLAN_TAG_STRIP; 2171 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2172 } 2173 2174 void 2175 age_iff(struct age_softc *sc) 2176 { 2177 struct arpcom *ac = &sc->sc_arpcom; 2178 struct ifnet *ifp = &ac->ac_if; 2179 struct ether_multi *enm; 2180 struct ether_multistep step; 2181 uint32_t crc; 2182 uint32_t mchash[2]; 2183 uint32_t rxcfg; 2184 2185 rxcfg = CSR_READ_4(sc, AGE_MAC_CFG); 2186 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 2187 ifp->if_flags &= ~IFF_ALLMULTI; 2188 2189 /* 2190 * Always accept broadcast frames. 2191 */ 2192 rxcfg |= MAC_CFG_BCAST; 2193 2194 if (ifp->if_flags & IFF_PROMISC || ac->ac_multirangecnt > 0) { 2195 ifp->if_flags |= IFF_ALLMULTI; 2196 if (ifp->if_flags & IFF_PROMISC) 2197 rxcfg |= MAC_CFG_PROMISC; 2198 else 2199 rxcfg |= MAC_CFG_ALLMULTI; 2200 mchash[0] = mchash[1] = 0xFFFFFFFF; 2201 } else { 2202 /* Program new filter. */ 2203 bzero(mchash, sizeof(mchash)); 2204 2205 ETHER_FIRST_MULTI(step, ac, enm); 2206 while (enm != NULL) { 2207 crc = ether_crc32_be(enm->enm_addrlo, 2208 ETHER_ADDR_LEN); 2209 2210 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 2211 2212 ETHER_NEXT_MULTI(step, enm); 2213 } 2214 } 2215 2216 CSR_WRITE_4(sc, AGE_MAR0, mchash[0]); 2217 CSR_WRITE_4(sc, AGE_MAR1, mchash[1]); 2218 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg); 2219 } 2220