1 /* $OpenBSD: if_age.c,v 1.19 2011/10/19 05:23:44 kevlo Exp $ */ 2 3 /*- 4 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* Driver for Attansic Technology Corp. L1 Gigabit Ethernet. */ 31 32 #include "bpfilter.h" 33 #include "vlan.h" 34 35 #include <sys/param.h> 36 #include <sys/endian.h> 37 #include <sys/systm.h> 38 #include <sys/types.h> 39 #include <sys/sockio.h> 40 #include <sys/mbuf.h> 41 #include <sys/queue.h> 42 #include <sys/kernel.h> 43 #include <sys/device.h> 44 #include <sys/timeout.h> 45 #include <sys/socket.h> 46 47 #include <machine/bus.h> 48 49 #include <net/if.h> 50 #include <net/if_dl.h> 51 #include <net/if_media.h> 52 53 #ifdef INET 54 #include <netinet/in.h> 55 #include <netinet/in_systm.h> 56 #include <netinet/in_var.h> 57 #include <netinet/ip.h> 58 #include <netinet/if_ether.h> 59 #endif 60 61 #include <net/if_types.h> 62 #include <net/if_vlan_var.h> 63 64 #if NBPFILTER > 0 65 #include <net/bpf.h> 66 #endif 67 68 #include <dev/rndvar.h> 69 70 #include <dev/mii/mii.h> 71 #include <dev/mii/miivar.h> 72 73 #include <dev/pci/pcireg.h> 74 #include <dev/pci/pcivar.h> 75 #include <dev/pci/pcidevs.h> 76 77 #include <dev/pci/if_agereg.h> 78 79 int age_match(struct device *, void *, void *); 80 void age_attach(struct device *, struct device *, void *); 81 int age_detach(struct device *, int); 82 83 int age_miibus_readreg(struct device *, int, int); 84 void age_miibus_writereg(struct device *, int, int, int); 85 void age_miibus_statchg(struct device *); 86 87 int age_init(struct ifnet *); 88 int age_ioctl(struct ifnet *, u_long, caddr_t); 89 void age_start(struct ifnet *); 90 void age_watchdog(struct ifnet *); 91 void age_mediastatus(struct ifnet *, struct ifmediareq *); 92 int age_mediachange(struct ifnet *); 93 94 int age_intr(void *); 95 int age_dma_alloc(struct age_softc *); 96 void age_dma_free(struct age_softc *); 97 void age_get_macaddr(struct age_softc *); 98 void age_phy_reset(struct age_softc *); 99 100 int age_encap(struct age_softc *, struct mbuf **); 101 void age_init_tx_ring(struct age_softc *); 102 int age_init_rx_ring(struct age_softc *); 103 void age_init_rr_ring(struct age_softc *); 104 void age_init_cmb_block(struct age_softc *); 105 void age_init_smb_block(struct age_softc *); 106 int age_newbuf(struct age_softc *, struct age_rxdesc *); 107 void age_mac_config(struct age_softc *); 108 void age_txintr(struct age_softc *, int); 109 void age_rxeof(struct age_softc *sc, struct rx_rdesc *); 110 void age_rxintr(struct age_softc *, int); 111 void age_tick(void *); 112 void age_reset(struct age_softc *); 113 void age_stop(struct age_softc *); 114 void age_stats_update(struct age_softc *); 115 void age_stop_txmac(struct age_softc *); 116 void age_stop_rxmac(struct age_softc *); 117 void age_rxvlan(struct age_softc *sc); 118 void age_iff(struct age_softc *); 119 120 const struct pci_matchid age_devices[] = { 121 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L1 } 122 }; 123 124 struct cfattach age_ca = { 125 sizeof (struct age_softc), age_match, age_attach 126 }; 127 128 struct cfdriver age_cd = { 129 NULL, "age", DV_IFNET 130 }; 131 132 int agedebug = 0; 133 #define DPRINTF(x) do { if (agedebug) printf x; } while (0) 134 135 #define AGE_CSUM_FEATURES (M_TCP_CSUM_OUT | M_UDP_CSUM_OUT) 136 137 int 138 age_match(struct device *dev, void *match, void *aux) 139 { 140 return pci_matchbyid((struct pci_attach_args *)aux, age_devices, 141 sizeof (age_devices) / sizeof (age_devices[0])); 142 } 143 144 void 145 age_attach(struct device *parent, struct device *self, void *aux) 146 { 147 struct age_softc *sc = (struct age_softc *)self; 148 struct pci_attach_args *pa = aux; 149 pci_chipset_tag_t pc = pa->pa_pc; 150 pci_intr_handle_t ih; 151 const char *intrstr; 152 struct ifnet *ifp; 153 pcireg_t memtype; 154 int error = 0; 155 156 /* 157 * Allocate IO memory 158 */ 159 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, AGE_PCIR_BAR); 160 if (pci_mapreg_map(pa, AGE_PCIR_BAR, memtype, 0, &sc->sc_mem_bt, 161 &sc->sc_mem_bh, NULL, &sc->sc_mem_size, 0)) { 162 printf(": can't map mem space\n"); 163 return; 164 } 165 166 if (pci_intr_map_msi(pa, &ih) != 0 && pci_intr_map(pa, &ih) != 0) { 167 printf(": can't map interrupt\n"); 168 goto fail; 169 } 170 171 /* 172 * Allocate IRQ 173 */ 174 intrstr = pci_intr_string(pc, ih); 175 sc->sc_irq_handle = pci_intr_establish(pc, ih, IPL_NET, age_intr, sc, 176 sc->sc_dev.dv_xname); 177 if (sc->sc_irq_handle == NULL) { 178 printf(": could not establish interrupt"); 179 if (intrstr != NULL) 180 printf(" at %s", intrstr); 181 printf("\n"); 182 goto fail; 183 } 184 printf(": %s", intrstr); 185 186 sc->sc_dmat = pa->pa_dmat; 187 sc->sc_pct = pa->pa_pc; 188 sc->sc_pcitag = pa->pa_tag; 189 190 /* Set PHY address. */ 191 sc->age_phyaddr = AGE_PHY_ADDR; 192 193 /* Reset PHY. */ 194 age_phy_reset(sc); 195 196 /* Reset the ethernet controller. */ 197 age_reset(sc); 198 199 /* Get PCI and chip id/revision. */ 200 sc->age_rev = PCI_REVISION(pa->pa_class); 201 sc->age_chip_rev = CSR_READ_4(sc, AGE_MASTER_CFG) >> 202 MASTER_CHIP_REV_SHIFT; 203 if (agedebug) { 204 printf("%s: PCI device revision : 0x%04x\n", 205 sc->sc_dev.dv_xname, sc->age_rev); 206 printf("%s: Chip id/revision : 0x%04x\n", 207 sc->sc_dev.dv_xname, sc->age_chip_rev); 208 } 209 210 if (agedebug) { 211 printf("%s: %d Tx FIFO, %d Rx FIFO\n", sc->sc_dev.dv_xname, 212 CSR_READ_4(sc, AGE_SRAM_TX_FIFO_LEN), 213 CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN)); 214 } 215 216 /* Set max allowable DMA size. */ 217 sc->age_dma_rd_burst = DMA_CFG_RD_BURST_128; 218 sc->age_dma_wr_burst = DMA_CFG_WR_BURST_128; 219 220 /* Allocate DMA stuffs */ 221 error = age_dma_alloc(sc); 222 if (error) 223 goto fail; 224 225 /* Load station address. */ 226 age_get_macaddr(sc); 227 228 ifp = &sc->sc_arpcom.ac_if; 229 ifp->if_softc = sc; 230 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 231 ifp->if_ioctl = age_ioctl; 232 ifp->if_start = age_start; 233 ifp->if_watchdog = age_watchdog; 234 ifp->if_baudrate = IF_Gbps(1); 235 IFQ_SET_MAXLEN(&ifp->if_snd, AGE_TX_RING_CNT - 1); 236 IFQ_SET_READY(&ifp->if_snd); 237 bcopy(sc->age_eaddr, sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN); 238 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 239 240 ifp->if_capabilities = IFCAP_VLAN_MTU; 241 242 #ifdef AGE_CHECKSUM 243 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 244 IFCAP_CSUM_UDPv4; 245 #endif 246 247 #if NVLAN > 0 248 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 249 #endif 250 251 printf(", address %s\n", ether_sprintf(sc->sc_arpcom.ac_enaddr)); 252 253 /* Set up MII bus. */ 254 sc->sc_miibus.mii_ifp = ifp; 255 sc->sc_miibus.mii_readreg = age_miibus_readreg; 256 sc->sc_miibus.mii_writereg = age_miibus_writereg; 257 sc->sc_miibus.mii_statchg = age_miibus_statchg; 258 259 ifmedia_init(&sc->sc_miibus.mii_media, 0, age_mediachange, 260 age_mediastatus); 261 mii_attach(self, &sc->sc_miibus, 0xffffffff, MII_PHY_ANY, 262 MII_OFFSET_ANY, MIIF_DOPAUSE); 263 264 if (LIST_FIRST(&sc->sc_miibus.mii_phys) == NULL) { 265 printf("%s: no PHY found!\n", sc->sc_dev.dv_xname); 266 ifmedia_add(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL, 267 0, NULL); 268 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL); 269 } else 270 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_AUTO); 271 272 if_attach(ifp); 273 ether_ifattach(ifp); 274 275 timeout_set(&sc->age_tick_ch, age_tick, sc); 276 277 return; 278 fail: 279 age_dma_free(sc); 280 if (sc->sc_irq_handle != NULL) 281 pci_intr_disestablish(pc, sc->sc_irq_handle); 282 if (sc->sc_mem_size) 283 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 284 } 285 286 int 287 age_detach(struct device *self, int flags) 288 { 289 struct age_softc *sc = (struct age_softc *)self; 290 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 291 int s; 292 293 s = splnet(); 294 age_stop(sc); 295 splx(s); 296 297 mii_detach(&sc->sc_miibus, MII_PHY_ANY, MII_OFFSET_ANY); 298 299 /* Delete all remaining media. */ 300 ifmedia_delete_instance(&sc->sc_miibus.mii_media, IFM_INST_ANY); 301 302 ether_ifdetach(ifp); 303 if_detach(ifp); 304 age_dma_free(sc); 305 306 if (sc->sc_irq_handle != NULL) { 307 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 308 sc->sc_irq_handle = NULL; 309 } 310 311 return (0); 312 } 313 314 /* 315 * Read a PHY register on the MII of the L1. 316 */ 317 int 318 age_miibus_readreg(struct device *dev, int phy, int reg) 319 { 320 struct age_softc *sc = (struct age_softc *)dev; 321 uint32_t v; 322 int i; 323 324 if (phy != sc->age_phyaddr) 325 return (0); 326 327 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 328 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 329 for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 330 DELAY(1); 331 v = CSR_READ_4(sc, AGE_MDIO); 332 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 333 break; 334 } 335 336 if (i == 0) { 337 printf("%s: phy read timeout: phy %d, reg %d\n", 338 sc->sc_dev.dv_xname, phy, reg); 339 return (0); 340 } 341 342 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 343 } 344 345 /* 346 * Write a PHY register on the MII of the L1. 347 */ 348 void 349 age_miibus_writereg(struct device *dev, int phy, int reg, int val) 350 { 351 struct age_softc *sc = (struct age_softc *)dev; 352 uint32_t v; 353 int i; 354 355 if (phy != sc->age_phyaddr) 356 return; 357 358 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 359 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 360 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 361 362 for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 363 DELAY(1); 364 v = CSR_READ_4(sc, AGE_MDIO); 365 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 366 break; 367 } 368 369 if (i == 0) { 370 printf("%s: phy write timeout: phy %d, reg %d\n", 371 sc->sc_dev.dv_xname, phy, reg); 372 } 373 } 374 375 /* 376 * Callback from MII layer when media changes. 377 */ 378 void 379 age_miibus_statchg(struct device *dev) 380 { 381 struct age_softc *sc = (struct age_softc *)dev; 382 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 383 struct mii_data *mii = &sc->sc_miibus; 384 385 if ((ifp->if_flags & IFF_RUNNING) == 0) 386 return; 387 388 sc->age_flags &= ~AGE_FLAG_LINK; 389 if ((mii->mii_media_status & IFM_AVALID) != 0) { 390 switch (IFM_SUBTYPE(mii->mii_media_active)) { 391 case IFM_10_T: 392 case IFM_100_TX: 393 case IFM_1000_T: 394 sc->age_flags |= AGE_FLAG_LINK; 395 break; 396 default: 397 break; 398 } 399 } 400 401 /* Stop Rx/Tx MACs. */ 402 age_stop_rxmac(sc); 403 age_stop_txmac(sc); 404 405 /* Program MACs with resolved speed/duplex/flow-control. */ 406 if ((sc->age_flags & AGE_FLAG_LINK) != 0) { 407 uint32_t reg; 408 409 age_mac_config(sc); 410 reg = CSR_READ_4(sc, AGE_MAC_CFG); 411 /* Restart DMA engine and Tx/Rx MAC. */ 412 CSR_WRITE_4(sc, AGE_DMA_CFG, CSR_READ_4(sc, AGE_DMA_CFG) | 413 DMA_CFG_RD_ENB | DMA_CFG_WR_ENB); 414 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 415 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 416 } 417 } 418 419 /* 420 * Get the current interface media status. 421 */ 422 void 423 age_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 424 { 425 struct age_softc *sc = ifp->if_softc; 426 struct mii_data *mii = &sc->sc_miibus; 427 428 mii_pollstat(mii); 429 ifmr->ifm_status = mii->mii_media_status; 430 ifmr->ifm_active = mii->mii_media_active; 431 } 432 433 /* 434 * Set hardware to newly-selected media. 435 */ 436 int 437 age_mediachange(struct ifnet *ifp) 438 { 439 struct age_softc *sc = ifp->if_softc; 440 struct mii_data *mii = &sc->sc_miibus; 441 int error; 442 443 if (mii->mii_instance != 0) { 444 struct mii_softc *miisc; 445 446 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 447 mii_phy_reset(miisc); 448 } 449 error = mii_mediachg(mii); 450 451 return (error); 452 } 453 454 int 455 age_intr(void *arg) 456 { 457 struct age_softc *sc = arg; 458 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 459 struct cmb *cmb; 460 uint32_t status; 461 462 status = CSR_READ_4(sc, AGE_INTR_STATUS); 463 if (status == 0 || (status & AGE_INTRS) == 0) 464 return (0); 465 466 /* Disable interrupts. */ 467 CSR_WRITE_4(sc, AGE_INTR_STATUS, status | INTR_DIS_INT); 468 469 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 470 sc->age_cdata.age_cmb_block_map->dm_mapsize, 471 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 472 cmb = sc->age_rdata.age_cmb_block; 473 status = letoh32(cmb->intr_status); 474 if ((status & AGE_INTRS) == 0) 475 goto back; 476 477 sc->age_tpd_cons = (letoh32(cmb->tpd_cons) & TPD_CONS_MASK) >> 478 TPD_CONS_SHIFT; 479 sc->age_rr_prod = (letoh32(cmb->rprod_cons) & RRD_PROD_MASK) >> 480 RRD_PROD_SHIFT; 481 /* Let hardware know CMB was served. */ 482 cmb->intr_status = 0; 483 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 484 sc->age_cdata.age_cmb_block_map->dm_mapsize, 485 BUS_DMASYNC_PREWRITE); 486 487 if (ifp->if_flags & IFF_RUNNING) { 488 if (status & INTR_CMB_RX) 489 age_rxintr(sc, sc->age_rr_prod); 490 491 if (status & INTR_CMB_TX) 492 age_txintr(sc, sc->age_tpd_cons); 493 494 if (status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) { 495 if (status & INTR_DMA_RD_TO_RST) 496 printf("%s: DMA read error! -- resetting\n", 497 sc->sc_dev.dv_xname); 498 if (status & INTR_DMA_WR_TO_RST) 499 printf("%s: DMA write error! -- resetting\n", 500 sc->sc_dev.dv_xname); 501 age_init(ifp); 502 } 503 504 age_start(ifp); 505 506 if (status & INTR_SMB) 507 age_stats_update(sc); 508 } 509 510 /* Check whether CMB was updated while serving Tx/Rx/SMB handler. */ 511 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 512 sc->age_cdata.age_cmb_block_map->dm_mapsize, 513 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 514 515 back: 516 /* Re-enable interrupts. */ 517 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); 518 519 return (1); 520 } 521 522 void 523 age_get_macaddr(struct age_softc *sc) 524 { 525 uint32_t ea[2], reg; 526 int i, vpdc; 527 528 reg = CSR_READ_4(sc, AGE_SPI_CTRL); 529 if ((reg & SPI_VPD_ENB) != 0) { 530 /* Get VPD stored in TWSI EEPROM. */ 531 reg &= ~SPI_VPD_ENB; 532 CSR_WRITE_4(sc, AGE_SPI_CTRL, reg); 533 } 534 535 if (pci_get_capability(sc->sc_pct, sc->sc_pcitag, 536 PCI_CAP_VPD, &vpdc, NULL)) { 537 /* 538 * PCI VPD capability found, let TWSI reload EEPROM. 539 * This will set Ethernet address of controller. 540 */ 541 CSR_WRITE_4(sc, AGE_TWSI_CTRL, CSR_READ_4(sc, AGE_TWSI_CTRL) | 542 TWSI_CTRL_SW_LD_START); 543 for (i = 100; i > 0; i--) { 544 DELAY(1000); 545 reg = CSR_READ_4(sc, AGE_TWSI_CTRL); 546 if ((reg & TWSI_CTRL_SW_LD_START) == 0) 547 break; 548 } 549 if (i == 0) 550 printf("%s: reloading EEPROM timeout!\n", 551 sc->sc_dev.dv_xname); 552 } else { 553 if (agedebug) 554 printf("%s: PCI VPD capability not found!\n", 555 sc->sc_dev.dv_xname); 556 } 557 558 ea[0] = CSR_READ_4(sc, AGE_PAR0); 559 ea[1] = CSR_READ_4(sc, AGE_PAR1); 560 sc->age_eaddr[0] = (ea[1] >> 8) & 0xFF; 561 sc->age_eaddr[1] = (ea[1] >> 0) & 0xFF; 562 sc->age_eaddr[2] = (ea[0] >> 24) & 0xFF; 563 sc->age_eaddr[3] = (ea[0] >> 16) & 0xFF; 564 sc->age_eaddr[4] = (ea[0] >> 8) & 0xFF; 565 sc->age_eaddr[5] = (ea[0] >> 0) & 0xFF; 566 } 567 568 void 569 age_phy_reset(struct age_softc *sc) 570 { 571 uint16_t reg, pn; 572 int i, linkup; 573 574 /* Reset PHY. */ 575 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_RST); 576 DELAY(2000); 577 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_CLR); 578 DELAY(2000); 579 580 #define ATPHY_DBG_ADDR 0x1D 581 #define ATPHY_DBG_DATA 0x1E 582 #define ATPHY_CDTC 0x16 583 #define PHY_CDTC_ENB 0x0001 584 #define PHY_CDTC_POFF 8 585 #define ATPHY_CDTS 0x1C 586 #define PHY_CDTS_STAT_OK 0x0000 587 #define PHY_CDTS_STAT_SHORT 0x0100 588 #define PHY_CDTS_STAT_OPEN 0x0200 589 #define PHY_CDTS_STAT_INVAL 0x0300 590 #define PHY_CDTS_STAT_MASK 0x0300 591 592 /* Check power saving mode. Magic from Linux. */ 593 age_miibus_writereg(&sc->sc_dev, sc->age_phyaddr, MII_BMCR, BMCR_RESET); 594 for (linkup = 0, pn = 0; pn < 4; pn++) { 595 age_miibus_writereg(&sc->sc_dev, sc->age_phyaddr, ATPHY_CDTC, 596 (pn << PHY_CDTC_POFF) | PHY_CDTC_ENB); 597 for (i = 200; i > 0; i--) { 598 DELAY(1000); 599 reg = age_miibus_readreg(&sc->sc_dev, sc->age_phyaddr, 600 ATPHY_CDTC); 601 if ((reg & PHY_CDTC_ENB) == 0) 602 break; 603 } 604 DELAY(1000); 605 reg = age_miibus_readreg(&sc->sc_dev, sc->age_phyaddr, 606 ATPHY_CDTS); 607 if ((reg & PHY_CDTS_STAT_MASK) != PHY_CDTS_STAT_OPEN) { 608 linkup++; 609 break; 610 } 611 } 612 age_miibus_writereg(&sc->sc_dev, sc->age_phyaddr, MII_BMCR, 613 BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 614 if (linkup == 0) { 615 age_miibus_writereg(&sc->sc_dev, sc->age_phyaddr, 616 ATPHY_DBG_ADDR, 0); 617 age_miibus_writereg(&sc->sc_dev, sc->age_phyaddr, 618 ATPHY_DBG_DATA, 0x124E); 619 age_miibus_writereg(&sc->sc_dev, sc->age_phyaddr, 620 ATPHY_DBG_ADDR, 1); 621 reg = age_miibus_readreg(&sc->sc_dev, sc->age_phyaddr, 622 ATPHY_DBG_DATA); 623 age_miibus_writereg(&sc->sc_dev, sc->age_phyaddr, 624 ATPHY_DBG_DATA, reg | 0x03); 625 /* XXX */ 626 DELAY(1500 * 1000); 627 age_miibus_writereg(&sc->sc_dev, sc->age_phyaddr, 628 ATPHY_DBG_ADDR, 0); 629 age_miibus_writereg(&sc->sc_dev, sc->age_phyaddr, 630 ATPHY_DBG_DATA, 0x024E); 631 } 632 633 #undef ATPHY_DBG_ADDR 634 #undef ATPHY_DBG_DATA 635 #undef ATPHY_CDTC 636 #undef PHY_CDTC_ENB 637 #undef PHY_CDTC_POFF 638 #undef ATPHY_CDTS 639 #undef PHY_CDTS_STAT_OK 640 #undef PHY_CDTS_STAT_SHORT 641 #undef PHY_CDTS_STAT_OPEN 642 #undef PHY_CDTS_STAT_INVAL 643 #undef PHY_CDTS_STAT_MASK 644 } 645 646 int 647 age_dma_alloc(struct age_softc *sc) 648 { 649 struct age_txdesc *txd; 650 struct age_rxdesc *rxd; 651 int nsegs, error, i; 652 653 /* 654 * Create DMA stuffs for TX ring 655 */ 656 error = bus_dmamap_create(sc->sc_dmat, AGE_TX_RING_SZ, 1, 657 AGE_TX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->age_cdata.age_tx_ring_map); 658 if (error) 659 return (ENOBUFS); 660 661 /* Allocate DMA'able memory for TX ring */ 662 error = bus_dmamem_alloc(sc->sc_dmat, AGE_TX_RING_SZ, 663 ETHER_ALIGN, 0, &sc->age_rdata.age_tx_ring_seg, 1, 664 &nsegs, BUS_DMA_WAITOK | BUS_DMA_ZERO); 665 if (error) { 666 printf("%s: could not allocate DMA'able memory for Tx ring.\n", 667 sc->sc_dev.dv_xname); 668 return error; 669 } 670 671 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_tx_ring_seg, 672 nsegs, AGE_TX_RING_SZ, (caddr_t *)&sc->age_rdata.age_tx_ring, 673 BUS_DMA_NOWAIT); 674 if (error) 675 return (ENOBUFS); 676 677 /* Load the DMA map for Tx ring. */ 678 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 679 sc->age_rdata.age_tx_ring, AGE_TX_RING_SZ, NULL, BUS_DMA_WAITOK); 680 if (error) { 681 printf("%s: could not load DMA'able memory for Tx ring.\n", 682 sc->sc_dev.dv_xname); 683 bus_dmamem_free(sc->sc_dmat, 684 (bus_dma_segment_t *)&sc->age_rdata.age_tx_ring, 1); 685 return error; 686 } 687 688 sc->age_rdata.age_tx_ring_paddr = 689 sc->age_cdata.age_tx_ring_map->dm_segs[0].ds_addr; 690 691 /* 692 * Create DMA stuffs for RX ring 693 */ 694 error = bus_dmamap_create(sc->sc_dmat, AGE_RX_RING_SZ, 1, 695 AGE_RX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->age_cdata.age_rx_ring_map); 696 if (error) 697 return (ENOBUFS); 698 699 /* Allocate DMA'able memory for RX ring */ 700 error = bus_dmamem_alloc(sc->sc_dmat, AGE_RX_RING_SZ, 701 ETHER_ALIGN, 0, &sc->age_rdata.age_rx_ring_seg, 1, 702 &nsegs, BUS_DMA_WAITOK | BUS_DMA_ZERO); 703 if (error) { 704 printf("%s: could not allocate DMA'able memory for Rx ring.\n", 705 sc->sc_dev.dv_xname); 706 return error; 707 } 708 709 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_rx_ring_seg, 710 nsegs, AGE_RX_RING_SZ, (caddr_t *)&sc->age_rdata.age_rx_ring, 711 BUS_DMA_NOWAIT); 712 if (error) 713 return (ENOBUFS); 714 715 /* Load the DMA map for Rx ring. */ 716 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_rx_ring_map, 717 sc->age_rdata.age_rx_ring, AGE_RX_RING_SZ, NULL, BUS_DMA_WAITOK); 718 if (error) { 719 printf("%s: could not load DMA'able memory for Rx ring.\n", 720 sc->sc_dev.dv_xname); 721 bus_dmamem_free(sc->sc_dmat, 722 (bus_dma_segment_t *)sc->age_rdata.age_rx_ring, 1); 723 return error; 724 } 725 726 sc->age_rdata.age_rx_ring_paddr = 727 sc->age_cdata.age_rx_ring_map->dm_segs[0].ds_addr; 728 729 /* 730 * Create DMA stuffs for RX return ring 731 */ 732 error = bus_dmamap_create(sc->sc_dmat, AGE_RR_RING_SZ, 1, 733 AGE_RR_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->age_cdata.age_rr_ring_map); 734 if (error) 735 return (ENOBUFS); 736 737 /* Allocate DMA'able memory for RX return ring */ 738 error = bus_dmamem_alloc(sc->sc_dmat, AGE_RR_RING_SZ, 739 ETHER_ALIGN, 0, &sc->age_rdata.age_rr_ring_seg, 1, 740 &nsegs, BUS_DMA_WAITOK | BUS_DMA_ZERO); 741 if (error) { 742 printf("%s: could not allocate DMA'able memory for Rx " 743 "return ring.\n", sc->sc_dev.dv_xname); 744 return error; 745 } 746 747 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_rr_ring_seg, 748 nsegs, AGE_RR_RING_SZ, (caddr_t *)&sc->age_rdata.age_rr_ring, 749 BUS_DMA_NOWAIT); 750 if (error) 751 return (ENOBUFS); 752 753 /* Load the DMA map for Rx return ring. */ 754 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 755 sc->age_rdata.age_rr_ring, AGE_RR_RING_SZ, NULL, BUS_DMA_WAITOK); 756 if (error) { 757 printf("%s: could not load DMA'able memory for Rx return ring." 758 "\n", sc->sc_dev.dv_xname); 759 bus_dmamem_free(sc->sc_dmat, 760 (bus_dma_segment_t *)&sc->age_rdata.age_rr_ring, 1); 761 return error; 762 } 763 764 sc->age_rdata.age_rr_ring_paddr = 765 sc->age_cdata.age_rr_ring_map->dm_segs[0].ds_addr; 766 767 /* 768 * Create DMA stuffs for CMB block 769 */ 770 error = bus_dmamap_create(sc->sc_dmat, AGE_CMB_BLOCK_SZ, 1, 771 AGE_CMB_BLOCK_SZ, 0, BUS_DMA_NOWAIT, 772 &sc->age_cdata.age_cmb_block_map); 773 if (error) 774 return (ENOBUFS); 775 776 /* Allocate DMA'able memory for CMB block */ 777 error = bus_dmamem_alloc(sc->sc_dmat, AGE_CMB_BLOCK_SZ, 778 ETHER_ALIGN, 0, &sc->age_rdata.age_cmb_block_seg, 1, 779 &nsegs, BUS_DMA_WAITOK | BUS_DMA_ZERO); 780 if (error) { 781 printf("%s: could not allocate DMA'able memory for " 782 "CMB block\n", sc->sc_dev.dv_xname); 783 return error; 784 } 785 786 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_cmb_block_seg, 787 nsegs, AGE_CMB_BLOCK_SZ, (caddr_t *)&sc->age_rdata.age_cmb_block, 788 BUS_DMA_NOWAIT); 789 if (error) 790 return (ENOBUFS); 791 792 /* Load the DMA map for CMB block. */ 793 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 794 sc->age_rdata.age_cmb_block, AGE_CMB_BLOCK_SZ, NULL, 795 BUS_DMA_WAITOK); 796 if (error) { 797 printf("%s: could not load DMA'able memory for CMB block\n", 798 sc->sc_dev.dv_xname); 799 bus_dmamem_free(sc->sc_dmat, 800 (bus_dma_segment_t *)&sc->age_rdata.age_cmb_block, 1); 801 return error; 802 } 803 804 sc->age_rdata.age_cmb_block_paddr = 805 sc->age_cdata.age_cmb_block_map->dm_segs[0].ds_addr; 806 807 /* 808 * Create DMA stuffs for SMB block 809 */ 810 error = bus_dmamap_create(sc->sc_dmat, AGE_SMB_BLOCK_SZ, 1, 811 AGE_SMB_BLOCK_SZ, 0, BUS_DMA_NOWAIT, 812 &sc->age_cdata.age_smb_block_map); 813 if (error) 814 return (ENOBUFS); 815 816 /* Allocate DMA'able memory for SMB block */ 817 error = bus_dmamem_alloc(sc->sc_dmat, AGE_SMB_BLOCK_SZ, 818 ETHER_ALIGN, 0, &sc->age_rdata.age_smb_block_seg, 1, 819 &nsegs, BUS_DMA_WAITOK | BUS_DMA_ZERO); 820 if (error) { 821 printf("%s: could not allocate DMA'able memory for " 822 "SMB block\n", sc->sc_dev.dv_xname); 823 return error; 824 } 825 826 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_smb_block_seg, 827 nsegs, AGE_SMB_BLOCK_SZ, (caddr_t *)&sc->age_rdata.age_smb_block, 828 BUS_DMA_NOWAIT); 829 if (error) 830 return (ENOBUFS); 831 832 /* Load the DMA map for SMB block */ 833 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 834 sc->age_rdata.age_smb_block, AGE_SMB_BLOCK_SZ, NULL, 835 BUS_DMA_WAITOK); 836 if (error) { 837 printf("%s: could not load DMA'able memory for SMB block\n", 838 sc->sc_dev.dv_xname); 839 bus_dmamem_free(sc->sc_dmat, 840 (bus_dma_segment_t *)&sc->age_rdata.age_smb_block, 1); 841 return error; 842 } 843 844 sc->age_rdata.age_smb_block_paddr = 845 sc->age_cdata.age_smb_block_map->dm_segs[0].ds_addr; 846 847 /* Create DMA maps for Tx buffers. */ 848 for (i = 0; i < AGE_TX_RING_CNT; i++) { 849 txd = &sc->age_cdata.age_txdesc[i]; 850 txd->tx_m = NULL; 851 txd->tx_dmamap = NULL; 852 error = bus_dmamap_create(sc->sc_dmat, AGE_TSO_MAXSIZE, 853 AGE_MAXTXSEGS, AGE_TSO_MAXSEGSIZE, 0, BUS_DMA_NOWAIT, 854 &txd->tx_dmamap); 855 if (error) { 856 printf("%s: could not create Tx dmamap.\n", 857 sc->sc_dev.dv_xname); 858 return error; 859 } 860 } 861 862 /* Create DMA maps for Rx buffers. */ 863 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 864 BUS_DMA_NOWAIT, &sc->age_cdata.age_rx_sparemap); 865 if (error) { 866 printf("%s: could not create spare Rx dmamap.\n", 867 sc->sc_dev.dv_xname); 868 return error; 869 } 870 for (i = 0; i < AGE_RX_RING_CNT; i++) { 871 rxd = &sc->age_cdata.age_rxdesc[i]; 872 rxd->rx_m = NULL; 873 rxd->rx_dmamap = NULL; 874 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 875 MCLBYTES, 0, BUS_DMA_NOWAIT, &rxd->rx_dmamap); 876 if (error) { 877 printf("%s: could not create Rx dmamap.\n", 878 sc->sc_dev.dv_xname); 879 return error; 880 } 881 } 882 883 return (0); 884 } 885 886 void 887 age_dma_free(struct age_softc *sc) 888 { 889 struct age_txdesc *txd; 890 struct age_rxdesc *rxd; 891 int i; 892 893 /* Tx buffers */ 894 for (i = 0; i < AGE_TX_RING_CNT; i++) { 895 txd = &sc->age_cdata.age_txdesc[i]; 896 if (txd->tx_dmamap != NULL) { 897 bus_dmamap_destroy(sc->sc_dmat, txd->tx_dmamap); 898 txd->tx_dmamap = NULL; 899 } 900 } 901 /* Rx buffers */ 902 for (i = 0; i < AGE_RX_RING_CNT; i++) { 903 rxd = &sc->age_cdata.age_rxdesc[i]; 904 if (rxd->rx_dmamap != NULL) { 905 bus_dmamap_destroy(sc->sc_dmat, rxd->rx_dmamap); 906 rxd->rx_dmamap = NULL; 907 } 908 } 909 if (sc->age_cdata.age_rx_sparemap != NULL) { 910 bus_dmamap_destroy(sc->sc_dmat, sc->age_cdata.age_rx_sparemap); 911 sc->age_cdata.age_rx_sparemap = NULL; 912 } 913 914 /* Tx ring. */ 915 if (sc->age_cdata.age_tx_ring_map != NULL) 916 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_tx_ring_map); 917 if (sc->age_cdata.age_tx_ring_map != NULL && 918 sc->age_rdata.age_tx_ring != NULL) 919 bus_dmamem_free(sc->sc_dmat, 920 (bus_dma_segment_t *)sc->age_rdata.age_tx_ring, 1); 921 sc->age_rdata.age_tx_ring = NULL; 922 sc->age_cdata.age_tx_ring_map = NULL; 923 924 /* Rx ring. */ 925 if (sc->age_cdata.age_rx_ring_map != NULL) 926 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_rx_ring_map); 927 if (sc->age_cdata.age_rx_ring_map != NULL && 928 sc->age_rdata.age_rx_ring != NULL) 929 bus_dmamem_free(sc->sc_dmat, 930 (bus_dma_segment_t *)sc->age_rdata.age_rx_ring, 1); 931 sc->age_rdata.age_rx_ring = NULL; 932 sc->age_cdata.age_rx_ring_map = NULL; 933 934 /* Rx return ring. */ 935 if (sc->age_cdata.age_rr_ring_map != NULL) 936 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_rr_ring_map); 937 if (sc->age_cdata.age_rr_ring_map != NULL && 938 sc->age_rdata.age_rr_ring != NULL) 939 bus_dmamem_free(sc->sc_dmat, 940 (bus_dma_segment_t *)sc->age_rdata.age_rr_ring, 1); 941 sc->age_rdata.age_rr_ring = NULL; 942 sc->age_cdata.age_rr_ring_map = NULL; 943 944 /* CMB block */ 945 if (sc->age_cdata.age_cmb_block_map != NULL) 946 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_cmb_block_map); 947 if (sc->age_cdata.age_cmb_block_map != NULL && 948 sc->age_rdata.age_cmb_block != NULL) 949 bus_dmamem_free(sc->sc_dmat, 950 (bus_dma_segment_t *)sc->age_rdata.age_cmb_block, 1); 951 sc->age_rdata.age_cmb_block = NULL; 952 sc->age_cdata.age_cmb_block_map = NULL; 953 954 /* SMB block */ 955 if (sc->age_cdata.age_smb_block_map != NULL) 956 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_smb_block_map); 957 if (sc->age_cdata.age_smb_block_map != NULL && 958 sc->age_rdata.age_smb_block != NULL) 959 bus_dmamem_free(sc->sc_dmat, 960 (bus_dma_segment_t *)sc->age_rdata.age_smb_block, 1); 961 sc->age_rdata.age_smb_block = NULL; 962 sc->age_cdata.age_smb_block_map = NULL; 963 } 964 965 void 966 age_start(struct ifnet *ifp) 967 { 968 struct age_softc *sc = ifp->if_softc; 969 struct mbuf *m_head; 970 int enq; 971 972 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 973 return; 974 if ((sc->age_flags & AGE_FLAG_LINK) == 0) 975 return; 976 if (IFQ_IS_EMPTY(&ifp->if_snd)) 977 return; 978 979 enq = 0; 980 for (;;) { 981 IFQ_DEQUEUE(&ifp->if_snd, m_head); 982 if (m_head == NULL) 983 break; 984 985 /* 986 * Pack the data into the transmit ring. If we 987 * don't have room, set the OACTIVE flag and wait 988 * for the NIC to drain the ring. 989 */ 990 if (age_encap(sc, &m_head)) { 991 if (m_head == NULL) 992 ifp->if_oerrors++; 993 else { 994 IF_PREPEND(&ifp->if_snd, m_head); 995 ifp->if_flags |= IFF_OACTIVE; 996 } 997 break; 998 } 999 enq = 1; 1000 1001 #if NBPFILTER > 0 1002 /* 1003 * If there's a BPF listener, bounce a copy of this frame 1004 * to him. 1005 */ 1006 if (ifp->if_bpf != NULL) 1007 bpf_mtap_ether(ifp->if_bpf, m_head, BPF_DIRECTION_OUT); 1008 #endif 1009 } 1010 1011 if (enq) { 1012 /* Update mbox. */ 1013 AGE_COMMIT_MBOX(sc); 1014 /* Set a timeout in case the chip goes out to lunch. */ 1015 ifp->if_timer = AGE_TX_TIMEOUT; 1016 } 1017 } 1018 1019 void 1020 age_watchdog(struct ifnet *ifp) 1021 { 1022 struct age_softc *sc = ifp->if_softc; 1023 1024 if ((sc->age_flags & AGE_FLAG_LINK) == 0) { 1025 printf("%s: watchdog timeout (missed link)\n", 1026 sc->sc_dev.dv_xname); 1027 ifp->if_oerrors++; 1028 age_init(ifp); 1029 return; 1030 } 1031 1032 if (sc->age_cdata.age_tx_cnt == 0) { 1033 printf("%s: watchdog timeout (missed Tx interrupts) " 1034 "-- recovering\n", sc->sc_dev.dv_xname); 1035 age_start(ifp); 1036 return; 1037 } 1038 1039 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 1040 ifp->if_oerrors++; 1041 age_init(ifp); 1042 age_start(ifp); 1043 } 1044 1045 int 1046 age_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1047 { 1048 struct age_softc *sc = ifp->if_softc; 1049 struct mii_data *mii = &sc->sc_miibus; 1050 struct ifaddr *ifa = (struct ifaddr *)data; 1051 struct ifreq *ifr = (struct ifreq *)data; 1052 int s, error = 0; 1053 1054 s = splnet(); 1055 1056 switch (cmd) { 1057 case SIOCSIFADDR: 1058 ifp->if_flags |= IFF_UP; 1059 if (!(ifp->if_flags & IFF_RUNNING)) 1060 age_init(ifp); 1061 #ifdef INET 1062 if (ifa->ifa_addr->sa_family == AF_INET) 1063 arp_ifinit(&sc->sc_arpcom, ifa); 1064 #endif 1065 break; 1066 1067 case SIOCSIFFLAGS: 1068 if (ifp->if_flags & IFF_UP) { 1069 if (ifp->if_flags & IFF_RUNNING) 1070 error = ENETRESET; 1071 else 1072 age_init(ifp); 1073 } else { 1074 if (ifp->if_flags & IFF_RUNNING) 1075 age_stop(sc); 1076 } 1077 break; 1078 1079 case SIOCSIFMEDIA: 1080 case SIOCGIFMEDIA: 1081 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1082 break; 1083 1084 default: 1085 error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data); 1086 break; 1087 } 1088 1089 if (error == ENETRESET) { 1090 if (ifp->if_flags & IFF_RUNNING) 1091 age_iff(sc); 1092 error = 0; 1093 } 1094 1095 splx(s); 1096 return (error); 1097 } 1098 1099 void 1100 age_mac_config(struct age_softc *sc) 1101 { 1102 struct mii_data *mii = &sc->sc_miibus; 1103 uint32_t reg; 1104 1105 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1106 reg &= ~MAC_CFG_FULL_DUPLEX; 1107 reg &= ~(MAC_CFG_TX_FC | MAC_CFG_RX_FC); 1108 reg &= ~MAC_CFG_SPEED_MASK; 1109 1110 /* Reprogram MAC with resolved speed/duplex. */ 1111 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1112 case IFM_10_T: 1113 case IFM_100_TX: 1114 reg |= MAC_CFG_SPEED_10_100; 1115 break; 1116 case IFM_1000_T: 1117 reg |= MAC_CFG_SPEED_1000; 1118 break; 1119 } 1120 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1121 reg |= MAC_CFG_FULL_DUPLEX; 1122 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1123 reg |= MAC_CFG_TX_FC; 1124 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1125 reg |= MAC_CFG_RX_FC; 1126 } 1127 1128 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1129 } 1130 1131 int 1132 age_encap(struct age_softc *sc, struct mbuf **m_head) 1133 { 1134 struct age_txdesc *txd, *txd_last; 1135 struct tx_desc *desc; 1136 struct mbuf *m; 1137 bus_dmamap_t map; 1138 uint32_t cflags, poff, vtag; 1139 int error, i, prod; 1140 1141 m = *m_head; 1142 cflags = vtag = 0; 1143 poff = 0; 1144 1145 prod = sc->age_cdata.age_tx_prod; 1146 txd = &sc->age_cdata.age_txdesc[prod]; 1147 txd_last = txd; 1148 map = txd->tx_dmamap; 1149 1150 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, BUS_DMA_NOWAIT); 1151 if (error != 0 && error != EFBIG) 1152 goto drop; 1153 if (error != 0) { 1154 if (m_defrag(*m_head, M_DONTWAIT)) { 1155 error = ENOBUFS; 1156 goto drop; 1157 } 1158 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, 1159 BUS_DMA_NOWAIT); 1160 if (error != 0) 1161 goto drop; 1162 } 1163 1164 /* Check descriptor overrun. */ 1165 if (sc->age_cdata.age_tx_cnt + map->dm_nsegs >= AGE_TX_RING_CNT - 2) { 1166 bus_dmamap_unload(sc->sc_dmat, map); 1167 return (ENOBUFS); 1168 } 1169 1170 m = *m_head; 1171 /* Configure Tx IP/TCP/UDP checksum offload. */ 1172 if ((m->m_pkthdr.csum_flags & AGE_CSUM_FEATURES) != 0) { 1173 cflags |= AGE_TD_CSUM; 1174 if ((m->m_pkthdr.csum_flags & M_TCP_CSUM_OUT) != 0) 1175 cflags |= AGE_TD_TCPCSUM; 1176 if ((m->m_pkthdr.csum_flags & M_UDP_CSUM_OUT) != 0) 1177 cflags |= AGE_TD_UDPCSUM; 1178 /* Set checksum start offset. */ 1179 cflags |= (poff << AGE_TD_CSUM_PLOADOFFSET_SHIFT); 1180 } 1181 1182 #if NVLAN > 0 1183 /* Configure VLAN hardware tag insertion. */ 1184 if (m->m_flags & M_VLANTAG) { 1185 vtag = AGE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag); 1186 vtag = ((vtag << AGE_TD_VLAN_SHIFT) & AGE_TD_VLAN_MASK); 1187 cflags |= AGE_TD_INSERT_VLAN_TAG; 1188 } 1189 #endif 1190 1191 desc = NULL; 1192 for (i = 0; i < map->dm_nsegs; i++) { 1193 desc = &sc->age_rdata.age_tx_ring[prod]; 1194 desc->addr = htole64(map->dm_segs[i].ds_addr); 1195 desc->len = 1196 htole32(AGE_TX_BYTES(map->dm_segs[i].ds_len) | vtag); 1197 desc->flags = htole32(cflags); 1198 sc->age_cdata.age_tx_cnt++; 1199 AGE_DESC_INC(prod, AGE_TX_RING_CNT); 1200 } 1201 1202 /* Update producer index. */ 1203 sc->age_cdata.age_tx_prod = prod; 1204 1205 /* Set EOP on the last descriptor. */ 1206 prod = (prod + AGE_TX_RING_CNT - 1) % AGE_TX_RING_CNT; 1207 desc = &sc->age_rdata.age_tx_ring[prod]; 1208 desc->flags |= htole32(AGE_TD_EOP); 1209 1210 /* Swap dmamap of the first and the last. */ 1211 txd = &sc->age_cdata.age_txdesc[prod]; 1212 map = txd_last->tx_dmamap; 1213 txd_last->tx_dmamap = txd->tx_dmamap; 1214 txd->tx_dmamap = map; 1215 txd->tx_m = m; 1216 1217 /* Sync descriptors. */ 1218 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1219 BUS_DMASYNC_PREWRITE); 1220 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 0, 1221 sc->age_cdata.age_tx_ring_map->dm_mapsize, 1222 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1223 1224 return (0); 1225 1226 drop: 1227 m_freem(*m_head); 1228 *m_head = NULL; 1229 return (error); 1230 } 1231 1232 void 1233 age_txintr(struct age_softc *sc, int tpd_cons) 1234 { 1235 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1236 struct age_txdesc *txd; 1237 int cons, prog; 1238 1239 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 0, 1240 sc->age_cdata.age_tx_ring_map->dm_mapsize, 1241 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1242 1243 /* 1244 * Go through our Tx list and free mbufs for those 1245 * frames which have been transmitted. 1246 */ 1247 cons = sc->age_cdata.age_tx_cons; 1248 for (prog = 0; cons != tpd_cons; AGE_DESC_INC(cons, AGE_TX_RING_CNT)) { 1249 if (sc->age_cdata.age_tx_cnt <= 0) 1250 break; 1251 prog++; 1252 ifp->if_flags &= ~IFF_OACTIVE; 1253 sc->age_cdata.age_tx_cnt--; 1254 txd = &sc->age_cdata.age_txdesc[cons]; 1255 /* 1256 * Clear Tx descriptors, it's not required but would 1257 * help debugging in case of Tx issues. 1258 */ 1259 txd->tx_desc->addr = 0; 1260 txd->tx_desc->len = 0; 1261 txd->tx_desc->flags = 0; 1262 1263 if (txd->tx_m == NULL) 1264 continue; 1265 /* Reclaim transmitted mbufs. */ 1266 bus_dmamap_sync(sc->sc_dmat, txd->tx_dmamap, 0, 1267 txd->tx_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1268 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1269 m_freem(txd->tx_m); 1270 txd->tx_m = NULL; 1271 } 1272 1273 if (prog > 0) { 1274 sc->age_cdata.age_tx_cons = cons; 1275 1276 /* 1277 * Unarm watchdog timer only when there are no pending 1278 * Tx descriptors in queue. 1279 */ 1280 if (sc->age_cdata.age_tx_cnt == 0) 1281 ifp->if_timer = 0; 1282 1283 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 0, 1284 sc->age_cdata.age_tx_ring_map->dm_mapsize, 1285 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1286 } 1287 } 1288 1289 /* Receive a frame. */ 1290 void 1291 age_rxeof(struct age_softc *sc, struct rx_rdesc *rxrd) 1292 { 1293 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1294 struct age_rxdesc *rxd; 1295 struct rx_desc *desc; 1296 struct mbuf *mp, *m; 1297 uint32_t status, index; 1298 int count, nsegs, pktlen; 1299 int rx_cons; 1300 1301 status = letoh32(rxrd->flags); 1302 index = letoh32(rxrd->index); 1303 rx_cons = AGE_RX_CONS(index); 1304 nsegs = AGE_RX_NSEGS(index); 1305 1306 sc->age_cdata.age_rxlen = AGE_RX_BYTES(letoh32(rxrd->len)); 1307 if ((status & AGE_RRD_ERROR) != 0 && 1308 (status & (AGE_RRD_CRC | AGE_RRD_CODE | AGE_RRD_DRIBBLE | 1309 AGE_RRD_RUNT | AGE_RRD_OFLOW | AGE_RRD_TRUNC)) != 0) { 1310 /* 1311 * We want to pass the following frames to upper 1312 * layer regardless of error status of Rx return 1313 * ring. 1314 * 1315 * o IP/TCP/UDP checksum is bad. 1316 * o frame length and protocol specific length 1317 * does not match. 1318 */ 1319 sc->age_cdata.age_rx_cons += nsegs; 1320 sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT; 1321 return; 1322 } 1323 1324 pktlen = 0; 1325 for (count = 0; count < nsegs; count++, 1326 AGE_DESC_INC(rx_cons, AGE_RX_RING_CNT)) { 1327 rxd = &sc->age_cdata.age_rxdesc[rx_cons]; 1328 mp = rxd->rx_m; 1329 desc = rxd->rx_desc; 1330 /* Add a new receive buffer to the ring. */ 1331 if (age_newbuf(sc, rxd) != 0) { 1332 ifp->if_iqdrops++; 1333 /* Reuse Rx buffers. */ 1334 if (sc->age_cdata.age_rxhead != NULL) { 1335 m_freem(sc->age_cdata.age_rxhead); 1336 AGE_RXCHAIN_RESET(sc); 1337 } 1338 break; 1339 } 1340 1341 /* The length of the first mbuf is computed last. */ 1342 if (count != 0) { 1343 mp->m_len = AGE_RX_BYTES(letoh32(desc->len)); 1344 pktlen += mp->m_len; 1345 } 1346 1347 /* Chain received mbufs. */ 1348 if (sc->age_cdata.age_rxhead == NULL) { 1349 sc->age_cdata.age_rxhead = mp; 1350 sc->age_cdata.age_rxtail = mp; 1351 } else { 1352 mp->m_flags &= ~M_PKTHDR; 1353 sc->age_cdata.age_rxprev_tail = 1354 sc->age_cdata.age_rxtail; 1355 sc->age_cdata.age_rxtail->m_next = mp; 1356 sc->age_cdata.age_rxtail = mp; 1357 } 1358 1359 if (count == nsegs - 1) { 1360 /* 1361 * It seems that L1 controller has no way 1362 * to tell hardware to strip CRC bytes. 1363 */ 1364 sc->age_cdata.age_rxlen -= ETHER_CRC_LEN; 1365 if (nsegs > 1) { 1366 /* Remove the CRC bytes in chained mbufs. */ 1367 pktlen -= ETHER_CRC_LEN; 1368 if (mp->m_len <= ETHER_CRC_LEN) { 1369 sc->age_cdata.age_rxtail = 1370 sc->age_cdata.age_rxprev_tail; 1371 sc->age_cdata.age_rxtail->m_len -= 1372 (ETHER_CRC_LEN - mp->m_len); 1373 sc->age_cdata.age_rxtail->m_next = NULL; 1374 m_freem(mp); 1375 } else { 1376 mp->m_len -= ETHER_CRC_LEN; 1377 } 1378 } 1379 1380 m = sc->age_cdata.age_rxhead; 1381 m->m_flags |= M_PKTHDR; 1382 m->m_pkthdr.rcvif = ifp; 1383 m->m_pkthdr.len = sc->age_cdata.age_rxlen; 1384 /* Set the first mbuf length. */ 1385 m->m_len = sc->age_cdata.age_rxlen - pktlen; 1386 1387 /* 1388 * Set checksum information. 1389 * It seems that L1 controller can compute partial 1390 * checksum. The partial checksum value can be used 1391 * to accelerate checksum computation for fragmented 1392 * TCP/UDP packets. Upper network stack already 1393 * takes advantage of the partial checksum value in 1394 * IP reassembly stage. But I'm not sure the 1395 * correctness of the partial hardware checksum 1396 * assistance due to lack of data sheet. If it is 1397 * proven to work on L1 I'll enable it. 1398 */ 1399 if (status & AGE_RRD_IPV4) { 1400 if ((status & AGE_RRD_IPCSUM_NOK) == 0) 1401 m->m_pkthdr.csum_flags |= 1402 M_IPV4_CSUM_IN_OK; 1403 if ((status & (AGE_RRD_TCP | AGE_RRD_UDP)) && 1404 (status & AGE_RRD_TCP_UDPCSUM_NOK) == 0) { 1405 m->m_pkthdr.csum_flags |= 1406 M_TCP_CSUM_IN_OK | M_UDP_CSUM_IN_OK; 1407 } 1408 /* 1409 * Don't mark bad checksum for TCP/UDP frames 1410 * as fragmented frames may always have set 1411 * bad checksummed bit of descriptor status. 1412 */ 1413 } 1414 #if NVLAN > 0 1415 /* Check for VLAN tagged frames. */ 1416 if (status & AGE_RRD_VLAN) { 1417 u_int32_t vtag = AGE_RX_VLAN(letoh32(rxrd->vtags)); 1418 m->m_pkthdr.ether_vtag = 1419 AGE_RX_VLAN_TAG(vtag); 1420 m->m_flags |= M_VLANTAG; 1421 } 1422 #endif 1423 1424 #if NBPFILTER > 0 1425 if (ifp->if_bpf) 1426 bpf_mtap_ether(ifp->if_bpf, m, 1427 BPF_DIRECTION_IN); 1428 #endif 1429 /* Pass it on. */ 1430 ether_input_mbuf(ifp, m); 1431 1432 /* Reset mbuf chains. */ 1433 AGE_RXCHAIN_RESET(sc); 1434 } 1435 } 1436 1437 if (count != nsegs) { 1438 sc->age_cdata.age_rx_cons += nsegs; 1439 sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT; 1440 } else 1441 sc->age_cdata.age_rx_cons = rx_cons; 1442 } 1443 1444 void 1445 age_rxintr(struct age_softc *sc, int rr_prod) 1446 { 1447 struct rx_rdesc *rxrd; 1448 int rr_cons, nsegs, pktlen, prog; 1449 1450 rr_cons = sc->age_cdata.age_rr_cons; 1451 if (rr_cons == rr_prod) 1452 return; 1453 1454 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 0, 1455 sc->age_cdata.age_rr_ring_map->dm_mapsize, 1456 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1457 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rx_ring_map, 0, 1458 sc->age_cdata.age_rx_ring_map->dm_mapsize, 1459 BUS_DMASYNC_POSTWRITE); 1460 1461 for (prog = 0; rr_cons != rr_prod; prog++) { 1462 rxrd = &sc->age_rdata.age_rr_ring[rr_cons]; 1463 nsegs = AGE_RX_NSEGS(letoh32(rxrd->index)); 1464 if (nsegs == 0) 1465 break; 1466 /* 1467 * Check number of segments against received bytes 1468 * Non-matching value would indicate that hardware 1469 * is still trying to update Rx return descriptors. 1470 * I'm not sure whether this check is really needed. 1471 */ 1472 pktlen = AGE_RX_BYTES(letoh32(rxrd->len)); 1473 if (nsegs != ((pktlen + (MCLBYTES - ETHER_ALIGN - 1)) / 1474 (MCLBYTES - ETHER_ALIGN))) 1475 break; 1476 1477 /* Received a frame. */ 1478 age_rxeof(sc, rxrd); 1479 1480 /* Clear return ring. */ 1481 rxrd->index = 0; 1482 AGE_DESC_INC(rr_cons, AGE_RR_RING_CNT); 1483 } 1484 1485 if (prog > 0) { 1486 /* Update the consumer index. */ 1487 sc->age_cdata.age_rr_cons = rr_cons; 1488 1489 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rx_ring_map, 0, 1490 sc->age_cdata.age_rx_ring_map->dm_mapsize, 1491 BUS_DMASYNC_PREWRITE); 1492 /* Sync descriptors. */ 1493 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 0, 1494 sc->age_cdata.age_rr_ring_map->dm_mapsize, 1495 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1496 1497 /* Notify hardware availability of new Rx buffers. */ 1498 AGE_COMMIT_MBOX(sc); 1499 } 1500 } 1501 1502 void 1503 age_tick(void *xsc) 1504 { 1505 struct age_softc *sc = xsc; 1506 struct mii_data *mii = &sc->sc_miibus; 1507 int s; 1508 1509 s = splnet(); 1510 mii_tick(mii); 1511 timeout_add_sec(&sc->age_tick_ch, 1); 1512 splx(s); 1513 } 1514 1515 void 1516 age_reset(struct age_softc *sc) 1517 { 1518 uint32_t reg; 1519 int i; 1520 1521 CSR_WRITE_4(sc, AGE_MASTER_CFG, MASTER_RESET); 1522 CSR_READ_4(sc, AGE_MASTER_CFG); 1523 DELAY(1000); 1524 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 1525 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 1526 break; 1527 DELAY(10); 1528 } 1529 1530 if (i == 0) 1531 printf("%s: reset timeout(0x%08x)!\n", sc->sc_dev.dv_xname, 1532 reg); 1533 1534 /* Initialize PCIe module. From Linux. */ 1535 CSR_WRITE_4(sc, 0x12FC, 0x6500); 1536 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 1537 } 1538 1539 int 1540 age_init(struct ifnet *ifp) 1541 { 1542 struct age_softc *sc = ifp->if_softc; 1543 struct mii_data *mii = &sc->sc_miibus; 1544 uint8_t eaddr[ETHER_ADDR_LEN]; 1545 bus_addr_t paddr; 1546 uint32_t reg, fsize; 1547 uint32_t rxf_hi, rxf_lo, rrd_hi, rrd_lo; 1548 int error; 1549 1550 /* 1551 * Cancel any pending I/O. 1552 */ 1553 age_stop(sc); 1554 1555 /* 1556 * Reset the chip to a known state. 1557 */ 1558 age_reset(sc); 1559 1560 /* Initialize descriptors. */ 1561 error = age_init_rx_ring(sc); 1562 if (error != 0) { 1563 printf("%s: no memory for Rx buffers.\n", sc->sc_dev.dv_xname); 1564 age_stop(sc); 1565 return (error); 1566 } 1567 age_init_rr_ring(sc); 1568 age_init_tx_ring(sc); 1569 age_init_cmb_block(sc); 1570 age_init_smb_block(sc); 1571 1572 /* Reprogram the station address. */ 1573 bcopy(LLADDR(ifp->if_sadl), eaddr, ETHER_ADDR_LEN); 1574 CSR_WRITE_4(sc, AGE_PAR0, 1575 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 1576 CSR_WRITE_4(sc, AGE_PAR1, eaddr[0] << 8 | eaddr[1]); 1577 1578 /* Set descriptor base addresses. */ 1579 paddr = sc->age_rdata.age_tx_ring_paddr; 1580 CSR_WRITE_4(sc, AGE_DESC_ADDR_HI, AGE_ADDR_HI(paddr)); 1581 paddr = sc->age_rdata.age_rx_ring_paddr; 1582 CSR_WRITE_4(sc, AGE_DESC_RD_ADDR_LO, AGE_ADDR_LO(paddr)); 1583 paddr = sc->age_rdata.age_rr_ring_paddr; 1584 CSR_WRITE_4(sc, AGE_DESC_RRD_ADDR_LO, AGE_ADDR_LO(paddr)); 1585 paddr = sc->age_rdata.age_tx_ring_paddr; 1586 CSR_WRITE_4(sc, AGE_DESC_TPD_ADDR_LO, AGE_ADDR_LO(paddr)); 1587 paddr = sc->age_rdata.age_cmb_block_paddr; 1588 CSR_WRITE_4(sc, AGE_DESC_CMB_ADDR_LO, AGE_ADDR_LO(paddr)); 1589 paddr = sc->age_rdata.age_smb_block_paddr; 1590 CSR_WRITE_4(sc, AGE_DESC_SMB_ADDR_LO, AGE_ADDR_LO(paddr)); 1591 1592 /* Set Rx/Rx return descriptor counter. */ 1593 CSR_WRITE_4(sc, AGE_DESC_RRD_RD_CNT, 1594 ((AGE_RR_RING_CNT << DESC_RRD_CNT_SHIFT) & 1595 DESC_RRD_CNT_MASK) | 1596 ((AGE_RX_RING_CNT << DESC_RD_CNT_SHIFT) & DESC_RD_CNT_MASK)); 1597 1598 /* Set Tx descriptor counter. */ 1599 CSR_WRITE_4(sc, AGE_DESC_TPD_CNT, 1600 (AGE_TX_RING_CNT << DESC_TPD_CNT_SHIFT) & DESC_TPD_CNT_MASK); 1601 1602 /* Tell hardware that we're ready to load descriptors. */ 1603 CSR_WRITE_4(sc, AGE_DMA_BLOCK, DMA_BLOCK_LOAD); 1604 1605 /* 1606 * Initialize mailbox register. 1607 * Updated producer/consumer index information is exchanged 1608 * through this mailbox register. However Tx producer and 1609 * Rx return consumer/Rx producer are all shared such that 1610 * it's hard to separate code path between Tx and Rx without 1611 * locking. If L1 hardware have a separate mail box register 1612 * for Tx and Rx consumer/producer management we could have 1613 * indepent Tx/Rx handler which in turn Rx handler could have 1614 * been run without any locking. 1615 */ 1616 AGE_COMMIT_MBOX(sc); 1617 1618 /* Configure IPG/IFG parameters. */ 1619 CSR_WRITE_4(sc, AGE_IPG_IFG_CFG, 1620 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK) | 1621 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 1622 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 1623 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK)); 1624 1625 /* Set parameters for half-duplex media. */ 1626 CSR_WRITE_4(sc, AGE_HDPX_CFG, 1627 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 1628 HDPX_CFG_LCOL_MASK) | 1629 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 1630 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 1631 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 1632 HDPX_CFG_ABEBT_MASK) | 1633 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 1634 HDPX_CFG_JAMIPG_MASK)); 1635 1636 /* Configure interrupt moderation timer. */ 1637 sc->age_int_mod = AGE_IM_TIMER_DEFAULT; 1638 CSR_WRITE_2(sc, AGE_IM_TIMER, AGE_USECS(sc->age_int_mod)); 1639 reg = CSR_READ_4(sc, AGE_MASTER_CFG); 1640 reg &= ~MASTER_MTIMER_ENB; 1641 if (AGE_USECS(sc->age_int_mod) == 0) 1642 reg &= ~MASTER_ITIMER_ENB; 1643 else 1644 reg |= MASTER_ITIMER_ENB; 1645 CSR_WRITE_4(sc, AGE_MASTER_CFG, reg); 1646 if (agedebug) 1647 printf("%s: interrupt moderation is %d us.\n", 1648 sc->sc_dev.dv_xname, sc->age_int_mod); 1649 CSR_WRITE_2(sc, AGE_INTR_CLR_TIMER, AGE_USECS(1000)); 1650 1651 /* Set Maximum frame size but don't let MTU be lass than ETHER_MTU. */ 1652 if (ifp->if_mtu < ETHERMTU) 1653 sc->age_max_frame_size = ETHERMTU; 1654 else 1655 sc->age_max_frame_size = ifp->if_mtu; 1656 sc->age_max_frame_size += ETHER_HDR_LEN + 1657 sizeof(struct ether_vlan_header) + ETHER_CRC_LEN; 1658 CSR_WRITE_4(sc, AGE_FRAME_SIZE, sc->age_max_frame_size); 1659 1660 /* Configure jumbo frame. */ 1661 fsize = roundup(sc->age_max_frame_size, sizeof(uint64_t)); 1662 CSR_WRITE_4(sc, AGE_RXQ_JUMBO_CFG, 1663 (((fsize / sizeof(uint64_t)) << 1664 RXQ_JUMBO_CFG_SZ_THRESH_SHIFT) & RXQ_JUMBO_CFG_SZ_THRESH_MASK) | 1665 ((RXQ_JUMBO_CFG_LKAH_DEFAULT << 1666 RXQ_JUMBO_CFG_LKAH_SHIFT) & RXQ_JUMBO_CFG_LKAH_MASK) | 1667 ((AGE_USECS(8) << RXQ_JUMBO_CFG_RRD_TIMER_SHIFT) & 1668 RXQ_JUMBO_CFG_RRD_TIMER_MASK)); 1669 1670 /* Configure flow-control parameters. From Linux. */ 1671 if ((sc->age_flags & AGE_FLAG_PCIE) != 0) { 1672 /* 1673 * Magic workaround for old-L1. 1674 * Don't know which hw revision requires this magic. 1675 */ 1676 CSR_WRITE_4(sc, 0x12FC, 0x6500); 1677 /* 1678 * Another magic workaround for flow-control mode 1679 * change. From Linux. 1680 */ 1681 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 1682 } 1683 /* 1684 * TODO 1685 * Should understand pause parameter relationships between FIFO 1686 * size and number of Rx descriptors and Rx return descriptors. 1687 * 1688 * Magic parameters came from Linux. 1689 */ 1690 switch (sc->age_chip_rev) { 1691 case 0x8001: 1692 case 0x9001: 1693 case 0x9002: 1694 case 0x9003: 1695 rxf_hi = AGE_RX_RING_CNT / 16; 1696 rxf_lo = (AGE_RX_RING_CNT * 7) / 8; 1697 rrd_hi = (AGE_RR_RING_CNT * 7) / 8; 1698 rrd_lo = AGE_RR_RING_CNT / 16; 1699 break; 1700 default: 1701 reg = CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN); 1702 rxf_lo = reg / 16; 1703 if (rxf_lo < 192) 1704 rxf_lo = 192; 1705 rxf_hi = (reg * 7) / 8; 1706 if (rxf_hi < rxf_lo) 1707 rxf_hi = rxf_lo + 16; 1708 reg = CSR_READ_4(sc, AGE_SRAM_RRD_LEN); 1709 rrd_lo = reg / 8; 1710 rrd_hi = (reg * 7) / 8; 1711 if (rrd_lo < 2) 1712 rrd_lo = 2; 1713 if (rrd_hi < rrd_lo) 1714 rrd_hi = rrd_lo + 3; 1715 break; 1716 } 1717 CSR_WRITE_4(sc, AGE_RXQ_FIFO_PAUSE_THRESH, 1718 ((rxf_lo << RXQ_FIFO_PAUSE_THRESH_LO_SHIFT) & 1719 RXQ_FIFO_PAUSE_THRESH_LO_MASK) | 1720 ((rxf_hi << RXQ_FIFO_PAUSE_THRESH_HI_SHIFT) & 1721 RXQ_FIFO_PAUSE_THRESH_HI_MASK)); 1722 CSR_WRITE_4(sc, AGE_RXQ_RRD_PAUSE_THRESH, 1723 ((rrd_lo << RXQ_RRD_PAUSE_THRESH_LO_SHIFT) & 1724 RXQ_RRD_PAUSE_THRESH_LO_MASK) | 1725 ((rrd_hi << RXQ_RRD_PAUSE_THRESH_HI_SHIFT) & 1726 RXQ_RRD_PAUSE_THRESH_HI_MASK)); 1727 1728 /* Configure RxQ. */ 1729 CSR_WRITE_4(sc, AGE_RXQ_CFG, 1730 ((RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 1731 RXQ_CFG_RD_BURST_MASK) | 1732 ((RXQ_CFG_RRD_BURST_THRESH_DEFAULT << 1733 RXQ_CFG_RRD_BURST_THRESH_SHIFT) & RXQ_CFG_RRD_BURST_THRESH_MASK) | 1734 ((RXQ_CFG_RD_PREF_MIN_IPG_DEFAULT << 1735 RXQ_CFG_RD_PREF_MIN_IPG_SHIFT) & RXQ_CFG_RD_PREF_MIN_IPG_MASK) | 1736 RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 1737 1738 /* Configure TxQ. */ 1739 CSR_WRITE_4(sc, AGE_TXQ_CFG, 1740 ((TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 1741 TXQ_CFG_TPD_BURST_MASK) | 1742 ((TXQ_CFG_TX_FIFO_BURST_DEFAULT << TXQ_CFG_TX_FIFO_BURST_SHIFT) & 1743 TXQ_CFG_TX_FIFO_BURST_MASK) | 1744 ((TXQ_CFG_TPD_FETCH_DEFAULT << 1745 TXQ_CFG_TPD_FETCH_THRESH_SHIFT) & TXQ_CFG_TPD_FETCH_THRESH_MASK) | 1746 TXQ_CFG_ENB); 1747 1748 /* Configure DMA parameters. */ 1749 CSR_WRITE_4(sc, AGE_DMA_CFG, 1750 DMA_CFG_ENH_ORDER | DMA_CFG_RCB_64 | 1751 sc->age_dma_rd_burst | DMA_CFG_RD_ENB | 1752 sc->age_dma_wr_burst | DMA_CFG_WR_ENB); 1753 1754 /* Configure CMB DMA write threshold. */ 1755 CSR_WRITE_4(sc, AGE_CMB_WR_THRESH, 1756 ((CMB_WR_THRESH_RRD_DEFAULT << CMB_WR_THRESH_RRD_SHIFT) & 1757 CMB_WR_THRESH_RRD_MASK) | 1758 ((CMB_WR_THRESH_TPD_DEFAULT << CMB_WR_THRESH_TPD_SHIFT) & 1759 CMB_WR_THRESH_TPD_MASK)); 1760 1761 /* Set CMB/SMB timer and enable them. */ 1762 CSR_WRITE_4(sc, AGE_CMB_WR_TIMER, 1763 ((AGE_USECS(2) << CMB_WR_TIMER_TX_SHIFT) & CMB_WR_TIMER_TX_MASK) | 1764 ((AGE_USECS(2) << CMB_WR_TIMER_RX_SHIFT) & CMB_WR_TIMER_RX_MASK)); 1765 1766 /* Request SMB updates for every seconds. */ 1767 CSR_WRITE_4(sc, AGE_SMB_TIMER, AGE_USECS(1000 * 1000)); 1768 CSR_WRITE_4(sc, AGE_CSMB_CTRL, CSMB_CTRL_SMB_ENB | CSMB_CTRL_CMB_ENB); 1769 1770 /* 1771 * Disable all WOL bits as WOL can interfere normal Rx 1772 * operation. 1773 */ 1774 CSR_WRITE_4(sc, AGE_WOL_CFG, 0); 1775 1776 /* 1777 * Configure Tx/Rx MACs. 1778 * - Auto-padding for short frames. 1779 * - Enable CRC generation. 1780 * Start with full-duplex/1000Mbps media. Actual reconfiguration 1781 * of MAC is followed after link establishment. 1782 */ 1783 CSR_WRITE_4(sc, AGE_MAC_CFG, 1784 MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | 1785 MAC_CFG_FULL_DUPLEX | MAC_CFG_SPEED_1000 | 1786 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 1787 MAC_CFG_PREAMBLE_MASK)); 1788 1789 /* Set up the receive filter. */ 1790 age_iff(sc); 1791 1792 age_rxvlan(sc); 1793 1794 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1795 reg |= MAC_CFG_RXCSUM_ENB; 1796 1797 /* Ack all pending interrupts and clear it. */ 1798 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); 1799 CSR_WRITE_4(sc, AGE_INTR_MASK, AGE_INTRS); 1800 1801 /* Finally enable Tx/Rx MAC. */ 1802 CSR_WRITE_4(sc, AGE_MAC_CFG, reg | MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 1803 1804 sc->age_flags &= ~AGE_FLAG_LINK; 1805 1806 /* Switch to the current media. */ 1807 mii_mediachg(mii); 1808 1809 timeout_add_sec(&sc->age_tick_ch, 1); 1810 1811 ifp->if_flags |= IFF_RUNNING; 1812 ifp->if_flags &= ~IFF_OACTIVE; 1813 1814 return (0); 1815 } 1816 1817 void 1818 age_stop(struct age_softc *sc) 1819 { 1820 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1821 struct age_txdesc *txd; 1822 struct age_rxdesc *rxd; 1823 uint32_t reg; 1824 int i; 1825 1826 /* 1827 * Mark the interface down and cancel the watchdog timer. 1828 */ 1829 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1830 ifp->if_timer = 0; 1831 1832 sc->age_flags &= ~AGE_FLAG_LINK; 1833 timeout_del(&sc->age_tick_ch); 1834 1835 /* 1836 * Disable interrupts. 1837 */ 1838 CSR_WRITE_4(sc, AGE_INTR_MASK, 0); 1839 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0xFFFFFFFF); 1840 1841 /* Stop CMB/SMB updates. */ 1842 CSR_WRITE_4(sc, AGE_CSMB_CTRL, 0); 1843 1844 /* Stop Rx/Tx MAC. */ 1845 age_stop_rxmac(sc); 1846 age_stop_txmac(sc); 1847 1848 /* Stop DMA. */ 1849 CSR_WRITE_4(sc, AGE_DMA_CFG, 1850 CSR_READ_4(sc, AGE_DMA_CFG) & ~(DMA_CFG_RD_ENB | DMA_CFG_WR_ENB)); 1851 1852 /* Stop TxQ/RxQ. */ 1853 CSR_WRITE_4(sc, AGE_TXQ_CFG, 1854 CSR_READ_4(sc, AGE_TXQ_CFG) & ~TXQ_CFG_ENB); 1855 CSR_WRITE_4(sc, AGE_RXQ_CFG, 1856 CSR_READ_4(sc, AGE_RXQ_CFG) & ~RXQ_CFG_ENB); 1857 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 1858 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 1859 break; 1860 DELAY(10); 1861 } 1862 if (i == 0) 1863 printf("%s: stopping Rx/Tx MACs timed out(0x%08x)!\n", 1864 sc->sc_dev.dv_xname, reg); 1865 1866 /* Reclaim Rx buffers that have been processed. */ 1867 if (sc->age_cdata.age_rxhead != NULL) 1868 m_freem(sc->age_cdata.age_rxhead); 1869 AGE_RXCHAIN_RESET(sc); 1870 1871 /* 1872 * Free RX and TX mbufs still in the queues. 1873 */ 1874 for (i = 0; i < AGE_RX_RING_CNT; i++) { 1875 rxd = &sc->age_cdata.age_rxdesc[i]; 1876 if (rxd->rx_m != NULL) { 1877 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0, 1878 rxd->rx_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1879 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 1880 m_freem(rxd->rx_m); 1881 rxd->rx_m = NULL; 1882 } 1883 } 1884 for (i = 0; i < AGE_TX_RING_CNT; i++) { 1885 txd = &sc->age_cdata.age_txdesc[i]; 1886 if (txd->tx_m != NULL) { 1887 bus_dmamap_sync(sc->sc_dmat, txd->tx_dmamap, 0, 1888 txd->tx_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1889 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1890 m_freem(txd->tx_m); 1891 txd->tx_m = NULL; 1892 } 1893 } 1894 } 1895 1896 void 1897 age_stats_update(struct age_softc *sc) 1898 { 1899 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1900 struct age_stats *stat; 1901 struct smb *smb; 1902 1903 stat = &sc->age_stat; 1904 1905 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 0, 1906 sc->age_cdata.age_smb_block_map->dm_mapsize, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1907 1908 smb = sc->age_rdata.age_smb_block; 1909 if (smb->updated == 0) 1910 return; 1911 1912 /* Rx stats. */ 1913 stat->rx_frames += smb->rx_frames; 1914 stat->rx_bcast_frames += smb->rx_bcast_frames; 1915 stat->rx_mcast_frames += smb->rx_mcast_frames; 1916 stat->rx_pause_frames += smb->rx_pause_frames; 1917 stat->rx_control_frames += smb->rx_control_frames; 1918 stat->rx_crcerrs += smb->rx_crcerrs; 1919 stat->rx_lenerrs += smb->rx_lenerrs; 1920 stat->rx_bytes += smb->rx_bytes; 1921 stat->rx_runts += smb->rx_runts; 1922 stat->rx_fragments += smb->rx_fragments; 1923 stat->rx_pkts_64 += smb->rx_pkts_64; 1924 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 1925 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 1926 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 1927 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 1928 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 1929 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 1930 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 1931 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 1932 stat->rx_desc_oflows += smb->rx_desc_oflows; 1933 stat->rx_alignerrs += smb->rx_alignerrs; 1934 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 1935 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 1936 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 1937 1938 /* Tx stats. */ 1939 stat->tx_frames += smb->tx_frames; 1940 stat->tx_bcast_frames += smb->tx_bcast_frames; 1941 stat->tx_mcast_frames += smb->tx_mcast_frames; 1942 stat->tx_pause_frames += smb->tx_pause_frames; 1943 stat->tx_excess_defer += smb->tx_excess_defer; 1944 stat->tx_control_frames += smb->tx_control_frames; 1945 stat->tx_deferred += smb->tx_deferred; 1946 stat->tx_bytes += smb->tx_bytes; 1947 stat->tx_pkts_64 += smb->tx_pkts_64; 1948 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 1949 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 1950 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 1951 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 1952 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 1953 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 1954 stat->tx_single_colls += smb->tx_single_colls; 1955 stat->tx_multi_colls += smb->tx_multi_colls; 1956 stat->tx_late_colls += smb->tx_late_colls; 1957 stat->tx_excess_colls += smb->tx_excess_colls; 1958 stat->tx_underrun += smb->tx_underrun; 1959 stat->tx_desc_underrun += smb->tx_desc_underrun; 1960 stat->tx_lenerrs += smb->tx_lenerrs; 1961 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 1962 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 1963 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 1964 1965 /* Update counters in ifnet. */ 1966 ifp->if_opackets += smb->tx_frames; 1967 1968 ifp->if_collisions += smb->tx_single_colls + 1969 smb->tx_multi_colls + smb->tx_late_colls + 1970 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT; 1971 1972 ifp->if_oerrors += smb->tx_excess_colls + 1973 smb->tx_late_colls + smb->tx_underrun + 1974 smb->tx_pkts_truncated; 1975 1976 ifp->if_ipackets += smb->rx_frames; 1977 1978 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 1979 smb->rx_runts + smb->rx_pkts_truncated + 1980 smb->rx_fifo_oflows + smb->rx_desc_oflows + 1981 smb->rx_alignerrs; 1982 1983 /* Update done, clear. */ 1984 smb->updated = 0; 1985 1986 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 0, 1987 sc->age_cdata.age_smb_block_map->dm_mapsize, 1988 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1989 } 1990 1991 void 1992 age_stop_txmac(struct age_softc *sc) 1993 { 1994 uint32_t reg; 1995 int i; 1996 1997 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1998 if ((reg & MAC_CFG_TX_ENB) != 0) { 1999 reg &= ~MAC_CFG_TX_ENB; 2000 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2001 } 2002 /* Stop Tx DMA engine. */ 2003 reg = CSR_READ_4(sc, AGE_DMA_CFG); 2004 if ((reg & DMA_CFG_RD_ENB) != 0) { 2005 reg &= ~DMA_CFG_RD_ENB; 2006 CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 2007 } 2008 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2009 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 2010 (IDLE_STATUS_TXMAC | IDLE_STATUS_DMARD)) == 0) 2011 break; 2012 DELAY(10); 2013 } 2014 if (i == 0) 2015 printf("%s: stopping TxMAC timeout!\n", sc->sc_dev.dv_xname); 2016 } 2017 2018 void 2019 age_stop_rxmac(struct age_softc *sc) 2020 { 2021 uint32_t reg; 2022 int i; 2023 2024 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2025 if ((reg & MAC_CFG_RX_ENB) != 0) { 2026 reg &= ~MAC_CFG_RX_ENB; 2027 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2028 } 2029 /* Stop Rx DMA engine. */ 2030 reg = CSR_READ_4(sc, AGE_DMA_CFG); 2031 if ((reg & DMA_CFG_WR_ENB) != 0) { 2032 reg &= ~DMA_CFG_WR_ENB; 2033 CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 2034 } 2035 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2036 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 2037 (IDLE_STATUS_RXMAC | IDLE_STATUS_DMAWR)) == 0) 2038 break; 2039 DELAY(10); 2040 } 2041 if (i == 0) 2042 printf("%s: stopping RxMAC timeout!\n", sc->sc_dev.dv_xname); 2043 } 2044 2045 void 2046 age_init_tx_ring(struct age_softc *sc) 2047 { 2048 struct age_ring_data *rd; 2049 struct age_txdesc *txd; 2050 int i; 2051 2052 sc->age_cdata.age_tx_prod = 0; 2053 sc->age_cdata.age_tx_cons = 0; 2054 sc->age_cdata.age_tx_cnt = 0; 2055 2056 rd = &sc->age_rdata; 2057 bzero(rd->age_tx_ring, AGE_TX_RING_SZ); 2058 for (i = 0; i < AGE_TX_RING_CNT; i++) { 2059 txd = &sc->age_cdata.age_txdesc[i]; 2060 txd->tx_desc = &rd->age_tx_ring[i]; 2061 txd->tx_m = NULL; 2062 } 2063 2064 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 0, 2065 sc->age_cdata.age_tx_ring_map->dm_mapsize, 2066 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2067 } 2068 2069 int 2070 age_init_rx_ring(struct age_softc *sc) 2071 { 2072 struct age_ring_data *rd; 2073 struct age_rxdesc *rxd; 2074 int i; 2075 2076 sc->age_cdata.age_rx_cons = AGE_RX_RING_CNT - 1; 2077 rd = &sc->age_rdata; 2078 bzero(rd->age_rx_ring, AGE_RX_RING_SZ); 2079 for (i = 0; i < AGE_RX_RING_CNT; i++) { 2080 rxd = &sc->age_cdata.age_rxdesc[i]; 2081 rxd->rx_m = NULL; 2082 rxd->rx_desc = &rd->age_rx_ring[i]; 2083 if (age_newbuf(sc, rxd) != 0) 2084 return (ENOBUFS); 2085 } 2086 2087 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rx_ring_map, 0, 2088 sc->age_cdata.age_rx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2089 2090 return (0); 2091 } 2092 2093 void 2094 age_init_rr_ring(struct age_softc *sc) 2095 { 2096 struct age_ring_data *rd; 2097 2098 sc->age_cdata.age_rr_cons = 0; 2099 AGE_RXCHAIN_RESET(sc); 2100 2101 rd = &sc->age_rdata; 2102 bzero(rd->age_rr_ring, AGE_RR_RING_SZ); 2103 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 0, 2104 sc->age_cdata.age_rr_ring_map->dm_mapsize, 2105 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2106 } 2107 2108 void 2109 age_init_cmb_block(struct age_softc *sc) 2110 { 2111 struct age_ring_data *rd; 2112 2113 rd = &sc->age_rdata; 2114 bzero(rd->age_cmb_block, AGE_CMB_BLOCK_SZ); 2115 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 2116 sc->age_cdata.age_cmb_block_map->dm_mapsize, 2117 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2118 } 2119 2120 void 2121 age_init_smb_block(struct age_softc *sc) 2122 { 2123 struct age_ring_data *rd; 2124 2125 rd = &sc->age_rdata; 2126 bzero(rd->age_smb_block, AGE_SMB_BLOCK_SZ); 2127 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 0, 2128 sc->age_cdata.age_smb_block_map->dm_mapsize, 2129 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2130 } 2131 2132 int 2133 age_newbuf(struct age_softc *sc, struct age_rxdesc *rxd) 2134 { 2135 struct rx_desc *desc; 2136 struct mbuf *m; 2137 bus_dmamap_t map; 2138 int error; 2139 2140 MGETHDR(m, M_DONTWAIT, MT_DATA); 2141 if (m == NULL) 2142 return (ENOBUFS); 2143 MCLGET(m, M_DONTWAIT); 2144 if (!(m->m_flags & M_EXT)) { 2145 m_freem(m); 2146 return (ENOBUFS); 2147 } 2148 2149 m->m_len = m->m_pkthdr.len = MCLBYTES; 2150 m_adj(m, ETHER_ALIGN); 2151 2152 error = bus_dmamap_load_mbuf(sc->sc_dmat, 2153 sc->age_cdata.age_rx_sparemap, m, BUS_DMA_NOWAIT); 2154 2155 if (error != 0) { 2156 m_freem(m); 2157 printf("%s: can't load RX mbuf\n", sc->sc_dev.dv_xname); 2158 return (error); 2159 } 2160 2161 if (rxd->rx_m != NULL) { 2162 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0, 2163 rxd->rx_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2164 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 2165 } 2166 map = rxd->rx_dmamap; 2167 rxd->rx_dmamap = sc->age_cdata.age_rx_sparemap; 2168 sc->age_cdata.age_rx_sparemap = map; 2169 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0, 2170 rxd->rx_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2171 rxd->rx_m = m; 2172 2173 desc = rxd->rx_desc; 2174 desc->addr = htole64(rxd->rx_dmamap->dm_segs[0].ds_addr); 2175 desc->len = 2176 htole32((rxd->rx_dmamap->dm_segs[0].ds_len & AGE_RD_LEN_MASK) << 2177 AGE_RD_LEN_SHIFT); 2178 2179 return (0); 2180 } 2181 2182 void 2183 age_rxvlan(struct age_softc *sc) 2184 { 2185 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 2186 uint32_t reg; 2187 2188 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2189 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 2190 if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) 2191 reg |= MAC_CFG_VLAN_TAG_STRIP; 2192 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2193 } 2194 2195 void 2196 age_iff(struct age_softc *sc) 2197 { 2198 struct arpcom *ac = &sc->sc_arpcom; 2199 struct ifnet *ifp = &ac->ac_if; 2200 struct ether_multi *enm; 2201 struct ether_multistep step; 2202 uint32_t crc; 2203 uint32_t mchash[2]; 2204 uint32_t rxcfg; 2205 2206 rxcfg = CSR_READ_4(sc, AGE_MAC_CFG); 2207 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 2208 ifp->if_flags &= ~IFF_ALLMULTI; 2209 2210 /* 2211 * Always accept broadcast frames. 2212 */ 2213 rxcfg |= MAC_CFG_BCAST; 2214 2215 if (ifp->if_flags & IFF_PROMISC || ac->ac_multirangecnt > 0) { 2216 ifp->if_flags |= IFF_ALLMULTI; 2217 if (ifp->if_flags & IFF_PROMISC) 2218 rxcfg |= MAC_CFG_PROMISC; 2219 else 2220 rxcfg |= MAC_CFG_ALLMULTI; 2221 mchash[0] = mchash[1] = 0xFFFFFFFF; 2222 } else { 2223 /* Program new filter. */ 2224 bzero(mchash, sizeof(mchash)); 2225 2226 ETHER_FIRST_MULTI(step, ac, enm); 2227 while (enm != NULL) { 2228 crc = ether_crc32_be(enm->enm_addrlo, 2229 ETHER_ADDR_LEN); 2230 2231 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 2232 2233 ETHER_NEXT_MULTI(step, enm); 2234 } 2235 } 2236 2237 CSR_WRITE_4(sc, AGE_MAR0, mchash[0]); 2238 CSR_WRITE_4(sc, AGE_MAR1, mchash[1]); 2239 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg); 2240 } 2241