1 /* $OpenBSD: if_age.c,v 1.4 2009/03/29 21:53:52 sthen Exp $ */ 2 3 /*- 4 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* Driver for Attansic Technology Corp. L1 Gigabit Ethernet. */ 31 32 #include "bpfilter.h" 33 #include "vlan.h" 34 35 #include <sys/param.h> 36 #include <sys/proc.h> 37 #include <sys/endian.h> 38 #include <sys/systm.h> 39 #include <sys/types.h> 40 #include <sys/sockio.h> 41 #include <sys/mbuf.h> 42 #include <sys/queue.h> 43 #include <sys/kernel.h> 44 #include <sys/device.h> 45 #include <sys/timeout.h> 46 #include <sys/socket.h> 47 48 #include <machine/bus.h> 49 50 #include <net/if.h> 51 #include <net/if_dl.h> 52 #include <net/if_media.h> 53 54 #ifdef INET 55 #include <netinet/in.h> 56 #include <netinet/in_systm.h> 57 #include <netinet/in_var.h> 58 #include <netinet/ip.h> 59 #include <netinet/if_ether.h> 60 #endif 61 62 #include <net/if_types.h> 63 #include <net/if_vlan_var.h> 64 65 #if NBPFILTER > 0 66 #include <net/bpf.h> 67 #endif 68 69 #include <dev/rndvar.h> 70 71 #include <dev/mii/mii.h> 72 #include <dev/mii/miivar.h> 73 74 #include <dev/pci/pcireg.h> 75 #include <dev/pci/pcivar.h> 76 #include <dev/pci/pcidevs.h> 77 78 #include <dev/pci/if_agereg.h> 79 80 int age_match(struct device *, void *, void *); 81 void age_attach(struct device *, struct device *, void *); 82 int age_detach(struct device *, int); 83 84 int age_miibus_readreg(struct device *, int, int); 85 void age_miibus_writereg(struct device *, int, int, int); 86 void age_miibus_statchg(struct device *); 87 88 int age_init(struct ifnet *); 89 int age_ioctl(struct ifnet *, u_long, caddr_t); 90 void age_start(struct ifnet *); 91 void age_watchdog(struct ifnet *); 92 void age_mediastatus(struct ifnet *, struct ifmediareq *); 93 int age_mediachange(struct ifnet *); 94 95 int age_intr(void *); 96 int age_read_vpd_word(struct age_softc *, uint32_t, uint32_t, uint32_t *); 97 int age_dma_alloc(struct age_softc *); 98 void age_dma_free(struct age_softc *); 99 void age_get_macaddr(struct age_softc *); 100 void age_phy_reset(struct age_softc *); 101 102 int age_encap(struct age_softc *, struct mbuf **); 103 void age_init_tx_ring(struct age_softc *); 104 int age_init_rx_ring(struct age_softc *); 105 void age_init_rr_ring(struct age_softc *); 106 void age_init_cmb_block(struct age_softc *); 107 void age_init_smb_block(struct age_softc *); 108 int age_newbuf(struct age_softc *, struct age_rxdesc *, int); 109 void age_mac_config(struct age_softc *); 110 void age_txintr(struct age_softc *, int); 111 void age_rxeof(struct age_softc *sc, struct rx_rdesc *); 112 void age_rxintr(struct age_softc *, int); 113 void age_tick(void *); 114 void age_reset(struct age_softc *); 115 void age_stop(struct age_softc *); 116 void age_stats_update(struct age_softc *); 117 void age_stop_txmac(struct age_softc *); 118 void age_stop_rxmac(struct age_softc *); 119 void age_rxvlan(struct age_softc *sc); 120 void age_rxfilter(struct age_softc *); 121 122 const struct pci_matchid age_devices[] = { 123 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L1 } 124 }; 125 126 struct cfattach age_ca = { 127 sizeof (struct age_softc), age_match, age_attach 128 }; 129 130 struct cfdriver age_cd = { 131 NULL, "age", DV_IFNET 132 }; 133 134 int agedebug = 0; 135 #define DPRINTF(x) do { if (agedebug) printf x; } while (0) 136 137 #define AGE_CSUM_FEATURES (M_TCPV4_CSUM_OUT | M_UDPV4_CSUM_OUT) 138 139 int 140 age_match(struct device *dev, void *match, void *aux) 141 { 142 return pci_matchbyid((struct pci_attach_args *)aux, age_devices, 143 sizeof (age_devices) / sizeof (age_devices[0])); 144 } 145 146 void 147 age_attach(struct device *parent, struct device *self, void *aux) 148 { 149 struct age_softc *sc = (struct age_softc *)self; 150 struct pci_attach_args *pa = aux; 151 pci_chipset_tag_t pc = pa->pa_pc; 152 pci_intr_handle_t ih; 153 const char *intrstr; 154 struct ifnet *ifp; 155 pcireg_t memtype; 156 int error = 0; 157 158 /* 159 * Allocate IO memory 160 */ 161 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, AGE_PCIR_BAR); 162 if (pci_mapreg_map(pa, AGE_PCIR_BAR, memtype, 0, &sc->sc_mem_bt, 163 &sc->sc_mem_bh, NULL, &sc->sc_mem_size, 0)) { 164 printf(": can't map mem space\n"); 165 return; 166 } 167 168 if (pci_intr_map(pa, &ih) != 0) { 169 printf(": can't map interrupt\n"); 170 goto fail; 171 } 172 173 /* 174 * Allocate IRQ 175 */ 176 intrstr = pci_intr_string(pc, ih); 177 sc->sc_irq_handle = pci_intr_establish(pc, ih, IPL_NET, age_intr, sc, 178 sc->sc_dev.dv_xname); 179 if (sc->sc_irq_handle == NULL) { 180 printf(": could not establish interrupt"); 181 if (intrstr != NULL) 182 printf(" at %s", intrstr); 183 printf("\n"); 184 goto fail; 185 } 186 printf(": %s", intrstr); 187 188 sc->sc_dmat = pa->pa_dmat; 189 sc->sc_pct = pa->pa_pc; 190 sc->sc_pcitag = pa->pa_tag; 191 192 /* Set PHY address. */ 193 sc->age_phyaddr = AGE_PHY_ADDR; 194 195 /* Reset PHY. */ 196 age_phy_reset(sc); 197 198 /* Reset the ethernet controller. */ 199 age_reset(sc); 200 201 /* Get PCI and chip id/revision. */ 202 sc->age_rev = PCI_REVISION(pa->pa_class); 203 sc->age_chip_rev = CSR_READ_4(sc, AGE_MASTER_CFG) >> 204 MASTER_CHIP_REV_SHIFT; 205 if (agedebug) { 206 printf("%s: PCI device revision : 0x%04x\n", 207 sc->sc_dev.dv_xname, sc->age_rev); 208 printf("%s: Chip id/revision : 0x%04x\n", 209 sc->sc_dev.dv_xname, sc->age_chip_rev); 210 } 211 212 if (agedebug) { 213 printf("%s: %d Tx FIFO, %d Rx FIFO\n", sc->sc_dev.dv_xname, 214 CSR_READ_4(sc, AGE_SRAM_TX_FIFO_LEN), 215 CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN)); 216 } 217 218 /* Set max allowable DMA size. */ 219 sc->age_dma_rd_burst = DMA_CFG_RD_BURST_128; 220 sc->age_dma_wr_burst = DMA_CFG_WR_BURST_128; 221 222 /* Allocate DMA stuffs */ 223 error = age_dma_alloc(sc); 224 if (error) 225 goto fail; 226 227 /* Load station address. */ 228 age_get_macaddr(sc); 229 230 ifp = &sc->sc_arpcom.ac_if; 231 ifp->if_softc = sc; 232 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 233 ifp->if_init = age_init; 234 ifp->if_ioctl = age_ioctl; 235 ifp->if_start = age_start; 236 ifp->if_watchdog = age_watchdog; 237 ifp->if_baudrate = IF_Gbps(1); 238 IFQ_SET_MAXLEN(&ifp->if_snd, AGE_TX_RING_CNT - 1); 239 IFQ_SET_READY(&ifp->if_snd); 240 bcopy(sc->age_eaddr, sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN); 241 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 242 243 ifp->if_capabilities = IFCAP_VLAN_MTU; 244 245 #ifdef AGE_CHECKSUM 246 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 247 IFCAP_CSUM_UDPv4; 248 #endif 249 250 #if NVLAN > 0 251 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 252 #endif 253 254 printf(", address %s\n", ether_sprintf(sc->sc_arpcom.ac_enaddr)); 255 256 /* Set up MII bus. */ 257 sc->sc_miibus.mii_ifp = ifp; 258 sc->sc_miibus.mii_readreg = age_miibus_readreg; 259 sc->sc_miibus.mii_writereg = age_miibus_writereg; 260 sc->sc_miibus.mii_statchg = age_miibus_statchg; 261 262 ifmedia_init(&sc->sc_miibus.mii_media, 0, age_mediachange, 263 age_mediastatus); 264 mii_attach(self, &sc->sc_miibus, 0xffffffff, MII_PHY_ANY, 265 MII_OFFSET_ANY, 0); 266 267 if (LIST_FIRST(&sc->sc_miibus.mii_phys) == NULL) { 268 printf("%s: no PHY found!\n", sc->sc_dev.dv_xname); 269 ifmedia_add(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL, 270 0, NULL); 271 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL); 272 } else 273 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_AUTO); 274 275 if_attach(ifp); 276 ether_ifattach(ifp); 277 278 timeout_set(&sc->age_tick_ch, age_tick, sc); 279 280 return; 281 fail: 282 age_dma_free(sc); 283 if (sc->sc_irq_handle != NULL) 284 pci_intr_disestablish(pc, sc->sc_irq_handle); 285 if (sc->sc_mem_size) 286 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 287 } 288 289 int 290 age_detach(struct device *self, int flags) 291 { 292 struct age_softc *sc = (struct age_softc *)self; 293 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 294 int s; 295 296 s = splnet(); 297 age_stop(sc); 298 splx(s); 299 300 mii_detach(&sc->sc_miibus, MII_PHY_ANY, MII_OFFSET_ANY); 301 302 /* Delete all remaining media. */ 303 ifmedia_delete_instance(&sc->sc_miibus.mii_media, IFM_INST_ANY); 304 305 ether_ifdetach(ifp); 306 if_detach(ifp); 307 age_dma_free(sc); 308 309 if (sc->sc_irq_handle != NULL) { 310 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 311 sc->sc_irq_handle = NULL; 312 } 313 314 return (0); 315 } 316 317 /* 318 * Read a PHY register on the MII of the L1. 319 */ 320 int 321 age_miibus_readreg(struct device *dev, int phy, int reg) 322 { 323 struct age_softc *sc = (struct age_softc *)dev; 324 uint32_t v; 325 int i; 326 327 if (phy != sc->age_phyaddr) 328 return (0); 329 330 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 331 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 332 for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 333 DELAY(1); 334 v = CSR_READ_4(sc, AGE_MDIO); 335 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 336 break; 337 } 338 339 if (i == 0) { 340 printf("%s: phy read timeout: phy %d, reg %d\n", 341 sc->sc_dev.dv_xname, phy, reg); 342 return (0); 343 } 344 345 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 346 } 347 348 /* 349 * Write a PHY register on the MII of the L1. 350 */ 351 void 352 age_miibus_writereg(struct device *dev, int phy, int reg, int val) 353 { 354 struct age_softc *sc = (struct age_softc *)dev; 355 uint32_t v; 356 int i; 357 358 if (phy != sc->age_phyaddr) 359 return; 360 361 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 362 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 363 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 364 365 for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 366 DELAY(1); 367 v = CSR_READ_4(sc, AGE_MDIO); 368 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 369 break; 370 } 371 372 if (i == 0) { 373 printf("%s: phy write timeout: phy %d, reg %d\n", 374 sc->sc_dev.dv_xname, phy, reg); 375 } 376 } 377 378 /* 379 * Callback from MII layer when media changes. 380 */ 381 void 382 age_miibus_statchg(struct device *dev) 383 { 384 struct age_softc *sc = (struct age_softc *)dev; 385 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 386 struct mii_data *mii; 387 388 if ((ifp->if_flags & IFF_RUNNING) == 0) 389 return; 390 391 mii = &sc->sc_miibus; 392 393 sc->age_flags &= ~AGE_FLAG_LINK; 394 if ((mii->mii_media_status & IFM_AVALID) != 0) { 395 switch (IFM_SUBTYPE(mii->mii_media_active)) { 396 case IFM_10_T: 397 case IFM_100_TX: 398 case IFM_1000_T: 399 sc->age_flags |= AGE_FLAG_LINK; 400 break; 401 default: 402 break; 403 } 404 } 405 406 /* Stop Rx/Tx MACs. */ 407 age_stop_rxmac(sc); 408 age_stop_txmac(sc); 409 410 /* Program MACs with resolved speed/duplex/flow-control. */ 411 if ((sc->age_flags & AGE_FLAG_LINK) != 0) { 412 uint32_t reg; 413 414 age_mac_config(sc); 415 reg = CSR_READ_4(sc, AGE_MAC_CFG); 416 /* Restart DMA engine and Tx/Rx MAC. */ 417 CSR_WRITE_4(sc, AGE_DMA_CFG, CSR_READ_4(sc, AGE_DMA_CFG) | 418 DMA_CFG_RD_ENB | DMA_CFG_WR_ENB); 419 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 420 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 421 } 422 } 423 424 /* 425 * Get the current interface media status. 426 */ 427 void 428 age_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 429 { 430 struct age_softc *sc = ifp->if_softc; 431 struct mii_data *mii = &sc->sc_miibus; 432 433 mii_pollstat(mii); 434 ifmr->ifm_status = mii->mii_media_status; 435 ifmr->ifm_active = mii->mii_media_active; 436 } 437 438 /* 439 * Set hardware to newly-selected media. 440 */ 441 int 442 age_mediachange(struct ifnet *ifp) 443 { 444 struct age_softc *sc = ifp->if_softc; 445 struct mii_data *mii = &sc->sc_miibus; 446 int error; 447 448 if (mii->mii_instance != 0) { 449 struct mii_softc *miisc; 450 451 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 452 mii_phy_reset(miisc); 453 } 454 error = mii_mediachg(mii); 455 456 return (error); 457 } 458 459 int 460 age_intr(void *arg) 461 { 462 struct age_softc *sc = arg; 463 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 464 struct cmb *cmb; 465 uint32_t status; 466 467 status = CSR_READ_4(sc, AGE_INTR_STATUS); 468 if (status == 0 || (status & AGE_INTRS) == 0) 469 return (0); 470 471 /* Disable interrupts. */ 472 CSR_WRITE_4(sc, AGE_INTR_STATUS, status | INTR_DIS_INT); 473 474 cmb = sc->age_rdata.age_cmb_block; 475 476 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 477 sc->age_cdata.age_cmb_block_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 478 status = letoh32(cmb->intr_status); 479 if ((status & AGE_INTRS) == 0) 480 goto back; 481 482 sc->age_tpd_cons = (letoh32(cmb->tpd_cons) & TPD_CONS_MASK) >> 483 TPD_CONS_SHIFT; 484 sc->age_rr_prod = (letoh32(cmb->rprod_cons) & RRD_PROD_MASK) >> 485 RRD_PROD_SHIFT; 486 487 /* Let hardware know CMB was served. */ 488 cmb->intr_status = 0; 489 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 490 sc->age_cdata.age_cmb_block_map->dm_mapsize, 491 BUS_DMASYNC_PREWRITE); 492 493 if (ifp->if_flags & IFF_RUNNING) { 494 if (status & INTR_CMB_RX) 495 age_rxintr(sc, sc->age_rr_prod); 496 497 if (status & INTR_CMB_TX) 498 age_txintr(sc, sc->age_tpd_cons); 499 500 if (status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) { 501 if (status & INTR_DMA_RD_TO_RST) 502 printf("%s: DMA read error! -- resetting\n", 503 sc->sc_dev.dv_xname); 504 if (status & INTR_DMA_WR_TO_RST) 505 printf("%s: DMA write error! -- resetting\n", 506 sc->sc_dev.dv_xname); 507 age_init(ifp); 508 } 509 510 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 511 age_start(ifp); 512 513 if (status & INTR_SMB) 514 age_stats_update(sc); 515 } 516 517 /* Check whether CMB was updated while serving Tx/Rx/SMB handler. */ 518 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 519 sc->age_cdata.age_cmb_block_map->dm_mapsize, 520 BUS_DMASYNC_POSTREAD); 521 522 back: 523 /* Re-enable interrupts. */ 524 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); 525 526 return (1); 527 } 528 529 int 530 age_read_vpd_word(struct age_softc *sc, uint32_t vpdc, uint32_t offset, 531 uint32_t *word) 532 { 533 int i; 534 pcireg_t rv; 535 536 pci_conf_write(sc->sc_pct, sc->sc_pcitag, PCI_VPD_ADDRESS(vpdc), 537 offset << PCI_VPD_ADDRESS_SHIFT); 538 539 for (i = AGE_TIMEOUT; i > 0; i--) { 540 DELAY(10); 541 rv = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 542 PCI_VPD_ADDRESS(vpdc)); 543 if ((rv & PCI_VPD_OPFLAG) == PCI_VPD_OPFLAG) 544 break; 545 } 546 if (i == 0) { 547 printf("%s: VPD read timeout!\n", sc->sc_dev.dv_xname); 548 *word = 0; 549 return (ETIMEDOUT); 550 } 551 552 *word = pci_conf_read(sc->sc_pct, sc->sc_pcitag, PCI_VPD_DATAREG(vpdc)); 553 return (0); 554 } 555 556 void 557 age_get_macaddr(struct age_softc *sc) 558 { 559 uint32_t ea[2], off, reg, word; 560 int vpd_error, match, vpdc; 561 562 reg = CSR_READ_4(sc, AGE_SPI_CTRL); 563 if ((reg & SPI_VPD_ENB) != 0) { 564 /* Get VPD stored in TWSI EEPROM. */ 565 reg &= ~SPI_VPD_ENB; 566 CSR_WRITE_4(sc, AGE_SPI_CTRL, reg); 567 } 568 569 vpd_error = 0; 570 ea[0] = ea[1] = 0; 571 if ((vpd_error = pci_get_capability(sc->sc_pct, sc->sc_pcitag, 572 PCI_CAP_VPD, &vpdc, NULL))) { 573 /* 574 * PCI VPD capability exists, but it seems that it's 575 * not in the standard form as stated in PCI VPD 576 * specification such that driver could not use 577 * pci_get_vpd_readonly(9) with keyword 'NA'. 578 * Search VPD data starting at address 0x0100. The data 579 * should be used as initializers to set AGE_PAR0, 580 * AGE_PAR1 register including other PCI configuration 581 * registers. 582 */ 583 word = 0; 584 match = 0; 585 reg = 0; 586 for (off = AGE_VPD_REG_CONF_START; off < AGE_VPD_REG_CONF_END; 587 off += sizeof(uint32_t)) { 588 vpd_error = age_read_vpd_word(sc, vpdc, off, &word); 589 if (vpd_error != 0) 590 break; 591 if (match != 0) { 592 switch (reg) { 593 case AGE_PAR0: 594 ea[0] = word; 595 break; 596 case AGE_PAR1: 597 ea[1] = word; 598 break; 599 default: 600 break; 601 } 602 match = 0; 603 } else if ((word & 0xFF) == AGE_VPD_REG_CONF_SIG) { 604 match = 1; 605 reg = word >> 16; 606 } else 607 break; 608 } 609 if (off >= AGE_VPD_REG_CONF_END) 610 vpd_error = ENOENT; 611 if (vpd_error == 0) { 612 /* 613 * Don't blindly trust ethernet address obtained 614 * from VPD. Check whether ethernet address is 615 * valid one. Otherwise fall-back to reading 616 * PAR register. 617 */ 618 ea[1] &= 0xFFFF; 619 if ((ea[0] == 0 && ea[1] == 0) || 620 (ea[0] == 0xFFFFFFFF && ea[1] == 0xFFFF)) { 621 if (agedebug) 622 printf("%s: invalid ethernet address " 623 "returned from VPD.\n", 624 sc->sc_dev.dv_xname); 625 vpd_error = EINVAL; 626 } 627 } 628 if (vpd_error != 0 && (agedebug)) 629 printf("%s: VPD access failure!\n", 630 sc->sc_dev.dv_xname); 631 } else { 632 if (agedebug) 633 printf("%s: PCI VPD capability not found!\n", 634 sc->sc_dev.dv_xname); 635 } 636 637 /* 638 * It seems that L1 also provides a way to extract ethernet 639 * address via SPI flash interface. Because SPI flash memory 640 * device of different vendors vary in their instruction 641 * codes for read ID instruction, it's very hard to get 642 * instructions codes without detailed information for the 643 * flash memory device used on ethernet controller. To simplify 644 * code, just read AGE_PAR0/AGE_PAR1 register to get ethernet 645 * address which is supposed to be set by hardware during 646 * power on reset. 647 */ 648 if (vpd_error != 0) { 649 /* 650 * VPD is mapped to SPI flash memory or BIOS set it. 651 */ 652 ea[0] = CSR_READ_4(sc, AGE_PAR0); 653 ea[1] = CSR_READ_4(sc, AGE_PAR1); 654 } 655 656 ea[1] &= 0xFFFF; 657 sc->age_eaddr[0] = (ea[1] >> 8) & 0xFF; 658 sc->age_eaddr[1] = (ea[1] >> 0) & 0xFF; 659 sc->age_eaddr[2] = (ea[0] >> 24) & 0xFF; 660 sc->age_eaddr[3] = (ea[0] >> 16) & 0xFF; 661 sc->age_eaddr[4] = (ea[0] >> 8) & 0xFF; 662 sc->age_eaddr[5] = (ea[0] >> 0) & 0xFF; 663 } 664 665 void 666 age_phy_reset(struct age_softc *sc) 667 { 668 /* Reset PHY. */ 669 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_RST); 670 DELAY(1000); 671 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_CLR); 672 DELAY(1000); 673 } 674 675 int 676 age_dma_alloc(struct age_softc *sc) 677 { 678 struct age_txdesc *txd; 679 struct age_rxdesc *rxd; 680 int nsegs, error, i; 681 682 /* 683 * Create DMA stuffs for TX ring 684 */ 685 error = bus_dmamap_create(sc->sc_dmat, AGE_TX_RING_SZ, 1, 686 AGE_TX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->age_cdata.age_tx_ring_map); 687 if (error) 688 return (ENOBUFS); 689 690 /* Allocate DMA'able memory for TX ring */ 691 error = bus_dmamem_alloc(sc->sc_dmat, AGE_TX_RING_SZ, 692 ETHER_ALIGN, 0, &sc->age_rdata.age_tx_ring_seg, 1, 693 &nsegs, BUS_DMA_WAITOK); 694 if (error) { 695 printf("%s: could not allocate DMA'able memory for Tx ring.\n", 696 sc->sc_dev.dv_xname); 697 return error; 698 } 699 700 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_tx_ring_seg, 701 nsegs, AGE_TX_RING_SZ, (caddr_t *)&sc->age_rdata.age_tx_ring, 702 BUS_DMA_NOWAIT); 703 if (error) 704 return (ENOBUFS); 705 706 bzero(sc->age_rdata.age_tx_ring, AGE_TX_RING_SZ); 707 708 /* Load the DMA map for Tx ring. */ 709 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 710 sc->age_rdata.age_tx_ring, AGE_TX_RING_SZ, NULL, BUS_DMA_WAITOK); 711 if (error) { 712 printf("%s: could not load DMA'able memory for Tx ring.\n", 713 sc->sc_dev.dv_xname); 714 bus_dmamem_free(sc->sc_dmat, 715 (bus_dma_segment_t *)&sc->age_rdata.age_tx_ring, 1); 716 return error; 717 } 718 719 sc->age_rdata.age_tx_ring_paddr = 720 sc->age_cdata.age_tx_ring_map->dm_segs[0].ds_addr; 721 722 /* 723 * Create DMA stuffs for RX ring 724 */ 725 error = bus_dmamap_create(sc->sc_dmat, AGE_RX_RING_SZ, 1, 726 AGE_RX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->age_cdata.age_rx_ring_map); 727 if (error) 728 return (ENOBUFS); 729 730 /* Allocate DMA'able memory for RX ring */ 731 error = bus_dmamem_alloc(sc->sc_dmat, AGE_RX_RING_SZ, 732 ETHER_ALIGN, 0, &sc->age_rdata.age_rx_ring_seg, 1, 733 &nsegs, BUS_DMA_WAITOK); 734 if (error) { 735 printf("%s: could not allocate DMA'able memory for Rx ring.\n", 736 sc->sc_dev.dv_xname); 737 return error; 738 } 739 740 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_rx_ring_seg, 741 nsegs, AGE_RX_RING_SZ, (caddr_t *)&sc->age_rdata.age_rx_ring, 742 BUS_DMA_NOWAIT); 743 if (error) 744 return (ENOBUFS); 745 746 bzero(sc->age_rdata.age_rx_ring, AGE_RX_RING_SZ); 747 748 /* Load the DMA map for Rx ring. */ 749 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_rx_ring_map, 750 sc->age_rdata.age_rx_ring, AGE_RX_RING_SZ, NULL, BUS_DMA_WAITOK); 751 if (error) { 752 printf("%s: could not load DMA'able memory for Rx ring.\n", 753 sc->sc_dev.dv_xname); 754 bus_dmamem_free(sc->sc_dmat, 755 (bus_dma_segment_t *)sc->age_rdata.age_rx_ring, 1); 756 return error; 757 } 758 759 sc->age_rdata.age_rx_ring_paddr = 760 sc->age_cdata.age_rx_ring_map->dm_segs[0].ds_addr; 761 762 /* 763 * Create DMA stuffs for RX return ring 764 */ 765 error = bus_dmamap_create(sc->sc_dmat, AGE_RR_RING_SZ, 1, 766 AGE_RR_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->age_cdata.age_rr_ring_map); 767 if (error) 768 return (ENOBUFS); 769 770 /* Allocate DMA'able memory for RX return ring */ 771 error = bus_dmamem_alloc(sc->sc_dmat, AGE_RR_RING_SZ, 772 ETHER_ALIGN, 0, &sc->age_rdata.age_rr_ring_seg, 1, 773 &nsegs, BUS_DMA_WAITOK); 774 if (error) { 775 printf("%s: could not allocate DMA'able memory for Rx " 776 "return ring.\n", sc->sc_dev.dv_xname); 777 return error; 778 } 779 780 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_rr_ring_seg, 781 nsegs, AGE_RR_RING_SZ, (caddr_t *)&sc->age_rdata.age_rr_ring, 782 BUS_DMA_NOWAIT); 783 if (error) 784 return (ENOBUFS); 785 786 bzero(sc->age_rdata.age_rr_ring, AGE_RR_RING_SZ); 787 788 /* Load the DMA map for Rx return ring. */ 789 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 790 sc->age_rdata.age_rr_ring, AGE_RR_RING_SZ, NULL, BUS_DMA_WAITOK); 791 if (error) { 792 printf("%s: could not load DMA'able memory for Rx return ring." 793 "\n", sc->sc_dev.dv_xname); 794 bus_dmamem_free(sc->sc_dmat, 795 (bus_dma_segment_t *)&sc->age_rdata.age_rr_ring, 1); 796 return error; 797 } 798 799 sc->age_rdata.age_rr_ring_paddr = 800 sc->age_cdata.age_rr_ring_map->dm_segs[0].ds_addr; 801 802 /* 803 * Create DMA stuffs for CMB block 804 */ 805 error = bus_dmamap_create(sc->sc_dmat, AGE_CMB_BLOCK_SZ, 1, 806 AGE_CMB_BLOCK_SZ, 0, BUS_DMA_NOWAIT, 807 &sc->age_cdata.age_cmb_block_map); 808 if (error) 809 return (ENOBUFS); 810 811 /* Allocate DMA'able memory for CMB block */ 812 error = bus_dmamem_alloc(sc->sc_dmat, AGE_CMB_BLOCK_SZ, 813 ETHER_ALIGN, 0, &sc->age_rdata.age_cmb_block_seg, 1, 814 &nsegs, BUS_DMA_WAITOK); 815 if (error) { 816 printf("%s: could not allocate DMA'able memory for " 817 "CMB block\n", sc->sc_dev.dv_xname); 818 return error; 819 } 820 821 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_cmb_block_seg, 822 nsegs, AGE_CMB_BLOCK_SZ, (caddr_t *)&sc->age_rdata.age_cmb_block, 823 BUS_DMA_NOWAIT); 824 if (error) 825 return (ENOBUFS); 826 827 bzero(sc->age_rdata.age_cmb_block, AGE_CMB_BLOCK_SZ); 828 829 /* Load the DMA map for CMB block. */ 830 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 831 sc->age_rdata.age_cmb_block, AGE_CMB_BLOCK_SZ, NULL, 832 BUS_DMA_WAITOK); 833 if (error) { 834 printf("%s: could not load DMA'able memory for CMB block\n", 835 sc->sc_dev.dv_xname); 836 bus_dmamem_free(sc->sc_dmat, 837 (bus_dma_segment_t *)&sc->age_rdata.age_cmb_block, 1); 838 return error; 839 } 840 841 sc->age_rdata.age_cmb_block_paddr = 842 sc->age_cdata.age_cmb_block_map->dm_segs[0].ds_addr; 843 844 /* 845 * Create DMA stuffs for SMB block 846 */ 847 error = bus_dmamap_create(sc->sc_dmat, AGE_SMB_BLOCK_SZ, 1, 848 AGE_SMB_BLOCK_SZ, 0, BUS_DMA_NOWAIT, 849 &sc->age_cdata.age_smb_block_map); 850 if (error) 851 return (ENOBUFS); 852 853 /* Allocate DMA'able memory for SMB block */ 854 error = bus_dmamem_alloc(sc->sc_dmat, AGE_SMB_BLOCK_SZ, 855 ETHER_ALIGN, 0, &sc->age_rdata.age_smb_block_seg, 1, 856 &nsegs, BUS_DMA_WAITOK); 857 if (error) { 858 printf("%s: could not allocate DMA'able memory for " 859 "SMB block\n", sc->sc_dev.dv_xname); 860 return error; 861 } 862 863 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_smb_block_seg, 864 nsegs, AGE_SMB_BLOCK_SZ, (caddr_t *)&sc->age_rdata.age_smb_block, 865 BUS_DMA_NOWAIT); 866 if (error) 867 return (ENOBUFS); 868 869 bzero(sc->age_rdata.age_smb_block, AGE_SMB_BLOCK_SZ); 870 871 /* Load the DMA map for SMB block */ 872 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 873 sc->age_rdata.age_smb_block, AGE_SMB_BLOCK_SZ, NULL, 874 BUS_DMA_WAITOK); 875 if (error) { 876 printf("%s: could not load DMA'able memory for SMB block\n", 877 sc->sc_dev.dv_xname); 878 bus_dmamem_free(sc->sc_dmat, 879 (bus_dma_segment_t *)&sc->age_rdata.age_smb_block, 1); 880 return error; 881 } 882 883 sc->age_rdata.age_smb_block_paddr = 884 sc->age_cdata.age_smb_block_map->dm_segs[0].ds_addr; 885 886 /* Create DMA maps for Tx buffers. */ 887 for (i = 0; i < AGE_TX_RING_CNT; i++) { 888 txd = &sc->age_cdata.age_txdesc[i]; 889 txd->tx_m = NULL; 890 txd->tx_dmamap = NULL; 891 error = bus_dmamap_create(sc->sc_dmat, AGE_TSO_MAXSIZE, 892 AGE_MAXTXSEGS, AGE_TSO_MAXSEGSIZE, 0, BUS_DMA_NOWAIT, 893 &txd->tx_dmamap); 894 if (error) { 895 printf("%s: could not create Tx dmamap.\n", 896 sc->sc_dev.dv_xname); 897 return error; 898 } 899 } 900 901 /* Create DMA maps for Rx buffers. */ 902 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 903 BUS_DMA_NOWAIT, &sc->age_cdata.age_rx_sparemap); 904 if (error) { 905 printf("%s: could not create spare Rx dmamap.\n", 906 sc->sc_dev.dv_xname); 907 return error; 908 } 909 for (i = 0; i < AGE_RX_RING_CNT; i++) { 910 rxd = &sc->age_cdata.age_rxdesc[i]; 911 rxd->rx_m = NULL; 912 rxd->rx_dmamap = NULL; 913 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 914 MCLBYTES, 0, BUS_DMA_NOWAIT, &rxd->rx_dmamap); 915 if (error) { 916 printf("%s: could not create Rx dmamap.\n", 917 sc->sc_dev.dv_xname); 918 return error; 919 } 920 } 921 922 return (0); 923 } 924 925 void 926 age_dma_free(struct age_softc *sc) 927 { 928 struct age_txdesc *txd; 929 struct age_rxdesc *rxd; 930 int i; 931 932 /* Tx buffers */ 933 for (i = 0; i < AGE_TX_RING_CNT; i++) { 934 txd = &sc->age_cdata.age_txdesc[i]; 935 if (txd->tx_dmamap != NULL) { 936 bus_dmamap_destroy(sc->sc_dmat, txd->tx_dmamap); 937 txd->tx_dmamap = NULL; 938 } 939 } 940 /* Rx buffers */ 941 for (i = 0; i < AGE_RX_RING_CNT; i++) { 942 rxd = &sc->age_cdata.age_rxdesc[i]; 943 if (rxd->rx_dmamap != NULL) { 944 bus_dmamap_destroy(sc->sc_dmat, rxd->rx_dmamap); 945 rxd->rx_dmamap = NULL; 946 } 947 } 948 if (sc->age_cdata.age_rx_sparemap != NULL) { 949 bus_dmamap_destroy(sc->sc_dmat, sc->age_cdata.age_rx_sparemap); 950 sc->age_cdata.age_rx_sparemap = NULL; 951 } 952 953 /* Tx ring. */ 954 if (sc->age_cdata.age_tx_ring_map != NULL) 955 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_tx_ring_map); 956 if (sc->age_cdata.age_tx_ring_map != NULL && 957 sc->age_rdata.age_tx_ring != NULL) 958 bus_dmamem_free(sc->sc_dmat, 959 (bus_dma_segment_t *)sc->age_rdata.age_tx_ring, 1); 960 sc->age_rdata.age_tx_ring = NULL; 961 sc->age_cdata.age_tx_ring_map = NULL; 962 963 /* Rx ring. */ 964 if (sc->age_cdata.age_rx_ring_map != NULL) 965 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_rx_ring_map); 966 if (sc->age_cdata.age_rx_ring_map != NULL && 967 sc->age_rdata.age_rx_ring != NULL) 968 bus_dmamem_free(sc->sc_dmat, 969 (bus_dma_segment_t *)sc->age_rdata.age_rx_ring, 1); 970 sc->age_rdata.age_rx_ring = NULL; 971 sc->age_cdata.age_rx_ring_map = NULL; 972 973 /* Rx return ring. */ 974 if (sc->age_cdata.age_rr_ring_map != NULL) 975 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_rr_ring_map); 976 if (sc->age_cdata.age_rr_ring_map != NULL && 977 sc->age_rdata.age_rr_ring != NULL) 978 bus_dmamem_free(sc->sc_dmat, 979 (bus_dma_segment_t *)sc->age_rdata.age_rr_ring, 1); 980 sc->age_rdata.age_rr_ring = NULL; 981 sc->age_cdata.age_rr_ring_map = NULL; 982 983 /* CMB block */ 984 if (sc->age_cdata.age_cmb_block_map != NULL) 985 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_cmb_block_map); 986 if (sc->age_cdata.age_cmb_block_map != NULL && 987 sc->age_rdata.age_cmb_block != NULL) 988 bus_dmamem_free(sc->sc_dmat, 989 (bus_dma_segment_t *)sc->age_rdata.age_cmb_block, 1); 990 sc->age_rdata.age_cmb_block = NULL; 991 sc->age_cdata.age_cmb_block_map = NULL; 992 993 /* SMB block */ 994 if (sc->age_cdata.age_smb_block_map != NULL) 995 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_smb_block_map); 996 if (sc->age_cdata.age_smb_block_map != NULL && 997 sc->age_rdata.age_smb_block != NULL) 998 bus_dmamem_free(sc->sc_dmat, 999 (bus_dma_segment_t *)sc->age_rdata.age_smb_block, 1); 1000 sc->age_rdata.age_smb_block = NULL; 1001 sc->age_cdata.age_smb_block_map = NULL; 1002 } 1003 1004 void 1005 age_start(struct ifnet *ifp) 1006 { 1007 struct age_softc *sc = ifp->if_softc; 1008 struct mbuf *m_head; 1009 int enq; 1010 1011 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1012 return; 1013 1014 enq = 0; 1015 for (;;) { 1016 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1017 if (m_head == NULL) 1018 break; 1019 1020 /* 1021 * Pack the data into the transmit ring. If we 1022 * don't have room, set the OACTIVE flag and wait 1023 * for the NIC to drain the ring. 1024 */ 1025 if (age_encap(sc, &m_head)) { 1026 if (m_head == NULL) 1027 break; 1028 ifp->if_flags |= IFF_OACTIVE; 1029 break; 1030 } 1031 enq = 1; 1032 1033 #if NBPFILTER > 0 1034 /* 1035 * If there's a BPF listener, bounce a copy of this frame 1036 * to him. 1037 */ 1038 if (ifp->if_bpf != NULL) 1039 bpf_mtap_ether(ifp->if_bpf, m_head, BPF_DIRECTION_OUT); 1040 #endif 1041 } 1042 1043 if (enq) { 1044 /* Update mbox. */ 1045 AGE_COMMIT_MBOX(sc); 1046 /* Set a timeout in case the chip goes out to lunch. */ 1047 ifp->if_timer = AGE_TX_TIMEOUT; 1048 } 1049 } 1050 1051 void 1052 age_watchdog(struct ifnet *ifp) 1053 { 1054 struct age_softc *sc = ifp->if_softc; 1055 1056 if ((sc->age_flags & AGE_FLAG_LINK) == 0) { 1057 printf("%s: watchdog timeout (missed link)\n", 1058 sc->sc_dev.dv_xname); 1059 ifp->if_oerrors++; 1060 age_init(ifp); 1061 return; 1062 } 1063 1064 if (sc->age_cdata.age_tx_cnt == 0) { 1065 printf("%s: watchdog timeout (missed Tx interrupts) " 1066 "-- recovering\n", sc->sc_dev.dv_xname); 1067 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1068 age_start(ifp); 1069 return; 1070 } 1071 1072 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 1073 ifp->if_oerrors++; 1074 age_init(ifp); 1075 1076 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1077 age_start(ifp); 1078 } 1079 1080 int 1081 age_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1082 { 1083 struct age_softc *sc = ifp->if_softc; 1084 struct mii_data *mii = &sc->sc_miibus; 1085 struct ifaddr *ifa = (struct ifaddr *)data; 1086 struct ifreq *ifr = (struct ifreq *)data; 1087 int s, error = 0; 1088 1089 s = splnet(); 1090 1091 switch (cmd) { 1092 case SIOCSIFADDR: 1093 ifp->if_flags |= IFF_UP; 1094 if (!(ifp->if_flags & IFF_RUNNING)) 1095 age_init(ifp); 1096 #ifdef INET 1097 if (ifa->ifa_addr->sa_family == AF_INET) 1098 arp_ifinit(&sc->sc_arpcom, ifa); 1099 #endif 1100 break; 1101 1102 case SIOCSIFFLAGS: 1103 if (ifp->if_flags & IFF_UP) { 1104 if (ifp->if_flags & IFF_RUNNING) 1105 error = ENETRESET; 1106 else 1107 age_init(ifp); 1108 } else { 1109 if (ifp->if_flags & IFF_RUNNING) 1110 age_stop(sc); 1111 } 1112 break; 1113 1114 case SIOCSIFMEDIA: 1115 case SIOCGIFMEDIA: 1116 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1117 break; 1118 1119 default: 1120 error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data); 1121 break; 1122 } 1123 1124 if (error == ENETRESET) { 1125 if (ifp->if_flags & IFF_RUNNING) 1126 age_rxfilter(sc); 1127 error = 0; 1128 } 1129 1130 splx(s); 1131 return (error); 1132 } 1133 1134 void 1135 age_mac_config(struct age_softc *sc) 1136 { 1137 struct mii_data *mii; 1138 uint32_t reg; 1139 1140 mii = &sc->sc_miibus; 1141 1142 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1143 reg &= ~MAC_CFG_FULL_DUPLEX; 1144 reg &= ~(MAC_CFG_TX_FC | MAC_CFG_RX_FC); 1145 reg &= ~MAC_CFG_SPEED_MASK; 1146 1147 /* Reprogram MAC with resolved speed/duplex. */ 1148 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1149 case IFM_10_T: 1150 case IFM_100_TX: 1151 reg |= MAC_CFG_SPEED_10_100; 1152 break; 1153 case IFM_1000_T: 1154 reg |= MAC_CFG_SPEED_1000; 1155 break; 1156 } 1157 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1158 reg |= MAC_CFG_FULL_DUPLEX; 1159 #ifdef notyet 1160 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1161 reg |= MAC_CFG_TX_FC; 1162 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1163 reg |= MAC_CFG_RX_FC; 1164 #endif 1165 } 1166 1167 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1168 } 1169 1170 int 1171 age_encap(struct age_softc *sc, struct mbuf **m_head) 1172 { 1173 struct age_txdesc *txd, *txd_last; 1174 struct tx_desc *desc; 1175 struct mbuf *m; 1176 bus_dmamap_t map; 1177 uint32_t cflags, poff, vtag; 1178 int error, i, nsegs, prod; 1179 1180 m = *m_head; 1181 cflags = vtag = 0; 1182 poff = 0; 1183 1184 prod = sc->age_cdata.age_tx_prod; 1185 txd = &sc->age_cdata.age_txdesc[prod]; 1186 txd_last = txd; 1187 map = txd->tx_dmamap; 1188 1189 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, BUS_DMA_NOWAIT); 1190 1191 if (error != 0) { 1192 bus_dmamap_unload(sc->sc_dmat, map); 1193 error = EFBIG; 1194 } 1195 if (error == EFBIG) { 1196 error = 0; 1197 1198 MGETHDR(m, M_DONTWAIT, MT_DATA); 1199 if (m == NULL) { 1200 printf("%s: can't defrag TX mbuf\n", 1201 sc->sc_dev.dv_xname); 1202 m_freem(*m_head); 1203 *m_head = NULL; 1204 return (ENOBUFS); 1205 } 1206 1207 M_DUP_PKTHDR(m, *m_head); 1208 if ((*m_head)->m_pkthdr.len > MHLEN) { 1209 MCLGET(m, M_DONTWAIT); 1210 if (!(m->m_flags & M_EXT)) { 1211 m_freem(*m_head); 1212 m_freem(m); 1213 *m_head = NULL; 1214 return (ENOBUFS); 1215 } 1216 } 1217 m_copydata(*m_head, 0, (*m_head)->m_pkthdr.len, 1218 mtod(m, caddr_t)); 1219 m_freem(*m_head); 1220 m->m_len = m->m_pkthdr.len; 1221 *m_head = m; 1222 1223 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, 1224 BUS_DMA_NOWAIT); 1225 1226 if (error != 0) { 1227 printf("%s: could not load defragged TX mbuf\n", 1228 sc->sc_dev.dv_xname); 1229 if (!error) { 1230 bus_dmamap_unload(sc->sc_dmat, map); 1231 error = EFBIG; 1232 } 1233 m_freem(*m_head); 1234 *m_head = NULL; 1235 return (error); 1236 } 1237 } else if (error) { 1238 printf("%s: could not load TX mbuf\n", sc->sc_dev.dv_xname); 1239 return (error); 1240 } 1241 1242 nsegs = map->dm_nsegs; 1243 1244 if (nsegs == 0) { 1245 m_freem(*m_head); 1246 *m_head = NULL; 1247 return (EIO); 1248 } 1249 1250 /* Check descriptor overrun. */ 1251 if (sc->age_cdata.age_tx_cnt + nsegs >= AGE_TX_RING_CNT - 2) { 1252 bus_dmamap_unload(sc->sc_dmat, map); 1253 return (ENOBUFS); 1254 } 1255 1256 m = *m_head; 1257 /* Configure Tx IP/TCP/UDP checksum offload. */ 1258 if ((m->m_pkthdr.csum_flags & AGE_CSUM_FEATURES) != 0) { 1259 cflags |= AGE_TD_CSUM; 1260 if ((m->m_pkthdr.csum_flags & M_TCPV4_CSUM_OUT) != 0) 1261 cflags |= AGE_TD_TCPCSUM; 1262 if ((m->m_pkthdr.csum_flags & M_UDPV4_CSUM_OUT) != 0) 1263 cflags |= AGE_TD_UDPCSUM; 1264 /* Set checksum start offset. */ 1265 cflags |= (poff << AGE_TD_CSUM_PLOADOFFSET_SHIFT); 1266 } 1267 1268 #if NVLAN > 0 1269 /* Configure VLAN hardware tag insertion. */ 1270 if (m->m_flags & M_VLANTAG) { 1271 vtag = AGE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag); 1272 vtag = ((vtag << AGE_TD_VLAN_SHIFT) & AGE_TD_VLAN_MASK); 1273 cflags |= AGE_TD_INSERT_VLAN_TAG; 1274 } 1275 #endif 1276 1277 desc = NULL; 1278 for (i = 0; i < nsegs; i++) { 1279 desc = &sc->age_rdata.age_tx_ring[prod]; 1280 desc->addr = htole64(map->dm_segs[i].ds_addr); 1281 desc->len = 1282 htole32(AGE_TX_BYTES(map->dm_segs[i].ds_len) | vtag); 1283 desc->flags = htole32(cflags); 1284 sc->age_cdata.age_tx_cnt++; 1285 AGE_DESC_INC(prod, AGE_TX_RING_CNT); 1286 } 1287 1288 /* Update producer index. */ 1289 sc->age_cdata.age_tx_prod = prod; 1290 1291 /* Set EOP on the last descriptor. */ 1292 prod = (prod + AGE_TX_RING_CNT - 1) % AGE_TX_RING_CNT; 1293 desc = &sc->age_rdata.age_tx_ring[prod]; 1294 desc->flags |= htole32(AGE_TD_EOP); 1295 1296 /* Swap dmamap of the first and the last. */ 1297 txd = &sc->age_cdata.age_txdesc[prod]; 1298 map = txd_last->tx_dmamap; 1299 txd_last->tx_dmamap = txd->tx_dmamap; 1300 txd->tx_dmamap = map; 1301 txd->tx_m = m; 1302 1303 /* Sync descriptors. */ 1304 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1305 BUS_DMASYNC_PREWRITE); 1306 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 0, 1307 sc->age_cdata.age_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1308 1309 return (0); 1310 } 1311 1312 void 1313 age_txintr(struct age_softc *sc, int tpd_cons) 1314 { 1315 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1316 struct age_txdesc *txd; 1317 int cons, prog; 1318 1319 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 0, 1320 sc->age_cdata.age_tx_ring_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1321 1322 /* 1323 * Go through our Tx list and free mbufs for those 1324 * frames which have been transmitted. 1325 */ 1326 cons = sc->age_cdata.age_tx_cons; 1327 for (prog = 0; cons != tpd_cons; AGE_DESC_INC(cons, AGE_TX_RING_CNT)) { 1328 if (sc->age_cdata.age_tx_cnt <= 0) 1329 break; 1330 prog++; 1331 ifp->if_flags &= ~IFF_OACTIVE; 1332 sc->age_cdata.age_tx_cnt--; 1333 txd = &sc->age_cdata.age_txdesc[cons]; 1334 /* 1335 * Clear Tx descriptors, it's not required but would 1336 * help debugging in case of Tx issues. 1337 */ 1338 txd->tx_desc->addr = 0; 1339 txd->tx_desc->len = 0; 1340 txd->tx_desc->flags = 0; 1341 1342 if (txd->tx_m == NULL) 1343 continue; 1344 /* Reclaim transmitted mbufs. */ 1345 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1346 m_freem(txd->tx_m); 1347 txd->tx_m = NULL; 1348 } 1349 1350 if (prog > 0) { 1351 sc->age_cdata.age_tx_cons = cons; 1352 1353 /* 1354 * Unarm watchdog timer only when there are no pending 1355 * Tx descriptors in queue. 1356 */ 1357 if (sc->age_cdata.age_tx_cnt == 0) 1358 ifp->if_timer = 0; 1359 1360 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 0, 1361 sc->age_cdata.age_tx_ring_map->dm_mapsize, 1362 BUS_DMASYNC_PREWRITE); 1363 } 1364 } 1365 1366 /* Receive a frame. */ 1367 void 1368 age_rxeof(struct age_softc *sc, struct rx_rdesc *rxrd) 1369 { 1370 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1371 struct age_rxdesc *rxd; 1372 struct rx_desc *desc; 1373 struct mbuf *mp, *m; 1374 uint32_t status, index; 1375 int count, nsegs, pktlen; 1376 int rx_cons; 1377 1378 status = letoh32(rxrd->flags); 1379 index = letoh32(rxrd->index); 1380 rx_cons = AGE_RX_CONS(index); 1381 nsegs = AGE_RX_NSEGS(index); 1382 1383 sc->age_cdata.age_rxlen = AGE_RX_BYTES(letoh32(rxrd->len)); 1384 if ((status & AGE_RRD_ERROR) != 0 && 1385 (status & (AGE_RRD_CRC | AGE_RRD_CODE | AGE_RRD_DRIBBLE | 1386 AGE_RRD_RUNT | AGE_RRD_OFLOW | AGE_RRD_TRUNC)) != 0) { 1387 /* 1388 * We want to pass the following frames to upper 1389 * layer regardless of error status of Rx return 1390 * ring. 1391 * 1392 * o IP/TCP/UDP checksum is bad. 1393 * o frame length and protocol specific length 1394 * does not match. 1395 */ 1396 sc->age_cdata.age_rx_cons += nsegs; 1397 sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT; 1398 return; 1399 } 1400 1401 pktlen = 0; 1402 for (count = 0; count < nsegs; count++, 1403 AGE_DESC_INC(rx_cons, AGE_RX_RING_CNT)) { 1404 rxd = &sc->age_cdata.age_rxdesc[rx_cons]; 1405 mp = rxd->rx_m; 1406 desc = rxd->rx_desc; 1407 /* Add a new receive buffer to the ring. */ 1408 if (age_newbuf(sc, rxd, 0) != 0) { 1409 ifp->if_iqdrops++; 1410 /* Reuse Rx buffers. */ 1411 if (sc->age_cdata.age_rxhead != NULL) { 1412 m_freem(sc->age_cdata.age_rxhead); 1413 AGE_RXCHAIN_RESET(sc); 1414 } 1415 break; 1416 } 1417 1418 /* The length of the first mbuf is computed last. */ 1419 if (count != 0) { 1420 mp->m_len = AGE_RX_BYTES(letoh32(desc->len)); 1421 pktlen += mp->m_len; 1422 } 1423 1424 /* Chain received mbufs. */ 1425 if (sc->age_cdata.age_rxhead == NULL) { 1426 sc->age_cdata.age_rxhead = mp; 1427 sc->age_cdata.age_rxtail = mp; 1428 } else { 1429 mp->m_flags &= ~M_PKTHDR; 1430 sc->age_cdata.age_rxprev_tail = 1431 sc->age_cdata.age_rxtail; 1432 sc->age_cdata.age_rxtail->m_next = mp; 1433 sc->age_cdata.age_rxtail = mp; 1434 } 1435 1436 if (count == nsegs - 1) { 1437 /* 1438 * It seems that L1 controller has no way 1439 * to tell hardware to strip CRC bytes. 1440 */ 1441 sc->age_cdata.age_rxlen -= ETHER_CRC_LEN; 1442 if (nsegs > 1) { 1443 /* Remove the CRC bytes in chained mbufs. */ 1444 pktlen -= ETHER_CRC_LEN; 1445 if (mp->m_len <= ETHER_CRC_LEN) { 1446 sc->age_cdata.age_rxtail = 1447 sc->age_cdata.age_rxprev_tail; 1448 sc->age_cdata.age_rxtail->m_len -= 1449 (ETHER_CRC_LEN - mp->m_len); 1450 sc->age_cdata.age_rxtail->m_next = NULL; 1451 m_freem(mp); 1452 } else { 1453 mp->m_len -= ETHER_CRC_LEN; 1454 } 1455 } 1456 1457 m = sc->age_cdata.age_rxhead; 1458 m->m_flags |= M_PKTHDR; 1459 m->m_pkthdr.rcvif = ifp; 1460 m->m_pkthdr.len = sc->age_cdata.age_rxlen; 1461 /* Set the first mbuf length. */ 1462 m->m_len = sc->age_cdata.age_rxlen - pktlen; 1463 1464 /* 1465 * Set checksum information. 1466 * It seems that L1 controller can compute partial 1467 * checksum. The partial checksum value can be used 1468 * to accelerate checksum computation for fragmented 1469 * TCP/UDP packets. Upper network stack already 1470 * takes advantage of the partial checksum value in 1471 * IP reassembly stage. But I'm not sure the 1472 * correctness of the partial hardware checksum 1473 * assistance due to lack of data sheet. If it is 1474 * proven to work on L1 I'll enable it. 1475 */ 1476 if (status & AGE_RRD_IPV4) { 1477 if ((status & AGE_RRD_IPCSUM_NOK) == 0) 1478 m->m_pkthdr.csum_flags |= 1479 M_IPV4_CSUM_IN_OK; 1480 if ((status & (AGE_RRD_TCP | AGE_RRD_UDP)) && 1481 (status & AGE_RRD_TCP_UDPCSUM_NOK) == 0) { 1482 m->m_pkthdr.csum_flags |= 1483 M_TCP_CSUM_IN_OK | M_UDP_CSUM_IN_OK; 1484 } 1485 /* 1486 * Don't mark bad checksum for TCP/UDP frames 1487 * as fragmented frames may always have set 1488 * bad checksummed bit of descriptor status. 1489 */ 1490 } 1491 #if NVLAN > 0 1492 /* Check for VLAN tagged frames. */ 1493 if (status & AGE_RRD_VLAN) { 1494 u_int32_t vtag = AGE_RX_VLAN(letoh32(rxrd->vtags)); 1495 m->m_pkthdr.ether_vtag = 1496 AGE_RX_VLAN_TAG(vtag); 1497 m->m_flags |= M_VLANTAG; 1498 } 1499 #endif 1500 1501 #if NBPFILTER > 0 1502 if (ifp->if_bpf) 1503 bpf_mtap_ether(ifp->if_bpf, m, 1504 BPF_DIRECTION_IN); 1505 #endif 1506 /* Pass it on. */ 1507 ether_input_mbuf(ifp, m); 1508 1509 /* Reset mbuf chains. */ 1510 AGE_RXCHAIN_RESET(sc); 1511 } 1512 } 1513 1514 if (count != nsegs) { 1515 sc->age_cdata.age_rx_cons += nsegs; 1516 sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT; 1517 } else 1518 sc->age_cdata.age_rx_cons = rx_cons; 1519 } 1520 1521 void 1522 age_rxintr(struct age_softc *sc, int rr_prod) 1523 { 1524 struct rx_rdesc *rxrd; 1525 int rr_cons, nsegs, pktlen, prog; 1526 1527 rr_cons = sc->age_cdata.age_rr_cons; 1528 if (rr_cons == rr_prod) 1529 return; 1530 1531 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 0, 1532 sc->age_cdata.age_rr_ring_map->dm_mapsize, 1533 BUS_DMASYNC_POSTREAD); 1534 1535 for (prog = 0; rr_cons != rr_prod; prog++) { 1536 rxrd = &sc->age_rdata.age_rr_ring[rr_cons]; 1537 nsegs = AGE_RX_NSEGS(letoh32(rxrd->index)); 1538 if (nsegs == 0) 1539 break; 1540 /* 1541 * Check number of segments against received bytes 1542 * Non-matching value would indicate that hardware 1543 * is still trying to update Rx return descriptors. 1544 * I'm not sure whether this check is really needed. 1545 */ 1546 pktlen = AGE_RX_BYTES(letoh32(rxrd->len)); 1547 if (nsegs != ((pktlen + (MCLBYTES - ETHER_ALIGN - 1)) / 1548 (MCLBYTES - ETHER_ALIGN))) 1549 break; 1550 1551 /* Received a frame. */ 1552 age_rxeof(sc, rxrd); 1553 1554 /* Clear return ring. */ 1555 rxrd->index = 0; 1556 AGE_DESC_INC(rr_cons, AGE_RR_RING_CNT); 1557 } 1558 1559 if (prog > 0) { 1560 /* Update the consumer index. */ 1561 sc->age_cdata.age_rr_cons = rr_cons; 1562 1563 /* Sync descriptors. */ 1564 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 0, 1565 sc->age_cdata.age_rr_ring_map->dm_mapsize, 1566 BUS_DMASYNC_PREWRITE); 1567 1568 /* Notify hardware availability of new Rx buffers. */ 1569 AGE_COMMIT_MBOX(sc); 1570 } 1571 } 1572 1573 void 1574 age_tick(void *xsc) 1575 { 1576 struct age_softc *sc = xsc; 1577 struct mii_data *mii = &sc->sc_miibus; 1578 int s; 1579 1580 s = splnet(); 1581 mii_tick(mii); 1582 timeout_add_sec(&sc->age_tick_ch, 1); 1583 splx(s); 1584 } 1585 1586 void 1587 age_reset(struct age_softc *sc) 1588 { 1589 uint32_t reg; 1590 int i; 1591 1592 CSR_WRITE_4(sc, AGE_MASTER_CFG, MASTER_RESET); 1593 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 1594 DELAY(1); 1595 if ((CSR_READ_4(sc, AGE_MASTER_CFG) & MASTER_RESET) == 0) 1596 break; 1597 } 1598 if (i == 0) 1599 printf("%s: master reset timeout!\n", sc->sc_dev.dv_xname); 1600 1601 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 1602 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 1603 break; 1604 DELAY(10); 1605 } 1606 1607 if (i == 0) 1608 printf("%s: reset timeout(0x%08x)!\n", sc->sc_dev.dv_xname, 1609 reg); 1610 1611 /* Initialize PCIe module. From Linux. */ 1612 CSR_WRITE_4(sc, 0x12FC, 0x6500); 1613 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 1614 } 1615 1616 int 1617 age_init(struct ifnet *ifp) 1618 { 1619 struct age_softc *sc = ifp->if_softc; 1620 struct mii_data *mii; 1621 uint8_t eaddr[ETHER_ADDR_LEN]; 1622 bus_addr_t paddr; 1623 uint32_t reg, fsize; 1624 uint32_t rxf_hi, rxf_lo, rrd_hi, rrd_lo; 1625 int error; 1626 1627 /* 1628 * Cancel any pending I/O. 1629 */ 1630 age_stop(sc); 1631 1632 /* 1633 * Reset the chip to a known state. 1634 */ 1635 age_reset(sc); 1636 1637 /* Initialize descriptors. */ 1638 error = age_init_rx_ring(sc); 1639 if (error != 0) { 1640 printf("%s: no memory for Rx buffers.\n", sc->sc_dev.dv_xname); 1641 age_stop(sc); 1642 return (error); 1643 } 1644 age_init_rr_ring(sc); 1645 age_init_tx_ring(sc); 1646 age_init_cmb_block(sc); 1647 age_init_smb_block(sc); 1648 1649 /* Reprogram the station address. */ 1650 bcopy(LLADDR(ifp->if_sadl), eaddr, ETHER_ADDR_LEN); 1651 CSR_WRITE_4(sc, AGE_PAR0, 1652 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 1653 CSR_WRITE_4(sc, AGE_PAR1, eaddr[0] << 8 | eaddr[1]); 1654 1655 /* Set descriptor base addresses. */ 1656 paddr = sc->age_rdata.age_tx_ring_paddr; 1657 CSR_WRITE_4(sc, AGE_DESC_ADDR_HI, AGE_ADDR_HI(paddr)); 1658 paddr = sc->age_rdata.age_rx_ring_paddr; 1659 CSR_WRITE_4(sc, AGE_DESC_RD_ADDR_LO, AGE_ADDR_LO(paddr)); 1660 paddr = sc->age_rdata.age_rr_ring_paddr; 1661 CSR_WRITE_4(sc, AGE_DESC_RRD_ADDR_LO, AGE_ADDR_LO(paddr)); 1662 paddr = sc->age_rdata.age_tx_ring_paddr; 1663 CSR_WRITE_4(sc, AGE_DESC_TPD_ADDR_LO, AGE_ADDR_LO(paddr)); 1664 paddr = sc->age_rdata.age_cmb_block_paddr; 1665 CSR_WRITE_4(sc, AGE_DESC_CMB_ADDR_LO, AGE_ADDR_LO(paddr)); 1666 paddr = sc->age_rdata.age_smb_block_paddr; 1667 CSR_WRITE_4(sc, AGE_DESC_SMB_ADDR_LO, AGE_ADDR_LO(paddr)); 1668 1669 /* Set Rx/Rx return descriptor counter. */ 1670 CSR_WRITE_4(sc, AGE_DESC_RRD_RD_CNT, 1671 ((AGE_RR_RING_CNT << DESC_RRD_CNT_SHIFT) & 1672 DESC_RRD_CNT_MASK) | 1673 ((AGE_RX_RING_CNT << DESC_RD_CNT_SHIFT) & DESC_RD_CNT_MASK)); 1674 1675 /* Set Tx descriptor counter. */ 1676 CSR_WRITE_4(sc, AGE_DESC_TPD_CNT, 1677 (AGE_TX_RING_CNT << DESC_TPD_CNT_SHIFT) & DESC_TPD_CNT_MASK); 1678 1679 /* Tell hardware that we're ready to load descriptors. */ 1680 CSR_WRITE_4(sc, AGE_DMA_BLOCK, DMA_BLOCK_LOAD); 1681 1682 /* 1683 * Initialize mailbox register. 1684 * Updated producer/consumer index information is exchanged 1685 * through this mailbox register. However Tx producer and 1686 * Rx return consumer/Rx producer are all shared such that 1687 * it's hard to separate code path between Tx and Rx without 1688 * locking. If L1 hardware have a separate mail box register 1689 * for Tx and Rx consumer/producer management we could have 1690 * indepent Tx/Rx handler which in turn Rx handler could have 1691 * been run without any locking. 1692 */ 1693 AGE_COMMIT_MBOX(sc); 1694 1695 /* Configure IPG/IFG parameters. */ 1696 CSR_WRITE_4(sc, AGE_IPG_IFG_CFG, 1697 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK) | 1698 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 1699 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 1700 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK)); 1701 1702 /* Set parameters for half-duplex media. */ 1703 CSR_WRITE_4(sc, AGE_HDPX_CFG, 1704 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 1705 HDPX_CFG_LCOL_MASK) | 1706 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 1707 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 1708 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 1709 HDPX_CFG_ABEBT_MASK) | 1710 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 1711 HDPX_CFG_JAMIPG_MASK)); 1712 1713 /* Configure interrupt moderation timer. */ 1714 sc->age_int_mod = AGE_IM_TIMER_DEFAULT; 1715 CSR_WRITE_2(sc, AGE_IM_TIMER, AGE_USECS(sc->age_int_mod)); 1716 reg = CSR_READ_4(sc, AGE_MASTER_CFG); 1717 reg &= ~MASTER_MTIMER_ENB; 1718 if (AGE_USECS(sc->age_int_mod) == 0) 1719 reg &= ~MASTER_ITIMER_ENB; 1720 else 1721 reg |= MASTER_ITIMER_ENB; 1722 CSR_WRITE_4(sc, AGE_MASTER_CFG, reg); 1723 if (agedebug) 1724 printf("%s: interrupt moderation is %d us.\n", 1725 sc->sc_dev.dv_xname, sc->age_int_mod); 1726 CSR_WRITE_2(sc, AGE_INTR_CLR_TIMER, AGE_USECS(1000)); 1727 1728 /* Set Maximum frame size but don't let MTU be lass than ETHER_MTU. */ 1729 if (ifp->if_mtu < ETHERMTU) 1730 sc->age_max_frame_size = ETHERMTU; 1731 else 1732 sc->age_max_frame_size = ifp->if_mtu; 1733 sc->age_max_frame_size += ETHER_HDR_LEN + 1734 sizeof(struct ether_vlan_header) + ETHER_CRC_LEN; 1735 CSR_WRITE_4(sc, AGE_FRAME_SIZE, sc->age_max_frame_size); 1736 1737 /* Configure jumbo frame. */ 1738 fsize = roundup(sc->age_max_frame_size, sizeof(uint64_t)); 1739 CSR_WRITE_4(sc, AGE_RXQ_JUMBO_CFG, 1740 (((fsize / sizeof(uint64_t)) << 1741 RXQ_JUMBO_CFG_SZ_THRESH_SHIFT) & RXQ_JUMBO_CFG_SZ_THRESH_MASK) | 1742 ((RXQ_JUMBO_CFG_LKAH_DEFAULT << 1743 RXQ_JUMBO_CFG_LKAH_SHIFT) & RXQ_JUMBO_CFG_LKAH_MASK) | 1744 ((AGE_USECS(8) << RXQ_JUMBO_CFG_RRD_TIMER_SHIFT) & 1745 RXQ_JUMBO_CFG_RRD_TIMER_MASK)); 1746 1747 /* Configure flow-control parameters. From Linux. */ 1748 if ((sc->age_flags & AGE_FLAG_PCIE) != 0) { 1749 /* 1750 * Magic workaround for old-L1. 1751 * Don't know which hw revision requires this magic. 1752 */ 1753 CSR_WRITE_4(sc, 0x12FC, 0x6500); 1754 /* 1755 * Another magic workaround for flow-control mode 1756 * change. From Linux. 1757 */ 1758 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 1759 } 1760 /* 1761 * TODO 1762 * Should understand pause parameter relationships between FIFO 1763 * size and number of Rx descriptors and Rx return descriptors. 1764 * 1765 * Magic parameters came from Linux. 1766 */ 1767 switch (sc->age_chip_rev) { 1768 case 0x8001: 1769 case 0x9001: 1770 case 0x9002: 1771 case 0x9003: 1772 rxf_hi = AGE_RX_RING_CNT / 16; 1773 rxf_lo = (AGE_RX_RING_CNT * 7) / 8; 1774 rrd_hi = (AGE_RR_RING_CNT * 7) / 8; 1775 rrd_lo = AGE_RR_RING_CNT / 16; 1776 break; 1777 default: 1778 reg = CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN); 1779 rxf_lo = reg / 16; 1780 if (rxf_lo < 192) 1781 rxf_lo = 192; 1782 rxf_hi = (reg * 7) / 8; 1783 if (rxf_hi < rxf_lo) 1784 rxf_hi = rxf_lo + 16; 1785 reg = CSR_READ_4(sc, AGE_SRAM_RRD_LEN); 1786 rrd_lo = reg / 8; 1787 rrd_hi = (reg * 7) / 8; 1788 if (rrd_lo < 2) 1789 rrd_lo = 2; 1790 if (rrd_hi < rrd_lo) 1791 rrd_hi = rrd_lo + 3; 1792 break; 1793 } 1794 CSR_WRITE_4(sc, AGE_RXQ_FIFO_PAUSE_THRESH, 1795 ((rxf_lo << RXQ_FIFO_PAUSE_THRESH_LO_SHIFT) & 1796 RXQ_FIFO_PAUSE_THRESH_LO_MASK) | 1797 ((rxf_hi << RXQ_FIFO_PAUSE_THRESH_HI_SHIFT) & 1798 RXQ_FIFO_PAUSE_THRESH_HI_MASK)); 1799 CSR_WRITE_4(sc, AGE_RXQ_RRD_PAUSE_THRESH, 1800 ((rrd_lo << RXQ_RRD_PAUSE_THRESH_LO_SHIFT) & 1801 RXQ_RRD_PAUSE_THRESH_LO_MASK) | 1802 ((rrd_hi << RXQ_RRD_PAUSE_THRESH_HI_SHIFT) & 1803 RXQ_RRD_PAUSE_THRESH_HI_MASK)); 1804 1805 /* Configure RxQ. */ 1806 CSR_WRITE_4(sc, AGE_RXQ_CFG, 1807 ((RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 1808 RXQ_CFG_RD_BURST_MASK) | 1809 ((RXQ_CFG_RRD_BURST_THRESH_DEFAULT << 1810 RXQ_CFG_RRD_BURST_THRESH_SHIFT) & RXQ_CFG_RRD_BURST_THRESH_MASK) | 1811 ((RXQ_CFG_RD_PREF_MIN_IPG_DEFAULT << 1812 RXQ_CFG_RD_PREF_MIN_IPG_SHIFT) & RXQ_CFG_RD_PREF_MIN_IPG_MASK) | 1813 RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 1814 1815 /* Configure TxQ. */ 1816 CSR_WRITE_4(sc, AGE_TXQ_CFG, 1817 ((TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 1818 TXQ_CFG_TPD_BURST_MASK) | 1819 ((TXQ_CFG_TX_FIFO_BURST_DEFAULT << TXQ_CFG_TX_FIFO_BURST_SHIFT) & 1820 TXQ_CFG_TX_FIFO_BURST_MASK) | 1821 ((TXQ_CFG_TPD_FETCH_DEFAULT << 1822 TXQ_CFG_TPD_FETCH_THRESH_SHIFT) & TXQ_CFG_TPD_FETCH_THRESH_MASK) | 1823 TXQ_CFG_ENB); 1824 1825 /* Configure DMA parameters. */ 1826 CSR_WRITE_4(sc, AGE_DMA_CFG, 1827 DMA_CFG_ENH_ORDER | DMA_CFG_RCB_64 | 1828 sc->age_dma_rd_burst | DMA_CFG_RD_ENB | 1829 sc->age_dma_wr_burst | DMA_CFG_WR_ENB); 1830 1831 /* Configure CMB DMA write threshold. */ 1832 CSR_WRITE_4(sc, AGE_CMB_WR_THRESH, 1833 ((CMB_WR_THRESH_RRD_DEFAULT << CMB_WR_THRESH_RRD_SHIFT) & 1834 CMB_WR_THRESH_RRD_MASK) | 1835 ((CMB_WR_THRESH_TPD_DEFAULT << CMB_WR_THRESH_TPD_SHIFT) & 1836 CMB_WR_THRESH_TPD_MASK)); 1837 1838 /* Set CMB/SMB timer and enable them. */ 1839 CSR_WRITE_4(sc, AGE_CMB_WR_TIMER, 1840 ((AGE_USECS(2) << CMB_WR_TIMER_TX_SHIFT) & CMB_WR_TIMER_TX_MASK) | 1841 ((AGE_USECS(2) << CMB_WR_TIMER_RX_SHIFT) & CMB_WR_TIMER_RX_MASK)); 1842 1843 /* Request SMB updates for every seconds. */ 1844 CSR_WRITE_4(sc, AGE_SMB_TIMER, AGE_USECS(1000 * 1000)); 1845 CSR_WRITE_4(sc, AGE_CSMB_CTRL, CSMB_CTRL_SMB_ENB | CSMB_CTRL_CMB_ENB); 1846 1847 /* 1848 * Disable all WOL bits as WOL can interfere normal Rx 1849 * operation. 1850 */ 1851 CSR_WRITE_4(sc, AGE_WOL_CFG, 0); 1852 1853 /* 1854 * Configure Tx/Rx MACs. 1855 * - Auto-padding for short frames. 1856 * - Enable CRC generation. 1857 * Start with full-duplex/1000Mbps media. Actual reconfiguration 1858 * of MAC is followed after link establishment. 1859 */ 1860 CSR_WRITE_4(sc, AGE_MAC_CFG, 1861 MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | 1862 MAC_CFG_FULL_DUPLEX | MAC_CFG_SPEED_1000 | 1863 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 1864 MAC_CFG_PREAMBLE_MASK)); 1865 1866 /* Set up the receive filter. */ 1867 age_rxfilter(sc); 1868 age_rxvlan(sc); 1869 1870 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1871 reg |= MAC_CFG_RXCSUM_ENB; 1872 1873 /* Ack all pending interrupts and clear it. */ 1874 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); 1875 CSR_WRITE_4(sc, AGE_INTR_MASK, AGE_INTRS); 1876 1877 /* Finally enable Tx/Rx MAC. */ 1878 CSR_WRITE_4(sc, AGE_MAC_CFG, reg | MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 1879 1880 sc->age_flags &= ~AGE_FLAG_LINK; 1881 1882 /* Switch to the current media. */ 1883 mii = &sc->sc_miibus; 1884 mii_mediachg(mii); 1885 1886 timeout_add_sec(&sc->age_tick_ch, 1); 1887 1888 ifp->if_flags |= IFF_RUNNING; 1889 ifp->if_flags &= ~IFF_OACTIVE; 1890 1891 return (0); 1892 } 1893 1894 void 1895 age_stop(struct age_softc *sc) 1896 { 1897 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1898 struct age_txdesc *txd; 1899 struct age_rxdesc *rxd; 1900 uint32_t reg; 1901 int i; 1902 1903 /* 1904 * Mark the interface down and cancel the watchdog timer. 1905 */ 1906 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1907 ifp->if_timer = 0; 1908 1909 sc->age_flags &= ~AGE_FLAG_LINK; 1910 timeout_del(&sc->age_tick_ch); 1911 1912 /* 1913 * Disable interrupts. 1914 */ 1915 CSR_WRITE_4(sc, AGE_INTR_MASK, 0); 1916 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0xFFFFFFFF); 1917 1918 /* Stop CMB/SMB updates. */ 1919 CSR_WRITE_4(sc, AGE_CSMB_CTRL, 0); 1920 1921 /* Stop Rx/Tx MAC. */ 1922 age_stop_rxmac(sc); 1923 age_stop_txmac(sc); 1924 1925 /* Stop DMA. */ 1926 CSR_WRITE_4(sc, AGE_DMA_CFG, 1927 CSR_READ_4(sc, AGE_DMA_CFG) & ~(DMA_CFG_RD_ENB | DMA_CFG_WR_ENB)); 1928 1929 /* Stop TxQ/RxQ. */ 1930 CSR_WRITE_4(sc, AGE_TXQ_CFG, 1931 CSR_READ_4(sc, AGE_TXQ_CFG) & ~TXQ_CFG_ENB); 1932 CSR_WRITE_4(sc, AGE_RXQ_CFG, 1933 CSR_READ_4(sc, AGE_RXQ_CFG) & ~RXQ_CFG_ENB); 1934 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 1935 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 1936 break; 1937 DELAY(10); 1938 } 1939 if (i == 0) 1940 printf("%s: stopping Rx/Tx MACs timed out(0x%08x)!\n", 1941 sc->sc_dev.dv_xname, reg); 1942 1943 /* Reclaim Rx buffers that have been processed. */ 1944 if (sc->age_cdata.age_rxhead != NULL) 1945 m_freem(sc->age_cdata.age_rxhead); 1946 AGE_RXCHAIN_RESET(sc); 1947 1948 /* 1949 * Free RX and TX mbufs still in the queues. 1950 */ 1951 for (i = 0; i < AGE_RX_RING_CNT; i++) { 1952 rxd = &sc->age_cdata.age_rxdesc[i]; 1953 if (rxd->rx_m != NULL) { 1954 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 1955 m_freem(rxd->rx_m); 1956 rxd->rx_m = NULL; 1957 } 1958 } 1959 for (i = 0; i < AGE_TX_RING_CNT; i++) { 1960 txd = &sc->age_cdata.age_txdesc[i]; 1961 if (txd->tx_m != NULL) { 1962 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1963 m_freem(txd->tx_m); 1964 txd->tx_m = NULL; 1965 } 1966 } 1967 } 1968 1969 void 1970 age_stats_update(struct age_softc *sc) 1971 { 1972 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1973 struct age_stats *stat; 1974 struct smb *smb; 1975 1976 stat = &sc->age_stat; 1977 1978 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 0, 1979 sc->age_cdata.age_smb_block_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1980 1981 smb = sc->age_rdata.age_smb_block; 1982 if (smb->updated == 0) 1983 return; 1984 1985 /* Rx stats. */ 1986 stat->rx_frames += smb->rx_frames; 1987 stat->rx_bcast_frames += smb->rx_bcast_frames; 1988 stat->rx_mcast_frames += smb->rx_mcast_frames; 1989 stat->rx_pause_frames += smb->rx_pause_frames; 1990 stat->rx_control_frames += smb->rx_control_frames; 1991 stat->rx_crcerrs += smb->rx_crcerrs; 1992 stat->rx_lenerrs += smb->rx_lenerrs; 1993 stat->rx_bytes += smb->rx_bytes; 1994 stat->rx_runts += smb->rx_runts; 1995 stat->rx_fragments += smb->rx_fragments; 1996 stat->rx_pkts_64 += smb->rx_pkts_64; 1997 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 1998 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 1999 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2000 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2001 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2002 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2003 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2004 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2005 stat->rx_desc_oflows += smb->rx_desc_oflows; 2006 stat->rx_alignerrs += smb->rx_alignerrs; 2007 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2008 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2009 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2010 2011 /* Tx stats. */ 2012 stat->tx_frames += smb->tx_frames; 2013 stat->tx_bcast_frames += smb->tx_bcast_frames; 2014 stat->tx_mcast_frames += smb->tx_mcast_frames; 2015 stat->tx_pause_frames += smb->tx_pause_frames; 2016 stat->tx_excess_defer += smb->tx_excess_defer; 2017 stat->tx_control_frames += smb->tx_control_frames; 2018 stat->tx_deferred += smb->tx_deferred; 2019 stat->tx_bytes += smb->tx_bytes; 2020 stat->tx_pkts_64 += smb->tx_pkts_64; 2021 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2022 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2023 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2024 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2025 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2026 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2027 stat->tx_single_colls += smb->tx_single_colls; 2028 stat->tx_multi_colls += smb->tx_multi_colls; 2029 stat->tx_late_colls += smb->tx_late_colls; 2030 stat->tx_excess_colls += smb->tx_excess_colls; 2031 stat->tx_underrun += smb->tx_underrun; 2032 stat->tx_desc_underrun += smb->tx_desc_underrun; 2033 stat->tx_lenerrs += smb->tx_lenerrs; 2034 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2035 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2036 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2037 2038 /* Update counters in ifnet. */ 2039 ifp->if_opackets += smb->tx_frames; 2040 2041 ifp->if_collisions += smb->tx_single_colls + 2042 smb->tx_multi_colls + smb->tx_late_colls + 2043 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT; 2044 2045 ifp->if_oerrors += smb->tx_excess_colls + 2046 smb->tx_late_colls + smb->tx_underrun + 2047 smb->tx_pkts_truncated; 2048 2049 ifp->if_ipackets += smb->rx_frames; 2050 2051 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 2052 smb->rx_runts + smb->rx_pkts_truncated + 2053 smb->rx_fifo_oflows + smb->rx_desc_oflows + 2054 smb->rx_alignerrs; 2055 2056 /* Update done, clear. */ 2057 smb->updated = 0; 2058 2059 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 0, 2060 sc->age_cdata.age_smb_block_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2061 } 2062 2063 void 2064 age_stop_txmac(struct age_softc *sc) 2065 { 2066 uint32_t reg; 2067 int i; 2068 2069 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2070 if ((reg & MAC_CFG_TX_ENB) != 0) { 2071 reg &= ~MAC_CFG_TX_ENB; 2072 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2073 } 2074 /* Stop Tx DMA engine. */ 2075 reg = CSR_READ_4(sc, AGE_DMA_CFG); 2076 if ((reg & DMA_CFG_RD_ENB) != 0) { 2077 reg &= ~DMA_CFG_RD_ENB; 2078 CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 2079 } 2080 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2081 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 2082 (IDLE_STATUS_TXMAC | IDLE_STATUS_DMARD)) == 0) 2083 break; 2084 DELAY(10); 2085 } 2086 if (i == 0) 2087 printf("%s: stopping TxMAC timeout!\n", sc->sc_dev.dv_xname); 2088 } 2089 2090 void 2091 age_stop_rxmac(struct age_softc *sc) 2092 { 2093 uint32_t reg; 2094 int i; 2095 2096 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2097 if ((reg & MAC_CFG_RX_ENB) != 0) { 2098 reg &= ~MAC_CFG_RX_ENB; 2099 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2100 } 2101 /* Stop Rx DMA engine. */ 2102 reg = CSR_READ_4(sc, AGE_DMA_CFG); 2103 if ((reg & DMA_CFG_WR_ENB) != 0) { 2104 reg &= ~DMA_CFG_WR_ENB; 2105 CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 2106 } 2107 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2108 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 2109 (IDLE_STATUS_RXMAC | IDLE_STATUS_DMAWR)) == 0) 2110 break; 2111 DELAY(10); 2112 } 2113 if (i == 0) 2114 printf("%s: stopping RxMAC timeout!\n", sc->sc_dev.dv_xname); 2115 } 2116 2117 void 2118 age_init_tx_ring(struct age_softc *sc) 2119 { 2120 struct age_ring_data *rd; 2121 struct age_txdesc *txd; 2122 int i; 2123 2124 sc->age_cdata.age_tx_prod = 0; 2125 sc->age_cdata.age_tx_cons = 0; 2126 sc->age_cdata.age_tx_cnt = 0; 2127 2128 rd = &sc->age_rdata; 2129 bzero(rd->age_tx_ring, AGE_TX_RING_SZ); 2130 for (i = 0; i < AGE_TX_RING_CNT; i++) { 2131 txd = &sc->age_cdata.age_txdesc[i]; 2132 txd->tx_desc = &rd->age_tx_ring[i]; 2133 txd->tx_m = NULL; 2134 } 2135 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 0, 2136 sc->age_cdata.age_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2137 } 2138 2139 int 2140 age_init_rx_ring(struct age_softc *sc) 2141 { 2142 struct age_ring_data *rd; 2143 struct age_rxdesc *rxd; 2144 int i; 2145 2146 sc->age_cdata.age_rx_cons = AGE_RX_RING_CNT - 1; 2147 rd = &sc->age_rdata; 2148 bzero(rd->age_rx_ring, AGE_RX_RING_SZ); 2149 for (i = 0; i < AGE_RX_RING_CNT; i++) { 2150 rxd = &sc->age_cdata.age_rxdesc[i]; 2151 rxd->rx_m = NULL; 2152 rxd->rx_desc = &rd->age_rx_ring[i]; 2153 if (age_newbuf(sc, rxd, 1) != 0) 2154 return (ENOBUFS); 2155 } 2156 2157 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rx_ring_map, 0, 2158 sc->age_cdata.age_rx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2159 2160 return (0); 2161 } 2162 2163 void 2164 age_init_rr_ring(struct age_softc *sc) 2165 { 2166 struct age_ring_data *rd; 2167 2168 sc->age_cdata.age_rr_cons = 0; 2169 AGE_RXCHAIN_RESET(sc); 2170 2171 rd = &sc->age_rdata; 2172 bzero(rd->age_rr_ring, AGE_RR_RING_SZ); 2173 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 0, 2174 sc->age_cdata.age_rr_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2175 } 2176 2177 void 2178 age_init_cmb_block(struct age_softc *sc) 2179 { 2180 struct age_ring_data *rd; 2181 2182 rd = &sc->age_rdata; 2183 bzero(rd->age_cmb_block, AGE_CMB_BLOCK_SZ); 2184 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 2185 sc->age_cdata.age_cmb_block_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2186 } 2187 2188 void 2189 age_init_smb_block(struct age_softc *sc) 2190 { 2191 struct age_ring_data *rd; 2192 2193 rd = &sc->age_rdata; 2194 bzero(rd->age_smb_block, AGE_SMB_BLOCK_SZ); 2195 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 0, 2196 sc->age_cdata.age_smb_block_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2197 } 2198 2199 int 2200 age_newbuf(struct age_softc *sc, struct age_rxdesc *rxd, int init) 2201 { 2202 struct rx_desc *desc; 2203 struct mbuf *m; 2204 bus_dmamap_t map; 2205 int error; 2206 2207 MGETHDR(m, init ? M_WAITOK : M_DONTWAIT, MT_DATA); 2208 if (m == NULL) 2209 return (ENOBUFS); 2210 MCLGET(m, init ? M_WAITOK : M_DONTWAIT); 2211 if (!(m->m_flags & M_EXT)) { 2212 m_freem(m); 2213 return (ENOBUFS); 2214 } 2215 2216 m->m_len = m->m_pkthdr.len = MCLBYTES; 2217 m_adj(m, ETHER_ALIGN); 2218 2219 error = bus_dmamap_load_mbuf(sc->sc_dmat, 2220 sc->age_cdata.age_rx_sparemap, m, BUS_DMA_NOWAIT); 2221 2222 if (error != 0) { 2223 if (!error) { 2224 bus_dmamap_unload(sc->sc_dmat, 2225 sc->age_cdata.age_rx_sparemap); 2226 error = EFBIG; 2227 printf("%s: too many segments?!\n", 2228 sc->sc_dev.dv_xname); 2229 } 2230 m_freem(m); 2231 2232 if (init) 2233 printf("%s: can't load RX mbuf\n", sc->sc_dev.dv_xname); 2234 return (error); 2235 } 2236 2237 if (rxd->rx_m != NULL) { 2238 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0, 2239 rxd->rx_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2240 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 2241 } 2242 map = rxd->rx_dmamap; 2243 rxd->rx_dmamap = sc->age_cdata.age_rx_sparemap; 2244 sc->age_cdata.age_rx_sparemap = map; 2245 rxd->rx_m = m; 2246 2247 desc = rxd->rx_desc; 2248 desc->addr = htole64(rxd->rx_dmamap->dm_segs[0].ds_addr); 2249 desc->len = 2250 htole32((rxd->rx_dmamap->dm_segs[0].ds_len & AGE_RD_LEN_MASK) << 2251 AGE_RD_LEN_SHIFT); 2252 2253 return (0); 2254 } 2255 2256 void 2257 age_rxvlan(struct age_softc *sc) 2258 { 2259 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 2260 uint32_t reg; 2261 2262 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2263 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 2264 if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) 2265 reg |= MAC_CFG_VLAN_TAG_STRIP; 2266 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2267 } 2268 2269 void 2270 age_rxfilter(struct age_softc *sc) 2271 { 2272 struct arpcom *ac = &sc->sc_arpcom; 2273 struct ifnet *ifp = &ac->ac_if; 2274 struct ether_multi *enm; 2275 struct ether_multistep step; 2276 uint32_t crc; 2277 uint32_t mchash[2]; 2278 uint32_t rxcfg; 2279 2280 rxcfg = CSR_READ_4(sc, AGE_MAC_CFG); 2281 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 2282 ifp->if_flags &= ~IFF_ALLMULTI; 2283 2284 /* 2285 * Always accept broadcast frames. 2286 */ 2287 rxcfg |= MAC_CFG_BCAST; 2288 2289 if (ifp->if_flags & IFF_PROMISC || ac->ac_multirangecnt > 0) { 2290 ifp->if_flags |= IFF_ALLMULTI; 2291 if (ifp->if_flags & IFF_PROMISC) 2292 rxcfg |= MAC_CFG_PROMISC; 2293 else 2294 rxcfg |= MAC_CFG_ALLMULTI; 2295 mchash[0] = mchash[1] = 0xFFFFFFFF; 2296 } else { 2297 /* Program new filter. */ 2298 bzero(mchash, sizeof(mchash)); 2299 2300 ETHER_FIRST_MULTI(step, ac, enm); 2301 while (enm != NULL) { 2302 crc = ether_crc32_le(enm->enm_addrlo, 2303 ETHER_ADDR_LEN); 2304 2305 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 2306 2307 ETHER_NEXT_MULTI(step, enm); 2308 } 2309 } 2310 2311 CSR_WRITE_4(sc, AGE_MAR0, mchash[0]); 2312 CSR_WRITE_4(sc, AGE_MAR1, mchash[1]); 2313 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg); 2314 } 2315