1 /* $OpenBSD: if_age.c,v 1.37 2020/07/10 13:26:37 patrick Exp $ */ 2 3 /*- 4 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* Driver for Attansic Technology Corp. L1 Gigabit Ethernet. */ 31 32 #include "bpfilter.h" 33 #include "vlan.h" 34 35 #include <sys/param.h> 36 #include <sys/endian.h> 37 #include <sys/systm.h> 38 #include <sys/sockio.h> 39 #include <sys/mbuf.h> 40 #include <sys/queue.h> 41 #include <sys/kernel.h> 42 #include <sys/device.h> 43 #include <sys/timeout.h> 44 #include <sys/socket.h> 45 46 #include <machine/bus.h> 47 48 #include <net/if.h> 49 #include <net/if_dl.h> 50 #include <net/if_media.h> 51 52 #include <netinet/in.h> 53 #include <netinet/if_ether.h> 54 55 #if NBPFILTER > 0 56 #include <net/bpf.h> 57 #endif 58 59 #include <dev/mii/mii.h> 60 #include <dev/mii/miivar.h> 61 62 #include <dev/pci/pcireg.h> 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pcidevs.h> 65 66 #include <dev/pci/if_agereg.h> 67 68 int age_match(struct device *, void *, void *); 69 void age_attach(struct device *, struct device *, void *); 70 int age_detach(struct device *, int); 71 72 int age_miibus_readreg(struct device *, int, int); 73 void age_miibus_writereg(struct device *, int, int, int); 74 void age_miibus_statchg(struct device *); 75 76 int age_init(struct ifnet *); 77 int age_ioctl(struct ifnet *, u_long, caddr_t); 78 void age_start(struct ifnet *); 79 void age_watchdog(struct ifnet *); 80 void age_mediastatus(struct ifnet *, struct ifmediareq *); 81 int age_mediachange(struct ifnet *); 82 83 int age_intr(void *); 84 int age_dma_alloc(struct age_softc *); 85 void age_dma_free(struct age_softc *); 86 void age_get_macaddr(struct age_softc *); 87 void age_phy_reset(struct age_softc *); 88 89 int age_encap(struct age_softc *, struct mbuf *); 90 void age_init_tx_ring(struct age_softc *); 91 int age_init_rx_ring(struct age_softc *); 92 void age_init_rr_ring(struct age_softc *); 93 void age_init_cmb_block(struct age_softc *); 94 void age_init_smb_block(struct age_softc *); 95 int age_newbuf(struct age_softc *, struct age_rxdesc *); 96 void age_mac_config(struct age_softc *); 97 void age_txintr(struct age_softc *, int); 98 void age_rxeof(struct age_softc *sc, struct rx_rdesc *); 99 void age_rxintr(struct age_softc *, int); 100 void age_tick(void *); 101 void age_reset(struct age_softc *); 102 void age_stop(struct age_softc *); 103 void age_stats_update(struct age_softc *); 104 void age_stop_txmac(struct age_softc *); 105 void age_stop_rxmac(struct age_softc *); 106 void age_rxvlan(struct age_softc *sc); 107 void age_iff(struct age_softc *); 108 109 const struct pci_matchid age_devices[] = { 110 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L1 } 111 }; 112 113 struct cfattach age_ca = { 114 sizeof (struct age_softc), age_match, age_attach 115 }; 116 117 struct cfdriver age_cd = { 118 NULL, "age", DV_IFNET 119 }; 120 121 int agedebug = 0; 122 #define DPRINTF(x) do { if (agedebug) printf x; } while (0) 123 124 #define AGE_CSUM_FEATURES (M_TCP_CSUM_OUT | M_UDP_CSUM_OUT) 125 126 int 127 age_match(struct device *dev, void *match, void *aux) 128 { 129 return pci_matchbyid((struct pci_attach_args *)aux, age_devices, 130 sizeof (age_devices) / sizeof (age_devices[0])); 131 } 132 133 void 134 age_attach(struct device *parent, struct device *self, void *aux) 135 { 136 struct age_softc *sc = (struct age_softc *)self; 137 struct pci_attach_args *pa = aux; 138 pci_chipset_tag_t pc = pa->pa_pc; 139 pci_intr_handle_t ih; 140 const char *intrstr; 141 struct ifnet *ifp; 142 pcireg_t memtype; 143 int error = 0; 144 145 /* 146 * Allocate IO memory 147 */ 148 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, AGE_PCIR_BAR); 149 if (pci_mapreg_map(pa, AGE_PCIR_BAR, memtype, 0, &sc->sc_mem_bt, 150 &sc->sc_mem_bh, NULL, &sc->sc_mem_size, 0)) { 151 printf(": can't map mem space\n"); 152 return; 153 } 154 155 if (pci_intr_map_msi(pa, &ih) != 0 && pci_intr_map(pa, &ih) != 0) { 156 printf(": can't map interrupt\n"); 157 goto fail; 158 } 159 160 /* 161 * Allocate IRQ 162 */ 163 intrstr = pci_intr_string(pc, ih); 164 sc->sc_irq_handle = pci_intr_establish(pc, ih, IPL_NET, age_intr, sc, 165 sc->sc_dev.dv_xname); 166 if (sc->sc_irq_handle == NULL) { 167 printf(": could not establish interrupt"); 168 if (intrstr != NULL) 169 printf(" at %s", intrstr); 170 printf("\n"); 171 goto fail; 172 } 173 printf(": %s", intrstr); 174 175 sc->sc_dmat = pa->pa_dmat; 176 sc->sc_pct = pa->pa_pc; 177 sc->sc_pcitag = pa->pa_tag; 178 179 /* Set PHY address. */ 180 sc->age_phyaddr = AGE_PHY_ADDR; 181 182 /* Reset PHY. */ 183 age_phy_reset(sc); 184 185 /* Reset the ethernet controller. */ 186 age_reset(sc); 187 188 /* Get PCI and chip id/revision. */ 189 sc->age_rev = PCI_REVISION(pa->pa_class); 190 sc->age_chip_rev = CSR_READ_4(sc, AGE_MASTER_CFG) >> 191 MASTER_CHIP_REV_SHIFT; 192 if (agedebug) { 193 printf("%s: PCI device revision : 0x%04x\n", 194 sc->sc_dev.dv_xname, sc->age_rev); 195 printf("%s: Chip id/revision : 0x%04x\n", 196 sc->sc_dev.dv_xname, sc->age_chip_rev); 197 } 198 199 if (agedebug) { 200 printf("%s: %d Tx FIFO, %d Rx FIFO\n", sc->sc_dev.dv_xname, 201 CSR_READ_4(sc, AGE_SRAM_TX_FIFO_LEN), 202 CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN)); 203 } 204 205 /* Set max allowable DMA size. */ 206 sc->age_dma_rd_burst = DMA_CFG_RD_BURST_128; 207 sc->age_dma_wr_burst = DMA_CFG_WR_BURST_128; 208 209 /* Allocate DMA stuffs */ 210 error = age_dma_alloc(sc); 211 if (error) 212 goto fail; 213 214 /* Load station address. */ 215 age_get_macaddr(sc); 216 217 ifp = &sc->sc_arpcom.ac_if; 218 ifp->if_softc = sc; 219 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 220 ifp->if_ioctl = age_ioctl; 221 ifp->if_start = age_start; 222 ifp->if_watchdog = age_watchdog; 223 ifq_set_maxlen(&ifp->if_snd, AGE_TX_RING_CNT - 1); 224 bcopy(sc->age_eaddr, sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN); 225 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 226 227 ifp->if_capabilities = IFCAP_VLAN_MTU; 228 229 #ifdef AGE_CHECKSUM 230 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 231 IFCAP_CSUM_UDPv4; 232 #endif 233 234 #if NVLAN > 0 235 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 236 #endif 237 238 printf(", address %s\n", ether_sprintf(sc->sc_arpcom.ac_enaddr)); 239 240 /* Set up MII bus. */ 241 sc->sc_miibus.mii_ifp = ifp; 242 sc->sc_miibus.mii_readreg = age_miibus_readreg; 243 sc->sc_miibus.mii_writereg = age_miibus_writereg; 244 sc->sc_miibus.mii_statchg = age_miibus_statchg; 245 246 ifmedia_init(&sc->sc_miibus.mii_media, 0, age_mediachange, 247 age_mediastatus); 248 mii_attach(self, &sc->sc_miibus, 0xffffffff, MII_PHY_ANY, 249 MII_OFFSET_ANY, MIIF_DOPAUSE); 250 251 if (LIST_FIRST(&sc->sc_miibus.mii_phys) == NULL) { 252 printf("%s: no PHY found!\n", sc->sc_dev.dv_xname); 253 ifmedia_add(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL, 254 0, NULL); 255 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL); 256 } else 257 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_AUTO); 258 259 if_attach(ifp); 260 ether_ifattach(ifp); 261 262 timeout_set(&sc->age_tick_ch, age_tick, sc); 263 264 return; 265 fail: 266 age_dma_free(sc); 267 if (sc->sc_irq_handle != NULL) 268 pci_intr_disestablish(pc, sc->sc_irq_handle); 269 if (sc->sc_mem_size) 270 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 271 } 272 273 int 274 age_detach(struct device *self, int flags) 275 { 276 struct age_softc *sc = (struct age_softc *)self; 277 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 278 int s; 279 280 s = splnet(); 281 age_stop(sc); 282 splx(s); 283 284 mii_detach(&sc->sc_miibus, MII_PHY_ANY, MII_OFFSET_ANY); 285 286 /* Delete all remaining media. */ 287 ifmedia_delete_instance(&sc->sc_miibus.mii_media, IFM_INST_ANY); 288 289 ether_ifdetach(ifp); 290 if_detach(ifp); 291 age_dma_free(sc); 292 293 if (sc->sc_irq_handle != NULL) { 294 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 295 sc->sc_irq_handle = NULL; 296 } 297 298 return (0); 299 } 300 301 /* 302 * Read a PHY register on the MII of the L1. 303 */ 304 int 305 age_miibus_readreg(struct device *dev, int phy, int reg) 306 { 307 struct age_softc *sc = (struct age_softc *)dev; 308 uint32_t v; 309 int i; 310 311 if (phy != sc->age_phyaddr) 312 return (0); 313 314 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 315 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 316 for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 317 DELAY(1); 318 v = CSR_READ_4(sc, AGE_MDIO); 319 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 320 break; 321 } 322 323 if (i == 0) { 324 printf("%s: phy read timeout: phy %d, reg %d\n", 325 sc->sc_dev.dv_xname, phy, reg); 326 return (0); 327 } 328 329 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 330 } 331 332 /* 333 * Write a PHY register on the MII of the L1. 334 */ 335 void 336 age_miibus_writereg(struct device *dev, int phy, int reg, int val) 337 { 338 struct age_softc *sc = (struct age_softc *)dev; 339 uint32_t v; 340 int i; 341 342 if (phy != sc->age_phyaddr) 343 return; 344 345 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 346 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 347 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 348 349 for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 350 DELAY(1); 351 v = CSR_READ_4(sc, AGE_MDIO); 352 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 353 break; 354 } 355 356 if (i == 0) { 357 printf("%s: phy write timeout: phy %d, reg %d\n", 358 sc->sc_dev.dv_xname, phy, reg); 359 } 360 } 361 362 /* 363 * Callback from MII layer when media changes. 364 */ 365 void 366 age_miibus_statchg(struct device *dev) 367 { 368 struct age_softc *sc = (struct age_softc *)dev; 369 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 370 struct mii_data *mii = &sc->sc_miibus; 371 372 if ((ifp->if_flags & IFF_RUNNING) == 0) 373 return; 374 375 sc->age_flags &= ~AGE_FLAG_LINK; 376 if ((mii->mii_media_status & IFM_AVALID) != 0) { 377 switch (IFM_SUBTYPE(mii->mii_media_active)) { 378 case IFM_10_T: 379 case IFM_100_TX: 380 case IFM_1000_T: 381 sc->age_flags |= AGE_FLAG_LINK; 382 break; 383 default: 384 break; 385 } 386 } 387 388 /* Stop Rx/Tx MACs. */ 389 age_stop_rxmac(sc); 390 age_stop_txmac(sc); 391 392 /* Program MACs with resolved speed/duplex/flow-control. */ 393 if ((sc->age_flags & AGE_FLAG_LINK) != 0) { 394 uint32_t reg; 395 396 age_mac_config(sc); 397 reg = CSR_READ_4(sc, AGE_MAC_CFG); 398 /* Restart DMA engine and Tx/Rx MAC. */ 399 CSR_WRITE_4(sc, AGE_DMA_CFG, CSR_READ_4(sc, AGE_DMA_CFG) | 400 DMA_CFG_RD_ENB | DMA_CFG_WR_ENB); 401 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 402 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 403 } 404 } 405 406 /* 407 * Get the current interface media status. 408 */ 409 void 410 age_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 411 { 412 struct age_softc *sc = ifp->if_softc; 413 struct mii_data *mii = &sc->sc_miibus; 414 415 mii_pollstat(mii); 416 ifmr->ifm_status = mii->mii_media_status; 417 ifmr->ifm_active = mii->mii_media_active; 418 } 419 420 /* 421 * Set hardware to newly-selected media. 422 */ 423 int 424 age_mediachange(struct ifnet *ifp) 425 { 426 struct age_softc *sc = ifp->if_softc; 427 struct mii_data *mii = &sc->sc_miibus; 428 int error; 429 430 if (mii->mii_instance != 0) { 431 struct mii_softc *miisc; 432 433 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 434 mii_phy_reset(miisc); 435 } 436 error = mii_mediachg(mii); 437 438 return (error); 439 } 440 441 int 442 age_intr(void *arg) 443 { 444 struct age_softc *sc = arg; 445 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 446 struct cmb *cmb; 447 uint32_t status; 448 449 status = CSR_READ_4(sc, AGE_INTR_STATUS); 450 if (status == 0 || (status & AGE_INTRS) == 0) 451 return (0); 452 453 /* Disable interrupts. */ 454 CSR_WRITE_4(sc, AGE_INTR_STATUS, status | INTR_DIS_INT); 455 456 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 457 sc->age_cdata.age_cmb_block_map->dm_mapsize, 458 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 459 cmb = sc->age_rdata.age_cmb_block; 460 status = letoh32(cmb->intr_status); 461 if ((status & AGE_INTRS) == 0) 462 goto back; 463 464 sc->age_tpd_cons = (letoh32(cmb->tpd_cons) & TPD_CONS_MASK) >> 465 TPD_CONS_SHIFT; 466 sc->age_rr_prod = (letoh32(cmb->rprod_cons) & RRD_PROD_MASK) >> 467 RRD_PROD_SHIFT; 468 /* Let hardware know CMB was served. */ 469 cmb->intr_status = 0; 470 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 471 sc->age_cdata.age_cmb_block_map->dm_mapsize, 472 BUS_DMASYNC_PREWRITE); 473 474 if (ifp->if_flags & IFF_RUNNING) { 475 if (status & INTR_CMB_RX) 476 age_rxintr(sc, sc->age_rr_prod); 477 478 if (status & INTR_CMB_TX) 479 age_txintr(sc, sc->age_tpd_cons); 480 481 if (status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) { 482 if (status & INTR_DMA_RD_TO_RST) 483 printf("%s: DMA read error! -- resetting\n", 484 sc->sc_dev.dv_xname); 485 if (status & INTR_DMA_WR_TO_RST) 486 printf("%s: DMA write error! -- resetting\n", 487 sc->sc_dev.dv_xname); 488 age_init(ifp); 489 } 490 491 age_start(ifp); 492 493 if (status & INTR_SMB) 494 age_stats_update(sc); 495 } 496 497 /* Check whether CMB was updated while serving Tx/Rx/SMB handler. */ 498 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 499 sc->age_cdata.age_cmb_block_map->dm_mapsize, 500 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 501 502 back: 503 /* Re-enable interrupts. */ 504 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); 505 506 return (1); 507 } 508 509 void 510 age_get_macaddr(struct age_softc *sc) 511 { 512 uint32_t ea[2], reg; 513 int i, vpdc; 514 515 reg = CSR_READ_4(sc, AGE_SPI_CTRL); 516 if ((reg & SPI_VPD_ENB) != 0) { 517 /* Get VPD stored in TWSI EEPROM. */ 518 reg &= ~SPI_VPD_ENB; 519 CSR_WRITE_4(sc, AGE_SPI_CTRL, reg); 520 } 521 522 if (pci_get_capability(sc->sc_pct, sc->sc_pcitag, 523 PCI_CAP_VPD, &vpdc, NULL)) { 524 /* 525 * PCI VPD capability found, let TWSI reload EEPROM. 526 * This will set Ethernet address of controller. 527 */ 528 CSR_WRITE_4(sc, AGE_TWSI_CTRL, CSR_READ_4(sc, AGE_TWSI_CTRL) | 529 TWSI_CTRL_SW_LD_START); 530 for (i = 100; i > 0; i--) { 531 DELAY(1000); 532 reg = CSR_READ_4(sc, AGE_TWSI_CTRL); 533 if ((reg & TWSI_CTRL_SW_LD_START) == 0) 534 break; 535 } 536 if (i == 0) 537 printf("%s: reloading EEPROM timeout!\n", 538 sc->sc_dev.dv_xname); 539 } else { 540 if (agedebug) 541 printf("%s: PCI VPD capability not found!\n", 542 sc->sc_dev.dv_xname); 543 } 544 545 ea[0] = CSR_READ_4(sc, AGE_PAR0); 546 ea[1] = CSR_READ_4(sc, AGE_PAR1); 547 sc->age_eaddr[0] = (ea[1] >> 8) & 0xFF; 548 sc->age_eaddr[1] = (ea[1] >> 0) & 0xFF; 549 sc->age_eaddr[2] = (ea[0] >> 24) & 0xFF; 550 sc->age_eaddr[3] = (ea[0] >> 16) & 0xFF; 551 sc->age_eaddr[4] = (ea[0] >> 8) & 0xFF; 552 sc->age_eaddr[5] = (ea[0] >> 0) & 0xFF; 553 } 554 555 void 556 age_phy_reset(struct age_softc *sc) 557 { 558 uint16_t reg, pn; 559 int i, linkup; 560 561 /* Reset PHY. */ 562 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_RST); 563 DELAY(2000); 564 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_CLR); 565 DELAY(2000); 566 567 #define ATPHY_DBG_ADDR 0x1D 568 #define ATPHY_DBG_DATA 0x1E 569 #define ATPHY_CDTC 0x16 570 #define PHY_CDTC_ENB 0x0001 571 #define PHY_CDTC_POFF 8 572 #define ATPHY_CDTS 0x1C 573 #define PHY_CDTS_STAT_OK 0x0000 574 #define PHY_CDTS_STAT_SHORT 0x0100 575 #define PHY_CDTS_STAT_OPEN 0x0200 576 #define PHY_CDTS_STAT_INVAL 0x0300 577 #define PHY_CDTS_STAT_MASK 0x0300 578 579 /* Check power saving mode. Magic from Linux. */ 580 age_miibus_writereg(&sc->sc_dev, sc->age_phyaddr, MII_BMCR, BMCR_RESET); 581 for (linkup = 0, pn = 0; pn < 4; pn++) { 582 age_miibus_writereg(&sc->sc_dev, sc->age_phyaddr, ATPHY_CDTC, 583 (pn << PHY_CDTC_POFF) | PHY_CDTC_ENB); 584 for (i = 200; i > 0; i--) { 585 DELAY(1000); 586 reg = age_miibus_readreg(&sc->sc_dev, sc->age_phyaddr, 587 ATPHY_CDTC); 588 if ((reg & PHY_CDTC_ENB) == 0) 589 break; 590 } 591 DELAY(1000); 592 reg = age_miibus_readreg(&sc->sc_dev, sc->age_phyaddr, 593 ATPHY_CDTS); 594 if ((reg & PHY_CDTS_STAT_MASK) != PHY_CDTS_STAT_OPEN) { 595 linkup++; 596 break; 597 } 598 } 599 age_miibus_writereg(&sc->sc_dev, sc->age_phyaddr, MII_BMCR, 600 BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 601 if (linkup == 0) { 602 age_miibus_writereg(&sc->sc_dev, sc->age_phyaddr, 603 ATPHY_DBG_ADDR, 0); 604 age_miibus_writereg(&sc->sc_dev, sc->age_phyaddr, 605 ATPHY_DBG_DATA, 0x124E); 606 age_miibus_writereg(&sc->sc_dev, sc->age_phyaddr, 607 ATPHY_DBG_ADDR, 1); 608 reg = age_miibus_readreg(&sc->sc_dev, sc->age_phyaddr, 609 ATPHY_DBG_DATA); 610 age_miibus_writereg(&sc->sc_dev, sc->age_phyaddr, 611 ATPHY_DBG_DATA, reg | 0x03); 612 /* XXX */ 613 DELAY(1500 * 1000); 614 age_miibus_writereg(&sc->sc_dev, sc->age_phyaddr, 615 ATPHY_DBG_ADDR, 0); 616 age_miibus_writereg(&sc->sc_dev, sc->age_phyaddr, 617 ATPHY_DBG_DATA, 0x024E); 618 } 619 620 #undef ATPHY_DBG_ADDR 621 #undef ATPHY_DBG_DATA 622 #undef ATPHY_CDTC 623 #undef PHY_CDTC_ENB 624 #undef PHY_CDTC_POFF 625 #undef ATPHY_CDTS 626 #undef PHY_CDTS_STAT_OK 627 #undef PHY_CDTS_STAT_SHORT 628 #undef PHY_CDTS_STAT_OPEN 629 #undef PHY_CDTS_STAT_INVAL 630 #undef PHY_CDTS_STAT_MASK 631 } 632 633 int 634 age_dma_alloc(struct age_softc *sc) 635 { 636 struct age_txdesc *txd; 637 struct age_rxdesc *rxd; 638 int nsegs, error, i; 639 640 /* 641 * Create DMA stuffs for TX ring 642 */ 643 error = bus_dmamap_create(sc->sc_dmat, AGE_TX_RING_SZ, 1, 644 AGE_TX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->age_cdata.age_tx_ring_map); 645 if (error) 646 return (ENOBUFS); 647 648 /* Allocate DMA'able memory for TX ring */ 649 error = bus_dmamem_alloc(sc->sc_dmat, AGE_TX_RING_SZ, 650 ETHER_ALIGN, 0, &sc->age_rdata.age_tx_ring_seg, 1, 651 &nsegs, BUS_DMA_WAITOK | BUS_DMA_ZERO); 652 if (error) { 653 printf("%s: could not allocate DMA'able memory for Tx ring.\n", 654 sc->sc_dev.dv_xname); 655 return error; 656 } 657 658 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_tx_ring_seg, 659 nsegs, AGE_TX_RING_SZ, (caddr_t *)&sc->age_rdata.age_tx_ring, 660 BUS_DMA_NOWAIT); 661 if (error) 662 return (ENOBUFS); 663 664 /* Load the DMA map for Tx ring. */ 665 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 666 sc->age_rdata.age_tx_ring, AGE_TX_RING_SZ, NULL, BUS_DMA_WAITOK); 667 if (error) { 668 printf("%s: could not load DMA'able memory for Tx ring.\n", 669 sc->sc_dev.dv_xname); 670 bus_dmamem_free(sc->sc_dmat, 671 (bus_dma_segment_t *)&sc->age_rdata.age_tx_ring, 1); 672 return error; 673 } 674 675 sc->age_rdata.age_tx_ring_paddr = 676 sc->age_cdata.age_tx_ring_map->dm_segs[0].ds_addr; 677 678 /* 679 * Create DMA stuffs for RX ring 680 */ 681 error = bus_dmamap_create(sc->sc_dmat, AGE_RX_RING_SZ, 1, 682 AGE_RX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->age_cdata.age_rx_ring_map); 683 if (error) 684 return (ENOBUFS); 685 686 /* Allocate DMA'able memory for RX ring */ 687 error = bus_dmamem_alloc(sc->sc_dmat, AGE_RX_RING_SZ, 688 ETHER_ALIGN, 0, &sc->age_rdata.age_rx_ring_seg, 1, 689 &nsegs, BUS_DMA_WAITOK | BUS_DMA_ZERO); 690 if (error) { 691 printf("%s: could not allocate DMA'able memory for Rx ring.\n", 692 sc->sc_dev.dv_xname); 693 return error; 694 } 695 696 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_rx_ring_seg, 697 nsegs, AGE_RX_RING_SZ, (caddr_t *)&sc->age_rdata.age_rx_ring, 698 BUS_DMA_NOWAIT); 699 if (error) 700 return (ENOBUFS); 701 702 /* Load the DMA map for Rx ring. */ 703 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_rx_ring_map, 704 sc->age_rdata.age_rx_ring, AGE_RX_RING_SZ, NULL, BUS_DMA_WAITOK); 705 if (error) { 706 printf("%s: could not load DMA'able memory for Rx ring.\n", 707 sc->sc_dev.dv_xname); 708 bus_dmamem_free(sc->sc_dmat, 709 (bus_dma_segment_t *)sc->age_rdata.age_rx_ring, 1); 710 return error; 711 } 712 713 sc->age_rdata.age_rx_ring_paddr = 714 sc->age_cdata.age_rx_ring_map->dm_segs[0].ds_addr; 715 716 /* 717 * Create DMA stuffs for RX return ring 718 */ 719 error = bus_dmamap_create(sc->sc_dmat, AGE_RR_RING_SZ, 1, 720 AGE_RR_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->age_cdata.age_rr_ring_map); 721 if (error) 722 return (ENOBUFS); 723 724 /* Allocate DMA'able memory for RX return ring */ 725 error = bus_dmamem_alloc(sc->sc_dmat, AGE_RR_RING_SZ, 726 ETHER_ALIGN, 0, &sc->age_rdata.age_rr_ring_seg, 1, 727 &nsegs, BUS_DMA_WAITOK | BUS_DMA_ZERO); 728 if (error) { 729 printf("%s: could not allocate DMA'able memory for Rx " 730 "return ring.\n", sc->sc_dev.dv_xname); 731 return error; 732 } 733 734 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_rr_ring_seg, 735 nsegs, AGE_RR_RING_SZ, (caddr_t *)&sc->age_rdata.age_rr_ring, 736 BUS_DMA_NOWAIT); 737 if (error) 738 return (ENOBUFS); 739 740 /* Load the DMA map for Rx return ring. */ 741 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 742 sc->age_rdata.age_rr_ring, AGE_RR_RING_SZ, NULL, BUS_DMA_WAITOK); 743 if (error) { 744 printf("%s: could not load DMA'able memory for Rx return ring." 745 "\n", sc->sc_dev.dv_xname); 746 bus_dmamem_free(sc->sc_dmat, 747 (bus_dma_segment_t *)&sc->age_rdata.age_rr_ring, 1); 748 return error; 749 } 750 751 sc->age_rdata.age_rr_ring_paddr = 752 sc->age_cdata.age_rr_ring_map->dm_segs[0].ds_addr; 753 754 /* 755 * Create DMA stuffs for CMB block 756 */ 757 error = bus_dmamap_create(sc->sc_dmat, AGE_CMB_BLOCK_SZ, 1, 758 AGE_CMB_BLOCK_SZ, 0, BUS_DMA_NOWAIT, 759 &sc->age_cdata.age_cmb_block_map); 760 if (error) 761 return (ENOBUFS); 762 763 /* Allocate DMA'able memory for CMB block */ 764 error = bus_dmamem_alloc(sc->sc_dmat, AGE_CMB_BLOCK_SZ, 765 ETHER_ALIGN, 0, &sc->age_rdata.age_cmb_block_seg, 1, 766 &nsegs, BUS_DMA_WAITOK | BUS_DMA_ZERO); 767 if (error) { 768 printf("%s: could not allocate DMA'able memory for " 769 "CMB block\n", sc->sc_dev.dv_xname); 770 return error; 771 } 772 773 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_cmb_block_seg, 774 nsegs, AGE_CMB_BLOCK_SZ, (caddr_t *)&sc->age_rdata.age_cmb_block, 775 BUS_DMA_NOWAIT); 776 if (error) 777 return (ENOBUFS); 778 779 /* Load the DMA map for CMB block. */ 780 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 781 sc->age_rdata.age_cmb_block, AGE_CMB_BLOCK_SZ, NULL, 782 BUS_DMA_WAITOK); 783 if (error) { 784 printf("%s: could not load DMA'able memory for CMB block\n", 785 sc->sc_dev.dv_xname); 786 bus_dmamem_free(sc->sc_dmat, 787 (bus_dma_segment_t *)&sc->age_rdata.age_cmb_block, 1); 788 return error; 789 } 790 791 sc->age_rdata.age_cmb_block_paddr = 792 sc->age_cdata.age_cmb_block_map->dm_segs[0].ds_addr; 793 794 /* 795 * Create DMA stuffs for SMB block 796 */ 797 error = bus_dmamap_create(sc->sc_dmat, AGE_SMB_BLOCK_SZ, 1, 798 AGE_SMB_BLOCK_SZ, 0, BUS_DMA_NOWAIT, 799 &sc->age_cdata.age_smb_block_map); 800 if (error) 801 return (ENOBUFS); 802 803 /* Allocate DMA'able memory for SMB block */ 804 error = bus_dmamem_alloc(sc->sc_dmat, AGE_SMB_BLOCK_SZ, 805 ETHER_ALIGN, 0, &sc->age_rdata.age_smb_block_seg, 1, 806 &nsegs, BUS_DMA_WAITOK | BUS_DMA_ZERO); 807 if (error) { 808 printf("%s: could not allocate DMA'able memory for " 809 "SMB block\n", sc->sc_dev.dv_xname); 810 return error; 811 } 812 813 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_smb_block_seg, 814 nsegs, AGE_SMB_BLOCK_SZ, (caddr_t *)&sc->age_rdata.age_smb_block, 815 BUS_DMA_NOWAIT); 816 if (error) 817 return (ENOBUFS); 818 819 /* Load the DMA map for SMB block */ 820 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 821 sc->age_rdata.age_smb_block, AGE_SMB_BLOCK_SZ, NULL, 822 BUS_DMA_WAITOK); 823 if (error) { 824 printf("%s: could not load DMA'able memory for SMB block\n", 825 sc->sc_dev.dv_xname); 826 bus_dmamem_free(sc->sc_dmat, 827 (bus_dma_segment_t *)&sc->age_rdata.age_smb_block, 1); 828 return error; 829 } 830 831 sc->age_rdata.age_smb_block_paddr = 832 sc->age_cdata.age_smb_block_map->dm_segs[0].ds_addr; 833 834 /* Create DMA maps for Tx buffers. */ 835 for (i = 0; i < AGE_TX_RING_CNT; i++) { 836 txd = &sc->age_cdata.age_txdesc[i]; 837 txd->tx_m = NULL; 838 txd->tx_dmamap = NULL; 839 error = bus_dmamap_create(sc->sc_dmat, AGE_TSO_MAXSIZE, 840 AGE_MAXTXSEGS, AGE_TSO_MAXSEGSIZE, 0, BUS_DMA_NOWAIT, 841 &txd->tx_dmamap); 842 if (error) { 843 printf("%s: could not create Tx dmamap.\n", 844 sc->sc_dev.dv_xname); 845 return error; 846 } 847 } 848 849 /* Create DMA maps for Rx buffers. */ 850 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 851 BUS_DMA_NOWAIT, &sc->age_cdata.age_rx_sparemap); 852 if (error) { 853 printf("%s: could not create spare Rx dmamap.\n", 854 sc->sc_dev.dv_xname); 855 return error; 856 } 857 for (i = 0; i < AGE_RX_RING_CNT; i++) { 858 rxd = &sc->age_cdata.age_rxdesc[i]; 859 rxd->rx_m = NULL; 860 rxd->rx_dmamap = NULL; 861 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 862 MCLBYTES, 0, BUS_DMA_NOWAIT, &rxd->rx_dmamap); 863 if (error) { 864 printf("%s: could not create Rx dmamap.\n", 865 sc->sc_dev.dv_xname); 866 return error; 867 } 868 } 869 870 return (0); 871 } 872 873 void 874 age_dma_free(struct age_softc *sc) 875 { 876 struct age_txdesc *txd; 877 struct age_rxdesc *rxd; 878 int i; 879 880 /* Tx buffers */ 881 for (i = 0; i < AGE_TX_RING_CNT; i++) { 882 txd = &sc->age_cdata.age_txdesc[i]; 883 if (txd->tx_dmamap != NULL) { 884 bus_dmamap_destroy(sc->sc_dmat, txd->tx_dmamap); 885 txd->tx_dmamap = NULL; 886 } 887 } 888 /* Rx buffers */ 889 for (i = 0; i < AGE_RX_RING_CNT; i++) { 890 rxd = &sc->age_cdata.age_rxdesc[i]; 891 if (rxd->rx_dmamap != NULL) { 892 bus_dmamap_destroy(sc->sc_dmat, rxd->rx_dmamap); 893 rxd->rx_dmamap = NULL; 894 } 895 } 896 if (sc->age_cdata.age_rx_sparemap != NULL) { 897 bus_dmamap_destroy(sc->sc_dmat, sc->age_cdata.age_rx_sparemap); 898 sc->age_cdata.age_rx_sparemap = NULL; 899 } 900 901 /* Tx ring. */ 902 if (sc->age_cdata.age_tx_ring_map != NULL) 903 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_tx_ring_map); 904 if (sc->age_cdata.age_tx_ring_map != NULL && 905 sc->age_rdata.age_tx_ring != NULL) 906 bus_dmamem_free(sc->sc_dmat, 907 (bus_dma_segment_t *)sc->age_rdata.age_tx_ring, 1); 908 sc->age_rdata.age_tx_ring = NULL; 909 sc->age_cdata.age_tx_ring_map = NULL; 910 911 /* Rx ring. */ 912 if (sc->age_cdata.age_rx_ring_map != NULL) 913 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_rx_ring_map); 914 if (sc->age_cdata.age_rx_ring_map != NULL && 915 sc->age_rdata.age_rx_ring != NULL) 916 bus_dmamem_free(sc->sc_dmat, 917 (bus_dma_segment_t *)sc->age_rdata.age_rx_ring, 1); 918 sc->age_rdata.age_rx_ring = NULL; 919 sc->age_cdata.age_rx_ring_map = NULL; 920 921 /* Rx return ring. */ 922 if (sc->age_cdata.age_rr_ring_map != NULL) 923 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_rr_ring_map); 924 if (sc->age_cdata.age_rr_ring_map != NULL && 925 sc->age_rdata.age_rr_ring != NULL) 926 bus_dmamem_free(sc->sc_dmat, 927 (bus_dma_segment_t *)sc->age_rdata.age_rr_ring, 1); 928 sc->age_rdata.age_rr_ring = NULL; 929 sc->age_cdata.age_rr_ring_map = NULL; 930 931 /* CMB block */ 932 if (sc->age_cdata.age_cmb_block_map != NULL) 933 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_cmb_block_map); 934 if (sc->age_cdata.age_cmb_block_map != NULL && 935 sc->age_rdata.age_cmb_block != NULL) 936 bus_dmamem_free(sc->sc_dmat, 937 (bus_dma_segment_t *)sc->age_rdata.age_cmb_block, 1); 938 sc->age_rdata.age_cmb_block = NULL; 939 sc->age_cdata.age_cmb_block_map = NULL; 940 941 /* SMB block */ 942 if (sc->age_cdata.age_smb_block_map != NULL) 943 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_smb_block_map); 944 if (sc->age_cdata.age_smb_block_map != NULL && 945 sc->age_rdata.age_smb_block != NULL) 946 bus_dmamem_free(sc->sc_dmat, 947 (bus_dma_segment_t *)sc->age_rdata.age_smb_block, 1); 948 sc->age_rdata.age_smb_block = NULL; 949 sc->age_cdata.age_smb_block_map = NULL; 950 } 951 952 void 953 age_start(struct ifnet *ifp) 954 { 955 struct age_softc *sc = ifp->if_softc; 956 struct mbuf *m; 957 int enq; 958 959 if (!(ifp->if_flags & IFF_RUNNING) || ifq_is_oactive(&ifp->if_snd)) 960 return; 961 if ((sc->age_flags & AGE_FLAG_LINK) == 0) 962 return; 963 if (ifq_empty(&ifp->if_snd)) 964 return; 965 966 enq = 0; 967 for (;;) { 968 if (sc->age_cdata.age_tx_cnt + AGE_MAXTXSEGS >= 969 AGE_TX_RING_CNT - 2) { 970 ifq_set_oactive(&ifp->if_snd); 971 break; 972 } 973 974 m = ifq_dequeue(&ifp->if_snd); 975 if (m == NULL) 976 break; 977 978 /* 979 * Pack the data into the transmit ring. If we 980 * don't have room, set the OACTIVE flag and wait 981 * for the NIC to drain the ring. 982 */ 983 if (age_encap(sc, m) != 0) { 984 ifp->if_oerrors++; 985 continue; 986 } 987 enq = 1; 988 989 #if NBPFILTER > 0 990 /* 991 * If there's a BPF listener, bounce a copy of this frame 992 * to him. 993 */ 994 if (ifp->if_bpf != NULL) 995 bpf_mtap_ether(ifp->if_bpf, m, BPF_DIRECTION_OUT); 996 #endif 997 } 998 999 if (enq) { 1000 /* Update mbox. */ 1001 AGE_COMMIT_MBOX(sc); 1002 /* Set a timeout in case the chip goes out to lunch. */ 1003 ifp->if_timer = AGE_TX_TIMEOUT; 1004 } 1005 } 1006 1007 void 1008 age_watchdog(struct ifnet *ifp) 1009 { 1010 struct age_softc *sc = ifp->if_softc; 1011 1012 if ((sc->age_flags & AGE_FLAG_LINK) == 0) { 1013 printf("%s: watchdog timeout (missed link)\n", 1014 sc->sc_dev.dv_xname); 1015 ifp->if_oerrors++; 1016 age_init(ifp); 1017 return; 1018 } 1019 1020 if (sc->age_cdata.age_tx_cnt == 0) { 1021 printf("%s: watchdog timeout (missed Tx interrupts) " 1022 "-- recovering\n", sc->sc_dev.dv_xname); 1023 age_start(ifp); 1024 return; 1025 } 1026 1027 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 1028 ifp->if_oerrors++; 1029 age_init(ifp); 1030 age_start(ifp); 1031 } 1032 1033 int 1034 age_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1035 { 1036 struct age_softc *sc = ifp->if_softc; 1037 struct mii_data *mii = &sc->sc_miibus; 1038 struct ifreq *ifr = (struct ifreq *)data; 1039 int s, error = 0; 1040 1041 s = splnet(); 1042 1043 switch (cmd) { 1044 case SIOCSIFADDR: 1045 ifp->if_flags |= IFF_UP; 1046 if (!(ifp->if_flags & IFF_RUNNING)) 1047 age_init(ifp); 1048 break; 1049 1050 case SIOCSIFFLAGS: 1051 if (ifp->if_flags & IFF_UP) { 1052 if (ifp->if_flags & IFF_RUNNING) 1053 error = ENETRESET; 1054 else 1055 age_init(ifp); 1056 } else { 1057 if (ifp->if_flags & IFF_RUNNING) 1058 age_stop(sc); 1059 } 1060 break; 1061 1062 case SIOCSIFMEDIA: 1063 case SIOCGIFMEDIA: 1064 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1065 break; 1066 1067 default: 1068 error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data); 1069 break; 1070 } 1071 1072 if (error == ENETRESET) { 1073 if (ifp->if_flags & IFF_RUNNING) 1074 age_iff(sc); 1075 error = 0; 1076 } 1077 1078 splx(s); 1079 return (error); 1080 } 1081 1082 void 1083 age_mac_config(struct age_softc *sc) 1084 { 1085 struct mii_data *mii = &sc->sc_miibus; 1086 uint32_t reg; 1087 1088 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1089 reg &= ~MAC_CFG_FULL_DUPLEX; 1090 reg &= ~(MAC_CFG_TX_FC | MAC_CFG_RX_FC); 1091 reg &= ~MAC_CFG_SPEED_MASK; 1092 1093 /* Reprogram MAC with resolved speed/duplex. */ 1094 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1095 case IFM_10_T: 1096 case IFM_100_TX: 1097 reg |= MAC_CFG_SPEED_10_100; 1098 break; 1099 case IFM_1000_T: 1100 reg |= MAC_CFG_SPEED_1000; 1101 break; 1102 } 1103 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1104 reg |= MAC_CFG_FULL_DUPLEX; 1105 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1106 reg |= MAC_CFG_TX_FC; 1107 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1108 reg |= MAC_CFG_RX_FC; 1109 } 1110 1111 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1112 } 1113 1114 int 1115 age_encap(struct age_softc *sc, struct mbuf *m) 1116 { 1117 struct age_txdesc *txd, *txd_last; 1118 struct tx_desc *desc; 1119 bus_dmamap_t map; 1120 uint32_t cflags, poff, vtag; 1121 int error, i, prod; 1122 1123 cflags = vtag = 0; 1124 poff = 0; 1125 1126 prod = sc->age_cdata.age_tx_prod; 1127 txd = &sc->age_cdata.age_txdesc[prod]; 1128 txd_last = txd; 1129 map = txd->tx_dmamap; 1130 1131 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, BUS_DMA_NOWAIT); 1132 if (error != 0 && error != EFBIG) 1133 goto drop; 1134 if (error != 0) { 1135 if (m_defrag(m, M_DONTWAIT)) { 1136 error = ENOBUFS; 1137 goto drop; 1138 } 1139 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1140 BUS_DMA_NOWAIT); 1141 if (error != 0) 1142 goto drop; 1143 } 1144 1145 /* Configure Tx IP/TCP/UDP checksum offload. */ 1146 if ((m->m_pkthdr.csum_flags & AGE_CSUM_FEATURES) != 0) { 1147 cflags |= AGE_TD_CSUM; 1148 if ((m->m_pkthdr.csum_flags & M_TCP_CSUM_OUT) != 0) 1149 cflags |= AGE_TD_TCPCSUM; 1150 if ((m->m_pkthdr.csum_flags & M_UDP_CSUM_OUT) != 0) 1151 cflags |= AGE_TD_UDPCSUM; 1152 /* Set checksum start offset. */ 1153 cflags |= (poff << AGE_TD_CSUM_PLOADOFFSET_SHIFT); 1154 } 1155 1156 #if NVLAN > 0 1157 /* Configure VLAN hardware tag insertion. */ 1158 if (m->m_flags & M_VLANTAG) { 1159 vtag = AGE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag); 1160 vtag = ((vtag << AGE_TD_VLAN_SHIFT) & AGE_TD_VLAN_MASK); 1161 cflags |= AGE_TD_INSERT_VLAN_TAG; 1162 } 1163 #endif 1164 1165 desc = NULL; 1166 for (i = 0; i < map->dm_nsegs; i++) { 1167 desc = &sc->age_rdata.age_tx_ring[prod]; 1168 desc->addr = htole64(map->dm_segs[i].ds_addr); 1169 desc->len = 1170 htole32(AGE_TX_BYTES(map->dm_segs[i].ds_len) | vtag); 1171 desc->flags = htole32(cflags); 1172 sc->age_cdata.age_tx_cnt++; 1173 AGE_DESC_INC(prod, AGE_TX_RING_CNT); 1174 } 1175 1176 /* Update producer index. */ 1177 sc->age_cdata.age_tx_prod = prod; 1178 1179 /* Set EOP on the last descriptor. */ 1180 prod = (prod + AGE_TX_RING_CNT - 1) % AGE_TX_RING_CNT; 1181 desc = &sc->age_rdata.age_tx_ring[prod]; 1182 desc->flags |= htole32(AGE_TD_EOP); 1183 1184 /* Swap dmamap of the first and the last. */ 1185 txd = &sc->age_cdata.age_txdesc[prod]; 1186 map = txd_last->tx_dmamap; 1187 txd_last->tx_dmamap = txd->tx_dmamap; 1188 txd->tx_dmamap = map; 1189 txd->tx_m = m; 1190 1191 /* Sync descriptors. */ 1192 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1193 BUS_DMASYNC_PREWRITE); 1194 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 0, 1195 sc->age_cdata.age_tx_ring_map->dm_mapsize, 1196 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1197 1198 return (0); 1199 1200 drop: 1201 m_freem(m); 1202 return (error); 1203 } 1204 1205 void 1206 age_txintr(struct age_softc *sc, int tpd_cons) 1207 { 1208 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1209 struct age_txdesc *txd; 1210 int cons, prog; 1211 1212 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 0, 1213 sc->age_cdata.age_tx_ring_map->dm_mapsize, 1214 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1215 1216 /* 1217 * Go through our Tx list and free mbufs for those 1218 * frames which have been transmitted. 1219 */ 1220 cons = sc->age_cdata.age_tx_cons; 1221 for (prog = 0; cons != tpd_cons; AGE_DESC_INC(cons, AGE_TX_RING_CNT)) { 1222 if (sc->age_cdata.age_tx_cnt <= 0) 1223 break; 1224 prog++; 1225 ifq_clr_oactive(&ifp->if_snd); 1226 sc->age_cdata.age_tx_cnt--; 1227 txd = &sc->age_cdata.age_txdesc[cons]; 1228 /* 1229 * Clear Tx descriptors, it's not required but would 1230 * help debugging in case of Tx issues. 1231 */ 1232 txd->tx_desc->addr = 0; 1233 txd->tx_desc->len = 0; 1234 txd->tx_desc->flags = 0; 1235 1236 if (txd->tx_m == NULL) 1237 continue; 1238 /* Reclaim transmitted mbufs. */ 1239 bus_dmamap_sync(sc->sc_dmat, txd->tx_dmamap, 0, 1240 txd->tx_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1241 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1242 m_freem(txd->tx_m); 1243 txd->tx_m = NULL; 1244 } 1245 1246 if (prog > 0) { 1247 sc->age_cdata.age_tx_cons = cons; 1248 1249 /* 1250 * Unarm watchdog timer only when there are no pending 1251 * Tx descriptors in queue. 1252 */ 1253 if (sc->age_cdata.age_tx_cnt == 0) 1254 ifp->if_timer = 0; 1255 1256 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 0, 1257 sc->age_cdata.age_tx_ring_map->dm_mapsize, 1258 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1259 } 1260 } 1261 1262 /* Receive a frame. */ 1263 void 1264 age_rxeof(struct age_softc *sc, struct rx_rdesc *rxrd) 1265 { 1266 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1267 struct age_rxdesc *rxd; 1268 struct rx_desc *desc; 1269 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 1270 struct mbuf *mp, *m; 1271 uint32_t status, index; 1272 int count, nsegs, pktlen; 1273 int rx_cons; 1274 1275 status = letoh32(rxrd->flags); 1276 index = letoh32(rxrd->index); 1277 rx_cons = AGE_RX_CONS(index); 1278 nsegs = AGE_RX_NSEGS(index); 1279 1280 sc->age_cdata.age_rxlen = AGE_RX_BYTES(letoh32(rxrd->len)); 1281 if ((status & AGE_RRD_ERROR) != 0 && 1282 (status & (AGE_RRD_CRC | AGE_RRD_CODE | AGE_RRD_DRIBBLE | 1283 AGE_RRD_RUNT | AGE_RRD_OFLOW | AGE_RRD_TRUNC)) != 0) { 1284 /* 1285 * We want to pass the following frames to upper 1286 * layer regardless of error status of Rx return 1287 * ring. 1288 * 1289 * o IP/TCP/UDP checksum is bad. 1290 * o frame length and protocol specific length 1291 * does not match. 1292 */ 1293 sc->age_cdata.age_rx_cons += nsegs; 1294 sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT; 1295 return; 1296 } 1297 1298 pktlen = 0; 1299 for (count = 0; count < nsegs; count++, 1300 AGE_DESC_INC(rx_cons, AGE_RX_RING_CNT)) { 1301 rxd = &sc->age_cdata.age_rxdesc[rx_cons]; 1302 mp = rxd->rx_m; 1303 desc = rxd->rx_desc; 1304 /* Add a new receive buffer to the ring. */ 1305 if (age_newbuf(sc, rxd) != 0) { 1306 ifp->if_iqdrops++; 1307 /* Reuse Rx buffers. */ 1308 if (sc->age_cdata.age_rxhead != NULL) { 1309 m_freem(sc->age_cdata.age_rxhead); 1310 AGE_RXCHAIN_RESET(sc); 1311 } 1312 break; 1313 } 1314 1315 /* The length of the first mbuf is computed last. */ 1316 if (count != 0) { 1317 mp->m_len = AGE_RX_BYTES(letoh32(desc->len)); 1318 pktlen += mp->m_len; 1319 } 1320 1321 /* Chain received mbufs. */ 1322 if (sc->age_cdata.age_rxhead == NULL) { 1323 sc->age_cdata.age_rxhead = mp; 1324 sc->age_cdata.age_rxtail = mp; 1325 } else { 1326 mp->m_flags &= ~M_PKTHDR; 1327 sc->age_cdata.age_rxprev_tail = 1328 sc->age_cdata.age_rxtail; 1329 sc->age_cdata.age_rxtail->m_next = mp; 1330 sc->age_cdata.age_rxtail = mp; 1331 } 1332 1333 if (count == nsegs - 1) { 1334 /* 1335 * It seems that L1 controller has no way 1336 * to tell hardware to strip CRC bytes. 1337 */ 1338 sc->age_cdata.age_rxlen -= ETHER_CRC_LEN; 1339 if (nsegs > 1) { 1340 /* Remove the CRC bytes in chained mbufs. */ 1341 pktlen -= ETHER_CRC_LEN; 1342 if (mp->m_len <= ETHER_CRC_LEN) { 1343 sc->age_cdata.age_rxtail = 1344 sc->age_cdata.age_rxprev_tail; 1345 sc->age_cdata.age_rxtail->m_len -= 1346 (ETHER_CRC_LEN - mp->m_len); 1347 sc->age_cdata.age_rxtail->m_next = NULL; 1348 m_freem(mp); 1349 } else { 1350 mp->m_len -= ETHER_CRC_LEN; 1351 } 1352 } 1353 1354 m = sc->age_cdata.age_rxhead; 1355 m->m_flags |= M_PKTHDR; 1356 m->m_pkthdr.len = sc->age_cdata.age_rxlen; 1357 /* Set the first mbuf length. */ 1358 m->m_len = sc->age_cdata.age_rxlen - pktlen; 1359 1360 /* 1361 * Set checksum information. 1362 * It seems that L1 controller can compute partial 1363 * checksum. The partial checksum value can be used 1364 * to accelerate checksum computation for fragmented 1365 * TCP/UDP packets. Upper network stack already 1366 * takes advantage of the partial checksum value in 1367 * IP reassembly stage. But I'm not sure the 1368 * correctness of the partial hardware checksum 1369 * assistance due to lack of data sheet. If it is 1370 * proven to work on L1 I'll enable it. 1371 */ 1372 if (status & AGE_RRD_IPV4) { 1373 if ((status & AGE_RRD_IPCSUM_NOK) == 0) 1374 m->m_pkthdr.csum_flags |= 1375 M_IPV4_CSUM_IN_OK; 1376 if ((status & (AGE_RRD_TCP | AGE_RRD_UDP)) && 1377 (status & AGE_RRD_TCP_UDPCSUM_NOK) == 0) { 1378 m->m_pkthdr.csum_flags |= 1379 M_TCP_CSUM_IN_OK | M_UDP_CSUM_IN_OK; 1380 } 1381 /* 1382 * Don't mark bad checksum for TCP/UDP frames 1383 * as fragmented frames may always have set 1384 * bad checksummed bit of descriptor status. 1385 */ 1386 } 1387 #if NVLAN > 0 1388 /* Check for VLAN tagged frames. */ 1389 if (status & AGE_RRD_VLAN) { 1390 u_int32_t vtag = AGE_RX_VLAN(letoh32(rxrd->vtags)); 1391 m->m_pkthdr.ether_vtag = 1392 AGE_RX_VLAN_TAG(vtag); 1393 m->m_flags |= M_VLANTAG; 1394 } 1395 #endif 1396 1397 ml_enqueue(&ml, m); 1398 1399 /* Reset mbuf chains. */ 1400 AGE_RXCHAIN_RESET(sc); 1401 } 1402 } 1403 1404 if_input(ifp, &ml); 1405 1406 if (count != nsegs) { 1407 sc->age_cdata.age_rx_cons += nsegs; 1408 sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT; 1409 } else 1410 sc->age_cdata.age_rx_cons = rx_cons; 1411 } 1412 1413 void 1414 age_rxintr(struct age_softc *sc, int rr_prod) 1415 { 1416 struct rx_rdesc *rxrd; 1417 int rr_cons, nsegs, pktlen, prog; 1418 1419 rr_cons = sc->age_cdata.age_rr_cons; 1420 if (rr_cons == rr_prod) 1421 return; 1422 1423 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 0, 1424 sc->age_cdata.age_rr_ring_map->dm_mapsize, 1425 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1426 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rx_ring_map, 0, 1427 sc->age_cdata.age_rx_ring_map->dm_mapsize, 1428 BUS_DMASYNC_POSTWRITE); 1429 1430 for (prog = 0; rr_cons != rr_prod; prog++) { 1431 rxrd = &sc->age_rdata.age_rr_ring[rr_cons]; 1432 nsegs = AGE_RX_NSEGS(letoh32(rxrd->index)); 1433 if (nsegs == 0) 1434 break; 1435 /* 1436 * Check number of segments against received bytes 1437 * Non-matching value would indicate that hardware 1438 * is still trying to update Rx return descriptors. 1439 * I'm not sure whether this check is really needed. 1440 */ 1441 pktlen = AGE_RX_BYTES(letoh32(rxrd->len)); 1442 if (nsegs != ((pktlen + (MCLBYTES - ETHER_ALIGN - 1)) / 1443 (MCLBYTES - ETHER_ALIGN))) 1444 break; 1445 1446 /* Received a frame. */ 1447 age_rxeof(sc, rxrd); 1448 1449 /* Clear return ring. */ 1450 rxrd->index = 0; 1451 AGE_DESC_INC(rr_cons, AGE_RR_RING_CNT); 1452 } 1453 1454 if (prog > 0) { 1455 /* Update the consumer index. */ 1456 sc->age_cdata.age_rr_cons = rr_cons; 1457 1458 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rx_ring_map, 0, 1459 sc->age_cdata.age_rx_ring_map->dm_mapsize, 1460 BUS_DMASYNC_PREWRITE); 1461 /* Sync descriptors. */ 1462 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 0, 1463 sc->age_cdata.age_rr_ring_map->dm_mapsize, 1464 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1465 1466 /* Notify hardware availability of new Rx buffers. */ 1467 AGE_COMMIT_MBOX(sc); 1468 } 1469 } 1470 1471 void 1472 age_tick(void *xsc) 1473 { 1474 struct age_softc *sc = xsc; 1475 struct mii_data *mii = &sc->sc_miibus; 1476 int s; 1477 1478 s = splnet(); 1479 mii_tick(mii); 1480 timeout_add_sec(&sc->age_tick_ch, 1); 1481 splx(s); 1482 } 1483 1484 void 1485 age_reset(struct age_softc *sc) 1486 { 1487 uint32_t reg; 1488 int i; 1489 1490 CSR_WRITE_4(sc, AGE_MASTER_CFG, MASTER_RESET); 1491 CSR_READ_4(sc, AGE_MASTER_CFG); 1492 DELAY(1000); 1493 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 1494 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 1495 break; 1496 DELAY(10); 1497 } 1498 1499 if (i == 0) 1500 printf("%s: reset timeout(0x%08x)!\n", sc->sc_dev.dv_xname, 1501 reg); 1502 1503 /* Initialize PCIe module. From Linux. */ 1504 CSR_WRITE_4(sc, 0x12FC, 0x6500); 1505 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 1506 } 1507 1508 int 1509 age_init(struct ifnet *ifp) 1510 { 1511 struct age_softc *sc = ifp->if_softc; 1512 struct mii_data *mii = &sc->sc_miibus; 1513 uint8_t eaddr[ETHER_ADDR_LEN]; 1514 bus_addr_t paddr; 1515 uint32_t reg, fsize; 1516 uint32_t rxf_hi, rxf_lo, rrd_hi, rrd_lo; 1517 int error; 1518 1519 /* 1520 * Cancel any pending I/O. 1521 */ 1522 age_stop(sc); 1523 1524 /* 1525 * Reset the chip to a known state. 1526 */ 1527 age_reset(sc); 1528 1529 /* Initialize descriptors. */ 1530 error = age_init_rx_ring(sc); 1531 if (error != 0) { 1532 printf("%s: no memory for Rx buffers.\n", sc->sc_dev.dv_xname); 1533 age_stop(sc); 1534 return (error); 1535 } 1536 age_init_rr_ring(sc); 1537 age_init_tx_ring(sc); 1538 age_init_cmb_block(sc); 1539 age_init_smb_block(sc); 1540 1541 /* Reprogram the station address. */ 1542 bcopy(LLADDR(ifp->if_sadl), eaddr, ETHER_ADDR_LEN); 1543 CSR_WRITE_4(sc, AGE_PAR0, 1544 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 1545 CSR_WRITE_4(sc, AGE_PAR1, eaddr[0] << 8 | eaddr[1]); 1546 1547 /* Set descriptor base addresses. */ 1548 paddr = sc->age_rdata.age_tx_ring_paddr; 1549 CSR_WRITE_4(sc, AGE_DESC_ADDR_HI, AGE_ADDR_HI(paddr)); 1550 paddr = sc->age_rdata.age_rx_ring_paddr; 1551 CSR_WRITE_4(sc, AGE_DESC_RD_ADDR_LO, AGE_ADDR_LO(paddr)); 1552 paddr = sc->age_rdata.age_rr_ring_paddr; 1553 CSR_WRITE_4(sc, AGE_DESC_RRD_ADDR_LO, AGE_ADDR_LO(paddr)); 1554 paddr = sc->age_rdata.age_tx_ring_paddr; 1555 CSR_WRITE_4(sc, AGE_DESC_TPD_ADDR_LO, AGE_ADDR_LO(paddr)); 1556 paddr = sc->age_rdata.age_cmb_block_paddr; 1557 CSR_WRITE_4(sc, AGE_DESC_CMB_ADDR_LO, AGE_ADDR_LO(paddr)); 1558 paddr = sc->age_rdata.age_smb_block_paddr; 1559 CSR_WRITE_4(sc, AGE_DESC_SMB_ADDR_LO, AGE_ADDR_LO(paddr)); 1560 1561 /* Set Rx/Rx return descriptor counter. */ 1562 CSR_WRITE_4(sc, AGE_DESC_RRD_RD_CNT, 1563 ((AGE_RR_RING_CNT << DESC_RRD_CNT_SHIFT) & 1564 DESC_RRD_CNT_MASK) | 1565 ((AGE_RX_RING_CNT << DESC_RD_CNT_SHIFT) & DESC_RD_CNT_MASK)); 1566 1567 /* Set Tx descriptor counter. */ 1568 CSR_WRITE_4(sc, AGE_DESC_TPD_CNT, 1569 (AGE_TX_RING_CNT << DESC_TPD_CNT_SHIFT) & DESC_TPD_CNT_MASK); 1570 1571 /* Tell hardware that we're ready to load descriptors. */ 1572 CSR_WRITE_4(sc, AGE_DMA_BLOCK, DMA_BLOCK_LOAD); 1573 1574 /* 1575 * Initialize mailbox register. 1576 * Updated producer/consumer index information is exchanged 1577 * through this mailbox register. However Tx producer and 1578 * Rx return consumer/Rx producer are all shared such that 1579 * it's hard to separate code path between Tx and Rx without 1580 * locking. If L1 hardware have a separate mail box register 1581 * for Tx and Rx consumer/producer management we could have 1582 * independent Tx/Rx handler which in turn Rx handler could have 1583 * been run without any locking. 1584 */ 1585 AGE_COMMIT_MBOX(sc); 1586 1587 /* Configure IPG/IFG parameters. */ 1588 CSR_WRITE_4(sc, AGE_IPG_IFG_CFG, 1589 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK) | 1590 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 1591 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 1592 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK)); 1593 1594 /* Set parameters for half-duplex media. */ 1595 CSR_WRITE_4(sc, AGE_HDPX_CFG, 1596 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 1597 HDPX_CFG_LCOL_MASK) | 1598 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 1599 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 1600 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 1601 HDPX_CFG_ABEBT_MASK) | 1602 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 1603 HDPX_CFG_JAMIPG_MASK)); 1604 1605 /* Configure interrupt moderation timer. */ 1606 sc->age_int_mod = AGE_IM_TIMER_DEFAULT; 1607 CSR_WRITE_2(sc, AGE_IM_TIMER, AGE_USECS(sc->age_int_mod)); 1608 reg = CSR_READ_4(sc, AGE_MASTER_CFG); 1609 reg &= ~MASTER_MTIMER_ENB; 1610 if (AGE_USECS(sc->age_int_mod) == 0) 1611 reg &= ~MASTER_ITIMER_ENB; 1612 else 1613 reg |= MASTER_ITIMER_ENB; 1614 CSR_WRITE_4(sc, AGE_MASTER_CFG, reg); 1615 if (agedebug) 1616 printf("%s: interrupt moderation is %d us.\n", 1617 sc->sc_dev.dv_xname, sc->age_int_mod); 1618 CSR_WRITE_2(sc, AGE_INTR_CLR_TIMER, AGE_USECS(1000)); 1619 1620 /* Set Maximum frame size but don't let MTU be lass than ETHER_MTU. */ 1621 if (ifp->if_mtu < ETHERMTU) 1622 sc->age_max_frame_size = ETHERMTU; 1623 else 1624 sc->age_max_frame_size = ifp->if_mtu; 1625 sc->age_max_frame_size += ETHER_HDR_LEN + 1626 sizeof(struct ether_vlan_header) + ETHER_CRC_LEN; 1627 CSR_WRITE_4(sc, AGE_FRAME_SIZE, sc->age_max_frame_size); 1628 1629 /* Configure jumbo frame. */ 1630 fsize = roundup(sc->age_max_frame_size, sizeof(uint64_t)); 1631 CSR_WRITE_4(sc, AGE_RXQ_JUMBO_CFG, 1632 (((fsize / sizeof(uint64_t)) << 1633 RXQ_JUMBO_CFG_SZ_THRESH_SHIFT) & RXQ_JUMBO_CFG_SZ_THRESH_MASK) | 1634 ((RXQ_JUMBO_CFG_LKAH_DEFAULT << 1635 RXQ_JUMBO_CFG_LKAH_SHIFT) & RXQ_JUMBO_CFG_LKAH_MASK) | 1636 ((AGE_USECS(8) << RXQ_JUMBO_CFG_RRD_TIMER_SHIFT) & 1637 RXQ_JUMBO_CFG_RRD_TIMER_MASK)); 1638 1639 /* Configure flow-control parameters. From Linux. */ 1640 if ((sc->age_flags & AGE_FLAG_PCIE) != 0) { 1641 /* 1642 * Magic workaround for old-L1. 1643 * Don't know which hw revision requires this magic. 1644 */ 1645 CSR_WRITE_4(sc, 0x12FC, 0x6500); 1646 /* 1647 * Another magic workaround for flow-control mode 1648 * change. From Linux. 1649 */ 1650 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 1651 } 1652 /* 1653 * TODO 1654 * Should understand pause parameter relationships between FIFO 1655 * size and number of Rx descriptors and Rx return descriptors. 1656 * 1657 * Magic parameters came from Linux. 1658 */ 1659 switch (sc->age_chip_rev) { 1660 case 0x8001: 1661 case 0x9001: 1662 case 0x9002: 1663 case 0x9003: 1664 rxf_hi = AGE_RX_RING_CNT / 16; 1665 rxf_lo = (AGE_RX_RING_CNT * 7) / 8; 1666 rrd_hi = (AGE_RR_RING_CNT * 7) / 8; 1667 rrd_lo = AGE_RR_RING_CNT / 16; 1668 break; 1669 default: 1670 reg = CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN); 1671 rxf_lo = reg / 16; 1672 if (rxf_lo < 192) 1673 rxf_lo = 192; 1674 rxf_hi = (reg * 7) / 8; 1675 if (rxf_hi < rxf_lo) 1676 rxf_hi = rxf_lo + 16; 1677 reg = CSR_READ_4(sc, AGE_SRAM_RRD_LEN); 1678 rrd_lo = reg / 8; 1679 rrd_hi = (reg * 7) / 8; 1680 if (rrd_lo < 2) 1681 rrd_lo = 2; 1682 if (rrd_hi < rrd_lo) 1683 rrd_hi = rrd_lo + 3; 1684 break; 1685 } 1686 CSR_WRITE_4(sc, AGE_RXQ_FIFO_PAUSE_THRESH, 1687 ((rxf_lo << RXQ_FIFO_PAUSE_THRESH_LO_SHIFT) & 1688 RXQ_FIFO_PAUSE_THRESH_LO_MASK) | 1689 ((rxf_hi << RXQ_FIFO_PAUSE_THRESH_HI_SHIFT) & 1690 RXQ_FIFO_PAUSE_THRESH_HI_MASK)); 1691 CSR_WRITE_4(sc, AGE_RXQ_RRD_PAUSE_THRESH, 1692 ((rrd_lo << RXQ_RRD_PAUSE_THRESH_LO_SHIFT) & 1693 RXQ_RRD_PAUSE_THRESH_LO_MASK) | 1694 ((rrd_hi << RXQ_RRD_PAUSE_THRESH_HI_SHIFT) & 1695 RXQ_RRD_PAUSE_THRESH_HI_MASK)); 1696 1697 /* Configure RxQ. */ 1698 CSR_WRITE_4(sc, AGE_RXQ_CFG, 1699 ((RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 1700 RXQ_CFG_RD_BURST_MASK) | 1701 ((RXQ_CFG_RRD_BURST_THRESH_DEFAULT << 1702 RXQ_CFG_RRD_BURST_THRESH_SHIFT) & RXQ_CFG_RRD_BURST_THRESH_MASK) | 1703 ((RXQ_CFG_RD_PREF_MIN_IPG_DEFAULT << 1704 RXQ_CFG_RD_PREF_MIN_IPG_SHIFT) & RXQ_CFG_RD_PREF_MIN_IPG_MASK) | 1705 RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 1706 1707 /* Configure TxQ. */ 1708 CSR_WRITE_4(sc, AGE_TXQ_CFG, 1709 ((TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 1710 TXQ_CFG_TPD_BURST_MASK) | 1711 ((TXQ_CFG_TX_FIFO_BURST_DEFAULT << TXQ_CFG_TX_FIFO_BURST_SHIFT) & 1712 TXQ_CFG_TX_FIFO_BURST_MASK) | 1713 ((TXQ_CFG_TPD_FETCH_DEFAULT << 1714 TXQ_CFG_TPD_FETCH_THRESH_SHIFT) & TXQ_CFG_TPD_FETCH_THRESH_MASK) | 1715 TXQ_CFG_ENB); 1716 1717 /* Configure DMA parameters. */ 1718 CSR_WRITE_4(sc, AGE_DMA_CFG, 1719 DMA_CFG_ENH_ORDER | DMA_CFG_RCB_64 | 1720 sc->age_dma_rd_burst | DMA_CFG_RD_ENB | 1721 sc->age_dma_wr_burst | DMA_CFG_WR_ENB); 1722 1723 /* Configure CMB DMA write threshold. */ 1724 CSR_WRITE_4(sc, AGE_CMB_WR_THRESH, 1725 ((CMB_WR_THRESH_RRD_DEFAULT << CMB_WR_THRESH_RRD_SHIFT) & 1726 CMB_WR_THRESH_RRD_MASK) | 1727 ((CMB_WR_THRESH_TPD_DEFAULT << CMB_WR_THRESH_TPD_SHIFT) & 1728 CMB_WR_THRESH_TPD_MASK)); 1729 1730 /* Set CMB/SMB timer and enable them. */ 1731 CSR_WRITE_4(sc, AGE_CMB_WR_TIMER, 1732 ((AGE_USECS(2) << CMB_WR_TIMER_TX_SHIFT) & CMB_WR_TIMER_TX_MASK) | 1733 ((AGE_USECS(2) << CMB_WR_TIMER_RX_SHIFT) & CMB_WR_TIMER_RX_MASK)); 1734 1735 /* Request SMB updates for every seconds. */ 1736 CSR_WRITE_4(sc, AGE_SMB_TIMER, AGE_USECS(1000 * 1000)); 1737 CSR_WRITE_4(sc, AGE_CSMB_CTRL, CSMB_CTRL_SMB_ENB | CSMB_CTRL_CMB_ENB); 1738 1739 /* 1740 * Disable all WOL bits as WOL can interfere normal Rx 1741 * operation. 1742 */ 1743 CSR_WRITE_4(sc, AGE_WOL_CFG, 0); 1744 1745 /* 1746 * Configure Tx/Rx MACs. 1747 * - Auto-padding for short frames. 1748 * - Enable CRC generation. 1749 * Start with full-duplex/1000Mbps media. Actual reconfiguration 1750 * of MAC is followed after link establishment. 1751 */ 1752 CSR_WRITE_4(sc, AGE_MAC_CFG, 1753 MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | 1754 MAC_CFG_FULL_DUPLEX | MAC_CFG_SPEED_1000 | 1755 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 1756 MAC_CFG_PREAMBLE_MASK)); 1757 1758 /* Set up the receive filter. */ 1759 age_iff(sc); 1760 1761 age_rxvlan(sc); 1762 1763 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1764 reg |= MAC_CFG_RXCSUM_ENB; 1765 1766 /* Ack all pending interrupts and clear it. */ 1767 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); 1768 CSR_WRITE_4(sc, AGE_INTR_MASK, AGE_INTRS); 1769 1770 /* Finally enable Tx/Rx MAC. */ 1771 CSR_WRITE_4(sc, AGE_MAC_CFG, reg | MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 1772 1773 sc->age_flags &= ~AGE_FLAG_LINK; 1774 1775 /* Switch to the current media. */ 1776 mii_mediachg(mii); 1777 1778 timeout_add_sec(&sc->age_tick_ch, 1); 1779 1780 ifp->if_flags |= IFF_RUNNING; 1781 ifq_clr_oactive(&ifp->if_snd); 1782 1783 return (0); 1784 } 1785 1786 void 1787 age_stop(struct age_softc *sc) 1788 { 1789 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1790 struct age_txdesc *txd; 1791 struct age_rxdesc *rxd; 1792 uint32_t reg; 1793 int i; 1794 1795 /* 1796 * Mark the interface down and cancel the watchdog timer. 1797 */ 1798 ifp->if_flags &= ~IFF_RUNNING; 1799 ifq_clr_oactive(&ifp->if_snd); 1800 ifp->if_timer = 0; 1801 1802 sc->age_flags &= ~AGE_FLAG_LINK; 1803 timeout_del(&sc->age_tick_ch); 1804 1805 /* 1806 * Disable interrupts. 1807 */ 1808 CSR_WRITE_4(sc, AGE_INTR_MASK, 0); 1809 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0xFFFFFFFF); 1810 1811 /* Stop CMB/SMB updates. */ 1812 CSR_WRITE_4(sc, AGE_CSMB_CTRL, 0); 1813 1814 /* Stop Rx/Tx MAC. */ 1815 age_stop_rxmac(sc); 1816 age_stop_txmac(sc); 1817 1818 /* Stop DMA. */ 1819 CSR_WRITE_4(sc, AGE_DMA_CFG, 1820 CSR_READ_4(sc, AGE_DMA_CFG) & ~(DMA_CFG_RD_ENB | DMA_CFG_WR_ENB)); 1821 1822 /* Stop TxQ/RxQ. */ 1823 CSR_WRITE_4(sc, AGE_TXQ_CFG, 1824 CSR_READ_4(sc, AGE_TXQ_CFG) & ~TXQ_CFG_ENB); 1825 CSR_WRITE_4(sc, AGE_RXQ_CFG, 1826 CSR_READ_4(sc, AGE_RXQ_CFG) & ~RXQ_CFG_ENB); 1827 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 1828 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 1829 break; 1830 DELAY(10); 1831 } 1832 if (i == 0) 1833 printf("%s: stopping Rx/Tx MACs timed out(0x%08x)!\n", 1834 sc->sc_dev.dv_xname, reg); 1835 1836 /* Reclaim Rx buffers that have been processed. */ 1837 if (sc->age_cdata.age_rxhead != NULL) 1838 m_freem(sc->age_cdata.age_rxhead); 1839 AGE_RXCHAIN_RESET(sc); 1840 1841 /* 1842 * Free RX and TX mbufs still in the queues. 1843 */ 1844 for (i = 0; i < AGE_RX_RING_CNT; i++) { 1845 rxd = &sc->age_cdata.age_rxdesc[i]; 1846 if (rxd->rx_m != NULL) { 1847 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0, 1848 rxd->rx_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1849 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 1850 m_freem(rxd->rx_m); 1851 rxd->rx_m = NULL; 1852 } 1853 } 1854 for (i = 0; i < AGE_TX_RING_CNT; i++) { 1855 txd = &sc->age_cdata.age_txdesc[i]; 1856 if (txd->tx_m != NULL) { 1857 bus_dmamap_sync(sc->sc_dmat, txd->tx_dmamap, 0, 1858 txd->tx_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1859 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1860 m_freem(txd->tx_m); 1861 txd->tx_m = NULL; 1862 } 1863 } 1864 } 1865 1866 void 1867 age_stats_update(struct age_softc *sc) 1868 { 1869 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1870 struct age_stats *stat; 1871 struct smb *smb; 1872 1873 stat = &sc->age_stat; 1874 1875 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 0, 1876 sc->age_cdata.age_smb_block_map->dm_mapsize, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1877 1878 smb = sc->age_rdata.age_smb_block; 1879 if (smb->updated == 0) 1880 return; 1881 1882 /* Rx stats. */ 1883 stat->rx_frames += smb->rx_frames; 1884 stat->rx_bcast_frames += smb->rx_bcast_frames; 1885 stat->rx_mcast_frames += smb->rx_mcast_frames; 1886 stat->rx_pause_frames += smb->rx_pause_frames; 1887 stat->rx_control_frames += smb->rx_control_frames; 1888 stat->rx_crcerrs += smb->rx_crcerrs; 1889 stat->rx_lenerrs += smb->rx_lenerrs; 1890 stat->rx_bytes += smb->rx_bytes; 1891 stat->rx_runts += smb->rx_runts; 1892 stat->rx_fragments += smb->rx_fragments; 1893 stat->rx_pkts_64 += smb->rx_pkts_64; 1894 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 1895 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 1896 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 1897 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 1898 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 1899 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 1900 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 1901 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 1902 stat->rx_desc_oflows += smb->rx_desc_oflows; 1903 stat->rx_alignerrs += smb->rx_alignerrs; 1904 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 1905 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 1906 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 1907 1908 /* Tx stats. */ 1909 stat->tx_frames += smb->tx_frames; 1910 stat->tx_bcast_frames += smb->tx_bcast_frames; 1911 stat->tx_mcast_frames += smb->tx_mcast_frames; 1912 stat->tx_pause_frames += smb->tx_pause_frames; 1913 stat->tx_excess_defer += smb->tx_excess_defer; 1914 stat->tx_control_frames += smb->tx_control_frames; 1915 stat->tx_deferred += smb->tx_deferred; 1916 stat->tx_bytes += smb->tx_bytes; 1917 stat->tx_pkts_64 += smb->tx_pkts_64; 1918 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 1919 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 1920 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 1921 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 1922 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 1923 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 1924 stat->tx_single_colls += smb->tx_single_colls; 1925 stat->tx_multi_colls += smb->tx_multi_colls; 1926 stat->tx_late_colls += smb->tx_late_colls; 1927 stat->tx_excess_colls += smb->tx_excess_colls; 1928 stat->tx_underrun += smb->tx_underrun; 1929 stat->tx_desc_underrun += smb->tx_desc_underrun; 1930 stat->tx_lenerrs += smb->tx_lenerrs; 1931 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 1932 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 1933 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 1934 1935 ifp->if_collisions += smb->tx_single_colls + 1936 smb->tx_multi_colls + smb->tx_late_colls + 1937 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT; 1938 1939 ifp->if_oerrors += smb->tx_excess_colls + 1940 smb->tx_late_colls + smb->tx_underrun + 1941 smb->tx_pkts_truncated; 1942 1943 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 1944 smb->rx_runts + smb->rx_pkts_truncated + 1945 smb->rx_fifo_oflows + smb->rx_desc_oflows + 1946 smb->rx_alignerrs; 1947 1948 /* Update done, clear. */ 1949 smb->updated = 0; 1950 1951 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 0, 1952 sc->age_cdata.age_smb_block_map->dm_mapsize, 1953 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1954 } 1955 1956 void 1957 age_stop_txmac(struct age_softc *sc) 1958 { 1959 uint32_t reg; 1960 int i; 1961 1962 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1963 if ((reg & MAC_CFG_TX_ENB) != 0) { 1964 reg &= ~MAC_CFG_TX_ENB; 1965 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1966 } 1967 /* Stop Tx DMA engine. */ 1968 reg = CSR_READ_4(sc, AGE_DMA_CFG); 1969 if ((reg & DMA_CFG_RD_ENB) != 0) { 1970 reg &= ~DMA_CFG_RD_ENB; 1971 CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 1972 } 1973 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 1974 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 1975 (IDLE_STATUS_TXMAC | IDLE_STATUS_DMARD)) == 0) 1976 break; 1977 DELAY(10); 1978 } 1979 if (i == 0) 1980 printf("%s: stopping TxMAC timeout!\n", sc->sc_dev.dv_xname); 1981 } 1982 1983 void 1984 age_stop_rxmac(struct age_softc *sc) 1985 { 1986 uint32_t reg; 1987 int i; 1988 1989 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1990 if ((reg & MAC_CFG_RX_ENB) != 0) { 1991 reg &= ~MAC_CFG_RX_ENB; 1992 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1993 } 1994 /* Stop Rx DMA engine. */ 1995 reg = CSR_READ_4(sc, AGE_DMA_CFG); 1996 if ((reg & DMA_CFG_WR_ENB) != 0) { 1997 reg &= ~DMA_CFG_WR_ENB; 1998 CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 1999 } 2000 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2001 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 2002 (IDLE_STATUS_RXMAC | IDLE_STATUS_DMAWR)) == 0) 2003 break; 2004 DELAY(10); 2005 } 2006 if (i == 0) 2007 printf("%s: stopping RxMAC timeout!\n", sc->sc_dev.dv_xname); 2008 } 2009 2010 void 2011 age_init_tx_ring(struct age_softc *sc) 2012 { 2013 struct age_ring_data *rd; 2014 struct age_txdesc *txd; 2015 int i; 2016 2017 sc->age_cdata.age_tx_prod = 0; 2018 sc->age_cdata.age_tx_cons = 0; 2019 sc->age_cdata.age_tx_cnt = 0; 2020 2021 rd = &sc->age_rdata; 2022 bzero(rd->age_tx_ring, AGE_TX_RING_SZ); 2023 for (i = 0; i < AGE_TX_RING_CNT; i++) { 2024 txd = &sc->age_cdata.age_txdesc[i]; 2025 txd->tx_desc = &rd->age_tx_ring[i]; 2026 txd->tx_m = NULL; 2027 } 2028 2029 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 0, 2030 sc->age_cdata.age_tx_ring_map->dm_mapsize, 2031 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2032 } 2033 2034 int 2035 age_init_rx_ring(struct age_softc *sc) 2036 { 2037 struct age_ring_data *rd; 2038 struct age_rxdesc *rxd; 2039 int i; 2040 2041 sc->age_cdata.age_rx_cons = AGE_RX_RING_CNT - 1; 2042 rd = &sc->age_rdata; 2043 bzero(rd->age_rx_ring, AGE_RX_RING_SZ); 2044 for (i = 0; i < AGE_RX_RING_CNT; i++) { 2045 rxd = &sc->age_cdata.age_rxdesc[i]; 2046 rxd->rx_m = NULL; 2047 rxd->rx_desc = &rd->age_rx_ring[i]; 2048 if (age_newbuf(sc, rxd) != 0) 2049 return (ENOBUFS); 2050 } 2051 2052 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rx_ring_map, 0, 2053 sc->age_cdata.age_rx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2054 2055 return (0); 2056 } 2057 2058 void 2059 age_init_rr_ring(struct age_softc *sc) 2060 { 2061 struct age_ring_data *rd; 2062 2063 sc->age_cdata.age_rr_cons = 0; 2064 AGE_RXCHAIN_RESET(sc); 2065 2066 rd = &sc->age_rdata; 2067 bzero(rd->age_rr_ring, AGE_RR_RING_SZ); 2068 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 0, 2069 sc->age_cdata.age_rr_ring_map->dm_mapsize, 2070 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2071 } 2072 2073 void 2074 age_init_cmb_block(struct age_softc *sc) 2075 { 2076 struct age_ring_data *rd; 2077 2078 rd = &sc->age_rdata; 2079 bzero(rd->age_cmb_block, AGE_CMB_BLOCK_SZ); 2080 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 2081 sc->age_cdata.age_cmb_block_map->dm_mapsize, 2082 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2083 } 2084 2085 void 2086 age_init_smb_block(struct age_softc *sc) 2087 { 2088 struct age_ring_data *rd; 2089 2090 rd = &sc->age_rdata; 2091 bzero(rd->age_smb_block, AGE_SMB_BLOCK_SZ); 2092 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 0, 2093 sc->age_cdata.age_smb_block_map->dm_mapsize, 2094 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2095 } 2096 2097 int 2098 age_newbuf(struct age_softc *sc, struct age_rxdesc *rxd) 2099 { 2100 struct rx_desc *desc; 2101 struct mbuf *m; 2102 bus_dmamap_t map; 2103 int error; 2104 2105 MGETHDR(m, M_DONTWAIT, MT_DATA); 2106 if (m == NULL) 2107 return (ENOBUFS); 2108 MCLGET(m, M_DONTWAIT); 2109 if (!(m->m_flags & M_EXT)) { 2110 m_freem(m); 2111 return (ENOBUFS); 2112 } 2113 2114 m->m_len = m->m_pkthdr.len = MCLBYTES; 2115 m_adj(m, ETHER_ALIGN); 2116 2117 error = bus_dmamap_load_mbuf(sc->sc_dmat, 2118 sc->age_cdata.age_rx_sparemap, m, BUS_DMA_NOWAIT); 2119 2120 if (error != 0) { 2121 m_freem(m); 2122 printf("%s: can't load RX mbuf\n", sc->sc_dev.dv_xname); 2123 return (error); 2124 } 2125 2126 if (rxd->rx_m != NULL) { 2127 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0, 2128 rxd->rx_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2129 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 2130 } 2131 map = rxd->rx_dmamap; 2132 rxd->rx_dmamap = sc->age_cdata.age_rx_sparemap; 2133 sc->age_cdata.age_rx_sparemap = map; 2134 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0, 2135 rxd->rx_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2136 rxd->rx_m = m; 2137 2138 desc = rxd->rx_desc; 2139 desc->addr = htole64(rxd->rx_dmamap->dm_segs[0].ds_addr); 2140 desc->len = 2141 htole32((rxd->rx_dmamap->dm_segs[0].ds_len & AGE_RD_LEN_MASK) << 2142 AGE_RD_LEN_SHIFT); 2143 2144 return (0); 2145 } 2146 2147 void 2148 age_rxvlan(struct age_softc *sc) 2149 { 2150 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 2151 uint32_t reg; 2152 2153 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2154 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 2155 if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) 2156 reg |= MAC_CFG_VLAN_TAG_STRIP; 2157 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2158 } 2159 2160 void 2161 age_iff(struct age_softc *sc) 2162 { 2163 struct arpcom *ac = &sc->sc_arpcom; 2164 struct ifnet *ifp = &ac->ac_if; 2165 struct ether_multi *enm; 2166 struct ether_multistep step; 2167 uint32_t crc; 2168 uint32_t mchash[2]; 2169 uint32_t rxcfg; 2170 2171 rxcfg = CSR_READ_4(sc, AGE_MAC_CFG); 2172 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 2173 ifp->if_flags &= ~IFF_ALLMULTI; 2174 2175 /* 2176 * Always accept broadcast frames. 2177 */ 2178 rxcfg |= MAC_CFG_BCAST; 2179 2180 if (ifp->if_flags & IFF_PROMISC || ac->ac_multirangecnt > 0) { 2181 ifp->if_flags |= IFF_ALLMULTI; 2182 if (ifp->if_flags & IFF_PROMISC) 2183 rxcfg |= MAC_CFG_PROMISC; 2184 else 2185 rxcfg |= MAC_CFG_ALLMULTI; 2186 mchash[0] = mchash[1] = 0xFFFFFFFF; 2187 } else { 2188 /* Program new filter. */ 2189 bzero(mchash, sizeof(mchash)); 2190 2191 ETHER_FIRST_MULTI(step, ac, enm); 2192 while (enm != NULL) { 2193 crc = ether_crc32_be(enm->enm_addrlo, 2194 ETHER_ADDR_LEN); 2195 2196 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 2197 2198 ETHER_NEXT_MULTI(step, enm); 2199 } 2200 } 2201 2202 CSR_WRITE_4(sc, AGE_MAR0, mchash[0]); 2203 CSR_WRITE_4(sc, AGE_MAR1, mchash[1]); 2204 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg); 2205 } 2206