1 /* $OpenBSD: ichiic.c,v 1.51 2023/02/05 02:26:02 jsg Exp $ */ 2 3 /* 4 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * Intel ICH SMBus controller driver. 21 */ 22 23 #include <sys/param.h> 24 #include <sys/systm.h> 25 #include <sys/device.h> 26 #include <sys/kernel.h> 27 #include <sys/rwlock.h> 28 29 #include <machine/bus.h> 30 31 #include <dev/pci/pcidevs.h> 32 #include <dev/pci/pcireg.h> 33 #include <dev/pci/pcivar.h> 34 35 #include <dev/pci/ichreg.h> 36 37 #include <dev/i2c/i2cvar.h> 38 39 #ifdef ICHIIC_DEBUG 40 #define DPRINTF(x) printf x 41 #else 42 #define DPRINTF(x) 43 #endif 44 45 #define ICHIIC_DELAY 100 46 #define ICHIIC_TIMEOUT 1 47 48 struct ichiic_softc { 49 struct device sc_dev; 50 51 bus_space_tag_t sc_iot; 52 bus_space_handle_t sc_ioh; 53 void * sc_ih; 54 int sc_poll; 55 56 struct i2c_controller sc_i2c_tag; 57 struct rwlock sc_i2c_lock; 58 struct { 59 i2c_op_t op; 60 void * buf; 61 size_t len; 62 int flags; 63 volatile int error; 64 } sc_i2c_xfer; 65 }; 66 67 int ichiic_match(struct device *, void *, void *); 68 void ichiic_attach(struct device *, struct device *, void *); 69 70 int ichiic_i2c_acquire_bus(void *, int); 71 void ichiic_i2c_release_bus(void *, int); 72 int ichiic_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, size_t, 73 void *, size_t, int); 74 75 int ichiic_intr(void *); 76 77 const struct cfattach ichiic_ca = { 78 sizeof(struct ichiic_softc), 79 ichiic_match, 80 ichiic_attach 81 }; 82 83 struct cfdriver ichiic_cd = { 84 NULL, "ichiic", DV_DULL 85 }; 86 87 const struct pci_matchid ichiic_ids[] = { 88 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_3400_SMB }, 89 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_6SERIES_SMB }, 90 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_6300ESB_SMB }, 91 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_6321ESB_SMB }, 92 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_7SERIES_SMB }, 93 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_8SERIES_SMB }, 94 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_8SERIES_LP_SMB }, 95 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_9SERIES_SMB }, 96 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_9SERIES_LP_SMB }, 97 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_SMB }, 98 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_SMB }, 99 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_SMB }, 100 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_SMB }, 101 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_SMB }, 102 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801E_SMB }, 103 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_SMB }, 104 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FB_SMB }, 105 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GB_SMB }, 106 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_SMB }, 107 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_SMB }, 108 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JD_SMB }, 109 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JI_SMB }, 110 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_APOLLOLAKE_SMB }, 111 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ATOMC2000_PCU_SMB }, 112 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_BAYTRAIL_SMB }, 113 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_BRASWELL_SMB }, 114 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C600_SMB }, 115 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C600_SMB_IDF_1 }, 116 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C600_SMB_IDF_2 }, 117 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C600_SMB_IDF_3 }, 118 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C610_SMB }, 119 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C610_MS_SMB_1 }, 120 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C610_MS_SMB_2 }, 121 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C610_MS_SMB_3 }, 122 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C620_SMB }, 123 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH8900_SMB }, 124 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EP80579_SMBUS }, 125 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_GLK_SMB }, 126 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_100SERIES_SMB }, 127 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_100SERIES_LP_SMB }, 128 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_200SERIES_SMB }, 129 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_300SERIES_SMB }, 130 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_300SERIES_U_SMB }, 131 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_SMB }, 132 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_LP_SMB }, 133 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_V_SMB }, 134 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_495SERIES_LP_SMB }, 135 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_SMB }, 136 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_LP_SMB }, 137 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_600SERIES_SMB }, 138 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_600SERIES_LP_SMB }, 139 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_700SERIES_SMB }, 140 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_JSL_SMB }, 141 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EHL_SMB }, 142 }; 143 144 int 145 ichiic_match(struct device *parent, void *match, void *aux) 146 { 147 return (pci_matchbyid(aux, ichiic_ids, 148 sizeof(ichiic_ids) / sizeof(ichiic_ids[0]))); 149 } 150 151 void 152 ichiic_attach(struct device *parent, struct device *self, void *aux) 153 { 154 struct ichiic_softc *sc = (struct ichiic_softc *)self; 155 struct pci_attach_args *pa = aux; 156 struct i2cbus_attach_args iba; 157 pcireg_t conf; 158 bus_size_t iosize; 159 pci_intr_handle_t ih; 160 const char *intrstr = NULL; 161 162 /* Read configuration */ 163 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_SMB_HOSTC); 164 DPRINTF((": conf 0x%08x", conf)); 165 166 if ((conf & ICH_SMB_HOSTC_HSTEN) == 0) { 167 printf(": SMBus disabled\n"); 168 return; 169 } 170 171 /* Map I/O space */ 172 if (pci_mapreg_map(pa, ICH_SMB_BASE, PCI_MAPREG_TYPE_IO, 0, 173 &sc->sc_iot, &sc->sc_ioh, NULL, &iosize, 0)) { 174 printf(": can't map i/o space\n"); 175 return; 176 } 177 178 sc->sc_poll = 1; 179 if (conf & ICH_SMB_HOSTC_SMIEN) { 180 /* No PCI IRQ */ 181 printf(": SMI"); 182 } else { 183 /* Install interrupt handler */ 184 if (pci_intr_map(pa, &ih) == 0) { 185 intrstr = pci_intr_string(pa->pa_pc, ih); 186 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 187 ichiic_intr, sc, sc->sc_dev.dv_xname); 188 if (sc->sc_ih != NULL) { 189 printf(": %s", intrstr); 190 sc->sc_poll = 0; 191 } 192 } 193 if (sc->sc_poll) 194 printf(": polling"); 195 } 196 197 printf("\n"); 198 199 /* Attach I2C bus */ 200 rw_init(&sc->sc_i2c_lock, "iiclk"); 201 sc->sc_i2c_tag.ic_cookie = sc; 202 sc->sc_i2c_tag.ic_acquire_bus = ichiic_i2c_acquire_bus; 203 sc->sc_i2c_tag.ic_release_bus = ichiic_i2c_release_bus; 204 sc->sc_i2c_tag.ic_exec = ichiic_i2c_exec; 205 206 bzero(&iba, sizeof(iba)); 207 iba.iba_name = "iic"; 208 iba.iba_tag = &sc->sc_i2c_tag; 209 config_found(self, &iba, iicbus_print); 210 211 return; 212 } 213 214 int 215 ichiic_i2c_acquire_bus(void *cookie, int flags) 216 { 217 struct ichiic_softc *sc = cookie; 218 219 if (cold || sc->sc_poll || (flags & I2C_F_POLL)) 220 return (0); 221 222 return (rw_enter(&sc->sc_i2c_lock, RW_WRITE | RW_INTR)); 223 } 224 225 void 226 ichiic_i2c_release_bus(void *cookie, int flags) 227 { 228 struct ichiic_softc *sc = cookie; 229 230 if (cold || sc->sc_poll || (flags & I2C_F_POLL)) 231 return; 232 233 rw_exit(&sc->sc_i2c_lock); 234 } 235 236 int 237 ichiic_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 238 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 239 { 240 struct ichiic_softc *sc = cookie; 241 u_int8_t *b; 242 u_int8_t ctl, st; 243 int retries; 244 245 DPRINTF(("%s: exec: op %d, addr 0x%02x, cmdlen %d, len %d, " 246 "flags 0x%02x\n", sc->sc_dev.dv_xname, op, addr, cmdlen, 247 len, flags)); 248 249 /* Wait for bus to be idle */ 250 for (retries = 100; retries > 0; retries--) { 251 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS); 252 if (!(st & ICH_SMB_HS_BUSY)) 253 break; 254 DELAY(ICHIIC_DELAY); 255 } 256 DPRINTF(("%s: exec: st 0x%b\n", sc->sc_dev.dv_xname, st, 257 ICH_SMB_HS_BITS)); 258 if (st & ICH_SMB_HS_BUSY) 259 return (1); 260 261 if (cold || sc->sc_poll) 262 flags |= I2C_F_POLL; 263 264 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2) 265 return (1); 266 267 /* Setup transfer */ 268 sc->sc_i2c_xfer.op = op; 269 sc->sc_i2c_xfer.buf = buf; 270 sc->sc_i2c_xfer.len = len; 271 sc->sc_i2c_xfer.flags = flags; 272 sc->sc_i2c_xfer.error = 0; 273 274 /* Set slave address and transfer direction */ 275 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_TXSLVA, 276 ICH_SMB_TXSLVA_ADDR(addr) | 277 (I2C_OP_READ_P(op) ? ICH_SMB_TXSLVA_READ : 0)); 278 279 b = (void *)cmdbuf; 280 if (cmdlen > 0) 281 /* Set command byte */ 282 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HCMD, b[0]); 283 284 if (I2C_OP_WRITE_P(op)) { 285 /* Write data */ 286 b = buf; 287 if (len > 0) 288 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 289 ICH_SMB_HD0, b[0]); 290 if (len > 1) 291 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 292 ICH_SMB_HD1, b[1]); 293 } 294 295 /* Set SMBus command */ 296 if (len == 0) 297 ctl = ICH_SMB_HC_CMD_BYTE; 298 else if (len == 1) 299 ctl = ICH_SMB_HC_CMD_BDATA; 300 else if (len == 2) 301 ctl = ICH_SMB_HC_CMD_WDATA; 302 else 303 panic("%s: unexpected len %zd", __func__, len); 304 305 if ((flags & I2C_F_POLL) == 0) 306 ctl |= ICH_SMB_HC_INTREN; 307 308 /* Start transaction */ 309 ctl |= ICH_SMB_HC_START; 310 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HC, ctl); 311 312 if (flags & I2C_F_POLL) { 313 /* Poll for completion */ 314 DELAY(ICHIIC_DELAY); 315 for (retries = 1000; retries > 0; retries--) { 316 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 317 ICH_SMB_HS); 318 if ((st & ICH_SMB_HS_BUSY) == 0) 319 break; 320 DELAY(ICHIIC_DELAY); 321 } 322 if (st & ICH_SMB_HS_BUSY) 323 goto timeout; 324 ichiic_intr(sc); 325 } else { 326 /* Wait for interrupt */ 327 if (tsleep_nsec(sc, PRIBIO, "ichiic", 328 SEC_TO_NSEC(ICHIIC_TIMEOUT))) 329 goto timeout; 330 } 331 332 if (sc->sc_i2c_xfer.error) 333 return (1); 334 335 return (0); 336 337 timeout: 338 /* 339 * Transfer timeout. Kill the transaction and clear status bits. 340 */ 341 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HC, 342 ICH_SMB_HC_KILL); 343 DELAY(ICHIIC_DELAY); 344 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS); 345 if ((st & ICH_SMB_HS_FAILED) == 0) 346 printf("%s: abort failed, status 0x%b\n", 347 sc->sc_dev.dv_xname, st, ICH_SMB_HS_BITS); 348 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS, st); 349 return (1); 350 } 351 352 int 353 ichiic_intr(void *arg) 354 { 355 struct ichiic_softc *sc = arg; 356 u_int8_t st; 357 u_int8_t *b; 358 size_t len; 359 360 /* Read status */ 361 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS); 362 363 /* Clear status bits */ 364 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS, st); 365 366 /* XXX Ignore SMBALERT# for now */ 367 if ((st & ICH_SMB_HS_BUSY) != 0 || (st & (ICH_SMB_HS_INTR | 368 ICH_SMB_HS_DEVERR | ICH_SMB_HS_BUSERR | ICH_SMB_HS_FAILED | 369 ICH_SMB_HS_BDONE)) == 0) 370 /* Interrupt was not for us */ 371 return (0); 372 373 DPRINTF(("%s: intr st 0x%b\n", sc->sc_dev.dv_xname, st, 374 ICH_SMB_HS_BITS)); 375 376 /* Check for errors */ 377 if (st & (ICH_SMB_HS_DEVERR | ICH_SMB_HS_BUSERR | ICH_SMB_HS_FAILED)) { 378 sc->sc_i2c_xfer.error = 1; 379 goto done; 380 } 381 382 if (st & ICH_SMB_HS_INTR) { 383 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 384 goto done; 385 386 /* Read data */ 387 b = sc->sc_i2c_xfer.buf; 388 len = sc->sc_i2c_xfer.len; 389 if (len > 0) 390 b[0] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 391 ICH_SMB_HD0); 392 if (len > 1) 393 b[1] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 394 ICH_SMB_HD1); 395 } 396 397 done: 398 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 399 wakeup(sc); 400 return (1); 401 } 402