1 /* $OpenBSD: ichiic.c,v 1.26 2011/04/21 21:56:53 jsg Exp $ */ 2 3 /* 4 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * Intel ICH SMBus controller driver. 21 */ 22 23 #include <sys/param.h> 24 #include <sys/systm.h> 25 #include <sys/device.h> 26 #include <sys/kernel.h> 27 #include <sys/rwlock.h> 28 29 #include <machine/bus.h> 30 31 #include <dev/pci/pcidevs.h> 32 #include <dev/pci/pcireg.h> 33 #include <dev/pci/pcivar.h> 34 35 #include <dev/pci/ichreg.h> 36 37 #include <dev/i2c/i2cvar.h> 38 39 #ifdef ICHIIC_DEBUG 40 #define DPRINTF(x) printf x 41 #else 42 #define DPRINTF(x) 43 #endif 44 45 #define ICHIIC_DELAY 100 46 #define ICHIIC_TIMEOUT 1 47 48 struct ichiic_softc { 49 struct device sc_dev; 50 51 bus_space_tag_t sc_iot; 52 bus_space_handle_t sc_ioh; 53 void * sc_ih; 54 int sc_poll; 55 56 struct i2c_controller sc_i2c_tag; 57 struct rwlock sc_i2c_lock; 58 struct { 59 i2c_op_t op; 60 void * buf; 61 size_t len; 62 int flags; 63 volatile int error; 64 } sc_i2c_xfer; 65 }; 66 67 int ichiic_match(struct device *, void *, void *); 68 void ichiic_attach(struct device *, struct device *, void *); 69 70 int ichiic_i2c_acquire_bus(void *, int); 71 void ichiic_i2c_release_bus(void *, int); 72 int ichiic_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, size_t, 73 void *, size_t, int); 74 75 int ichiic_intr(void *); 76 77 struct cfattach ichiic_ca = { 78 sizeof(struct ichiic_softc), 79 ichiic_match, 80 ichiic_attach 81 }; 82 83 struct cfdriver ichiic_cd = { 84 NULL, "ichiic", DV_DULL 85 }; 86 87 const struct pci_matchid ichiic_ids[] = { 88 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_3400_SMB }, 89 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_6SERIES_SMB }, 90 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_6300ESB_SMB }, 91 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_6321ESB_SMB }, 92 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_SMB }, 93 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_SMB }, 94 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_SMB }, 95 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_SMB }, 96 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_SMB }, 97 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801E_SMB }, 98 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_SMB }, 99 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FB_SMB }, 100 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GB_SMB }, 101 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_SMB }, 102 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_SMB }, 103 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JD_SMB }, 104 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JI_SMB } 105 }; 106 107 int 108 ichiic_match(struct device *parent, void *match, void *aux) 109 { 110 return (pci_matchbyid(aux, ichiic_ids, 111 sizeof(ichiic_ids) / sizeof(ichiic_ids[0]))); 112 } 113 114 void 115 ichiic_attach(struct device *parent, struct device *self, void *aux) 116 { 117 struct ichiic_softc *sc = (struct ichiic_softc *)self; 118 struct pci_attach_args *pa = aux; 119 struct i2cbus_attach_args iba; 120 pcireg_t conf; 121 bus_size_t iosize; 122 pci_intr_handle_t ih; 123 const char *intrstr = NULL; 124 125 /* Read configuration */ 126 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_SMB_HOSTC); 127 DPRINTF((": conf 0x%08x", conf)); 128 129 if ((conf & ICH_SMB_HOSTC_HSTEN) == 0) { 130 printf(": SMBus disabled\n"); 131 return; 132 } 133 134 /* Map I/O space */ 135 if (pci_mapreg_map(pa, ICH_SMB_BASE, PCI_MAPREG_TYPE_IO, 0, 136 &sc->sc_iot, &sc->sc_ioh, NULL, &iosize, 0)) { 137 printf(": can't map i/o space\n"); 138 return; 139 } 140 141 sc->sc_poll = 1; 142 if (conf & ICH_SMB_HOSTC_SMIEN) { 143 /* No PCI IRQ */ 144 printf(": SMI"); 145 } else { 146 /* Install interrupt handler */ 147 if (pci_intr_map(pa, &ih) == 0) { 148 intrstr = pci_intr_string(pa->pa_pc, ih); 149 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 150 ichiic_intr, sc, sc->sc_dev.dv_xname); 151 if (sc->sc_ih != NULL) { 152 printf(": %s", intrstr); 153 sc->sc_poll = 0; 154 } 155 } 156 if (sc->sc_poll) 157 printf(": polling"); 158 } 159 160 printf("\n"); 161 162 /* Attach I2C bus */ 163 rw_init(&sc->sc_i2c_lock, "iiclk"); 164 sc->sc_i2c_tag.ic_cookie = sc; 165 sc->sc_i2c_tag.ic_acquire_bus = ichiic_i2c_acquire_bus; 166 sc->sc_i2c_tag.ic_release_bus = ichiic_i2c_release_bus; 167 sc->sc_i2c_tag.ic_exec = ichiic_i2c_exec; 168 169 bzero(&iba, sizeof(iba)); 170 iba.iba_name = "iic"; 171 iba.iba_tag = &sc->sc_i2c_tag; 172 config_found(self, &iba, iicbus_print); 173 174 return; 175 } 176 177 int 178 ichiic_i2c_acquire_bus(void *cookie, int flags) 179 { 180 struct ichiic_softc *sc = cookie; 181 182 if (cold || sc->sc_poll || (flags & I2C_F_POLL)) 183 return (0); 184 185 return (rw_enter(&sc->sc_i2c_lock, RW_WRITE | RW_INTR)); 186 } 187 188 void 189 ichiic_i2c_release_bus(void *cookie, int flags) 190 { 191 struct ichiic_softc *sc = cookie; 192 193 if (cold || sc->sc_poll || (flags & I2C_F_POLL)) 194 return; 195 196 rw_exit(&sc->sc_i2c_lock); 197 } 198 199 int 200 ichiic_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 201 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 202 { 203 struct ichiic_softc *sc = cookie; 204 u_int8_t *b; 205 u_int8_t ctl, st; 206 int retries; 207 208 DPRINTF(("%s: exec: op %d, addr 0x%02x, cmdlen %d, len %d, " 209 "flags 0x%02x\n", sc->sc_dev.dv_xname, op, addr, cmdlen, 210 len, flags)); 211 212 /* Wait for bus to be idle */ 213 for (retries = 100; retries > 0; retries--) { 214 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS); 215 if (!(st & ICH_SMB_HS_BUSY)) 216 break; 217 DELAY(ICHIIC_DELAY); 218 } 219 DPRINTF(("%s: exec: st 0x%b\n", sc->sc_dev.dv_xname, st, 220 ICH_SMB_HS_BITS)); 221 if (st & ICH_SMB_HS_BUSY) 222 return (1); 223 224 if (cold || sc->sc_poll) 225 flags |= I2C_F_POLL; 226 227 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2) 228 return (1); 229 230 /* Setup transfer */ 231 sc->sc_i2c_xfer.op = op; 232 sc->sc_i2c_xfer.buf = buf; 233 sc->sc_i2c_xfer.len = len; 234 sc->sc_i2c_xfer.flags = flags; 235 sc->sc_i2c_xfer.error = 0; 236 237 /* Set slave address and transfer direction */ 238 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_TXSLVA, 239 ICH_SMB_TXSLVA_ADDR(addr) | 240 (I2C_OP_READ_P(op) ? ICH_SMB_TXSLVA_READ : 0)); 241 242 b = (void *)cmdbuf; 243 if (cmdlen > 0) 244 /* Set command byte */ 245 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HCMD, b[0]); 246 247 if (I2C_OP_WRITE_P(op)) { 248 /* Write data */ 249 b = buf; 250 if (len > 0) 251 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 252 ICH_SMB_HD0, b[0]); 253 if (len > 1) 254 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 255 ICH_SMB_HD1, b[1]); 256 } 257 258 /* Set SMBus command */ 259 if (len == 0) 260 ctl = ICH_SMB_HC_CMD_BYTE; 261 else if (len == 1) 262 ctl = ICH_SMB_HC_CMD_BDATA; 263 else if (len == 2) 264 ctl = ICH_SMB_HC_CMD_WDATA; 265 266 if ((flags & I2C_F_POLL) == 0) 267 ctl |= ICH_SMB_HC_INTREN; 268 269 /* Start transaction */ 270 ctl |= ICH_SMB_HC_START; 271 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HC, ctl); 272 273 if (flags & I2C_F_POLL) { 274 /* Poll for completion */ 275 DELAY(ICHIIC_DELAY); 276 for (retries = 1000; retries > 0; retries--) { 277 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 278 ICH_SMB_HS); 279 if ((st & ICH_SMB_HS_BUSY) == 0) 280 break; 281 DELAY(ICHIIC_DELAY); 282 } 283 if (st & ICH_SMB_HS_BUSY) 284 goto timeout; 285 ichiic_intr(sc); 286 } else { 287 /* Wait for interrupt */ 288 if (tsleep(sc, PRIBIO, "ichiic", ICHIIC_TIMEOUT * hz)) 289 goto timeout; 290 } 291 292 if (sc->sc_i2c_xfer.error) 293 return (1); 294 295 return (0); 296 297 timeout: 298 /* 299 * Transfer timeout. Kill the transaction and clear status bits. 300 */ 301 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HC, 302 ICH_SMB_HC_KILL); 303 DELAY(ICHIIC_DELAY); 304 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS); 305 if ((st & ICH_SMB_HS_FAILED) == 0) 306 printf("%s: abort failed, status 0x%b\n", 307 sc->sc_dev.dv_xname, st, ICH_SMB_HS_BITS); 308 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS, st); 309 return (1); 310 } 311 312 int 313 ichiic_intr(void *arg) 314 { 315 struct ichiic_softc *sc = arg; 316 u_int8_t st; 317 u_int8_t *b; 318 size_t len; 319 320 /* Read status */ 321 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS); 322 if ((st & ICH_SMB_HS_BUSY) != 0 || (st & (ICH_SMB_HS_INTR | 323 ICH_SMB_HS_DEVERR | ICH_SMB_HS_BUSERR | ICH_SMB_HS_FAILED | 324 ICH_SMB_HS_SMBAL | ICH_SMB_HS_BDONE)) == 0) 325 /* Interrupt was not for us */ 326 return (0); 327 328 DPRINTF(("%s: intr st 0x%b\n", sc->sc_dev.dv_xname, st, 329 ICH_SMB_HS_BITS)); 330 331 /* Clear status bits */ 332 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS, st); 333 334 /* Check for errors */ 335 if (st & (ICH_SMB_HS_DEVERR | ICH_SMB_HS_BUSERR | ICH_SMB_HS_FAILED)) { 336 sc->sc_i2c_xfer.error = 1; 337 goto done; 338 } 339 340 if (st & ICH_SMB_HS_INTR) { 341 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 342 goto done; 343 344 /* Read data */ 345 b = sc->sc_i2c_xfer.buf; 346 len = sc->sc_i2c_xfer.len; 347 if (len > 0) 348 b[0] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 349 ICH_SMB_HD0); 350 if (len > 1) 351 b[1] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 352 ICH_SMB_HD1); 353 } 354 355 done: 356 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 357 wakeup(sc); 358 return (1); 359 } 360