1 /* $OpenBSD: ichiic.c,v 1.48 2022/03/11 18:00:45 mpi Exp $ */ 2 3 /* 4 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * Intel ICH SMBus controller driver. 21 */ 22 23 #include <sys/param.h> 24 #include <sys/systm.h> 25 #include <sys/device.h> 26 #include <sys/kernel.h> 27 #include <sys/rwlock.h> 28 29 #include <machine/bus.h> 30 31 #include <dev/pci/pcidevs.h> 32 #include <dev/pci/pcireg.h> 33 #include <dev/pci/pcivar.h> 34 35 #include <dev/pci/ichreg.h> 36 37 #include <dev/i2c/i2cvar.h> 38 39 #ifdef ICHIIC_DEBUG 40 #define DPRINTF(x) printf x 41 #else 42 #define DPRINTF(x) 43 #endif 44 45 #define ICHIIC_DELAY 100 46 #define ICHIIC_TIMEOUT 1 47 48 struct ichiic_softc { 49 struct device sc_dev; 50 51 bus_space_tag_t sc_iot; 52 bus_space_handle_t sc_ioh; 53 void * sc_ih; 54 int sc_poll; 55 56 struct i2c_controller sc_i2c_tag; 57 struct rwlock sc_i2c_lock; 58 struct { 59 i2c_op_t op; 60 void * buf; 61 size_t len; 62 int flags; 63 volatile int error; 64 } sc_i2c_xfer; 65 }; 66 67 int ichiic_match(struct device *, void *, void *); 68 void ichiic_attach(struct device *, struct device *, void *); 69 70 int ichiic_i2c_acquire_bus(void *, int); 71 void ichiic_i2c_release_bus(void *, int); 72 int ichiic_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, size_t, 73 void *, size_t, int); 74 75 int ichiic_intr(void *); 76 77 const struct cfattach ichiic_ca = { 78 sizeof(struct ichiic_softc), 79 ichiic_match, 80 ichiic_attach 81 }; 82 83 struct cfdriver ichiic_cd = { 84 NULL, "ichiic", DV_DULL 85 }; 86 87 const struct pci_matchid ichiic_ids[] = { 88 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_3400_SMB }, 89 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_6SERIES_SMB }, 90 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_6300ESB_SMB }, 91 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_6321ESB_SMB }, 92 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_7SERIES_SMB }, 93 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_8SERIES_SMB }, 94 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_8SERIES_LP_SMB }, 95 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_9SERIES_SMB }, 96 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_9SERIES_LP_SMB }, 97 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_SMB }, 98 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_SMB }, 99 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_SMB }, 100 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_SMB }, 101 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_SMB }, 102 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801E_SMB }, 103 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_SMB }, 104 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FB_SMB }, 105 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GB_SMB }, 106 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_SMB }, 107 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_SMB }, 108 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JD_SMB }, 109 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JI_SMB }, 110 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_APOLLOLAKE_SMB }, 111 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ATOMC2000_PCU_SMB }, 112 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_BAYTRAIL_SMB }, 113 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_BRASWELL_SMB }, 114 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C600_SMB }, 115 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C600_SMB_IDF_1 }, 116 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C600_SMB_IDF_2 }, 117 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C600_SMB_IDF_3 }, 118 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C610_SMB }, 119 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C610_MS_SMB_1 }, 120 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C610_MS_SMB_2 }, 121 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C610_MS_SMB_3 }, 122 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C620_SMB }, 123 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH8900_SMB }, 124 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EP80579_SMBUS }, 125 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_GLK_SMB }, 126 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_100SERIES_SMB }, 127 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_100SERIES_LP_SMB }, 128 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_200SERIES_SMB }, 129 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_300SERIES_SMB }, 130 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_300SERIES_U_SMB }, 131 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_SMB }, 132 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_LP_SMB }, 133 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_V_SMB }, 134 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_495SERIES_LP_SMB }, 135 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_SMB }, 136 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_LP_SMB }, 137 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_600SERIES_SMB }, 138 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_JSL_SMB }, 139 }; 140 141 int 142 ichiic_match(struct device *parent, void *match, void *aux) 143 { 144 return (pci_matchbyid(aux, ichiic_ids, 145 sizeof(ichiic_ids) / sizeof(ichiic_ids[0]))); 146 } 147 148 void 149 ichiic_attach(struct device *parent, struct device *self, void *aux) 150 { 151 struct ichiic_softc *sc = (struct ichiic_softc *)self; 152 struct pci_attach_args *pa = aux; 153 struct i2cbus_attach_args iba; 154 pcireg_t conf; 155 bus_size_t iosize; 156 pci_intr_handle_t ih; 157 const char *intrstr = NULL; 158 159 /* Read configuration */ 160 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_SMB_HOSTC); 161 DPRINTF((": conf 0x%08x", conf)); 162 163 if ((conf & ICH_SMB_HOSTC_HSTEN) == 0) { 164 printf(": SMBus disabled\n"); 165 return; 166 } 167 168 /* Map I/O space */ 169 if (pci_mapreg_map(pa, ICH_SMB_BASE, PCI_MAPREG_TYPE_IO, 0, 170 &sc->sc_iot, &sc->sc_ioh, NULL, &iosize, 0)) { 171 printf(": can't map i/o space\n"); 172 return; 173 } 174 175 sc->sc_poll = 1; 176 if (conf & ICH_SMB_HOSTC_SMIEN) { 177 /* No PCI IRQ */ 178 printf(": SMI"); 179 } else { 180 /* Install interrupt handler */ 181 if (pci_intr_map(pa, &ih) == 0) { 182 intrstr = pci_intr_string(pa->pa_pc, ih); 183 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 184 ichiic_intr, sc, sc->sc_dev.dv_xname); 185 if (sc->sc_ih != NULL) { 186 printf(": %s", intrstr); 187 sc->sc_poll = 0; 188 } 189 } 190 if (sc->sc_poll) 191 printf(": polling"); 192 } 193 194 printf("\n"); 195 196 /* Attach I2C bus */ 197 rw_init(&sc->sc_i2c_lock, "iiclk"); 198 sc->sc_i2c_tag.ic_cookie = sc; 199 sc->sc_i2c_tag.ic_acquire_bus = ichiic_i2c_acquire_bus; 200 sc->sc_i2c_tag.ic_release_bus = ichiic_i2c_release_bus; 201 sc->sc_i2c_tag.ic_exec = ichiic_i2c_exec; 202 203 bzero(&iba, sizeof(iba)); 204 iba.iba_name = "iic"; 205 iba.iba_tag = &sc->sc_i2c_tag; 206 config_found(self, &iba, iicbus_print); 207 208 return; 209 } 210 211 int 212 ichiic_i2c_acquire_bus(void *cookie, int flags) 213 { 214 struct ichiic_softc *sc = cookie; 215 216 if (cold || sc->sc_poll || (flags & I2C_F_POLL)) 217 return (0); 218 219 return (rw_enter(&sc->sc_i2c_lock, RW_WRITE | RW_INTR)); 220 } 221 222 void 223 ichiic_i2c_release_bus(void *cookie, int flags) 224 { 225 struct ichiic_softc *sc = cookie; 226 227 if (cold || sc->sc_poll || (flags & I2C_F_POLL)) 228 return; 229 230 rw_exit(&sc->sc_i2c_lock); 231 } 232 233 int 234 ichiic_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 235 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 236 { 237 struct ichiic_softc *sc = cookie; 238 u_int8_t *b; 239 u_int8_t ctl, st; 240 int retries; 241 242 DPRINTF(("%s: exec: op %d, addr 0x%02x, cmdlen %d, len %d, " 243 "flags 0x%02x\n", sc->sc_dev.dv_xname, op, addr, cmdlen, 244 len, flags)); 245 246 /* Wait for bus to be idle */ 247 for (retries = 100; retries > 0; retries--) { 248 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS); 249 if (!(st & ICH_SMB_HS_BUSY)) 250 break; 251 DELAY(ICHIIC_DELAY); 252 } 253 DPRINTF(("%s: exec: st 0x%b\n", sc->sc_dev.dv_xname, st, 254 ICH_SMB_HS_BITS)); 255 if (st & ICH_SMB_HS_BUSY) 256 return (1); 257 258 if (cold || sc->sc_poll) 259 flags |= I2C_F_POLL; 260 261 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2) 262 return (1); 263 264 /* Setup transfer */ 265 sc->sc_i2c_xfer.op = op; 266 sc->sc_i2c_xfer.buf = buf; 267 sc->sc_i2c_xfer.len = len; 268 sc->sc_i2c_xfer.flags = flags; 269 sc->sc_i2c_xfer.error = 0; 270 271 /* Set slave address and transfer direction */ 272 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_TXSLVA, 273 ICH_SMB_TXSLVA_ADDR(addr) | 274 (I2C_OP_READ_P(op) ? ICH_SMB_TXSLVA_READ : 0)); 275 276 b = (void *)cmdbuf; 277 if (cmdlen > 0) 278 /* Set command byte */ 279 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HCMD, b[0]); 280 281 if (I2C_OP_WRITE_P(op)) { 282 /* Write data */ 283 b = buf; 284 if (len > 0) 285 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 286 ICH_SMB_HD0, b[0]); 287 if (len > 1) 288 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 289 ICH_SMB_HD1, b[1]); 290 } 291 292 /* Set SMBus command */ 293 if (len == 0) 294 ctl = ICH_SMB_HC_CMD_BYTE; 295 else if (len == 1) 296 ctl = ICH_SMB_HC_CMD_BDATA; 297 else if (len == 2) 298 ctl = ICH_SMB_HC_CMD_WDATA; 299 else 300 panic("%s: unexpected len %zd", __func__, len); 301 302 if ((flags & I2C_F_POLL) == 0) 303 ctl |= ICH_SMB_HC_INTREN; 304 305 /* Start transaction */ 306 ctl |= ICH_SMB_HC_START; 307 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HC, ctl); 308 309 if (flags & I2C_F_POLL) { 310 /* Poll for completion */ 311 DELAY(ICHIIC_DELAY); 312 for (retries = 1000; retries > 0; retries--) { 313 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 314 ICH_SMB_HS); 315 if ((st & ICH_SMB_HS_BUSY) == 0) 316 break; 317 DELAY(ICHIIC_DELAY); 318 } 319 if (st & ICH_SMB_HS_BUSY) 320 goto timeout; 321 ichiic_intr(sc); 322 } else { 323 /* Wait for interrupt */ 324 if (tsleep_nsec(sc, PRIBIO, "ichiic", 325 SEC_TO_NSEC(ICHIIC_TIMEOUT))) 326 goto timeout; 327 } 328 329 if (sc->sc_i2c_xfer.error) 330 return (1); 331 332 return (0); 333 334 timeout: 335 /* 336 * Transfer timeout. Kill the transaction and clear status bits. 337 */ 338 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HC, 339 ICH_SMB_HC_KILL); 340 DELAY(ICHIIC_DELAY); 341 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS); 342 if ((st & ICH_SMB_HS_FAILED) == 0) 343 printf("%s: abort failed, status 0x%b\n", 344 sc->sc_dev.dv_xname, st, ICH_SMB_HS_BITS); 345 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS, st); 346 return (1); 347 } 348 349 int 350 ichiic_intr(void *arg) 351 { 352 struct ichiic_softc *sc = arg; 353 u_int8_t st; 354 u_int8_t *b; 355 size_t len; 356 357 /* Read status */ 358 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS); 359 360 /* Clear status bits */ 361 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS, st); 362 363 /* XXX Ignore SMBALERT# for now */ 364 if ((st & ICH_SMB_HS_BUSY) != 0 || (st & (ICH_SMB_HS_INTR | 365 ICH_SMB_HS_DEVERR | ICH_SMB_HS_BUSERR | ICH_SMB_HS_FAILED | 366 ICH_SMB_HS_BDONE)) == 0) 367 /* Interrupt was not for us */ 368 return (0); 369 370 DPRINTF(("%s: intr st 0x%b\n", sc->sc_dev.dv_xname, st, 371 ICH_SMB_HS_BITS)); 372 373 /* Check for errors */ 374 if (st & (ICH_SMB_HS_DEVERR | ICH_SMB_HS_BUSERR | ICH_SMB_HS_FAILED)) { 375 sc->sc_i2c_xfer.error = 1; 376 goto done; 377 } 378 379 if (st & ICH_SMB_HS_INTR) { 380 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 381 goto done; 382 383 /* Read data */ 384 b = sc->sc_i2c_xfer.buf; 385 len = sc->sc_i2c_xfer.len; 386 if (len > 0) 387 b[0] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 388 ICH_SMB_HD0); 389 if (len > 1) 390 b[1] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 391 ICH_SMB_HD1); 392 } 393 394 done: 395 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 396 wakeup(sc); 397 return (1); 398 } 399