1 /* $OpenBSD: ichiic.c,v 1.30 2013/03/02 06:56:16 jsg Exp $ */ 2 3 /* 4 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * Intel ICH SMBus controller driver. 21 */ 22 23 #include <sys/param.h> 24 #include <sys/systm.h> 25 #include <sys/device.h> 26 #include <sys/kernel.h> 27 #include <sys/rwlock.h> 28 29 #include <machine/bus.h> 30 31 #include <dev/pci/pcidevs.h> 32 #include <dev/pci/pcireg.h> 33 #include <dev/pci/pcivar.h> 34 35 #include <dev/pci/ichreg.h> 36 37 #include <dev/i2c/i2cvar.h> 38 39 #ifdef ICHIIC_DEBUG 40 #define DPRINTF(x) printf x 41 #else 42 #define DPRINTF(x) 43 #endif 44 45 #define ICHIIC_DELAY 100 46 #define ICHIIC_TIMEOUT 1 47 48 struct ichiic_softc { 49 struct device sc_dev; 50 51 bus_space_tag_t sc_iot; 52 bus_space_handle_t sc_ioh; 53 void * sc_ih; 54 int sc_poll; 55 56 struct i2c_controller sc_i2c_tag; 57 struct rwlock sc_i2c_lock; 58 struct { 59 i2c_op_t op; 60 void * buf; 61 size_t len; 62 int flags; 63 volatile int error; 64 } sc_i2c_xfer; 65 }; 66 67 int ichiic_match(struct device *, void *, void *); 68 void ichiic_attach(struct device *, struct device *, void *); 69 70 int ichiic_i2c_acquire_bus(void *, int); 71 void ichiic_i2c_release_bus(void *, int); 72 int ichiic_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, size_t, 73 void *, size_t, int); 74 75 int ichiic_intr(void *); 76 77 struct cfattach ichiic_ca = { 78 sizeof(struct ichiic_softc), 79 ichiic_match, 80 ichiic_attach 81 }; 82 83 struct cfdriver ichiic_cd = { 84 NULL, "ichiic", DV_DULL 85 }; 86 87 const struct pci_matchid ichiic_ids[] = { 88 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_3400_SMB }, 89 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_6SERIES_SMB }, 90 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_6300ESB_SMB }, 91 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_6321ESB_SMB }, 92 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_7SERIES_SMB }, 93 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_SMB }, 94 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_SMB }, 95 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_SMB }, 96 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_SMB }, 97 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_SMB }, 98 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801E_SMB }, 99 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_SMB }, 100 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FB_SMB }, 101 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GB_SMB }, 102 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_SMB }, 103 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_SMB }, 104 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JD_SMB }, 105 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JI_SMB }, 106 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C600_SMB }, 107 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EP80579_SMBUS } 108 }; 109 110 int 111 ichiic_match(struct device *parent, void *match, void *aux) 112 { 113 return (pci_matchbyid(aux, ichiic_ids, 114 sizeof(ichiic_ids) / sizeof(ichiic_ids[0]))); 115 } 116 117 void 118 ichiic_attach(struct device *parent, struct device *self, void *aux) 119 { 120 struct ichiic_softc *sc = (struct ichiic_softc *)self; 121 struct pci_attach_args *pa = aux; 122 struct i2cbus_attach_args iba; 123 pcireg_t conf; 124 bus_size_t iosize; 125 pci_intr_handle_t ih; 126 const char *intrstr = NULL; 127 128 /* Read configuration */ 129 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_SMB_HOSTC); 130 DPRINTF((": conf 0x%08x", conf)); 131 132 if ((conf & ICH_SMB_HOSTC_HSTEN) == 0) { 133 printf(": SMBus disabled\n"); 134 return; 135 } 136 137 /* Map I/O space */ 138 if (pci_mapreg_map(pa, ICH_SMB_BASE, PCI_MAPREG_TYPE_IO, 0, 139 &sc->sc_iot, &sc->sc_ioh, NULL, &iosize, 0)) { 140 printf(": can't map i/o space\n"); 141 return; 142 } 143 144 sc->sc_poll = 1; 145 if (conf & ICH_SMB_HOSTC_SMIEN) { 146 /* No PCI IRQ */ 147 printf(": SMI"); 148 } else { 149 /* Install interrupt handler */ 150 if (pci_intr_map(pa, &ih) == 0) { 151 intrstr = pci_intr_string(pa->pa_pc, ih); 152 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 153 ichiic_intr, sc, sc->sc_dev.dv_xname); 154 if (sc->sc_ih != NULL) { 155 printf(": %s", intrstr); 156 sc->sc_poll = 0; 157 } 158 } 159 if (sc->sc_poll) 160 printf(": polling"); 161 } 162 163 printf("\n"); 164 165 /* Attach I2C bus */ 166 rw_init(&sc->sc_i2c_lock, "iiclk"); 167 sc->sc_i2c_tag.ic_cookie = sc; 168 sc->sc_i2c_tag.ic_acquire_bus = ichiic_i2c_acquire_bus; 169 sc->sc_i2c_tag.ic_release_bus = ichiic_i2c_release_bus; 170 sc->sc_i2c_tag.ic_exec = ichiic_i2c_exec; 171 172 bzero(&iba, sizeof(iba)); 173 iba.iba_name = "iic"; 174 iba.iba_tag = &sc->sc_i2c_tag; 175 config_found(self, &iba, iicbus_print); 176 177 return; 178 } 179 180 int 181 ichiic_i2c_acquire_bus(void *cookie, int flags) 182 { 183 struct ichiic_softc *sc = cookie; 184 185 if (cold || sc->sc_poll || (flags & I2C_F_POLL)) 186 return (0); 187 188 return (rw_enter(&sc->sc_i2c_lock, RW_WRITE | RW_INTR)); 189 } 190 191 void 192 ichiic_i2c_release_bus(void *cookie, int flags) 193 { 194 struct ichiic_softc *sc = cookie; 195 196 if (cold || sc->sc_poll || (flags & I2C_F_POLL)) 197 return; 198 199 rw_exit(&sc->sc_i2c_lock); 200 } 201 202 int 203 ichiic_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 204 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 205 { 206 struct ichiic_softc *sc = cookie; 207 u_int8_t *b; 208 u_int8_t ctl, st; 209 int retries; 210 211 DPRINTF(("%s: exec: op %d, addr 0x%02x, cmdlen %d, len %d, " 212 "flags 0x%02x\n", sc->sc_dev.dv_xname, op, addr, cmdlen, 213 len, flags)); 214 215 /* Wait for bus to be idle */ 216 for (retries = 100; retries > 0; retries--) { 217 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS); 218 if (!(st & ICH_SMB_HS_BUSY)) 219 break; 220 DELAY(ICHIIC_DELAY); 221 } 222 DPRINTF(("%s: exec: st 0x%b\n", sc->sc_dev.dv_xname, st, 223 ICH_SMB_HS_BITS)); 224 if (st & ICH_SMB_HS_BUSY) 225 return (1); 226 227 if (cold || sc->sc_poll) 228 flags |= I2C_F_POLL; 229 230 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2) 231 return (1); 232 233 /* Setup transfer */ 234 sc->sc_i2c_xfer.op = op; 235 sc->sc_i2c_xfer.buf = buf; 236 sc->sc_i2c_xfer.len = len; 237 sc->sc_i2c_xfer.flags = flags; 238 sc->sc_i2c_xfer.error = 0; 239 240 /* Set slave address and transfer direction */ 241 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_TXSLVA, 242 ICH_SMB_TXSLVA_ADDR(addr) | 243 (I2C_OP_READ_P(op) ? ICH_SMB_TXSLVA_READ : 0)); 244 245 b = (void *)cmdbuf; 246 if (cmdlen > 0) 247 /* Set command byte */ 248 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HCMD, b[0]); 249 250 if (I2C_OP_WRITE_P(op)) { 251 /* Write data */ 252 b = buf; 253 if (len > 0) 254 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 255 ICH_SMB_HD0, b[0]); 256 if (len > 1) 257 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 258 ICH_SMB_HD1, b[1]); 259 } 260 261 /* Set SMBus command */ 262 if (len == 0) 263 ctl = ICH_SMB_HC_CMD_BYTE; 264 else if (len == 1) 265 ctl = ICH_SMB_HC_CMD_BDATA; 266 else if (len == 2) 267 ctl = ICH_SMB_HC_CMD_WDATA; 268 else 269 panic("%s: unexpected len %zd", __func__, len); 270 271 if ((flags & I2C_F_POLL) == 0) 272 ctl |= ICH_SMB_HC_INTREN; 273 274 /* Start transaction */ 275 ctl |= ICH_SMB_HC_START; 276 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HC, ctl); 277 278 if (flags & I2C_F_POLL) { 279 /* Poll for completion */ 280 DELAY(ICHIIC_DELAY); 281 for (retries = 1000; retries > 0; retries--) { 282 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 283 ICH_SMB_HS); 284 if ((st & ICH_SMB_HS_BUSY) == 0) 285 break; 286 DELAY(ICHIIC_DELAY); 287 } 288 if (st & ICH_SMB_HS_BUSY) 289 goto timeout; 290 ichiic_intr(sc); 291 } else { 292 /* Wait for interrupt */ 293 if (tsleep(sc, PRIBIO, "ichiic", ICHIIC_TIMEOUT * hz)) 294 goto timeout; 295 } 296 297 if (sc->sc_i2c_xfer.error) 298 return (1); 299 300 return (0); 301 302 timeout: 303 /* 304 * Transfer timeout. Kill the transaction and clear status bits. 305 */ 306 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HC, 307 ICH_SMB_HC_KILL); 308 DELAY(ICHIIC_DELAY); 309 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS); 310 if ((st & ICH_SMB_HS_FAILED) == 0) 311 printf("%s: abort failed, status 0x%b\n", 312 sc->sc_dev.dv_xname, st, ICH_SMB_HS_BITS); 313 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS, st); 314 return (1); 315 } 316 317 int 318 ichiic_intr(void *arg) 319 { 320 struct ichiic_softc *sc = arg; 321 u_int8_t st; 322 u_int8_t *b; 323 size_t len; 324 325 /* Read status */ 326 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS); 327 if ((st & ICH_SMB_HS_BUSY) != 0 || (st & (ICH_SMB_HS_INTR | 328 ICH_SMB_HS_DEVERR | ICH_SMB_HS_BUSERR | ICH_SMB_HS_FAILED | 329 ICH_SMB_HS_SMBAL | ICH_SMB_HS_BDONE)) == 0) 330 /* Interrupt was not for us */ 331 return (0); 332 333 DPRINTF(("%s: intr st 0x%b\n", sc->sc_dev.dv_xname, st, 334 ICH_SMB_HS_BITS)); 335 336 /* Clear status bits */ 337 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS, st); 338 339 /* Check for errors */ 340 if (st & (ICH_SMB_HS_DEVERR | ICH_SMB_HS_BUSERR | ICH_SMB_HS_FAILED)) { 341 sc->sc_i2c_xfer.error = 1; 342 goto done; 343 } 344 345 if (st & ICH_SMB_HS_INTR) { 346 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 347 goto done; 348 349 /* Read data */ 350 b = sc->sc_i2c_xfer.buf; 351 len = sc->sc_i2c_xfer.len; 352 if (len > 0) 353 b[0] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 354 ICH_SMB_HD0); 355 if (len > 1) 356 b[1] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 357 ICH_SMB_HD1); 358 } 359 360 done: 361 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 362 wakeup(sc); 363 return (1); 364 } 365