1 /* $OpenBSD: ichiic.c,v 1.20 2008/04/20 20:51:58 deraadt Exp $ */ 2 3 /* 4 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * Intel ICH SMBus controller driver. 21 */ 22 23 #include <sys/param.h> 24 #include <sys/systm.h> 25 #include <sys/device.h> 26 #include <sys/kernel.h> 27 #include <sys/rwlock.h> 28 #include <sys/proc.h> 29 30 #include <machine/bus.h> 31 32 #include <dev/pci/pcidevs.h> 33 #include <dev/pci/pcireg.h> 34 #include <dev/pci/pcivar.h> 35 36 #include <dev/pci/ichreg.h> 37 38 #include <dev/i2c/i2cvar.h> 39 40 #ifdef ICHIIC_DEBUG 41 #define DPRINTF(x) printf x 42 #else 43 #define DPRINTF(x) 44 #endif 45 46 #define ICHIIC_DELAY 100 47 #define ICHIIC_TIMEOUT 1 48 49 struct ichiic_softc { 50 struct device sc_dev; 51 52 bus_space_tag_t sc_iot; 53 bus_space_handle_t sc_ioh; 54 void * sc_ih; 55 int sc_poll; 56 57 struct i2c_controller sc_i2c_tag; 58 struct rwlock sc_i2c_lock; 59 struct { 60 i2c_op_t op; 61 void * buf; 62 size_t len; 63 int flags; 64 volatile int error; 65 } sc_i2c_xfer; 66 }; 67 68 int ichiic_match(struct device *, void *, void *); 69 void ichiic_attach(struct device *, struct device *, void *); 70 71 int ichiic_i2c_acquire_bus(void *, int); 72 void ichiic_i2c_release_bus(void *, int); 73 int ichiic_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, size_t, 74 void *, size_t, int); 75 76 int ichiic_intr(void *); 77 78 struct cfattach ichiic_ca = { 79 sizeof(struct ichiic_softc), 80 ichiic_match, 81 ichiic_attach 82 }; 83 84 struct cfdriver ichiic_cd = { 85 NULL, "ichiic", DV_DULL 86 }; 87 88 const struct pci_matchid ichiic_ids[] = { 89 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_6300ESB_SMB }, 90 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_6321ESB_SMB }, 91 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_SMB }, 92 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_SMB }, 93 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_SMB }, 94 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_SMB }, 95 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_SMB }, 96 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801E_SMB }, 97 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_SMB }, 98 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FB_SMB }, 99 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GB_SMB }, 100 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_SMB }, 101 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_SMB } 102 }; 103 104 int 105 ichiic_match(struct device *parent, void *match, void *aux) 106 { 107 return (pci_matchbyid(aux, ichiic_ids, 108 sizeof(ichiic_ids) / sizeof(ichiic_ids[0]))); 109 } 110 111 void 112 ichiic_attach(struct device *parent, struct device *self, void *aux) 113 { 114 struct ichiic_softc *sc = (struct ichiic_softc *)self; 115 struct pci_attach_args *pa = aux; 116 struct i2cbus_attach_args iba; 117 pcireg_t conf; 118 bus_size_t iosize; 119 pci_intr_handle_t ih; 120 const char *intrstr = NULL; 121 122 /* Read configuration */ 123 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_SMB_HOSTC); 124 DPRINTF((": conf 0x%08x", conf)); 125 126 if ((conf & ICH_SMB_HOSTC_HSTEN) == 0) { 127 printf(": SMBus disabled\n"); 128 return; 129 } 130 131 /* Map I/O space */ 132 if (pci_mapreg_map(pa, ICH_SMB_BASE, PCI_MAPREG_TYPE_IO, 0, 133 &sc->sc_iot, &sc->sc_ioh, NULL, &iosize, 0)) { 134 printf(": can't map I/O space\n"); 135 return; 136 } 137 138 sc->sc_poll = 1; 139 if (conf & ICH_SMB_HOSTC_SMIEN) { 140 /* No PCI IRQ */ 141 printf(": SMI"); 142 } else { 143 /* Install interrupt handler */ 144 if (pci_intr_map(pa, &ih) == 0) { 145 intrstr = pci_intr_string(pa->pa_pc, ih); 146 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 147 ichiic_intr, sc, sc->sc_dev.dv_xname); 148 if (sc->sc_ih != NULL) { 149 printf(": %s", intrstr); 150 sc->sc_poll = 0; 151 } 152 } 153 if (sc->sc_poll) 154 printf(": polling"); 155 } 156 157 printf("\n"); 158 159 /* Attach I2C bus */ 160 rw_init(&sc->sc_i2c_lock, "iiclk"); 161 sc->sc_i2c_tag.ic_cookie = sc; 162 sc->sc_i2c_tag.ic_acquire_bus = ichiic_i2c_acquire_bus; 163 sc->sc_i2c_tag.ic_release_bus = ichiic_i2c_release_bus; 164 sc->sc_i2c_tag.ic_exec = ichiic_i2c_exec; 165 166 bzero(&iba, sizeof(iba)); 167 iba.iba_name = "iic"; 168 iba.iba_tag = &sc->sc_i2c_tag; 169 config_found(self, &iba, iicbus_print); 170 171 return; 172 } 173 174 int 175 ichiic_i2c_acquire_bus(void *cookie, int flags) 176 { 177 struct ichiic_softc *sc = cookie; 178 179 if (cold || sc->sc_poll || (flags & I2C_F_POLL)) 180 return (0); 181 182 return (rw_enter(&sc->sc_i2c_lock, RW_WRITE | RW_INTR)); 183 } 184 185 void 186 ichiic_i2c_release_bus(void *cookie, int flags) 187 { 188 struct ichiic_softc *sc = cookie; 189 190 if (cold || sc->sc_poll || (flags & I2C_F_POLL)) 191 return; 192 193 rw_exit(&sc->sc_i2c_lock); 194 } 195 196 int 197 ichiic_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 198 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 199 { 200 struct ichiic_softc *sc = cookie; 201 u_int8_t *b; 202 u_int8_t ctl, st; 203 int retries; 204 205 DPRINTF(("%s: exec: op %d, addr 0x%02x, cmdlen %d, len %d, " 206 "flags 0x%02x\n", sc->sc_dev.dv_xname, op, addr, cmdlen, 207 len, flags)); 208 209 /* Wait for bus to be idle */ 210 for (retries = 100; retries > 0; retries--) { 211 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS); 212 if (!(st & ICH_SMB_HS_BUSY)) 213 break; 214 DELAY(ICHIIC_DELAY); 215 } 216 DPRINTF(("%s: exec: st 0x%b\n", sc->sc_dev.dv_xname, st, 217 ICH_SMB_HS_BITS)); 218 if (st & ICH_SMB_HS_BUSY) 219 return (1); 220 221 if (cold || sc->sc_poll) 222 flags |= I2C_F_POLL; 223 224 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2) 225 return (1); 226 227 /* Setup transfer */ 228 sc->sc_i2c_xfer.op = op; 229 sc->sc_i2c_xfer.buf = buf; 230 sc->sc_i2c_xfer.len = len; 231 sc->sc_i2c_xfer.flags = flags; 232 sc->sc_i2c_xfer.error = 0; 233 234 /* Set slave address and transfer direction */ 235 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_TXSLVA, 236 ICH_SMB_TXSLVA_ADDR(addr) | 237 (I2C_OP_READ_P(op) ? ICH_SMB_TXSLVA_READ : 0)); 238 239 b = (void *)cmdbuf; 240 if (cmdlen > 0) 241 /* Set command byte */ 242 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HCMD, b[0]); 243 244 if (I2C_OP_WRITE_P(op)) { 245 /* Write data */ 246 b = buf; 247 if (len > 0) 248 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 249 ICH_SMB_HD0, b[0]); 250 if (len > 1) 251 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 252 ICH_SMB_HD1, b[1]); 253 } 254 255 /* Set SMBus command */ 256 if (len == 0) 257 ctl = ICH_SMB_HC_CMD_BYTE; 258 else if (len == 1) 259 ctl = ICH_SMB_HC_CMD_BDATA; 260 else if (len == 2) 261 ctl = ICH_SMB_HC_CMD_WDATA; 262 263 if ((flags & I2C_F_POLL) == 0) 264 ctl |= ICH_SMB_HC_INTREN; 265 266 /* Start transaction */ 267 ctl |= ICH_SMB_HC_START; 268 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HC, ctl); 269 270 if (flags & I2C_F_POLL) { 271 /* Poll for completion */ 272 DELAY(ICHIIC_DELAY); 273 for (retries = 1000; retries > 0; retries--) { 274 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 275 ICH_SMB_HS); 276 if ((st & ICH_SMB_HS_BUSY) == 0) 277 break; 278 DELAY(ICHIIC_DELAY); 279 } 280 if (st & ICH_SMB_HS_BUSY) 281 goto timeout; 282 ichiic_intr(sc); 283 } else { 284 /* Wait for interrupt */ 285 if (tsleep(sc, PRIBIO, "iicexec", ICHIIC_TIMEOUT * hz)) 286 goto timeout; 287 } 288 289 if (sc->sc_i2c_xfer.error) 290 return (1); 291 292 return (0); 293 294 timeout: 295 /* 296 * Transfer timeout. Kill the transaction and clear status bits. 297 */ 298 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HC, 299 ICH_SMB_HC_KILL); 300 DELAY(ICHIIC_DELAY); 301 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS); 302 if ((st & ICH_SMB_HS_FAILED) == 0) 303 printf("%s: abort failed, status 0x%b\n", 304 sc->sc_dev.dv_xname, st, ICH_SMB_HS_BITS); 305 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS, st); 306 return (1); 307 } 308 309 int 310 ichiic_intr(void *arg) 311 { 312 struct ichiic_softc *sc = arg; 313 u_int8_t st; 314 u_int8_t *b; 315 size_t len; 316 317 /* Read status */ 318 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS); 319 if ((st & ICH_SMB_HS_BUSY) != 0 || (st & (ICH_SMB_HS_INTR | 320 ICH_SMB_HS_DEVERR | ICH_SMB_HS_BUSERR | ICH_SMB_HS_FAILED | 321 ICH_SMB_HS_SMBAL | ICH_SMB_HS_BDONE)) == 0) 322 /* Interrupt was not for us */ 323 return (0); 324 325 DPRINTF(("%s: intr st 0x%b\n", sc->sc_dev.dv_xname, st, 326 ICH_SMB_HS_BITS)); 327 328 /* Clear status bits */ 329 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS, st); 330 331 /* Check for errors */ 332 if (st & (ICH_SMB_HS_DEVERR | ICH_SMB_HS_BUSERR | ICH_SMB_HS_FAILED)) { 333 sc->sc_i2c_xfer.error = 1; 334 goto done; 335 } 336 337 if (st & ICH_SMB_HS_INTR) { 338 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 339 goto done; 340 341 /* Read data */ 342 b = sc->sc_i2c_xfer.buf; 343 len = sc->sc_i2c_xfer.len; 344 if (len > 0) 345 b[0] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 346 ICH_SMB_HD0); 347 if (len > 1) 348 b[1] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 349 ICH_SMB_HD1); 350 } 351 352 done: 353 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 354 wakeup(sc); 355 return (1); 356 } 357