1 /* $OpenBSD: ichiic.c,v 1.46 2021/10/30 03:27:35 jsg Exp $ */ 2 3 /* 4 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * Intel ICH SMBus controller driver. 21 */ 22 23 #include <sys/param.h> 24 #include <sys/systm.h> 25 #include <sys/device.h> 26 #include <sys/kernel.h> 27 #include <sys/rwlock.h> 28 29 #include <machine/bus.h> 30 31 #include <dev/pci/pcidevs.h> 32 #include <dev/pci/pcireg.h> 33 #include <dev/pci/pcivar.h> 34 35 #include <dev/pci/ichreg.h> 36 37 #include <dev/i2c/i2cvar.h> 38 39 #ifdef ICHIIC_DEBUG 40 #define DPRINTF(x) printf x 41 #else 42 #define DPRINTF(x) 43 #endif 44 45 #define ICHIIC_DELAY 100 46 #define ICHIIC_TIMEOUT 1 47 48 struct ichiic_softc { 49 struct device sc_dev; 50 51 bus_space_tag_t sc_iot; 52 bus_space_handle_t sc_ioh; 53 void * sc_ih; 54 int sc_poll; 55 56 struct i2c_controller sc_i2c_tag; 57 struct rwlock sc_i2c_lock; 58 struct { 59 i2c_op_t op; 60 void * buf; 61 size_t len; 62 int flags; 63 volatile int error; 64 } sc_i2c_xfer; 65 }; 66 67 int ichiic_match(struct device *, void *, void *); 68 void ichiic_attach(struct device *, struct device *, void *); 69 70 int ichiic_i2c_acquire_bus(void *, int); 71 void ichiic_i2c_release_bus(void *, int); 72 int ichiic_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, size_t, 73 void *, size_t, int); 74 75 int ichiic_intr(void *); 76 77 struct cfattach ichiic_ca = { 78 sizeof(struct ichiic_softc), 79 ichiic_match, 80 ichiic_attach 81 }; 82 83 struct cfdriver ichiic_cd = { 84 NULL, "ichiic", DV_DULL 85 }; 86 87 const struct pci_matchid ichiic_ids[] = { 88 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_3400_SMB }, 89 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_6SERIES_SMB }, 90 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_6300ESB_SMB }, 91 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_6321ESB_SMB }, 92 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_7SERIES_SMB }, 93 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_8SERIES_SMB }, 94 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_8SERIES_LP_SMB }, 95 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_9SERIES_SMB }, 96 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_9SERIES_LP_SMB }, 97 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_SMB }, 98 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_SMB }, 99 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_SMB }, 100 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_SMB }, 101 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_SMB }, 102 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801E_SMB }, 103 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_SMB }, 104 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FB_SMB }, 105 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GB_SMB }, 106 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_SMB }, 107 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_SMB }, 108 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JD_SMB }, 109 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JI_SMB }, 110 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_APOLLOLAKE_SMB }, 111 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ATOMC2000_PCU_SMB }, 112 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_BAYTRAIL_SMB }, 113 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_BRASWELL_SMB }, 114 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C600_SMB }, 115 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C600_SMB_IDF_1 }, 116 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C600_SMB_IDF_2 }, 117 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C600_SMB_IDF_3 }, 118 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C610_SMB }, 119 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C610_MS_SMB_1 }, 120 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C610_MS_SMB_2 }, 121 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C610_MS_SMB_3 }, 122 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C620_SMB }, 123 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH8900_SMB }, 124 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EP80579_SMBUS }, 125 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_GLK_SMB }, 126 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_100SERIES_SMB }, 127 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_100SERIES_LP_SMB }, 128 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_200SERIES_SMB }, 129 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_300SERIES_SMB }, 130 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_300SERIES_U_SMB }, 131 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_SMB }, 132 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_LP_SMB }, 133 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_V_SMB }, 134 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_495SERIES_LP_SMB }, 135 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_SMB }, 136 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_LP_SMB }, 137 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_600SERIES_SMB }, 138 }; 139 140 int 141 ichiic_match(struct device *parent, void *match, void *aux) 142 { 143 return (pci_matchbyid(aux, ichiic_ids, 144 sizeof(ichiic_ids) / sizeof(ichiic_ids[0]))); 145 } 146 147 void 148 ichiic_attach(struct device *parent, struct device *self, void *aux) 149 { 150 struct ichiic_softc *sc = (struct ichiic_softc *)self; 151 struct pci_attach_args *pa = aux; 152 struct i2cbus_attach_args iba; 153 pcireg_t conf; 154 bus_size_t iosize; 155 pci_intr_handle_t ih; 156 const char *intrstr = NULL; 157 158 /* Read configuration */ 159 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_SMB_HOSTC); 160 DPRINTF((": conf 0x%08x", conf)); 161 162 if ((conf & ICH_SMB_HOSTC_HSTEN) == 0) { 163 printf(": SMBus disabled\n"); 164 return; 165 } 166 167 /* Map I/O space */ 168 if (pci_mapreg_map(pa, ICH_SMB_BASE, PCI_MAPREG_TYPE_IO, 0, 169 &sc->sc_iot, &sc->sc_ioh, NULL, &iosize, 0)) { 170 printf(": can't map i/o space\n"); 171 return; 172 } 173 174 sc->sc_poll = 1; 175 if (conf & ICH_SMB_HOSTC_SMIEN) { 176 /* No PCI IRQ */ 177 printf(": SMI"); 178 } else { 179 /* Install interrupt handler */ 180 if (pci_intr_map(pa, &ih) == 0) { 181 intrstr = pci_intr_string(pa->pa_pc, ih); 182 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 183 ichiic_intr, sc, sc->sc_dev.dv_xname); 184 if (sc->sc_ih != NULL) { 185 printf(": %s", intrstr); 186 sc->sc_poll = 0; 187 } 188 } 189 if (sc->sc_poll) 190 printf(": polling"); 191 } 192 193 printf("\n"); 194 195 /* Attach I2C bus */ 196 rw_init(&sc->sc_i2c_lock, "iiclk"); 197 sc->sc_i2c_tag.ic_cookie = sc; 198 sc->sc_i2c_tag.ic_acquire_bus = ichiic_i2c_acquire_bus; 199 sc->sc_i2c_tag.ic_release_bus = ichiic_i2c_release_bus; 200 sc->sc_i2c_tag.ic_exec = ichiic_i2c_exec; 201 202 bzero(&iba, sizeof(iba)); 203 iba.iba_name = "iic"; 204 iba.iba_tag = &sc->sc_i2c_tag; 205 config_found(self, &iba, iicbus_print); 206 207 return; 208 } 209 210 int 211 ichiic_i2c_acquire_bus(void *cookie, int flags) 212 { 213 struct ichiic_softc *sc = cookie; 214 215 if (cold || sc->sc_poll || (flags & I2C_F_POLL)) 216 return (0); 217 218 return (rw_enter(&sc->sc_i2c_lock, RW_WRITE | RW_INTR)); 219 } 220 221 void 222 ichiic_i2c_release_bus(void *cookie, int flags) 223 { 224 struct ichiic_softc *sc = cookie; 225 226 if (cold || sc->sc_poll || (flags & I2C_F_POLL)) 227 return; 228 229 rw_exit(&sc->sc_i2c_lock); 230 } 231 232 int 233 ichiic_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 234 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 235 { 236 struct ichiic_softc *sc = cookie; 237 u_int8_t *b; 238 u_int8_t ctl, st; 239 int retries; 240 241 DPRINTF(("%s: exec: op %d, addr 0x%02x, cmdlen %d, len %d, " 242 "flags 0x%02x\n", sc->sc_dev.dv_xname, op, addr, cmdlen, 243 len, flags)); 244 245 /* Wait for bus to be idle */ 246 for (retries = 100; retries > 0; retries--) { 247 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS); 248 if (!(st & ICH_SMB_HS_BUSY)) 249 break; 250 DELAY(ICHIIC_DELAY); 251 } 252 DPRINTF(("%s: exec: st 0x%b\n", sc->sc_dev.dv_xname, st, 253 ICH_SMB_HS_BITS)); 254 if (st & ICH_SMB_HS_BUSY) 255 return (1); 256 257 if (cold || sc->sc_poll) 258 flags |= I2C_F_POLL; 259 260 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2) 261 return (1); 262 263 /* Setup transfer */ 264 sc->sc_i2c_xfer.op = op; 265 sc->sc_i2c_xfer.buf = buf; 266 sc->sc_i2c_xfer.len = len; 267 sc->sc_i2c_xfer.flags = flags; 268 sc->sc_i2c_xfer.error = 0; 269 270 /* Set slave address and transfer direction */ 271 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_TXSLVA, 272 ICH_SMB_TXSLVA_ADDR(addr) | 273 (I2C_OP_READ_P(op) ? ICH_SMB_TXSLVA_READ : 0)); 274 275 b = (void *)cmdbuf; 276 if (cmdlen > 0) 277 /* Set command byte */ 278 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HCMD, b[0]); 279 280 if (I2C_OP_WRITE_P(op)) { 281 /* Write data */ 282 b = buf; 283 if (len > 0) 284 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 285 ICH_SMB_HD0, b[0]); 286 if (len > 1) 287 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 288 ICH_SMB_HD1, b[1]); 289 } 290 291 /* Set SMBus command */ 292 if (len == 0) 293 ctl = ICH_SMB_HC_CMD_BYTE; 294 else if (len == 1) 295 ctl = ICH_SMB_HC_CMD_BDATA; 296 else if (len == 2) 297 ctl = ICH_SMB_HC_CMD_WDATA; 298 else 299 panic("%s: unexpected len %zd", __func__, len); 300 301 if ((flags & I2C_F_POLL) == 0) 302 ctl |= ICH_SMB_HC_INTREN; 303 304 /* Start transaction */ 305 ctl |= ICH_SMB_HC_START; 306 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HC, ctl); 307 308 if (flags & I2C_F_POLL) { 309 /* Poll for completion */ 310 DELAY(ICHIIC_DELAY); 311 for (retries = 1000; retries > 0; retries--) { 312 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 313 ICH_SMB_HS); 314 if ((st & ICH_SMB_HS_BUSY) == 0) 315 break; 316 DELAY(ICHIIC_DELAY); 317 } 318 if (st & ICH_SMB_HS_BUSY) 319 goto timeout; 320 ichiic_intr(sc); 321 } else { 322 /* Wait for interrupt */ 323 if (tsleep_nsec(sc, PRIBIO, "ichiic", 324 SEC_TO_NSEC(ICHIIC_TIMEOUT))) 325 goto timeout; 326 } 327 328 if (sc->sc_i2c_xfer.error) 329 return (1); 330 331 return (0); 332 333 timeout: 334 /* 335 * Transfer timeout. Kill the transaction and clear status bits. 336 */ 337 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HC, 338 ICH_SMB_HC_KILL); 339 DELAY(ICHIIC_DELAY); 340 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS); 341 if ((st & ICH_SMB_HS_FAILED) == 0) 342 printf("%s: abort failed, status 0x%b\n", 343 sc->sc_dev.dv_xname, st, ICH_SMB_HS_BITS); 344 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS, st); 345 return (1); 346 } 347 348 int 349 ichiic_intr(void *arg) 350 { 351 struct ichiic_softc *sc = arg; 352 u_int8_t st; 353 u_int8_t *b; 354 size_t len; 355 356 /* Read status */ 357 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS); 358 359 /* Clear status bits */ 360 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS, st); 361 362 /* XXX Ignore SMBALERT# for now */ 363 if ((st & ICH_SMB_HS_BUSY) != 0 || (st & (ICH_SMB_HS_INTR | 364 ICH_SMB_HS_DEVERR | ICH_SMB_HS_BUSERR | ICH_SMB_HS_FAILED | 365 ICH_SMB_HS_BDONE)) == 0) 366 /* Interrupt was not for us */ 367 return (0); 368 369 DPRINTF(("%s: intr st 0x%b\n", sc->sc_dev.dv_xname, st, 370 ICH_SMB_HS_BITS)); 371 372 /* Check for errors */ 373 if (st & (ICH_SMB_HS_DEVERR | ICH_SMB_HS_BUSERR | ICH_SMB_HS_FAILED)) { 374 sc->sc_i2c_xfer.error = 1; 375 goto done; 376 } 377 378 if (st & ICH_SMB_HS_INTR) { 379 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 380 goto done; 381 382 /* Read data */ 383 b = sc->sc_i2c_xfer.buf; 384 len = sc->sc_i2c_xfer.len; 385 if (len > 0) 386 b[0] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 387 ICH_SMB_HD0); 388 if (len > 1) 389 b[1] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 390 ICH_SMB_HD1); 391 } 392 393 done: 394 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 395 wakeup(sc); 396 return (1); 397 } 398