1 /* $OpenBSD: ichiic.c,v 1.43 2020/01/09 14:35:19 mpi Exp $ */ 2 3 /* 4 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * Intel ICH SMBus controller driver. 21 */ 22 23 #include <sys/param.h> 24 #include <sys/systm.h> 25 #include <sys/device.h> 26 #include <sys/kernel.h> 27 #include <sys/rwlock.h> 28 29 #include <machine/bus.h> 30 31 #include <dev/pci/pcidevs.h> 32 #include <dev/pci/pcireg.h> 33 #include <dev/pci/pcivar.h> 34 35 #include <dev/pci/ichreg.h> 36 37 #include <dev/i2c/i2cvar.h> 38 39 #ifdef ICHIIC_DEBUG 40 #define DPRINTF(x) printf x 41 #else 42 #define DPRINTF(x) 43 #endif 44 45 #define ICHIIC_DELAY 100 46 #define ICHIIC_TIMEOUT 1 47 48 struct ichiic_softc { 49 struct device sc_dev; 50 51 bus_space_tag_t sc_iot; 52 bus_space_handle_t sc_ioh; 53 void * sc_ih; 54 int sc_poll; 55 56 struct i2c_controller sc_i2c_tag; 57 struct rwlock sc_i2c_lock; 58 struct { 59 i2c_op_t op; 60 void * buf; 61 size_t len; 62 int flags; 63 volatile int error; 64 } sc_i2c_xfer; 65 }; 66 67 int ichiic_match(struct device *, void *, void *); 68 void ichiic_attach(struct device *, struct device *, void *); 69 70 int ichiic_i2c_acquire_bus(void *, int); 71 void ichiic_i2c_release_bus(void *, int); 72 int ichiic_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, size_t, 73 void *, size_t, int); 74 75 int ichiic_intr(void *); 76 77 struct cfattach ichiic_ca = { 78 sizeof(struct ichiic_softc), 79 ichiic_match, 80 ichiic_attach 81 }; 82 83 struct cfdriver ichiic_cd = { 84 NULL, "ichiic", DV_DULL 85 }; 86 87 const struct pci_matchid ichiic_ids[] = { 88 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_3400_SMB }, 89 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_6SERIES_SMB }, 90 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_6300ESB_SMB }, 91 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_6321ESB_SMB }, 92 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_7SERIES_SMB }, 93 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_8SERIES_SMB }, 94 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_8SERIES_LP_SMB }, 95 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_9SERIES_SMB }, 96 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_9SERIES_LP_SMB }, 97 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_SMB }, 98 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_SMB }, 99 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_SMB }, 100 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_SMB }, 101 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_SMB }, 102 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801E_SMB }, 103 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_SMB }, 104 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FB_SMB }, 105 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GB_SMB }, 106 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_SMB }, 107 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_SMB }, 108 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JD_SMB }, 109 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JI_SMB }, 110 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_APOLLOLAKE_SMB }, 111 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ATOMC2000_PCU_SMB }, 112 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_BAYTRAIL_SMB }, 113 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_BRASWELL_SMB }, 114 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C600_SMB }, 115 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C600_SMB_IDF_1 }, 116 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C600_SMB_IDF_2 }, 117 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C600_SMB_IDF_3 }, 118 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C610_SMB }, 119 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C610_MS_SMB_1 }, 120 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C610_MS_SMB_2 }, 121 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C610_MS_SMB_3 }, 122 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH8900_SMB }, 123 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EP80579_SMBUS }, 124 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_100SERIES_SMB }, 125 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_100SERIES_LP_SMB }, 126 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_200SERIES_SMB }, 127 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_300SERIES_SMB }, 128 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_300SERIES_U_SMB } 129 }; 130 131 int 132 ichiic_match(struct device *parent, void *match, void *aux) 133 { 134 return (pci_matchbyid(aux, ichiic_ids, 135 sizeof(ichiic_ids) / sizeof(ichiic_ids[0]))); 136 } 137 138 void 139 ichiic_attach(struct device *parent, struct device *self, void *aux) 140 { 141 struct ichiic_softc *sc = (struct ichiic_softc *)self; 142 struct pci_attach_args *pa = aux; 143 struct i2cbus_attach_args iba; 144 pcireg_t conf; 145 bus_size_t iosize; 146 pci_intr_handle_t ih; 147 const char *intrstr = NULL; 148 149 /* Read configuration */ 150 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_SMB_HOSTC); 151 DPRINTF((": conf 0x%08x", conf)); 152 153 if ((conf & ICH_SMB_HOSTC_HSTEN) == 0) { 154 printf(": SMBus disabled\n"); 155 return; 156 } 157 158 /* Map I/O space */ 159 if (pci_mapreg_map(pa, ICH_SMB_BASE, PCI_MAPREG_TYPE_IO, 0, 160 &sc->sc_iot, &sc->sc_ioh, NULL, &iosize, 0)) { 161 printf(": can't map i/o space\n"); 162 return; 163 } 164 165 sc->sc_poll = 1; 166 if (conf & ICH_SMB_HOSTC_SMIEN) { 167 /* No PCI IRQ */ 168 printf(": SMI"); 169 } else { 170 /* Install interrupt handler */ 171 if (pci_intr_map(pa, &ih) == 0) { 172 intrstr = pci_intr_string(pa->pa_pc, ih); 173 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 174 ichiic_intr, sc, sc->sc_dev.dv_xname); 175 if (sc->sc_ih != NULL) { 176 printf(": %s", intrstr); 177 sc->sc_poll = 0; 178 } 179 } 180 if (sc->sc_poll) 181 printf(": polling"); 182 } 183 184 printf("\n"); 185 186 /* Attach I2C bus */ 187 rw_init(&sc->sc_i2c_lock, "iiclk"); 188 sc->sc_i2c_tag.ic_cookie = sc; 189 sc->sc_i2c_tag.ic_acquire_bus = ichiic_i2c_acquire_bus; 190 sc->sc_i2c_tag.ic_release_bus = ichiic_i2c_release_bus; 191 sc->sc_i2c_tag.ic_exec = ichiic_i2c_exec; 192 193 bzero(&iba, sizeof(iba)); 194 iba.iba_name = "iic"; 195 iba.iba_tag = &sc->sc_i2c_tag; 196 config_found(self, &iba, iicbus_print); 197 198 return; 199 } 200 201 int 202 ichiic_i2c_acquire_bus(void *cookie, int flags) 203 { 204 struct ichiic_softc *sc = cookie; 205 206 if (cold || sc->sc_poll || (flags & I2C_F_POLL)) 207 return (0); 208 209 return (rw_enter(&sc->sc_i2c_lock, RW_WRITE | RW_INTR)); 210 } 211 212 void 213 ichiic_i2c_release_bus(void *cookie, int flags) 214 { 215 struct ichiic_softc *sc = cookie; 216 217 if (cold || sc->sc_poll || (flags & I2C_F_POLL)) 218 return; 219 220 rw_exit(&sc->sc_i2c_lock); 221 } 222 223 int 224 ichiic_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 225 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 226 { 227 struct ichiic_softc *sc = cookie; 228 u_int8_t *b; 229 u_int8_t ctl, st; 230 int retries; 231 232 DPRINTF(("%s: exec: op %d, addr 0x%02x, cmdlen %d, len %d, " 233 "flags 0x%02x\n", sc->sc_dev.dv_xname, op, addr, cmdlen, 234 len, flags)); 235 236 /* Wait for bus to be idle */ 237 for (retries = 100; retries > 0; retries--) { 238 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS); 239 if (!(st & ICH_SMB_HS_BUSY)) 240 break; 241 DELAY(ICHIIC_DELAY); 242 } 243 DPRINTF(("%s: exec: st 0x%b\n", sc->sc_dev.dv_xname, st, 244 ICH_SMB_HS_BITS)); 245 if (st & ICH_SMB_HS_BUSY) 246 return (1); 247 248 if (cold || sc->sc_poll) 249 flags |= I2C_F_POLL; 250 251 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2) 252 return (1); 253 254 /* Setup transfer */ 255 sc->sc_i2c_xfer.op = op; 256 sc->sc_i2c_xfer.buf = buf; 257 sc->sc_i2c_xfer.len = len; 258 sc->sc_i2c_xfer.flags = flags; 259 sc->sc_i2c_xfer.error = 0; 260 261 /* Set slave address and transfer direction */ 262 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_TXSLVA, 263 ICH_SMB_TXSLVA_ADDR(addr) | 264 (I2C_OP_READ_P(op) ? ICH_SMB_TXSLVA_READ : 0)); 265 266 b = (void *)cmdbuf; 267 if (cmdlen > 0) 268 /* Set command byte */ 269 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HCMD, b[0]); 270 271 if (I2C_OP_WRITE_P(op)) { 272 /* Write data */ 273 b = buf; 274 if (len > 0) 275 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 276 ICH_SMB_HD0, b[0]); 277 if (len > 1) 278 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 279 ICH_SMB_HD1, b[1]); 280 } 281 282 /* Set SMBus command */ 283 if (len == 0) 284 ctl = ICH_SMB_HC_CMD_BYTE; 285 else if (len == 1) 286 ctl = ICH_SMB_HC_CMD_BDATA; 287 else if (len == 2) 288 ctl = ICH_SMB_HC_CMD_WDATA; 289 else 290 panic("%s: unexpected len %zd", __func__, len); 291 292 if ((flags & I2C_F_POLL) == 0) 293 ctl |= ICH_SMB_HC_INTREN; 294 295 /* Start transaction */ 296 ctl |= ICH_SMB_HC_START; 297 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HC, ctl); 298 299 if (flags & I2C_F_POLL) { 300 /* Poll for completion */ 301 DELAY(ICHIIC_DELAY); 302 for (retries = 1000; retries > 0; retries--) { 303 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 304 ICH_SMB_HS); 305 if ((st & ICH_SMB_HS_BUSY) == 0) 306 break; 307 DELAY(ICHIIC_DELAY); 308 } 309 if (st & ICH_SMB_HS_BUSY) 310 goto timeout; 311 ichiic_intr(sc); 312 } else { 313 /* Wait for interrupt */ 314 if (tsleep_nsec(sc, PRIBIO, "ichiic", 315 SEC_TO_NSEC(ICHIIC_TIMEOUT))) 316 goto timeout; 317 } 318 319 if (sc->sc_i2c_xfer.error) 320 return (1); 321 322 return (0); 323 324 timeout: 325 /* 326 * Transfer timeout. Kill the transaction and clear status bits. 327 */ 328 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HC, 329 ICH_SMB_HC_KILL); 330 DELAY(ICHIIC_DELAY); 331 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS); 332 if ((st & ICH_SMB_HS_FAILED) == 0) 333 printf("%s: abort failed, status 0x%b\n", 334 sc->sc_dev.dv_xname, st, ICH_SMB_HS_BITS); 335 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS, st); 336 return (1); 337 } 338 339 int 340 ichiic_intr(void *arg) 341 { 342 struct ichiic_softc *sc = arg; 343 u_int8_t st; 344 u_int8_t *b; 345 size_t len; 346 347 /* Read status */ 348 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS); 349 350 /* Clear status bits */ 351 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS, st); 352 353 /* XXX Ignore SMBALERT# for now */ 354 if ((st & ICH_SMB_HS_BUSY) != 0 || (st & (ICH_SMB_HS_INTR | 355 ICH_SMB_HS_DEVERR | ICH_SMB_HS_BUSERR | ICH_SMB_HS_FAILED | 356 ICH_SMB_HS_BDONE)) == 0) 357 /* Interrupt was not for us */ 358 return (0); 359 360 DPRINTF(("%s: intr st 0x%b\n", sc->sc_dev.dv_xname, st, 361 ICH_SMB_HS_BITS)); 362 363 /* Check for errors */ 364 if (st & (ICH_SMB_HS_DEVERR | ICH_SMB_HS_BUSERR | ICH_SMB_HS_FAILED)) { 365 sc->sc_i2c_xfer.error = 1; 366 goto done; 367 } 368 369 if (st & ICH_SMB_HS_INTR) { 370 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 371 goto done; 372 373 /* Read data */ 374 b = sc->sc_i2c_xfer.buf; 375 len = sc->sc_i2c_xfer.len; 376 if (len > 0) 377 b[0] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 378 ICH_SMB_HD0); 379 if (len > 1) 380 b[1] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 381 ICH_SMB_HD1); 382 } 383 384 done: 385 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 386 wakeup(sc); 387 return (1); 388 } 389